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647a1567 | 1 | /* Dwarf2 Call Frame Information helper routines. |
8d9254fc | 2 | Copyright (C) 1992-2020 Free Software Foundation, Inc. |
647a1567 RH |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 3, or (at your option) any later | |
9 | version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
957060b5 AM |
23 | #include "target.h" |
24 | #include "function.h" | |
25 | #include "rtl.h" | |
26 | #include "tree.h" | |
27 | #include "tree-pass.h" | |
4d0cdd0c | 28 | #include "memmodel.h" |
957060b5 | 29 | #include "tm_p.h" |
957060b5 | 30 | #include "emit-rtl.h" |
40e23961 | 31 | #include "stor-layout.h" |
60393bbc | 32 | #include "cfgbuild.h" |
647a1567 RH |
33 | #include "dwarf2out.h" |
34 | #include "dwarf2asm.h" | |
647a1567 | 35 | #include "common/common-target.h" |
647a1567 RH |
36 | |
37 | #include "except.h" /* expand_builtin_dwarf_sp_column */ | |
357067f2 | 38 | #include "profile-count.h" /* For expr.h */ |
647a1567 | 39 | #include "expr.h" /* init_return_column_size */ |
647a1567 RH |
40 | #include "output.h" /* asm_out_file */ |
41 | #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */ | |
42 | ||
43 | ||
44 | /* ??? Poison these here until it can be done generically. They've been | |
45 | totally replaced in this file; make sure it stays that way. */ | |
46 | #undef DWARF2_UNWIND_INFO | |
47 | #undef DWARF2_FRAME_INFO | |
48 | #if (GCC_VERSION >= 3000) | |
49 | #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO | |
50 | #endif | |
51 | ||
52 | #ifndef INCOMING_RETURN_ADDR_RTX | |
53 | #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX) | |
54 | #endif | |
26fc730d JJ |
55 | |
56 | #ifndef DEFAULT_INCOMING_FRAME_SP_OFFSET | |
57 | #define DEFAULT_INCOMING_FRAME_SP_OFFSET INCOMING_FRAME_SP_OFFSET | |
58 | #endif | |
647a1567 | 59 | \f |
f17d3401 | 60 | /* A collected description of an entire row of the abstract CFI table. */ |
a79683d5 | 61 | struct GTY(()) dw_cfi_row |
f17d3401 RH |
62 | { |
63 | /* The expression that computes the CFA, expressed in two different ways. | |
64 | The CFA member for the simple cases, and the full CFI expression for | |
65 | the complex cases. The later will be a DW_CFA_cfa_expression. */ | |
66 | dw_cfa_location cfa; | |
67 | dw_cfi_ref cfa_cfi; | |
68 | ||
69 | /* The expressions for any register column that is saved. */ | |
70 | cfi_vec reg_save; | |
dfe1fe91 EB |
71 | |
72 | /* True if the register window is saved. */ | |
73 | bool window_save; | |
acdf7336 SN |
74 | |
75 | /* True if the return address is in a mangled state. */ | |
76 | bool ra_mangled; | |
a79683d5 | 77 | }; |
f17d3401 | 78 | |
43215a89 | 79 | /* The caller's ORIG_REG is saved in SAVED_IN_REG. */ |
a79683d5 | 80 | struct GTY(()) reg_saved_in_data { |
43215a89 RH |
81 | rtx orig_reg; |
82 | rtx saved_in_reg; | |
a79683d5 | 83 | }; |
43215a89 | 84 | |
43215a89 RH |
85 | |
86 | /* Since we no longer have a proper CFG, we're going to create a facsimile | |
87 | of one on the fly while processing the frame-related insns. | |
88 | ||
829bdd4b RH |
89 | We create dw_trace_info structures for each extended basic block beginning |
90 | and ending at a "save point". Save points are labels, barriers, certain | |
91 | notes, and of course the beginning and end of the function. | |
43215a89 RH |
92 | |
93 | As we encounter control transfer insns, we propagate the "current" | |
829bdd4b RH |
94 | row state across the edges to the starts of traces. When checking is |
95 | enabled, we validate that we propagate the same data from all sources. | |
43215a89 RH |
96 | |
97 | All traces are members of the TRACE_INFO array, in the order in which | |
98 | they appear in the instruction stream. | |
99 | ||
829bdd4b RH |
100 | All save points are present in the TRACE_INDEX hash, mapping the insn |
101 | starting a trace to the dw_trace_info describing the trace. */ | |
43215a89 | 102 | |
a79683d5 | 103 | struct dw_trace_info |
43215a89 | 104 | { |
829bdd4b | 105 | /* The insn that begins the trace. */ |
7583d99a | 106 | rtx_insn *head; |
43215a89 RH |
107 | |
108 | /* The row state at the beginning and end of the trace. */ | |
829bdd4b RH |
109 | dw_cfi_row *beg_row, *end_row; |
110 | ||
9a08d230 RH |
111 | /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find |
112 | while scanning insns. However, the args_size value is irrelevant at | |
113 | any point except can_throw_internal_p insns. Therefore the "delay" | |
114 | sizes the values that must actually be emitted for this trace. */ | |
68184180 RS |
115 | poly_int64_pod beg_true_args_size, end_true_args_size; |
116 | poly_int64_pod beg_delay_args_size, end_delay_args_size; | |
9a08d230 RH |
117 | |
118 | /* The first EH insn in the trace, where beg_delay_args_size must be set. */ | |
dc01c3d1 | 119 | rtx_insn *eh_head; |
9a08d230 | 120 | |
43215a89 RH |
121 | /* The following variables contain data used in interpreting frame related |
122 | expressions. These are not part of the "real" row state as defined by | |
123 | Dwarf, but it seems like they need to be propagated into a trace in case | |
124 | frame related expressions have been sunk. */ | |
125 | /* ??? This seems fragile. These variables are fragments of a larger | |
126 | expression. If we do not keep the entire expression together, we risk | |
127 | not being able to put it together properly. Consider forcing targets | |
128 | to generate self-contained expressions and dropping all of the magic | |
129 | interpretation code in this file. Or at least refusing to shrink wrap | |
130 | any frame related insn that doesn't contain a complete expression. */ | |
131 | ||
132 | /* The register used for saving registers to the stack, and its offset | |
133 | from the CFA. */ | |
134 | dw_cfa_location cfa_store; | |
135 | ||
136 | /* A temporary register holding an integral value used in adjusting SP | |
137 | or setting up the store_reg. The "offset" field holds the integer | |
138 | value, not an offset. */ | |
139 | dw_cfa_location cfa_temp; | |
140 | ||
141 | /* A set of registers saved in other registers. This is the inverse of | |
142 | the row->reg_save info, if the entry is a DW_CFA_register. This is | |
143 | implemented as a flat array because it normally contains zero or 1 | |
144 | entry, depending on the target. IA-64 is the big spender here, using | |
145 | a maximum of 5 entries. */ | |
9771b263 | 146 | vec<reg_saved_in_data> regs_saved_in_regs; |
43215a89 | 147 | |
200e10dc RH |
148 | /* An identifier for this trace. Used only for debugging dumps. */ |
149 | unsigned id; | |
150 | ||
151 | /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */ | |
152 | bool switch_sections; | |
9a08d230 RH |
153 | |
154 | /* True if we've seen different values incoming to beg_true_args_size. */ | |
155 | bool args_size_undefined; | |
464b6c11 EB |
156 | |
157 | /* True if we've seen an insn with a REG_ARGS_SIZE note before EH_HEAD. */ | |
158 | bool args_size_defined_for_eh; | |
a79683d5 | 159 | }; |
43215a89 | 160 | |
43215a89 | 161 | |
4a8fb1a1 LC |
162 | /* Hashtable helpers. */ |
163 | ||
8d67ee55 | 164 | struct trace_info_hasher : nofree_ptr_hash <dw_trace_info> |
4a8fb1a1 | 165 | { |
67f58944 TS |
166 | static inline hashval_t hash (const dw_trace_info *); |
167 | static inline bool equal (const dw_trace_info *, const dw_trace_info *); | |
4a8fb1a1 LC |
168 | }; |
169 | ||
170 | inline hashval_t | |
67f58944 | 171 | trace_info_hasher::hash (const dw_trace_info *ti) |
4a8fb1a1 LC |
172 | { |
173 | return INSN_UID (ti->head); | |
174 | } | |
175 | ||
176 | inline bool | |
67f58944 | 177 | trace_info_hasher::equal (const dw_trace_info *a, const dw_trace_info *b) |
4a8fb1a1 LC |
178 | { |
179 | return a->head == b->head; | |
180 | } | |
181 | ||
182 | ||
43215a89 | 183 | /* The variables making up the pseudo-cfg, as described above. */ |
9771b263 | 184 | static vec<dw_trace_info> trace_info; |
b01c08c7 | 185 | static vec<dw_trace_info *> trace_work_list; |
c203e8a7 | 186 | static hash_table<trace_info_hasher> *trace_index; |
43215a89 | 187 | |
647a1567 RH |
188 | /* A vector of call frame insns for the CIE. */ |
189 | cfi_vec cie_cfi_vec; | |
190 | ||
f17d3401 RH |
191 | /* The state of the first row of the FDE table, which includes the |
192 | state provided by the CIE. */ | |
ce363ef2 | 193 | static GTY(()) dw_cfi_row *cie_cfi_row; |
f17d3401 | 194 | |
43215a89 RH |
195 | static GTY(()) reg_saved_in_data *cie_return_save; |
196 | ||
647a1567 RH |
197 | static GTY(()) unsigned long dwarf2out_cfi_label_num; |
198 | ||
bc5612ed | 199 | /* The insn after which a new CFI note should be emitted. */ |
15f63a9a | 200 | static rtx_insn *add_cfi_insn; |
bc5612ed | 201 | |
3edb53aa RH |
202 | /* When non-null, add_cfi will add the CFI to this vector. */ |
203 | static cfi_vec *add_cfi_vec; | |
204 | ||
43215a89 RH |
205 | /* The current instruction trace. */ |
206 | static dw_trace_info *cur_trace; | |
207 | ||
208 | /* The current, i.e. most recently generated, row of the CFI table. */ | |
209 | static dw_cfi_row *cur_row; | |
210 | ||
9a08d230 RH |
211 | /* A copy of the current CFA, for use during the processing of a |
212 | single insn. */ | |
213 | static dw_cfa_location *cur_cfa; | |
214 | ||
43215a89 RH |
215 | /* We delay emitting a register save until either (a) we reach the end |
216 | of the prologue or (b) the register is clobbered. This clusters | |
217 | register saves so that there are fewer pc advances. */ | |
218 | ||
a79683d5 | 219 | struct queued_reg_save { |
43215a89 RH |
220 | rtx reg; |
221 | rtx saved_reg; | |
21810de4 | 222 | poly_int64_pod cfa_offset; |
a79683d5 | 223 | }; |
43215a89 | 224 | |
43215a89 | 225 | |
9771b263 | 226 | static vec<queued_reg_save> queued_reg_saves; |
43215a89 | 227 | |
bc5612ed BS |
228 | /* True if any CFI directives were emitted at the current insn. */ |
229 | static bool any_cfis_emitted; | |
4f42d714 RH |
230 | |
231 | /* Short-hand for commonly used register numbers. */ | |
232 | static unsigned dw_stack_pointer_regnum; | |
233 | static unsigned dw_frame_pointer_regnum; | |
647a1567 RH |
234 | \f |
235 | /* Hook used by __throw. */ | |
236 | ||
237 | rtx | |
238 | expand_builtin_dwarf_sp_column (void) | |
239 | { | |
4f42d714 | 240 | unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); |
647a1567 RH |
241 | return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1)); |
242 | } | |
243 | ||
244 | /* MEM is a memory reference for the register size table, each element of | |
245 | which has mode MODE. Initialize column C as a return address column. */ | |
246 | ||
247 | static void | |
095a2d76 | 248 | init_return_column_size (scalar_int_mode mode, rtx mem, unsigned int c) |
647a1567 RH |
249 | { |
250 | HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode); | |
251 | HOST_WIDE_INT size = GET_MODE_SIZE (Pmode); | |
69db2d57 RS |
252 | emit_move_insn (adjust_address (mem, mode, offset), |
253 | gen_int_mode (size, mode)); | |
647a1567 RH |
254 | } |
255 | ||
edbbaf3b OH |
256 | /* Datastructure used by expand_builtin_init_dwarf_reg_sizes and |
257 | init_one_dwarf_reg_size to communicate on what has been done by the | |
258 | latter. */ | |
259 | ||
a79683d5 | 260 | struct init_one_dwarf_reg_state |
edbbaf3b OH |
261 | { |
262 | /* Whether the dwarf return column was initialized. */ | |
263 | bool wrote_return_column; | |
264 | ||
265 | /* For each hard register REGNO, whether init_one_dwarf_reg_size | |
266 | was given REGNO to process already. */ | |
267 | bool processed_regno [FIRST_PSEUDO_REGISTER]; | |
268 | ||
a79683d5 | 269 | }; |
edbbaf3b OH |
270 | |
271 | /* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to | |
272 | initialize the dwarf register size table entry corresponding to register | |
273 | REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to | |
274 | use for the size entry to initialize, and INIT_STATE is the communication | |
275 | datastructure conveying what we're doing to our caller. */ | |
276 | ||
277 | static | |
278 | void init_one_dwarf_reg_size (int regno, machine_mode regmode, | |
279 | rtx table, machine_mode slotmode, | |
280 | init_one_dwarf_reg_state *init_state) | |
281 | { | |
282 | const unsigned int dnum = DWARF_FRAME_REGNUM (regno); | |
283 | const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); | |
a66272f6 | 284 | const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum); |
edbbaf3b | 285 | |
cf098191 RS |
286 | poly_int64 slotoffset = dcol * GET_MODE_SIZE (slotmode); |
287 | poly_int64 regsize = GET_MODE_SIZE (regmode); | |
edbbaf3b OH |
288 | |
289 | init_state->processed_regno[regno] = true; | |
290 | ||
291 | if (rnum >= DWARF_FRAME_REGISTERS) | |
292 | return; | |
293 | ||
294 | if (dnum == DWARF_FRAME_RETURN_COLUMN) | |
295 | { | |
296 | if (regmode == VOIDmode) | |
297 | return; | |
298 | init_state->wrote_return_column = true; | |
299 | } | |
300 | ||
cf098191 RS |
301 | /* ??? When is this true? Should it be a test based on DCOL instead? */ |
302 | if (maybe_lt (slotoffset, 0)) | |
edbbaf3b OH |
303 | return; |
304 | ||
305 | emit_move_insn (adjust_address (table, slotmode, slotoffset), | |
306 | gen_int_mode (regsize, slotmode)); | |
307 | } | |
308 | ||
309 | /* Generate code to initialize the dwarf register size table located | |
310 | at the provided ADDRESS. */ | |
647a1567 RH |
311 | |
312 | void | |
313 | expand_builtin_init_dwarf_reg_sizes (tree address) | |
314 | { | |
315 | unsigned int i; | |
7a504f33 | 316 | scalar_int_mode mode = SCALAR_INT_TYPE_MODE (char_type_node); |
647a1567 RH |
317 | rtx addr = expand_normal (address); |
318 | rtx mem = gen_rtx_MEM (BLKmode, addr); | |
edbbaf3b OH |
319 | |
320 | init_one_dwarf_reg_state init_state; | |
321 | ||
322 | memset ((char *)&init_state, 0, sizeof (init_state)); | |
647a1567 RH |
323 | |
324 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
325 | { | |
edbbaf3b OH |
326 | machine_mode save_mode; |
327 | rtx span; | |
647a1567 | 328 | |
edbbaf3b OH |
329 | /* No point in processing a register multiple times. This could happen |
330 | with register spans, e.g. when a reg is first processed as a piece of | |
331 | a span, then as a register on its own later on. */ | |
332 | ||
333 | if (init_state.processed_regno[i]) | |
334 | continue; | |
335 | ||
336 | save_mode = targetm.dwarf_frame_reg_mode (i); | |
337 | span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)); | |
647a1567 | 338 | |
edbbaf3b OH |
339 | if (!span) |
340 | init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state); | |
341 | else | |
342 | { | |
343 | for (int si = 0; si < XVECLEN (span, 0); si++) | |
647a1567 | 344 | { |
edbbaf3b | 345 | rtx reg = XVECEXP (span, 0, si); |
647a1567 | 346 | |
edbbaf3b OH |
347 | init_one_dwarf_reg_size |
348 | (REGNO (reg), GET_MODE (reg), mem, mode, &init_state); | |
349 | } | |
647a1567 RH |
350 | } |
351 | } | |
352 | ||
edbbaf3b | 353 | if (!init_state.wrote_return_column) |
647a1567 RH |
354 | init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); |
355 | ||
356 | #ifdef DWARF_ALT_FRAME_RETURN_COLUMN | |
357 | init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN); | |
358 | #endif | |
359 | ||
360 | targetm.init_dwarf_reg_sizes_extra (address); | |
361 | } | |
362 | ||
829bdd4b | 363 | \f |
829bdd4b | 364 | static dw_trace_info * |
7583d99a | 365 | get_trace_info (rtx_insn *insn) |
829bdd4b RH |
366 | { |
367 | dw_trace_info dummy; | |
368 | dummy.head = insn; | |
c203e8a7 | 369 | return trace_index->find_with_hash (&dummy, INSN_UID (insn)); |
829bdd4b RH |
370 | } |
371 | ||
372 | static bool | |
7583d99a | 373 | save_point_p (rtx_insn *insn) |
829bdd4b RH |
374 | { |
375 | /* Labels, except those that are really jump tables. */ | |
376 | if (LABEL_P (insn)) | |
377 | return inside_basic_block_p (insn); | |
378 | ||
379 | /* We split traces at the prologue/epilogue notes because those | |
380 | are points at which the unwind info is usually stable. This | |
381 | makes it easier to find spots with identical unwind info so | |
382 | that we can use remember/restore_state opcodes. */ | |
383 | if (NOTE_P (insn)) | |
384 | switch (NOTE_KIND (insn)) | |
385 | { | |
386 | case NOTE_INSN_PROLOGUE_END: | |
387 | case NOTE_INSN_EPILOGUE_BEG: | |
388 | return true; | |
389 | } | |
390 | ||
391 | return false; | |
392 | } | |
393 | ||
647a1567 RH |
394 | /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */ |
395 | ||
396 | static inline HOST_WIDE_INT | |
397 | div_data_align (HOST_WIDE_INT off) | |
398 | { | |
399 | HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT; | |
400 | gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off); | |
401 | return r; | |
402 | } | |
403 | ||
404 | /* Return true if we need a signed version of a given opcode | |
405 | (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */ | |
406 | ||
407 | static inline bool | |
408 | need_data_align_sf_opcode (HOST_WIDE_INT off) | |
409 | { | |
410 | return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0; | |
411 | } | |
412 | ||
413 | /* Return a pointer to a newly allocated Call Frame Instruction. */ | |
414 | ||
415 | static inline dw_cfi_ref | |
416 | new_cfi (void) | |
417 | { | |
766090c2 | 418 | dw_cfi_ref cfi = ggc_alloc<dw_cfi_node> (); |
647a1567 RH |
419 | |
420 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0; | |
421 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0; | |
422 | ||
423 | return cfi; | |
424 | } | |
425 | ||
f17d3401 RH |
426 | /* Return a newly allocated CFI row, with no defined data. */ |
427 | ||
ce363ef2 | 428 | static dw_cfi_row * |
f17d3401 RH |
429 | new_cfi_row (void) |
430 | { | |
766090c2 | 431 | dw_cfi_row *row = ggc_cleared_alloc<dw_cfi_row> (); |
f17d3401 RH |
432 | |
433 | row->cfa.reg = INVALID_REGNUM; | |
434 | ||
435 | return row; | |
436 | } | |
437 | ||
438 | /* Return a copy of an existing CFI row. */ | |
439 | ||
ce363ef2 RH |
440 | static dw_cfi_row * |
441 | copy_cfi_row (dw_cfi_row *src) | |
f17d3401 | 442 | { |
766090c2 | 443 | dw_cfi_row *dst = ggc_alloc<dw_cfi_row> (); |
f17d3401 RH |
444 | |
445 | *dst = *src; | |
9771b263 | 446 | dst->reg_save = vec_safe_copy (src->reg_save); |
f17d3401 RH |
447 | |
448 | return dst; | |
449 | } | |
450 | ||
21810de4 RS |
451 | /* Return a copy of an existing CFA location. */ |
452 | ||
453 | static dw_cfa_location * | |
454 | copy_cfa (dw_cfa_location *src) | |
455 | { | |
456 | dw_cfa_location *dst = ggc_alloc<dw_cfa_location> (); | |
457 | *dst = *src; | |
458 | return dst; | |
459 | } | |
460 | ||
89e25f95 | 461 | /* Generate a new label for the CFI info to refer to. */ |
647a1567 RH |
462 | |
463 | static char * | |
89e25f95 | 464 | dwarf2out_cfi_label (void) |
647a1567 | 465 | { |
89e25f95 BS |
466 | int num = dwarf2out_cfi_label_num++; |
467 | char label[20]; | |
647a1567 | 468 | |
89e25f95 | 469 | ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num); |
647a1567 | 470 | |
89e25f95 | 471 | return xstrdup (label); |
647a1567 RH |
472 | } |
473 | ||
3edb53aa | 474 | /* Add CFI either to the current insn stream or to a vector, or both. */ |
647a1567 RH |
475 | |
476 | static void | |
3edb53aa | 477 | add_cfi (dw_cfi_ref cfi) |
647a1567 | 478 | { |
89e25f95 | 479 | any_cfis_emitted = true; |
141618e2 RH |
480 | |
481 | if (add_cfi_insn != NULL) | |
647a1567 | 482 | { |
141618e2 RH |
483 | add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn); |
484 | NOTE_CFI (add_cfi_insn) = cfi; | |
647a1567 | 485 | } |
141618e2 | 486 | |
3edb53aa | 487 | if (add_cfi_vec != NULL) |
9771b263 | 488 | vec_safe_push (*add_cfi_vec, cfi); |
647a1567 RH |
489 | } |
490 | ||
57e16c96 | 491 | static void |
68184180 | 492 | add_cfi_args_size (poly_int64 size) |
57e16c96 | 493 | { |
68184180 RS |
494 | /* We don't yet have a representation for polynomial sizes. */ |
495 | HOST_WIDE_INT const_size = size.to_constant (); | |
496 | ||
57e16c96 RH |
497 | dw_cfi_ref cfi = new_cfi (); |
498 | ||
9a08d230 RH |
499 | /* While we can occasionally have args_size < 0 internally, this state |
500 | should not persist at a point we actually need an opcode. */ | |
68184180 | 501 | gcc_assert (const_size >= 0); |
9a08d230 | 502 | |
57e16c96 | 503 | cfi->dw_cfi_opc = DW_CFA_GNU_args_size; |
68184180 | 504 | cfi->dw_cfi_oprnd1.dw_cfi_offset = const_size; |
57e16c96 RH |
505 | |
506 | add_cfi (cfi); | |
507 | } | |
508 | ||
509 | static void | |
510 | add_cfi_restore (unsigned reg) | |
511 | { | |
512 | dw_cfi_ref cfi = new_cfi (); | |
513 | ||
514 | cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore); | |
515 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
516 | ||
517 | add_cfi (cfi); | |
518 | } | |
519 | ||
f1a0e830 RH |
520 | /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating |
521 | that the register column is no longer saved. */ | |
522 | ||
523 | static void | |
ce363ef2 | 524 | update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi) |
f1a0e830 | 525 | { |
9771b263 DN |
526 | if (vec_safe_length (row->reg_save) <= column) |
527 | vec_safe_grow_cleared (row->reg_save, column + 1); | |
528 | (*row->reg_save)[column] = cfi; | |
f1a0e830 RH |
529 | } |
530 | ||
647a1567 RH |
531 | /* This function fills in aa dw_cfa_location structure from a dwarf location |
532 | descriptor sequence. */ | |
533 | ||
534 | static void | |
84562394 | 535 | get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_node *loc) |
647a1567 | 536 | { |
84562394 | 537 | struct dw_loc_descr_node *ptr; |
647a1567 RH |
538 | cfa->offset = 0; |
539 | cfa->base_offset = 0; | |
540 | cfa->indirect = 0; | |
541 | cfa->reg = -1; | |
542 | ||
543 | for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next) | |
544 | { | |
545 | enum dwarf_location_atom op = ptr->dw_loc_opc; | |
546 | ||
547 | switch (op) | |
548 | { | |
549 | case DW_OP_reg0: | |
550 | case DW_OP_reg1: | |
551 | case DW_OP_reg2: | |
552 | case DW_OP_reg3: | |
553 | case DW_OP_reg4: | |
554 | case DW_OP_reg5: | |
555 | case DW_OP_reg6: | |
556 | case DW_OP_reg7: | |
557 | case DW_OP_reg8: | |
558 | case DW_OP_reg9: | |
559 | case DW_OP_reg10: | |
560 | case DW_OP_reg11: | |
561 | case DW_OP_reg12: | |
562 | case DW_OP_reg13: | |
563 | case DW_OP_reg14: | |
564 | case DW_OP_reg15: | |
565 | case DW_OP_reg16: | |
566 | case DW_OP_reg17: | |
567 | case DW_OP_reg18: | |
568 | case DW_OP_reg19: | |
569 | case DW_OP_reg20: | |
570 | case DW_OP_reg21: | |
571 | case DW_OP_reg22: | |
572 | case DW_OP_reg23: | |
573 | case DW_OP_reg24: | |
574 | case DW_OP_reg25: | |
575 | case DW_OP_reg26: | |
576 | case DW_OP_reg27: | |
577 | case DW_OP_reg28: | |
578 | case DW_OP_reg29: | |
579 | case DW_OP_reg30: | |
580 | case DW_OP_reg31: | |
581 | cfa->reg = op - DW_OP_reg0; | |
582 | break; | |
583 | case DW_OP_regx: | |
584 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
585 | break; | |
586 | case DW_OP_breg0: | |
587 | case DW_OP_breg1: | |
588 | case DW_OP_breg2: | |
589 | case DW_OP_breg3: | |
590 | case DW_OP_breg4: | |
591 | case DW_OP_breg5: | |
592 | case DW_OP_breg6: | |
593 | case DW_OP_breg7: | |
594 | case DW_OP_breg8: | |
595 | case DW_OP_breg9: | |
596 | case DW_OP_breg10: | |
597 | case DW_OP_breg11: | |
598 | case DW_OP_breg12: | |
599 | case DW_OP_breg13: | |
600 | case DW_OP_breg14: | |
601 | case DW_OP_breg15: | |
602 | case DW_OP_breg16: | |
603 | case DW_OP_breg17: | |
604 | case DW_OP_breg18: | |
605 | case DW_OP_breg19: | |
606 | case DW_OP_breg20: | |
607 | case DW_OP_breg21: | |
608 | case DW_OP_breg22: | |
609 | case DW_OP_breg23: | |
610 | case DW_OP_breg24: | |
611 | case DW_OP_breg25: | |
612 | case DW_OP_breg26: | |
613 | case DW_OP_breg27: | |
614 | case DW_OP_breg28: | |
615 | case DW_OP_breg29: | |
616 | case DW_OP_breg30: | |
617 | case DW_OP_breg31: | |
618 | cfa->reg = op - DW_OP_breg0; | |
619 | cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int; | |
620 | break; | |
621 | case DW_OP_bregx: | |
622 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
623 | cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int; | |
624 | break; | |
625 | case DW_OP_deref: | |
626 | cfa->indirect = 1; | |
627 | break; | |
628 | case DW_OP_plus_uconst: | |
629 | cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned; | |
630 | break; | |
631 | default: | |
632 | gcc_unreachable (); | |
633 | } | |
634 | } | |
635 | } | |
636 | ||
4a8ee122 RH |
637 | /* Find the previous value for the CFA, iteratively. CFI is the opcode |
638 | to interpret, *LOC will be updated as necessary, *REMEMBER is used for | |
639 | one level of remember/restore state processing. */ | |
647a1567 RH |
640 | |
641 | void | |
642 | lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember) | |
643 | { | |
644 | switch (cfi->dw_cfi_opc) | |
645 | { | |
646 | case DW_CFA_def_cfa_offset: | |
647 | case DW_CFA_def_cfa_offset_sf: | |
648 | loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset; | |
649 | break; | |
650 | case DW_CFA_def_cfa_register: | |
651 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
652 | break; | |
653 | case DW_CFA_def_cfa: | |
654 | case DW_CFA_def_cfa_sf: | |
655 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
656 | loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset; | |
657 | break; | |
658 | case DW_CFA_def_cfa_expression: | |
21810de4 RS |
659 | if (cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc) |
660 | *loc = *cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc; | |
661 | else | |
662 | get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc); | |
647a1567 RH |
663 | break; |
664 | ||
665 | case DW_CFA_remember_state: | |
666 | gcc_assert (!remember->in_use); | |
667 | *remember = *loc; | |
668 | remember->in_use = 1; | |
669 | break; | |
670 | case DW_CFA_restore_state: | |
671 | gcc_assert (remember->in_use); | |
672 | *loc = *remember; | |
673 | remember->in_use = 0; | |
674 | break; | |
675 | ||
676 | default: | |
677 | break; | |
678 | } | |
679 | } | |
680 | ||
647a1567 RH |
681 | /* Determine if two dw_cfa_location structures define the same data. */ |
682 | ||
683 | bool | |
684 | cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2) | |
685 | { | |
686 | return (loc1->reg == loc2->reg | |
21810de4 | 687 | && known_eq (loc1->offset, loc2->offset) |
647a1567 RH |
688 | && loc1->indirect == loc2->indirect |
689 | && (loc1->indirect == 0 | |
21810de4 | 690 | || known_eq (loc1->base_offset, loc2->base_offset))); |
647a1567 RH |
691 | } |
692 | ||
57e16c96 | 693 | /* Determine if two CFI operands are identical. */ |
647a1567 | 694 | |
57e16c96 RH |
695 | static bool |
696 | cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b) | |
647a1567 | 697 | { |
57e16c96 RH |
698 | switch (t) |
699 | { | |
700 | case dw_cfi_oprnd_unused: | |
701 | return true; | |
702 | case dw_cfi_oprnd_reg_num: | |
703 | return a->dw_cfi_reg_num == b->dw_cfi_reg_num; | |
704 | case dw_cfi_oprnd_offset: | |
705 | return a->dw_cfi_offset == b->dw_cfi_offset; | |
706 | case dw_cfi_oprnd_addr: | |
707 | return (a->dw_cfi_addr == b->dw_cfi_addr | |
708 | || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0); | |
709 | case dw_cfi_oprnd_loc: | |
710 | return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc); | |
21810de4 RS |
711 | case dw_cfi_oprnd_cfa_loc: |
712 | return cfa_equal_p (a->dw_cfi_cfa_loc, b->dw_cfi_cfa_loc); | |
57e16c96 RH |
713 | } |
714 | gcc_unreachable (); | |
715 | } | |
647a1567 | 716 | |
57e16c96 RH |
717 | /* Determine if two CFI entries are identical. */ |
718 | ||
719 | static bool | |
720 | cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b) | |
721 | { | |
722 | enum dwarf_call_frame_info opc; | |
723 | ||
724 | /* Make things easier for our callers, including missing operands. */ | |
725 | if (a == b) | |
726 | return true; | |
727 | if (a == NULL || b == NULL) | |
728 | return false; | |
729 | ||
730 | /* Obviously, the opcodes must match. */ | |
731 | opc = a->dw_cfi_opc; | |
732 | if (opc != b->dw_cfi_opc) | |
733 | return false; | |
734 | ||
735 | /* Compare the two operands, re-using the type of the operands as | |
736 | already exposed elsewhere. */ | |
737 | return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc), | |
738 | &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1) | |
739 | && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc), | |
740 | &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2)); | |
741 | } | |
742 | ||
829bdd4b RH |
743 | /* Determine if two CFI_ROW structures are identical. */ |
744 | ||
745 | static bool | |
746 | cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b) | |
747 | { | |
748 | size_t i, n_a, n_b, n_max; | |
749 | ||
750 | if (a->cfa_cfi) | |
751 | { | |
752 | if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi)) | |
753 | return false; | |
754 | } | |
755 | else if (!cfa_equal_p (&a->cfa, &b->cfa)) | |
756 | return false; | |
757 | ||
9771b263 DN |
758 | n_a = vec_safe_length (a->reg_save); |
759 | n_b = vec_safe_length (b->reg_save); | |
829bdd4b RH |
760 | n_max = MAX (n_a, n_b); |
761 | ||
762 | for (i = 0; i < n_max; ++i) | |
763 | { | |
764 | dw_cfi_ref r_a = NULL, r_b = NULL; | |
765 | ||
766 | if (i < n_a) | |
9771b263 | 767 | r_a = (*a->reg_save)[i]; |
829bdd4b | 768 | if (i < n_b) |
9771b263 | 769 | r_b = (*b->reg_save)[i]; |
829bdd4b RH |
770 | |
771 | if (!cfi_equal_p (r_a, r_b)) | |
772 | return false; | |
773 | } | |
774 | ||
dfe1fe91 EB |
775 | if (a->window_save != b->window_save) |
776 | return false; | |
777 | ||
acdf7336 SN |
778 | if (a->ra_mangled != b->ra_mangled) |
779 | return false; | |
780 | ||
829bdd4b RH |
781 | return true; |
782 | } | |
783 | ||
57e16c96 RH |
784 | /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining |
785 | what opcode to emit. Returns the CFI opcode to effect the change, or | |
786 | NULL if NEW_CFA == OLD_CFA. */ | |
787 | ||
788 | static dw_cfi_ref | |
789 | def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa) | |
790 | { | |
791 | dw_cfi_ref cfi; | |
647a1567 | 792 | |
647a1567 | 793 | /* If nothing changed, no need to issue any call frame instructions. */ |
57e16c96 RH |
794 | if (cfa_equal_p (old_cfa, new_cfa)) |
795 | return NULL; | |
647a1567 RH |
796 | |
797 | cfi = new_cfi (); | |
798 | ||
21810de4 RS |
799 | HOST_WIDE_INT const_offset; |
800 | if (new_cfa->reg == old_cfa->reg | |
801 | && !new_cfa->indirect | |
802 | && !old_cfa->indirect | |
803 | && new_cfa->offset.is_constant (&const_offset)) | |
647a1567 RH |
804 | { |
805 | /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating | |
806 | the CFA register did not change but the offset did. The data | |
807 | factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or | |
808 | in the assembler via the .cfi_def_cfa_offset directive. */ | |
21810de4 | 809 | if (const_offset < 0) |
647a1567 RH |
810 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf; |
811 | else | |
812 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset; | |
21810de4 | 813 | cfi->dw_cfi_oprnd1.dw_cfi_offset = const_offset; |
647a1567 | 814 | } |
21810de4 RS |
815 | else if (new_cfa->offset.is_constant () |
816 | && known_eq (new_cfa->offset, old_cfa->offset) | |
57e16c96 RH |
817 | && old_cfa->reg != INVALID_REGNUM |
818 | && !new_cfa->indirect | |
819 | && !old_cfa->indirect) | |
647a1567 RH |
820 | { |
821 | /* Construct a "DW_CFA_def_cfa_register <register>" instruction, | |
822 | indicating the CFA register has changed to <register> but the | |
21810de4 RS |
823 | offset has not changed. This requires the old CFA to have |
824 | been set as a register plus offset rather than a general | |
825 | DW_CFA_def_cfa_expression. */ | |
647a1567 | 826 | cfi->dw_cfi_opc = DW_CFA_def_cfa_register; |
57e16c96 | 827 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
647a1567 | 828 | } |
21810de4 RS |
829 | else if (new_cfa->indirect == 0 |
830 | && new_cfa->offset.is_constant (&const_offset)) | |
647a1567 RH |
831 | { |
832 | /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction, | |
833 | indicating the CFA register has changed to <register> with | |
834 | the specified offset. The data factoring for DW_CFA_def_cfa_sf | |
835 | happens in output_cfi, or in the assembler via the .cfi_def_cfa | |
836 | directive. */ | |
21810de4 | 837 | if (const_offset < 0) |
647a1567 RH |
838 | cfi->dw_cfi_opc = DW_CFA_def_cfa_sf; |
839 | else | |
840 | cfi->dw_cfi_opc = DW_CFA_def_cfa; | |
57e16c96 | 841 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
21810de4 | 842 | cfi->dw_cfi_oprnd2.dw_cfi_offset = const_offset; |
647a1567 RH |
843 | } |
844 | else | |
845 | { | |
846 | /* Construct a DW_CFA_def_cfa_expression instruction to | |
847 | calculate the CFA using a full location expression since no | |
848 | register-offset pair is available. */ | |
84562394 | 849 | struct dw_loc_descr_node *loc_list; |
647a1567 RH |
850 | |
851 | cfi->dw_cfi_opc = DW_CFA_def_cfa_expression; | |
57e16c96 | 852 | loc_list = build_cfa_loc (new_cfa, 0); |
647a1567 | 853 | cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list; |
21810de4 RS |
854 | if (!new_cfa->offset.is_constant () |
855 | || !new_cfa->base_offset.is_constant ()) | |
856 | /* It's hard to reconstruct the CFA location for a polynomial | |
857 | expression, so just cache it instead. */ | |
858 | cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc = copy_cfa (new_cfa); | |
859 | else | |
860 | cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc = NULL; | |
647a1567 RH |
861 | } |
862 | ||
57e16c96 RH |
863 | return cfi; |
864 | } | |
865 | ||
866 | /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */ | |
867 | ||
868 | static void | |
869 | def_cfa_1 (dw_cfa_location *new_cfa) | |
870 | { | |
871 | dw_cfi_ref cfi; | |
872 | ||
43215a89 RH |
873 | if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0) |
874 | cur_trace->cfa_store.offset = new_cfa->offset; | |
57e16c96 RH |
875 | |
876 | cfi = def_cfa_0 (&cur_row->cfa, new_cfa); | |
877 | if (cfi) | |
878 | { | |
879 | cur_row->cfa = *new_cfa; | |
8f1594b2 RH |
880 | cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression |
881 | ? cfi : NULL); | |
57e16c96 RH |
882 | |
883 | add_cfi (cfi); | |
884 | } | |
647a1567 RH |
885 | } |
886 | ||
887 | /* Add the CFI for saving a register. REG is the CFA column number. | |
647a1567 RH |
888 | If SREG is -1, the register is saved at OFFSET from the CFA; |
889 | otherwise it is saved in SREG. */ | |
890 | ||
891 | static void | |
21810de4 | 892 | reg_save (unsigned int reg, unsigned int sreg, poly_int64 offset) |
647a1567 | 893 | { |
3edb53aa | 894 | dw_fde_ref fde = cfun ? cfun->fde : NULL; |
647a1567 | 895 | dw_cfi_ref cfi = new_cfi (); |
647a1567 RH |
896 | |
897 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
898 | ||
21810de4 | 899 | if (sreg == INVALID_REGNUM) |
647a1567 | 900 | { |
21810de4 RS |
901 | HOST_WIDE_INT const_offset; |
902 | /* When stack is aligned, store REG using DW_CFA_expression with FP. */ | |
903 | if (fde && fde->stack_realign) | |
904 | { | |
905 | cfi->dw_cfi_opc = DW_CFA_expression; | |
906 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
907 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
908 | = build_cfa_aligned_loc (&cur_row->cfa, offset, | |
909 | fde->stack_realignment); | |
910 | } | |
911 | else if (offset.is_constant (&const_offset)) | |
912 | { | |
913 | if (need_data_align_sf_opcode (const_offset)) | |
914 | cfi->dw_cfi_opc = DW_CFA_offset_extended_sf; | |
915 | else if (reg & ~0x3f) | |
916 | cfi->dw_cfi_opc = DW_CFA_offset_extended; | |
917 | else | |
918 | cfi->dw_cfi_opc = DW_CFA_offset; | |
919 | cfi->dw_cfi_oprnd2.dw_cfi_offset = const_offset; | |
920 | } | |
647a1567 | 921 | else |
21810de4 RS |
922 | { |
923 | cfi->dw_cfi_opc = DW_CFA_expression; | |
924 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
925 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
926 | = build_cfa_loc (&cur_row->cfa, offset); | |
927 | } | |
647a1567 RH |
928 | } |
929 | else if (sreg == reg) | |
f1a0e830 RH |
930 | { |
931 | /* While we could emit something like DW_CFA_same_value or | |
932 | DW_CFA_restore, we never expect to see something like that | |
933 | in a prologue. This is more likely to be a bug. A backend | |
934 | can always bypass this by using REG_CFA_RESTORE directly. */ | |
935 | gcc_unreachable (); | |
936 | } | |
647a1567 RH |
937 | else |
938 | { | |
939 | cfi->dw_cfi_opc = DW_CFA_register; | |
940 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg; | |
941 | } | |
942 | ||
3edb53aa | 943 | add_cfi (cfi); |
f1a0e830 | 944 | update_row_reg_save (cur_row, reg, cfi); |
647a1567 RH |
945 | } |
946 | ||
9a08d230 RH |
947 | /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note |
948 | and adjust data structures to match. */ | |
647a1567 RH |
949 | |
950 | static void | |
23f57f5a | 951 | notice_args_size (rtx_insn *insn) |
647a1567 | 952 | { |
68184180 | 953 | poly_int64 args_size, delta; |
9a08d230 | 954 | rtx note; |
647a1567 | 955 | |
9a08d230 RH |
956 | note = find_reg_note (insn, REG_ARGS_SIZE, NULL); |
957 | if (note == NULL) | |
958 | return; | |
f17d3401 | 959 | |
464b6c11 EB |
960 | if (!cur_trace->eh_head) |
961 | cur_trace->args_size_defined_for_eh = true; | |
962 | ||
68184180 | 963 | args_size = get_args_size (note); |
9a08d230 | 964 | delta = args_size - cur_trace->end_true_args_size; |
68184180 | 965 | if (known_eq (delta, 0)) |
9a08d230 | 966 | return; |
647a1567 | 967 | |
9a08d230 | 968 | cur_trace->end_true_args_size = args_size; |
43215a89 | 969 | |
9a08d230 RH |
970 | /* If the CFA is computed off the stack pointer, then we must adjust |
971 | the computation of the CFA as well. */ | |
972 | if (cur_cfa->reg == dw_stack_pointer_regnum) | |
973 | { | |
974 | gcc_assert (!cur_cfa->indirect); | |
647a1567 | 975 | |
9a08d230 RH |
976 | /* Convert a change in args_size (always a positive in the |
977 | direction of stack growth) to a change in stack pointer. */ | |
581edfa3 TS |
978 | if (!STACK_GROWS_DOWNWARD) |
979 | delta = -delta; | |
980 | ||
9a08d230 RH |
981 | cur_cfa->offset += delta; |
982 | } | |
647a1567 RH |
983 | } |
984 | ||
9a08d230 RH |
985 | /* A subroutine of scan_trace. INSN is can_throw_internal. Update the |
986 | data within the trace related to EH insns and args_size. */ | |
647a1567 RH |
987 | |
988 | static void | |
dc01c3d1 | 989 | notice_eh_throw (rtx_insn *insn) |
647a1567 | 990 | { |
68184180 | 991 | poly_int64 args_size = cur_trace->end_true_args_size; |
9a08d230 | 992 | if (cur_trace->eh_head == NULL) |
647a1567 | 993 | { |
9a08d230 RH |
994 | cur_trace->eh_head = insn; |
995 | cur_trace->beg_delay_args_size = args_size; | |
996 | cur_trace->end_delay_args_size = args_size; | |
647a1567 | 997 | } |
68184180 | 998 | else if (maybe_ne (cur_trace->end_delay_args_size, args_size)) |
647a1567 | 999 | { |
9a08d230 | 1000 | cur_trace->end_delay_args_size = args_size; |
647a1567 | 1001 | |
9a08d230 RH |
1002 | /* ??? If the CFA is the stack pointer, search backward for the last |
1003 | CFI note and insert there. Given that the stack changed for the | |
1004 | args_size change, there *must* be such a note in between here and | |
1005 | the last eh insn. */ | |
1006 | add_cfi_args_size (args_size); | |
1007 | } | |
647a1567 RH |
1008 | } |
1009 | ||
7263c6d7 | 1010 | /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */ |
4f42d714 RH |
1011 | /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is |
1012 | used in places where rtl is prohibited. */ | |
7263c6d7 RH |
1013 | |
1014 | static inline unsigned | |
1015 | dwf_regno (const_rtx reg) | |
1016 | { | |
362805fc | 1017 | gcc_assert (REGNO (reg) < FIRST_PSEUDO_REGISTER); |
4f42d714 | 1018 | return DWARF_FRAME_REGNUM (REGNO (reg)); |
7263c6d7 RH |
1019 | } |
1020 | ||
647a1567 RH |
1021 | /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */ |
1022 | ||
1023 | static bool | |
1024 | compare_reg_or_pc (rtx x, rtx y) | |
1025 | { | |
1026 | if (REG_P (x) && REG_P (y)) | |
1027 | return REGNO (x) == REGNO (y); | |
1028 | return x == y; | |
1029 | } | |
1030 | ||
1031 | /* Record SRC as being saved in DEST. DEST may be null to delete an | |
1032 | existing entry. SRC may be a register or PC_RTX. */ | |
1033 | ||
1034 | static void | |
1035 | record_reg_saved_in_reg (rtx dest, rtx src) | |
1036 | { | |
1037 | reg_saved_in_data *elt; | |
1038 | size_t i; | |
1039 | ||
9771b263 | 1040 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt) |
647a1567 RH |
1041 | if (compare_reg_or_pc (elt->orig_reg, src)) |
1042 | { | |
1043 | if (dest == NULL) | |
9771b263 | 1044 | cur_trace->regs_saved_in_regs.unordered_remove (i); |
647a1567 RH |
1045 | else |
1046 | elt->saved_in_reg = dest; | |
1047 | return; | |
1048 | } | |
1049 | ||
1050 | if (dest == NULL) | |
1051 | return; | |
1052 | ||
f32682ca | 1053 | reg_saved_in_data e = {src, dest}; |
9771b263 | 1054 | cur_trace->regs_saved_in_regs.safe_push (e); |
647a1567 RH |
1055 | } |
1056 | ||
647a1567 RH |
1057 | /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at |
1058 | SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */ | |
1059 | ||
1060 | static void | |
21810de4 | 1061 | queue_reg_save (rtx reg, rtx sreg, poly_int64 offset) |
647a1567 | 1062 | { |
999646c1 | 1063 | queued_reg_save *q; |
f32682ca | 1064 | queued_reg_save e = {reg, sreg, offset}; |
999646c1 | 1065 | size_t i; |
647a1567 RH |
1066 | |
1067 | /* Duplicates waste space, but it's also necessary to remove them | |
a8e5c0e7 | 1068 | for correctness, since the queue gets output in reverse order. */ |
9771b263 | 1069 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
a8e5c0e7 | 1070 | if (compare_reg_or_pc (q->reg, reg)) |
f32682ca DN |
1071 | { |
1072 | *q = e; | |
1073 | return; | |
1074 | } | |
647a1567 | 1075 | |
9771b263 | 1076 | queued_reg_saves.safe_push (e); |
647a1567 RH |
1077 | } |
1078 | ||
1079 | /* Output all the entries in QUEUED_REG_SAVES. */ | |
1080 | ||
1081 | static void | |
1082 | dwarf2out_flush_queued_reg_saves (void) | |
1083 | { | |
999646c1 RH |
1084 | queued_reg_save *q; |
1085 | size_t i; | |
647a1567 | 1086 | |
9771b263 | 1087 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
647a1567 RH |
1088 | { |
1089 | unsigned int reg, sreg; | |
1090 | ||
1091 | record_reg_saved_in_reg (q->saved_reg, q->reg); | |
1092 | ||
a8e5c0e7 RH |
1093 | if (q->reg == pc_rtx) |
1094 | reg = DWARF_FRAME_RETURN_COLUMN; | |
1095 | else | |
7263c6d7 | 1096 | reg = dwf_regno (q->reg); |
647a1567 | 1097 | if (q->saved_reg) |
7263c6d7 | 1098 | sreg = dwf_regno (q->saved_reg); |
647a1567 RH |
1099 | else |
1100 | sreg = INVALID_REGNUM; | |
3edb53aa | 1101 | reg_save (reg, sreg, q->cfa_offset); |
647a1567 RH |
1102 | } |
1103 | ||
9771b263 | 1104 | queued_reg_saves.truncate (0); |
647a1567 RH |
1105 | } |
1106 | ||
1107 | /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved | |
1108 | location for? Or, does it clobber a register which we've previously | |
1109 | said that some other register is saved in, and for which we now | |
1110 | have a new location for? */ | |
1111 | ||
1112 | static bool | |
1113 | clobbers_queued_reg_save (const_rtx insn) | |
1114 | { | |
999646c1 RH |
1115 | queued_reg_save *q; |
1116 | size_t iq; | |
647a1567 | 1117 | |
9771b263 | 1118 | FOR_EACH_VEC_ELT (queued_reg_saves, iq, q) |
647a1567 | 1119 | { |
999646c1 | 1120 | size_t ir; |
647a1567 RH |
1121 | reg_saved_in_data *rir; |
1122 | ||
1123 | if (modified_in_p (q->reg, insn)) | |
1124 | return true; | |
1125 | ||
9771b263 | 1126 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, ir, rir) |
647a1567 RH |
1127 | if (compare_reg_or_pc (q->reg, rir->orig_reg) |
1128 | && modified_in_p (rir->saved_in_reg, insn)) | |
1129 | return true; | |
1130 | } | |
1131 | ||
1132 | return false; | |
1133 | } | |
1134 | ||
1135 | /* What register, if any, is currently saved in REG? */ | |
1136 | ||
1137 | static rtx | |
1138 | reg_saved_in (rtx reg) | |
1139 | { | |
1140 | unsigned int regn = REGNO (reg); | |
999646c1 | 1141 | queued_reg_save *q; |
647a1567 RH |
1142 | reg_saved_in_data *rir; |
1143 | size_t i; | |
1144 | ||
9771b263 | 1145 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
647a1567 RH |
1146 | if (q->saved_reg && regn == REGNO (q->saved_reg)) |
1147 | return q->reg; | |
1148 | ||
9771b263 | 1149 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, rir) |
647a1567 RH |
1150 | if (regn == REGNO (rir->saved_in_reg)) |
1151 | return rir->orig_reg; | |
1152 | ||
1153 | return NULL_RTX; | |
1154 | } | |
1155 | ||
647a1567 RH |
1156 | /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */ |
1157 | ||
1158 | static void | |
89e25f95 | 1159 | dwarf2out_frame_debug_def_cfa (rtx pat) |
647a1567 | 1160 | { |
9a08d230 | 1161 | memset (cur_cfa, 0, sizeof (*cur_cfa)); |
647a1567 | 1162 | |
21810de4 | 1163 | pat = strip_offset (pat, &cur_cfa->offset); |
8f1594b2 RH |
1164 | if (MEM_P (pat)) |
1165 | { | |
9a08d230 | 1166 | cur_cfa->indirect = 1; |
21810de4 | 1167 | pat = strip_offset (XEXP (pat, 0), &cur_cfa->base_offset); |
647a1567 | 1168 | } |
8f1594b2 RH |
1169 | /* ??? If this fails, we could be calling into the _loc functions to |
1170 | define a full expression. So far no port does that. */ | |
1171 | gcc_assert (REG_P (pat)); | |
9a08d230 | 1172 | cur_cfa->reg = dwf_regno (pat); |
647a1567 RH |
1173 | } |
1174 | ||
1175 | /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */ | |
1176 | ||
1177 | static void | |
89e25f95 | 1178 | dwarf2out_frame_debug_adjust_cfa (rtx pat) |
647a1567 RH |
1179 | { |
1180 | rtx src, dest; | |
1181 | ||
1182 | gcc_assert (GET_CODE (pat) == SET); | |
1183 | dest = XEXP (pat, 0); | |
1184 | src = XEXP (pat, 1); | |
1185 | ||
1186 | switch (GET_CODE (src)) | |
1187 | { | |
1188 | case PLUS: | |
9a08d230 | 1189 | gcc_assert (dwf_regno (XEXP (src, 0)) == cur_cfa->reg); |
21810de4 | 1190 | cur_cfa->offset -= rtx_to_poly_int64 (XEXP (src, 1)); |
647a1567 RH |
1191 | break; |
1192 | ||
1193 | case REG: | |
9a08d230 | 1194 | break; |
647a1567 RH |
1195 | |
1196 | default: | |
9a08d230 | 1197 | gcc_unreachable (); |
647a1567 RH |
1198 | } |
1199 | ||
9a08d230 RH |
1200 | cur_cfa->reg = dwf_regno (dest); |
1201 | gcc_assert (cur_cfa->indirect == 0); | |
647a1567 RH |
1202 | } |
1203 | ||
1204 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */ | |
1205 | ||
1206 | static void | |
89e25f95 | 1207 | dwarf2out_frame_debug_cfa_offset (rtx set) |
647a1567 | 1208 | { |
21810de4 | 1209 | poly_int64 offset; |
647a1567 RH |
1210 | rtx src, addr, span; |
1211 | unsigned int sregno; | |
1212 | ||
1213 | src = XEXP (set, 1); | |
1214 | addr = XEXP (set, 0); | |
1215 | gcc_assert (MEM_P (addr)); | |
1216 | addr = XEXP (addr, 0); | |
1217 | ||
1218 | /* As documented, only consider extremely simple addresses. */ | |
1219 | switch (GET_CODE (addr)) | |
1220 | { | |
1221 | case REG: | |
9a08d230 RH |
1222 | gcc_assert (dwf_regno (addr) == cur_cfa->reg); |
1223 | offset = -cur_cfa->offset; | |
647a1567 RH |
1224 | break; |
1225 | case PLUS: | |
9a08d230 | 1226 | gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_cfa->reg); |
21810de4 | 1227 | offset = rtx_to_poly_int64 (XEXP (addr, 1)) - cur_cfa->offset; |
647a1567 RH |
1228 | break; |
1229 | default: | |
1230 | gcc_unreachable (); | |
1231 | } | |
1232 | ||
1233 | if (src == pc_rtx) | |
1234 | { | |
1235 | span = NULL; | |
1236 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1237 | } | |
43215a89 | 1238 | else |
647a1567 RH |
1239 | { |
1240 | span = targetm.dwarf_register_span (src); | |
7263c6d7 | 1241 | sregno = dwf_regno (src); |
647a1567 RH |
1242 | } |
1243 | ||
1244 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1245 | a different flushing heuristic for epilogues. */ | |
1246 | if (!span) | |
3edb53aa | 1247 | reg_save (sregno, INVALID_REGNUM, offset); |
647a1567 RH |
1248 | else |
1249 | { | |
1250 | /* We have a PARALLEL describing where the contents of SRC live. | |
a4d47cac | 1251 | Adjust the offset for each piece of the PARALLEL. */ |
21810de4 | 1252 | poly_int64 span_offset = offset; |
647a1567 RH |
1253 | |
1254 | gcc_assert (GET_CODE (span) == PARALLEL); | |
1255 | ||
a4d47cac EB |
1256 | const int par_len = XVECLEN (span, 0); |
1257 | for (int par_index = 0; par_index < par_len; par_index++) | |
647a1567 RH |
1258 | { |
1259 | rtx elem = XVECEXP (span, 0, par_index); | |
7263c6d7 | 1260 | sregno = dwf_regno (src); |
3edb53aa | 1261 | reg_save (sregno, INVALID_REGNUM, span_offset); |
647a1567 RH |
1262 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); |
1263 | } | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */ | |
1268 | ||
1269 | static void | |
89e25f95 | 1270 | dwarf2out_frame_debug_cfa_register (rtx set) |
647a1567 RH |
1271 | { |
1272 | rtx src, dest; | |
1273 | unsigned sregno, dregno; | |
1274 | ||
1275 | src = XEXP (set, 1); | |
1276 | dest = XEXP (set, 0); | |
1277 | ||
a8e5c0e7 | 1278 | record_reg_saved_in_reg (dest, src); |
647a1567 RH |
1279 | if (src == pc_rtx) |
1280 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1281 | else | |
7263c6d7 | 1282 | sregno = dwf_regno (src); |
647a1567 | 1283 | |
7263c6d7 | 1284 | dregno = dwf_regno (dest); |
647a1567 RH |
1285 | |
1286 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1287 | a different flushing heuristic for epilogues. */ | |
3edb53aa | 1288 | reg_save (sregno, dregno, 0); |
647a1567 RH |
1289 | } |
1290 | ||
ac5b3eff | 1291 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ |
647a1567 RH |
1292 | |
1293 | static void | |
89e25f95 | 1294 | dwarf2out_frame_debug_cfa_expression (rtx set) |
647a1567 RH |
1295 | { |
1296 | rtx src, dest, span; | |
1297 | dw_cfi_ref cfi = new_cfi (); | |
f1a0e830 | 1298 | unsigned regno; |
647a1567 RH |
1299 | |
1300 | dest = SET_DEST (set); | |
1301 | src = SET_SRC (set); | |
1302 | ||
1303 | gcc_assert (REG_P (src)); | |
1304 | gcc_assert (MEM_P (dest)); | |
1305 | ||
1306 | span = targetm.dwarf_register_span (src); | |
1307 | gcc_assert (!span); | |
1308 | ||
f1a0e830 RH |
1309 | regno = dwf_regno (src); |
1310 | ||
647a1567 | 1311 | cfi->dw_cfi_opc = DW_CFA_expression; |
f1a0e830 | 1312 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno; |
647a1567 RH |
1313 | cfi->dw_cfi_oprnd2.dw_cfi_loc |
1314 | = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest), | |
1315 | GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); | |
1316 | ||
1317 | /* ??? We'd like to use queue_reg_save, were the interface different, | |
1318 | and, as above, we could manage flushing for epilogues. */ | |
3edb53aa | 1319 | add_cfi (cfi); |
f1a0e830 | 1320 | update_row_reg_save (cur_row, regno, cfi); |
647a1567 RH |
1321 | } |
1322 | ||
ac5b3eff JW |
1323 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_VAL_EXPRESSION |
1324 | note. */ | |
1325 | ||
1326 | static void | |
1327 | dwarf2out_frame_debug_cfa_val_expression (rtx set) | |
1328 | { | |
1329 | rtx dest = SET_DEST (set); | |
1330 | gcc_assert (REG_P (dest)); | |
1331 | ||
1332 | rtx span = targetm.dwarf_register_span (dest); | |
1333 | gcc_assert (!span); | |
1334 | ||
1335 | rtx src = SET_SRC (set); | |
1336 | dw_cfi_ref cfi = new_cfi (); | |
1337 | cfi->dw_cfi_opc = DW_CFA_val_expression; | |
1338 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = dwf_regno (dest); | |
1339 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
1340 | = mem_loc_descriptor (src, GET_MODE (src), | |
1341 | GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); | |
1342 | add_cfi (cfi); | |
1343 | update_row_reg_save (cur_row, dwf_regno (dest), cfi); | |
1344 | } | |
1345 | ||
647a1567 RH |
1346 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */ |
1347 | ||
1348 | static void | |
89e25f95 | 1349 | dwarf2out_frame_debug_cfa_restore (rtx reg) |
647a1567 | 1350 | { |
a4d47cac EB |
1351 | gcc_assert (REG_P (reg)); |
1352 | ||
1353 | rtx span = targetm.dwarf_register_span (reg); | |
1354 | if (!span) | |
1355 | { | |
1356 | unsigned int regno = dwf_regno (reg); | |
1357 | add_cfi_restore (regno); | |
1358 | update_row_reg_save (cur_row, regno, NULL); | |
1359 | } | |
1360 | else | |
1361 | { | |
1362 | /* We have a PARALLEL describing where the contents of REG live. | |
1363 | Restore the register for each piece of the PARALLEL. */ | |
1364 | gcc_assert (GET_CODE (span) == PARALLEL); | |
647a1567 | 1365 | |
a4d47cac EB |
1366 | const int par_len = XVECLEN (span, 0); |
1367 | for (int par_index = 0; par_index < par_len; par_index++) | |
1368 | { | |
1369 | reg = XVECEXP (span, 0, par_index); | |
1370 | gcc_assert (REG_P (reg)); | |
1371 | unsigned int regno = dwf_regno (reg); | |
1372 | add_cfi_restore (regno); | |
1373 | update_row_reg_save (cur_row, regno, NULL); | |
1374 | } | |
1375 | } | |
647a1567 RH |
1376 | } |
1377 | ||
1378 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE. | |
dfe1fe91 EB |
1379 | |
1380 | ??? Perhaps we should note in the CIE where windows are saved (instead | |
1381 | of assuming 0(cfa)) and what registers are in the window. */ | |
647a1567 RH |
1382 | |
1383 | static void | |
acdf7336 | 1384 | dwarf2out_frame_debug_cfa_window_save (void) |
647a1567 RH |
1385 | { |
1386 | dw_cfi_ref cfi = new_cfi (); | |
1387 | ||
1388 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; | |
3edb53aa | 1389 | add_cfi (cfi); |
acdf7336 SN |
1390 | cur_row->window_save = true; |
1391 | } | |
1392 | ||
1393 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_TOGGLE_RA_MANGLE. | |
1394 | Note: DW_CFA_GNU_window_save dwarf opcode is reused for toggling RA mangle | |
1395 | state, this is a target specific operation on AArch64 and can only be used | |
1396 | on other targets if they don't use the window save operation otherwise. */ | |
1397 | ||
1398 | static void | |
1399 | dwarf2out_frame_debug_cfa_toggle_ra_mangle (void) | |
1400 | { | |
1401 | dw_cfi_ref cfi = new_cfi (); | |
1402 | ||
1403 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; | |
1404 | add_cfi (cfi); | |
1405 | cur_row->ra_mangled = !cur_row->ra_mangled; | |
647a1567 RH |
1406 | } |
1407 | ||
1408 | /* Record call frame debugging information for an expression EXPR, | |
1409 | which either sets SP or FP (adjusting how we calculate the frame | |
1410 | address) or saves a register to the stack or another register. | |
1411 | LABEL indicates the address of EXPR. | |
1412 | ||
1413 | This function encodes a state machine mapping rtxes to actions on | |
1414 | cfa, cfa_store, and cfa_temp.reg. We describe these rules so | |
1415 | users need not read the source code. | |
1416 | ||
1417 | The High-Level Picture | |
1418 | ||
1419 | Changes in the register we use to calculate the CFA: Currently we | |
1420 | assume that if you copy the CFA register into another register, we | |
1421 | should take the other one as the new CFA register; this seems to | |
1422 | work pretty well. If it's wrong for some target, it's simple | |
1423 | enough not to set RTX_FRAME_RELATED_P on the insn in question. | |
1424 | ||
1425 | Changes in the register we use for saving registers to the stack: | |
1426 | This is usually SP, but not always. Again, we deduce that if you | |
1427 | copy SP into another register (and SP is not the CFA register), | |
1428 | then the new register is the one we will be using for register | |
1429 | saves. This also seems to work. | |
1430 | ||
1431 | Register saves: There's not much guesswork about this one; if | |
1432 | RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a | |
1433 | register save, and the register used to calculate the destination | |
1434 | had better be the one we think we're using for this purpose. | |
1435 | It's also assumed that a copy from a call-saved register to another | |
1436 | register is saving that register if RTX_FRAME_RELATED_P is set on | |
1437 | that instruction. If the copy is from a call-saved register to | |
1438 | the *same* register, that means that the register is now the same | |
1439 | value as in the caller. | |
1440 | ||
1441 | Except: If the register being saved is the CFA register, and the | |
1442 | offset is nonzero, we are saving the CFA, so we assume we have to | |
1443 | use DW_CFA_def_cfa_expression. If the offset is 0, we assume that | |
1444 | the intent is to save the value of SP from the previous frame. | |
1445 | ||
1446 | In addition, if a register has previously been saved to a different | |
1447 | register, | |
1448 | ||
1449 | Invariants / Summaries of Rules | |
1450 | ||
1451 | cfa current rule for calculating the CFA. It usually | |
f17d3401 | 1452 | consists of a register and an offset. This is |
9a08d230 | 1453 | actually stored in *cur_cfa, but abbreviated |
f17d3401 | 1454 | for the purposes of this documentation. |
647a1567 RH |
1455 | cfa_store register used by prologue code to save things to the stack |
1456 | cfa_store.offset is the offset from the value of | |
1457 | cfa_store.reg to the actual CFA | |
1458 | cfa_temp register holding an integral value. cfa_temp.offset | |
1459 | stores the value, which will be used to adjust the | |
1460 | stack pointer. cfa_temp is also used like cfa_store, | |
1461 | to track stores to the stack via fp or a temp reg. | |
1462 | ||
1463 | Rules 1- 4: Setting a register's value to cfa.reg or an expression | |
1464 | with cfa.reg as the first operand changes the cfa.reg and its | |
1465 | cfa.offset. Rule 1 and 4 also set cfa_temp.reg and | |
1466 | cfa_temp.offset. | |
1467 | ||
1468 | Rules 6- 9: Set a non-cfa.reg register value to a constant or an | |
1469 | expression yielding a constant. This sets cfa_temp.reg | |
1470 | and cfa_temp.offset. | |
1471 | ||
1472 | Rule 5: Create a new register cfa_store used to save items to the | |
1473 | stack. | |
1474 | ||
1475 | Rules 10-14: Save a register to the stack. Define offset as the | |
1476 | difference of the original location and cfa_store's | |
1477 | location (or cfa_temp's location if cfa_temp is used). | |
1478 | ||
1479 | Rules 16-20: If AND operation happens on sp in prologue, we assume | |
1480 | stack is realigned. We will use a group of DW_OP_XXX | |
1481 | expressions to represent the location of the stored | |
1482 | register instead of CFA+offset. | |
1483 | ||
1484 | The Rules | |
1485 | ||
1486 | "{a,b}" indicates a choice of a xor b. | |
1487 | "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg. | |
1488 | ||
1489 | Rule 1: | |
1490 | (set <reg1> <reg2>:cfa.reg) | |
1491 | effects: cfa.reg = <reg1> | |
1492 | cfa.offset unchanged | |
1493 | cfa_temp.reg = <reg1> | |
1494 | cfa_temp.offset = cfa.offset | |
1495 | ||
1496 | Rule 2: | |
1497 | (set sp ({minus,plus,losum} {sp,fp}:cfa.reg | |
1498 | {<const_int>,<reg>:cfa_temp.reg})) | |
1499 | effects: cfa.reg = sp if fp used | |
1500 | cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp | |
1501 | cfa_store.offset += {+/- <const_int>, cfa_temp.offset} | |
1502 | if cfa_store.reg==sp | |
1503 | ||
1504 | Rule 3: | |
1505 | (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>)) | |
1506 | effects: cfa.reg = fp | |
1507 | cfa_offset += +/- <const_int> | |
1508 | ||
1509 | Rule 4: | |
1510 | (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>)) | |
1511 | constraints: <reg1> != fp | |
1512 | <reg1> != sp | |
1513 | effects: cfa.reg = <reg1> | |
1514 | cfa_temp.reg = <reg1> | |
1515 | cfa_temp.offset = cfa.offset | |
1516 | ||
1517 | Rule 5: | |
1518 | (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg)) | |
1519 | constraints: <reg1> != fp | |
1520 | <reg1> != sp | |
1521 | effects: cfa_store.reg = <reg1> | |
1522 | cfa_store.offset = cfa.offset - cfa_temp.offset | |
1523 | ||
1524 | Rule 6: | |
1525 | (set <reg> <const_int>) | |
1526 | effects: cfa_temp.reg = <reg> | |
1527 | cfa_temp.offset = <const_int> | |
1528 | ||
1529 | Rule 7: | |
1530 | (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>)) | |
1531 | effects: cfa_temp.reg = <reg1> | |
1532 | cfa_temp.offset |= <const_int> | |
1533 | ||
1534 | Rule 8: | |
1535 | (set <reg> (high <exp>)) | |
1536 | effects: none | |
1537 | ||
1538 | Rule 9: | |
1539 | (set <reg> (lo_sum <exp> <const_int>)) | |
1540 | effects: cfa_temp.reg = <reg> | |
1541 | cfa_temp.offset = <const_int> | |
1542 | ||
1543 | Rule 10: | |
1544 | (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>) | |
1545 | effects: cfa_store.offset -= <const_int> | |
1546 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1547 | cfa.reg = sp | |
1548 | cfa.base_offset = -cfa_store.offset | |
1549 | ||
1550 | Rule 11: | |
1551 | (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>) | |
1552 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1553 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1554 | cfa.reg = sp | |
1555 | cfa.base_offset = -cfa_store.offset | |
1556 | ||
1557 | Rule 12: | |
1558 | (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>)) | |
1559 | ||
1560 | <reg2>) | |
1561 | effects: cfa.reg = <reg1> | |
1562 | cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset | |
1563 | ||
1564 | Rule 13: | |
1565 | (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>) | |
1566 | effects: cfa.reg = <reg1> | |
1567 | cfa.base_offset = -{cfa_store,cfa_temp}.offset | |
1568 | ||
1569 | Rule 14: | |
1570 | (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>) | |
1571 | effects: cfa.reg = <reg1> | |
1572 | cfa.base_offset = -cfa_temp.offset | |
1573 | cfa_temp.offset -= mode_size(mem) | |
1574 | ||
1575 | Rule 15: | |
1576 | (set <reg> {unspec, unspec_volatile}) | |
1577 | effects: target-dependent | |
1578 | ||
1579 | Rule 16: | |
1580 | (set sp (and: sp <const_int>)) | |
1581 | constraints: cfa_store.reg == sp | |
a518b996 | 1582 | effects: cfun->fde.stack_realign = 1 |
647a1567 RH |
1583 | cfa_store.offset = 0 |
1584 | fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp | |
1585 | ||
1586 | Rule 17: | |
1587 | (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int)))) | |
1588 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1589 | ||
1590 | Rule 18: | |
1591 | (set (mem ({pre_inc, pre_dec} sp)) fp) | |
1592 | constraints: fde->stack_realign == 1 | |
1593 | effects: cfa_store.offset = 0 | |
1594 | cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1595 | ||
1596 | Rule 19: | |
1597 | (set (mem ({pre_inc, pre_dec} sp)) cfa.reg) | |
1598 | constraints: fde->stack_realign == 1 | |
1599 | && cfa.offset == 0 | |
1600 | && cfa.indirect == 0 | |
1601 | && cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1602 | effects: Use DW_CFA_def_cfa_expression to define cfa | |
1603 | cfa.reg == fde->drap_reg */ | |
1604 | ||
1605 | static void | |
89e25f95 | 1606 | dwarf2out_frame_debug_expr (rtx expr) |
647a1567 RH |
1607 | { |
1608 | rtx src, dest, span; | |
21810de4 | 1609 | poly_int64 offset; |
647a1567 RH |
1610 | dw_fde_ref fde; |
1611 | ||
1612 | /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of | |
1613 | the PARALLEL independently. The first element is always processed if | |
1614 | it is a SET. This is for backward compatibility. Other elements | |
1615 | are processed only if they are SETs and the RTX_FRAME_RELATED_P | |
1616 | flag is set in them. */ | |
1617 | if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE) | |
1618 | { | |
1619 | int par_index; | |
1620 | int limit = XVECLEN (expr, 0); | |
1621 | rtx elem; | |
1622 | ||
1623 | /* PARALLELs have strict read-modify-write semantics, so we | |
1624 | ought to evaluate every rvalue before changing any lvalue. | |
1625 | It's cumbersome to do that in general, but there's an | |
1626 | easy approximation that is enough for all current users: | |
1627 | handle register saves before register assignments. */ | |
1628 | if (GET_CODE (expr) == PARALLEL) | |
1629 | for (par_index = 0; par_index < limit; par_index++) | |
1630 | { | |
1631 | elem = XVECEXP (expr, 0, par_index); | |
1632 | if (GET_CODE (elem) == SET | |
1633 | && MEM_P (SET_DEST (elem)) | |
1634 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
89e25f95 | 1635 | dwarf2out_frame_debug_expr (elem); |
647a1567 RH |
1636 | } |
1637 | ||
1638 | for (par_index = 0; par_index < limit; par_index++) | |
1639 | { | |
1640 | elem = XVECEXP (expr, 0, par_index); | |
1641 | if (GET_CODE (elem) == SET | |
1642 | && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE) | |
1643 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
89e25f95 | 1644 | dwarf2out_frame_debug_expr (elem); |
647a1567 RH |
1645 | } |
1646 | return; | |
1647 | } | |
1648 | ||
1649 | gcc_assert (GET_CODE (expr) == SET); | |
1650 | ||
1651 | src = SET_SRC (expr); | |
1652 | dest = SET_DEST (expr); | |
1653 | ||
1654 | if (REG_P (src)) | |
1655 | { | |
1656 | rtx rsi = reg_saved_in (src); | |
1657 | if (rsi) | |
1658 | src = rsi; | |
1659 | } | |
1660 | ||
a518b996 | 1661 | fde = cfun->fde; |
647a1567 RH |
1662 | |
1663 | switch (GET_CODE (dest)) | |
1664 | { | |
1665 | case REG: | |
1666 | switch (GET_CODE (src)) | |
1667 | { | |
1668 | /* Setting FP from SP. */ | |
1669 | case REG: | |
9a08d230 | 1670 | if (cur_cfa->reg == dwf_regno (src)) |
647a1567 RH |
1671 | { |
1672 | /* Rule 1 */ | |
1673 | /* Update the CFA rule wrt SP or FP. Make sure src is | |
1674 | relative to the current CFA register. | |
1675 | ||
1676 | We used to require that dest be either SP or FP, but the | |
1677 | ARM copies SP to a temporary register, and from there to | |
1678 | FP. So we just rely on the backends to only set | |
1679 | RTX_FRAME_RELATED_P on appropriate insns. */ | |
9a08d230 RH |
1680 | cur_cfa->reg = dwf_regno (dest); |
1681 | cur_trace->cfa_temp.reg = cur_cfa->reg; | |
1682 | cur_trace->cfa_temp.offset = cur_cfa->offset; | |
647a1567 RH |
1683 | } |
1684 | else | |
1685 | { | |
1686 | /* Saving a register in a register. */ | |
1687 | gcc_assert (!fixed_regs [REGNO (dest)] | |
1688 | /* For the SPARC and its register window. */ | |
7263c6d7 | 1689 | || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN)); |
647a1567 RH |
1690 | |
1691 | /* After stack is aligned, we can only save SP in FP | |
1692 | if drap register is used. In this case, we have | |
1693 | to restore stack pointer with the CFA value and we | |
1694 | don't generate this DWARF information. */ | |
1695 | if (fde | |
1696 | && fde->stack_realign | |
1697 | && REGNO (src) == STACK_POINTER_REGNUM) | |
1698 | gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM | |
1699 | && fde->drap_reg != INVALID_REGNUM | |
9a08d230 | 1700 | && cur_cfa->reg != dwf_regno (src)); |
647a1567 | 1701 | else |
89e25f95 | 1702 | queue_reg_save (src, dest, 0); |
647a1567 RH |
1703 | } |
1704 | break; | |
1705 | ||
1706 | case PLUS: | |
1707 | case MINUS: | |
1708 | case LO_SUM: | |
1709 | if (dest == stack_pointer_rtx) | |
1710 | { | |
1711 | /* Rule 2 */ | |
1712 | /* Adjusting SP. */ | |
21810de4 | 1713 | if (REG_P (XEXP (src, 1))) |
647a1567 | 1714 | { |
43215a89 RH |
1715 | gcc_assert (dwf_regno (XEXP (src, 1)) |
1716 | == cur_trace->cfa_temp.reg); | |
1717 | offset = cur_trace->cfa_temp.offset; | |
647a1567 | 1718 | } |
21810de4 RS |
1719 | else if (!poly_int_rtx_p (XEXP (src, 1), &offset)) |
1720 | gcc_unreachable (); | |
647a1567 RH |
1721 | |
1722 | if (XEXP (src, 0) == hard_frame_pointer_rtx) | |
1723 | { | |
1724 | /* Restoring SP from FP in the epilogue. */ | |
9a08d230 RH |
1725 | gcc_assert (cur_cfa->reg == dw_frame_pointer_regnum); |
1726 | cur_cfa->reg = dw_stack_pointer_regnum; | |
647a1567 RH |
1727 | } |
1728 | else if (GET_CODE (src) == LO_SUM) | |
1729 | /* Assume we've set the source reg of the LO_SUM from sp. */ | |
1730 | ; | |
1731 | else | |
1732 | gcc_assert (XEXP (src, 0) == stack_pointer_rtx); | |
1733 | ||
1734 | if (GET_CODE (src) != MINUS) | |
1735 | offset = -offset; | |
9a08d230 RH |
1736 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1737 | cur_cfa->offset += offset; | |
43215a89 RH |
1738 | if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum) |
1739 | cur_trace->cfa_store.offset += offset; | |
647a1567 RH |
1740 | } |
1741 | else if (dest == hard_frame_pointer_rtx) | |
1742 | { | |
1743 | /* Rule 3 */ | |
1744 | /* Either setting the FP from an offset of the SP, | |
1745 | or adjusting the FP */ | |
1746 | gcc_assert (frame_pointer_needed); | |
1747 | ||
1748 | gcc_assert (REG_P (XEXP (src, 0)) | |
21810de4 RS |
1749 | && dwf_regno (XEXP (src, 0)) == cur_cfa->reg); |
1750 | offset = rtx_to_poly_int64 (XEXP (src, 1)); | |
647a1567 RH |
1751 | if (GET_CODE (src) != MINUS) |
1752 | offset = -offset; | |
9a08d230 RH |
1753 | cur_cfa->offset += offset; |
1754 | cur_cfa->reg = dw_frame_pointer_regnum; | |
647a1567 RH |
1755 | } |
1756 | else | |
1757 | { | |
1758 | gcc_assert (GET_CODE (src) != MINUS); | |
1759 | ||
1760 | /* Rule 4 */ | |
1761 | if (REG_P (XEXP (src, 0)) | |
9a08d230 | 1762 | && dwf_regno (XEXP (src, 0)) == cur_cfa->reg |
21810de4 | 1763 | && poly_int_rtx_p (XEXP (src, 1), &offset)) |
647a1567 RH |
1764 | { |
1765 | /* Setting a temporary CFA register that will be copied | |
1766 | into the FP later on. */ | |
21810de4 | 1767 | offset = -offset; |
9a08d230 RH |
1768 | cur_cfa->offset += offset; |
1769 | cur_cfa->reg = dwf_regno (dest); | |
647a1567 | 1770 | /* Or used to save regs to the stack. */ |
9a08d230 RH |
1771 | cur_trace->cfa_temp.reg = cur_cfa->reg; |
1772 | cur_trace->cfa_temp.offset = cur_cfa->offset; | |
647a1567 RH |
1773 | } |
1774 | ||
1775 | /* Rule 5 */ | |
1776 | else if (REG_P (XEXP (src, 0)) | |
43215a89 | 1777 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
647a1567 RH |
1778 | && XEXP (src, 1) == stack_pointer_rtx) |
1779 | { | |
1780 | /* Setting a scratch register that we will use instead | |
1781 | of SP for saving registers to the stack. */ | |
9a08d230 | 1782 | gcc_assert (cur_cfa->reg == dw_stack_pointer_regnum); |
43215a89 RH |
1783 | cur_trace->cfa_store.reg = dwf_regno (dest); |
1784 | cur_trace->cfa_store.offset | |
9a08d230 | 1785 | = cur_cfa->offset - cur_trace->cfa_temp.offset; |
647a1567 RH |
1786 | } |
1787 | ||
1788 | /* Rule 9 */ | |
1789 | else if (GET_CODE (src) == LO_SUM | |
21810de4 RS |
1790 | && poly_int_rtx_p (XEXP (src, 1), |
1791 | &cur_trace->cfa_temp.offset)) | |
1792 | cur_trace->cfa_temp.reg = dwf_regno (dest); | |
647a1567 RH |
1793 | else |
1794 | gcc_unreachable (); | |
1795 | } | |
1796 | break; | |
1797 | ||
1798 | /* Rule 6 */ | |
1799 | case CONST_INT: | |
3a3998f3 | 1800 | case CONST_POLY_INT: |
43215a89 | 1801 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
21810de4 | 1802 | cur_trace->cfa_temp.offset = rtx_to_poly_int64 (src); |
647a1567 RH |
1803 | break; |
1804 | ||
1805 | /* Rule 7 */ | |
1806 | case IOR: | |
1807 | gcc_assert (REG_P (XEXP (src, 0)) | |
43215a89 | 1808 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
647a1567 RH |
1809 | && CONST_INT_P (XEXP (src, 1))); |
1810 | ||
43215a89 | 1811 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
21810de4 RS |
1812 | if (!can_ior_p (cur_trace->cfa_temp.offset, INTVAL (XEXP (src, 1)), |
1813 | &cur_trace->cfa_temp.offset)) | |
1814 | /* The target shouldn't generate this kind of CFI note if we | |
1815 | can't represent it. */ | |
1816 | gcc_unreachable (); | |
647a1567 RH |
1817 | break; |
1818 | ||
1819 | /* Skip over HIGH, assuming it will be followed by a LO_SUM, | |
1820 | which will fill in all of the bits. */ | |
1821 | /* Rule 8 */ | |
1822 | case HIGH: | |
1823 | break; | |
1824 | ||
1825 | /* Rule 15 */ | |
1826 | case UNSPEC: | |
1827 | case UNSPEC_VOLATILE: | |
89e25f95 BS |
1828 | /* All unspecs should be represented by REG_CFA_* notes. */ |
1829 | gcc_unreachable (); | |
647a1567 RH |
1830 | return; |
1831 | ||
1832 | /* Rule 16 */ | |
1833 | case AND: | |
1834 | /* If this AND operation happens on stack pointer in prologue, | |
1835 | we assume the stack is realigned and we extract the | |
1836 | alignment. */ | |
1837 | if (fde && XEXP (src, 0) == stack_pointer_rtx) | |
1838 | { | |
1839 | /* We interpret reg_save differently with stack_realign set. | |
1840 | Thus we must flush whatever we have queued first. */ | |
1841 | dwarf2out_flush_queued_reg_saves (); | |
1842 | ||
43215a89 RH |
1843 | gcc_assert (cur_trace->cfa_store.reg |
1844 | == dwf_regno (XEXP (src, 0))); | |
647a1567 RH |
1845 | fde->stack_realign = 1; |
1846 | fde->stack_realignment = INTVAL (XEXP (src, 1)); | |
43215a89 | 1847 | cur_trace->cfa_store.offset = 0; |
647a1567 | 1848 | |
9a08d230 RH |
1849 | if (cur_cfa->reg != dw_stack_pointer_regnum |
1850 | && cur_cfa->reg != dw_frame_pointer_regnum) | |
1851 | fde->drap_reg = cur_cfa->reg; | |
647a1567 RH |
1852 | } |
1853 | return; | |
1854 | ||
1855 | default: | |
1856 | gcc_unreachable (); | |
1857 | } | |
647a1567 RH |
1858 | break; |
1859 | ||
1860 | case MEM: | |
1861 | ||
1862 | /* Saving a register to the stack. Make sure dest is relative to the | |
1863 | CFA register. */ | |
1864 | switch (GET_CODE (XEXP (dest, 0))) | |
1865 | { | |
1866 | /* Rule 10 */ | |
1867 | /* With a push. */ | |
1868 | case PRE_MODIFY: | |
1869 | case POST_MODIFY: | |
1870 | /* We can't handle variable size modifications. */ | |
21810de4 | 1871 | offset = -rtx_to_poly_int64 (XEXP (XEXP (XEXP (dest, 0), 1), 1)); |
647a1567 RH |
1872 | |
1873 | gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
43215a89 | 1874 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
647a1567 | 1875 | |
43215a89 | 1876 | cur_trace->cfa_store.offset += offset; |
9a08d230 RH |
1877 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1878 | cur_cfa->offset = cur_trace->cfa_store.offset; | |
647a1567 RH |
1879 | |
1880 | if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY) | |
43215a89 | 1881 | offset -= cur_trace->cfa_store.offset; |
647a1567 | 1882 | else |
43215a89 | 1883 | offset = -cur_trace->cfa_store.offset; |
647a1567 RH |
1884 | break; |
1885 | ||
1886 | /* Rule 11 */ | |
1887 | case PRE_INC: | |
1888 | case PRE_DEC: | |
1889 | case POST_DEC: | |
1890 | offset = GET_MODE_SIZE (GET_MODE (dest)); | |
1891 | if (GET_CODE (XEXP (dest, 0)) == PRE_INC) | |
1892 | offset = -offset; | |
1893 | ||
1894 | gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0)) | |
1895 | == STACK_POINTER_REGNUM) | |
43215a89 | 1896 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
647a1567 | 1897 | |
43215a89 | 1898 | cur_trace->cfa_store.offset += offset; |
647a1567 RH |
1899 | |
1900 | /* Rule 18: If stack is aligned, we will use FP as a | |
1901 | reference to represent the address of the stored | |
1902 | regiser. */ | |
1903 | if (fde | |
1904 | && fde->stack_realign | |
7b4d5595 L |
1905 | && REG_P (src) |
1906 | && REGNO (src) == HARD_FRAME_POINTER_REGNUM) | |
647a1567 | 1907 | { |
9a08d230 | 1908 | gcc_assert (cur_cfa->reg != dw_frame_pointer_regnum); |
43215a89 | 1909 | cur_trace->cfa_store.offset = 0; |
647a1567 RH |
1910 | } |
1911 | ||
9a08d230 RH |
1912 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1913 | cur_cfa->offset = cur_trace->cfa_store.offset; | |
647a1567 RH |
1914 | |
1915 | if (GET_CODE (XEXP (dest, 0)) == POST_DEC) | |
43215a89 | 1916 | offset += -cur_trace->cfa_store.offset; |
647a1567 | 1917 | else |
43215a89 | 1918 | offset = -cur_trace->cfa_store.offset; |
647a1567 RH |
1919 | break; |
1920 | ||
1921 | /* Rule 12 */ | |
1922 | /* With an offset. */ | |
1923 | case PLUS: | |
1924 | case MINUS: | |
1925 | case LO_SUM: | |
1926 | { | |
7263c6d7 | 1927 | unsigned int regno; |
647a1567 | 1928 | |
21810de4 RS |
1929 | gcc_assert (REG_P (XEXP (XEXP (dest, 0), 0))); |
1930 | offset = rtx_to_poly_int64 (XEXP (XEXP (dest, 0), 1)); | |
647a1567 RH |
1931 | if (GET_CODE (XEXP (dest, 0)) == MINUS) |
1932 | offset = -offset; | |
1933 | ||
7263c6d7 | 1934 | regno = dwf_regno (XEXP (XEXP (dest, 0), 0)); |
647a1567 | 1935 | |
9a08d230 RH |
1936 | if (cur_cfa->reg == regno) |
1937 | offset -= cur_cfa->offset; | |
43215a89 RH |
1938 | else if (cur_trace->cfa_store.reg == regno) |
1939 | offset -= cur_trace->cfa_store.offset; | |
647a1567 RH |
1940 | else |
1941 | { | |
43215a89 RH |
1942 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1943 | offset -= cur_trace->cfa_temp.offset; | |
647a1567 RH |
1944 | } |
1945 | } | |
1946 | break; | |
1947 | ||
1948 | /* Rule 13 */ | |
1949 | /* Without an offset. */ | |
1950 | case REG: | |
1951 | { | |
7263c6d7 | 1952 | unsigned int regno = dwf_regno (XEXP (dest, 0)); |
647a1567 | 1953 | |
9a08d230 RH |
1954 | if (cur_cfa->reg == regno) |
1955 | offset = -cur_cfa->offset; | |
43215a89 RH |
1956 | else if (cur_trace->cfa_store.reg == regno) |
1957 | offset = -cur_trace->cfa_store.offset; | |
647a1567 RH |
1958 | else |
1959 | { | |
43215a89 RH |
1960 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1961 | offset = -cur_trace->cfa_temp.offset; | |
647a1567 RH |
1962 | } |
1963 | } | |
1964 | break; | |
1965 | ||
1966 | /* Rule 14 */ | |
1967 | case POST_INC: | |
43215a89 RH |
1968 | gcc_assert (cur_trace->cfa_temp.reg |
1969 | == dwf_regno (XEXP (XEXP (dest, 0), 0))); | |
1970 | offset = -cur_trace->cfa_temp.offset; | |
1971 | cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest)); | |
647a1567 RH |
1972 | break; |
1973 | ||
1974 | default: | |
1975 | gcc_unreachable (); | |
1976 | } | |
1977 | ||
a8e5c0e7 RH |
1978 | /* Rule 17 */ |
1979 | /* If the source operand of this MEM operation is a memory, | |
1980 | we only care how much stack grew. */ | |
1981 | if (MEM_P (src)) | |
647a1567 RH |
1982 | break; |
1983 | ||
a8e5c0e7 RH |
1984 | if (REG_P (src) |
1985 | && REGNO (src) != STACK_POINTER_REGNUM | |
647a1567 | 1986 | && REGNO (src) != HARD_FRAME_POINTER_REGNUM |
9a08d230 | 1987 | && dwf_regno (src) == cur_cfa->reg) |
647a1567 RH |
1988 | { |
1989 | /* We're storing the current CFA reg into the stack. */ | |
1990 | ||
21810de4 | 1991 | if (known_eq (cur_cfa->offset, 0)) |
647a1567 RH |
1992 | { |
1993 | /* Rule 19 */ | |
1994 | /* If stack is aligned, putting CFA reg into stack means | |
1995 | we can no longer use reg + offset to represent CFA. | |
1996 | Here we use DW_CFA_def_cfa_expression instead. The | |
1997 | result of this expression equals to the original CFA | |
1998 | value. */ | |
1999 | if (fde | |
2000 | && fde->stack_realign | |
9a08d230 RH |
2001 | && cur_cfa->indirect == 0 |
2002 | && cur_cfa->reg != dw_frame_pointer_regnum) | |
647a1567 | 2003 | { |
9a08d230 | 2004 | gcc_assert (fde->drap_reg == cur_cfa->reg); |
647a1567 | 2005 | |
9a08d230 RH |
2006 | cur_cfa->indirect = 1; |
2007 | cur_cfa->reg = dw_frame_pointer_regnum; | |
2008 | cur_cfa->base_offset = offset; | |
2009 | cur_cfa->offset = 0; | |
647a1567 RH |
2010 | |
2011 | fde->drap_reg_saved = 1; | |
647a1567 RH |
2012 | break; |
2013 | } | |
2014 | ||
2015 | /* If the source register is exactly the CFA, assume | |
2016 | we're saving SP like any other register; this happens | |
2017 | on the ARM. */ | |
89e25f95 | 2018 | queue_reg_save (stack_pointer_rtx, NULL_RTX, offset); |
647a1567 RH |
2019 | break; |
2020 | } | |
2021 | else | |
2022 | { | |
2023 | /* Otherwise, we'll need to look in the stack to | |
2024 | calculate the CFA. */ | |
2025 | rtx x = XEXP (dest, 0); | |
2026 | ||
2027 | if (!REG_P (x)) | |
2028 | x = XEXP (x, 0); | |
2029 | gcc_assert (REG_P (x)); | |
2030 | ||
9a08d230 RH |
2031 | cur_cfa->reg = dwf_regno (x); |
2032 | cur_cfa->base_offset = offset; | |
2033 | cur_cfa->indirect = 1; | |
647a1567 RH |
2034 | break; |
2035 | } | |
2036 | } | |
2037 | ||
a8e5c0e7 RH |
2038 | if (REG_P (src)) |
2039 | span = targetm.dwarf_register_span (src); | |
a4d47cac EB |
2040 | else |
2041 | span = NULL; | |
2042 | ||
a8e5c0e7 RH |
2043 | if (!span) |
2044 | queue_reg_save (src, NULL_RTX, offset); | |
2045 | else | |
2046 | { | |
2047 | /* We have a PARALLEL describing where the contents of SRC live. | |
2048 | Queue register saves for each piece of the PARALLEL. */ | |
21810de4 | 2049 | poly_int64 span_offset = offset; |
647a1567 | 2050 | |
a8e5c0e7 | 2051 | gcc_assert (GET_CODE (span) == PARALLEL); |
647a1567 | 2052 | |
a4d47cac EB |
2053 | const int par_len = XVECLEN (span, 0); |
2054 | for (int par_index = 0; par_index < par_len; par_index++) | |
a8e5c0e7 RH |
2055 | { |
2056 | rtx elem = XVECEXP (span, 0, par_index); | |
2057 | queue_reg_save (elem, NULL_RTX, span_offset); | |
2058 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); | |
2059 | } | |
2060 | } | |
647a1567 RH |
2061 | break; |
2062 | ||
2063 | default: | |
2064 | gcc_unreachable (); | |
2065 | } | |
2066 | } | |
2067 | ||
9a08d230 RH |
2068 | /* Record call frame debugging information for INSN, which either sets |
2069 | SP or FP (adjusting how we calculate the frame address) or saves a | |
2070 | register to the stack. */ | |
647a1567 | 2071 | |
7644b3c7 | 2072 | static void |
e8a54173 | 2073 | dwarf2out_frame_debug (rtx_insn *insn) |
647a1567 | 2074 | { |
e8a54173 | 2075 | rtx note, n, pat; |
647a1567 | 2076 | bool handled_one = false; |
647a1567 RH |
2077 | |
2078 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2079 | switch (REG_NOTE_KIND (note)) | |
2080 | { | |
2081 | case REG_FRAME_RELATED_EXPR: | |
e8a54173 | 2082 | pat = XEXP (note, 0); |
647a1567 RH |
2083 | goto do_frame_expr; |
2084 | ||
2085 | case REG_CFA_DEF_CFA: | |
89e25f95 | 2086 | dwarf2out_frame_debug_def_cfa (XEXP (note, 0)); |
647a1567 RH |
2087 | handled_one = true; |
2088 | break; | |
2089 | ||
2090 | case REG_CFA_ADJUST_CFA: | |
2091 | n = XEXP (note, 0); | |
2092 | if (n == NULL) | |
2093 | { | |
2094 | n = PATTERN (insn); | |
2095 | if (GET_CODE (n) == PARALLEL) | |
2096 | n = XVECEXP (n, 0, 0); | |
2097 | } | |
89e25f95 | 2098 | dwarf2out_frame_debug_adjust_cfa (n); |
647a1567 RH |
2099 | handled_one = true; |
2100 | break; | |
2101 | ||
2102 | case REG_CFA_OFFSET: | |
2103 | n = XEXP (note, 0); | |
2104 | if (n == NULL) | |
2105 | n = single_set (insn); | |
89e25f95 | 2106 | dwarf2out_frame_debug_cfa_offset (n); |
647a1567 RH |
2107 | handled_one = true; |
2108 | break; | |
2109 | ||
2110 | case REG_CFA_REGISTER: | |
2111 | n = XEXP (note, 0); | |
2112 | if (n == NULL) | |
2113 | { | |
2114 | n = PATTERN (insn); | |
2115 | if (GET_CODE (n) == PARALLEL) | |
2116 | n = XVECEXP (n, 0, 0); | |
2117 | } | |
89e25f95 | 2118 | dwarf2out_frame_debug_cfa_register (n); |
647a1567 RH |
2119 | handled_one = true; |
2120 | break; | |
2121 | ||
2122 | case REG_CFA_EXPRESSION: | |
ac5b3eff | 2123 | case REG_CFA_VAL_EXPRESSION: |
647a1567 RH |
2124 | n = XEXP (note, 0); |
2125 | if (n == NULL) | |
2126 | n = single_set (insn); | |
ac5b3eff JW |
2127 | |
2128 | if (REG_NOTE_KIND (note) == REG_CFA_EXPRESSION) | |
2129 | dwarf2out_frame_debug_cfa_expression (n); | |
2130 | else | |
2131 | dwarf2out_frame_debug_cfa_val_expression (n); | |
2132 | ||
647a1567 RH |
2133 | handled_one = true; |
2134 | break; | |
2135 | ||
2136 | case REG_CFA_RESTORE: | |
2137 | n = XEXP (note, 0); | |
2138 | if (n == NULL) | |
2139 | { | |
2140 | n = PATTERN (insn); | |
2141 | if (GET_CODE (n) == PARALLEL) | |
2142 | n = XVECEXP (n, 0, 0); | |
2143 | n = XEXP (n, 0); | |
2144 | } | |
89e25f95 | 2145 | dwarf2out_frame_debug_cfa_restore (n); |
647a1567 RH |
2146 | handled_one = true; |
2147 | break; | |
2148 | ||
2149 | case REG_CFA_SET_VDRAP: | |
2150 | n = XEXP (note, 0); | |
2151 | if (REG_P (n)) | |
2152 | { | |
a518b996 | 2153 | dw_fde_ref fde = cfun->fde; |
647a1567 RH |
2154 | if (fde) |
2155 | { | |
2156 | gcc_assert (fde->vdrap_reg == INVALID_REGNUM); | |
2157 | if (REG_P (n)) | |
7263c6d7 | 2158 | fde->vdrap_reg = dwf_regno (n); |
647a1567 RH |
2159 | } |
2160 | } | |
2161 | handled_one = true; | |
2162 | break; | |
2163 | ||
27169e45 | 2164 | case REG_CFA_TOGGLE_RA_MANGLE: |
acdf7336 | 2165 | dwarf2out_frame_debug_cfa_toggle_ra_mangle (); |
dfe1fe91 EB |
2166 | handled_one = true; |
2167 | break; | |
2168 | ||
647a1567 | 2169 | case REG_CFA_WINDOW_SAVE: |
acdf7336 | 2170 | dwarf2out_frame_debug_cfa_window_save (); |
647a1567 RH |
2171 | handled_one = true; |
2172 | break; | |
2173 | ||
2174 | case REG_CFA_FLUSH_QUEUE: | |
67d7405e | 2175 | /* The actual flush happens elsewhere. */ |
647a1567 RH |
2176 | handled_one = true; |
2177 | break; | |
2178 | ||
2179 | default: | |
2180 | break; | |
2181 | } | |
2182 | ||
67d7405e | 2183 | if (!handled_one) |
647a1567 | 2184 | { |
e8a54173 | 2185 | pat = PATTERN (insn); |
647a1567 | 2186 | do_frame_expr: |
e8a54173 | 2187 | dwarf2out_frame_debug_expr (pat); |
647a1567 RH |
2188 | |
2189 | /* Check again. A parallel can save and update the same register. | |
2190 | We could probably check just once, here, but this is safer than | |
2191 | removing the check at the start of the function. */ | |
e8a54173 | 2192 | if (clobbers_queued_reg_save (pat)) |
67d7405e | 2193 | dwarf2out_flush_queued_reg_saves (); |
647a1567 | 2194 | } |
647a1567 RH |
2195 | } |
2196 | ||
57e16c96 RH |
2197 | /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */ |
2198 | ||
2199 | static void | |
ce363ef2 | 2200 | change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row) |
57e16c96 RH |
2201 | { |
2202 | size_t i, n_old, n_new, n_max; | |
2203 | dw_cfi_ref cfi; | |
2204 | ||
2205 | if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi)) | |
2206 | add_cfi (new_row->cfa_cfi); | |
2207 | else | |
2208 | { | |
2209 | cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa); | |
2210 | if (cfi) | |
2211 | add_cfi (cfi); | |
2212 | } | |
2213 | ||
9771b263 DN |
2214 | n_old = vec_safe_length (old_row->reg_save); |
2215 | n_new = vec_safe_length (new_row->reg_save); | |
57e16c96 RH |
2216 | n_max = MAX (n_old, n_new); |
2217 | ||
2218 | for (i = 0; i < n_max; ++i) | |
2219 | { | |
2220 | dw_cfi_ref r_old = NULL, r_new = NULL; | |
2221 | ||
2222 | if (i < n_old) | |
9771b263 | 2223 | r_old = (*old_row->reg_save)[i]; |
57e16c96 | 2224 | if (i < n_new) |
9771b263 | 2225 | r_new = (*new_row->reg_save)[i]; |
57e16c96 RH |
2226 | |
2227 | if (r_old == r_new) | |
2228 | ; | |
2229 | else if (r_new == NULL) | |
2230 | add_cfi_restore (i); | |
2231 | else if (!cfi_equal_p (r_old, r_new)) | |
2232 | add_cfi (r_new); | |
2233 | } | |
dfe1fe91 EB |
2234 | |
2235 | if (!old_row->window_save && new_row->window_save) | |
2236 | { | |
2237 | dw_cfi_ref cfi = new_cfi (); | |
2238 | ||
acdf7336 SN |
2239 | gcc_assert (!old_row->ra_mangled && !new_row->ra_mangled); |
2240 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; | |
2241 | add_cfi (cfi); | |
2242 | } | |
2243 | ||
2244 | if (old_row->ra_mangled != new_row->ra_mangled) | |
2245 | { | |
2246 | dw_cfi_ref cfi = new_cfi (); | |
2247 | ||
2248 | gcc_assert (!old_row->window_save && !new_row->window_save); | |
2249 | /* DW_CFA_GNU_window_save is reused for toggling RA mangle state. */ | |
dfe1fe91 EB |
2250 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; |
2251 | add_cfi (cfi); | |
2252 | } | |
57e16c96 RH |
2253 | } |
2254 | ||
89e25f95 BS |
2255 | /* Examine CFI and return true if a cfi label and set_loc is needed |
2256 | beforehand. Even when generating CFI assembler instructions, we | |
4a8ee122 | 2257 | still have to add the cfi to the list so that lookup_cfa_1 works |
89e25f95 BS |
2258 | later on. When -g2 and above we even need to force emitting of |
2259 | CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list | |
2260 | purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa | |
2261 | and so don't use convert_cfa_to_fb_loc_list. */ | |
2262 | ||
2263 | static bool | |
2264 | cfi_label_required_p (dw_cfi_ref cfi) | |
2265 | { | |
2266 | if (!dwarf2out_do_cfi_asm ()) | |
2267 | return true; | |
2268 | ||
2269 | if (dwarf_version == 2 | |
2270 | && debug_info_level > DINFO_LEVEL_TERSE | |
2271 | && (write_symbols == DWARF2_DEBUG | |
2272 | || write_symbols == VMS_AND_DWARF2_DEBUG)) | |
2273 | { | |
2274 | switch (cfi->dw_cfi_opc) | |
2275 | { | |
2276 | case DW_CFA_def_cfa_offset: | |
2277 | case DW_CFA_def_cfa_offset_sf: | |
2278 | case DW_CFA_def_cfa_register: | |
2279 | case DW_CFA_def_cfa: | |
2280 | case DW_CFA_def_cfa_sf: | |
2281 | case DW_CFA_def_cfa_expression: | |
2282 | case DW_CFA_restore_state: | |
2283 | return true; | |
2284 | default: | |
2285 | return false; | |
2286 | } | |
2287 | } | |
2288 | return false; | |
2289 | } | |
2290 | ||
2291 | /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the | |
2292 | function's FDE, adding CFI labels and set_loc/advance_loc opcodes as | |
2293 | necessary. */ | |
2294 | static void | |
2295 | add_cfis_to_fde (void) | |
2296 | { | |
a518b996 | 2297 | dw_fde_ref fde = cfun->fde; |
f65c531e | 2298 | rtx_insn *insn, *next; |
89e25f95 BS |
2299 | |
2300 | for (insn = get_insns (); insn; insn = next) | |
2301 | { | |
2302 | next = NEXT_INSN (insn); | |
2303 | ||
2304 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
0eeb9f3d | 2305 | fde->dw_fde_switch_cfi_index = vec_safe_length (fde->dw_fde_cfi); |
89e25f95 BS |
2306 | |
2307 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) | |
2308 | { | |
2309 | bool required = cfi_label_required_p (NOTE_CFI (insn)); | |
b84dad8e JJ |
2310 | while (next) |
2311 | if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI) | |
2312 | { | |
2313 | required |= cfi_label_required_p (NOTE_CFI (next)); | |
2314 | next = NEXT_INSN (next); | |
2315 | } | |
2316 | else if (active_insn_p (next) | |
2317 | || (NOTE_P (next) && (NOTE_KIND (next) | |
2318 | == NOTE_INSN_SWITCH_TEXT_SECTIONS))) | |
2319 | break; | |
2320 | else | |
89e25f95 | 2321 | next = NEXT_INSN (next); |
89e25f95 BS |
2322 | if (required) |
2323 | { | |
2324 | int num = dwarf2out_cfi_label_num; | |
2325 | const char *label = dwarf2out_cfi_label (); | |
2326 | dw_cfi_ref xcfi; | |
89e25f95 BS |
2327 | |
2328 | /* Set the location counter to the new label. */ | |
2329 | xcfi = new_cfi (); | |
0eeb9f3d | 2330 | xcfi->dw_cfi_opc = DW_CFA_advance_loc4; |
89e25f95 | 2331 | xcfi->dw_cfi_oprnd1.dw_cfi_addr = label; |
9771b263 | 2332 | vec_safe_push (fde->dw_fde_cfi, xcfi); |
89e25f95 | 2333 | |
e67d1102 | 2334 | rtx_note *tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn); |
89e25f95 BS |
2335 | NOTE_LABEL_NUMBER (tmp) = num; |
2336 | } | |
2337 | ||
2338 | do | |
2339 | { | |
b84dad8e | 2340 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) |
9771b263 | 2341 | vec_safe_push (fde->dw_fde_cfi, NOTE_CFI (insn)); |
89e25f95 BS |
2342 | insn = NEXT_INSN (insn); |
2343 | } | |
2344 | while (insn != next); | |
89e25f95 BS |
2345 | } |
2346 | } | |
2347 | } | |
2348 | ||
a1566696 SB |
2349 | static void dump_cfi_row (FILE *f, dw_cfi_row *row); |
2350 | ||
829bdd4b RH |
2351 | /* If LABEL is the start of a trace, then initialize the state of that |
2352 | trace from CUR_TRACE and CUR_ROW. */ | |
43215a89 | 2353 | |
7644b3c7 | 2354 | static void |
7583d99a | 2355 | maybe_record_trace_start (rtx_insn *start, rtx_insn *origin) |
89e25f95 | 2356 | { |
829bdd4b | 2357 | dw_trace_info *ti; |
829bdd4b RH |
2358 | |
2359 | ti = get_trace_info (start); | |
2360 | gcc_assert (ti != NULL); | |
647a1567 | 2361 | |
829bdd4b | 2362 | if (dump_file) |
647a1567 | 2363 | { |
829bdd4b | 2364 | fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n", |
200e10dc | 2365 | cur_trace->id, ti->id, |
829bdd4b RH |
2366 | (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"), |
2367 | (origin ? INSN_UID (origin) : 0)); | |
2368 | } | |
bc5612ed | 2369 | |
68184180 | 2370 | poly_int64 args_size = cur_trace->end_true_args_size; |
829bdd4b RH |
2371 | if (ti->beg_row == NULL) |
2372 | { | |
2373 | /* This is the first time we've encountered this trace. Propagate | |
2374 | state across the edge and push the trace onto the work list. */ | |
2375 | ti->beg_row = copy_cfi_row (cur_row); | |
9a08d230 | 2376 | ti->beg_true_args_size = args_size; |
2f23f97a | 2377 | |
829bdd4b RH |
2378 | ti->cfa_store = cur_trace->cfa_store; |
2379 | ti->cfa_temp = cur_trace->cfa_temp; | |
9771b263 | 2380 | ti->regs_saved_in_regs = cur_trace->regs_saved_in_regs.copy (); |
829bdd4b | 2381 | |
9771b263 | 2382 | trace_work_list.safe_push (ti); |
829bdd4b RH |
2383 | |
2384 | if (dump_file) | |
200e10dc | 2385 | fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id); |
829bdd4b RH |
2386 | } |
2387 | else | |
2388 | { | |
9a08d230 | 2389 | |
829bdd4b RH |
2390 | /* We ought to have the same state incoming to a given trace no |
2391 | matter how we arrive at the trace. Anything else means we've | |
2392 | got some kind of optimization error. */ | |
a1566696 SB |
2393 | #if CHECKING_P |
2394 | if (!cfi_row_equal_p (cur_row, ti->beg_row)) | |
2395 | { | |
2396 | if (dump_file) | |
2397 | { | |
2398 | fprintf (dump_file, "Inconsistent CFI state!\n"); | |
2399 | fprintf (dump_file, "SHOULD have:\n"); | |
2400 | dump_cfi_row (dump_file, ti->beg_row); | |
2401 | fprintf (dump_file, "DO have:\n"); | |
2402 | dump_cfi_row (dump_file, cur_row); | |
2403 | } | |
2404 | ||
2405 | gcc_unreachable (); | |
2406 | } | |
2407 | #endif | |
9a08d230 RH |
2408 | |
2409 | /* The args_size is allowed to conflict if it isn't actually used. */ | |
68184180 | 2410 | if (maybe_ne (ti->beg_true_args_size, args_size)) |
9a08d230 RH |
2411 | ti->args_size_undefined = true; |
2412 | } | |
2413 | } | |
2414 | ||
2415 | /* Similarly, but handle the args_size and CFA reset across EH | |
2416 | and non-local goto edges. */ | |
2417 | ||
2418 | static void | |
7583d99a | 2419 | maybe_record_trace_start_abnormal (rtx_insn *start, rtx_insn *origin) |
9a08d230 | 2420 | { |
68184180 | 2421 | poly_int64 save_args_size, delta; |
9a08d230 RH |
2422 | dw_cfa_location save_cfa; |
2423 | ||
2424 | save_args_size = cur_trace->end_true_args_size; | |
68184180 | 2425 | if (known_eq (save_args_size, 0)) |
9a08d230 RH |
2426 | { |
2427 | maybe_record_trace_start (start, origin); | |
2428 | return; | |
2429 | } | |
2430 | ||
2431 | delta = -save_args_size; | |
2432 | cur_trace->end_true_args_size = 0; | |
2433 | ||
2434 | save_cfa = cur_row->cfa; | |
2435 | if (cur_row->cfa.reg == dw_stack_pointer_regnum) | |
2436 | { | |
2437 | /* Convert a change in args_size (always a positive in the | |
2438 | direction of stack growth) to a change in stack pointer. */ | |
581edfa3 TS |
2439 | if (!STACK_GROWS_DOWNWARD) |
2440 | delta = -delta; | |
2441 | ||
9a08d230 | 2442 | cur_row->cfa.offset += delta; |
829bdd4b | 2443 | } |
9a08d230 RH |
2444 | |
2445 | maybe_record_trace_start (start, origin); | |
2446 | ||
2447 | cur_trace->end_true_args_size = save_args_size; | |
2448 | cur_row->cfa = save_cfa; | |
829bdd4b | 2449 | } |
45fba6d1 | 2450 | |
829bdd4b RH |
2451 | /* Propagate CUR_TRACE state to the destinations implied by INSN. */ |
2452 | /* ??? Sadly, this is in large part a duplicate of make_edges. */ | |
2453 | ||
2454 | static void | |
7583d99a | 2455 | create_trace_edges (rtx_insn *insn) |
829bdd4b | 2456 | { |
ca486330 | 2457 | rtx tmp; |
829bdd4b RH |
2458 | int i, n; |
2459 | ||
2460 | if (JUMP_P (insn)) | |
2461 | { | |
8942ee0f DM |
2462 | rtx_jump_table_data *table; |
2463 | ||
829bdd4b | 2464 | if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) |
9a08d230 RH |
2465 | return; |
2466 | ||
8942ee0f | 2467 | if (tablejump_p (insn, NULL, &table)) |
bc5612ed | 2468 | { |
95c43227 | 2469 | rtvec vec = table->get_labels (); |
829bdd4b RH |
2470 | |
2471 | n = GET_NUM_ELEM (vec); | |
2472 | for (i = 0; i < n; ++i) | |
2473 | { | |
7583d99a | 2474 | rtx_insn *lab = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, i), 0)); |
9a08d230 | 2475 | maybe_record_trace_start (lab, insn); |
829bdd4b | 2476 | } |
3010ee55 OH |
2477 | |
2478 | /* Handle casesi dispatch insns. */ | |
2479 | if ((tmp = tablejump_casesi_pattern (insn)) != NULL_RTX) | |
2480 | { | |
2481 | rtx_insn * lab = label_ref_label (XEXP (SET_SRC (tmp), 2)); | |
2482 | maybe_record_trace_start (lab, insn); | |
2483 | } | |
829bdd4b RH |
2484 | } |
2485 | else if (computed_jump_p (insn)) | |
bc5612ed | 2486 | { |
6f7eba34 TS |
2487 | rtx_insn *temp; |
2488 | unsigned int i; | |
2489 | FOR_EACH_VEC_SAFE_ELT (forced_labels, i, temp) | |
2490 | maybe_record_trace_start (temp, insn); | |
829bdd4b RH |
2491 | } |
2492 | else if (returnjump_p (insn)) | |
2493 | ; | |
2494 | else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL) | |
2495 | { | |
2496 | n = ASM_OPERANDS_LABEL_LENGTH (tmp); | |
2497 | for (i = 0; i < n; ++i) | |
bc5612ed | 2498 | { |
7583d99a DM |
2499 | rtx_insn *lab = |
2500 | as_a <rtx_insn *> (XEXP (ASM_OPERANDS_LABEL (tmp, i), 0)); | |
9a08d230 | 2501 | maybe_record_trace_start (lab, insn); |
829bdd4b RH |
2502 | } |
2503 | } | |
2504 | else | |
2505 | { | |
7583d99a | 2506 | rtx_insn *lab = JUMP_LABEL_AS_INSN (insn); |
829bdd4b | 2507 | gcc_assert (lab != NULL); |
9a08d230 | 2508 | maybe_record_trace_start (lab, insn); |
829bdd4b RH |
2509 | } |
2510 | } | |
2511 | else if (CALL_P (insn)) | |
2512 | { | |
2513 | /* Sibling calls don't have edges inside this function. */ | |
2514 | if (SIBLING_CALL_P (insn)) | |
2515 | return; | |
965b2557 | 2516 | |
829bdd4b RH |
2517 | /* Process non-local goto edges. */ |
2518 | if (can_nonlocal_goto (insn)) | |
b5241a5a | 2519 | for (rtx_insn_list *lab = nonlocal_goto_handler_labels; |
2382940b DM |
2520 | lab; |
2521 | lab = lab->next ()) | |
b5241a5a | 2522 | maybe_record_trace_start_abnormal (lab->insn (), insn); |
829bdd4b | 2523 | } |
292d1dfb | 2524 | else if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) |
3382318a | 2525 | { |
292d1dfb | 2526 | int i, n = seq->len (); |
3382318a | 2527 | for (i = 0; i < n; ++i) |
292d1dfb | 2528 | create_trace_edges (seq->insn (i)); |
3382318a RH |
2529 | return; |
2530 | } | |
965b2557 | 2531 | |
829bdd4b RH |
2532 | /* Process EH edges. */ |
2533 | if (CALL_P (insn) || cfun->can_throw_non_call_exceptions) | |
2534 | { | |
2535 | eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn); | |
2536 | if (lp) | |
9a08d230 | 2537 | maybe_record_trace_start_abnormal (lp->landing_pad, insn); |
829bdd4b RH |
2538 | } |
2539 | } | |
57e16c96 | 2540 | |
eebc8f37 RH |
2541 | /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */ |
2542 | ||
2543 | static void | |
e8a54173 | 2544 | scan_insn_after (rtx_insn *insn) |
eebc8f37 RH |
2545 | { |
2546 | if (RTX_FRAME_RELATED_P (insn)) | |
2547 | dwarf2out_frame_debug (insn); | |
2548 | notice_args_size (insn); | |
2549 | } | |
2550 | ||
829bdd4b RH |
2551 | /* Scan the trace beginning at INSN and create the CFI notes for the |
2552 | instructions therein. */ | |
2553 | ||
2554 | static void | |
26fc730d | 2555 | scan_trace (dw_trace_info *trace, bool entry) |
829bdd4b | 2556 | { |
7583d99a | 2557 | rtx_insn *prev, *insn = trace->head; |
9a08d230 | 2558 | dw_cfa_location this_cfa; |
829bdd4b RH |
2559 | |
2560 | if (dump_file) | |
2561 | fprintf (dump_file, "Processing trace %u : start at %s %d\n", | |
200e10dc | 2562 | trace->id, rtx_name[(int) GET_CODE (insn)], |
829bdd4b RH |
2563 | INSN_UID (insn)); |
2564 | ||
2565 | trace->end_row = copy_cfi_row (trace->beg_row); | |
9a08d230 | 2566 | trace->end_true_args_size = trace->beg_true_args_size; |
829bdd4b RH |
2567 | |
2568 | cur_trace = trace; | |
2569 | cur_row = trace->end_row; | |
9a08d230 RH |
2570 | |
2571 | this_cfa = cur_row->cfa; | |
2572 | cur_cfa = &this_cfa; | |
829bdd4b | 2573 | |
26fc730d JJ |
2574 | /* If the current function starts with a non-standard incoming frame |
2575 | sp offset, emit a note before the first instruction. */ | |
2576 | if (entry | |
2577 | && DEFAULT_INCOMING_FRAME_SP_OFFSET != INCOMING_FRAME_SP_OFFSET) | |
2578 | { | |
2579 | add_cfi_insn = insn; | |
2580 | gcc_assert (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED); | |
2581 | this_cfa.offset = INCOMING_FRAME_SP_OFFSET; | |
2582 | def_cfa_1 (&this_cfa); | |
2583 | } | |
2584 | ||
eebc8f37 RH |
2585 | for (prev = insn, insn = NEXT_INSN (insn); |
2586 | insn; | |
2587 | prev = insn, insn = NEXT_INSN (insn)) | |
829bdd4b | 2588 | { |
7583d99a | 2589 | rtx_insn *control; |
eebc8f37 | 2590 | |
9a08d230 | 2591 | /* Do everything that happens "before" the insn. */ |
eebc8f37 | 2592 | add_cfi_insn = prev; |
829bdd4b RH |
2593 | |
2594 | /* Notice the end of a trace. */ | |
9a08d230 RH |
2595 | if (BARRIER_P (insn)) |
2596 | { | |
2597 | /* Don't bother saving the unneeded queued registers at all. */ | |
9771b263 | 2598 | queued_reg_saves.truncate (0); |
9a08d230 RH |
2599 | break; |
2600 | } | |
2601 | if (save_point_p (insn)) | |
829bdd4b | 2602 | { |
829bdd4b | 2603 | /* Propagate across fallthru edges. */ |
9a08d230 RH |
2604 | dwarf2out_flush_queued_reg_saves (); |
2605 | maybe_record_trace_start (insn, NULL); | |
829bdd4b | 2606 | break; |
bc5612ed BS |
2607 | } |
2608 | ||
829bdd4b | 2609 | if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn)) |
bc5612ed BS |
2610 | continue; |
2611 | ||
eebc8f37 RH |
2612 | /* Handle all changes to the row state. Sequences require special |
2613 | handling for the positioning of the notes. */ | |
292d1dfb | 2614 | if (rtx_sequence *pat = dyn_cast <rtx_sequence *> (PATTERN (insn))) |
bc5612ed | 2615 | { |
e8a54173 | 2616 | rtx_insn *elt; |
292d1dfb | 2617 | int i, n = pat->len (); |
9a08d230 | 2618 | |
7583d99a | 2619 | control = pat->insn (0); |
eebc8f37 RH |
2620 | if (can_throw_internal (control)) |
2621 | notice_eh_throw (control); | |
2622 | dwarf2out_flush_queued_reg_saves (); | |
2623 | ||
8f06d483 | 2624 | if (JUMP_P (control) && INSN_ANNULLED_BRANCH_P (control)) |
829bdd4b | 2625 | { |
9a08d230 RH |
2626 | /* ??? Hopefully multiple delay slots are not annulled. */ |
2627 | gcc_assert (n == 2); | |
eebc8f37 RH |
2628 | gcc_assert (!RTX_FRAME_RELATED_P (control)); |
2629 | gcc_assert (!find_reg_note (control, REG_ARGS_SIZE, NULL)); | |
2630 | ||
e8a54173 | 2631 | elt = pat->insn (1); |
9a08d230 | 2632 | |
9a08d230 RH |
2633 | if (INSN_FROM_TARGET_P (elt)) |
2634 | { | |
5d1f1cd5 | 2635 | cfi_vec save_row_reg_save; |
829bdd4b | 2636 | |
bf27c43e RH |
2637 | /* If ELT is an instruction from target of an annulled |
2638 | branch, the effects are for the target only and so | |
2639 | the args_size and CFA along the current path | |
2640 | shouldn't change. */ | |
eebc8f37 | 2641 | add_cfi_insn = NULL; |
68184180 | 2642 | poly_int64 restore_args_size = cur_trace->end_true_args_size; |
9a08d230 | 2643 | cur_cfa = &cur_row->cfa; |
9771b263 | 2644 | save_row_reg_save = vec_safe_copy (cur_row->reg_save); |
bc5612ed | 2645 | |
eebc8f37 RH |
2646 | scan_insn_after (elt); |
2647 | ||
2648 | /* ??? Should we instead save the entire row state? */ | |
9771b263 | 2649 | gcc_assert (!queued_reg_saves.length ()); |
eebc8f37 RH |
2650 | |
2651 | create_trace_edges (control); | |
bc5612ed | 2652 | |
9a08d230 RH |
2653 | cur_trace->end_true_args_size = restore_args_size; |
2654 | cur_row->cfa = this_cfa; | |
5d1f1cd5 | 2655 | cur_row->reg_save = save_row_reg_save; |
9a08d230 | 2656 | cur_cfa = &this_cfa; |
9a08d230 | 2657 | } |
bf27c43e RH |
2658 | else |
2659 | { | |
2660 | /* If ELT is a annulled branch-taken instruction (i.e. | |
2661 | executed only when branch is not taken), the args_size | |
2662 | and CFA should not change through the jump. */ | |
2663 | create_trace_edges (control); | |
2664 | ||
2665 | /* Update and continue with the trace. */ | |
2666 | add_cfi_insn = insn; | |
2667 | scan_insn_after (elt); | |
2668 | def_cfa_1 (&this_cfa); | |
2669 | } | |
2670 | continue; | |
9a08d230 RH |
2671 | } |
2672 | ||
eebc8f37 RH |
2673 | /* The insns in the delay slot should all be considered to happen |
2674 | "before" a call insn. Consider a call with a stack pointer | |
2675 | adjustment in the delay slot. The backtrace from the callee | |
2676 | should include the sp adjustment. Unfortunately, that leaves | |
2677 | us with an unavoidable unwinding error exactly at the call insn | |
2678 | itself. For jump insns we'd prefer to avoid this error by | |
2679 | placing the notes after the sequence. */ | |
2680 | if (JUMP_P (control)) | |
2681 | add_cfi_insn = insn; | |
2682 | ||
9a08d230 RH |
2683 | for (i = 1; i < n; ++i) |
2684 | { | |
e8a54173 | 2685 | elt = pat->insn (i); |
eebc8f37 | 2686 | scan_insn_after (elt); |
9a08d230 | 2687 | } |
eebc8f37 RH |
2688 | |
2689 | /* Make sure any register saves are visible at the jump target. */ | |
2690 | dwarf2out_flush_queued_reg_saves (); | |
67d7405e | 2691 | any_cfis_emitted = false; |
eebc8f37 RH |
2692 | |
2693 | /* However, if there is some adjustment on the call itself, e.g. | |
2694 | a call_pop, that action should be considered to happen after | |
2695 | the call returns. */ | |
2696 | add_cfi_insn = insn; | |
2697 | scan_insn_after (control); | |
829bdd4b | 2698 | } |
9a08d230 | 2699 | else |
eebc8f37 RH |
2700 | { |
2701 | /* Flush data before calls and jumps, and of course if necessary. */ | |
2702 | if (can_throw_internal (insn)) | |
2703 | { | |
2704 | notice_eh_throw (insn); | |
2705 | dwarf2out_flush_queued_reg_saves (); | |
2706 | } | |
2707 | else if (!NONJUMP_INSN_P (insn) | |
2708 | || clobbers_queued_reg_save (insn) | |
2709 | || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) | |
2710 | dwarf2out_flush_queued_reg_saves (); | |
67d7405e | 2711 | any_cfis_emitted = false; |
eebc8f37 RH |
2712 | |
2713 | add_cfi_insn = insn; | |
2714 | scan_insn_after (insn); | |
2715 | control = insn; | |
2716 | } | |
9a08d230 RH |
2717 | |
2718 | /* Between frame-related-p and args_size we might have otherwise | |
2719 | emitted two cfa adjustments. Do it now. */ | |
2720 | def_cfa_1 (&this_cfa); | |
45fba6d1 | 2721 | |
67d7405e RH |
2722 | /* Minimize the number of advances by emitting the entire queue |
2723 | once anything is emitted. */ | |
2724 | if (any_cfis_emitted | |
2725 | || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) | |
2726 | dwarf2out_flush_queued_reg_saves (); | |
2727 | ||
829bdd4b RH |
2728 | /* Note that a test for control_flow_insn_p does exactly the |
2729 | same tests as are done to actually create the edges. So | |
2730 | always call the routine and let it not create edges for | |
2731 | non-control-flow insns. */ | |
eebc8f37 | 2732 | create_trace_edges (control); |
647a1567 | 2733 | } |
45fba6d1 | 2734 | |
141618e2 | 2735 | add_cfi_insn = NULL; |
829bdd4b RH |
2736 | cur_row = NULL; |
2737 | cur_trace = NULL; | |
9a08d230 | 2738 | cur_cfa = NULL; |
647a1567 RH |
2739 | } |
2740 | ||
829bdd4b | 2741 | /* Scan the function and create the initial set of CFI notes. */ |
647a1567 | 2742 | |
bc5612ed | 2743 | static void |
829bdd4b | 2744 | create_cfi_notes (void) |
647a1567 | 2745 | { |
829bdd4b | 2746 | dw_trace_info *ti; |
647a1567 | 2747 | |
9771b263 DN |
2748 | gcc_checking_assert (!queued_reg_saves.exists ()); |
2749 | gcc_checking_assert (!trace_work_list.exists ()); | |
647a1567 | 2750 | |
829bdd4b | 2751 | /* Always begin at the entry trace. */ |
9771b263 | 2752 | ti = &trace_info[0]; |
26fc730d | 2753 | scan_trace (ti, true); |
647a1567 | 2754 | |
9771b263 | 2755 | while (!trace_work_list.is_empty ()) |
829bdd4b | 2756 | { |
9771b263 | 2757 | ti = trace_work_list.pop (); |
26fc730d | 2758 | scan_trace (ti, false); |
647a1567 RH |
2759 | } |
2760 | ||
9771b263 DN |
2761 | queued_reg_saves.release (); |
2762 | trace_work_list.release (); | |
829bdd4b | 2763 | } |
647a1567 | 2764 | |
200e10dc RH |
2765 | /* Return the insn before the first NOTE_INSN_CFI after START. */ |
2766 | ||
dc01c3d1 DM |
2767 | static rtx_insn * |
2768 | before_next_cfi_note (rtx_insn *start) | |
200e10dc | 2769 | { |
dc01c3d1 | 2770 | rtx_insn *prev = start; |
200e10dc RH |
2771 | while (start) |
2772 | { | |
2773 | if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI) | |
2774 | return prev; | |
2775 | prev = start; | |
2776 | start = NEXT_INSN (start); | |
2777 | } | |
2778 | gcc_unreachable (); | |
2779 | } | |
2780 | ||
829bdd4b | 2781 | /* Insert CFI notes between traces to properly change state between them. */ |
647a1567 | 2782 | |
829bdd4b RH |
2783 | static void |
2784 | connect_traces (void) | |
2785 | { | |
b94c2dc1 | 2786 | unsigned i, n; |
829bdd4b RH |
2787 | dw_trace_info *prev_ti, *ti; |
2788 | ||
200e10dc RH |
2789 | /* ??? Ideally, we should have both queued and processed every trace. |
2790 | However the current representation of constant pools on various targets | |
2791 | is indistinguishable from unreachable code. Assume for the moment that | |
2792 | we can simply skip over such traces. */ | |
2793 | /* ??? Consider creating a DATA_INSN rtx code to indicate that | |
2794 | these are not "real" instructions, and should not be considered. | |
2795 | This could be generically useful for tablejump data as well. */ | |
2796 | /* Remove all unprocessed traces from the list. */ | |
b94c2dc1 TV |
2797 | unsigned ix, ix2; |
2798 | VEC_ORDERED_REMOVE_IF_FROM_TO (trace_info, ix, ix2, ti, 1, | |
2799 | trace_info.length (), ti->beg_row == NULL); | |
2800 | FOR_EACH_VEC_ELT (trace_info, ix, ti) | |
2801 | gcc_assert (ti->end_row != NULL); | |
829bdd4b | 2802 | |
200e10dc RH |
2803 | /* Work from the end back to the beginning. This lets us easily insert |
2804 | remember/restore_state notes in the correct order wrt other notes. */ | |
b94c2dc1 | 2805 | n = trace_info.length (); |
9771b263 | 2806 | prev_ti = &trace_info[n - 1]; |
200e10dc | 2807 | for (i = n - 1; i > 0; --i) |
647a1567 | 2808 | { |
829bdd4b | 2809 | dw_cfi_row *old_row; |
647a1567 | 2810 | |
200e10dc | 2811 | ti = prev_ti; |
9771b263 | 2812 | prev_ti = &trace_info[i - 1]; |
647a1567 | 2813 | |
200e10dc | 2814 | add_cfi_insn = ti->head; |
829bdd4b RH |
2815 | |
2816 | /* In dwarf2out_switch_text_section, we'll begin a new FDE | |
2817 | for the portion of the function in the alternate text | |
2818 | section. The row state at the very beginning of that | |
2819 | new FDE will be exactly the row state from the CIE. */ | |
2820 | if (ti->switch_sections) | |
2821 | old_row = cie_cfi_row; | |
2822 | else | |
200e10dc RH |
2823 | { |
2824 | old_row = prev_ti->end_row; | |
2825 | /* If there's no change from the previous end state, fine. */ | |
2826 | if (cfi_row_equal_p (old_row, ti->beg_row)) | |
2827 | ; | |
2828 | /* Otherwise check for the common case of sharing state with | |
2829 | the beginning of an epilogue, but not the end. Insert | |
2830 | remember/restore opcodes in that case. */ | |
2831 | else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row)) | |
2832 | { | |
2833 | dw_cfi_ref cfi; | |
2834 | ||
2835 | /* Note that if we blindly insert the remember at the | |
2836 | start of the trace, we can wind up increasing the | |
2837 | size of the unwind info due to extra advance opcodes. | |
2838 | Instead, put the remember immediately before the next | |
2839 | state change. We know there must be one, because the | |
2840 | state at the beginning and head of the trace differ. */ | |
2841 | add_cfi_insn = before_next_cfi_note (prev_ti->head); | |
2842 | cfi = new_cfi (); | |
2843 | cfi->dw_cfi_opc = DW_CFA_remember_state; | |
2844 | add_cfi (cfi); | |
2845 | ||
2846 | add_cfi_insn = ti->head; | |
2847 | cfi = new_cfi (); | |
2848 | cfi->dw_cfi_opc = DW_CFA_restore_state; | |
2849 | add_cfi (cfi); | |
2850 | ||
2851 | old_row = prev_ti->beg_row; | |
2852 | } | |
2853 | /* Otherwise, we'll simply change state from the previous end. */ | |
2854 | } | |
829bdd4b | 2855 | |
829bdd4b RH |
2856 | change_cfi_row (old_row, ti->beg_row); |
2857 | ||
2858 | if (dump_file && add_cfi_insn != ti->head) | |
2859 | { | |
dc01c3d1 | 2860 | rtx_insn *note; |
829bdd4b | 2861 | |
200e10dc RH |
2862 | fprintf (dump_file, "Fixup between trace %u and %u:\n", |
2863 | prev_ti->id, ti->id); | |
829bdd4b RH |
2864 | |
2865 | note = ti->head; | |
2866 | do | |
2867 | { | |
2868 | note = NEXT_INSN (note); | |
2869 | gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI); | |
2870 | output_cfi_directive (dump_file, NOTE_CFI (note)); | |
2871 | } | |
2872 | while (note != add_cfi_insn); | |
2873 | } | |
2874 | } | |
9a08d230 RH |
2875 | |
2876 | /* Connect args_size between traces that have can_throw_internal insns. */ | |
9771b263 | 2877 | if (cfun->eh->lp_array) |
9a08d230 | 2878 | { |
68184180 | 2879 | poly_int64 prev_args_size = 0; |
9a08d230 RH |
2880 | |
2881 | for (i = 0; i < n; ++i) | |
2882 | { | |
9771b263 | 2883 | ti = &trace_info[i]; |
9a08d230 RH |
2884 | |
2885 | if (ti->switch_sections) | |
2886 | prev_args_size = 0; | |
464b6c11 | 2887 | |
9a08d230 RH |
2888 | if (ti->eh_head == NULL) |
2889 | continue; | |
9a08d230 | 2890 | |
464b6c11 EB |
2891 | /* We require either the incoming args_size values to match or the |
2892 | presence of an insn setting it before the first EH insn. */ | |
2893 | gcc_assert (!ti->args_size_undefined || ti->args_size_defined_for_eh); | |
2894 | ||
2895 | /* In the latter case, we force the creation of a CFI note. */ | |
2896 | if (ti->args_size_undefined | |
2897 | || maybe_ne (ti->beg_delay_args_size, prev_args_size)) | |
9a08d230 RH |
2898 | { |
2899 | /* ??? Search back to previous CFI note. */ | |
2900 | add_cfi_insn = PREV_INSN (ti->eh_head); | |
2901 | add_cfi_args_size (ti->beg_delay_args_size); | |
2902 | } | |
2903 | ||
2904 | prev_args_size = ti->end_delay_args_size; | |
2905 | } | |
2906 | } | |
647a1567 RH |
2907 | } |
2908 | ||
829bdd4b RH |
2909 | /* Set up the pseudo-cfg of instruction traces, as described at the |
2910 | block comment at the top of the file. */ | |
647a1567 | 2911 | |
bc5612ed | 2912 | static void |
829bdd4b | 2913 | create_pseudo_cfg (void) |
647a1567 | 2914 | { |
829bdd4b | 2915 | bool saw_barrier, switch_sections; |
f32682ca | 2916 | dw_trace_info ti; |
f65c531e | 2917 | rtx_insn *insn; |
829bdd4b RH |
2918 | unsigned i; |
2919 | ||
2920 | /* The first trace begins at the start of the function, | |
2921 | and begins with the CIE row state. */ | |
9771b263 | 2922 | trace_info.create (16); |
f32682ca DN |
2923 | memset (&ti, 0, sizeof (ti)); |
2924 | ti.head = get_insns (); | |
2925 | ti.beg_row = cie_cfi_row; | |
2926 | ti.cfa_store = cie_cfi_row->cfa; | |
2927 | ti.cfa_temp.reg = INVALID_REGNUM; | |
9771b263 | 2928 | trace_info.quick_push (ti); |
829bdd4b | 2929 | |
829bdd4b | 2930 | if (cie_return_save) |
9771b263 | 2931 | ti.regs_saved_in_regs.safe_push (*cie_return_save); |
647a1567 | 2932 | |
829bdd4b RH |
2933 | /* Walk all the insns, collecting start of trace locations. */ |
2934 | saw_barrier = false; | |
2935 | switch_sections = false; | |
2936 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2937 | { | |
2938 | if (BARRIER_P (insn)) | |
2939 | saw_barrier = true; | |
2940 | else if (NOTE_P (insn) | |
2941 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
2942 | { | |
2943 | /* We should have just seen a barrier. */ | |
2944 | gcc_assert (saw_barrier); | |
2945 | switch_sections = true; | |
2946 | } | |
2947 | /* Watch out for save_point notes between basic blocks. | |
2948 | In particular, a note after a barrier. Do not record these, | |
2949 | delaying trace creation until the label. */ | |
2950 | else if (save_point_p (insn) | |
2951 | && (LABEL_P (insn) || !saw_barrier)) | |
2952 | { | |
f32682ca DN |
2953 | memset (&ti, 0, sizeof (ti)); |
2954 | ti.head = insn; | |
2955 | ti.switch_sections = switch_sections; | |
f8ed2fc2 | 2956 | ti.id = trace_info.length (); |
9771b263 | 2957 | trace_info.safe_push (ti); |
829bdd4b RH |
2958 | |
2959 | saw_barrier = false; | |
2960 | switch_sections = false; | |
2961 | } | |
2962 | } | |
2963 | ||
2964 | /* Create the trace index after we've finished building trace_info, | |
2965 | avoiding stale pointer problems due to reallocation. */ | |
c203e8a7 TS |
2966 | trace_index |
2967 | = new hash_table<trace_info_hasher> (trace_info.length ()); | |
f32682ca | 2968 | dw_trace_info *tp; |
9771b263 | 2969 | FOR_EACH_VEC_ELT (trace_info, i, tp) |
829bdd4b | 2970 | { |
4a8fb1a1 | 2971 | dw_trace_info **slot; |
647a1567 | 2972 | |
829bdd4b | 2973 | if (dump_file) |
f8ed2fc2 | 2974 | fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", tp->id, |
f32682ca DN |
2975 | rtx_name[(int) GET_CODE (tp->head)], INSN_UID (tp->head), |
2976 | tp->switch_sections ? " (section switch)" : ""); | |
829bdd4b | 2977 | |
c203e8a7 | 2978 | slot = trace_index->find_slot_with_hash (tp, INSN_UID (tp->head), INSERT); |
829bdd4b | 2979 | gcc_assert (*slot == NULL); |
4a8fb1a1 | 2980 | *slot = tp; |
829bdd4b | 2981 | } |
647a1567 | 2982 | } |
829bdd4b | 2983 | |
a8e5c0e7 RH |
2984 | /* Record the initial position of the return address. RTL is |
2985 | INCOMING_RETURN_ADDR_RTX. */ | |
2986 | ||
2987 | static void | |
2988 | initial_return_save (rtx rtl) | |
2989 | { | |
2990 | unsigned int reg = INVALID_REGNUM; | |
21810de4 | 2991 | poly_int64 offset = 0; |
a8e5c0e7 RH |
2992 | |
2993 | switch (GET_CODE (rtl)) | |
2994 | { | |
2995 | case REG: | |
2996 | /* RA is in a register. */ | |
7263c6d7 | 2997 | reg = dwf_regno (rtl); |
a8e5c0e7 RH |
2998 | break; |
2999 | ||
3000 | case MEM: | |
3001 | /* RA is on the stack. */ | |
3002 | rtl = XEXP (rtl, 0); | |
3003 | switch (GET_CODE (rtl)) | |
3004 | { | |
3005 | case REG: | |
3006 | gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM); | |
3007 | offset = 0; | |
3008 | break; | |
3009 | ||
3010 | case PLUS: | |
3011 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
21810de4 | 3012 | offset = rtx_to_poly_int64 (XEXP (rtl, 1)); |
a8e5c0e7 RH |
3013 | break; |
3014 | ||
3015 | case MINUS: | |
3016 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
21810de4 | 3017 | offset = -rtx_to_poly_int64 (XEXP (rtl, 1)); |
a8e5c0e7 RH |
3018 | break; |
3019 | ||
3020 | default: | |
3021 | gcc_unreachable (); | |
3022 | } | |
3023 | ||
3024 | break; | |
3025 | ||
3026 | case PLUS: | |
3027 | /* The return address is at some offset from any value we can | |
3028 | actually load. For instance, on the SPARC it is in %i7+8. Just | |
3029 | ignore the offset for now; it doesn't matter for unwinding frames. */ | |
3030 | gcc_assert (CONST_INT_P (XEXP (rtl, 1))); | |
3031 | initial_return_save (XEXP (rtl, 0)); | |
3032 | return; | |
3033 | ||
3034 | default: | |
3035 | gcc_unreachable (); | |
3036 | } | |
3037 | ||
3038 | if (reg != DWARF_FRAME_RETURN_COLUMN) | |
3039 | { | |
3040 | if (reg != INVALID_REGNUM) | |
3041 | record_reg_saved_in_reg (rtl, pc_rtx); | |
f17d3401 | 3042 | reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset); |
a8e5c0e7 RH |
3043 | } |
3044 | } | |
647a1567 | 3045 | |
43215a89 RH |
3046 | static void |
3047 | create_cie_data (void) | |
3048 | { | |
3049 | dw_cfa_location loc; | |
3050 | dw_trace_info cie_trace; | |
3051 | ||
3052 | dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); | |
43215a89 | 3053 | |
c3284718 | 3054 | memset (&cie_trace, 0, sizeof (cie_trace)); |
43215a89 RH |
3055 | cur_trace = &cie_trace; |
3056 | ||
3057 | add_cfi_vec = &cie_cfi_vec; | |
3058 | cie_cfi_row = cur_row = new_cfi_row (); | |
3059 | ||
3060 | /* On entry, the Canonical Frame Address is at SP. */ | |
c3284718 | 3061 | memset (&loc, 0, sizeof (loc)); |
43215a89 | 3062 | loc.reg = dw_stack_pointer_regnum; |
26fc730d JJ |
3063 | /* create_cie_data is called just once per TU, and when using .cfi_startproc |
3064 | is even done by the assembler rather than the compiler. If the target | |
3065 | has different incoming frame sp offsets depending on what kind of | |
3066 | function it is, use a single constant offset for the target and | |
3067 | if needed, adjust before the first instruction in insn stream. */ | |
3068 | loc.offset = DEFAULT_INCOMING_FRAME_SP_OFFSET; | |
43215a89 RH |
3069 | def_cfa_1 (&loc); |
3070 | ||
3071 | if (targetm.debug_unwind_info () == UI_DWARF2 | |
3072 | || targetm_common.except_unwind_info (&global_options) == UI_DWARF2) | |
3073 | { | |
3074 | initial_return_save (INCOMING_RETURN_ADDR_RTX); | |
3075 | ||
3076 | /* For a few targets, we have the return address incoming into a | |
3077 | register, but choose a different return column. This will result | |
3078 | in a DW_CFA_register for the return, and an entry in | |
3079 | regs_saved_in_regs to match. If the target later stores that | |
3080 | return address register to the stack, we want to be able to emit | |
3081 | the DW_CFA_offset against the return column, not the intermediate | |
3082 | save register. Save the contents of regs_saved_in_regs so that | |
3083 | we can re-initialize it at the start of each function. */ | |
9771b263 | 3084 | switch (cie_trace.regs_saved_in_regs.length ()) |
43215a89 RH |
3085 | { |
3086 | case 0: | |
3087 | break; | |
3088 | case 1: | |
766090c2 | 3089 | cie_return_save = ggc_alloc<reg_saved_in_data> (); |
9771b263 DN |
3090 | *cie_return_save = cie_trace.regs_saved_in_regs[0]; |
3091 | cie_trace.regs_saved_in_regs.release (); | |
43215a89 RH |
3092 | break; |
3093 | default: | |
3094 | gcc_unreachable (); | |
3095 | } | |
3096 | } | |
3097 | ||
3098 | add_cfi_vec = NULL; | |
3099 | cur_row = NULL; | |
3100 | cur_trace = NULL; | |
3101 | } | |
3102 | ||
7644b3c7 RH |
3103 | /* Annotate the function with NOTE_INSN_CFI notes to record the CFI |
3104 | state at each location within the function. These notes will be | |
3105 | emitted during pass_final. */ | |
647a1567 | 3106 | |
7644b3c7 RH |
3107 | static unsigned int |
3108 | execute_dwarf2_frame (void) | |
647a1567 | 3109 | { |
703fa2e6 CB |
3110 | /* Different HARD_FRAME_POINTER_REGNUM might coexist in the same file. */ |
3111 | dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM); | |
3112 | ||
7644b3c7 RH |
3113 | /* The first time we're called, compute the incoming frame state. */ |
3114 | if (cie_cfi_vec == NULL) | |
43215a89 | 3115 | create_cie_data (); |
3edb53aa | 3116 | |
7644b3c7 RH |
3117 | dwarf2out_alloc_current_fde (); |
3118 | ||
829bdd4b RH |
3119 | create_pseudo_cfg (); |
3120 | ||
7644b3c7 RH |
3121 | /* Do the work. */ |
3122 | create_cfi_notes (); | |
829bdd4b | 3123 | connect_traces (); |
7644b3c7 RH |
3124 | add_cfis_to_fde (); |
3125 | ||
829bdd4b RH |
3126 | /* Free all the data we allocated. */ |
3127 | { | |
3128 | size_t i; | |
3129 | dw_trace_info *ti; | |
647a1567 | 3130 | |
9771b263 DN |
3131 | FOR_EACH_VEC_ELT (trace_info, i, ti) |
3132 | ti->regs_saved_in_regs.release (); | |
829bdd4b | 3133 | } |
9771b263 | 3134 | trace_info.release (); |
829bdd4b | 3135 | |
c203e8a7 TS |
3136 | delete trace_index; |
3137 | trace_index = NULL; | |
f17d3401 | 3138 | |
7644b3c7 | 3139 | return 0; |
647a1567 RH |
3140 | } |
3141 | \f | |
948d330e RH |
3142 | /* Convert a DWARF call frame info. operation to its string name */ |
3143 | ||
3144 | static const char * | |
3145 | dwarf_cfi_name (unsigned int cfi_opc) | |
3146 | { | |
11ec770e | 3147 | const char *name = get_DW_CFA_name (cfi_opc); |
948d330e | 3148 | |
11ec770e TT |
3149 | if (name != NULL) |
3150 | return name; | |
948d330e | 3151 | |
11ec770e | 3152 | return "DW_CFA_<unknown>"; |
948d330e RH |
3153 | } |
3154 | ||
3155 | /* This routine will generate the correct assembly data for a location | |
3156 | description based on a cfi entry with a complex address. */ | |
3157 | ||
3158 | static void | |
3159 | output_cfa_loc (dw_cfi_ref cfi, int for_eh) | |
3160 | { | |
3161 | dw_loc_descr_ref loc; | |
3162 | unsigned long size; | |
3163 | ||
ac5b3eff JW |
3164 | if (cfi->dw_cfi_opc == DW_CFA_expression |
3165 | || cfi->dw_cfi_opc == DW_CFA_val_expression) | |
948d330e | 3166 | { |
43215a89 | 3167 | unsigned r = |
948d330e RH |
3168 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); |
3169 | dw2_asm_output_data (1, r, NULL); | |
3170 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3171 | } | |
3172 | else | |
3173 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3174 | ||
3175 | /* Output the size of the block. */ | |
3176 | size = size_of_locs (loc); | |
3177 | dw2_asm_output_data_uleb128 (size, NULL); | |
3178 | ||
3179 | /* Now output the operations themselves. */ | |
3180 | output_loc_sequence (loc, for_eh); | |
3181 | } | |
3182 | ||
3183 | /* Similar, but used for .cfi_escape. */ | |
3184 | ||
3185 | static void | |
3186 | output_cfa_loc_raw (dw_cfi_ref cfi) | |
3187 | { | |
3188 | dw_loc_descr_ref loc; | |
3189 | unsigned long size; | |
3190 | ||
ac5b3eff JW |
3191 | if (cfi->dw_cfi_opc == DW_CFA_expression |
3192 | || cfi->dw_cfi_opc == DW_CFA_val_expression) | |
948d330e | 3193 | { |
43215a89 | 3194 | unsigned r = |
948d330e RH |
3195 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); |
3196 | fprintf (asm_out_file, "%#x,", r); | |
3197 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3198 | } | |
3199 | else | |
3200 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3201 | ||
3202 | /* Output the size of the block. */ | |
3203 | size = size_of_locs (loc); | |
3204 | dw2_asm_output_data_uleb128_raw (size); | |
3205 | fputc (',', asm_out_file); | |
3206 | ||
3207 | /* Now output the operations themselves. */ | |
3208 | output_loc_sequence_raw (loc); | |
3209 | } | |
3210 | ||
3211 | /* Output a Call Frame Information opcode and its operand(s). */ | |
3212 | ||
3213 | void | |
3214 | output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh) | |
3215 | { | |
3216 | unsigned long r; | |
3217 | HOST_WIDE_INT off; | |
3218 | ||
3219 | if (cfi->dw_cfi_opc == DW_CFA_advance_loc) | |
3220 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | |
3221 | | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)), | |
3222 | "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX, | |
3223 | ((unsigned HOST_WIDE_INT) | |
3224 | cfi->dw_cfi_oprnd1.dw_cfi_offset)); | |
3225 | else if (cfi->dw_cfi_opc == DW_CFA_offset) | |
3226 | { | |
3227 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3228 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3229 | "DW_CFA_offset, column %#lx", r); | |
3230 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3231 | dw2_asm_output_data_uleb128 (off, NULL); | |
3232 | } | |
3233 | else if (cfi->dw_cfi_opc == DW_CFA_restore) | |
3234 | { | |
3235 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3236 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3237 | "DW_CFA_restore, column %#lx", r); | |
3238 | } | |
3239 | else | |
3240 | { | |
3241 | dw2_asm_output_data (1, cfi->dw_cfi_opc, | |
3242 | "%s", dwarf_cfi_name (cfi->dw_cfi_opc)); | |
3243 | ||
3244 | switch (cfi->dw_cfi_opc) | |
3245 | { | |
3246 | case DW_CFA_set_loc: | |
3247 | if (for_eh) | |
3248 | dw2_asm_output_encoded_addr_rtx ( | |
3249 | ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0), | |
3250 | gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr), | |
3251 | false, NULL); | |
3252 | else | |
3253 | dw2_asm_output_addr (DWARF2_ADDR_SIZE, | |
3254 | cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL); | |
3255 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3256 | break; | |
3257 | ||
3258 | case DW_CFA_advance_loc1: | |
3259 | dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3260 | fde->dw_fde_current_label, NULL); | |
3261 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3262 | break; | |
3263 | ||
3264 | case DW_CFA_advance_loc2: | |
3265 | dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3266 | fde->dw_fde_current_label, NULL); | |
3267 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3268 | break; | |
3269 | ||
3270 | case DW_CFA_advance_loc4: | |
3271 | dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3272 | fde->dw_fde_current_label, NULL); | |
3273 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3274 | break; | |
3275 | ||
3276 | case DW_CFA_MIPS_advance_loc8: | |
3277 | dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3278 | fde->dw_fde_current_label, NULL); | |
3279 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3280 | break; | |
3281 | ||
3282 | case DW_CFA_offset_extended: | |
3283 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3284 | dw2_asm_output_data_uleb128 (r, NULL); | |
3285 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3286 | dw2_asm_output_data_uleb128 (off, NULL); | |
3287 | break; | |
3288 | ||
3289 | case DW_CFA_def_cfa: | |
3290 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3291 | dw2_asm_output_data_uleb128 (r, NULL); | |
3292 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL); | |
3293 | break; | |
3294 | ||
3295 | case DW_CFA_offset_extended_sf: | |
3296 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3297 | dw2_asm_output_data_uleb128 (r, NULL); | |
3298 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3299 | dw2_asm_output_data_sleb128 (off, NULL); | |
3300 | break; | |
3301 | ||
3302 | case DW_CFA_def_cfa_sf: | |
3303 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3304 | dw2_asm_output_data_uleb128 (r, NULL); | |
3305 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3306 | dw2_asm_output_data_sleb128 (off, NULL); | |
3307 | break; | |
3308 | ||
3309 | case DW_CFA_restore_extended: | |
3310 | case DW_CFA_undefined: | |
3311 | case DW_CFA_same_value: | |
3312 | case DW_CFA_def_cfa_register: | |
3313 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3314 | dw2_asm_output_data_uleb128 (r, NULL); | |
3315 | break; | |
3316 | ||
3317 | case DW_CFA_register: | |
3318 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3319 | dw2_asm_output_data_uleb128 (r, NULL); | |
3320 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh); | |
3321 | dw2_asm_output_data_uleb128 (r, NULL); | |
3322 | break; | |
3323 | ||
3324 | case DW_CFA_def_cfa_offset: | |
3325 | case DW_CFA_GNU_args_size: | |
3326 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL); | |
3327 | break; | |
3328 | ||
3329 | case DW_CFA_def_cfa_offset_sf: | |
3330 | off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3331 | dw2_asm_output_data_sleb128 (off, NULL); | |
3332 | break; | |
3333 | ||
3334 | case DW_CFA_GNU_window_save: | |
3335 | break; | |
3336 | ||
3337 | case DW_CFA_def_cfa_expression: | |
3338 | case DW_CFA_expression: | |
ac5b3eff | 3339 | case DW_CFA_val_expression: |
948d330e RH |
3340 | output_cfa_loc (cfi, for_eh); |
3341 | break; | |
3342 | ||
3343 | case DW_CFA_GNU_negative_offset_extended: | |
3344 | /* Obsoleted by DW_CFA_offset_extended_sf. */ | |
3345 | gcc_unreachable (); | |
3346 | ||
3347 | default: | |
3348 | break; | |
3349 | } | |
3350 | } | |
3351 | } | |
3352 | ||
3353 | /* Similar, but do it via assembler directives instead. */ | |
3354 | ||
3355 | void | |
3356 | output_cfi_directive (FILE *f, dw_cfi_ref cfi) | |
3357 | { | |
3358 | unsigned long r, r2; | |
3359 | ||
3360 | switch (cfi->dw_cfi_opc) | |
3361 | { | |
3362 | case DW_CFA_advance_loc: | |
3363 | case DW_CFA_advance_loc1: | |
3364 | case DW_CFA_advance_loc2: | |
3365 | case DW_CFA_advance_loc4: | |
3366 | case DW_CFA_MIPS_advance_loc8: | |
3367 | case DW_CFA_set_loc: | |
3368 | /* Should only be created in a code path not followed when emitting | |
3369 | via directives. The assembler is going to take care of this for | |
3370 | us. But this routines is also used for debugging dumps, so | |
3371 | print something. */ | |
3372 | gcc_assert (f != asm_out_file); | |
3373 | fprintf (f, "\t.cfi_advance_loc\n"); | |
3374 | break; | |
3375 | ||
3376 | case DW_CFA_offset: | |
3377 | case DW_CFA_offset_extended: | |
3378 | case DW_CFA_offset_extended_sf: | |
3379 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
16998094 | 3380 | fprintf (f, "\t.cfi_offset %lu, " HOST_WIDE_INT_PRINT_DEC"\n", |
948d330e RH |
3381 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); |
3382 | break; | |
3383 | ||
3384 | case DW_CFA_restore: | |
3385 | case DW_CFA_restore_extended: | |
3386 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3387 | fprintf (f, "\t.cfi_restore %lu\n", r); | |
3388 | break; | |
3389 | ||
3390 | case DW_CFA_undefined: | |
3391 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3392 | fprintf (f, "\t.cfi_undefined %lu\n", r); | |
3393 | break; | |
3394 | ||
3395 | case DW_CFA_same_value: | |
3396 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3397 | fprintf (f, "\t.cfi_same_value %lu\n", r); | |
3398 | break; | |
3399 | ||
3400 | case DW_CFA_def_cfa: | |
3401 | case DW_CFA_def_cfa_sf: | |
3402 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
16998094 | 3403 | fprintf (f, "\t.cfi_def_cfa %lu, " HOST_WIDE_INT_PRINT_DEC"\n", |
948d330e RH |
3404 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); |
3405 | break; | |
3406 | ||
3407 | case DW_CFA_def_cfa_register: | |
3408 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3409 | fprintf (f, "\t.cfi_def_cfa_register %lu\n", r); | |
3410 | break; | |
3411 | ||
3412 | case DW_CFA_register: | |
3413 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3414 | r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1); | |
3415 | fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2); | |
3416 | break; | |
3417 | ||
3418 | case DW_CFA_def_cfa_offset: | |
3419 | case DW_CFA_def_cfa_offset_sf: | |
3420 | fprintf (f, "\t.cfi_def_cfa_offset " | |
3421 | HOST_WIDE_INT_PRINT_DEC"\n", | |
3422 | cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3423 | break; | |
3424 | ||
3425 | case DW_CFA_remember_state: | |
3426 | fprintf (f, "\t.cfi_remember_state\n"); | |
3427 | break; | |
3428 | case DW_CFA_restore_state: | |
3429 | fprintf (f, "\t.cfi_restore_state\n"); | |
3430 | break; | |
3431 | ||
3432 | case DW_CFA_GNU_args_size: | |
3433 | if (f == asm_out_file) | |
3434 | { | |
3435 | fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size); | |
3436 | dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3437 | if (flag_debug_asm) | |
16998094 | 3438 | fprintf (f, "\t%s args_size " HOST_WIDE_INT_PRINT_DEC, |
948d330e RH |
3439 | ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset); |
3440 | fputc ('\n', f); | |
3441 | } | |
3442 | else | |
3443 | { | |
16998094 | 3444 | fprintf (f, "\t.cfi_GNU_args_size " HOST_WIDE_INT_PRINT_DEC "\n", |
948d330e RH |
3445 | cfi->dw_cfi_oprnd1.dw_cfi_offset); |
3446 | } | |
3447 | break; | |
3448 | ||
3449 | case DW_CFA_GNU_window_save: | |
3450 | fprintf (f, "\t.cfi_window_save\n"); | |
3451 | break; | |
3452 | ||
3453 | case DW_CFA_def_cfa_expression: | |
948d330e | 3454 | case DW_CFA_expression: |
ac5b3eff | 3455 | case DW_CFA_val_expression: |
948d330e RH |
3456 | if (f != asm_out_file) |
3457 | { | |
ac5b3eff JW |
3458 | fprintf (f, "\t.cfi_%scfa_%sexpression ...\n", |
3459 | cfi->dw_cfi_opc == DW_CFA_def_cfa_expression ? "def_" : "", | |
3460 | cfi->dw_cfi_opc == DW_CFA_val_expression ? "val_" : ""); | |
948d330e RH |
3461 | break; |
3462 | } | |
3463 | fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc); | |
3464 | output_cfa_loc_raw (cfi); | |
3465 | fputc ('\n', f); | |
3466 | break; | |
3467 | ||
3468 | default: | |
3469 | gcc_unreachable (); | |
3470 | } | |
3471 | } | |
3472 | ||
3473 | void | |
3474 | dwarf2out_emit_cfi (dw_cfi_ref cfi) | |
3475 | { | |
3476 | if (dwarf2out_do_cfi_asm ()) | |
3477 | output_cfi_directive (asm_out_file, cfi); | |
3478 | } | |
a5d0ce89 RH |
3479 | |
3480 | static void | |
3481 | dump_cfi_row (FILE *f, dw_cfi_row *row) | |
3482 | { | |
3483 | dw_cfi_ref cfi; | |
3484 | unsigned i; | |
3485 | ||
3486 | cfi = row->cfa_cfi; | |
3487 | if (!cfi) | |
3488 | { | |
3489 | dw_cfa_location dummy; | |
c3284718 | 3490 | memset (&dummy, 0, sizeof (dummy)); |
a5d0ce89 RH |
3491 | dummy.reg = INVALID_REGNUM; |
3492 | cfi = def_cfa_0 (&dummy, &row->cfa); | |
3493 | } | |
3494 | output_cfi_directive (f, cfi); | |
3495 | ||
9771b263 | 3496 | FOR_EACH_VEC_SAFE_ELT (row->reg_save, i, cfi) |
a5d0ce89 RH |
3497 | if (cfi) |
3498 | output_cfi_directive (f, cfi); | |
a5d0ce89 RH |
3499 | } |
3500 | ||
3501 | void debug_cfi_row (dw_cfi_row *row); | |
3502 | ||
3503 | void | |
3504 | debug_cfi_row (dw_cfi_row *row) | |
3505 | { | |
3506 | dump_cfi_row (stderr, row); | |
3507 | } | |
948d330e | 3508 | \f |
647a1567 | 3509 | |
7644b3c7 RH |
3510 | /* Save the result of dwarf2out_do_frame across PCH. |
3511 | This variable is tri-state, with 0 unset, >0 true, <0 false. */ | |
3512 | static GTY(()) signed char saved_do_cfi_asm = 0; | |
647a1567 | 3513 | |
2f02b2c2 EB |
3514 | /* Decide whether to emit EH frame unwind information for the current |
3515 | translation unit. */ | |
3516 | ||
3517 | bool | |
3518 | dwarf2out_do_eh_frame (void) | |
3519 | { | |
3520 | return | |
3521 | (flag_unwind_tables || flag_exceptions) | |
3522 | && targetm_common.except_unwind_info (&global_options) == UI_DWARF2; | |
3523 | } | |
3524 | ||
647a1567 RH |
3525 | /* Decide whether we want to emit frame unwind information for the current |
3526 | translation unit. */ | |
3527 | ||
7644b3c7 | 3528 | bool |
647a1567 RH |
3529 | dwarf2out_do_frame (void) |
3530 | { | |
3531 | /* We want to emit correct CFA location expressions or lists, so we | |
3532 | have to return true if we're going to output debug info, even if | |
3533 | we're not going to output frame or unwind info. */ | |
3534 | if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG) | |
3535 | return true; | |
3536 | ||
7644b3c7 | 3537 | if (saved_do_cfi_asm > 0) |
647a1567 RH |
3538 | return true; |
3539 | ||
3540 | if (targetm.debug_unwind_info () == UI_DWARF2) | |
3541 | return true; | |
3542 | ||
2f02b2c2 | 3543 | if (dwarf2out_do_eh_frame ()) |
647a1567 RH |
3544 | return true; |
3545 | ||
3546 | return false; | |
3547 | } | |
3548 | ||
3549 | /* Decide whether to emit frame unwind via assembler directives. */ | |
3550 | ||
7644b3c7 | 3551 | bool |
647a1567 RH |
3552 | dwarf2out_do_cfi_asm (void) |
3553 | { | |
3554 | int enc; | |
3555 | ||
7644b3c7 RH |
3556 | if (saved_do_cfi_asm != 0) |
3557 | return saved_do_cfi_asm > 0; | |
3558 | ||
3559 | /* Assume failure for a moment. */ | |
3560 | saved_do_cfi_asm = -1; | |
3561 | ||
647a1567 RH |
3562 | if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ()) |
3563 | return false; | |
3564 | if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) | |
3565 | return false; | |
3566 | ||
3567 | /* Make sure the personality encoding is one the assembler can support. | |
3568 | In particular, aligned addresses can't be handled. */ | |
3569 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1); | |
3570 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3571 | return false; | |
3572 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0); | |
3573 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3574 | return false; | |
3575 | ||
3576 | /* If we can't get the assembler to emit only .debug_frame, and we don't need | |
3577 | dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */ | |
2f02b2c2 | 3578 | if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE && !dwarf2out_do_eh_frame ()) |
647a1567 RH |
3579 | return false; |
3580 | ||
7644b3c7 RH |
3581 | /* Success! */ |
3582 | saved_do_cfi_asm = 1; | |
647a1567 RH |
3583 | return true; |
3584 | } | |
3585 | ||
27a4cd48 DM |
3586 | namespace { |
3587 | ||
3588 | const pass_data pass_data_dwarf2_frame = | |
3589 | { | |
3590 | RTL_PASS, /* type */ | |
3591 | "dwarf2", /* name */ | |
3592 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
3593 | TV_FINAL, /* tv_id */ |
3594 | 0, /* properties_required */ | |
3595 | 0, /* properties_provided */ | |
3596 | 0, /* properties_destroyed */ | |
3597 | 0, /* todo_flags_start */ | |
3598 | 0, /* todo_flags_finish */ | |
7644b3c7 RH |
3599 | }; |
3600 | ||
27a4cd48 DM |
3601 | class pass_dwarf2_frame : public rtl_opt_pass |
3602 | { | |
3603 | public: | |
c3284718 RS |
3604 | pass_dwarf2_frame (gcc::context *ctxt) |
3605 | : rtl_opt_pass (pass_data_dwarf2_frame, ctxt) | |
27a4cd48 DM |
3606 | {} |
3607 | ||
3608 | /* opt_pass methods: */ | |
1a3d085c | 3609 | virtual bool gate (function *); |
be55bfe6 | 3610 | virtual unsigned int execute (function *) { return execute_dwarf2_frame (); } |
27a4cd48 DM |
3611 | |
3612 | }; // class pass_dwarf2_frame | |
3613 | ||
1a3d085c TS |
3614 | bool |
3615 | pass_dwarf2_frame::gate (function *) | |
3616 | { | |
1a3d085c TS |
3617 | /* Targets which still implement the prologue in assembler text |
3618 | cannot use the generic dwarf2 unwinding. */ | |
e86a9946 RS |
3619 | if (!targetm.have_prologue ()) |
3620 | return false; | |
1a3d085c TS |
3621 | |
3622 | /* ??? What to do for UI_TARGET unwinding? They might be able to benefit | |
3623 | from the optimized shrink-wrapping annotations that we will compute. | |
3624 | For now, only produce the CFI notes for dwarf2. */ | |
3625 | return dwarf2out_do_frame (); | |
3626 | } | |
3627 | ||
27a4cd48 DM |
3628 | } // anon namespace |
3629 | ||
3630 | rtl_opt_pass * | |
3631 | make_pass_dwarf2_frame (gcc::context *ctxt) | |
3632 | { | |
3633 | return new pass_dwarf2_frame (ctxt); | |
3634 | } | |
3635 | ||
647a1567 | 3636 | #include "gt-dwarf2cfi.h" |