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dwarf2cfi: Reset args_size properly across abnormal edges.
[thirdparty/gcc.git] / gcc / dwarf2cfi.c
CommitLineData
647a1567
RH
1/* Dwarf2 Call Frame Information helper routines.
2 Copyright (C) 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "tm.h"
26#include "version.h"
27#include "flags.h"
28#include "rtl.h"
29#include "function.h"
829bdd4b 30#include "basic-block.h"
647a1567
RH
31#include "dwarf2.h"
32#include "dwarf2out.h"
33#include "dwarf2asm.h"
34#include "ggc.h"
35#include "tm_p.h"
36#include "target.h"
37#include "common/common-target.h"
38#include "tree-pass.h"
39
40#include "except.h" /* expand_builtin_dwarf_sp_column */
41#include "expr.h" /* init_return_column_size */
42#include "regs.h" /* expand_builtin_init_dwarf_reg_sizes */
43#include "output.h" /* asm_out_file */
44#include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */
45
46
47/* ??? Poison these here until it can be done generically. They've been
48 totally replaced in this file; make sure it stays that way. */
49#undef DWARF2_UNWIND_INFO
50#undef DWARF2_FRAME_INFO
51#if (GCC_VERSION >= 3000)
52 #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO
53#endif
54
55#ifndef INCOMING_RETURN_ADDR_RTX
56#define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX)
57#endif
58
647a1567
RH
59/* Maximum size (in bytes) of an artificially generated label. */
60#define MAX_ARTIFICIAL_LABEL_BYTES 30
647a1567 61\f
f17d3401
RH
62/* A collected description of an entire row of the abstract CFI table. */
63typedef struct GTY(()) dw_cfi_row_struct
64{
65 /* The expression that computes the CFA, expressed in two different ways.
66 The CFA member for the simple cases, and the full CFI expression for
67 the complex cases. The later will be a DW_CFA_cfa_expression. */
68 dw_cfa_location cfa;
69 dw_cfi_ref cfa_cfi;
70
71 /* The expressions for any register column that is saved. */
72 cfi_vec reg_save;
73
74 /* The value of any DW_CFA_GNU_args_size. */
75 HOST_WIDE_INT args_size;
76} dw_cfi_row;
77
43215a89
RH
78/* The caller's ORIG_REG is saved in SAVED_IN_REG. */
79typedef struct GTY(()) reg_saved_in_data_struct {
80 rtx orig_reg;
81 rtx saved_in_reg;
82} reg_saved_in_data;
83
84DEF_VEC_O (reg_saved_in_data);
85DEF_VEC_ALLOC_O (reg_saved_in_data, heap);
86
87/* Since we no longer have a proper CFG, we're going to create a facsimile
88 of one on the fly while processing the frame-related insns.
89
829bdd4b
RH
90 We create dw_trace_info structures for each extended basic block beginning
91 and ending at a "save point". Save points are labels, barriers, certain
92 notes, and of course the beginning and end of the function.
43215a89
RH
93
94 As we encounter control transfer insns, we propagate the "current"
829bdd4b
RH
95 row state across the edges to the starts of traces. When checking is
96 enabled, we validate that we propagate the same data from all sources.
43215a89
RH
97
98 All traces are members of the TRACE_INFO array, in the order in which
99 they appear in the instruction stream.
100
829bdd4b
RH
101 All save points are present in the TRACE_INDEX hash, mapping the insn
102 starting a trace to the dw_trace_info describing the trace. */
43215a89
RH
103
104typedef struct
105{
829bdd4b
RH
106 /* The insn that begins the trace. */
107 rtx head;
43215a89
RH
108
109 /* The row state at the beginning and end of the trace. */
829bdd4b
RH
110 dw_cfi_row *beg_row, *end_row;
111
112 /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */
113 bool switch_sections;
43215a89
RH
114
115 /* The following variables contain data used in interpreting frame related
116 expressions. These are not part of the "real" row state as defined by
117 Dwarf, but it seems like they need to be propagated into a trace in case
118 frame related expressions have been sunk. */
119 /* ??? This seems fragile. These variables are fragments of a larger
120 expression. If we do not keep the entire expression together, we risk
121 not being able to put it together properly. Consider forcing targets
122 to generate self-contained expressions and dropping all of the magic
123 interpretation code in this file. Or at least refusing to shrink wrap
124 any frame related insn that doesn't contain a complete expression. */
125
126 /* The register used for saving registers to the stack, and its offset
127 from the CFA. */
128 dw_cfa_location cfa_store;
129
130 /* A temporary register holding an integral value used in adjusting SP
131 or setting up the store_reg. The "offset" field holds the integer
132 value, not an offset. */
133 dw_cfa_location cfa_temp;
134
135 /* A set of registers saved in other registers. This is the inverse of
136 the row->reg_save info, if the entry is a DW_CFA_register. This is
137 implemented as a flat array because it normally contains zero or 1
138 entry, depending on the target. IA-64 is the big spender here, using
139 a maximum of 5 entries. */
140 VEC(reg_saved_in_data, heap) *regs_saved_in_regs;
141
142} dw_trace_info;
143
144DEF_VEC_O (dw_trace_info);
145DEF_VEC_ALLOC_O (dw_trace_info, heap);
146
829bdd4b 147typedef dw_trace_info *dw_trace_info_ref;
43215a89 148
829bdd4b
RH
149DEF_VEC_P (dw_trace_info_ref);
150DEF_VEC_ALLOC_P (dw_trace_info_ref, heap);
43215a89
RH
151
152/* The variables making up the pseudo-cfg, as described above. */
43215a89 153static VEC (dw_trace_info, heap) *trace_info;
829bdd4b
RH
154static VEC (dw_trace_info_ref, heap) *trace_work_list;
155static htab_t trace_index;
43215a89 156
647a1567
RH
157/* A vector of call frame insns for the CIE. */
158cfi_vec cie_cfi_vec;
159
f17d3401
RH
160/* The state of the first row of the FDE table, which includes the
161 state provided by the CIE. */
ce363ef2 162static GTY(()) dw_cfi_row *cie_cfi_row;
f17d3401 163
43215a89
RH
164static GTY(()) reg_saved_in_data *cie_return_save;
165
647a1567
RH
166static GTY(()) unsigned long dwarf2out_cfi_label_num;
167
bc5612ed 168/* The insn after which a new CFI note should be emitted. */
141618e2 169static rtx add_cfi_insn;
bc5612ed 170
3edb53aa
RH
171/* When non-null, add_cfi will add the CFI to this vector. */
172static cfi_vec *add_cfi_vec;
173
43215a89
RH
174/* The current instruction trace. */
175static dw_trace_info *cur_trace;
176
177/* The current, i.e. most recently generated, row of the CFI table. */
178static dw_cfi_row *cur_row;
179
43215a89
RH
180/* We delay emitting a register save until either (a) we reach the end
181 of the prologue or (b) the register is clobbered. This clusters
182 register saves so that there are fewer pc advances. */
183
184typedef struct {
185 rtx reg;
186 rtx saved_reg;
187 HOST_WIDE_INT cfa_offset;
188} queued_reg_save;
189
190DEF_VEC_O (queued_reg_save);
191DEF_VEC_ALLOC_O (queued_reg_save, heap);
192
193static VEC(queued_reg_save, heap) *queued_reg_saves;
194
195/* The (really) current value for DW_CFA_GNU_args_size. We delay actually
196 emitting this data, i.e. updating CUR_ROW, without async unwind. */
197static HOST_WIDE_INT queued_args_size;
198
bc5612ed
BS
199/* True if any CFI directives were emitted at the current insn. */
200static bool any_cfis_emitted;
4f42d714
RH
201
202/* Short-hand for commonly used register numbers. */
203static unsigned dw_stack_pointer_regnum;
204static unsigned dw_frame_pointer_regnum;
647a1567
RH
205\f
206/* Hook used by __throw. */
207
208rtx
209expand_builtin_dwarf_sp_column (void)
210{
4f42d714 211 unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
647a1567
RH
212 return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1));
213}
214
215/* MEM is a memory reference for the register size table, each element of
216 which has mode MODE. Initialize column C as a return address column. */
217
218static void
219init_return_column_size (enum machine_mode mode, rtx mem, unsigned int c)
220{
221 HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode);
222 HOST_WIDE_INT size = GET_MODE_SIZE (Pmode);
223 emit_move_insn (adjust_address (mem, mode, offset), GEN_INT (size));
224}
225
226/* Generate code to initialize the register size table. */
227
228void
229expand_builtin_init_dwarf_reg_sizes (tree address)
230{
231 unsigned int i;
232 enum machine_mode mode = TYPE_MODE (char_type_node);
233 rtx addr = expand_normal (address);
234 rtx mem = gen_rtx_MEM (BLKmode, addr);
235 bool wrote_return_column = false;
236
237 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
238 {
4f42d714
RH
239 unsigned int dnum = DWARF_FRAME_REGNUM (i);
240 unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
647a1567
RH
241
242 if (rnum < DWARF_FRAME_REGISTERS)
243 {
244 HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
245 enum machine_mode save_mode = reg_raw_mode[i];
246 HOST_WIDE_INT size;
247
248 if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode))
249 save_mode = choose_hard_reg_mode (i, 1, true);
4f42d714 250 if (dnum == DWARF_FRAME_RETURN_COLUMN)
647a1567
RH
251 {
252 if (save_mode == VOIDmode)
253 continue;
254 wrote_return_column = true;
255 }
256 size = GET_MODE_SIZE (save_mode);
257 if (offset < 0)
258 continue;
259
260 emit_move_insn (adjust_address (mem, mode, offset),
261 gen_int_mode (size, mode));
262 }
263 }
264
265 if (!wrote_return_column)
266 init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN);
267
268#ifdef DWARF_ALT_FRAME_RETURN_COLUMN
269 init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN);
270#endif
271
272 targetm.init_dwarf_reg_sizes_extra (address);
273}
274
829bdd4b
RH
275\f
276static hashval_t
277dw_trace_info_hash (const void *ptr)
278{
279 const dw_trace_info *ti = (const dw_trace_info *) ptr;
280 return INSN_UID (ti->head);
281}
282
283static int
284dw_trace_info_eq (const void *ptr_a, const void *ptr_b)
285{
286 const dw_trace_info *a = (const dw_trace_info *) ptr_a;
287 const dw_trace_info *b = (const dw_trace_info *) ptr_b;
288 return a->head == b->head;
289}
290
291static unsigned
292get_trace_index (dw_trace_info *trace)
293{
294 return trace - VEC_address (dw_trace_info, trace_info);
295}
296
297static dw_trace_info *
298get_trace_info (rtx insn)
299{
300 dw_trace_info dummy;
301 dummy.head = insn;
302 return (dw_trace_info *)
303 htab_find_with_hash (trace_index, &dummy, INSN_UID (insn));
304}
305
306static bool
307save_point_p (rtx insn)
308{
309 /* Labels, except those that are really jump tables. */
310 if (LABEL_P (insn))
311 return inside_basic_block_p (insn);
312
313 /* We split traces at the prologue/epilogue notes because those
314 are points at which the unwind info is usually stable. This
315 makes it easier to find spots with identical unwind info so
316 that we can use remember/restore_state opcodes. */
317 if (NOTE_P (insn))
318 switch (NOTE_KIND (insn))
319 {
320 case NOTE_INSN_PROLOGUE_END:
321 case NOTE_INSN_EPILOGUE_BEG:
322 return true;
323 }
324
325 return false;
326}
327
647a1567
RH
328/* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */
329
330static inline HOST_WIDE_INT
331div_data_align (HOST_WIDE_INT off)
332{
333 HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT;
334 gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off);
335 return r;
336}
337
338/* Return true if we need a signed version of a given opcode
339 (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */
340
341static inline bool
342need_data_align_sf_opcode (HOST_WIDE_INT off)
343{
344 return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0;
345}
346
347/* Return a pointer to a newly allocated Call Frame Instruction. */
348
349static inline dw_cfi_ref
350new_cfi (void)
351{
352 dw_cfi_ref cfi = ggc_alloc_dw_cfi_node ();
353
354 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0;
355 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0;
356
357 return cfi;
358}
359
f17d3401
RH
360/* Return a newly allocated CFI row, with no defined data. */
361
ce363ef2 362static dw_cfi_row *
f17d3401
RH
363new_cfi_row (void)
364{
ce363ef2 365 dw_cfi_row *row = ggc_alloc_cleared_dw_cfi_row ();
f17d3401
RH
366
367 row->cfa.reg = INVALID_REGNUM;
368
369 return row;
370}
371
372/* Return a copy of an existing CFI row. */
373
ce363ef2
RH
374static dw_cfi_row *
375copy_cfi_row (dw_cfi_row *src)
f17d3401 376{
ce363ef2 377 dw_cfi_row *dst = ggc_alloc_dw_cfi_row ();
f17d3401
RH
378
379 *dst = *src;
380 dst->reg_save = VEC_copy (dw_cfi_ref, gc, src->reg_save);
381
382 return dst;
383}
384
89e25f95 385/* Generate a new label for the CFI info to refer to. */
647a1567
RH
386
387static char *
89e25f95 388dwarf2out_cfi_label (void)
647a1567 389{
89e25f95
BS
390 int num = dwarf2out_cfi_label_num++;
391 char label[20];
647a1567 392
89e25f95 393 ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num);
647a1567 394
89e25f95 395 return xstrdup (label);
647a1567
RH
396}
397
3edb53aa 398/* Add CFI either to the current insn stream or to a vector, or both. */
647a1567
RH
399
400static void
3edb53aa 401add_cfi (dw_cfi_ref cfi)
647a1567 402{
89e25f95 403 any_cfis_emitted = true;
141618e2
RH
404
405 if (add_cfi_insn != NULL)
647a1567 406 {
141618e2
RH
407 add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn);
408 NOTE_CFI (add_cfi_insn) = cfi;
647a1567 409 }
141618e2 410
3edb53aa
RH
411 if (add_cfi_vec != NULL)
412 VEC_safe_push (dw_cfi_ref, gc, *add_cfi_vec, cfi);
647a1567
RH
413}
414
57e16c96
RH
415static void
416add_cfi_args_size (HOST_WIDE_INT size)
417{
418 dw_cfi_ref cfi = new_cfi ();
419
420 cfi->dw_cfi_opc = DW_CFA_GNU_args_size;
421 cfi->dw_cfi_oprnd1.dw_cfi_offset = size;
422
423 add_cfi (cfi);
424}
425
426static void
427add_cfi_restore (unsigned reg)
428{
429 dw_cfi_ref cfi = new_cfi ();
430
431 cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore);
432 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
433
434 add_cfi (cfi);
435}
436
f1a0e830
RH
437/* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating
438 that the register column is no longer saved. */
439
440static void
ce363ef2 441update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi)
f1a0e830
RH
442{
443 if (VEC_length (dw_cfi_ref, row->reg_save) <= column)
444 VEC_safe_grow_cleared (dw_cfi_ref, gc, row->reg_save, column + 1);
445 VEC_replace (dw_cfi_ref, row->reg_save, column, cfi);
446}
447
647a1567
RH
448/* This function fills in aa dw_cfa_location structure from a dwarf location
449 descriptor sequence. */
450
451static void
452get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_struct *loc)
453{
454 struct dw_loc_descr_struct *ptr;
455 cfa->offset = 0;
456 cfa->base_offset = 0;
457 cfa->indirect = 0;
458 cfa->reg = -1;
459
460 for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next)
461 {
462 enum dwarf_location_atom op = ptr->dw_loc_opc;
463
464 switch (op)
465 {
466 case DW_OP_reg0:
467 case DW_OP_reg1:
468 case DW_OP_reg2:
469 case DW_OP_reg3:
470 case DW_OP_reg4:
471 case DW_OP_reg5:
472 case DW_OP_reg6:
473 case DW_OP_reg7:
474 case DW_OP_reg8:
475 case DW_OP_reg9:
476 case DW_OP_reg10:
477 case DW_OP_reg11:
478 case DW_OP_reg12:
479 case DW_OP_reg13:
480 case DW_OP_reg14:
481 case DW_OP_reg15:
482 case DW_OP_reg16:
483 case DW_OP_reg17:
484 case DW_OP_reg18:
485 case DW_OP_reg19:
486 case DW_OP_reg20:
487 case DW_OP_reg21:
488 case DW_OP_reg22:
489 case DW_OP_reg23:
490 case DW_OP_reg24:
491 case DW_OP_reg25:
492 case DW_OP_reg26:
493 case DW_OP_reg27:
494 case DW_OP_reg28:
495 case DW_OP_reg29:
496 case DW_OP_reg30:
497 case DW_OP_reg31:
498 cfa->reg = op - DW_OP_reg0;
499 break;
500 case DW_OP_regx:
501 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
502 break;
503 case DW_OP_breg0:
504 case DW_OP_breg1:
505 case DW_OP_breg2:
506 case DW_OP_breg3:
507 case DW_OP_breg4:
508 case DW_OP_breg5:
509 case DW_OP_breg6:
510 case DW_OP_breg7:
511 case DW_OP_breg8:
512 case DW_OP_breg9:
513 case DW_OP_breg10:
514 case DW_OP_breg11:
515 case DW_OP_breg12:
516 case DW_OP_breg13:
517 case DW_OP_breg14:
518 case DW_OP_breg15:
519 case DW_OP_breg16:
520 case DW_OP_breg17:
521 case DW_OP_breg18:
522 case DW_OP_breg19:
523 case DW_OP_breg20:
524 case DW_OP_breg21:
525 case DW_OP_breg22:
526 case DW_OP_breg23:
527 case DW_OP_breg24:
528 case DW_OP_breg25:
529 case DW_OP_breg26:
530 case DW_OP_breg27:
531 case DW_OP_breg28:
532 case DW_OP_breg29:
533 case DW_OP_breg30:
534 case DW_OP_breg31:
535 cfa->reg = op - DW_OP_breg0;
536 cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int;
537 break;
538 case DW_OP_bregx:
539 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
540 cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int;
541 break;
542 case DW_OP_deref:
543 cfa->indirect = 1;
544 break;
545 case DW_OP_plus_uconst:
546 cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned;
547 break;
548 default:
549 gcc_unreachable ();
550 }
551 }
552}
553
4a8ee122
RH
554/* Find the previous value for the CFA, iteratively. CFI is the opcode
555 to interpret, *LOC will be updated as necessary, *REMEMBER is used for
556 one level of remember/restore state processing. */
647a1567
RH
557
558void
559lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember)
560{
561 switch (cfi->dw_cfi_opc)
562 {
563 case DW_CFA_def_cfa_offset:
564 case DW_CFA_def_cfa_offset_sf:
565 loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset;
566 break;
567 case DW_CFA_def_cfa_register:
568 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
569 break;
570 case DW_CFA_def_cfa:
571 case DW_CFA_def_cfa_sf:
572 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
573 loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset;
574 break;
575 case DW_CFA_def_cfa_expression:
576 get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc);
577 break;
578
579 case DW_CFA_remember_state:
580 gcc_assert (!remember->in_use);
581 *remember = *loc;
582 remember->in_use = 1;
583 break;
584 case DW_CFA_restore_state:
585 gcc_assert (remember->in_use);
586 *loc = *remember;
587 remember->in_use = 0;
588 break;
589
590 default:
591 break;
592 }
593}
594
647a1567
RH
595/* Determine if two dw_cfa_location structures define the same data. */
596
597bool
598cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2)
599{
600 return (loc1->reg == loc2->reg
601 && loc1->offset == loc2->offset
602 && loc1->indirect == loc2->indirect
603 && (loc1->indirect == 0
604 || loc1->base_offset == loc2->base_offset));
605}
606
57e16c96 607/* Determine if two CFI operands are identical. */
647a1567 608
57e16c96
RH
609static bool
610cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b)
647a1567 611{
57e16c96
RH
612 switch (t)
613 {
614 case dw_cfi_oprnd_unused:
615 return true;
616 case dw_cfi_oprnd_reg_num:
617 return a->dw_cfi_reg_num == b->dw_cfi_reg_num;
618 case dw_cfi_oprnd_offset:
619 return a->dw_cfi_offset == b->dw_cfi_offset;
620 case dw_cfi_oprnd_addr:
621 return (a->dw_cfi_addr == b->dw_cfi_addr
622 || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0);
623 case dw_cfi_oprnd_loc:
624 return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc);
625 }
626 gcc_unreachable ();
627}
647a1567 628
57e16c96
RH
629/* Determine if two CFI entries are identical. */
630
631static bool
632cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b)
633{
634 enum dwarf_call_frame_info opc;
635
636 /* Make things easier for our callers, including missing operands. */
637 if (a == b)
638 return true;
639 if (a == NULL || b == NULL)
640 return false;
641
642 /* Obviously, the opcodes must match. */
643 opc = a->dw_cfi_opc;
644 if (opc != b->dw_cfi_opc)
645 return false;
646
647 /* Compare the two operands, re-using the type of the operands as
648 already exposed elsewhere. */
649 return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc),
650 &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1)
651 && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc),
652 &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2));
653}
654
829bdd4b
RH
655/* Determine if two CFI_ROW structures are identical. */
656
657static bool
658cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b)
659{
660 size_t i, n_a, n_b, n_max;
661
662 if (a->cfa_cfi)
663 {
664 if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi))
665 return false;
666 }
667 else if (!cfa_equal_p (&a->cfa, &b->cfa))
668 return false;
669
2edb462e
RH
670 /* Logic suggests that we compare args_size here. However, if
671 EXIT_IGNORE_STACK we don't bother tracking the args_size after
672 the last time it really matters within the function. This does
673 in fact lead to paths with differing arg_size, but in cases for
674 which it doesn't matter. */
675 /* ??? If we really want to sanity check the output of the optimizers,
676 find a way to backtrack from epilogues to the last EH site. This
677 would allow us to distinguish regions with garbage args_size and
678 regions where paths ought to agree. */
829bdd4b
RH
679
680 n_a = VEC_length (dw_cfi_ref, a->reg_save);
681 n_b = VEC_length (dw_cfi_ref, b->reg_save);
682 n_max = MAX (n_a, n_b);
683
684 for (i = 0; i < n_max; ++i)
685 {
686 dw_cfi_ref r_a = NULL, r_b = NULL;
687
688 if (i < n_a)
689 r_a = VEC_index (dw_cfi_ref, a->reg_save, i);
690 if (i < n_b)
691 r_b = VEC_index (dw_cfi_ref, b->reg_save, i);
692
693 if (!cfi_equal_p (r_a, r_b))
694 return false;
695 }
696
697 return true;
698}
699
57e16c96
RH
700/* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining
701 what opcode to emit. Returns the CFI opcode to effect the change, or
702 NULL if NEW_CFA == OLD_CFA. */
703
704static dw_cfi_ref
705def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa)
706{
707 dw_cfi_ref cfi;
647a1567 708
647a1567 709 /* If nothing changed, no need to issue any call frame instructions. */
57e16c96
RH
710 if (cfa_equal_p (old_cfa, new_cfa))
711 return NULL;
647a1567
RH
712
713 cfi = new_cfi ();
714
57e16c96 715 if (new_cfa->reg == old_cfa->reg && !new_cfa->indirect && !old_cfa->indirect)
647a1567
RH
716 {
717 /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating
718 the CFA register did not change but the offset did. The data
719 factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or
720 in the assembler via the .cfi_def_cfa_offset directive. */
57e16c96 721 if (new_cfa->offset < 0)
647a1567
RH
722 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf;
723 else
724 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset;
57e16c96 725 cfi->dw_cfi_oprnd1.dw_cfi_offset = new_cfa->offset;
647a1567
RH
726 }
727
728#ifndef MIPS_DEBUGGING_INFO /* SGI dbx thinks this means no offset. */
57e16c96
RH
729 else if (new_cfa->offset == old_cfa->offset
730 && old_cfa->reg != INVALID_REGNUM
731 && !new_cfa->indirect
732 && !old_cfa->indirect)
647a1567
RH
733 {
734 /* Construct a "DW_CFA_def_cfa_register <register>" instruction,
735 indicating the CFA register has changed to <register> but the
736 offset has not changed. */
737 cfi->dw_cfi_opc = DW_CFA_def_cfa_register;
57e16c96 738 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
647a1567
RH
739 }
740#endif
741
57e16c96 742 else if (new_cfa->indirect == 0)
647a1567
RH
743 {
744 /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction,
745 indicating the CFA register has changed to <register> with
746 the specified offset. The data factoring for DW_CFA_def_cfa_sf
747 happens in output_cfi, or in the assembler via the .cfi_def_cfa
748 directive. */
57e16c96 749 if (new_cfa->offset < 0)
647a1567
RH
750 cfi->dw_cfi_opc = DW_CFA_def_cfa_sf;
751 else
752 cfi->dw_cfi_opc = DW_CFA_def_cfa;
57e16c96
RH
753 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
754 cfi->dw_cfi_oprnd2.dw_cfi_offset = new_cfa->offset;
647a1567
RH
755 }
756 else
757 {
758 /* Construct a DW_CFA_def_cfa_expression instruction to
759 calculate the CFA using a full location expression since no
760 register-offset pair is available. */
761 struct dw_loc_descr_struct *loc_list;
762
763 cfi->dw_cfi_opc = DW_CFA_def_cfa_expression;
57e16c96 764 loc_list = build_cfa_loc (new_cfa, 0);
647a1567
RH
765 cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list;
766 }
767
57e16c96
RH
768 return cfi;
769}
770
771/* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */
772
773static void
774def_cfa_1 (dw_cfa_location *new_cfa)
775{
776 dw_cfi_ref cfi;
777
43215a89
RH
778 if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0)
779 cur_trace->cfa_store.offset = new_cfa->offset;
57e16c96
RH
780
781 cfi = def_cfa_0 (&cur_row->cfa, new_cfa);
782 if (cfi)
783 {
784 cur_row->cfa = *new_cfa;
785 if (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression)
786 cur_row->cfa_cfi = cfi;
787
788 add_cfi (cfi);
789 }
647a1567
RH
790}
791
792/* Add the CFI for saving a register. REG is the CFA column number.
647a1567
RH
793 If SREG is -1, the register is saved at OFFSET from the CFA;
794 otherwise it is saved in SREG. */
795
796static void
3edb53aa 797reg_save (unsigned int reg, unsigned int sreg, HOST_WIDE_INT offset)
647a1567 798{
3edb53aa 799 dw_fde_ref fde = cfun ? cfun->fde : NULL;
647a1567 800 dw_cfi_ref cfi = new_cfi ();
647a1567
RH
801
802 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
803
804 /* When stack is aligned, store REG using DW_CFA_expression with FP. */
805 if (fde
806 && fde->stack_realign
807 && sreg == INVALID_REGNUM)
808 {
809 cfi->dw_cfi_opc = DW_CFA_expression;
810 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
811 cfi->dw_cfi_oprnd2.dw_cfi_loc
f17d3401
RH
812 = build_cfa_aligned_loc (&cur_row->cfa, offset,
813 fde->stack_realignment);
647a1567
RH
814 }
815 else if (sreg == INVALID_REGNUM)
816 {
817 if (need_data_align_sf_opcode (offset))
818 cfi->dw_cfi_opc = DW_CFA_offset_extended_sf;
819 else if (reg & ~0x3f)
820 cfi->dw_cfi_opc = DW_CFA_offset_extended;
821 else
822 cfi->dw_cfi_opc = DW_CFA_offset;
823 cfi->dw_cfi_oprnd2.dw_cfi_offset = offset;
824 }
825 else if (sreg == reg)
f1a0e830
RH
826 {
827 /* While we could emit something like DW_CFA_same_value or
828 DW_CFA_restore, we never expect to see something like that
829 in a prologue. This is more likely to be a bug. A backend
830 can always bypass this by using REG_CFA_RESTORE directly. */
831 gcc_unreachable ();
832 }
647a1567
RH
833 else
834 {
835 cfi->dw_cfi_opc = DW_CFA_register;
836 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg;
837 }
838
3edb53aa 839 add_cfi (cfi);
f1a0e830 840 update_row_reg_save (cur_row, reg, cfi);
647a1567
RH
841}
842
647a1567
RH
843/* Given a SET, calculate the amount of stack adjustment it
844 contains. */
845
846static HOST_WIDE_INT
847stack_adjust_offset (const_rtx pattern, HOST_WIDE_INT cur_args_size,
848 HOST_WIDE_INT cur_offset)
849{
850 const_rtx src = SET_SRC (pattern);
851 const_rtx dest = SET_DEST (pattern);
852 HOST_WIDE_INT offset = 0;
853 enum rtx_code code;
854
855 if (dest == stack_pointer_rtx)
856 {
857 code = GET_CODE (src);
858
859 /* Assume (set (reg sp) (reg whatever)) sets args_size
860 level to 0. */
861 if (code == REG && src != stack_pointer_rtx)
862 {
863 offset = -cur_args_size;
864#ifndef STACK_GROWS_DOWNWARD
865 offset = -offset;
866#endif
867 return offset - cur_offset;
868 }
869
870 if (! (code == PLUS || code == MINUS)
871 || XEXP (src, 0) != stack_pointer_rtx
872 || !CONST_INT_P (XEXP (src, 1)))
873 return 0;
874
875 /* (set (reg sp) (plus (reg sp) (const_int))) */
876 offset = INTVAL (XEXP (src, 1));
877 if (code == PLUS)
878 offset = -offset;
879 return offset;
880 }
881
882 if (MEM_P (src) && !MEM_P (dest))
883 dest = src;
884 if (MEM_P (dest))
885 {
886 /* (set (mem (pre_dec (reg sp))) (foo)) */
887 src = XEXP (dest, 0);
888 code = GET_CODE (src);
889
890 switch (code)
891 {
892 case PRE_MODIFY:
893 case POST_MODIFY:
894 if (XEXP (src, 0) == stack_pointer_rtx)
895 {
896 rtx val = XEXP (XEXP (src, 1), 1);
897 /* We handle only adjustments by constant amount. */
898 gcc_assert (GET_CODE (XEXP (src, 1)) == PLUS
899 && CONST_INT_P (val));
900 offset = -INTVAL (val);
901 break;
902 }
903 return 0;
904
905 case PRE_DEC:
906 case POST_DEC:
907 if (XEXP (src, 0) == stack_pointer_rtx)
908 {
909 offset = GET_MODE_SIZE (GET_MODE (dest));
910 break;
911 }
912 return 0;
913
914 case PRE_INC:
915 case POST_INC:
916 if (XEXP (src, 0) == stack_pointer_rtx)
917 {
918 offset = -GET_MODE_SIZE (GET_MODE (dest));
919 break;
920 }
921 return 0;
922
923 default:
924 return 0;
925 }
926 }
927 else
928 return 0;
929
930 return offset;
931}
932
647a1567
RH
933/* Add a CFI to update the running total of the size of arguments
934 pushed onto the stack. */
935
936static void
89e25f95 937dwarf2out_args_size (HOST_WIDE_INT size)
647a1567 938{
f17d3401 939 if (size == cur_row->args_size)
647a1567
RH
940 return;
941
f17d3401 942 cur_row->args_size = size;
57e16c96 943 add_cfi_args_size (size);
647a1567
RH
944}
945
946/* Record a stack adjustment of OFFSET bytes. */
947
948static void
89e25f95 949dwarf2out_stack_adjust (HOST_WIDE_INT offset)
647a1567 950{
f17d3401
RH
951 dw_cfa_location loc = cur_row->cfa;
952
953 if (loc.reg == dw_stack_pointer_regnum)
954 loc.offset += offset;
647a1567 955
43215a89
RH
956 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum)
957 cur_trace->cfa_store.offset += offset;
958
959#ifndef STACK_GROWS_DOWNWARD
960 offset = -offset;
961#endif
962
963 queued_args_size += offset;
964 if (queued_args_size < 0)
965 queued_args_size = 0;
647a1567 966
f17d3401
RH
967 /* ??? The assumption seems to be that if A_O_A, the only CFA adjustments
968 involving the stack pointer are inside the prologue and marked as
969 RTX_FRAME_RELATED_P. That said, should we not verify this assumption
970 by *asserting* A_O_A at this point? Why else would we have a change
971 to the stack pointer? */
647a1567
RH
972 if (ACCUMULATE_OUTGOING_ARGS)
973 return;
974
f17d3401 975 def_cfa_1 (&loc);
647a1567 976 if (flag_asynchronous_unwind_tables)
43215a89 977 dwarf2out_args_size (queued_args_size);
647a1567
RH
978}
979
980/* Check INSN to see if it looks like a push or a stack adjustment, and
981 make a note of it if it does. EH uses this information to find out
982 how much extra space it needs to pop off the stack. */
983
984static void
985dwarf2out_notice_stack_adjust (rtx insn, bool after_p)
986{
987 HOST_WIDE_INT offset;
647a1567
RH
988 int i;
989
990 /* Don't handle epilogues at all. Certainly it would be wrong to do so
991 with this function. Proper support would require all frame-related
992 insns to be marked, and to be able to handle saving state around
993 epilogues textually in the middle of the function. */
994 if (prologue_epilogue_contains (insn))
995 return;
996
997 /* If INSN is an instruction from target of an annulled branch, the
998 effects are for the target only and so current argument size
999 shouldn't change at all. */
1000 if (final_sequence
1001 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
1002 && INSN_FROM_TARGET_P (insn))
1003 return;
1004
1005 /* If only calls can throw, and we have a frame pointer,
1006 save up adjustments until we see the CALL_INSN. */
f17d3401
RH
1007 if (!flag_asynchronous_unwind_tables
1008 && cur_row->cfa.reg != dw_stack_pointer_regnum)
647a1567
RH
1009 {
1010 if (CALL_P (insn) && !after_p)
1011 {
1012 /* Extract the size of the args from the CALL rtx itself. */
1013 insn = PATTERN (insn);
1014 if (GET_CODE (insn) == PARALLEL)
1015 insn = XVECEXP (insn, 0, 0);
1016 if (GET_CODE (insn) == SET)
1017 insn = SET_SRC (insn);
1018 gcc_assert (GET_CODE (insn) == CALL);
43215a89
RH
1019 gcc_assert (queued_args_size == INTVAL (XEXP (insn, 1)));
1020 dwarf2out_args_size (queued_args_size);
647a1567
RH
1021 }
1022 return;
1023 }
1024
1025 if (CALL_P (insn) && !after_p)
1026 {
1027 if (!flag_asynchronous_unwind_tables)
43215a89 1028 dwarf2out_args_size (queued_args_size);
647a1567
RH
1029 return;
1030 }
1031 else if (BARRIER_P (insn))
829bdd4b 1032 return;
647a1567 1033 else if (GET_CODE (PATTERN (insn)) == SET)
43215a89 1034 offset = stack_adjust_offset (PATTERN (insn), queued_args_size, 0);
647a1567
RH
1035 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1036 || GET_CODE (PATTERN (insn)) == SEQUENCE)
1037 {
1038 /* There may be stack adjustments inside compound insns. Search
1039 for them. */
1040 for (offset = 0, i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1041 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET)
1042 offset += stack_adjust_offset (XVECEXP (PATTERN (insn), 0, i),
43215a89 1043 queued_args_size, offset);
647a1567
RH
1044 }
1045 else
1046 return;
1047
1048 if (offset == 0)
1049 return;
1050
89e25f95 1051 dwarf2out_stack_adjust (offset);
647a1567
RH
1052}
1053
7263c6d7 1054/* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */
4f42d714
RH
1055/* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is
1056 used in places where rtl is prohibited. */
7263c6d7
RH
1057
1058static inline unsigned
1059dwf_regno (const_rtx reg)
1060{
4f42d714 1061 return DWARF_FRAME_REGNUM (REGNO (reg));
7263c6d7
RH
1062}
1063
647a1567
RH
1064/* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */
1065
1066static bool
1067compare_reg_or_pc (rtx x, rtx y)
1068{
1069 if (REG_P (x) && REG_P (y))
1070 return REGNO (x) == REGNO (y);
1071 return x == y;
1072}
1073
1074/* Record SRC as being saved in DEST. DEST may be null to delete an
1075 existing entry. SRC may be a register or PC_RTX. */
1076
1077static void
1078record_reg_saved_in_reg (rtx dest, rtx src)
1079{
1080 reg_saved_in_data *elt;
1081 size_t i;
1082
43215a89 1083 FOR_EACH_VEC_ELT (reg_saved_in_data, cur_trace->regs_saved_in_regs, i, elt)
647a1567
RH
1084 if (compare_reg_or_pc (elt->orig_reg, src))
1085 {
1086 if (dest == NULL)
43215a89
RH
1087 VEC_unordered_remove (reg_saved_in_data,
1088 cur_trace->regs_saved_in_regs, i);
647a1567
RH
1089 else
1090 elt->saved_in_reg = dest;
1091 return;
1092 }
1093
1094 if (dest == NULL)
1095 return;
1096
43215a89
RH
1097 elt = VEC_safe_push (reg_saved_in_data, heap,
1098 cur_trace->regs_saved_in_regs, NULL);
647a1567
RH
1099 elt->orig_reg = src;
1100 elt->saved_in_reg = dest;
1101}
1102
647a1567
RH
1103/* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at
1104 SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */
1105
1106static void
89e25f95 1107queue_reg_save (rtx reg, rtx sreg, HOST_WIDE_INT offset)
647a1567 1108{
999646c1
RH
1109 queued_reg_save *q;
1110 size_t i;
647a1567
RH
1111
1112 /* Duplicates waste space, but it's also necessary to remove them
a8e5c0e7 1113 for correctness, since the queue gets output in reverse order. */
999646c1 1114 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q)
a8e5c0e7 1115 if (compare_reg_or_pc (q->reg, reg))
999646c1 1116 goto found;
647a1567 1117
999646c1 1118 q = VEC_safe_push (queued_reg_save, heap, queued_reg_saves, NULL);
647a1567 1119
999646c1 1120 found:
647a1567 1121 q->reg = reg;
647a1567 1122 q->saved_reg = sreg;
999646c1 1123 q->cfa_offset = offset;
647a1567
RH
1124}
1125
1126/* Output all the entries in QUEUED_REG_SAVES. */
1127
1128static void
1129dwarf2out_flush_queued_reg_saves (void)
1130{
999646c1
RH
1131 queued_reg_save *q;
1132 size_t i;
647a1567 1133
999646c1 1134 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q)
647a1567
RH
1135 {
1136 unsigned int reg, sreg;
1137
1138 record_reg_saved_in_reg (q->saved_reg, q->reg);
1139
a8e5c0e7
RH
1140 if (q->reg == pc_rtx)
1141 reg = DWARF_FRAME_RETURN_COLUMN;
1142 else
7263c6d7 1143 reg = dwf_regno (q->reg);
647a1567 1144 if (q->saved_reg)
7263c6d7 1145 sreg = dwf_regno (q->saved_reg);
647a1567
RH
1146 else
1147 sreg = INVALID_REGNUM;
3edb53aa 1148 reg_save (reg, sreg, q->cfa_offset);
647a1567
RH
1149 }
1150
999646c1 1151 VEC_truncate (queued_reg_save, queued_reg_saves, 0);
647a1567
RH
1152}
1153
1154/* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved
1155 location for? Or, does it clobber a register which we've previously
1156 said that some other register is saved in, and for which we now
1157 have a new location for? */
1158
1159static bool
1160clobbers_queued_reg_save (const_rtx insn)
1161{
999646c1
RH
1162 queued_reg_save *q;
1163 size_t iq;
647a1567 1164
999646c1 1165 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, iq, q)
647a1567 1166 {
999646c1 1167 size_t ir;
647a1567
RH
1168 reg_saved_in_data *rir;
1169
1170 if (modified_in_p (q->reg, insn))
1171 return true;
1172
43215a89
RH
1173 FOR_EACH_VEC_ELT (reg_saved_in_data,
1174 cur_trace->regs_saved_in_regs, ir, rir)
647a1567
RH
1175 if (compare_reg_or_pc (q->reg, rir->orig_reg)
1176 && modified_in_p (rir->saved_in_reg, insn))
1177 return true;
1178 }
1179
1180 return false;
1181}
1182
1183/* What register, if any, is currently saved in REG? */
1184
1185static rtx
1186reg_saved_in (rtx reg)
1187{
1188 unsigned int regn = REGNO (reg);
999646c1 1189 queued_reg_save *q;
647a1567
RH
1190 reg_saved_in_data *rir;
1191 size_t i;
1192
999646c1 1193 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q)
647a1567
RH
1194 if (q->saved_reg && regn == REGNO (q->saved_reg))
1195 return q->reg;
1196
43215a89 1197 FOR_EACH_VEC_ELT (reg_saved_in_data, cur_trace->regs_saved_in_regs, i, rir)
647a1567
RH
1198 if (regn == REGNO (rir->saved_in_reg))
1199 return rir->orig_reg;
1200
1201 return NULL_RTX;
1202}
1203
647a1567
RH
1204/* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */
1205
1206static void
89e25f95 1207dwarf2out_frame_debug_def_cfa (rtx pat)
647a1567 1208{
f17d3401
RH
1209 dw_cfa_location loc;
1210
1211 memset (&loc, 0, sizeof (loc));
647a1567
RH
1212
1213 switch (GET_CODE (pat))
1214 {
1215 case PLUS:
f17d3401
RH
1216 loc.reg = dwf_regno (XEXP (pat, 0));
1217 loc.offset = INTVAL (XEXP (pat, 1));
647a1567
RH
1218 break;
1219
1220 case REG:
f17d3401 1221 loc.reg = dwf_regno (pat);
647a1567
RH
1222 break;
1223
1224 case MEM:
f17d3401 1225 loc.indirect = 1;
647a1567
RH
1226 pat = XEXP (pat, 0);
1227 if (GET_CODE (pat) == PLUS)
1228 {
f17d3401 1229 loc.base_offset = INTVAL (XEXP (pat, 1));
647a1567
RH
1230 pat = XEXP (pat, 0);
1231 }
f17d3401 1232 loc.reg = dwf_regno (pat);
647a1567
RH
1233 break;
1234
1235 default:
1236 /* Recurse and define an expression. */
1237 gcc_unreachable ();
1238 }
1239
f17d3401 1240 def_cfa_1 (&loc);
647a1567
RH
1241}
1242
1243/* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */
1244
1245static void
89e25f95 1246dwarf2out_frame_debug_adjust_cfa (rtx pat)
647a1567 1247{
f17d3401 1248 dw_cfa_location loc = cur_row->cfa;
647a1567
RH
1249 rtx src, dest;
1250
1251 gcc_assert (GET_CODE (pat) == SET);
1252 dest = XEXP (pat, 0);
1253 src = XEXP (pat, 1);
1254
1255 switch (GET_CODE (src))
1256 {
1257 case PLUS:
f17d3401
RH
1258 gcc_assert (dwf_regno (XEXP (src, 0)) == loc.reg);
1259 loc.offset -= INTVAL (XEXP (src, 1));
647a1567
RH
1260 break;
1261
1262 case REG:
1263 break;
1264
1265 default:
1266 gcc_unreachable ();
1267 }
1268
f17d3401
RH
1269 loc.reg = dwf_regno (dest);
1270 gcc_assert (loc.indirect == 0);
647a1567 1271
f17d3401 1272 def_cfa_1 (&loc);
647a1567
RH
1273}
1274
1275/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */
1276
1277static void
89e25f95 1278dwarf2out_frame_debug_cfa_offset (rtx set)
647a1567
RH
1279{
1280 HOST_WIDE_INT offset;
1281 rtx src, addr, span;
1282 unsigned int sregno;
1283
1284 src = XEXP (set, 1);
1285 addr = XEXP (set, 0);
1286 gcc_assert (MEM_P (addr));
1287 addr = XEXP (addr, 0);
1288
1289 /* As documented, only consider extremely simple addresses. */
1290 switch (GET_CODE (addr))
1291 {
1292 case REG:
f17d3401
RH
1293 gcc_assert (dwf_regno (addr) == cur_row->cfa.reg);
1294 offset = -cur_row->cfa.offset;
647a1567
RH
1295 break;
1296 case PLUS:
f17d3401
RH
1297 gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_row->cfa.reg);
1298 offset = INTVAL (XEXP (addr, 1)) - cur_row->cfa.offset;
647a1567
RH
1299 break;
1300 default:
1301 gcc_unreachable ();
1302 }
1303
1304 if (src == pc_rtx)
1305 {
1306 span = NULL;
1307 sregno = DWARF_FRAME_RETURN_COLUMN;
1308 }
43215a89 1309 else
647a1567
RH
1310 {
1311 span = targetm.dwarf_register_span (src);
7263c6d7 1312 sregno = dwf_regno (src);
647a1567
RH
1313 }
1314
1315 /* ??? We'd like to use queue_reg_save, but we need to come up with
1316 a different flushing heuristic for epilogues. */
1317 if (!span)
3edb53aa 1318 reg_save (sregno, INVALID_REGNUM, offset);
647a1567
RH
1319 else
1320 {
1321 /* We have a PARALLEL describing where the contents of SRC live.
1322 Queue register saves for each piece of the PARALLEL. */
1323 int par_index;
1324 int limit;
1325 HOST_WIDE_INT span_offset = offset;
1326
1327 gcc_assert (GET_CODE (span) == PARALLEL);
1328
1329 limit = XVECLEN (span, 0);
1330 for (par_index = 0; par_index < limit; par_index++)
1331 {
1332 rtx elem = XVECEXP (span, 0, par_index);
1333
7263c6d7 1334 sregno = dwf_regno (src);
3edb53aa 1335 reg_save (sregno, INVALID_REGNUM, span_offset);
647a1567
RH
1336 span_offset += GET_MODE_SIZE (GET_MODE (elem));
1337 }
1338 }
1339}
1340
1341/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */
1342
1343static void
89e25f95 1344dwarf2out_frame_debug_cfa_register (rtx set)
647a1567
RH
1345{
1346 rtx src, dest;
1347 unsigned sregno, dregno;
1348
1349 src = XEXP (set, 1);
1350 dest = XEXP (set, 0);
1351
a8e5c0e7 1352 record_reg_saved_in_reg (dest, src);
647a1567
RH
1353 if (src == pc_rtx)
1354 sregno = DWARF_FRAME_RETURN_COLUMN;
1355 else
7263c6d7 1356 sregno = dwf_regno (src);
647a1567 1357
7263c6d7 1358 dregno = dwf_regno (dest);
647a1567
RH
1359
1360 /* ??? We'd like to use queue_reg_save, but we need to come up with
1361 a different flushing heuristic for epilogues. */
3edb53aa 1362 reg_save (sregno, dregno, 0);
647a1567
RH
1363}
1364
1365/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */
1366
1367static void
89e25f95 1368dwarf2out_frame_debug_cfa_expression (rtx set)
647a1567
RH
1369{
1370 rtx src, dest, span;
1371 dw_cfi_ref cfi = new_cfi ();
f1a0e830 1372 unsigned regno;
647a1567
RH
1373
1374 dest = SET_DEST (set);
1375 src = SET_SRC (set);
1376
1377 gcc_assert (REG_P (src));
1378 gcc_assert (MEM_P (dest));
1379
1380 span = targetm.dwarf_register_span (src);
1381 gcc_assert (!span);
1382
f1a0e830
RH
1383 regno = dwf_regno (src);
1384
647a1567 1385 cfi->dw_cfi_opc = DW_CFA_expression;
f1a0e830 1386 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno;
647a1567
RH
1387 cfi->dw_cfi_oprnd2.dw_cfi_loc
1388 = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest),
1389 GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED);
1390
1391 /* ??? We'd like to use queue_reg_save, were the interface different,
1392 and, as above, we could manage flushing for epilogues. */
3edb53aa 1393 add_cfi (cfi);
f1a0e830 1394 update_row_reg_save (cur_row, regno, cfi);
647a1567
RH
1395}
1396
1397/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */
1398
1399static void
89e25f95 1400dwarf2out_frame_debug_cfa_restore (rtx reg)
647a1567 1401{
7263c6d7 1402 unsigned int regno = dwf_regno (reg);
647a1567 1403
57e16c96 1404 add_cfi_restore (regno);
f1a0e830 1405 update_row_reg_save (cur_row, regno, NULL);
647a1567
RH
1406}
1407
1408/* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE.
1409 ??? Perhaps we should note in the CIE where windows are saved (instead of
1410 assuming 0(cfa)) and what registers are in the window. */
1411
1412static void
89e25f95 1413dwarf2out_frame_debug_cfa_window_save (void)
647a1567
RH
1414{
1415 dw_cfi_ref cfi = new_cfi ();
1416
1417 cfi->dw_cfi_opc = DW_CFA_GNU_window_save;
3edb53aa 1418 add_cfi (cfi);
647a1567
RH
1419}
1420
1421/* Record call frame debugging information for an expression EXPR,
1422 which either sets SP or FP (adjusting how we calculate the frame
1423 address) or saves a register to the stack or another register.
1424 LABEL indicates the address of EXPR.
1425
1426 This function encodes a state machine mapping rtxes to actions on
1427 cfa, cfa_store, and cfa_temp.reg. We describe these rules so
1428 users need not read the source code.
1429
1430 The High-Level Picture
1431
1432 Changes in the register we use to calculate the CFA: Currently we
1433 assume that if you copy the CFA register into another register, we
1434 should take the other one as the new CFA register; this seems to
1435 work pretty well. If it's wrong for some target, it's simple
1436 enough not to set RTX_FRAME_RELATED_P on the insn in question.
1437
1438 Changes in the register we use for saving registers to the stack:
1439 This is usually SP, but not always. Again, we deduce that if you
1440 copy SP into another register (and SP is not the CFA register),
1441 then the new register is the one we will be using for register
1442 saves. This also seems to work.
1443
1444 Register saves: There's not much guesswork about this one; if
1445 RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a
1446 register save, and the register used to calculate the destination
1447 had better be the one we think we're using for this purpose.
1448 It's also assumed that a copy from a call-saved register to another
1449 register is saving that register if RTX_FRAME_RELATED_P is set on
1450 that instruction. If the copy is from a call-saved register to
1451 the *same* register, that means that the register is now the same
1452 value as in the caller.
1453
1454 Except: If the register being saved is the CFA register, and the
1455 offset is nonzero, we are saving the CFA, so we assume we have to
1456 use DW_CFA_def_cfa_expression. If the offset is 0, we assume that
1457 the intent is to save the value of SP from the previous frame.
1458
1459 In addition, if a register has previously been saved to a different
1460 register,
1461
1462 Invariants / Summaries of Rules
1463
1464 cfa current rule for calculating the CFA. It usually
f17d3401
RH
1465 consists of a register and an offset. This is
1466 actually stored in cur_row->cfa, but abbreviated
1467 for the purposes of this documentation.
647a1567
RH
1468 cfa_store register used by prologue code to save things to the stack
1469 cfa_store.offset is the offset from the value of
1470 cfa_store.reg to the actual CFA
1471 cfa_temp register holding an integral value. cfa_temp.offset
1472 stores the value, which will be used to adjust the
1473 stack pointer. cfa_temp is also used like cfa_store,
1474 to track stores to the stack via fp or a temp reg.
1475
1476 Rules 1- 4: Setting a register's value to cfa.reg or an expression
1477 with cfa.reg as the first operand changes the cfa.reg and its
1478 cfa.offset. Rule 1 and 4 also set cfa_temp.reg and
1479 cfa_temp.offset.
1480
1481 Rules 6- 9: Set a non-cfa.reg register value to a constant or an
1482 expression yielding a constant. This sets cfa_temp.reg
1483 and cfa_temp.offset.
1484
1485 Rule 5: Create a new register cfa_store used to save items to the
1486 stack.
1487
1488 Rules 10-14: Save a register to the stack. Define offset as the
1489 difference of the original location and cfa_store's
1490 location (or cfa_temp's location if cfa_temp is used).
1491
1492 Rules 16-20: If AND operation happens on sp in prologue, we assume
1493 stack is realigned. We will use a group of DW_OP_XXX
1494 expressions to represent the location of the stored
1495 register instead of CFA+offset.
1496
1497 The Rules
1498
1499 "{a,b}" indicates a choice of a xor b.
1500 "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg.
1501
1502 Rule 1:
1503 (set <reg1> <reg2>:cfa.reg)
1504 effects: cfa.reg = <reg1>
1505 cfa.offset unchanged
1506 cfa_temp.reg = <reg1>
1507 cfa_temp.offset = cfa.offset
1508
1509 Rule 2:
1510 (set sp ({minus,plus,losum} {sp,fp}:cfa.reg
1511 {<const_int>,<reg>:cfa_temp.reg}))
1512 effects: cfa.reg = sp if fp used
1513 cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp
1514 cfa_store.offset += {+/- <const_int>, cfa_temp.offset}
1515 if cfa_store.reg==sp
1516
1517 Rule 3:
1518 (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>))
1519 effects: cfa.reg = fp
1520 cfa_offset += +/- <const_int>
1521
1522 Rule 4:
1523 (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>))
1524 constraints: <reg1> != fp
1525 <reg1> != sp
1526 effects: cfa.reg = <reg1>
1527 cfa_temp.reg = <reg1>
1528 cfa_temp.offset = cfa.offset
1529
1530 Rule 5:
1531 (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg))
1532 constraints: <reg1> != fp
1533 <reg1> != sp
1534 effects: cfa_store.reg = <reg1>
1535 cfa_store.offset = cfa.offset - cfa_temp.offset
1536
1537 Rule 6:
1538 (set <reg> <const_int>)
1539 effects: cfa_temp.reg = <reg>
1540 cfa_temp.offset = <const_int>
1541
1542 Rule 7:
1543 (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>))
1544 effects: cfa_temp.reg = <reg1>
1545 cfa_temp.offset |= <const_int>
1546
1547 Rule 8:
1548 (set <reg> (high <exp>))
1549 effects: none
1550
1551 Rule 9:
1552 (set <reg> (lo_sum <exp> <const_int>))
1553 effects: cfa_temp.reg = <reg>
1554 cfa_temp.offset = <const_int>
1555
1556 Rule 10:
1557 (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>)
1558 effects: cfa_store.offset -= <const_int>
1559 cfa.offset = cfa_store.offset if cfa.reg == sp
1560 cfa.reg = sp
1561 cfa.base_offset = -cfa_store.offset
1562
1563 Rule 11:
1564 (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>)
1565 effects: cfa_store.offset += -/+ mode_size(mem)
1566 cfa.offset = cfa_store.offset if cfa.reg == sp
1567 cfa.reg = sp
1568 cfa.base_offset = -cfa_store.offset
1569
1570 Rule 12:
1571 (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>))
1572
1573 <reg2>)
1574 effects: cfa.reg = <reg1>
1575 cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset
1576
1577 Rule 13:
1578 (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>)
1579 effects: cfa.reg = <reg1>
1580 cfa.base_offset = -{cfa_store,cfa_temp}.offset
1581
1582 Rule 14:
1583 (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>)
1584 effects: cfa.reg = <reg1>
1585 cfa.base_offset = -cfa_temp.offset
1586 cfa_temp.offset -= mode_size(mem)
1587
1588 Rule 15:
1589 (set <reg> {unspec, unspec_volatile})
1590 effects: target-dependent
1591
1592 Rule 16:
1593 (set sp (and: sp <const_int>))
1594 constraints: cfa_store.reg == sp
a518b996 1595 effects: cfun->fde.stack_realign = 1
647a1567
RH
1596 cfa_store.offset = 0
1597 fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp
1598
1599 Rule 17:
1600 (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int))))
1601 effects: cfa_store.offset += -/+ mode_size(mem)
1602
1603 Rule 18:
1604 (set (mem ({pre_inc, pre_dec} sp)) fp)
1605 constraints: fde->stack_realign == 1
1606 effects: cfa_store.offset = 0
1607 cfa.reg != HARD_FRAME_POINTER_REGNUM
1608
1609 Rule 19:
1610 (set (mem ({pre_inc, pre_dec} sp)) cfa.reg)
1611 constraints: fde->stack_realign == 1
1612 && cfa.offset == 0
1613 && cfa.indirect == 0
1614 && cfa.reg != HARD_FRAME_POINTER_REGNUM
1615 effects: Use DW_CFA_def_cfa_expression to define cfa
1616 cfa.reg == fde->drap_reg */
1617
1618static void
89e25f95 1619dwarf2out_frame_debug_expr (rtx expr)
647a1567 1620{
f17d3401 1621 dw_cfa_location cfa = cur_row->cfa;
647a1567
RH
1622 rtx src, dest, span;
1623 HOST_WIDE_INT offset;
1624 dw_fde_ref fde;
1625
1626 /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of
1627 the PARALLEL independently. The first element is always processed if
1628 it is a SET. This is for backward compatibility. Other elements
1629 are processed only if they are SETs and the RTX_FRAME_RELATED_P
1630 flag is set in them. */
1631 if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE)
1632 {
1633 int par_index;
1634 int limit = XVECLEN (expr, 0);
1635 rtx elem;
1636
1637 /* PARALLELs have strict read-modify-write semantics, so we
1638 ought to evaluate every rvalue before changing any lvalue.
1639 It's cumbersome to do that in general, but there's an
1640 easy approximation that is enough for all current users:
1641 handle register saves before register assignments. */
1642 if (GET_CODE (expr) == PARALLEL)
1643 for (par_index = 0; par_index < limit; par_index++)
1644 {
1645 elem = XVECEXP (expr, 0, par_index);
1646 if (GET_CODE (elem) == SET
1647 && MEM_P (SET_DEST (elem))
1648 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
89e25f95 1649 dwarf2out_frame_debug_expr (elem);
647a1567
RH
1650 }
1651
1652 for (par_index = 0; par_index < limit; par_index++)
1653 {
1654 elem = XVECEXP (expr, 0, par_index);
1655 if (GET_CODE (elem) == SET
1656 && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE)
1657 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
89e25f95 1658 dwarf2out_frame_debug_expr (elem);
647a1567
RH
1659 else if (GET_CODE (elem) == SET
1660 && par_index != 0
1661 && !RTX_FRAME_RELATED_P (elem))
1662 {
1663 /* Stack adjustment combining might combine some post-prologue
1664 stack adjustment into a prologue stack adjustment. */
43215a89
RH
1665 HOST_WIDE_INT offset
1666 = stack_adjust_offset (elem, queued_args_size, 0);
647a1567
RH
1667
1668 if (offset != 0)
89e25f95 1669 dwarf2out_stack_adjust (offset);
647a1567
RH
1670 }
1671 }
1672 return;
1673 }
1674
1675 gcc_assert (GET_CODE (expr) == SET);
1676
1677 src = SET_SRC (expr);
1678 dest = SET_DEST (expr);
1679
1680 if (REG_P (src))
1681 {
1682 rtx rsi = reg_saved_in (src);
1683 if (rsi)
1684 src = rsi;
1685 }
1686
a518b996 1687 fde = cfun->fde;
647a1567
RH
1688
1689 switch (GET_CODE (dest))
1690 {
1691 case REG:
1692 switch (GET_CODE (src))
1693 {
1694 /* Setting FP from SP. */
1695 case REG:
7263c6d7 1696 if (cfa.reg == dwf_regno (src))
647a1567
RH
1697 {
1698 /* Rule 1 */
1699 /* Update the CFA rule wrt SP or FP. Make sure src is
1700 relative to the current CFA register.
1701
1702 We used to require that dest be either SP or FP, but the
1703 ARM copies SP to a temporary register, and from there to
1704 FP. So we just rely on the backends to only set
1705 RTX_FRAME_RELATED_P on appropriate insns. */
7263c6d7 1706 cfa.reg = dwf_regno (dest);
43215a89
RH
1707 cur_trace->cfa_temp.reg = cfa.reg;
1708 cur_trace->cfa_temp.offset = cfa.offset;
647a1567
RH
1709 }
1710 else
1711 {
1712 /* Saving a register in a register. */
1713 gcc_assert (!fixed_regs [REGNO (dest)]
1714 /* For the SPARC and its register window. */
7263c6d7 1715 || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN));
647a1567
RH
1716
1717 /* After stack is aligned, we can only save SP in FP
1718 if drap register is used. In this case, we have
1719 to restore stack pointer with the CFA value and we
1720 don't generate this DWARF information. */
1721 if (fde
1722 && fde->stack_realign
1723 && REGNO (src) == STACK_POINTER_REGNUM)
1724 gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM
1725 && fde->drap_reg != INVALID_REGNUM
7263c6d7 1726 && cfa.reg != dwf_regno (src));
647a1567 1727 else
89e25f95 1728 queue_reg_save (src, dest, 0);
647a1567
RH
1729 }
1730 break;
1731
1732 case PLUS:
1733 case MINUS:
1734 case LO_SUM:
1735 if (dest == stack_pointer_rtx)
1736 {
1737 /* Rule 2 */
1738 /* Adjusting SP. */
1739 switch (GET_CODE (XEXP (src, 1)))
1740 {
1741 case CONST_INT:
1742 offset = INTVAL (XEXP (src, 1));
1743 break;
1744 case REG:
43215a89
RH
1745 gcc_assert (dwf_regno (XEXP (src, 1))
1746 == cur_trace->cfa_temp.reg);
1747 offset = cur_trace->cfa_temp.offset;
647a1567
RH
1748 break;
1749 default:
1750 gcc_unreachable ();
1751 }
1752
1753 if (XEXP (src, 0) == hard_frame_pointer_rtx)
1754 {
1755 /* Restoring SP from FP in the epilogue. */
4f42d714
RH
1756 gcc_assert (cfa.reg == dw_frame_pointer_regnum);
1757 cfa.reg = dw_stack_pointer_regnum;
647a1567
RH
1758 }
1759 else if (GET_CODE (src) == LO_SUM)
1760 /* Assume we've set the source reg of the LO_SUM from sp. */
1761 ;
1762 else
1763 gcc_assert (XEXP (src, 0) == stack_pointer_rtx);
1764
1765 if (GET_CODE (src) != MINUS)
1766 offset = -offset;
4f42d714 1767 if (cfa.reg == dw_stack_pointer_regnum)
647a1567 1768 cfa.offset += offset;
43215a89
RH
1769 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum)
1770 cur_trace->cfa_store.offset += offset;
647a1567
RH
1771 }
1772 else if (dest == hard_frame_pointer_rtx)
1773 {
1774 /* Rule 3 */
1775 /* Either setting the FP from an offset of the SP,
1776 or adjusting the FP */
1777 gcc_assert (frame_pointer_needed);
1778
1779 gcc_assert (REG_P (XEXP (src, 0))
7263c6d7 1780 && dwf_regno (XEXP (src, 0)) == cfa.reg
647a1567
RH
1781 && CONST_INT_P (XEXP (src, 1)));
1782 offset = INTVAL (XEXP (src, 1));
1783 if (GET_CODE (src) != MINUS)
1784 offset = -offset;
1785 cfa.offset += offset;
4f42d714 1786 cfa.reg = dw_frame_pointer_regnum;
647a1567
RH
1787 }
1788 else
1789 {
1790 gcc_assert (GET_CODE (src) != MINUS);
1791
1792 /* Rule 4 */
1793 if (REG_P (XEXP (src, 0))
7263c6d7 1794 && dwf_regno (XEXP (src, 0)) == cfa.reg
647a1567
RH
1795 && CONST_INT_P (XEXP (src, 1)))
1796 {
1797 /* Setting a temporary CFA register that will be copied
1798 into the FP later on. */
1799 offset = - INTVAL (XEXP (src, 1));
1800 cfa.offset += offset;
7263c6d7 1801 cfa.reg = dwf_regno (dest);
647a1567 1802 /* Or used to save regs to the stack. */
43215a89
RH
1803 cur_trace->cfa_temp.reg = cfa.reg;
1804 cur_trace->cfa_temp.offset = cfa.offset;
647a1567
RH
1805 }
1806
1807 /* Rule 5 */
1808 else if (REG_P (XEXP (src, 0))
43215a89 1809 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
647a1567
RH
1810 && XEXP (src, 1) == stack_pointer_rtx)
1811 {
1812 /* Setting a scratch register that we will use instead
1813 of SP for saving registers to the stack. */
4f42d714 1814 gcc_assert (cfa.reg == dw_stack_pointer_regnum);
43215a89
RH
1815 cur_trace->cfa_store.reg = dwf_regno (dest);
1816 cur_trace->cfa_store.offset
1817 = cfa.offset - cur_trace->cfa_temp.offset;
647a1567
RH
1818 }
1819
1820 /* Rule 9 */
1821 else if (GET_CODE (src) == LO_SUM
1822 && CONST_INT_P (XEXP (src, 1)))
1823 {
43215a89
RH
1824 cur_trace->cfa_temp.reg = dwf_regno (dest);
1825 cur_trace->cfa_temp.offset = INTVAL (XEXP (src, 1));
647a1567
RH
1826 }
1827 else
1828 gcc_unreachable ();
1829 }
1830 break;
1831
1832 /* Rule 6 */
1833 case CONST_INT:
43215a89
RH
1834 cur_trace->cfa_temp.reg = dwf_regno (dest);
1835 cur_trace->cfa_temp.offset = INTVAL (src);
647a1567
RH
1836 break;
1837
1838 /* Rule 7 */
1839 case IOR:
1840 gcc_assert (REG_P (XEXP (src, 0))
43215a89 1841 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
647a1567
RH
1842 && CONST_INT_P (XEXP (src, 1)));
1843
43215a89
RH
1844 cur_trace->cfa_temp.reg = dwf_regno (dest);
1845 cur_trace->cfa_temp.offset |= INTVAL (XEXP (src, 1));
647a1567
RH
1846 break;
1847
1848 /* Skip over HIGH, assuming it will be followed by a LO_SUM,
1849 which will fill in all of the bits. */
1850 /* Rule 8 */
1851 case HIGH:
1852 break;
1853
1854 /* Rule 15 */
1855 case UNSPEC:
1856 case UNSPEC_VOLATILE:
89e25f95
BS
1857 /* All unspecs should be represented by REG_CFA_* notes. */
1858 gcc_unreachable ();
647a1567
RH
1859 return;
1860
1861 /* Rule 16 */
1862 case AND:
1863 /* If this AND operation happens on stack pointer in prologue,
1864 we assume the stack is realigned and we extract the
1865 alignment. */
1866 if (fde && XEXP (src, 0) == stack_pointer_rtx)
1867 {
1868 /* We interpret reg_save differently with stack_realign set.
1869 Thus we must flush whatever we have queued first. */
1870 dwarf2out_flush_queued_reg_saves ();
1871
43215a89
RH
1872 gcc_assert (cur_trace->cfa_store.reg
1873 == dwf_regno (XEXP (src, 0)));
647a1567
RH
1874 fde->stack_realign = 1;
1875 fde->stack_realignment = INTVAL (XEXP (src, 1));
43215a89 1876 cur_trace->cfa_store.offset = 0;
647a1567 1877
4f42d714
RH
1878 if (cfa.reg != dw_stack_pointer_regnum
1879 && cfa.reg != dw_frame_pointer_regnum)
647a1567
RH
1880 fde->drap_reg = cfa.reg;
1881 }
1882 return;
1883
1884 default:
1885 gcc_unreachable ();
1886 }
1887
3edb53aa 1888 def_cfa_1 (&cfa);
647a1567
RH
1889 break;
1890
1891 case MEM:
1892
1893 /* Saving a register to the stack. Make sure dest is relative to the
1894 CFA register. */
1895 switch (GET_CODE (XEXP (dest, 0)))
1896 {
1897 /* Rule 10 */
1898 /* With a push. */
1899 case PRE_MODIFY:
1900 case POST_MODIFY:
1901 /* We can't handle variable size modifications. */
1902 gcc_assert (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
1903 == CONST_INT);
1904 offset = -INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1));
1905
1906 gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
43215a89 1907 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
647a1567 1908
43215a89 1909 cur_trace->cfa_store.offset += offset;
4f42d714 1910 if (cfa.reg == dw_stack_pointer_regnum)
43215a89 1911 cfa.offset = cur_trace->cfa_store.offset;
647a1567
RH
1912
1913 if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY)
43215a89 1914 offset -= cur_trace->cfa_store.offset;
647a1567 1915 else
43215a89 1916 offset = -cur_trace->cfa_store.offset;
647a1567
RH
1917 break;
1918
1919 /* Rule 11 */
1920 case PRE_INC:
1921 case PRE_DEC:
1922 case POST_DEC:
1923 offset = GET_MODE_SIZE (GET_MODE (dest));
1924 if (GET_CODE (XEXP (dest, 0)) == PRE_INC)
1925 offset = -offset;
1926
1927 gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0))
1928 == STACK_POINTER_REGNUM)
43215a89 1929 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
647a1567 1930
43215a89 1931 cur_trace->cfa_store.offset += offset;
647a1567
RH
1932
1933 /* Rule 18: If stack is aligned, we will use FP as a
1934 reference to represent the address of the stored
1935 regiser. */
1936 if (fde
1937 && fde->stack_realign
1938 && src == hard_frame_pointer_rtx)
1939 {
4f42d714 1940 gcc_assert (cfa.reg != dw_frame_pointer_regnum);
43215a89 1941 cur_trace->cfa_store.offset = 0;
647a1567
RH
1942 }
1943
4f42d714 1944 if (cfa.reg == dw_stack_pointer_regnum)
43215a89 1945 cfa.offset = cur_trace->cfa_store.offset;
647a1567
RH
1946
1947 if (GET_CODE (XEXP (dest, 0)) == POST_DEC)
43215a89 1948 offset += -cur_trace->cfa_store.offset;
647a1567 1949 else
43215a89 1950 offset = -cur_trace->cfa_store.offset;
647a1567
RH
1951 break;
1952
1953 /* Rule 12 */
1954 /* With an offset. */
1955 case PLUS:
1956 case MINUS:
1957 case LO_SUM:
1958 {
7263c6d7 1959 unsigned int regno;
647a1567
RH
1960
1961 gcc_assert (CONST_INT_P (XEXP (XEXP (dest, 0), 1))
1962 && REG_P (XEXP (XEXP (dest, 0), 0)));
1963 offset = INTVAL (XEXP (XEXP (dest, 0), 1));
1964 if (GET_CODE (XEXP (dest, 0)) == MINUS)
1965 offset = -offset;
1966
7263c6d7 1967 regno = dwf_regno (XEXP (XEXP (dest, 0), 0));
647a1567 1968
7263c6d7 1969 if (cfa.reg == regno)
647a1567 1970 offset -= cfa.offset;
43215a89
RH
1971 else if (cur_trace->cfa_store.reg == regno)
1972 offset -= cur_trace->cfa_store.offset;
647a1567
RH
1973 else
1974 {
43215a89
RH
1975 gcc_assert (cur_trace->cfa_temp.reg == regno);
1976 offset -= cur_trace->cfa_temp.offset;
647a1567
RH
1977 }
1978 }
1979 break;
1980
1981 /* Rule 13 */
1982 /* Without an offset. */
1983 case REG:
1984 {
7263c6d7 1985 unsigned int regno = dwf_regno (XEXP (dest, 0));
647a1567 1986
7263c6d7 1987 if (cfa.reg == regno)
647a1567 1988 offset = -cfa.offset;
43215a89
RH
1989 else if (cur_trace->cfa_store.reg == regno)
1990 offset = -cur_trace->cfa_store.offset;
647a1567
RH
1991 else
1992 {
43215a89
RH
1993 gcc_assert (cur_trace->cfa_temp.reg == regno);
1994 offset = -cur_trace->cfa_temp.offset;
647a1567
RH
1995 }
1996 }
1997 break;
1998
1999 /* Rule 14 */
2000 case POST_INC:
43215a89
RH
2001 gcc_assert (cur_trace->cfa_temp.reg
2002 == dwf_regno (XEXP (XEXP (dest, 0), 0)));
2003 offset = -cur_trace->cfa_temp.offset;
2004 cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest));
647a1567
RH
2005 break;
2006
2007 default:
2008 gcc_unreachable ();
2009 }
2010
a8e5c0e7
RH
2011 /* Rule 17 */
2012 /* If the source operand of this MEM operation is a memory,
2013 we only care how much stack grew. */
2014 if (MEM_P (src))
647a1567
RH
2015 break;
2016
a8e5c0e7
RH
2017 if (REG_P (src)
2018 && REGNO (src) != STACK_POINTER_REGNUM
647a1567 2019 && REGNO (src) != HARD_FRAME_POINTER_REGNUM
7263c6d7 2020 && dwf_regno (src) == cfa.reg)
647a1567
RH
2021 {
2022 /* We're storing the current CFA reg into the stack. */
2023
2024 if (cfa.offset == 0)
2025 {
2026 /* Rule 19 */
2027 /* If stack is aligned, putting CFA reg into stack means
2028 we can no longer use reg + offset to represent CFA.
2029 Here we use DW_CFA_def_cfa_expression instead. The
2030 result of this expression equals to the original CFA
2031 value. */
2032 if (fde
2033 && fde->stack_realign
2034 && cfa.indirect == 0
4f42d714 2035 && cfa.reg != dw_frame_pointer_regnum)
647a1567
RH
2036 {
2037 dw_cfa_location cfa_exp;
2038
2039 gcc_assert (fde->drap_reg == cfa.reg);
2040
2041 cfa_exp.indirect = 1;
4f42d714 2042 cfa_exp.reg = dw_frame_pointer_regnum;
647a1567
RH
2043 cfa_exp.base_offset = offset;
2044 cfa_exp.offset = 0;
2045
2046 fde->drap_reg_saved = 1;
2047
3edb53aa 2048 def_cfa_1 (&cfa_exp);
647a1567
RH
2049 break;
2050 }
2051
2052 /* If the source register is exactly the CFA, assume
2053 we're saving SP like any other register; this happens
2054 on the ARM. */
3edb53aa 2055 def_cfa_1 (&cfa);
89e25f95 2056 queue_reg_save (stack_pointer_rtx, NULL_RTX, offset);
647a1567
RH
2057 break;
2058 }
2059 else
2060 {
2061 /* Otherwise, we'll need to look in the stack to
2062 calculate the CFA. */
2063 rtx x = XEXP (dest, 0);
2064
2065 if (!REG_P (x))
2066 x = XEXP (x, 0);
2067 gcc_assert (REG_P (x));
2068
7263c6d7 2069 cfa.reg = dwf_regno (x);
647a1567
RH
2070 cfa.base_offset = offset;
2071 cfa.indirect = 1;
3edb53aa 2072 def_cfa_1 (&cfa);
647a1567
RH
2073 break;
2074 }
2075 }
2076
3edb53aa 2077 def_cfa_1 (&cfa);
647a1567 2078
a8e5c0e7
RH
2079 span = NULL;
2080 if (REG_P (src))
2081 span = targetm.dwarf_register_span (src);
2082 if (!span)
2083 queue_reg_save (src, NULL_RTX, offset);
2084 else
2085 {
2086 /* We have a PARALLEL describing where the contents of SRC live.
2087 Queue register saves for each piece of the PARALLEL. */
2088 int par_index;
2089 int limit;
2090 HOST_WIDE_INT span_offset = offset;
647a1567 2091
a8e5c0e7 2092 gcc_assert (GET_CODE (span) == PARALLEL);
647a1567 2093
a8e5c0e7
RH
2094 limit = XVECLEN (span, 0);
2095 for (par_index = 0; par_index < limit; par_index++)
2096 {
2097 rtx elem = XVECEXP (span, 0, par_index);
2098 queue_reg_save (elem, NULL_RTX, span_offset);
2099 span_offset += GET_MODE_SIZE (GET_MODE (elem));
2100 }
2101 }
647a1567
RH
2102 break;
2103
2104 default:
2105 gcc_unreachable ();
2106 }
2107}
2108
2109/* Record call frame debugging information for INSN, which either
2110 sets SP or FP (adjusting how we calculate the frame address) or saves a
2111 register to the stack. If INSN is NULL_RTX, initialize our state.
2112
2113 If AFTER_P is false, we're being called before the insn is emitted,
2114 otherwise after. Call instructions get invoked twice. */
2115
7644b3c7 2116static void
647a1567
RH
2117dwarf2out_frame_debug (rtx insn, bool after_p)
2118{
647a1567
RH
2119 rtx note, n;
2120 bool handled_one = false;
2121 bool need_flush = false;
2122
2123 if (!NONJUMP_INSN_P (insn) || clobbers_queued_reg_save (insn))
2124 dwarf2out_flush_queued_reg_saves ();
2125
2126 if (!RTX_FRAME_RELATED_P (insn))
2127 {
2128 /* ??? This should be done unconditionally since stack adjustments
2129 matter if the stack pointer is not the CFA register anymore but
2130 is still used to save registers. */
2131 if (!ACCUMULATE_OUTGOING_ARGS)
2132 dwarf2out_notice_stack_adjust (insn, after_p);
2133 return;
2134 }
2135
647a1567
RH
2136 any_cfis_emitted = false;
2137
2138 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2139 switch (REG_NOTE_KIND (note))
2140 {
2141 case REG_FRAME_RELATED_EXPR:
2142 insn = XEXP (note, 0);
2143 goto do_frame_expr;
2144
2145 case REG_CFA_DEF_CFA:
89e25f95 2146 dwarf2out_frame_debug_def_cfa (XEXP (note, 0));
647a1567
RH
2147 handled_one = true;
2148 break;
2149
2150 case REG_CFA_ADJUST_CFA:
2151 n = XEXP (note, 0);
2152 if (n == NULL)
2153 {
2154 n = PATTERN (insn);
2155 if (GET_CODE (n) == PARALLEL)
2156 n = XVECEXP (n, 0, 0);
2157 }
89e25f95 2158 dwarf2out_frame_debug_adjust_cfa (n);
647a1567
RH
2159 handled_one = true;
2160 break;
2161
2162 case REG_CFA_OFFSET:
2163 n = XEXP (note, 0);
2164 if (n == NULL)
2165 n = single_set (insn);
89e25f95 2166 dwarf2out_frame_debug_cfa_offset (n);
647a1567
RH
2167 handled_one = true;
2168 break;
2169
2170 case REG_CFA_REGISTER:
2171 n = XEXP (note, 0);
2172 if (n == NULL)
2173 {
2174 n = PATTERN (insn);
2175 if (GET_CODE (n) == PARALLEL)
2176 n = XVECEXP (n, 0, 0);
2177 }
89e25f95 2178 dwarf2out_frame_debug_cfa_register (n);
647a1567
RH
2179 handled_one = true;
2180 break;
2181
2182 case REG_CFA_EXPRESSION:
2183 n = XEXP (note, 0);
2184 if (n == NULL)
2185 n = single_set (insn);
89e25f95 2186 dwarf2out_frame_debug_cfa_expression (n);
647a1567
RH
2187 handled_one = true;
2188 break;
2189
2190 case REG_CFA_RESTORE:
2191 n = XEXP (note, 0);
2192 if (n == NULL)
2193 {
2194 n = PATTERN (insn);
2195 if (GET_CODE (n) == PARALLEL)
2196 n = XVECEXP (n, 0, 0);
2197 n = XEXP (n, 0);
2198 }
89e25f95 2199 dwarf2out_frame_debug_cfa_restore (n);
647a1567
RH
2200 handled_one = true;
2201 break;
2202
2203 case REG_CFA_SET_VDRAP:
2204 n = XEXP (note, 0);
2205 if (REG_P (n))
2206 {
a518b996 2207 dw_fde_ref fde = cfun->fde;
647a1567
RH
2208 if (fde)
2209 {
2210 gcc_assert (fde->vdrap_reg == INVALID_REGNUM);
2211 if (REG_P (n))
7263c6d7 2212 fde->vdrap_reg = dwf_regno (n);
647a1567
RH
2213 }
2214 }
2215 handled_one = true;
2216 break;
2217
2218 case REG_CFA_WINDOW_SAVE:
89e25f95 2219 dwarf2out_frame_debug_cfa_window_save ();
647a1567
RH
2220 handled_one = true;
2221 break;
2222
2223 case REG_CFA_FLUSH_QUEUE:
2224 /* The actual flush happens below. */
2225 need_flush = true;
2226 handled_one = true;
2227 break;
2228
2229 default:
2230 break;
2231 }
2232
2233 if (handled_one)
2234 {
2235 /* Minimize the number of advances by emitting the entire queue
2236 once anything is emitted. */
2237 need_flush |= any_cfis_emitted;
2238 }
2239 else
2240 {
2241 insn = PATTERN (insn);
2242 do_frame_expr:
89e25f95 2243 dwarf2out_frame_debug_expr (insn);
647a1567
RH
2244
2245 /* Check again. A parallel can save and update the same register.
2246 We could probably check just once, here, but this is safer than
2247 removing the check at the start of the function. */
2248 if (any_cfis_emitted || clobbers_queued_reg_save (insn))
2249 need_flush = true;
2250 }
2251
2252 if (need_flush)
2253 dwarf2out_flush_queued_reg_saves ();
2254}
2255
57e16c96
RH
2256/* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */
2257
2258static void
ce363ef2 2259change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row)
57e16c96
RH
2260{
2261 size_t i, n_old, n_new, n_max;
2262 dw_cfi_ref cfi;
2263
2264 if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi))
2265 add_cfi (new_row->cfa_cfi);
2266 else
2267 {
2268 cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa);
2269 if (cfi)
2270 add_cfi (cfi);
2271 }
2272
2273 if (old_row->args_size != new_row->args_size)
2274 add_cfi_args_size (new_row->args_size);
2275
2276 n_old = VEC_length (dw_cfi_ref, old_row->reg_save);
2277 n_new = VEC_length (dw_cfi_ref, new_row->reg_save);
2278 n_max = MAX (n_old, n_new);
2279
2280 for (i = 0; i < n_max; ++i)
2281 {
2282 dw_cfi_ref r_old = NULL, r_new = NULL;
2283
2284 if (i < n_old)
2285 r_old = VEC_index (dw_cfi_ref, old_row->reg_save, i);
2286 if (i < n_new)
2287 r_new = VEC_index (dw_cfi_ref, new_row->reg_save, i);
2288
2289 if (r_old == r_new)
2290 ;
2291 else if (r_new == NULL)
2292 add_cfi_restore (i);
2293 else if (!cfi_equal_p (r_old, r_new))
2294 add_cfi (r_new);
2295 }
2296}
2297
89e25f95
BS
2298/* Examine CFI and return true if a cfi label and set_loc is needed
2299 beforehand. Even when generating CFI assembler instructions, we
4a8ee122 2300 still have to add the cfi to the list so that lookup_cfa_1 works
89e25f95
BS
2301 later on. When -g2 and above we even need to force emitting of
2302 CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list
2303 purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa
2304 and so don't use convert_cfa_to_fb_loc_list. */
2305
2306static bool
2307cfi_label_required_p (dw_cfi_ref cfi)
2308{
2309 if (!dwarf2out_do_cfi_asm ())
2310 return true;
2311
2312 if (dwarf_version == 2
2313 && debug_info_level > DINFO_LEVEL_TERSE
2314 && (write_symbols == DWARF2_DEBUG
2315 || write_symbols == VMS_AND_DWARF2_DEBUG))
2316 {
2317 switch (cfi->dw_cfi_opc)
2318 {
2319 case DW_CFA_def_cfa_offset:
2320 case DW_CFA_def_cfa_offset_sf:
2321 case DW_CFA_def_cfa_register:
2322 case DW_CFA_def_cfa:
2323 case DW_CFA_def_cfa_sf:
2324 case DW_CFA_def_cfa_expression:
2325 case DW_CFA_restore_state:
2326 return true;
2327 default:
2328 return false;
2329 }
2330 }
2331 return false;
2332}
2333
2334/* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the
2335 function's FDE, adding CFI labels and set_loc/advance_loc opcodes as
2336 necessary. */
2337static void
2338add_cfis_to_fde (void)
2339{
a518b996 2340 dw_fde_ref fde = cfun->fde;
89e25f95
BS
2341 rtx insn, next;
2342 /* We always start with a function_begin label. */
2343 bool first = false;
2344
2345 for (insn = get_insns (); insn; insn = next)
2346 {
2347 next = NEXT_INSN (insn);
2348
2349 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2350 {
57e16c96
RH
2351 fde->dw_fde_switch_cfi_index
2352 = VEC_length (dw_cfi_ref, fde->dw_fde_cfi);
89e25f95
BS
2353 /* Don't attempt to advance_loc4 between labels
2354 in different sections. */
2355 first = true;
2356 }
2357
2358 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI)
2359 {
2360 bool required = cfi_label_required_p (NOTE_CFI (insn));
2361 while (next && NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI)
2362 {
2363 required |= cfi_label_required_p (NOTE_CFI (next));
2364 next = NEXT_INSN (next);
2365 }
2366 if (required)
2367 {
2368 int num = dwarf2out_cfi_label_num;
2369 const char *label = dwarf2out_cfi_label ();
2370 dw_cfi_ref xcfi;
2371 rtx tmp;
2372
2373 /* Set the location counter to the new label. */
2374 xcfi = new_cfi ();
2375 xcfi->dw_cfi_opc = (first ? DW_CFA_set_loc
2376 : DW_CFA_advance_loc4);
2377 xcfi->dw_cfi_oprnd1.dw_cfi_addr = label;
2378 VEC_safe_push (dw_cfi_ref, gc, fde->dw_fde_cfi, xcfi);
2379
2380 tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn);
2381 NOTE_LABEL_NUMBER (tmp) = num;
2382 }
2383
2384 do
2385 {
2386 VEC_safe_push (dw_cfi_ref, gc, fde->dw_fde_cfi, NOTE_CFI (insn));
2387 insn = NEXT_INSN (insn);
2388 }
2389 while (insn != next);
2390 first = false;
2391 }
2392 }
2393}
2394
829bdd4b
RH
2395/* If LABEL is the start of a trace, then initialize the state of that
2396 trace from CUR_TRACE and CUR_ROW. */
43215a89 2397
7644b3c7 2398static void
2f23f97a 2399maybe_record_trace_start (rtx start, rtx origin, bool abnormal)
89e25f95 2400{
829bdd4b
RH
2401 dw_trace_info *ti;
2402
2403 /* Sync queued data before propagating to a destination,
2404 lest we propagate out-of-date data. */
2405 dwarf2out_flush_queued_reg_saves ();
2406 dwarf2out_args_size (queued_args_size);
2407
2408 ti = get_trace_info (start);
2409 gcc_assert (ti != NULL);
647a1567 2410
829bdd4b 2411 if (dump_file)
647a1567 2412 {
829bdd4b
RH
2413 fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n",
2414 get_trace_index (cur_trace), get_trace_index (ti),
2415 (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"),
2416 (origin ? INSN_UID (origin) : 0));
2417 }
bc5612ed 2418
829bdd4b
RH
2419 if (ti->beg_row == NULL)
2420 {
2421 /* This is the first time we've encountered this trace. Propagate
2422 state across the edge and push the trace onto the work list. */
2423 ti->beg_row = copy_cfi_row (cur_row);
2f23f97a
RH
2424 /* On all abnormal edges, especially EH and non-local-goto, we take
2425 care to free the pushed arguments. */
2426 if (abnormal)
2427 ti->beg_row->args_size = 0;
2428
829bdd4b
RH
2429 ti->cfa_store = cur_trace->cfa_store;
2430 ti->cfa_temp = cur_trace->cfa_temp;
2431 ti->regs_saved_in_regs = VEC_copy (reg_saved_in_data, heap,
2432 cur_trace->regs_saved_in_regs);
2433
2434 VEC_safe_push (dw_trace_info_ref, heap, trace_work_list, ti);
2435
2436 if (dump_file)
2437 fprintf (dump_file, "\tpush trace %u to worklist\n",
2438 get_trace_index (ti));
2439 }
2440 else
2441 {
2442 /* We ought to have the same state incoming to a given trace no
2443 matter how we arrive at the trace. Anything else means we've
2444 got some kind of optimization error. */
2445 gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row));
2446 }
2447}
45fba6d1 2448
829bdd4b
RH
2449/* Propagate CUR_TRACE state to the destinations implied by INSN. */
2450/* ??? Sadly, this is in large part a duplicate of make_edges. */
2451
2452static void
2453create_trace_edges (rtx insn)
2454{
2455 rtx tmp, lab;
2456 int i, n;
2457
2458 if (JUMP_P (insn))
2459 {
2460 if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
2461 ;
2462 else if (tablejump_p (insn, NULL, &tmp))
bc5612ed 2463 {
829bdd4b 2464 rtvec vec;
bc5612ed 2465
829bdd4b
RH
2466 tmp = PATTERN (tmp);
2467 vec = XVEC (tmp, GET_CODE (tmp) == ADDR_DIFF_VEC);
2468
2469 n = GET_NUM_ELEM (vec);
2470 for (i = 0; i < n; ++i)
2471 {
2472 lab = XEXP (RTVEC_ELT (vec, i), 0);
2f23f97a 2473 maybe_record_trace_start (lab, insn, false);
829bdd4b
RH
2474 }
2475 }
2476 else if (computed_jump_p (insn))
bc5612ed 2477 {
829bdd4b 2478 for (lab = forced_labels; lab; lab = XEXP (lab, 1))
2f23f97a 2479 maybe_record_trace_start (XEXP (lab, 0), insn, true);
829bdd4b
RH
2480 }
2481 else if (returnjump_p (insn))
2482 ;
2483 else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL)
2484 {
2485 n = ASM_OPERANDS_LABEL_LENGTH (tmp);
2486 for (i = 0; i < n; ++i)
bc5612ed 2487 {
829bdd4b 2488 lab = XEXP (ASM_OPERANDS_LABEL (tmp, i), 0);
2f23f97a 2489 maybe_record_trace_start (lab, insn, true);
829bdd4b
RH
2490 }
2491 }
2492 else
2493 {
2494 lab = JUMP_LABEL (insn);
2495 gcc_assert (lab != NULL);
2f23f97a 2496 maybe_record_trace_start (lab, insn, false);
829bdd4b
RH
2497 }
2498 }
2499 else if (CALL_P (insn))
2500 {
2501 /* Sibling calls don't have edges inside this function. */
2502 if (SIBLING_CALL_P (insn))
2503 return;
965b2557 2504
829bdd4b
RH
2505 /* Process non-local goto edges. */
2506 if (can_nonlocal_goto (insn))
2507 for (lab = nonlocal_goto_handler_labels; lab; lab = XEXP (lab, 1))
2f23f97a 2508 maybe_record_trace_start (XEXP (lab, 0), insn, true);
829bdd4b 2509 }
965b2557 2510
829bdd4b
RH
2511 /* Process EH edges. */
2512 if (CALL_P (insn) || cfun->can_throw_non_call_exceptions)
2513 {
2514 eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn);
2515 if (lp)
2f23f97a 2516 maybe_record_trace_start (lp->landing_pad, insn, true);
829bdd4b
RH
2517 }
2518}
57e16c96 2519
829bdd4b
RH
2520/* Scan the trace beginning at INSN and create the CFI notes for the
2521 instructions therein. */
2522
2523static void
2524scan_trace (dw_trace_info *trace)
2525{
2526 rtx insn = trace->head;
2527
2528 if (dump_file)
2529 fprintf (dump_file, "Processing trace %u : start at %s %d\n",
2530 get_trace_index (trace), rtx_name[(int) GET_CODE (insn)],
2531 INSN_UID (insn));
2532
2533 trace->end_row = copy_cfi_row (trace->beg_row);
2534
2535 cur_trace = trace;
2536 cur_row = trace->end_row;
2537 queued_args_size = cur_row->args_size;
2538
2539 for (insn = NEXT_INSN (insn); insn ; insn = NEXT_INSN (insn))
2540 {
2541 rtx pat;
2542
2543 add_cfi_insn = PREV_INSN (insn);
2544
2545 /* Notice the end of a trace. */
2546 if (BARRIER_P (insn) || save_point_p (insn))
2547 {
2548 dwarf2out_flush_queued_reg_saves ();
2549 dwarf2out_args_size (queued_args_size);
2550
2551 /* Propagate across fallthru edges. */
2552 if (!BARRIER_P (insn))
2f23f97a 2553 maybe_record_trace_start (insn, NULL, false);
829bdd4b 2554 break;
bc5612ed
BS
2555 }
2556
829bdd4b 2557 if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn))
bc5612ed
BS
2558 continue;
2559
2560 pat = PATTERN (insn);
2561 if (asm_noperands (pat) >= 0)
2562 {
2563 dwarf2out_frame_debug (insn, false);
829bdd4b 2564 add_cfi_insn = insn;
bc5612ed 2565 }
829bdd4b 2566 else
bc5612ed 2567 {
829bdd4b
RH
2568 if (GET_CODE (pat) == SEQUENCE)
2569 {
2570 int i, n = XVECLEN (pat, 0);
2571 for (i = 1; i < n; ++i)
2572 dwarf2out_frame_debug (XVECEXP (pat, 0, i), false);
2573 }
2574
2575 if (CALL_P (insn))
2576 dwarf2out_frame_debug (insn, false);
2577 else if (find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)
2578 || (cfun->can_throw_non_call_exceptions
2579 && can_throw_internal (insn)))
2580 dwarf2out_flush_queued_reg_saves ();
bc5612ed 2581
829bdd4b
RH
2582 /* Do not separate tablejump insns from their ADDR_DIFF_VEC.
2583 Putting the note after the VEC should be ok. */
2584 if (!tablejump_p (insn, NULL, &add_cfi_insn))
2585 add_cfi_insn = insn;
bc5612ed 2586
829bdd4b
RH
2587 dwarf2out_frame_debug (insn, true);
2588 }
45fba6d1 2589
829bdd4b
RH
2590 /* Note that a test for control_flow_insn_p does exactly the
2591 same tests as are done to actually create the edges. So
2592 always call the routine and let it not create edges for
2593 non-control-flow insns. */
2594 create_trace_edges (insn);
647a1567 2595 }
45fba6d1 2596
141618e2 2597 add_cfi_insn = NULL;
829bdd4b
RH
2598 cur_row = NULL;
2599 cur_trace = NULL;
647a1567
RH
2600}
2601
829bdd4b 2602/* Scan the function and create the initial set of CFI notes. */
647a1567 2603
bc5612ed 2604static void
829bdd4b 2605create_cfi_notes (void)
647a1567 2606{
829bdd4b 2607 dw_trace_info *ti;
647a1567 2608
829bdd4b
RH
2609 gcc_checking_assert (queued_reg_saves == NULL);
2610 gcc_checking_assert (trace_work_list == NULL);
647a1567 2611
829bdd4b
RH
2612 /* Always begin at the entry trace. */
2613 ti = VEC_index (dw_trace_info, trace_info, 0);
2614 scan_trace (ti);
647a1567 2615
829bdd4b
RH
2616 while (!VEC_empty (dw_trace_info_ref, trace_work_list))
2617 {
2618 ti = VEC_pop (dw_trace_info_ref, trace_work_list);
2619 scan_trace (ti);
647a1567
RH
2620 }
2621
829bdd4b
RH
2622 VEC_free (queued_reg_save, heap, queued_reg_saves);
2623 VEC_free (dw_trace_info_ref, heap, trace_work_list);
2624}
647a1567 2625
829bdd4b
RH
2626/* Insert CFI notes between traces to properly change state between them. */
2627/* ??? TODO: Make use of remember/restore_state. */
647a1567 2628
829bdd4b
RH
2629static void
2630connect_traces (void)
2631{
2632 unsigned i, n = VEC_length (dw_trace_info, trace_info);
2633 dw_trace_info *prev_ti, *ti;
2634
2635 prev_ti = VEC_index (dw_trace_info, trace_info, 0);
2636
2637 for (i = 1; i < n; ++i, prev_ti = ti)
647a1567 2638 {
829bdd4b 2639 dw_cfi_row *old_row;
647a1567 2640
829bdd4b 2641 ti = VEC_index (dw_trace_info, trace_info, i);
647a1567 2642
829bdd4b
RH
2643 /* We must have both queued and processed every trace. */
2644 gcc_assert (ti->beg_row && ti->end_row);
2645
2646 /* In dwarf2out_switch_text_section, we'll begin a new FDE
2647 for the portion of the function in the alternate text
2648 section. The row state at the very beginning of that
2649 new FDE will be exactly the row state from the CIE. */
2650 if (ti->switch_sections)
2651 old_row = cie_cfi_row;
2652 else
2653 old_row = prev_ti->end_row;
2654
2655 add_cfi_insn = ti->head;
2656 change_cfi_row (old_row, ti->beg_row);
2657
2658 if (dump_file && add_cfi_insn != ti->head)
2659 {
2660 rtx note;
2661
2662 fprintf (dump_file, "Fixup between trace %u and %u:\n", i - 1, i);
2663
2664 note = ti->head;
2665 do
2666 {
2667 note = NEXT_INSN (note);
2668 gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI);
2669 output_cfi_directive (dump_file, NOTE_CFI (note));
2670 }
2671 while (note != add_cfi_insn);
2672 }
2673 }
647a1567
RH
2674}
2675
829bdd4b
RH
2676/* Set up the pseudo-cfg of instruction traces, as described at the
2677 block comment at the top of the file. */
647a1567 2678
bc5612ed 2679static void
829bdd4b 2680create_pseudo_cfg (void)
647a1567 2681{
829bdd4b
RH
2682 bool saw_barrier, switch_sections;
2683 dw_trace_info *ti;
2684 rtx insn;
2685 unsigned i;
2686
2687 /* The first trace begins at the start of the function,
2688 and begins with the CIE row state. */
2689 trace_info = VEC_alloc (dw_trace_info, heap, 16);
2690 ti = VEC_quick_push (dw_trace_info, trace_info, NULL);
2691
2692 memset (ti, 0, sizeof (*ti));
2693 ti->head = get_insns ();
2694 ti->beg_row = cie_cfi_row;
2695 ti->cfa_store = cie_cfi_row->cfa;
2696 ti->cfa_temp.reg = INVALID_REGNUM;
2697 if (cie_return_save)
2698 VEC_safe_push (reg_saved_in_data, heap,
2699 ti->regs_saved_in_regs, cie_return_save);
647a1567 2700
829bdd4b
RH
2701 /* Walk all the insns, collecting start of trace locations. */
2702 saw_barrier = false;
2703 switch_sections = false;
2704 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2705 {
2706 if (BARRIER_P (insn))
2707 saw_barrier = true;
2708 else if (NOTE_P (insn)
2709 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2710 {
2711 /* We should have just seen a barrier. */
2712 gcc_assert (saw_barrier);
2713 switch_sections = true;
2714 }
2715 /* Watch out for save_point notes between basic blocks.
2716 In particular, a note after a barrier. Do not record these,
2717 delaying trace creation until the label. */
2718 else if (save_point_p (insn)
2719 && (LABEL_P (insn) || !saw_barrier))
2720 {
2721 ti = VEC_safe_push (dw_trace_info, heap, trace_info, NULL);
2722 memset (ti, 0, sizeof (*ti));
2723 ti->head = insn;
2724 ti->switch_sections = switch_sections;
2725
2726 saw_barrier = false;
2727 switch_sections = false;
2728 }
2729 }
2730
2731 /* Create the trace index after we've finished building trace_info,
2732 avoiding stale pointer problems due to reallocation. */
2733 trace_index = htab_create (VEC_length (dw_trace_info, trace_info),
2734 dw_trace_info_hash, dw_trace_info_eq, NULL);
2735 FOR_EACH_VEC_ELT (dw_trace_info, trace_info, i, ti)
2736 {
2737 void **slot;
647a1567 2738
829bdd4b
RH
2739 if (dump_file)
2740 fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", i,
2741 rtx_name[(int) GET_CODE (ti->head)], INSN_UID (ti->head),
2742 ti->switch_sections ? " (section switch)" : "");
2743
2744 slot = htab_find_slot_with_hash (trace_index, ti,
2745 INSN_UID (ti->head), INSERT);
2746 gcc_assert (*slot == NULL);
2747 *slot = (void *) ti;
2748 }
647a1567 2749}
829bdd4b 2750
a8e5c0e7
RH
2751/* Record the initial position of the return address. RTL is
2752 INCOMING_RETURN_ADDR_RTX. */
2753
2754static void
2755initial_return_save (rtx rtl)
2756{
2757 unsigned int reg = INVALID_REGNUM;
2758 HOST_WIDE_INT offset = 0;
2759
2760 switch (GET_CODE (rtl))
2761 {
2762 case REG:
2763 /* RA is in a register. */
7263c6d7 2764 reg = dwf_regno (rtl);
a8e5c0e7
RH
2765 break;
2766
2767 case MEM:
2768 /* RA is on the stack. */
2769 rtl = XEXP (rtl, 0);
2770 switch (GET_CODE (rtl))
2771 {
2772 case REG:
2773 gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM);
2774 offset = 0;
2775 break;
2776
2777 case PLUS:
2778 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2779 offset = INTVAL (XEXP (rtl, 1));
2780 break;
2781
2782 case MINUS:
2783 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2784 offset = -INTVAL (XEXP (rtl, 1));
2785 break;
2786
2787 default:
2788 gcc_unreachable ();
2789 }
2790
2791 break;
2792
2793 case PLUS:
2794 /* The return address is at some offset from any value we can
2795 actually load. For instance, on the SPARC it is in %i7+8. Just
2796 ignore the offset for now; it doesn't matter for unwinding frames. */
2797 gcc_assert (CONST_INT_P (XEXP (rtl, 1)));
2798 initial_return_save (XEXP (rtl, 0));
2799 return;
2800
2801 default:
2802 gcc_unreachable ();
2803 }
2804
2805 if (reg != DWARF_FRAME_RETURN_COLUMN)
2806 {
2807 if (reg != INVALID_REGNUM)
2808 record_reg_saved_in_reg (rtl, pc_rtx);
f17d3401 2809 reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset);
a8e5c0e7
RH
2810 }
2811}
647a1567 2812
43215a89
RH
2813static void
2814create_cie_data (void)
2815{
2816 dw_cfa_location loc;
2817 dw_trace_info cie_trace;
2818
2819 dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
2820 dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM);
2821
2822 memset (&cie_trace, 0, sizeof(cie_trace));
2823 cur_trace = &cie_trace;
2824
2825 add_cfi_vec = &cie_cfi_vec;
2826 cie_cfi_row = cur_row = new_cfi_row ();
2827
2828 /* On entry, the Canonical Frame Address is at SP. */
2829 memset(&loc, 0, sizeof (loc));
2830 loc.reg = dw_stack_pointer_regnum;
2831 loc.offset = INCOMING_FRAME_SP_OFFSET;
2832 def_cfa_1 (&loc);
2833
2834 if (targetm.debug_unwind_info () == UI_DWARF2
2835 || targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
2836 {
2837 initial_return_save (INCOMING_RETURN_ADDR_RTX);
2838
2839 /* For a few targets, we have the return address incoming into a
2840 register, but choose a different return column. This will result
2841 in a DW_CFA_register for the return, and an entry in
2842 regs_saved_in_regs to match. If the target later stores that
2843 return address register to the stack, we want to be able to emit
2844 the DW_CFA_offset against the return column, not the intermediate
2845 save register. Save the contents of regs_saved_in_regs so that
2846 we can re-initialize it at the start of each function. */
2847 switch (VEC_length (reg_saved_in_data, cie_trace.regs_saved_in_regs))
2848 {
2849 case 0:
2850 break;
2851 case 1:
2852 cie_return_save = ggc_alloc_reg_saved_in_data ();
2853 *cie_return_save = *VEC_index (reg_saved_in_data,
2854 cie_trace.regs_saved_in_regs, 0);
2855 VEC_free (reg_saved_in_data, heap, cie_trace.regs_saved_in_regs);
2856 break;
2857 default:
2858 gcc_unreachable ();
2859 }
2860 }
2861
2862 add_cfi_vec = NULL;
2863 cur_row = NULL;
2864 cur_trace = NULL;
2865}
2866
7644b3c7
RH
2867/* Annotate the function with NOTE_INSN_CFI notes to record the CFI
2868 state at each location within the function. These notes will be
2869 emitted during pass_final. */
647a1567 2870
7644b3c7
RH
2871static unsigned int
2872execute_dwarf2_frame (void)
647a1567 2873{
7644b3c7
RH
2874 /* The first time we're called, compute the incoming frame state. */
2875 if (cie_cfi_vec == NULL)
43215a89 2876 create_cie_data ();
3edb53aa 2877
7644b3c7
RH
2878 dwarf2out_alloc_current_fde ();
2879
829bdd4b
RH
2880 create_pseudo_cfg ();
2881
7644b3c7
RH
2882 /* Do the work. */
2883 create_cfi_notes ();
829bdd4b 2884 connect_traces ();
7644b3c7
RH
2885 add_cfis_to_fde ();
2886
829bdd4b
RH
2887 /* Free all the data we allocated. */
2888 {
2889 size_t i;
2890 dw_trace_info *ti;
647a1567 2891
829bdd4b
RH
2892 FOR_EACH_VEC_ELT (dw_trace_info, trace_info, i, ti)
2893 VEC_free (reg_saved_in_data, heap, ti->regs_saved_in_regs);
2894 }
2895 VEC_free (dw_trace_info, heap, trace_info);
2896
2897 htab_delete (trace_index);
2898 trace_index = NULL;
f17d3401 2899
7644b3c7 2900 return 0;
647a1567
RH
2901}
2902\f
948d330e
RH
2903/* Convert a DWARF call frame info. operation to its string name */
2904
2905static const char *
2906dwarf_cfi_name (unsigned int cfi_opc)
2907{
2908 switch (cfi_opc)
2909 {
2910 case DW_CFA_advance_loc:
2911 return "DW_CFA_advance_loc";
2912 case DW_CFA_offset:
2913 return "DW_CFA_offset";
2914 case DW_CFA_restore:
2915 return "DW_CFA_restore";
2916 case DW_CFA_nop:
2917 return "DW_CFA_nop";
2918 case DW_CFA_set_loc:
2919 return "DW_CFA_set_loc";
2920 case DW_CFA_advance_loc1:
2921 return "DW_CFA_advance_loc1";
2922 case DW_CFA_advance_loc2:
2923 return "DW_CFA_advance_loc2";
2924 case DW_CFA_advance_loc4:
2925 return "DW_CFA_advance_loc4";
2926 case DW_CFA_offset_extended:
2927 return "DW_CFA_offset_extended";
2928 case DW_CFA_restore_extended:
2929 return "DW_CFA_restore_extended";
2930 case DW_CFA_undefined:
2931 return "DW_CFA_undefined";
2932 case DW_CFA_same_value:
2933 return "DW_CFA_same_value";
2934 case DW_CFA_register:
2935 return "DW_CFA_register";
2936 case DW_CFA_remember_state:
2937 return "DW_CFA_remember_state";
2938 case DW_CFA_restore_state:
2939 return "DW_CFA_restore_state";
2940 case DW_CFA_def_cfa:
2941 return "DW_CFA_def_cfa";
2942 case DW_CFA_def_cfa_register:
2943 return "DW_CFA_def_cfa_register";
2944 case DW_CFA_def_cfa_offset:
2945 return "DW_CFA_def_cfa_offset";
2946
2947 /* DWARF 3 */
2948 case DW_CFA_def_cfa_expression:
2949 return "DW_CFA_def_cfa_expression";
2950 case DW_CFA_expression:
2951 return "DW_CFA_expression";
2952 case DW_CFA_offset_extended_sf:
2953 return "DW_CFA_offset_extended_sf";
2954 case DW_CFA_def_cfa_sf:
2955 return "DW_CFA_def_cfa_sf";
2956 case DW_CFA_def_cfa_offset_sf:
2957 return "DW_CFA_def_cfa_offset_sf";
2958
2959 /* SGI/MIPS specific */
2960 case DW_CFA_MIPS_advance_loc8:
2961 return "DW_CFA_MIPS_advance_loc8";
2962
2963 /* GNU extensions */
2964 case DW_CFA_GNU_window_save:
2965 return "DW_CFA_GNU_window_save";
2966 case DW_CFA_GNU_args_size:
2967 return "DW_CFA_GNU_args_size";
2968 case DW_CFA_GNU_negative_offset_extended:
2969 return "DW_CFA_GNU_negative_offset_extended";
2970
2971 default:
2972 return "DW_CFA_<unknown>";
2973 }
2974}
2975
2976/* This routine will generate the correct assembly data for a location
2977 description based on a cfi entry with a complex address. */
2978
2979static void
2980output_cfa_loc (dw_cfi_ref cfi, int for_eh)
2981{
2982 dw_loc_descr_ref loc;
2983 unsigned long size;
2984
2985 if (cfi->dw_cfi_opc == DW_CFA_expression)
2986 {
43215a89 2987 unsigned r =
948d330e
RH
2988 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
2989 dw2_asm_output_data (1, r, NULL);
2990 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
2991 }
2992 else
2993 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
2994
2995 /* Output the size of the block. */
2996 size = size_of_locs (loc);
2997 dw2_asm_output_data_uleb128 (size, NULL);
2998
2999 /* Now output the operations themselves. */
3000 output_loc_sequence (loc, for_eh);
3001}
3002
3003/* Similar, but used for .cfi_escape. */
3004
3005static void
3006output_cfa_loc_raw (dw_cfi_ref cfi)
3007{
3008 dw_loc_descr_ref loc;
3009 unsigned long size;
3010
3011 if (cfi->dw_cfi_opc == DW_CFA_expression)
3012 {
43215a89 3013 unsigned r =
948d330e
RH
3014 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3015 fprintf (asm_out_file, "%#x,", r);
3016 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
3017 }
3018 else
3019 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
3020
3021 /* Output the size of the block. */
3022 size = size_of_locs (loc);
3023 dw2_asm_output_data_uleb128_raw (size);
3024 fputc (',', asm_out_file);
3025
3026 /* Now output the operations themselves. */
3027 output_loc_sequence_raw (loc);
3028}
3029
3030/* Output a Call Frame Information opcode and its operand(s). */
3031
3032void
3033output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh)
3034{
3035 unsigned long r;
3036 HOST_WIDE_INT off;
3037
3038 if (cfi->dw_cfi_opc == DW_CFA_advance_loc)
3039 dw2_asm_output_data (1, (cfi->dw_cfi_opc
3040 | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)),
3041 "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX,
3042 ((unsigned HOST_WIDE_INT)
3043 cfi->dw_cfi_oprnd1.dw_cfi_offset));
3044 else if (cfi->dw_cfi_opc == DW_CFA_offset)
3045 {
3046 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3047 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3048 "DW_CFA_offset, column %#lx", r);
3049 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3050 dw2_asm_output_data_uleb128 (off, NULL);
3051 }
3052 else if (cfi->dw_cfi_opc == DW_CFA_restore)
3053 {
3054 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3055 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3056 "DW_CFA_restore, column %#lx", r);
3057 }
3058 else
3059 {
3060 dw2_asm_output_data (1, cfi->dw_cfi_opc,
3061 "%s", dwarf_cfi_name (cfi->dw_cfi_opc));
3062
3063 switch (cfi->dw_cfi_opc)
3064 {
3065 case DW_CFA_set_loc:
3066 if (for_eh)
3067 dw2_asm_output_encoded_addr_rtx (
3068 ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0),
3069 gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr),
3070 false, NULL);
3071 else
3072 dw2_asm_output_addr (DWARF2_ADDR_SIZE,
3073 cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL);
3074 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3075 break;
3076
3077 case DW_CFA_advance_loc1:
3078 dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3079 fde->dw_fde_current_label, NULL);
3080 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3081 break;
3082
3083 case DW_CFA_advance_loc2:
3084 dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3085 fde->dw_fde_current_label, NULL);
3086 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3087 break;
3088
3089 case DW_CFA_advance_loc4:
3090 dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3091 fde->dw_fde_current_label, NULL);
3092 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3093 break;
3094
3095 case DW_CFA_MIPS_advance_loc8:
3096 dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3097 fde->dw_fde_current_label, NULL);
3098 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3099 break;
3100
3101 case DW_CFA_offset_extended:
3102 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3103 dw2_asm_output_data_uleb128 (r, NULL);
3104 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3105 dw2_asm_output_data_uleb128 (off, NULL);
3106 break;
3107
3108 case DW_CFA_def_cfa:
3109 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3110 dw2_asm_output_data_uleb128 (r, NULL);
3111 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL);
3112 break;
3113
3114 case DW_CFA_offset_extended_sf:
3115 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3116 dw2_asm_output_data_uleb128 (r, NULL);
3117 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3118 dw2_asm_output_data_sleb128 (off, NULL);
3119 break;
3120
3121 case DW_CFA_def_cfa_sf:
3122 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3123 dw2_asm_output_data_uleb128 (r, NULL);
3124 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3125 dw2_asm_output_data_sleb128 (off, NULL);
3126 break;
3127
3128 case DW_CFA_restore_extended:
3129 case DW_CFA_undefined:
3130 case DW_CFA_same_value:
3131 case DW_CFA_def_cfa_register:
3132 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3133 dw2_asm_output_data_uleb128 (r, NULL);
3134 break;
3135
3136 case DW_CFA_register:
3137 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3138 dw2_asm_output_data_uleb128 (r, NULL);
3139 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh);
3140 dw2_asm_output_data_uleb128 (r, NULL);
3141 break;
3142
3143 case DW_CFA_def_cfa_offset:
3144 case DW_CFA_GNU_args_size:
3145 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL);
3146 break;
3147
3148 case DW_CFA_def_cfa_offset_sf:
3149 off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3150 dw2_asm_output_data_sleb128 (off, NULL);
3151 break;
3152
3153 case DW_CFA_GNU_window_save:
3154 break;
3155
3156 case DW_CFA_def_cfa_expression:
3157 case DW_CFA_expression:
3158 output_cfa_loc (cfi, for_eh);
3159 break;
3160
3161 case DW_CFA_GNU_negative_offset_extended:
3162 /* Obsoleted by DW_CFA_offset_extended_sf. */
3163 gcc_unreachable ();
3164
3165 default:
3166 break;
3167 }
3168 }
3169}
3170
3171/* Similar, but do it via assembler directives instead. */
3172
3173void
3174output_cfi_directive (FILE *f, dw_cfi_ref cfi)
3175{
3176 unsigned long r, r2;
3177
3178 switch (cfi->dw_cfi_opc)
3179 {
3180 case DW_CFA_advance_loc:
3181 case DW_CFA_advance_loc1:
3182 case DW_CFA_advance_loc2:
3183 case DW_CFA_advance_loc4:
3184 case DW_CFA_MIPS_advance_loc8:
3185 case DW_CFA_set_loc:
3186 /* Should only be created in a code path not followed when emitting
3187 via directives. The assembler is going to take care of this for
3188 us. But this routines is also used for debugging dumps, so
3189 print something. */
3190 gcc_assert (f != asm_out_file);
3191 fprintf (f, "\t.cfi_advance_loc\n");
3192 break;
3193
3194 case DW_CFA_offset:
3195 case DW_CFA_offset_extended:
3196 case DW_CFA_offset_extended_sf:
3197 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3198 fprintf (f, "\t.cfi_offset %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3199 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3200 break;
3201
3202 case DW_CFA_restore:
3203 case DW_CFA_restore_extended:
3204 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3205 fprintf (f, "\t.cfi_restore %lu\n", r);
3206 break;
3207
3208 case DW_CFA_undefined:
3209 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3210 fprintf (f, "\t.cfi_undefined %lu\n", r);
3211 break;
3212
3213 case DW_CFA_same_value:
3214 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3215 fprintf (f, "\t.cfi_same_value %lu\n", r);
3216 break;
3217
3218 case DW_CFA_def_cfa:
3219 case DW_CFA_def_cfa_sf:
3220 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3221 fprintf (f, "\t.cfi_def_cfa %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3222 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3223 break;
3224
3225 case DW_CFA_def_cfa_register:
3226 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3227 fprintf (f, "\t.cfi_def_cfa_register %lu\n", r);
3228 break;
3229
3230 case DW_CFA_register:
3231 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3232 r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1);
3233 fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2);
3234 break;
3235
3236 case DW_CFA_def_cfa_offset:
3237 case DW_CFA_def_cfa_offset_sf:
3238 fprintf (f, "\t.cfi_def_cfa_offset "
3239 HOST_WIDE_INT_PRINT_DEC"\n",
3240 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3241 break;
3242
3243 case DW_CFA_remember_state:
3244 fprintf (f, "\t.cfi_remember_state\n");
3245 break;
3246 case DW_CFA_restore_state:
3247 fprintf (f, "\t.cfi_restore_state\n");
3248 break;
3249
3250 case DW_CFA_GNU_args_size:
3251 if (f == asm_out_file)
3252 {
3253 fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size);
3254 dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3255 if (flag_debug_asm)
3256 fprintf (f, "\t%s args_size "HOST_WIDE_INT_PRINT_DEC,
3257 ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset);
3258 fputc ('\n', f);
3259 }
3260 else
3261 {
3262 fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n",
3263 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3264 }
3265 break;
3266
3267 case DW_CFA_GNU_window_save:
3268 fprintf (f, "\t.cfi_window_save\n");
3269 break;
3270
3271 case DW_CFA_def_cfa_expression:
3272 if (f != asm_out_file)
3273 {
3274 fprintf (f, "\t.cfi_def_cfa_expression ...\n");
3275 break;
3276 }
3277 /* FALLTHRU */
3278 case DW_CFA_expression:
3279 if (f != asm_out_file)
3280 {
3281 fprintf (f, "\t.cfi_cfa_expression ...\n");
3282 break;
3283 }
3284 fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc);
3285 output_cfa_loc_raw (cfi);
3286 fputc ('\n', f);
3287 break;
3288
3289 default:
3290 gcc_unreachable ();
3291 }
3292}
3293
3294void
3295dwarf2out_emit_cfi (dw_cfi_ref cfi)
3296{
3297 if (dwarf2out_do_cfi_asm ())
3298 output_cfi_directive (asm_out_file, cfi);
3299}
948d330e 3300\f
647a1567 3301
7644b3c7
RH
3302/* Save the result of dwarf2out_do_frame across PCH.
3303 This variable is tri-state, with 0 unset, >0 true, <0 false. */
3304static GTY(()) signed char saved_do_cfi_asm = 0;
647a1567
RH
3305
3306/* Decide whether we want to emit frame unwind information for the current
3307 translation unit. */
3308
7644b3c7 3309bool
647a1567
RH
3310dwarf2out_do_frame (void)
3311{
3312 /* We want to emit correct CFA location expressions or lists, so we
3313 have to return true if we're going to output debug info, even if
3314 we're not going to output frame or unwind info. */
3315 if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG)
3316 return true;
3317
7644b3c7 3318 if (saved_do_cfi_asm > 0)
647a1567
RH
3319 return true;
3320
3321 if (targetm.debug_unwind_info () == UI_DWARF2)
3322 return true;
3323
3324 if ((flag_unwind_tables || flag_exceptions)
3325 && targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
3326 return true;
3327
3328 return false;
3329}
3330
3331/* Decide whether to emit frame unwind via assembler directives. */
3332
7644b3c7 3333bool
647a1567
RH
3334dwarf2out_do_cfi_asm (void)
3335{
3336 int enc;
3337
3338#ifdef MIPS_DEBUGGING_INFO
3339 return false;
3340#endif
7644b3c7
RH
3341
3342 if (saved_do_cfi_asm != 0)
3343 return saved_do_cfi_asm > 0;
3344
3345 /* Assume failure for a moment. */
3346 saved_do_cfi_asm = -1;
3347
647a1567
RH
3348 if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ())
3349 return false;
3350 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
3351 return false;
3352
3353 /* Make sure the personality encoding is one the assembler can support.
3354 In particular, aligned addresses can't be handled. */
3355 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1);
3356 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3357 return false;
3358 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0);
3359 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3360 return false;
3361
3362 /* If we can't get the assembler to emit only .debug_frame, and we don't need
3363 dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */
3364 if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE
3365 && !flag_unwind_tables && !flag_exceptions
3366 && targetm_common.except_unwind_info (&global_options) != UI_DWARF2)
3367 return false;
3368
7644b3c7
RH
3369 /* Success! */
3370 saved_do_cfi_asm = 1;
647a1567
RH
3371 return true;
3372}
3373
7644b3c7
RH
3374static bool
3375gate_dwarf2_frame (void)
3376{
3377#ifndef HAVE_prologue
3378 /* Targets which still implement the prologue in assembler text
3379 cannot use the generic dwarf2 unwinding. */
3380 return false;
3381#endif
3382
3383 /* ??? What to do for UI_TARGET unwinding? They might be able to benefit
3384 from the optimized shrink-wrapping annotations that we will compute.
3385 For now, only produce the CFI notes for dwarf2. */
3386 return dwarf2out_do_frame ();
3387}
3388
3389struct rtl_opt_pass pass_dwarf2_frame =
3390{
3391 {
3392 RTL_PASS,
3393 "dwarf2", /* name */
3394 gate_dwarf2_frame, /* gate */
3395 execute_dwarf2_frame, /* execute */
3396 NULL, /* sub */
3397 NULL, /* next */
3398 0, /* static_pass_number */
3399 TV_FINAL, /* tv_id */
3400 0, /* properties_required */
3401 0, /* properties_provided */
3402 0, /* properties_destroyed */
3403 0, /* todo_flags_start */
3404 0 /* todo_flags_finish */
3405 }
3406};
3407
647a1567 3408#include "gt-dwarf2cfi.h"