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647a1567 RH |
1 | /* Dwarf2 Call Frame Information helper routines. |
2 | Copyright (C) 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, | |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 | |
4 | Free Software Foundation, Inc. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "system.h" | |
24 | #include "coretypes.h" | |
25 | #include "tm.h" | |
26 | #include "version.h" | |
27 | #include "flags.h" | |
28 | #include "rtl.h" | |
29 | #include "function.h" | |
829bdd4b | 30 | #include "basic-block.h" |
647a1567 RH |
31 | #include "dwarf2.h" |
32 | #include "dwarf2out.h" | |
33 | #include "dwarf2asm.h" | |
34 | #include "ggc.h" | |
35 | #include "tm_p.h" | |
36 | #include "target.h" | |
37 | #include "common/common-target.h" | |
38 | #include "tree-pass.h" | |
39 | ||
40 | #include "except.h" /* expand_builtin_dwarf_sp_column */ | |
41 | #include "expr.h" /* init_return_column_size */ | |
42 | #include "regs.h" /* expand_builtin_init_dwarf_reg_sizes */ | |
43 | #include "output.h" /* asm_out_file */ | |
44 | #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */ | |
45 | ||
46 | ||
47 | /* ??? Poison these here until it can be done generically. They've been | |
48 | totally replaced in this file; make sure it stays that way. */ | |
49 | #undef DWARF2_UNWIND_INFO | |
50 | #undef DWARF2_FRAME_INFO | |
51 | #if (GCC_VERSION >= 3000) | |
52 | #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO | |
53 | #endif | |
54 | ||
55 | #ifndef INCOMING_RETURN_ADDR_RTX | |
56 | #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX) | |
57 | #endif | |
58 | ||
647a1567 RH |
59 | /* Maximum size (in bytes) of an artificially generated label. */ |
60 | #define MAX_ARTIFICIAL_LABEL_BYTES 30 | |
647a1567 | 61 | \f |
f17d3401 RH |
62 | /* A collected description of an entire row of the abstract CFI table. */ |
63 | typedef struct GTY(()) dw_cfi_row_struct | |
64 | { | |
65 | /* The expression that computes the CFA, expressed in two different ways. | |
66 | The CFA member for the simple cases, and the full CFI expression for | |
67 | the complex cases. The later will be a DW_CFA_cfa_expression. */ | |
68 | dw_cfa_location cfa; | |
69 | dw_cfi_ref cfa_cfi; | |
70 | ||
71 | /* The expressions for any register column that is saved. */ | |
72 | cfi_vec reg_save; | |
73 | ||
74 | /* The value of any DW_CFA_GNU_args_size. */ | |
75 | HOST_WIDE_INT args_size; | |
76 | } dw_cfi_row; | |
77 | ||
43215a89 RH |
78 | /* The caller's ORIG_REG is saved in SAVED_IN_REG. */ |
79 | typedef struct GTY(()) reg_saved_in_data_struct { | |
80 | rtx orig_reg; | |
81 | rtx saved_in_reg; | |
82 | } reg_saved_in_data; | |
83 | ||
84 | DEF_VEC_O (reg_saved_in_data); | |
85 | DEF_VEC_ALLOC_O (reg_saved_in_data, heap); | |
86 | ||
87 | /* Since we no longer have a proper CFG, we're going to create a facsimile | |
88 | of one on the fly while processing the frame-related insns. | |
89 | ||
829bdd4b RH |
90 | We create dw_trace_info structures for each extended basic block beginning |
91 | and ending at a "save point". Save points are labels, barriers, certain | |
92 | notes, and of course the beginning and end of the function. | |
43215a89 RH |
93 | |
94 | As we encounter control transfer insns, we propagate the "current" | |
829bdd4b RH |
95 | row state across the edges to the starts of traces. When checking is |
96 | enabled, we validate that we propagate the same data from all sources. | |
43215a89 RH |
97 | |
98 | All traces are members of the TRACE_INFO array, in the order in which | |
99 | they appear in the instruction stream. | |
100 | ||
829bdd4b RH |
101 | All save points are present in the TRACE_INDEX hash, mapping the insn |
102 | starting a trace to the dw_trace_info describing the trace. */ | |
43215a89 RH |
103 | |
104 | typedef struct | |
105 | { | |
829bdd4b RH |
106 | /* The insn that begins the trace. */ |
107 | rtx head; | |
43215a89 RH |
108 | |
109 | /* The row state at the beginning and end of the trace. */ | |
829bdd4b RH |
110 | dw_cfi_row *beg_row, *end_row; |
111 | ||
43215a89 RH |
112 | /* The following variables contain data used in interpreting frame related |
113 | expressions. These are not part of the "real" row state as defined by | |
114 | Dwarf, but it seems like they need to be propagated into a trace in case | |
115 | frame related expressions have been sunk. */ | |
116 | /* ??? This seems fragile. These variables are fragments of a larger | |
117 | expression. If we do not keep the entire expression together, we risk | |
118 | not being able to put it together properly. Consider forcing targets | |
119 | to generate self-contained expressions and dropping all of the magic | |
120 | interpretation code in this file. Or at least refusing to shrink wrap | |
121 | any frame related insn that doesn't contain a complete expression. */ | |
122 | ||
123 | /* The register used for saving registers to the stack, and its offset | |
124 | from the CFA. */ | |
125 | dw_cfa_location cfa_store; | |
126 | ||
127 | /* A temporary register holding an integral value used in adjusting SP | |
128 | or setting up the store_reg. The "offset" field holds the integer | |
129 | value, not an offset. */ | |
130 | dw_cfa_location cfa_temp; | |
131 | ||
132 | /* A set of registers saved in other registers. This is the inverse of | |
133 | the row->reg_save info, if the entry is a DW_CFA_register. This is | |
134 | implemented as a flat array because it normally contains zero or 1 | |
135 | entry, depending on the target. IA-64 is the big spender here, using | |
136 | a maximum of 5 entries. */ | |
137 | VEC(reg_saved_in_data, heap) *regs_saved_in_regs; | |
138 | ||
200e10dc RH |
139 | /* An identifier for this trace. Used only for debugging dumps. */ |
140 | unsigned id; | |
141 | ||
142 | /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */ | |
143 | bool switch_sections; | |
43215a89 RH |
144 | } dw_trace_info; |
145 | ||
146 | DEF_VEC_O (dw_trace_info); | |
147 | DEF_VEC_ALLOC_O (dw_trace_info, heap); | |
148 | ||
829bdd4b | 149 | typedef dw_trace_info *dw_trace_info_ref; |
43215a89 | 150 | |
829bdd4b RH |
151 | DEF_VEC_P (dw_trace_info_ref); |
152 | DEF_VEC_ALLOC_P (dw_trace_info_ref, heap); | |
43215a89 RH |
153 | |
154 | /* The variables making up the pseudo-cfg, as described above. */ | |
43215a89 | 155 | static VEC (dw_trace_info, heap) *trace_info; |
829bdd4b RH |
156 | static VEC (dw_trace_info_ref, heap) *trace_work_list; |
157 | static htab_t trace_index; | |
43215a89 | 158 | |
647a1567 RH |
159 | /* A vector of call frame insns for the CIE. */ |
160 | cfi_vec cie_cfi_vec; | |
161 | ||
f17d3401 RH |
162 | /* The state of the first row of the FDE table, which includes the |
163 | state provided by the CIE. */ | |
ce363ef2 | 164 | static GTY(()) dw_cfi_row *cie_cfi_row; |
f17d3401 | 165 | |
43215a89 RH |
166 | static GTY(()) reg_saved_in_data *cie_return_save; |
167 | ||
647a1567 RH |
168 | static GTY(()) unsigned long dwarf2out_cfi_label_num; |
169 | ||
bc5612ed | 170 | /* The insn after which a new CFI note should be emitted. */ |
141618e2 | 171 | static rtx add_cfi_insn; |
bc5612ed | 172 | |
3edb53aa RH |
173 | /* When non-null, add_cfi will add the CFI to this vector. */ |
174 | static cfi_vec *add_cfi_vec; | |
175 | ||
43215a89 RH |
176 | /* The current instruction trace. */ |
177 | static dw_trace_info *cur_trace; | |
178 | ||
179 | /* The current, i.e. most recently generated, row of the CFI table. */ | |
180 | static dw_cfi_row *cur_row; | |
181 | ||
43215a89 RH |
182 | /* We delay emitting a register save until either (a) we reach the end |
183 | of the prologue or (b) the register is clobbered. This clusters | |
184 | register saves so that there are fewer pc advances. */ | |
185 | ||
186 | typedef struct { | |
187 | rtx reg; | |
188 | rtx saved_reg; | |
189 | HOST_WIDE_INT cfa_offset; | |
190 | } queued_reg_save; | |
191 | ||
192 | DEF_VEC_O (queued_reg_save); | |
193 | DEF_VEC_ALLOC_O (queued_reg_save, heap); | |
194 | ||
195 | static VEC(queued_reg_save, heap) *queued_reg_saves; | |
196 | ||
197 | /* The (really) current value for DW_CFA_GNU_args_size. We delay actually | |
198 | emitting this data, i.e. updating CUR_ROW, without async unwind. */ | |
199 | static HOST_WIDE_INT queued_args_size; | |
200 | ||
bc5612ed BS |
201 | /* True if any CFI directives were emitted at the current insn. */ |
202 | static bool any_cfis_emitted; | |
4f42d714 RH |
203 | |
204 | /* Short-hand for commonly used register numbers. */ | |
205 | static unsigned dw_stack_pointer_regnum; | |
206 | static unsigned dw_frame_pointer_regnum; | |
647a1567 RH |
207 | \f |
208 | /* Hook used by __throw. */ | |
209 | ||
210 | rtx | |
211 | expand_builtin_dwarf_sp_column (void) | |
212 | { | |
4f42d714 | 213 | unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); |
647a1567 RH |
214 | return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1)); |
215 | } | |
216 | ||
217 | /* MEM is a memory reference for the register size table, each element of | |
218 | which has mode MODE. Initialize column C as a return address column. */ | |
219 | ||
220 | static void | |
221 | init_return_column_size (enum machine_mode mode, rtx mem, unsigned int c) | |
222 | { | |
223 | HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode); | |
224 | HOST_WIDE_INT size = GET_MODE_SIZE (Pmode); | |
225 | emit_move_insn (adjust_address (mem, mode, offset), GEN_INT (size)); | |
226 | } | |
227 | ||
228 | /* Generate code to initialize the register size table. */ | |
229 | ||
230 | void | |
231 | expand_builtin_init_dwarf_reg_sizes (tree address) | |
232 | { | |
233 | unsigned int i; | |
234 | enum machine_mode mode = TYPE_MODE (char_type_node); | |
235 | rtx addr = expand_normal (address); | |
236 | rtx mem = gen_rtx_MEM (BLKmode, addr); | |
237 | bool wrote_return_column = false; | |
238 | ||
239 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
240 | { | |
4f42d714 RH |
241 | unsigned int dnum = DWARF_FRAME_REGNUM (i); |
242 | unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); | |
647a1567 RH |
243 | |
244 | if (rnum < DWARF_FRAME_REGISTERS) | |
245 | { | |
246 | HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode); | |
247 | enum machine_mode save_mode = reg_raw_mode[i]; | |
248 | HOST_WIDE_INT size; | |
249 | ||
250 | if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode)) | |
251 | save_mode = choose_hard_reg_mode (i, 1, true); | |
4f42d714 | 252 | if (dnum == DWARF_FRAME_RETURN_COLUMN) |
647a1567 RH |
253 | { |
254 | if (save_mode == VOIDmode) | |
255 | continue; | |
256 | wrote_return_column = true; | |
257 | } | |
258 | size = GET_MODE_SIZE (save_mode); | |
259 | if (offset < 0) | |
260 | continue; | |
261 | ||
262 | emit_move_insn (adjust_address (mem, mode, offset), | |
263 | gen_int_mode (size, mode)); | |
264 | } | |
265 | } | |
266 | ||
267 | if (!wrote_return_column) | |
268 | init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); | |
269 | ||
270 | #ifdef DWARF_ALT_FRAME_RETURN_COLUMN | |
271 | init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN); | |
272 | #endif | |
273 | ||
274 | targetm.init_dwarf_reg_sizes_extra (address); | |
275 | } | |
276 | ||
829bdd4b RH |
277 | \f |
278 | static hashval_t | |
279 | dw_trace_info_hash (const void *ptr) | |
280 | { | |
281 | const dw_trace_info *ti = (const dw_trace_info *) ptr; | |
282 | return INSN_UID (ti->head); | |
283 | } | |
284 | ||
285 | static int | |
286 | dw_trace_info_eq (const void *ptr_a, const void *ptr_b) | |
287 | { | |
288 | const dw_trace_info *a = (const dw_trace_info *) ptr_a; | |
289 | const dw_trace_info *b = (const dw_trace_info *) ptr_b; | |
290 | return a->head == b->head; | |
291 | } | |
292 | ||
829bdd4b RH |
293 | static dw_trace_info * |
294 | get_trace_info (rtx insn) | |
295 | { | |
296 | dw_trace_info dummy; | |
297 | dummy.head = insn; | |
298 | return (dw_trace_info *) | |
299 | htab_find_with_hash (trace_index, &dummy, INSN_UID (insn)); | |
300 | } | |
301 | ||
302 | static bool | |
303 | save_point_p (rtx insn) | |
304 | { | |
305 | /* Labels, except those that are really jump tables. */ | |
306 | if (LABEL_P (insn)) | |
307 | return inside_basic_block_p (insn); | |
308 | ||
309 | /* We split traces at the prologue/epilogue notes because those | |
310 | are points at which the unwind info is usually stable. This | |
311 | makes it easier to find spots with identical unwind info so | |
312 | that we can use remember/restore_state opcodes. */ | |
313 | if (NOTE_P (insn)) | |
314 | switch (NOTE_KIND (insn)) | |
315 | { | |
316 | case NOTE_INSN_PROLOGUE_END: | |
317 | case NOTE_INSN_EPILOGUE_BEG: | |
318 | return true; | |
319 | } | |
320 | ||
321 | return false; | |
322 | } | |
323 | ||
647a1567 RH |
324 | /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */ |
325 | ||
326 | static inline HOST_WIDE_INT | |
327 | div_data_align (HOST_WIDE_INT off) | |
328 | { | |
329 | HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT; | |
330 | gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off); | |
331 | return r; | |
332 | } | |
333 | ||
334 | /* Return true if we need a signed version of a given opcode | |
335 | (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */ | |
336 | ||
337 | static inline bool | |
338 | need_data_align_sf_opcode (HOST_WIDE_INT off) | |
339 | { | |
340 | return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0; | |
341 | } | |
342 | ||
343 | /* Return a pointer to a newly allocated Call Frame Instruction. */ | |
344 | ||
345 | static inline dw_cfi_ref | |
346 | new_cfi (void) | |
347 | { | |
348 | dw_cfi_ref cfi = ggc_alloc_dw_cfi_node (); | |
349 | ||
350 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0; | |
351 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0; | |
352 | ||
353 | return cfi; | |
354 | } | |
355 | ||
f17d3401 RH |
356 | /* Return a newly allocated CFI row, with no defined data. */ |
357 | ||
ce363ef2 | 358 | static dw_cfi_row * |
f17d3401 RH |
359 | new_cfi_row (void) |
360 | { | |
ce363ef2 | 361 | dw_cfi_row *row = ggc_alloc_cleared_dw_cfi_row (); |
f17d3401 RH |
362 | |
363 | row->cfa.reg = INVALID_REGNUM; | |
364 | ||
365 | return row; | |
366 | } | |
367 | ||
368 | /* Return a copy of an existing CFI row. */ | |
369 | ||
ce363ef2 RH |
370 | static dw_cfi_row * |
371 | copy_cfi_row (dw_cfi_row *src) | |
f17d3401 | 372 | { |
ce363ef2 | 373 | dw_cfi_row *dst = ggc_alloc_dw_cfi_row (); |
f17d3401 RH |
374 | |
375 | *dst = *src; | |
376 | dst->reg_save = VEC_copy (dw_cfi_ref, gc, src->reg_save); | |
377 | ||
378 | return dst; | |
379 | } | |
380 | ||
89e25f95 | 381 | /* Generate a new label for the CFI info to refer to. */ |
647a1567 RH |
382 | |
383 | static char * | |
89e25f95 | 384 | dwarf2out_cfi_label (void) |
647a1567 | 385 | { |
89e25f95 BS |
386 | int num = dwarf2out_cfi_label_num++; |
387 | char label[20]; | |
647a1567 | 388 | |
89e25f95 | 389 | ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num); |
647a1567 | 390 | |
89e25f95 | 391 | return xstrdup (label); |
647a1567 RH |
392 | } |
393 | ||
3edb53aa | 394 | /* Add CFI either to the current insn stream or to a vector, or both. */ |
647a1567 RH |
395 | |
396 | static void | |
3edb53aa | 397 | add_cfi (dw_cfi_ref cfi) |
647a1567 | 398 | { |
89e25f95 | 399 | any_cfis_emitted = true; |
141618e2 RH |
400 | |
401 | if (add_cfi_insn != NULL) | |
647a1567 | 402 | { |
141618e2 RH |
403 | add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn); |
404 | NOTE_CFI (add_cfi_insn) = cfi; | |
647a1567 | 405 | } |
141618e2 | 406 | |
3edb53aa RH |
407 | if (add_cfi_vec != NULL) |
408 | VEC_safe_push (dw_cfi_ref, gc, *add_cfi_vec, cfi); | |
647a1567 RH |
409 | } |
410 | ||
57e16c96 RH |
411 | static void |
412 | add_cfi_args_size (HOST_WIDE_INT size) | |
413 | { | |
414 | dw_cfi_ref cfi = new_cfi (); | |
415 | ||
416 | cfi->dw_cfi_opc = DW_CFA_GNU_args_size; | |
417 | cfi->dw_cfi_oprnd1.dw_cfi_offset = size; | |
418 | ||
419 | add_cfi (cfi); | |
420 | } | |
421 | ||
422 | static void | |
423 | add_cfi_restore (unsigned reg) | |
424 | { | |
425 | dw_cfi_ref cfi = new_cfi (); | |
426 | ||
427 | cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore); | |
428 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
429 | ||
430 | add_cfi (cfi); | |
431 | } | |
432 | ||
f1a0e830 RH |
433 | /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating |
434 | that the register column is no longer saved. */ | |
435 | ||
436 | static void | |
ce363ef2 | 437 | update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi) |
f1a0e830 RH |
438 | { |
439 | if (VEC_length (dw_cfi_ref, row->reg_save) <= column) | |
440 | VEC_safe_grow_cleared (dw_cfi_ref, gc, row->reg_save, column + 1); | |
441 | VEC_replace (dw_cfi_ref, row->reg_save, column, cfi); | |
442 | } | |
443 | ||
647a1567 RH |
444 | /* This function fills in aa dw_cfa_location structure from a dwarf location |
445 | descriptor sequence. */ | |
446 | ||
447 | static void | |
448 | get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_struct *loc) | |
449 | { | |
450 | struct dw_loc_descr_struct *ptr; | |
451 | cfa->offset = 0; | |
452 | cfa->base_offset = 0; | |
453 | cfa->indirect = 0; | |
454 | cfa->reg = -1; | |
455 | ||
456 | for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next) | |
457 | { | |
458 | enum dwarf_location_atom op = ptr->dw_loc_opc; | |
459 | ||
460 | switch (op) | |
461 | { | |
462 | case DW_OP_reg0: | |
463 | case DW_OP_reg1: | |
464 | case DW_OP_reg2: | |
465 | case DW_OP_reg3: | |
466 | case DW_OP_reg4: | |
467 | case DW_OP_reg5: | |
468 | case DW_OP_reg6: | |
469 | case DW_OP_reg7: | |
470 | case DW_OP_reg8: | |
471 | case DW_OP_reg9: | |
472 | case DW_OP_reg10: | |
473 | case DW_OP_reg11: | |
474 | case DW_OP_reg12: | |
475 | case DW_OP_reg13: | |
476 | case DW_OP_reg14: | |
477 | case DW_OP_reg15: | |
478 | case DW_OP_reg16: | |
479 | case DW_OP_reg17: | |
480 | case DW_OP_reg18: | |
481 | case DW_OP_reg19: | |
482 | case DW_OP_reg20: | |
483 | case DW_OP_reg21: | |
484 | case DW_OP_reg22: | |
485 | case DW_OP_reg23: | |
486 | case DW_OP_reg24: | |
487 | case DW_OP_reg25: | |
488 | case DW_OP_reg26: | |
489 | case DW_OP_reg27: | |
490 | case DW_OP_reg28: | |
491 | case DW_OP_reg29: | |
492 | case DW_OP_reg30: | |
493 | case DW_OP_reg31: | |
494 | cfa->reg = op - DW_OP_reg0; | |
495 | break; | |
496 | case DW_OP_regx: | |
497 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
498 | break; | |
499 | case DW_OP_breg0: | |
500 | case DW_OP_breg1: | |
501 | case DW_OP_breg2: | |
502 | case DW_OP_breg3: | |
503 | case DW_OP_breg4: | |
504 | case DW_OP_breg5: | |
505 | case DW_OP_breg6: | |
506 | case DW_OP_breg7: | |
507 | case DW_OP_breg8: | |
508 | case DW_OP_breg9: | |
509 | case DW_OP_breg10: | |
510 | case DW_OP_breg11: | |
511 | case DW_OP_breg12: | |
512 | case DW_OP_breg13: | |
513 | case DW_OP_breg14: | |
514 | case DW_OP_breg15: | |
515 | case DW_OP_breg16: | |
516 | case DW_OP_breg17: | |
517 | case DW_OP_breg18: | |
518 | case DW_OP_breg19: | |
519 | case DW_OP_breg20: | |
520 | case DW_OP_breg21: | |
521 | case DW_OP_breg22: | |
522 | case DW_OP_breg23: | |
523 | case DW_OP_breg24: | |
524 | case DW_OP_breg25: | |
525 | case DW_OP_breg26: | |
526 | case DW_OP_breg27: | |
527 | case DW_OP_breg28: | |
528 | case DW_OP_breg29: | |
529 | case DW_OP_breg30: | |
530 | case DW_OP_breg31: | |
531 | cfa->reg = op - DW_OP_breg0; | |
532 | cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int; | |
533 | break; | |
534 | case DW_OP_bregx: | |
535 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
536 | cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int; | |
537 | break; | |
538 | case DW_OP_deref: | |
539 | cfa->indirect = 1; | |
540 | break; | |
541 | case DW_OP_plus_uconst: | |
542 | cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned; | |
543 | break; | |
544 | default: | |
545 | gcc_unreachable (); | |
546 | } | |
547 | } | |
548 | } | |
549 | ||
4a8ee122 RH |
550 | /* Find the previous value for the CFA, iteratively. CFI is the opcode |
551 | to interpret, *LOC will be updated as necessary, *REMEMBER is used for | |
552 | one level of remember/restore state processing. */ | |
647a1567 RH |
553 | |
554 | void | |
555 | lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember) | |
556 | { | |
557 | switch (cfi->dw_cfi_opc) | |
558 | { | |
559 | case DW_CFA_def_cfa_offset: | |
560 | case DW_CFA_def_cfa_offset_sf: | |
561 | loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset; | |
562 | break; | |
563 | case DW_CFA_def_cfa_register: | |
564 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
565 | break; | |
566 | case DW_CFA_def_cfa: | |
567 | case DW_CFA_def_cfa_sf: | |
568 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
569 | loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset; | |
570 | break; | |
571 | case DW_CFA_def_cfa_expression: | |
572 | get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc); | |
573 | break; | |
574 | ||
575 | case DW_CFA_remember_state: | |
576 | gcc_assert (!remember->in_use); | |
577 | *remember = *loc; | |
578 | remember->in_use = 1; | |
579 | break; | |
580 | case DW_CFA_restore_state: | |
581 | gcc_assert (remember->in_use); | |
582 | *loc = *remember; | |
583 | remember->in_use = 0; | |
584 | break; | |
585 | ||
586 | default: | |
587 | break; | |
588 | } | |
589 | } | |
590 | ||
647a1567 RH |
591 | /* Determine if two dw_cfa_location structures define the same data. */ |
592 | ||
593 | bool | |
594 | cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2) | |
595 | { | |
596 | return (loc1->reg == loc2->reg | |
597 | && loc1->offset == loc2->offset | |
598 | && loc1->indirect == loc2->indirect | |
599 | && (loc1->indirect == 0 | |
600 | || loc1->base_offset == loc2->base_offset)); | |
601 | } | |
602 | ||
57e16c96 | 603 | /* Determine if two CFI operands are identical. */ |
647a1567 | 604 | |
57e16c96 RH |
605 | static bool |
606 | cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b) | |
647a1567 | 607 | { |
57e16c96 RH |
608 | switch (t) |
609 | { | |
610 | case dw_cfi_oprnd_unused: | |
611 | return true; | |
612 | case dw_cfi_oprnd_reg_num: | |
613 | return a->dw_cfi_reg_num == b->dw_cfi_reg_num; | |
614 | case dw_cfi_oprnd_offset: | |
615 | return a->dw_cfi_offset == b->dw_cfi_offset; | |
616 | case dw_cfi_oprnd_addr: | |
617 | return (a->dw_cfi_addr == b->dw_cfi_addr | |
618 | || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0); | |
619 | case dw_cfi_oprnd_loc: | |
620 | return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc); | |
621 | } | |
622 | gcc_unreachable (); | |
623 | } | |
647a1567 | 624 | |
57e16c96 RH |
625 | /* Determine if two CFI entries are identical. */ |
626 | ||
627 | static bool | |
628 | cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b) | |
629 | { | |
630 | enum dwarf_call_frame_info opc; | |
631 | ||
632 | /* Make things easier for our callers, including missing operands. */ | |
633 | if (a == b) | |
634 | return true; | |
635 | if (a == NULL || b == NULL) | |
636 | return false; | |
637 | ||
638 | /* Obviously, the opcodes must match. */ | |
639 | opc = a->dw_cfi_opc; | |
640 | if (opc != b->dw_cfi_opc) | |
641 | return false; | |
642 | ||
643 | /* Compare the two operands, re-using the type of the operands as | |
644 | already exposed elsewhere. */ | |
645 | return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc), | |
646 | &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1) | |
647 | && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc), | |
648 | &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2)); | |
649 | } | |
650 | ||
829bdd4b RH |
651 | /* Determine if two CFI_ROW structures are identical. */ |
652 | ||
653 | static bool | |
654 | cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b) | |
655 | { | |
656 | size_t i, n_a, n_b, n_max; | |
657 | ||
658 | if (a->cfa_cfi) | |
659 | { | |
660 | if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi)) | |
661 | return false; | |
662 | } | |
663 | else if (!cfa_equal_p (&a->cfa, &b->cfa)) | |
664 | return false; | |
665 | ||
2edb462e RH |
666 | /* Logic suggests that we compare args_size here. However, if |
667 | EXIT_IGNORE_STACK we don't bother tracking the args_size after | |
668 | the last time it really matters within the function. This does | |
669 | in fact lead to paths with differing arg_size, but in cases for | |
670 | which it doesn't matter. */ | |
671 | /* ??? If we really want to sanity check the output of the optimizers, | |
672 | find a way to backtrack from epilogues to the last EH site. This | |
673 | would allow us to distinguish regions with garbage args_size and | |
674 | regions where paths ought to agree. */ | |
829bdd4b RH |
675 | |
676 | n_a = VEC_length (dw_cfi_ref, a->reg_save); | |
677 | n_b = VEC_length (dw_cfi_ref, b->reg_save); | |
678 | n_max = MAX (n_a, n_b); | |
679 | ||
680 | for (i = 0; i < n_max; ++i) | |
681 | { | |
682 | dw_cfi_ref r_a = NULL, r_b = NULL; | |
683 | ||
684 | if (i < n_a) | |
685 | r_a = VEC_index (dw_cfi_ref, a->reg_save, i); | |
686 | if (i < n_b) | |
687 | r_b = VEC_index (dw_cfi_ref, b->reg_save, i); | |
688 | ||
689 | if (!cfi_equal_p (r_a, r_b)) | |
690 | return false; | |
691 | } | |
692 | ||
693 | return true; | |
694 | } | |
695 | ||
57e16c96 RH |
696 | /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining |
697 | what opcode to emit. Returns the CFI opcode to effect the change, or | |
698 | NULL if NEW_CFA == OLD_CFA. */ | |
699 | ||
700 | static dw_cfi_ref | |
701 | def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa) | |
702 | { | |
703 | dw_cfi_ref cfi; | |
647a1567 | 704 | |
647a1567 | 705 | /* If nothing changed, no need to issue any call frame instructions. */ |
57e16c96 RH |
706 | if (cfa_equal_p (old_cfa, new_cfa)) |
707 | return NULL; | |
647a1567 RH |
708 | |
709 | cfi = new_cfi (); | |
710 | ||
57e16c96 | 711 | if (new_cfa->reg == old_cfa->reg && !new_cfa->indirect && !old_cfa->indirect) |
647a1567 RH |
712 | { |
713 | /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating | |
714 | the CFA register did not change but the offset did. The data | |
715 | factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or | |
716 | in the assembler via the .cfi_def_cfa_offset directive. */ | |
57e16c96 | 717 | if (new_cfa->offset < 0) |
647a1567 RH |
718 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf; |
719 | else | |
720 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset; | |
57e16c96 | 721 | cfi->dw_cfi_oprnd1.dw_cfi_offset = new_cfa->offset; |
647a1567 RH |
722 | } |
723 | ||
724 | #ifndef MIPS_DEBUGGING_INFO /* SGI dbx thinks this means no offset. */ | |
57e16c96 RH |
725 | else if (new_cfa->offset == old_cfa->offset |
726 | && old_cfa->reg != INVALID_REGNUM | |
727 | && !new_cfa->indirect | |
728 | && !old_cfa->indirect) | |
647a1567 RH |
729 | { |
730 | /* Construct a "DW_CFA_def_cfa_register <register>" instruction, | |
731 | indicating the CFA register has changed to <register> but the | |
732 | offset has not changed. */ | |
733 | cfi->dw_cfi_opc = DW_CFA_def_cfa_register; | |
57e16c96 | 734 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
647a1567 RH |
735 | } |
736 | #endif | |
737 | ||
57e16c96 | 738 | else if (new_cfa->indirect == 0) |
647a1567 RH |
739 | { |
740 | /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction, | |
741 | indicating the CFA register has changed to <register> with | |
742 | the specified offset. The data factoring for DW_CFA_def_cfa_sf | |
743 | happens in output_cfi, or in the assembler via the .cfi_def_cfa | |
744 | directive. */ | |
57e16c96 | 745 | if (new_cfa->offset < 0) |
647a1567 RH |
746 | cfi->dw_cfi_opc = DW_CFA_def_cfa_sf; |
747 | else | |
748 | cfi->dw_cfi_opc = DW_CFA_def_cfa; | |
57e16c96 RH |
749 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
750 | cfi->dw_cfi_oprnd2.dw_cfi_offset = new_cfa->offset; | |
647a1567 RH |
751 | } |
752 | else | |
753 | { | |
754 | /* Construct a DW_CFA_def_cfa_expression instruction to | |
755 | calculate the CFA using a full location expression since no | |
756 | register-offset pair is available. */ | |
757 | struct dw_loc_descr_struct *loc_list; | |
758 | ||
759 | cfi->dw_cfi_opc = DW_CFA_def_cfa_expression; | |
57e16c96 | 760 | loc_list = build_cfa_loc (new_cfa, 0); |
647a1567 RH |
761 | cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list; |
762 | } | |
763 | ||
57e16c96 RH |
764 | return cfi; |
765 | } | |
766 | ||
767 | /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */ | |
768 | ||
769 | static void | |
770 | def_cfa_1 (dw_cfa_location *new_cfa) | |
771 | { | |
772 | dw_cfi_ref cfi; | |
773 | ||
43215a89 RH |
774 | if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0) |
775 | cur_trace->cfa_store.offset = new_cfa->offset; | |
57e16c96 RH |
776 | |
777 | cfi = def_cfa_0 (&cur_row->cfa, new_cfa); | |
778 | if (cfi) | |
779 | { | |
780 | cur_row->cfa = *new_cfa; | |
781 | if (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression) | |
782 | cur_row->cfa_cfi = cfi; | |
783 | ||
784 | add_cfi (cfi); | |
785 | } | |
647a1567 RH |
786 | } |
787 | ||
788 | /* Add the CFI for saving a register. REG is the CFA column number. | |
647a1567 RH |
789 | If SREG is -1, the register is saved at OFFSET from the CFA; |
790 | otherwise it is saved in SREG. */ | |
791 | ||
792 | static void | |
3edb53aa | 793 | reg_save (unsigned int reg, unsigned int sreg, HOST_WIDE_INT offset) |
647a1567 | 794 | { |
3edb53aa | 795 | dw_fde_ref fde = cfun ? cfun->fde : NULL; |
647a1567 | 796 | dw_cfi_ref cfi = new_cfi (); |
647a1567 RH |
797 | |
798 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
799 | ||
800 | /* When stack is aligned, store REG using DW_CFA_expression with FP. */ | |
801 | if (fde | |
802 | && fde->stack_realign | |
803 | && sreg == INVALID_REGNUM) | |
804 | { | |
805 | cfi->dw_cfi_opc = DW_CFA_expression; | |
806 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
807 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
f17d3401 RH |
808 | = build_cfa_aligned_loc (&cur_row->cfa, offset, |
809 | fde->stack_realignment); | |
647a1567 RH |
810 | } |
811 | else if (sreg == INVALID_REGNUM) | |
812 | { | |
813 | if (need_data_align_sf_opcode (offset)) | |
814 | cfi->dw_cfi_opc = DW_CFA_offset_extended_sf; | |
815 | else if (reg & ~0x3f) | |
816 | cfi->dw_cfi_opc = DW_CFA_offset_extended; | |
817 | else | |
818 | cfi->dw_cfi_opc = DW_CFA_offset; | |
819 | cfi->dw_cfi_oprnd2.dw_cfi_offset = offset; | |
820 | } | |
821 | else if (sreg == reg) | |
f1a0e830 RH |
822 | { |
823 | /* While we could emit something like DW_CFA_same_value or | |
824 | DW_CFA_restore, we never expect to see something like that | |
825 | in a prologue. This is more likely to be a bug. A backend | |
826 | can always bypass this by using REG_CFA_RESTORE directly. */ | |
827 | gcc_unreachable (); | |
828 | } | |
647a1567 RH |
829 | else |
830 | { | |
831 | cfi->dw_cfi_opc = DW_CFA_register; | |
832 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg; | |
833 | } | |
834 | ||
3edb53aa | 835 | add_cfi (cfi); |
f1a0e830 | 836 | update_row_reg_save (cur_row, reg, cfi); |
647a1567 RH |
837 | } |
838 | ||
647a1567 RH |
839 | /* Given a SET, calculate the amount of stack adjustment it |
840 | contains. */ | |
841 | ||
842 | static HOST_WIDE_INT | |
843 | stack_adjust_offset (const_rtx pattern, HOST_WIDE_INT cur_args_size, | |
844 | HOST_WIDE_INT cur_offset) | |
845 | { | |
846 | const_rtx src = SET_SRC (pattern); | |
847 | const_rtx dest = SET_DEST (pattern); | |
848 | HOST_WIDE_INT offset = 0; | |
849 | enum rtx_code code; | |
850 | ||
851 | if (dest == stack_pointer_rtx) | |
852 | { | |
853 | code = GET_CODE (src); | |
854 | ||
855 | /* Assume (set (reg sp) (reg whatever)) sets args_size | |
856 | level to 0. */ | |
857 | if (code == REG && src != stack_pointer_rtx) | |
858 | { | |
859 | offset = -cur_args_size; | |
860 | #ifndef STACK_GROWS_DOWNWARD | |
861 | offset = -offset; | |
862 | #endif | |
863 | return offset - cur_offset; | |
864 | } | |
865 | ||
866 | if (! (code == PLUS || code == MINUS) | |
867 | || XEXP (src, 0) != stack_pointer_rtx | |
868 | || !CONST_INT_P (XEXP (src, 1))) | |
869 | return 0; | |
870 | ||
871 | /* (set (reg sp) (plus (reg sp) (const_int))) */ | |
872 | offset = INTVAL (XEXP (src, 1)); | |
873 | if (code == PLUS) | |
874 | offset = -offset; | |
875 | return offset; | |
876 | } | |
877 | ||
878 | if (MEM_P (src) && !MEM_P (dest)) | |
879 | dest = src; | |
880 | if (MEM_P (dest)) | |
881 | { | |
882 | /* (set (mem (pre_dec (reg sp))) (foo)) */ | |
883 | src = XEXP (dest, 0); | |
884 | code = GET_CODE (src); | |
885 | ||
886 | switch (code) | |
887 | { | |
888 | case PRE_MODIFY: | |
889 | case POST_MODIFY: | |
890 | if (XEXP (src, 0) == stack_pointer_rtx) | |
891 | { | |
892 | rtx val = XEXP (XEXP (src, 1), 1); | |
893 | /* We handle only adjustments by constant amount. */ | |
894 | gcc_assert (GET_CODE (XEXP (src, 1)) == PLUS | |
895 | && CONST_INT_P (val)); | |
896 | offset = -INTVAL (val); | |
897 | break; | |
898 | } | |
899 | return 0; | |
900 | ||
901 | case PRE_DEC: | |
902 | case POST_DEC: | |
903 | if (XEXP (src, 0) == stack_pointer_rtx) | |
904 | { | |
905 | offset = GET_MODE_SIZE (GET_MODE (dest)); | |
906 | break; | |
907 | } | |
908 | return 0; | |
909 | ||
910 | case PRE_INC: | |
911 | case POST_INC: | |
912 | if (XEXP (src, 0) == stack_pointer_rtx) | |
913 | { | |
914 | offset = -GET_MODE_SIZE (GET_MODE (dest)); | |
915 | break; | |
916 | } | |
917 | return 0; | |
918 | ||
919 | default: | |
920 | return 0; | |
921 | } | |
922 | } | |
923 | else | |
924 | return 0; | |
925 | ||
926 | return offset; | |
927 | } | |
928 | ||
647a1567 RH |
929 | /* Add a CFI to update the running total of the size of arguments |
930 | pushed onto the stack. */ | |
931 | ||
932 | static void | |
89e25f95 | 933 | dwarf2out_args_size (HOST_WIDE_INT size) |
647a1567 | 934 | { |
f17d3401 | 935 | if (size == cur_row->args_size) |
647a1567 RH |
936 | return; |
937 | ||
f17d3401 | 938 | cur_row->args_size = size; |
57e16c96 | 939 | add_cfi_args_size (size); |
647a1567 RH |
940 | } |
941 | ||
942 | /* Record a stack adjustment of OFFSET bytes. */ | |
943 | ||
944 | static void | |
89e25f95 | 945 | dwarf2out_stack_adjust (HOST_WIDE_INT offset) |
647a1567 | 946 | { |
f17d3401 RH |
947 | dw_cfa_location loc = cur_row->cfa; |
948 | ||
949 | if (loc.reg == dw_stack_pointer_regnum) | |
950 | loc.offset += offset; | |
647a1567 | 951 | |
43215a89 RH |
952 | if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum) |
953 | cur_trace->cfa_store.offset += offset; | |
954 | ||
f17d3401 RH |
955 | /* ??? The assumption seems to be that if A_O_A, the only CFA adjustments |
956 | involving the stack pointer are inside the prologue and marked as | |
957 | RTX_FRAME_RELATED_P. That said, should we not verify this assumption | |
958 | by *asserting* A_O_A at this point? Why else would we have a change | |
959 | to the stack pointer? */ | |
647a1567 RH |
960 | if (ACCUMULATE_OUTGOING_ARGS) |
961 | return; | |
962 | ||
981dc735 RH |
963 | #ifndef STACK_GROWS_DOWNWARD |
964 | offset = -offset; | |
965 | #endif | |
966 | ||
967 | queued_args_size += offset; | |
968 | if (queued_args_size < 0) | |
969 | queued_args_size = 0; | |
970 | ||
f17d3401 | 971 | def_cfa_1 (&loc); |
647a1567 | 972 | if (flag_asynchronous_unwind_tables) |
43215a89 | 973 | dwarf2out_args_size (queued_args_size); |
647a1567 RH |
974 | } |
975 | ||
976 | /* Check INSN to see if it looks like a push or a stack adjustment, and | |
977 | make a note of it if it does. EH uses this information to find out | |
978 | how much extra space it needs to pop off the stack. */ | |
979 | ||
980 | static void | |
981 | dwarf2out_notice_stack_adjust (rtx insn, bool after_p) | |
982 | { | |
983 | HOST_WIDE_INT offset; | |
647a1567 RH |
984 | int i; |
985 | ||
986 | /* Don't handle epilogues at all. Certainly it would be wrong to do so | |
987 | with this function. Proper support would require all frame-related | |
988 | insns to be marked, and to be able to handle saving state around | |
989 | epilogues textually in the middle of the function. */ | |
990 | if (prologue_epilogue_contains (insn)) | |
991 | return; | |
992 | ||
993 | /* If INSN is an instruction from target of an annulled branch, the | |
994 | effects are for the target only and so current argument size | |
995 | shouldn't change at all. */ | |
996 | if (final_sequence | |
997 | && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)) | |
998 | && INSN_FROM_TARGET_P (insn)) | |
999 | return; | |
1000 | ||
1001 | /* If only calls can throw, and we have a frame pointer, | |
1002 | save up adjustments until we see the CALL_INSN. */ | |
f17d3401 RH |
1003 | if (!flag_asynchronous_unwind_tables |
1004 | && cur_row->cfa.reg != dw_stack_pointer_regnum) | |
647a1567 RH |
1005 | { |
1006 | if (CALL_P (insn) && !after_p) | |
1007 | { | |
1008 | /* Extract the size of the args from the CALL rtx itself. */ | |
1009 | insn = PATTERN (insn); | |
1010 | if (GET_CODE (insn) == PARALLEL) | |
1011 | insn = XVECEXP (insn, 0, 0); | |
1012 | if (GET_CODE (insn) == SET) | |
1013 | insn = SET_SRC (insn); | |
1014 | gcc_assert (GET_CODE (insn) == CALL); | |
981dc735 | 1015 | dwarf2out_args_size (INTVAL (XEXP (insn, 1))); |
647a1567 RH |
1016 | } |
1017 | return; | |
1018 | } | |
1019 | ||
1020 | if (CALL_P (insn) && !after_p) | |
1021 | { | |
1022 | if (!flag_asynchronous_unwind_tables) | |
43215a89 | 1023 | dwarf2out_args_size (queued_args_size); |
647a1567 RH |
1024 | return; |
1025 | } | |
1026 | else if (BARRIER_P (insn)) | |
829bdd4b | 1027 | return; |
647a1567 | 1028 | else if (GET_CODE (PATTERN (insn)) == SET) |
43215a89 | 1029 | offset = stack_adjust_offset (PATTERN (insn), queued_args_size, 0); |
647a1567 RH |
1030 | else if (GET_CODE (PATTERN (insn)) == PARALLEL |
1031 | || GET_CODE (PATTERN (insn)) == SEQUENCE) | |
1032 | { | |
1033 | /* There may be stack adjustments inside compound insns. Search | |
1034 | for them. */ | |
1035 | for (offset = 0, i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
1036 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) | |
1037 | offset += stack_adjust_offset (XVECEXP (PATTERN (insn), 0, i), | |
43215a89 | 1038 | queued_args_size, offset); |
647a1567 RH |
1039 | } |
1040 | else | |
1041 | return; | |
1042 | ||
1043 | if (offset == 0) | |
1044 | return; | |
1045 | ||
89e25f95 | 1046 | dwarf2out_stack_adjust (offset); |
647a1567 RH |
1047 | } |
1048 | ||
7263c6d7 | 1049 | /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */ |
4f42d714 RH |
1050 | /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is |
1051 | used in places where rtl is prohibited. */ | |
7263c6d7 RH |
1052 | |
1053 | static inline unsigned | |
1054 | dwf_regno (const_rtx reg) | |
1055 | { | |
4f42d714 | 1056 | return DWARF_FRAME_REGNUM (REGNO (reg)); |
7263c6d7 RH |
1057 | } |
1058 | ||
647a1567 RH |
1059 | /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */ |
1060 | ||
1061 | static bool | |
1062 | compare_reg_or_pc (rtx x, rtx y) | |
1063 | { | |
1064 | if (REG_P (x) && REG_P (y)) | |
1065 | return REGNO (x) == REGNO (y); | |
1066 | return x == y; | |
1067 | } | |
1068 | ||
1069 | /* Record SRC as being saved in DEST. DEST may be null to delete an | |
1070 | existing entry. SRC may be a register or PC_RTX. */ | |
1071 | ||
1072 | static void | |
1073 | record_reg_saved_in_reg (rtx dest, rtx src) | |
1074 | { | |
1075 | reg_saved_in_data *elt; | |
1076 | size_t i; | |
1077 | ||
43215a89 | 1078 | FOR_EACH_VEC_ELT (reg_saved_in_data, cur_trace->regs_saved_in_regs, i, elt) |
647a1567 RH |
1079 | if (compare_reg_or_pc (elt->orig_reg, src)) |
1080 | { | |
1081 | if (dest == NULL) | |
43215a89 RH |
1082 | VEC_unordered_remove (reg_saved_in_data, |
1083 | cur_trace->regs_saved_in_regs, i); | |
647a1567 RH |
1084 | else |
1085 | elt->saved_in_reg = dest; | |
1086 | return; | |
1087 | } | |
1088 | ||
1089 | if (dest == NULL) | |
1090 | return; | |
1091 | ||
43215a89 RH |
1092 | elt = VEC_safe_push (reg_saved_in_data, heap, |
1093 | cur_trace->regs_saved_in_regs, NULL); | |
647a1567 RH |
1094 | elt->orig_reg = src; |
1095 | elt->saved_in_reg = dest; | |
1096 | } | |
1097 | ||
647a1567 RH |
1098 | /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at |
1099 | SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */ | |
1100 | ||
1101 | static void | |
89e25f95 | 1102 | queue_reg_save (rtx reg, rtx sreg, HOST_WIDE_INT offset) |
647a1567 | 1103 | { |
999646c1 RH |
1104 | queued_reg_save *q; |
1105 | size_t i; | |
647a1567 RH |
1106 | |
1107 | /* Duplicates waste space, but it's also necessary to remove them | |
a8e5c0e7 | 1108 | for correctness, since the queue gets output in reverse order. */ |
999646c1 | 1109 | FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q) |
a8e5c0e7 | 1110 | if (compare_reg_or_pc (q->reg, reg)) |
999646c1 | 1111 | goto found; |
647a1567 | 1112 | |
999646c1 | 1113 | q = VEC_safe_push (queued_reg_save, heap, queued_reg_saves, NULL); |
647a1567 | 1114 | |
999646c1 | 1115 | found: |
647a1567 | 1116 | q->reg = reg; |
647a1567 | 1117 | q->saved_reg = sreg; |
999646c1 | 1118 | q->cfa_offset = offset; |
647a1567 RH |
1119 | } |
1120 | ||
1121 | /* Output all the entries in QUEUED_REG_SAVES. */ | |
1122 | ||
1123 | static void | |
1124 | dwarf2out_flush_queued_reg_saves (void) | |
1125 | { | |
999646c1 RH |
1126 | queued_reg_save *q; |
1127 | size_t i; | |
647a1567 | 1128 | |
999646c1 | 1129 | FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q) |
647a1567 RH |
1130 | { |
1131 | unsigned int reg, sreg; | |
1132 | ||
1133 | record_reg_saved_in_reg (q->saved_reg, q->reg); | |
1134 | ||
a8e5c0e7 RH |
1135 | if (q->reg == pc_rtx) |
1136 | reg = DWARF_FRAME_RETURN_COLUMN; | |
1137 | else | |
7263c6d7 | 1138 | reg = dwf_regno (q->reg); |
647a1567 | 1139 | if (q->saved_reg) |
7263c6d7 | 1140 | sreg = dwf_regno (q->saved_reg); |
647a1567 RH |
1141 | else |
1142 | sreg = INVALID_REGNUM; | |
3edb53aa | 1143 | reg_save (reg, sreg, q->cfa_offset); |
647a1567 RH |
1144 | } |
1145 | ||
999646c1 | 1146 | VEC_truncate (queued_reg_save, queued_reg_saves, 0); |
647a1567 RH |
1147 | } |
1148 | ||
1149 | /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved | |
1150 | location for? Or, does it clobber a register which we've previously | |
1151 | said that some other register is saved in, and for which we now | |
1152 | have a new location for? */ | |
1153 | ||
1154 | static bool | |
1155 | clobbers_queued_reg_save (const_rtx insn) | |
1156 | { | |
999646c1 RH |
1157 | queued_reg_save *q; |
1158 | size_t iq; | |
647a1567 | 1159 | |
999646c1 | 1160 | FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, iq, q) |
647a1567 | 1161 | { |
999646c1 | 1162 | size_t ir; |
647a1567 RH |
1163 | reg_saved_in_data *rir; |
1164 | ||
1165 | if (modified_in_p (q->reg, insn)) | |
1166 | return true; | |
1167 | ||
43215a89 RH |
1168 | FOR_EACH_VEC_ELT (reg_saved_in_data, |
1169 | cur_trace->regs_saved_in_regs, ir, rir) | |
647a1567 RH |
1170 | if (compare_reg_or_pc (q->reg, rir->orig_reg) |
1171 | && modified_in_p (rir->saved_in_reg, insn)) | |
1172 | return true; | |
1173 | } | |
1174 | ||
1175 | return false; | |
1176 | } | |
1177 | ||
1178 | /* What register, if any, is currently saved in REG? */ | |
1179 | ||
1180 | static rtx | |
1181 | reg_saved_in (rtx reg) | |
1182 | { | |
1183 | unsigned int regn = REGNO (reg); | |
999646c1 | 1184 | queued_reg_save *q; |
647a1567 RH |
1185 | reg_saved_in_data *rir; |
1186 | size_t i; | |
1187 | ||
999646c1 | 1188 | FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q) |
647a1567 RH |
1189 | if (q->saved_reg && regn == REGNO (q->saved_reg)) |
1190 | return q->reg; | |
1191 | ||
43215a89 | 1192 | FOR_EACH_VEC_ELT (reg_saved_in_data, cur_trace->regs_saved_in_regs, i, rir) |
647a1567 RH |
1193 | if (regn == REGNO (rir->saved_in_reg)) |
1194 | return rir->orig_reg; | |
1195 | ||
1196 | return NULL_RTX; | |
1197 | } | |
1198 | ||
647a1567 RH |
1199 | /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */ |
1200 | ||
1201 | static void | |
89e25f95 | 1202 | dwarf2out_frame_debug_def_cfa (rtx pat) |
647a1567 | 1203 | { |
f17d3401 RH |
1204 | dw_cfa_location loc; |
1205 | ||
1206 | memset (&loc, 0, sizeof (loc)); | |
647a1567 RH |
1207 | |
1208 | switch (GET_CODE (pat)) | |
1209 | { | |
1210 | case PLUS: | |
f17d3401 RH |
1211 | loc.reg = dwf_regno (XEXP (pat, 0)); |
1212 | loc.offset = INTVAL (XEXP (pat, 1)); | |
647a1567 RH |
1213 | break; |
1214 | ||
1215 | case REG: | |
f17d3401 | 1216 | loc.reg = dwf_regno (pat); |
647a1567 RH |
1217 | break; |
1218 | ||
1219 | case MEM: | |
f17d3401 | 1220 | loc.indirect = 1; |
647a1567 RH |
1221 | pat = XEXP (pat, 0); |
1222 | if (GET_CODE (pat) == PLUS) | |
1223 | { | |
f17d3401 | 1224 | loc.base_offset = INTVAL (XEXP (pat, 1)); |
647a1567 RH |
1225 | pat = XEXP (pat, 0); |
1226 | } | |
f17d3401 | 1227 | loc.reg = dwf_regno (pat); |
647a1567 RH |
1228 | break; |
1229 | ||
1230 | default: | |
1231 | /* Recurse and define an expression. */ | |
1232 | gcc_unreachable (); | |
1233 | } | |
1234 | ||
f17d3401 | 1235 | def_cfa_1 (&loc); |
647a1567 RH |
1236 | } |
1237 | ||
1238 | /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */ | |
1239 | ||
1240 | static void | |
89e25f95 | 1241 | dwarf2out_frame_debug_adjust_cfa (rtx pat) |
647a1567 | 1242 | { |
f17d3401 | 1243 | dw_cfa_location loc = cur_row->cfa; |
647a1567 RH |
1244 | rtx src, dest; |
1245 | ||
1246 | gcc_assert (GET_CODE (pat) == SET); | |
1247 | dest = XEXP (pat, 0); | |
1248 | src = XEXP (pat, 1); | |
1249 | ||
1250 | switch (GET_CODE (src)) | |
1251 | { | |
1252 | case PLUS: | |
f17d3401 RH |
1253 | gcc_assert (dwf_regno (XEXP (src, 0)) == loc.reg); |
1254 | loc.offset -= INTVAL (XEXP (src, 1)); | |
647a1567 RH |
1255 | break; |
1256 | ||
1257 | case REG: | |
1258 | break; | |
1259 | ||
1260 | default: | |
1261 | gcc_unreachable (); | |
1262 | } | |
1263 | ||
f17d3401 RH |
1264 | loc.reg = dwf_regno (dest); |
1265 | gcc_assert (loc.indirect == 0); | |
647a1567 | 1266 | |
f17d3401 | 1267 | def_cfa_1 (&loc); |
647a1567 RH |
1268 | } |
1269 | ||
1270 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */ | |
1271 | ||
1272 | static void | |
89e25f95 | 1273 | dwarf2out_frame_debug_cfa_offset (rtx set) |
647a1567 RH |
1274 | { |
1275 | HOST_WIDE_INT offset; | |
1276 | rtx src, addr, span; | |
1277 | unsigned int sregno; | |
1278 | ||
1279 | src = XEXP (set, 1); | |
1280 | addr = XEXP (set, 0); | |
1281 | gcc_assert (MEM_P (addr)); | |
1282 | addr = XEXP (addr, 0); | |
1283 | ||
1284 | /* As documented, only consider extremely simple addresses. */ | |
1285 | switch (GET_CODE (addr)) | |
1286 | { | |
1287 | case REG: | |
f17d3401 RH |
1288 | gcc_assert (dwf_regno (addr) == cur_row->cfa.reg); |
1289 | offset = -cur_row->cfa.offset; | |
647a1567 RH |
1290 | break; |
1291 | case PLUS: | |
f17d3401 RH |
1292 | gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_row->cfa.reg); |
1293 | offset = INTVAL (XEXP (addr, 1)) - cur_row->cfa.offset; | |
647a1567 RH |
1294 | break; |
1295 | default: | |
1296 | gcc_unreachable (); | |
1297 | } | |
1298 | ||
1299 | if (src == pc_rtx) | |
1300 | { | |
1301 | span = NULL; | |
1302 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1303 | } | |
43215a89 | 1304 | else |
647a1567 RH |
1305 | { |
1306 | span = targetm.dwarf_register_span (src); | |
7263c6d7 | 1307 | sregno = dwf_regno (src); |
647a1567 RH |
1308 | } |
1309 | ||
1310 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1311 | a different flushing heuristic for epilogues. */ | |
1312 | if (!span) | |
3edb53aa | 1313 | reg_save (sregno, INVALID_REGNUM, offset); |
647a1567 RH |
1314 | else |
1315 | { | |
1316 | /* We have a PARALLEL describing where the contents of SRC live. | |
1317 | Queue register saves for each piece of the PARALLEL. */ | |
1318 | int par_index; | |
1319 | int limit; | |
1320 | HOST_WIDE_INT span_offset = offset; | |
1321 | ||
1322 | gcc_assert (GET_CODE (span) == PARALLEL); | |
1323 | ||
1324 | limit = XVECLEN (span, 0); | |
1325 | for (par_index = 0; par_index < limit; par_index++) | |
1326 | { | |
1327 | rtx elem = XVECEXP (span, 0, par_index); | |
1328 | ||
7263c6d7 | 1329 | sregno = dwf_regno (src); |
3edb53aa | 1330 | reg_save (sregno, INVALID_REGNUM, span_offset); |
647a1567 RH |
1331 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); |
1332 | } | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */ | |
1337 | ||
1338 | static void | |
89e25f95 | 1339 | dwarf2out_frame_debug_cfa_register (rtx set) |
647a1567 RH |
1340 | { |
1341 | rtx src, dest; | |
1342 | unsigned sregno, dregno; | |
1343 | ||
1344 | src = XEXP (set, 1); | |
1345 | dest = XEXP (set, 0); | |
1346 | ||
a8e5c0e7 | 1347 | record_reg_saved_in_reg (dest, src); |
647a1567 RH |
1348 | if (src == pc_rtx) |
1349 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1350 | else | |
7263c6d7 | 1351 | sregno = dwf_regno (src); |
647a1567 | 1352 | |
7263c6d7 | 1353 | dregno = dwf_regno (dest); |
647a1567 RH |
1354 | |
1355 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1356 | a different flushing heuristic for epilogues. */ | |
3edb53aa | 1357 | reg_save (sregno, dregno, 0); |
647a1567 RH |
1358 | } |
1359 | ||
1360 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ | |
1361 | ||
1362 | static void | |
89e25f95 | 1363 | dwarf2out_frame_debug_cfa_expression (rtx set) |
647a1567 RH |
1364 | { |
1365 | rtx src, dest, span; | |
1366 | dw_cfi_ref cfi = new_cfi (); | |
f1a0e830 | 1367 | unsigned regno; |
647a1567 RH |
1368 | |
1369 | dest = SET_DEST (set); | |
1370 | src = SET_SRC (set); | |
1371 | ||
1372 | gcc_assert (REG_P (src)); | |
1373 | gcc_assert (MEM_P (dest)); | |
1374 | ||
1375 | span = targetm.dwarf_register_span (src); | |
1376 | gcc_assert (!span); | |
1377 | ||
f1a0e830 RH |
1378 | regno = dwf_regno (src); |
1379 | ||
647a1567 | 1380 | cfi->dw_cfi_opc = DW_CFA_expression; |
f1a0e830 | 1381 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno; |
647a1567 RH |
1382 | cfi->dw_cfi_oprnd2.dw_cfi_loc |
1383 | = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest), | |
1384 | GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); | |
1385 | ||
1386 | /* ??? We'd like to use queue_reg_save, were the interface different, | |
1387 | and, as above, we could manage flushing for epilogues. */ | |
3edb53aa | 1388 | add_cfi (cfi); |
f1a0e830 | 1389 | update_row_reg_save (cur_row, regno, cfi); |
647a1567 RH |
1390 | } |
1391 | ||
1392 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */ | |
1393 | ||
1394 | static void | |
89e25f95 | 1395 | dwarf2out_frame_debug_cfa_restore (rtx reg) |
647a1567 | 1396 | { |
7263c6d7 | 1397 | unsigned int regno = dwf_regno (reg); |
647a1567 | 1398 | |
57e16c96 | 1399 | add_cfi_restore (regno); |
f1a0e830 | 1400 | update_row_reg_save (cur_row, regno, NULL); |
647a1567 RH |
1401 | } |
1402 | ||
1403 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE. | |
1404 | ??? Perhaps we should note in the CIE where windows are saved (instead of | |
1405 | assuming 0(cfa)) and what registers are in the window. */ | |
1406 | ||
1407 | static void | |
89e25f95 | 1408 | dwarf2out_frame_debug_cfa_window_save (void) |
647a1567 RH |
1409 | { |
1410 | dw_cfi_ref cfi = new_cfi (); | |
1411 | ||
1412 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; | |
3edb53aa | 1413 | add_cfi (cfi); |
647a1567 RH |
1414 | } |
1415 | ||
1416 | /* Record call frame debugging information for an expression EXPR, | |
1417 | which either sets SP or FP (adjusting how we calculate the frame | |
1418 | address) or saves a register to the stack or another register. | |
1419 | LABEL indicates the address of EXPR. | |
1420 | ||
1421 | This function encodes a state machine mapping rtxes to actions on | |
1422 | cfa, cfa_store, and cfa_temp.reg. We describe these rules so | |
1423 | users need not read the source code. | |
1424 | ||
1425 | The High-Level Picture | |
1426 | ||
1427 | Changes in the register we use to calculate the CFA: Currently we | |
1428 | assume that if you copy the CFA register into another register, we | |
1429 | should take the other one as the new CFA register; this seems to | |
1430 | work pretty well. If it's wrong for some target, it's simple | |
1431 | enough not to set RTX_FRAME_RELATED_P on the insn in question. | |
1432 | ||
1433 | Changes in the register we use for saving registers to the stack: | |
1434 | This is usually SP, but not always. Again, we deduce that if you | |
1435 | copy SP into another register (and SP is not the CFA register), | |
1436 | then the new register is the one we will be using for register | |
1437 | saves. This also seems to work. | |
1438 | ||
1439 | Register saves: There's not much guesswork about this one; if | |
1440 | RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a | |
1441 | register save, and the register used to calculate the destination | |
1442 | had better be the one we think we're using for this purpose. | |
1443 | It's also assumed that a copy from a call-saved register to another | |
1444 | register is saving that register if RTX_FRAME_RELATED_P is set on | |
1445 | that instruction. If the copy is from a call-saved register to | |
1446 | the *same* register, that means that the register is now the same | |
1447 | value as in the caller. | |
1448 | ||
1449 | Except: If the register being saved is the CFA register, and the | |
1450 | offset is nonzero, we are saving the CFA, so we assume we have to | |
1451 | use DW_CFA_def_cfa_expression. If the offset is 0, we assume that | |
1452 | the intent is to save the value of SP from the previous frame. | |
1453 | ||
1454 | In addition, if a register has previously been saved to a different | |
1455 | register, | |
1456 | ||
1457 | Invariants / Summaries of Rules | |
1458 | ||
1459 | cfa current rule for calculating the CFA. It usually | |
f17d3401 RH |
1460 | consists of a register and an offset. This is |
1461 | actually stored in cur_row->cfa, but abbreviated | |
1462 | for the purposes of this documentation. | |
647a1567 RH |
1463 | cfa_store register used by prologue code to save things to the stack |
1464 | cfa_store.offset is the offset from the value of | |
1465 | cfa_store.reg to the actual CFA | |
1466 | cfa_temp register holding an integral value. cfa_temp.offset | |
1467 | stores the value, which will be used to adjust the | |
1468 | stack pointer. cfa_temp is also used like cfa_store, | |
1469 | to track stores to the stack via fp or a temp reg. | |
1470 | ||
1471 | Rules 1- 4: Setting a register's value to cfa.reg or an expression | |
1472 | with cfa.reg as the first operand changes the cfa.reg and its | |
1473 | cfa.offset. Rule 1 and 4 also set cfa_temp.reg and | |
1474 | cfa_temp.offset. | |
1475 | ||
1476 | Rules 6- 9: Set a non-cfa.reg register value to a constant or an | |
1477 | expression yielding a constant. This sets cfa_temp.reg | |
1478 | and cfa_temp.offset. | |
1479 | ||
1480 | Rule 5: Create a new register cfa_store used to save items to the | |
1481 | stack. | |
1482 | ||
1483 | Rules 10-14: Save a register to the stack. Define offset as the | |
1484 | difference of the original location and cfa_store's | |
1485 | location (or cfa_temp's location if cfa_temp is used). | |
1486 | ||
1487 | Rules 16-20: If AND operation happens on sp in prologue, we assume | |
1488 | stack is realigned. We will use a group of DW_OP_XXX | |
1489 | expressions to represent the location of the stored | |
1490 | register instead of CFA+offset. | |
1491 | ||
1492 | The Rules | |
1493 | ||
1494 | "{a,b}" indicates a choice of a xor b. | |
1495 | "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg. | |
1496 | ||
1497 | Rule 1: | |
1498 | (set <reg1> <reg2>:cfa.reg) | |
1499 | effects: cfa.reg = <reg1> | |
1500 | cfa.offset unchanged | |
1501 | cfa_temp.reg = <reg1> | |
1502 | cfa_temp.offset = cfa.offset | |
1503 | ||
1504 | Rule 2: | |
1505 | (set sp ({minus,plus,losum} {sp,fp}:cfa.reg | |
1506 | {<const_int>,<reg>:cfa_temp.reg})) | |
1507 | effects: cfa.reg = sp if fp used | |
1508 | cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp | |
1509 | cfa_store.offset += {+/- <const_int>, cfa_temp.offset} | |
1510 | if cfa_store.reg==sp | |
1511 | ||
1512 | Rule 3: | |
1513 | (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>)) | |
1514 | effects: cfa.reg = fp | |
1515 | cfa_offset += +/- <const_int> | |
1516 | ||
1517 | Rule 4: | |
1518 | (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>)) | |
1519 | constraints: <reg1> != fp | |
1520 | <reg1> != sp | |
1521 | effects: cfa.reg = <reg1> | |
1522 | cfa_temp.reg = <reg1> | |
1523 | cfa_temp.offset = cfa.offset | |
1524 | ||
1525 | Rule 5: | |
1526 | (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg)) | |
1527 | constraints: <reg1> != fp | |
1528 | <reg1> != sp | |
1529 | effects: cfa_store.reg = <reg1> | |
1530 | cfa_store.offset = cfa.offset - cfa_temp.offset | |
1531 | ||
1532 | Rule 6: | |
1533 | (set <reg> <const_int>) | |
1534 | effects: cfa_temp.reg = <reg> | |
1535 | cfa_temp.offset = <const_int> | |
1536 | ||
1537 | Rule 7: | |
1538 | (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>)) | |
1539 | effects: cfa_temp.reg = <reg1> | |
1540 | cfa_temp.offset |= <const_int> | |
1541 | ||
1542 | Rule 8: | |
1543 | (set <reg> (high <exp>)) | |
1544 | effects: none | |
1545 | ||
1546 | Rule 9: | |
1547 | (set <reg> (lo_sum <exp> <const_int>)) | |
1548 | effects: cfa_temp.reg = <reg> | |
1549 | cfa_temp.offset = <const_int> | |
1550 | ||
1551 | Rule 10: | |
1552 | (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>) | |
1553 | effects: cfa_store.offset -= <const_int> | |
1554 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1555 | cfa.reg = sp | |
1556 | cfa.base_offset = -cfa_store.offset | |
1557 | ||
1558 | Rule 11: | |
1559 | (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>) | |
1560 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1561 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1562 | cfa.reg = sp | |
1563 | cfa.base_offset = -cfa_store.offset | |
1564 | ||
1565 | Rule 12: | |
1566 | (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>)) | |
1567 | ||
1568 | <reg2>) | |
1569 | effects: cfa.reg = <reg1> | |
1570 | cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset | |
1571 | ||
1572 | Rule 13: | |
1573 | (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>) | |
1574 | effects: cfa.reg = <reg1> | |
1575 | cfa.base_offset = -{cfa_store,cfa_temp}.offset | |
1576 | ||
1577 | Rule 14: | |
1578 | (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>) | |
1579 | effects: cfa.reg = <reg1> | |
1580 | cfa.base_offset = -cfa_temp.offset | |
1581 | cfa_temp.offset -= mode_size(mem) | |
1582 | ||
1583 | Rule 15: | |
1584 | (set <reg> {unspec, unspec_volatile}) | |
1585 | effects: target-dependent | |
1586 | ||
1587 | Rule 16: | |
1588 | (set sp (and: sp <const_int>)) | |
1589 | constraints: cfa_store.reg == sp | |
a518b996 | 1590 | effects: cfun->fde.stack_realign = 1 |
647a1567 RH |
1591 | cfa_store.offset = 0 |
1592 | fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp | |
1593 | ||
1594 | Rule 17: | |
1595 | (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int)))) | |
1596 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1597 | ||
1598 | Rule 18: | |
1599 | (set (mem ({pre_inc, pre_dec} sp)) fp) | |
1600 | constraints: fde->stack_realign == 1 | |
1601 | effects: cfa_store.offset = 0 | |
1602 | cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1603 | ||
1604 | Rule 19: | |
1605 | (set (mem ({pre_inc, pre_dec} sp)) cfa.reg) | |
1606 | constraints: fde->stack_realign == 1 | |
1607 | && cfa.offset == 0 | |
1608 | && cfa.indirect == 0 | |
1609 | && cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1610 | effects: Use DW_CFA_def_cfa_expression to define cfa | |
1611 | cfa.reg == fde->drap_reg */ | |
1612 | ||
1613 | static void | |
89e25f95 | 1614 | dwarf2out_frame_debug_expr (rtx expr) |
647a1567 | 1615 | { |
f17d3401 | 1616 | dw_cfa_location cfa = cur_row->cfa; |
647a1567 RH |
1617 | rtx src, dest, span; |
1618 | HOST_WIDE_INT offset; | |
1619 | dw_fde_ref fde; | |
1620 | ||
1621 | /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of | |
1622 | the PARALLEL independently. The first element is always processed if | |
1623 | it is a SET. This is for backward compatibility. Other elements | |
1624 | are processed only if they are SETs and the RTX_FRAME_RELATED_P | |
1625 | flag is set in them. */ | |
1626 | if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE) | |
1627 | { | |
1628 | int par_index; | |
1629 | int limit = XVECLEN (expr, 0); | |
1630 | rtx elem; | |
1631 | ||
1632 | /* PARALLELs have strict read-modify-write semantics, so we | |
1633 | ought to evaluate every rvalue before changing any lvalue. | |
1634 | It's cumbersome to do that in general, but there's an | |
1635 | easy approximation that is enough for all current users: | |
1636 | handle register saves before register assignments. */ | |
1637 | if (GET_CODE (expr) == PARALLEL) | |
1638 | for (par_index = 0; par_index < limit; par_index++) | |
1639 | { | |
1640 | elem = XVECEXP (expr, 0, par_index); | |
1641 | if (GET_CODE (elem) == SET | |
1642 | && MEM_P (SET_DEST (elem)) | |
1643 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
89e25f95 | 1644 | dwarf2out_frame_debug_expr (elem); |
647a1567 RH |
1645 | } |
1646 | ||
1647 | for (par_index = 0; par_index < limit; par_index++) | |
1648 | { | |
1649 | elem = XVECEXP (expr, 0, par_index); | |
1650 | if (GET_CODE (elem) == SET | |
1651 | && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE) | |
1652 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
89e25f95 | 1653 | dwarf2out_frame_debug_expr (elem); |
647a1567 RH |
1654 | else if (GET_CODE (elem) == SET |
1655 | && par_index != 0 | |
1656 | && !RTX_FRAME_RELATED_P (elem)) | |
1657 | { | |
1658 | /* Stack adjustment combining might combine some post-prologue | |
1659 | stack adjustment into a prologue stack adjustment. */ | |
43215a89 RH |
1660 | HOST_WIDE_INT offset |
1661 | = stack_adjust_offset (elem, queued_args_size, 0); | |
647a1567 RH |
1662 | |
1663 | if (offset != 0) | |
89e25f95 | 1664 | dwarf2out_stack_adjust (offset); |
647a1567 RH |
1665 | } |
1666 | } | |
1667 | return; | |
1668 | } | |
1669 | ||
1670 | gcc_assert (GET_CODE (expr) == SET); | |
1671 | ||
1672 | src = SET_SRC (expr); | |
1673 | dest = SET_DEST (expr); | |
1674 | ||
1675 | if (REG_P (src)) | |
1676 | { | |
1677 | rtx rsi = reg_saved_in (src); | |
1678 | if (rsi) | |
1679 | src = rsi; | |
1680 | } | |
1681 | ||
a518b996 | 1682 | fde = cfun->fde; |
647a1567 RH |
1683 | |
1684 | switch (GET_CODE (dest)) | |
1685 | { | |
1686 | case REG: | |
1687 | switch (GET_CODE (src)) | |
1688 | { | |
1689 | /* Setting FP from SP. */ | |
1690 | case REG: | |
7263c6d7 | 1691 | if (cfa.reg == dwf_regno (src)) |
647a1567 RH |
1692 | { |
1693 | /* Rule 1 */ | |
1694 | /* Update the CFA rule wrt SP or FP. Make sure src is | |
1695 | relative to the current CFA register. | |
1696 | ||
1697 | We used to require that dest be either SP or FP, but the | |
1698 | ARM copies SP to a temporary register, and from there to | |
1699 | FP. So we just rely on the backends to only set | |
1700 | RTX_FRAME_RELATED_P on appropriate insns. */ | |
7263c6d7 | 1701 | cfa.reg = dwf_regno (dest); |
43215a89 RH |
1702 | cur_trace->cfa_temp.reg = cfa.reg; |
1703 | cur_trace->cfa_temp.offset = cfa.offset; | |
647a1567 RH |
1704 | } |
1705 | else | |
1706 | { | |
1707 | /* Saving a register in a register. */ | |
1708 | gcc_assert (!fixed_regs [REGNO (dest)] | |
1709 | /* For the SPARC and its register window. */ | |
7263c6d7 | 1710 | || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN)); |
647a1567 RH |
1711 | |
1712 | /* After stack is aligned, we can only save SP in FP | |
1713 | if drap register is used. In this case, we have | |
1714 | to restore stack pointer with the CFA value and we | |
1715 | don't generate this DWARF information. */ | |
1716 | if (fde | |
1717 | && fde->stack_realign | |
1718 | && REGNO (src) == STACK_POINTER_REGNUM) | |
1719 | gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM | |
1720 | && fde->drap_reg != INVALID_REGNUM | |
7263c6d7 | 1721 | && cfa.reg != dwf_regno (src)); |
647a1567 | 1722 | else |
89e25f95 | 1723 | queue_reg_save (src, dest, 0); |
647a1567 RH |
1724 | } |
1725 | break; | |
1726 | ||
1727 | case PLUS: | |
1728 | case MINUS: | |
1729 | case LO_SUM: | |
1730 | if (dest == stack_pointer_rtx) | |
1731 | { | |
1732 | /* Rule 2 */ | |
1733 | /* Adjusting SP. */ | |
1734 | switch (GET_CODE (XEXP (src, 1))) | |
1735 | { | |
1736 | case CONST_INT: | |
1737 | offset = INTVAL (XEXP (src, 1)); | |
1738 | break; | |
1739 | case REG: | |
43215a89 RH |
1740 | gcc_assert (dwf_regno (XEXP (src, 1)) |
1741 | == cur_trace->cfa_temp.reg); | |
1742 | offset = cur_trace->cfa_temp.offset; | |
647a1567 RH |
1743 | break; |
1744 | default: | |
1745 | gcc_unreachable (); | |
1746 | } | |
1747 | ||
1748 | if (XEXP (src, 0) == hard_frame_pointer_rtx) | |
1749 | { | |
1750 | /* Restoring SP from FP in the epilogue. */ | |
4f42d714 RH |
1751 | gcc_assert (cfa.reg == dw_frame_pointer_regnum); |
1752 | cfa.reg = dw_stack_pointer_regnum; | |
647a1567 RH |
1753 | } |
1754 | else if (GET_CODE (src) == LO_SUM) | |
1755 | /* Assume we've set the source reg of the LO_SUM from sp. */ | |
1756 | ; | |
1757 | else | |
1758 | gcc_assert (XEXP (src, 0) == stack_pointer_rtx); | |
1759 | ||
1760 | if (GET_CODE (src) != MINUS) | |
1761 | offset = -offset; | |
4f42d714 | 1762 | if (cfa.reg == dw_stack_pointer_regnum) |
647a1567 | 1763 | cfa.offset += offset; |
43215a89 RH |
1764 | if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum) |
1765 | cur_trace->cfa_store.offset += offset; | |
647a1567 RH |
1766 | } |
1767 | else if (dest == hard_frame_pointer_rtx) | |
1768 | { | |
1769 | /* Rule 3 */ | |
1770 | /* Either setting the FP from an offset of the SP, | |
1771 | or adjusting the FP */ | |
1772 | gcc_assert (frame_pointer_needed); | |
1773 | ||
1774 | gcc_assert (REG_P (XEXP (src, 0)) | |
7263c6d7 | 1775 | && dwf_regno (XEXP (src, 0)) == cfa.reg |
647a1567 RH |
1776 | && CONST_INT_P (XEXP (src, 1))); |
1777 | offset = INTVAL (XEXP (src, 1)); | |
1778 | if (GET_CODE (src) != MINUS) | |
1779 | offset = -offset; | |
1780 | cfa.offset += offset; | |
4f42d714 | 1781 | cfa.reg = dw_frame_pointer_regnum; |
647a1567 RH |
1782 | } |
1783 | else | |
1784 | { | |
1785 | gcc_assert (GET_CODE (src) != MINUS); | |
1786 | ||
1787 | /* Rule 4 */ | |
1788 | if (REG_P (XEXP (src, 0)) | |
7263c6d7 | 1789 | && dwf_regno (XEXP (src, 0)) == cfa.reg |
647a1567 RH |
1790 | && CONST_INT_P (XEXP (src, 1))) |
1791 | { | |
1792 | /* Setting a temporary CFA register that will be copied | |
1793 | into the FP later on. */ | |
1794 | offset = - INTVAL (XEXP (src, 1)); | |
1795 | cfa.offset += offset; | |
7263c6d7 | 1796 | cfa.reg = dwf_regno (dest); |
647a1567 | 1797 | /* Or used to save regs to the stack. */ |
43215a89 RH |
1798 | cur_trace->cfa_temp.reg = cfa.reg; |
1799 | cur_trace->cfa_temp.offset = cfa.offset; | |
647a1567 RH |
1800 | } |
1801 | ||
1802 | /* Rule 5 */ | |
1803 | else if (REG_P (XEXP (src, 0)) | |
43215a89 | 1804 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
647a1567 RH |
1805 | && XEXP (src, 1) == stack_pointer_rtx) |
1806 | { | |
1807 | /* Setting a scratch register that we will use instead | |
1808 | of SP for saving registers to the stack. */ | |
4f42d714 | 1809 | gcc_assert (cfa.reg == dw_stack_pointer_regnum); |
43215a89 RH |
1810 | cur_trace->cfa_store.reg = dwf_regno (dest); |
1811 | cur_trace->cfa_store.offset | |
1812 | = cfa.offset - cur_trace->cfa_temp.offset; | |
647a1567 RH |
1813 | } |
1814 | ||
1815 | /* Rule 9 */ | |
1816 | else if (GET_CODE (src) == LO_SUM | |
1817 | && CONST_INT_P (XEXP (src, 1))) | |
1818 | { | |
43215a89 RH |
1819 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
1820 | cur_trace->cfa_temp.offset = INTVAL (XEXP (src, 1)); | |
647a1567 RH |
1821 | } |
1822 | else | |
1823 | gcc_unreachable (); | |
1824 | } | |
1825 | break; | |
1826 | ||
1827 | /* Rule 6 */ | |
1828 | case CONST_INT: | |
43215a89 RH |
1829 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
1830 | cur_trace->cfa_temp.offset = INTVAL (src); | |
647a1567 RH |
1831 | break; |
1832 | ||
1833 | /* Rule 7 */ | |
1834 | case IOR: | |
1835 | gcc_assert (REG_P (XEXP (src, 0)) | |
43215a89 | 1836 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
647a1567 RH |
1837 | && CONST_INT_P (XEXP (src, 1))); |
1838 | ||
43215a89 RH |
1839 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
1840 | cur_trace->cfa_temp.offset |= INTVAL (XEXP (src, 1)); | |
647a1567 RH |
1841 | break; |
1842 | ||
1843 | /* Skip over HIGH, assuming it will be followed by a LO_SUM, | |
1844 | which will fill in all of the bits. */ | |
1845 | /* Rule 8 */ | |
1846 | case HIGH: | |
1847 | break; | |
1848 | ||
1849 | /* Rule 15 */ | |
1850 | case UNSPEC: | |
1851 | case UNSPEC_VOLATILE: | |
89e25f95 BS |
1852 | /* All unspecs should be represented by REG_CFA_* notes. */ |
1853 | gcc_unreachable (); | |
647a1567 RH |
1854 | return; |
1855 | ||
1856 | /* Rule 16 */ | |
1857 | case AND: | |
1858 | /* If this AND operation happens on stack pointer in prologue, | |
1859 | we assume the stack is realigned and we extract the | |
1860 | alignment. */ | |
1861 | if (fde && XEXP (src, 0) == stack_pointer_rtx) | |
1862 | { | |
1863 | /* We interpret reg_save differently with stack_realign set. | |
1864 | Thus we must flush whatever we have queued first. */ | |
1865 | dwarf2out_flush_queued_reg_saves (); | |
1866 | ||
43215a89 RH |
1867 | gcc_assert (cur_trace->cfa_store.reg |
1868 | == dwf_regno (XEXP (src, 0))); | |
647a1567 RH |
1869 | fde->stack_realign = 1; |
1870 | fde->stack_realignment = INTVAL (XEXP (src, 1)); | |
43215a89 | 1871 | cur_trace->cfa_store.offset = 0; |
647a1567 | 1872 | |
4f42d714 RH |
1873 | if (cfa.reg != dw_stack_pointer_regnum |
1874 | && cfa.reg != dw_frame_pointer_regnum) | |
647a1567 RH |
1875 | fde->drap_reg = cfa.reg; |
1876 | } | |
1877 | return; | |
1878 | ||
1879 | default: | |
1880 | gcc_unreachable (); | |
1881 | } | |
1882 | ||
3edb53aa | 1883 | def_cfa_1 (&cfa); |
647a1567 RH |
1884 | break; |
1885 | ||
1886 | case MEM: | |
1887 | ||
1888 | /* Saving a register to the stack. Make sure dest is relative to the | |
1889 | CFA register. */ | |
1890 | switch (GET_CODE (XEXP (dest, 0))) | |
1891 | { | |
1892 | /* Rule 10 */ | |
1893 | /* With a push. */ | |
1894 | case PRE_MODIFY: | |
1895 | case POST_MODIFY: | |
1896 | /* We can't handle variable size modifications. */ | |
1897 | gcc_assert (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1)) | |
1898 | == CONST_INT); | |
1899 | offset = -INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1)); | |
1900 | ||
1901 | gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
43215a89 | 1902 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
647a1567 | 1903 | |
43215a89 | 1904 | cur_trace->cfa_store.offset += offset; |
4f42d714 | 1905 | if (cfa.reg == dw_stack_pointer_regnum) |
43215a89 | 1906 | cfa.offset = cur_trace->cfa_store.offset; |
647a1567 RH |
1907 | |
1908 | if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY) | |
43215a89 | 1909 | offset -= cur_trace->cfa_store.offset; |
647a1567 | 1910 | else |
43215a89 | 1911 | offset = -cur_trace->cfa_store.offset; |
647a1567 RH |
1912 | break; |
1913 | ||
1914 | /* Rule 11 */ | |
1915 | case PRE_INC: | |
1916 | case PRE_DEC: | |
1917 | case POST_DEC: | |
1918 | offset = GET_MODE_SIZE (GET_MODE (dest)); | |
1919 | if (GET_CODE (XEXP (dest, 0)) == PRE_INC) | |
1920 | offset = -offset; | |
1921 | ||
1922 | gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0)) | |
1923 | == STACK_POINTER_REGNUM) | |
43215a89 | 1924 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
647a1567 | 1925 | |
43215a89 | 1926 | cur_trace->cfa_store.offset += offset; |
647a1567 RH |
1927 | |
1928 | /* Rule 18: If stack is aligned, we will use FP as a | |
1929 | reference to represent the address of the stored | |
1930 | regiser. */ | |
1931 | if (fde | |
1932 | && fde->stack_realign | |
1933 | && src == hard_frame_pointer_rtx) | |
1934 | { | |
4f42d714 | 1935 | gcc_assert (cfa.reg != dw_frame_pointer_regnum); |
43215a89 | 1936 | cur_trace->cfa_store.offset = 0; |
647a1567 RH |
1937 | } |
1938 | ||
4f42d714 | 1939 | if (cfa.reg == dw_stack_pointer_regnum) |
43215a89 | 1940 | cfa.offset = cur_trace->cfa_store.offset; |
647a1567 RH |
1941 | |
1942 | if (GET_CODE (XEXP (dest, 0)) == POST_DEC) | |
43215a89 | 1943 | offset += -cur_trace->cfa_store.offset; |
647a1567 | 1944 | else |
43215a89 | 1945 | offset = -cur_trace->cfa_store.offset; |
647a1567 RH |
1946 | break; |
1947 | ||
1948 | /* Rule 12 */ | |
1949 | /* With an offset. */ | |
1950 | case PLUS: | |
1951 | case MINUS: | |
1952 | case LO_SUM: | |
1953 | { | |
7263c6d7 | 1954 | unsigned int regno; |
647a1567 RH |
1955 | |
1956 | gcc_assert (CONST_INT_P (XEXP (XEXP (dest, 0), 1)) | |
1957 | && REG_P (XEXP (XEXP (dest, 0), 0))); | |
1958 | offset = INTVAL (XEXP (XEXP (dest, 0), 1)); | |
1959 | if (GET_CODE (XEXP (dest, 0)) == MINUS) | |
1960 | offset = -offset; | |
1961 | ||
7263c6d7 | 1962 | regno = dwf_regno (XEXP (XEXP (dest, 0), 0)); |
647a1567 | 1963 | |
7263c6d7 | 1964 | if (cfa.reg == regno) |
647a1567 | 1965 | offset -= cfa.offset; |
43215a89 RH |
1966 | else if (cur_trace->cfa_store.reg == regno) |
1967 | offset -= cur_trace->cfa_store.offset; | |
647a1567 RH |
1968 | else |
1969 | { | |
43215a89 RH |
1970 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1971 | offset -= cur_trace->cfa_temp.offset; | |
647a1567 RH |
1972 | } |
1973 | } | |
1974 | break; | |
1975 | ||
1976 | /* Rule 13 */ | |
1977 | /* Without an offset. */ | |
1978 | case REG: | |
1979 | { | |
7263c6d7 | 1980 | unsigned int regno = dwf_regno (XEXP (dest, 0)); |
647a1567 | 1981 | |
7263c6d7 | 1982 | if (cfa.reg == regno) |
647a1567 | 1983 | offset = -cfa.offset; |
43215a89 RH |
1984 | else if (cur_trace->cfa_store.reg == regno) |
1985 | offset = -cur_trace->cfa_store.offset; | |
647a1567 RH |
1986 | else |
1987 | { | |
43215a89 RH |
1988 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1989 | offset = -cur_trace->cfa_temp.offset; | |
647a1567 RH |
1990 | } |
1991 | } | |
1992 | break; | |
1993 | ||
1994 | /* Rule 14 */ | |
1995 | case POST_INC: | |
43215a89 RH |
1996 | gcc_assert (cur_trace->cfa_temp.reg |
1997 | == dwf_regno (XEXP (XEXP (dest, 0), 0))); | |
1998 | offset = -cur_trace->cfa_temp.offset; | |
1999 | cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest)); | |
647a1567 RH |
2000 | break; |
2001 | ||
2002 | default: | |
2003 | gcc_unreachable (); | |
2004 | } | |
2005 | ||
a8e5c0e7 RH |
2006 | /* Rule 17 */ |
2007 | /* If the source operand of this MEM operation is a memory, | |
2008 | we only care how much stack grew. */ | |
2009 | if (MEM_P (src)) | |
647a1567 RH |
2010 | break; |
2011 | ||
a8e5c0e7 RH |
2012 | if (REG_P (src) |
2013 | && REGNO (src) != STACK_POINTER_REGNUM | |
647a1567 | 2014 | && REGNO (src) != HARD_FRAME_POINTER_REGNUM |
7263c6d7 | 2015 | && dwf_regno (src) == cfa.reg) |
647a1567 RH |
2016 | { |
2017 | /* We're storing the current CFA reg into the stack. */ | |
2018 | ||
2019 | if (cfa.offset == 0) | |
2020 | { | |
2021 | /* Rule 19 */ | |
2022 | /* If stack is aligned, putting CFA reg into stack means | |
2023 | we can no longer use reg + offset to represent CFA. | |
2024 | Here we use DW_CFA_def_cfa_expression instead. The | |
2025 | result of this expression equals to the original CFA | |
2026 | value. */ | |
2027 | if (fde | |
2028 | && fde->stack_realign | |
2029 | && cfa.indirect == 0 | |
4f42d714 | 2030 | && cfa.reg != dw_frame_pointer_regnum) |
647a1567 RH |
2031 | { |
2032 | dw_cfa_location cfa_exp; | |
2033 | ||
2034 | gcc_assert (fde->drap_reg == cfa.reg); | |
2035 | ||
2036 | cfa_exp.indirect = 1; | |
4f42d714 | 2037 | cfa_exp.reg = dw_frame_pointer_regnum; |
647a1567 RH |
2038 | cfa_exp.base_offset = offset; |
2039 | cfa_exp.offset = 0; | |
2040 | ||
2041 | fde->drap_reg_saved = 1; | |
2042 | ||
3edb53aa | 2043 | def_cfa_1 (&cfa_exp); |
647a1567 RH |
2044 | break; |
2045 | } | |
2046 | ||
2047 | /* If the source register is exactly the CFA, assume | |
2048 | we're saving SP like any other register; this happens | |
2049 | on the ARM. */ | |
3edb53aa | 2050 | def_cfa_1 (&cfa); |
89e25f95 | 2051 | queue_reg_save (stack_pointer_rtx, NULL_RTX, offset); |
647a1567 RH |
2052 | break; |
2053 | } | |
2054 | else | |
2055 | { | |
2056 | /* Otherwise, we'll need to look in the stack to | |
2057 | calculate the CFA. */ | |
2058 | rtx x = XEXP (dest, 0); | |
2059 | ||
2060 | if (!REG_P (x)) | |
2061 | x = XEXP (x, 0); | |
2062 | gcc_assert (REG_P (x)); | |
2063 | ||
7263c6d7 | 2064 | cfa.reg = dwf_regno (x); |
647a1567 RH |
2065 | cfa.base_offset = offset; |
2066 | cfa.indirect = 1; | |
3edb53aa | 2067 | def_cfa_1 (&cfa); |
647a1567 RH |
2068 | break; |
2069 | } | |
2070 | } | |
2071 | ||
3edb53aa | 2072 | def_cfa_1 (&cfa); |
647a1567 | 2073 | |
a8e5c0e7 RH |
2074 | span = NULL; |
2075 | if (REG_P (src)) | |
2076 | span = targetm.dwarf_register_span (src); | |
2077 | if (!span) | |
2078 | queue_reg_save (src, NULL_RTX, offset); | |
2079 | else | |
2080 | { | |
2081 | /* We have a PARALLEL describing where the contents of SRC live. | |
2082 | Queue register saves for each piece of the PARALLEL. */ | |
2083 | int par_index; | |
2084 | int limit; | |
2085 | HOST_WIDE_INT span_offset = offset; | |
647a1567 | 2086 | |
a8e5c0e7 | 2087 | gcc_assert (GET_CODE (span) == PARALLEL); |
647a1567 | 2088 | |
a8e5c0e7 RH |
2089 | limit = XVECLEN (span, 0); |
2090 | for (par_index = 0; par_index < limit; par_index++) | |
2091 | { | |
2092 | rtx elem = XVECEXP (span, 0, par_index); | |
2093 | queue_reg_save (elem, NULL_RTX, span_offset); | |
2094 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); | |
2095 | } | |
2096 | } | |
647a1567 RH |
2097 | break; |
2098 | ||
2099 | default: | |
2100 | gcc_unreachable (); | |
2101 | } | |
2102 | } | |
2103 | ||
2104 | /* Record call frame debugging information for INSN, which either | |
2105 | sets SP or FP (adjusting how we calculate the frame address) or saves a | |
2106 | register to the stack. If INSN is NULL_RTX, initialize our state. | |
2107 | ||
2108 | If AFTER_P is false, we're being called before the insn is emitted, | |
2109 | otherwise after. Call instructions get invoked twice. */ | |
2110 | ||
7644b3c7 | 2111 | static void |
647a1567 RH |
2112 | dwarf2out_frame_debug (rtx insn, bool after_p) |
2113 | { | |
647a1567 RH |
2114 | rtx note, n; |
2115 | bool handled_one = false; | |
2116 | bool need_flush = false; | |
2117 | ||
2118 | if (!NONJUMP_INSN_P (insn) || clobbers_queued_reg_save (insn)) | |
2119 | dwarf2out_flush_queued_reg_saves (); | |
2120 | ||
2121 | if (!RTX_FRAME_RELATED_P (insn)) | |
2122 | { | |
2123 | /* ??? This should be done unconditionally since stack adjustments | |
2124 | matter if the stack pointer is not the CFA register anymore but | |
2125 | is still used to save registers. */ | |
2126 | if (!ACCUMULATE_OUTGOING_ARGS) | |
2127 | dwarf2out_notice_stack_adjust (insn, after_p); | |
2128 | return; | |
2129 | } | |
2130 | ||
647a1567 RH |
2131 | any_cfis_emitted = false; |
2132 | ||
2133 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2134 | switch (REG_NOTE_KIND (note)) | |
2135 | { | |
2136 | case REG_FRAME_RELATED_EXPR: | |
2137 | insn = XEXP (note, 0); | |
2138 | goto do_frame_expr; | |
2139 | ||
2140 | case REG_CFA_DEF_CFA: | |
89e25f95 | 2141 | dwarf2out_frame_debug_def_cfa (XEXP (note, 0)); |
647a1567 RH |
2142 | handled_one = true; |
2143 | break; | |
2144 | ||
2145 | case REG_CFA_ADJUST_CFA: | |
2146 | n = XEXP (note, 0); | |
2147 | if (n == NULL) | |
2148 | { | |
2149 | n = PATTERN (insn); | |
2150 | if (GET_CODE (n) == PARALLEL) | |
2151 | n = XVECEXP (n, 0, 0); | |
2152 | } | |
89e25f95 | 2153 | dwarf2out_frame_debug_adjust_cfa (n); |
647a1567 RH |
2154 | handled_one = true; |
2155 | break; | |
2156 | ||
2157 | case REG_CFA_OFFSET: | |
2158 | n = XEXP (note, 0); | |
2159 | if (n == NULL) | |
2160 | n = single_set (insn); | |
89e25f95 | 2161 | dwarf2out_frame_debug_cfa_offset (n); |
647a1567 RH |
2162 | handled_one = true; |
2163 | break; | |
2164 | ||
2165 | case REG_CFA_REGISTER: | |
2166 | n = XEXP (note, 0); | |
2167 | if (n == NULL) | |
2168 | { | |
2169 | n = PATTERN (insn); | |
2170 | if (GET_CODE (n) == PARALLEL) | |
2171 | n = XVECEXP (n, 0, 0); | |
2172 | } | |
89e25f95 | 2173 | dwarf2out_frame_debug_cfa_register (n); |
647a1567 RH |
2174 | handled_one = true; |
2175 | break; | |
2176 | ||
2177 | case REG_CFA_EXPRESSION: | |
2178 | n = XEXP (note, 0); | |
2179 | if (n == NULL) | |
2180 | n = single_set (insn); | |
89e25f95 | 2181 | dwarf2out_frame_debug_cfa_expression (n); |
647a1567 RH |
2182 | handled_one = true; |
2183 | break; | |
2184 | ||
2185 | case REG_CFA_RESTORE: | |
2186 | n = XEXP (note, 0); | |
2187 | if (n == NULL) | |
2188 | { | |
2189 | n = PATTERN (insn); | |
2190 | if (GET_CODE (n) == PARALLEL) | |
2191 | n = XVECEXP (n, 0, 0); | |
2192 | n = XEXP (n, 0); | |
2193 | } | |
89e25f95 | 2194 | dwarf2out_frame_debug_cfa_restore (n); |
647a1567 RH |
2195 | handled_one = true; |
2196 | break; | |
2197 | ||
2198 | case REG_CFA_SET_VDRAP: | |
2199 | n = XEXP (note, 0); | |
2200 | if (REG_P (n)) | |
2201 | { | |
a518b996 | 2202 | dw_fde_ref fde = cfun->fde; |
647a1567 RH |
2203 | if (fde) |
2204 | { | |
2205 | gcc_assert (fde->vdrap_reg == INVALID_REGNUM); | |
2206 | if (REG_P (n)) | |
7263c6d7 | 2207 | fde->vdrap_reg = dwf_regno (n); |
647a1567 RH |
2208 | } |
2209 | } | |
2210 | handled_one = true; | |
2211 | break; | |
2212 | ||
2213 | case REG_CFA_WINDOW_SAVE: | |
89e25f95 | 2214 | dwarf2out_frame_debug_cfa_window_save (); |
647a1567 RH |
2215 | handled_one = true; |
2216 | break; | |
2217 | ||
2218 | case REG_CFA_FLUSH_QUEUE: | |
2219 | /* The actual flush happens below. */ | |
2220 | need_flush = true; | |
2221 | handled_one = true; | |
2222 | break; | |
2223 | ||
2224 | default: | |
2225 | break; | |
2226 | } | |
2227 | ||
2228 | if (handled_one) | |
2229 | { | |
2230 | /* Minimize the number of advances by emitting the entire queue | |
2231 | once anything is emitted. */ | |
2232 | need_flush |= any_cfis_emitted; | |
2233 | } | |
2234 | else | |
2235 | { | |
2236 | insn = PATTERN (insn); | |
2237 | do_frame_expr: | |
89e25f95 | 2238 | dwarf2out_frame_debug_expr (insn); |
647a1567 RH |
2239 | |
2240 | /* Check again. A parallel can save and update the same register. | |
2241 | We could probably check just once, here, but this is safer than | |
2242 | removing the check at the start of the function. */ | |
2243 | if (any_cfis_emitted || clobbers_queued_reg_save (insn)) | |
2244 | need_flush = true; | |
2245 | } | |
2246 | ||
2247 | if (need_flush) | |
2248 | dwarf2out_flush_queued_reg_saves (); | |
2249 | } | |
2250 | ||
57e16c96 RH |
2251 | /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */ |
2252 | ||
2253 | static void | |
ce363ef2 | 2254 | change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row) |
57e16c96 RH |
2255 | { |
2256 | size_t i, n_old, n_new, n_max; | |
2257 | dw_cfi_ref cfi; | |
2258 | ||
2259 | if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi)) | |
2260 | add_cfi (new_row->cfa_cfi); | |
2261 | else | |
2262 | { | |
2263 | cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa); | |
2264 | if (cfi) | |
2265 | add_cfi (cfi); | |
2266 | } | |
2267 | ||
2268 | if (old_row->args_size != new_row->args_size) | |
2269 | add_cfi_args_size (new_row->args_size); | |
2270 | ||
2271 | n_old = VEC_length (dw_cfi_ref, old_row->reg_save); | |
2272 | n_new = VEC_length (dw_cfi_ref, new_row->reg_save); | |
2273 | n_max = MAX (n_old, n_new); | |
2274 | ||
2275 | for (i = 0; i < n_max; ++i) | |
2276 | { | |
2277 | dw_cfi_ref r_old = NULL, r_new = NULL; | |
2278 | ||
2279 | if (i < n_old) | |
2280 | r_old = VEC_index (dw_cfi_ref, old_row->reg_save, i); | |
2281 | if (i < n_new) | |
2282 | r_new = VEC_index (dw_cfi_ref, new_row->reg_save, i); | |
2283 | ||
2284 | if (r_old == r_new) | |
2285 | ; | |
2286 | else if (r_new == NULL) | |
2287 | add_cfi_restore (i); | |
2288 | else if (!cfi_equal_p (r_old, r_new)) | |
2289 | add_cfi (r_new); | |
2290 | } | |
2291 | } | |
2292 | ||
89e25f95 BS |
2293 | /* Examine CFI and return true if a cfi label and set_loc is needed |
2294 | beforehand. Even when generating CFI assembler instructions, we | |
4a8ee122 | 2295 | still have to add the cfi to the list so that lookup_cfa_1 works |
89e25f95 BS |
2296 | later on. When -g2 and above we even need to force emitting of |
2297 | CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list | |
2298 | purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa | |
2299 | and so don't use convert_cfa_to_fb_loc_list. */ | |
2300 | ||
2301 | static bool | |
2302 | cfi_label_required_p (dw_cfi_ref cfi) | |
2303 | { | |
2304 | if (!dwarf2out_do_cfi_asm ()) | |
2305 | return true; | |
2306 | ||
2307 | if (dwarf_version == 2 | |
2308 | && debug_info_level > DINFO_LEVEL_TERSE | |
2309 | && (write_symbols == DWARF2_DEBUG | |
2310 | || write_symbols == VMS_AND_DWARF2_DEBUG)) | |
2311 | { | |
2312 | switch (cfi->dw_cfi_opc) | |
2313 | { | |
2314 | case DW_CFA_def_cfa_offset: | |
2315 | case DW_CFA_def_cfa_offset_sf: | |
2316 | case DW_CFA_def_cfa_register: | |
2317 | case DW_CFA_def_cfa: | |
2318 | case DW_CFA_def_cfa_sf: | |
2319 | case DW_CFA_def_cfa_expression: | |
2320 | case DW_CFA_restore_state: | |
2321 | return true; | |
2322 | default: | |
2323 | return false; | |
2324 | } | |
2325 | } | |
2326 | return false; | |
2327 | } | |
2328 | ||
2329 | /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the | |
2330 | function's FDE, adding CFI labels and set_loc/advance_loc opcodes as | |
2331 | necessary. */ | |
2332 | static void | |
2333 | add_cfis_to_fde (void) | |
2334 | { | |
a518b996 | 2335 | dw_fde_ref fde = cfun->fde; |
89e25f95 BS |
2336 | rtx insn, next; |
2337 | /* We always start with a function_begin label. */ | |
2338 | bool first = false; | |
2339 | ||
2340 | for (insn = get_insns (); insn; insn = next) | |
2341 | { | |
2342 | next = NEXT_INSN (insn); | |
2343 | ||
2344 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
2345 | { | |
57e16c96 RH |
2346 | fde->dw_fde_switch_cfi_index |
2347 | = VEC_length (dw_cfi_ref, fde->dw_fde_cfi); | |
89e25f95 BS |
2348 | /* Don't attempt to advance_loc4 between labels |
2349 | in different sections. */ | |
2350 | first = true; | |
2351 | } | |
2352 | ||
2353 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) | |
2354 | { | |
2355 | bool required = cfi_label_required_p (NOTE_CFI (insn)); | |
2356 | while (next && NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI) | |
2357 | { | |
2358 | required |= cfi_label_required_p (NOTE_CFI (next)); | |
2359 | next = NEXT_INSN (next); | |
2360 | } | |
2361 | if (required) | |
2362 | { | |
2363 | int num = dwarf2out_cfi_label_num; | |
2364 | const char *label = dwarf2out_cfi_label (); | |
2365 | dw_cfi_ref xcfi; | |
2366 | rtx tmp; | |
2367 | ||
2368 | /* Set the location counter to the new label. */ | |
2369 | xcfi = new_cfi (); | |
2370 | xcfi->dw_cfi_opc = (first ? DW_CFA_set_loc | |
2371 | : DW_CFA_advance_loc4); | |
2372 | xcfi->dw_cfi_oprnd1.dw_cfi_addr = label; | |
2373 | VEC_safe_push (dw_cfi_ref, gc, fde->dw_fde_cfi, xcfi); | |
2374 | ||
2375 | tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn); | |
2376 | NOTE_LABEL_NUMBER (tmp) = num; | |
2377 | } | |
2378 | ||
2379 | do | |
2380 | { | |
2381 | VEC_safe_push (dw_cfi_ref, gc, fde->dw_fde_cfi, NOTE_CFI (insn)); | |
2382 | insn = NEXT_INSN (insn); | |
2383 | } | |
2384 | while (insn != next); | |
2385 | first = false; | |
2386 | } | |
2387 | } | |
2388 | } | |
2389 | ||
829bdd4b RH |
2390 | /* If LABEL is the start of a trace, then initialize the state of that |
2391 | trace from CUR_TRACE and CUR_ROW. */ | |
43215a89 | 2392 | |
7644b3c7 | 2393 | static void |
2f23f97a | 2394 | maybe_record_trace_start (rtx start, rtx origin, bool abnormal) |
89e25f95 | 2395 | { |
829bdd4b RH |
2396 | dw_trace_info *ti; |
2397 | ||
2398 | /* Sync queued data before propagating to a destination, | |
2399 | lest we propagate out-of-date data. */ | |
2400 | dwarf2out_flush_queued_reg_saves (); | |
2401 | dwarf2out_args_size (queued_args_size); | |
2402 | ||
2403 | ti = get_trace_info (start); | |
2404 | gcc_assert (ti != NULL); | |
647a1567 | 2405 | |
829bdd4b | 2406 | if (dump_file) |
647a1567 | 2407 | { |
829bdd4b | 2408 | fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n", |
200e10dc | 2409 | cur_trace->id, ti->id, |
829bdd4b RH |
2410 | (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"), |
2411 | (origin ? INSN_UID (origin) : 0)); | |
2412 | } | |
bc5612ed | 2413 | |
829bdd4b RH |
2414 | if (ti->beg_row == NULL) |
2415 | { | |
2416 | /* This is the first time we've encountered this trace. Propagate | |
2417 | state across the edge and push the trace onto the work list. */ | |
2418 | ti->beg_row = copy_cfi_row (cur_row); | |
2f23f97a RH |
2419 | /* On all abnormal edges, especially EH and non-local-goto, we take |
2420 | care to free the pushed arguments. */ | |
2421 | if (abnormal) | |
2422 | ti->beg_row->args_size = 0; | |
2423 | ||
829bdd4b RH |
2424 | ti->cfa_store = cur_trace->cfa_store; |
2425 | ti->cfa_temp = cur_trace->cfa_temp; | |
2426 | ti->regs_saved_in_regs = VEC_copy (reg_saved_in_data, heap, | |
2427 | cur_trace->regs_saved_in_regs); | |
2428 | ||
2429 | VEC_safe_push (dw_trace_info_ref, heap, trace_work_list, ti); | |
2430 | ||
2431 | if (dump_file) | |
200e10dc | 2432 | fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id); |
829bdd4b RH |
2433 | } |
2434 | else | |
2435 | { | |
2436 | /* We ought to have the same state incoming to a given trace no | |
2437 | matter how we arrive at the trace. Anything else means we've | |
2438 | got some kind of optimization error. */ | |
2439 | gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row)); | |
2440 | } | |
2441 | } | |
45fba6d1 | 2442 | |
829bdd4b RH |
2443 | /* Propagate CUR_TRACE state to the destinations implied by INSN. */ |
2444 | /* ??? Sadly, this is in large part a duplicate of make_edges. */ | |
2445 | ||
2446 | static void | |
2447 | create_trace_edges (rtx insn) | |
2448 | { | |
2449 | rtx tmp, lab; | |
2450 | int i, n; | |
2451 | ||
2452 | if (JUMP_P (insn)) | |
2453 | { | |
2454 | if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
2455 | ; | |
2456 | else if (tablejump_p (insn, NULL, &tmp)) | |
bc5612ed | 2457 | { |
829bdd4b | 2458 | rtvec vec; |
bc5612ed | 2459 | |
829bdd4b RH |
2460 | tmp = PATTERN (tmp); |
2461 | vec = XVEC (tmp, GET_CODE (tmp) == ADDR_DIFF_VEC); | |
2462 | ||
2463 | n = GET_NUM_ELEM (vec); | |
2464 | for (i = 0; i < n; ++i) | |
2465 | { | |
2466 | lab = XEXP (RTVEC_ELT (vec, i), 0); | |
2f23f97a | 2467 | maybe_record_trace_start (lab, insn, false); |
829bdd4b RH |
2468 | } |
2469 | } | |
2470 | else if (computed_jump_p (insn)) | |
bc5612ed | 2471 | { |
829bdd4b | 2472 | for (lab = forced_labels; lab; lab = XEXP (lab, 1)) |
2f23f97a | 2473 | maybe_record_trace_start (XEXP (lab, 0), insn, true); |
829bdd4b RH |
2474 | } |
2475 | else if (returnjump_p (insn)) | |
2476 | ; | |
2477 | else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL) | |
2478 | { | |
2479 | n = ASM_OPERANDS_LABEL_LENGTH (tmp); | |
2480 | for (i = 0; i < n; ++i) | |
bc5612ed | 2481 | { |
829bdd4b | 2482 | lab = XEXP (ASM_OPERANDS_LABEL (tmp, i), 0); |
2f23f97a | 2483 | maybe_record_trace_start (lab, insn, true); |
829bdd4b RH |
2484 | } |
2485 | } | |
2486 | else | |
2487 | { | |
2488 | lab = JUMP_LABEL (insn); | |
2489 | gcc_assert (lab != NULL); | |
2f23f97a | 2490 | maybe_record_trace_start (lab, insn, false); |
829bdd4b RH |
2491 | } |
2492 | } | |
2493 | else if (CALL_P (insn)) | |
2494 | { | |
2495 | /* Sibling calls don't have edges inside this function. */ | |
2496 | if (SIBLING_CALL_P (insn)) | |
2497 | return; | |
965b2557 | 2498 | |
829bdd4b RH |
2499 | /* Process non-local goto edges. */ |
2500 | if (can_nonlocal_goto (insn)) | |
2501 | for (lab = nonlocal_goto_handler_labels; lab; lab = XEXP (lab, 1)) | |
2f23f97a | 2502 | maybe_record_trace_start (XEXP (lab, 0), insn, true); |
829bdd4b | 2503 | } |
3382318a RH |
2504 | else if (GET_CODE (PATTERN (insn)) == SEQUENCE) |
2505 | { | |
2506 | rtx seq = PATTERN (insn); | |
2507 | int i, n = XVECLEN (seq, 0); | |
2508 | for (i = 0; i < n; ++i) | |
2509 | create_trace_edges (XVECEXP (seq, 0, i)); | |
2510 | return; | |
2511 | } | |
965b2557 | 2512 | |
829bdd4b RH |
2513 | /* Process EH edges. */ |
2514 | if (CALL_P (insn) || cfun->can_throw_non_call_exceptions) | |
2515 | { | |
2516 | eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn); | |
2517 | if (lp) | |
2f23f97a | 2518 | maybe_record_trace_start (lp->landing_pad, insn, true); |
829bdd4b RH |
2519 | } |
2520 | } | |
57e16c96 | 2521 | |
829bdd4b RH |
2522 | /* Scan the trace beginning at INSN and create the CFI notes for the |
2523 | instructions therein. */ | |
2524 | ||
2525 | static void | |
2526 | scan_trace (dw_trace_info *trace) | |
2527 | { | |
2528 | rtx insn = trace->head; | |
2529 | ||
2530 | if (dump_file) | |
2531 | fprintf (dump_file, "Processing trace %u : start at %s %d\n", | |
200e10dc | 2532 | trace->id, rtx_name[(int) GET_CODE (insn)], |
829bdd4b RH |
2533 | INSN_UID (insn)); |
2534 | ||
2535 | trace->end_row = copy_cfi_row (trace->beg_row); | |
2536 | ||
2537 | cur_trace = trace; | |
2538 | cur_row = trace->end_row; | |
2539 | queued_args_size = cur_row->args_size; | |
2540 | ||
2541 | for (insn = NEXT_INSN (insn); insn ; insn = NEXT_INSN (insn)) | |
2542 | { | |
2543 | rtx pat; | |
2544 | ||
2545 | add_cfi_insn = PREV_INSN (insn); | |
2546 | ||
2547 | /* Notice the end of a trace. */ | |
2548 | if (BARRIER_P (insn) || save_point_p (insn)) | |
2549 | { | |
2550 | dwarf2out_flush_queued_reg_saves (); | |
2551 | dwarf2out_args_size (queued_args_size); | |
2552 | ||
2553 | /* Propagate across fallthru edges. */ | |
2554 | if (!BARRIER_P (insn)) | |
2f23f97a | 2555 | maybe_record_trace_start (insn, NULL, false); |
829bdd4b | 2556 | break; |
bc5612ed BS |
2557 | } |
2558 | ||
829bdd4b | 2559 | if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn)) |
bc5612ed BS |
2560 | continue; |
2561 | ||
2562 | pat = PATTERN (insn); | |
2563 | if (asm_noperands (pat) >= 0) | |
2564 | { | |
2565 | dwarf2out_frame_debug (insn, false); | |
829bdd4b | 2566 | add_cfi_insn = insn; |
bc5612ed | 2567 | } |
829bdd4b | 2568 | else |
bc5612ed | 2569 | { |
829bdd4b RH |
2570 | if (GET_CODE (pat) == SEQUENCE) |
2571 | { | |
2572 | int i, n = XVECLEN (pat, 0); | |
2573 | for (i = 1; i < n; ++i) | |
2574 | dwarf2out_frame_debug (XVECEXP (pat, 0, i), false); | |
2575 | } | |
2576 | ||
2577 | if (CALL_P (insn)) | |
2578 | dwarf2out_frame_debug (insn, false); | |
2579 | else if (find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL) | |
2580 | || (cfun->can_throw_non_call_exceptions | |
2581 | && can_throw_internal (insn))) | |
2582 | dwarf2out_flush_queued_reg_saves (); | |
bc5612ed | 2583 | |
829bdd4b RH |
2584 | /* Do not separate tablejump insns from their ADDR_DIFF_VEC. |
2585 | Putting the note after the VEC should be ok. */ | |
2586 | if (!tablejump_p (insn, NULL, &add_cfi_insn)) | |
2587 | add_cfi_insn = insn; | |
bc5612ed | 2588 | |
829bdd4b RH |
2589 | dwarf2out_frame_debug (insn, true); |
2590 | } | |
45fba6d1 | 2591 | |
829bdd4b RH |
2592 | /* Note that a test for control_flow_insn_p does exactly the |
2593 | same tests as are done to actually create the edges. So | |
2594 | always call the routine and let it not create edges for | |
2595 | non-control-flow insns. */ | |
2596 | create_trace_edges (insn); | |
647a1567 | 2597 | } |
45fba6d1 | 2598 | |
141618e2 | 2599 | add_cfi_insn = NULL; |
829bdd4b RH |
2600 | cur_row = NULL; |
2601 | cur_trace = NULL; | |
647a1567 RH |
2602 | } |
2603 | ||
829bdd4b | 2604 | /* Scan the function and create the initial set of CFI notes. */ |
647a1567 | 2605 | |
bc5612ed | 2606 | static void |
829bdd4b | 2607 | create_cfi_notes (void) |
647a1567 | 2608 | { |
829bdd4b | 2609 | dw_trace_info *ti; |
647a1567 | 2610 | |
829bdd4b RH |
2611 | gcc_checking_assert (queued_reg_saves == NULL); |
2612 | gcc_checking_assert (trace_work_list == NULL); | |
647a1567 | 2613 | |
829bdd4b RH |
2614 | /* Always begin at the entry trace. */ |
2615 | ti = VEC_index (dw_trace_info, trace_info, 0); | |
2616 | scan_trace (ti); | |
647a1567 | 2617 | |
829bdd4b RH |
2618 | while (!VEC_empty (dw_trace_info_ref, trace_work_list)) |
2619 | { | |
2620 | ti = VEC_pop (dw_trace_info_ref, trace_work_list); | |
2621 | scan_trace (ti); | |
647a1567 RH |
2622 | } |
2623 | ||
829bdd4b RH |
2624 | VEC_free (queued_reg_save, heap, queued_reg_saves); |
2625 | VEC_free (dw_trace_info_ref, heap, trace_work_list); | |
2626 | } | |
647a1567 | 2627 | |
200e10dc RH |
2628 | /* Return the insn before the first NOTE_INSN_CFI after START. */ |
2629 | ||
2630 | static rtx | |
2631 | before_next_cfi_note (rtx start) | |
2632 | { | |
2633 | rtx prev = start; | |
2634 | while (start) | |
2635 | { | |
2636 | if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI) | |
2637 | return prev; | |
2638 | prev = start; | |
2639 | start = NEXT_INSN (start); | |
2640 | } | |
2641 | gcc_unreachable (); | |
2642 | } | |
2643 | ||
829bdd4b | 2644 | /* Insert CFI notes between traces to properly change state between them. */ |
647a1567 | 2645 | |
829bdd4b RH |
2646 | static void |
2647 | connect_traces (void) | |
2648 | { | |
2649 | unsigned i, n = VEC_length (dw_trace_info, trace_info); | |
2650 | dw_trace_info *prev_ti, *ti; | |
2651 | ||
200e10dc RH |
2652 | /* ??? Ideally, we should have both queued and processed every trace. |
2653 | However the current representation of constant pools on various targets | |
2654 | is indistinguishable from unreachable code. Assume for the moment that | |
2655 | we can simply skip over such traces. */ | |
2656 | /* ??? Consider creating a DATA_INSN rtx code to indicate that | |
2657 | these are not "real" instructions, and should not be considered. | |
2658 | This could be generically useful for tablejump data as well. */ | |
2659 | /* Remove all unprocessed traces from the list. */ | |
2660 | for (i = n - 1; i > 0; --i) | |
2661 | { | |
2662 | ti = VEC_index (dw_trace_info, trace_info, i); | |
2663 | if (ti->beg_row == NULL) | |
2664 | { | |
2665 | VEC_ordered_remove (dw_trace_info, trace_info, i); | |
2666 | n -= 1; | |
2667 | } | |
2668 | else | |
2669 | gcc_assert (ti->end_row != NULL); | |
2670 | } | |
829bdd4b | 2671 | |
200e10dc RH |
2672 | /* Work from the end back to the beginning. This lets us easily insert |
2673 | remember/restore_state notes in the correct order wrt other notes. */ | |
2674 | prev_ti = VEC_index (dw_trace_info, trace_info, n - 1); | |
2675 | for (i = n - 1; i > 0; --i) | |
647a1567 | 2676 | { |
829bdd4b | 2677 | dw_cfi_row *old_row; |
647a1567 | 2678 | |
200e10dc RH |
2679 | ti = prev_ti; |
2680 | prev_ti = VEC_index (dw_trace_info, trace_info, i - 1); | |
647a1567 | 2681 | |
200e10dc | 2682 | add_cfi_insn = ti->head; |
829bdd4b RH |
2683 | |
2684 | /* In dwarf2out_switch_text_section, we'll begin a new FDE | |
2685 | for the portion of the function in the alternate text | |
2686 | section. The row state at the very beginning of that | |
2687 | new FDE will be exactly the row state from the CIE. */ | |
2688 | if (ti->switch_sections) | |
2689 | old_row = cie_cfi_row; | |
2690 | else | |
200e10dc RH |
2691 | { |
2692 | old_row = prev_ti->end_row; | |
2693 | /* If there's no change from the previous end state, fine. */ | |
2694 | if (cfi_row_equal_p (old_row, ti->beg_row)) | |
2695 | ; | |
2696 | /* Otherwise check for the common case of sharing state with | |
2697 | the beginning of an epilogue, but not the end. Insert | |
2698 | remember/restore opcodes in that case. */ | |
2699 | else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row)) | |
2700 | { | |
2701 | dw_cfi_ref cfi; | |
2702 | ||
2703 | /* Note that if we blindly insert the remember at the | |
2704 | start of the trace, we can wind up increasing the | |
2705 | size of the unwind info due to extra advance opcodes. | |
2706 | Instead, put the remember immediately before the next | |
2707 | state change. We know there must be one, because the | |
2708 | state at the beginning and head of the trace differ. */ | |
2709 | add_cfi_insn = before_next_cfi_note (prev_ti->head); | |
2710 | cfi = new_cfi (); | |
2711 | cfi->dw_cfi_opc = DW_CFA_remember_state; | |
2712 | add_cfi (cfi); | |
2713 | ||
2714 | add_cfi_insn = ti->head; | |
2715 | cfi = new_cfi (); | |
2716 | cfi->dw_cfi_opc = DW_CFA_restore_state; | |
2717 | add_cfi (cfi); | |
2718 | ||
2719 | old_row = prev_ti->beg_row; | |
2720 | } | |
2721 | /* Otherwise, we'll simply change state from the previous end. */ | |
2722 | } | |
829bdd4b | 2723 | |
829bdd4b RH |
2724 | change_cfi_row (old_row, ti->beg_row); |
2725 | ||
2726 | if (dump_file && add_cfi_insn != ti->head) | |
2727 | { | |
2728 | rtx note; | |
2729 | ||
200e10dc RH |
2730 | fprintf (dump_file, "Fixup between trace %u and %u:\n", |
2731 | prev_ti->id, ti->id); | |
829bdd4b RH |
2732 | |
2733 | note = ti->head; | |
2734 | do | |
2735 | { | |
2736 | note = NEXT_INSN (note); | |
2737 | gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI); | |
2738 | output_cfi_directive (dump_file, NOTE_CFI (note)); | |
2739 | } | |
2740 | while (note != add_cfi_insn); | |
2741 | } | |
2742 | } | |
647a1567 RH |
2743 | } |
2744 | ||
829bdd4b RH |
2745 | /* Set up the pseudo-cfg of instruction traces, as described at the |
2746 | block comment at the top of the file. */ | |
647a1567 | 2747 | |
bc5612ed | 2748 | static void |
829bdd4b | 2749 | create_pseudo_cfg (void) |
647a1567 | 2750 | { |
829bdd4b RH |
2751 | bool saw_barrier, switch_sections; |
2752 | dw_trace_info *ti; | |
2753 | rtx insn; | |
2754 | unsigned i; | |
2755 | ||
2756 | /* The first trace begins at the start of the function, | |
2757 | and begins with the CIE row state. */ | |
2758 | trace_info = VEC_alloc (dw_trace_info, heap, 16); | |
2759 | ti = VEC_quick_push (dw_trace_info, trace_info, NULL); | |
2760 | ||
2761 | memset (ti, 0, sizeof (*ti)); | |
2762 | ti->head = get_insns (); | |
2763 | ti->beg_row = cie_cfi_row; | |
2764 | ti->cfa_store = cie_cfi_row->cfa; | |
2765 | ti->cfa_temp.reg = INVALID_REGNUM; | |
2766 | if (cie_return_save) | |
2767 | VEC_safe_push (reg_saved_in_data, heap, | |
2768 | ti->regs_saved_in_regs, cie_return_save); | |
647a1567 | 2769 | |
829bdd4b RH |
2770 | /* Walk all the insns, collecting start of trace locations. */ |
2771 | saw_barrier = false; | |
2772 | switch_sections = false; | |
2773 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2774 | { | |
2775 | if (BARRIER_P (insn)) | |
2776 | saw_barrier = true; | |
2777 | else if (NOTE_P (insn) | |
2778 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
2779 | { | |
2780 | /* We should have just seen a barrier. */ | |
2781 | gcc_assert (saw_barrier); | |
2782 | switch_sections = true; | |
2783 | } | |
2784 | /* Watch out for save_point notes between basic blocks. | |
2785 | In particular, a note after a barrier. Do not record these, | |
2786 | delaying trace creation until the label. */ | |
2787 | else if (save_point_p (insn) | |
2788 | && (LABEL_P (insn) || !saw_barrier)) | |
2789 | { | |
2790 | ti = VEC_safe_push (dw_trace_info, heap, trace_info, NULL); | |
2791 | memset (ti, 0, sizeof (*ti)); | |
2792 | ti->head = insn; | |
2793 | ti->switch_sections = switch_sections; | |
200e10dc | 2794 | ti->id = VEC_length (dw_trace_info, trace_info) - 1; |
829bdd4b RH |
2795 | |
2796 | saw_barrier = false; | |
2797 | switch_sections = false; | |
2798 | } | |
2799 | } | |
2800 | ||
2801 | /* Create the trace index after we've finished building trace_info, | |
2802 | avoiding stale pointer problems due to reallocation. */ | |
2803 | trace_index = htab_create (VEC_length (dw_trace_info, trace_info), | |
2804 | dw_trace_info_hash, dw_trace_info_eq, NULL); | |
2805 | FOR_EACH_VEC_ELT (dw_trace_info, trace_info, i, ti) | |
2806 | { | |
2807 | void **slot; | |
647a1567 | 2808 | |
829bdd4b RH |
2809 | if (dump_file) |
2810 | fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", i, | |
2811 | rtx_name[(int) GET_CODE (ti->head)], INSN_UID (ti->head), | |
2812 | ti->switch_sections ? " (section switch)" : ""); | |
2813 | ||
2814 | slot = htab_find_slot_with_hash (trace_index, ti, | |
2815 | INSN_UID (ti->head), INSERT); | |
2816 | gcc_assert (*slot == NULL); | |
2817 | *slot = (void *) ti; | |
2818 | } | |
647a1567 | 2819 | } |
829bdd4b | 2820 | |
a8e5c0e7 RH |
2821 | /* Record the initial position of the return address. RTL is |
2822 | INCOMING_RETURN_ADDR_RTX. */ | |
2823 | ||
2824 | static void | |
2825 | initial_return_save (rtx rtl) | |
2826 | { | |
2827 | unsigned int reg = INVALID_REGNUM; | |
2828 | HOST_WIDE_INT offset = 0; | |
2829 | ||
2830 | switch (GET_CODE (rtl)) | |
2831 | { | |
2832 | case REG: | |
2833 | /* RA is in a register. */ | |
7263c6d7 | 2834 | reg = dwf_regno (rtl); |
a8e5c0e7 RH |
2835 | break; |
2836 | ||
2837 | case MEM: | |
2838 | /* RA is on the stack. */ | |
2839 | rtl = XEXP (rtl, 0); | |
2840 | switch (GET_CODE (rtl)) | |
2841 | { | |
2842 | case REG: | |
2843 | gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM); | |
2844 | offset = 0; | |
2845 | break; | |
2846 | ||
2847 | case PLUS: | |
2848 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
2849 | offset = INTVAL (XEXP (rtl, 1)); | |
2850 | break; | |
2851 | ||
2852 | case MINUS: | |
2853 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
2854 | offset = -INTVAL (XEXP (rtl, 1)); | |
2855 | break; | |
2856 | ||
2857 | default: | |
2858 | gcc_unreachable (); | |
2859 | } | |
2860 | ||
2861 | break; | |
2862 | ||
2863 | case PLUS: | |
2864 | /* The return address is at some offset from any value we can | |
2865 | actually load. For instance, on the SPARC it is in %i7+8. Just | |
2866 | ignore the offset for now; it doesn't matter for unwinding frames. */ | |
2867 | gcc_assert (CONST_INT_P (XEXP (rtl, 1))); | |
2868 | initial_return_save (XEXP (rtl, 0)); | |
2869 | return; | |
2870 | ||
2871 | default: | |
2872 | gcc_unreachable (); | |
2873 | } | |
2874 | ||
2875 | if (reg != DWARF_FRAME_RETURN_COLUMN) | |
2876 | { | |
2877 | if (reg != INVALID_REGNUM) | |
2878 | record_reg_saved_in_reg (rtl, pc_rtx); | |
f17d3401 | 2879 | reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset); |
a8e5c0e7 RH |
2880 | } |
2881 | } | |
647a1567 | 2882 | |
43215a89 RH |
2883 | static void |
2884 | create_cie_data (void) | |
2885 | { | |
2886 | dw_cfa_location loc; | |
2887 | dw_trace_info cie_trace; | |
2888 | ||
2889 | dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); | |
2890 | dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM); | |
2891 | ||
2892 | memset (&cie_trace, 0, sizeof(cie_trace)); | |
2893 | cur_trace = &cie_trace; | |
2894 | ||
2895 | add_cfi_vec = &cie_cfi_vec; | |
2896 | cie_cfi_row = cur_row = new_cfi_row (); | |
2897 | ||
2898 | /* On entry, the Canonical Frame Address is at SP. */ | |
2899 | memset(&loc, 0, sizeof (loc)); | |
2900 | loc.reg = dw_stack_pointer_regnum; | |
2901 | loc.offset = INCOMING_FRAME_SP_OFFSET; | |
2902 | def_cfa_1 (&loc); | |
2903 | ||
2904 | if (targetm.debug_unwind_info () == UI_DWARF2 | |
2905 | || targetm_common.except_unwind_info (&global_options) == UI_DWARF2) | |
2906 | { | |
2907 | initial_return_save (INCOMING_RETURN_ADDR_RTX); | |
2908 | ||
2909 | /* For a few targets, we have the return address incoming into a | |
2910 | register, but choose a different return column. This will result | |
2911 | in a DW_CFA_register for the return, and an entry in | |
2912 | regs_saved_in_regs to match. If the target later stores that | |
2913 | return address register to the stack, we want to be able to emit | |
2914 | the DW_CFA_offset against the return column, not the intermediate | |
2915 | save register. Save the contents of regs_saved_in_regs so that | |
2916 | we can re-initialize it at the start of each function. */ | |
2917 | switch (VEC_length (reg_saved_in_data, cie_trace.regs_saved_in_regs)) | |
2918 | { | |
2919 | case 0: | |
2920 | break; | |
2921 | case 1: | |
2922 | cie_return_save = ggc_alloc_reg_saved_in_data (); | |
2923 | *cie_return_save = *VEC_index (reg_saved_in_data, | |
2924 | cie_trace.regs_saved_in_regs, 0); | |
2925 | VEC_free (reg_saved_in_data, heap, cie_trace.regs_saved_in_regs); | |
2926 | break; | |
2927 | default: | |
2928 | gcc_unreachable (); | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | add_cfi_vec = NULL; | |
2933 | cur_row = NULL; | |
2934 | cur_trace = NULL; | |
2935 | } | |
2936 | ||
7644b3c7 RH |
2937 | /* Annotate the function with NOTE_INSN_CFI notes to record the CFI |
2938 | state at each location within the function. These notes will be | |
2939 | emitted during pass_final. */ | |
647a1567 | 2940 | |
7644b3c7 RH |
2941 | static unsigned int |
2942 | execute_dwarf2_frame (void) | |
647a1567 | 2943 | { |
7644b3c7 RH |
2944 | /* The first time we're called, compute the incoming frame state. */ |
2945 | if (cie_cfi_vec == NULL) | |
43215a89 | 2946 | create_cie_data (); |
3edb53aa | 2947 | |
7644b3c7 RH |
2948 | dwarf2out_alloc_current_fde (); |
2949 | ||
829bdd4b RH |
2950 | create_pseudo_cfg (); |
2951 | ||
7644b3c7 RH |
2952 | /* Do the work. */ |
2953 | create_cfi_notes (); | |
829bdd4b | 2954 | connect_traces (); |
7644b3c7 RH |
2955 | add_cfis_to_fde (); |
2956 | ||
829bdd4b RH |
2957 | /* Free all the data we allocated. */ |
2958 | { | |
2959 | size_t i; | |
2960 | dw_trace_info *ti; | |
647a1567 | 2961 | |
829bdd4b RH |
2962 | FOR_EACH_VEC_ELT (dw_trace_info, trace_info, i, ti) |
2963 | VEC_free (reg_saved_in_data, heap, ti->regs_saved_in_regs); | |
2964 | } | |
2965 | VEC_free (dw_trace_info, heap, trace_info); | |
2966 | ||
2967 | htab_delete (trace_index); | |
2968 | trace_index = NULL; | |
f17d3401 | 2969 | |
7644b3c7 | 2970 | return 0; |
647a1567 RH |
2971 | } |
2972 | \f | |
948d330e RH |
2973 | /* Convert a DWARF call frame info. operation to its string name */ |
2974 | ||
2975 | static const char * | |
2976 | dwarf_cfi_name (unsigned int cfi_opc) | |
2977 | { | |
2978 | switch (cfi_opc) | |
2979 | { | |
2980 | case DW_CFA_advance_loc: | |
2981 | return "DW_CFA_advance_loc"; | |
2982 | case DW_CFA_offset: | |
2983 | return "DW_CFA_offset"; | |
2984 | case DW_CFA_restore: | |
2985 | return "DW_CFA_restore"; | |
2986 | case DW_CFA_nop: | |
2987 | return "DW_CFA_nop"; | |
2988 | case DW_CFA_set_loc: | |
2989 | return "DW_CFA_set_loc"; | |
2990 | case DW_CFA_advance_loc1: | |
2991 | return "DW_CFA_advance_loc1"; | |
2992 | case DW_CFA_advance_loc2: | |
2993 | return "DW_CFA_advance_loc2"; | |
2994 | case DW_CFA_advance_loc4: | |
2995 | return "DW_CFA_advance_loc4"; | |
2996 | case DW_CFA_offset_extended: | |
2997 | return "DW_CFA_offset_extended"; | |
2998 | case DW_CFA_restore_extended: | |
2999 | return "DW_CFA_restore_extended"; | |
3000 | case DW_CFA_undefined: | |
3001 | return "DW_CFA_undefined"; | |
3002 | case DW_CFA_same_value: | |
3003 | return "DW_CFA_same_value"; | |
3004 | case DW_CFA_register: | |
3005 | return "DW_CFA_register"; | |
3006 | case DW_CFA_remember_state: | |
3007 | return "DW_CFA_remember_state"; | |
3008 | case DW_CFA_restore_state: | |
3009 | return "DW_CFA_restore_state"; | |
3010 | case DW_CFA_def_cfa: | |
3011 | return "DW_CFA_def_cfa"; | |
3012 | case DW_CFA_def_cfa_register: | |
3013 | return "DW_CFA_def_cfa_register"; | |
3014 | case DW_CFA_def_cfa_offset: | |
3015 | return "DW_CFA_def_cfa_offset"; | |
3016 | ||
3017 | /* DWARF 3 */ | |
3018 | case DW_CFA_def_cfa_expression: | |
3019 | return "DW_CFA_def_cfa_expression"; | |
3020 | case DW_CFA_expression: | |
3021 | return "DW_CFA_expression"; | |
3022 | case DW_CFA_offset_extended_sf: | |
3023 | return "DW_CFA_offset_extended_sf"; | |
3024 | case DW_CFA_def_cfa_sf: | |
3025 | return "DW_CFA_def_cfa_sf"; | |
3026 | case DW_CFA_def_cfa_offset_sf: | |
3027 | return "DW_CFA_def_cfa_offset_sf"; | |
3028 | ||
3029 | /* SGI/MIPS specific */ | |
3030 | case DW_CFA_MIPS_advance_loc8: | |
3031 | return "DW_CFA_MIPS_advance_loc8"; | |
3032 | ||
3033 | /* GNU extensions */ | |
3034 | case DW_CFA_GNU_window_save: | |
3035 | return "DW_CFA_GNU_window_save"; | |
3036 | case DW_CFA_GNU_args_size: | |
3037 | return "DW_CFA_GNU_args_size"; | |
3038 | case DW_CFA_GNU_negative_offset_extended: | |
3039 | return "DW_CFA_GNU_negative_offset_extended"; | |
3040 | ||
3041 | default: | |
3042 | return "DW_CFA_<unknown>"; | |
3043 | } | |
3044 | } | |
3045 | ||
3046 | /* This routine will generate the correct assembly data for a location | |
3047 | description based on a cfi entry with a complex address. */ | |
3048 | ||
3049 | static void | |
3050 | output_cfa_loc (dw_cfi_ref cfi, int for_eh) | |
3051 | { | |
3052 | dw_loc_descr_ref loc; | |
3053 | unsigned long size; | |
3054 | ||
3055 | if (cfi->dw_cfi_opc == DW_CFA_expression) | |
3056 | { | |
43215a89 | 3057 | unsigned r = |
948d330e RH |
3058 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); |
3059 | dw2_asm_output_data (1, r, NULL); | |
3060 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3061 | } | |
3062 | else | |
3063 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3064 | ||
3065 | /* Output the size of the block. */ | |
3066 | size = size_of_locs (loc); | |
3067 | dw2_asm_output_data_uleb128 (size, NULL); | |
3068 | ||
3069 | /* Now output the operations themselves. */ | |
3070 | output_loc_sequence (loc, for_eh); | |
3071 | } | |
3072 | ||
3073 | /* Similar, but used for .cfi_escape. */ | |
3074 | ||
3075 | static void | |
3076 | output_cfa_loc_raw (dw_cfi_ref cfi) | |
3077 | { | |
3078 | dw_loc_descr_ref loc; | |
3079 | unsigned long size; | |
3080 | ||
3081 | if (cfi->dw_cfi_opc == DW_CFA_expression) | |
3082 | { | |
43215a89 | 3083 | unsigned r = |
948d330e RH |
3084 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); |
3085 | fprintf (asm_out_file, "%#x,", r); | |
3086 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3087 | } | |
3088 | else | |
3089 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3090 | ||
3091 | /* Output the size of the block. */ | |
3092 | size = size_of_locs (loc); | |
3093 | dw2_asm_output_data_uleb128_raw (size); | |
3094 | fputc (',', asm_out_file); | |
3095 | ||
3096 | /* Now output the operations themselves. */ | |
3097 | output_loc_sequence_raw (loc); | |
3098 | } | |
3099 | ||
3100 | /* Output a Call Frame Information opcode and its operand(s). */ | |
3101 | ||
3102 | void | |
3103 | output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh) | |
3104 | { | |
3105 | unsigned long r; | |
3106 | HOST_WIDE_INT off; | |
3107 | ||
3108 | if (cfi->dw_cfi_opc == DW_CFA_advance_loc) | |
3109 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | |
3110 | | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)), | |
3111 | "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX, | |
3112 | ((unsigned HOST_WIDE_INT) | |
3113 | cfi->dw_cfi_oprnd1.dw_cfi_offset)); | |
3114 | else if (cfi->dw_cfi_opc == DW_CFA_offset) | |
3115 | { | |
3116 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3117 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3118 | "DW_CFA_offset, column %#lx", r); | |
3119 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3120 | dw2_asm_output_data_uleb128 (off, NULL); | |
3121 | } | |
3122 | else if (cfi->dw_cfi_opc == DW_CFA_restore) | |
3123 | { | |
3124 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3125 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3126 | "DW_CFA_restore, column %#lx", r); | |
3127 | } | |
3128 | else | |
3129 | { | |
3130 | dw2_asm_output_data (1, cfi->dw_cfi_opc, | |
3131 | "%s", dwarf_cfi_name (cfi->dw_cfi_opc)); | |
3132 | ||
3133 | switch (cfi->dw_cfi_opc) | |
3134 | { | |
3135 | case DW_CFA_set_loc: | |
3136 | if (for_eh) | |
3137 | dw2_asm_output_encoded_addr_rtx ( | |
3138 | ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0), | |
3139 | gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr), | |
3140 | false, NULL); | |
3141 | else | |
3142 | dw2_asm_output_addr (DWARF2_ADDR_SIZE, | |
3143 | cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL); | |
3144 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3145 | break; | |
3146 | ||
3147 | case DW_CFA_advance_loc1: | |
3148 | dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3149 | fde->dw_fde_current_label, NULL); | |
3150 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3151 | break; | |
3152 | ||
3153 | case DW_CFA_advance_loc2: | |
3154 | dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3155 | fde->dw_fde_current_label, NULL); | |
3156 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3157 | break; | |
3158 | ||
3159 | case DW_CFA_advance_loc4: | |
3160 | dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3161 | fde->dw_fde_current_label, NULL); | |
3162 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3163 | break; | |
3164 | ||
3165 | case DW_CFA_MIPS_advance_loc8: | |
3166 | dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3167 | fde->dw_fde_current_label, NULL); | |
3168 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3169 | break; | |
3170 | ||
3171 | case DW_CFA_offset_extended: | |
3172 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3173 | dw2_asm_output_data_uleb128 (r, NULL); | |
3174 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3175 | dw2_asm_output_data_uleb128 (off, NULL); | |
3176 | break; | |
3177 | ||
3178 | case DW_CFA_def_cfa: | |
3179 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3180 | dw2_asm_output_data_uleb128 (r, NULL); | |
3181 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL); | |
3182 | break; | |
3183 | ||
3184 | case DW_CFA_offset_extended_sf: | |
3185 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3186 | dw2_asm_output_data_uleb128 (r, NULL); | |
3187 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3188 | dw2_asm_output_data_sleb128 (off, NULL); | |
3189 | break; | |
3190 | ||
3191 | case DW_CFA_def_cfa_sf: | |
3192 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3193 | dw2_asm_output_data_uleb128 (r, NULL); | |
3194 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3195 | dw2_asm_output_data_sleb128 (off, NULL); | |
3196 | break; | |
3197 | ||
3198 | case DW_CFA_restore_extended: | |
3199 | case DW_CFA_undefined: | |
3200 | case DW_CFA_same_value: | |
3201 | case DW_CFA_def_cfa_register: | |
3202 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3203 | dw2_asm_output_data_uleb128 (r, NULL); | |
3204 | break; | |
3205 | ||
3206 | case DW_CFA_register: | |
3207 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3208 | dw2_asm_output_data_uleb128 (r, NULL); | |
3209 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh); | |
3210 | dw2_asm_output_data_uleb128 (r, NULL); | |
3211 | break; | |
3212 | ||
3213 | case DW_CFA_def_cfa_offset: | |
3214 | case DW_CFA_GNU_args_size: | |
3215 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL); | |
3216 | break; | |
3217 | ||
3218 | case DW_CFA_def_cfa_offset_sf: | |
3219 | off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3220 | dw2_asm_output_data_sleb128 (off, NULL); | |
3221 | break; | |
3222 | ||
3223 | case DW_CFA_GNU_window_save: | |
3224 | break; | |
3225 | ||
3226 | case DW_CFA_def_cfa_expression: | |
3227 | case DW_CFA_expression: | |
3228 | output_cfa_loc (cfi, for_eh); | |
3229 | break; | |
3230 | ||
3231 | case DW_CFA_GNU_negative_offset_extended: | |
3232 | /* Obsoleted by DW_CFA_offset_extended_sf. */ | |
3233 | gcc_unreachable (); | |
3234 | ||
3235 | default: | |
3236 | break; | |
3237 | } | |
3238 | } | |
3239 | } | |
3240 | ||
3241 | /* Similar, but do it via assembler directives instead. */ | |
3242 | ||
3243 | void | |
3244 | output_cfi_directive (FILE *f, dw_cfi_ref cfi) | |
3245 | { | |
3246 | unsigned long r, r2; | |
3247 | ||
3248 | switch (cfi->dw_cfi_opc) | |
3249 | { | |
3250 | case DW_CFA_advance_loc: | |
3251 | case DW_CFA_advance_loc1: | |
3252 | case DW_CFA_advance_loc2: | |
3253 | case DW_CFA_advance_loc4: | |
3254 | case DW_CFA_MIPS_advance_loc8: | |
3255 | case DW_CFA_set_loc: | |
3256 | /* Should only be created in a code path not followed when emitting | |
3257 | via directives. The assembler is going to take care of this for | |
3258 | us. But this routines is also used for debugging dumps, so | |
3259 | print something. */ | |
3260 | gcc_assert (f != asm_out_file); | |
3261 | fprintf (f, "\t.cfi_advance_loc\n"); | |
3262 | break; | |
3263 | ||
3264 | case DW_CFA_offset: | |
3265 | case DW_CFA_offset_extended: | |
3266 | case DW_CFA_offset_extended_sf: | |
3267 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3268 | fprintf (f, "\t.cfi_offset %lu, "HOST_WIDE_INT_PRINT_DEC"\n", | |
3269 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3270 | break; | |
3271 | ||
3272 | case DW_CFA_restore: | |
3273 | case DW_CFA_restore_extended: | |
3274 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3275 | fprintf (f, "\t.cfi_restore %lu\n", r); | |
3276 | break; | |
3277 | ||
3278 | case DW_CFA_undefined: | |
3279 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3280 | fprintf (f, "\t.cfi_undefined %lu\n", r); | |
3281 | break; | |
3282 | ||
3283 | case DW_CFA_same_value: | |
3284 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3285 | fprintf (f, "\t.cfi_same_value %lu\n", r); | |
3286 | break; | |
3287 | ||
3288 | case DW_CFA_def_cfa: | |
3289 | case DW_CFA_def_cfa_sf: | |
3290 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3291 | fprintf (f, "\t.cfi_def_cfa %lu, "HOST_WIDE_INT_PRINT_DEC"\n", | |
3292 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3293 | break; | |
3294 | ||
3295 | case DW_CFA_def_cfa_register: | |
3296 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3297 | fprintf (f, "\t.cfi_def_cfa_register %lu\n", r); | |
3298 | break; | |
3299 | ||
3300 | case DW_CFA_register: | |
3301 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3302 | r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1); | |
3303 | fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2); | |
3304 | break; | |
3305 | ||
3306 | case DW_CFA_def_cfa_offset: | |
3307 | case DW_CFA_def_cfa_offset_sf: | |
3308 | fprintf (f, "\t.cfi_def_cfa_offset " | |
3309 | HOST_WIDE_INT_PRINT_DEC"\n", | |
3310 | cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3311 | break; | |
3312 | ||
3313 | case DW_CFA_remember_state: | |
3314 | fprintf (f, "\t.cfi_remember_state\n"); | |
3315 | break; | |
3316 | case DW_CFA_restore_state: | |
3317 | fprintf (f, "\t.cfi_restore_state\n"); | |
3318 | break; | |
3319 | ||
3320 | case DW_CFA_GNU_args_size: | |
3321 | if (f == asm_out_file) | |
3322 | { | |
3323 | fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size); | |
3324 | dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3325 | if (flag_debug_asm) | |
3326 | fprintf (f, "\t%s args_size "HOST_WIDE_INT_PRINT_DEC, | |
3327 | ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3328 | fputc ('\n', f); | |
3329 | } | |
3330 | else | |
3331 | { | |
3332 | fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n", | |
3333 | cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3334 | } | |
3335 | break; | |
3336 | ||
3337 | case DW_CFA_GNU_window_save: | |
3338 | fprintf (f, "\t.cfi_window_save\n"); | |
3339 | break; | |
3340 | ||
3341 | case DW_CFA_def_cfa_expression: | |
3342 | if (f != asm_out_file) | |
3343 | { | |
3344 | fprintf (f, "\t.cfi_def_cfa_expression ...\n"); | |
3345 | break; | |
3346 | } | |
3347 | /* FALLTHRU */ | |
3348 | case DW_CFA_expression: | |
3349 | if (f != asm_out_file) | |
3350 | { | |
3351 | fprintf (f, "\t.cfi_cfa_expression ...\n"); | |
3352 | break; | |
3353 | } | |
3354 | fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc); | |
3355 | output_cfa_loc_raw (cfi); | |
3356 | fputc ('\n', f); | |
3357 | break; | |
3358 | ||
3359 | default: | |
3360 | gcc_unreachable (); | |
3361 | } | |
3362 | } | |
3363 | ||
3364 | void | |
3365 | dwarf2out_emit_cfi (dw_cfi_ref cfi) | |
3366 | { | |
3367 | if (dwarf2out_do_cfi_asm ()) | |
3368 | output_cfi_directive (asm_out_file, cfi); | |
3369 | } | |
a5d0ce89 RH |
3370 | |
3371 | static void | |
3372 | dump_cfi_row (FILE *f, dw_cfi_row *row) | |
3373 | { | |
3374 | dw_cfi_ref cfi; | |
3375 | unsigned i; | |
3376 | ||
3377 | cfi = row->cfa_cfi; | |
3378 | if (!cfi) | |
3379 | { | |
3380 | dw_cfa_location dummy; | |
3381 | memset(&dummy, 0, sizeof(dummy)); | |
3382 | dummy.reg = INVALID_REGNUM; | |
3383 | cfi = def_cfa_0 (&dummy, &row->cfa); | |
3384 | } | |
3385 | output_cfi_directive (f, cfi); | |
3386 | ||
3387 | FOR_EACH_VEC_ELT (dw_cfi_ref, row->reg_save, i, cfi) | |
3388 | if (cfi) | |
3389 | output_cfi_directive (f, cfi); | |
3390 | ||
3391 | fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n", | |
3392 | row->args_size); | |
3393 | } | |
3394 | ||
3395 | void debug_cfi_row (dw_cfi_row *row); | |
3396 | ||
3397 | void | |
3398 | debug_cfi_row (dw_cfi_row *row) | |
3399 | { | |
3400 | dump_cfi_row (stderr, row); | |
3401 | } | |
948d330e | 3402 | \f |
647a1567 | 3403 | |
7644b3c7 RH |
3404 | /* Save the result of dwarf2out_do_frame across PCH. |
3405 | This variable is tri-state, with 0 unset, >0 true, <0 false. */ | |
3406 | static GTY(()) signed char saved_do_cfi_asm = 0; | |
647a1567 RH |
3407 | |
3408 | /* Decide whether we want to emit frame unwind information for the current | |
3409 | translation unit. */ | |
3410 | ||
7644b3c7 | 3411 | bool |
647a1567 RH |
3412 | dwarf2out_do_frame (void) |
3413 | { | |
3414 | /* We want to emit correct CFA location expressions or lists, so we | |
3415 | have to return true if we're going to output debug info, even if | |
3416 | we're not going to output frame or unwind info. */ | |
3417 | if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG) | |
3418 | return true; | |
3419 | ||
7644b3c7 | 3420 | if (saved_do_cfi_asm > 0) |
647a1567 RH |
3421 | return true; |
3422 | ||
3423 | if (targetm.debug_unwind_info () == UI_DWARF2) | |
3424 | return true; | |
3425 | ||
3426 | if ((flag_unwind_tables || flag_exceptions) | |
3427 | && targetm_common.except_unwind_info (&global_options) == UI_DWARF2) | |
3428 | return true; | |
3429 | ||
3430 | return false; | |
3431 | } | |
3432 | ||
3433 | /* Decide whether to emit frame unwind via assembler directives. */ | |
3434 | ||
7644b3c7 | 3435 | bool |
647a1567 RH |
3436 | dwarf2out_do_cfi_asm (void) |
3437 | { | |
3438 | int enc; | |
3439 | ||
3440 | #ifdef MIPS_DEBUGGING_INFO | |
3441 | return false; | |
3442 | #endif | |
7644b3c7 RH |
3443 | |
3444 | if (saved_do_cfi_asm != 0) | |
3445 | return saved_do_cfi_asm > 0; | |
3446 | ||
3447 | /* Assume failure for a moment. */ | |
3448 | saved_do_cfi_asm = -1; | |
3449 | ||
647a1567 RH |
3450 | if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ()) |
3451 | return false; | |
3452 | if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) | |
3453 | return false; | |
3454 | ||
3455 | /* Make sure the personality encoding is one the assembler can support. | |
3456 | In particular, aligned addresses can't be handled. */ | |
3457 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1); | |
3458 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3459 | return false; | |
3460 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0); | |
3461 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3462 | return false; | |
3463 | ||
3464 | /* If we can't get the assembler to emit only .debug_frame, and we don't need | |
3465 | dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */ | |
3466 | if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE | |
3467 | && !flag_unwind_tables && !flag_exceptions | |
3468 | && targetm_common.except_unwind_info (&global_options) != UI_DWARF2) | |
3469 | return false; | |
3470 | ||
7644b3c7 RH |
3471 | /* Success! */ |
3472 | saved_do_cfi_asm = 1; | |
647a1567 RH |
3473 | return true; |
3474 | } | |
3475 | ||
7644b3c7 RH |
3476 | static bool |
3477 | gate_dwarf2_frame (void) | |
3478 | { | |
3479 | #ifndef HAVE_prologue | |
3480 | /* Targets which still implement the prologue in assembler text | |
3481 | cannot use the generic dwarf2 unwinding. */ | |
3482 | return false; | |
3483 | #endif | |
3484 | ||
3485 | /* ??? What to do for UI_TARGET unwinding? They might be able to benefit | |
3486 | from the optimized shrink-wrapping annotations that we will compute. | |
3487 | For now, only produce the CFI notes for dwarf2. */ | |
3488 | return dwarf2out_do_frame (); | |
3489 | } | |
3490 | ||
3491 | struct rtl_opt_pass pass_dwarf2_frame = | |
3492 | { | |
3493 | { | |
3494 | RTL_PASS, | |
3495 | "dwarf2", /* name */ | |
3496 | gate_dwarf2_frame, /* gate */ | |
3497 | execute_dwarf2_frame, /* execute */ | |
3498 | NULL, /* sub */ | |
3499 | NULL, /* next */ | |
3500 | 0, /* static_pass_number */ | |
3501 | TV_FINAL, /* tv_id */ | |
3502 | 0, /* properties_required */ | |
3503 | 0, /* properties_provided */ | |
3504 | 0, /* properties_destroyed */ | |
3505 | 0, /* todo_flags_start */ | |
3506 | 0 /* todo_flags_finish */ | |
3507 | } | |
3508 | }; | |
3509 | ||
647a1567 | 3510 | #include "gt-dwarf2cfi.h" |