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dcdf448e | 1 | /* Dwarf2 Call Frame Information helper routines. |
d353bf18 | 2 | Copyright (C) 1992-2015 Free Software Foundation, Inc. |
dcdf448e | 3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 3, or (at your option) any later | |
9 | version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
23 | #include "tm.h" | |
24 | #include "version.h" | |
25 | #include "flags.h" | |
26 | #include "rtl.h" | |
b20a8bb4 | 27 | #include "alias.h" |
28 | #include "symtab.h" | |
b20a8bb4 | 29 | #include "tree.h" |
30 | #include "stor-layout.h" | |
a3020f2f | 31 | #include "hard-reg-set.h" |
dcdf448e | 32 | #include "function.h" |
94ea8568 | 33 | #include "cfgbuild.h" |
dcdf448e | 34 | #include "dwarf2.h" |
35 | #include "dwarf2out.h" | |
36 | #include "dwarf2asm.h" | |
dcdf448e | 37 | #include "tm_p.h" |
38 | #include "target.h" | |
39 | #include "common/common-target.h" | |
40 | #include "tree-pass.h" | |
41 | ||
42 | #include "except.h" /* expand_builtin_dwarf_sp_column */ | |
d53441c8 | 43 | #include "insn-config.h" |
44 | #include "expmed.h" | |
45 | #include "dojump.h" | |
46 | #include "explow.h" | |
47 | #include "calls.h" | |
48 | #include "emit-rtl.h" | |
49 | #include "varasm.h" | |
50 | #include "stmt.h" | |
dcdf448e | 51 | #include "expr.h" /* init_return_column_size */ |
52 | #include "regs.h" /* expand_builtin_init_dwarf_reg_sizes */ | |
53 | #include "output.h" /* asm_out_file */ | |
54 | #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */ | |
55 | ||
56 | ||
57 | /* ??? Poison these here until it can be done generically. They've been | |
58 | totally replaced in this file; make sure it stays that way. */ | |
59 | #undef DWARF2_UNWIND_INFO | |
60 | #undef DWARF2_FRAME_INFO | |
61 | #if (GCC_VERSION >= 3000) | |
62 | #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO | |
63 | #endif | |
64 | ||
65 | #ifndef INCOMING_RETURN_ADDR_RTX | |
66 | #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX) | |
67 | #endif | |
68 | ||
dcdf448e | 69 | /* Maximum size (in bytes) of an artificially generated label. */ |
70 | #define MAX_ARTIFICIAL_LABEL_BYTES 30 | |
dcdf448e | 71 | \f |
eb93b3f4 | 72 | /* A collected description of an entire row of the abstract CFI table. */ |
73 | typedef struct GTY(()) dw_cfi_row_struct | |
74 | { | |
75 | /* The expression that computes the CFA, expressed in two different ways. | |
76 | The CFA member for the simple cases, and the full CFI expression for | |
77 | the complex cases. The later will be a DW_CFA_cfa_expression. */ | |
78 | dw_cfa_location cfa; | |
79 | dw_cfi_ref cfa_cfi; | |
80 | ||
81 | /* The expressions for any register column that is saved. */ | |
82 | cfi_vec reg_save; | |
eb93b3f4 | 83 | } dw_cfi_row; |
84 | ||
b1613fc3 | 85 | /* The caller's ORIG_REG is saved in SAVED_IN_REG. */ |
86 | typedef struct GTY(()) reg_saved_in_data_struct { | |
87 | rtx orig_reg; | |
88 | rtx saved_in_reg; | |
89 | } reg_saved_in_data; | |
90 | ||
b1613fc3 | 91 | |
92 | /* Since we no longer have a proper CFG, we're going to create a facsimile | |
93 | of one on the fly while processing the frame-related insns. | |
94 | ||
97c251e4 | 95 | We create dw_trace_info structures for each extended basic block beginning |
96 | and ending at a "save point". Save points are labels, barriers, certain | |
97 | notes, and of course the beginning and end of the function. | |
b1613fc3 | 98 | |
99 | As we encounter control transfer insns, we propagate the "current" | |
97c251e4 | 100 | row state across the edges to the starts of traces. When checking is |
101 | enabled, we validate that we propagate the same data from all sources. | |
b1613fc3 | 102 | |
103 | All traces are members of the TRACE_INFO array, in the order in which | |
104 | they appear in the instruction stream. | |
105 | ||
97c251e4 | 106 | All save points are present in the TRACE_INDEX hash, mapping the insn |
107 | starting a trace to the dw_trace_info describing the trace. */ | |
b1613fc3 | 108 | |
109 | typedef struct | |
110 | { | |
97c251e4 | 111 | /* The insn that begins the trace. */ |
f6d940f9 | 112 | rtx_insn *head; |
b1613fc3 | 113 | |
114 | /* The row state at the beginning and end of the trace. */ | |
97c251e4 | 115 | dw_cfi_row *beg_row, *end_row; |
116 | ||
dfe00a8f | 117 | /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find |
118 | while scanning insns. However, the args_size value is irrelevant at | |
119 | any point except can_throw_internal_p insns. Therefore the "delay" | |
120 | sizes the values that must actually be emitted for this trace. */ | |
121 | HOST_WIDE_INT beg_true_args_size, end_true_args_size; | |
122 | HOST_WIDE_INT beg_delay_args_size, end_delay_args_size; | |
123 | ||
124 | /* The first EH insn in the trace, where beg_delay_args_size must be set. */ | |
4cd001d5 | 125 | rtx_insn *eh_head; |
dfe00a8f | 126 | |
b1613fc3 | 127 | /* The following variables contain data used in interpreting frame related |
128 | expressions. These are not part of the "real" row state as defined by | |
129 | Dwarf, but it seems like they need to be propagated into a trace in case | |
130 | frame related expressions have been sunk. */ | |
131 | /* ??? This seems fragile. These variables are fragments of a larger | |
132 | expression. If we do not keep the entire expression together, we risk | |
133 | not being able to put it together properly. Consider forcing targets | |
134 | to generate self-contained expressions and dropping all of the magic | |
135 | interpretation code in this file. Or at least refusing to shrink wrap | |
136 | any frame related insn that doesn't contain a complete expression. */ | |
137 | ||
138 | /* The register used for saving registers to the stack, and its offset | |
139 | from the CFA. */ | |
140 | dw_cfa_location cfa_store; | |
141 | ||
142 | /* A temporary register holding an integral value used in adjusting SP | |
143 | or setting up the store_reg. The "offset" field holds the integer | |
144 | value, not an offset. */ | |
145 | dw_cfa_location cfa_temp; | |
146 | ||
147 | /* A set of registers saved in other registers. This is the inverse of | |
148 | the row->reg_save info, if the entry is a DW_CFA_register. This is | |
149 | implemented as a flat array because it normally contains zero or 1 | |
150 | entry, depending on the target. IA-64 is the big spender here, using | |
151 | a maximum of 5 entries. */ | |
f1f41a6c | 152 | vec<reg_saved_in_data> regs_saved_in_regs; |
b1613fc3 | 153 | |
ce4a64fd | 154 | /* An identifier for this trace. Used only for debugging dumps. */ |
155 | unsigned id; | |
156 | ||
157 | /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */ | |
158 | bool switch_sections; | |
dfe00a8f | 159 | |
160 | /* True if we've seen different values incoming to beg_true_args_size. */ | |
161 | bool args_size_undefined; | |
b1613fc3 | 162 | } dw_trace_info; |
163 | ||
b1613fc3 | 164 | |
97c251e4 | 165 | typedef dw_trace_info *dw_trace_info_ref; |
b1613fc3 | 166 | |
b1613fc3 | 167 | |
d9dd21a8 | 168 | /* Hashtable helpers. */ |
169 | ||
770ff93b | 170 | struct trace_info_hasher : nofree_ptr_hash <dw_trace_info> |
d9dd21a8 | 171 | { |
9969c043 | 172 | static inline hashval_t hash (const dw_trace_info *); |
173 | static inline bool equal (const dw_trace_info *, const dw_trace_info *); | |
d9dd21a8 | 174 | }; |
175 | ||
176 | inline hashval_t | |
9969c043 | 177 | trace_info_hasher::hash (const dw_trace_info *ti) |
d9dd21a8 | 178 | { |
179 | return INSN_UID (ti->head); | |
180 | } | |
181 | ||
182 | inline bool | |
9969c043 | 183 | trace_info_hasher::equal (const dw_trace_info *a, const dw_trace_info *b) |
d9dd21a8 | 184 | { |
185 | return a->head == b->head; | |
186 | } | |
187 | ||
188 | ||
b1613fc3 | 189 | /* The variables making up the pseudo-cfg, as described above. */ |
f1f41a6c | 190 | static vec<dw_trace_info> trace_info; |
191 | static vec<dw_trace_info_ref> trace_work_list; | |
c1f445d2 | 192 | static hash_table<trace_info_hasher> *trace_index; |
b1613fc3 | 193 | |
dcdf448e | 194 | /* A vector of call frame insns for the CIE. */ |
195 | cfi_vec cie_cfi_vec; | |
196 | ||
eb93b3f4 | 197 | /* The state of the first row of the FDE table, which includes the |
198 | state provided by the CIE. */ | |
1b1ea44c | 199 | static GTY(()) dw_cfi_row *cie_cfi_row; |
eb93b3f4 | 200 | |
b1613fc3 | 201 | static GTY(()) reg_saved_in_data *cie_return_save; |
202 | ||
dcdf448e | 203 | static GTY(()) unsigned long dwarf2out_cfi_label_num; |
204 | ||
46346a52 | 205 | /* The insn after which a new CFI note should be emitted. */ |
c0937357 | 206 | static rtx_insn *add_cfi_insn; |
46346a52 | 207 | |
d4898332 | 208 | /* When non-null, add_cfi will add the CFI to this vector. */ |
209 | static cfi_vec *add_cfi_vec; | |
210 | ||
b1613fc3 | 211 | /* The current instruction trace. */ |
212 | static dw_trace_info *cur_trace; | |
213 | ||
214 | /* The current, i.e. most recently generated, row of the CFI table. */ | |
215 | static dw_cfi_row *cur_row; | |
216 | ||
dfe00a8f | 217 | /* A copy of the current CFA, for use during the processing of a |
218 | single insn. */ | |
219 | static dw_cfa_location *cur_cfa; | |
220 | ||
b1613fc3 | 221 | /* We delay emitting a register save until either (a) we reach the end |
222 | of the prologue or (b) the register is clobbered. This clusters | |
223 | register saves so that there are fewer pc advances. */ | |
224 | ||
225 | typedef struct { | |
226 | rtx reg; | |
227 | rtx saved_reg; | |
228 | HOST_WIDE_INT cfa_offset; | |
229 | } queued_reg_save; | |
230 | ||
b1613fc3 | 231 | |
f1f41a6c | 232 | static vec<queued_reg_save> queued_reg_saves; |
b1613fc3 | 233 | |
46346a52 | 234 | /* True if any CFI directives were emitted at the current insn. */ |
235 | static bool any_cfis_emitted; | |
26a649dd | 236 | |
237 | /* Short-hand for commonly used register numbers. */ | |
238 | static unsigned dw_stack_pointer_regnum; | |
239 | static unsigned dw_frame_pointer_regnum; | |
dcdf448e | 240 | \f |
241 | /* Hook used by __throw. */ | |
242 | ||
243 | rtx | |
244 | expand_builtin_dwarf_sp_column (void) | |
245 | { | |
26a649dd | 246 | unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); |
dcdf448e | 247 | return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1)); |
248 | } | |
249 | ||
250 | /* MEM is a memory reference for the register size table, each element of | |
251 | which has mode MODE. Initialize column C as a return address column. */ | |
252 | ||
253 | static void | |
3754d046 | 254 | init_return_column_size (machine_mode mode, rtx mem, unsigned int c) |
dcdf448e | 255 | { |
256 | HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode); | |
257 | HOST_WIDE_INT size = GET_MODE_SIZE (Pmode); | |
d11aedc7 | 258 | emit_move_insn (adjust_address (mem, mode, offset), |
259 | gen_int_mode (size, mode)); | |
dcdf448e | 260 | } |
261 | ||
4fd39f13 | 262 | /* Datastructure used by expand_builtin_init_dwarf_reg_sizes and |
263 | init_one_dwarf_reg_size to communicate on what has been done by the | |
264 | latter. */ | |
265 | ||
266 | typedef struct | |
267 | { | |
268 | /* Whether the dwarf return column was initialized. */ | |
269 | bool wrote_return_column; | |
270 | ||
271 | /* For each hard register REGNO, whether init_one_dwarf_reg_size | |
272 | was given REGNO to process already. */ | |
273 | bool processed_regno [FIRST_PSEUDO_REGISTER]; | |
274 | ||
275 | } init_one_dwarf_reg_state; | |
276 | ||
277 | /* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to | |
278 | initialize the dwarf register size table entry corresponding to register | |
279 | REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to | |
280 | use for the size entry to initialize, and INIT_STATE is the communication | |
281 | datastructure conveying what we're doing to our caller. */ | |
282 | ||
283 | static | |
284 | void init_one_dwarf_reg_size (int regno, machine_mode regmode, | |
285 | rtx table, machine_mode slotmode, | |
286 | init_one_dwarf_reg_state *init_state) | |
287 | { | |
288 | const unsigned int dnum = DWARF_FRAME_REGNUM (regno); | |
289 | const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); | |
c0235a33 | 290 | const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum); |
4fd39f13 | 291 | |
c0235a33 | 292 | const HOST_WIDE_INT slotoffset = dcol * GET_MODE_SIZE (slotmode); |
4fd39f13 | 293 | const HOST_WIDE_INT regsize = GET_MODE_SIZE (regmode); |
294 | ||
295 | init_state->processed_regno[regno] = true; | |
296 | ||
297 | if (rnum >= DWARF_FRAME_REGISTERS) | |
298 | return; | |
299 | ||
300 | if (dnum == DWARF_FRAME_RETURN_COLUMN) | |
301 | { | |
302 | if (regmode == VOIDmode) | |
303 | return; | |
304 | init_state->wrote_return_column = true; | |
305 | } | |
306 | ||
307 | if (slotoffset < 0) | |
308 | return; | |
309 | ||
310 | emit_move_insn (adjust_address (table, slotmode, slotoffset), | |
311 | gen_int_mode (regsize, slotmode)); | |
312 | } | |
313 | ||
314 | /* Generate code to initialize the dwarf register size table located | |
315 | at the provided ADDRESS. */ | |
dcdf448e | 316 | |
317 | void | |
318 | expand_builtin_init_dwarf_reg_sizes (tree address) | |
319 | { | |
320 | unsigned int i; | |
3754d046 | 321 | machine_mode mode = TYPE_MODE (char_type_node); |
dcdf448e | 322 | rtx addr = expand_normal (address); |
323 | rtx mem = gen_rtx_MEM (BLKmode, addr); | |
4fd39f13 | 324 | |
325 | init_one_dwarf_reg_state init_state; | |
326 | ||
327 | memset ((char *)&init_state, 0, sizeof (init_state)); | |
dcdf448e | 328 | |
329 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
330 | { | |
4fd39f13 | 331 | machine_mode save_mode; |
332 | rtx span; | |
dcdf448e | 333 | |
4fd39f13 | 334 | /* No point in processing a register multiple times. This could happen |
335 | with register spans, e.g. when a reg is first processed as a piece of | |
336 | a span, then as a register on its own later on. */ | |
337 | ||
338 | if (init_state.processed_regno[i]) | |
339 | continue; | |
340 | ||
341 | save_mode = targetm.dwarf_frame_reg_mode (i); | |
342 | span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)); | |
dcdf448e | 343 | |
4fd39f13 | 344 | if (!span) |
345 | init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state); | |
346 | else | |
347 | { | |
348 | for (int si = 0; si < XVECLEN (span, 0); si++) | |
dcdf448e | 349 | { |
4fd39f13 | 350 | rtx reg = XVECEXP (span, 0, si); |
dcdf448e | 351 | |
4fd39f13 | 352 | init_one_dwarf_reg_size |
353 | (REGNO (reg), GET_MODE (reg), mem, mode, &init_state); | |
354 | } | |
dcdf448e | 355 | } |
356 | } | |
357 | ||
4fd39f13 | 358 | if (!init_state.wrote_return_column) |
dcdf448e | 359 | init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); |
360 | ||
361 | #ifdef DWARF_ALT_FRAME_RETURN_COLUMN | |
362 | init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN); | |
363 | #endif | |
364 | ||
365 | targetm.init_dwarf_reg_sizes_extra (address); | |
366 | } | |
367 | ||
97c251e4 | 368 | \f |
97c251e4 | 369 | static dw_trace_info * |
f6d940f9 | 370 | get_trace_info (rtx_insn *insn) |
97c251e4 | 371 | { |
372 | dw_trace_info dummy; | |
373 | dummy.head = insn; | |
c1f445d2 | 374 | return trace_index->find_with_hash (&dummy, INSN_UID (insn)); |
97c251e4 | 375 | } |
376 | ||
377 | static bool | |
f6d940f9 | 378 | save_point_p (rtx_insn *insn) |
97c251e4 | 379 | { |
380 | /* Labels, except those that are really jump tables. */ | |
381 | if (LABEL_P (insn)) | |
382 | return inside_basic_block_p (insn); | |
383 | ||
384 | /* We split traces at the prologue/epilogue notes because those | |
385 | are points at which the unwind info is usually stable. This | |
386 | makes it easier to find spots with identical unwind info so | |
387 | that we can use remember/restore_state opcodes. */ | |
388 | if (NOTE_P (insn)) | |
389 | switch (NOTE_KIND (insn)) | |
390 | { | |
391 | case NOTE_INSN_PROLOGUE_END: | |
392 | case NOTE_INSN_EPILOGUE_BEG: | |
393 | return true; | |
394 | } | |
395 | ||
396 | return false; | |
397 | } | |
398 | ||
dcdf448e | 399 | /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */ |
400 | ||
401 | static inline HOST_WIDE_INT | |
402 | div_data_align (HOST_WIDE_INT off) | |
403 | { | |
404 | HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT; | |
405 | gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off); | |
406 | return r; | |
407 | } | |
408 | ||
409 | /* Return true if we need a signed version of a given opcode | |
410 | (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */ | |
411 | ||
412 | static inline bool | |
413 | need_data_align_sf_opcode (HOST_WIDE_INT off) | |
414 | { | |
415 | return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0; | |
416 | } | |
417 | ||
418 | /* Return a pointer to a newly allocated Call Frame Instruction. */ | |
419 | ||
420 | static inline dw_cfi_ref | |
421 | new_cfi (void) | |
422 | { | |
25a27413 | 423 | dw_cfi_ref cfi = ggc_alloc<dw_cfi_node> (); |
dcdf448e | 424 | |
425 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0; | |
426 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0; | |
427 | ||
428 | return cfi; | |
429 | } | |
430 | ||
eb93b3f4 | 431 | /* Return a newly allocated CFI row, with no defined data. */ |
432 | ||
1b1ea44c | 433 | static dw_cfi_row * |
eb93b3f4 | 434 | new_cfi_row (void) |
435 | { | |
25a27413 | 436 | dw_cfi_row *row = ggc_cleared_alloc<dw_cfi_row> (); |
eb93b3f4 | 437 | |
438 | row->cfa.reg = INVALID_REGNUM; | |
439 | ||
440 | return row; | |
441 | } | |
442 | ||
443 | /* Return a copy of an existing CFI row. */ | |
444 | ||
1b1ea44c | 445 | static dw_cfi_row * |
446 | copy_cfi_row (dw_cfi_row *src) | |
eb93b3f4 | 447 | { |
25a27413 | 448 | dw_cfi_row *dst = ggc_alloc<dw_cfi_row> (); |
eb93b3f4 | 449 | |
450 | *dst = *src; | |
f1f41a6c | 451 | dst->reg_save = vec_safe_copy (src->reg_save); |
eb93b3f4 | 452 | |
453 | return dst; | |
454 | } | |
455 | ||
c746c5c3 | 456 | /* Generate a new label for the CFI info to refer to. */ |
dcdf448e | 457 | |
458 | static char * | |
c746c5c3 | 459 | dwarf2out_cfi_label (void) |
dcdf448e | 460 | { |
c746c5c3 | 461 | int num = dwarf2out_cfi_label_num++; |
462 | char label[20]; | |
dcdf448e | 463 | |
c746c5c3 | 464 | ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num); |
dcdf448e | 465 | |
c746c5c3 | 466 | return xstrdup (label); |
dcdf448e | 467 | } |
468 | ||
d4898332 | 469 | /* Add CFI either to the current insn stream or to a vector, or both. */ |
dcdf448e | 470 | |
471 | static void | |
d4898332 | 472 | add_cfi (dw_cfi_ref cfi) |
dcdf448e | 473 | { |
c746c5c3 | 474 | any_cfis_emitted = true; |
7b1c31a0 | 475 | |
476 | if (add_cfi_insn != NULL) | |
dcdf448e | 477 | { |
7b1c31a0 | 478 | add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn); |
479 | NOTE_CFI (add_cfi_insn) = cfi; | |
dcdf448e | 480 | } |
7b1c31a0 | 481 | |
d4898332 | 482 | if (add_cfi_vec != NULL) |
f1f41a6c | 483 | vec_safe_push (*add_cfi_vec, cfi); |
dcdf448e | 484 | } |
485 | ||
0b3b5cad | 486 | static void |
487 | add_cfi_args_size (HOST_WIDE_INT size) | |
488 | { | |
489 | dw_cfi_ref cfi = new_cfi (); | |
490 | ||
dfe00a8f | 491 | /* While we can occasionally have args_size < 0 internally, this state |
492 | should not persist at a point we actually need an opcode. */ | |
493 | gcc_assert (size >= 0); | |
494 | ||
0b3b5cad | 495 | cfi->dw_cfi_opc = DW_CFA_GNU_args_size; |
496 | cfi->dw_cfi_oprnd1.dw_cfi_offset = size; | |
497 | ||
498 | add_cfi (cfi); | |
499 | } | |
500 | ||
501 | static void | |
502 | add_cfi_restore (unsigned reg) | |
503 | { | |
504 | dw_cfi_ref cfi = new_cfi (); | |
505 | ||
506 | cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore); | |
507 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
508 | ||
509 | add_cfi (cfi); | |
510 | } | |
511 | ||
e9fe542d | 512 | /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating |
513 | that the register column is no longer saved. */ | |
514 | ||
515 | static void | |
1b1ea44c | 516 | update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi) |
e9fe542d | 517 | { |
f1f41a6c | 518 | if (vec_safe_length (row->reg_save) <= column) |
519 | vec_safe_grow_cleared (row->reg_save, column + 1); | |
520 | (*row->reg_save)[column] = cfi; | |
e9fe542d | 521 | } |
522 | ||
dcdf448e | 523 | /* This function fills in aa dw_cfa_location structure from a dwarf location |
524 | descriptor sequence. */ | |
525 | ||
526 | static void | |
b3e7c666 | 527 | get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_node *loc) |
dcdf448e | 528 | { |
b3e7c666 | 529 | struct dw_loc_descr_node *ptr; |
dcdf448e | 530 | cfa->offset = 0; |
531 | cfa->base_offset = 0; | |
532 | cfa->indirect = 0; | |
533 | cfa->reg = -1; | |
534 | ||
535 | for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next) | |
536 | { | |
537 | enum dwarf_location_atom op = ptr->dw_loc_opc; | |
538 | ||
539 | switch (op) | |
540 | { | |
541 | case DW_OP_reg0: | |
542 | case DW_OP_reg1: | |
543 | case DW_OP_reg2: | |
544 | case DW_OP_reg3: | |
545 | case DW_OP_reg4: | |
546 | case DW_OP_reg5: | |
547 | case DW_OP_reg6: | |
548 | case DW_OP_reg7: | |
549 | case DW_OP_reg8: | |
550 | case DW_OP_reg9: | |
551 | case DW_OP_reg10: | |
552 | case DW_OP_reg11: | |
553 | case DW_OP_reg12: | |
554 | case DW_OP_reg13: | |
555 | case DW_OP_reg14: | |
556 | case DW_OP_reg15: | |
557 | case DW_OP_reg16: | |
558 | case DW_OP_reg17: | |
559 | case DW_OP_reg18: | |
560 | case DW_OP_reg19: | |
561 | case DW_OP_reg20: | |
562 | case DW_OP_reg21: | |
563 | case DW_OP_reg22: | |
564 | case DW_OP_reg23: | |
565 | case DW_OP_reg24: | |
566 | case DW_OP_reg25: | |
567 | case DW_OP_reg26: | |
568 | case DW_OP_reg27: | |
569 | case DW_OP_reg28: | |
570 | case DW_OP_reg29: | |
571 | case DW_OP_reg30: | |
572 | case DW_OP_reg31: | |
573 | cfa->reg = op - DW_OP_reg0; | |
574 | break; | |
575 | case DW_OP_regx: | |
576 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
577 | break; | |
578 | case DW_OP_breg0: | |
579 | case DW_OP_breg1: | |
580 | case DW_OP_breg2: | |
581 | case DW_OP_breg3: | |
582 | case DW_OP_breg4: | |
583 | case DW_OP_breg5: | |
584 | case DW_OP_breg6: | |
585 | case DW_OP_breg7: | |
586 | case DW_OP_breg8: | |
587 | case DW_OP_breg9: | |
588 | case DW_OP_breg10: | |
589 | case DW_OP_breg11: | |
590 | case DW_OP_breg12: | |
591 | case DW_OP_breg13: | |
592 | case DW_OP_breg14: | |
593 | case DW_OP_breg15: | |
594 | case DW_OP_breg16: | |
595 | case DW_OP_breg17: | |
596 | case DW_OP_breg18: | |
597 | case DW_OP_breg19: | |
598 | case DW_OP_breg20: | |
599 | case DW_OP_breg21: | |
600 | case DW_OP_breg22: | |
601 | case DW_OP_breg23: | |
602 | case DW_OP_breg24: | |
603 | case DW_OP_breg25: | |
604 | case DW_OP_breg26: | |
605 | case DW_OP_breg27: | |
606 | case DW_OP_breg28: | |
607 | case DW_OP_breg29: | |
608 | case DW_OP_breg30: | |
609 | case DW_OP_breg31: | |
610 | cfa->reg = op - DW_OP_breg0; | |
611 | cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int; | |
612 | break; | |
613 | case DW_OP_bregx: | |
614 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
615 | cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int; | |
616 | break; | |
617 | case DW_OP_deref: | |
618 | cfa->indirect = 1; | |
619 | break; | |
620 | case DW_OP_plus_uconst: | |
621 | cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned; | |
622 | break; | |
623 | default: | |
624 | gcc_unreachable (); | |
625 | } | |
626 | } | |
627 | } | |
628 | ||
4a7a4715 | 629 | /* Find the previous value for the CFA, iteratively. CFI is the opcode |
630 | to interpret, *LOC will be updated as necessary, *REMEMBER is used for | |
631 | one level of remember/restore state processing. */ | |
dcdf448e | 632 | |
633 | void | |
634 | lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember) | |
635 | { | |
636 | switch (cfi->dw_cfi_opc) | |
637 | { | |
638 | case DW_CFA_def_cfa_offset: | |
639 | case DW_CFA_def_cfa_offset_sf: | |
640 | loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset; | |
641 | break; | |
642 | case DW_CFA_def_cfa_register: | |
643 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
644 | break; | |
645 | case DW_CFA_def_cfa: | |
646 | case DW_CFA_def_cfa_sf: | |
647 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
648 | loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset; | |
649 | break; | |
650 | case DW_CFA_def_cfa_expression: | |
651 | get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc); | |
652 | break; | |
653 | ||
654 | case DW_CFA_remember_state: | |
655 | gcc_assert (!remember->in_use); | |
656 | *remember = *loc; | |
657 | remember->in_use = 1; | |
658 | break; | |
659 | case DW_CFA_restore_state: | |
660 | gcc_assert (remember->in_use); | |
661 | *loc = *remember; | |
662 | remember->in_use = 0; | |
663 | break; | |
664 | ||
665 | default: | |
666 | break; | |
667 | } | |
668 | } | |
669 | ||
dcdf448e | 670 | /* Determine if two dw_cfa_location structures define the same data. */ |
671 | ||
672 | bool | |
673 | cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2) | |
674 | { | |
675 | return (loc1->reg == loc2->reg | |
676 | && loc1->offset == loc2->offset | |
677 | && loc1->indirect == loc2->indirect | |
678 | && (loc1->indirect == 0 | |
679 | || loc1->base_offset == loc2->base_offset)); | |
680 | } | |
681 | ||
0b3b5cad | 682 | /* Determine if two CFI operands are identical. */ |
dcdf448e | 683 | |
0b3b5cad | 684 | static bool |
685 | cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b) | |
dcdf448e | 686 | { |
0b3b5cad | 687 | switch (t) |
688 | { | |
689 | case dw_cfi_oprnd_unused: | |
690 | return true; | |
691 | case dw_cfi_oprnd_reg_num: | |
692 | return a->dw_cfi_reg_num == b->dw_cfi_reg_num; | |
693 | case dw_cfi_oprnd_offset: | |
694 | return a->dw_cfi_offset == b->dw_cfi_offset; | |
695 | case dw_cfi_oprnd_addr: | |
696 | return (a->dw_cfi_addr == b->dw_cfi_addr | |
697 | || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0); | |
698 | case dw_cfi_oprnd_loc: | |
699 | return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc); | |
700 | } | |
701 | gcc_unreachable (); | |
702 | } | |
dcdf448e | 703 | |
0b3b5cad | 704 | /* Determine if two CFI entries are identical. */ |
705 | ||
706 | static bool | |
707 | cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b) | |
708 | { | |
709 | enum dwarf_call_frame_info opc; | |
710 | ||
711 | /* Make things easier for our callers, including missing operands. */ | |
712 | if (a == b) | |
713 | return true; | |
714 | if (a == NULL || b == NULL) | |
715 | return false; | |
716 | ||
717 | /* Obviously, the opcodes must match. */ | |
718 | opc = a->dw_cfi_opc; | |
719 | if (opc != b->dw_cfi_opc) | |
720 | return false; | |
721 | ||
722 | /* Compare the two operands, re-using the type of the operands as | |
723 | already exposed elsewhere. */ | |
724 | return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc), | |
725 | &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1) | |
726 | && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc), | |
727 | &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2)); | |
728 | } | |
729 | ||
97c251e4 | 730 | /* Determine if two CFI_ROW structures are identical. */ |
731 | ||
732 | static bool | |
733 | cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b) | |
734 | { | |
735 | size_t i, n_a, n_b, n_max; | |
736 | ||
737 | if (a->cfa_cfi) | |
738 | { | |
739 | if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi)) | |
740 | return false; | |
741 | } | |
742 | else if (!cfa_equal_p (&a->cfa, &b->cfa)) | |
743 | return false; | |
744 | ||
f1f41a6c | 745 | n_a = vec_safe_length (a->reg_save); |
746 | n_b = vec_safe_length (b->reg_save); | |
97c251e4 | 747 | n_max = MAX (n_a, n_b); |
748 | ||
749 | for (i = 0; i < n_max; ++i) | |
750 | { | |
751 | dw_cfi_ref r_a = NULL, r_b = NULL; | |
752 | ||
753 | if (i < n_a) | |
f1f41a6c | 754 | r_a = (*a->reg_save)[i]; |
97c251e4 | 755 | if (i < n_b) |
f1f41a6c | 756 | r_b = (*b->reg_save)[i]; |
97c251e4 | 757 | |
758 | if (!cfi_equal_p (r_a, r_b)) | |
759 | return false; | |
760 | } | |
761 | ||
762 | return true; | |
763 | } | |
764 | ||
0b3b5cad | 765 | /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining |
766 | what opcode to emit. Returns the CFI opcode to effect the change, or | |
767 | NULL if NEW_CFA == OLD_CFA. */ | |
768 | ||
769 | static dw_cfi_ref | |
770 | def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa) | |
771 | { | |
772 | dw_cfi_ref cfi; | |
dcdf448e | 773 | |
dcdf448e | 774 | /* If nothing changed, no need to issue any call frame instructions. */ |
0b3b5cad | 775 | if (cfa_equal_p (old_cfa, new_cfa)) |
776 | return NULL; | |
dcdf448e | 777 | |
778 | cfi = new_cfi (); | |
779 | ||
0b3b5cad | 780 | if (new_cfa->reg == old_cfa->reg && !new_cfa->indirect && !old_cfa->indirect) |
dcdf448e | 781 | { |
782 | /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating | |
783 | the CFA register did not change but the offset did. The data | |
784 | factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or | |
785 | in the assembler via the .cfi_def_cfa_offset directive. */ | |
0b3b5cad | 786 | if (new_cfa->offset < 0) |
dcdf448e | 787 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf; |
788 | else | |
789 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset; | |
0b3b5cad | 790 | cfi->dw_cfi_oprnd1.dw_cfi_offset = new_cfa->offset; |
dcdf448e | 791 | } |
0b3b5cad | 792 | else if (new_cfa->offset == old_cfa->offset |
793 | && old_cfa->reg != INVALID_REGNUM | |
794 | && !new_cfa->indirect | |
795 | && !old_cfa->indirect) | |
dcdf448e | 796 | { |
797 | /* Construct a "DW_CFA_def_cfa_register <register>" instruction, | |
798 | indicating the CFA register has changed to <register> but the | |
799 | offset has not changed. */ | |
800 | cfi->dw_cfi_opc = DW_CFA_def_cfa_register; | |
0b3b5cad | 801 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
dcdf448e | 802 | } |
0b3b5cad | 803 | else if (new_cfa->indirect == 0) |
dcdf448e | 804 | { |
805 | /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction, | |
806 | indicating the CFA register has changed to <register> with | |
807 | the specified offset. The data factoring for DW_CFA_def_cfa_sf | |
808 | happens in output_cfi, or in the assembler via the .cfi_def_cfa | |
809 | directive. */ | |
0b3b5cad | 810 | if (new_cfa->offset < 0) |
dcdf448e | 811 | cfi->dw_cfi_opc = DW_CFA_def_cfa_sf; |
812 | else | |
813 | cfi->dw_cfi_opc = DW_CFA_def_cfa; | |
0b3b5cad | 814 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
815 | cfi->dw_cfi_oprnd2.dw_cfi_offset = new_cfa->offset; | |
dcdf448e | 816 | } |
817 | else | |
818 | { | |
819 | /* Construct a DW_CFA_def_cfa_expression instruction to | |
820 | calculate the CFA using a full location expression since no | |
821 | register-offset pair is available. */ | |
b3e7c666 | 822 | struct dw_loc_descr_node *loc_list; |
dcdf448e | 823 | |
824 | cfi->dw_cfi_opc = DW_CFA_def_cfa_expression; | |
0b3b5cad | 825 | loc_list = build_cfa_loc (new_cfa, 0); |
dcdf448e | 826 | cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list; |
827 | } | |
828 | ||
0b3b5cad | 829 | return cfi; |
830 | } | |
831 | ||
832 | /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */ | |
833 | ||
834 | static void | |
835 | def_cfa_1 (dw_cfa_location *new_cfa) | |
836 | { | |
837 | dw_cfi_ref cfi; | |
838 | ||
b1613fc3 | 839 | if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0) |
840 | cur_trace->cfa_store.offset = new_cfa->offset; | |
0b3b5cad | 841 | |
842 | cfi = def_cfa_0 (&cur_row->cfa, new_cfa); | |
843 | if (cfi) | |
844 | { | |
845 | cur_row->cfa = *new_cfa; | |
a5c6cfdd | 846 | cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression |
847 | ? cfi : NULL); | |
0b3b5cad | 848 | |
849 | add_cfi (cfi); | |
850 | } | |
dcdf448e | 851 | } |
852 | ||
853 | /* Add the CFI for saving a register. REG is the CFA column number. | |
dcdf448e | 854 | If SREG is -1, the register is saved at OFFSET from the CFA; |
855 | otherwise it is saved in SREG. */ | |
856 | ||
857 | static void | |
d4898332 | 858 | reg_save (unsigned int reg, unsigned int sreg, HOST_WIDE_INT offset) |
dcdf448e | 859 | { |
d4898332 | 860 | dw_fde_ref fde = cfun ? cfun->fde : NULL; |
dcdf448e | 861 | dw_cfi_ref cfi = new_cfi (); |
dcdf448e | 862 | |
863 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
864 | ||
865 | /* When stack is aligned, store REG using DW_CFA_expression with FP. */ | |
866 | if (fde | |
867 | && fde->stack_realign | |
868 | && sreg == INVALID_REGNUM) | |
869 | { | |
870 | cfi->dw_cfi_opc = DW_CFA_expression; | |
871 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
872 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
eb93b3f4 | 873 | = build_cfa_aligned_loc (&cur_row->cfa, offset, |
874 | fde->stack_realignment); | |
dcdf448e | 875 | } |
876 | else if (sreg == INVALID_REGNUM) | |
877 | { | |
878 | if (need_data_align_sf_opcode (offset)) | |
879 | cfi->dw_cfi_opc = DW_CFA_offset_extended_sf; | |
880 | else if (reg & ~0x3f) | |
881 | cfi->dw_cfi_opc = DW_CFA_offset_extended; | |
882 | else | |
883 | cfi->dw_cfi_opc = DW_CFA_offset; | |
884 | cfi->dw_cfi_oprnd2.dw_cfi_offset = offset; | |
885 | } | |
886 | else if (sreg == reg) | |
e9fe542d | 887 | { |
888 | /* While we could emit something like DW_CFA_same_value or | |
889 | DW_CFA_restore, we never expect to see something like that | |
890 | in a prologue. This is more likely to be a bug. A backend | |
891 | can always bypass this by using REG_CFA_RESTORE directly. */ | |
892 | gcc_unreachable (); | |
893 | } | |
dcdf448e | 894 | else |
895 | { | |
896 | cfi->dw_cfi_opc = DW_CFA_register; | |
897 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg; | |
898 | } | |
899 | ||
d4898332 | 900 | add_cfi (cfi); |
e9fe542d | 901 | update_row_reg_save (cur_row, reg, cfi); |
dcdf448e | 902 | } |
903 | ||
dfe00a8f | 904 | /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note |
905 | and adjust data structures to match. */ | |
dcdf448e | 906 | |
907 | static void | |
bfc53c49 | 908 | notice_args_size (rtx_insn *insn) |
dcdf448e | 909 | { |
dfe00a8f | 910 | HOST_WIDE_INT args_size, delta; |
911 | rtx note; | |
dcdf448e | 912 | |
dfe00a8f | 913 | note = find_reg_note (insn, REG_ARGS_SIZE, NULL); |
914 | if (note == NULL) | |
915 | return; | |
eb93b3f4 | 916 | |
dfe00a8f | 917 | args_size = INTVAL (XEXP (note, 0)); |
918 | delta = args_size - cur_trace->end_true_args_size; | |
919 | if (delta == 0) | |
920 | return; | |
dcdf448e | 921 | |
dfe00a8f | 922 | cur_trace->end_true_args_size = args_size; |
b1613fc3 | 923 | |
dfe00a8f | 924 | /* If the CFA is computed off the stack pointer, then we must adjust |
925 | the computation of the CFA as well. */ | |
926 | if (cur_cfa->reg == dw_stack_pointer_regnum) | |
927 | { | |
928 | gcc_assert (!cur_cfa->indirect); | |
dcdf448e | 929 | |
dfe00a8f | 930 | /* Convert a change in args_size (always a positive in the |
931 | direction of stack growth) to a change in stack pointer. */ | |
3764c94e | 932 | if (!STACK_GROWS_DOWNWARD) |
933 | delta = -delta; | |
934 | ||
dfe00a8f | 935 | cur_cfa->offset += delta; |
936 | } | |
dcdf448e | 937 | } |
938 | ||
dfe00a8f | 939 | /* A subroutine of scan_trace. INSN is can_throw_internal. Update the |
940 | data within the trace related to EH insns and args_size. */ | |
dcdf448e | 941 | |
942 | static void | |
4cd001d5 | 943 | notice_eh_throw (rtx_insn *insn) |
dcdf448e | 944 | { |
dfe00a8f | 945 | HOST_WIDE_INT args_size; |
dcdf448e | 946 | |
dfe00a8f | 947 | args_size = cur_trace->end_true_args_size; |
948 | if (cur_trace->eh_head == NULL) | |
dcdf448e | 949 | { |
dfe00a8f | 950 | cur_trace->eh_head = insn; |
951 | cur_trace->beg_delay_args_size = args_size; | |
952 | cur_trace->end_delay_args_size = args_size; | |
dcdf448e | 953 | } |
dfe00a8f | 954 | else if (cur_trace->end_delay_args_size != args_size) |
dcdf448e | 955 | { |
dfe00a8f | 956 | cur_trace->end_delay_args_size = args_size; |
dcdf448e | 957 | |
dfe00a8f | 958 | /* ??? If the CFA is the stack pointer, search backward for the last |
959 | CFI note and insert there. Given that the stack changed for the | |
960 | args_size change, there *must* be such a note in between here and | |
961 | the last eh insn. */ | |
962 | add_cfi_args_size (args_size); | |
963 | } | |
dcdf448e | 964 | } |
965 | ||
559e966b | 966 | /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */ |
26a649dd | 967 | /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is |
968 | used in places where rtl is prohibited. */ | |
559e966b | 969 | |
970 | static inline unsigned | |
971 | dwf_regno (const_rtx reg) | |
972 | { | |
561af01c | 973 | gcc_assert (REGNO (reg) < FIRST_PSEUDO_REGISTER); |
26a649dd | 974 | return DWARF_FRAME_REGNUM (REGNO (reg)); |
559e966b | 975 | } |
976 | ||
dcdf448e | 977 | /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */ |
978 | ||
979 | static bool | |
980 | compare_reg_or_pc (rtx x, rtx y) | |
981 | { | |
982 | if (REG_P (x) && REG_P (y)) | |
983 | return REGNO (x) == REGNO (y); | |
984 | return x == y; | |
985 | } | |
986 | ||
987 | /* Record SRC as being saved in DEST. DEST may be null to delete an | |
988 | existing entry. SRC may be a register or PC_RTX. */ | |
989 | ||
990 | static void | |
991 | record_reg_saved_in_reg (rtx dest, rtx src) | |
992 | { | |
993 | reg_saved_in_data *elt; | |
994 | size_t i; | |
995 | ||
f1f41a6c | 996 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt) |
dcdf448e | 997 | if (compare_reg_or_pc (elt->orig_reg, src)) |
998 | { | |
999 | if (dest == NULL) | |
f1f41a6c | 1000 | cur_trace->regs_saved_in_regs.unordered_remove (i); |
dcdf448e | 1001 | else |
1002 | elt->saved_in_reg = dest; | |
1003 | return; | |
1004 | } | |
1005 | ||
1006 | if (dest == NULL) | |
1007 | return; | |
1008 | ||
e82e4eb5 | 1009 | reg_saved_in_data e = {src, dest}; |
f1f41a6c | 1010 | cur_trace->regs_saved_in_regs.safe_push (e); |
dcdf448e | 1011 | } |
1012 | ||
dcdf448e | 1013 | /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at |
1014 | SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */ | |
1015 | ||
1016 | static void | |
c746c5c3 | 1017 | queue_reg_save (rtx reg, rtx sreg, HOST_WIDE_INT offset) |
dcdf448e | 1018 | { |
c73aa568 | 1019 | queued_reg_save *q; |
e82e4eb5 | 1020 | queued_reg_save e = {reg, sreg, offset}; |
c73aa568 | 1021 | size_t i; |
dcdf448e | 1022 | |
1023 | /* Duplicates waste space, but it's also necessary to remove them | |
6ca363a7 | 1024 | for correctness, since the queue gets output in reverse order. */ |
f1f41a6c | 1025 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
6ca363a7 | 1026 | if (compare_reg_or_pc (q->reg, reg)) |
e82e4eb5 | 1027 | { |
1028 | *q = e; | |
1029 | return; | |
1030 | } | |
dcdf448e | 1031 | |
f1f41a6c | 1032 | queued_reg_saves.safe_push (e); |
dcdf448e | 1033 | } |
1034 | ||
1035 | /* Output all the entries in QUEUED_REG_SAVES. */ | |
1036 | ||
1037 | static void | |
1038 | dwarf2out_flush_queued_reg_saves (void) | |
1039 | { | |
c73aa568 | 1040 | queued_reg_save *q; |
1041 | size_t i; | |
dcdf448e | 1042 | |
f1f41a6c | 1043 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
dcdf448e | 1044 | { |
1045 | unsigned int reg, sreg; | |
1046 | ||
1047 | record_reg_saved_in_reg (q->saved_reg, q->reg); | |
1048 | ||
6ca363a7 | 1049 | if (q->reg == pc_rtx) |
1050 | reg = DWARF_FRAME_RETURN_COLUMN; | |
1051 | else | |
559e966b | 1052 | reg = dwf_regno (q->reg); |
dcdf448e | 1053 | if (q->saved_reg) |
559e966b | 1054 | sreg = dwf_regno (q->saved_reg); |
dcdf448e | 1055 | else |
1056 | sreg = INVALID_REGNUM; | |
d4898332 | 1057 | reg_save (reg, sreg, q->cfa_offset); |
dcdf448e | 1058 | } |
1059 | ||
f1f41a6c | 1060 | queued_reg_saves.truncate (0); |
dcdf448e | 1061 | } |
1062 | ||
1063 | /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved | |
1064 | location for? Or, does it clobber a register which we've previously | |
1065 | said that some other register is saved in, and for which we now | |
1066 | have a new location for? */ | |
1067 | ||
1068 | static bool | |
1069 | clobbers_queued_reg_save (const_rtx insn) | |
1070 | { | |
c73aa568 | 1071 | queued_reg_save *q; |
1072 | size_t iq; | |
dcdf448e | 1073 | |
f1f41a6c | 1074 | FOR_EACH_VEC_ELT (queued_reg_saves, iq, q) |
dcdf448e | 1075 | { |
c73aa568 | 1076 | size_t ir; |
dcdf448e | 1077 | reg_saved_in_data *rir; |
1078 | ||
1079 | if (modified_in_p (q->reg, insn)) | |
1080 | return true; | |
1081 | ||
f1f41a6c | 1082 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, ir, rir) |
dcdf448e | 1083 | if (compare_reg_or_pc (q->reg, rir->orig_reg) |
1084 | && modified_in_p (rir->saved_in_reg, insn)) | |
1085 | return true; | |
1086 | } | |
1087 | ||
1088 | return false; | |
1089 | } | |
1090 | ||
1091 | /* What register, if any, is currently saved in REG? */ | |
1092 | ||
1093 | static rtx | |
1094 | reg_saved_in (rtx reg) | |
1095 | { | |
1096 | unsigned int regn = REGNO (reg); | |
c73aa568 | 1097 | queued_reg_save *q; |
dcdf448e | 1098 | reg_saved_in_data *rir; |
1099 | size_t i; | |
1100 | ||
f1f41a6c | 1101 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
dcdf448e | 1102 | if (q->saved_reg && regn == REGNO (q->saved_reg)) |
1103 | return q->reg; | |
1104 | ||
f1f41a6c | 1105 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, rir) |
dcdf448e | 1106 | if (regn == REGNO (rir->saved_in_reg)) |
1107 | return rir->orig_reg; | |
1108 | ||
1109 | return NULL_RTX; | |
1110 | } | |
1111 | ||
dcdf448e | 1112 | /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */ |
1113 | ||
1114 | static void | |
c746c5c3 | 1115 | dwarf2out_frame_debug_def_cfa (rtx pat) |
dcdf448e | 1116 | { |
dfe00a8f | 1117 | memset (cur_cfa, 0, sizeof (*cur_cfa)); |
dcdf448e | 1118 | |
a5c6cfdd | 1119 | if (GET_CODE (pat) == PLUS) |
dcdf448e | 1120 | { |
dfe00a8f | 1121 | cur_cfa->offset = INTVAL (XEXP (pat, 1)); |
a5c6cfdd | 1122 | pat = XEXP (pat, 0); |
1123 | } | |
1124 | if (MEM_P (pat)) | |
1125 | { | |
dfe00a8f | 1126 | cur_cfa->indirect = 1; |
dcdf448e | 1127 | pat = XEXP (pat, 0); |
1128 | if (GET_CODE (pat) == PLUS) | |
1129 | { | |
dfe00a8f | 1130 | cur_cfa->base_offset = INTVAL (XEXP (pat, 1)); |
dcdf448e | 1131 | pat = XEXP (pat, 0); |
1132 | } | |
dcdf448e | 1133 | } |
a5c6cfdd | 1134 | /* ??? If this fails, we could be calling into the _loc functions to |
1135 | define a full expression. So far no port does that. */ | |
1136 | gcc_assert (REG_P (pat)); | |
dfe00a8f | 1137 | cur_cfa->reg = dwf_regno (pat); |
dcdf448e | 1138 | } |
1139 | ||
1140 | /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */ | |
1141 | ||
1142 | static void | |
c746c5c3 | 1143 | dwarf2out_frame_debug_adjust_cfa (rtx pat) |
dcdf448e | 1144 | { |
1145 | rtx src, dest; | |
1146 | ||
1147 | gcc_assert (GET_CODE (pat) == SET); | |
1148 | dest = XEXP (pat, 0); | |
1149 | src = XEXP (pat, 1); | |
1150 | ||
1151 | switch (GET_CODE (src)) | |
1152 | { | |
1153 | case PLUS: | |
dfe00a8f | 1154 | gcc_assert (dwf_regno (XEXP (src, 0)) == cur_cfa->reg); |
1155 | cur_cfa->offset -= INTVAL (XEXP (src, 1)); | |
dcdf448e | 1156 | break; |
1157 | ||
1158 | case REG: | |
dfe00a8f | 1159 | break; |
dcdf448e | 1160 | |
1161 | default: | |
dfe00a8f | 1162 | gcc_unreachable (); |
dcdf448e | 1163 | } |
1164 | ||
dfe00a8f | 1165 | cur_cfa->reg = dwf_regno (dest); |
1166 | gcc_assert (cur_cfa->indirect == 0); | |
dcdf448e | 1167 | } |
1168 | ||
1169 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */ | |
1170 | ||
1171 | static void | |
c746c5c3 | 1172 | dwarf2out_frame_debug_cfa_offset (rtx set) |
dcdf448e | 1173 | { |
1174 | HOST_WIDE_INT offset; | |
1175 | rtx src, addr, span; | |
1176 | unsigned int sregno; | |
1177 | ||
1178 | src = XEXP (set, 1); | |
1179 | addr = XEXP (set, 0); | |
1180 | gcc_assert (MEM_P (addr)); | |
1181 | addr = XEXP (addr, 0); | |
1182 | ||
1183 | /* As documented, only consider extremely simple addresses. */ | |
1184 | switch (GET_CODE (addr)) | |
1185 | { | |
1186 | case REG: | |
dfe00a8f | 1187 | gcc_assert (dwf_regno (addr) == cur_cfa->reg); |
1188 | offset = -cur_cfa->offset; | |
dcdf448e | 1189 | break; |
1190 | case PLUS: | |
dfe00a8f | 1191 | gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_cfa->reg); |
1192 | offset = INTVAL (XEXP (addr, 1)) - cur_cfa->offset; | |
dcdf448e | 1193 | break; |
1194 | default: | |
1195 | gcc_unreachable (); | |
1196 | } | |
1197 | ||
1198 | if (src == pc_rtx) | |
1199 | { | |
1200 | span = NULL; | |
1201 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1202 | } | |
b1613fc3 | 1203 | else |
dcdf448e | 1204 | { |
1205 | span = targetm.dwarf_register_span (src); | |
559e966b | 1206 | sregno = dwf_regno (src); |
dcdf448e | 1207 | } |
1208 | ||
1209 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1210 | a different flushing heuristic for epilogues. */ | |
1211 | if (!span) | |
d4898332 | 1212 | reg_save (sregno, INVALID_REGNUM, offset); |
dcdf448e | 1213 | else |
1214 | { | |
1215 | /* We have a PARALLEL describing where the contents of SRC live. | |
fad67b80 | 1216 | Adjust the offset for each piece of the PARALLEL. */ |
dcdf448e | 1217 | HOST_WIDE_INT span_offset = offset; |
1218 | ||
1219 | gcc_assert (GET_CODE (span) == PARALLEL); | |
1220 | ||
fad67b80 | 1221 | const int par_len = XVECLEN (span, 0); |
1222 | for (int par_index = 0; par_index < par_len; par_index++) | |
dcdf448e | 1223 | { |
1224 | rtx elem = XVECEXP (span, 0, par_index); | |
559e966b | 1225 | sregno = dwf_regno (src); |
d4898332 | 1226 | reg_save (sregno, INVALID_REGNUM, span_offset); |
dcdf448e | 1227 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); |
1228 | } | |
1229 | } | |
1230 | } | |
1231 | ||
1232 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */ | |
1233 | ||
1234 | static void | |
c746c5c3 | 1235 | dwarf2out_frame_debug_cfa_register (rtx set) |
dcdf448e | 1236 | { |
1237 | rtx src, dest; | |
1238 | unsigned sregno, dregno; | |
1239 | ||
1240 | src = XEXP (set, 1); | |
1241 | dest = XEXP (set, 0); | |
1242 | ||
6ca363a7 | 1243 | record_reg_saved_in_reg (dest, src); |
dcdf448e | 1244 | if (src == pc_rtx) |
1245 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1246 | else | |
559e966b | 1247 | sregno = dwf_regno (src); |
dcdf448e | 1248 | |
559e966b | 1249 | dregno = dwf_regno (dest); |
dcdf448e | 1250 | |
1251 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1252 | a different flushing heuristic for epilogues. */ | |
d4898332 | 1253 | reg_save (sregno, dregno, 0); |
dcdf448e | 1254 | } |
1255 | ||
1256 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ | |
1257 | ||
1258 | static void | |
c746c5c3 | 1259 | dwarf2out_frame_debug_cfa_expression (rtx set) |
dcdf448e | 1260 | { |
1261 | rtx src, dest, span; | |
1262 | dw_cfi_ref cfi = new_cfi (); | |
e9fe542d | 1263 | unsigned regno; |
dcdf448e | 1264 | |
1265 | dest = SET_DEST (set); | |
1266 | src = SET_SRC (set); | |
1267 | ||
1268 | gcc_assert (REG_P (src)); | |
1269 | gcc_assert (MEM_P (dest)); | |
1270 | ||
1271 | span = targetm.dwarf_register_span (src); | |
1272 | gcc_assert (!span); | |
1273 | ||
e9fe542d | 1274 | regno = dwf_regno (src); |
1275 | ||
dcdf448e | 1276 | cfi->dw_cfi_opc = DW_CFA_expression; |
e9fe542d | 1277 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno; |
dcdf448e | 1278 | cfi->dw_cfi_oprnd2.dw_cfi_loc |
1279 | = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest), | |
1280 | GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); | |
1281 | ||
1282 | /* ??? We'd like to use queue_reg_save, were the interface different, | |
1283 | and, as above, we could manage flushing for epilogues. */ | |
d4898332 | 1284 | add_cfi (cfi); |
e9fe542d | 1285 | update_row_reg_save (cur_row, regno, cfi); |
dcdf448e | 1286 | } |
1287 | ||
1288 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */ | |
1289 | ||
1290 | static void | |
c746c5c3 | 1291 | dwarf2out_frame_debug_cfa_restore (rtx reg) |
dcdf448e | 1292 | { |
fad67b80 | 1293 | gcc_assert (REG_P (reg)); |
1294 | ||
1295 | rtx span = targetm.dwarf_register_span (reg); | |
1296 | if (!span) | |
1297 | { | |
1298 | unsigned int regno = dwf_regno (reg); | |
1299 | add_cfi_restore (regno); | |
1300 | update_row_reg_save (cur_row, regno, NULL); | |
1301 | } | |
1302 | else | |
1303 | { | |
1304 | /* We have a PARALLEL describing where the contents of REG live. | |
1305 | Restore the register for each piece of the PARALLEL. */ | |
1306 | gcc_assert (GET_CODE (span) == PARALLEL); | |
dcdf448e | 1307 | |
fad67b80 | 1308 | const int par_len = XVECLEN (span, 0); |
1309 | for (int par_index = 0; par_index < par_len; par_index++) | |
1310 | { | |
1311 | reg = XVECEXP (span, 0, par_index); | |
1312 | gcc_assert (REG_P (reg)); | |
1313 | unsigned int regno = dwf_regno (reg); | |
1314 | add_cfi_restore (regno); | |
1315 | update_row_reg_save (cur_row, regno, NULL); | |
1316 | } | |
1317 | } | |
dcdf448e | 1318 | } |
1319 | ||
1320 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE. | |
1321 | ??? Perhaps we should note in the CIE where windows are saved (instead of | |
1322 | assuming 0(cfa)) and what registers are in the window. */ | |
1323 | ||
1324 | static void | |
c746c5c3 | 1325 | dwarf2out_frame_debug_cfa_window_save (void) |
dcdf448e | 1326 | { |
1327 | dw_cfi_ref cfi = new_cfi (); | |
1328 | ||
1329 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; | |
d4898332 | 1330 | add_cfi (cfi); |
dcdf448e | 1331 | } |
1332 | ||
1333 | /* Record call frame debugging information for an expression EXPR, | |
1334 | which either sets SP or FP (adjusting how we calculate the frame | |
1335 | address) or saves a register to the stack or another register. | |
1336 | LABEL indicates the address of EXPR. | |
1337 | ||
1338 | This function encodes a state machine mapping rtxes to actions on | |
1339 | cfa, cfa_store, and cfa_temp.reg. We describe these rules so | |
1340 | users need not read the source code. | |
1341 | ||
1342 | The High-Level Picture | |
1343 | ||
1344 | Changes in the register we use to calculate the CFA: Currently we | |
1345 | assume that if you copy the CFA register into another register, we | |
1346 | should take the other one as the new CFA register; this seems to | |
1347 | work pretty well. If it's wrong for some target, it's simple | |
1348 | enough not to set RTX_FRAME_RELATED_P on the insn in question. | |
1349 | ||
1350 | Changes in the register we use for saving registers to the stack: | |
1351 | This is usually SP, but not always. Again, we deduce that if you | |
1352 | copy SP into another register (and SP is not the CFA register), | |
1353 | then the new register is the one we will be using for register | |
1354 | saves. This also seems to work. | |
1355 | ||
1356 | Register saves: There's not much guesswork about this one; if | |
1357 | RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a | |
1358 | register save, and the register used to calculate the destination | |
1359 | had better be the one we think we're using for this purpose. | |
1360 | It's also assumed that a copy from a call-saved register to another | |
1361 | register is saving that register if RTX_FRAME_RELATED_P is set on | |
1362 | that instruction. If the copy is from a call-saved register to | |
1363 | the *same* register, that means that the register is now the same | |
1364 | value as in the caller. | |
1365 | ||
1366 | Except: If the register being saved is the CFA register, and the | |
1367 | offset is nonzero, we are saving the CFA, so we assume we have to | |
1368 | use DW_CFA_def_cfa_expression. If the offset is 0, we assume that | |
1369 | the intent is to save the value of SP from the previous frame. | |
1370 | ||
1371 | In addition, if a register has previously been saved to a different | |
1372 | register, | |
1373 | ||
1374 | Invariants / Summaries of Rules | |
1375 | ||
1376 | cfa current rule for calculating the CFA. It usually | |
eb93b3f4 | 1377 | consists of a register and an offset. This is |
dfe00a8f | 1378 | actually stored in *cur_cfa, but abbreviated |
eb93b3f4 | 1379 | for the purposes of this documentation. |
dcdf448e | 1380 | cfa_store register used by prologue code to save things to the stack |
1381 | cfa_store.offset is the offset from the value of | |
1382 | cfa_store.reg to the actual CFA | |
1383 | cfa_temp register holding an integral value. cfa_temp.offset | |
1384 | stores the value, which will be used to adjust the | |
1385 | stack pointer. cfa_temp is also used like cfa_store, | |
1386 | to track stores to the stack via fp or a temp reg. | |
1387 | ||
1388 | Rules 1- 4: Setting a register's value to cfa.reg or an expression | |
1389 | with cfa.reg as the first operand changes the cfa.reg and its | |
1390 | cfa.offset. Rule 1 and 4 also set cfa_temp.reg and | |
1391 | cfa_temp.offset. | |
1392 | ||
1393 | Rules 6- 9: Set a non-cfa.reg register value to a constant or an | |
1394 | expression yielding a constant. This sets cfa_temp.reg | |
1395 | and cfa_temp.offset. | |
1396 | ||
1397 | Rule 5: Create a new register cfa_store used to save items to the | |
1398 | stack. | |
1399 | ||
1400 | Rules 10-14: Save a register to the stack. Define offset as the | |
1401 | difference of the original location and cfa_store's | |
1402 | location (or cfa_temp's location if cfa_temp is used). | |
1403 | ||
1404 | Rules 16-20: If AND operation happens on sp in prologue, we assume | |
1405 | stack is realigned. We will use a group of DW_OP_XXX | |
1406 | expressions to represent the location of the stored | |
1407 | register instead of CFA+offset. | |
1408 | ||
1409 | The Rules | |
1410 | ||
1411 | "{a,b}" indicates a choice of a xor b. | |
1412 | "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg. | |
1413 | ||
1414 | Rule 1: | |
1415 | (set <reg1> <reg2>:cfa.reg) | |
1416 | effects: cfa.reg = <reg1> | |
1417 | cfa.offset unchanged | |
1418 | cfa_temp.reg = <reg1> | |
1419 | cfa_temp.offset = cfa.offset | |
1420 | ||
1421 | Rule 2: | |
1422 | (set sp ({minus,plus,losum} {sp,fp}:cfa.reg | |
1423 | {<const_int>,<reg>:cfa_temp.reg})) | |
1424 | effects: cfa.reg = sp if fp used | |
1425 | cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp | |
1426 | cfa_store.offset += {+/- <const_int>, cfa_temp.offset} | |
1427 | if cfa_store.reg==sp | |
1428 | ||
1429 | Rule 3: | |
1430 | (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>)) | |
1431 | effects: cfa.reg = fp | |
1432 | cfa_offset += +/- <const_int> | |
1433 | ||
1434 | Rule 4: | |
1435 | (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>)) | |
1436 | constraints: <reg1> != fp | |
1437 | <reg1> != sp | |
1438 | effects: cfa.reg = <reg1> | |
1439 | cfa_temp.reg = <reg1> | |
1440 | cfa_temp.offset = cfa.offset | |
1441 | ||
1442 | Rule 5: | |
1443 | (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg)) | |
1444 | constraints: <reg1> != fp | |
1445 | <reg1> != sp | |
1446 | effects: cfa_store.reg = <reg1> | |
1447 | cfa_store.offset = cfa.offset - cfa_temp.offset | |
1448 | ||
1449 | Rule 6: | |
1450 | (set <reg> <const_int>) | |
1451 | effects: cfa_temp.reg = <reg> | |
1452 | cfa_temp.offset = <const_int> | |
1453 | ||
1454 | Rule 7: | |
1455 | (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>)) | |
1456 | effects: cfa_temp.reg = <reg1> | |
1457 | cfa_temp.offset |= <const_int> | |
1458 | ||
1459 | Rule 8: | |
1460 | (set <reg> (high <exp>)) | |
1461 | effects: none | |
1462 | ||
1463 | Rule 9: | |
1464 | (set <reg> (lo_sum <exp> <const_int>)) | |
1465 | effects: cfa_temp.reg = <reg> | |
1466 | cfa_temp.offset = <const_int> | |
1467 | ||
1468 | Rule 10: | |
1469 | (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>) | |
1470 | effects: cfa_store.offset -= <const_int> | |
1471 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1472 | cfa.reg = sp | |
1473 | cfa.base_offset = -cfa_store.offset | |
1474 | ||
1475 | Rule 11: | |
1476 | (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>) | |
1477 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1478 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1479 | cfa.reg = sp | |
1480 | cfa.base_offset = -cfa_store.offset | |
1481 | ||
1482 | Rule 12: | |
1483 | (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>)) | |
1484 | ||
1485 | <reg2>) | |
1486 | effects: cfa.reg = <reg1> | |
1487 | cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset | |
1488 | ||
1489 | Rule 13: | |
1490 | (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>) | |
1491 | effects: cfa.reg = <reg1> | |
1492 | cfa.base_offset = -{cfa_store,cfa_temp}.offset | |
1493 | ||
1494 | Rule 14: | |
1495 | (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>) | |
1496 | effects: cfa.reg = <reg1> | |
1497 | cfa.base_offset = -cfa_temp.offset | |
1498 | cfa_temp.offset -= mode_size(mem) | |
1499 | ||
1500 | Rule 15: | |
1501 | (set <reg> {unspec, unspec_volatile}) | |
1502 | effects: target-dependent | |
1503 | ||
1504 | Rule 16: | |
1505 | (set sp (and: sp <const_int>)) | |
1506 | constraints: cfa_store.reg == sp | |
6033bf11 | 1507 | effects: cfun->fde.stack_realign = 1 |
dcdf448e | 1508 | cfa_store.offset = 0 |
1509 | fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp | |
1510 | ||
1511 | Rule 17: | |
1512 | (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int)))) | |
1513 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1514 | ||
1515 | Rule 18: | |
1516 | (set (mem ({pre_inc, pre_dec} sp)) fp) | |
1517 | constraints: fde->stack_realign == 1 | |
1518 | effects: cfa_store.offset = 0 | |
1519 | cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1520 | ||
1521 | Rule 19: | |
1522 | (set (mem ({pre_inc, pre_dec} sp)) cfa.reg) | |
1523 | constraints: fde->stack_realign == 1 | |
1524 | && cfa.offset == 0 | |
1525 | && cfa.indirect == 0 | |
1526 | && cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1527 | effects: Use DW_CFA_def_cfa_expression to define cfa | |
1528 | cfa.reg == fde->drap_reg */ | |
1529 | ||
1530 | static void | |
c746c5c3 | 1531 | dwarf2out_frame_debug_expr (rtx expr) |
dcdf448e | 1532 | { |
1533 | rtx src, dest, span; | |
1534 | HOST_WIDE_INT offset; | |
1535 | dw_fde_ref fde; | |
1536 | ||
1537 | /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of | |
1538 | the PARALLEL independently. The first element is always processed if | |
1539 | it is a SET. This is for backward compatibility. Other elements | |
1540 | are processed only if they are SETs and the RTX_FRAME_RELATED_P | |
1541 | flag is set in them. */ | |
1542 | if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE) | |
1543 | { | |
1544 | int par_index; | |
1545 | int limit = XVECLEN (expr, 0); | |
1546 | rtx elem; | |
1547 | ||
1548 | /* PARALLELs have strict read-modify-write semantics, so we | |
1549 | ought to evaluate every rvalue before changing any lvalue. | |
1550 | It's cumbersome to do that in general, but there's an | |
1551 | easy approximation that is enough for all current users: | |
1552 | handle register saves before register assignments. */ | |
1553 | if (GET_CODE (expr) == PARALLEL) | |
1554 | for (par_index = 0; par_index < limit; par_index++) | |
1555 | { | |
1556 | elem = XVECEXP (expr, 0, par_index); | |
1557 | if (GET_CODE (elem) == SET | |
1558 | && MEM_P (SET_DEST (elem)) | |
1559 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
c746c5c3 | 1560 | dwarf2out_frame_debug_expr (elem); |
dcdf448e | 1561 | } |
1562 | ||
1563 | for (par_index = 0; par_index < limit; par_index++) | |
1564 | { | |
1565 | elem = XVECEXP (expr, 0, par_index); | |
1566 | if (GET_CODE (elem) == SET | |
1567 | && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE) | |
1568 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
c746c5c3 | 1569 | dwarf2out_frame_debug_expr (elem); |
dcdf448e | 1570 | } |
1571 | return; | |
1572 | } | |
1573 | ||
1574 | gcc_assert (GET_CODE (expr) == SET); | |
1575 | ||
1576 | src = SET_SRC (expr); | |
1577 | dest = SET_DEST (expr); | |
1578 | ||
1579 | if (REG_P (src)) | |
1580 | { | |
1581 | rtx rsi = reg_saved_in (src); | |
1582 | if (rsi) | |
1583 | src = rsi; | |
1584 | } | |
1585 | ||
6033bf11 | 1586 | fde = cfun->fde; |
dcdf448e | 1587 | |
1588 | switch (GET_CODE (dest)) | |
1589 | { | |
1590 | case REG: | |
1591 | switch (GET_CODE (src)) | |
1592 | { | |
1593 | /* Setting FP from SP. */ | |
1594 | case REG: | |
dfe00a8f | 1595 | if (cur_cfa->reg == dwf_regno (src)) |
dcdf448e | 1596 | { |
1597 | /* Rule 1 */ | |
1598 | /* Update the CFA rule wrt SP or FP. Make sure src is | |
1599 | relative to the current CFA register. | |
1600 | ||
1601 | We used to require that dest be either SP or FP, but the | |
1602 | ARM copies SP to a temporary register, and from there to | |
1603 | FP. So we just rely on the backends to only set | |
1604 | RTX_FRAME_RELATED_P on appropriate insns. */ | |
dfe00a8f | 1605 | cur_cfa->reg = dwf_regno (dest); |
1606 | cur_trace->cfa_temp.reg = cur_cfa->reg; | |
1607 | cur_trace->cfa_temp.offset = cur_cfa->offset; | |
dcdf448e | 1608 | } |
1609 | else | |
1610 | { | |
1611 | /* Saving a register in a register. */ | |
1612 | gcc_assert (!fixed_regs [REGNO (dest)] | |
1613 | /* For the SPARC and its register window. */ | |
559e966b | 1614 | || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN)); |
dcdf448e | 1615 | |
1616 | /* After stack is aligned, we can only save SP in FP | |
1617 | if drap register is used. In this case, we have | |
1618 | to restore stack pointer with the CFA value and we | |
1619 | don't generate this DWARF information. */ | |
1620 | if (fde | |
1621 | && fde->stack_realign | |
1622 | && REGNO (src) == STACK_POINTER_REGNUM) | |
1623 | gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM | |
1624 | && fde->drap_reg != INVALID_REGNUM | |
dfe00a8f | 1625 | && cur_cfa->reg != dwf_regno (src)); |
dcdf448e | 1626 | else |
c746c5c3 | 1627 | queue_reg_save (src, dest, 0); |
dcdf448e | 1628 | } |
1629 | break; | |
1630 | ||
1631 | case PLUS: | |
1632 | case MINUS: | |
1633 | case LO_SUM: | |
1634 | if (dest == stack_pointer_rtx) | |
1635 | { | |
1636 | /* Rule 2 */ | |
1637 | /* Adjusting SP. */ | |
1638 | switch (GET_CODE (XEXP (src, 1))) | |
1639 | { | |
1640 | case CONST_INT: | |
1641 | offset = INTVAL (XEXP (src, 1)); | |
1642 | break; | |
1643 | case REG: | |
b1613fc3 | 1644 | gcc_assert (dwf_regno (XEXP (src, 1)) |
1645 | == cur_trace->cfa_temp.reg); | |
1646 | offset = cur_trace->cfa_temp.offset; | |
dcdf448e | 1647 | break; |
1648 | default: | |
1649 | gcc_unreachable (); | |
1650 | } | |
1651 | ||
1652 | if (XEXP (src, 0) == hard_frame_pointer_rtx) | |
1653 | { | |
1654 | /* Restoring SP from FP in the epilogue. */ | |
dfe00a8f | 1655 | gcc_assert (cur_cfa->reg == dw_frame_pointer_regnum); |
1656 | cur_cfa->reg = dw_stack_pointer_regnum; | |
dcdf448e | 1657 | } |
1658 | else if (GET_CODE (src) == LO_SUM) | |
1659 | /* Assume we've set the source reg of the LO_SUM from sp. */ | |
1660 | ; | |
1661 | else | |
1662 | gcc_assert (XEXP (src, 0) == stack_pointer_rtx); | |
1663 | ||
1664 | if (GET_CODE (src) != MINUS) | |
1665 | offset = -offset; | |
dfe00a8f | 1666 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1667 | cur_cfa->offset += offset; | |
b1613fc3 | 1668 | if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum) |
1669 | cur_trace->cfa_store.offset += offset; | |
dcdf448e | 1670 | } |
1671 | else if (dest == hard_frame_pointer_rtx) | |
1672 | { | |
1673 | /* Rule 3 */ | |
1674 | /* Either setting the FP from an offset of the SP, | |
1675 | or adjusting the FP */ | |
1676 | gcc_assert (frame_pointer_needed); | |
1677 | ||
1678 | gcc_assert (REG_P (XEXP (src, 0)) | |
dfe00a8f | 1679 | && dwf_regno (XEXP (src, 0)) == cur_cfa->reg |
dcdf448e | 1680 | && CONST_INT_P (XEXP (src, 1))); |
1681 | offset = INTVAL (XEXP (src, 1)); | |
1682 | if (GET_CODE (src) != MINUS) | |
1683 | offset = -offset; | |
dfe00a8f | 1684 | cur_cfa->offset += offset; |
1685 | cur_cfa->reg = dw_frame_pointer_regnum; | |
dcdf448e | 1686 | } |
1687 | else | |
1688 | { | |
1689 | gcc_assert (GET_CODE (src) != MINUS); | |
1690 | ||
1691 | /* Rule 4 */ | |
1692 | if (REG_P (XEXP (src, 0)) | |
dfe00a8f | 1693 | && dwf_regno (XEXP (src, 0)) == cur_cfa->reg |
dcdf448e | 1694 | && CONST_INT_P (XEXP (src, 1))) |
1695 | { | |
1696 | /* Setting a temporary CFA register that will be copied | |
1697 | into the FP later on. */ | |
1698 | offset = - INTVAL (XEXP (src, 1)); | |
dfe00a8f | 1699 | cur_cfa->offset += offset; |
1700 | cur_cfa->reg = dwf_regno (dest); | |
dcdf448e | 1701 | /* Or used to save regs to the stack. */ |
dfe00a8f | 1702 | cur_trace->cfa_temp.reg = cur_cfa->reg; |
1703 | cur_trace->cfa_temp.offset = cur_cfa->offset; | |
dcdf448e | 1704 | } |
1705 | ||
1706 | /* Rule 5 */ | |
1707 | else if (REG_P (XEXP (src, 0)) | |
b1613fc3 | 1708 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
dcdf448e | 1709 | && XEXP (src, 1) == stack_pointer_rtx) |
1710 | { | |
1711 | /* Setting a scratch register that we will use instead | |
1712 | of SP for saving registers to the stack. */ | |
dfe00a8f | 1713 | gcc_assert (cur_cfa->reg == dw_stack_pointer_regnum); |
b1613fc3 | 1714 | cur_trace->cfa_store.reg = dwf_regno (dest); |
1715 | cur_trace->cfa_store.offset | |
dfe00a8f | 1716 | = cur_cfa->offset - cur_trace->cfa_temp.offset; |
dcdf448e | 1717 | } |
1718 | ||
1719 | /* Rule 9 */ | |
1720 | else if (GET_CODE (src) == LO_SUM | |
1721 | && CONST_INT_P (XEXP (src, 1))) | |
1722 | { | |
b1613fc3 | 1723 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
1724 | cur_trace->cfa_temp.offset = INTVAL (XEXP (src, 1)); | |
dcdf448e | 1725 | } |
1726 | else | |
1727 | gcc_unreachable (); | |
1728 | } | |
1729 | break; | |
1730 | ||
1731 | /* Rule 6 */ | |
1732 | case CONST_INT: | |
b1613fc3 | 1733 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
1734 | cur_trace->cfa_temp.offset = INTVAL (src); | |
dcdf448e | 1735 | break; |
1736 | ||
1737 | /* Rule 7 */ | |
1738 | case IOR: | |
1739 | gcc_assert (REG_P (XEXP (src, 0)) | |
b1613fc3 | 1740 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
dcdf448e | 1741 | && CONST_INT_P (XEXP (src, 1))); |
1742 | ||
b1613fc3 | 1743 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
1744 | cur_trace->cfa_temp.offset |= INTVAL (XEXP (src, 1)); | |
dcdf448e | 1745 | break; |
1746 | ||
1747 | /* Skip over HIGH, assuming it will be followed by a LO_SUM, | |
1748 | which will fill in all of the bits. */ | |
1749 | /* Rule 8 */ | |
1750 | case HIGH: | |
1751 | break; | |
1752 | ||
1753 | /* Rule 15 */ | |
1754 | case UNSPEC: | |
1755 | case UNSPEC_VOLATILE: | |
c746c5c3 | 1756 | /* All unspecs should be represented by REG_CFA_* notes. */ |
1757 | gcc_unreachable (); | |
dcdf448e | 1758 | return; |
1759 | ||
1760 | /* Rule 16 */ | |
1761 | case AND: | |
1762 | /* If this AND operation happens on stack pointer in prologue, | |
1763 | we assume the stack is realigned and we extract the | |
1764 | alignment. */ | |
1765 | if (fde && XEXP (src, 0) == stack_pointer_rtx) | |
1766 | { | |
1767 | /* We interpret reg_save differently with stack_realign set. | |
1768 | Thus we must flush whatever we have queued first. */ | |
1769 | dwarf2out_flush_queued_reg_saves (); | |
1770 | ||
b1613fc3 | 1771 | gcc_assert (cur_trace->cfa_store.reg |
1772 | == dwf_regno (XEXP (src, 0))); | |
dcdf448e | 1773 | fde->stack_realign = 1; |
1774 | fde->stack_realignment = INTVAL (XEXP (src, 1)); | |
b1613fc3 | 1775 | cur_trace->cfa_store.offset = 0; |
dcdf448e | 1776 | |
dfe00a8f | 1777 | if (cur_cfa->reg != dw_stack_pointer_regnum |
1778 | && cur_cfa->reg != dw_frame_pointer_regnum) | |
1779 | fde->drap_reg = cur_cfa->reg; | |
dcdf448e | 1780 | } |
1781 | return; | |
1782 | ||
1783 | default: | |
1784 | gcc_unreachable (); | |
1785 | } | |
dcdf448e | 1786 | break; |
1787 | ||
1788 | case MEM: | |
1789 | ||
1790 | /* Saving a register to the stack. Make sure dest is relative to the | |
1791 | CFA register. */ | |
1792 | switch (GET_CODE (XEXP (dest, 0))) | |
1793 | { | |
1794 | /* Rule 10 */ | |
1795 | /* With a push. */ | |
1796 | case PRE_MODIFY: | |
1797 | case POST_MODIFY: | |
1798 | /* We can't handle variable size modifications. */ | |
1799 | gcc_assert (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1)) | |
1800 | == CONST_INT); | |
1801 | offset = -INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1)); | |
1802 | ||
1803 | gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
b1613fc3 | 1804 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
dcdf448e | 1805 | |
b1613fc3 | 1806 | cur_trace->cfa_store.offset += offset; |
dfe00a8f | 1807 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1808 | cur_cfa->offset = cur_trace->cfa_store.offset; | |
dcdf448e | 1809 | |
1810 | if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY) | |
b1613fc3 | 1811 | offset -= cur_trace->cfa_store.offset; |
dcdf448e | 1812 | else |
b1613fc3 | 1813 | offset = -cur_trace->cfa_store.offset; |
dcdf448e | 1814 | break; |
1815 | ||
1816 | /* Rule 11 */ | |
1817 | case PRE_INC: | |
1818 | case PRE_DEC: | |
1819 | case POST_DEC: | |
1820 | offset = GET_MODE_SIZE (GET_MODE (dest)); | |
1821 | if (GET_CODE (XEXP (dest, 0)) == PRE_INC) | |
1822 | offset = -offset; | |
1823 | ||
1824 | gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0)) | |
1825 | == STACK_POINTER_REGNUM) | |
b1613fc3 | 1826 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
dcdf448e | 1827 | |
b1613fc3 | 1828 | cur_trace->cfa_store.offset += offset; |
dcdf448e | 1829 | |
1830 | /* Rule 18: If stack is aligned, we will use FP as a | |
1831 | reference to represent the address of the stored | |
1832 | regiser. */ | |
1833 | if (fde | |
1834 | && fde->stack_realign | |
2013c33b | 1835 | && REG_P (src) |
1836 | && REGNO (src) == HARD_FRAME_POINTER_REGNUM) | |
dcdf448e | 1837 | { |
dfe00a8f | 1838 | gcc_assert (cur_cfa->reg != dw_frame_pointer_regnum); |
b1613fc3 | 1839 | cur_trace->cfa_store.offset = 0; |
dcdf448e | 1840 | } |
1841 | ||
dfe00a8f | 1842 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1843 | cur_cfa->offset = cur_trace->cfa_store.offset; | |
dcdf448e | 1844 | |
1845 | if (GET_CODE (XEXP (dest, 0)) == POST_DEC) | |
b1613fc3 | 1846 | offset += -cur_trace->cfa_store.offset; |
dcdf448e | 1847 | else |
b1613fc3 | 1848 | offset = -cur_trace->cfa_store.offset; |
dcdf448e | 1849 | break; |
1850 | ||
1851 | /* Rule 12 */ | |
1852 | /* With an offset. */ | |
1853 | case PLUS: | |
1854 | case MINUS: | |
1855 | case LO_SUM: | |
1856 | { | |
559e966b | 1857 | unsigned int regno; |
dcdf448e | 1858 | |
1859 | gcc_assert (CONST_INT_P (XEXP (XEXP (dest, 0), 1)) | |
1860 | && REG_P (XEXP (XEXP (dest, 0), 0))); | |
1861 | offset = INTVAL (XEXP (XEXP (dest, 0), 1)); | |
1862 | if (GET_CODE (XEXP (dest, 0)) == MINUS) | |
1863 | offset = -offset; | |
1864 | ||
559e966b | 1865 | regno = dwf_regno (XEXP (XEXP (dest, 0), 0)); |
dcdf448e | 1866 | |
dfe00a8f | 1867 | if (cur_cfa->reg == regno) |
1868 | offset -= cur_cfa->offset; | |
b1613fc3 | 1869 | else if (cur_trace->cfa_store.reg == regno) |
1870 | offset -= cur_trace->cfa_store.offset; | |
dcdf448e | 1871 | else |
1872 | { | |
b1613fc3 | 1873 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1874 | offset -= cur_trace->cfa_temp.offset; | |
dcdf448e | 1875 | } |
1876 | } | |
1877 | break; | |
1878 | ||
1879 | /* Rule 13 */ | |
1880 | /* Without an offset. */ | |
1881 | case REG: | |
1882 | { | |
559e966b | 1883 | unsigned int regno = dwf_regno (XEXP (dest, 0)); |
dcdf448e | 1884 | |
dfe00a8f | 1885 | if (cur_cfa->reg == regno) |
1886 | offset = -cur_cfa->offset; | |
b1613fc3 | 1887 | else if (cur_trace->cfa_store.reg == regno) |
1888 | offset = -cur_trace->cfa_store.offset; | |
dcdf448e | 1889 | else |
1890 | { | |
b1613fc3 | 1891 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1892 | offset = -cur_trace->cfa_temp.offset; | |
dcdf448e | 1893 | } |
1894 | } | |
1895 | break; | |
1896 | ||
1897 | /* Rule 14 */ | |
1898 | case POST_INC: | |
b1613fc3 | 1899 | gcc_assert (cur_trace->cfa_temp.reg |
1900 | == dwf_regno (XEXP (XEXP (dest, 0), 0))); | |
1901 | offset = -cur_trace->cfa_temp.offset; | |
1902 | cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest)); | |
dcdf448e | 1903 | break; |
1904 | ||
1905 | default: | |
1906 | gcc_unreachable (); | |
1907 | } | |
1908 | ||
6ca363a7 | 1909 | /* Rule 17 */ |
1910 | /* If the source operand of this MEM operation is a memory, | |
1911 | we only care how much stack grew. */ | |
1912 | if (MEM_P (src)) | |
dcdf448e | 1913 | break; |
1914 | ||
6ca363a7 | 1915 | if (REG_P (src) |
1916 | && REGNO (src) != STACK_POINTER_REGNUM | |
dcdf448e | 1917 | && REGNO (src) != HARD_FRAME_POINTER_REGNUM |
dfe00a8f | 1918 | && dwf_regno (src) == cur_cfa->reg) |
dcdf448e | 1919 | { |
1920 | /* We're storing the current CFA reg into the stack. */ | |
1921 | ||
dfe00a8f | 1922 | if (cur_cfa->offset == 0) |
dcdf448e | 1923 | { |
1924 | /* Rule 19 */ | |
1925 | /* If stack is aligned, putting CFA reg into stack means | |
1926 | we can no longer use reg + offset to represent CFA. | |
1927 | Here we use DW_CFA_def_cfa_expression instead. The | |
1928 | result of this expression equals to the original CFA | |
1929 | value. */ | |
1930 | if (fde | |
1931 | && fde->stack_realign | |
dfe00a8f | 1932 | && cur_cfa->indirect == 0 |
1933 | && cur_cfa->reg != dw_frame_pointer_regnum) | |
dcdf448e | 1934 | { |
dfe00a8f | 1935 | gcc_assert (fde->drap_reg == cur_cfa->reg); |
dcdf448e | 1936 | |
dfe00a8f | 1937 | cur_cfa->indirect = 1; |
1938 | cur_cfa->reg = dw_frame_pointer_regnum; | |
1939 | cur_cfa->base_offset = offset; | |
1940 | cur_cfa->offset = 0; | |
dcdf448e | 1941 | |
1942 | fde->drap_reg_saved = 1; | |
dcdf448e | 1943 | break; |
1944 | } | |
1945 | ||
1946 | /* If the source register is exactly the CFA, assume | |
1947 | we're saving SP like any other register; this happens | |
1948 | on the ARM. */ | |
c746c5c3 | 1949 | queue_reg_save (stack_pointer_rtx, NULL_RTX, offset); |
dcdf448e | 1950 | break; |
1951 | } | |
1952 | else | |
1953 | { | |
1954 | /* Otherwise, we'll need to look in the stack to | |
1955 | calculate the CFA. */ | |
1956 | rtx x = XEXP (dest, 0); | |
1957 | ||
1958 | if (!REG_P (x)) | |
1959 | x = XEXP (x, 0); | |
1960 | gcc_assert (REG_P (x)); | |
1961 | ||
dfe00a8f | 1962 | cur_cfa->reg = dwf_regno (x); |
1963 | cur_cfa->base_offset = offset; | |
1964 | cur_cfa->indirect = 1; | |
dcdf448e | 1965 | break; |
1966 | } | |
1967 | } | |
1968 | ||
6ca363a7 | 1969 | if (REG_P (src)) |
1970 | span = targetm.dwarf_register_span (src); | |
fad67b80 | 1971 | else |
1972 | span = NULL; | |
1973 | ||
6ca363a7 | 1974 | if (!span) |
1975 | queue_reg_save (src, NULL_RTX, offset); | |
1976 | else | |
1977 | { | |
1978 | /* We have a PARALLEL describing where the contents of SRC live. | |
1979 | Queue register saves for each piece of the PARALLEL. */ | |
6ca363a7 | 1980 | HOST_WIDE_INT span_offset = offset; |
dcdf448e | 1981 | |
6ca363a7 | 1982 | gcc_assert (GET_CODE (span) == PARALLEL); |
dcdf448e | 1983 | |
fad67b80 | 1984 | const int par_len = XVECLEN (span, 0); |
1985 | for (int par_index = 0; par_index < par_len; par_index++) | |
6ca363a7 | 1986 | { |
1987 | rtx elem = XVECEXP (span, 0, par_index); | |
1988 | queue_reg_save (elem, NULL_RTX, span_offset); | |
1989 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); | |
1990 | } | |
1991 | } | |
dcdf448e | 1992 | break; |
1993 | ||
1994 | default: | |
1995 | gcc_unreachable (); | |
1996 | } | |
1997 | } | |
1998 | ||
dfe00a8f | 1999 | /* Record call frame debugging information for INSN, which either sets |
2000 | SP or FP (adjusting how we calculate the frame address) or saves a | |
2001 | register to the stack. */ | |
dcdf448e | 2002 | |
fe2dc6d6 | 2003 | static void |
50fc2d35 | 2004 | dwarf2out_frame_debug (rtx_insn *insn) |
dcdf448e | 2005 | { |
50fc2d35 | 2006 | rtx note, n, pat; |
dcdf448e | 2007 | bool handled_one = false; |
dcdf448e | 2008 | |
2009 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2010 | switch (REG_NOTE_KIND (note)) | |
2011 | { | |
2012 | case REG_FRAME_RELATED_EXPR: | |
50fc2d35 | 2013 | pat = XEXP (note, 0); |
dcdf448e | 2014 | goto do_frame_expr; |
2015 | ||
2016 | case REG_CFA_DEF_CFA: | |
c746c5c3 | 2017 | dwarf2out_frame_debug_def_cfa (XEXP (note, 0)); |
dcdf448e | 2018 | handled_one = true; |
2019 | break; | |
2020 | ||
2021 | case REG_CFA_ADJUST_CFA: | |
2022 | n = XEXP (note, 0); | |
2023 | if (n == NULL) | |
2024 | { | |
2025 | n = PATTERN (insn); | |
2026 | if (GET_CODE (n) == PARALLEL) | |
2027 | n = XVECEXP (n, 0, 0); | |
2028 | } | |
c746c5c3 | 2029 | dwarf2out_frame_debug_adjust_cfa (n); |
dcdf448e | 2030 | handled_one = true; |
2031 | break; | |
2032 | ||
2033 | case REG_CFA_OFFSET: | |
2034 | n = XEXP (note, 0); | |
2035 | if (n == NULL) | |
2036 | n = single_set (insn); | |
c746c5c3 | 2037 | dwarf2out_frame_debug_cfa_offset (n); |
dcdf448e | 2038 | handled_one = true; |
2039 | break; | |
2040 | ||
2041 | case REG_CFA_REGISTER: | |
2042 | n = XEXP (note, 0); | |
2043 | if (n == NULL) | |
2044 | { | |
2045 | n = PATTERN (insn); | |
2046 | if (GET_CODE (n) == PARALLEL) | |
2047 | n = XVECEXP (n, 0, 0); | |
2048 | } | |
c746c5c3 | 2049 | dwarf2out_frame_debug_cfa_register (n); |
dcdf448e | 2050 | handled_one = true; |
2051 | break; | |
2052 | ||
2053 | case REG_CFA_EXPRESSION: | |
2054 | n = XEXP (note, 0); | |
2055 | if (n == NULL) | |
2056 | n = single_set (insn); | |
c746c5c3 | 2057 | dwarf2out_frame_debug_cfa_expression (n); |
dcdf448e | 2058 | handled_one = true; |
2059 | break; | |
2060 | ||
2061 | case REG_CFA_RESTORE: | |
2062 | n = XEXP (note, 0); | |
2063 | if (n == NULL) | |
2064 | { | |
2065 | n = PATTERN (insn); | |
2066 | if (GET_CODE (n) == PARALLEL) | |
2067 | n = XVECEXP (n, 0, 0); | |
2068 | n = XEXP (n, 0); | |
2069 | } | |
c746c5c3 | 2070 | dwarf2out_frame_debug_cfa_restore (n); |
dcdf448e | 2071 | handled_one = true; |
2072 | break; | |
2073 | ||
2074 | case REG_CFA_SET_VDRAP: | |
2075 | n = XEXP (note, 0); | |
2076 | if (REG_P (n)) | |
2077 | { | |
6033bf11 | 2078 | dw_fde_ref fde = cfun->fde; |
dcdf448e | 2079 | if (fde) |
2080 | { | |
2081 | gcc_assert (fde->vdrap_reg == INVALID_REGNUM); | |
2082 | if (REG_P (n)) | |
559e966b | 2083 | fde->vdrap_reg = dwf_regno (n); |
dcdf448e | 2084 | } |
2085 | } | |
2086 | handled_one = true; | |
2087 | break; | |
2088 | ||
2089 | case REG_CFA_WINDOW_SAVE: | |
c746c5c3 | 2090 | dwarf2out_frame_debug_cfa_window_save (); |
dcdf448e | 2091 | handled_one = true; |
2092 | break; | |
2093 | ||
2094 | case REG_CFA_FLUSH_QUEUE: | |
637c318f | 2095 | /* The actual flush happens elsewhere. */ |
dcdf448e | 2096 | handled_one = true; |
2097 | break; | |
2098 | ||
2099 | default: | |
2100 | break; | |
2101 | } | |
2102 | ||
637c318f | 2103 | if (!handled_one) |
dcdf448e | 2104 | { |
50fc2d35 | 2105 | pat = PATTERN (insn); |
dcdf448e | 2106 | do_frame_expr: |
50fc2d35 | 2107 | dwarf2out_frame_debug_expr (pat); |
dcdf448e | 2108 | |
2109 | /* Check again. A parallel can save and update the same register. | |
2110 | We could probably check just once, here, but this is safer than | |
2111 | removing the check at the start of the function. */ | |
50fc2d35 | 2112 | if (clobbers_queued_reg_save (pat)) |
637c318f | 2113 | dwarf2out_flush_queued_reg_saves (); |
dcdf448e | 2114 | } |
dcdf448e | 2115 | } |
2116 | ||
0b3b5cad | 2117 | /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */ |
2118 | ||
2119 | static void | |
1b1ea44c | 2120 | change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row) |
0b3b5cad | 2121 | { |
2122 | size_t i, n_old, n_new, n_max; | |
2123 | dw_cfi_ref cfi; | |
2124 | ||
2125 | if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi)) | |
2126 | add_cfi (new_row->cfa_cfi); | |
2127 | else | |
2128 | { | |
2129 | cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa); | |
2130 | if (cfi) | |
2131 | add_cfi (cfi); | |
2132 | } | |
2133 | ||
f1f41a6c | 2134 | n_old = vec_safe_length (old_row->reg_save); |
2135 | n_new = vec_safe_length (new_row->reg_save); | |
0b3b5cad | 2136 | n_max = MAX (n_old, n_new); |
2137 | ||
2138 | for (i = 0; i < n_max; ++i) | |
2139 | { | |
2140 | dw_cfi_ref r_old = NULL, r_new = NULL; | |
2141 | ||
2142 | if (i < n_old) | |
f1f41a6c | 2143 | r_old = (*old_row->reg_save)[i]; |
0b3b5cad | 2144 | if (i < n_new) |
f1f41a6c | 2145 | r_new = (*new_row->reg_save)[i]; |
0b3b5cad | 2146 | |
2147 | if (r_old == r_new) | |
2148 | ; | |
2149 | else if (r_new == NULL) | |
2150 | add_cfi_restore (i); | |
2151 | else if (!cfi_equal_p (r_old, r_new)) | |
2152 | add_cfi (r_new); | |
2153 | } | |
2154 | } | |
2155 | ||
c746c5c3 | 2156 | /* Examine CFI and return true if a cfi label and set_loc is needed |
2157 | beforehand. Even when generating CFI assembler instructions, we | |
4a7a4715 | 2158 | still have to add the cfi to the list so that lookup_cfa_1 works |
c746c5c3 | 2159 | later on. When -g2 and above we even need to force emitting of |
2160 | CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list | |
2161 | purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa | |
2162 | and so don't use convert_cfa_to_fb_loc_list. */ | |
2163 | ||
2164 | static bool | |
2165 | cfi_label_required_p (dw_cfi_ref cfi) | |
2166 | { | |
2167 | if (!dwarf2out_do_cfi_asm ()) | |
2168 | return true; | |
2169 | ||
2170 | if (dwarf_version == 2 | |
2171 | && debug_info_level > DINFO_LEVEL_TERSE | |
2172 | && (write_symbols == DWARF2_DEBUG | |
2173 | || write_symbols == VMS_AND_DWARF2_DEBUG)) | |
2174 | { | |
2175 | switch (cfi->dw_cfi_opc) | |
2176 | { | |
2177 | case DW_CFA_def_cfa_offset: | |
2178 | case DW_CFA_def_cfa_offset_sf: | |
2179 | case DW_CFA_def_cfa_register: | |
2180 | case DW_CFA_def_cfa: | |
2181 | case DW_CFA_def_cfa_sf: | |
2182 | case DW_CFA_def_cfa_expression: | |
2183 | case DW_CFA_restore_state: | |
2184 | return true; | |
2185 | default: | |
2186 | return false; | |
2187 | } | |
2188 | } | |
2189 | return false; | |
2190 | } | |
2191 | ||
2192 | /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the | |
2193 | function's FDE, adding CFI labels and set_loc/advance_loc opcodes as | |
2194 | necessary. */ | |
2195 | static void | |
2196 | add_cfis_to_fde (void) | |
2197 | { | |
6033bf11 | 2198 | dw_fde_ref fde = cfun->fde; |
d3a42743 | 2199 | rtx_insn *insn, *next; |
c746c5c3 | 2200 | /* We always start with a function_begin label. */ |
2201 | bool first = false; | |
2202 | ||
2203 | for (insn = get_insns (); insn; insn = next) | |
2204 | { | |
2205 | next = NEXT_INSN (insn); | |
2206 | ||
2207 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
2208 | { | |
f1f41a6c | 2209 | fde->dw_fde_switch_cfi_index = vec_safe_length (fde->dw_fde_cfi); |
c746c5c3 | 2210 | /* Don't attempt to advance_loc4 between labels |
2211 | in different sections. */ | |
2212 | first = true; | |
2213 | } | |
2214 | ||
2215 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) | |
2216 | { | |
2217 | bool required = cfi_label_required_p (NOTE_CFI (insn)); | |
08cc385a | 2218 | while (next) |
2219 | if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI) | |
2220 | { | |
2221 | required |= cfi_label_required_p (NOTE_CFI (next)); | |
2222 | next = NEXT_INSN (next); | |
2223 | } | |
2224 | else if (active_insn_p (next) | |
2225 | || (NOTE_P (next) && (NOTE_KIND (next) | |
2226 | == NOTE_INSN_SWITCH_TEXT_SECTIONS))) | |
2227 | break; | |
2228 | else | |
c746c5c3 | 2229 | next = NEXT_INSN (next); |
c746c5c3 | 2230 | if (required) |
2231 | { | |
2232 | int num = dwarf2out_cfi_label_num; | |
2233 | const char *label = dwarf2out_cfi_label (); | |
2234 | dw_cfi_ref xcfi; | |
c746c5c3 | 2235 | |
2236 | /* Set the location counter to the new label. */ | |
2237 | xcfi = new_cfi (); | |
2238 | xcfi->dw_cfi_opc = (first ? DW_CFA_set_loc | |
2239 | : DW_CFA_advance_loc4); | |
2240 | xcfi->dw_cfi_oprnd1.dw_cfi_addr = label; | |
f1f41a6c | 2241 | vec_safe_push (fde->dw_fde_cfi, xcfi); |
c746c5c3 | 2242 | |
9ed997be | 2243 | rtx_note *tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn); |
c746c5c3 | 2244 | NOTE_LABEL_NUMBER (tmp) = num; |
2245 | } | |
2246 | ||
2247 | do | |
2248 | { | |
08cc385a | 2249 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) |
f1f41a6c | 2250 | vec_safe_push (fde->dw_fde_cfi, NOTE_CFI (insn)); |
c746c5c3 | 2251 | insn = NEXT_INSN (insn); |
2252 | } | |
2253 | while (insn != next); | |
2254 | first = false; | |
2255 | } | |
2256 | } | |
2257 | } | |
2258 | ||
97c251e4 | 2259 | /* If LABEL is the start of a trace, then initialize the state of that |
2260 | trace from CUR_TRACE and CUR_ROW. */ | |
b1613fc3 | 2261 | |
fe2dc6d6 | 2262 | static void |
f6d940f9 | 2263 | maybe_record_trace_start (rtx_insn *start, rtx_insn *origin) |
c746c5c3 | 2264 | { |
97c251e4 | 2265 | dw_trace_info *ti; |
dfe00a8f | 2266 | HOST_WIDE_INT args_size; |
97c251e4 | 2267 | |
2268 | ti = get_trace_info (start); | |
2269 | gcc_assert (ti != NULL); | |
dcdf448e | 2270 | |
97c251e4 | 2271 | if (dump_file) |
dcdf448e | 2272 | { |
97c251e4 | 2273 | fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n", |
ce4a64fd | 2274 | cur_trace->id, ti->id, |
97c251e4 | 2275 | (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"), |
2276 | (origin ? INSN_UID (origin) : 0)); | |
2277 | } | |
46346a52 | 2278 | |
dfe00a8f | 2279 | args_size = cur_trace->end_true_args_size; |
97c251e4 | 2280 | if (ti->beg_row == NULL) |
2281 | { | |
2282 | /* This is the first time we've encountered this trace. Propagate | |
2283 | state across the edge and push the trace onto the work list. */ | |
2284 | ti->beg_row = copy_cfi_row (cur_row); | |
dfe00a8f | 2285 | ti->beg_true_args_size = args_size; |
eb656671 | 2286 | |
97c251e4 | 2287 | ti->cfa_store = cur_trace->cfa_store; |
2288 | ti->cfa_temp = cur_trace->cfa_temp; | |
f1f41a6c | 2289 | ti->regs_saved_in_regs = cur_trace->regs_saved_in_regs.copy (); |
97c251e4 | 2290 | |
f1f41a6c | 2291 | trace_work_list.safe_push (ti); |
97c251e4 | 2292 | |
2293 | if (dump_file) | |
ce4a64fd | 2294 | fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id); |
97c251e4 | 2295 | } |
2296 | else | |
2297 | { | |
dfe00a8f | 2298 | |
97c251e4 | 2299 | /* We ought to have the same state incoming to a given trace no |
2300 | matter how we arrive at the trace. Anything else means we've | |
2301 | got some kind of optimization error. */ | |
2302 | gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row)); | |
dfe00a8f | 2303 | |
2304 | /* The args_size is allowed to conflict if it isn't actually used. */ | |
2305 | if (ti->beg_true_args_size != args_size) | |
2306 | ti->args_size_undefined = true; | |
2307 | } | |
2308 | } | |
2309 | ||
2310 | /* Similarly, but handle the args_size and CFA reset across EH | |
2311 | and non-local goto edges. */ | |
2312 | ||
2313 | static void | |
f6d940f9 | 2314 | maybe_record_trace_start_abnormal (rtx_insn *start, rtx_insn *origin) |
dfe00a8f | 2315 | { |
2316 | HOST_WIDE_INT save_args_size, delta; | |
2317 | dw_cfa_location save_cfa; | |
2318 | ||
2319 | save_args_size = cur_trace->end_true_args_size; | |
2320 | if (save_args_size == 0) | |
2321 | { | |
2322 | maybe_record_trace_start (start, origin); | |
2323 | return; | |
2324 | } | |
2325 | ||
2326 | delta = -save_args_size; | |
2327 | cur_trace->end_true_args_size = 0; | |
2328 | ||
2329 | save_cfa = cur_row->cfa; | |
2330 | if (cur_row->cfa.reg == dw_stack_pointer_regnum) | |
2331 | { | |
2332 | /* Convert a change in args_size (always a positive in the | |
2333 | direction of stack growth) to a change in stack pointer. */ | |
3764c94e | 2334 | if (!STACK_GROWS_DOWNWARD) |
2335 | delta = -delta; | |
2336 | ||
dfe00a8f | 2337 | cur_row->cfa.offset += delta; |
97c251e4 | 2338 | } |
dfe00a8f | 2339 | |
2340 | maybe_record_trace_start (start, origin); | |
2341 | ||
2342 | cur_trace->end_true_args_size = save_args_size; | |
2343 | cur_row->cfa = save_cfa; | |
97c251e4 | 2344 | } |
a6b622eb | 2345 | |
97c251e4 | 2346 | /* Propagate CUR_TRACE state to the destinations implied by INSN. */ |
2347 | /* ??? Sadly, this is in large part a duplicate of make_edges. */ | |
2348 | ||
2349 | static void | |
f6d940f9 | 2350 | create_trace_edges (rtx_insn *insn) |
97c251e4 | 2351 | { |
ae799283 | 2352 | rtx tmp; |
97c251e4 | 2353 | int i, n; |
2354 | ||
2355 | if (JUMP_P (insn)) | |
2356 | { | |
c86d86ff | 2357 | rtx_jump_table_data *table; |
2358 | ||
97c251e4 | 2359 | if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) |
dfe00a8f | 2360 | return; |
2361 | ||
c86d86ff | 2362 | if (tablejump_p (insn, NULL, &table)) |
46346a52 | 2363 | { |
b77639be | 2364 | rtvec vec = table->get_labels (); |
97c251e4 | 2365 | |
2366 | n = GET_NUM_ELEM (vec); | |
2367 | for (i = 0; i < n; ++i) | |
2368 | { | |
f6d940f9 | 2369 | rtx_insn *lab = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, i), 0)); |
dfe00a8f | 2370 | maybe_record_trace_start (lab, insn); |
97c251e4 | 2371 | } |
2372 | } | |
2373 | else if (computed_jump_p (insn)) | |
46346a52 | 2374 | { |
231c0441 | 2375 | for (rtx_insn_list *lab = forced_labels; lab; lab = lab->next ()) |
2376 | maybe_record_trace_start (lab->insn (), insn); | |
97c251e4 | 2377 | } |
2378 | else if (returnjump_p (insn)) | |
2379 | ; | |
2380 | else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL) | |
2381 | { | |
2382 | n = ASM_OPERANDS_LABEL_LENGTH (tmp); | |
2383 | for (i = 0; i < n; ++i) | |
46346a52 | 2384 | { |
f6d940f9 | 2385 | rtx_insn *lab = |
2386 | as_a <rtx_insn *> (XEXP (ASM_OPERANDS_LABEL (tmp, i), 0)); | |
dfe00a8f | 2387 | maybe_record_trace_start (lab, insn); |
97c251e4 | 2388 | } |
2389 | } | |
2390 | else | |
2391 | { | |
f6d940f9 | 2392 | rtx_insn *lab = JUMP_LABEL_AS_INSN (insn); |
97c251e4 | 2393 | gcc_assert (lab != NULL); |
dfe00a8f | 2394 | maybe_record_trace_start (lab, insn); |
97c251e4 | 2395 | } |
2396 | } | |
2397 | else if (CALL_P (insn)) | |
2398 | { | |
2399 | /* Sibling calls don't have edges inside this function. */ | |
2400 | if (SIBLING_CALL_P (insn)) | |
2401 | return; | |
de9b0618 | 2402 | |
97c251e4 | 2403 | /* Process non-local goto edges. */ |
2404 | if (can_nonlocal_goto (insn)) | |
a4de1c23 | 2405 | for (rtx_insn_list *lab = nonlocal_goto_handler_labels; |
6e16e157 | 2406 | lab; |
2407 | lab = lab->next ()) | |
a4de1c23 | 2408 | maybe_record_trace_start_abnormal (lab->insn (), insn); |
97c251e4 | 2409 | } |
b873289f | 2410 | else if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) |
ad5618b3 | 2411 | { |
b873289f | 2412 | int i, n = seq->len (); |
ad5618b3 | 2413 | for (i = 0; i < n; ++i) |
b873289f | 2414 | create_trace_edges (seq->insn (i)); |
ad5618b3 | 2415 | return; |
2416 | } | |
de9b0618 | 2417 | |
97c251e4 | 2418 | /* Process EH edges. */ |
2419 | if (CALL_P (insn) || cfun->can_throw_non_call_exceptions) | |
2420 | { | |
2421 | eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn); | |
2422 | if (lp) | |
dfe00a8f | 2423 | maybe_record_trace_start_abnormal (lp->landing_pad, insn); |
97c251e4 | 2424 | } |
2425 | } | |
0b3b5cad | 2426 | |
4d256106 | 2427 | /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */ |
2428 | ||
2429 | static void | |
50fc2d35 | 2430 | scan_insn_after (rtx_insn *insn) |
4d256106 | 2431 | { |
2432 | if (RTX_FRAME_RELATED_P (insn)) | |
2433 | dwarf2out_frame_debug (insn); | |
2434 | notice_args_size (insn); | |
2435 | } | |
2436 | ||
97c251e4 | 2437 | /* Scan the trace beginning at INSN and create the CFI notes for the |
2438 | instructions therein. */ | |
2439 | ||
2440 | static void | |
2441 | scan_trace (dw_trace_info *trace) | |
2442 | { | |
f6d940f9 | 2443 | rtx_insn *prev, *insn = trace->head; |
dfe00a8f | 2444 | dw_cfa_location this_cfa; |
97c251e4 | 2445 | |
2446 | if (dump_file) | |
2447 | fprintf (dump_file, "Processing trace %u : start at %s %d\n", | |
ce4a64fd | 2448 | trace->id, rtx_name[(int) GET_CODE (insn)], |
97c251e4 | 2449 | INSN_UID (insn)); |
2450 | ||
2451 | trace->end_row = copy_cfi_row (trace->beg_row); | |
dfe00a8f | 2452 | trace->end_true_args_size = trace->beg_true_args_size; |
97c251e4 | 2453 | |
2454 | cur_trace = trace; | |
2455 | cur_row = trace->end_row; | |
dfe00a8f | 2456 | |
2457 | this_cfa = cur_row->cfa; | |
2458 | cur_cfa = &this_cfa; | |
97c251e4 | 2459 | |
4d256106 | 2460 | for (prev = insn, insn = NEXT_INSN (insn); |
2461 | insn; | |
2462 | prev = insn, insn = NEXT_INSN (insn)) | |
97c251e4 | 2463 | { |
f6d940f9 | 2464 | rtx_insn *control; |
4d256106 | 2465 | |
dfe00a8f | 2466 | /* Do everything that happens "before" the insn. */ |
4d256106 | 2467 | add_cfi_insn = prev; |
97c251e4 | 2468 | |
2469 | /* Notice the end of a trace. */ | |
dfe00a8f | 2470 | if (BARRIER_P (insn)) |
2471 | { | |
2472 | /* Don't bother saving the unneeded queued registers at all. */ | |
f1f41a6c | 2473 | queued_reg_saves.truncate (0); |
dfe00a8f | 2474 | break; |
2475 | } | |
2476 | if (save_point_p (insn)) | |
97c251e4 | 2477 | { |
97c251e4 | 2478 | /* Propagate across fallthru edges. */ |
dfe00a8f | 2479 | dwarf2out_flush_queued_reg_saves (); |
2480 | maybe_record_trace_start (insn, NULL); | |
97c251e4 | 2481 | break; |
46346a52 | 2482 | } |
2483 | ||
97c251e4 | 2484 | if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn)) |
46346a52 | 2485 | continue; |
2486 | ||
4d256106 | 2487 | /* Handle all changes to the row state. Sequences require special |
2488 | handling for the positioning of the notes. */ | |
b873289f | 2489 | if (rtx_sequence *pat = dyn_cast <rtx_sequence *> (PATTERN (insn))) |
46346a52 | 2490 | { |
50fc2d35 | 2491 | rtx_insn *elt; |
b873289f | 2492 | int i, n = pat->len (); |
dfe00a8f | 2493 | |
f6d940f9 | 2494 | control = pat->insn (0); |
4d256106 | 2495 | if (can_throw_internal (control)) |
2496 | notice_eh_throw (control); | |
2497 | dwarf2out_flush_queued_reg_saves (); | |
2498 | ||
7e66a69e | 2499 | if (JUMP_P (control) && INSN_ANNULLED_BRANCH_P (control)) |
97c251e4 | 2500 | { |
dfe00a8f | 2501 | /* ??? Hopefully multiple delay slots are not annulled. */ |
2502 | gcc_assert (n == 2); | |
4d256106 | 2503 | gcc_assert (!RTX_FRAME_RELATED_P (control)); |
2504 | gcc_assert (!find_reg_note (control, REG_ARGS_SIZE, NULL)); | |
2505 | ||
50fc2d35 | 2506 | elt = pat->insn (1); |
dfe00a8f | 2507 | |
dfe00a8f | 2508 | if (INSN_FROM_TARGET_P (elt)) |
2509 | { | |
2510 | HOST_WIDE_INT restore_args_size; | |
e2ab608c | 2511 | cfi_vec save_row_reg_save; |
97c251e4 | 2512 | |
dfed30bc | 2513 | /* If ELT is an instruction from target of an annulled |
2514 | branch, the effects are for the target only and so | |
2515 | the args_size and CFA along the current path | |
2516 | shouldn't change. */ | |
4d256106 | 2517 | add_cfi_insn = NULL; |
dfe00a8f | 2518 | restore_args_size = cur_trace->end_true_args_size; |
2519 | cur_cfa = &cur_row->cfa; | |
f1f41a6c | 2520 | save_row_reg_save = vec_safe_copy (cur_row->reg_save); |
46346a52 | 2521 | |
4d256106 | 2522 | scan_insn_after (elt); |
2523 | ||
2524 | /* ??? Should we instead save the entire row state? */ | |
f1f41a6c | 2525 | gcc_assert (!queued_reg_saves.length ()); |
4d256106 | 2526 | |
2527 | create_trace_edges (control); | |
46346a52 | 2528 | |
dfe00a8f | 2529 | cur_trace->end_true_args_size = restore_args_size; |
2530 | cur_row->cfa = this_cfa; | |
e2ab608c | 2531 | cur_row->reg_save = save_row_reg_save; |
dfe00a8f | 2532 | cur_cfa = &this_cfa; |
dfe00a8f | 2533 | } |
dfed30bc | 2534 | else |
2535 | { | |
2536 | /* If ELT is a annulled branch-taken instruction (i.e. | |
2537 | executed only when branch is not taken), the args_size | |
2538 | and CFA should not change through the jump. */ | |
2539 | create_trace_edges (control); | |
2540 | ||
2541 | /* Update and continue with the trace. */ | |
2542 | add_cfi_insn = insn; | |
2543 | scan_insn_after (elt); | |
2544 | def_cfa_1 (&this_cfa); | |
2545 | } | |
2546 | continue; | |
dfe00a8f | 2547 | } |
2548 | ||
4d256106 | 2549 | /* The insns in the delay slot should all be considered to happen |
2550 | "before" a call insn. Consider a call with a stack pointer | |
2551 | adjustment in the delay slot. The backtrace from the callee | |
2552 | should include the sp adjustment. Unfortunately, that leaves | |
2553 | us with an unavoidable unwinding error exactly at the call insn | |
2554 | itself. For jump insns we'd prefer to avoid this error by | |
2555 | placing the notes after the sequence. */ | |
2556 | if (JUMP_P (control)) | |
2557 | add_cfi_insn = insn; | |
2558 | ||
dfe00a8f | 2559 | for (i = 1; i < n; ++i) |
2560 | { | |
50fc2d35 | 2561 | elt = pat->insn (i); |
4d256106 | 2562 | scan_insn_after (elt); |
dfe00a8f | 2563 | } |
4d256106 | 2564 | |
2565 | /* Make sure any register saves are visible at the jump target. */ | |
2566 | dwarf2out_flush_queued_reg_saves (); | |
637c318f | 2567 | any_cfis_emitted = false; |
4d256106 | 2568 | |
2569 | /* However, if there is some adjustment on the call itself, e.g. | |
2570 | a call_pop, that action should be considered to happen after | |
2571 | the call returns. */ | |
2572 | add_cfi_insn = insn; | |
2573 | scan_insn_after (control); | |
97c251e4 | 2574 | } |
dfe00a8f | 2575 | else |
4d256106 | 2576 | { |
2577 | /* Flush data before calls and jumps, and of course if necessary. */ | |
2578 | if (can_throw_internal (insn)) | |
2579 | { | |
2580 | notice_eh_throw (insn); | |
2581 | dwarf2out_flush_queued_reg_saves (); | |
2582 | } | |
2583 | else if (!NONJUMP_INSN_P (insn) | |
2584 | || clobbers_queued_reg_save (insn) | |
2585 | || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) | |
2586 | dwarf2out_flush_queued_reg_saves (); | |
637c318f | 2587 | any_cfis_emitted = false; |
4d256106 | 2588 | |
2589 | add_cfi_insn = insn; | |
2590 | scan_insn_after (insn); | |
2591 | control = insn; | |
2592 | } | |
dfe00a8f | 2593 | |
2594 | /* Between frame-related-p and args_size we might have otherwise | |
2595 | emitted two cfa adjustments. Do it now. */ | |
2596 | def_cfa_1 (&this_cfa); | |
a6b622eb | 2597 | |
637c318f | 2598 | /* Minimize the number of advances by emitting the entire queue |
2599 | once anything is emitted. */ | |
2600 | if (any_cfis_emitted | |
2601 | || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) | |
2602 | dwarf2out_flush_queued_reg_saves (); | |
2603 | ||
97c251e4 | 2604 | /* Note that a test for control_flow_insn_p does exactly the |
2605 | same tests as are done to actually create the edges. So | |
2606 | always call the routine and let it not create edges for | |
2607 | non-control-flow insns. */ | |
4d256106 | 2608 | create_trace_edges (control); |
dcdf448e | 2609 | } |
a6b622eb | 2610 | |
7b1c31a0 | 2611 | add_cfi_insn = NULL; |
97c251e4 | 2612 | cur_row = NULL; |
2613 | cur_trace = NULL; | |
dfe00a8f | 2614 | cur_cfa = NULL; |
dcdf448e | 2615 | } |
2616 | ||
97c251e4 | 2617 | /* Scan the function and create the initial set of CFI notes. */ |
dcdf448e | 2618 | |
46346a52 | 2619 | static void |
97c251e4 | 2620 | create_cfi_notes (void) |
dcdf448e | 2621 | { |
97c251e4 | 2622 | dw_trace_info *ti; |
dcdf448e | 2623 | |
f1f41a6c | 2624 | gcc_checking_assert (!queued_reg_saves.exists ()); |
2625 | gcc_checking_assert (!trace_work_list.exists ()); | |
dcdf448e | 2626 | |
97c251e4 | 2627 | /* Always begin at the entry trace. */ |
f1f41a6c | 2628 | ti = &trace_info[0]; |
97c251e4 | 2629 | scan_trace (ti); |
dcdf448e | 2630 | |
f1f41a6c | 2631 | while (!trace_work_list.is_empty ()) |
97c251e4 | 2632 | { |
f1f41a6c | 2633 | ti = trace_work_list.pop (); |
97c251e4 | 2634 | scan_trace (ti); |
dcdf448e | 2635 | } |
2636 | ||
f1f41a6c | 2637 | queued_reg_saves.release (); |
2638 | trace_work_list.release (); | |
97c251e4 | 2639 | } |
dcdf448e | 2640 | |
ce4a64fd | 2641 | /* Return the insn before the first NOTE_INSN_CFI after START. */ |
2642 | ||
4cd001d5 | 2643 | static rtx_insn * |
2644 | before_next_cfi_note (rtx_insn *start) | |
ce4a64fd | 2645 | { |
4cd001d5 | 2646 | rtx_insn *prev = start; |
ce4a64fd | 2647 | while (start) |
2648 | { | |
2649 | if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI) | |
2650 | return prev; | |
2651 | prev = start; | |
2652 | start = NEXT_INSN (start); | |
2653 | } | |
2654 | gcc_unreachable (); | |
2655 | } | |
2656 | ||
97c251e4 | 2657 | /* Insert CFI notes between traces to properly change state between them. */ |
dcdf448e | 2658 | |
97c251e4 | 2659 | static void |
2660 | connect_traces (void) | |
2661 | { | |
f1f41a6c | 2662 | unsigned i, n = trace_info.length (); |
97c251e4 | 2663 | dw_trace_info *prev_ti, *ti; |
2664 | ||
ce4a64fd | 2665 | /* ??? Ideally, we should have both queued and processed every trace. |
2666 | However the current representation of constant pools on various targets | |
2667 | is indistinguishable from unreachable code. Assume for the moment that | |
2668 | we can simply skip over such traces. */ | |
2669 | /* ??? Consider creating a DATA_INSN rtx code to indicate that | |
2670 | these are not "real" instructions, and should not be considered. | |
2671 | This could be generically useful for tablejump data as well. */ | |
2672 | /* Remove all unprocessed traces from the list. */ | |
2673 | for (i = n - 1; i > 0; --i) | |
2674 | { | |
f1f41a6c | 2675 | ti = &trace_info[i]; |
ce4a64fd | 2676 | if (ti->beg_row == NULL) |
2677 | { | |
f1f41a6c | 2678 | trace_info.ordered_remove (i); |
ce4a64fd | 2679 | n -= 1; |
2680 | } | |
2681 | else | |
2682 | gcc_assert (ti->end_row != NULL); | |
2683 | } | |
97c251e4 | 2684 | |
ce4a64fd | 2685 | /* Work from the end back to the beginning. This lets us easily insert |
2686 | remember/restore_state notes in the correct order wrt other notes. */ | |
f1f41a6c | 2687 | prev_ti = &trace_info[n - 1]; |
ce4a64fd | 2688 | for (i = n - 1; i > 0; --i) |
dcdf448e | 2689 | { |
97c251e4 | 2690 | dw_cfi_row *old_row; |
dcdf448e | 2691 | |
ce4a64fd | 2692 | ti = prev_ti; |
f1f41a6c | 2693 | prev_ti = &trace_info[i - 1]; |
dcdf448e | 2694 | |
ce4a64fd | 2695 | add_cfi_insn = ti->head; |
97c251e4 | 2696 | |
2697 | /* In dwarf2out_switch_text_section, we'll begin a new FDE | |
2698 | for the portion of the function in the alternate text | |
2699 | section. The row state at the very beginning of that | |
2700 | new FDE will be exactly the row state from the CIE. */ | |
2701 | if (ti->switch_sections) | |
2702 | old_row = cie_cfi_row; | |
2703 | else | |
ce4a64fd | 2704 | { |
2705 | old_row = prev_ti->end_row; | |
2706 | /* If there's no change from the previous end state, fine. */ | |
2707 | if (cfi_row_equal_p (old_row, ti->beg_row)) | |
2708 | ; | |
2709 | /* Otherwise check for the common case of sharing state with | |
2710 | the beginning of an epilogue, but not the end. Insert | |
2711 | remember/restore opcodes in that case. */ | |
2712 | else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row)) | |
2713 | { | |
2714 | dw_cfi_ref cfi; | |
2715 | ||
2716 | /* Note that if we blindly insert the remember at the | |
2717 | start of the trace, we can wind up increasing the | |
2718 | size of the unwind info due to extra advance opcodes. | |
2719 | Instead, put the remember immediately before the next | |
2720 | state change. We know there must be one, because the | |
2721 | state at the beginning and head of the trace differ. */ | |
2722 | add_cfi_insn = before_next_cfi_note (prev_ti->head); | |
2723 | cfi = new_cfi (); | |
2724 | cfi->dw_cfi_opc = DW_CFA_remember_state; | |
2725 | add_cfi (cfi); | |
2726 | ||
2727 | add_cfi_insn = ti->head; | |
2728 | cfi = new_cfi (); | |
2729 | cfi->dw_cfi_opc = DW_CFA_restore_state; | |
2730 | add_cfi (cfi); | |
2731 | ||
2732 | old_row = prev_ti->beg_row; | |
2733 | } | |
2734 | /* Otherwise, we'll simply change state from the previous end. */ | |
2735 | } | |
97c251e4 | 2736 | |
97c251e4 | 2737 | change_cfi_row (old_row, ti->beg_row); |
2738 | ||
2739 | if (dump_file && add_cfi_insn != ti->head) | |
2740 | { | |
4cd001d5 | 2741 | rtx_insn *note; |
97c251e4 | 2742 | |
ce4a64fd | 2743 | fprintf (dump_file, "Fixup between trace %u and %u:\n", |
2744 | prev_ti->id, ti->id); | |
97c251e4 | 2745 | |
2746 | note = ti->head; | |
2747 | do | |
2748 | { | |
2749 | note = NEXT_INSN (note); | |
2750 | gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI); | |
2751 | output_cfi_directive (dump_file, NOTE_CFI (note)); | |
2752 | } | |
2753 | while (note != add_cfi_insn); | |
2754 | } | |
2755 | } | |
dfe00a8f | 2756 | |
2757 | /* Connect args_size between traces that have can_throw_internal insns. */ | |
f1f41a6c | 2758 | if (cfun->eh->lp_array) |
dfe00a8f | 2759 | { |
2760 | HOST_WIDE_INT prev_args_size = 0; | |
2761 | ||
2762 | for (i = 0; i < n; ++i) | |
2763 | { | |
f1f41a6c | 2764 | ti = &trace_info[i]; |
dfe00a8f | 2765 | |
2766 | if (ti->switch_sections) | |
2767 | prev_args_size = 0; | |
2768 | if (ti->eh_head == NULL) | |
2769 | continue; | |
2770 | gcc_assert (!ti->args_size_undefined); | |
2771 | ||
2772 | if (ti->beg_delay_args_size != prev_args_size) | |
2773 | { | |
2774 | /* ??? Search back to previous CFI note. */ | |
2775 | add_cfi_insn = PREV_INSN (ti->eh_head); | |
2776 | add_cfi_args_size (ti->beg_delay_args_size); | |
2777 | } | |
2778 | ||
2779 | prev_args_size = ti->end_delay_args_size; | |
2780 | } | |
2781 | } | |
dcdf448e | 2782 | } |
2783 | ||
97c251e4 | 2784 | /* Set up the pseudo-cfg of instruction traces, as described at the |
2785 | block comment at the top of the file. */ | |
dcdf448e | 2786 | |
46346a52 | 2787 | static void |
97c251e4 | 2788 | create_pseudo_cfg (void) |
dcdf448e | 2789 | { |
97c251e4 | 2790 | bool saw_barrier, switch_sections; |
e82e4eb5 | 2791 | dw_trace_info ti; |
d3a42743 | 2792 | rtx_insn *insn; |
97c251e4 | 2793 | unsigned i; |
2794 | ||
2795 | /* The first trace begins at the start of the function, | |
2796 | and begins with the CIE row state. */ | |
f1f41a6c | 2797 | trace_info.create (16); |
e82e4eb5 | 2798 | memset (&ti, 0, sizeof (ti)); |
2799 | ti.head = get_insns (); | |
2800 | ti.beg_row = cie_cfi_row; | |
2801 | ti.cfa_store = cie_cfi_row->cfa; | |
2802 | ti.cfa_temp.reg = INVALID_REGNUM; | |
f1f41a6c | 2803 | trace_info.quick_push (ti); |
97c251e4 | 2804 | |
97c251e4 | 2805 | if (cie_return_save) |
f1f41a6c | 2806 | ti.regs_saved_in_regs.safe_push (*cie_return_save); |
dcdf448e | 2807 | |
97c251e4 | 2808 | /* Walk all the insns, collecting start of trace locations. */ |
2809 | saw_barrier = false; | |
2810 | switch_sections = false; | |
2811 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2812 | { | |
2813 | if (BARRIER_P (insn)) | |
2814 | saw_barrier = true; | |
2815 | else if (NOTE_P (insn) | |
2816 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
2817 | { | |
2818 | /* We should have just seen a barrier. */ | |
2819 | gcc_assert (saw_barrier); | |
2820 | switch_sections = true; | |
2821 | } | |
2822 | /* Watch out for save_point notes between basic blocks. | |
2823 | In particular, a note after a barrier. Do not record these, | |
2824 | delaying trace creation until the label. */ | |
2825 | else if (save_point_p (insn) | |
2826 | && (LABEL_P (insn) || !saw_barrier)) | |
2827 | { | |
e82e4eb5 | 2828 | memset (&ti, 0, sizeof (ti)); |
2829 | ti.head = insn; | |
2830 | ti.switch_sections = switch_sections; | |
91c603de | 2831 | ti.id = trace_info.length (); |
f1f41a6c | 2832 | trace_info.safe_push (ti); |
97c251e4 | 2833 | |
2834 | saw_barrier = false; | |
2835 | switch_sections = false; | |
2836 | } | |
2837 | } | |
2838 | ||
2839 | /* Create the trace index after we've finished building trace_info, | |
2840 | avoiding stale pointer problems due to reallocation. */ | |
c1f445d2 | 2841 | trace_index |
2842 | = new hash_table<trace_info_hasher> (trace_info.length ()); | |
e82e4eb5 | 2843 | dw_trace_info *tp; |
f1f41a6c | 2844 | FOR_EACH_VEC_ELT (trace_info, i, tp) |
97c251e4 | 2845 | { |
d9dd21a8 | 2846 | dw_trace_info **slot; |
dcdf448e | 2847 | |
97c251e4 | 2848 | if (dump_file) |
91c603de | 2849 | fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", tp->id, |
e82e4eb5 | 2850 | rtx_name[(int) GET_CODE (tp->head)], INSN_UID (tp->head), |
2851 | tp->switch_sections ? " (section switch)" : ""); | |
97c251e4 | 2852 | |
c1f445d2 | 2853 | slot = trace_index->find_slot_with_hash (tp, INSN_UID (tp->head), INSERT); |
97c251e4 | 2854 | gcc_assert (*slot == NULL); |
d9dd21a8 | 2855 | *slot = tp; |
97c251e4 | 2856 | } |
dcdf448e | 2857 | } |
97c251e4 | 2858 | |
6ca363a7 | 2859 | /* Record the initial position of the return address. RTL is |
2860 | INCOMING_RETURN_ADDR_RTX. */ | |
2861 | ||
2862 | static void | |
2863 | initial_return_save (rtx rtl) | |
2864 | { | |
2865 | unsigned int reg = INVALID_REGNUM; | |
2866 | HOST_WIDE_INT offset = 0; | |
2867 | ||
2868 | switch (GET_CODE (rtl)) | |
2869 | { | |
2870 | case REG: | |
2871 | /* RA is in a register. */ | |
559e966b | 2872 | reg = dwf_regno (rtl); |
6ca363a7 | 2873 | break; |
2874 | ||
2875 | case MEM: | |
2876 | /* RA is on the stack. */ | |
2877 | rtl = XEXP (rtl, 0); | |
2878 | switch (GET_CODE (rtl)) | |
2879 | { | |
2880 | case REG: | |
2881 | gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM); | |
2882 | offset = 0; | |
2883 | break; | |
2884 | ||
2885 | case PLUS: | |
2886 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
2887 | offset = INTVAL (XEXP (rtl, 1)); | |
2888 | break; | |
2889 | ||
2890 | case MINUS: | |
2891 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
2892 | offset = -INTVAL (XEXP (rtl, 1)); | |
2893 | break; | |
2894 | ||
2895 | default: | |
2896 | gcc_unreachable (); | |
2897 | } | |
2898 | ||
2899 | break; | |
2900 | ||
2901 | case PLUS: | |
2902 | /* The return address is at some offset from any value we can | |
2903 | actually load. For instance, on the SPARC it is in %i7+8. Just | |
2904 | ignore the offset for now; it doesn't matter for unwinding frames. */ | |
2905 | gcc_assert (CONST_INT_P (XEXP (rtl, 1))); | |
2906 | initial_return_save (XEXP (rtl, 0)); | |
2907 | return; | |
2908 | ||
2909 | default: | |
2910 | gcc_unreachable (); | |
2911 | } | |
2912 | ||
2913 | if (reg != DWARF_FRAME_RETURN_COLUMN) | |
2914 | { | |
2915 | if (reg != INVALID_REGNUM) | |
2916 | record_reg_saved_in_reg (rtl, pc_rtx); | |
eb93b3f4 | 2917 | reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset); |
6ca363a7 | 2918 | } |
2919 | } | |
dcdf448e | 2920 | |
b1613fc3 | 2921 | static void |
2922 | create_cie_data (void) | |
2923 | { | |
2924 | dw_cfa_location loc; | |
2925 | dw_trace_info cie_trace; | |
2926 | ||
2927 | dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); | |
b1613fc3 | 2928 | |
9af5ce0c | 2929 | memset (&cie_trace, 0, sizeof (cie_trace)); |
b1613fc3 | 2930 | cur_trace = &cie_trace; |
2931 | ||
2932 | add_cfi_vec = &cie_cfi_vec; | |
2933 | cie_cfi_row = cur_row = new_cfi_row (); | |
2934 | ||
2935 | /* On entry, the Canonical Frame Address is at SP. */ | |
9af5ce0c | 2936 | memset (&loc, 0, sizeof (loc)); |
b1613fc3 | 2937 | loc.reg = dw_stack_pointer_regnum; |
2938 | loc.offset = INCOMING_FRAME_SP_OFFSET; | |
2939 | def_cfa_1 (&loc); | |
2940 | ||
2941 | if (targetm.debug_unwind_info () == UI_DWARF2 | |
2942 | || targetm_common.except_unwind_info (&global_options) == UI_DWARF2) | |
2943 | { | |
2944 | initial_return_save (INCOMING_RETURN_ADDR_RTX); | |
2945 | ||
2946 | /* For a few targets, we have the return address incoming into a | |
2947 | register, but choose a different return column. This will result | |
2948 | in a DW_CFA_register for the return, and an entry in | |
2949 | regs_saved_in_regs to match. If the target later stores that | |
2950 | return address register to the stack, we want to be able to emit | |
2951 | the DW_CFA_offset against the return column, not the intermediate | |
2952 | save register. Save the contents of regs_saved_in_regs so that | |
2953 | we can re-initialize it at the start of each function. */ | |
f1f41a6c | 2954 | switch (cie_trace.regs_saved_in_regs.length ()) |
b1613fc3 | 2955 | { |
2956 | case 0: | |
2957 | break; | |
2958 | case 1: | |
25a27413 | 2959 | cie_return_save = ggc_alloc<reg_saved_in_data> (); |
f1f41a6c | 2960 | *cie_return_save = cie_trace.regs_saved_in_regs[0]; |
2961 | cie_trace.regs_saved_in_regs.release (); | |
b1613fc3 | 2962 | break; |
2963 | default: | |
2964 | gcc_unreachable (); | |
2965 | } | |
2966 | } | |
2967 | ||
2968 | add_cfi_vec = NULL; | |
2969 | cur_row = NULL; | |
2970 | cur_trace = NULL; | |
2971 | } | |
2972 | ||
fe2dc6d6 | 2973 | /* Annotate the function with NOTE_INSN_CFI notes to record the CFI |
2974 | state at each location within the function. These notes will be | |
2975 | emitted during pass_final. */ | |
dcdf448e | 2976 | |
fe2dc6d6 | 2977 | static unsigned int |
2978 | execute_dwarf2_frame (void) | |
dcdf448e | 2979 | { |
2d4340b0 | 2980 | /* Different HARD_FRAME_POINTER_REGNUM might coexist in the same file. */ |
2981 | dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM); | |
2982 | ||
fe2dc6d6 | 2983 | /* The first time we're called, compute the incoming frame state. */ |
2984 | if (cie_cfi_vec == NULL) | |
b1613fc3 | 2985 | create_cie_data (); |
d4898332 | 2986 | |
fe2dc6d6 | 2987 | dwarf2out_alloc_current_fde (); |
2988 | ||
97c251e4 | 2989 | create_pseudo_cfg (); |
2990 | ||
fe2dc6d6 | 2991 | /* Do the work. */ |
2992 | create_cfi_notes (); | |
97c251e4 | 2993 | connect_traces (); |
fe2dc6d6 | 2994 | add_cfis_to_fde (); |
2995 | ||
97c251e4 | 2996 | /* Free all the data we allocated. */ |
2997 | { | |
2998 | size_t i; | |
2999 | dw_trace_info *ti; | |
dcdf448e | 3000 | |
f1f41a6c | 3001 | FOR_EACH_VEC_ELT (trace_info, i, ti) |
3002 | ti->regs_saved_in_regs.release (); | |
97c251e4 | 3003 | } |
f1f41a6c | 3004 | trace_info.release (); |
97c251e4 | 3005 | |
c1f445d2 | 3006 | delete trace_index; |
3007 | trace_index = NULL; | |
eb93b3f4 | 3008 | |
fe2dc6d6 | 3009 | return 0; |
dcdf448e | 3010 | } |
3011 | \f | |
04dfc41a | 3012 | /* Convert a DWARF call frame info. operation to its string name */ |
3013 | ||
3014 | static const char * | |
3015 | dwarf_cfi_name (unsigned int cfi_opc) | |
3016 | { | |
c9f46599 | 3017 | const char *name = get_DW_CFA_name (cfi_opc); |
04dfc41a | 3018 | |
c9f46599 | 3019 | if (name != NULL) |
3020 | return name; | |
04dfc41a | 3021 | |
c9f46599 | 3022 | return "DW_CFA_<unknown>"; |
04dfc41a | 3023 | } |
3024 | ||
3025 | /* This routine will generate the correct assembly data for a location | |
3026 | description based on a cfi entry with a complex address. */ | |
3027 | ||
3028 | static void | |
3029 | output_cfa_loc (dw_cfi_ref cfi, int for_eh) | |
3030 | { | |
3031 | dw_loc_descr_ref loc; | |
3032 | unsigned long size; | |
3033 | ||
3034 | if (cfi->dw_cfi_opc == DW_CFA_expression) | |
3035 | { | |
b1613fc3 | 3036 | unsigned r = |
04dfc41a | 3037 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); |
3038 | dw2_asm_output_data (1, r, NULL); | |
3039 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3040 | } | |
3041 | else | |
3042 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3043 | ||
3044 | /* Output the size of the block. */ | |
3045 | size = size_of_locs (loc); | |
3046 | dw2_asm_output_data_uleb128 (size, NULL); | |
3047 | ||
3048 | /* Now output the operations themselves. */ | |
3049 | output_loc_sequence (loc, for_eh); | |
3050 | } | |
3051 | ||
3052 | /* Similar, but used for .cfi_escape. */ | |
3053 | ||
3054 | static void | |
3055 | output_cfa_loc_raw (dw_cfi_ref cfi) | |
3056 | { | |
3057 | dw_loc_descr_ref loc; | |
3058 | unsigned long size; | |
3059 | ||
3060 | if (cfi->dw_cfi_opc == DW_CFA_expression) | |
3061 | { | |
b1613fc3 | 3062 | unsigned r = |
04dfc41a | 3063 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); |
3064 | fprintf (asm_out_file, "%#x,", r); | |
3065 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3066 | } | |
3067 | else | |
3068 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3069 | ||
3070 | /* Output the size of the block. */ | |
3071 | size = size_of_locs (loc); | |
3072 | dw2_asm_output_data_uleb128_raw (size); | |
3073 | fputc (',', asm_out_file); | |
3074 | ||
3075 | /* Now output the operations themselves. */ | |
3076 | output_loc_sequence_raw (loc); | |
3077 | } | |
3078 | ||
3079 | /* Output a Call Frame Information opcode and its operand(s). */ | |
3080 | ||
3081 | void | |
3082 | output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh) | |
3083 | { | |
3084 | unsigned long r; | |
3085 | HOST_WIDE_INT off; | |
3086 | ||
3087 | if (cfi->dw_cfi_opc == DW_CFA_advance_loc) | |
3088 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | |
3089 | | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)), | |
3090 | "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX, | |
3091 | ((unsigned HOST_WIDE_INT) | |
3092 | cfi->dw_cfi_oprnd1.dw_cfi_offset)); | |
3093 | else if (cfi->dw_cfi_opc == DW_CFA_offset) | |
3094 | { | |
3095 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3096 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3097 | "DW_CFA_offset, column %#lx", r); | |
3098 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3099 | dw2_asm_output_data_uleb128 (off, NULL); | |
3100 | } | |
3101 | else if (cfi->dw_cfi_opc == DW_CFA_restore) | |
3102 | { | |
3103 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3104 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3105 | "DW_CFA_restore, column %#lx", r); | |
3106 | } | |
3107 | else | |
3108 | { | |
3109 | dw2_asm_output_data (1, cfi->dw_cfi_opc, | |
3110 | "%s", dwarf_cfi_name (cfi->dw_cfi_opc)); | |
3111 | ||
3112 | switch (cfi->dw_cfi_opc) | |
3113 | { | |
3114 | case DW_CFA_set_loc: | |
3115 | if (for_eh) | |
3116 | dw2_asm_output_encoded_addr_rtx ( | |
3117 | ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0), | |
3118 | gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr), | |
3119 | false, NULL); | |
3120 | else | |
3121 | dw2_asm_output_addr (DWARF2_ADDR_SIZE, | |
3122 | cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL); | |
3123 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3124 | break; | |
3125 | ||
3126 | case DW_CFA_advance_loc1: | |
3127 | dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3128 | fde->dw_fde_current_label, NULL); | |
3129 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3130 | break; | |
3131 | ||
3132 | case DW_CFA_advance_loc2: | |
3133 | dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3134 | fde->dw_fde_current_label, NULL); | |
3135 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3136 | break; | |
3137 | ||
3138 | case DW_CFA_advance_loc4: | |
3139 | dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3140 | fde->dw_fde_current_label, NULL); | |
3141 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3142 | break; | |
3143 | ||
3144 | case DW_CFA_MIPS_advance_loc8: | |
3145 | dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3146 | fde->dw_fde_current_label, NULL); | |
3147 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3148 | break; | |
3149 | ||
3150 | case DW_CFA_offset_extended: | |
3151 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3152 | dw2_asm_output_data_uleb128 (r, NULL); | |
3153 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3154 | dw2_asm_output_data_uleb128 (off, NULL); | |
3155 | break; | |
3156 | ||
3157 | case DW_CFA_def_cfa: | |
3158 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3159 | dw2_asm_output_data_uleb128 (r, NULL); | |
3160 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL); | |
3161 | break; | |
3162 | ||
3163 | case DW_CFA_offset_extended_sf: | |
3164 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3165 | dw2_asm_output_data_uleb128 (r, NULL); | |
3166 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3167 | dw2_asm_output_data_sleb128 (off, NULL); | |
3168 | break; | |
3169 | ||
3170 | case DW_CFA_def_cfa_sf: | |
3171 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3172 | dw2_asm_output_data_uleb128 (r, NULL); | |
3173 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3174 | dw2_asm_output_data_sleb128 (off, NULL); | |
3175 | break; | |
3176 | ||
3177 | case DW_CFA_restore_extended: | |
3178 | case DW_CFA_undefined: | |
3179 | case DW_CFA_same_value: | |
3180 | case DW_CFA_def_cfa_register: | |
3181 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3182 | dw2_asm_output_data_uleb128 (r, NULL); | |
3183 | break; | |
3184 | ||
3185 | case DW_CFA_register: | |
3186 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3187 | dw2_asm_output_data_uleb128 (r, NULL); | |
3188 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh); | |
3189 | dw2_asm_output_data_uleb128 (r, NULL); | |
3190 | break; | |
3191 | ||
3192 | case DW_CFA_def_cfa_offset: | |
3193 | case DW_CFA_GNU_args_size: | |
3194 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL); | |
3195 | break; | |
3196 | ||
3197 | case DW_CFA_def_cfa_offset_sf: | |
3198 | off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3199 | dw2_asm_output_data_sleb128 (off, NULL); | |
3200 | break; | |
3201 | ||
3202 | case DW_CFA_GNU_window_save: | |
3203 | break; | |
3204 | ||
3205 | case DW_CFA_def_cfa_expression: | |
3206 | case DW_CFA_expression: | |
3207 | output_cfa_loc (cfi, for_eh); | |
3208 | break; | |
3209 | ||
3210 | case DW_CFA_GNU_negative_offset_extended: | |
3211 | /* Obsoleted by DW_CFA_offset_extended_sf. */ | |
3212 | gcc_unreachable (); | |
3213 | ||
3214 | default: | |
3215 | break; | |
3216 | } | |
3217 | } | |
3218 | } | |
3219 | ||
3220 | /* Similar, but do it via assembler directives instead. */ | |
3221 | ||
3222 | void | |
3223 | output_cfi_directive (FILE *f, dw_cfi_ref cfi) | |
3224 | { | |
3225 | unsigned long r, r2; | |
3226 | ||
3227 | switch (cfi->dw_cfi_opc) | |
3228 | { | |
3229 | case DW_CFA_advance_loc: | |
3230 | case DW_CFA_advance_loc1: | |
3231 | case DW_CFA_advance_loc2: | |
3232 | case DW_CFA_advance_loc4: | |
3233 | case DW_CFA_MIPS_advance_loc8: | |
3234 | case DW_CFA_set_loc: | |
3235 | /* Should only be created in a code path not followed when emitting | |
3236 | via directives. The assembler is going to take care of this for | |
3237 | us. But this routines is also used for debugging dumps, so | |
3238 | print something. */ | |
3239 | gcc_assert (f != asm_out_file); | |
3240 | fprintf (f, "\t.cfi_advance_loc\n"); | |
3241 | break; | |
3242 | ||
3243 | case DW_CFA_offset: | |
3244 | case DW_CFA_offset_extended: | |
3245 | case DW_CFA_offset_extended_sf: | |
3246 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
f03df321 | 3247 | fprintf (f, "\t.cfi_offset %lu, " HOST_WIDE_INT_PRINT_DEC"\n", |
04dfc41a | 3248 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); |
3249 | break; | |
3250 | ||
3251 | case DW_CFA_restore: | |
3252 | case DW_CFA_restore_extended: | |
3253 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3254 | fprintf (f, "\t.cfi_restore %lu\n", r); | |
3255 | break; | |
3256 | ||
3257 | case DW_CFA_undefined: | |
3258 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3259 | fprintf (f, "\t.cfi_undefined %lu\n", r); | |
3260 | break; | |
3261 | ||
3262 | case DW_CFA_same_value: | |
3263 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3264 | fprintf (f, "\t.cfi_same_value %lu\n", r); | |
3265 | break; | |
3266 | ||
3267 | case DW_CFA_def_cfa: | |
3268 | case DW_CFA_def_cfa_sf: | |
3269 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
f03df321 | 3270 | fprintf (f, "\t.cfi_def_cfa %lu, " HOST_WIDE_INT_PRINT_DEC"\n", |
04dfc41a | 3271 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); |
3272 | break; | |
3273 | ||
3274 | case DW_CFA_def_cfa_register: | |
3275 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3276 | fprintf (f, "\t.cfi_def_cfa_register %lu\n", r); | |
3277 | break; | |
3278 | ||
3279 | case DW_CFA_register: | |
3280 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3281 | r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1); | |
3282 | fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2); | |
3283 | break; | |
3284 | ||
3285 | case DW_CFA_def_cfa_offset: | |
3286 | case DW_CFA_def_cfa_offset_sf: | |
3287 | fprintf (f, "\t.cfi_def_cfa_offset " | |
3288 | HOST_WIDE_INT_PRINT_DEC"\n", | |
3289 | cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3290 | break; | |
3291 | ||
3292 | case DW_CFA_remember_state: | |
3293 | fprintf (f, "\t.cfi_remember_state\n"); | |
3294 | break; | |
3295 | case DW_CFA_restore_state: | |
3296 | fprintf (f, "\t.cfi_restore_state\n"); | |
3297 | break; | |
3298 | ||
3299 | case DW_CFA_GNU_args_size: | |
3300 | if (f == asm_out_file) | |
3301 | { | |
3302 | fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size); | |
3303 | dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3304 | if (flag_debug_asm) | |
f03df321 | 3305 | fprintf (f, "\t%s args_size " HOST_WIDE_INT_PRINT_DEC, |
04dfc41a | 3306 | ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset); |
3307 | fputc ('\n', f); | |
3308 | } | |
3309 | else | |
3310 | { | |
f03df321 | 3311 | fprintf (f, "\t.cfi_GNU_args_size " HOST_WIDE_INT_PRINT_DEC "\n", |
04dfc41a | 3312 | cfi->dw_cfi_oprnd1.dw_cfi_offset); |
3313 | } | |
3314 | break; | |
3315 | ||
3316 | case DW_CFA_GNU_window_save: | |
3317 | fprintf (f, "\t.cfi_window_save\n"); | |
3318 | break; | |
3319 | ||
3320 | case DW_CFA_def_cfa_expression: | |
3321 | if (f != asm_out_file) | |
3322 | { | |
3323 | fprintf (f, "\t.cfi_def_cfa_expression ...\n"); | |
3324 | break; | |
3325 | } | |
3326 | /* FALLTHRU */ | |
3327 | case DW_CFA_expression: | |
3328 | if (f != asm_out_file) | |
3329 | { | |
3330 | fprintf (f, "\t.cfi_cfa_expression ...\n"); | |
3331 | break; | |
3332 | } | |
3333 | fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc); | |
3334 | output_cfa_loc_raw (cfi); | |
3335 | fputc ('\n', f); | |
3336 | break; | |
3337 | ||
3338 | default: | |
3339 | gcc_unreachable (); | |
3340 | } | |
3341 | } | |
3342 | ||
3343 | void | |
3344 | dwarf2out_emit_cfi (dw_cfi_ref cfi) | |
3345 | { | |
3346 | if (dwarf2out_do_cfi_asm ()) | |
3347 | output_cfi_directive (asm_out_file, cfi); | |
3348 | } | |
35bf1d17 | 3349 | |
3350 | static void | |
3351 | dump_cfi_row (FILE *f, dw_cfi_row *row) | |
3352 | { | |
3353 | dw_cfi_ref cfi; | |
3354 | unsigned i; | |
3355 | ||
3356 | cfi = row->cfa_cfi; | |
3357 | if (!cfi) | |
3358 | { | |
3359 | dw_cfa_location dummy; | |
9af5ce0c | 3360 | memset (&dummy, 0, sizeof (dummy)); |
35bf1d17 | 3361 | dummy.reg = INVALID_REGNUM; |
3362 | cfi = def_cfa_0 (&dummy, &row->cfa); | |
3363 | } | |
3364 | output_cfi_directive (f, cfi); | |
3365 | ||
f1f41a6c | 3366 | FOR_EACH_VEC_SAFE_ELT (row->reg_save, i, cfi) |
35bf1d17 | 3367 | if (cfi) |
3368 | output_cfi_directive (f, cfi); | |
35bf1d17 | 3369 | } |
3370 | ||
3371 | void debug_cfi_row (dw_cfi_row *row); | |
3372 | ||
3373 | void | |
3374 | debug_cfi_row (dw_cfi_row *row) | |
3375 | { | |
3376 | dump_cfi_row (stderr, row); | |
3377 | } | |
04dfc41a | 3378 | \f |
dcdf448e | 3379 | |
fe2dc6d6 | 3380 | /* Save the result of dwarf2out_do_frame across PCH. |
3381 | This variable is tri-state, with 0 unset, >0 true, <0 false. */ | |
3382 | static GTY(()) signed char saved_do_cfi_asm = 0; | |
dcdf448e | 3383 | |
3384 | /* Decide whether we want to emit frame unwind information for the current | |
3385 | translation unit. */ | |
3386 | ||
fe2dc6d6 | 3387 | bool |
dcdf448e | 3388 | dwarf2out_do_frame (void) |
3389 | { | |
3390 | /* We want to emit correct CFA location expressions or lists, so we | |
3391 | have to return true if we're going to output debug info, even if | |
3392 | we're not going to output frame or unwind info. */ | |
3393 | if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG) | |
3394 | return true; | |
3395 | ||
fe2dc6d6 | 3396 | if (saved_do_cfi_asm > 0) |
dcdf448e | 3397 | return true; |
3398 | ||
3399 | if (targetm.debug_unwind_info () == UI_DWARF2) | |
3400 | return true; | |
3401 | ||
3402 | if ((flag_unwind_tables || flag_exceptions) | |
3403 | && targetm_common.except_unwind_info (&global_options) == UI_DWARF2) | |
3404 | return true; | |
3405 | ||
3406 | return false; | |
3407 | } | |
3408 | ||
3409 | /* Decide whether to emit frame unwind via assembler directives. */ | |
3410 | ||
fe2dc6d6 | 3411 | bool |
dcdf448e | 3412 | dwarf2out_do_cfi_asm (void) |
3413 | { | |
3414 | int enc; | |
3415 | ||
fe2dc6d6 | 3416 | if (saved_do_cfi_asm != 0) |
3417 | return saved_do_cfi_asm > 0; | |
3418 | ||
3419 | /* Assume failure for a moment. */ | |
3420 | saved_do_cfi_asm = -1; | |
3421 | ||
dcdf448e | 3422 | if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ()) |
3423 | return false; | |
3424 | if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) | |
3425 | return false; | |
3426 | ||
3427 | /* Make sure the personality encoding is one the assembler can support. | |
3428 | In particular, aligned addresses can't be handled. */ | |
3429 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1); | |
3430 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3431 | return false; | |
3432 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0); | |
3433 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3434 | return false; | |
3435 | ||
3436 | /* If we can't get the assembler to emit only .debug_frame, and we don't need | |
3437 | dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */ | |
3438 | if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE | |
3439 | && !flag_unwind_tables && !flag_exceptions | |
3440 | && targetm_common.except_unwind_info (&global_options) != UI_DWARF2) | |
3441 | return false; | |
3442 | ||
fe2dc6d6 | 3443 | /* Success! */ |
3444 | saved_do_cfi_asm = 1; | |
dcdf448e | 3445 | return true; |
3446 | } | |
3447 | ||
cbe8bda8 | 3448 | namespace { |
3449 | ||
3450 | const pass_data pass_data_dwarf2_frame = | |
3451 | { | |
3452 | RTL_PASS, /* type */ | |
3453 | "dwarf2", /* name */ | |
3454 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 3455 | TV_FINAL, /* tv_id */ |
3456 | 0, /* properties_required */ | |
3457 | 0, /* properties_provided */ | |
3458 | 0, /* properties_destroyed */ | |
3459 | 0, /* todo_flags_start */ | |
3460 | 0, /* todo_flags_finish */ | |
fe2dc6d6 | 3461 | }; |
3462 | ||
cbe8bda8 | 3463 | class pass_dwarf2_frame : public rtl_opt_pass |
3464 | { | |
3465 | public: | |
9af5ce0c | 3466 | pass_dwarf2_frame (gcc::context *ctxt) |
3467 | : rtl_opt_pass (pass_data_dwarf2_frame, ctxt) | |
cbe8bda8 | 3468 | {} |
3469 | ||
3470 | /* opt_pass methods: */ | |
31315c24 | 3471 | virtual bool gate (function *); |
65b0537f | 3472 | virtual unsigned int execute (function *) { return execute_dwarf2_frame (); } |
cbe8bda8 | 3473 | |
3474 | }; // class pass_dwarf2_frame | |
3475 | ||
31315c24 | 3476 | bool |
3477 | pass_dwarf2_frame::gate (function *) | |
3478 | { | |
3479 | #ifndef HAVE_prologue | |
3480 | /* Targets which still implement the prologue in assembler text | |
3481 | cannot use the generic dwarf2 unwinding. */ | |
3482 | return false; | |
3483 | #endif | |
3484 | ||
3485 | /* ??? What to do for UI_TARGET unwinding? They might be able to benefit | |
3486 | from the optimized shrink-wrapping annotations that we will compute. | |
3487 | For now, only produce the CFI notes for dwarf2. */ | |
3488 | return dwarf2out_do_frame (); | |
3489 | } | |
3490 | ||
cbe8bda8 | 3491 | } // anon namespace |
3492 | ||
3493 | rtl_opt_pass * | |
3494 | make_pass_dwarf2_frame (gcc::context *ctxt) | |
3495 | { | |
3496 | return new pass_dwarf2_frame (ctxt); | |
3497 | } | |
3498 | ||
dcdf448e | 3499 | #include "gt-dwarf2cfi.h" |