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647a1567 | 1 | /* Dwarf2 Call Frame Information helper routines. |
85ec4feb | 2 | Copyright (C) 1992-2018 Free Software Foundation, Inc. |
647a1567 RH |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it under | |
7 | the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 3, or (at your option) any later | |
9 | version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "config.h" | |
21 | #include "system.h" | |
22 | #include "coretypes.h" | |
957060b5 AM |
23 | #include "target.h" |
24 | #include "function.h" | |
25 | #include "rtl.h" | |
26 | #include "tree.h" | |
27 | #include "tree-pass.h" | |
4d0cdd0c | 28 | #include "memmodel.h" |
957060b5 | 29 | #include "tm_p.h" |
957060b5 | 30 | #include "emit-rtl.h" |
40e23961 | 31 | #include "stor-layout.h" |
60393bbc | 32 | #include "cfgbuild.h" |
647a1567 RH |
33 | #include "dwarf2out.h" |
34 | #include "dwarf2asm.h" | |
647a1567 | 35 | #include "common/common-target.h" |
647a1567 RH |
36 | |
37 | #include "except.h" /* expand_builtin_dwarf_sp_column */ | |
357067f2 | 38 | #include "profile-count.h" /* For expr.h */ |
647a1567 | 39 | #include "expr.h" /* init_return_column_size */ |
647a1567 RH |
40 | #include "output.h" /* asm_out_file */ |
41 | #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */ | |
42 | ||
43 | ||
44 | /* ??? Poison these here until it can be done generically. They've been | |
45 | totally replaced in this file; make sure it stays that way. */ | |
46 | #undef DWARF2_UNWIND_INFO | |
47 | #undef DWARF2_FRAME_INFO | |
48 | #if (GCC_VERSION >= 3000) | |
49 | #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO | |
50 | #endif | |
51 | ||
52 | #ifndef INCOMING_RETURN_ADDR_RTX | |
53 | #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX) | |
54 | #endif | |
647a1567 | 55 | \f |
f17d3401 | 56 | /* A collected description of an entire row of the abstract CFI table. */ |
a79683d5 | 57 | struct GTY(()) dw_cfi_row |
f17d3401 RH |
58 | { |
59 | /* The expression that computes the CFA, expressed in two different ways. | |
60 | The CFA member for the simple cases, and the full CFI expression for | |
61 | the complex cases. The later will be a DW_CFA_cfa_expression. */ | |
62 | dw_cfa_location cfa; | |
63 | dw_cfi_ref cfa_cfi; | |
64 | ||
65 | /* The expressions for any register column that is saved. */ | |
66 | cfi_vec reg_save; | |
a79683d5 | 67 | }; |
f17d3401 | 68 | |
43215a89 | 69 | /* The caller's ORIG_REG is saved in SAVED_IN_REG. */ |
a79683d5 | 70 | struct GTY(()) reg_saved_in_data { |
43215a89 RH |
71 | rtx orig_reg; |
72 | rtx saved_in_reg; | |
a79683d5 | 73 | }; |
43215a89 | 74 | |
43215a89 RH |
75 | |
76 | /* Since we no longer have a proper CFG, we're going to create a facsimile | |
77 | of one on the fly while processing the frame-related insns. | |
78 | ||
829bdd4b RH |
79 | We create dw_trace_info structures for each extended basic block beginning |
80 | and ending at a "save point". Save points are labels, barriers, certain | |
81 | notes, and of course the beginning and end of the function. | |
43215a89 RH |
82 | |
83 | As we encounter control transfer insns, we propagate the "current" | |
829bdd4b RH |
84 | row state across the edges to the starts of traces. When checking is |
85 | enabled, we validate that we propagate the same data from all sources. | |
43215a89 RH |
86 | |
87 | All traces are members of the TRACE_INFO array, in the order in which | |
88 | they appear in the instruction stream. | |
89 | ||
829bdd4b RH |
90 | All save points are present in the TRACE_INDEX hash, mapping the insn |
91 | starting a trace to the dw_trace_info describing the trace. */ | |
43215a89 | 92 | |
a79683d5 | 93 | struct dw_trace_info |
43215a89 | 94 | { |
829bdd4b | 95 | /* The insn that begins the trace. */ |
7583d99a | 96 | rtx_insn *head; |
43215a89 RH |
97 | |
98 | /* The row state at the beginning and end of the trace. */ | |
829bdd4b RH |
99 | dw_cfi_row *beg_row, *end_row; |
100 | ||
9a08d230 RH |
101 | /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find |
102 | while scanning insns. However, the args_size value is irrelevant at | |
103 | any point except can_throw_internal_p insns. Therefore the "delay" | |
104 | sizes the values that must actually be emitted for this trace. */ | |
68184180 RS |
105 | poly_int64_pod beg_true_args_size, end_true_args_size; |
106 | poly_int64_pod beg_delay_args_size, end_delay_args_size; | |
9a08d230 RH |
107 | |
108 | /* The first EH insn in the trace, where beg_delay_args_size must be set. */ | |
dc01c3d1 | 109 | rtx_insn *eh_head; |
9a08d230 | 110 | |
43215a89 RH |
111 | /* The following variables contain data used in interpreting frame related |
112 | expressions. These are not part of the "real" row state as defined by | |
113 | Dwarf, but it seems like they need to be propagated into a trace in case | |
114 | frame related expressions have been sunk. */ | |
115 | /* ??? This seems fragile. These variables are fragments of a larger | |
116 | expression. If we do not keep the entire expression together, we risk | |
117 | not being able to put it together properly. Consider forcing targets | |
118 | to generate self-contained expressions and dropping all of the magic | |
119 | interpretation code in this file. Or at least refusing to shrink wrap | |
120 | any frame related insn that doesn't contain a complete expression. */ | |
121 | ||
122 | /* The register used for saving registers to the stack, and its offset | |
123 | from the CFA. */ | |
124 | dw_cfa_location cfa_store; | |
125 | ||
126 | /* A temporary register holding an integral value used in adjusting SP | |
127 | or setting up the store_reg. The "offset" field holds the integer | |
128 | value, not an offset. */ | |
129 | dw_cfa_location cfa_temp; | |
130 | ||
131 | /* A set of registers saved in other registers. This is the inverse of | |
132 | the row->reg_save info, if the entry is a DW_CFA_register. This is | |
133 | implemented as a flat array because it normally contains zero or 1 | |
134 | entry, depending on the target. IA-64 is the big spender here, using | |
135 | a maximum of 5 entries. */ | |
9771b263 | 136 | vec<reg_saved_in_data> regs_saved_in_regs; |
43215a89 | 137 | |
200e10dc RH |
138 | /* An identifier for this trace. Used only for debugging dumps. */ |
139 | unsigned id; | |
140 | ||
141 | /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */ | |
142 | bool switch_sections; | |
9a08d230 RH |
143 | |
144 | /* True if we've seen different values incoming to beg_true_args_size. */ | |
145 | bool args_size_undefined; | |
a79683d5 | 146 | }; |
43215a89 | 147 | |
43215a89 | 148 | |
4a8fb1a1 LC |
149 | /* Hashtable helpers. */ |
150 | ||
8d67ee55 | 151 | struct trace_info_hasher : nofree_ptr_hash <dw_trace_info> |
4a8fb1a1 | 152 | { |
67f58944 TS |
153 | static inline hashval_t hash (const dw_trace_info *); |
154 | static inline bool equal (const dw_trace_info *, const dw_trace_info *); | |
4a8fb1a1 LC |
155 | }; |
156 | ||
157 | inline hashval_t | |
67f58944 | 158 | trace_info_hasher::hash (const dw_trace_info *ti) |
4a8fb1a1 LC |
159 | { |
160 | return INSN_UID (ti->head); | |
161 | } | |
162 | ||
163 | inline bool | |
67f58944 | 164 | trace_info_hasher::equal (const dw_trace_info *a, const dw_trace_info *b) |
4a8fb1a1 LC |
165 | { |
166 | return a->head == b->head; | |
167 | } | |
168 | ||
169 | ||
43215a89 | 170 | /* The variables making up the pseudo-cfg, as described above. */ |
9771b263 | 171 | static vec<dw_trace_info> trace_info; |
b01c08c7 | 172 | static vec<dw_trace_info *> trace_work_list; |
c203e8a7 | 173 | static hash_table<trace_info_hasher> *trace_index; |
43215a89 | 174 | |
647a1567 RH |
175 | /* A vector of call frame insns for the CIE. */ |
176 | cfi_vec cie_cfi_vec; | |
177 | ||
f17d3401 RH |
178 | /* The state of the first row of the FDE table, which includes the |
179 | state provided by the CIE. */ | |
ce363ef2 | 180 | static GTY(()) dw_cfi_row *cie_cfi_row; |
f17d3401 | 181 | |
43215a89 RH |
182 | static GTY(()) reg_saved_in_data *cie_return_save; |
183 | ||
647a1567 RH |
184 | static GTY(()) unsigned long dwarf2out_cfi_label_num; |
185 | ||
bc5612ed | 186 | /* The insn after which a new CFI note should be emitted. */ |
15f63a9a | 187 | static rtx_insn *add_cfi_insn; |
bc5612ed | 188 | |
3edb53aa RH |
189 | /* When non-null, add_cfi will add the CFI to this vector. */ |
190 | static cfi_vec *add_cfi_vec; | |
191 | ||
43215a89 RH |
192 | /* The current instruction trace. */ |
193 | static dw_trace_info *cur_trace; | |
194 | ||
195 | /* The current, i.e. most recently generated, row of the CFI table. */ | |
196 | static dw_cfi_row *cur_row; | |
197 | ||
9a08d230 RH |
198 | /* A copy of the current CFA, for use during the processing of a |
199 | single insn. */ | |
200 | static dw_cfa_location *cur_cfa; | |
201 | ||
43215a89 RH |
202 | /* We delay emitting a register save until either (a) we reach the end |
203 | of the prologue or (b) the register is clobbered. This clusters | |
204 | register saves so that there are fewer pc advances. */ | |
205 | ||
a79683d5 | 206 | struct queued_reg_save { |
43215a89 RH |
207 | rtx reg; |
208 | rtx saved_reg; | |
21810de4 | 209 | poly_int64_pod cfa_offset; |
a79683d5 | 210 | }; |
43215a89 | 211 | |
43215a89 | 212 | |
9771b263 | 213 | static vec<queued_reg_save> queued_reg_saves; |
43215a89 | 214 | |
bc5612ed BS |
215 | /* True if any CFI directives were emitted at the current insn. */ |
216 | static bool any_cfis_emitted; | |
4f42d714 RH |
217 | |
218 | /* Short-hand for commonly used register numbers. */ | |
219 | static unsigned dw_stack_pointer_regnum; | |
220 | static unsigned dw_frame_pointer_regnum; | |
647a1567 RH |
221 | \f |
222 | /* Hook used by __throw. */ | |
223 | ||
224 | rtx | |
225 | expand_builtin_dwarf_sp_column (void) | |
226 | { | |
4f42d714 | 227 | unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); |
647a1567 RH |
228 | return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1)); |
229 | } | |
230 | ||
231 | /* MEM is a memory reference for the register size table, each element of | |
232 | which has mode MODE. Initialize column C as a return address column. */ | |
233 | ||
234 | static void | |
095a2d76 | 235 | init_return_column_size (scalar_int_mode mode, rtx mem, unsigned int c) |
647a1567 RH |
236 | { |
237 | HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode); | |
238 | HOST_WIDE_INT size = GET_MODE_SIZE (Pmode); | |
69db2d57 RS |
239 | emit_move_insn (adjust_address (mem, mode, offset), |
240 | gen_int_mode (size, mode)); | |
647a1567 RH |
241 | } |
242 | ||
edbbaf3b OH |
243 | /* Datastructure used by expand_builtin_init_dwarf_reg_sizes and |
244 | init_one_dwarf_reg_size to communicate on what has been done by the | |
245 | latter. */ | |
246 | ||
a79683d5 | 247 | struct init_one_dwarf_reg_state |
edbbaf3b OH |
248 | { |
249 | /* Whether the dwarf return column was initialized. */ | |
250 | bool wrote_return_column; | |
251 | ||
252 | /* For each hard register REGNO, whether init_one_dwarf_reg_size | |
253 | was given REGNO to process already. */ | |
254 | bool processed_regno [FIRST_PSEUDO_REGISTER]; | |
255 | ||
a79683d5 | 256 | }; |
edbbaf3b OH |
257 | |
258 | /* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to | |
259 | initialize the dwarf register size table entry corresponding to register | |
260 | REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to | |
261 | use for the size entry to initialize, and INIT_STATE is the communication | |
262 | datastructure conveying what we're doing to our caller. */ | |
263 | ||
264 | static | |
265 | void init_one_dwarf_reg_size (int regno, machine_mode regmode, | |
266 | rtx table, machine_mode slotmode, | |
267 | init_one_dwarf_reg_state *init_state) | |
268 | { | |
269 | const unsigned int dnum = DWARF_FRAME_REGNUM (regno); | |
270 | const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); | |
a66272f6 | 271 | const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum); |
edbbaf3b | 272 | |
cf098191 RS |
273 | poly_int64 slotoffset = dcol * GET_MODE_SIZE (slotmode); |
274 | poly_int64 regsize = GET_MODE_SIZE (regmode); | |
edbbaf3b OH |
275 | |
276 | init_state->processed_regno[regno] = true; | |
277 | ||
278 | if (rnum >= DWARF_FRAME_REGISTERS) | |
279 | return; | |
280 | ||
281 | if (dnum == DWARF_FRAME_RETURN_COLUMN) | |
282 | { | |
283 | if (regmode == VOIDmode) | |
284 | return; | |
285 | init_state->wrote_return_column = true; | |
286 | } | |
287 | ||
cf098191 RS |
288 | /* ??? When is this true? Should it be a test based on DCOL instead? */ |
289 | if (maybe_lt (slotoffset, 0)) | |
edbbaf3b OH |
290 | return; |
291 | ||
292 | emit_move_insn (adjust_address (table, slotmode, slotoffset), | |
293 | gen_int_mode (regsize, slotmode)); | |
294 | } | |
295 | ||
296 | /* Generate code to initialize the dwarf register size table located | |
297 | at the provided ADDRESS. */ | |
647a1567 RH |
298 | |
299 | void | |
300 | expand_builtin_init_dwarf_reg_sizes (tree address) | |
301 | { | |
302 | unsigned int i; | |
7a504f33 | 303 | scalar_int_mode mode = SCALAR_INT_TYPE_MODE (char_type_node); |
647a1567 RH |
304 | rtx addr = expand_normal (address); |
305 | rtx mem = gen_rtx_MEM (BLKmode, addr); | |
edbbaf3b OH |
306 | |
307 | init_one_dwarf_reg_state init_state; | |
308 | ||
309 | memset ((char *)&init_state, 0, sizeof (init_state)); | |
647a1567 RH |
310 | |
311 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
312 | { | |
edbbaf3b OH |
313 | machine_mode save_mode; |
314 | rtx span; | |
647a1567 | 315 | |
edbbaf3b OH |
316 | /* No point in processing a register multiple times. This could happen |
317 | with register spans, e.g. when a reg is first processed as a piece of | |
318 | a span, then as a register on its own later on. */ | |
319 | ||
320 | if (init_state.processed_regno[i]) | |
321 | continue; | |
322 | ||
323 | save_mode = targetm.dwarf_frame_reg_mode (i); | |
324 | span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)); | |
647a1567 | 325 | |
edbbaf3b OH |
326 | if (!span) |
327 | init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state); | |
328 | else | |
329 | { | |
330 | for (int si = 0; si < XVECLEN (span, 0); si++) | |
647a1567 | 331 | { |
edbbaf3b | 332 | rtx reg = XVECEXP (span, 0, si); |
647a1567 | 333 | |
edbbaf3b OH |
334 | init_one_dwarf_reg_size |
335 | (REGNO (reg), GET_MODE (reg), mem, mode, &init_state); | |
336 | } | |
647a1567 RH |
337 | } |
338 | } | |
339 | ||
edbbaf3b | 340 | if (!init_state.wrote_return_column) |
647a1567 RH |
341 | init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); |
342 | ||
343 | #ifdef DWARF_ALT_FRAME_RETURN_COLUMN | |
344 | init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN); | |
345 | #endif | |
346 | ||
347 | targetm.init_dwarf_reg_sizes_extra (address); | |
348 | } | |
349 | ||
829bdd4b | 350 | \f |
829bdd4b | 351 | static dw_trace_info * |
7583d99a | 352 | get_trace_info (rtx_insn *insn) |
829bdd4b RH |
353 | { |
354 | dw_trace_info dummy; | |
355 | dummy.head = insn; | |
c203e8a7 | 356 | return trace_index->find_with_hash (&dummy, INSN_UID (insn)); |
829bdd4b RH |
357 | } |
358 | ||
359 | static bool | |
7583d99a | 360 | save_point_p (rtx_insn *insn) |
829bdd4b RH |
361 | { |
362 | /* Labels, except those that are really jump tables. */ | |
363 | if (LABEL_P (insn)) | |
364 | return inside_basic_block_p (insn); | |
365 | ||
366 | /* We split traces at the prologue/epilogue notes because those | |
367 | are points at which the unwind info is usually stable. This | |
368 | makes it easier to find spots with identical unwind info so | |
369 | that we can use remember/restore_state opcodes. */ | |
370 | if (NOTE_P (insn)) | |
371 | switch (NOTE_KIND (insn)) | |
372 | { | |
373 | case NOTE_INSN_PROLOGUE_END: | |
374 | case NOTE_INSN_EPILOGUE_BEG: | |
375 | return true; | |
376 | } | |
377 | ||
378 | return false; | |
379 | } | |
380 | ||
647a1567 RH |
381 | /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */ |
382 | ||
383 | static inline HOST_WIDE_INT | |
384 | div_data_align (HOST_WIDE_INT off) | |
385 | { | |
386 | HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT; | |
387 | gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off); | |
388 | return r; | |
389 | } | |
390 | ||
391 | /* Return true if we need a signed version of a given opcode | |
392 | (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */ | |
393 | ||
394 | static inline bool | |
395 | need_data_align_sf_opcode (HOST_WIDE_INT off) | |
396 | { | |
397 | return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0; | |
398 | } | |
399 | ||
400 | /* Return a pointer to a newly allocated Call Frame Instruction. */ | |
401 | ||
402 | static inline dw_cfi_ref | |
403 | new_cfi (void) | |
404 | { | |
766090c2 | 405 | dw_cfi_ref cfi = ggc_alloc<dw_cfi_node> (); |
647a1567 RH |
406 | |
407 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0; | |
408 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0; | |
409 | ||
410 | return cfi; | |
411 | } | |
412 | ||
f17d3401 RH |
413 | /* Return a newly allocated CFI row, with no defined data. */ |
414 | ||
ce363ef2 | 415 | static dw_cfi_row * |
f17d3401 RH |
416 | new_cfi_row (void) |
417 | { | |
766090c2 | 418 | dw_cfi_row *row = ggc_cleared_alloc<dw_cfi_row> (); |
f17d3401 RH |
419 | |
420 | row->cfa.reg = INVALID_REGNUM; | |
421 | ||
422 | return row; | |
423 | } | |
424 | ||
425 | /* Return a copy of an existing CFI row. */ | |
426 | ||
ce363ef2 RH |
427 | static dw_cfi_row * |
428 | copy_cfi_row (dw_cfi_row *src) | |
f17d3401 | 429 | { |
766090c2 | 430 | dw_cfi_row *dst = ggc_alloc<dw_cfi_row> (); |
f17d3401 RH |
431 | |
432 | *dst = *src; | |
9771b263 | 433 | dst->reg_save = vec_safe_copy (src->reg_save); |
f17d3401 RH |
434 | |
435 | return dst; | |
436 | } | |
437 | ||
21810de4 RS |
438 | /* Return a copy of an existing CFA location. */ |
439 | ||
440 | static dw_cfa_location * | |
441 | copy_cfa (dw_cfa_location *src) | |
442 | { | |
443 | dw_cfa_location *dst = ggc_alloc<dw_cfa_location> (); | |
444 | *dst = *src; | |
445 | return dst; | |
446 | } | |
447 | ||
89e25f95 | 448 | /* Generate a new label for the CFI info to refer to. */ |
647a1567 RH |
449 | |
450 | static char * | |
89e25f95 | 451 | dwarf2out_cfi_label (void) |
647a1567 | 452 | { |
89e25f95 BS |
453 | int num = dwarf2out_cfi_label_num++; |
454 | char label[20]; | |
647a1567 | 455 | |
89e25f95 | 456 | ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num); |
647a1567 | 457 | |
89e25f95 | 458 | return xstrdup (label); |
647a1567 RH |
459 | } |
460 | ||
3edb53aa | 461 | /* Add CFI either to the current insn stream or to a vector, or both. */ |
647a1567 RH |
462 | |
463 | static void | |
3edb53aa | 464 | add_cfi (dw_cfi_ref cfi) |
647a1567 | 465 | { |
89e25f95 | 466 | any_cfis_emitted = true; |
141618e2 RH |
467 | |
468 | if (add_cfi_insn != NULL) | |
647a1567 | 469 | { |
141618e2 RH |
470 | add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn); |
471 | NOTE_CFI (add_cfi_insn) = cfi; | |
647a1567 | 472 | } |
141618e2 | 473 | |
3edb53aa | 474 | if (add_cfi_vec != NULL) |
9771b263 | 475 | vec_safe_push (*add_cfi_vec, cfi); |
647a1567 RH |
476 | } |
477 | ||
57e16c96 | 478 | static void |
68184180 | 479 | add_cfi_args_size (poly_int64 size) |
57e16c96 | 480 | { |
68184180 RS |
481 | /* We don't yet have a representation for polynomial sizes. */ |
482 | HOST_WIDE_INT const_size = size.to_constant (); | |
483 | ||
57e16c96 RH |
484 | dw_cfi_ref cfi = new_cfi (); |
485 | ||
9a08d230 RH |
486 | /* While we can occasionally have args_size < 0 internally, this state |
487 | should not persist at a point we actually need an opcode. */ | |
68184180 | 488 | gcc_assert (const_size >= 0); |
9a08d230 | 489 | |
57e16c96 | 490 | cfi->dw_cfi_opc = DW_CFA_GNU_args_size; |
68184180 | 491 | cfi->dw_cfi_oprnd1.dw_cfi_offset = const_size; |
57e16c96 RH |
492 | |
493 | add_cfi (cfi); | |
494 | } | |
495 | ||
496 | static void | |
497 | add_cfi_restore (unsigned reg) | |
498 | { | |
499 | dw_cfi_ref cfi = new_cfi (); | |
500 | ||
501 | cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore); | |
502 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
503 | ||
504 | add_cfi (cfi); | |
505 | } | |
506 | ||
f1a0e830 RH |
507 | /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating |
508 | that the register column is no longer saved. */ | |
509 | ||
510 | static void | |
ce363ef2 | 511 | update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi) |
f1a0e830 | 512 | { |
9771b263 DN |
513 | if (vec_safe_length (row->reg_save) <= column) |
514 | vec_safe_grow_cleared (row->reg_save, column + 1); | |
515 | (*row->reg_save)[column] = cfi; | |
f1a0e830 RH |
516 | } |
517 | ||
647a1567 RH |
518 | /* This function fills in aa dw_cfa_location structure from a dwarf location |
519 | descriptor sequence. */ | |
520 | ||
521 | static void | |
84562394 | 522 | get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_node *loc) |
647a1567 | 523 | { |
84562394 | 524 | struct dw_loc_descr_node *ptr; |
647a1567 RH |
525 | cfa->offset = 0; |
526 | cfa->base_offset = 0; | |
527 | cfa->indirect = 0; | |
528 | cfa->reg = -1; | |
529 | ||
530 | for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next) | |
531 | { | |
532 | enum dwarf_location_atom op = ptr->dw_loc_opc; | |
533 | ||
534 | switch (op) | |
535 | { | |
536 | case DW_OP_reg0: | |
537 | case DW_OP_reg1: | |
538 | case DW_OP_reg2: | |
539 | case DW_OP_reg3: | |
540 | case DW_OP_reg4: | |
541 | case DW_OP_reg5: | |
542 | case DW_OP_reg6: | |
543 | case DW_OP_reg7: | |
544 | case DW_OP_reg8: | |
545 | case DW_OP_reg9: | |
546 | case DW_OP_reg10: | |
547 | case DW_OP_reg11: | |
548 | case DW_OP_reg12: | |
549 | case DW_OP_reg13: | |
550 | case DW_OP_reg14: | |
551 | case DW_OP_reg15: | |
552 | case DW_OP_reg16: | |
553 | case DW_OP_reg17: | |
554 | case DW_OP_reg18: | |
555 | case DW_OP_reg19: | |
556 | case DW_OP_reg20: | |
557 | case DW_OP_reg21: | |
558 | case DW_OP_reg22: | |
559 | case DW_OP_reg23: | |
560 | case DW_OP_reg24: | |
561 | case DW_OP_reg25: | |
562 | case DW_OP_reg26: | |
563 | case DW_OP_reg27: | |
564 | case DW_OP_reg28: | |
565 | case DW_OP_reg29: | |
566 | case DW_OP_reg30: | |
567 | case DW_OP_reg31: | |
568 | cfa->reg = op - DW_OP_reg0; | |
569 | break; | |
570 | case DW_OP_regx: | |
571 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
572 | break; | |
573 | case DW_OP_breg0: | |
574 | case DW_OP_breg1: | |
575 | case DW_OP_breg2: | |
576 | case DW_OP_breg3: | |
577 | case DW_OP_breg4: | |
578 | case DW_OP_breg5: | |
579 | case DW_OP_breg6: | |
580 | case DW_OP_breg7: | |
581 | case DW_OP_breg8: | |
582 | case DW_OP_breg9: | |
583 | case DW_OP_breg10: | |
584 | case DW_OP_breg11: | |
585 | case DW_OP_breg12: | |
586 | case DW_OP_breg13: | |
587 | case DW_OP_breg14: | |
588 | case DW_OP_breg15: | |
589 | case DW_OP_breg16: | |
590 | case DW_OP_breg17: | |
591 | case DW_OP_breg18: | |
592 | case DW_OP_breg19: | |
593 | case DW_OP_breg20: | |
594 | case DW_OP_breg21: | |
595 | case DW_OP_breg22: | |
596 | case DW_OP_breg23: | |
597 | case DW_OP_breg24: | |
598 | case DW_OP_breg25: | |
599 | case DW_OP_breg26: | |
600 | case DW_OP_breg27: | |
601 | case DW_OP_breg28: | |
602 | case DW_OP_breg29: | |
603 | case DW_OP_breg30: | |
604 | case DW_OP_breg31: | |
605 | cfa->reg = op - DW_OP_breg0; | |
606 | cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int; | |
607 | break; | |
608 | case DW_OP_bregx: | |
609 | cfa->reg = ptr->dw_loc_oprnd1.v.val_int; | |
610 | cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int; | |
611 | break; | |
612 | case DW_OP_deref: | |
613 | cfa->indirect = 1; | |
614 | break; | |
615 | case DW_OP_plus_uconst: | |
616 | cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned; | |
617 | break; | |
618 | default: | |
619 | gcc_unreachable (); | |
620 | } | |
621 | } | |
622 | } | |
623 | ||
4a8ee122 RH |
624 | /* Find the previous value for the CFA, iteratively. CFI is the opcode |
625 | to interpret, *LOC will be updated as necessary, *REMEMBER is used for | |
626 | one level of remember/restore state processing. */ | |
647a1567 RH |
627 | |
628 | void | |
629 | lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember) | |
630 | { | |
631 | switch (cfi->dw_cfi_opc) | |
632 | { | |
633 | case DW_CFA_def_cfa_offset: | |
634 | case DW_CFA_def_cfa_offset_sf: | |
635 | loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset; | |
636 | break; | |
637 | case DW_CFA_def_cfa_register: | |
638 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
639 | break; | |
640 | case DW_CFA_def_cfa: | |
641 | case DW_CFA_def_cfa_sf: | |
642 | loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; | |
643 | loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset; | |
644 | break; | |
645 | case DW_CFA_def_cfa_expression: | |
21810de4 RS |
646 | if (cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc) |
647 | *loc = *cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc; | |
648 | else | |
649 | get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc); | |
647a1567 RH |
650 | break; |
651 | ||
652 | case DW_CFA_remember_state: | |
653 | gcc_assert (!remember->in_use); | |
654 | *remember = *loc; | |
655 | remember->in_use = 1; | |
656 | break; | |
657 | case DW_CFA_restore_state: | |
658 | gcc_assert (remember->in_use); | |
659 | *loc = *remember; | |
660 | remember->in_use = 0; | |
661 | break; | |
662 | ||
663 | default: | |
664 | break; | |
665 | } | |
666 | } | |
667 | ||
647a1567 RH |
668 | /* Determine if two dw_cfa_location structures define the same data. */ |
669 | ||
670 | bool | |
671 | cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2) | |
672 | { | |
673 | return (loc1->reg == loc2->reg | |
21810de4 | 674 | && known_eq (loc1->offset, loc2->offset) |
647a1567 RH |
675 | && loc1->indirect == loc2->indirect |
676 | && (loc1->indirect == 0 | |
21810de4 | 677 | || known_eq (loc1->base_offset, loc2->base_offset))); |
647a1567 RH |
678 | } |
679 | ||
57e16c96 | 680 | /* Determine if two CFI operands are identical. */ |
647a1567 | 681 | |
57e16c96 RH |
682 | static bool |
683 | cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b) | |
647a1567 | 684 | { |
57e16c96 RH |
685 | switch (t) |
686 | { | |
687 | case dw_cfi_oprnd_unused: | |
688 | return true; | |
689 | case dw_cfi_oprnd_reg_num: | |
690 | return a->dw_cfi_reg_num == b->dw_cfi_reg_num; | |
691 | case dw_cfi_oprnd_offset: | |
692 | return a->dw_cfi_offset == b->dw_cfi_offset; | |
693 | case dw_cfi_oprnd_addr: | |
694 | return (a->dw_cfi_addr == b->dw_cfi_addr | |
695 | || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0); | |
696 | case dw_cfi_oprnd_loc: | |
697 | return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc); | |
21810de4 RS |
698 | case dw_cfi_oprnd_cfa_loc: |
699 | return cfa_equal_p (a->dw_cfi_cfa_loc, b->dw_cfi_cfa_loc); | |
57e16c96 RH |
700 | } |
701 | gcc_unreachable (); | |
702 | } | |
647a1567 | 703 | |
57e16c96 RH |
704 | /* Determine if two CFI entries are identical. */ |
705 | ||
706 | static bool | |
707 | cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b) | |
708 | { | |
709 | enum dwarf_call_frame_info opc; | |
710 | ||
711 | /* Make things easier for our callers, including missing operands. */ | |
712 | if (a == b) | |
713 | return true; | |
714 | if (a == NULL || b == NULL) | |
715 | return false; | |
716 | ||
717 | /* Obviously, the opcodes must match. */ | |
718 | opc = a->dw_cfi_opc; | |
719 | if (opc != b->dw_cfi_opc) | |
720 | return false; | |
721 | ||
722 | /* Compare the two operands, re-using the type of the operands as | |
723 | already exposed elsewhere. */ | |
724 | return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc), | |
725 | &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1) | |
726 | && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc), | |
727 | &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2)); | |
728 | } | |
729 | ||
829bdd4b RH |
730 | /* Determine if two CFI_ROW structures are identical. */ |
731 | ||
732 | static bool | |
733 | cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b) | |
734 | { | |
735 | size_t i, n_a, n_b, n_max; | |
736 | ||
737 | if (a->cfa_cfi) | |
738 | { | |
739 | if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi)) | |
740 | return false; | |
741 | } | |
742 | else if (!cfa_equal_p (&a->cfa, &b->cfa)) | |
743 | return false; | |
744 | ||
9771b263 DN |
745 | n_a = vec_safe_length (a->reg_save); |
746 | n_b = vec_safe_length (b->reg_save); | |
829bdd4b RH |
747 | n_max = MAX (n_a, n_b); |
748 | ||
749 | for (i = 0; i < n_max; ++i) | |
750 | { | |
751 | dw_cfi_ref r_a = NULL, r_b = NULL; | |
752 | ||
753 | if (i < n_a) | |
9771b263 | 754 | r_a = (*a->reg_save)[i]; |
829bdd4b | 755 | if (i < n_b) |
9771b263 | 756 | r_b = (*b->reg_save)[i]; |
829bdd4b RH |
757 | |
758 | if (!cfi_equal_p (r_a, r_b)) | |
759 | return false; | |
760 | } | |
761 | ||
762 | return true; | |
763 | } | |
764 | ||
57e16c96 RH |
765 | /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining |
766 | what opcode to emit. Returns the CFI opcode to effect the change, or | |
767 | NULL if NEW_CFA == OLD_CFA. */ | |
768 | ||
769 | static dw_cfi_ref | |
770 | def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa) | |
771 | { | |
772 | dw_cfi_ref cfi; | |
647a1567 | 773 | |
647a1567 | 774 | /* If nothing changed, no need to issue any call frame instructions. */ |
57e16c96 RH |
775 | if (cfa_equal_p (old_cfa, new_cfa)) |
776 | return NULL; | |
647a1567 RH |
777 | |
778 | cfi = new_cfi (); | |
779 | ||
21810de4 RS |
780 | HOST_WIDE_INT const_offset; |
781 | if (new_cfa->reg == old_cfa->reg | |
782 | && !new_cfa->indirect | |
783 | && !old_cfa->indirect | |
784 | && new_cfa->offset.is_constant (&const_offset)) | |
647a1567 RH |
785 | { |
786 | /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating | |
787 | the CFA register did not change but the offset did. The data | |
788 | factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or | |
789 | in the assembler via the .cfi_def_cfa_offset directive. */ | |
21810de4 | 790 | if (const_offset < 0) |
647a1567 RH |
791 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf; |
792 | else | |
793 | cfi->dw_cfi_opc = DW_CFA_def_cfa_offset; | |
21810de4 | 794 | cfi->dw_cfi_oprnd1.dw_cfi_offset = const_offset; |
647a1567 | 795 | } |
21810de4 RS |
796 | else if (new_cfa->offset.is_constant () |
797 | && known_eq (new_cfa->offset, old_cfa->offset) | |
57e16c96 RH |
798 | && old_cfa->reg != INVALID_REGNUM |
799 | && !new_cfa->indirect | |
800 | && !old_cfa->indirect) | |
647a1567 RH |
801 | { |
802 | /* Construct a "DW_CFA_def_cfa_register <register>" instruction, | |
803 | indicating the CFA register has changed to <register> but the | |
21810de4 RS |
804 | offset has not changed. This requires the old CFA to have |
805 | been set as a register plus offset rather than a general | |
806 | DW_CFA_def_cfa_expression. */ | |
647a1567 | 807 | cfi->dw_cfi_opc = DW_CFA_def_cfa_register; |
57e16c96 | 808 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
647a1567 | 809 | } |
21810de4 RS |
810 | else if (new_cfa->indirect == 0 |
811 | && new_cfa->offset.is_constant (&const_offset)) | |
647a1567 RH |
812 | { |
813 | /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction, | |
814 | indicating the CFA register has changed to <register> with | |
815 | the specified offset. The data factoring for DW_CFA_def_cfa_sf | |
816 | happens in output_cfi, or in the assembler via the .cfi_def_cfa | |
817 | directive. */ | |
21810de4 | 818 | if (const_offset < 0) |
647a1567 RH |
819 | cfi->dw_cfi_opc = DW_CFA_def_cfa_sf; |
820 | else | |
821 | cfi->dw_cfi_opc = DW_CFA_def_cfa; | |
57e16c96 | 822 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; |
21810de4 | 823 | cfi->dw_cfi_oprnd2.dw_cfi_offset = const_offset; |
647a1567 RH |
824 | } |
825 | else | |
826 | { | |
827 | /* Construct a DW_CFA_def_cfa_expression instruction to | |
828 | calculate the CFA using a full location expression since no | |
829 | register-offset pair is available. */ | |
84562394 | 830 | struct dw_loc_descr_node *loc_list; |
647a1567 RH |
831 | |
832 | cfi->dw_cfi_opc = DW_CFA_def_cfa_expression; | |
57e16c96 | 833 | loc_list = build_cfa_loc (new_cfa, 0); |
647a1567 | 834 | cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list; |
21810de4 RS |
835 | if (!new_cfa->offset.is_constant () |
836 | || !new_cfa->base_offset.is_constant ()) | |
837 | /* It's hard to reconstruct the CFA location for a polynomial | |
838 | expression, so just cache it instead. */ | |
839 | cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc = copy_cfa (new_cfa); | |
840 | else | |
841 | cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc = NULL; | |
647a1567 RH |
842 | } |
843 | ||
57e16c96 RH |
844 | return cfi; |
845 | } | |
846 | ||
847 | /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */ | |
848 | ||
849 | static void | |
850 | def_cfa_1 (dw_cfa_location *new_cfa) | |
851 | { | |
852 | dw_cfi_ref cfi; | |
853 | ||
43215a89 RH |
854 | if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0) |
855 | cur_trace->cfa_store.offset = new_cfa->offset; | |
57e16c96 RH |
856 | |
857 | cfi = def_cfa_0 (&cur_row->cfa, new_cfa); | |
858 | if (cfi) | |
859 | { | |
860 | cur_row->cfa = *new_cfa; | |
8f1594b2 RH |
861 | cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression |
862 | ? cfi : NULL); | |
57e16c96 RH |
863 | |
864 | add_cfi (cfi); | |
865 | } | |
647a1567 RH |
866 | } |
867 | ||
868 | /* Add the CFI for saving a register. REG is the CFA column number. | |
647a1567 RH |
869 | If SREG is -1, the register is saved at OFFSET from the CFA; |
870 | otherwise it is saved in SREG. */ | |
871 | ||
872 | static void | |
21810de4 | 873 | reg_save (unsigned int reg, unsigned int sreg, poly_int64 offset) |
647a1567 | 874 | { |
3edb53aa | 875 | dw_fde_ref fde = cfun ? cfun->fde : NULL; |
647a1567 | 876 | dw_cfi_ref cfi = new_cfi (); |
647a1567 RH |
877 | |
878 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
879 | ||
21810de4 | 880 | if (sreg == INVALID_REGNUM) |
647a1567 | 881 | { |
21810de4 RS |
882 | HOST_WIDE_INT const_offset; |
883 | /* When stack is aligned, store REG using DW_CFA_expression with FP. */ | |
884 | if (fde && fde->stack_realign) | |
885 | { | |
886 | cfi->dw_cfi_opc = DW_CFA_expression; | |
887 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
888 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
889 | = build_cfa_aligned_loc (&cur_row->cfa, offset, | |
890 | fde->stack_realignment); | |
891 | } | |
892 | else if (offset.is_constant (&const_offset)) | |
893 | { | |
894 | if (need_data_align_sf_opcode (const_offset)) | |
895 | cfi->dw_cfi_opc = DW_CFA_offset_extended_sf; | |
896 | else if (reg & ~0x3f) | |
897 | cfi->dw_cfi_opc = DW_CFA_offset_extended; | |
898 | else | |
899 | cfi->dw_cfi_opc = DW_CFA_offset; | |
900 | cfi->dw_cfi_oprnd2.dw_cfi_offset = const_offset; | |
901 | } | |
647a1567 | 902 | else |
21810de4 RS |
903 | { |
904 | cfi->dw_cfi_opc = DW_CFA_expression; | |
905 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; | |
906 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
907 | = build_cfa_loc (&cur_row->cfa, offset); | |
908 | } | |
647a1567 RH |
909 | } |
910 | else if (sreg == reg) | |
f1a0e830 RH |
911 | { |
912 | /* While we could emit something like DW_CFA_same_value or | |
913 | DW_CFA_restore, we never expect to see something like that | |
914 | in a prologue. This is more likely to be a bug. A backend | |
915 | can always bypass this by using REG_CFA_RESTORE directly. */ | |
916 | gcc_unreachable (); | |
917 | } | |
647a1567 RH |
918 | else |
919 | { | |
920 | cfi->dw_cfi_opc = DW_CFA_register; | |
921 | cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg; | |
922 | } | |
923 | ||
3edb53aa | 924 | add_cfi (cfi); |
f1a0e830 | 925 | update_row_reg_save (cur_row, reg, cfi); |
647a1567 RH |
926 | } |
927 | ||
9a08d230 RH |
928 | /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note |
929 | and adjust data structures to match. */ | |
647a1567 RH |
930 | |
931 | static void | |
23f57f5a | 932 | notice_args_size (rtx_insn *insn) |
647a1567 | 933 | { |
68184180 | 934 | poly_int64 args_size, delta; |
9a08d230 | 935 | rtx note; |
647a1567 | 936 | |
9a08d230 RH |
937 | note = find_reg_note (insn, REG_ARGS_SIZE, NULL); |
938 | if (note == NULL) | |
939 | return; | |
f17d3401 | 940 | |
68184180 | 941 | args_size = get_args_size (note); |
9a08d230 | 942 | delta = args_size - cur_trace->end_true_args_size; |
68184180 | 943 | if (known_eq (delta, 0)) |
9a08d230 | 944 | return; |
647a1567 | 945 | |
9a08d230 | 946 | cur_trace->end_true_args_size = args_size; |
43215a89 | 947 | |
9a08d230 RH |
948 | /* If the CFA is computed off the stack pointer, then we must adjust |
949 | the computation of the CFA as well. */ | |
950 | if (cur_cfa->reg == dw_stack_pointer_regnum) | |
951 | { | |
952 | gcc_assert (!cur_cfa->indirect); | |
647a1567 | 953 | |
9a08d230 RH |
954 | /* Convert a change in args_size (always a positive in the |
955 | direction of stack growth) to a change in stack pointer. */ | |
581edfa3 TS |
956 | if (!STACK_GROWS_DOWNWARD) |
957 | delta = -delta; | |
958 | ||
9a08d230 RH |
959 | cur_cfa->offset += delta; |
960 | } | |
647a1567 RH |
961 | } |
962 | ||
9a08d230 RH |
963 | /* A subroutine of scan_trace. INSN is can_throw_internal. Update the |
964 | data within the trace related to EH insns and args_size. */ | |
647a1567 RH |
965 | |
966 | static void | |
dc01c3d1 | 967 | notice_eh_throw (rtx_insn *insn) |
647a1567 | 968 | { |
68184180 | 969 | poly_int64 args_size = cur_trace->end_true_args_size; |
9a08d230 | 970 | if (cur_trace->eh_head == NULL) |
647a1567 | 971 | { |
9a08d230 RH |
972 | cur_trace->eh_head = insn; |
973 | cur_trace->beg_delay_args_size = args_size; | |
974 | cur_trace->end_delay_args_size = args_size; | |
647a1567 | 975 | } |
68184180 | 976 | else if (maybe_ne (cur_trace->end_delay_args_size, args_size)) |
647a1567 | 977 | { |
9a08d230 | 978 | cur_trace->end_delay_args_size = args_size; |
647a1567 | 979 | |
9a08d230 RH |
980 | /* ??? If the CFA is the stack pointer, search backward for the last |
981 | CFI note and insert there. Given that the stack changed for the | |
982 | args_size change, there *must* be such a note in between here and | |
983 | the last eh insn. */ | |
984 | add_cfi_args_size (args_size); | |
985 | } | |
647a1567 RH |
986 | } |
987 | ||
7263c6d7 | 988 | /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */ |
4f42d714 RH |
989 | /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is |
990 | used in places where rtl is prohibited. */ | |
7263c6d7 RH |
991 | |
992 | static inline unsigned | |
993 | dwf_regno (const_rtx reg) | |
994 | { | |
362805fc | 995 | gcc_assert (REGNO (reg) < FIRST_PSEUDO_REGISTER); |
4f42d714 | 996 | return DWARF_FRAME_REGNUM (REGNO (reg)); |
7263c6d7 RH |
997 | } |
998 | ||
647a1567 RH |
999 | /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */ |
1000 | ||
1001 | static bool | |
1002 | compare_reg_or_pc (rtx x, rtx y) | |
1003 | { | |
1004 | if (REG_P (x) && REG_P (y)) | |
1005 | return REGNO (x) == REGNO (y); | |
1006 | return x == y; | |
1007 | } | |
1008 | ||
1009 | /* Record SRC as being saved in DEST. DEST may be null to delete an | |
1010 | existing entry. SRC may be a register or PC_RTX. */ | |
1011 | ||
1012 | static void | |
1013 | record_reg_saved_in_reg (rtx dest, rtx src) | |
1014 | { | |
1015 | reg_saved_in_data *elt; | |
1016 | size_t i; | |
1017 | ||
9771b263 | 1018 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt) |
647a1567 RH |
1019 | if (compare_reg_or_pc (elt->orig_reg, src)) |
1020 | { | |
1021 | if (dest == NULL) | |
9771b263 | 1022 | cur_trace->regs_saved_in_regs.unordered_remove (i); |
647a1567 RH |
1023 | else |
1024 | elt->saved_in_reg = dest; | |
1025 | return; | |
1026 | } | |
1027 | ||
1028 | if (dest == NULL) | |
1029 | return; | |
1030 | ||
f32682ca | 1031 | reg_saved_in_data e = {src, dest}; |
9771b263 | 1032 | cur_trace->regs_saved_in_regs.safe_push (e); |
647a1567 RH |
1033 | } |
1034 | ||
647a1567 RH |
1035 | /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at |
1036 | SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */ | |
1037 | ||
1038 | static void | |
21810de4 | 1039 | queue_reg_save (rtx reg, rtx sreg, poly_int64 offset) |
647a1567 | 1040 | { |
999646c1 | 1041 | queued_reg_save *q; |
f32682ca | 1042 | queued_reg_save e = {reg, sreg, offset}; |
999646c1 | 1043 | size_t i; |
647a1567 RH |
1044 | |
1045 | /* Duplicates waste space, but it's also necessary to remove them | |
a8e5c0e7 | 1046 | for correctness, since the queue gets output in reverse order. */ |
9771b263 | 1047 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
a8e5c0e7 | 1048 | if (compare_reg_or_pc (q->reg, reg)) |
f32682ca DN |
1049 | { |
1050 | *q = e; | |
1051 | return; | |
1052 | } | |
647a1567 | 1053 | |
9771b263 | 1054 | queued_reg_saves.safe_push (e); |
647a1567 RH |
1055 | } |
1056 | ||
1057 | /* Output all the entries in QUEUED_REG_SAVES. */ | |
1058 | ||
1059 | static void | |
1060 | dwarf2out_flush_queued_reg_saves (void) | |
1061 | { | |
999646c1 RH |
1062 | queued_reg_save *q; |
1063 | size_t i; | |
647a1567 | 1064 | |
9771b263 | 1065 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
647a1567 RH |
1066 | { |
1067 | unsigned int reg, sreg; | |
1068 | ||
1069 | record_reg_saved_in_reg (q->saved_reg, q->reg); | |
1070 | ||
a8e5c0e7 RH |
1071 | if (q->reg == pc_rtx) |
1072 | reg = DWARF_FRAME_RETURN_COLUMN; | |
1073 | else | |
7263c6d7 | 1074 | reg = dwf_regno (q->reg); |
647a1567 | 1075 | if (q->saved_reg) |
7263c6d7 | 1076 | sreg = dwf_regno (q->saved_reg); |
647a1567 RH |
1077 | else |
1078 | sreg = INVALID_REGNUM; | |
3edb53aa | 1079 | reg_save (reg, sreg, q->cfa_offset); |
647a1567 RH |
1080 | } |
1081 | ||
9771b263 | 1082 | queued_reg_saves.truncate (0); |
647a1567 RH |
1083 | } |
1084 | ||
1085 | /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved | |
1086 | location for? Or, does it clobber a register which we've previously | |
1087 | said that some other register is saved in, and for which we now | |
1088 | have a new location for? */ | |
1089 | ||
1090 | static bool | |
1091 | clobbers_queued_reg_save (const_rtx insn) | |
1092 | { | |
999646c1 RH |
1093 | queued_reg_save *q; |
1094 | size_t iq; | |
647a1567 | 1095 | |
9771b263 | 1096 | FOR_EACH_VEC_ELT (queued_reg_saves, iq, q) |
647a1567 | 1097 | { |
999646c1 | 1098 | size_t ir; |
647a1567 RH |
1099 | reg_saved_in_data *rir; |
1100 | ||
1101 | if (modified_in_p (q->reg, insn)) | |
1102 | return true; | |
1103 | ||
9771b263 | 1104 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, ir, rir) |
647a1567 RH |
1105 | if (compare_reg_or_pc (q->reg, rir->orig_reg) |
1106 | && modified_in_p (rir->saved_in_reg, insn)) | |
1107 | return true; | |
1108 | } | |
1109 | ||
1110 | return false; | |
1111 | } | |
1112 | ||
1113 | /* What register, if any, is currently saved in REG? */ | |
1114 | ||
1115 | static rtx | |
1116 | reg_saved_in (rtx reg) | |
1117 | { | |
1118 | unsigned int regn = REGNO (reg); | |
999646c1 | 1119 | queued_reg_save *q; |
647a1567 RH |
1120 | reg_saved_in_data *rir; |
1121 | size_t i; | |
1122 | ||
9771b263 | 1123 | FOR_EACH_VEC_ELT (queued_reg_saves, i, q) |
647a1567 RH |
1124 | if (q->saved_reg && regn == REGNO (q->saved_reg)) |
1125 | return q->reg; | |
1126 | ||
9771b263 | 1127 | FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, rir) |
647a1567 RH |
1128 | if (regn == REGNO (rir->saved_in_reg)) |
1129 | return rir->orig_reg; | |
1130 | ||
1131 | return NULL_RTX; | |
1132 | } | |
1133 | ||
647a1567 RH |
1134 | /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */ |
1135 | ||
1136 | static void | |
89e25f95 | 1137 | dwarf2out_frame_debug_def_cfa (rtx pat) |
647a1567 | 1138 | { |
9a08d230 | 1139 | memset (cur_cfa, 0, sizeof (*cur_cfa)); |
647a1567 | 1140 | |
21810de4 | 1141 | pat = strip_offset (pat, &cur_cfa->offset); |
8f1594b2 RH |
1142 | if (MEM_P (pat)) |
1143 | { | |
9a08d230 | 1144 | cur_cfa->indirect = 1; |
21810de4 | 1145 | pat = strip_offset (XEXP (pat, 0), &cur_cfa->base_offset); |
647a1567 | 1146 | } |
8f1594b2 RH |
1147 | /* ??? If this fails, we could be calling into the _loc functions to |
1148 | define a full expression. So far no port does that. */ | |
1149 | gcc_assert (REG_P (pat)); | |
9a08d230 | 1150 | cur_cfa->reg = dwf_regno (pat); |
647a1567 RH |
1151 | } |
1152 | ||
1153 | /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */ | |
1154 | ||
1155 | static void | |
89e25f95 | 1156 | dwarf2out_frame_debug_adjust_cfa (rtx pat) |
647a1567 RH |
1157 | { |
1158 | rtx src, dest; | |
1159 | ||
1160 | gcc_assert (GET_CODE (pat) == SET); | |
1161 | dest = XEXP (pat, 0); | |
1162 | src = XEXP (pat, 1); | |
1163 | ||
1164 | switch (GET_CODE (src)) | |
1165 | { | |
1166 | case PLUS: | |
9a08d230 | 1167 | gcc_assert (dwf_regno (XEXP (src, 0)) == cur_cfa->reg); |
21810de4 | 1168 | cur_cfa->offset -= rtx_to_poly_int64 (XEXP (src, 1)); |
647a1567 RH |
1169 | break; |
1170 | ||
1171 | case REG: | |
9a08d230 | 1172 | break; |
647a1567 RH |
1173 | |
1174 | default: | |
9a08d230 | 1175 | gcc_unreachable (); |
647a1567 RH |
1176 | } |
1177 | ||
9a08d230 RH |
1178 | cur_cfa->reg = dwf_regno (dest); |
1179 | gcc_assert (cur_cfa->indirect == 0); | |
647a1567 RH |
1180 | } |
1181 | ||
1182 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */ | |
1183 | ||
1184 | static void | |
89e25f95 | 1185 | dwarf2out_frame_debug_cfa_offset (rtx set) |
647a1567 | 1186 | { |
21810de4 | 1187 | poly_int64 offset; |
647a1567 RH |
1188 | rtx src, addr, span; |
1189 | unsigned int sregno; | |
1190 | ||
1191 | src = XEXP (set, 1); | |
1192 | addr = XEXP (set, 0); | |
1193 | gcc_assert (MEM_P (addr)); | |
1194 | addr = XEXP (addr, 0); | |
1195 | ||
1196 | /* As documented, only consider extremely simple addresses. */ | |
1197 | switch (GET_CODE (addr)) | |
1198 | { | |
1199 | case REG: | |
9a08d230 RH |
1200 | gcc_assert (dwf_regno (addr) == cur_cfa->reg); |
1201 | offset = -cur_cfa->offset; | |
647a1567 RH |
1202 | break; |
1203 | case PLUS: | |
9a08d230 | 1204 | gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_cfa->reg); |
21810de4 | 1205 | offset = rtx_to_poly_int64 (XEXP (addr, 1)) - cur_cfa->offset; |
647a1567 RH |
1206 | break; |
1207 | default: | |
1208 | gcc_unreachable (); | |
1209 | } | |
1210 | ||
1211 | if (src == pc_rtx) | |
1212 | { | |
1213 | span = NULL; | |
1214 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1215 | } | |
43215a89 | 1216 | else |
647a1567 RH |
1217 | { |
1218 | span = targetm.dwarf_register_span (src); | |
7263c6d7 | 1219 | sregno = dwf_regno (src); |
647a1567 RH |
1220 | } |
1221 | ||
1222 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1223 | a different flushing heuristic for epilogues. */ | |
1224 | if (!span) | |
3edb53aa | 1225 | reg_save (sregno, INVALID_REGNUM, offset); |
647a1567 RH |
1226 | else |
1227 | { | |
1228 | /* We have a PARALLEL describing where the contents of SRC live. | |
a4d47cac | 1229 | Adjust the offset for each piece of the PARALLEL. */ |
21810de4 | 1230 | poly_int64 span_offset = offset; |
647a1567 RH |
1231 | |
1232 | gcc_assert (GET_CODE (span) == PARALLEL); | |
1233 | ||
a4d47cac EB |
1234 | const int par_len = XVECLEN (span, 0); |
1235 | for (int par_index = 0; par_index < par_len; par_index++) | |
647a1567 RH |
1236 | { |
1237 | rtx elem = XVECEXP (span, 0, par_index); | |
7263c6d7 | 1238 | sregno = dwf_regno (src); |
3edb53aa | 1239 | reg_save (sregno, INVALID_REGNUM, span_offset); |
647a1567 RH |
1240 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); |
1241 | } | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */ | |
1246 | ||
1247 | static void | |
89e25f95 | 1248 | dwarf2out_frame_debug_cfa_register (rtx set) |
647a1567 RH |
1249 | { |
1250 | rtx src, dest; | |
1251 | unsigned sregno, dregno; | |
1252 | ||
1253 | src = XEXP (set, 1); | |
1254 | dest = XEXP (set, 0); | |
1255 | ||
a8e5c0e7 | 1256 | record_reg_saved_in_reg (dest, src); |
647a1567 RH |
1257 | if (src == pc_rtx) |
1258 | sregno = DWARF_FRAME_RETURN_COLUMN; | |
1259 | else | |
7263c6d7 | 1260 | sregno = dwf_regno (src); |
647a1567 | 1261 | |
7263c6d7 | 1262 | dregno = dwf_regno (dest); |
647a1567 RH |
1263 | |
1264 | /* ??? We'd like to use queue_reg_save, but we need to come up with | |
1265 | a different flushing heuristic for epilogues. */ | |
3edb53aa | 1266 | reg_save (sregno, dregno, 0); |
647a1567 RH |
1267 | } |
1268 | ||
ac5b3eff | 1269 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ |
647a1567 RH |
1270 | |
1271 | static void | |
89e25f95 | 1272 | dwarf2out_frame_debug_cfa_expression (rtx set) |
647a1567 RH |
1273 | { |
1274 | rtx src, dest, span; | |
1275 | dw_cfi_ref cfi = new_cfi (); | |
f1a0e830 | 1276 | unsigned regno; |
647a1567 RH |
1277 | |
1278 | dest = SET_DEST (set); | |
1279 | src = SET_SRC (set); | |
1280 | ||
1281 | gcc_assert (REG_P (src)); | |
1282 | gcc_assert (MEM_P (dest)); | |
1283 | ||
1284 | span = targetm.dwarf_register_span (src); | |
1285 | gcc_assert (!span); | |
1286 | ||
f1a0e830 RH |
1287 | regno = dwf_regno (src); |
1288 | ||
647a1567 | 1289 | cfi->dw_cfi_opc = DW_CFA_expression; |
f1a0e830 | 1290 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno; |
647a1567 RH |
1291 | cfi->dw_cfi_oprnd2.dw_cfi_loc |
1292 | = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest), | |
1293 | GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); | |
1294 | ||
1295 | /* ??? We'd like to use queue_reg_save, were the interface different, | |
1296 | and, as above, we could manage flushing for epilogues. */ | |
3edb53aa | 1297 | add_cfi (cfi); |
f1a0e830 | 1298 | update_row_reg_save (cur_row, regno, cfi); |
647a1567 RH |
1299 | } |
1300 | ||
ac5b3eff JW |
1301 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_VAL_EXPRESSION |
1302 | note. */ | |
1303 | ||
1304 | static void | |
1305 | dwarf2out_frame_debug_cfa_val_expression (rtx set) | |
1306 | { | |
1307 | rtx dest = SET_DEST (set); | |
1308 | gcc_assert (REG_P (dest)); | |
1309 | ||
1310 | rtx span = targetm.dwarf_register_span (dest); | |
1311 | gcc_assert (!span); | |
1312 | ||
1313 | rtx src = SET_SRC (set); | |
1314 | dw_cfi_ref cfi = new_cfi (); | |
1315 | cfi->dw_cfi_opc = DW_CFA_val_expression; | |
1316 | cfi->dw_cfi_oprnd1.dw_cfi_reg_num = dwf_regno (dest); | |
1317 | cfi->dw_cfi_oprnd2.dw_cfi_loc | |
1318 | = mem_loc_descriptor (src, GET_MODE (src), | |
1319 | GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); | |
1320 | add_cfi (cfi); | |
1321 | update_row_reg_save (cur_row, dwf_regno (dest), cfi); | |
1322 | } | |
1323 | ||
647a1567 RH |
1324 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */ |
1325 | ||
1326 | static void | |
89e25f95 | 1327 | dwarf2out_frame_debug_cfa_restore (rtx reg) |
647a1567 | 1328 | { |
a4d47cac EB |
1329 | gcc_assert (REG_P (reg)); |
1330 | ||
1331 | rtx span = targetm.dwarf_register_span (reg); | |
1332 | if (!span) | |
1333 | { | |
1334 | unsigned int regno = dwf_regno (reg); | |
1335 | add_cfi_restore (regno); | |
1336 | update_row_reg_save (cur_row, regno, NULL); | |
1337 | } | |
1338 | else | |
1339 | { | |
1340 | /* We have a PARALLEL describing where the contents of REG live. | |
1341 | Restore the register for each piece of the PARALLEL. */ | |
1342 | gcc_assert (GET_CODE (span) == PARALLEL); | |
647a1567 | 1343 | |
a4d47cac EB |
1344 | const int par_len = XVECLEN (span, 0); |
1345 | for (int par_index = 0; par_index < par_len; par_index++) | |
1346 | { | |
1347 | reg = XVECEXP (span, 0, par_index); | |
1348 | gcc_assert (REG_P (reg)); | |
1349 | unsigned int regno = dwf_regno (reg); | |
1350 | add_cfi_restore (regno); | |
1351 | update_row_reg_save (cur_row, regno, NULL); | |
1352 | } | |
1353 | } | |
647a1567 RH |
1354 | } |
1355 | ||
1356 | /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE. | |
1357 | ??? Perhaps we should note in the CIE where windows are saved (instead of | |
1358 | assuming 0(cfa)) and what registers are in the window. */ | |
1359 | ||
1360 | static void | |
89e25f95 | 1361 | dwarf2out_frame_debug_cfa_window_save (void) |
647a1567 RH |
1362 | { |
1363 | dw_cfi_ref cfi = new_cfi (); | |
1364 | ||
1365 | cfi->dw_cfi_opc = DW_CFA_GNU_window_save; | |
3edb53aa | 1366 | add_cfi (cfi); |
647a1567 RH |
1367 | } |
1368 | ||
1369 | /* Record call frame debugging information for an expression EXPR, | |
1370 | which either sets SP or FP (adjusting how we calculate the frame | |
1371 | address) or saves a register to the stack or another register. | |
1372 | LABEL indicates the address of EXPR. | |
1373 | ||
1374 | This function encodes a state machine mapping rtxes to actions on | |
1375 | cfa, cfa_store, and cfa_temp.reg. We describe these rules so | |
1376 | users need not read the source code. | |
1377 | ||
1378 | The High-Level Picture | |
1379 | ||
1380 | Changes in the register we use to calculate the CFA: Currently we | |
1381 | assume that if you copy the CFA register into another register, we | |
1382 | should take the other one as the new CFA register; this seems to | |
1383 | work pretty well. If it's wrong for some target, it's simple | |
1384 | enough not to set RTX_FRAME_RELATED_P on the insn in question. | |
1385 | ||
1386 | Changes in the register we use for saving registers to the stack: | |
1387 | This is usually SP, but not always. Again, we deduce that if you | |
1388 | copy SP into another register (and SP is not the CFA register), | |
1389 | then the new register is the one we will be using for register | |
1390 | saves. This also seems to work. | |
1391 | ||
1392 | Register saves: There's not much guesswork about this one; if | |
1393 | RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a | |
1394 | register save, and the register used to calculate the destination | |
1395 | had better be the one we think we're using for this purpose. | |
1396 | It's also assumed that a copy from a call-saved register to another | |
1397 | register is saving that register if RTX_FRAME_RELATED_P is set on | |
1398 | that instruction. If the copy is from a call-saved register to | |
1399 | the *same* register, that means that the register is now the same | |
1400 | value as in the caller. | |
1401 | ||
1402 | Except: If the register being saved is the CFA register, and the | |
1403 | offset is nonzero, we are saving the CFA, so we assume we have to | |
1404 | use DW_CFA_def_cfa_expression. If the offset is 0, we assume that | |
1405 | the intent is to save the value of SP from the previous frame. | |
1406 | ||
1407 | In addition, if a register has previously been saved to a different | |
1408 | register, | |
1409 | ||
1410 | Invariants / Summaries of Rules | |
1411 | ||
1412 | cfa current rule for calculating the CFA. It usually | |
f17d3401 | 1413 | consists of a register and an offset. This is |
9a08d230 | 1414 | actually stored in *cur_cfa, but abbreviated |
f17d3401 | 1415 | for the purposes of this documentation. |
647a1567 RH |
1416 | cfa_store register used by prologue code to save things to the stack |
1417 | cfa_store.offset is the offset from the value of | |
1418 | cfa_store.reg to the actual CFA | |
1419 | cfa_temp register holding an integral value. cfa_temp.offset | |
1420 | stores the value, which will be used to adjust the | |
1421 | stack pointer. cfa_temp is also used like cfa_store, | |
1422 | to track stores to the stack via fp or a temp reg. | |
1423 | ||
1424 | Rules 1- 4: Setting a register's value to cfa.reg or an expression | |
1425 | with cfa.reg as the first operand changes the cfa.reg and its | |
1426 | cfa.offset. Rule 1 and 4 also set cfa_temp.reg and | |
1427 | cfa_temp.offset. | |
1428 | ||
1429 | Rules 6- 9: Set a non-cfa.reg register value to a constant or an | |
1430 | expression yielding a constant. This sets cfa_temp.reg | |
1431 | and cfa_temp.offset. | |
1432 | ||
1433 | Rule 5: Create a new register cfa_store used to save items to the | |
1434 | stack. | |
1435 | ||
1436 | Rules 10-14: Save a register to the stack. Define offset as the | |
1437 | difference of the original location and cfa_store's | |
1438 | location (or cfa_temp's location if cfa_temp is used). | |
1439 | ||
1440 | Rules 16-20: If AND operation happens on sp in prologue, we assume | |
1441 | stack is realigned. We will use a group of DW_OP_XXX | |
1442 | expressions to represent the location of the stored | |
1443 | register instead of CFA+offset. | |
1444 | ||
1445 | The Rules | |
1446 | ||
1447 | "{a,b}" indicates a choice of a xor b. | |
1448 | "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg. | |
1449 | ||
1450 | Rule 1: | |
1451 | (set <reg1> <reg2>:cfa.reg) | |
1452 | effects: cfa.reg = <reg1> | |
1453 | cfa.offset unchanged | |
1454 | cfa_temp.reg = <reg1> | |
1455 | cfa_temp.offset = cfa.offset | |
1456 | ||
1457 | Rule 2: | |
1458 | (set sp ({minus,plus,losum} {sp,fp}:cfa.reg | |
1459 | {<const_int>,<reg>:cfa_temp.reg})) | |
1460 | effects: cfa.reg = sp if fp used | |
1461 | cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp | |
1462 | cfa_store.offset += {+/- <const_int>, cfa_temp.offset} | |
1463 | if cfa_store.reg==sp | |
1464 | ||
1465 | Rule 3: | |
1466 | (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>)) | |
1467 | effects: cfa.reg = fp | |
1468 | cfa_offset += +/- <const_int> | |
1469 | ||
1470 | Rule 4: | |
1471 | (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>)) | |
1472 | constraints: <reg1> != fp | |
1473 | <reg1> != sp | |
1474 | effects: cfa.reg = <reg1> | |
1475 | cfa_temp.reg = <reg1> | |
1476 | cfa_temp.offset = cfa.offset | |
1477 | ||
1478 | Rule 5: | |
1479 | (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg)) | |
1480 | constraints: <reg1> != fp | |
1481 | <reg1> != sp | |
1482 | effects: cfa_store.reg = <reg1> | |
1483 | cfa_store.offset = cfa.offset - cfa_temp.offset | |
1484 | ||
1485 | Rule 6: | |
1486 | (set <reg> <const_int>) | |
1487 | effects: cfa_temp.reg = <reg> | |
1488 | cfa_temp.offset = <const_int> | |
1489 | ||
1490 | Rule 7: | |
1491 | (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>)) | |
1492 | effects: cfa_temp.reg = <reg1> | |
1493 | cfa_temp.offset |= <const_int> | |
1494 | ||
1495 | Rule 8: | |
1496 | (set <reg> (high <exp>)) | |
1497 | effects: none | |
1498 | ||
1499 | Rule 9: | |
1500 | (set <reg> (lo_sum <exp> <const_int>)) | |
1501 | effects: cfa_temp.reg = <reg> | |
1502 | cfa_temp.offset = <const_int> | |
1503 | ||
1504 | Rule 10: | |
1505 | (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>) | |
1506 | effects: cfa_store.offset -= <const_int> | |
1507 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1508 | cfa.reg = sp | |
1509 | cfa.base_offset = -cfa_store.offset | |
1510 | ||
1511 | Rule 11: | |
1512 | (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>) | |
1513 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1514 | cfa.offset = cfa_store.offset if cfa.reg == sp | |
1515 | cfa.reg = sp | |
1516 | cfa.base_offset = -cfa_store.offset | |
1517 | ||
1518 | Rule 12: | |
1519 | (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>)) | |
1520 | ||
1521 | <reg2>) | |
1522 | effects: cfa.reg = <reg1> | |
1523 | cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset | |
1524 | ||
1525 | Rule 13: | |
1526 | (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>) | |
1527 | effects: cfa.reg = <reg1> | |
1528 | cfa.base_offset = -{cfa_store,cfa_temp}.offset | |
1529 | ||
1530 | Rule 14: | |
1531 | (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>) | |
1532 | effects: cfa.reg = <reg1> | |
1533 | cfa.base_offset = -cfa_temp.offset | |
1534 | cfa_temp.offset -= mode_size(mem) | |
1535 | ||
1536 | Rule 15: | |
1537 | (set <reg> {unspec, unspec_volatile}) | |
1538 | effects: target-dependent | |
1539 | ||
1540 | Rule 16: | |
1541 | (set sp (and: sp <const_int>)) | |
1542 | constraints: cfa_store.reg == sp | |
a518b996 | 1543 | effects: cfun->fde.stack_realign = 1 |
647a1567 RH |
1544 | cfa_store.offset = 0 |
1545 | fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp | |
1546 | ||
1547 | Rule 17: | |
1548 | (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int)))) | |
1549 | effects: cfa_store.offset += -/+ mode_size(mem) | |
1550 | ||
1551 | Rule 18: | |
1552 | (set (mem ({pre_inc, pre_dec} sp)) fp) | |
1553 | constraints: fde->stack_realign == 1 | |
1554 | effects: cfa_store.offset = 0 | |
1555 | cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1556 | ||
1557 | Rule 19: | |
1558 | (set (mem ({pre_inc, pre_dec} sp)) cfa.reg) | |
1559 | constraints: fde->stack_realign == 1 | |
1560 | && cfa.offset == 0 | |
1561 | && cfa.indirect == 0 | |
1562 | && cfa.reg != HARD_FRAME_POINTER_REGNUM | |
1563 | effects: Use DW_CFA_def_cfa_expression to define cfa | |
1564 | cfa.reg == fde->drap_reg */ | |
1565 | ||
1566 | static void | |
89e25f95 | 1567 | dwarf2out_frame_debug_expr (rtx expr) |
647a1567 RH |
1568 | { |
1569 | rtx src, dest, span; | |
21810de4 | 1570 | poly_int64 offset; |
647a1567 RH |
1571 | dw_fde_ref fde; |
1572 | ||
1573 | /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of | |
1574 | the PARALLEL independently. The first element is always processed if | |
1575 | it is a SET. This is for backward compatibility. Other elements | |
1576 | are processed only if they are SETs and the RTX_FRAME_RELATED_P | |
1577 | flag is set in them. */ | |
1578 | if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE) | |
1579 | { | |
1580 | int par_index; | |
1581 | int limit = XVECLEN (expr, 0); | |
1582 | rtx elem; | |
1583 | ||
1584 | /* PARALLELs have strict read-modify-write semantics, so we | |
1585 | ought to evaluate every rvalue before changing any lvalue. | |
1586 | It's cumbersome to do that in general, but there's an | |
1587 | easy approximation that is enough for all current users: | |
1588 | handle register saves before register assignments. */ | |
1589 | if (GET_CODE (expr) == PARALLEL) | |
1590 | for (par_index = 0; par_index < limit; par_index++) | |
1591 | { | |
1592 | elem = XVECEXP (expr, 0, par_index); | |
1593 | if (GET_CODE (elem) == SET | |
1594 | && MEM_P (SET_DEST (elem)) | |
1595 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
89e25f95 | 1596 | dwarf2out_frame_debug_expr (elem); |
647a1567 RH |
1597 | } |
1598 | ||
1599 | for (par_index = 0; par_index < limit; par_index++) | |
1600 | { | |
1601 | elem = XVECEXP (expr, 0, par_index); | |
1602 | if (GET_CODE (elem) == SET | |
1603 | && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE) | |
1604 | && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) | |
89e25f95 | 1605 | dwarf2out_frame_debug_expr (elem); |
647a1567 RH |
1606 | } |
1607 | return; | |
1608 | } | |
1609 | ||
1610 | gcc_assert (GET_CODE (expr) == SET); | |
1611 | ||
1612 | src = SET_SRC (expr); | |
1613 | dest = SET_DEST (expr); | |
1614 | ||
1615 | if (REG_P (src)) | |
1616 | { | |
1617 | rtx rsi = reg_saved_in (src); | |
1618 | if (rsi) | |
1619 | src = rsi; | |
1620 | } | |
1621 | ||
a518b996 | 1622 | fde = cfun->fde; |
647a1567 RH |
1623 | |
1624 | switch (GET_CODE (dest)) | |
1625 | { | |
1626 | case REG: | |
1627 | switch (GET_CODE (src)) | |
1628 | { | |
1629 | /* Setting FP from SP. */ | |
1630 | case REG: | |
9a08d230 | 1631 | if (cur_cfa->reg == dwf_regno (src)) |
647a1567 RH |
1632 | { |
1633 | /* Rule 1 */ | |
1634 | /* Update the CFA rule wrt SP or FP. Make sure src is | |
1635 | relative to the current CFA register. | |
1636 | ||
1637 | We used to require that dest be either SP or FP, but the | |
1638 | ARM copies SP to a temporary register, and from there to | |
1639 | FP. So we just rely on the backends to only set | |
1640 | RTX_FRAME_RELATED_P on appropriate insns. */ | |
9a08d230 RH |
1641 | cur_cfa->reg = dwf_regno (dest); |
1642 | cur_trace->cfa_temp.reg = cur_cfa->reg; | |
1643 | cur_trace->cfa_temp.offset = cur_cfa->offset; | |
647a1567 RH |
1644 | } |
1645 | else | |
1646 | { | |
1647 | /* Saving a register in a register. */ | |
1648 | gcc_assert (!fixed_regs [REGNO (dest)] | |
1649 | /* For the SPARC and its register window. */ | |
7263c6d7 | 1650 | || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN)); |
647a1567 RH |
1651 | |
1652 | /* After stack is aligned, we can only save SP in FP | |
1653 | if drap register is used. In this case, we have | |
1654 | to restore stack pointer with the CFA value and we | |
1655 | don't generate this DWARF information. */ | |
1656 | if (fde | |
1657 | && fde->stack_realign | |
1658 | && REGNO (src) == STACK_POINTER_REGNUM) | |
1659 | gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM | |
1660 | && fde->drap_reg != INVALID_REGNUM | |
9a08d230 | 1661 | && cur_cfa->reg != dwf_regno (src)); |
647a1567 | 1662 | else |
89e25f95 | 1663 | queue_reg_save (src, dest, 0); |
647a1567 RH |
1664 | } |
1665 | break; | |
1666 | ||
1667 | case PLUS: | |
1668 | case MINUS: | |
1669 | case LO_SUM: | |
1670 | if (dest == stack_pointer_rtx) | |
1671 | { | |
1672 | /* Rule 2 */ | |
1673 | /* Adjusting SP. */ | |
21810de4 | 1674 | if (REG_P (XEXP (src, 1))) |
647a1567 | 1675 | { |
43215a89 RH |
1676 | gcc_assert (dwf_regno (XEXP (src, 1)) |
1677 | == cur_trace->cfa_temp.reg); | |
1678 | offset = cur_trace->cfa_temp.offset; | |
647a1567 | 1679 | } |
21810de4 RS |
1680 | else if (!poly_int_rtx_p (XEXP (src, 1), &offset)) |
1681 | gcc_unreachable (); | |
647a1567 RH |
1682 | |
1683 | if (XEXP (src, 0) == hard_frame_pointer_rtx) | |
1684 | { | |
1685 | /* Restoring SP from FP in the epilogue. */ | |
9a08d230 RH |
1686 | gcc_assert (cur_cfa->reg == dw_frame_pointer_regnum); |
1687 | cur_cfa->reg = dw_stack_pointer_regnum; | |
647a1567 RH |
1688 | } |
1689 | else if (GET_CODE (src) == LO_SUM) | |
1690 | /* Assume we've set the source reg of the LO_SUM from sp. */ | |
1691 | ; | |
1692 | else | |
1693 | gcc_assert (XEXP (src, 0) == stack_pointer_rtx); | |
1694 | ||
1695 | if (GET_CODE (src) != MINUS) | |
1696 | offset = -offset; | |
9a08d230 RH |
1697 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1698 | cur_cfa->offset += offset; | |
43215a89 RH |
1699 | if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum) |
1700 | cur_trace->cfa_store.offset += offset; | |
647a1567 RH |
1701 | } |
1702 | else if (dest == hard_frame_pointer_rtx) | |
1703 | { | |
1704 | /* Rule 3 */ | |
1705 | /* Either setting the FP from an offset of the SP, | |
1706 | or adjusting the FP */ | |
1707 | gcc_assert (frame_pointer_needed); | |
1708 | ||
1709 | gcc_assert (REG_P (XEXP (src, 0)) | |
21810de4 RS |
1710 | && dwf_regno (XEXP (src, 0)) == cur_cfa->reg); |
1711 | offset = rtx_to_poly_int64 (XEXP (src, 1)); | |
647a1567 RH |
1712 | if (GET_CODE (src) != MINUS) |
1713 | offset = -offset; | |
9a08d230 RH |
1714 | cur_cfa->offset += offset; |
1715 | cur_cfa->reg = dw_frame_pointer_regnum; | |
647a1567 RH |
1716 | } |
1717 | else | |
1718 | { | |
1719 | gcc_assert (GET_CODE (src) != MINUS); | |
1720 | ||
1721 | /* Rule 4 */ | |
1722 | if (REG_P (XEXP (src, 0)) | |
9a08d230 | 1723 | && dwf_regno (XEXP (src, 0)) == cur_cfa->reg |
21810de4 | 1724 | && poly_int_rtx_p (XEXP (src, 1), &offset)) |
647a1567 RH |
1725 | { |
1726 | /* Setting a temporary CFA register that will be copied | |
1727 | into the FP later on. */ | |
21810de4 | 1728 | offset = -offset; |
9a08d230 RH |
1729 | cur_cfa->offset += offset; |
1730 | cur_cfa->reg = dwf_regno (dest); | |
647a1567 | 1731 | /* Or used to save regs to the stack. */ |
9a08d230 RH |
1732 | cur_trace->cfa_temp.reg = cur_cfa->reg; |
1733 | cur_trace->cfa_temp.offset = cur_cfa->offset; | |
647a1567 RH |
1734 | } |
1735 | ||
1736 | /* Rule 5 */ | |
1737 | else if (REG_P (XEXP (src, 0)) | |
43215a89 | 1738 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
647a1567 RH |
1739 | && XEXP (src, 1) == stack_pointer_rtx) |
1740 | { | |
1741 | /* Setting a scratch register that we will use instead | |
1742 | of SP for saving registers to the stack. */ | |
9a08d230 | 1743 | gcc_assert (cur_cfa->reg == dw_stack_pointer_regnum); |
43215a89 RH |
1744 | cur_trace->cfa_store.reg = dwf_regno (dest); |
1745 | cur_trace->cfa_store.offset | |
9a08d230 | 1746 | = cur_cfa->offset - cur_trace->cfa_temp.offset; |
647a1567 RH |
1747 | } |
1748 | ||
1749 | /* Rule 9 */ | |
1750 | else if (GET_CODE (src) == LO_SUM | |
21810de4 RS |
1751 | && poly_int_rtx_p (XEXP (src, 1), |
1752 | &cur_trace->cfa_temp.offset)) | |
1753 | cur_trace->cfa_temp.reg = dwf_regno (dest); | |
647a1567 RH |
1754 | else |
1755 | gcc_unreachable (); | |
1756 | } | |
1757 | break; | |
1758 | ||
1759 | /* Rule 6 */ | |
1760 | case CONST_INT: | |
21810de4 | 1761 | case POLY_INT_CST: |
43215a89 | 1762 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
21810de4 | 1763 | cur_trace->cfa_temp.offset = rtx_to_poly_int64 (src); |
647a1567 RH |
1764 | break; |
1765 | ||
1766 | /* Rule 7 */ | |
1767 | case IOR: | |
1768 | gcc_assert (REG_P (XEXP (src, 0)) | |
43215a89 | 1769 | && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg |
647a1567 RH |
1770 | && CONST_INT_P (XEXP (src, 1))); |
1771 | ||
43215a89 | 1772 | cur_trace->cfa_temp.reg = dwf_regno (dest); |
21810de4 RS |
1773 | if (!can_ior_p (cur_trace->cfa_temp.offset, INTVAL (XEXP (src, 1)), |
1774 | &cur_trace->cfa_temp.offset)) | |
1775 | /* The target shouldn't generate this kind of CFI note if we | |
1776 | can't represent it. */ | |
1777 | gcc_unreachable (); | |
647a1567 RH |
1778 | break; |
1779 | ||
1780 | /* Skip over HIGH, assuming it will be followed by a LO_SUM, | |
1781 | which will fill in all of the bits. */ | |
1782 | /* Rule 8 */ | |
1783 | case HIGH: | |
1784 | break; | |
1785 | ||
1786 | /* Rule 15 */ | |
1787 | case UNSPEC: | |
1788 | case UNSPEC_VOLATILE: | |
89e25f95 BS |
1789 | /* All unspecs should be represented by REG_CFA_* notes. */ |
1790 | gcc_unreachable (); | |
647a1567 RH |
1791 | return; |
1792 | ||
1793 | /* Rule 16 */ | |
1794 | case AND: | |
1795 | /* If this AND operation happens on stack pointer in prologue, | |
1796 | we assume the stack is realigned and we extract the | |
1797 | alignment. */ | |
1798 | if (fde && XEXP (src, 0) == stack_pointer_rtx) | |
1799 | { | |
1800 | /* We interpret reg_save differently with stack_realign set. | |
1801 | Thus we must flush whatever we have queued first. */ | |
1802 | dwarf2out_flush_queued_reg_saves (); | |
1803 | ||
43215a89 RH |
1804 | gcc_assert (cur_trace->cfa_store.reg |
1805 | == dwf_regno (XEXP (src, 0))); | |
647a1567 RH |
1806 | fde->stack_realign = 1; |
1807 | fde->stack_realignment = INTVAL (XEXP (src, 1)); | |
43215a89 | 1808 | cur_trace->cfa_store.offset = 0; |
647a1567 | 1809 | |
9a08d230 RH |
1810 | if (cur_cfa->reg != dw_stack_pointer_regnum |
1811 | && cur_cfa->reg != dw_frame_pointer_regnum) | |
1812 | fde->drap_reg = cur_cfa->reg; | |
647a1567 RH |
1813 | } |
1814 | return; | |
1815 | ||
1816 | default: | |
1817 | gcc_unreachable (); | |
1818 | } | |
647a1567 RH |
1819 | break; |
1820 | ||
1821 | case MEM: | |
1822 | ||
1823 | /* Saving a register to the stack. Make sure dest is relative to the | |
1824 | CFA register. */ | |
1825 | switch (GET_CODE (XEXP (dest, 0))) | |
1826 | { | |
1827 | /* Rule 10 */ | |
1828 | /* With a push. */ | |
1829 | case PRE_MODIFY: | |
1830 | case POST_MODIFY: | |
1831 | /* We can't handle variable size modifications. */ | |
21810de4 | 1832 | offset = -rtx_to_poly_int64 (XEXP (XEXP (XEXP (dest, 0), 1), 1)); |
647a1567 RH |
1833 | |
1834 | gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM | |
43215a89 | 1835 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
647a1567 | 1836 | |
43215a89 | 1837 | cur_trace->cfa_store.offset += offset; |
9a08d230 RH |
1838 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1839 | cur_cfa->offset = cur_trace->cfa_store.offset; | |
647a1567 RH |
1840 | |
1841 | if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY) | |
43215a89 | 1842 | offset -= cur_trace->cfa_store.offset; |
647a1567 | 1843 | else |
43215a89 | 1844 | offset = -cur_trace->cfa_store.offset; |
647a1567 RH |
1845 | break; |
1846 | ||
1847 | /* Rule 11 */ | |
1848 | case PRE_INC: | |
1849 | case PRE_DEC: | |
1850 | case POST_DEC: | |
1851 | offset = GET_MODE_SIZE (GET_MODE (dest)); | |
1852 | if (GET_CODE (XEXP (dest, 0)) == PRE_INC) | |
1853 | offset = -offset; | |
1854 | ||
1855 | gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0)) | |
1856 | == STACK_POINTER_REGNUM) | |
43215a89 | 1857 | && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); |
647a1567 | 1858 | |
43215a89 | 1859 | cur_trace->cfa_store.offset += offset; |
647a1567 RH |
1860 | |
1861 | /* Rule 18: If stack is aligned, we will use FP as a | |
1862 | reference to represent the address of the stored | |
1863 | regiser. */ | |
1864 | if (fde | |
1865 | && fde->stack_realign | |
7b4d5595 L |
1866 | && REG_P (src) |
1867 | && REGNO (src) == HARD_FRAME_POINTER_REGNUM) | |
647a1567 | 1868 | { |
9a08d230 | 1869 | gcc_assert (cur_cfa->reg != dw_frame_pointer_regnum); |
43215a89 | 1870 | cur_trace->cfa_store.offset = 0; |
647a1567 RH |
1871 | } |
1872 | ||
9a08d230 RH |
1873 | if (cur_cfa->reg == dw_stack_pointer_regnum) |
1874 | cur_cfa->offset = cur_trace->cfa_store.offset; | |
647a1567 RH |
1875 | |
1876 | if (GET_CODE (XEXP (dest, 0)) == POST_DEC) | |
43215a89 | 1877 | offset += -cur_trace->cfa_store.offset; |
647a1567 | 1878 | else |
43215a89 | 1879 | offset = -cur_trace->cfa_store.offset; |
647a1567 RH |
1880 | break; |
1881 | ||
1882 | /* Rule 12 */ | |
1883 | /* With an offset. */ | |
1884 | case PLUS: | |
1885 | case MINUS: | |
1886 | case LO_SUM: | |
1887 | { | |
7263c6d7 | 1888 | unsigned int regno; |
647a1567 | 1889 | |
21810de4 RS |
1890 | gcc_assert (REG_P (XEXP (XEXP (dest, 0), 0))); |
1891 | offset = rtx_to_poly_int64 (XEXP (XEXP (dest, 0), 1)); | |
647a1567 RH |
1892 | if (GET_CODE (XEXP (dest, 0)) == MINUS) |
1893 | offset = -offset; | |
1894 | ||
7263c6d7 | 1895 | regno = dwf_regno (XEXP (XEXP (dest, 0), 0)); |
647a1567 | 1896 | |
9a08d230 RH |
1897 | if (cur_cfa->reg == regno) |
1898 | offset -= cur_cfa->offset; | |
43215a89 RH |
1899 | else if (cur_trace->cfa_store.reg == regno) |
1900 | offset -= cur_trace->cfa_store.offset; | |
647a1567 RH |
1901 | else |
1902 | { | |
43215a89 RH |
1903 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1904 | offset -= cur_trace->cfa_temp.offset; | |
647a1567 RH |
1905 | } |
1906 | } | |
1907 | break; | |
1908 | ||
1909 | /* Rule 13 */ | |
1910 | /* Without an offset. */ | |
1911 | case REG: | |
1912 | { | |
7263c6d7 | 1913 | unsigned int regno = dwf_regno (XEXP (dest, 0)); |
647a1567 | 1914 | |
9a08d230 RH |
1915 | if (cur_cfa->reg == regno) |
1916 | offset = -cur_cfa->offset; | |
43215a89 RH |
1917 | else if (cur_trace->cfa_store.reg == regno) |
1918 | offset = -cur_trace->cfa_store.offset; | |
647a1567 RH |
1919 | else |
1920 | { | |
43215a89 RH |
1921 | gcc_assert (cur_trace->cfa_temp.reg == regno); |
1922 | offset = -cur_trace->cfa_temp.offset; | |
647a1567 RH |
1923 | } |
1924 | } | |
1925 | break; | |
1926 | ||
1927 | /* Rule 14 */ | |
1928 | case POST_INC: | |
43215a89 RH |
1929 | gcc_assert (cur_trace->cfa_temp.reg |
1930 | == dwf_regno (XEXP (XEXP (dest, 0), 0))); | |
1931 | offset = -cur_trace->cfa_temp.offset; | |
1932 | cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest)); | |
647a1567 RH |
1933 | break; |
1934 | ||
1935 | default: | |
1936 | gcc_unreachable (); | |
1937 | } | |
1938 | ||
a8e5c0e7 RH |
1939 | /* Rule 17 */ |
1940 | /* If the source operand of this MEM operation is a memory, | |
1941 | we only care how much stack grew. */ | |
1942 | if (MEM_P (src)) | |
647a1567 RH |
1943 | break; |
1944 | ||
a8e5c0e7 RH |
1945 | if (REG_P (src) |
1946 | && REGNO (src) != STACK_POINTER_REGNUM | |
647a1567 | 1947 | && REGNO (src) != HARD_FRAME_POINTER_REGNUM |
9a08d230 | 1948 | && dwf_regno (src) == cur_cfa->reg) |
647a1567 RH |
1949 | { |
1950 | /* We're storing the current CFA reg into the stack. */ | |
1951 | ||
21810de4 | 1952 | if (known_eq (cur_cfa->offset, 0)) |
647a1567 RH |
1953 | { |
1954 | /* Rule 19 */ | |
1955 | /* If stack is aligned, putting CFA reg into stack means | |
1956 | we can no longer use reg + offset to represent CFA. | |
1957 | Here we use DW_CFA_def_cfa_expression instead. The | |
1958 | result of this expression equals to the original CFA | |
1959 | value. */ | |
1960 | if (fde | |
1961 | && fde->stack_realign | |
9a08d230 RH |
1962 | && cur_cfa->indirect == 0 |
1963 | && cur_cfa->reg != dw_frame_pointer_regnum) | |
647a1567 | 1964 | { |
9a08d230 | 1965 | gcc_assert (fde->drap_reg == cur_cfa->reg); |
647a1567 | 1966 | |
9a08d230 RH |
1967 | cur_cfa->indirect = 1; |
1968 | cur_cfa->reg = dw_frame_pointer_regnum; | |
1969 | cur_cfa->base_offset = offset; | |
1970 | cur_cfa->offset = 0; | |
647a1567 RH |
1971 | |
1972 | fde->drap_reg_saved = 1; | |
647a1567 RH |
1973 | break; |
1974 | } | |
1975 | ||
1976 | /* If the source register is exactly the CFA, assume | |
1977 | we're saving SP like any other register; this happens | |
1978 | on the ARM. */ | |
89e25f95 | 1979 | queue_reg_save (stack_pointer_rtx, NULL_RTX, offset); |
647a1567 RH |
1980 | break; |
1981 | } | |
1982 | else | |
1983 | { | |
1984 | /* Otherwise, we'll need to look in the stack to | |
1985 | calculate the CFA. */ | |
1986 | rtx x = XEXP (dest, 0); | |
1987 | ||
1988 | if (!REG_P (x)) | |
1989 | x = XEXP (x, 0); | |
1990 | gcc_assert (REG_P (x)); | |
1991 | ||
9a08d230 RH |
1992 | cur_cfa->reg = dwf_regno (x); |
1993 | cur_cfa->base_offset = offset; | |
1994 | cur_cfa->indirect = 1; | |
647a1567 RH |
1995 | break; |
1996 | } | |
1997 | } | |
1998 | ||
a8e5c0e7 RH |
1999 | if (REG_P (src)) |
2000 | span = targetm.dwarf_register_span (src); | |
a4d47cac EB |
2001 | else |
2002 | span = NULL; | |
2003 | ||
a8e5c0e7 RH |
2004 | if (!span) |
2005 | queue_reg_save (src, NULL_RTX, offset); | |
2006 | else | |
2007 | { | |
2008 | /* We have a PARALLEL describing where the contents of SRC live. | |
2009 | Queue register saves for each piece of the PARALLEL. */ | |
21810de4 | 2010 | poly_int64 span_offset = offset; |
647a1567 | 2011 | |
a8e5c0e7 | 2012 | gcc_assert (GET_CODE (span) == PARALLEL); |
647a1567 | 2013 | |
a4d47cac EB |
2014 | const int par_len = XVECLEN (span, 0); |
2015 | for (int par_index = 0; par_index < par_len; par_index++) | |
a8e5c0e7 RH |
2016 | { |
2017 | rtx elem = XVECEXP (span, 0, par_index); | |
2018 | queue_reg_save (elem, NULL_RTX, span_offset); | |
2019 | span_offset += GET_MODE_SIZE (GET_MODE (elem)); | |
2020 | } | |
2021 | } | |
647a1567 RH |
2022 | break; |
2023 | ||
2024 | default: | |
2025 | gcc_unreachable (); | |
2026 | } | |
2027 | } | |
2028 | ||
9a08d230 RH |
2029 | /* Record call frame debugging information for INSN, which either sets |
2030 | SP or FP (adjusting how we calculate the frame address) or saves a | |
2031 | register to the stack. */ | |
647a1567 | 2032 | |
7644b3c7 | 2033 | static void |
e8a54173 | 2034 | dwarf2out_frame_debug (rtx_insn *insn) |
647a1567 | 2035 | { |
e8a54173 | 2036 | rtx note, n, pat; |
647a1567 | 2037 | bool handled_one = false; |
647a1567 RH |
2038 | |
2039 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
2040 | switch (REG_NOTE_KIND (note)) | |
2041 | { | |
2042 | case REG_FRAME_RELATED_EXPR: | |
e8a54173 | 2043 | pat = XEXP (note, 0); |
647a1567 RH |
2044 | goto do_frame_expr; |
2045 | ||
2046 | case REG_CFA_DEF_CFA: | |
89e25f95 | 2047 | dwarf2out_frame_debug_def_cfa (XEXP (note, 0)); |
647a1567 RH |
2048 | handled_one = true; |
2049 | break; | |
2050 | ||
2051 | case REG_CFA_ADJUST_CFA: | |
2052 | n = XEXP (note, 0); | |
2053 | if (n == NULL) | |
2054 | { | |
2055 | n = PATTERN (insn); | |
2056 | if (GET_CODE (n) == PARALLEL) | |
2057 | n = XVECEXP (n, 0, 0); | |
2058 | } | |
89e25f95 | 2059 | dwarf2out_frame_debug_adjust_cfa (n); |
647a1567 RH |
2060 | handled_one = true; |
2061 | break; | |
2062 | ||
2063 | case REG_CFA_OFFSET: | |
2064 | n = XEXP (note, 0); | |
2065 | if (n == NULL) | |
2066 | n = single_set (insn); | |
89e25f95 | 2067 | dwarf2out_frame_debug_cfa_offset (n); |
647a1567 RH |
2068 | handled_one = true; |
2069 | break; | |
2070 | ||
2071 | case REG_CFA_REGISTER: | |
2072 | n = XEXP (note, 0); | |
2073 | if (n == NULL) | |
2074 | { | |
2075 | n = PATTERN (insn); | |
2076 | if (GET_CODE (n) == PARALLEL) | |
2077 | n = XVECEXP (n, 0, 0); | |
2078 | } | |
89e25f95 | 2079 | dwarf2out_frame_debug_cfa_register (n); |
647a1567 RH |
2080 | handled_one = true; |
2081 | break; | |
2082 | ||
2083 | case REG_CFA_EXPRESSION: | |
ac5b3eff | 2084 | case REG_CFA_VAL_EXPRESSION: |
647a1567 RH |
2085 | n = XEXP (note, 0); |
2086 | if (n == NULL) | |
2087 | n = single_set (insn); | |
ac5b3eff JW |
2088 | |
2089 | if (REG_NOTE_KIND (note) == REG_CFA_EXPRESSION) | |
2090 | dwarf2out_frame_debug_cfa_expression (n); | |
2091 | else | |
2092 | dwarf2out_frame_debug_cfa_val_expression (n); | |
2093 | ||
647a1567 RH |
2094 | handled_one = true; |
2095 | break; | |
2096 | ||
2097 | case REG_CFA_RESTORE: | |
2098 | n = XEXP (note, 0); | |
2099 | if (n == NULL) | |
2100 | { | |
2101 | n = PATTERN (insn); | |
2102 | if (GET_CODE (n) == PARALLEL) | |
2103 | n = XVECEXP (n, 0, 0); | |
2104 | n = XEXP (n, 0); | |
2105 | } | |
89e25f95 | 2106 | dwarf2out_frame_debug_cfa_restore (n); |
647a1567 RH |
2107 | handled_one = true; |
2108 | break; | |
2109 | ||
2110 | case REG_CFA_SET_VDRAP: | |
2111 | n = XEXP (note, 0); | |
2112 | if (REG_P (n)) | |
2113 | { | |
a518b996 | 2114 | dw_fde_ref fde = cfun->fde; |
647a1567 RH |
2115 | if (fde) |
2116 | { | |
2117 | gcc_assert (fde->vdrap_reg == INVALID_REGNUM); | |
2118 | if (REG_P (n)) | |
7263c6d7 | 2119 | fde->vdrap_reg = dwf_regno (n); |
647a1567 RH |
2120 | } |
2121 | } | |
2122 | handled_one = true; | |
2123 | break; | |
2124 | ||
27169e45 | 2125 | case REG_CFA_TOGGLE_RA_MANGLE: |
647a1567 | 2126 | case REG_CFA_WINDOW_SAVE: |
27169e45 | 2127 | /* We overload both of these operations onto the same DWARF opcode. */ |
89e25f95 | 2128 | dwarf2out_frame_debug_cfa_window_save (); |
647a1567 RH |
2129 | handled_one = true; |
2130 | break; | |
2131 | ||
2132 | case REG_CFA_FLUSH_QUEUE: | |
67d7405e | 2133 | /* The actual flush happens elsewhere. */ |
647a1567 RH |
2134 | handled_one = true; |
2135 | break; | |
2136 | ||
2137 | default: | |
2138 | break; | |
2139 | } | |
2140 | ||
67d7405e | 2141 | if (!handled_one) |
647a1567 | 2142 | { |
e8a54173 | 2143 | pat = PATTERN (insn); |
647a1567 | 2144 | do_frame_expr: |
e8a54173 | 2145 | dwarf2out_frame_debug_expr (pat); |
647a1567 RH |
2146 | |
2147 | /* Check again. A parallel can save and update the same register. | |
2148 | We could probably check just once, here, but this is safer than | |
2149 | removing the check at the start of the function. */ | |
e8a54173 | 2150 | if (clobbers_queued_reg_save (pat)) |
67d7405e | 2151 | dwarf2out_flush_queued_reg_saves (); |
647a1567 | 2152 | } |
647a1567 RH |
2153 | } |
2154 | ||
57e16c96 RH |
2155 | /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */ |
2156 | ||
2157 | static void | |
ce363ef2 | 2158 | change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row) |
57e16c96 RH |
2159 | { |
2160 | size_t i, n_old, n_new, n_max; | |
2161 | dw_cfi_ref cfi; | |
2162 | ||
2163 | if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi)) | |
2164 | add_cfi (new_row->cfa_cfi); | |
2165 | else | |
2166 | { | |
2167 | cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa); | |
2168 | if (cfi) | |
2169 | add_cfi (cfi); | |
2170 | } | |
2171 | ||
9771b263 DN |
2172 | n_old = vec_safe_length (old_row->reg_save); |
2173 | n_new = vec_safe_length (new_row->reg_save); | |
57e16c96 RH |
2174 | n_max = MAX (n_old, n_new); |
2175 | ||
2176 | for (i = 0; i < n_max; ++i) | |
2177 | { | |
2178 | dw_cfi_ref r_old = NULL, r_new = NULL; | |
2179 | ||
2180 | if (i < n_old) | |
9771b263 | 2181 | r_old = (*old_row->reg_save)[i]; |
57e16c96 | 2182 | if (i < n_new) |
9771b263 | 2183 | r_new = (*new_row->reg_save)[i]; |
57e16c96 RH |
2184 | |
2185 | if (r_old == r_new) | |
2186 | ; | |
2187 | else if (r_new == NULL) | |
2188 | add_cfi_restore (i); | |
2189 | else if (!cfi_equal_p (r_old, r_new)) | |
2190 | add_cfi (r_new); | |
2191 | } | |
2192 | } | |
2193 | ||
89e25f95 BS |
2194 | /* Examine CFI and return true if a cfi label and set_loc is needed |
2195 | beforehand. Even when generating CFI assembler instructions, we | |
4a8ee122 | 2196 | still have to add the cfi to the list so that lookup_cfa_1 works |
89e25f95 BS |
2197 | later on. When -g2 and above we even need to force emitting of |
2198 | CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list | |
2199 | purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa | |
2200 | and so don't use convert_cfa_to_fb_loc_list. */ | |
2201 | ||
2202 | static bool | |
2203 | cfi_label_required_p (dw_cfi_ref cfi) | |
2204 | { | |
2205 | if (!dwarf2out_do_cfi_asm ()) | |
2206 | return true; | |
2207 | ||
2208 | if (dwarf_version == 2 | |
2209 | && debug_info_level > DINFO_LEVEL_TERSE | |
2210 | && (write_symbols == DWARF2_DEBUG | |
2211 | || write_symbols == VMS_AND_DWARF2_DEBUG)) | |
2212 | { | |
2213 | switch (cfi->dw_cfi_opc) | |
2214 | { | |
2215 | case DW_CFA_def_cfa_offset: | |
2216 | case DW_CFA_def_cfa_offset_sf: | |
2217 | case DW_CFA_def_cfa_register: | |
2218 | case DW_CFA_def_cfa: | |
2219 | case DW_CFA_def_cfa_sf: | |
2220 | case DW_CFA_def_cfa_expression: | |
2221 | case DW_CFA_restore_state: | |
2222 | return true; | |
2223 | default: | |
2224 | return false; | |
2225 | } | |
2226 | } | |
2227 | return false; | |
2228 | } | |
2229 | ||
2230 | /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the | |
2231 | function's FDE, adding CFI labels and set_loc/advance_loc opcodes as | |
2232 | necessary. */ | |
2233 | static void | |
2234 | add_cfis_to_fde (void) | |
2235 | { | |
a518b996 | 2236 | dw_fde_ref fde = cfun->fde; |
f65c531e | 2237 | rtx_insn *insn, *next; |
89e25f95 BS |
2238 | |
2239 | for (insn = get_insns (); insn; insn = next) | |
2240 | { | |
2241 | next = NEXT_INSN (insn); | |
2242 | ||
2243 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
0eeb9f3d | 2244 | fde->dw_fde_switch_cfi_index = vec_safe_length (fde->dw_fde_cfi); |
89e25f95 BS |
2245 | |
2246 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) | |
2247 | { | |
2248 | bool required = cfi_label_required_p (NOTE_CFI (insn)); | |
b84dad8e JJ |
2249 | while (next) |
2250 | if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI) | |
2251 | { | |
2252 | required |= cfi_label_required_p (NOTE_CFI (next)); | |
2253 | next = NEXT_INSN (next); | |
2254 | } | |
2255 | else if (active_insn_p (next) | |
2256 | || (NOTE_P (next) && (NOTE_KIND (next) | |
2257 | == NOTE_INSN_SWITCH_TEXT_SECTIONS))) | |
2258 | break; | |
2259 | else | |
89e25f95 | 2260 | next = NEXT_INSN (next); |
89e25f95 BS |
2261 | if (required) |
2262 | { | |
2263 | int num = dwarf2out_cfi_label_num; | |
2264 | const char *label = dwarf2out_cfi_label (); | |
2265 | dw_cfi_ref xcfi; | |
89e25f95 BS |
2266 | |
2267 | /* Set the location counter to the new label. */ | |
2268 | xcfi = new_cfi (); | |
0eeb9f3d | 2269 | xcfi->dw_cfi_opc = DW_CFA_advance_loc4; |
89e25f95 | 2270 | xcfi->dw_cfi_oprnd1.dw_cfi_addr = label; |
9771b263 | 2271 | vec_safe_push (fde->dw_fde_cfi, xcfi); |
89e25f95 | 2272 | |
e67d1102 | 2273 | rtx_note *tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn); |
89e25f95 BS |
2274 | NOTE_LABEL_NUMBER (tmp) = num; |
2275 | } | |
2276 | ||
2277 | do | |
2278 | { | |
b84dad8e | 2279 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) |
9771b263 | 2280 | vec_safe_push (fde->dw_fde_cfi, NOTE_CFI (insn)); |
89e25f95 BS |
2281 | insn = NEXT_INSN (insn); |
2282 | } | |
2283 | while (insn != next); | |
89e25f95 BS |
2284 | } |
2285 | } | |
2286 | } | |
2287 | ||
a1566696 SB |
2288 | static void dump_cfi_row (FILE *f, dw_cfi_row *row); |
2289 | ||
829bdd4b RH |
2290 | /* If LABEL is the start of a trace, then initialize the state of that |
2291 | trace from CUR_TRACE and CUR_ROW. */ | |
43215a89 | 2292 | |
7644b3c7 | 2293 | static void |
7583d99a | 2294 | maybe_record_trace_start (rtx_insn *start, rtx_insn *origin) |
89e25f95 | 2295 | { |
829bdd4b | 2296 | dw_trace_info *ti; |
829bdd4b RH |
2297 | |
2298 | ti = get_trace_info (start); | |
2299 | gcc_assert (ti != NULL); | |
647a1567 | 2300 | |
829bdd4b | 2301 | if (dump_file) |
647a1567 | 2302 | { |
829bdd4b | 2303 | fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n", |
200e10dc | 2304 | cur_trace->id, ti->id, |
829bdd4b RH |
2305 | (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"), |
2306 | (origin ? INSN_UID (origin) : 0)); | |
2307 | } | |
bc5612ed | 2308 | |
68184180 | 2309 | poly_int64 args_size = cur_trace->end_true_args_size; |
829bdd4b RH |
2310 | if (ti->beg_row == NULL) |
2311 | { | |
2312 | /* This is the first time we've encountered this trace. Propagate | |
2313 | state across the edge and push the trace onto the work list. */ | |
2314 | ti->beg_row = copy_cfi_row (cur_row); | |
9a08d230 | 2315 | ti->beg_true_args_size = args_size; |
2f23f97a | 2316 | |
829bdd4b RH |
2317 | ti->cfa_store = cur_trace->cfa_store; |
2318 | ti->cfa_temp = cur_trace->cfa_temp; | |
9771b263 | 2319 | ti->regs_saved_in_regs = cur_trace->regs_saved_in_regs.copy (); |
829bdd4b | 2320 | |
9771b263 | 2321 | trace_work_list.safe_push (ti); |
829bdd4b RH |
2322 | |
2323 | if (dump_file) | |
200e10dc | 2324 | fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id); |
829bdd4b RH |
2325 | } |
2326 | else | |
2327 | { | |
9a08d230 | 2328 | |
829bdd4b RH |
2329 | /* We ought to have the same state incoming to a given trace no |
2330 | matter how we arrive at the trace. Anything else means we've | |
2331 | got some kind of optimization error. */ | |
a1566696 SB |
2332 | #if CHECKING_P |
2333 | if (!cfi_row_equal_p (cur_row, ti->beg_row)) | |
2334 | { | |
2335 | if (dump_file) | |
2336 | { | |
2337 | fprintf (dump_file, "Inconsistent CFI state!\n"); | |
2338 | fprintf (dump_file, "SHOULD have:\n"); | |
2339 | dump_cfi_row (dump_file, ti->beg_row); | |
2340 | fprintf (dump_file, "DO have:\n"); | |
2341 | dump_cfi_row (dump_file, cur_row); | |
2342 | } | |
2343 | ||
2344 | gcc_unreachable (); | |
2345 | } | |
2346 | #endif | |
9a08d230 RH |
2347 | |
2348 | /* The args_size is allowed to conflict if it isn't actually used. */ | |
68184180 | 2349 | if (maybe_ne (ti->beg_true_args_size, args_size)) |
9a08d230 RH |
2350 | ti->args_size_undefined = true; |
2351 | } | |
2352 | } | |
2353 | ||
2354 | /* Similarly, but handle the args_size and CFA reset across EH | |
2355 | and non-local goto edges. */ | |
2356 | ||
2357 | static void | |
7583d99a | 2358 | maybe_record_trace_start_abnormal (rtx_insn *start, rtx_insn *origin) |
9a08d230 | 2359 | { |
68184180 | 2360 | poly_int64 save_args_size, delta; |
9a08d230 RH |
2361 | dw_cfa_location save_cfa; |
2362 | ||
2363 | save_args_size = cur_trace->end_true_args_size; | |
68184180 | 2364 | if (known_eq (save_args_size, 0)) |
9a08d230 RH |
2365 | { |
2366 | maybe_record_trace_start (start, origin); | |
2367 | return; | |
2368 | } | |
2369 | ||
2370 | delta = -save_args_size; | |
2371 | cur_trace->end_true_args_size = 0; | |
2372 | ||
2373 | save_cfa = cur_row->cfa; | |
2374 | if (cur_row->cfa.reg == dw_stack_pointer_regnum) | |
2375 | { | |
2376 | /* Convert a change in args_size (always a positive in the | |
2377 | direction of stack growth) to a change in stack pointer. */ | |
581edfa3 TS |
2378 | if (!STACK_GROWS_DOWNWARD) |
2379 | delta = -delta; | |
2380 | ||
9a08d230 | 2381 | cur_row->cfa.offset += delta; |
829bdd4b | 2382 | } |
9a08d230 RH |
2383 | |
2384 | maybe_record_trace_start (start, origin); | |
2385 | ||
2386 | cur_trace->end_true_args_size = save_args_size; | |
2387 | cur_row->cfa = save_cfa; | |
829bdd4b | 2388 | } |
45fba6d1 | 2389 | |
829bdd4b RH |
2390 | /* Propagate CUR_TRACE state to the destinations implied by INSN. */ |
2391 | /* ??? Sadly, this is in large part a duplicate of make_edges. */ | |
2392 | ||
2393 | static void | |
7583d99a | 2394 | create_trace_edges (rtx_insn *insn) |
829bdd4b | 2395 | { |
ca486330 | 2396 | rtx tmp; |
829bdd4b RH |
2397 | int i, n; |
2398 | ||
2399 | if (JUMP_P (insn)) | |
2400 | { | |
8942ee0f DM |
2401 | rtx_jump_table_data *table; |
2402 | ||
829bdd4b | 2403 | if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) |
9a08d230 RH |
2404 | return; |
2405 | ||
8942ee0f | 2406 | if (tablejump_p (insn, NULL, &table)) |
bc5612ed | 2407 | { |
95c43227 | 2408 | rtvec vec = table->get_labels (); |
829bdd4b RH |
2409 | |
2410 | n = GET_NUM_ELEM (vec); | |
2411 | for (i = 0; i < n; ++i) | |
2412 | { | |
7583d99a | 2413 | rtx_insn *lab = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, i), 0)); |
9a08d230 | 2414 | maybe_record_trace_start (lab, insn); |
829bdd4b RH |
2415 | } |
2416 | } | |
2417 | else if (computed_jump_p (insn)) | |
bc5612ed | 2418 | { |
6f7eba34 TS |
2419 | rtx_insn *temp; |
2420 | unsigned int i; | |
2421 | FOR_EACH_VEC_SAFE_ELT (forced_labels, i, temp) | |
2422 | maybe_record_trace_start (temp, insn); | |
829bdd4b RH |
2423 | } |
2424 | else if (returnjump_p (insn)) | |
2425 | ; | |
2426 | else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL) | |
2427 | { | |
2428 | n = ASM_OPERANDS_LABEL_LENGTH (tmp); | |
2429 | for (i = 0; i < n; ++i) | |
bc5612ed | 2430 | { |
7583d99a DM |
2431 | rtx_insn *lab = |
2432 | as_a <rtx_insn *> (XEXP (ASM_OPERANDS_LABEL (tmp, i), 0)); | |
9a08d230 | 2433 | maybe_record_trace_start (lab, insn); |
829bdd4b RH |
2434 | } |
2435 | } | |
2436 | else | |
2437 | { | |
7583d99a | 2438 | rtx_insn *lab = JUMP_LABEL_AS_INSN (insn); |
829bdd4b | 2439 | gcc_assert (lab != NULL); |
9a08d230 | 2440 | maybe_record_trace_start (lab, insn); |
829bdd4b RH |
2441 | } |
2442 | } | |
2443 | else if (CALL_P (insn)) | |
2444 | { | |
2445 | /* Sibling calls don't have edges inside this function. */ | |
2446 | if (SIBLING_CALL_P (insn)) | |
2447 | return; | |
965b2557 | 2448 | |
829bdd4b RH |
2449 | /* Process non-local goto edges. */ |
2450 | if (can_nonlocal_goto (insn)) | |
b5241a5a | 2451 | for (rtx_insn_list *lab = nonlocal_goto_handler_labels; |
2382940b DM |
2452 | lab; |
2453 | lab = lab->next ()) | |
b5241a5a | 2454 | maybe_record_trace_start_abnormal (lab->insn (), insn); |
829bdd4b | 2455 | } |
292d1dfb | 2456 | else if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) |
3382318a | 2457 | { |
292d1dfb | 2458 | int i, n = seq->len (); |
3382318a | 2459 | for (i = 0; i < n; ++i) |
292d1dfb | 2460 | create_trace_edges (seq->insn (i)); |
3382318a RH |
2461 | return; |
2462 | } | |
965b2557 | 2463 | |
829bdd4b RH |
2464 | /* Process EH edges. */ |
2465 | if (CALL_P (insn) || cfun->can_throw_non_call_exceptions) | |
2466 | { | |
2467 | eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn); | |
2468 | if (lp) | |
9a08d230 | 2469 | maybe_record_trace_start_abnormal (lp->landing_pad, insn); |
829bdd4b RH |
2470 | } |
2471 | } | |
57e16c96 | 2472 | |
eebc8f37 RH |
2473 | /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */ |
2474 | ||
2475 | static void | |
e8a54173 | 2476 | scan_insn_after (rtx_insn *insn) |
eebc8f37 RH |
2477 | { |
2478 | if (RTX_FRAME_RELATED_P (insn)) | |
2479 | dwarf2out_frame_debug (insn); | |
2480 | notice_args_size (insn); | |
2481 | } | |
2482 | ||
829bdd4b RH |
2483 | /* Scan the trace beginning at INSN and create the CFI notes for the |
2484 | instructions therein. */ | |
2485 | ||
2486 | static void | |
2487 | scan_trace (dw_trace_info *trace) | |
2488 | { | |
7583d99a | 2489 | rtx_insn *prev, *insn = trace->head; |
9a08d230 | 2490 | dw_cfa_location this_cfa; |
829bdd4b RH |
2491 | |
2492 | if (dump_file) | |
2493 | fprintf (dump_file, "Processing trace %u : start at %s %d\n", | |
200e10dc | 2494 | trace->id, rtx_name[(int) GET_CODE (insn)], |
829bdd4b RH |
2495 | INSN_UID (insn)); |
2496 | ||
2497 | trace->end_row = copy_cfi_row (trace->beg_row); | |
9a08d230 | 2498 | trace->end_true_args_size = trace->beg_true_args_size; |
829bdd4b RH |
2499 | |
2500 | cur_trace = trace; | |
2501 | cur_row = trace->end_row; | |
9a08d230 RH |
2502 | |
2503 | this_cfa = cur_row->cfa; | |
2504 | cur_cfa = &this_cfa; | |
829bdd4b | 2505 | |
eebc8f37 RH |
2506 | for (prev = insn, insn = NEXT_INSN (insn); |
2507 | insn; | |
2508 | prev = insn, insn = NEXT_INSN (insn)) | |
829bdd4b | 2509 | { |
7583d99a | 2510 | rtx_insn *control; |
eebc8f37 | 2511 | |
9a08d230 | 2512 | /* Do everything that happens "before" the insn. */ |
eebc8f37 | 2513 | add_cfi_insn = prev; |
829bdd4b RH |
2514 | |
2515 | /* Notice the end of a trace. */ | |
9a08d230 RH |
2516 | if (BARRIER_P (insn)) |
2517 | { | |
2518 | /* Don't bother saving the unneeded queued registers at all. */ | |
9771b263 | 2519 | queued_reg_saves.truncate (0); |
9a08d230 RH |
2520 | break; |
2521 | } | |
2522 | if (save_point_p (insn)) | |
829bdd4b | 2523 | { |
829bdd4b | 2524 | /* Propagate across fallthru edges. */ |
9a08d230 RH |
2525 | dwarf2out_flush_queued_reg_saves (); |
2526 | maybe_record_trace_start (insn, NULL); | |
829bdd4b | 2527 | break; |
bc5612ed BS |
2528 | } |
2529 | ||
829bdd4b | 2530 | if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn)) |
bc5612ed BS |
2531 | continue; |
2532 | ||
eebc8f37 RH |
2533 | /* Handle all changes to the row state. Sequences require special |
2534 | handling for the positioning of the notes. */ | |
292d1dfb | 2535 | if (rtx_sequence *pat = dyn_cast <rtx_sequence *> (PATTERN (insn))) |
bc5612ed | 2536 | { |
e8a54173 | 2537 | rtx_insn *elt; |
292d1dfb | 2538 | int i, n = pat->len (); |
9a08d230 | 2539 | |
7583d99a | 2540 | control = pat->insn (0); |
eebc8f37 RH |
2541 | if (can_throw_internal (control)) |
2542 | notice_eh_throw (control); | |
2543 | dwarf2out_flush_queued_reg_saves (); | |
2544 | ||
8f06d483 | 2545 | if (JUMP_P (control) && INSN_ANNULLED_BRANCH_P (control)) |
829bdd4b | 2546 | { |
9a08d230 RH |
2547 | /* ??? Hopefully multiple delay slots are not annulled. */ |
2548 | gcc_assert (n == 2); | |
eebc8f37 RH |
2549 | gcc_assert (!RTX_FRAME_RELATED_P (control)); |
2550 | gcc_assert (!find_reg_note (control, REG_ARGS_SIZE, NULL)); | |
2551 | ||
e8a54173 | 2552 | elt = pat->insn (1); |
9a08d230 | 2553 | |
9a08d230 RH |
2554 | if (INSN_FROM_TARGET_P (elt)) |
2555 | { | |
5d1f1cd5 | 2556 | cfi_vec save_row_reg_save; |
829bdd4b | 2557 | |
bf27c43e RH |
2558 | /* If ELT is an instruction from target of an annulled |
2559 | branch, the effects are for the target only and so | |
2560 | the args_size and CFA along the current path | |
2561 | shouldn't change. */ | |
eebc8f37 | 2562 | add_cfi_insn = NULL; |
68184180 | 2563 | poly_int64 restore_args_size = cur_trace->end_true_args_size; |
9a08d230 | 2564 | cur_cfa = &cur_row->cfa; |
9771b263 | 2565 | save_row_reg_save = vec_safe_copy (cur_row->reg_save); |
bc5612ed | 2566 | |
eebc8f37 RH |
2567 | scan_insn_after (elt); |
2568 | ||
2569 | /* ??? Should we instead save the entire row state? */ | |
9771b263 | 2570 | gcc_assert (!queued_reg_saves.length ()); |
eebc8f37 RH |
2571 | |
2572 | create_trace_edges (control); | |
bc5612ed | 2573 | |
9a08d230 RH |
2574 | cur_trace->end_true_args_size = restore_args_size; |
2575 | cur_row->cfa = this_cfa; | |
5d1f1cd5 | 2576 | cur_row->reg_save = save_row_reg_save; |
9a08d230 | 2577 | cur_cfa = &this_cfa; |
9a08d230 | 2578 | } |
bf27c43e RH |
2579 | else |
2580 | { | |
2581 | /* If ELT is a annulled branch-taken instruction (i.e. | |
2582 | executed only when branch is not taken), the args_size | |
2583 | and CFA should not change through the jump. */ | |
2584 | create_trace_edges (control); | |
2585 | ||
2586 | /* Update and continue with the trace. */ | |
2587 | add_cfi_insn = insn; | |
2588 | scan_insn_after (elt); | |
2589 | def_cfa_1 (&this_cfa); | |
2590 | } | |
2591 | continue; | |
9a08d230 RH |
2592 | } |
2593 | ||
eebc8f37 RH |
2594 | /* The insns in the delay slot should all be considered to happen |
2595 | "before" a call insn. Consider a call with a stack pointer | |
2596 | adjustment in the delay slot. The backtrace from the callee | |
2597 | should include the sp adjustment. Unfortunately, that leaves | |
2598 | us with an unavoidable unwinding error exactly at the call insn | |
2599 | itself. For jump insns we'd prefer to avoid this error by | |
2600 | placing the notes after the sequence. */ | |
2601 | if (JUMP_P (control)) | |
2602 | add_cfi_insn = insn; | |
2603 | ||
9a08d230 RH |
2604 | for (i = 1; i < n; ++i) |
2605 | { | |
e8a54173 | 2606 | elt = pat->insn (i); |
eebc8f37 | 2607 | scan_insn_after (elt); |
9a08d230 | 2608 | } |
eebc8f37 RH |
2609 | |
2610 | /* Make sure any register saves are visible at the jump target. */ | |
2611 | dwarf2out_flush_queued_reg_saves (); | |
67d7405e | 2612 | any_cfis_emitted = false; |
eebc8f37 RH |
2613 | |
2614 | /* However, if there is some adjustment on the call itself, e.g. | |
2615 | a call_pop, that action should be considered to happen after | |
2616 | the call returns. */ | |
2617 | add_cfi_insn = insn; | |
2618 | scan_insn_after (control); | |
829bdd4b | 2619 | } |
9a08d230 | 2620 | else |
eebc8f37 RH |
2621 | { |
2622 | /* Flush data before calls and jumps, and of course if necessary. */ | |
2623 | if (can_throw_internal (insn)) | |
2624 | { | |
2625 | notice_eh_throw (insn); | |
2626 | dwarf2out_flush_queued_reg_saves (); | |
2627 | } | |
2628 | else if (!NONJUMP_INSN_P (insn) | |
2629 | || clobbers_queued_reg_save (insn) | |
2630 | || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) | |
2631 | dwarf2out_flush_queued_reg_saves (); | |
67d7405e | 2632 | any_cfis_emitted = false; |
eebc8f37 RH |
2633 | |
2634 | add_cfi_insn = insn; | |
2635 | scan_insn_after (insn); | |
2636 | control = insn; | |
2637 | } | |
9a08d230 RH |
2638 | |
2639 | /* Between frame-related-p and args_size we might have otherwise | |
2640 | emitted two cfa adjustments. Do it now. */ | |
2641 | def_cfa_1 (&this_cfa); | |
45fba6d1 | 2642 | |
67d7405e RH |
2643 | /* Minimize the number of advances by emitting the entire queue |
2644 | once anything is emitted. */ | |
2645 | if (any_cfis_emitted | |
2646 | || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) | |
2647 | dwarf2out_flush_queued_reg_saves (); | |
2648 | ||
829bdd4b RH |
2649 | /* Note that a test for control_flow_insn_p does exactly the |
2650 | same tests as are done to actually create the edges. So | |
2651 | always call the routine and let it not create edges for | |
2652 | non-control-flow insns. */ | |
eebc8f37 | 2653 | create_trace_edges (control); |
647a1567 | 2654 | } |
45fba6d1 | 2655 | |
141618e2 | 2656 | add_cfi_insn = NULL; |
829bdd4b RH |
2657 | cur_row = NULL; |
2658 | cur_trace = NULL; | |
9a08d230 | 2659 | cur_cfa = NULL; |
647a1567 RH |
2660 | } |
2661 | ||
829bdd4b | 2662 | /* Scan the function and create the initial set of CFI notes. */ |
647a1567 | 2663 | |
bc5612ed | 2664 | static void |
829bdd4b | 2665 | create_cfi_notes (void) |
647a1567 | 2666 | { |
829bdd4b | 2667 | dw_trace_info *ti; |
647a1567 | 2668 | |
9771b263 DN |
2669 | gcc_checking_assert (!queued_reg_saves.exists ()); |
2670 | gcc_checking_assert (!trace_work_list.exists ()); | |
647a1567 | 2671 | |
829bdd4b | 2672 | /* Always begin at the entry trace. */ |
9771b263 | 2673 | ti = &trace_info[0]; |
829bdd4b | 2674 | scan_trace (ti); |
647a1567 | 2675 | |
9771b263 | 2676 | while (!trace_work_list.is_empty ()) |
829bdd4b | 2677 | { |
9771b263 | 2678 | ti = trace_work_list.pop (); |
829bdd4b | 2679 | scan_trace (ti); |
647a1567 RH |
2680 | } |
2681 | ||
9771b263 DN |
2682 | queued_reg_saves.release (); |
2683 | trace_work_list.release (); | |
829bdd4b | 2684 | } |
647a1567 | 2685 | |
200e10dc RH |
2686 | /* Return the insn before the first NOTE_INSN_CFI after START. */ |
2687 | ||
dc01c3d1 DM |
2688 | static rtx_insn * |
2689 | before_next_cfi_note (rtx_insn *start) | |
200e10dc | 2690 | { |
dc01c3d1 | 2691 | rtx_insn *prev = start; |
200e10dc RH |
2692 | while (start) |
2693 | { | |
2694 | if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI) | |
2695 | return prev; | |
2696 | prev = start; | |
2697 | start = NEXT_INSN (start); | |
2698 | } | |
2699 | gcc_unreachable (); | |
2700 | } | |
2701 | ||
829bdd4b | 2702 | /* Insert CFI notes between traces to properly change state between them. */ |
647a1567 | 2703 | |
829bdd4b RH |
2704 | static void |
2705 | connect_traces (void) | |
2706 | { | |
9771b263 | 2707 | unsigned i, n = trace_info.length (); |
829bdd4b RH |
2708 | dw_trace_info *prev_ti, *ti; |
2709 | ||
200e10dc RH |
2710 | /* ??? Ideally, we should have both queued and processed every trace. |
2711 | However the current representation of constant pools on various targets | |
2712 | is indistinguishable from unreachable code. Assume for the moment that | |
2713 | we can simply skip over such traces. */ | |
2714 | /* ??? Consider creating a DATA_INSN rtx code to indicate that | |
2715 | these are not "real" instructions, and should not be considered. | |
2716 | This could be generically useful for tablejump data as well. */ | |
2717 | /* Remove all unprocessed traces from the list. */ | |
2718 | for (i = n - 1; i > 0; --i) | |
2719 | { | |
9771b263 | 2720 | ti = &trace_info[i]; |
200e10dc RH |
2721 | if (ti->beg_row == NULL) |
2722 | { | |
9771b263 | 2723 | trace_info.ordered_remove (i); |
200e10dc RH |
2724 | n -= 1; |
2725 | } | |
2726 | else | |
2727 | gcc_assert (ti->end_row != NULL); | |
2728 | } | |
829bdd4b | 2729 | |
200e10dc RH |
2730 | /* Work from the end back to the beginning. This lets us easily insert |
2731 | remember/restore_state notes in the correct order wrt other notes. */ | |
9771b263 | 2732 | prev_ti = &trace_info[n - 1]; |
200e10dc | 2733 | for (i = n - 1; i > 0; --i) |
647a1567 | 2734 | { |
829bdd4b | 2735 | dw_cfi_row *old_row; |
647a1567 | 2736 | |
200e10dc | 2737 | ti = prev_ti; |
9771b263 | 2738 | prev_ti = &trace_info[i - 1]; |
647a1567 | 2739 | |
200e10dc | 2740 | add_cfi_insn = ti->head; |
829bdd4b RH |
2741 | |
2742 | /* In dwarf2out_switch_text_section, we'll begin a new FDE | |
2743 | for the portion of the function in the alternate text | |
2744 | section. The row state at the very beginning of that | |
2745 | new FDE will be exactly the row state from the CIE. */ | |
2746 | if (ti->switch_sections) | |
2747 | old_row = cie_cfi_row; | |
2748 | else | |
200e10dc RH |
2749 | { |
2750 | old_row = prev_ti->end_row; | |
2751 | /* If there's no change from the previous end state, fine. */ | |
2752 | if (cfi_row_equal_p (old_row, ti->beg_row)) | |
2753 | ; | |
2754 | /* Otherwise check for the common case of sharing state with | |
2755 | the beginning of an epilogue, but not the end. Insert | |
2756 | remember/restore opcodes in that case. */ | |
2757 | else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row)) | |
2758 | { | |
2759 | dw_cfi_ref cfi; | |
2760 | ||
2761 | /* Note that if we blindly insert the remember at the | |
2762 | start of the trace, we can wind up increasing the | |
2763 | size of the unwind info due to extra advance opcodes. | |
2764 | Instead, put the remember immediately before the next | |
2765 | state change. We know there must be one, because the | |
2766 | state at the beginning and head of the trace differ. */ | |
2767 | add_cfi_insn = before_next_cfi_note (prev_ti->head); | |
2768 | cfi = new_cfi (); | |
2769 | cfi->dw_cfi_opc = DW_CFA_remember_state; | |
2770 | add_cfi (cfi); | |
2771 | ||
2772 | add_cfi_insn = ti->head; | |
2773 | cfi = new_cfi (); | |
2774 | cfi->dw_cfi_opc = DW_CFA_restore_state; | |
2775 | add_cfi (cfi); | |
2776 | ||
2777 | old_row = prev_ti->beg_row; | |
2778 | } | |
2779 | /* Otherwise, we'll simply change state from the previous end. */ | |
2780 | } | |
829bdd4b | 2781 | |
829bdd4b RH |
2782 | change_cfi_row (old_row, ti->beg_row); |
2783 | ||
2784 | if (dump_file && add_cfi_insn != ti->head) | |
2785 | { | |
dc01c3d1 | 2786 | rtx_insn *note; |
829bdd4b | 2787 | |
200e10dc RH |
2788 | fprintf (dump_file, "Fixup between trace %u and %u:\n", |
2789 | prev_ti->id, ti->id); | |
829bdd4b RH |
2790 | |
2791 | note = ti->head; | |
2792 | do | |
2793 | { | |
2794 | note = NEXT_INSN (note); | |
2795 | gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI); | |
2796 | output_cfi_directive (dump_file, NOTE_CFI (note)); | |
2797 | } | |
2798 | while (note != add_cfi_insn); | |
2799 | } | |
2800 | } | |
9a08d230 RH |
2801 | |
2802 | /* Connect args_size between traces that have can_throw_internal insns. */ | |
9771b263 | 2803 | if (cfun->eh->lp_array) |
9a08d230 | 2804 | { |
68184180 | 2805 | poly_int64 prev_args_size = 0; |
9a08d230 RH |
2806 | |
2807 | for (i = 0; i < n; ++i) | |
2808 | { | |
9771b263 | 2809 | ti = &trace_info[i]; |
9a08d230 RH |
2810 | |
2811 | if (ti->switch_sections) | |
2812 | prev_args_size = 0; | |
2813 | if (ti->eh_head == NULL) | |
2814 | continue; | |
2815 | gcc_assert (!ti->args_size_undefined); | |
2816 | ||
68184180 | 2817 | if (maybe_ne (ti->beg_delay_args_size, prev_args_size)) |
9a08d230 RH |
2818 | { |
2819 | /* ??? Search back to previous CFI note. */ | |
2820 | add_cfi_insn = PREV_INSN (ti->eh_head); | |
2821 | add_cfi_args_size (ti->beg_delay_args_size); | |
2822 | } | |
2823 | ||
2824 | prev_args_size = ti->end_delay_args_size; | |
2825 | } | |
2826 | } | |
647a1567 RH |
2827 | } |
2828 | ||
829bdd4b RH |
2829 | /* Set up the pseudo-cfg of instruction traces, as described at the |
2830 | block comment at the top of the file. */ | |
647a1567 | 2831 | |
bc5612ed | 2832 | static void |
829bdd4b | 2833 | create_pseudo_cfg (void) |
647a1567 | 2834 | { |
829bdd4b | 2835 | bool saw_barrier, switch_sections; |
f32682ca | 2836 | dw_trace_info ti; |
f65c531e | 2837 | rtx_insn *insn; |
829bdd4b RH |
2838 | unsigned i; |
2839 | ||
2840 | /* The first trace begins at the start of the function, | |
2841 | and begins with the CIE row state. */ | |
9771b263 | 2842 | trace_info.create (16); |
f32682ca DN |
2843 | memset (&ti, 0, sizeof (ti)); |
2844 | ti.head = get_insns (); | |
2845 | ti.beg_row = cie_cfi_row; | |
2846 | ti.cfa_store = cie_cfi_row->cfa; | |
2847 | ti.cfa_temp.reg = INVALID_REGNUM; | |
9771b263 | 2848 | trace_info.quick_push (ti); |
829bdd4b | 2849 | |
829bdd4b | 2850 | if (cie_return_save) |
9771b263 | 2851 | ti.regs_saved_in_regs.safe_push (*cie_return_save); |
647a1567 | 2852 | |
829bdd4b RH |
2853 | /* Walk all the insns, collecting start of trace locations. */ |
2854 | saw_barrier = false; | |
2855 | switch_sections = false; | |
2856 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
2857 | { | |
2858 | if (BARRIER_P (insn)) | |
2859 | saw_barrier = true; | |
2860 | else if (NOTE_P (insn) | |
2861 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
2862 | { | |
2863 | /* We should have just seen a barrier. */ | |
2864 | gcc_assert (saw_barrier); | |
2865 | switch_sections = true; | |
2866 | } | |
2867 | /* Watch out for save_point notes between basic blocks. | |
2868 | In particular, a note after a barrier. Do not record these, | |
2869 | delaying trace creation until the label. */ | |
2870 | else if (save_point_p (insn) | |
2871 | && (LABEL_P (insn) || !saw_barrier)) | |
2872 | { | |
f32682ca DN |
2873 | memset (&ti, 0, sizeof (ti)); |
2874 | ti.head = insn; | |
2875 | ti.switch_sections = switch_sections; | |
f8ed2fc2 | 2876 | ti.id = trace_info.length (); |
9771b263 | 2877 | trace_info.safe_push (ti); |
829bdd4b RH |
2878 | |
2879 | saw_barrier = false; | |
2880 | switch_sections = false; | |
2881 | } | |
2882 | } | |
2883 | ||
2884 | /* Create the trace index after we've finished building trace_info, | |
2885 | avoiding stale pointer problems due to reallocation. */ | |
c203e8a7 TS |
2886 | trace_index |
2887 | = new hash_table<trace_info_hasher> (trace_info.length ()); | |
f32682ca | 2888 | dw_trace_info *tp; |
9771b263 | 2889 | FOR_EACH_VEC_ELT (trace_info, i, tp) |
829bdd4b | 2890 | { |
4a8fb1a1 | 2891 | dw_trace_info **slot; |
647a1567 | 2892 | |
829bdd4b | 2893 | if (dump_file) |
f8ed2fc2 | 2894 | fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", tp->id, |
f32682ca DN |
2895 | rtx_name[(int) GET_CODE (tp->head)], INSN_UID (tp->head), |
2896 | tp->switch_sections ? " (section switch)" : ""); | |
829bdd4b | 2897 | |
c203e8a7 | 2898 | slot = trace_index->find_slot_with_hash (tp, INSN_UID (tp->head), INSERT); |
829bdd4b | 2899 | gcc_assert (*slot == NULL); |
4a8fb1a1 | 2900 | *slot = tp; |
829bdd4b | 2901 | } |
647a1567 | 2902 | } |
829bdd4b | 2903 | |
a8e5c0e7 RH |
2904 | /* Record the initial position of the return address. RTL is |
2905 | INCOMING_RETURN_ADDR_RTX. */ | |
2906 | ||
2907 | static void | |
2908 | initial_return_save (rtx rtl) | |
2909 | { | |
2910 | unsigned int reg = INVALID_REGNUM; | |
21810de4 | 2911 | poly_int64 offset = 0; |
a8e5c0e7 RH |
2912 | |
2913 | switch (GET_CODE (rtl)) | |
2914 | { | |
2915 | case REG: | |
2916 | /* RA is in a register. */ | |
7263c6d7 | 2917 | reg = dwf_regno (rtl); |
a8e5c0e7 RH |
2918 | break; |
2919 | ||
2920 | case MEM: | |
2921 | /* RA is on the stack. */ | |
2922 | rtl = XEXP (rtl, 0); | |
2923 | switch (GET_CODE (rtl)) | |
2924 | { | |
2925 | case REG: | |
2926 | gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM); | |
2927 | offset = 0; | |
2928 | break; | |
2929 | ||
2930 | case PLUS: | |
2931 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
21810de4 | 2932 | offset = rtx_to_poly_int64 (XEXP (rtl, 1)); |
a8e5c0e7 RH |
2933 | break; |
2934 | ||
2935 | case MINUS: | |
2936 | gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); | |
21810de4 | 2937 | offset = -rtx_to_poly_int64 (XEXP (rtl, 1)); |
a8e5c0e7 RH |
2938 | break; |
2939 | ||
2940 | default: | |
2941 | gcc_unreachable (); | |
2942 | } | |
2943 | ||
2944 | break; | |
2945 | ||
2946 | case PLUS: | |
2947 | /* The return address is at some offset from any value we can | |
2948 | actually load. For instance, on the SPARC it is in %i7+8. Just | |
2949 | ignore the offset for now; it doesn't matter for unwinding frames. */ | |
2950 | gcc_assert (CONST_INT_P (XEXP (rtl, 1))); | |
2951 | initial_return_save (XEXP (rtl, 0)); | |
2952 | return; | |
2953 | ||
2954 | default: | |
2955 | gcc_unreachable (); | |
2956 | } | |
2957 | ||
2958 | if (reg != DWARF_FRAME_RETURN_COLUMN) | |
2959 | { | |
2960 | if (reg != INVALID_REGNUM) | |
2961 | record_reg_saved_in_reg (rtl, pc_rtx); | |
f17d3401 | 2962 | reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset); |
a8e5c0e7 RH |
2963 | } |
2964 | } | |
647a1567 | 2965 | |
43215a89 RH |
2966 | static void |
2967 | create_cie_data (void) | |
2968 | { | |
2969 | dw_cfa_location loc; | |
2970 | dw_trace_info cie_trace; | |
2971 | ||
2972 | dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); | |
43215a89 | 2973 | |
c3284718 | 2974 | memset (&cie_trace, 0, sizeof (cie_trace)); |
43215a89 RH |
2975 | cur_trace = &cie_trace; |
2976 | ||
2977 | add_cfi_vec = &cie_cfi_vec; | |
2978 | cie_cfi_row = cur_row = new_cfi_row (); | |
2979 | ||
2980 | /* On entry, the Canonical Frame Address is at SP. */ | |
c3284718 | 2981 | memset (&loc, 0, sizeof (loc)); |
43215a89 RH |
2982 | loc.reg = dw_stack_pointer_regnum; |
2983 | loc.offset = INCOMING_FRAME_SP_OFFSET; | |
2984 | def_cfa_1 (&loc); | |
2985 | ||
2986 | if (targetm.debug_unwind_info () == UI_DWARF2 | |
2987 | || targetm_common.except_unwind_info (&global_options) == UI_DWARF2) | |
2988 | { | |
2989 | initial_return_save (INCOMING_RETURN_ADDR_RTX); | |
2990 | ||
2991 | /* For a few targets, we have the return address incoming into a | |
2992 | register, but choose a different return column. This will result | |
2993 | in a DW_CFA_register for the return, and an entry in | |
2994 | regs_saved_in_regs to match. If the target later stores that | |
2995 | return address register to the stack, we want to be able to emit | |
2996 | the DW_CFA_offset against the return column, not the intermediate | |
2997 | save register. Save the contents of regs_saved_in_regs so that | |
2998 | we can re-initialize it at the start of each function. */ | |
9771b263 | 2999 | switch (cie_trace.regs_saved_in_regs.length ()) |
43215a89 RH |
3000 | { |
3001 | case 0: | |
3002 | break; | |
3003 | case 1: | |
766090c2 | 3004 | cie_return_save = ggc_alloc<reg_saved_in_data> (); |
9771b263 DN |
3005 | *cie_return_save = cie_trace.regs_saved_in_regs[0]; |
3006 | cie_trace.regs_saved_in_regs.release (); | |
43215a89 RH |
3007 | break; |
3008 | default: | |
3009 | gcc_unreachable (); | |
3010 | } | |
3011 | } | |
3012 | ||
3013 | add_cfi_vec = NULL; | |
3014 | cur_row = NULL; | |
3015 | cur_trace = NULL; | |
3016 | } | |
3017 | ||
7644b3c7 RH |
3018 | /* Annotate the function with NOTE_INSN_CFI notes to record the CFI |
3019 | state at each location within the function. These notes will be | |
3020 | emitted during pass_final. */ | |
647a1567 | 3021 | |
7644b3c7 RH |
3022 | static unsigned int |
3023 | execute_dwarf2_frame (void) | |
647a1567 | 3024 | { |
703fa2e6 CB |
3025 | /* Different HARD_FRAME_POINTER_REGNUM might coexist in the same file. */ |
3026 | dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM); | |
3027 | ||
7644b3c7 RH |
3028 | /* The first time we're called, compute the incoming frame state. */ |
3029 | if (cie_cfi_vec == NULL) | |
43215a89 | 3030 | create_cie_data (); |
3edb53aa | 3031 | |
7644b3c7 RH |
3032 | dwarf2out_alloc_current_fde (); |
3033 | ||
829bdd4b RH |
3034 | create_pseudo_cfg (); |
3035 | ||
7644b3c7 RH |
3036 | /* Do the work. */ |
3037 | create_cfi_notes (); | |
829bdd4b | 3038 | connect_traces (); |
7644b3c7 RH |
3039 | add_cfis_to_fde (); |
3040 | ||
829bdd4b RH |
3041 | /* Free all the data we allocated. */ |
3042 | { | |
3043 | size_t i; | |
3044 | dw_trace_info *ti; | |
647a1567 | 3045 | |
9771b263 DN |
3046 | FOR_EACH_VEC_ELT (trace_info, i, ti) |
3047 | ti->regs_saved_in_regs.release (); | |
829bdd4b | 3048 | } |
9771b263 | 3049 | trace_info.release (); |
829bdd4b | 3050 | |
c203e8a7 TS |
3051 | delete trace_index; |
3052 | trace_index = NULL; | |
f17d3401 | 3053 | |
7644b3c7 | 3054 | return 0; |
647a1567 RH |
3055 | } |
3056 | \f | |
948d330e RH |
3057 | /* Convert a DWARF call frame info. operation to its string name */ |
3058 | ||
3059 | static const char * | |
3060 | dwarf_cfi_name (unsigned int cfi_opc) | |
3061 | { | |
11ec770e | 3062 | const char *name = get_DW_CFA_name (cfi_opc); |
948d330e | 3063 | |
11ec770e TT |
3064 | if (name != NULL) |
3065 | return name; | |
948d330e | 3066 | |
11ec770e | 3067 | return "DW_CFA_<unknown>"; |
948d330e RH |
3068 | } |
3069 | ||
3070 | /* This routine will generate the correct assembly data for a location | |
3071 | description based on a cfi entry with a complex address. */ | |
3072 | ||
3073 | static void | |
3074 | output_cfa_loc (dw_cfi_ref cfi, int for_eh) | |
3075 | { | |
3076 | dw_loc_descr_ref loc; | |
3077 | unsigned long size; | |
3078 | ||
ac5b3eff JW |
3079 | if (cfi->dw_cfi_opc == DW_CFA_expression |
3080 | || cfi->dw_cfi_opc == DW_CFA_val_expression) | |
948d330e | 3081 | { |
43215a89 | 3082 | unsigned r = |
948d330e RH |
3083 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); |
3084 | dw2_asm_output_data (1, r, NULL); | |
3085 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3086 | } | |
3087 | else | |
3088 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3089 | ||
3090 | /* Output the size of the block. */ | |
3091 | size = size_of_locs (loc); | |
3092 | dw2_asm_output_data_uleb128 (size, NULL); | |
3093 | ||
3094 | /* Now output the operations themselves. */ | |
3095 | output_loc_sequence (loc, for_eh); | |
3096 | } | |
3097 | ||
3098 | /* Similar, but used for .cfi_escape. */ | |
3099 | ||
3100 | static void | |
3101 | output_cfa_loc_raw (dw_cfi_ref cfi) | |
3102 | { | |
3103 | dw_loc_descr_ref loc; | |
3104 | unsigned long size; | |
3105 | ||
ac5b3eff JW |
3106 | if (cfi->dw_cfi_opc == DW_CFA_expression |
3107 | || cfi->dw_cfi_opc == DW_CFA_val_expression) | |
948d330e | 3108 | { |
43215a89 | 3109 | unsigned r = |
948d330e RH |
3110 | DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); |
3111 | fprintf (asm_out_file, "%#x,", r); | |
3112 | loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; | |
3113 | } | |
3114 | else | |
3115 | loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; | |
3116 | ||
3117 | /* Output the size of the block. */ | |
3118 | size = size_of_locs (loc); | |
3119 | dw2_asm_output_data_uleb128_raw (size); | |
3120 | fputc (',', asm_out_file); | |
3121 | ||
3122 | /* Now output the operations themselves. */ | |
3123 | output_loc_sequence_raw (loc); | |
3124 | } | |
3125 | ||
3126 | /* Output a Call Frame Information opcode and its operand(s). */ | |
3127 | ||
3128 | void | |
3129 | output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh) | |
3130 | { | |
3131 | unsigned long r; | |
3132 | HOST_WIDE_INT off; | |
3133 | ||
3134 | if (cfi->dw_cfi_opc == DW_CFA_advance_loc) | |
3135 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | |
3136 | | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)), | |
3137 | "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX, | |
3138 | ((unsigned HOST_WIDE_INT) | |
3139 | cfi->dw_cfi_oprnd1.dw_cfi_offset)); | |
3140 | else if (cfi->dw_cfi_opc == DW_CFA_offset) | |
3141 | { | |
3142 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3143 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3144 | "DW_CFA_offset, column %#lx", r); | |
3145 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3146 | dw2_asm_output_data_uleb128 (off, NULL); | |
3147 | } | |
3148 | else if (cfi->dw_cfi_opc == DW_CFA_restore) | |
3149 | { | |
3150 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3151 | dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), | |
3152 | "DW_CFA_restore, column %#lx", r); | |
3153 | } | |
3154 | else | |
3155 | { | |
3156 | dw2_asm_output_data (1, cfi->dw_cfi_opc, | |
3157 | "%s", dwarf_cfi_name (cfi->dw_cfi_opc)); | |
3158 | ||
3159 | switch (cfi->dw_cfi_opc) | |
3160 | { | |
3161 | case DW_CFA_set_loc: | |
3162 | if (for_eh) | |
3163 | dw2_asm_output_encoded_addr_rtx ( | |
3164 | ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0), | |
3165 | gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr), | |
3166 | false, NULL); | |
3167 | else | |
3168 | dw2_asm_output_addr (DWARF2_ADDR_SIZE, | |
3169 | cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL); | |
3170 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3171 | break; | |
3172 | ||
3173 | case DW_CFA_advance_loc1: | |
3174 | dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3175 | fde->dw_fde_current_label, NULL); | |
3176 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3177 | break; | |
3178 | ||
3179 | case DW_CFA_advance_loc2: | |
3180 | dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3181 | fde->dw_fde_current_label, NULL); | |
3182 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3183 | break; | |
3184 | ||
3185 | case DW_CFA_advance_loc4: | |
3186 | dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3187 | fde->dw_fde_current_label, NULL); | |
3188 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3189 | break; | |
3190 | ||
3191 | case DW_CFA_MIPS_advance_loc8: | |
3192 | dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr, | |
3193 | fde->dw_fde_current_label, NULL); | |
3194 | fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; | |
3195 | break; | |
3196 | ||
3197 | case DW_CFA_offset_extended: | |
3198 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3199 | dw2_asm_output_data_uleb128 (r, NULL); | |
3200 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3201 | dw2_asm_output_data_uleb128 (off, NULL); | |
3202 | break; | |
3203 | ||
3204 | case DW_CFA_def_cfa: | |
3205 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3206 | dw2_asm_output_data_uleb128 (r, NULL); | |
3207 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL); | |
3208 | break; | |
3209 | ||
3210 | case DW_CFA_offset_extended_sf: | |
3211 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3212 | dw2_asm_output_data_uleb128 (r, NULL); | |
3213 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3214 | dw2_asm_output_data_sleb128 (off, NULL); | |
3215 | break; | |
3216 | ||
3217 | case DW_CFA_def_cfa_sf: | |
3218 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3219 | dw2_asm_output_data_uleb128 (r, NULL); | |
3220 | off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); | |
3221 | dw2_asm_output_data_sleb128 (off, NULL); | |
3222 | break; | |
3223 | ||
3224 | case DW_CFA_restore_extended: | |
3225 | case DW_CFA_undefined: | |
3226 | case DW_CFA_same_value: | |
3227 | case DW_CFA_def_cfa_register: | |
3228 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3229 | dw2_asm_output_data_uleb128 (r, NULL); | |
3230 | break; | |
3231 | ||
3232 | case DW_CFA_register: | |
3233 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); | |
3234 | dw2_asm_output_data_uleb128 (r, NULL); | |
3235 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh); | |
3236 | dw2_asm_output_data_uleb128 (r, NULL); | |
3237 | break; | |
3238 | ||
3239 | case DW_CFA_def_cfa_offset: | |
3240 | case DW_CFA_GNU_args_size: | |
3241 | dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL); | |
3242 | break; | |
3243 | ||
3244 | case DW_CFA_def_cfa_offset_sf: | |
3245 | off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3246 | dw2_asm_output_data_sleb128 (off, NULL); | |
3247 | break; | |
3248 | ||
3249 | case DW_CFA_GNU_window_save: | |
3250 | break; | |
3251 | ||
3252 | case DW_CFA_def_cfa_expression: | |
3253 | case DW_CFA_expression: | |
ac5b3eff | 3254 | case DW_CFA_val_expression: |
948d330e RH |
3255 | output_cfa_loc (cfi, for_eh); |
3256 | break; | |
3257 | ||
3258 | case DW_CFA_GNU_negative_offset_extended: | |
3259 | /* Obsoleted by DW_CFA_offset_extended_sf. */ | |
3260 | gcc_unreachable (); | |
3261 | ||
3262 | default: | |
3263 | break; | |
3264 | } | |
3265 | } | |
3266 | } | |
3267 | ||
3268 | /* Similar, but do it via assembler directives instead. */ | |
3269 | ||
3270 | void | |
3271 | output_cfi_directive (FILE *f, dw_cfi_ref cfi) | |
3272 | { | |
3273 | unsigned long r, r2; | |
3274 | ||
3275 | switch (cfi->dw_cfi_opc) | |
3276 | { | |
3277 | case DW_CFA_advance_loc: | |
3278 | case DW_CFA_advance_loc1: | |
3279 | case DW_CFA_advance_loc2: | |
3280 | case DW_CFA_advance_loc4: | |
3281 | case DW_CFA_MIPS_advance_loc8: | |
3282 | case DW_CFA_set_loc: | |
3283 | /* Should only be created in a code path not followed when emitting | |
3284 | via directives. The assembler is going to take care of this for | |
3285 | us. But this routines is also used for debugging dumps, so | |
3286 | print something. */ | |
3287 | gcc_assert (f != asm_out_file); | |
3288 | fprintf (f, "\t.cfi_advance_loc\n"); | |
3289 | break; | |
3290 | ||
3291 | case DW_CFA_offset: | |
3292 | case DW_CFA_offset_extended: | |
3293 | case DW_CFA_offset_extended_sf: | |
3294 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
16998094 | 3295 | fprintf (f, "\t.cfi_offset %lu, " HOST_WIDE_INT_PRINT_DEC"\n", |
948d330e RH |
3296 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); |
3297 | break; | |
3298 | ||
3299 | case DW_CFA_restore: | |
3300 | case DW_CFA_restore_extended: | |
3301 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3302 | fprintf (f, "\t.cfi_restore %lu\n", r); | |
3303 | break; | |
3304 | ||
3305 | case DW_CFA_undefined: | |
3306 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3307 | fprintf (f, "\t.cfi_undefined %lu\n", r); | |
3308 | break; | |
3309 | ||
3310 | case DW_CFA_same_value: | |
3311 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3312 | fprintf (f, "\t.cfi_same_value %lu\n", r); | |
3313 | break; | |
3314 | ||
3315 | case DW_CFA_def_cfa: | |
3316 | case DW_CFA_def_cfa_sf: | |
3317 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
16998094 | 3318 | fprintf (f, "\t.cfi_def_cfa %lu, " HOST_WIDE_INT_PRINT_DEC"\n", |
948d330e RH |
3319 | r, cfi->dw_cfi_oprnd2.dw_cfi_offset); |
3320 | break; | |
3321 | ||
3322 | case DW_CFA_def_cfa_register: | |
3323 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3324 | fprintf (f, "\t.cfi_def_cfa_register %lu\n", r); | |
3325 | break; | |
3326 | ||
3327 | case DW_CFA_register: | |
3328 | r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); | |
3329 | r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1); | |
3330 | fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2); | |
3331 | break; | |
3332 | ||
3333 | case DW_CFA_def_cfa_offset: | |
3334 | case DW_CFA_def_cfa_offset_sf: | |
3335 | fprintf (f, "\t.cfi_def_cfa_offset " | |
3336 | HOST_WIDE_INT_PRINT_DEC"\n", | |
3337 | cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3338 | break; | |
3339 | ||
3340 | case DW_CFA_remember_state: | |
3341 | fprintf (f, "\t.cfi_remember_state\n"); | |
3342 | break; | |
3343 | case DW_CFA_restore_state: | |
3344 | fprintf (f, "\t.cfi_restore_state\n"); | |
3345 | break; | |
3346 | ||
3347 | case DW_CFA_GNU_args_size: | |
3348 | if (f == asm_out_file) | |
3349 | { | |
3350 | fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size); | |
3351 | dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset); | |
3352 | if (flag_debug_asm) | |
16998094 | 3353 | fprintf (f, "\t%s args_size " HOST_WIDE_INT_PRINT_DEC, |
948d330e RH |
3354 | ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset); |
3355 | fputc ('\n', f); | |
3356 | } | |
3357 | else | |
3358 | { | |
16998094 | 3359 | fprintf (f, "\t.cfi_GNU_args_size " HOST_WIDE_INT_PRINT_DEC "\n", |
948d330e RH |
3360 | cfi->dw_cfi_oprnd1.dw_cfi_offset); |
3361 | } | |
3362 | break; | |
3363 | ||
3364 | case DW_CFA_GNU_window_save: | |
3365 | fprintf (f, "\t.cfi_window_save\n"); | |
3366 | break; | |
3367 | ||
3368 | case DW_CFA_def_cfa_expression: | |
948d330e | 3369 | case DW_CFA_expression: |
ac5b3eff | 3370 | case DW_CFA_val_expression: |
948d330e RH |
3371 | if (f != asm_out_file) |
3372 | { | |
ac5b3eff JW |
3373 | fprintf (f, "\t.cfi_%scfa_%sexpression ...\n", |
3374 | cfi->dw_cfi_opc == DW_CFA_def_cfa_expression ? "def_" : "", | |
3375 | cfi->dw_cfi_opc == DW_CFA_val_expression ? "val_" : ""); | |
948d330e RH |
3376 | break; |
3377 | } | |
3378 | fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc); | |
3379 | output_cfa_loc_raw (cfi); | |
3380 | fputc ('\n', f); | |
3381 | break; | |
3382 | ||
3383 | default: | |
3384 | gcc_unreachable (); | |
3385 | } | |
3386 | } | |
3387 | ||
3388 | void | |
3389 | dwarf2out_emit_cfi (dw_cfi_ref cfi) | |
3390 | { | |
3391 | if (dwarf2out_do_cfi_asm ()) | |
3392 | output_cfi_directive (asm_out_file, cfi); | |
3393 | } | |
a5d0ce89 RH |
3394 | |
3395 | static void | |
3396 | dump_cfi_row (FILE *f, dw_cfi_row *row) | |
3397 | { | |
3398 | dw_cfi_ref cfi; | |
3399 | unsigned i; | |
3400 | ||
3401 | cfi = row->cfa_cfi; | |
3402 | if (!cfi) | |
3403 | { | |
3404 | dw_cfa_location dummy; | |
c3284718 | 3405 | memset (&dummy, 0, sizeof (dummy)); |
a5d0ce89 RH |
3406 | dummy.reg = INVALID_REGNUM; |
3407 | cfi = def_cfa_0 (&dummy, &row->cfa); | |
3408 | } | |
3409 | output_cfi_directive (f, cfi); | |
3410 | ||
9771b263 | 3411 | FOR_EACH_VEC_SAFE_ELT (row->reg_save, i, cfi) |
a5d0ce89 RH |
3412 | if (cfi) |
3413 | output_cfi_directive (f, cfi); | |
a5d0ce89 RH |
3414 | } |
3415 | ||
3416 | void debug_cfi_row (dw_cfi_row *row); | |
3417 | ||
3418 | void | |
3419 | debug_cfi_row (dw_cfi_row *row) | |
3420 | { | |
3421 | dump_cfi_row (stderr, row); | |
3422 | } | |
948d330e | 3423 | \f |
647a1567 | 3424 | |
7644b3c7 RH |
3425 | /* Save the result of dwarf2out_do_frame across PCH. |
3426 | This variable is tri-state, with 0 unset, >0 true, <0 false. */ | |
3427 | static GTY(()) signed char saved_do_cfi_asm = 0; | |
647a1567 | 3428 | |
2f02b2c2 EB |
3429 | /* Decide whether to emit EH frame unwind information for the current |
3430 | translation unit. */ | |
3431 | ||
3432 | bool | |
3433 | dwarf2out_do_eh_frame (void) | |
3434 | { | |
3435 | return | |
3436 | (flag_unwind_tables || flag_exceptions) | |
3437 | && targetm_common.except_unwind_info (&global_options) == UI_DWARF2; | |
3438 | } | |
3439 | ||
647a1567 RH |
3440 | /* Decide whether we want to emit frame unwind information for the current |
3441 | translation unit. */ | |
3442 | ||
7644b3c7 | 3443 | bool |
647a1567 RH |
3444 | dwarf2out_do_frame (void) |
3445 | { | |
3446 | /* We want to emit correct CFA location expressions or lists, so we | |
3447 | have to return true if we're going to output debug info, even if | |
3448 | we're not going to output frame or unwind info. */ | |
3449 | if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG) | |
3450 | return true; | |
3451 | ||
7644b3c7 | 3452 | if (saved_do_cfi_asm > 0) |
647a1567 RH |
3453 | return true; |
3454 | ||
3455 | if (targetm.debug_unwind_info () == UI_DWARF2) | |
3456 | return true; | |
3457 | ||
2f02b2c2 | 3458 | if (dwarf2out_do_eh_frame ()) |
647a1567 RH |
3459 | return true; |
3460 | ||
3461 | return false; | |
3462 | } | |
3463 | ||
3464 | /* Decide whether to emit frame unwind via assembler directives. */ | |
3465 | ||
7644b3c7 | 3466 | bool |
647a1567 RH |
3467 | dwarf2out_do_cfi_asm (void) |
3468 | { | |
3469 | int enc; | |
3470 | ||
7644b3c7 RH |
3471 | if (saved_do_cfi_asm != 0) |
3472 | return saved_do_cfi_asm > 0; | |
3473 | ||
3474 | /* Assume failure for a moment. */ | |
3475 | saved_do_cfi_asm = -1; | |
3476 | ||
647a1567 RH |
3477 | if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ()) |
3478 | return false; | |
3479 | if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) | |
3480 | return false; | |
3481 | ||
3482 | /* Make sure the personality encoding is one the assembler can support. | |
3483 | In particular, aligned addresses can't be handled. */ | |
3484 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1); | |
3485 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3486 | return false; | |
3487 | enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0); | |
3488 | if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) | |
3489 | return false; | |
3490 | ||
3491 | /* If we can't get the assembler to emit only .debug_frame, and we don't need | |
3492 | dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */ | |
2f02b2c2 | 3493 | if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE && !dwarf2out_do_eh_frame ()) |
647a1567 RH |
3494 | return false; |
3495 | ||
7644b3c7 RH |
3496 | /* Success! */ |
3497 | saved_do_cfi_asm = 1; | |
647a1567 RH |
3498 | return true; |
3499 | } | |
3500 | ||
27a4cd48 DM |
3501 | namespace { |
3502 | ||
3503 | const pass_data pass_data_dwarf2_frame = | |
3504 | { | |
3505 | RTL_PASS, /* type */ | |
3506 | "dwarf2", /* name */ | |
3507 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
3508 | TV_FINAL, /* tv_id */ |
3509 | 0, /* properties_required */ | |
3510 | 0, /* properties_provided */ | |
3511 | 0, /* properties_destroyed */ | |
3512 | 0, /* todo_flags_start */ | |
3513 | 0, /* todo_flags_finish */ | |
7644b3c7 RH |
3514 | }; |
3515 | ||
27a4cd48 DM |
3516 | class pass_dwarf2_frame : public rtl_opt_pass |
3517 | { | |
3518 | public: | |
c3284718 RS |
3519 | pass_dwarf2_frame (gcc::context *ctxt) |
3520 | : rtl_opt_pass (pass_data_dwarf2_frame, ctxt) | |
27a4cd48 DM |
3521 | {} |
3522 | ||
3523 | /* opt_pass methods: */ | |
1a3d085c | 3524 | virtual bool gate (function *); |
be55bfe6 | 3525 | virtual unsigned int execute (function *) { return execute_dwarf2_frame (); } |
27a4cd48 DM |
3526 | |
3527 | }; // class pass_dwarf2_frame | |
3528 | ||
1a3d085c TS |
3529 | bool |
3530 | pass_dwarf2_frame::gate (function *) | |
3531 | { | |
1a3d085c TS |
3532 | /* Targets which still implement the prologue in assembler text |
3533 | cannot use the generic dwarf2 unwinding. */ | |
e86a9946 RS |
3534 | if (!targetm.have_prologue ()) |
3535 | return false; | |
1a3d085c TS |
3536 | |
3537 | /* ??? What to do for UI_TARGET unwinding? They might be able to benefit | |
3538 | from the optimized shrink-wrapping annotations that we will compute. | |
3539 | For now, only produce the CFI notes for dwarf2. */ | |
3540 | return dwarf2out_do_frame (); | |
3541 | } | |
3542 | ||
27a4cd48 DM |
3543 | } // anon namespace |
3544 | ||
3545 | rtl_opt_pass * | |
3546 | make_pass_dwarf2_frame (gcc::context *ctxt) | |
3547 | { | |
3548 | return new pass_dwarf2_frame (ctxt); | |
3549 | } | |
3550 | ||
647a1567 | 3551 | #include "gt-dwarf2cfi.h" |