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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
99dee823 | 2 | Copyright (C) 1987-2021 Free Software Foundation, Inc. |
23b2ce53 | 3 | |
1322177d | 4 | This file is part of GCC. |
23b2ce53 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
23b2ce53 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
23b2ce53 RS |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
19 | |
20 | ||
21 | /* Middle-to-low level generation of rtx code and insns. | |
22 | ||
f822fcf7 KH |
23 | This file contains support functions for creating rtl expressions |
24 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
25 | |
26 | The patterns of the insns are created by machine-dependent | |
27 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
28 | the machine description. These routines make the individual rtx's |
29 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
30 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
31 | dependent is the kind of rtx's they make and what arguments they |
32 | use. */ | |
23b2ce53 RS |
33 | |
34 | #include "config.h" | |
670ee920 | 35 | #include "system.h" |
4977bab6 | 36 | #include "coretypes.h" |
4d0cdd0c | 37 | #include "memmodel.h" |
c7131fb2 | 38 | #include "backend.h" |
957060b5 | 39 | #include "target.h" |
23b2ce53 | 40 | #include "rtl.h" |
957060b5 | 41 | #include "tree.h" |
c7131fb2 | 42 | #include "df.h" |
957060b5 AM |
43 | #include "tm_p.h" |
44 | #include "stringpool.h" | |
957060b5 AM |
45 | #include "insn-config.h" |
46 | #include "regs.h" | |
47 | #include "emit-rtl.h" | |
48 | #include "recog.h" | |
c7131fb2 | 49 | #include "diagnostic-core.h" |
40e23961 | 50 | #include "alias.h" |
40e23961 | 51 | #include "fold-const.h" |
d8a2d370 | 52 | #include "varasm.h" |
60393bbc | 53 | #include "cfgrtl.h" |
60393bbc | 54 | #include "tree-eh.h" |
36566b39 | 55 | #include "explow.h" |
23b2ce53 | 56 | #include "expr.h" |
9b2b7279 | 57 | #include "builtins.h" |
9021b8ec | 58 | #include "rtl-iter.h" |
1f9ceff1 | 59 | #include "stor-layout.h" |
ecf835e9 | 60 | #include "opts.h" |
5fa396ad | 61 | #include "predict.h" |
3877c560 | 62 | #include "rtx-vector-builder.h" |
fa70c221 RB |
63 | #include "gimple.h" |
64 | #include "gimple-ssa.h" | |
65 | #include "gimplify.h" | |
ca695ac9 | 66 | |
5fb0e246 RS |
67 | struct target_rtl default_target_rtl; |
68 | #if SWITCHABLE_TARGET | |
69 | struct target_rtl *this_target_rtl = &default_target_rtl; | |
70 | #endif | |
71 | ||
72 | #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx) | |
73 | ||
1d445e9e ILT |
74 | /* Commonly used modes. */ |
75 | ||
501623d4 RS |
76 | scalar_int_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
77 | scalar_int_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
78 | scalar_int_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ | |
1d445e9e | 79 | |
bd60bab2 JH |
80 | /* Datastructures maintained for currently processed function in RTL form. */ |
81 | ||
3e029763 | 82 | struct rtl_data x_rtl; |
bd60bab2 JH |
83 | |
84 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
b8698a0f | 85 | Allocated in parallel with regno_pointer_align. |
bd60bab2 JH |
86 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal |
87 | with length attribute nested in top level structures. */ | |
88 | ||
89 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
90 | |
91 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
92 | in the entire compilation a unique label number. */ | |
93 | ||
044b4de3 | 94 | static GTY(()) int label_num = 1; |
23b2ce53 | 95 | |
23b2ce53 RS |
96 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
97 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
e7c82a99 JJ |
98 | record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX |
99 | is set only for MODE_INT and MODE_VECTOR_INT modes. */ | |
23b2ce53 | 100 | |
e7c82a99 | 101 | rtx const_tiny_rtx[4][(int) MAX_MACHINE_MODE]; |
23b2ce53 | 102 | |
68d75312 JC |
103 | rtx const_true_rtx; |
104 | ||
23b2ce53 RS |
105 | REAL_VALUE_TYPE dconst0; |
106 | REAL_VALUE_TYPE dconst1; | |
107 | REAL_VALUE_TYPE dconst2; | |
108 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 109 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 110 | |
325217ed CF |
111 | /* Record fixed-point constant 0 and 1. */ |
112 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
113 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
114 | ||
23b2ce53 RS |
115 | /* We make one copy of (const_int C) where C is in |
116 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
117 | to save space during the compilation and simplify comparisons of | |
118 | integers. */ | |
119 | ||
5da077de | 120 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 121 | |
ca4adc91 RS |
122 | /* Standard pieces of rtx, to be substituted directly into things. */ |
123 | rtx pc_rtx; | |
124 | rtx ret_rtx; | |
125 | rtx simple_return_rtx; | |
ca4adc91 | 126 | |
1476d1bd MM |
127 | /* Marker used for denoting an INSN, which should never be accessed (i.e., |
128 | this pointer should normally never be dereferenced), but is required to be | |
129 | distinct from NULL_RTX. Currently used by peephole2 pass. */ | |
130 | rtx_insn *invalid_insn_rtx; | |
131 | ||
c13e8210 MM |
132 | /* A hash table storing CONST_INTs whose absolute value is greater |
133 | than MAX_SAVED_CONST_INT. */ | |
134 | ||
6c907cff | 135 | struct const_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
136 | { |
137 | typedef HOST_WIDE_INT compare_type; | |
138 | ||
139 | static hashval_t hash (rtx i); | |
140 | static bool equal (rtx i, HOST_WIDE_INT h); | |
141 | }; | |
c13e8210 | 142 | |
aebf76a2 TS |
143 | static GTY ((cache)) hash_table<const_int_hasher> *const_int_htab; |
144 | ||
6c907cff | 145 | struct const_wide_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
146 | { |
147 | static hashval_t hash (rtx x); | |
148 | static bool equal (rtx x, rtx y); | |
149 | }; | |
150 | ||
151 | static GTY ((cache)) hash_table<const_wide_int_hasher> *const_wide_int_htab; | |
807e902e | 152 | |
0c12fc9b RS |
153 | struct const_poly_int_hasher : ggc_cache_ptr_hash<rtx_def> |
154 | { | |
155 | typedef std::pair<machine_mode, poly_wide_int_ref> compare_type; | |
156 | ||
157 | static hashval_t hash (rtx x); | |
158 | static bool equal (rtx x, const compare_type &y); | |
159 | }; | |
160 | ||
161 | static GTY ((cache)) hash_table<const_poly_int_hasher> *const_poly_int_htab; | |
162 | ||
a560d4d4 | 163 | /* A hash table storing register attribute structures. */ |
6c907cff | 164 | struct reg_attr_hasher : ggc_cache_ptr_hash<reg_attrs> |
aebf76a2 TS |
165 | { |
166 | static hashval_t hash (reg_attrs *x); | |
167 | static bool equal (reg_attrs *a, reg_attrs *b); | |
168 | }; | |
169 | ||
170 | static GTY ((cache)) hash_table<reg_attr_hasher> *reg_attrs_htab; | |
a560d4d4 | 171 | |
5692c7bc | 172 | /* A hash table storing all CONST_DOUBLEs. */ |
6c907cff | 173 | struct const_double_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
174 | { |
175 | static hashval_t hash (rtx x); | |
176 | static bool equal (rtx x, rtx y); | |
177 | }; | |
178 | ||
179 | static GTY ((cache)) hash_table<const_double_hasher> *const_double_htab; | |
5692c7bc | 180 | |
091a3ac7 | 181 | /* A hash table storing all CONST_FIXEDs. */ |
6c907cff | 182 | struct const_fixed_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
183 | { |
184 | static hashval_t hash (rtx x); | |
185 | static bool equal (rtx x, rtx y); | |
186 | }; | |
187 | ||
188 | static GTY ((cache)) hash_table<const_fixed_hasher> *const_fixed_htab; | |
091a3ac7 | 189 | |
3e029763 | 190 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) |
b5b8b0ac | 191 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 | 192 | #define first_label_num (crtl->emit.x_first_label_num) |
23b2ce53 | 193 | |
5eb2a9f2 | 194 | static void set_used_decls (tree); |
502b8322 | 195 | static void mark_label_nuses (rtx); |
807e902e | 196 | #if TARGET_SUPPORTS_WIDE_INT |
807e902e KZ |
197 | static rtx lookup_const_wide_int (rtx); |
198 | #endif | |
502b8322 | 199 | static rtx lookup_const_double (rtx); |
091a3ac7 | 200 | static rtx lookup_const_fixed (rtx); |
ef4bddc2 | 201 | static rtx gen_const_vector (machine_mode, int); |
32b32b16 | 202 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 203 | |
5fa396ad JH |
204 | /* Probability of the conditional branch currently proceeded by try_split. */ |
205 | profile_probability split_branch_probability; | |
ca695ac9 | 206 | \f |
c13e8210 MM |
207 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
208 | ||
aebf76a2 TS |
209 | hashval_t |
210 | const_int_hasher::hash (rtx x) | |
c13e8210 | 211 | { |
aebf76a2 | 212 | return (hashval_t) INTVAL (x); |
c13e8210 MM |
213 | } |
214 | ||
cc2902df | 215 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
216 | CONST_INT) is the same as that given by Y (which is really a |
217 | HOST_WIDE_INT *). */ | |
218 | ||
aebf76a2 TS |
219 | bool |
220 | const_int_hasher::equal (rtx x, HOST_WIDE_INT y) | |
c13e8210 | 221 | { |
aebf76a2 | 222 | return (INTVAL (x) == y); |
5692c7bc ZW |
223 | } |
224 | ||
807e902e KZ |
225 | #if TARGET_SUPPORTS_WIDE_INT |
226 | /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */ | |
227 | ||
aebf76a2 TS |
228 | hashval_t |
229 | const_wide_int_hasher::hash (rtx x) | |
807e902e KZ |
230 | { |
231 | int i; | |
d7ca26e4 | 232 | unsigned HOST_WIDE_INT hash = 0; |
aebf76a2 | 233 | const_rtx xr = x; |
807e902e KZ |
234 | |
235 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
236 | hash += CONST_WIDE_INT_ELT (xr, i); | |
237 | ||
238 | return (hashval_t) hash; | |
239 | } | |
240 | ||
241 | /* Returns nonzero if the value represented by X (which is really a | |
242 | CONST_WIDE_INT) is the same as that given by Y (which is really a | |
243 | CONST_WIDE_INT). */ | |
244 | ||
aebf76a2 TS |
245 | bool |
246 | const_wide_int_hasher::equal (rtx x, rtx y) | |
807e902e KZ |
247 | { |
248 | int i; | |
aebf76a2 TS |
249 | const_rtx xr = x; |
250 | const_rtx yr = y; | |
807e902e | 251 | if (CONST_WIDE_INT_NUNITS (xr) != CONST_WIDE_INT_NUNITS (yr)) |
aebf76a2 | 252 | return false; |
807e902e KZ |
253 | |
254 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
255 | if (CONST_WIDE_INT_ELT (xr, i) != CONST_WIDE_INT_ELT (yr, i)) | |
aebf76a2 | 256 | return false; |
807e902e | 257 | |
aebf76a2 | 258 | return true; |
807e902e KZ |
259 | } |
260 | #endif | |
261 | ||
0c12fc9b RS |
262 | /* Returns a hash code for CONST_POLY_INT X. */ |
263 | ||
264 | hashval_t | |
265 | const_poly_int_hasher::hash (rtx x) | |
266 | { | |
267 | inchash::hash h; | |
268 | h.add_int (GET_MODE (x)); | |
269 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
270 | h.add_wide_int (CONST_POLY_INT_COEFFS (x)[i]); | |
271 | return h.end (); | |
272 | } | |
273 | ||
274 | /* Returns nonzero if CONST_POLY_INT X is an rtx representation of Y. */ | |
275 | ||
276 | bool | |
277 | const_poly_int_hasher::equal (rtx x, const compare_type &y) | |
278 | { | |
279 | if (GET_MODE (x) != y.first) | |
280 | return false; | |
281 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
282 | if (CONST_POLY_INT_COEFFS (x)[i] != y.second.coeffs[i]) | |
283 | return false; | |
284 | return true; | |
285 | } | |
286 | ||
5692c7bc | 287 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ |
aebf76a2 TS |
288 | hashval_t |
289 | const_double_hasher::hash (rtx x) | |
5692c7bc | 290 | { |
aebf76a2 | 291 | const_rtx const value = x; |
46b33600 | 292 | hashval_t h; |
5692c7bc | 293 | |
807e902e | 294 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (value) == VOIDmode) |
46b33600 RH |
295 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); |
296 | else | |
fe352c29 | 297 | { |
15c812e3 | 298 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
299 | /* MODE is used in the comparison, so it should be in the hash. */ |
300 | h ^= GET_MODE (value); | |
301 | } | |
5692c7bc ZW |
302 | return h; |
303 | } | |
304 | ||
cc2902df | 305 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc | 306 | is the same as that represented by Y (really a ...) */ |
aebf76a2 TS |
307 | bool |
308 | const_double_hasher::equal (rtx x, rtx y) | |
5692c7bc | 309 | { |
aebf76a2 | 310 | const_rtx const a = x, b = y; |
5692c7bc ZW |
311 | |
312 | if (GET_MODE (a) != GET_MODE (b)) | |
313 | return 0; | |
807e902e | 314 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (a) == VOIDmode) |
8580f7a0 RH |
315 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) |
316 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
317 | else | |
318 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
319 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
320 | } |
321 | ||
091a3ac7 CF |
322 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
323 | ||
aebf76a2 TS |
324 | hashval_t |
325 | const_fixed_hasher::hash (rtx x) | |
091a3ac7 | 326 | { |
aebf76a2 | 327 | const_rtx const value = x; |
091a3ac7 CF |
328 | hashval_t h; |
329 | ||
330 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
331 | /* MODE is used in the comparison, so it should be in the hash. */ | |
332 | h ^= GET_MODE (value); | |
333 | return h; | |
334 | } | |
335 | ||
aebf76a2 TS |
336 | /* Returns nonzero if the value represented by X is the same as that |
337 | represented by Y. */ | |
091a3ac7 | 338 | |
aebf76a2 TS |
339 | bool |
340 | const_fixed_hasher::equal (rtx x, rtx y) | |
091a3ac7 | 341 | { |
aebf76a2 | 342 | const_rtx const a = x, b = y; |
091a3ac7 CF |
343 | |
344 | if (GET_MODE (a) != GET_MODE (b)) | |
345 | return 0; | |
346 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
347 | } | |
348 | ||
f12144dd | 349 | /* Return true if the given memory attributes are equal. */ |
c13e8210 | 350 | |
96b3c03f | 351 | bool |
99b1c316 | 352 | mem_attrs_eq_p (const class mem_attrs *p, const class mem_attrs *q) |
c13e8210 | 353 | { |
96b3c03f RB |
354 | if (p == q) |
355 | return true; | |
356 | if (!p || !q) | |
357 | return false; | |
754c3d5d RS |
358 | return (p->alias == q->alias |
359 | && p->offset_known_p == q->offset_known_p | |
d05d7551 | 360 | && (!p->offset_known_p || known_eq (p->offset, q->offset)) |
754c3d5d | 361 | && p->size_known_p == q->size_known_p |
d05d7551 | 362 | && (!p->size_known_p || known_eq (p->size, q->size)) |
754c3d5d | 363 | && p->align == q->align |
09e881c9 | 364 | && p->addrspace == q->addrspace |
78b76d08 SB |
365 | && (p->expr == q->expr |
366 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
367 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
368 | } |
369 | ||
f12144dd | 370 | /* Set MEM's memory attributes so that they are the same as ATTRS. */ |
10b76d73 | 371 | |
f12144dd RS |
372 | static void |
373 | set_mem_attrs (rtx mem, mem_attrs *attrs) | |
374 | { | |
f12144dd RS |
375 | /* If everything is the default, we can just clear the attributes. */ |
376 | if (mem_attrs_eq_p (attrs, mode_mem_attrs[(int) GET_MODE (mem)])) | |
377 | { | |
378 | MEM_ATTRS (mem) = 0; | |
379 | return; | |
380 | } | |
173b24b9 | 381 | |
84053e02 RB |
382 | if (!MEM_ATTRS (mem) |
383 | || !mem_attrs_eq_p (attrs, MEM_ATTRS (mem))) | |
173b24b9 | 384 | { |
766090c2 | 385 | MEM_ATTRS (mem) = ggc_alloc<mem_attrs> (); |
84053e02 | 386 | memcpy (MEM_ATTRS (mem), attrs, sizeof (mem_attrs)); |
173b24b9 | 387 | } |
c13e8210 MM |
388 | } |
389 | ||
a560d4d4 JH |
390 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
391 | ||
aebf76a2 TS |
392 | hashval_t |
393 | reg_attr_hasher::hash (reg_attrs *x) | |
a560d4d4 | 394 | { |
aebf76a2 | 395 | const reg_attrs *const p = x; |
a560d4d4 | 396 | |
84bc717b RS |
397 | inchash::hash h; |
398 | h.add_ptr (p->decl); | |
399 | h.add_poly_hwi (p->offset); | |
400 | return h.end (); | |
a560d4d4 JH |
401 | } |
402 | ||
aebf76a2 TS |
403 | /* Returns nonzero if the value represented by X is the same as that given by |
404 | Y. */ | |
a560d4d4 | 405 | |
aebf76a2 TS |
406 | bool |
407 | reg_attr_hasher::equal (reg_attrs *x, reg_attrs *y) | |
a560d4d4 | 408 | { |
aebf76a2 TS |
409 | const reg_attrs *const p = x; |
410 | const reg_attrs *const q = y; | |
a560d4d4 | 411 | |
84bc717b | 412 | return (p->decl == q->decl && known_eq (p->offset, q->offset)); |
a560d4d4 JH |
413 | } |
414 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
415 | one identical to it is not already in the table. We are doing this for | |
416 | MEM of mode MODE. */ | |
417 | ||
418 | static reg_attrs * | |
84bc717b | 419 | get_reg_attrs (tree decl, poly_int64 offset) |
a560d4d4 JH |
420 | { |
421 | reg_attrs attrs; | |
a560d4d4 JH |
422 | |
423 | /* If everything is the default, we can just return zero. */ | |
84bc717b | 424 | if (decl == 0 && known_eq (offset, 0)) |
a560d4d4 JH |
425 | return 0; |
426 | ||
427 | attrs.decl = decl; | |
428 | attrs.offset = offset; | |
429 | ||
aebf76a2 | 430 | reg_attrs **slot = reg_attrs_htab->find_slot (&attrs, INSERT); |
a560d4d4 JH |
431 | if (*slot == 0) |
432 | { | |
766090c2 | 433 | *slot = ggc_alloc<reg_attrs> (); |
a560d4d4 JH |
434 | memcpy (*slot, &attrs, sizeof (reg_attrs)); |
435 | } | |
436 | ||
aebf76a2 | 437 | return *slot; |
a560d4d4 JH |
438 | } |
439 | ||
6fb5fa3c DB |
440 | |
441 | #if !HAVE_blockage | |
adddc347 HPN |
442 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule, |
443 | and to block register equivalences to be seen across this insn. */ | |
6fb5fa3c DB |
444 | |
445 | rtx | |
446 | gen_blockage (void) | |
447 | { | |
448 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
449 | MEM_VOLATILE_P (x) = true; | |
450 | return x; | |
451 | } | |
452 | #endif | |
453 | ||
454 | ||
8deccbb7 RS |
455 | /* Set the mode and register number of X to MODE and REGNO. */ |
456 | ||
457 | void | |
458 | set_mode_and_regno (rtx x, machine_mode mode, unsigned int regno) | |
459 | { | |
9188b286 | 460 | unsigned int nregs = (HARD_REGISTER_NUM_P (regno) |
ad474626 | 461 | ? hard_regno_nregs (regno, mode) |
9188b286 | 462 | : 1); |
8deccbb7 | 463 | PUT_MODE_RAW (x, mode); |
9188b286 | 464 | set_regno_raw (x, regno, nregs); |
8deccbb7 RS |
465 | } |
466 | ||
20fa157e IL |
467 | /* Initialize a fresh REG rtx with mode MODE and register REGNO. */ |
468 | ||
469 | rtx | |
470 | init_raw_REG (rtx x, machine_mode mode, unsigned int regno) | |
471 | { | |
472 | set_mode_and_regno (x, mode, regno); | |
473 | REG_ATTRS (x) = NULL; | |
474 | ORIGINAL_REGNO (x) = regno; | |
475 | return x; | |
476 | } | |
477 | ||
08394eef BS |
478 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
479 | don't attempt to share with the various global pieces of rtl (such as | |
480 | frame_pointer_rtx). */ | |
481 | ||
482 | rtx | |
8deccbb7 | 483 | gen_raw_REG (machine_mode mode, unsigned int regno) |
08394eef | 484 | { |
84c2ad23 | 485 | rtx x = rtx_alloc (REG MEM_STAT_INFO); |
20fa157e | 486 | init_raw_REG (x, mode, regno); |
08394eef BS |
487 | return x; |
488 | } | |
489 | ||
c5c76735 JL |
490 | /* There are some RTL codes that require special attention; the generation |
491 | functions do the raw handling. If you add to this list, modify | |
492 | special_rtx in gengenrtl.c as well. */ | |
493 | ||
38e60c55 | 494 | rtx_expr_list * |
ef4bddc2 | 495 | gen_rtx_EXPR_LIST (machine_mode mode, rtx expr, rtx expr_list) |
38e60c55 DM |
496 | { |
497 | return as_a <rtx_expr_list *> (gen_rtx_fmt_ee (EXPR_LIST, mode, expr, | |
498 | expr_list)); | |
499 | } | |
500 | ||
a756c6be | 501 | rtx_insn_list * |
ef4bddc2 | 502 | gen_rtx_INSN_LIST (machine_mode mode, rtx insn, rtx insn_list) |
a756c6be DM |
503 | { |
504 | return as_a <rtx_insn_list *> (gen_rtx_fmt_ue (INSN_LIST, mode, insn, | |
505 | insn_list)); | |
506 | } | |
507 | ||
d6e1e8b8 | 508 | rtx_insn * |
ef4bddc2 | 509 | gen_rtx_INSN (machine_mode mode, rtx_insn *prev_insn, rtx_insn *next_insn, |
d6e1e8b8 DM |
510 | basic_block bb, rtx pattern, int location, int code, |
511 | rtx reg_notes) | |
512 | { | |
513 | return as_a <rtx_insn *> (gen_rtx_fmt_uuBeiie (INSN, mode, | |
514 | prev_insn, next_insn, | |
515 | bb, pattern, location, code, | |
516 | reg_notes)); | |
517 | } | |
518 | ||
3b80f6ca | 519 | rtx |
ef4bddc2 | 520 | gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca RH |
521 | { |
522 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) | |
5da077de | 523 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
524 | |
525 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
526 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
527 | return const_true_rtx; | |
528 | #endif | |
529 | ||
c13e8210 | 530 | /* Look up the CONST_INT in the hash table. */ |
aebf76a2 TS |
531 | rtx *slot = const_int_htab->find_slot_with_hash (arg, (hashval_t) arg, |
532 | INSERT); | |
29105cea | 533 | if (*slot == 0) |
1f8f4a0b | 534 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 | 535 | |
aebf76a2 | 536 | return *slot; |
3b80f6ca RH |
537 | } |
538 | ||
2496c7bd | 539 | rtx |
0c12fc9b | 540 | gen_int_mode (poly_int64 c, machine_mode mode) |
2496c7bd | 541 | { |
0c12fc9b RS |
542 | c = trunc_int_for_mode (c, mode); |
543 | if (c.is_constant ()) | |
544 | return GEN_INT (c.coeffs[0]); | |
545 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
546 | return immed_wide_int_const (poly_wide_int::from (c, prec, SIGNED), mode); | |
2496c7bd LB |
547 | } |
548 | ||
5692c7bc ZW |
549 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
550 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
551 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
552 | ||
553 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
554 | hash table. If so, return its counterpart; otherwise add it | |
555 | to the hash table and return it. */ | |
556 | static rtx | |
502b8322 | 557 | lookup_const_double (rtx real) |
5692c7bc | 558 | { |
aebf76a2 | 559 | rtx *slot = const_double_htab->find_slot (real, INSERT); |
5692c7bc ZW |
560 | if (*slot == 0) |
561 | *slot = real; | |
562 | ||
aebf76a2 | 563 | return *slot; |
5692c7bc | 564 | } |
29105cea | 565 | |
5692c7bc ZW |
566 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
567 | VALUE in mode MODE. */ | |
0133b7d9 | 568 | rtx |
ef4bddc2 | 569 | const_double_from_real_value (REAL_VALUE_TYPE value, machine_mode mode) |
0133b7d9 | 570 | { |
5692c7bc ZW |
571 | rtx real = rtx_alloc (CONST_DOUBLE); |
572 | PUT_MODE (real, mode); | |
573 | ||
9e254451 | 574 | real->u.rv = value; |
5692c7bc ZW |
575 | |
576 | return lookup_const_double (real); | |
577 | } | |
578 | ||
091a3ac7 CF |
579 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
580 | hash table. If so, return its counterpart; otherwise add it | |
581 | to the hash table and return it. */ | |
582 | ||
583 | static rtx | |
584 | lookup_const_fixed (rtx fixed) | |
585 | { | |
aebf76a2 | 586 | rtx *slot = const_fixed_htab->find_slot (fixed, INSERT); |
091a3ac7 CF |
587 | if (*slot == 0) |
588 | *slot = fixed; | |
589 | ||
aebf76a2 | 590 | return *slot; |
091a3ac7 CF |
591 | } |
592 | ||
593 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
594 | VALUE in mode MODE. */ | |
595 | ||
596 | rtx | |
ef4bddc2 | 597 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, machine_mode mode) |
091a3ac7 CF |
598 | { |
599 | rtx fixed = rtx_alloc (CONST_FIXED); | |
600 | PUT_MODE (fixed, mode); | |
601 | ||
602 | fixed->u.fv = value; | |
603 | ||
604 | return lookup_const_fixed (fixed); | |
605 | } | |
606 | ||
807e902e | 607 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
3e93ff81 AS |
608 | /* Constructs double_int from rtx CST. */ |
609 | ||
610 | double_int | |
611 | rtx_to_double_int (const_rtx cst) | |
612 | { | |
613 | double_int r; | |
614 | ||
615 | if (CONST_INT_P (cst)) | |
27bcd47c | 616 | r = double_int::from_shwi (INTVAL (cst)); |
48175537 | 617 | else if (CONST_DOUBLE_AS_INT_P (cst)) |
3e93ff81 AS |
618 | { |
619 | r.low = CONST_DOUBLE_LOW (cst); | |
620 | r.high = CONST_DOUBLE_HIGH (cst); | |
621 | } | |
622 | else | |
623 | gcc_unreachable (); | |
624 | ||
625 | return r; | |
626 | } | |
807e902e | 627 | #endif |
3e93ff81 | 628 | |
807e902e KZ |
629 | #if TARGET_SUPPORTS_WIDE_INT |
630 | /* Determine whether CONST_WIDE_INT WINT already exists in the hash table. | |
631 | If so, return its counterpart; otherwise add it to the hash table and | |
632 | return it. */ | |
3e93ff81 | 633 | |
807e902e KZ |
634 | static rtx |
635 | lookup_const_wide_int (rtx wint) | |
636 | { | |
aebf76a2 | 637 | rtx *slot = const_wide_int_htab->find_slot (wint, INSERT); |
807e902e KZ |
638 | if (*slot == 0) |
639 | *slot = wint; | |
640 | ||
aebf76a2 | 641 | return *slot; |
807e902e KZ |
642 | } |
643 | #endif | |
644 | ||
645 | /* Return an rtx constant for V, given that the constant has mode MODE. | |
646 | The returned rtx will be a CONST_INT if V fits, otherwise it will be | |
647 | a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT | |
648 | (if TARGET_SUPPORTS_WIDE_INT). */ | |
54fb1ae0 | 649 | |
0c12fc9b RS |
650 | static rtx |
651 | immed_wide_int_const_1 (const wide_int_ref &v, machine_mode mode) | |
54fb1ae0 | 652 | { |
807e902e | 653 | unsigned int len = v.get_len (); |
db61b7f9 RS |
654 | /* Not scalar_int_mode because we also allow pointer bound modes. */ |
655 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
807e902e KZ |
656 | |
657 | /* Allow truncation but not extension since we do not know if the | |
658 | number is signed or unsigned. */ | |
659 | gcc_assert (prec <= v.get_precision ()); | |
660 | ||
661 | if (len < 2 || prec <= HOST_BITS_PER_WIDE_INT) | |
662 | return gen_int_mode (v.elt (0), mode); | |
663 | ||
664 | #if TARGET_SUPPORTS_WIDE_INT | |
665 | { | |
666 | unsigned int i; | |
667 | rtx value; | |
668 | unsigned int blocks_needed | |
669 | = (prec + HOST_BITS_PER_WIDE_INT - 1) / HOST_BITS_PER_WIDE_INT; | |
670 | ||
671 | if (len > blocks_needed) | |
672 | len = blocks_needed; | |
673 | ||
674 | value = const_wide_int_alloc (len); | |
675 | ||
676 | /* It is so tempting to just put the mode in here. Must control | |
677 | myself ... */ | |
678 | PUT_MODE (value, VOIDmode); | |
679 | CWI_PUT_NUM_ELEM (value, len); | |
680 | ||
681 | for (i = 0; i < len; i++) | |
682 | CONST_WIDE_INT_ELT (value, i) = v.elt (i); | |
683 | ||
684 | return lookup_const_wide_int (value); | |
685 | } | |
686 | #else | |
687 | return immed_double_const (v.elt (0), v.elt (1), mode); | |
688 | #endif | |
54fb1ae0 AS |
689 | } |
690 | ||
807e902e | 691 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
5692c7bc ZW |
692 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
693 | of ints: I0 is the low-order word and I1 is the high-order word. | |
49ab6098 | 694 | For values that are larger than HOST_BITS_PER_DOUBLE_INT, the |
929e10f4 MS |
695 | implied upper bits are copies of the high bit of i1. The value |
696 | itself is neither signed nor unsigned. Do not use this routine for | |
697 | non-integer modes; convert to REAL_VALUE_TYPE and use | |
555affd7 | 698 | const_double_from_real_value. */ |
5692c7bc ZW |
699 | |
700 | rtx | |
ef4bddc2 | 701 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, machine_mode mode) |
5692c7bc ZW |
702 | { |
703 | rtx value; | |
704 | unsigned int i; | |
705 | ||
65acccdd | 706 | /* There are the following cases (note that there are no modes with |
49ab6098 | 707 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT): |
65acccdd ZD |
708 | |
709 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
710 | gen_int_mode. | |
929e10f4 MS |
711 | 2) If the value of the integer fits into HOST_WIDE_INT anyway |
712 | (i.e., i1 consists only from copies of the sign bit, and sign | |
713 | of i0 and i1 are the same), then we return a CONST_INT for i0. | |
65acccdd | 714 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ |
db61b7f9 RS |
715 | scalar_mode smode; |
716 | if (is_a <scalar_mode> (mode, &smode) | |
717 | && GET_MODE_BITSIZE (smode) <= HOST_BITS_PER_WIDE_INT) | |
718 | return gen_int_mode (i0, mode); | |
5692c7bc ZW |
719 | |
720 | /* If this integer fits in one word, return a CONST_INT. */ | |
721 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
722 | return GEN_INT (i0); | |
723 | ||
724 | /* We use VOIDmode for integers. */ | |
725 | value = rtx_alloc (CONST_DOUBLE); | |
726 | PUT_MODE (value, VOIDmode); | |
727 | ||
728 | CONST_DOUBLE_LOW (value) = i0; | |
729 | CONST_DOUBLE_HIGH (value) = i1; | |
730 | ||
731 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
732 | XWINT (value, i) = 0; | |
733 | ||
734 | return lookup_const_double (value); | |
0133b7d9 | 735 | } |
807e902e | 736 | #endif |
0133b7d9 | 737 | |
0c12fc9b RS |
738 | /* Return an rtx representation of C in mode MODE. */ |
739 | ||
740 | rtx | |
741 | immed_wide_int_const (const poly_wide_int_ref &c, machine_mode mode) | |
742 | { | |
743 | if (c.is_constant ()) | |
744 | return immed_wide_int_const_1 (c.coeffs[0], mode); | |
745 | ||
746 | /* Not scalar_int_mode because we also allow pointer bound modes. */ | |
747 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
748 | ||
749 | /* Allow truncation but not extension since we do not know if the | |
750 | number is signed or unsigned. */ | |
751 | gcc_assert (prec <= c.coeffs[0].get_precision ()); | |
752 | poly_wide_int newc = poly_wide_int::from (c, prec, SIGNED); | |
753 | ||
754 | /* See whether we already have an rtx for this constant. */ | |
755 | inchash::hash h; | |
756 | h.add_int (mode); | |
757 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
758 | h.add_wide_int (newc.coeffs[i]); | |
759 | const_poly_int_hasher::compare_type typed_value (mode, newc); | |
760 | rtx *slot = const_poly_int_htab->find_slot_with_hash (typed_value, | |
761 | h.end (), INSERT); | |
762 | rtx x = *slot; | |
763 | if (x) | |
764 | return x; | |
765 | ||
766 | /* Create a new rtx. There's a choice to be made here between installing | |
767 | the actual mode of the rtx or leaving it as VOIDmode (for consistency | |
768 | with CONST_INT). In practice the handling of the codes is different | |
769 | enough that we get no benefit from using VOIDmode, and various places | |
770 | assume that VOIDmode implies CONST_INT. Using the real mode seems like | |
771 | the right long-term direction anyway. */ | |
772 | typedef trailing_wide_ints<NUM_POLY_INT_COEFFS> twi; | |
773 | size_t extra_size = twi::extra_size (prec); | |
774 | x = rtx_alloc_v (CONST_POLY_INT, | |
775 | sizeof (struct const_poly_int_def) + extra_size); | |
776 | PUT_MODE (x, mode); | |
777 | CONST_POLY_INT_COEFFS (x).set_precision (prec); | |
778 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
779 | CONST_POLY_INT_COEFFS (x)[i] = newc.coeffs[i]; | |
780 | ||
781 | *slot = x; | |
782 | return x; | |
783 | } | |
784 | ||
3b80f6ca | 785 | rtx |
ef4bddc2 | 786 | gen_rtx_REG (machine_mode mode, unsigned int regno) |
3b80f6ca RH |
787 | { |
788 | /* In case the MD file explicitly references the frame pointer, have | |
789 | all such references point to the same frame pointer. This is | |
790 | used during frame pointer elimination to distinguish the explicit | |
791 | references to these registers from pseudos that happened to be | |
792 | assigned to them. | |
793 | ||
794 | If we have eliminated the frame pointer or arg pointer, we will | |
795 | be using it as a normal register, for example as a spill | |
796 | register. In such cases, we might be accessing it in a mode that | |
797 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
798 | ||
799 | Also don't do this when we are making new REGs in reload, since | |
800 | we don't want to get confused with the real pointers. */ | |
801 | ||
55a2c322 | 802 | if (mode == Pmode && !reload_in_progress && !lra_in_progress) |
3b80f6ca | 803 | { |
e10c79fe LB |
804 | if (regno == FRAME_POINTER_REGNUM |
805 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca | 806 | return frame_pointer_rtx; |
c3e08036 TS |
807 | |
808 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER | |
809 | && regno == HARD_FRAME_POINTER_REGNUM | |
e10c79fe | 810 | && (!reload_completed || frame_pointer_needed)) |
3b80f6ca | 811 | return hard_frame_pointer_rtx; |
3f393fc6 TS |
812 | #if !HARD_FRAME_POINTER_IS_ARG_POINTER |
813 | if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
814 | && regno == ARG_POINTER_REGNUM) | |
3b80f6ca RH |
815 | return arg_pointer_rtx; |
816 | #endif | |
817 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 818 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
819 | return return_address_pointer_rtx; |
820 | #endif | |
fc555370 | 821 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
bf9412cd | 822 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM |
2d67bd7b | 823 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 824 | return pic_offset_table_rtx; |
bcb33994 | 825 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
826 | return stack_pointer_rtx; |
827 | } | |
828 | ||
006a94b0 | 829 | #if 0 |
6cde4876 | 830 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
831 | an existing entry in that table to avoid useless generation of RTL. |
832 | ||
833 | This code is disabled for now until we can fix the various backends | |
834 | which depend on having non-shared hard registers in some cases. Long | |
835 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
836 | on the amount of useless RTL that gets generated. |
837 | ||
838 | We'll also need to fix some code that runs after reload that wants to | |
839 | set ORIGINAL_REGNO. */ | |
840 | ||
6cde4876 JL |
841 | if (cfun |
842 | && cfun->emit | |
843 | && regno_reg_rtx | |
844 | && regno < FIRST_PSEUDO_REGISTER | |
845 | && reg_raw_mode[regno] == mode) | |
846 | return regno_reg_rtx[regno]; | |
006a94b0 | 847 | #endif |
6cde4876 | 848 | |
08394eef | 849 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
850 | } |
851 | ||
41472af8 | 852 | rtx |
ef4bddc2 | 853 | gen_rtx_MEM (machine_mode mode, rtx addr) |
41472af8 MM |
854 | { |
855 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
856 | ||
857 | /* This field is not cleared by the mere allocation of the rtx, so | |
858 | we clear it here. */ | |
173b24b9 | 859 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
860 | |
861 | return rt; | |
862 | } | |
ddef6bc7 | 863 | |
542a8afa RH |
864 | /* Generate a memory referring to non-trapping constant memory. */ |
865 | ||
866 | rtx | |
ef4bddc2 | 867 | gen_const_mem (machine_mode mode, rtx addr) |
542a8afa RH |
868 | { |
869 | rtx mem = gen_rtx_MEM (mode, addr); | |
870 | MEM_READONLY_P (mem) = 1; | |
871 | MEM_NOTRAP_P (mem) = 1; | |
872 | return mem; | |
873 | } | |
874 | ||
bf877a76 R |
875 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
876 | save areas. */ | |
877 | ||
878 | rtx | |
ef4bddc2 | 879 | gen_frame_mem (machine_mode mode, rtx addr) |
bf877a76 R |
880 | { |
881 | rtx mem = gen_rtx_MEM (mode, addr); | |
882 | MEM_NOTRAP_P (mem) = 1; | |
883 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
884 | return mem; | |
885 | } | |
886 | ||
887 | /* Generate a MEM referring to a temporary use of the stack, not part | |
888 | of the fixed stack frame. For example, something which is pushed | |
889 | by a target splitter. */ | |
890 | rtx | |
ef4bddc2 | 891 | gen_tmp_stack_mem (machine_mode mode, rtx addr) |
bf877a76 R |
892 | { |
893 | rtx mem = gen_rtx_MEM (mode, addr); | |
894 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 895 | if (!cfun->calls_alloca) |
bf877a76 R |
896 | set_mem_alias_set (mem, get_frame_alias_set ()); |
897 | return mem; | |
898 | } | |
899 | ||
beb72684 RH |
900 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
901 | this construct would be valid, and false otherwise. */ | |
902 | ||
903 | bool | |
ef4bddc2 | 904 | validate_subreg (machine_mode omode, machine_mode imode, |
91914e56 | 905 | const_rtx reg, poly_uint64 offset) |
ddef6bc7 | 906 | { |
fad2288b RS |
907 | poly_uint64 isize = GET_MODE_SIZE (imode); |
908 | poly_uint64 osize = GET_MODE_SIZE (omode); | |
909 | ||
910 | /* The sizes must be ordered, so that we know whether the subreg | |
911 | is partial, paradoxical or complete. */ | |
912 | if (!ordered_p (isize, osize)) | |
913 | return false; | |
beb72684 RH |
914 | |
915 | /* All subregs must be aligned. */ | |
91914e56 | 916 | if (!multiple_p (offset, osize)) |
beb72684 RH |
917 | return false; |
918 | ||
919 | /* The subreg offset cannot be outside the inner object. */ | |
91914e56 | 920 | if (maybe_ge (offset, isize)) |
beb72684 RH |
921 | return false; |
922 | ||
fad2288b | 923 | poly_uint64 regsize = REGMODE_NATURAL_SIZE (imode); |
1eae67f8 | 924 | |
57b7c432 | 925 | /* ??? This should not be here. Temporarily continue to allow word_mode |
926 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
927 | Generally, backends are doing something sketchy but it'll take time to | |
928 | fix them all. */ | |
929 | if (omode == word_mode) | |
930 | ; | |
931 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
932 | is the culprit here, and not the backends. */ | |
933 | else if (known_ge (osize, regsize) && known_ge (isize, osize)) | |
934 | ; | |
935 | /* Allow component subregs of complex and vector. Though given the below | |
936 | extraction rules, it's not always clear what that means. */ | |
937 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
938 | && GET_MODE_INNER (imode) == omode) | |
939 | ; | |
940 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
941 | i.e. (subreg:V4SF (reg:SF) 0) or (subreg:V4SF (reg:V2SF) 0). This | |
942 | surely isn't the cleanest way to represent this. It's questionable | |
943 | if this ought to be represented at all -- why can't this all be hidden | |
944 | in post-reload splitters that make arbitrarily mode changes to the | |
945 | registers themselves. */ | |
946 | else if (VECTOR_MODE_P (omode) | |
947 | && GET_MODE_INNER (omode) == GET_MODE_INNER (imode)) | |
948 | ; | |
949 | /* Subregs involving floating point modes are not allowed to | |
950 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
951 | (subreg:SI (reg:DF) 0) isn't. */ | |
952 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
953 | { | |
954 | if (! (known_eq (isize, osize) | |
955 | /* LRA can use subreg to store a floating point value in | |
956 | an integer mode. Although the floating point and the | |
957 | integer modes need the same number of hard registers, | |
958 | the size of floating point mode can be less than the | |
959 | integer mode. LRA also uses subregs for a register | |
960 | should be used in different mode in on insn. */ | |
961 | || lra_in_progress)) | |
962 | return false; | |
963 | } | |
964 | ||
beb72684 | 965 | /* Paradoxical subregs must have offset zero. */ |
fad2288b | 966 | if (maybe_gt (osize, isize)) |
91914e56 | 967 | return known_eq (offset, 0U); |
beb72684 RH |
968 | |
969 | /* This is a normal subreg. Verify that the offset is representable. */ | |
970 | ||
971 | /* For hard registers, we already have most of these rules collected in | |
972 | subreg_offset_representable_p. */ | |
973 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
974 | { | |
975 | unsigned int regno = REGNO (reg); | |
976 | ||
beb72684 RH |
977 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) |
978 | && GET_MODE_INNER (imode) == omode) | |
979 | ; | |
0d803030 | 980 | else if (!REG_CAN_CHANGE_MODE_P (regno, imode, omode)) |
beb72684 | 981 | return false; |
beb72684 RH |
982 | |
983 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
984 | } | |
985 | ||
fad2288b RS |
986 | /* The outer size must be ordered wrt the register size, otherwise |
987 | we wouldn't know at compile time how many registers the outer | |
988 | mode occupies. */ | |
989 | if (!ordered_p (osize, regsize)) | |
990 | return false; | |
991 | ||
beb72684 | 992 | /* For pseudo registers, we want most of the same checks. Namely: |
1eae67f8 RS |
993 | |
994 | Assume that the pseudo register will be allocated to hard registers | |
995 | that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE, | |
996 | the remainder must correspond to the lowpart of the containing hard | |
997 | register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset, | |
998 | otherwise it is at the lowest offset. | |
999 | ||
1000 | Given that we've already checked the mode and offset alignment, | |
1001 | we only have to check subblock subregs here. */ | |
fad2288b | 1002 | if (maybe_lt (osize, regsize) |
55a2c322 | 1003 | && ! (lra_in_progress && (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)))) |
beb72684 | 1004 | { |
fad2288b RS |
1005 | /* It is invalid for the target to pick a register size for a mode |
1006 | that isn't ordered wrt to the size of that mode. */ | |
1007 | poly_uint64 block_size = ordered_min (isize, regsize); | |
91914e56 RS |
1008 | unsigned int start_reg; |
1009 | poly_uint64 offset_within_reg; | |
1010 | if (!can_div_trunc_p (offset, block_size, &start_reg, &offset_within_reg) | |
1011 | || (BYTES_BIG_ENDIAN | |
1012 | ? maybe_ne (offset_within_reg, block_size - osize) | |
1013 | : maybe_ne (offset_within_reg, 0U))) | |
beb72684 RH |
1014 | return false; |
1015 | } | |
1016 | return true; | |
1017 | } | |
1018 | ||
1019 | rtx | |
91914e56 | 1020 | gen_rtx_SUBREG (machine_mode mode, rtx reg, poly_uint64 offset) |
beb72684 RH |
1021 | { |
1022 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 1023 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
1024 | } |
1025 | ||
173b24b9 RK |
1026 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
1027 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
1028 | ||
ddef6bc7 | 1029 | rtx |
ef4bddc2 | 1030 | gen_lowpart_SUBREG (machine_mode mode, rtx reg) |
ddef6bc7 | 1031 | { |
ef4bddc2 | 1032 | machine_mode inmode; |
ddef6bc7 JJ |
1033 | |
1034 | inmode = GET_MODE (reg); | |
1035 | if (inmode == VOIDmode) | |
1036 | inmode = mode; | |
e0e08ac2 JH |
1037 | return gen_rtx_SUBREG (mode, reg, |
1038 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 1039 | } |
fcc74520 RS |
1040 | |
1041 | rtx | |
ef4bddc2 | 1042 | gen_rtx_VAR_LOCATION (machine_mode mode, tree decl, rtx loc, |
fcc74520 RS |
1043 | enum var_init_status status) |
1044 | { | |
1045 | rtx x = gen_rtx_fmt_te (VAR_LOCATION, mode, decl, loc); | |
1046 | PAT_VAR_LOCATION_STATUS (x) = status; | |
1047 | return x; | |
1048 | } | |
c5c76735 | 1049 | \f |
23b2ce53 | 1050 | |
80379f51 PB |
1051 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
1052 | ||
23b2ce53 | 1053 | rtvec |
e34d07f2 | 1054 | gen_rtvec (int n, ...) |
23b2ce53 | 1055 | { |
80379f51 PB |
1056 | int i; |
1057 | rtvec rt_val; | |
e34d07f2 | 1058 | va_list p; |
23b2ce53 | 1059 | |
e34d07f2 | 1060 | va_start (p, n); |
23b2ce53 | 1061 | |
80379f51 | 1062 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 1063 | if (n == 0) |
0edf1bb2 JL |
1064 | { |
1065 | va_end (p); | |
1066 | return NULL_RTVEC; | |
1067 | } | |
23b2ce53 | 1068 | |
80379f51 | 1069 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 1070 | |
23b2ce53 | 1071 | for (i = 0; i < n; i++) |
80379f51 | 1072 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 1073 | |
e34d07f2 | 1074 | va_end (p); |
80379f51 | 1075 | return rt_val; |
23b2ce53 RS |
1076 | } |
1077 | ||
1078 | rtvec | |
502b8322 | 1079 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 1080 | { |
b3694847 SS |
1081 | int i; |
1082 | rtvec rt_val; | |
23b2ce53 | 1083 | |
80379f51 | 1084 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 1085 | if (n == 0) |
80379f51 | 1086 | return NULL_RTVEC; |
23b2ce53 | 1087 | |
80379f51 | 1088 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
1089 | |
1090 | for (i = 0; i < n; i++) | |
8f985ec4 | 1091 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
1092 | |
1093 | return rt_val; | |
1094 | } | |
e6eda746 DM |
1095 | |
1096 | rtvec | |
1097 | gen_rtvec_v (int n, rtx_insn **argp) | |
1098 | { | |
1099 | int i; | |
1100 | rtvec rt_val; | |
1101 | ||
1102 | /* Don't allocate an empty rtvec... */ | |
1103 | if (n == 0) | |
1104 | return NULL_RTVEC; | |
1105 | ||
1106 | rt_val = rtvec_alloc (n); | |
1107 | ||
1108 | for (i = 0; i < n; i++) | |
1109 | rt_val->elem[i] = *argp++; | |
1110 | ||
1111 | return rt_val; | |
1112 | } | |
1113 | ||
23b2ce53 | 1114 | \f |
38ae7651 RS |
1115 | /* Return the number of bytes between the start of an OUTER_MODE |
1116 | in-memory value and the start of an INNER_MODE in-memory value, | |
1117 | given that the former is a lowpart of the latter. It may be a | |
1118 | paradoxical lowpart, in which case the offset will be negative | |
1119 | on big-endian targets. */ | |
1120 | ||
91914e56 | 1121 | poly_int64 |
ef4bddc2 RS |
1122 | byte_lowpart_offset (machine_mode outer_mode, |
1123 | machine_mode inner_mode) | |
38ae7651 | 1124 | { |
03a95621 | 1125 | if (paradoxical_subreg_p (outer_mode, inner_mode)) |
38ae7651 | 1126 | return -subreg_lowpart_offset (inner_mode, outer_mode); |
03a95621 RS |
1127 | else |
1128 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
38ae7651 | 1129 | } |
3d09ba95 RS |
1130 | |
1131 | /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET) | |
1132 | from address X. For paradoxical big-endian subregs this is a | |
1133 | negative value, otherwise it's the same as OFFSET. */ | |
1134 | ||
91914e56 | 1135 | poly_int64 |
3d09ba95 | 1136 | subreg_memory_offset (machine_mode outer_mode, machine_mode inner_mode, |
91914e56 | 1137 | poly_uint64 offset) |
3d09ba95 RS |
1138 | { |
1139 | if (paradoxical_subreg_p (outer_mode, inner_mode)) | |
1140 | { | |
91914e56 | 1141 | gcc_assert (known_eq (offset, 0U)); |
3d09ba95 RS |
1142 | return -subreg_lowpart_offset (inner_mode, outer_mode); |
1143 | } | |
1144 | return offset; | |
1145 | } | |
1146 | ||
1147 | /* As above, but return the offset that existing subreg X would have | |
1148 | if SUBREG_REG (X) were stored in memory. The only significant thing | |
1149 | about the current SUBREG_REG is its mode. */ | |
1150 | ||
91914e56 | 1151 | poly_int64 |
3d09ba95 RS |
1152 | subreg_memory_offset (const_rtx x) |
1153 | { | |
1154 | return subreg_memory_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)), | |
1155 | SUBREG_BYTE (x)); | |
1156 | } | |
38ae7651 | 1157 | \f |
23b2ce53 RS |
1158 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
1159 | This pseudo is assigned the next sequential register number. */ | |
1160 | ||
1161 | rtx | |
ef4bddc2 | 1162 | gen_reg_rtx (machine_mode mode) |
23b2ce53 | 1163 | { |
b3694847 | 1164 | rtx val; |
2e3f842f | 1165 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 1166 | |
f8335a4f | 1167 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 1168 | |
2e3f842f L |
1169 | /* If a virtual register with bigger mode alignment is generated, |
1170 | increase stack alignment estimation because it might be spilled | |
1171 | to stack later. */ | |
b8698a0f | 1172 | if (SUPPORTS_STACK_ALIGNMENT |
2e3f842f L |
1173 | && crtl->stack_alignment_estimated < align |
1174 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
1175 | { |
1176 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
1177 | if (crtl->stack_alignment_estimated < min_align) | |
1178 | crtl->stack_alignment_estimated = min_align; | |
1179 | } | |
2e3f842f | 1180 | |
1b3d8f8a GK |
1181 | if (generating_concat_p |
1182 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
1183 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
1184 | { |
1185 | /* For complex modes, don't make a single pseudo. | |
1186 | Instead, make a CONCAT of two pseudos. | |
1187 | This allows noncontiguous allocation of the real and imaginary parts, | |
1188 | which makes much better code. Besides, allocating DCmode | |
1189 | pseudos overstrains reload on some machines like the 386. */ | |
1190 | rtx realpart, imagpart; | |
ef4bddc2 | 1191 | machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
1192 | |
1193 | realpart = gen_reg_rtx (partmode); | |
1194 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 1195 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
1196 | } |
1197 | ||
004a7e45 UB |
1198 | /* Do not call gen_reg_rtx with uninitialized crtl. */ |
1199 | gcc_assert (crtl->emit.regno_pointer_align_length); | |
1200 | ||
f44986d7 DM |
1201 | crtl->emit.ensure_regno_capacity (); |
1202 | gcc_assert (reg_rtx_no < crtl->emit.regno_pointer_align_length); | |
23b2ce53 | 1203 | |
f44986d7 DM |
1204 | val = gen_raw_REG (mode, reg_rtx_no); |
1205 | regno_reg_rtx[reg_rtx_no++] = val; | |
1206 | return val; | |
1207 | } | |
0d4903b8 | 1208 | |
f44986d7 DM |
1209 | /* Make sure m_regno_pointer_align, and regno_reg_rtx are large |
1210 | enough to have elements in the range 0 <= idx <= reg_rtx_no. */ | |
49ad7cfa | 1211 | |
f44986d7 DM |
1212 | void |
1213 | emit_status::ensure_regno_capacity () | |
1214 | { | |
1215 | int old_size = regno_pointer_align_length; | |
23b2ce53 | 1216 | |
f44986d7 DM |
1217 | if (reg_rtx_no < old_size) |
1218 | return; | |
23b2ce53 | 1219 | |
f44986d7 DM |
1220 | int new_size = old_size * 2; |
1221 | while (reg_rtx_no >= new_size) | |
1222 | new_size *= 2; | |
1223 | ||
1224 | char *tmp = XRESIZEVEC (char, regno_pointer_align, new_size); | |
1225 | memset (tmp + old_size, 0, new_size - old_size); | |
1226 | regno_pointer_align = (unsigned char *) tmp; | |
1227 | ||
1228 | rtx *new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, new_size); | |
1229 | memset (new1 + old_size, 0, (new_size - old_size) * sizeof (rtx)); | |
1230 | regno_reg_rtx = new1; | |
1231 | ||
1232 | crtl->emit.regno_pointer_align_length = new_size; | |
23b2ce53 RS |
1233 | } |
1234 | ||
a698cc03 JL |
1235 | /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */ |
1236 | ||
1237 | bool | |
1238 | reg_is_parm_p (rtx reg) | |
1239 | { | |
1240 | tree decl; | |
1241 | ||
1242 | gcc_assert (REG_P (reg)); | |
1243 | decl = REG_EXPR (reg); | |
1244 | return (decl && TREE_CODE (decl) == PARM_DECL); | |
1245 | } | |
1246 | ||
38ae7651 RS |
1247 | /* Update NEW with the same attributes as REG, but with OFFSET added |
1248 | to the REG_OFFSET. */ | |
a560d4d4 | 1249 | |
e53a16e7 | 1250 | static void |
84bc717b | 1251 | update_reg_offset (rtx new_rtx, rtx reg, poly_int64 offset) |
a560d4d4 | 1252 | { |
60564289 | 1253 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
84bc717b | 1254 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
1255 | } |
1256 | ||
38ae7651 RS |
1257 | /* Generate a register with same attributes as REG, but with OFFSET |
1258 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
1259 | |
1260 | rtx | |
ef4bddc2 | 1261 | gen_rtx_REG_offset (rtx reg, machine_mode mode, unsigned int regno, |
84bc717b | 1262 | poly_int64 offset) |
e53a16e7 | 1263 | { |
60564289 | 1264 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 1265 | |
60564289 KG |
1266 | update_reg_offset (new_rtx, reg, offset); |
1267 | return new_rtx; | |
e53a16e7 ILT |
1268 | } |
1269 | ||
1270 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 1271 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
1272 | |
1273 | rtx | |
ef4bddc2 | 1274 | gen_reg_rtx_offset (rtx reg, machine_mode mode, int offset) |
e53a16e7 | 1275 | { |
60564289 | 1276 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 1277 | |
60564289 KG |
1278 | update_reg_offset (new_rtx, reg, offset); |
1279 | return new_rtx; | |
a560d4d4 JH |
1280 | } |
1281 | ||
38ae7651 RS |
1282 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
1283 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
1284 | |
1285 | void | |
ef4bddc2 | 1286 | adjust_reg_mode (rtx reg, machine_mode mode) |
a560d4d4 | 1287 | { |
38ae7651 RS |
1288 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
1289 | PUT_MODE (reg, mode); | |
1290 | } | |
1291 | ||
1292 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
1293 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
1294 | ||
1295 | void | |
1296 | set_reg_attrs_from_value (rtx reg, rtx x) | |
1297 | { | |
84bc717b | 1298 | poly_int64 offset; |
de6f3f7a L |
1299 | bool can_be_reg_pointer = true; |
1300 | ||
1301 | /* Don't call mark_reg_pointer for incompatible pointer sign | |
1302 | extension. */ | |
1303 | while (GET_CODE (x) == SIGN_EXTEND | |
1304 | || GET_CODE (x) == ZERO_EXTEND | |
1305 | || GET_CODE (x) == TRUNCATE | |
1306 | || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x))) | |
1307 | { | |
2a870875 RS |
1308 | #if defined(POINTERS_EXTEND_UNSIGNED) |
1309 | if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED) | |
8d8e740c BE |
1310 | || (GET_CODE (x) == ZERO_EXTEND && ! POINTERS_EXTEND_UNSIGNED) |
1311 | || (paradoxical_subreg_p (x) | |
1312 | && ! (SUBREG_PROMOTED_VAR_P (x) | |
1313 | && SUBREG_CHECK_PROMOTED_SIGN (x, | |
1314 | POINTERS_EXTEND_UNSIGNED)))) | |
2a870875 | 1315 | && !targetm.have_ptr_extend ()) |
de6f3f7a L |
1316 | can_be_reg_pointer = false; |
1317 | #endif | |
1318 | x = XEXP (x, 0); | |
1319 | } | |
38ae7651 | 1320 | |
923ba36f JJ |
1321 | /* Hard registers can be reused for multiple purposes within the same |
1322 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
1323 | on them is wrong. */ | |
1324 | if (HARD_REGISTER_P (reg)) | |
1325 | return; | |
1326 | ||
38ae7651 | 1327 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
1328 | if (MEM_P (x)) |
1329 | { | |
527210c4 RS |
1330 | if (MEM_OFFSET_KNOWN_P (x)) |
1331 | REG_ATTRS (reg) = get_reg_attrs (MEM_EXPR (x), | |
1332 | MEM_OFFSET (x) + offset); | |
de6f3f7a | 1333 | if (can_be_reg_pointer && MEM_POINTER (x)) |
0a317111 | 1334 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
1335 | } |
1336 | else if (REG_P (x)) | |
1337 | { | |
1338 | if (REG_ATTRS (x)) | |
1339 | update_reg_offset (reg, x, offset); | |
de6f3f7a | 1340 | if (can_be_reg_pointer && REG_POINTER (x)) |
46b71b03 PB |
1341 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); |
1342 | } | |
1343 | } | |
1344 | ||
1345 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
1346 | and attributes from X. */ | |
1347 | ||
1348 | rtx | |
1349 | gen_reg_rtx_and_attrs (rtx x) | |
1350 | { | |
1351 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1352 | set_reg_attrs_from_value (reg, x); | |
1353 | return reg; | |
a560d4d4 JH |
1354 | } |
1355 | ||
9d18e06b JZ |
1356 | /* Set the register attributes for registers contained in PARM_RTX. |
1357 | Use needed values from memory attributes of MEM. */ | |
1358 | ||
1359 | void | |
502b8322 | 1360 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1361 | { |
f8cfc6aa | 1362 | if (REG_P (parm_rtx)) |
38ae7651 | 1363 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1364 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1365 | { | |
1366 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1367 | parameter goes both on the stack and in registers. */ | |
1368 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1369 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1370 | { | |
1371 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1372 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1373 | REG_ATTRS (XEXP (x, 0)) |
1374 | = get_reg_attrs (MEM_EXPR (mem), | |
1375 | INTVAL (XEXP (x, 1))); | |
1376 | } | |
1377 | } | |
1378 | } | |
1379 | ||
38ae7651 RS |
1380 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1381 | decl T. */ | |
a560d4d4 | 1382 | |
4e3825db | 1383 | void |
38ae7651 RS |
1384 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1385 | { | |
1f9ceff1 AO |
1386 | if (!t) |
1387 | return; | |
1388 | tree tdecl = t; | |
38ae7651 | 1389 | if (GET_CODE (x) == SUBREG) |
fbe6ec81 | 1390 | { |
38ae7651 RS |
1391 | gcc_assert (subreg_lowpart_p (x)); |
1392 | x = SUBREG_REG (x); | |
fbe6ec81 | 1393 | } |
f8cfc6aa | 1394 | if (REG_P (x)) |
38ae7651 RS |
1395 | REG_ATTRS (x) |
1396 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
1f9ceff1 AO |
1397 | DECL_P (tdecl) |
1398 | ? DECL_MODE (tdecl) | |
1399 | : TYPE_MODE (TREE_TYPE (tdecl)))); | |
a560d4d4 JH |
1400 | if (GET_CODE (x) == CONCAT) |
1401 | { | |
1402 | if (REG_P (XEXP (x, 0))) | |
1403 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1404 | if (REG_P (XEXP (x, 1))) | |
1405 | REG_ATTRS (XEXP (x, 1)) | |
1406 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1407 | } | |
1408 | if (GET_CODE (x) == PARALLEL) | |
1409 | { | |
d4afac5b JZ |
1410 | int i, start; |
1411 | ||
1412 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1413 | both on the stack and in registers. */ | |
1414 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1415 | start = 0; | |
1416 | else | |
1417 | start = 1; | |
1418 | ||
1419 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1420 | { |
1421 | rtx y = XVECEXP (x, 0, i); | |
1422 | if (REG_P (XEXP (y, 0))) | |
1423 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1424 | } | |
1425 | } | |
1426 | } | |
1427 | ||
38ae7651 RS |
1428 | /* Assign the RTX X to declaration T. */ |
1429 | ||
1430 | void | |
1431 | set_decl_rtl (tree t, rtx x) | |
1432 | { | |
1433 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1434 | if (x) | |
1435 | set_reg_attrs_for_decl_rtl (t, x); | |
1436 | } | |
1437 | ||
5141868d RS |
1438 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1439 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1440 | |
1441 | void | |
5141868d | 1442 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1443 | { |
1444 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1445 | if (x && !by_reference_p) |
38ae7651 RS |
1446 | set_reg_attrs_for_decl_rtl (t, x); |
1447 | } | |
1448 | ||
754fdcca RK |
1449 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1450 | ||
1451 | void | |
502b8322 | 1452 | mark_user_reg (rtx reg) |
754fdcca RK |
1453 | { |
1454 | if (GET_CODE (reg) == CONCAT) | |
1455 | { | |
1456 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1457 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1458 | } | |
754fdcca | 1459 | else |
5b0264cb NS |
1460 | { |
1461 | gcc_assert (REG_P (reg)); | |
1462 | REG_USERVAR_P (reg) = 1; | |
1463 | } | |
754fdcca RK |
1464 | } |
1465 | ||
86fe05e0 RK |
1466 | /* Identify REG as a probable pointer register and show its alignment |
1467 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1468 | |
1469 | void | |
502b8322 | 1470 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1471 | { |
3502dc9c | 1472 | if (! REG_POINTER (reg)) |
00995e78 | 1473 | { |
3502dc9c | 1474 | REG_POINTER (reg) = 1; |
86fe05e0 | 1475 | |
00995e78 RE |
1476 | if (align) |
1477 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1478 | } | |
1479 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1480 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1481 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1482 | } |
1483 | ||
1484 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1485 | ||
1486 | int | |
502b8322 | 1487 | max_reg_num (void) |
23b2ce53 RS |
1488 | { |
1489 | return reg_rtx_no; | |
1490 | } | |
1491 | ||
1492 | /* Return 1 + the largest label number used so far in the current function. */ | |
1493 | ||
1494 | int | |
502b8322 | 1495 | max_label_num (void) |
23b2ce53 | 1496 | { |
23b2ce53 RS |
1497 | return label_num; |
1498 | } | |
1499 | ||
1500 | /* Return first label number used in this function (if any were used). */ | |
1501 | ||
1502 | int | |
502b8322 | 1503 | get_first_label_num (void) |
23b2ce53 RS |
1504 | { |
1505 | return first_label_num; | |
1506 | } | |
6de9cd9a DN |
1507 | |
1508 | /* If the rtx for label was created during the expansion of a nested | |
1509 | function, then first_label_num won't include this label number. | |
fa10beec | 1510 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1511 | |
1512 | void | |
9aa50db7 | 1513 | maybe_set_first_label_num (rtx_code_label *x) |
6de9cd9a DN |
1514 | { |
1515 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1516 | first_label_num = CODE_LABEL_NUMBER (x); | |
1517 | } | |
51b86113 DM |
1518 | |
1519 | /* For use by the RTL function loader, when mingling with normal | |
1520 | functions. | |
1521 | Ensure that label_num is greater than the label num of X, to avoid | |
1522 | duplicate labels in the generated assembler. */ | |
1523 | ||
1524 | void | |
1525 | maybe_set_max_label_num (rtx_code_label *x) | |
1526 | { | |
1527 | if (CODE_LABEL_NUMBER (x) >= label_num) | |
1528 | label_num = CODE_LABEL_NUMBER (x) + 1; | |
1529 | } | |
1530 | ||
23b2ce53 RS |
1531 | \f |
1532 | /* Return a value representing some low-order bits of X, where the number | |
1533 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1534 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1535 | representation is returned. |
1536 | ||
1537 | This function handles the cases in common between gen_lowpart, below, | |
1538 | and two variants in cse.c and combine.c. These are the cases that can | |
1539 | be safely handled at all points in the compilation. | |
1540 | ||
1541 | If this is not a case we can handle, return 0. */ | |
1542 | ||
1543 | rtx | |
ef4bddc2 | 1544 | gen_lowpart_common (machine_mode mode, rtx x) |
23b2ce53 | 1545 | { |
fad2288b | 1546 | poly_uint64 msize = GET_MODE_SIZE (mode); |
ef4bddc2 | 1547 | machine_mode innermode; |
550d1387 GK |
1548 | |
1549 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1550 | so we have to make one up. Yuk. */ | |
1551 | innermode = GET_MODE (x); | |
481683e1 | 1552 | if (CONST_INT_P (x) |
fad2288b RS |
1553 | && known_le (msize * BITS_PER_UNIT, |
1554 | (unsigned HOST_WIDE_INT) HOST_BITS_PER_WIDE_INT)) | |
f4b31647 | 1555 | innermode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require (); |
550d1387 | 1556 | else if (innermode == VOIDmode) |
f4b31647 | 1557 | innermode = int_mode_for_size (HOST_BITS_PER_DOUBLE_INT, 0).require (); |
b8698a0f | 1558 | |
5b0264cb | 1559 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1560 | |
550d1387 | 1561 | if (innermode == mode) |
23b2ce53 RS |
1562 | return x; |
1563 | ||
fad2288b RS |
1564 | /* The size of the outer and inner modes must be ordered. */ |
1565 | poly_uint64 xsize = GET_MODE_SIZE (innermode); | |
1566 | if (!ordered_p (msize, xsize)) | |
1567 | return 0; | |
1568 | ||
1eae67f8 RS |
1569 | if (SCALAR_FLOAT_MODE_P (mode)) |
1570 | { | |
1571 | /* Don't allow paradoxical FLOAT_MODE subregs. */ | |
fad2288b | 1572 | if (maybe_gt (msize, xsize)) |
1eae67f8 RS |
1573 | return 0; |
1574 | } | |
1575 | else | |
1576 | { | |
1577 | /* MODE must occupy no more of the underlying registers than X. */ | |
fad2288b RS |
1578 | poly_uint64 regsize = REGMODE_NATURAL_SIZE (innermode); |
1579 | unsigned int mregs, xregs; | |
1580 | if (!can_div_away_from_zero_p (msize, regsize, &mregs) | |
1581 | || !can_div_away_from_zero_p (xsize, regsize, &xregs) | |
1582 | || mregs > xregs) | |
1eae67f8 RS |
1583 | return 0; |
1584 | } | |
53501a19 | 1585 | |
54651377 | 1586 | scalar_int_mode int_mode, int_innermode, from_mode; |
23b2ce53 | 1587 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) |
54651377 RS |
1588 | && is_a <scalar_int_mode> (mode, &int_mode) |
1589 | && is_a <scalar_int_mode> (innermode, &int_innermode) | |
1590 | && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &from_mode)) | |
23b2ce53 RS |
1591 | { |
1592 | /* If we are getting the low-order part of something that has been | |
1593 | sign- or zero-extended, we can either just use the object being | |
1594 | extended or make a narrower extension. If we want an even smaller | |
1595 | piece than the size of the object being extended, call ourselves | |
1596 | recursively. | |
1597 | ||
1598 | This case is used mostly by combine and cse. */ | |
1599 | ||
54651377 | 1600 | if (from_mode == int_mode) |
23b2ce53 | 1601 | return XEXP (x, 0); |
54651377 RS |
1602 | else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (from_mode)) |
1603 | return gen_lowpart_common (int_mode, XEXP (x, 0)); | |
1604 | else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode)) | |
1605 | return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0)); | |
23b2ce53 | 1606 | } |
f8cfc6aa | 1607 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
2072a319 | 1608 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
0c12fc9b RS |
1609 | || CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x) |
1610 | || CONST_POLY_INT_P (x)) | |
3403a1a9 | 1611 | return lowpart_subreg (mode, x, innermode); |
8aada4ad | 1612 | |
23b2ce53 RS |
1613 | /* Otherwise, we can't do this. */ |
1614 | return 0; | |
1615 | } | |
1616 | \f | |
ccba022b | 1617 | rtx |
ef4bddc2 | 1618 | gen_highpart (machine_mode mode, rtx x) |
ccba022b | 1619 | { |
cf098191 | 1620 | poly_uint64 msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1621 | rtx result; |
ddef6bc7 | 1622 | |
ccba022b RS |
1623 | /* This case loses if X is a subreg. To catch bugs early, |
1624 | complain if an invalid MODE is used even in other cases. */ | |
cf098191 RS |
1625 | gcc_assert (known_le (msize, (unsigned int) UNITS_PER_WORD) |
1626 | || known_eq (msize, GET_MODE_UNIT_SIZE (GET_MODE (x)))); | |
ddef6bc7 | 1627 | |
408e8b90 RE |
1628 | /* gen_lowpart_common handles a lot of special cases due to needing to handle |
1629 | paradoxical subregs; it only calls simplify_gen_subreg when certain that | |
1630 | it will produce something meaningful. The only case we need to handle | |
1631 | specially here is MEM. */ | |
1632 | if (MEM_P (x)) | |
5b0264cb | 1633 | { |
408e8b90 RE |
1634 | poly_int64 offset = subreg_highpart_offset (mode, GET_MODE (x)); |
1635 | return adjust_address (x, mode, offset); | |
5b0264cb | 1636 | } |
b8698a0f | 1637 | |
408e8b90 RE |
1638 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1639 | subreg_highpart_offset (mode, GET_MODE (x))); | |
1640 | /* Since we handle MEM directly above, we should never get a MEM back | |
1641 | from simplify_gen_subreg. */ | |
1642 | gcc_assert (result && !MEM_P (result)); | |
1643 | ||
e0e08ac2 JH |
1644 | return result; |
1645 | } | |
5222e470 | 1646 | |
26d249eb | 1647 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1648 | be VOIDmode constant. */ |
1649 | rtx | |
ef4bddc2 | 1650 | gen_highpart_mode (machine_mode outermode, machine_mode innermode, rtx exp) |
5222e470 JH |
1651 | { |
1652 | if (GET_MODE (exp) != VOIDmode) | |
1653 | { | |
5b0264cb | 1654 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1655 | return gen_highpart (outermode, exp); |
1656 | } | |
1657 | return simplify_gen_subreg (outermode, exp, innermode, | |
1658 | subreg_highpart_offset (outermode, innermode)); | |
1659 | } | |
68252e27 | 1660 | |
33951763 RS |
1661 | /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has |
1662 | OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */ | |
8698cce3 | 1663 | |
91914e56 RS |
1664 | poly_uint64 |
1665 | subreg_size_lowpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes) | |
e0e08ac2 | 1666 | { |
91914e56 RS |
1667 | gcc_checking_assert (ordered_p (outer_bytes, inner_bytes)); |
1668 | if (maybe_gt (outer_bytes, inner_bytes)) | |
33951763 RS |
1669 | /* Paradoxical subregs always have a SUBREG_BYTE of 0. */ |
1670 | return 0; | |
ddef6bc7 | 1671 | |
33951763 RS |
1672 | if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN) |
1673 | return inner_bytes - outer_bytes; | |
1674 | else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN) | |
1675 | return 0; | |
1676 | else | |
1677 | return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, 0); | |
ccba022b | 1678 | } |
eea50aa0 | 1679 | |
33951763 RS |
1680 | /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has |
1681 | OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */ | |
1682 | ||
91914e56 RS |
1683 | poly_uint64 |
1684 | subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes) | |
eea50aa0 | 1685 | { |
91914e56 | 1686 | gcc_assert (known_ge (inner_bytes, outer_bytes)); |
eea50aa0 | 1687 | |
33951763 RS |
1688 | if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN) |
1689 | return 0; | |
1690 | else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN) | |
1691 | return inner_bytes - outer_bytes; | |
1692 | else | |
1693 | return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, | |
1694 | (inner_bytes - outer_bytes) | |
1695 | * BITS_PER_UNIT); | |
eea50aa0 | 1696 | } |
ccba022b | 1697 | |
23b2ce53 RS |
1698 | /* Return 1 iff X, assumed to be a SUBREG, |
1699 | refers to the least significant part of its containing reg. | |
1700 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1701 | ||
1702 | int | |
fa233e34 | 1703 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1704 | { |
1705 | if (GET_CODE (x) != SUBREG) | |
1706 | return 1; | |
a3a03040 RK |
1707 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1708 | return 0; | |
23b2ce53 | 1709 | |
91914e56 RS |
1710 | return known_eq (subreg_lowpart_offset (GET_MODE (x), |
1711 | GET_MODE (SUBREG_REG (x))), | |
1712 | SUBREG_BYTE (x)); | |
23b2ce53 RS |
1713 | } |
1714 | \f | |
ddef6bc7 JJ |
1715 | /* Return subword OFFSET of operand OP. |
1716 | The word number, OFFSET, is interpreted as the word number starting | |
1717 | at the low-order address. OFFSET 0 is the low-order word if not | |
1718 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1719 | ||
1720 | If we cannot extract the required word, we return zero. Otherwise, | |
1721 | an rtx corresponding to the requested word will be returned. | |
1722 | ||
1723 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1724 | reload has completed, a valid address will always be returned. After | |
1725 | reload, if a valid address cannot be returned, we return zero. | |
1726 | ||
1727 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1728 | it is the responsibility of the caller. | |
1729 | ||
1730 | MODE is the mode of OP in case it is a CONST_INT. | |
1731 | ||
1732 | ??? This is still rather broken for some cases. The problem for the | |
1733 | moment is that all callers of this thing provide no 'goal mode' to | |
1734 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1735 | in a word based SUBREG world. |
1736 | Now use of this function can be deprecated by simplify_subreg in most | |
1737 | cases. | |
1738 | */ | |
ddef6bc7 JJ |
1739 | |
1740 | rtx | |
fdbfe4e5 RS |
1741 | operand_subword (rtx op, poly_uint64 offset, int validate_address, |
1742 | machine_mode mode) | |
ddef6bc7 JJ |
1743 | { |
1744 | if (mode == VOIDmode) | |
1745 | mode = GET_MODE (op); | |
1746 | ||
5b0264cb | 1747 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1748 | |
30f7a378 | 1749 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 | 1750 | if (mode != BLKmode |
fdbfe4e5 | 1751 | && maybe_lt (GET_MODE_SIZE (mode), UNITS_PER_WORD)) |
ddef6bc7 JJ |
1752 | return 0; |
1753 | ||
30f7a378 | 1754 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 | 1755 | if (mode != BLKmode |
fdbfe4e5 | 1756 | && maybe_gt ((offset + 1) * UNITS_PER_WORD, GET_MODE_SIZE (mode))) |
ddef6bc7 JJ |
1757 | return const0_rtx; |
1758 | ||
ddef6bc7 | 1759 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1760 | if (MEM_P (op)) |
ddef6bc7 | 1761 | { |
60564289 | 1762 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1763 | |
f1ec5147 | 1764 | if (! validate_address) |
60564289 | 1765 | return new_rtx; |
f1ec5147 RK |
1766 | |
1767 | else if (reload_completed) | |
ddef6bc7 | 1768 | { |
09e881c9 BE |
1769 | if (! strict_memory_address_addr_space_p (word_mode, |
1770 | XEXP (new_rtx, 0), | |
1771 | MEM_ADDR_SPACE (op))) | |
f1ec5147 | 1772 | return 0; |
ddef6bc7 | 1773 | } |
f1ec5147 | 1774 | else |
60564289 | 1775 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1776 | } |
1777 | ||
0631e0bf JH |
1778 | /* Rest can be handled by simplify_subreg. */ |
1779 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1780 | } |
1781 | ||
535a42b1 NS |
1782 | /* Similar to `operand_subword', but never return 0. If we can't |
1783 | extract the required subword, put OP into a register and try again. | |
1784 | The second attempt must succeed. We always validate the address in | |
1785 | this case. | |
23b2ce53 RS |
1786 | |
1787 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1788 | ||
1789 | rtx | |
fdbfe4e5 | 1790 | operand_subword_force (rtx op, poly_uint64 offset, machine_mode mode) |
23b2ce53 | 1791 | { |
ddef6bc7 | 1792 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1793 | |
1794 | if (result) | |
1795 | return result; | |
1796 | ||
1797 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb | 1798 | { |
67914693 | 1799 | /* If this is a register which cannot be accessed by words, copy it |
77e6b0eb | 1800 | to a pseudo register. */ |
f8cfc6aa | 1801 | if (REG_P (op)) |
77e6b0eb JC |
1802 | op = copy_to_reg (op); |
1803 | else | |
1804 | op = force_reg (mode, op); | |
1805 | } | |
23b2ce53 | 1806 | |
ddef6bc7 | 1807 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1808 | gcc_assert (result); |
23b2ce53 RS |
1809 | |
1810 | return result; | |
1811 | } | |
1812 | \f | |
d05d7551 RS |
1813 | mem_attrs::mem_attrs () |
1814 | : expr (NULL_TREE), | |
1815 | offset (0), | |
1816 | size (0), | |
1817 | alias (0), | |
1818 | align (0), | |
1819 | addrspace (ADDR_SPACE_GENERIC), | |
1820 | offset_known_p (false), | |
1821 | size_known_p (false) | |
1822 | {} | |
1823 | ||
2b3493c8 AK |
1824 | /* Returns 1 if both MEM_EXPR can be considered equal |
1825 | and 0 otherwise. */ | |
1826 | ||
1827 | int | |
4f588890 | 1828 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1829 | { |
1830 | if (expr1 == expr2) | |
1831 | return 1; | |
1832 | ||
1833 | if (! expr1 || ! expr2) | |
1834 | return 0; | |
1835 | ||
1836 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1837 | return 0; | |
1838 | ||
55b34b5f | 1839 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1840 | } |
1841 | ||
805903b5 JJ |
1842 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1843 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1844 | -1 if not known. */ | |
1845 | ||
1846 | int | |
d9223014 | 1847 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1848 | { |
1849 | tree expr; | |
d05d7551 | 1850 | poly_uint64 offset; |
805903b5 JJ |
1851 | |
1852 | /* This function can't use | |
527210c4 | 1853 | if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem) |
e80c2726 | 1854 | || (MAX (MEM_ALIGN (mem), |
0eb77834 | 1855 | MAX (align, get_object_alignment (MEM_EXPR (mem)))) |
805903b5 JJ |
1856 | < align)) |
1857 | return -1; | |
1858 | else | |
527210c4 | 1859 | return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1); |
805903b5 JJ |
1860 | for two reasons: |
1861 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1862 | for <variable>. get_inner_reference doesn't handle it and | |
1863 | even if it did, the alignment in that case needs to be determined | |
1864 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1865 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1866 | isn't sufficiently aligned, the object it is in might be. */ | |
1867 | gcc_assert (MEM_P (mem)); | |
1868 | expr = MEM_EXPR (mem); | |
527210c4 | 1869 | if (expr == NULL_TREE || !MEM_OFFSET_KNOWN_P (mem)) |
805903b5 JJ |
1870 | return -1; |
1871 | ||
527210c4 | 1872 | offset = MEM_OFFSET (mem); |
805903b5 JJ |
1873 | if (DECL_P (expr)) |
1874 | { | |
1875 | if (DECL_ALIGN (expr) < align) | |
1876 | return -1; | |
1877 | } | |
1878 | else if (INDIRECT_REF_P (expr)) | |
1879 | { | |
1880 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1881 | return -1; | |
1882 | } | |
1883 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1884 | { | |
1885 | while (1) | |
1886 | { | |
1887 | tree inner = TREE_OPERAND (expr, 0); | |
1888 | tree field = TREE_OPERAND (expr, 1); | |
1889 | tree byte_offset = component_ref_field_offset (expr); | |
1890 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1891 | ||
d05d7551 | 1892 | poly_uint64 suboffset; |
805903b5 | 1893 | if (!byte_offset |
d05d7551 | 1894 | || !poly_int_tree_p (byte_offset, &suboffset) |
cc269bb6 | 1895 | || !tree_fits_uhwi_p (bit_offset)) |
805903b5 JJ |
1896 | return -1; |
1897 | ||
d05d7551 | 1898 | offset += suboffset; |
ae7e9ddd | 1899 | offset += tree_to_uhwi (bit_offset) / BITS_PER_UNIT; |
805903b5 JJ |
1900 | |
1901 | if (inner == NULL_TREE) | |
1902 | { | |
1903 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1904 | < (unsigned int) align) | |
1905 | return -1; | |
1906 | break; | |
1907 | } | |
1908 | else if (DECL_P (inner)) | |
1909 | { | |
1910 | if (DECL_ALIGN (inner) < align) | |
1911 | return -1; | |
1912 | break; | |
1913 | } | |
1914 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1915 | return -1; | |
1916 | expr = inner; | |
1917 | } | |
1918 | } | |
1919 | else | |
1920 | return -1; | |
1921 | ||
d05d7551 RS |
1922 | HOST_WIDE_INT misalign; |
1923 | if (!known_misalignment (offset, align / BITS_PER_UNIT, &misalign)) | |
1924 | return -1; | |
1925 | return misalign; | |
805903b5 JJ |
1926 | } |
1927 | ||
6926c713 | 1928 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1929 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1930 | if we are making a new object of this type. BITPOS is nonzero if |
1931 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1932 | |
1933 | void | |
502b8322 | 1934 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
d05d7551 | 1935 | poly_int64 bitpos) |
173b24b9 | 1936 | { |
d05d7551 | 1937 | poly_int64 apply_bitpos = 0; |
173b24b9 | 1938 | tree type; |
99b1c316 | 1939 | class mem_attrs attrs, *defattrs, *refattrs; |
f18a7b25 | 1940 | addr_space_t as; |
173b24b9 RK |
1941 | |
1942 | /* It can happen that type_for_mode was given a mode for which there | |
1943 | is no language-level type. In which case it returns NULL, which | |
1944 | we can see here. */ | |
1945 | if (t == NULL_TREE) | |
1946 | return; | |
1947 | ||
1948 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1949 | if (type == error_mark_node) |
1950 | return; | |
173b24b9 | 1951 | |
173b24b9 RK |
1952 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1953 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1954 | info. Callers should not set DECL_RTL until after the call to | |
1955 | set_mem_attributes. */ | |
5b0264cb | 1956 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1957 | |
738cc472 | 1958 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 | 1959 | front-end routine) and use it. */ |
f12144dd | 1960 | attrs.alias = get_alias_set (t); |
173b24b9 | 1961 | |
a5e9c810 | 1962 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
f8ad8d7c | 1963 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1964 | |
268f7033 | 1965 | /* Default values from pre-existing memory attributes if present. */ |
f12144dd RS |
1966 | refattrs = MEM_ATTRS (ref); |
1967 | if (refattrs) | |
268f7033 UW |
1968 | { |
1969 | /* ??? Can this ever happen? Calling this routine on a MEM that | |
1970 | already carries memory attributes should probably be invalid. */ | |
f12144dd | 1971 | attrs.expr = refattrs->expr; |
754c3d5d | 1972 | attrs.offset_known_p = refattrs->offset_known_p; |
f12144dd | 1973 | attrs.offset = refattrs->offset; |
754c3d5d | 1974 | attrs.size_known_p = refattrs->size_known_p; |
f12144dd RS |
1975 | attrs.size = refattrs->size; |
1976 | attrs.align = refattrs->align; | |
268f7033 UW |
1977 | } |
1978 | ||
1979 | /* Otherwise, default values from the mode of the MEM reference. */ | |
f12144dd | 1980 | else |
268f7033 | 1981 | { |
f12144dd RS |
1982 | defattrs = mode_mem_attrs[(int) GET_MODE (ref)]; |
1983 | gcc_assert (!defattrs->expr); | |
754c3d5d | 1984 | gcc_assert (!defattrs->offset_known_p); |
f12144dd | 1985 | |
268f7033 | 1986 | /* Respect mode size. */ |
754c3d5d | 1987 | attrs.size_known_p = defattrs->size_known_p; |
f12144dd | 1988 | attrs.size = defattrs->size; |
268f7033 UW |
1989 | /* ??? Is this really necessary? We probably should always get |
1990 | the size from the type below. */ | |
1991 | ||
1992 | /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type; | |
1993 | if T is an object, always compute the object alignment below. */ | |
f12144dd RS |
1994 | if (TYPE_P (t)) |
1995 | attrs.align = defattrs->align; | |
1996 | else | |
1997 | attrs.align = BITS_PER_UNIT; | |
268f7033 UW |
1998 | /* ??? If T is a type, respecting mode alignment may *also* be wrong |
1999 | e.g. if the type carries an alignment attribute. Should we be | |
2000 | able to simply always use TYPE_ALIGN? */ | |
2001 | } | |
2002 | ||
25b75a48 BE |
2003 | /* We can set the alignment from the type if we are making an object or if |
2004 | this is an INDIRECT_REF. */ | |
2005 | if (objectp || TREE_CODE (t) == INDIRECT_REF) | |
f12144dd | 2006 | attrs.align = MAX (attrs.align, TYPE_ALIGN (type)); |
a80903ff | 2007 | |
738cc472 | 2008 | /* If the size is known, we can set that. */ |
a787ccc3 | 2009 | tree new_size = TYPE_SIZE_UNIT (type); |
738cc472 | 2010 | |
30b0317c RB |
2011 | /* The address-space is that of the type. */ |
2012 | as = TYPE_ADDR_SPACE (type); | |
2013 | ||
80965c18 RK |
2014 | /* If T is not a type, we may be able to deduce some more information about |
2015 | the expression. */ | |
2016 | if (! TYPE_P (t)) | |
8ac61af7 | 2017 | { |
8476af98 | 2018 | tree base; |
389fdba0 | 2019 | |
8ac61af7 RK |
2020 | if (TREE_THIS_VOLATILE (t)) |
2021 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 2022 | |
c56e3582 RK |
2023 | /* Now remove any conversions: they don't change what the underlying |
2024 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 2025 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
2026 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
2027 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
2028 | t = TREE_OPERAND (t, 0); |
2029 | ||
4994da65 RG |
2030 | /* Note whether this expression can trap. */ |
2031 | MEM_NOTRAP_P (ref) = !tree_could_trap_p (t); | |
2032 | ||
2033 | base = get_base_address (t); | |
f18a7b25 MJ |
2034 | if (base) |
2035 | { | |
2036 | if (DECL_P (base) | |
2037 | && TREE_READONLY (base) | |
2038 | && (TREE_STATIC (base) || DECL_EXTERNAL (base)) | |
2039 | && !TREE_THIS_VOLATILE (base)) | |
2040 | MEM_READONLY_P (ref) = 1; | |
2041 | ||
2042 | /* Mark static const strings readonly as well. */ | |
2043 | if (TREE_CODE (base) == STRING_CST | |
2044 | && TREE_READONLY (base) | |
2045 | && TREE_STATIC (base)) | |
2046 | MEM_READONLY_P (ref) = 1; | |
2047 | ||
30b0317c | 2048 | /* Address-space information is on the base object. */ |
f18a7b25 MJ |
2049 | if (TREE_CODE (base) == MEM_REF |
2050 | || TREE_CODE (base) == TARGET_MEM_REF) | |
2051 | as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base, | |
2052 | 0)))); | |
2053 | else | |
2054 | as = TYPE_ADDR_SPACE (TREE_TYPE (base)); | |
2055 | } | |
ba30e50d | 2056 | |
2039d7aa RH |
2057 | /* If this expression uses it's parent's alias set, mark it such |
2058 | that we won't change it. */ | |
b4ada065 | 2059 | if (component_uses_parent_alias_set_from (t) != NULL_TREE) |
10b76d73 RK |
2060 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
2061 | ||
8ac61af7 RK |
2062 | /* If this is a decl, set the attributes of the MEM from it. */ |
2063 | if (DECL_P (t)) | |
2064 | { | |
f12144dd | 2065 | attrs.expr = t; |
754c3d5d RS |
2066 | attrs.offset_known_p = true; |
2067 | attrs.offset = 0; | |
6f1087be | 2068 | apply_bitpos = bitpos; |
a787ccc3 | 2069 | new_size = DECL_SIZE_UNIT (t); |
8ac61af7 RK |
2070 | } |
2071 | ||
80d6f89e RB |
2072 | /* ??? If we end up with a constant or a descriptor do not |
2073 | record a MEM_EXPR. */ | |
2074 | else if (CONSTANT_CLASS_P (t) | |
2075 | || TREE_CODE (t) == CONSTRUCTOR) | |
30b0317c | 2076 | ; |
998d7deb | 2077 | |
a787ccc3 RS |
2078 | /* If this is a field reference, record it. */ |
2079 | else if (TREE_CODE (t) == COMPONENT_REF) | |
998d7deb | 2080 | { |
f12144dd | 2081 | attrs.expr = t; |
754c3d5d RS |
2082 | attrs.offset_known_p = true; |
2083 | attrs.offset = 0; | |
6f1087be | 2084 | apply_bitpos = bitpos; |
a787ccc3 RS |
2085 | if (DECL_BIT_FIELD (TREE_OPERAND (t, 1))) |
2086 | new_size = DECL_SIZE_UNIT (TREE_OPERAND (t, 1)); | |
998d7deb RH |
2087 | } |
2088 | ||
80d6f89e RB |
2089 | /* Else record it. */ |
2090 | else | |
56c47f22 | 2091 | { |
80d6f89e RB |
2092 | gcc_assert (handled_component_p (t) |
2093 | || TREE_CODE (t) == MEM_REF | |
2094 | || TREE_CODE (t) == TARGET_MEM_REF); | |
f12144dd | 2095 | attrs.expr = t; |
754c3d5d RS |
2096 | attrs.offset_known_p = true; |
2097 | attrs.offset = 0; | |
56c47f22 RG |
2098 | apply_bitpos = bitpos; |
2099 | } | |
2100 | ||
fa70c221 RB |
2101 | /* If this is a reference based on a partitioned decl replace the |
2102 | base with a MEM_REF of the pointer representative we created | |
2103 | during stack slot partitioning. */ | |
2104 | if (attrs.expr | |
2105 | && VAR_P (base) | |
2106 | && ! is_global_var (base) | |
2107 | && cfun->gimple_df->decls_to_pointers != NULL) | |
2108 | { | |
2109 | tree *namep = cfun->gimple_df->decls_to_pointers->get (base); | |
2110 | if (namep) | |
2111 | { | |
2112 | attrs.expr = unshare_expr (attrs.expr); | |
2113 | tree *orig_base = &attrs.expr; | |
2114 | while (handled_component_p (*orig_base)) | |
2115 | orig_base = &TREE_OPERAND (*orig_base, 0); | |
2116 | tree aptrt = reference_alias_ptr_type (*orig_base); | |
2117 | *orig_base = build2 (MEM_REF, TREE_TYPE (*orig_base), *namep, | |
2118 | build_int_cst (aptrt, 0)); | |
2119 | } | |
2120 | } | |
2121 | ||
30b0317c RB |
2122 | /* Compute the alignment. */ |
2123 | unsigned int obj_align; | |
2124 | unsigned HOST_WIDE_INT obj_bitpos; | |
2125 | get_object_alignment_1 (t, &obj_align, &obj_bitpos); | |
d05d7551 RS |
2126 | unsigned int diff_align = known_alignment (obj_bitpos - bitpos); |
2127 | if (diff_align != 0) | |
2128 | obj_align = MIN (obj_align, diff_align); | |
30b0317c | 2129 | attrs.align = MAX (attrs.align, obj_align); |
8ac61af7 RK |
2130 | } |
2131 | ||
d05d7551 RS |
2132 | poly_uint64 const_size; |
2133 | if (poly_int_tree_p (new_size, &const_size)) | |
a787ccc3 RS |
2134 | { |
2135 | attrs.size_known_p = true; | |
d05d7551 | 2136 | attrs.size = const_size; |
a787ccc3 RS |
2137 | } |
2138 | ||
15c812e3 | 2139 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
2140 | bit position offset. Similarly, increase the size of the accessed |
2141 | object to contain the negative offset. */ | |
d05d7551 | 2142 | if (maybe_ne (apply_bitpos, 0)) |
8c317c5f | 2143 | { |
754c3d5d | 2144 | gcc_assert (attrs.offset_known_p); |
d05d7551 RS |
2145 | poly_int64 bytepos = bits_to_bytes_round_down (apply_bitpos); |
2146 | attrs.offset -= bytepos; | |
754c3d5d | 2147 | if (attrs.size_known_p) |
d05d7551 | 2148 | attrs.size += bytepos; |
8c317c5f | 2149 | } |
6f1087be | 2150 | |
8ac61af7 | 2151 | /* Now set the attributes we computed above. */ |
f18a7b25 | 2152 | attrs.addrspace = as; |
f12144dd | 2153 | set_mem_attrs (ref, &attrs); |
173b24b9 RK |
2154 | } |
2155 | ||
6f1087be | 2156 | void |
502b8322 | 2157 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
2158 | { |
2159 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
2160 | } | |
2161 | ||
173b24b9 RK |
2162 | /* Set the alias set of MEM to SET. */ |
2163 | ||
2164 | void | |
4862826d | 2165 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 2166 | { |
173b24b9 | 2167 | /* If the new and old alias sets don't conflict, something is wrong. */ |
77a74ed7 | 2168 | gcc_checking_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
d05d7551 | 2169 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2170 | attrs.alias = set; |
2171 | set_mem_attrs (mem, &attrs); | |
09e881c9 BE |
2172 | } |
2173 | ||
2174 | /* Set the address space of MEM to ADDRSPACE (target-defined). */ | |
2175 | ||
2176 | void | |
2177 | set_mem_addr_space (rtx mem, addr_space_t addrspace) | |
2178 | { | |
d05d7551 | 2179 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2180 | attrs.addrspace = addrspace; |
2181 | set_mem_attrs (mem, &attrs); | |
173b24b9 | 2182 | } |
738cc472 | 2183 | |
d022d93e | 2184 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
2185 | |
2186 | void | |
502b8322 | 2187 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 2188 | { |
d05d7551 | 2189 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2190 | attrs.align = align; |
2191 | set_mem_attrs (mem, &attrs); | |
738cc472 | 2192 | } |
1285011e | 2193 | |
998d7deb | 2194 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
2195 | |
2196 | void | |
502b8322 | 2197 | set_mem_expr (rtx mem, tree expr) |
1285011e | 2198 | { |
d05d7551 | 2199 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2200 | attrs.expr = expr; |
2201 | set_mem_attrs (mem, &attrs); | |
1285011e | 2202 | } |
998d7deb RH |
2203 | |
2204 | /* Set the offset of MEM to OFFSET. */ | |
2205 | ||
2206 | void | |
d05d7551 | 2207 | set_mem_offset (rtx mem, poly_int64 offset) |
998d7deb | 2208 | { |
d05d7551 | 2209 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d RS |
2210 | attrs.offset_known_p = true; |
2211 | attrs.offset = offset; | |
527210c4 RS |
2212 | set_mem_attrs (mem, &attrs); |
2213 | } | |
2214 | ||
2215 | /* Clear the offset of MEM. */ | |
2216 | ||
2217 | void | |
2218 | clear_mem_offset (rtx mem) | |
2219 | { | |
d05d7551 | 2220 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d | 2221 | attrs.offset_known_p = false; |
f12144dd | 2222 | set_mem_attrs (mem, &attrs); |
35aff10b AM |
2223 | } |
2224 | ||
2225 | /* Set the size of MEM to SIZE. */ | |
2226 | ||
2227 | void | |
d05d7551 | 2228 | set_mem_size (rtx mem, poly_int64 size) |
35aff10b | 2229 | { |
d05d7551 | 2230 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d RS |
2231 | attrs.size_known_p = true; |
2232 | attrs.size = size; | |
f5541398 RS |
2233 | set_mem_attrs (mem, &attrs); |
2234 | } | |
2235 | ||
2236 | /* Clear the size of MEM. */ | |
2237 | ||
2238 | void | |
2239 | clear_mem_size (rtx mem) | |
2240 | { | |
d05d7551 | 2241 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d | 2242 | attrs.size_known_p = false; |
f12144dd | 2243 | set_mem_attrs (mem, &attrs); |
998d7deb | 2244 | } |
173b24b9 | 2245 | \f |
738cc472 RK |
2246 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
2247 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
2248 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
23b33725 RS |
2249 | returned memory location is required to be valid. INPLACE is true if any |
2250 | changes can be made directly to MEMREF or false if MEMREF must be treated | |
2251 | as immutable. | |
2252 | ||
2253 | The memory attributes are not changed. */ | |
23b2ce53 | 2254 | |
738cc472 | 2255 | static rtx |
ef4bddc2 | 2256 | change_address_1 (rtx memref, machine_mode mode, rtx addr, int validate, |
23b33725 | 2257 | bool inplace) |
23b2ce53 | 2258 | { |
09e881c9 | 2259 | addr_space_t as; |
60564289 | 2260 | rtx new_rtx; |
23b2ce53 | 2261 | |
5b0264cb | 2262 | gcc_assert (MEM_P (memref)); |
09e881c9 | 2263 | as = MEM_ADDR_SPACE (memref); |
23b2ce53 RS |
2264 | if (mode == VOIDmode) |
2265 | mode = GET_MODE (memref); | |
2266 | if (addr == 0) | |
2267 | addr = XEXP (memref, 0); | |
a74ff877 | 2268 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
09e881c9 | 2269 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
a74ff877 | 2270 | return memref; |
23b2ce53 | 2271 | |
91c5ee5b VM |
2272 | /* Don't validate address for LRA. LRA can make the address valid |
2273 | by itself in most efficient way. */ | |
2274 | if (validate && !lra_in_progress) | |
23b2ce53 | 2275 | { |
f1ec5147 | 2276 | if (reload_in_progress || reload_completed) |
09e881c9 | 2277 | gcc_assert (memory_address_addr_space_p (mode, addr, as)); |
f1ec5147 | 2278 | else |
09e881c9 | 2279 | addr = memory_address_addr_space (mode, addr, as); |
23b2ce53 | 2280 | } |
750c9258 | 2281 | |
9b04c6a8 RK |
2282 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
2283 | return memref; | |
2284 | ||
23b33725 RS |
2285 | if (inplace) |
2286 | { | |
2287 | XEXP (memref, 0) = addr; | |
2288 | return memref; | |
2289 | } | |
2290 | ||
60564289 KG |
2291 | new_rtx = gen_rtx_MEM (mode, addr); |
2292 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
2293 | return new_rtx; | |
23b2ce53 | 2294 | } |
792760b9 | 2295 | |
738cc472 RK |
2296 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
2297 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
2298 | |
2299 | rtx | |
ef4bddc2 | 2300 | change_address (rtx memref, machine_mode mode, rtx addr) |
f4ef873c | 2301 | { |
23b33725 | 2302 | rtx new_rtx = change_address_1 (memref, mode, addr, 1, false); |
ef4bddc2 | 2303 | machine_mode mmode = GET_MODE (new_rtx); |
99b1c316 | 2304 | class mem_attrs *defattrs; |
4e44c1ef | 2305 | |
d05d7551 | 2306 | mem_attrs attrs (*get_mem_attrs (memref)); |
f12144dd | 2307 | defattrs = mode_mem_attrs[(int) mmode]; |
754c3d5d RS |
2308 | attrs.expr = NULL_TREE; |
2309 | attrs.offset_known_p = false; | |
2310 | attrs.size_known_p = defattrs->size_known_p; | |
f12144dd RS |
2311 | attrs.size = defattrs->size; |
2312 | attrs.align = defattrs->align; | |
c2f7bcc3 | 2313 | |
fdb1c7b3 | 2314 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 2315 | if (new_rtx == memref) |
4e44c1ef | 2316 | { |
f12144dd | 2317 | if (mem_attrs_eq_p (get_mem_attrs (memref), &attrs)) |
60564289 | 2318 | return new_rtx; |
4e44c1ef | 2319 | |
60564289 KG |
2320 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
2321 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 2322 | } |
fdb1c7b3 | 2323 | |
f12144dd | 2324 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2325 | return new_rtx; |
f4ef873c | 2326 | } |
792760b9 | 2327 | |
738cc472 RK |
2328 | /* Return a memory reference like MEMREF, but with its mode changed |
2329 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 | 2330 | nonzero, the memory address is forced to be valid. |
5ef0b50d EB |
2331 | If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS |
2332 | and the caller is responsible for adjusting MEMREF base register. | |
2333 | If ADJUST_OBJECT is zero, the underlying object associated with the | |
2334 | memory reference is left unchanged and the caller is responsible for | |
2335 | dealing with it. Otherwise, if the new memory reference is outside | |
5f2cbd0d RS |
2336 | the underlying object, even partially, then the object is dropped. |
2337 | SIZE, if nonzero, is the size of an access in cases where MODE | |
2338 | has no inherent size. */ | |
f1ec5147 RK |
2339 | |
2340 | rtx | |
d05d7551 | 2341 | adjust_address_1 (rtx memref, machine_mode mode, poly_int64 offset, |
5f2cbd0d | 2342 | int validate, int adjust_address, int adjust_object, |
d05d7551 | 2343 | poly_int64 size) |
f1ec5147 | 2344 | { |
823e3574 | 2345 | rtx addr = XEXP (memref, 0); |
60564289 | 2346 | rtx new_rtx; |
095a2d76 | 2347 | scalar_int_mode address_mode; |
99b1c316 | 2348 | class mem_attrs attrs (*get_mem_attrs (memref)), *defattrs; |
f12144dd | 2349 | unsigned HOST_WIDE_INT max_align; |
0207fa90 | 2350 | #ifdef POINTERS_EXTEND_UNSIGNED |
095a2d76 | 2351 | scalar_int_mode pointer_mode |
0207fa90 EB |
2352 | = targetm.addr_space.pointer_mode (attrs.addrspace); |
2353 | #endif | |
823e3574 | 2354 | |
ee88e690 EB |
2355 | /* VOIDmode means no mode change for change_address_1. */ |
2356 | if (mode == VOIDmode) | |
2357 | mode = GET_MODE (memref); | |
2358 | ||
5f2cbd0d RS |
2359 | /* Take the size of non-BLKmode accesses from the mode. */ |
2360 | defattrs = mode_mem_attrs[(int) mode]; | |
2361 | if (defattrs->size_known_p) | |
2362 | size = defattrs->size; | |
2363 | ||
fdb1c7b3 | 2364 | /* If there are no changes, just return the original memory reference. */ |
d05d7551 RS |
2365 | if (mode == GET_MODE (memref) |
2366 | && known_eq (offset, 0) | |
2367 | && (known_eq (size, 0) | |
2368 | || (attrs.size_known_p && known_eq (attrs.size, size))) | |
f12144dd RS |
2369 | && (!validate || memory_address_addr_space_p (mode, addr, |
2370 | attrs.addrspace))) | |
fdb1c7b3 JH |
2371 | return memref; |
2372 | ||
d14419e4 | 2373 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2374 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2375 | (plus (plus reg reg) const_int) -- so do this always. */ |
2376 | addr = copy_rtx (addr); | |
2377 | ||
a6fe9ed4 JM |
2378 | /* Convert a possibly large offset to a signed value within the |
2379 | range of the target address space. */ | |
372d6395 | 2380 | address_mode = get_address_mode (memref); |
d05d7551 | 2381 | offset = trunc_int_for_mode (offset, address_mode); |
a6fe9ed4 | 2382 | |
5ef0b50d | 2383 | if (adjust_address) |
4a78c787 RH |
2384 | { |
2385 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2386 | object, we can merge it into the LO_SUM. */ | |
d05d7551 RS |
2387 | if (GET_MODE (memref) != BLKmode |
2388 | && GET_CODE (addr) == LO_SUM | |
2389 | && known_in_range_p (offset, | |
2390 | 0, (GET_MODE_ALIGNMENT (GET_MODE (memref)) | |
2391 | / BITS_PER_UNIT))) | |
d4ebfa65 | 2392 | addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0), |
0a81f074 RS |
2393 | plus_constant (address_mode, |
2394 | XEXP (addr, 1), offset)); | |
0207fa90 EB |
2395 | #ifdef POINTERS_EXTEND_UNSIGNED |
2396 | /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid | |
2397 | in that mode, we merge it into the ZERO_EXTEND. We take advantage of | |
2398 | the fact that pointers are not allowed to overflow. */ | |
2399 | else if (POINTERS_EXTEND_UNSIGNED > 0 | |
2400 | && GET_CODE (addr) == ZERO_EXTEND | |
2401 | && GET_MODE (XEXP (addr, 0)) == pointer_mode | |
d05d7551 | 2402 | && known_eq (trunc_int_for_mode (offset, pointer_mode), offset)) |
0207fa90 EB |
2403 | addr = gen_rtx_ZERO_EXTEND (address_mode, |
2404 | plus_constant (pointer_mode, | |
2405 | XEXP (addr, 0), offset)); | |
2406 | #endif | |
4a78c787 | 2407 | else |
0a81f074 | 2408 | addr = plus_constant (address_mode, addr, offset); |
4a78c787 | 2409 | } |
823e3574 | 2410 | |
23b33725 | 2411 | new_rtx = change_address_1 (memref, mode, addr, validate, false); |
738cc472 | 2412 | |
09efeca1 PB |
2413 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2414 | but this would destroy memref's MEM_ATTRS. */ | |
d05d7551 | 2415 | if (new_rtx == memref && maybe_ne (offset, 0)) |
09efeca1 PB |
2416 | new_rtx = copy_rtx (new_rtx); |
2417 | ||
5ef0b50d EB |
2418 | /* Conservatively drop the object if we don't know where we start from. */ |
2419 | if (adjust_object && (!attrs.offset_known_p || !attrs.size_known_p)) | |
2420 | { | |
2421 | attrs.expr = NULL_TREE; | |
2422 | attrs.alias = 0; | |
2423 | } | |
2424 | ||
738cc472 RK |
2425 | /* Compute the new values of the memory attributes due to this adjustment. |
2426 | We add the offsets and update the alignment. */ | |
754c3d5d | 2427 | if (attrs.offset_known_p) |
5ef0b50d EB |
2428 | { |
2429 | attrs.offset += offset; | |
2430 | ||
2431 | /* Drop the object if the new left end is not within its bounds. */ | |
d05d7551 | 2432 | if (adjust_object && maybe_lt (attrs.offset, 0)) |
5ef0b50d EB |
2433 | { |
2434 | attrs.expr = NULL_TREE; | |
2435 | attrs.alias = 0; | |
2436 | } | |
2437 | } | |
738cc472 | 2438 | |
03bf2c23 RK |
2439 | /* Compute the new alignment by taking the MIN of the alignment and the |
2440 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2441 | if zero. */ | |
d05d7551 | 2442 | if (maybe_ne (offset, 0)) |
f12144dd | 2443 | { |
d05d7551 | 2444 | max_align = known_alignment (offset) * BITS_PER_UNIT; |
f12144dd RS |
2445 | attrs.align = MIN (attrs.align, max_align); |
2446 | } | |
738cc472 | 2447 | |
d05d7551 | 2448 | if (maybe_ne (size, 0)) |
754c3d5d | 2449 | { |
5ef0b50d | 2450 | /* Drop the object if the new right end is not within its bounds. */ |
d05d7551 | 2451 | if (adjust_object && maybe_gt (offset + size, attrs.size)) |
5ef0b50d EB |
2452 | { |
2453 | attrs.expr = NULL_TREE; | |
2454 | attrs.alias = 0; | |
2455 | } | |
754c3d5d | 2456 | attrs.size_known_p = true; |
5f2cbd0d | 2457 | attrs.size = size; |
754c3d5d RS |
2458 | } |
2459 | else if (attrs.size_known_p) | |
5ef0b50d | 2460 | { |
5f2cbd0d | 2461 | gcc_assert (!adjust_object); |
5ef0b50d | 2462 | attrs.size -= offset; |
5f2cbd0d RS |
2463 | /* ??? The store_by_pieces machinery generates negative sizes, |
2464 | so don't assert for that here. */ | |
5ef0b50d | 2465 | } |
10b76d73 | 2466 | |
f12144dd | 2467 | set_mem_attrs (new_rtx, &attrs); |
738cc472 | 2468 | |
60564289 | 2469 | return new_rtx; |
f1ec5147 RK |
2470 | } |
2471 | ||
630036c6 JJ |
2472 | /* Return a memory reference like MEMREF, but with its mode changed |
2473 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2474 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2475 | nonzero, the memory address is forced to be valid. */ |
2476 | ||
2477 | rtx | |
ef4bddc2 | 2478 | adjust_automodify_address_1 (rtx memref, machine_mode mode, rtx addr, |
d05d7551 | 2479 | poly_int64 offset, int validate) |
630036c6 | 2480 | { |
23b33725 | 2481 | memref = change_address_1 (memref, VOIDmode, addr, validate, false); |
5f2cbd0d | 2482 | return adjust_address_1 (memref, mode, offset, validate, 0, 0, 0); |
630036c6 JJ |
2483 | } |
2484 | ||
8ac61af7 RK |
2485 | /* Return a memory reference like MEMREF, but whose address is changed by |
2486 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2487 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2488 | |
2489 | rtx | |
502b8322 | 2490 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2491 | { |
60564289 | 2492 | rtx new_rtx, addr = XEXP (memref, 0); |
ef4bddc2 | 2493 | machine_mode address_mode; |
99b1c316 | 2494 | class mem_attrs *defattrs; |
e3c8ea67 | 2495 | |
d05d7551 | 2496 | mem_attrs attrs (*get_mem_attrs (memref)); |
372d6395 | 2497 | address_mode = get_address_mode (memref); |
d4ebfa65 | 2498 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 | 2499 | |
68252e27 | 2500 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2501 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2502 | |
2503 | However, if we did go and rearrange things, we can wind up not | |
2504 | being able to recognize the magic around pic_offset_table_rtx. | |
2505 | This stuff is fragile, and is yet another example of why it is | |
2506 | bad to expose PIC machinery too early. */ | |
f12144dd RS |
2507 | if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, |
2508 | attrs.addrspace) | |
e3c8ea67 RH |
2509 | && GET_CODE (addr) == PLUS |
2510 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2511 | { | |
2512 | addr = force_reg (GET_MODE (addr), addr); | |
d4ebfa65 | 2513 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 RH |
2514 | } |
2515 | ||
60564289 | 2516 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
23b33725 | 2517 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1, false); |
0d4903b8 | 2518 | |
fdb1c7b3 | 2519 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2520 | if (new_rtx == memref) |
2521 | return new_rtx; | |
fdb1c7b3 | 2522 | |
0d4903b8 RK |
2523 | /* Update the alignment to reflect the offset. Reset the offset, which |
2524 | we don't know. */ | |
754c3d5d RS |
2525 | defattrs = mode_mem_attrs[(int) GET_MODE (new_rtx)]; |
2526 | attrs.offset_known_p = false; | |
2527 | attrs.size_known_p = defattrs->size_known_p; | |
2528 | attrs.size = defattrs->size; | |
f12144dd RS |
2529 | attrs.align = MIN (attrs.align, pow2 * BITS_PER_UNIT); |
2530 | set_mem_attrs (new_rtx, &attrs); | |
60564289 | 2531 | return new_rtx; |
0d4903b8 | 2532 | } |
68252e27 | 2533 | |
792760b9 RK |
2534 | /* Return a memory reference like MEMREF, but with its address changed to |
2535 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2536 | to is the same, just the form of the address is being changed, such as | |
23b33725 RS |
2537 | by putting something into a register. INPLACE is true if any changes |
2538 | can be made directly to MEMREF or false if MEMREF must be treated as | |
2539 | immutable. */ | |
792760b9 RK |
2540 | |
2541 | rtx | |
23b33725 | 2542 | replace_equiv_address (rtx memref, rtx addr, bool inplace) |
792760b9 | 2543 | { |
738cc472 RK |
2544 | /* change_address_1 copies the memory attribute structure without change |
2545 | and that's exactly what we want here. */ | |
40c0668b | 2546 | update_temp_slot_address (XEXP (memref, 0), addr); |
23b33725 | 2547 | return change_address_1 (memref, VOIDmode, addr, 1, inplace); |
792760b9 | 2548 | } |
738cc472 | 2549 | |
f1ec5147 RK |
2550 | /* Likewise, but the reference is not required to be valid. */ |
2551 | ||
2552 | rtx | |
23b33725 | 2553 | replace_equiv_address_nv (rtx memref, rtx addr, bool inplace) |
f1ec5147 | 2554 | { |
23b33725 | 2555 | return change_address_1 (memref, VOIDmode, addr, 0, inplace); |
f1ec5147 | 2556 | } |
e7dfe4bb RH |
2557 | |
2558 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2559 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2560 | cannot issue QImode memory operations and have to use SImode memory | |
2561 | operations plus masking logic. */ | |
2562 | ||
2563 | rtx | |
d05d7551 | 2564 | widen_memory_access (rtx memref, machine_mode mode, poly_int64 offset) |
e7dfe4bb | 2565 | { |
5f2cbd0d | 2566 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1, 0, 0); |
cf098191 | 2567 | poly_uint64 size = GET_MODE_SIZE (mode); |
e7dfe4bb | 2568 | |
fdb1c7b3 | 2569 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2570 | if (new_rtx == memref) |
2571 | return new_rtx; | |
fdb1c7b3 | 2572 | |
d05d7551 | 2573 | mem_attrs attrs (*get_mem_attrs (new_rtx)); |
f12144dd | 2574 | |
e7dfe4bb RH |
2575 | /* If we don't know what offset we were at within the expression, then |
2576 | we can't know if we've overstepped the bounds. */ | |
754c3d5d | 2577 | if (! attrs.offset_known_p) |
f12144dd | 2578 | attrs.expr = NULL_TREE; |
e7dfe4bb | 2579 | |
f12144dd | 2580 | while (attrs.expr) |
e7dfe4bb | 2581 | { |
f12144dd | 2582 | if (TREE_CODE (attrs.expr) == COMPONENT_REF) |
e7dfe4bb | 2583 | { |
f12144dd RS |
2584 | tree field = TREE_OPERAND (attrs.expr, 1); |
2585 | tree offset = component_ref_field_offset (attrs.expr); | |
e7dfe4bb RH |
2586 | |
2587 | if (! DECL_SIZE_UNIT (field)) | |
2588 | { | |
f12144dd | 2589 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2590 | break; |
2591 | } | |
2592 | ||
2593 | /* Is the field at least as large as the access? If so, ok, | |
2594 | otherwise strip back to the containing structure. */ | |
d05d7551 RS |
2595 | if (poly_int_tree_p (DECL_SIZE_UNIT (field)) |
2596 | && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (field)), size) | |
2597 | && known_ge (attrs.offset, 0)) | |
e7dfe4bb RH |
2598 | break; |
2599 | ||
d05d7551 RS |
2600 | poly_uint64 suboffset; |
2601 | if (!poly_int_tree_p (offset, &suboffset)) | |
e7dfe4bb | 2602 | { |
f12144dd | 2603 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2604 | break; |
2605 | } | |
2606 | ||
f12144dd | 2607 | attrs.expr = TREE_OPERAND (attrs.expr, 0); |
d05d7551 | 2608 | attrs.offset += suboffset; |
ae7e9ddd | 2609 | attrs.offset += (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field)) |
754c3d5d | 2610 | / BITS_PER_UNIT); |
e7dfe4bb RH |
2611 | } |
2612 | /* Similarly for the decl. */ | |
f12144dd RS |
2613 | else if (DECL_P (attrs.expr) |
2614 | && DECL_SIZE_UNIT (attrs.expr) | |
d05d7551 RS |
2615 | && poly_int_tree_p (DECL_SIZE_UNIT (attrs.expr)) |
2616 | && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (attrs.expr)), | |
2617 | size) | |
2618 | && known_ge (attrs.offset, 0)) | |
e7dfe4bb RH |
2619 | break; |
2620 | else | |
2621 | { | |
2622 | /* The widened memory access overflows the expression, which means | |
2623 | that it could alias another expression. Zap it. */ | |
f12144dd | 2624 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2625 | break; |
2626 | } | |
2627 | } | |
2628 | ||
f12144dd | 2629 | if (! attrs.expr) |
754c3d5d | 2630 | attrs.offset_known_p = false; |
e7dfe4bb RH |
2631 | |
2632 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2633 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
f12144dd | 2634 | attrs.alias = 0; |
754c3d5d RS |
2635 | attrs.size_known_p = true; |
2636 | attrs.size = size; | |
f12144dd | 2637 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2638 | return new_rtx; |
e7dfe4bb | 2639 | } |
23b2ce53 | 2640 | \f |
f6129d66 RH |
2641 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2642 | static GTY(()) tree spill_slot_decl; | |
2643 | ||
3d7e23f6 RH |
2644 | tree |
2645 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2646 | { |
2647 | tree d = spill_slot_decl; | |
2648 | rtx rd; | |
2649 | ||
3d7e23f6 | 2650 | if (d || !force_build_p) |
f6129d66 RH |
2651 | return d; |
2652 | ||
c2255bc4 AH |
2653 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2654 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2655 | DECL_ARTIFICIAL (d) = 1; |
2656 | DECL_IGNORED_P (d) = 1; | |
2657 | TREE_USED (d) = 1; | |
f6129d66 RH |
2658 | spill_slot_decl = d; |
2659 | ||
2660 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2661 | MEM_NOTRAP_P (rd) = 1; | |
d05d7551 | 2662 | mem_attrs attrs (*mode_mem_attrs[(int) BLKmode]); |
f12144dd RS |
2663 | attrs.alias = new_alias_set (); |
2664 | attrs.expr = d; | |
2665 | set_mem_attrs (rd, &attrs); | |
f6129d66 RH |
2666 | SET_DECL_RTL (d, rd); |
2667 | ||
2668 | return d; | |
2669 | } | |
2670 | ||
2671 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2672 | attributes as appropriate for a register allocator spill slot. | |
2673 | These slots are not aliasable by other memory. We arrange for | |
2674 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2675 | work properly in the case of shared spill slots. */ | |
2676 | ||
2677 | void | |
2678 | set_mem_attrs_for_spill (rtx mem) | |
2679 | { | |
f12144dd | 2680 | rtx addr; |
f6129d66 | 2681 | |
d05d7551 | 2682 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2683 | attrs.expr = get_spill_slot_decl (true); |
2684 | attrs.alias = MEM_ALIAS_SET (DECL_RTL (attrs.expr)); | |
2685 | attrs.addrspace = ADDR_SPACE_GENERIC; | |
f6129d66 RH |
2686 | |
2687 | /* We expect the incoming memory to be of the form: | |
2688 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2689 | with perhaps the plus missing for offset = 0. */ | |
2690 | addr = XEXP (mem, 0); | |
754c3d5d | 2691 | attrs.offset_known_p = true; |
d05d7551 | 2692 | strip_offset (addr, &attrs.offset); |
f6129d66 | 2693 | |
f12144dd | 2694 | set_mem_attrs (mem, &attrs); |
f6129d66 RH |
2695 | MEM_NOTRAP_P (mem) = 1; |
2696 | } | |
2697 | \f | |
23b2ce53 RS |
2698 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2699 | ||
7dcc3ab5 | 2700 | rtx_code_label * |
502b8322 | 2701 | gen_label_rtx (void) |
23b2ce53 | 2702 | { |
7dcc3ab5 DM |
2703 | return as_a <rtx_code_label *> ( |
2704 | gen_rtx_CODE_LABEL (VOIDmode, NULL_RTX, NULL_RTX, | |
2705 | NULL, label_num++, NULL)); | |
23b2ce53 RS |
2706 | } |
2707 | \f | |
2708 | /* For procedure integration. */ | |
2709 | ||
23b2ce53 | 2710 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2711 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2712 | Used for an inline-procedure after copying the insn chain. */ |
2713 | ||
2714 | void | |
fee3e72c | 2715 | set_new_first_and_last_insn (rtx_insn *first, rtx_insn *last) |
23b2ce53 | 2716 | { |
fee3e72c | 2717 | rtx_insn *insn; |
86fe05e0 | 2718 | |
5936d944 JH |
2719 | set_first_insn (first); |
2720 | set_last_insn (last); | |
86fe05e0 RK |
2721 | cur_insn_uid = 0; |
2722 | ||
028d4092 | 2723 | if (param_min_nondebug_insn_uid || MAY_HAVE_DEBUG_INSNS) |
b5b8b0ac AO |
2724 | { |
2725 | int debug_count = 0; | |
2726 | ||
028d4092 | 2727 | cur_insn_uid = param_min_nondebug_insn_uid - 1; |
b5b8b0ac AO |
2728 | cur_debug_insn_uid = 0; |
2729 | ||
2730 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
028d4092 | 2731 | if (INSN_UID (insn) < param_min_nondebug_insn_uid) |
b5b8b0ac AO |
2732 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); |
2733 | else | |
2734 | { | |
2735 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2736 | if (DEBUG_INSN_P (insn)) | |
2737 | debug_count++; | |
2738 | } | |
2739 | ||
2740 | if (debug_count) | |
028d4092 | 2741 | cur_debug_insn_uid = param_min_nondebug_insn_uid + debug_count; |
b5b8b0ac AO |
2742 | else |
2743 | cur_debug_insn_uid++; | |
2744 | } | |
2745 | else | |
2746 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2747 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2748 | |
2749 | cur_insn_uid++; | |
23b2ce53 | 2750 | } |
23b2ce53 | 2751 | \f |
750c9258 | 2752 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2753 | structure. This routine should only be called once. */ |
23b2ce53 | 2754 | |
fd743bc1 | 2755 | static void |
6bb9bf63 | 2756 | unshare_all_rtl_1 (rtx_insn *insn) |
23b2ce53 | 2757 | { |
d1b81779 | 2758 | /* Unshare just about everything else. */ |
2c07f13b | 2759 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2760 | |
23b2ce53 RS |
2761 | /* Make sure the addresses of stack slots found outside the insn chain |
2762 | (such as, in DECL_RTL of a variable) are not shared | |
2763 | with the insn chain. | |
2764 | ||
2765 | This special care is necessary when the stack slot MEM does not | |
2766 | actually appear in the insn chain. If it does appear, its address | |
2767 | is unshared from all else at that point. */ | |
8c39f8ae TS |
2768 | unsigned int i; |
2769 | rtx temp; | |
2770 | FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp) | |
2771 | (*stack_slot_list)[i] = copy_rtx_if_shared (temp); | |
23b2ce53 RS |
2772 | } |
2773 | ||
750c9258 | 2774 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2775 | structure, again. This is a fairly expensive thing to do so it |
2776 | should be done sparingly. */ | |
2777 | ||
2778 | void | |
6bb9bf63 | 2779 | unshare_all_rtl_again (rtx_insn *insn) |
d1b81779 | 2780 | { |
6bb9bf63 | 2781 | rtx_insn *p; |
624c87aa RE |
2782 | tree decl; |
2783 | ||
d1b81779 | 2784 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2785 | if (INSN_P (p)) |
d1b81779 GK |
2786 | { |
2787 | reset_used_flags (PATTERN (p)); | |
2788 | reset_used_flags (REG_NOTES (p)); | |
776bebcd JJ |
2789 | if (CALL_P (p)) |
2790 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (p)); | |
d1b81779 | 2791 | } |
624c87aa | 2792 | |
2d4aecb3 | 2793 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2794 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2795 | |
624c87aa | 2796 | /* Make sure that virtual parameters are not shared. */ |
910ad8de | 2797 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) |
5eb2a9f2 | 2798 | set_used_flags (DECL_RTL (decl)); |
624c87aa | 2799 | |
8c39f8ae TS |
2800 | rtx temp; |
2801 | unsigned int i; | |
2802 | FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp) | |
2803 | reset_used_flags (temp); | |
624c87aa | 2804 | |
b4aaa77b | 2805 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2806 | } |
2807 | ||
c2924966 | 2808 | unsigned int |
fd743bc1 PB |
2809 | unshare_all_rtl (void) |
2810 | { | |
b4aaa77b | 2811 | unshare_all_rtl_1 (get_insns ()); |
60ebe8ce JJ |
2812 | |
2813 | for (tree decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) | |
2814 | { | |
2815 | if (DECL_RTL_SET_P (decl)) | |
2816 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); | |
2817 | DECL_INCOMING_RTL (decl) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl)); | |
2818 | } | |
2819 | ||
c2924966 | 2820 | return 0; |
d1b81779 GK |
2821 | } |
2822 | ||
ef330312 | 2823 | |
2c07f13b JH |
2824 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2825 | Recursively does the same for subexpressions. */ | |
2826 | ||
2827 | static void | |
2828 | verify_rtx_sharing (rtx orig, rtx insn) | |
2829 | { | |
2830 | rtx x = orig; | |
2831 | int i; | |
2832 | enum rtx_code code; | |
2833 | const char *format_ptr; | |
2834 | ||
2835 | if (x == 0) | |
2836 | return; | |
2837 | ||
2838 | code = GET_CODE (x); | |
2839 | ||
2840 | /* These types may be freely shared. */ | |
2841 | ||
2842 | switch (code) | |
2843 | { | |
2844 | case REG: | |
0ca5af51 AO |
2845 | case DEBUG_EXPR: |
2846 | case VALUE: | |
d8116890 | 2847 | CASE_CONST_ANY: |
2c07f13b JH |
2848 | case SYMBOL_REF: |
2849 | case LABEL_REF: | |
2850 | case CODE_LABEL: | |
2851 | case PC: | |
3810076b | 2852 | case RETURN: |
26898771 | 2853 | case SIMPLE_RETURN: |
2c07f13b | 2854 | case SCRATCH: |
3e89ed8d | 2855 | /* SCRATCH must be shared because they represent distinct values. */ |
c5c5ba89 | 2856 | return; |
3e89ed8d | 2857 | case CLOBBER: |
bd1cd0d0 | 2858 | /* Share clobbers of hard registers, but do not share pseudo reg |
c5c5ba89 JH |
2859 | clobbers or clobbers of hard registers that originated as pseudos. |
2860 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
2861 | if (REG_P (XEXP (x, 0)) |
2862 | && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0))) | |
2863 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0)))) | |
3e89ed8d JH |
2864 | return; |
2865 | break; | |
2c07f13b JH |
2866 | |
2867 | case CONST: | |
6fb5fa3c | 2868 | if (shared_const_p (orig)) |
2c07f13b JH |
2869 | return; |
2870 | break; | |
2871 | ||
2872 | case MEM: | |
2873 | /* A MEM is allowed to be shared if its address is constant. */ | |
2874 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2875 | || reload_completed || reload_in_progress) | |
2876 | return; | |
2877 | ||
2878 | break; | |
2879 | ||
2880 | default: | |
2881 | break; | |
2882 | } | |
2883 | ||
2884 | /* This rtx may not be shared. If it has already been seen, | |
2885 | replace it with a copy of itself. */ | |
b2b29377 | 2886 | if (flag_checking && RTX_FLAG (x, used)) |
2c07f13b | 2887 | { |
ab532386 | 2888 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2889 | debug_rtx (insn); |
ab532386 | 2890 | error ("shared rtx"); |
2c07f13b | 2891 | debug_rtx (x); |
ab532386 | 2892 | internal_error ("internal consistency failure"); |
2c07f13b | 2893 | } |
1a2caa7a | 2894 | gcc_assert (!RTX_FLAG (x, used)); |
b8698a0f | 2895 | |
2c07f13b JH |
2896 | RTX_FLAG (x, used) = 1; |
2897 | ||
6614fd40 | 2898 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2899 | |
2900 | format_ptr = GET_RTX_FORMAT (code); | |
2901 | ||
2902 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2903 | { | |
2904 | switch (*format_ptr++) | |
2905 | { | |
2906 | case 'e': | |
2907 | verify_rtx_sharing (XEXP (x, i), insn); | |
2908 | break; | |
2909 | ||
2910 | case 'E': | |
2911 | if (XVEC (x, i) != NULL) | |
2912 | { | |
2913 | int j; | |
2914 | int len = XVECLEN (x, i); | |
2915 | ||
2916 | for (j = 0; j < len; j++) | |
2917 | { | |
1a2caa7a NS |
2918 | /* We allow sharing of ASM_OPERANDS inside single |
2919 | instruction. */ | |
2c07f13b | 2920 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2921 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2922 | == ASM_OPERANDS)) | |
2c07f13b JH |
2923 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2924 | else | |
2925 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2926 | } | |
2927 | } | |
2928 | break; | |
2929 | } | |
2930 | } | |
2931 | return; | |
2932 | } | |
2933 | ||
0e0f87d4 SB |
2934 | /* Reset used-flags for INSN. */ |
2935 | ||
2936 | static void | |
2937 | reset_insn_used_flags (rtx insn) | |
2938 | { | |
2939 | gcc_assert (INSN_P (insn)); | |
2940 | reset_used_flags (PATTERN (insn)); | |
2941 | reset_used_flags (REG_NOTES (insn)); | |
2942 | if (CALL_P (insn)) | |
2943 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn)); | |
2944 | } | |
2945 | ||
a24243a0 | 2946 | /* Go through all the RTL insn bodies and clear all the USED bits. */ |
2c07f13b | 2947 | |
a24243a0 AK |
2948 | static void |
2949 | reset_all_used_flags (void) | |
2c07f13b | 2950 | { |
dc01c3d1 | 2951 | rtx_insn *p; |
2c07f13b JH |
2952 | |
2953 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2954 | if (INSN_P (p)) | |
2955 | { | |
0e0f87d4 SB |
2956 | rtx pat = PATTERN (p); |
2957 | if (GET_CODE (pat) != SEQUENCE) | |
2958 | reset_insn_used_flags (p); | |
2959 | else | |
2954a813 | 2960 | { |
0e0f87d4 SB |
2961 | gcc_assert (REG_NOTES (p) == NULL); |
2962 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
2963 | { |
2964 | rtx insn = XVECEXP (pat, 0, i); | |
2965 | if (INSN_P (insn)) | |
2966 | reset_insn_used_flags (insn); | |
2967 | } | |
2954a813 | 2968 | } |
2c07f13b | 2969 | } |
a24243a0 AK |
2970 | } |
2971 | ||
0e0f87d4 SB |
2972 | /* Verify sharing in INSN. */ |
2973 | ||
2974 | static void | |
2975 | verify_insn_sharing (rtx insn) | |
2976 | { | |
2977 | gcc_assert (INSN_P (insn)); | |
4b498f72 JJ |
2978 | verify_rtx_sharing (PATTERN (insn), insn); |
2979 | verify_rtx_sharing (REG_NOTES (insn), insn); | |
0e0f87d4 | 2980 | if (CALL_P (insn)) |
4b498f72 | 2981 | verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn), insn); |
0e0f87d4 SB |
2982 | } |
2983 | ||
a24243a0 AK |
2984 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2985 | sharing in between the subexpressions. */ | |
2986 | ||
2987 | DEBUG_FUNCTION void | |
2988 | verify_rtl_sharing (void) | |
2989 | { | |
dc01c3d1 | 2990 | rtx_insn *p; |
a24243a0 AK |
2991 | |
2992 | timevar_push (TV_VERIFY_RTL_SHARING); | |
2993 | ||
2994 | reset_all_used_flags (); | |
2c07f13b JH |
2995 | |
2996 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2997 | if (INSN_P (p)) | |
2998 | { | |
0e0f87d4 SB |
2999 | rtx pat = PATTERN (p); |
3000 | if (GET_CODE (pat) != SEQUENCE) | |
3001 | verify_insn_sharing (p); | |
3002 | else | |
3003 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
3004 | { |
3005 | rtx insn = XVECEXP (pat, 0, i); | |
3006 | if (INSN_P (insn)) | |
3007 | verify_insn_sharing (insn); | |
3008 | } | |
2c07f13b | 3009 | } |
a222c01a | 3010 | |
a24243a0 AK |
3011 | reset_all_used_flags (); |
3012 | ||
a222c01a | 3013 | timevar_pop (TV_VERIFY_RTL_SHARING); |
2c07f13b JH |
3014 | } |
3015 | ||
d1b81779 GK |
3016 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
3017 | Assumes the mark bits are cleared at entry. */ | |
3018 | ||
2c07f13b | 3019 | void |
dc01c3d1 | 3020 | unshare_all_rtl_in_chain (rtx_insn *insn) |
d1b81779 GK |
3021 | { |
3022 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 3023 | if (INSN_P (insn)) |
d1b81779 GK |
3024 | { |
3025 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
3026 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
776bebcd JJ |
3027 | if (CALL_P (insn)) |
3028 | CALL_INSN_FUNCTION_USAGE (insn) | |
3029 | = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn)); | |
d1b81779 GK |
3030 | } |
3031 | } | |
3032 | ||
2d4aecb3 | 3033 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
3034 | shared. We never replace the DECL_RTLs themselves with a copy, |
3035 | but expressions mentioned into a DECL_RTL cannot be shared with | |
3036 | expressions in the instruction stream. | |
3037 | ||
3038 | Note that reload may convert pseudo registers into memories in-place. | |
3039 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
3040 | reset the used flags on MEMs in the instruction stream, we must set | |
3041 | them again on MEMs that appear in DECL_RTLs. */ | |
3042 | ||
2d4aecb3 | 3043 | static void |
5eb2a9f2 | 3044 | set_used_decls (tree blk) |
2d4aecb3 AO |
3045 | { |
3046 | tree t; | |
3047 | ||
3048 | /* Mark decls. */ | |
910ad8de | 3049 | for (t = BLOCK_VARS (blk); t; t = DECL_CHAIN (t)) |
19e7881c | 3050 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 3051 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
3052 | |
3053 | /* Now process sub-blocks. */ | |
87caf699 | 3054 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 3055 | set_used_decls (t); |
2d4aecb3 AO |
3056 | } |
3057 | ||
23b2ce53 | 3058 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
3059 | Recursively does the same for subexpressions. Uses |
3060 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
3061 | |
3062 | rtx | |
502b8322 | 3063 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 3064 | { |
32b32b16 AP |
3065 | copy_rtx_if_shared_1 (&orig); |
3066 | return orig; | |
3067 | } | |
3068 | ||
ff954f39 AP |
3069 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
3070 | use. Recursively does the same for subexpressions. */ | |
3071 | ||
32b32b16 AP |
3072 | static void |
3073 | copy_rtx_if_shared_1 (rtx *orig1) | |
3074 | { | |
3075 | rtx x; | |
b3694847 SS |
3076 | int i; |
3077 | enum rtx_code code; | |
32b32b16 | 3078 | rtx *last_ptr; |
b3694847 | 3079 | const char *format_ptr; |
23b2ce53 | 3080 | int copied = 0; |
32b32b16 AP |
3081 | int length; |
3082 | ||
3083 | /* Repeat is used to turn tail-recursion into iteration. */ | |
3084 | repeat: | |
3085 | x = *orig1; | |
23b2ce53 RS |
3086 | |
3087 | if (x == 0) | |
32b32b16 | 3088 | return; |
23b2ce53 RS |
3089 | |
3090 | code = GET_CODE (x); | |
3091 | ||
3092 | /* These types may be freely shared. */ | |
3093 | ||
3094 | switch (code) | |
3095 | { | |
3096 | case REG: | |
0ca5af51 AO |
3097 | case DEBUG_EXPR: |
3098 | case VALUE: | |
d8116890 | 3099 | CASE_CONST_ANY: |
23b2ce53 | 3100 | case SYMBOL_REF: |
2c07f13b | 3101 | case LABEL_REF: |
23b2ce53 RS |
3102 | case CODE_LABEL: |
3103 | case PC: | |
276e0224 | 3104 | case RETURN: |
26898771 | 3105 | case SIMPLE_RETURN: |
23b2ce53 | 3106 | case SCRATCH: |
0f41302f | 3107 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 3108 | return; |
3e89ed8d | 3109 | case CLOBBER: |
bd1cd0d0 | 3110 | /* Share clobbers of hard registers, but do not share pseudo reg |
c5c5ba89 JH |
3111 | clobbers or clobbers of hard registers that originated as pseudos. |
3112 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
3113 | if (REG_P (XEXP (x, 0)) |
3114 | && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0))) | |
3115 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0)))) | |
3e89ed8d JH |
3116 | return; |
3117 | break; | |
23b2ce53 | 3118 | |
b851ea09 | 3119 | case CONST: |
6fb5fa3c | 3120 | if (shared_const_p (x)) |
32b32b16 | 3121 | return; |
b851ea09 RK |
3122 | break; |
3123 | ||
b5b8b0ac | 3124 | case DEBUG_INSN: |
23b2ce53 RS |
3125 | case INSN: |
3126 | case JUMP_INSN: | |
3127 | case CALL_INSN: | |
3128 | case NOTE: | |
23b2ce53 RS |
3129 | case BARRIER: |
3130 | /* The chain of insns is not being copied. */ | |
32b32b16 | 3131 | return; |
23b2ce53 | 3132 | |
e9a25f70 JL |
3133 | default: |
3134 | break; | |
23b2ce53 RS |
3135 | } |
3136 | ||
3137 | /* This rtx may not be shared. If it has already been seen, | |
3138 | replace it with a copy of itself. */ | |
3139 | ||
2adc7f12 | 3140 | if (RTX_FLAG (x, used)) |
23b2ce53 | 3141 | { |
aacd3885 | 3142 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
3143 | copied = 1; |
3144 | } | |
2adc7f12 | 3145 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
3146 | |
3147 | /* Now scan the subexpressions recursively. | |
3148 | We can store any replaced subexpressions directly into X | |
3149 | since we know X is not shared! Any vectors in X | |
3150 | must be copied if X was copied. */ | |
3151 | ||
3152 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
3153 | length = GET_RTX_LENGTH (code); |
3154 | last_ptr = NULL; | |
b8698a0f | 3155 | |
32b32b16 | 3156 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3157 | { |
3158 | switch (*format_ptr++) | |
3159 | { | |
3160 | case 'e': | |
32b32b16 AP |
3161 | if (last_ptr) |
3162 | copy_rtx_if_shared_1 (last_ptr); | |
3163 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
3164 | break; |
3165 | ||
3166 | case 'E': | |
3167 | if (XVEC (x, i) != NULL) | |
3168 | { | |
b3694847 | 3169 | int j; |
f0722107 | 3170 | int len = XVECLEN (x, i); |
b8698a0f | 3171 | |
6614fd40 KH |
3172 | /* Copy the vector iff I copied the rtx and the length |
3173 | is nonzero. */ | |
f0722107 | 3174 | if (copied && len > 0) |
8f985ec4 | 3175 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
b8698a0f | 3176 | |
5d3cc252 | 3177 | /* Call recursively on all inside the vector. */ |
f0722107 | 3178 | for (j = 0; j < len; j++) |
32b32b16 AP |
3179 | { |
3180 | if (last_ptr) | |
3181 | copy_rtx_if_shared_1 (last_ptr); | |
3182 | last_ptr = &XVECEXP (x, i, j); | |
3183 | } | |
23b2ce53 RS |
3184 | } |
3185 | break; | |
3186 | } | |
3187 | } | |
32b32b16 AP |
3188 | *orig1 = x; |
3189 | if (last_ptr) | |
3190 | { | |
3191 | orig1 = last_ptr; | |
3192 | goto repeat; | |
3193 | } | |
3194 | return; | |
23b2ce53 RS |
3195 | } |
3196 | ||
76369a82 | 3197 | /* Set the USED bit in X and its non-shareable subparts to FLAG. */ |
23b2ce53 | 3198 | |
76369a82 NF |
3199 | static void |
3200 | mark_used_flags (rtx x, int flag) | |
23b2ce53 | 3201 | { |
b3694847 SS |
3202 | int i, j; |
3203 | enum rtx_code code; | |
3204 | const char *format_ptr; | |
32b32b16 | 3205 | int length; |
23b2ce53 | 3206 | |
32b32b16 AP |
3207 | /* Repeat is used to turn tail-recursion into iteration. */ |
3208 | repeat: | |
23b2ce53 RS |
3209 | if (x == 0) |
3210 | return; | |
3211 | ||
3212 | code = GET_CODE (x); | |
3213 | ||
9faa82d8 | 3214 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
3215 | for them. */ |
3216 | ||
3217 | switch (code) | |
3218 | { | |
3219 | case REG: | |
0ca5af51 AO |
3220 | case DEBUG_EXPR: |
3221 | case VALUE: | |
d8116890 | 3222 | CASE_CONST_ANY: |
23b2ce53 RS |
3223 | case SYMBOL_REF: |
3224 | case CODE_LABEL: | |
3225 | case PC: | |
276e0224 | 3226 | case RETURN: |
26898771 | 3227 | case SIMPLE_RETURN: |
23b2ce53 RS |
3228 | return; |
3229 | ||
b5b8b0ac | 3230 | case DEBUG_INSN: |
23b2ce53 RS |
3231 | case INSN: |
3232 | case JUMP_INSN: | |
3233 | case CALL_INSN: | |
3234 | case NOTE: | |
3235 | case LABEL_REF: | |
3236 | case BARRIER: | |
3237 | /* The chain of insns is not being copied. */ | |
3238 | return; | |
750c9258 | 3239 | |
e9a25f70 JL |
3240 | default: |
3241 | break; | |
23b2ce53 RS |
3242 | } |
3243 | ||
76369a82 | 3244 | RTX_FLAG (x, used) = flag; |
23b2ce53 RS |
3245 | |
3246 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 | 3247 | length = GET_RTX_LENGTH (code); |
b8698a0f | 3248 | |
32b32b16 | 3249 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3250 | { |
3251 | switch (*format_ptr++) | |
3252 | { | |
3253 | case 'e': | |
32b32b16 AP |
3254 | if (i == length-1) |
3255 | { | |
3256 | x = XEXP (x, i); | |
3257 | goto repeat; | |
3258 | } | |
76369a82 | 3259 | mark_used_flags (XEXP (x, i), flag); |
23b2ce53 RS |
3260 | break; |
3261 | ||
3262 | case 'E': | |
3263 | for (j = 0; j < XVECLEN (x, i); j++) | |
76369a82 | 3264 | mark_used_flags (XVECEXP (x, i, j), flag); |
23b2ce53 RS |
3265 | break; |
3266 | } | |
3267 | } | |
3268 | } | |
2c07f13b | 3269 | |
76369a82 | 3270 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used |
2c07f13b JH |
3271 | to look for shared sub-parts. */ |
3272 | ||
3273 | void | |
76369a82 | 3274 | reset_used_flags (rtx x) |
2c07f13b | 3275 | { |
76369a82 NF |
3276 | mark_used_flags (x, 0); |
3277 | } | |
2c07f13b | 3278 | |
76369a82 NF |
3279 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used |
3280 | to look for shared sub-parts. */ | |
2c07f13b | 3281 | |
76369a82 NF |
3282 | void |
3283 | set_used_flags (rtx x) | |
3284 | { | |
3285 | mark_used_flags (x, 1); | |
2c07f13b | 3286 | } |
23b2ce53 RS |
3287 | \f |
3288 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
3289 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
3290 | OTHER must be valid as a SET_DEST. */ | |
3291 | ||
3292 | rtx | |
502b8322 | 3293 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
3294 | { |
3295 | while (1) | |
3296 | switch (GET_CODE (other)) | |
3297 | { | |
3298 | case SUBREG: | |
3299 | other = SUBREG_REG (other); | |
3300 | break; | |
3301 | case STRICT_LOW_PART: | |
3302 | case SIGN_EXTEND: | |
3303 | case ZERO_EXTEND: | |
3304 | other = XEXP (other, 0); | |
3305 | break; | |
3306 | default: | |
3307 | goto done; | |
3308 | } | |
3309 | done: | |
3c0cb5de | 3310 | if ((MEM_P (other) |
23b2ce53 | 3311 | && ! CONSTANT_P (x) |
f8cfc6aa | 3312 | && !REG_P (x) |
23b2ce53 | 3313 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 3314 | || (REG_P (other) |
23b2ce53 RS |
3315 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
3316 | || reg_mentioned_p (other, x)))) | |
3317 | { | |
3318 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
3319 | emit_move_insn (temp, x); | |
3320 | return temp; | |
3321 | } | |
3322 | return x; | |
3323 | } | |
3324 | \f | |
3325 | /* Emission of insns (adding them to the doubly-linked list). */ | |
3326 | ||
23b2ce53 RS |
3327 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ |
3328 | ||
db76cf1e | 3329 | rtx_insn * |
502b8322 | 3330 | get_last_insn_anywhere (void) |
23b2ce53 | 3331 | { |
614d5bd8 AM |
3332 | struct sequence_stack *seq; |
3333 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
3334 | if (seq->last != 0) | |
3335 | return seq->last; | |
23b2ce53 RS |
3336 | return 0; |
3337 | } | |
3338 | ||
2a496e8b JDA |
3339 | /* Return the first nonnote insn emitted in current sequence or current |
3340 | function. This routine looks inside SEQUENCEs. */ | |
3341 | ||
e4685bc8 | 3342 | rtx_insn * |
502b8322 | 3343 | get_first_nonnote_insn (void) |
2a496e8b | 3344 | { |
dc01c3d1 | 3345 | rtx_insn *insn = get_insns (); |
91373fe8 JDA |
3346 | |
3347 | if (insn) | |
3348 | { | |
3349 | if (NOTE_P (insn)) | |
3350 | for (insn = next_insn (insn); | |
3351 | insn && NOTE_P (insn); | |
3352 | insn = next_insn (insn)) | |
3353 | continue; | |
3354 | else | |
3355 | { | |
2ca202e7 | 3356 | if (NONJUMP_INSN_P (insn) |
91373fe8 | 3357 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
dc01c3d1 | 3358 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
91373fe8 JDA |
3359 | } |
3360 | } | |
2a496e8b JDA |
3361 | |
3362 | return insn; | |
3363 | } | |
3364 | ||
3365 | /* Return the last nonnote insn emitted in current sequence or current | |
3366 | function. This routine looks inside SEQUENCEs. */ | |
3367 | ||
e4685bc8 | 3368 | rtx_insn * |
502b8322 | 3369 | get_last_nonnote_insn (void) |
2a496e8b | 3370 | { |
dc01c3d1 | 3371 | rtx_insn *insn = get_last_insn (); |
91373fe8 JDA |
3372 | |
3373 | if (insn) | |
3374 | { | |
3375 | if (NOTE_P (insn)) | |
3376 | for (insn = previous_insn (insn); | |
3377 | insn && NOTE_P (insn); | |
3378 | insn = previous_insn (insn)) | |
3379 | continue; | |
3380 | else | |
3381 | { | |
dc01c3d1 DM |
3382 | if (NONJUMP_INSN_P (insn)) |
3383 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3384 | insn = seq->insn (seq->len () - 1); | |
91373fe8 JDA |
3385 | } |
3386 | } | |
2a496e8b JDA |
3387 | |
3388 | return insn; | |
3389 | } | |
3390 | ||
b5b8b0ac AO |
3391 | /* Return the number of actual (non-debug) insns emitted in this |
3392 | function. */ | |
3393 | ||
3394 | int | |
3395 | get_max_insn_count (void) | |
3396 | { | |
3397 | int n = cur_insn_uid; | |
3398 | ||
3399 | /* The table size must be stable across -g, to avoid codegen | |
3400 | differences due to debug insns, and not be affected by | |
3401 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
3402 | debugging of -fcompare-debug failures. */ | |
028d4092 | 3403 | if (cur_debug_insn_uid > param_min_nondebug_insn_uid) |
b5b8b0ac AO |
3404 | n -= cur_debug_insn_uid; |
3405 | else | |
028d4092 | 3406 | n -= param_min_nondebug_insn_uid; |
b5b8b0ac AO |
3407 | |
3408 | return n; | |
3409 | } | |
3410 | ||
23b2ce53 RS |
3411 | \f |
3412 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
3413 | of the sequence. */ | |
3414 | ||
eb51c837 | 3415 | rtx_insn * |
4ce524a1 | 3416 | next_insn (rtx_insn *insn) |
23b2ce53 | 3417 | { |
75547801 KG |
3418 | if (insn) |
3419 | { | |
3420 | insn = NEXT_INSN (insn); | |
3421 | if (insn && NONJUMP_INSN_P (insn) | |
3422 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
dc01c3d1 | 3423 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
75547801 | 3424 | } |
23b2ce53 | 3425 | |
dc01c3d1 | 3426 | return insn; |
23b2ce53 RS |
3427 | } |
3428 | ||
3429 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3430 | of the sequence. */ | |
3431 | ||
eb51c837 | 3432 | rtx_insn * |
4ce524a1 | 3433 | previous_insn (rtx_insn *insn) |
23b2ce53 | 3434 | { |
75547801 KG |
3435 | if (insn) |
3436 | { | |
3437 | insn = PREV_INSN (insn); | |
dc01c3d1 DM |
3438 | if (insn && NONJUMP_INSN_P (insn)) |
3439 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3440 | insn = seq->insn (seq->len () - 1); | |
75547801 | 3441 | } |
23b2ce53 | 3442 | |
dc01c3d1 | 3443 | return insn; |
23b2ce53 RS |
3444 | } |
3445 | ||
3446 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3447 | look inside SEQUENCEs. */ | |
3448 | ||
eb51c837 | 3449 | rtx_insn * |
c9b0a227 | 3450 | next_nonnote_insn (rtx_insn *insn) |
23b2ce53 | 3451 | { |
75547801 KG |
3452 | while (insn) |
3453 | { | |
3454 | insn = NEXT_INSN (insn); | |
3455 | if (insn == 0 || !NOTE_P (insn)) | |
3456 | break; | |
3457 | } | |
23b2ce53 | 3458 | |
dc01c3d1 | 3459 | return insn; |
23b2ce53 RS |
3460 | } |
3461 | ||
f40dd646 AO |
3462 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3463 | routine does not look inside SEQUENCEs. */ | |
1e211590 | 3464 | |
eb51c837 | 3465 | rtx_insn * |
f40dd646 | 3466 | next_nondebug_insn (rtx_insn *insn) |
1e211590 DD |
3467 | { |
3468 | while (insn) | |
3469 | { | |
3470 | insn = NEXT_INSN (insn); | |
f40dd646 | 3471 | if (insn == 0 || !DEBUG_INSN_P (insn)) |
1e211590 | 3472 | break; |
1e211590 DD |
3473 | } |
3474 | ||
dc01c3d1 | 3475 | return insn; |
1e211590 DD |
3476 | } |
3477 | ||
23b2ce53 RS |
3478 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3479 | not look inside SEQUENCEs. */ | |
3480 | ||
eb51c837 | 3481 | rtx_insn * |
c9b0a227 | 3482 | prev_nonnote_insn (rtx_insn *insn) |
23b2ce53 | 3483 | { |
75547801 KG |
3484 | while (insn) |
3485 | { | |
3486 | insn = PREV_INSN (insn); | |
3487 | if (insn == 0 || !NOTE_P (insn)) | |
3488 | break; | |
3489 | } | |
23b2ce53 | 3490 | |
dc01c3d1 | 3491 | return insn; |
23b2ce53 RS |
3492 | } |
3493 | ||
f40dd646 AO |
3494 | /* Return the previous insn before INSN that is not a DEBUG_INSN. |
3495 | This routine does not look inside SEQUENCEs. */ | |
896aa4ea | 3496 | |
eb51c837 | 3497 | rtx_insn * |
f40dd646 | 3498 | prev_nondebug_insn (rtx_insn *insn) |
896aa4ea DD |
3499 | { |
3500 | while (insn) | |
3501 | { | |
3502 | insn = PREV_INSN (insn); | |
f40dd646 | 3503 | if (insn == 0 || !DEBUG_INSN_P (insn)) |
896aa4ea | 3504 | break; |
896aa4ea DD |
3505 | } |
3506 | ||
dc01c3d1 | 3507 | return insn; |
896aa4ea DD |
3508 | } |
3509 | ||
f40dd646 AO |
3510 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN. |
3511 | This routine does not look inside SEQUENCEs. */ | |
b5b8b0ac | 3512 | |
eb51c837 | 3513 | rtx_insn * |
f40dd646 | 3514 | next_nonnote_nondebug_insn (rtx_insn *insn) |
b5b8b0ac AO |
3515 | { |
3516 | while (insn) | |
3517 | { | |
3518 | insn = NEXT_INSN (insn); | |
f40dd646 | 3519 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) |
b5b8b0ac AO |
3520 | break; |
3521 | } | |
3522 | ||
dc01c3d1 | 3523 | return insn; |
b5b8b0ac AO |
3524 | } |
3525 | ||
f40dd646 AO |
3526 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN, |
3527 | but stop the search before we enter another basic block. This | |
3528 | routine does not look inside SEQUENCEs. */ | |
b5b8b0ac | 3529 | |
eb51c837 | 3530 | rtx_insn * |
f40dd646 | 3531 | next_nonnote_nondebug_insn_bb (rtx_insn *insn) |
b5b8b0ac AO |
3532 | { |
3533 | while (insn) | |
3534 | { | |
f40dd646 AO |
3535 | insn = NEXT_INSN (insn); |
3536 | if (insn == 0) | |
3537 | break; | |
3538 | if (DEBUG_INSN_P (insn)) | |
3539 | continue; | |
3540 | if (!NOTE_P (insn)) | |
b5b8b0ac | 3541 | break; |
f40dd646 AO |
3542 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
3543 | return NULL; | |
b5b8b0ac AO |
3544 | } |
3545 | ||
dc01c3d1 | 3546 | return insn; |
b5b8b0ac AO |
3547 | } |
3548 | ||
f40dd646 | 3549 | /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN. |
f0fc0803 JJ |
3550 | This routine does not look inside SEQUENCEs. */ |
3551 | ||
eb51c837 | 3552 | rtx_insn * |
f40dd646 | 3553 | prev_nonnote_nondebug_insn (rtx_insn *insn) |
f0fc0803 JJ |
3554 | { |
3555 | while (insn) | |
3556 | { | |
f40dd646 | 3557 | insn = PREV_INSN (insn); |
f0fc0803 JJ |
3558 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) |
3559 | break; | |
3560 | } | |
3561 | ||
dc01c3d1 | 3562 | return insn; |
f0fc0803 JJ |
3563 | } |
3564 | ||
f40dd646 AO |
3565 | /* Return the previous insn before INSN that is not a NOTE nor |
3566 | DEBUG_INSN, but stop the search before we enter another basic | |
3567 | block. This routine does not look inside SEQUENCEs. */ | |
f0fc0803 | 3568 | |
eb51c837 | 3569 | rtx_insn * |
f40dd646 | 3570 | prev_nonnote_nondebug_insn_bb (rtx_insn *insn) |
f0fc0803 JJ |
3571 | { |
3572 | while (insn) | |
3573 | { | |
3574 | insn = PREV_INSN (insn); | |
f40dd646 | 3575 | if (insn == 0) |
f0fc0803 | 3576 | break; |
f40dd646 AO |
3577 | if (DEBUG_INSN_P (insn)) |
3578 | continue; | |
3579 | if (!NOTE_P (insn)) | |
3580 | break; | |
3581 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3582 | return NULL; | |
f0fc0803 JJ |
3583 | } |
3584 | ||
dc01c3d1 | 3585 | return insn; |
f0fc0803 JJ |
3586 | } |
3587 | ||
ec2d7121 | 3588 | /* Return the next INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN after INSN; |
23b2ce53 | 3589 | or 0, if there is none. This routine does not look inside |
0f41302f | 3590 | SEQUENCEs. */ |
23b2ce53 | 3591 | |
eb51c837 | 3592 | rtx_insn * |
4dea3bff | 3593 | next_real_insn (rtx_insn *insn) |
23b2ce53 | 3594 | { |
75547801 KG |
3595 | while (insn) |
3596 | { | |
3597 | insn = NEXT_INSN (insn); | |
3598 | if (insn == 0 || INSN_P (insn)) | |
3599 | break; | |
3600 | } | |
23b2ce53 | 3601 | |
dc01c3d1 | 3602 | return insn; |
23b2ce53 RS |
3603 | } |
3604 | ||
ec2d7121 | 3605 | /* Return the last INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN before INSN; |
23b2ce53 RS |
3606 | or 0, if there is none. This routine does not look inside |
3607 | SEQUENCEs. */ | |
3608 | ||
eb51c837 | 3609 | rtx_insn * |
d8fd56b2 | 3610 | prev_real_insn (rtx_insn *insn) |
23b2ce53 | 3611 | { |
75547801 KG |
3612 | while (insn) |
3613 | { | |
3614 | insn = PREV_INSN (insn); | |
3615 | if (insn == 0 || INSN_P (insn)) | |
3616 | break; | |
3617 | } | |
23b2ce53 | 3618 | |
dc01c3d1 | 3619 | return insn; |
23b2ce53 RS |
3620 | } |
3621 | ||
ec2d7121 JJ |
3622 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3623 | or 0, if there is none. This routine does not look inside | |
3624 | SEQUENCEs. */ | |
3625 | ||
3626 | rtx_insn * | |
3627 | next_real_nondebug_insn (rtx uncast_insn) | |
3628 | { | |
3629 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); | |
3630 | ||
3631 | while (insn) | |
3632 | { | |
3633 | insn = NEXT_INSN (insn); | |
3634 | if (insn == 0 || NONDEBUG_INSN_P (insn)) | |
3635 | break; | |
3636 | } | |
3637 | ||
3638 | return insn; | |
3639 | } | |
3640 | ||
3641 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3642 | or 0, if there is none. This routine does not look inside | |
3643 | SEQUENCEs. */ | |
3644 | ||
3645 | rtx_insn * | |
3646 | prev_real_nondebug_insn (rtx_insn *insn) | |
3647 | { | |
3648 | while (insn) | |
3649 | { | |
3650 | insn = PREV_INSN (insn); | |
3651 | if (insn == 0 || NONDEBUG_INSN_P (insn)) | |
3652 | break; | |
3653 | } | |
3654 | ||
3655 | return insn; | |
3656 | } | |
3657 | ||
ee960939 OH |
3658 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3659 | This routine does not look inside SEQUENCEs. */ | |
3660 | ||
049cfc4a | 3661 | rtx_call_insn * |
502b8322 | 3662 | last_call_insn (void) |
ee960939 | 3663 | { |
049cfc4a | 3664 | rtx_insn *insn; |
ee960939 OH |
3665 | |
3666 | for (insn = get_last_insn (); | |
4b4bf941 | 3667 | insn && !CALL_P (insn); |
ee960939 OH |
3668 | insn = PREV_INSN (insn)) |
3669 | ; | |
3670 | ||
049cfc4a | 3671 | return safe_as_a <rtx_call_insn *> (insn); |
ee960939 OH |
3672 | } |
3673 | ||
23b2ce53 | 3674 | /* Find the next insn after INSN that really does something. This routine |
9c517bf3 AK |
3675 | does not look inside SEQUENCEs. After reload this also skips over |
3676 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3677 | |
69732dcb | 3678 | int |
7c9796ed | 3679 | active_insn_p (const rtx_insn *insn) |
69732dcb | 3680 | { |
4b4bf941 | 3681 | return (CALL_P (insn) || JUMP_P (insn) |
39718607 | 3682 | || JUMP_TABLE_DATA_P (insn) /* FIXME */ |
4b4bf941 | 3683 | || (NONJUMP_INSN_P (insn) |
23b8ba81 RH |
3684 | && (! reload_completed |
3685 | || (GET_CODE (PATTERN (insn)) != USE | |
3686 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3687 | } |
3688 | ||
eb51c837 | 3689 | rtx_insn * |
7c9796ed | 3690 | next_active_insn (rtx_insn *insn) |
23b2ce53 | 3691 | { |
75547801 KG |
3692 | while (insn) |
3693 | { | |
3694 | insn = NEXT_INSN (insn); | |
3695 | if (insn == 0 || active_insn_p (insn)) | |
3696 | break; | |
3697 | } | |
23b2ce53 | 3698 | |
dc01c3d1 | 3699 | return insn; |
23b2ce53 RS |
3700 | } |
3701 | ||
3702 | /* Find the last insn before INSN that really does something. This routine | |
9c517bf3 AK |
3703 | does not look inside SEQUENCEs. After reload this also skips over |
3704 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3705 | |
eb51c837 | 3706 | rtx_insn * |
7c9796ed | 3707 | prev_active_insn (rtx_insn *insn) |
23b2ce53 | 3708 | { |
75547801 KG |
3709 | while (insn) |
3710 | { | |
3711 | insn = PREV_INSN (insn); | |
3712 | if (insn == 0 || active_insn_p (insn)) | |
3713 | break; | |
3714 | } | |
23b2ce53 | 3715 | |
dc01c3d1 | 3716 | return insn; |
23b2ce53 | 3717 | } |
23b2ce53 | 3718 | \f |
594f8779 RZ |
3719 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ |
3720 | ||
3721 | static int | |
9021b8ec | 3722 | find_auto_inc (const_rtx x, const_rtx reg) |
594f8779 | 3723 | { |
9021b8ec RS |
3724 | subrtx_iterator::array_type array; |
3725 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
594f8779 | 3726 | { |
9021b8ec RS |
3727 | const_rtx x = *iter; |
3728 | if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC | |
3729 | && rtx_equal_p (reg, XEXP (x, 0))) | |
3730 | return true; | |
594f8779 | 3731 | } |
9021b8ec | 3732 | return false; |
594f8779 | 3733 | } |
594f8779 | 3734 | |
e5bef2e4 HB |
3735 | /* Increment the label uses for all labels present in rtx. */ |
3736 | ||
3737 | static void | |
502b8322 | 3738 | mark_label_nuses (rtx x) |
e5bef2e4 | 3739 | { |
b3694847 SS |
3740 | enum rtx_code code; |
3741 | int i, j; | |
3742 | const char *fmt; | |
e5bef2e4 HB |
3743 | |
3744 | code = GET_CODE (x); | |
04a121a7 TS |
3745 | if (code == LABEL_REF && LABEL_P (label_ref_label (x))) |
3746 | LABEL_NUSES (label_ref_label (x))++; | |
e5bef2e4 HB |
3747 | |
3748 | fmt = GET_RTX_FORMAT (code); | |
3749 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3750 | { | |
3751 | if (fmt[i] == 'e') | |
0fb7aeda | 3752 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3753 | else if (fmt[i] == 'E') |
0fb7aeda | 3754 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3755 | mark_label_nuses (XVECEXP (x, i, j)); |
3756 | } | |
3757 | } | |
3758 | ||
23b2ce53 RS |
3759 | \f |
3760 | /* Try splitting insns that can be split for better scheduling. | |
3761 | PAT is the pattern which might split. | |
3762 | TRIAL is the insn providing PAT. | |
cc2902df | 3763 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3764 | |
3765 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3766 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3767 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3768 | ||
53f04688 | 3769 | rtx_insn * |
bb5c4956 | 3770 | try_split (rtx pat, rtx_insn *trial, int last) |
23b2ce53 | 3771 | { |
d4eff95b | 3772 | rtx_insn *before, *after; |
dc01c3d1 DM |
3773 | rtx note; |
3774 | rtx_insn *seq, *tem; | |
5fa396ad | 3775 | profile_probability probability; |
dc01c3d1 | 3776 | rtx_insn *insn_last, *insn; |
599aedd9 | 3777 | int njumps = 0; |
e67d1102 | 3778 | rtx_insn *call_insn = NULL; |
6b24c259 JH |
3779 | |
3780 | if (any_condjump_p (trial) | |
3781 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
5fa396ad JH |
3782 | split_branch_probability |
3783 | = profile_probability::from_reg_br_prob_note (XINT (note, 0)); | |
3784 | else | |
3785 | split_branch_probability = profile_probability::uninitialized (); | |
3786 | ||
6b24c259 JH |
3787 | probability = split_branch_probability; |
3788 | ||
bb5c4956 | 3789 | seq = split_insns (pat, trial); |
6b24c259 | 3790 | |
5fa396ad | 3791 | split_branch_probability = profile_probability::uninitialized (); |
23b2ce53 | 3792 | |
599aedd9 | 3793 | if (!seq) |
dc01c3d1 | 3794 | return trial; |
599aedd9 | 3795 | |
e7d55c6b | 3796 | int split_insn_count = 0; |
599aedd9 RH |
3797 | /* Avoid infinite loop if any insn of the result matches |
3798 | the original pattern. */ | |
3799 | insn_last = seq; | |
3800 | while (1) | |
23b2ce53 | 3801 | { |
599aedd9 RH |
3802 | if (INSN_P (insn_last) |
3803 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
dc01c3d1 | 3804 | return trial; |
e7d55c6b | 3805 | split_insn_count++; |
599aedd9 RH |
3806 | if (!NEXT_INSN (insn_last)) |
3807 | break; | |
3808 | insn_last = NEXT_INSN (insn_last); | |
3809 | } | |
750c9258 | 3810 | |
e7d55c6b SKS |
3811 | /* We're not good at redistributing frame information if |
3812 | the split occurs before reload or if it results in more | |
3813 | than one insn. */ | |
3814 | if (RTX_FRAME_RELATED_P (trial)) | |
3815 | { | |
3816 | if (!reload_completed || split_insn_count != 1) | |
3817 | return trial; | |
3818 | ||
3819 | rtx_insn *new_insn = seq; | |
3820 | rtx_insn *old_insn = trial; | |
3821 | copy_frame_info_to_split_insn (old_insn, new_insn); | |
3822 | } | |
3823 | ||
6fb5fa3c DB |
3824 | /* We will be adding the new sequence to the function. The splitters |
3825 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3826 | unshare_all_rtl_in_chain (seq); | |
3827 | ||
339ba33b | 3828 | /* Mark labels and copy flags. */ |
599aedd9 RH |
3829 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) |
3830 | { | |
4b4bf941 | 3831 | if (JUMP_P (insn)) |
599aedd9 | 3832 | { |
339ba33b RS |
3833 | if (JUMP_P (trial)) |
3834 | CROSSING_JUMP_P (insn) = CROSSING_JUMP_P (trial); | |
599aedd9 RH |
3835 | mark_jump_label (PATTERN (insn), insn, 0); |
3836 | njumps++; | |
5fa396ad | 3837 | if (probability.initialized_p () |
599aedd9 RH |
3838 | && any_condjump_p (insn) |
3839 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3840 | { |
599aedd9 RH |
3841 | /* We can preserve the REG_BR_PROB notes only if exactly |
3842 | one jump is created, otherwise the machine description | |
3843 | is responsible for this step using | |
3844 | split_branch_probability variable. */ | |
5b0264cb | 3845 | gcc_assert (njumps == 1); |
5fa396ad | 3846 | add_reg_br_prob_note (insn, probability); |
2f937369 | 3847 | } |
599aedd9 RH |
3848 | } |
3849 | } | |
3850 | ||
3851 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
65712d5c | 3852 | in SEQ and copy any additional information across. */ |
4b4bf941 | 3853 | if (CALL_P (trial)) |
599aedd9 RH |
3854 | { |
3855 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3856 | if (CALL_P (insn)) |
599aedd9 | 3857 | { |
4f660b15 RO |
3858 | gcc_assert (call_insn == NULL_RTX); |
3859 | call_insn = insn; | |
3860 | ||
65712d5c RS |
3861 | /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the |
3862 | target may have explicitly specified. */ | |
00b94487 | 3863 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
f6a1f3f6 RH |
3864 | while (*p) |
3865 | p = &XEXP (*p, 1); | |
3866 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
65712d5c RS |
3867 | |
3868 | /* If the old call was a sibling call, the new one must | |
3869 | be too. */ | |
599aedd9 RH |
3870 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3871 | } | |
3872 | } | |
4b5e8abe | 3873 | |
599aedd9 RH |
3874 | /* Copy notes, particularly those related to the CFG. */ |
3875 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3876 | { | |
3877 | switch (REG_NOTE_KIND (note)) | |
3878 | { | |
3879 | case REG_EH_REGION: | |
1d65f45c | 3880 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3881 | break; |
216183ce | 3882 | |
599aedd9 RH |
3883 | case REG_NORETURN: |
3884 | case REG_SETJMP: | |
0a35513e | 3885 | case REG_TM: |
5c5f0b65 | 3886 | case REG_CALL_NOCF_CHECK: |
00b94487 | 3887 | case REG_CALL_ARG_LOCATION: |
594f8779 | 3888 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3889 | { |
4b4bf941 | 3890 | if (CALL_P (insn)) |
65c5f2a6 | 3891 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3892 | } |
599aedd9 | 3893 | break; |
d6e95df8 | 3894 | |
599aedd9 | 3895 | case REG_NON_LOCAL_GOTO: |
73f1289e | 3896 | case REG_LABEL_TARGET: |
594f8779 | 3897 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3898 | { |
4b4bf941 | 3899 | if (JUMP_P (insn)) |
65c5f2a6 | 3900 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3901 | } |
599aedd9 | 3902 | break; |
e5bef2e4 | 3903 | |
594f8779 | 3904 | case REG_INC: |
760edf20 TS |
3905 | if (!AUTO_INC_DEC) |
3906 | break; | |
3907 | ||
594f8779 RZ |
3908 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
3909 | { | |
3910 | rtx reg = XEXP (note, 0); | |
3911 | if (!FIND_REG_INC_NOTE (insn, reg) | |
9021b8ec | 3912 | && find_auto_inc (PATTERN (insn), reg)) |
65c5f2a6 | 3913 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3914 | } |
3915 | break; | |
594f8779 | 3916 | |
9a08d230 | 3917 | case REG_ARGS_SIZE: |
68184180 | 3918 | fixup_args_size_notes (NULL, insn_last, get_args_size (note)); |
9a08d230 RH |
3919 | break; |
3920 | ||
4f660b15 | 3921 | case REG_CALL_DECL: |
49e65199 | 3922 | case REG_UNTYPED_CALL: |
4f660b15 RO |
3923 | gcc_assert (call_insn != NULL_RTX); |
3924 | add_reg_note (call_insn, REG_NOTE_KIND (note), XEXP (note, 0)); | |
3925 | break; | |
3926 | ||
599aedd9 RH |
3927 | default: |
3928 | break; | |
23b2ce53 | 3929 | } |
599aedd9 RH |
3930 | } |
3931 | ||
3932 | /* If there are LABELS inside the split insns increment the | |
3933 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3934 | if (INSN_P (trial)) |
599aedd9 RH |
3935 | { |
3936 | insn = insn_last; | |
3937 | while (insn != NULL_RTX) | |
23b2ce53 | 3938 | { |
cf7c4aa6 | 3939 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3940 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3941 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3942 | |
599aedd9 RH |
3943 | insn = PREV_INSN (insn); |
3944 | } | |
23b2ce53 RS |
3945 | } |
3946 | ||
d4eff95b JC |
3947 | before = PREV_INSN (trial); |
3948 | after = NEXT_INSN (trial); | |
3949 | ||
45309d28 | 3950 | emit_insn_after_setloc (seq, trial, INSN_LOCATION (trial)); |
599aedd9 RH |
3951 | |
3952 | delete_insn (trial); | |
599aedd9 RH |
3953 | |
3954 | /* Recursively call try_split for each new insn created; by the | |
3955 | time control returns here that insn will be fully split, so | |
3956 | set LAST and continue from the insn after the one returned. | |
3957 | We can't use next_active_insn here since AFTER may be a note. | |
3958 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3959 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
4654c0cf | 3960 | if (! tem->deleted () && INSN_P (tem)) |
599aedd9 RH |
3961 | tem = try_split (PATTERN (tem), tem, 1); |
3962 | ||
3963 | /* Return either the first or the last insn, depending on which was | |
3964 | requested. */ | |
3965 | return last | |
5936d944 | 3966 | ? (after ? PREV_INSN (after) : get_last_insn ()) |
599aedd9 | 3967 | : NEXT_INSN (before); |
23b2ce53 RS |
3968 | } |
3969 | \f | |
3970 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3971 | Store PATTERN in the pattern slots. */ |
23b2ce53 | 3972 | |
167b9fae | 3973 | rtx_insn * |
502b8322 | 3974 | make_insn_raw (rtx pattern) |
23b2ce53 | 3975 | { |
167b9fae | 3976 | rtx_insn *insn; |
23b2ce53 | 3977 | |
167b9fae | 3978 | insn = as_a <rtx_insn *> (rtx_alloc (INSN)); |
23b2ce53 | 3979 | |
43127294 | 3980 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3981 | PATTERN (insn) = pattern; |
3982 | INSN_CODE (insn) = -1; | |
1632afca | 3983 | REG_NOTES (insn) = NULL; |
5368224f | 3984 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3985 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3986 | |
47984720 NC |
3987 | #ifdef ENABLE_RTL_CHECKING |
3988 | if (insn | |
2c3c49de | 3989 | && INSN_P (insn) |
47984720 NC |
3990 | && (returnjump_p (insn) |
3991 | || (GET_CODE (insn) == SET | |
3992 | && SET_DEST (insn) == pc_rtx))) | |
3993 | { | |
d4ee4d25 | 3994 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3995 | debug_rtx (insn); |
3996 | } | |
3997 | #endif | |
750c9258 | 3998 | |
23b2ce53 RS |
3999 | return insn; |
4000 | } | |
4001 | ||
b5b8b0ac AO |
4002 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
4003 | ||
167b9fae | 4004 | static rtx_insn * |
b5b8b0ac AO |
4005 | make_debug_insn_raw (rtx pattern) |
4006 | { | |
167b9fae | 4007 | rtx_debug_insn *insn; |
b5b8b0ac | 4008 | |
167b9fae | 4009 | insn = as_a <rtx_debug_insn *> (rtx_alloc (DEBUG_INSN)); |
b5b8b0ac | 4010 | INSN_UID (insn) = cur_debug_insn_uid++; |
028d4092 | 4011 | if (cur_debug_insn_uid > param_min_nondebug_insn_uid) |
b5b8b0ac AO |
4012 | INSN_UID (insn) = cur_insn_uid++; |
4013 | ||
4014 | PATTERN (insn) = pattern; | |
4015 | INSN_CODE (insn) = -1; | |
4016 | REG_NOTES (insn) = NULL; | |
5368224f | 4017 | INSN_LOCATION (insn) = curr_insn_location (); |
b5b8b0ac AO |
4018 | BLOCK_FOR_INSN (insn) = NULL; |
4019 | ||
4020 | return insn; | |
4021 | } | |
4022 | ||
2f937369 | 4023 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 4024 | |
167b9fae | 4025 | static rtx_insn * |
502b8322 | 4026 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 4027 | { |
167b9fae | 4028 | rtx_jump_insn *insn; |
23b2ce53 | 4029 | |
167b9fae | 4030 | insn = as_a <rtx_jump_insn *> (rtx_alloc (JUMP_INSN)); |
1632afca | 4031 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
4032 | |
4033 | PATTERN (insn) = pattern; | |
4034 | INSN_CODE (insn) = -1; | |
1632afca RS |
4035 | REG_NOTES (insn) = NULL; |
4036 | JUMP_LABEL (insn) = NULL; | |
5368224f | 4037 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 4038 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
4039 | |
4040 | return insn; | |
4041 | } | |
aff507f4 | 4042 | |
2f937369 | 4043 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 | 4044 | |
167b9fae | 4045 | static rtx_insn * |
502b8322 | 4046 | make_call_insn_raw (rtx pattern) |
aff507f4 | 4047 | { |
167b9fae | 4048 | rtx_call_insn *insn; |
aff507f4 | 4049 | |
167b9fae | 4050 | insn = as_a <rtx_call_insn *> (rtx_alloc (CALL_INSN)); |
aff507f4 RK |
4051 | INSN_UID (insn) = cur_insn_uid++; |
4052 | ||
4053 | PATTERN (insn) = pattern; | |
4054 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
4055 | REG_NOTES (insn) = NULL; |
4056 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
5368224f | 4057 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 4058 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
4059 | |
4060 | return insn; | |
4061 | } | |
96fba521 SB |
4062 | |
4063 | /* Like `make_insn_raw' but make a NOTE instead of an insn. */ | |
4064 | ||
66e8df53 | 4065 | static rtx_note * |
96fba521 SB |
4066 | make_note_raw (enum insn_note subtype) |
4067 | { | |
4068 | /* Some notes are never created this way at all. These notes are | |
4069 | only created by patching out insns. */ | |
4070 | gcc_assert (subtype != NOTE_INSN_DELETED_LABEL | |
4071 | && subtype != NOTE_INSN_DELETED_DEBUG_LABEL); | |
4072 | ||
66e8df53 | 4073 | rtx_note *note = as_a <rtx_note *> (rtx_alloc (NOTE)); |
96fba521 SB |
4074 | INSN_UID (note) = cur_insn_uid++; |
4075 | NOTE_KIND (note) = subtype; | |
4076 | BLOCK_FOR_INSN (note) = NULL; | |
4077 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); | |
4078 | return note; | |
4079 | } | |
23b2ce53 | 4080 | \f |
96fba521 SB |
4081 | /* Add INSN to the end of the doubly-linked list, between PREV and NEXT. |
4082 | INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects, | |
4083 | but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */ | |
4084 | ||
4085 | static inline void | |
9152e0aa | 4086 | link_insn_into_chain (rtx_insn *insn, rtx_insn *prev, rtx_insn *next) |
96fba521 | 4087 | { |
0f82e5c9 DM |
4088 | SET_PREV_INSN (insn) = prev; |
4089 | SET_NEXT_INSN (insn) = next; | |
96fba521 SB |
4090 | if (prev != NULL) |
4091 | { | |
0f82e5c9 | 4092 | SET_NEXT_INSN (prev) = insn; |
96fba521 SB |
4093 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
4094 | { | |
e6eda746 DM |
4095 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4096 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = insn; | |
96fba521 SB |
4097 | } |
4098 | } | |
4099 | if (next != NULL) | |
4100 | { | |
0f82e5c9 | 4101 | SET_PREV_INSN (next) = insn; |
96fba521 | 4102 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4103 | { |
4104 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4105 | SET_PREV_INSN (sequence->insn (0)) = insn; | |
4106 | } | |
96fba521 | 4107 | } |
3ccb989e SB |
4108 | |
4109 | if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4110 | { | |
e6eda746 DM |
4111 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (insn)); |
4112 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4113 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
3ccb989e | 4114 | } |
96fba521 SB |
4115 | } |
4116 | ||
23b2ce53 RS |
4117 | /* Add INSN to the end of the doubly-linked list. |
4118 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
4119 | ||
4120 | void | |
9152e0aa | 4121 | add_insn (rtx_insn *insn) |
23b2ce53 | 4122 | { |
9152e0aa | 4123 | rtx_insn *prev = get_last_insn (); |
96fba521 | 4124 | link_insn_into_chain (insn, prev, NULL); |
01512446 | 4125 | if (get_insns () == NULL) |
5936d944 | 4126 | set_first_insn (insn); |
5936d944 | 4127 | set_last_insn (insn); |
23b2ce53 RS |
4128 | } |
4129 | ||
96fba521 | 4130 | /* Add INSN into the doubly-linked list after insn AFTER. */ |
23b2ce53 | 4131 | |
96fba521 | 4132 | static void |
9152e0aa | 4133 | add_insn_after_nobb (rtx_insn *insn, rtx_insn *after) |
23b2ce53 | 4134 | { |
9152e0aa | 4135 | rtx_insn *next = NEXT_INSN (after); |
23b2ce53 | 4136 | |
4654c0cf | 4137 | gcc_assert (!optimize || !after->deleted ()); |
ba213285 | 4138 | |
96fba521 | 4139 | link_insn_into_chain (insn, after, next); |
23b2ce53 | 4140 | |
96fba521 | 4141 | if (next == NULL) |
23b2ce53 | 4142 | { |
614d5bd8 AM |
4143 | struct sequence_stack *seq; |
4144 | ||
4145 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4146 | if (after == seq->last) | |
4147 | { | |
4148 | seq->last = insn; | |
4149 | break; | |
4150 | } | |
23b2ce53 | 4151 | } |
96fba521 SB |
4152 | } |
4153 | ||
4154 | /* Add INSN into the doubly-linked list before insn BEFORE. */ | |
4155 | ||
4156 | static void | |
9152e0aa | 4157 | add_insn_before_nobb (rtx_insn *insn, rtx_insn *before) |
96fba521 | 4158 | { |
9152e0aa | 4159 | rtx_insn *prev = PREV_INSN (before); |
96fba521 | 4160 | |
4654c0cf | 4161 | gcc_assert (!optimize || !before->deleted ()); |
96fba521 SB |
4162 | |
4163 | link_insn_into_chain (insn, prev, before); | |
4164 | ||
4165 | if (prev == NULL) | |
23b2ce53 | 4166 | { |
614d5bd8 | 4167 | struct sequence_stack *seq; |
a0ae8e8d | 4168 | |
614d5bd8 AM |
4169 | for (seq = get_current_sequence (); seq; seq = seq->next) |
4170 | if (before == seq->first) | |
4171 | { | |
4172 | seq->first = insn; | |
4173 | break; | |
4174 | } | |
4175 | ||
4176 | gcc_assert (seq); | |
23b2ce53 | 4177 | } |
96fba521 SB |
4178 | } |
4179 | ||
4180 | /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN. | |
4181 | If BB is NULL, an attempt is made to infer the bb from before. | |
4182 | ||
4183 | This and the next function should be the only functions called | |
4184 | to insert an insn once delay slots have been filled since only | |
4185 | they know how to update a SEQUENCE. */ | |
23b2ce53 | 4186 | |
96fba521 | 4187 | void |
4dea3bff | 4188 | add_insn_after (rtx_insn *insn, rtx_insn *after, basic_block bb) |
96fba521 SB |
4189 | { |
4190 | add_insn_after_nobb (insn, after); | |
4b4bf941 JQ |
4191 | if (!BARRIER_P (after) |
4192 | && !BARRIER_P (insn) | |
3c030e88 JH |
4193 | && (bb = BLOCK_FOR_INSN (after))) |
4194 | { | |
4195 | set_block_for_insn (insn, bb); | |
38c1593d | 4196 | if (INSN_P (insn)) |
6fb5fa3c | 4197 | df_insn_rescan (insn); |
3c030e88 | 4198 | /* Should not happen as first in the BB is always |
a1f300c0 | 4199 | either NOTE or LABEL. */ |
a813c111 | 4200 | if (BB_END (bb) == after |
3c030e88 | 4201 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 4202 | && !BARRIER_P (insn) |
a38e7aa5 | 4203 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
1130d5e3 | 4204 | BB_END (bb) = insn; |
3c030e88 | 4205 | } |
23b2ce53 RS |
4206 | } |
4207 | ||
96fba521 SB |
4208 | /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN. |
4209 | If BB is NULL, an attempt is made to infer the bb from before. | |
4210 | ||
4211 | This and the previous function should be the only functions called | |
4212 | to insert an insn once delay slots have been filled since only | |
4213 | they know how to update a SEQUENCE. */ | |
a0ae8e8d RK |
4214 | |
4215 | void | |
4dea3bff | 4216 | add_insn_before (rtx_insn *insn, rtx_insn *before, basic_block bb) |
a0ae8e8d | 4217 | { |
96fba521 | 4218 | add_insn_before_nobb (insn, before); |
a0ae8e8d | 4219 | |
b8698a0f | 4220 | if (!bb |
6fb5fa3c DB |
4221 | && !BARRIER_P (before) |
4222 | && !BARRIER_P (insn)) | |
4223 | bb = BLOCK_FOR_INSN (before); | |
4224 | ||
4225 | if (bb) | |
3c030e88 JH |
4226 | { |
4227 | set_block_for_insn (insn, bb); | |
38c1593d | 4228 | if (INSN_P (insn)) |
6fb5fa3c | 4229 | df_insn_rescan (insn); |
5b0264cb | 4230 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 4231 | LABEL. */ |
5b0264cb NS |
4232 | gcc_assert (BB_HEAD (bb) != insn |
4233 | /* Avoid clobbering of structure when creating new BB. */ | |
4234 | || BARRIER_P (insn) | |
a38e7aa5 | 4235 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 | 4236 | } |
a0ae8e8d RK |
4237 | } |
4238 | ||
6fb5fa3c DB |
4239 | /* Replace insn with an deleted instruction note. */ |
4240 | ||
0ce2b299 | 4241 | void |
df0b55f0 | 4242 | set_insn_deleted (rtx_insn *insn) |
6fb5fa3c | 4243 | { |
39718607 | 4244 | if (INSN_P (insn)) |
df0b55f0 | 4245 | df_insn_delete (insn); |
6fb5fa3c DB |
4246 | PUT_CODE (insn, NOTE); |
4247 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
4248 | } | |
4249 | ||
4250 | ||
1f397f45 SB |
4251 | /* Unlink INSN from the insn chain. |
4252 | ||
4253 | This function knows how to handle sequences. | |
4254 | ||
4255 | This function does not invalidate data flow information associated with | |
4256 | INSN (i.e. does not call df_insn_delete). That makes this function | |
4257 | usable for only disconnecting an insn from the chain, and re-emit it | |
4258 | elsewhere later. | |
4259 | ||
4260 | To later insert INSN elsewhere in the insn chain via add_insn and | |
4261 | similar functions, PREV_INSN and NEXT_INSN must be nullified by | |
4262 | the caller. Nullifying them here breaks many insn chain walks. | |
4263 | ||
4264 | To really delete an insn and related DF information, use delete_insn. */ | |
4265 | ||
89e99eea | 4266 | void |
4dea3bff | 4267 | remove_insn (rtx_insn *insn) |
89e99eea | 4268 | { |
1130d5e3 DM |
4269 | rtx_insn *next = NEXT_INSN (insn); |
4270 | rtx_insn *prev = PREV_INSN (insn); | |
53c17031 JH |
4271 | basic_block bb; |
4272 | ||
89e99eea DB |
4273 | if (prev) |
4274 | { | |
0f82e5c9 | 4275 | SET_NEXT_INSN (prev) = next; |
4b4bf941 | 4276 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea | 4277 | { |
e6eda746 DM |
4278 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4279 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
89e99eea DB |
4280 | } |
4281 | } | |
89e99eea DB |
4282 | else |
4283 | { | |
614d5bd8 AM |
4284 | struct sequence_stack *seq; |
4285 | ||
4286 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4287 | if (insn == seq->first) | |
89e99eea | 4288 | { |
614d5bd8 | 4289 | seq->first = next; |
89e99eea DB |
4290 | break; |
4291 | } | |
4292 | ||
614d5bd8 | 4293 | gcc_assert (seq); |
89e99eea DB |
4294 | } |
4295 | ||
4296 | if (next) | |
4297 | { | |
0f82e5c9 | 4298 | SET_PREV_INSN (next) = prev; |
4b4bf941 | 4299 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4300 | { |
4301 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4302 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4303 | } | |
89e99eea | 4304 | } |
89e99eea DB |
4305 | else |
4306 | { | |
614d5bd8 AM |
4307 | struct sequence_stack *seq; |
4308 | ||
4309 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4310 | if (insn == seq->last) | |
89e99eea | 4311 | { |
614d5bd8 | 4312 | seq->last = prev; |
89e99eea DB |
4313 | break; |
4314 | } | |
4315 | ||
614d5bd8 | 4316 | gcc_assert (seq); |
89e99eea | 4317 | } |
80eb8028 | 4318 | |
80eb8028 | 4319 | /* Fix up basic block boundaries, if necessary. */ |
4b4bf941 | 4320 | if (!BARRIER_P (insn) |
53c17031 JH |
4321 | && (bb = BLOCK_FOR_INSN (insn))) |
4322 | { | |
a813c111 | 4323 | if (BB_HEAD (bb) == insn) |
53c17031 | 4324 | { |
3bf1e984 RK |
4325 | /* Never ever delete the basic block note without deleting whole |
4326 | basic block. */ | |
5b0264cb | 4327 | gcc_assert (!NOTE_P (insn)); |
1130d5e3 | 4328 | BB_HEAD (bb) = next; |
53c17031 | 4329 | } |
a813c111 | 4330 | if (BB_END (bb) == insn) |
1130d5e3 | 4331 | BB_END (bb) = prev; |
53c17031 | 4332 | } |
89e99eea DB |
4333 | } |
4334 | ||
ee960939 OH |
4335 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
4336 | ||
4337 | void | |
502b8322 | 4338 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 4339 | { |
5b0264cb | 4340 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
4341 | |
4342 | /* Put the register usage information on the CALL. If there is already | |
4343 | some usage information, put ours at the end. */ | |
4344 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
4345 | { | |
4346 | rtx link; | |
4347 | ||
4348 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
4349 | link = XEXP (link, 1)) | |
4350 | ; | |
4351 | ||
4352 | XEXP (link, 1) = call_fusage; | |
4353 | } | |
4354 | else | |
4355 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
4356 | } | |
4357 | ||
23b2ce53 RS |
4358 | /* Delete all insns made since FROM. |
4359 | FROM becomes the new last instruction. */ | |
4360 | ||
4361 | void | |
fee3e72c | 4362 | delete_insns_since (rtx_insn *from) |
23b2ce53 RS |
4363 | { |
4364 | if (from == 0) | |
5936d944 | 4365 | set_first_insn (0); |
23b2ce53 | 4366 | else |
0f82e5c9 | 4367 | SET_NEXT_INSN (from) = 0; |
5936d944 | 4368 | set_last_insn (from); |
23b2ce53 RS |
4369 | } |
4370 | ||
5dab5552 MS |
4371 | /* This function is deprecated, please use sequences instead. |
4372 | ||
4373 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
4374 | The insns to be moved are those between FROM and TO. |
4375 | They are moved to a new position after the insn AFTER. | |
4376 | AFTER must not be FROM or TO or any insn in between. | |
4377 | ||
4378 | This function does not know about SEQUENCEs and hence should not be | |
4379 | called after delay-slot filling has been done. */ | |
4380 | ||
4381 | void | |
fee3e72c | 4382 | reorder_insns_nobb (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
23b2ce53 | 4383 | { |
b2b29377 MM |
4384 | if (flag_checking) |
4385 | { | |
4386 | for (rtx_insn *x = from; x != to; x = NEXT_INSN (x)) | |
4387 | gcc_assert (after != x); | |
4388 | gcc_assert (after != to); | |
4389 | } | |
4f8344eb | 4390 | |
23b2ce53 RS |
4391 | /* Splice this bunch out of where it is now. */ |
4392 | if (PREV_INSN (from)) | |
0f82e5c9 | 4393 | SET_NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); |
23b2ce53 | 4394 | if (NEXT_INSN (to)) |
0f82e5c9 | 4395 | SET_PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); |
5936d944 JH |
4396 | if (get_last_insn () == to) |
4397 | set_last_insn (PREV_INSN (from)); | |
4398 | if (get_insns () == from) | |
4399 | set_first_insn (NEXT_INSN (to)); | |
23b2ce53 RS |
4400 | |
4401 | /* Make the new neighbors point to it and it to them. */ | |
4402 | if (NEXT_INSN (after)) | |
0f82e5c9 | 4403 | SET_PREV_INSN (NEXT_INSN (after)) = to; |
23b2ce53 | 4404 | |
0f82e5c9 DM |
4405 | SET_NEXT_INSN (to) = NEXT_INSN (after); |
4406 | SET_PREV_INSN (from) = after; | |
4407 | SET_NEXT_INSN (after) = from; | |
c3284718 | 4408 | if (after == get_last_insn ()) |
5936d944 | 4409 | set_last_insn (to); |
23b2ce53 RS |
4410 | } |
4411 | ||
3c030e88 JH |
4412 | /* Same as function above, but take care to update BB boundaries. */ |
4413 | void | |
ac9d2d2c | 4414 | reorder_insns (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
3c030e88 | 4415 | { |
ac9d2d2c | 4416 | rtx_insn *prev = PREV_INSN (from); |
3c030e88 JH |
4417 | basic_block bb, bb2; |
4418 | ||
4419 | reorder_insns_nobb (from, to, after); | |
4420 | ||
4b4bf941 | 4421 | if (!BARRIER_P (after) |
3c030e88 JH |
4422 | && (bb = BLOCK_FOR_INSN (after))) |
4423 | { | |
b2908ba6 | 4424 | rtx_insn *x; |
6fb5fa3c | 4425 | df_set_bb_dirty (bb); |
68252e27 | 4426 | |
4b4bf941 | 4427 | if (!BARRIER_P (from) |
3c030e88 JH |
4428 | && (bb2 = BLOCK_FOR_INSN (from))) |
4429 | { | |
a813c111 | 4430 | if (BB_END (bb2) == to) |
1130d5e3 | 4431 | BB_END (bb2) = prev; |
6fb5fa3c | 4432 | df_set_bb_dirty (bb2); |
3c030e88 JH |
4433 | } |
4434 | ||
a813c111 | 4435 | if (BB_END (bb) == after) |
1130d5e3 | 4436 | BB_END (bb) = to; |
3c030e88 JH |
4437 | |
4438 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 4439 | if (!BARRIER_P (x)) |
63642d5a | 4440 | df_insn_change_bb (x, bb); |
3c030e88 JH |
4441 | } |
4442 | } | |
4443 | ||
23b2ce53 | 4444 | \f |
2f937369 DM |
4445 | /* Emit insn(s) of given code and pattern |
4446 | at a specified place within the doubly-linked list. | |
23b2ce53 | 4447 | |
2f937369 DM |
4448 | All of the emit_foo global entry points accept an object |
4449 | X which is either an insn list or a PATTERN of a single | |
4450 | instruction. | |
23b2ce53 | 4451 | |
2f937369 DM |
4452 | There are thus a few canonical ways to generate code and |
4453 | emit it at a specific place in the instruction stream. For | |
4454 | example, consider the instruction named SPOT and the fact that | |
4455 | we would like to emit some instructions before SPOT. We might | |
4456 | do it like this: | |
23b2ce53 | 4457 | |
2f937369 DM |
4458 | start_sequence (); |
4459 | ... emit the new instructions ... | |
4460 | insns_head = get_insns (); | |
4461 | end_sequence (); | |
23b2ce53 | 4462 | |
2f937369 | 4463 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4464 | |
2f937369 DM |
4465 | It used to be common to generate SEQUENCE rtl instead, but that |
4466 | is a relic of the past which no longer occurs. The reason is that | |
4467 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4468 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4469 | |
cd459bf8 | 4470 | static rtx_insn * |
4dea3bff DM |
4471 | emit_pattern_before_noloc (rtx x, rtx_insn *before, rtx_insn *last, |
4472 | basic_block bb, | |
167b9fae | 4473 | rtx_insn *(*make_raw) (rtx)) |
23b2ce53 | 4474 | { |
167b9fae | 4475 | rtx_insn *insn; |
23b2ce53 | 4476 | |
5b0264cb | 4477 | gcc_assert (before); |
2f937369 DM |
4478 | |
4479 | if (x == NULL_RTX) | |
4dea3bff | 4480 | return last; |
2f937369 DM |
4481 | |
4482 | switch (GET_CODE (x)) | |
23b2ce53 | 4483 | { |
b5b8b0ac | 4484 | case DEBUG_INSN: |
2f937369 DM |
4485 | case INSN: |
4486 | case JUMP_INSN: | |
4487 | case CALL_INSN: | |
4488 | case CODE_LABEL: | |
4489 | case BARRIER: | |
4490 | case NOTE: | |
167b9fae | 4491 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
4492 | while (insn) |
4493 | { | |
167b9fae | 4494 | rtx_insn *next = NEXT_INSN (insn); |
6fb5fa3c | 4495 | add_insn_before (insn, before, bb); |
2f937369 DM |
4496 | last = insn; |
4497 | insn = next; | |
4498 | } | |
4499 | break; | |
4500 | ||
4501 | #ifdef ENABLE_RTL_CHECKING | |
4502 | case SEQUENCE: | |
5b0264cb | 4503 | gcc_unreachable (); |
2f937369 DM |
4504 | break; |
4505 | #endif | |
4506 | ||
4507 | default: | |
5f02387d | 4508 | last = (*make_raw) (x); |
6fb5fa3c | 4509 | add_insn_before (last, before, bb); |
2f937369 | 4510 | break; |
23b2ce53 RS |
4511 | } |
4512 | ||
4dea3bff | 4513 | return last; |
23b2ce53 RS |
4514 | } |
4515 | ||
5f02387d NF |
4516 | /* Make X be output before the instruction BEFORE. */ |
4517 | ||
cd459bf8 | 4518 | rtx_insn * |
596f2b17 | 4519 | emit_insn_before_noloc (rtx x, rtx_insn *before, basic_block bb) |
5f02387d NF |
4520 | { |
4521 | return emit_pattern_before_noloc (x, before, before, bb, make_insn_raw); | |
4522 | } | |
4523 | ||
2f937369 | 4524 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4525 | and output it before the instruction BEFORE. */ |
4526 | ||
1476d1bd | 4527 | rtx_jump_insn * |
596f2b17 | 4528 | emit_jump_insn_before_noloc (rtx x, rtx_insn *before) |
23b2ce53 | 4529 | { |
1476d1bd | 4530 | return as_a <rtx_jump_insn *> ( |
4dea3bff | 4531 | emit_pattern_before_noloc (x, before, NULL, NULL, |
1476d1bd | 4532 | make_jump_insn_raw)); |
23b2ce53 RS |
4533 | } |
4534 | ||
2f937369 | 4535 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4536 | and output it before the instruction BEFORE. */ |
4537 | ||
cd459bf8 | 4538 | rtx_insn * |
596f2b17 | 4539 | emit_call_insn_before_noloc (rtx x, rtx_insn *before) |
969d70ca | 4540 | { |
4dea3bff | 4541 | return emit_pattern_before_noloc (x, before, NULL, NULL, |
5f02387d | 4542 | make_call_insn_raw); |
969d70ca JH |
4543 | } |
4544 | ||
b5b8b0ac AO |
4545 | /* Make an instruction with body X and code DEBUG_INSN |
4546 | and output it before the instruction BEFORE. */ | |
4547 | ||
cd459bf8 | 4548 | rtx_insn * |
4dea3bff | 4549 | emit_debug_insn_before_noloc (rtx x, rtx_insn *before) |
b5b8b0ac | 4550 | { |
4dea3bff | 4551 | return emit_pattern_before_noloc (x, before, NULL, NULL, |
5f02387d | 4552 | make_debug_insn_raw); |
b5b8b0ac AO |
4553 | } |
4554 | ||
23b2ce53 | 4555 | /* Make an insn of code BARRIER |
e881bb1b | 4556 | and output it before the insn BEFORE. */ |
23b2ce53 | 4557 | |
cd459bf8 | 4558 | rtx_barrier * |
4dea3bff | 4559 | emit_barrier_before (rtx_insn *before) |
23b2ce53 | 4560 | { |
cd459bf8 | 4561 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4562 | |
4563 | INSN_UID (insn) = cur_insn_uid++; | |
4564 | ||
6fb5fa3c | 4565 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4566 | return insn; |
4567 | } | |
4568 | ||
e881bb1b RH |
4569 | /* Emit the label LABEL before the insn BEFORE. */ |
4570 | ||
1476d1bd | 4571 | rtx_code_label * |
4dea3bff | 4572 | emit_label_before (rtx_code_label *label, rtx_insn *before) |
e881bb1b | 4573 | { |
468660d3 SB |
4574 | gcc_checking_assert (INSN_UID (label) == 0); |
4575 | INSN_UID (label) = cur_insn_uid++; | |
4576 | add_insn_before (label, before, NULL); | |
4dea3bff | 4577 | return label; |
e881bb1b | 4578 | } |
23b2ce53 | 4579 | \f |
2f937369 DM |
4580 | /* Helper for emit_insn_after, handles lists of instructions |
4581 | efficiently. */ | |
23b2ce53 | 4582 | |
e6eda746 | 4583 | static rtx_insn * |
4dea3bff | 4584 | emit_insn_after_1 (rtx_insn *first, rtx_insn *after, basic_block bb) |
23b2ce53 | 4585 | { |
1130d5e3 DM |
4586 | rtx_insn *last; |
4587 | rtx_insn *after_after; | |
6fb5fa3c DB |
4588 | if (!bb && !BARRIER_P (after)) |
4589 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4590 | |
6fb5fa3c | 4591 | if (bb) |
23b2ce53 | 4592 | { |
6fb5fa3c | 4593 | df_set_bb_dirty (bb); |
2f937369 | 4594 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4595 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4596 | { |
4597 | set_block_for_insn (last, bb); | |
4598 | df_insn_rescan (last); | |
4599 | } | |
4b4bf941 | 4600 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4601 | { |
4602 | set_block_for_insn (last, bb); | |
4603 | df_insn_rescan (last); | |
4604 | } | |
a813c111 | 4605 | if (BB_END (bb) == after) |
1130d5e3 | 4606 | BB_END (bb) = last; |
23b2ce53 RS |
4607 | } |
4608 | else | |
2f937369 DM |
4609 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4610 | continue; | |
4611 | ||
4612 | after_after = NEXT_INSN (after); | |
4613 | ||
0f82e5c9 DM |
4614 | SET_NEXT_INSN (after) = first; |
4615 | SET_PREV_INSN (first) = after; | |
4616 | SET_NEXT_INSN (last) = after_after; | |
2f937369 | 4617 | if (after_after) |
0f82e5c9 | 4618 | SET_PREV_INSN (after_after) = last; |
2f937369 | 4619 | |
c3284718 | 4620 | if (after == get_last_insn ()) |
5936d944 | 4621 | set_last_insn (last); |
e855c69d | 4622 | |
2f937369 DM |
4623 | return last; |
4624 | } | |
4625 | ||
cd459bf8 | 4626 | static rtx_insn * |
4dea3bff | 4627 | emit_pattern_after_noloc (rtx x, rtx_insn *after, basic_block bb, |
167b9fae | 4628 | rtx_insn *(*make_raw)(rtx)) |
2f937369 | 4629 | { |
e6eda746 | 4630 | rtx_insn *last = after; |
2f937369 | 4631 | |
5b0264cb | 4632 | gcc_assert (after); |
2f937369 DM |
4633 | |
4634 | if (x == NULL_RTX) | |
e6eda746 | 4635 | return last; |
2f937369 DM |
4636 | |
4637 | switch (GET_CODE (x)) | |
23b2ce53 | 4638 | { |
b5b8b0ac | 4639 | case DEBUG_INSN: |
2f937369 DM |
4640 | case INSN: |
4641 | case JUMP_INSN: | |
4642 | case CALL_INSN: | |
4643 | case CODE_LABEL: | |
4644 | case BARRIER: | |
4645 | case NOTE: | |
1130d5e3 | 4646 | last = emit_insn_after_1 (as_a <rtx_insn *> (x), after, bb); |
2f937369 DM |
4647 | break; |
4648 | ||
4649 | #ifdef ENABLE_RTL_CHECKING | |
4650 | case SEQUENCE: | |
5b0264cb | 4651 | gcc_unreachable (); |
2f937369 DM |
4652 | break; |
4653 | #endif | |
4654 | ||
4655 | default: | |
5f02387d | 4656 | last = (*make_raw) (x); |
6fb5fa3c | 4657 | add_insn_after (last, after, bb); |
2f937369 | 4658 | break; |
23b2ce53 RS |
4659 | } |
4660 | ||
e6eda746 | 4661 | return last; |
23b2ce53 RS |
4662 | } |
4663 | ||
5f02387d NF |
4664 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4665 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
4666 | ||
cd459bf8 | 4667 | rtx_insn * |
4dea3bff | 4668 | emit_insn_after_noloc (rtx x, rtx_insn *after, basic_block bb) |
5f02387d NF |
4669 | { |
4670 | return emit_pattern_after_noloc (x, after, bb, make_insn_raw); | |
4671 | } | |
4672 | ||
255680cf | 4673 | |
2f937369 | 4674 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4675 | and output it after the insn AFTER. */ |
4676 | ||
1476d1bd | 4677 | rtx_jump_insn * |
4dea3bff | 4678 | emit_jump_insn_after_noloc (rtx x, rtx_insn *after) |
23b2ce53 | 4679 | { |
1476d1bd MM |
4680 | return as_a <rtx_jump_insn *> ( |
4681 | emit_pattern_after_noloc (x, after, NULL, make_jump_insn_raw)); | |
2f937369 DM |
4682 | } |
4683 | ||
4684 | /* Make an instruction with body X and code CALL_INSN | |
4685 | and output it after the instruction AFTER. */ | |
4686 | ||
cd459bf8 | 4687 | rtx_insn * |
4dea3bff | 4688 | emit_call_insn_after_noloc (rtx x, rtx_insn *after) |
2f937369 | 4689 | { |
5f02387d | 4690 | return emit_pattern_after_noloc (x, after, NULL, make_call_insn_raw); |
23b2ce53 RS |
4691 | } |
4692 | ||
b5b8b0ac AO |
4693 | /* Make an instruction with body X and code CALL_INSN |
4694 | and output it after the instruction AFTER. */ | |
4695 | ||
cd459bf8 | 4696 | rtx_insn * |
4dea3bff | 4697 | emit_debug_insn_after_noloc (rtx x, rtx_insn *after) |
b5b8b0ac | 4698 | { |
5f02387d | 4699 | return emit_pattern_after_noloc (x, after, NULL, make_debug_insn_raw); |
b5b8b0ac AO |
4700 | } |
4701 | ||
23b2ce53 RS |
4702 | /* Make an insn of code BARRIER |
4703 | and output it after the insn AFTER. */ | |
4704 | ||
cd459bf8 | 4705 | rtx_barrier * |
4dea3bff | 4706 | emit_barrier_after (rtx_insn *after) |
23b2ce53 | 4707 | { |
cd459bf8 | 4708 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4709 | |
4710 | INSN_UID (insn) = cur_insn_uid++; | |
4711 | ||
6fb5fa3c | 4712 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4713 | return insn; |
4714 | } | |
4715 | ||
4716 | /* Emit the label LABEL after the insn AFTER. */ | |
4717 | ||
cd459bf8 | 4718 | rtx_insn * |
4dea3bff | 4719 | emit_label_after (rtx_insn *label, rtx_insn *after) |
23b2ce53 | 4720 | { |
468660d3 SB |
4721 | gcc_checking_assert (INSN_UID (label) == 0); |
4722 | INSN_UID (label) = cur_insn_uid++; | |
4723 | add_insn_after (label, after, NULL); | |
4dea3bff | 4724 | return label; |
23b2ce53 | 4725 | } |
96fba521 SB |
4726 | \f |
4727 | /* Notes require a bit of special handling: Some notes need to have their | |
4728 | BLOCK_FOR_INSN set, others should never have it set, and some should | |
4729 | have it set or clear depending on the context. */ | |
4730 | ||
4731 | /* Return true iff a note of kind SUBTYPE should be emitted with routines | |
4732 | that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the | |
4733 | caller is asked to emit a note before BB_HEAD, or after BB_END. */ | |
4734 | ||
4735 | static bool | |
4736 | note_outside_basic_block_p (enum insn_note subtype, bool on_bb_boundary_p) | |
4737 | { | |
4738 | switch (subtype) | |
4739 | { | |
4740 | /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */ | |
4741 | case NOTE_INSN_SWITCH_TEXT_SECTIONS: | |
4742 | return true; | |
4743 | ||
4744 | /* Notes for var tracking and EH region markers can appear between or | |
4745 | inside basic blocks. If the caller is emitting on the basic block | |
4746 | boundary, do not set BLOCK_FOR_INSN on the new note. */ | |
4747 | case NOTE_INSN_VAR_LOCATION: | |
96fba521 SB |
4748 | case NOTE_INSN_EH_REGION_BEG: |
4749 | case NOTE_INSN_EH_REGION_END: | |
4750 | return on_bb_boundary_p; | |
4751 | ||
4752 | /* Otherwise, BLOCK_FOR_INSN must be set. */ | |
4753 | default: | |
4754 | return false; | |
4755 | } | |
4756 | } | |
23b2ce53 RS |
4757 | |
4758 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4759 | ||
66e8df53 | 4760 | rtx_note * |
589e43f9 | 4761 | emit_note_after (enum insn_note subtype, rtx_insn *after) |
23b2ce53 | 4762 | { |
66e8df53 | 4763 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4764 | basic_block bb = BARRIER_P (after) ? NULL : BLOCK_FOR_INSN (after); |
4765 | bool on_bb_boundary_p = (bb != NULL && BB_END (bb) == after); | |
4766 | ||
4767 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4768 | add_insn_after_nobb (note, after); | |
4769 | else | |
4770 | add_insn_after (note, after, bb); | |
4771 | return note; | |
4772 | } | |
4773 | ||
4774 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ | |
4775 | ||
66e8df53 | 4776 | rtx_note * |
89b6250d | 4777 | emit_note_before (enum insn_note subtype, rtx_insn *before) |
96fba521 | 4778 | { |
66e8df53 | 4779 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4780 | basic_block bb = BARRIER_P (before) ? NULL : BLOCK_FOR_INSN (before); |
4781 | bool on_bb_boundary_p = (bb != NULL && BB_HEAD (bb) == before); | |
4782 | ||
4783 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4784 | add_insn_before_nobb (note, before); | |
4785 | else | |
4786 | add_insn_before (note, before, bb); | |
23b2ce53 RS |
4787 | return note; |
4788 | } | |
23b2ce53 | 4789 | \f |
e8110d6f NF |
4790 | /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC. |
4791 | MAKE_RAW indicates how to turn PATTERN into a real insn. */ | |
4792 | ||
cd459bf8 | 4793 | static rtx_insn * |
4dea3bff | 4794 | emit_pattern_after_setloc (rtx pattern, rtx_insn *after, location_t loc, |
167b9fae | 4795 | rtx_insn *(*make_raw) (rtx)) |
0d682900 | 4796 | { |
e67d1102 | 4797 | rtx_insn *last = emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
0d682900 | 4798 | |
a7102479 | 4799 | if (pattern == NULL_RTX || !loc) |
e67d1102 | 4800 | return last; |
dd3adcf8 | 4801 | |
2f937369 DM |
4802 | after = NEXT_INSN (after); |
4803 | while (1) | |
4804 | { | |
20d4397a EB |
4805 | if (active_insn_p (after) |
4806 | && !JUMP_TABLE_DATA_P (after) /* FIXME */ | |
4807 | && !INSN_LOCATION (after)) | |
5368224f | 4808 | INSN_LOCATION (after) = loc; |
2f937369 DM |
4809 | if (after == last) |
4810 | break; | |
4811 | after = NEXT_INSN (after); | |
4812 | } | |
e67d1102 | 4813 | return last; |
0d682900 JH |
4814 | } |
4815 | ||
e8110d6f NF |
4816 | /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN |
4817 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after | |
4818 | any DEBUG_INSNs. */ | |
4819 | ||
cd459bf8 | 4820 | static rtx_insn * |
df0b55f0 | 4821 | emit_pattern_after (rtx pattern, rtx_insn *after, bool skip_debug_insns, |
167b9fae | 4822 | rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4823 | { |
dc01c3d1 | 4824 | rtx_insn *prev = after; |
b5b8b0ac | 4825 | |
e8110d6f NF |
4826 | if (skip_debug_insns) |
4827 | while (DEBUG_INSN_P (prev)) | |
4828 | prev = PREV_INSN (prev); | |
b5b8b0ac AO |
4829 | |
4830 | if (INSN_P (prev)) | |
5368224f | 4831 | return emit_pattern_after_setloc (pattern, after, INSN_LOCATION (prev), |
e8110d6f | 4832 | make_raw); |
a7102479 | 4833 | else |
e8110d6f | 4834 | return emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
a7102479 JH |
4835 | } |
4836 | ||
5368224f | 4837 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4838 | rtx_insn * |
4dea3bff | 4839 | emit_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
0d682900 | 4840 | { |
e8110d6f NF |
4841 | return emit_pattern_after_setloc (pattern, after, loc, make_insn_raw); |
4842 | } | |
2f937369 | 4843 | |
5368224f | 4844 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4845 | rtx_insn * |
df0b55f0 | 4846 | emit_insn_after (rtx pattern, rtx_insn *after) |
e8110d6f NF |
4847 | { |
4848 | return emit_pattern_after (pattern, after, true, make_insn_raw); | |
4849 | } | |
dd3adcf8 | 4850 | |
5368224f | 4851 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4852 | rtx_jump_insn * |
4dea3bff | 4853 | emit_jump_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
e8110d6f | 4854 | { |
1476d1bd MM |
4855 | return as_a <rtx_jump_insn *> ( |
4856 | emit_pattern_after_setloc (pattern, after, loc, make_jump_insn_raw)); | |
0d682900 JH |
4857 | } |
4858 | ||
5368224f | 4859 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
1476d1bd | 4860 | rtx_jump_insn * |
df0b55f0 | 4861 | emit_jump_insn_after (rtx pattern, rtx_insn *after) |
a7102479 | 4862 | { |
1476d1bd MM |
4863 | return as_a <rtx_jump_insn *> ( |
4864 | emit_pattern_after (pattern, after, true, make_jump_insn_raw)); | |
a7102479 JH |
4865 | } |
4866 | ||
5368224f | 4867 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4868 | rtx_insn * |
4dea3bff | 4869 | emit_call_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
0d682900 | 4870 | { |
e8110d6f | 4871 | return emit_pattern_after_setloc (pattern, after, loc, make_call_insn_raw); |
0d682900 JH |
4872 | } |
4873 | ||
5368224f | 4874 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4875 | rtx_insn * |
df0b55f0 | 4876 | emit_call_insn_after (rtx pattern, rtx_insn *after) |
a7102479 | 4877 | { |
e8110d6f | 4878 | return emit_pattern_after (pattern, after, true, make_call_insn_raw); |
a7102479 JH |
4879 | } |
4880 | ||
5368224f | 4881 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4882 | rtx_insn * |
4dea3bff | 4883 | emit_debug_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
b5b8b0ac | 4884 | { |
e8110d6f | 4885 | return emit_pattern_after_setloc (pattern, after, loc, make_debug_insn_raw); |
b5b8b0ac AO |
4886 | } |
4887 | ||
5368224f | 4888 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4889 | rtx_insn * |
df0b55f0 | 4890 | emit_debug_insn_after (rtx pattern, rtx_insn *after) |
b5b8b0ac | 4891 | { |
e8110d6f | 4892 | return emit_pattern_after (pattern, after, false, make_debug_insn_raw); |
b5b8b0ac AO |
4893 | } |
4894 | ||
e8110d6f NF |
4895 | /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC. |
4896 | MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP | |
4897 | indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN, | |
4898 | CALL_INSN, etc. */ | |
4899 | ||
cd459bf8 | 4900 | static rtx_insn * |
4dea3bff DM |
4901 | emit_pattern_before_setloc (rtx pattern, rtx_insn *before, location_t loc, |
4902 | bool insnp, rtx_insn *(*make_raw) (rtx)) | |
0d682900 | 4903 | { |
dc01c3d1 DM |
4904 | rtx_insn *first = PREV_INSN (before); |
4905 | rtx_insn *last = emit_pattern_before_noloc (pattern, before, | |
4dea3bff | 4906 | insnp ? before : NULL, |
dc01c3d1 | 4907 | NULL, make_raw); |
a7102479 JH |
4908 | |
4909 | if (pattern == NULL_RTX || !loc) | |
dc01c3d1 | 4910 | return last; |
a7102479 | 4911 | |
26cb3993 JH |
4912 | if (!first) |
4913 | first = get_insns (); | |
4914 | else | |
4915 | first = NEXT_INSN (first); | |
a7102479 JH |
4916 | while (1) |
4917 | { | |
20d4397a EB |
4918 | if (active_insn_p (first) |
4919 | && !JUMP_TABLE_DATA_P (first) /* FIXME */ | |
4920 | && !INSN_LOCATION (first)) | |
5368224f | 4921 | INSN_LOCATION (first) = loc; |
a7102479 JH |
4922 | if (first == last) |
4923 | break; | |
4924 | first = NEXT_INSN (first); | |
4925 | } | |
dc01c3d1 | 4926 | return last; |
a7102479 JH |
4927 | } |
4928 | ||
e8110d6f NF |
4929 | /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN |
4930 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert | |
4931 | before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an | |
4932 | INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */ | |
4933 | ||
cd459bf8 | 4934 | static rtx_insn * |
df0b55f0 | 4935 | emit_pattern_before (rtx pattern, rtx_insn *before, bool skip_debug_insns, |
167b9fae | 4936 | bool insnp, rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4937 | { |
dc01c3d1 | 4938 | rtx_insn *next = before; |
b5b8b0ac | 4939 | |
e8110d6f NF |
4940 | if (skip_debug_insns) |
4941 | while (DEBUG_INSN_P (next)) | |
4942 | next = PREV_INSN (next); | |
b5b8b0ac AO |
4943 | |
4944 | if (INSN_P (next)) | |
5368224f | 4945 | return emit_pattern_before_setloc (pattern, before, INSN_LOCATION (next), |
e8110d6f | 4946 | insnp, make_raw); |
a7102479 | 4947 | else |
e8110d6f | 4948 | return emit_pattern_before_noloc (pattern, before, |
4dea3bff | 4949 | insnp ? before : NULL, |
e8110d6f | 4950 | NULL, make_raw); |
a7102479 JH |
4951 | } |
4952 | ||
5368224f | 4953 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4954 | rtx_insn * |
4dea3bff | 4955 | emit_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
a7102479 | 4956 | { |
e8110d6f NF |
4957 | return emit_pattern_before_setloc (pattern, before, loc, true, |
4958 | make_insn_raw); | |
4959 | } | |
a7102479 | 4960 | |
5368224f | 4961 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
cd459bf8 | 4962 | rtx_insn * |
df0b55f0 | 4963 | emit_insn_before (rtx pattern, rtx_insn *before) |
e8110d6f NF |
4964 | { |
4965 | return emit_pattern_before (pattern, before, true, true, make_insn_raw); | |
4966 | } | |
a7102479 | 4967 | |
5368224f | 4968 | /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4969 | rtx_jump_insn * |
4dea3bff | 4970 | emit_jump_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
e8110d6f | 4971 | { |
1476d1bd MM |
4972 | return as_a <rtx_jump_insn *> ( |
4973 | emit_pattern_before_setloc (pattern, before, loc, false, | |
4974 | make_jump_insn_raw)); | |
a7102479 JH |
4975 | } |
4976 | ||
5368224f | 4977 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
1476d1bd | 4978 | rtx_jump_insn * |
df0b55f0 | 4979 | emit_jump_insn_before (rtx pattern, rtx_insn *before) |
a7102479 | 4980 | { |
1476d1bd MM |
4981 | return as_a <rtx_jump_insn *> ( |
4982 | emit_pattern_before (pattern, before, true, false, | |
4983 | make_jump_insn_raw)); | |
a7102479 JH |
4984 | } |
4985 | ||
5368224f | 4986 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4987 | rtx_insn * |
4dea3bff | 4988 | emit_call_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
a7102479 | 4989 | { |
e8110d6f NF |
4990 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4991 | make_call_insn_raw); | |
0d682900 | 4992 | } |
a7102479 | 4993 | |
e8110d6f | 4994 | /* Like emit_call_insn_before_noloc, |
5368224f | 4995 | but set insn_location according to BEFORE. */ |
cd459bf8 | 4996 | rtx_insn * |
596f2b17 | 4997 | emit_call_insn_before (rtx pattern, rtx_insn *before) |
a7102479 | 4998 | { |
e8110d6f NF |
4999 | return emit_pattern_before (pattern, before, true, false, |
5000 | make_call_insn_raw); | |
a7102479 | 5001 | } |
b5b8b0ac | 5002 | |
5368224f | 5003 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 5004 | rtx_insn * |
4dea3bff | 5005 | emit_debug_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
b5b8b0ac | 5006 | { |
e8110d6f NF |
5007 | return emit_pattern_before_setloc (pattern, before, loc, false, |
5008 | make_debug_insn_raw); | |
b5b8b0ac AO |
5009 | } |
5010 | ||
e8110d6f | 5011 | /* Like emit_debug_insn_before_noloc, |
5368224f | 5012 | but set insn_location according to BEFORE. */ |
cd459bf8 | 5013 | rtx_insn * |
3a6216b0 | 5014 | emit_debug_insn_before (rtx pattern, rtx_insn *before) |
b5b8b0ac | 5015 | { |
e8110d6f NF |
5016 | return emit_pattern_before (pattern, before, false, false, |
5017 | make_debug_insn_raw); | |
b5b8b0ac | 5018 | } |
0d682900 | 5019 | \f |
2f937369 DM |
5020 | /* Take X and emit it at the end of the doubly-linked |
5021 | INSN list. | |
23b2ce53 RS |
5022 | |
5023 | Returns the last insn emitted. */ | |
5024 | ||
cd459bf8 | 5025 | rtx_insn * |
502b8322 | 5026 | emit_insn (rtx x) |
23b2ce53 | 5027 | { |
cd459bf8 DM |
5028 | rtx_insn *last = get_last_insn (); |
5029 | rtx_insn *insn; | |
23b2ce53 | 5030 | |
2f937369 DM |
5031 | if (x == NULL_RTX) |
5032 | return last; | |
23b2ce53 | 5033 | |
2f937369 DM |
5034 | switch (GET_CODE (x)) |
5035 | { | |
b5b8b0ac | 5036 | case DEBUG_INSN: |
2f937369 DM |
5037 | case INSN: |
5038 | case JUMP_INSN: | |
5039 | case CALL_INSN: | |
5040 | case CODE_LABEL: | |
5041 | case BARRIER: | |
5042 | case NOTE: | |
cd459bf8 | 5043 | insn = as_a <rtx_insn *> (x); |
2f937369 | 5044 | while (insn) |
23b2ce53 | 5045 | { |
cd459bf8 | 5046 | rtx_insn *next = NEXT_INSN (insn); |
23b2ce53 | 5047 | add_insn (insn); |
2f937369 DM |
5048 | last = insn; |
5049 | insn = next; | |
23b2ce53 | 5050 | } |
2f937369 | 5051 | break; |
23b2ce53 | 5052 | |
2f937369 | 5053 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 5054 | case JUMP_TABLE_DATA: |
2f937369 | 5055 | case SEQUENCE: |
5b0264cb | 5056 | gcc_unreachable (); |
2f937369 DM |
5057 | break; |
5058 | #endif | |
23b2ce53 | 5059 | |
2f937369 DM |
5060 | default: |
5061 | last = make_insn_raw (x); | |
5062 | add_insn (last); | |
5063 | break; | |
23b2ce53 RS |
5064 | } |
5065 | ||
5066 | return last; | |
5067 | } | |
5068 | ||
b5b8b0ac AO |
5069 | /* Make an insn of code DEBUG_INSN with pattern X |
5070 | and add it to the end of the doubly-linked list. */ | |
5071 | ||
cd459bf8 | 5072 | rtx_insn * |
b5b8b0ac AO |
5073 | emit_debug_insn (rtx x) |
5074 | { | |
cd459bf8 DM |
5075 | rtx_insn *last = get_last_insn (); |
5076 | rtx_insn *insn; | |
b5b8b0ac AO |
5077 | |
5078 | if (x == NULL_RTX) | |
5079 | return last; | |
5080 | ||
5081 | switch (GET_CODE (x)) | |
5082 | { | |
5083 | case DEBUG_INSN: | |
5084 | case INSN: | |
5085 | case JUMP_INSN: | |
5086 | case CALL_INSN: | |
5087 | case CODE_LABEL: | |
5088 | case BARRIER: | |
5089 | case NOTE: | |
cd459bf8 | 5090 | insn = as_a <rtx_insn *> (x); |
b5b8b0ac AO |
5091 | while (insn) |
5092 | { | |
cd459bf8 | 5093 | rtx_insn *next = NEXT_INSN (insn); |
b5b8b0ac AO |
5094 | add_insn (insn); |
5095 | last = insn; | |
5096 | insn = next; | |
5097 | } | |
5098 | break; | |
5099 | ||
5100 | #ifdef ENABLE_RTL_CHECKING | |
39718607 | 5101 | case JUMP_TABLE_DATA: |
b5b8b0ac AO |
5102 | case SEQUENCE: |
5103 | gcc_unreachable (); | |
5104 | break; | |
5105 | #endif | |
5106 | ||
5107 | default: | |
5108 | last = make_debug_insn_raw (x); | |
5109 | add_insn (last); | |
5110 | break; | |
5111 | } | |
5112 | ||
5113 | return last; | |
5114 | } | |
5115 | ||
2f937369 DM |
5116 | /* Make an insn of code JUMP_INSN with pattern X |
5117 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5118 | |
cd459bf8 | 5119 | rtx_insn * |
502b8322 | 5120 | emit_jump_insn (rtx x) |
23b2ce53 | 5121 | { |
cd459bf8 DM |
5122 | rtx_insn *last = NULL; |
5123 | rtx_insn *insn; | |
23b2ce53 | 5124 | |
2f937369 | 5125 | switch (GET_CODE (x)) |
23b2ce53 | 5126 | { |
b5b8b0ac | 5127 | case DEBUG_INSN: |
2f937369 DM |
5128 | case INSN: |
5129 | case JUMP_INSN: | |
5130 | case CALL_INSN: | |
5131 | case CODE_LABEL: | |
5132 | case BARRIER: | |
5133 | case NOTE: | |
cd459bf8 | 5134 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
5135 | while (insn) |
5136 | { | |
cd459bf8 | 5137 | rtx_insn *next = NEXT_INSN (insn); |
2f937369 DM |
5138 | add_insn (insn); |
5139 | last = insn; | |
5140 | insn = next; | |
5141 | } | |
5142 | break; | |
e0a5c5eb | 5143 | |
2f937369 | 5144 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 5145 | case JUMP_TABLE_DATA: |
2f937369 | 5146 | case SEQUENCE: |
5b0264cb | 5147 | gcc_unreachable (); |
2f937369 DM |
5148 | break; |
5149 | #endif | |
e0a5c5eb | 5150 | |
2f937369 DM |
5151 | default: |
5152 | last = make_jump_insn_raw (x); | |
5153 | add_insn (last); | |
5154 | break; | |
3c030e88 | 5155 | } |
e0a5c5eb RS |
5156 | |
5157 | return last; | |
5158 | } | |
5159 | ||
2f937369 | 5160 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
5161 | and add it to the end of the doubly-linked list. */ |
5162 | ||
cd459bf8 | 5163 | rtx_insn * |
502b8322 | 5164 | emit_call_insn (rtx x) |
23b2ce53 | 5165 | { |
cd459bf8 | 5166 | rtx_insn *insn; |
2f937369 DM |
5167 | |
5168 | switch (GET_CODE (x)) | |
23b2ce53 | 5169 | { |
b5b8b0ac | 5170 | case DEBUG_INSN: |
2f937369 DM |
5171 | case INSN: |
5172 | case JUMP_INSN: | |
5173 | case CALL_INSN: | |
5174 | case CODE_LABEL: | |
5175 | case BARRIER: | |
5176 | case NOTE: | |
5177 | insn = emit_insn (x); | |
5178 | break; | |
23b2ce53 | 5179 | |
2f937369 DM |
5180 | #ifdef ENABLE_RTL_CHECKING |
5181 | case SEQUENCE: | |
39718607 | 5182 | case JUMP_TABLE_DATA: |
5b0264cb | 5183 | gcc_unreachable (); |
2f937369 DM |
5184 | break; |
5185 | #endif | |
23b2ce53 | 5186 | |
2f937369 DM |
5187 | default: |
5188 | insn = make_call_insn_raw (x); | |
23b2ce53 | 5189 | add_insn (insn); |
2f937369 | 5190 | break; |
23b2ce53 | 5191 | } |
2f937369 DM |
5192 | |
5193 | return insn; | |
23b2ce53 RS |
5194 | } |
5195 | ||
5196 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
5197 | ||
1476d1bd MM |
5198 | rtx_code_label * |
5199 | emit_label (rtx uncast_label) | |
23b2ce53 | 5200 | { |
1476d1bd MM |
5201 | rtx_code_label *label = as_a <rtx_code_label *> (uncast_label); |
5202 | ||
468660d3 SB |
5203 | gcc_checking_assert (INSN_UID (label) == 0); |
5204 | INSN_UID (label) = cur_insn_uid++; | |
1476d1bd MM |
5205 | add_insn (label); |
5206 | return label; | |
23b2ce53 RS |
5207 | } |
5208 | ||
39718607 SB |
5209 | /* Make an insn of code JUMP_TABLE_DATA |
5210 | and add it to the end of the doubly-linked list. */ | |
5211 | ||
4598afdd | 5212 | rtx_jump_table_data * |
39718607 SB |
5213 | emit_jump_table_data (rtx table) |
5214 | { | |
4598afdd DM |
5215 | rtx_jump_table_data *jump_table_data = |
5216 | as_a <rtx_jump_table_data *> (rtx_alloc (JUMP_TABLE_DATA)); | |
39718607 SB |
5217 | INSN_UID (jump_table_data) = cur_insn_uid++; |
5218 | PATTERN (jump_table_data) = table; | |
5219 | BLOCK_FOR_INSN (jump_table_data) = NULL; | |
5220 | add_insn (jump_table_data); | |
5221 | return jump_table_data; | |
5222 | } | |
5223 | ||
23b2ce53 RS |
5224 | /* Make an insn of code BARRIER |
5225 | and add it to the end of the doubly-linked list. */ | |
5226 | ||
cd459bf8 | 5227 | rtx_barrier * |
502b8322 | 5228 | emit_barrier (void) |
23b2ce53 | 5229 | { |
cd459bf8 | 5230 | rtx_barrier *barrier = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
5231 | INSN_UID (barrier) = cur_insn_uid++; |
5232 | add_insn (barrier); | |
5233 | return barrier; | |
5234 | } | |
5235 | ||
5f2fc772 | 5236 | /* Emit a copy of note ORIG. */ |
502b8322 | 5237 | |
66e8df53 DM |
5238 | rtx_note * |
5239 | emit_note_copy (rtx_note *orig) | |
5f2fc772 | 5240 | { |
96fba521 | 5241 | enum insn_note kind = (enum insn_note) NOTE_KIND (orig); |
66e8df53 | 5242 | rtx_note *note = make_note_raw (kind); |
5f2fc772 | 5243 | NOTE_DATA (note) = NOTE_DATA (orig); |
5f2fc772 | 5244 | add_insn (note); |
2e040219 | 5245 | return note; |
23b2ce53 RS |
5246 | } |
5247 | ||
2e040219 NS |
5248 | /* Make an insn of code NOTE or type NOTE_NO |
5249 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5250 | |
66e8df53 | 5251 | rtx_note * |
a38e7aa5 | 5252 | emit_note (enum insn_note kind) |
23b2ce53 | 5253 | { |
66e8df53 | 5254 | rtx_note *note = make_note_raw (kind); |
23b2ce53 RS |
5255 | add_insn (note); |
5256 | return note; | |
5257 | } | |
5258 | ||
c41c1387 RS |
5259 | /* Emit a clobber of lvalue X. */ |
5260 | ||
cd459bf8 | 5261 | rtx_insn * |
c41c1387 RS |
5262 | emit_clobber (rtx x) |
5263 | { | |
5264 | /* CONCATs should not appear in the insn stream. */ | |
5265 | if (GET_CODE (x) == CONCAT) | |
5266 | { | |
5267 | emit_clobber (XEXP (x, 0)); | |
5268 | return emit_clobber (XEXP (x, 1)); | |
5269 | } | |
5270 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
5271 | } | |
5272 | ||
5273 | /* Return a sequence of insns to clobber lvalue X. */ | |
5274 | ||
cd459bf8 | 5275 | rtx_insn * |
c41c1387 RS |
5276 | gen_clobber (rtx x) |
5277 | { | |
cd459bf8 | 5278 | rtx_insn *seq; |
c41c1387 RS |
5279 | |
5280 | start_sequence (); | |
5281 | emit_clobber (x); | |
5282 | seq = get_insns (); | |
5283 | end_sequence (); | |
5284 | return seq; | |
5285 | } | |
5286 | ||
5287 | /* Emit a use of rvalue X. */ | |
5288 | ||
cd459bf8 | 5289 | rtx_insn * |
c41c1387 RS |
5290 | emit_use (rtx x) |
5291 | { | |
5292 | /* CONCATs should not appear in the insn stream. */ | |
5293 | if (GET_CODE (x) == CONCAT) | |
5294 | { | |
5295 | emit_use (XEXP (x, 0)); | |
5296 | return emit_use (XEXP (x, 1)); | |
5297 | } | |
5298 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
5299 | } | |
5300 | ||
5301 | /* Return a sequence of insns to use rvalue X. */ | |
5302 | ||
cd459bf8 | 5303 | rtx_insn * |
c41c1387 RS |
5304 | gen_use (rtx x) |
5305 | { | |
cd459bf8 | 5306 | rtx_insn *seq; |
c41c1387 RS |
5307 | |
5308 | start_sequence (); | |
5309 | emit_use (x); | |
5310 | seq = get_insns (); | |
5311 | end_sequence (); | |
5312 | return seq; | |
5313 | } | |
5314 | ||
c8912e53 RS |
5315 | /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction. |
5316 | Return the set in INSN that such notes describe, or NULL if the notes | |
5317 | have no meaning for INSN. */ | |
5318 | ||
5319 | rtx | |
5320 | set_for_reg_notes (rtx insn) | |
5321 | { | |
5322 | rtx pat, reg; | |
5323 | ||
5324 | if (!INSN_P (insn)) | |
5325 | return NULL_RTX; | |
5326 | ||
5327 | pat = PATTERN (insn); | |
5328 | if (GET_CODE (pat) == PARALLEL) | |
5329 | { | |
5330 | /* We do not use single_set because that ignores SETs of unused | |
5331 | registers. REG_EQUAL and REG_EQUIV notes really do require the | |
5332 | PARALLEL to have a single SET. */ | |
5333 | if (multiple_sets (insn)) | |
5334 | return NULL_RTX; | |
5335 | pat = XVECEXP (pat, 0, 0); | |
5336 | } | |
5337 | ||
5338 | if (GET_CODE (pat) != SET) | |
5339 | return NULL_RTX; | |
5340 | ||
5341 | reg = SET_DEST (pat); | |
5342 | ||
5343 | /* Notes apply to the contents of a STRICT_LOW_PART. */ | |
7f7379f6 KV |
5344 | if (GET_CODE (reg) == STRICT_LOW_PART |
5345 | || GET_CODE (reg) == ZERO_EXTRACT) | |
c8912e53 RS |
5346 | reg = XEXP (reg, 0); |
5347 | ||
5348 | /* Check that we have a register. */ | |
5349 | if (!(REG_P (reg) || GET_CODE (reg) == SUBREG)) | |
5350 | return NULL_RTX; | |
5351 | ||
5352 | return pat; | |
5353 | } | |
5354 | ||
87b47c85 | 5355 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a |
30f7a378 | 5356 | note of this type already exists, remove it first. */ |
87b47c85 | 5357 | |
3d238248 | 5358 | rtx |
502b8322 | 5359 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
5360 | { |
5361 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
5362 | ||
52488da1 JW |
5363 | switch (kind) |
5364 | { | |
5365 | case REG_EQUAL: | |
5366 | case REG_EQUIV: | |
8073cbd4 EB |
5367 | /* We need to support the REG_EQUAL on USE trick of find_reloads. */ |
5368 | if (!set_for_reg_notes (insn) && GET_CODE (PATTERN (insn)) != USE) | |
c8912e53 | 5369 | return NULL_RTX; |
52488da1 JW |
5370 | |
5371 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
5372 | It serves no useful purpose and breaks eliminate_regs. */ | |
5373 | if (GET_CODE (datum) == ASM_OPERANDS) | |
5374 | return NULL_RTX; | |
109374e2 RS |
5375 | |
5376 | /* Notes with side effects are dangerous. Even if the side-effect | |
5377 | initially mirrors one in PATTERN (INSN), later optimizations | |
5378 | might alter the way that the final register value is calculated | |
5379 | and so move or alter the side-effect in some way. The note would | |
5380 | then no longer be a valid substitution for SET_SRC. */ | |
5381 | if (side_effects_p (datum)) | |
5382 | return NULL_RTX; | |
52488da1 JW |
5383 | break; |
5384 | ||
5385 | default: | |
5386 | break; | |
5387 | } | |
3d238248 | 5388 | |
c8912e53 RS |
5389 | if (note) |
5390 | XEXP (note, 0) = datum; | |
5391 | else | |
5392 | { | |
5393 | add_reg_note (insn, kind, datum); | |
5394 | note = REG_NOTES (insn); | |
5395 | } | |
6fb5fa3c DB |
5396 | |
5397 | switch (kind) | |
3d238248 | 5398 | { |
6fb5fa3c DB |
5399 | case REG_EQUAL: |
5400 | case REG_EQUIV: | |
b2908ba6 | 5401 | df_notes_rescan (as_a <rtx_insn *> (insn)); |
6fb5fa3c DB |
5402 | break; |
5403 | default: | |
5404 | break; | |
3d238248 | 5405 | } |
87b47c85 | 5406 | |
c8912e53 | 5407 | return note; |
87b47c85 | 5408 | } |
7543f918 JR |
5409 | |
5410 | /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */ | |
5411 | rtx | |
5412 | set_dst_reg_note (rtx insn, enum reg_note kind, rtx datum, rtx dst) | |
5413 | { | |
c8912e53 | 5414 | rtx set = set_for_reg_notes (insn); |
7543f918 JR |
5415 | |
5416 | if (set && SET_DEST (set) == dst) | |
5417 | return set_unique_reg_note (insn, kind, datum); | |
5418 | return NULL_RTX; | |
5419 | } | |
23b2ce53 | 5420 | \f |
9d8895c9 RS |
5421 | /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a |
5422 | following barrier if the instruction needs one and if ALLOW_BARRIER_P | |
5423 | is true. | |
5424 | ||
23b2ce53 RS |
5425 | If X is a label, it is simply added into the insn chain. */ |
5426 | ||
cd459bf8 | 5427 | rtx_insn * |
9d8895c9 | 5428 | emit (rtx x, bool allow_barrier_p) |
23b2ce53 RS |
5429 | { |
5430 | enum rtx_code code = classify_insn (x); | |
5431 | ||
5b0264cb | 5432 | switch (code) |
23b2ce53 | 5433 | { |
5b0264cb NS |
5434 | case CODE_LABEL: |
5435 | return emit_label (x); | |
5436 | case INSN: | |
5437 | return emit_insn (x); | |
5438 | case JUMP_INSN: | |
5439 | { | |
cd459bf8 | 5440 | rtx_insn *insn = emit_jump_insn (x); |
9d8895c9 RS |
5441 | if (allow_barrier_p |
5442 | && (any_uncondjump_p (insn) || GET_CODE (x) == RETURN)) | |
5b0264cb NS |
5443 | return emit_barrier (); |
5444 | return insn; | |
5445 | } | |
5446 | case CALL_INSN: | |
5447 | return emit_call_insn (x); | |
b5b8b0ac AO |
5448 | case DEBUG_INSN: |
5449 | return emit_debug_insn (x); | |
5b0264cb NS |
5450 | default: |
5451 | gcc_unreachable (); | |
23b2ce53 | 5452 | } |
23b2ce53 RS |
5453 | } |
5454 | \f | |
e2500fed | 5455 | /* Space for free sequence stack entries. */ |
1431042e | 5456 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 5457 | |
4dfa0342 RH |
5458 | /* Begin emitting insns to a sequence. If this sequence will contain |
5459 | something that might cause the compiler to pop arguments to function | |
5460 | calls (because those pops have previously been deferred; see | |
5461 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
5462 | before calling this function. That will ensure that the deferred | |
5463 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
5464 | |
5465 | void | |
502b8322 | 5466 | start_sequence (void) |
23b2ce53 RS |
5467 | { |
5468 | struct sequence_stack *tem; | |
5469 | ||
e2500fed GK |
5470 | if (free_sequence_stack != NULL) |
5471 | { | |
5472 | tem = free_sequence_stack; | |
5473 | free_sequence_stack = tem->next; | |
5474 | } | |
5475 | else | |
766090c2 | 5476 | tem = ggc_alloc<sequence_stack> (); |
23b2ce53 | 5477 | |
614d5bd8 | 5478 | tem->next = get_current_sequence ()->next; |
5936d944 JH |
5479 | tem->first = get_insns (); |
5480 | tem->last = get_last_insn (); | |
614d5bd8 | 5481 | get_current_sequence ()->next = tem; |
23b2ce53 | 5482 | |
5936d944 JH |
5483 | set_first_insn (0); |
5484 | set_last_insn (0); | |
23b2ce53 RS |
5485 | } |
5486 | ||
5c7a310f MM |
5487 | /* Set up the insn chain starting with FIRST as the current sequence, |
5488 | saving the previously current one. See the documentation for | |
5489 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5490 | |
5491 | void | |
fee3e72c | 5492 | push_to_sequence (rtx_insn *first) |
23b2ce53 | 5493 | { |
fee3e72c | 5494 | rtx_insn *last; |
23b2ce53 RS |
5495 | |
5496 | start_sequence (); | |
5497 | ||
e84a58ff EB |
5498 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)) |
5499 | ; | |
23b2ce53 | 5500 | |
5936d944 JH |
5501 | set_first_insn (first); |
5502 | set_last_insn (last); | |
23b2ce53 RS |
5503 | } |
5504 | ||
bb27eeda SE |
5505 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5506 | looping through the list. */ | |
5507 | ||
5508 | void | |
fee3e72c | 5509 | push_to_sequence2 (rtx_insn *first, rtx_insn *last) |
bb27eeda SE |
5510 | { |
5511 | start_sequence (); | |
5512 | ||
5936d944 JH |
5513 | set_first_insn (first); |
5514 | set_last_insn (last); | |
bb27eeda SE |
5515 | } |
5516 | ||
f15ae3a1 TW |
5517 | /* Set up the outer-level insn chain |
5518 | as the current sequence, saving the previously current one. */ | |
5519 | ||
5520 | void | |
502b8322 | 5521 | push_topmost_sequence (void) |
f15ae3a1 | 5522 | { |
614d5bd8 | 5523 | struct sequence_stack *top; |
f15ae3a1 TW |
5524 | |
5525 | start_sequence (); | |
5526 | ||
614d5bd8 | 5527 | top = get_topmost_sequence (); |
5936d944 JH |
5528 | set_first_insn (top->first); |
5529 | set_last_insn (top->last); | |
f15ae3a1 TW |
5530 | } |
5531 | ||
5532 | /* After emitting to the outer-level insn chain, update the outer-level | |
5533 | insn chain, and restore the previous saved state. */ | |
5534 | ||
5535 | void | |
502b8322 | 5536 | pop_topmost_sequence (void) |
f15ae3a1 | 5537 | { |
614d5bd8 | 5538 | struct sequence_stack *top; |
f15ae3a1 | 5539 | |
614d5bd8 | 5540 | top = get_topmost_sequence (); |
5936d944 JH |
5541 | top->first = get_insns (); |
5542 | top->last = get_last_insn (); | |
f15ae3a1 TW |
5543 | |
5544 | end_sequence (); | |
5545 | } | |
5546 | ||
23b2ce53 RS |
5547 | /* After emitting to a sequence, restore previous saved state. |
5548 | ||
5c7a310f | 5549 | To get the contents of the sequence just made, you must call |
2f937369 | 5550 | `get_insns' *before* calling here. |
5c7a310f MM |
5551 | |
5552 | If the compiler might have deferred popping arguments while | |
5553 | generating this sequence, and this sequence will not be immediately | |
5554 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5555 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5556 | pops are inserted into this sequence, and not into some random |
5557 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5558 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5559 | |
5560 | void | |
502b8322 | 5561 | end_sequence (void) |
23b2ce53 | 5562 | { |
614d5bd8 | 5563 | struct sequence_stack *tem = get_current_sequence ()->next; |
23b2ce53 | 5564 | |
5936d944 JH |
5565 | set_first_insn (tem->first); |
5566 | set_last_insn (tem->last); | |
614d5bd8 | 5567 | get_current_sequence ()->next = tem->next; |
23b2ce53 | 5568 | |
e2500fed GK |
5569 | memset (tem, 0, sizeof (*tem)); |
5570 | tem->next = free_sequence_stack; | |
5571 | free_sequence_stack = tem; | |
23b2ce53 RS |
5572 | } |
5573 | ||
5574 | /* Return 1 if currently emitting into a sequence. */ | |
5575 | ||
5576 | int | |
502b8322 | 5577 | in_sequence_p (void) |
23b2ce53 | 5578 | { |
614d5bd8 | 5579 | return get_current_sequence ()->next != 0; |
23b2ce53 | 5580 | } |
23b2ce53 | 5581 | \f |
59ec66dc MM |
5582 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5583 | ||
2bbdec73 | 5584 | static void |
bd60bab2 | 5585 | init_virtual_regs (void) |
59ec66dc | 5586 | { |
bd60bab2 JH |
5587 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5588 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5589 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5590 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5591 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
32990d5b JJ |
5592 | regno_reg_rtx[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM] |
5593 | = virtual_preferred_stack_boundary_rtx; | |
49ad7cfa BS |
5594 | } |
5595 | ||
da43a810 BS |
5596 | \f |
5597 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5598 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5599 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5600 | static int copy_insn_n_scratches; | |
5601 | ||
5602 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5603 | copied an ASM_OPERANDS. | |
5604 | In that case, it is the original input-operand vector. */ | |
5605 | static rtvec orig_asm_operands_vector; | |
5606 | ||
5607 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5608 | copied an ASM_OPERANDS. | |
5609 | In that case, it is the copied input-operand vector. */ | |
5610 | static rtvec copy_asm_operands_vector; | |
5611 | ||
5612 | /* Likewise for the constraints vector. */ | |
5613 | static rtvec orig_asm_constraints_vector; | |
5614 | static rtvec copy_asm_constraints_vector; | |
5615 | ||
5616 | /* Recursively create a new copy of an rtx for copy_insn. | |
5617 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5618 | ASM_OPERANDs properly. | |
5619 | Normally, this function is not used directly; use copy_insn as front end. | |
5620 | However, you could first copy an insn pattern with copy_insn and then use | |
5621 | this function afterwards to properly copy any REG_NOTEs containing | |
5622 | SCRATCHes. */ | |
5623 | ||
5624 | rtx | |
502b8322 | 5625 | copy_insn_1 (rtx orig) |
da43a810 | 5626 | { |
b3694847 SS |
5627 | rtx copy; |
5628 | int i, j; | |
5629 | RTX_CODE code; | |
5630 | const char *format_ptr; | |
da43a810 | 5631 | |
cd9c1ca8 RH |
5632 | if (orig == NULL) |
5633 | return NULL; | |
5634 | ||
da43a810 BS |
5635 | code = GET_CODE (orig); |
5636 | ||
5637 | switch (code) | |
5638 | { | |
5639 | case REG: | |
a52a87c3 | 5640 | case DEBUG_EXPR: |
d8116890 | 5641 | CASE_CONST_ANY: |
da43a810 BS |
5642 | case SYMBOL_REF: |
5643 | case CODE_LABEL: | |
5644 | case PC: | |
276e0224 | 5645 | case RETURN: |
26898771 | 5646 | case SIMPLE_RETURN: |
da43a810 | 5647 | return orig; |
3e89ed8d | 5648 | case CLOBBER: |
bd1cd0d0 | 5649 | /* Share clobbers of hard registers, but do not share pseudo reg |
c5c5ba89 JH |
5650 | clobbers or clobbers of hard registers that originated as pseudos. |
5651 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
5652 | if (REG_P (XEXP (orig, 0)) |
5653 | && HARD_REGISTER_NUM_P (REGNO (XEXP (orig, 0))) | |
5654 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig, 0)))) | |
3e89ed8d JH |
5655 | return orig; |
5656 | break; | |
da43a810 BS |
5657 | |
5658 | case SCRATCH: | |
5659 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5660 | if (copy_insn_scratch_in[i] == orig) | |
5661 | return copy_insn_scratch_out[i]; | |
5662 | break; | |
5663 | ||
5664 | case CONST: | |
6fb5fa3c | 5665 | if (shared_const_p (orig)) |
da43a810 BS |
5666 | return orig; |
5667 | break; | |
750c9258 | 5668 | |
da43a810 BS |
5669 | /* A MEM with a constant address is not sharable. The problem is that |
5670 | the constant address may need to be reloaded. If the mem is shared, | |
5671 | then reloading one copy of this mem will cause all copies to appear | |
5672 | to have been reloaded. */ | |
5673 | ||
5674 | default: | |
5675 | break; | |
5676 | } | |
5677 | ||
aacd3885 RS |
5678 | /* Copy the various flags, fields, and other information. We assume |
5679 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5680 | not be copied. That is the sensible default behavior, and forces |
5681 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5682 | copy = shallow_copy_rtx (orig); |
da43a810 | 5683 | |
da43a810 | 5684 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ |
ec8e098d | 5685 | if (INSN_P (orig)) |
da43a810 | 5686 | { |
2adc7f12 JJ |
5687 | RTX_FLAG (copy, jump) = 0; |
5688 | RTX_FLAG (copy, call) = 0; | |
5689 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5690 | } |
750c9258 | 5691 | |
da43a810 BS |
5692 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5693 | ||
5694 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5695 | switch (*format_ptr++) |
5696 | { | |
5697 | case 'e': | |
5698 | if (XEXP (orig, i) != NULL) | |
5699 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5700 | break; | |
da43a810 | 5701 | |
aacd3885 RS |
5702 | case 'E': |
5703 | case 'V': | |
5704 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5705 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5706 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5707 | XVEC (copy, i) = copy_asm_operands_vector; | |
5708 | else if (XVEC (orig, i) != NULL) | |
5709 | { | |
5710 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5711 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5712 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5713 | } | |
5714 | break; | |
da43a810 | 5715 | |
aacd3885 RS |
5716 | case 't': |
5717 | case 'w': | |
5718 | case 'i': | |
91914e56 | 5719 | case 'p': |
aacd3885 RS |
5720 | case 's': |
5721 | case 'S': | |
5722 | case 'u': | |
5723 | case '0': | |
5724 | /* These are left unchanged. */ | |
5725 | break; | |
da43a810 | 5726 | |
aacd3885 RS |
5727 | default: |
5728 | gcc_unreachable (); | |
5729 | } | |
da43a810 BS |
5730 | |
5731 | if (code == SCRATCH) | |
5732 | { | |
5733 | i = copy_insn_n_scratches++; | |
5b0264cb | 5734 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5735 | copy_insn_scratch_in[i] = orig; |
5736 | copy_insn_scratch_out[i] = copy; | |
5737 | } | |
5738 | else if (code == ASM_OPERANDS) | |
5739 | { | |
6462bb43 AO |
5740 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5741 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5742 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5743 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5744 | } |
5745 | ||
5746 | return copy; | |
5747 | } | |
5748 | ||
5749 | /* Create a new copy of an rtx. | |
5750 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5751 | ASM_OPERANDs properly. | |
5752 | INSN doesn't really have to be a full INSN; it could be just the | |
5753 | pattern. */ | |
5754 | rtx | |
502b8322 | 5755 | copy_insn (rtx insn) |
da43a810 BS |
5756 | { |
5757 | copy_insn_n_scratches = 0; | |
5758 | orig_asm_operands_vector = 0; | |
5759 | orig_asm_constraints_vector = 0; | |
5760 | copy_asm_operands_vector = 0; | |
5761 | copy_asm_constraints_vector = 0; | |
5762 | return copy_insn_1 (insn); | |
5763 | } | |
59ec66dc | 5764 | |
8e383849 JR |
5765 | /* Return a copy of INSN that can be used in a SEQUENCE delay slot, |
5766 | on that assumption that INSN itself remains in its original place. */ | |
5767 | ||
f8f0516e DM |
5768 | rtx_insn * |
5769 | copy_delay_slot_insn (rtx_insn *insn) | |
8e383849 JR |
5770 | { |
5771 | /* Copy INSN with its rtx_code, all its notes, location etc. */ | |
f8f0516e | 5772 | insn = as_a <rtx_insn *> (copy_rtx (insn)); |
8e383849 JR |
5773 | INSN_UID (insn) = cur_insn_uid++; |
5774 | return insn; | |
5775 | } | |
5776 | ||
23b2ce53 RS |
5777 | /* Initialize data structures and variables in this file |
5778 | before generating rtl for each function. */ | |
5779 | ||
5780 | void | |
502b8322 | 5781 | init_emit (void) |
23b2ce53 | 5782 | { |
5936d944 JH |
5783 | set_first_insn (NULL); |
5784 | set_last_insn (NULL); | |
028d4092 ML |
5785 | if (param_min_nondebug_insn_uid) |
5786 | cur_insn_uid = param_min_nondebug_insn_uid; | |
b5b8b0ac AO |
5787 | else |
5788 | cur_insn_uid = 1; | |
5789 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5790 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
23b2ce53 | 5791 | first_label_num = label_num; |
614d5bd8 | 5792 | get_current_sequence ()->next = NULL; |
23b2ce53 | 5793 | |
23b2ce53 RS |
5794 | /* Init the tables that describe all the pseudo regs. */ |
5795 | ||
3e029763 | 5796 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5797 | |
3e029763 | 5798 | crtl->emit.regno_pointer_align |
1b4572a8 | 5799 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5800 | |
f44986d7 DM |
5801 | regno_reg_rtx |
5802 | = ggc_cleared_vec_alloc<rtx> (crtl->emit.regno_pointer_align_length); | |
0d4903b8 | 5803 | |
e50126e8 | 5804 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 | 5805 | memcpy (regno_reg_rtx, |
5fb0e246 | 5806 | initial_regno_reg_rtx, |
6cde4876 | 5807 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
e50126e8 | 5808 | |
23b2ce53 | 5809 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5810 | init_virtual_regs (); |
740ab4a2 RK |
5811 | |
5812 | /* Indicate that the virtual registers and stack locations are | |
5813 | all pointers. */ | |
3502dc9c JDA |
5814 | REG_POINTER (stack_pointer_rtx) = 1; |
5815 | REG_POINTER (frame_pointer_rtx) = 1; | |
5816 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5817 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5818 | |
3502dc9c JDA |
5819 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5820 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5821 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5822 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5823 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5824 | |
86fe05e0 | 5825 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5826 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5827 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5828 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5829 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5830 | ||
5831 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5832 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5833 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5834 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
da75ca93 | 5835 | |
bdb429a5 | 5836 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; |
86fe05e0 RK |
5837 | #endif |
5838 | ||
5e82e7bd JVA |
5839 | #ifdef INIT_EXPANDERS |
5840 | INIT_EXPANDERS; | |
5841 | #endif | |
23b2ce53 RS |
5842 | } |
5843 | ||
cd5ff7bc RS |
5844 | /* Return the value of element I of CONST_VECTOR X as a wide_int. */ |
5845 | ||
5846 | wide_int | |
5847 | const_vector_int_elt (const_rtx x, unsigned int i) | |
5848 | { | |
5849 | /* First handle elements that are directly encoded. */ | |
5850 | machine_mode elt_mode = GET_MODE_INNER (GET_MODE (x)); | |
5851 | if (i < (unsigned int) XVECLEN (x, 0)) | |
5852 | return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x, i), elt_mode); | |
5853 | ||
5854 | /* Identify the pattern that contains element I and work out the index of | |
5855 | the last encoded element for that pattern. */ | |
5856 | unsigned int encoded_nelts = const_vector_encoded_nelts (x); | |
5857 | unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); | |
5858 | unsigned int count = i / npatterns; | |
5859 | unsigned int pattern = i % npatterns; | |
5860 | unsigned int final_i = encoded_nelts - npatterns + pattern; | |
5861 | ||
5862 | /* If there are no steps, the final encoded value is the right one. */ | |
5863 | if (!CONST_VECTOR_STEPPED_P (x)) | |
5864 | return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x, final_i), elt_mode); | |
5865 | ||
5866 | /* Otherwise work out the value from the last two encoded elements. */ | |
5867 | rtx v1 = CONST_VECTOR_ENCODED_ELT (x, final_i - npatterns); | |
5868 | rtx v2 = CONST_VECTOR_ENCODED_ELT (x, final_i); | |
5869 | wide_int diff = wi::sub (rtx_mode_t (v2, elt_mode), | |
5870 | rtx_mode_t (v1, elt_mode)); | |
5871 | return wi::add (rtx_mode_t (v2, elt_mode), (count - 2) * diff); | |
5872 | } | |
5873 | ||
5874 | /* Return the value of element I of CONST_VECTOR X. */ | |
5875 | ||
5876 | rtx | |
5877 | const_vector_elt (const_rtx x, unsigned int i) | |
5878 | { | |
5879 | /* First handle elements that are directly encoded. */ | |
5880 | if (i < (unsigned int) XVECLEN (x, 0)) | |
5881 | return CONST_VECTOR_ENCODED_ELT (x, i); | |
5882 | ||
5883 | /* If there are no steps, the final encoded value is the right one. */ | |
5884 | if (!CONST_VECTOR_STEPPED_P (x)) | |
5885 | { | |
5886 | /* Identify the pattern that contains element I and work out the index of | |
5887 | the last encoded element for that pattern. */ | |
5888 | unsigned int encoded_nelts = const_vector_encoded_nelts (x); | |
5889 | unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); | |
5890 | unsigned int pattern = i % npatterns; | |
5891 | unsigned int final_i = encoded_nelts - npatterns + pattern; | |
5892 | return CONST_VECTOR_ENCODED_ELT (x, final_i); | |
5893 | } | |
5894 | ||
5895 | /* Otherwise work out the value from the last two encoded elements. */ | |
5896 | return immed_wide_int_const (const_vector_int_elt (x, i), | |
5897 | GET_MODE_INNER (GET_MODE (x))); | |
5898 | } | |
5899 | ||
c0cc00c4 JJ |
5900 | /* Return true if X is a valid element for a CONST_VECTOR of the given |
5901 | mode. */ | |
9b4473b6 RS |
5902 | |
5903 | bool | |
c0cc00c4 | 5904 | valid_for_const_vector_p (machine_mode, rtx x) |
9b4473b6 RS |
5905 | { |
5906 | return (CONST_SCALAR_INT_P (x) | |
1b5f74e8 | 5907 | || CONST_POLY_INT_P (x) |
9b4473b6 RS |
5908 | || CONST_DOUBLE_AS_FLOAT_P (x) |
5909 | || CONST_FIXED_P (x)); | |
5910 | } | |
5911 | ||
59d06c05 RS |
5912 | /* Generate a vector constant of mode MODE in which every element has |
5913 | value ELT. */ | |
69ef87e2 | 5914 | |
59d06c05 RS |
5915 | rtx |
5916 | gen_const_vec_duplicate (machine_mode mode, rtx elt) | |
5917 | { | |
3877c560 RS |
5918 | rtx_vector_builder builder (mode, 1, 1); |
5919 | builder.quick_push (elt); | |
5920 | return builder.build (); | |
59d06c05 RS |
5921 | } |
5922 | ||
5923 | /* Return a vector rtx of mode MODE in which every element has value X. | |
5924 | The result will be a constant if X is constant. */ | |
5925 | ||
5926 | rtx | |
5927 | gen_vec_duplicate (machine_mode mode, rtx x) | |
5928 | { | |
c0cc00c4 | 5929 | if (valid_for_const_vector_p (mode, x)) |
59d06c05 RS |
5930 | return gen_const_vec_duplicate (mode, x); |
5931 | return gen_rtx_VEC_DUPLICATE (mode, x); | |
5932 | } | |
15ed7b52 | 5933 | |
3877c560 RS |
5934 | /* A subroutine of const_vec_series_p that handles the case in which: |
5935 | ||
5936 | (GET_CODE (X) == CONST_VECTOR | |
5937 | && CONST_VECTOR_NPATTERNS (X) == 1 | |
5938 | && !CONST_VECTOR_DUPLICATE_P (X)) | |
5939 | ||
5940 | is known to hold. */ | |
ef339d6e RS |
5941 | |
5942 | bool | |
5943 | const_vec_series_p_1 (const_rtx x, rtx *base_out, rtx *step_out) | |
5944 | { | |
3877c560 RS |
5945 | /* Stepped sequences are only defined for integers, to avoid specifying |
5946 | rounding behavior. */ | |
5947 | if (GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT) | |
5948 | return false; | |
5949 | ||
5950 | /* A non-duplicated vector with two elements can always be seen as a | |
5951 | series with a nonzero step. Longer vectors must have a stepped | |
5952 | encoding. */ | |
7b777afa | 5953 | if (maybe_ne (CONST_VECTOR_NUNITS (x), 2) |
3877c560 | 5954 | && !CONST_VECTOR_STEPPED_P (x)) |
ef339d6e RS |
5955 | return false; |
5956 | ||
3877c560 | 5957 | /* Calculate the step between the first and second elements. */ |
ef339d6e RS |
5958 | scalar_mode inner = GET_MODE_INNER (GET_MODE (x)); |
5959 | rtx base = CONST_VECTOR_ELT (x, 0); | |
5960 | rtx step = simplify_binary_operation (MINUS, inner, | |
3877c560 | 5961 | CONST_VECTOR_ENCODED_ELT (x, 1), base); |
ef339d6e RS |
5962 | if (rtx_equal_p (step, CONST0_RTX (inner))) |
5963 | return false; | |
5964 | ||
3877c560 RS |
5965 | /* If we have a stepped encoding, check that the step between the |
5966 | second and third elements is the same as STEP. */ | |
5967 | if (CONST_VECTOR_STEPPED_P (x)) | |
ef339d6e RS |
5968 | { |
5969 | rtx diff = simplify_binary_operation (MINUS, inner, | |
3877c560 RS |
5970 | CONST_VECTOR_ENCODED_ELT (x, 2), |
5971 | CONST_VECTOR_ENCODED_ELT (x, 1)); | |
ef339d6e RS |
5972 | if (!rtx_equal_p (step, diff)) |
5973 | return false; | |
5974 | } | |
5975 | ||
5976 | *base_out = base; | |
5977 | *step_out = step; | |
5978 | return true; | |
5979 | } | |
5980 | ||
5981 | /* Generate a vector constant of mode MODE in which element I has | |
5982 | the value BASE + I * STEP. */ | |
5983 | ||
5984 | rtx | |
5985 | gen_const_vec_series (machine_mode mode, rtx base, rtx step) | |
5986 | { | |
af2e4475 RS |
5987 | gcc_assert (valid_for_const_vector_p (mode, base) |
5988 | && valid_for_const_vector_p (mode, step)); | |
ef339d6e | 5989 | |
3877c560 RS |
5990 | rtx_vector_builder builder (mode, 1, 3); |
5991 | builder.quick_push (base); | |
5992 | for (int i = 1; i < 3; ++i) | |
5993 | builder.quick_push (simplify_gen_binary (PLUS, GET_MODE_INNER (mode), | |
5994 | builder[i - 1], step)); | |
5995 | return builder.build (); | |
ef339d6e RS |
5996 | } |
5997 | ||
5998 | /* Generate a vector of mode MODE in which element I has the value | |
5999 | BASE + I * STEP. The result will be a constant if BASE and STEP | |
6000 | are both constants. */ | |
6001 | ||
6002 | rtx | |
6003 | gen_vec_series (machine_mode mode, rtx base, rtx step) | |
6004 | { | |
6005 | if (step == const0_rtx) | |
6006 | return gen_vec_duplicate (mode, base); | |
af2e4475 RS |
6007 | if (valid_for_const_vector_p (mode, base) |
6008 | && valid_for_const_vector_p (mode, step)) | |
ef339d6e RS |
6009 | return gen_const_vec_series (mode, base, step); |
6010 | return gen_rtx_VEC_SERIES (mode, base, step); | |
6011 | } | |
6012 | ||
59d06c05 RS |
6013 | /* Generate a new vector constant for mode MODE and constant value |
6014 | CONSTANT. */ | |
69ef87e2 | 6015 | |
59d06c05 RS |
6016 | static rtx |
6017 | gen_const_vector (machine_mode mode, int constant) | |
6018 | { | |
6019 | machine_mode inner = GET_MODE_INNER (mode); | |
69ef87e2 | 6020 | |
59d06c05 RS |
6021 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
6022 | ||
6023 | rtx el = const_tiny_rtx[constant][(int) inner]; | |
6024 | gcc_assert (el); | |
69ef87e2 | 6025 | |
3877c560 | 6026 | return gen_const_vec_duplicate (mode, el); |
69ef87e2 AH |
6027 | } |
6028 | ||
a06e3c40 | 6029 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 6030 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 6031 | rtx |
ef4bddc2 | 6032 | gen_rtx_CONST_VECTOR (machine_mode mode, rtvec v) |
a06e3c40 | 6033 | { |
7b777afa | 6034 | gcc_assert (known_eq (GET_MODE_NUNITS (mode), GET_NUM_ELEM (v))); |
a73b091d JW |
6035 | |
6036 | /* If the values are all the same, check to see if we can use one of the | |
6037 | standard constant vectors. */ | |
59d06c05 RS |
6038 | if (rtvec_all_equal_p (v)) |
6039 | return gen_const_vec_duplicate (mode, RTVEC_ELT (v, 0)); | |
a73b091d | 6040 | |
3877c560 RS |
6041 | unsigned int nunits = GET_NUM_ELEM (v); |
6042 | rtx_vector_builder builder (mode, nunits, 1); | |
6043 | for (unsigned int i = 0; i < nunits; ++i) | |
6044 | builder.quick_push (RTVEC_ELT (v, i)); | |
6045 | return builder.build (v); | |
a06e3c40 R |
6046 | } |
6047 | ||
b5deb7b6 SL |
6048 | /* Initialise global register information required by all functions. */ |
6049 | ||
6050 | void | |
6051 | init_emit_regs (void) | |
6052 | { | |
6053 | int i; | |
ef4bddc2 | 6054 | machine_mode mode; |
1c3f523e | 6055 | mem_attrs *attrs; |
b5deb7b6 SL |
6056 | |
6057 | /* Reset register attributes */ | |
aebf76a2 | 6058 | reg_attrs_htab->empty (); |
b5deb7b6 SL |
6059 | |
6060 | /* We need reg_raw_mode, so initialize the modes now. */ | |
6061 | init_reg_modes_target (); | |
6062 | ||
6063 | /* Assign register numbers to the globally defined register rtx. */ | |
b5deb7b6 SL |
6064 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
6065 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
6066 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
6067 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
6068 | virtual_incoming_args_rtx = | |
6069 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
6070 | virtual_stack_vars_rtx = | |
6071 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
6072 | virtual_stack_dynamic_rtx = | |
6073 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
6074 | virtual_outgoing_args_rtx = | |
6075 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
6076 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
32990d5b JJ |
6077 | virtual_preferred_stack_boundary_rtx = |
6078 | gen_raw_REG (Pmode, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM); | |
b5deb7b6 SL |
6079 | |
6080 | /* Initialize RTL for commonly used hard registers. These are | |
6081 | copied into regno_reg_rtx as we begin to compile each function. */ | |
6082 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5fb0e246 | 6083 | initial_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); |
b5deb7b6 SL |
6084 | |
6085 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
6086 | return_address_pointer_rtx | |
6087 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
6088 | #endif | |
6089 | ||
ca72dad5 | 6090 | pic_offset_table_rtx = NULL_RTX; |
b5deb7b6 SL |
6091 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
6092 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
1c3f523e RS |
6093 | |
6094 | for (i = 0; i < (int) MAX_MACHINE_MODE; i++) | |
6095 | { | |
ef4bddc2 | 6096 | mode = (machine_mode) i; |
766090c2 | 6097 | attrs = ggc_cleared_alloc<mem_attrs> (); |
1c3f523e RS |
6098 | attrs->align = BITS_PER_UNIT; |
6099 | attrs->addrspace = ADDR_SPACE_GENERIC; | |
532c7a45 | 6100 | if (mode != BLKmode && mode != VOIDmode) |
1c3f523e | 6101 | { |
754c3d5d RS |
6102 | attrs->size_known_p = true; |
6103 | attrs->size = GET_MODE_SIZE (mode); | |
1c3f523e RS |
6104 | if (STRICT_ALIGNMENT) |
6105 | attrs->align = GET_MODE_ALIGNMENT (mode); | |
6106 | } | |
6107 | mode_mem_attrs[i] = attrs; | |
6108 | } | |
af364399 ML |
6109 | |
6110 | split_branch_probability = profile_probability::uninitialized (); | |
b5deb7b6 SL |
6111 | } |
6112 | ||
aa3a12d6 RS |
6113 | /* Initialize global machine_mode variables. */ |
6114 | ||
6115 | void | |
6116 | init_derived_machine_modes (void) | |
6117 | { | |
501623d4 RS |
6118 | opt_scalar_int_mode mode_iter, opt_byte_mode, opt_word_mode; |
6119 | FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT) | |
aa3a12d6 | 6120 | { |
501623d4 RS |
6121 | scalar_int_mode mode = mode_iter.require (); |
6122 | ||
aa3a12d6 | 6123 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT |
501623d4 RS |
6124 | && !opt_byte_mode.exists ()) |
6125 | opt_byte_mode = mode; | |
aa3a12d6 RS |
6126 | |
6127 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
501623d4 RS |
6128 | && !opt_word_mode.exists ()) |
6129 | opt_word_mode = mode; | |
aa3a12d6 RS |
6130 | } |
6131 | ||
501623d4 RS |
6132 | byte_mode = opt_byte_mode.require (); |
6133 | word_mode = opt_word_mode.require (); | |
f95c5b8e RS |
6134 | ptr_mode = as_a <scalar_int_mode> |
6135 | (mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0).require ()); | |
aa3a12d6 RS |
6136 | } |
6137 | ||
2d888286 | 6138 | /* Create some permanent unique rtl objects shared between all functions. */ |
23b2ce53 RS |
6139 | |
6140 | void | |
2d888286 | 6141 | init_emit_once (void) |
23b2ce53 RS |
6142 | { |
6143 | int i; | |
ef4bddc2 | 6144 | machine_mode mode; |
857c7b46 | 6145 | scalar_float_mode double_mode; |
16d22000 | 6146 | opt_scalar_mode smode_iter; |
23b2ce53 | 6147 | |
807e902e KZ |
6148 | /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE, |
6149 | CONST_FIXED, and memory attribute hash tables. */ | |
aebf76a2 | 6150 | const_int_htab = hash_table<const_int_hasher>::create_ggc (37); |
173b24b9 | 6151 | |
807e902e | 6152 | #if TARGET_SUPPORTS_WIDE_INT |
aebf76a2 | 6153 | const_wide_int_htab = hash_table<const_wide_int_hasher>::create_ggc (37); |
807e902e | 6154 | #endif |
aebf76a2 | 6155 | const_double_htab = hash_table<const_double_hasher>::create_ggc (37); |
5692c7bc | 6156 | |
0c12fc9b RS |
6157 | if (NUM_POLY_INT_COEFFS > 1) |
6158 | const_poly_int_htab = hash_table<const_poly_int_hasher>::create_ggc (37); | |
6159 | ||
aebf76a2 | 6160 | const_fixed_htab = hash_table<const_fixed_hasher>::create_ggc (37); |
091a3ac7 | 6161 | |
aebf76a2 | 6162 | reg_attrs_htab = hash_table<reg_attr_hasher>::create_ggc (37); |
67673f5c | 6163 | |
5da077de | 6164 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
6165 | /* This is to initialize {init|mark|free}_machine_status before the first |
6166 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 6167 | end which calls push_function_context_to before the first call to |
5da077de AS |
6168 | init_function_start. */ |
6169 | INIT_EXPANDERS; | |
6170 | #endif | |
6171 | ||
23b2ce53 RS |
6172 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
6173 | ||
ecf835e9 KN |
6174 | /* Process stack-limiting command-line options. */ |
6175 | if (opt_fstack_limit_symbol_arg != NULL) | |
6176 | stack_limit_rtx | |
6177 | = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (opt_fstack_limit_symbol_arg)); | |
6178 | if (opt_fstack_limit_register_no >= 0) | |
6179 | stack_limit_rtx = gen_rtx_REG (Pmode, opt_fstack_limit_register_no); | |
6180 | ||
a2a8cc44 | 6181 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 6182 | tries to use these variables. */ |
23b2ce53 | 6183 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 6184 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 6185 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 6186 | |
68d75312 JC |
6187 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
6188 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 6189 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 6190 | else |
3b80f6ca | 6191 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 6192 | |
857c7b46 | 6193 | double_mode = float_mode_for_size (DOUBLE_TYPE_SIZE).require (); |
aa3a12d6 | 6194 | |
807e902e KZ |
6195 | real_from_integer (&dconst0, double_mode, 0, SIGNED); |
6196 | real_from_integer (&dconst1, double_mode, 1, SIGNED); | |
6197 | real_from_integer (&dconst2, double_mode, 2, SIGNED); | |
aefa9d43 KG |
6198 | |
6199 | dconstm1 = dconst1; | |
6200 | dconstm1.sign = 1; | |
03f2ea93 RS |
6201 | |
6202 | dconsthalf = dconst1; | |
1e92bbb9 | 6203 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 6204 | |
e7c82a99 | 6205 | for (i = 0; i < 3; i++) |
23b2ce53 | 6206 | { |
aefa9d43 | 6207 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
6208 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
6209 | ||
c94843d2 | 6210 | FOR_EACH_MODE_IN_CLASS (mode, MODE_FLOAT) |
15ed7b52 | 6211 | const_tiny_rtx[i][(int) mode] = |
555affd7 | 6212 | const_double_from_real_value (*r, mode); |
15ed7b52 | 6213 | |
c94843d2 | 6214 | FOR_EACH_MODE_IN_CLASS (mode, MODE_DECIMAL_FLOAT) |
5692c7bc | 6215 | const_tiny_rtx[i][(int) mode] = |
555affd7 | 6216 | const_double_from_real_value (*r, mode); |
23b2ce53 | 6217 | |
906c4e36 | 6218 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 6219 | |
c94843d2 | 6220 | FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
906c4e36 | 6221 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 | 6222 | |
ede6c734 MS |
6223 | for (mode = MIN_MODE_PARTIAL_INT; |
6224 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 6225 | mode = (machine_mode)((int)(mode) + 1)) |
33d3e559 | 6226 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
23b2ce53 RS |
6227 | } |
6228 | ||
e7c82a99 JJ |
6229 | const_tiny_rtx[3][(int) VOIDmode] = constm1_rtx; |
6230 | ||
c94843d2 | 6231 | FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
e7c82a99 JJ |
6232 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
6233 | ||
5c0caeb3 RS |
6234 | /* For BImode, 1 and -1 are unsigned and signed interpretations |
6235 | of the same value. */ | |
6236 | const_tiny_rtx[0][(int) BImode] = const0_rtx; | |
6237 | const_tiny_rtx[1][(int) BImode] = const_true_rtx; | |
6238 | const_tiny_rtx[3][(int) BImode] = const_true_rtx; | |
6239 | ||
ede6c734 MS |
6240 | for (mode = MIN_MODE_PARTIAL_INT; |
6241 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 6242 | mode = (machine_mode)((int)(mode) + 1)) |
c8a89d2a | 6243 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
c94843d2 RS |
6244 | |
6245 | FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_INT) | |
e90721b1 AP |
6246 | { |
6247 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
6248 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
6249 | } | |
6250 | ||
c94843d2 | 6251 | FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_FLOAT) |
e90721b1 AP |
6252 | { |
6253 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
6254 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
6255 | } | |
6256 | ||
5c0caeb3 RS |
6257 | /* As for BImode, "all 1" and "all -1" are unsigned and signed |
6258 | interpretations of the same value. */ | |
6259 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_BOOL) | |
6260 | { | |
6261 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6262 | const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3); | |
6263 | const_tiny_rtx[1][(int) mode] = const_tiny_rtx[3][(int) mode]; | |
6264 | } | |
6265 | ||
c94843d2 | 6266 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) |
a73b091d JW |
6267 | { |
6268 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6269 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
e7c82a99 | 6270 | const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3); |
a73b091d | 6271 | } |
69ef87e2 | 6272 | |
c94843d2 | 6273 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT) |
a73b091d JW |
6274 | { |
6275 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6276 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6277 | } | |
69ef87e2 | 6278 | |
16d22000 | 6279 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_FRACT) |
325217ed | 6280 | { |
16d22000 RS |
6281 | scalar_mode smode = smode_iter.require (); |
6282 | FCONST0 (smode).data.high = 0; | |
6283 | FCONST0 (smode).data.low = 0; | |
6284 | FCONST0 (smode).mode = smode; | |
6285 | const_tiny_rtx[0][(int) smode] | |
6286 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6287 | } |
6288 | ||
16d22000 | 6289 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UFRACT) |
325217ed | 6290 | { |
16d22000 RS |
6291 | scalar_mode smode = smode_iter.require (); |
6292 | FCONST0 (smode).data.high = 0; | |
6293 | FCONST0 (smode).data.low = 0; | |
6294 | FCONST0 (smode).mode = smode; | |
6295 | const_tiny_rtx[0][(int) smode] | |
6296 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6297 | } |
6298 | ||
16d22000 | 6299 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_ACCUM) |
325217ed | 6300 | { |
16d22000 RS |
6301 | scalar_mode smode = smode_iter.require (); |
6302 | FCONST0 (smode).data.high = 0; | |
6303 | FCONST0 (smode).data.low = 0; | |
6304 | FCONST0 (smode).mode = smode; | |
6305 | const_tiny_rtx[0][(int) smode] | |
6306 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6307 | |
6308 | /* We store the value 1. */ | |
16d22000 RS |
6309 | FCONST1 (smode).data.high = 0; |
6310 | FCONST1 (smode).data.low = 0; | |
6311 | FCONST1 (smode).mode = smode; | |
6312 | FCONST1 (smode).data | |
6313 | = double_int_one.lshift (GET_MODE_FBIT (smode), | |
9be0ac8c | 6314 | HOST_BITS_PER_DOUBLE_INT, |
16d22000 RS |
6315 | SIGNED_FIXED_POINT_MODE_P (smode)); |
6316 | const_tiny_rtx[1][(int) smode] | |
6317 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode); | |
325217ed CF |
6318 | } |
6319 | ||
16d22000 | 6320 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UACCUM) |
325217ed | 6321 | { |
16d22000 RS |
6322 | scalar_mode smode = smode_iter.require (); |
6323 | FCONST0 (smode).data.high = 0; | |
6324 | FCONST0 (smode).data.low = 0; | |
6325 | FCONST0 (smode).mode = smode; | |
6326 | const_tiny_rtx[0][(int) smode] | |
6327 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6328 | |
6329 | /* We store the value 1. */ | |
16d22000 RS |
6330 | FCONST1 (smode).data.high = 0; |
6331 | FCONST1 (smode).data.low = 0; | |
6332 | FCONST1 (smode).mode = smode; | |
6333 | FCONST1 (smode).data | |
6334 | = double_int_one.lshift (GET_MODE_FBIT (smode), | |
9be0ac8c | 6335 | HOST_BITS_PER_DOUBLE_INT, |
16d22000 RS |
6336 | SIGNED_FIXED_POINT_MODE_P (smode)); |
6337 | const_tiny_rtx[1][(int) smode] | |
6338 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode); | |
091a3ac7 CF |
6339 | } |
6340 | ||
c94843d2 | 6341 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FRACT) |
091a3ac7 CF |
6342 | { |
6343 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6344 | } | |
6345 | ||
c94843d2 | 6346 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UFRACT) |
091a3ac7 CF |
6347 | { |
6348 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6349 | } | |
6350 | ||
c94843d2 | 6351 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_ACCUM) |
091a3ac7 CF |
6352 | { |
6353 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6354 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6355 | } | |
6356 | ||
c94843d2 | 6357 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UACCUM) |
091a3ac7 CF |
6358 | { |
6359 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6360 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
6361 | } |
6362 | ||
dbbbbf3b | 6363 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
ef4bddc2 | 6364 | if (GET_MODE_CLASS ((machine_mode) i) == MODE_CC) |
dbbbbf3b | 6365 | const_tiny_rtx[0][i] = const0_rtx; |
23b2ce53 | 6366 | |
ca4adc91 RS |
6367 | pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); |
6368 | ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | |
6369 | simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); | |
1476d1bd MM |
6370 | invalid_insn_rtx = gen_rtx_INSN (VOIDmode, |
6371 | /*prev_insn=*/NULL, | |
6372 | /*next_insn=*/NULL, | |
6373 | /*bb=*/NULL, | |
6374 | /*pattern=*/NULL_RTX, | |
6375 | /*location=*/-1, | |
6376 | CODE_FOR_nothing, | |
6377 | /*reg_notes=*/NULL_RTX); | |
23b2ce53 | 6378 | } |
a11759a3 | 6379 | \f |
969d70ca JH |
6380 | /* Produce exact duplicate of insn INSN after AFTER. |
6381 | Care updating of libcall regions if present. */ | |
6382 | ||
cd459bf8 | 6383 | rtx_insn * |
a1950df3 | 6384 | emit_copy_of_insn_after (rtx_insn *insn, rtx_insn *after) |
969d70ca | 6385 | { |
cd459bf8 DM |
6386 | rtx_insn *new_rtx; |
6387 | rtx link; | |
969d70ca JH |
6388 | |
6389 | switch (GET_CODE (insn)) | |
6390 | { | |
6391 | case INSN: | |
60564289 | 6392 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
6393 | break; |
6394 | ||
6395 | case JUMP_INSN: | |
60564289 | 6396 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
ec27069c | 6397 | CROSSING_JUMP_P (new_rtx) = CROSSING_JUMP_P (insn); |
969d70ca JH |
6398 | break; |
6399 | ||
b5b8b0ac AO |
6400 | case DEBUG_INSN: |
6401 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
6402 | break; | |
6403 | ||
969d70ca | 6404 | case CALL_INSN: |
60564289 | 6405 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 6406 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 6407 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 6408 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
6409 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
6410 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
6411 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
b8698a0f | 6412 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) |
becfd6e5 | 6413 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
6414 | break; |
6415 | ||
6416 | default: | |
5b0264cb | 6417 | gcc_unreachable (); |
969d70ca JH |
6418 | } |
6419 | ||
6420 | /* Update LABEL_NUSES. */ | |
60564289 | 6421 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 6422 | |
5368224f | 6423 | INSN_LOCATION (new_rtx) = INSN_LOCATION (insn); |
ba4f7968 | 6424 | |
0a3d71f5 JW |
6425 | /* If the old insn is frame related, then so is the new one. This is |
6426 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
6427 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 6428 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 6429 | |
1581a12c BS |
6430 | /* Locate the end of existing REG_NOTES in NEW_RTX. */ |
6431 | rtx *ptail = ®_NOTES (new_rtx); | |
6432 | while (*ptail != NULL_RTX) | |
6433 | ptail = &XEXP (*ptail, 1); | |
6434 | ||
cf7c4aa6 HPN |
6435 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
6436 | will make them. REG_LABEL_TARGETs are created there too, but are | |
6437 | supposed to be sticky, so we copy them. */ | |
969d70ca | 6438 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 6439 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca | 6440 | { |
1581a12c BS |
6441 | *ptail = duplicate_reg_note (link); |
6442 | ptail = &XEXP (*ptail, 1); | |
969d70ca JH |
6443 | } |
6444 | ||
60564289 KG |
6445 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
6446 | return new_rtx; | |
969d70ca | 6447 | } |
e2500fed | 6448 | |
1431042e | 6449 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d | 6450 | rtx |
ef4bddc2 | 6451 | gen_hard_reg_clobber (machine_mode mode, unsigned int regno) |
3e89ed8d JH |
6452 | { |
6453 | if (hard_reg_clobbers[mode][regno]) | |
6454 | return hard_reg_clobbers[mode][regno]; | |
6455 | else | |
6456 | return (hard_reg_clobbers[mode][regno] = | |
6457 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
6458 | } | |
6459 | ||
5368224f DC |
6460 | location_t prologue_location; |
6461 | location_t epilogue_location; | |
78bde837 SB |
6462 | |
6463 | /* Hold current location information and last location information, so the | |
6464 | datastructures are built lazily only when some instructions in given | |
6465 | place are needed. */ | |
3a50da34 | 6466 | static location_t curr_location; |
78bde837 | 6467 | |
5368224f | 6468 | /* Allocate insn location datastructure. */ |
78bde837 | 6469 | void |
5368224f | 6470 | insn_locations_init (void) |
78bde837 | 6471 | { |
5368224f | 6472 | prologue_location = epilogue_location = 0; |
78bde837 | 6473 | curr_location = UNKNOWN_LOCATION; |
78bde837 SB |
6474 | } |
6475 | ||
6476 | /* At the end of emit stage, clear current location. */ | |
6477 | void | |
5368224f | 6478 | insn_locations_finalize (void) |
78bde837 | 6479 | { |
5368224f DC |
6480 | epilogue_location = curr_location; |
6481 | curr_location = UNKNOWN_LOCATION; | |
78bde837 SB |
6482 | } |
6483 | ||
6484 | /* Set current location. */ | |
6485 | void | |
5368224f | 6486 | set_curr_insn_location (location_t location) |
78bde837 | 6487 | { |
78bde837 SB |
6488 | curr_location = location; |
6489 | } | |
6490 | ||
6491 | /* Get current location. */ | |
6492 | location_t | |
5368224f | 6493 | curr_insn_location (void) |
78bde837 SB |
6494 | { |
6495 | return curr_location; | |
6496 | } | |
6497 | ||
079e0f61 EB |
6498 | /* Set the location of the insn chain starting at INSN to LOC. */ |
6499 | void | |
6500 | set_insn_locations (rtx_insn *insn, location_t loc) | |
6501 | { | |
6502 | while (insn) | |
6503 | { | |
6504 | if (INSN_P (insn)) | |
6505 | INSN_LOCATION (insn) = loc; | |
6506 | insn = NEXT_INSN (insn); | |
6507 | } | |
6508 | } | |
6509 | ||
78bde837 SB |
6510 | /* Return lexical scope block insn belongs to. */ |
6511 | tree | |
a1950df3 | 6512 | insn_scope (const rtx_insn *insn) |
78bde837 | 6513 | { |
5368224f | 6514 | return LOCATION_BLOCK (INSN_LOCATION (insn)); |
78bde837 SB |
6515 | } |
6516 | ||
6517 | /* Return line number of the statement that produced this insn. */ | |
6518 | int | |
a1950df3 | 6519 | insn_line (const rtx_insn *insn) |
78bde837 | 6520 | { |
5368224f | 6521 | return LOCATION_LINE (INSN_LOCATION (insn)); |
78bde837 SB |
6522 | } |
6523 | ||
6524 | /* Return source file of the statement that produced this insn. */ | |
6525 | const char * | |
a1950df3 | 6526 | insn_file (const rtx_insn *insn) |
78bde837 | 6527 | { |
5368224f | 6528 | return LOCATION_FILE (INSN_LOCATION (insn)); |
78bde837 | 6529 | } |
8930883e | 6530 | |
ffa4602f EB |
6531 | /* Return expanded location of the statement that produced this insn. */ |
6532 | expanded_location | |
a1950df3 | 6533 | insn_location (const rtx_insn *insn) |
ffa4602f EB |
6534 | { |
6535 | return expand_location (INSN_LOCATION (insn)); | |
6536 | } | |
6537 | ||
8930883e MK |
6538 | /* Return true if memory model MODEL requires a pre-operation (release-style) |
6539 | barrier or a post-operation (acquire-style) barrier. While not universal, | |
6540 | this function matches behavior of several targets. */ | |
6541 | ||
6542 | bool | |
6543 | need_atomic_barrier_p (enum memmodel model, bool pre) | |
6544 | { | |
40ad260d | 6545 | switch (model & MEMMODEL_BASE_MASK) |
8930883e MK |
6546 | { |
6547 | case MEMMODEL_RELAXED: | |
6548 | case MEMMODEL_CONSUME: | |
6549 | return false; | |
6550 | case MEMMODEL_RELEASE: | |
6551 | return pre; | |
6552 | case MEMMODEL_ACQUIRE: | |
6553 | return !pre; | |
6554 | case MEMMODEL_ACQ_REL: | |
6555 | case MEMMODEL_SEQ_CST: | |
6556 | return true; | |
6557 | default: | |
6558 | gcc_unreachable (); | |
6559 | } | |
6560 | } | |
8194c537 | 6561 | |
abd3c800 RS |
6562 | /* Return a constant shift amount for shifting a value of mode MODE |
6563 | by VALUE bits. */ | |
6564 | ||
6565 | rtx | |
0c12fc9b | 6566 | gen_int_shift_amount (machine_mode, poly_int64 value) |
abd3c800 RS |
6567 | { |
6568 | /* Use a 64-bit mode, to avoid any truncation. | |
6569 | ||
6570 | ??? Perhaps this should be automatically derived from the .md files | |
6571 | instead, or perhaps have a target hook. */ | |
6572 | scalar_int_mode shift_mode = (BITS_PER_UNIT == 8 | |
6573 | ? DImode | |
6574 | : int_mode_for_size (64, 0).require ()); | |
6575 | return gen_int_mode (value, shift_mode); | |
6576 | } | |
6577 | ||
8194c537 DM |
6578 | /* Initialize fields of rtl_data related to stack alignment. */ |
6579 | ||
6580 | void | |
6581 | rtl_data::init_stack_alignment () | |
6582 | { | |
6583 | stack_alignment_needed = STACK_BOUNDARY; | |
6584 | max_used_stack_slot_alignment = STACK_BOUNDARY; | |
6585 | stack_alignment_estimated = 0; | |
6586 | preferred_stack_boundary = STACK_BOUNDARY; | |
6587 | } | |
6588 | ||
8930883e | 6589 | \f |
e2500fed | 6590 | #include "gt-emit-rtl.h" |