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15bbde2b | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ddca3e9d | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
5377f687 | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
15bbde2b | 4 | |
f12b58b3 | 5 | This file is part of GCC. |
15bbde2b | 6 | |
f12b58b3 | 7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
15bbde2b | 11 | |
f12b58b3 | 12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
15bbde2b | 16 | |
17 | You should have received a copy of the GNU General Public License | |
f12b58b3 | 18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
15bbde2b | 21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
405711de | 39 | #include "system.h" |
d3b64f2d | 40 | #include "toplev.h" |
15bbde2b | 41 | #include "rtl.h" |
3fd7e17f | 42 | #include "tree.h" |
7953c610 | 43 | #include "tm_p.h" |
15bbde2b | 44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
c6b6c51f | 48 | #include "hard-reg-set.h" |
73f5c1e3 | 49 | #include "hashtab.h" |
15bbde2b | 50 | #include "insn-config.h" |
0dbd1c74 | 51 | #include "recog.h" |
15bbde2b | 52 | #include "real.h" |
649d8da6 | 53 | #include "obstack.h" |
a3426c4c | 54 | #include "bitmap.h" |
f3d96a58 | 55 | #include "basic-block.h" |
a7b0c170 | 56 | #include "ggc.h" |
b29760a8 | 57 | #include "debug.h" |
649d8da6 | 58 | |
399d45d3 | 59 | /* Commonly used modes. */ |
60 | ||
a92771b8 | 61 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
62 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9e042f31 | 63 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
a92771b8 | 64 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
399d45d3 | 65 | |
15bbde2b | 66 | |
67 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
68 | in the entire compilation a unique label number. */ | |
69 | ||
70 | static int label_num = 1; | |
71 | ||
15bbde2b | 72 | /* Highest label number in current function. |
73 | Zero means use the value of label_num instead. | |
74 | This is nonzero only when belatedly compiling an inline function. */ | |
75 | ||
76 | static int last_label_num; | |
77 | ||
78 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
79 | If label_num has not changed since then, last_label_num is valid. */ | |
80 | ||
81 | static int base_label_num; | |
82 | ||
83 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
84 | ||
85 | static int no_line_numbers; | |
86 | ||
87 | /* Commonly used rtx's, so that we only need space for one copy. | |
88 | These are initialized once for the entire compilation. | |
89 | All of these except perhaps the floating-point CONST_DOUBLEs | |
90 | are unique; no other rtx-object will be equal to any of these. */ | |
91 | ||
57c097d5 | 92 | rtx global_rtl[GR_MAX]; |
15bbde2b | 93 | |
94 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
95 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
96 | record a copy of const[012]_rtx. */ | |
97 | ||
98 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
99 | ||
1a60f06a | 100 | rtx const_true_rtx; |
101 | ||
15bbde2b | 102 | REAL_VALUE_TYPE dconst0; |
103 | REAL_VALUE_TYPE dconst1; | |
104 | REAL_VALUE_TYPE dconst2; | |
105 | REAL_VALUE_TYPE dconstm1; | |
106 | ||
107 | /* All references to the following fixed hard registers go through | |
108 | these unique rtl objects. On machines where the frame-pointer and | |
109 | arg-pointer are the same register, they use the same unique object. | |
110 | ||
111 | After register allocation, other rtl objects which used to be pseudo-regs | |
112 | may be clobbered to refer to the frame-pointer register. | |
113 | But references that were originally to the frame-pointer can be | |
114 | distinguished from the others because they contain frame_pointer_rtx. | |
115 | ||
90c25824 | 116 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
117 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
d823ba47 | 118 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
90c25824 | 119 | register elimination hard_frame_pointer_rtx should always be used. |
120 | On machines where the two registers are same (most) then these are the | |
121 | same. | |
122 | ||
15bbde2b | 123 | In an inline procedure, the stack and frame pointer rtxs may not be |
124 | used for anything else. */ | |
15bbde2b | 125 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
126 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
127 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
128 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
129 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
130 | ||
4b0c5859 | 131 | /* This is used to implement __builtin_return_address for some machines. |
132 | See for instance the MIPS port. */ | |
133 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
134 | ||
15bbde2b | 135 | /* We make one copy of (const_int C) where C is in |
136 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
137 | to save space during the compilation and simplify comparisons of | |
138 | integers. */ | |
139 | ||
57c097d5 | 140 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
15bbde2b | 141 | |
73f5c1e3 | 142 | /* A hash table storing CONST_INTs whose absolute value is greater |
143 | than MAX_SAVED_CONST_INT. */ | |
144 | ||
145 | static htab_t const_int_htab; | |
146 | ||
15bbde2b | 147 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
148 | shortly thrown away. We use two mechanisms to prevent this waste: | |
149 | ||
1bfd55c5 | 150 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
151 | rtvec for use by gen_sequence. One entry for each size is | |
152 | sufficient because most cases are calls to gen_sequence followed by | |
153 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
154 | sequence is destructive on the insn in it anyway and hence can't be | |
155 | redone. | |
15bbde2b | 156 | |
157 | We do not bother to save this cached data over nested function calls. | |
158 | Instead, we just reinitialize them. */ | |
159 | ||
160 | #define SEQUENCE_RESULT_SIZE 5 | |
161 | ||
15bbde2b | 162 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
163 | ||
a92771b8 | 164 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
575333f9 | 165 | static rtx free_insn; |
166 | ||
08513b52 | 167 | #define first_insn (cfun->emit->x_first_insn) |
168 | #define last_insn (cfun->emit->x_last_insn) | |
169 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
170 | #define last_linenum (cfun->emit->x_last_linenum) | |
171 | #define last_filename (cfun->emit->x_last_filename) | |
172 | #define first_label_num (cfun->emit->x_first_label_num) | |
15bbde2b | 173 | |
621f6678 | 174 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
175 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
176 | static rtx find_line_note PARAMS ((rtx)); | |
177 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
2d96a59a | 178 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
72ec8878 | 179 | static void unshare_all_decls PARAMS ((tree)); |
01dc9f0c | 180 | static void reset_used_decls PARAMS ((tree)); |
344dc2fa | 181 | static void mark_label_nuses PARAMS ((rtx)); |
73f5c1e3 | 182 | static hashval_t const_int_htab_hash PARAMS ((const void *)); |
183 | static int const_int_htab_eq PARAMS ((const void *, | |
184 | const void *)); | |
185 | static int rtx_htab_mark_1 PARAMS ((void **, void *)); | |
186 | static void rtx_htab_mark PARAMS ((void *)); | |
187 | ||
3cd757b1 | 188 | /* Probability of the conditional branch currently proceeded by try_split. |
189 | Set to -1 otherwise. */ | |
190 | int split_branch_probability = -1; | |
191 | ||
649d8da6 | 192 | \f |
73f5c1e3 | 193 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
194 | ||
195 | static hashval_t | |
196 | const_int_htab_hash (x) | |
197 | const void *x; | |
198 | { | |
5e431971 | 199 | return (hashval_t) INTVAL ((const struct rtx_def *) x); |
73f5c1e3 | 200 | } |
201 | ||
202 | /* Returns non-zero if the value represented by X (which is really a | |
203 | CONST_INT) is the same as that given by Y (which is really a | |
204 | HOST_WIDE_INT *). */ | |
205 | ||
206 | static int | |
207 | const_int_htab_eq (x, y) | |
208 | const void *x; | |
209 | const void *y; | |
210 | { | |
5e431971 | 211 | return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y)); |
73f5c1e3 | 212 | } |
213 | ||
214 | /* Mark the hash-table element X (which is really a pointer to an | |
215 | rtx). */ | |
216 | ||
217 | static int | |
218 | rtx_htab_mark_1 (x, data) | |
219 | void **x; | |
220 | void *data ATTRIBUTE_UNUSED; | |
221 | { | |
222 | ggc_mark_rtx (*x); | |
223 | return 1; | |
224 | } | |
225 | ||
226 | /* Mark all the elements of HTAB (which is really an htab_t full of | |
227 | rtxs). */ | |
228 | ||
229 | static void | |
230 | rtx_htab_mark (htab) | |
231 | void *htab; | |
232 | { | |
233 | htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL); | |
234 | } | |
235 | ||
22cf44bc | 236 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
237 | don't attempt to share with the various global pieces of rtl (such as | |
238 | frame_pointer_rtx). */ | |
239 | ||
240 | rtx | |
241 | gen_raw_REG (mode, regno) | |
242 | enum machine_mode mode; | |
243 | int regno; | |
244 | { | |
245 | rtx x = gen_rtx_raw_REG (mode, regno); | |
246 | ORIGINAL_REGNO (x) = regno; | |
247 | return x; | |
248 | } | |
249 | ||
7014838c | 250 | /* There are some RTL codes that require special attention; the generation |
251 | functions do the raw handling. If you add to this list, modify | |
252 | special_rtx in gengenrtl.c as well. */ | |
253 | ||
3ad7bb1c | 254 | rtx |
255 | gen_rtx_CONST_INT (mode, arg) | |
73f5c1e3 | 256 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3ad7bb1c | 257 | HOST_WIDE_INT arg; |
258 | { | |
73f5c1e3 | 259 | void **slot; |
260 | ||
3ad7bb1c | 261 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
57c097d5 | 262 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3ad7bb1c | 263 | |
264 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
265 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
266 | return const_true_rtx; | |
267 | #endif | |
268 | ||
73f5c1e3 | 269 | /* Look up the CONST_INT in the hash table. */ |
2b3dbc20 | 270 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
271 | (hashval_t) arg, INSERT); | |
7f2875d3 | 272 | if (*slot == 0) |
d7c47c0e | 273 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
73f5c1e3 | 274 | |
275 | return (rtx) *slot; | |
3ad7bb1c | 276 | } |
277 | ||
7f2875d3 | 278 | /* CONST_DOUBLEs needs special handling because their length is known |
67f2a2eb | 279 | only at run-time. */ |
7f2875d3 | 280 | |
67f2a2eb | 281 | rtx |
282 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
283 | enum machine_mode mode; | |
284 | rtx arg0; | |
285 | HOST_WIDE_INT arg1, arg2; | |
286 | { | |
287 | rtx r = rtx_alloc (CONST_DOUBLE); | |
4e929432 | 288 | int i; |
289 | ||
67f2a2eb | 290 | PUT_MODE (r, mode); |
291 | XEXP (r, 0) = arg0; | |
25999090 | 292 | X0EXP (r, 1) = NULL_RTX; |
4e929432 | 293 | XWINT (r, 2) = arg1; |
294 | XWINT (r, 3) = arg2; | |
295 | ||
296 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
297 | XWINT (r, i) = 0; | |
298 | ||
67f2a2eb | 299 | return r; |
300 | } | |
301 | ||
3ad7bb1c | 302 | rtx |
303 | gen_rtx_REG (mode, regno) | |
304 | enum machine_mode mode; | |
305 | int regno; | |
306 | { | |
307 | /* In case the MD file explicitly references the frame pointer, have | |
308 | all such references point to the same frame pointer. This is | |
309 | used during frame pointer elimination to distinguish the explicit | |
310 | references to these registers from pseudos that happened to be | |
311 | assigned to them. | |
312 | ||
313 | If we have eliminated the frame pointer or arg pointer, we will | |
314 | be using it as a normal register, for example as a spill | |
315 | register. In such cases, we might be accessing it in a mode that | |
316 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
317 | ||
318 | Also don't do this when we are making new REGs in reload, since | |
319 | we don't want to get confused with the real pointers. */ | |
320 | ||
321 | if (mode == Pmode && !reload_in_progress) | |
322 | { | |
e8b59353 | 323 | if (regno == FRAME_POINTER_REGNUM) |
3ad7bb1c | 324 | return frame_pointer_rtx; |
325 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e8b59353 | 326 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3ad7bb1c | 327 | return hard_frame_pointer_rtx; |
328 | #endif | |
329 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
e8b59353 | 330 | if (regno == ARG_POINTER_REGNUM) |
3ad7bb1c | 331 | return arg_pointer_rtx; |
332 | #endif | |
333 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
e8b59353 | 334 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3ad7bb1c | 335 | return return_address_pointer_rtx; |
336 | #endif | |
e8b59353 | 337 | if (regno == STACK_POINTER_REGNUM) |
3ad7bb1c | 338 | return stack_pointer_rtx; |
339 | } | |
340 | ||
22cf44bc | 341 | return gen_raw_REG (mode, regno); |
3ad7bb1c | 342 | } |
343 | ||
b5ba9f3a | 344 | rtx |
345 | gen_rtx_MEM (mode, addr) | |
346 | enum machine_mode mode; | |
347 | rtx addr; | |
348 | { | |
349 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
350 | ||
351 | /* This field is not cleared by the mere allocation of the rtx, so | |
352 | we clear it here. */ | |
353 | MEM_ALIAS_SET (rt) = 0; | |
354 | ||
355 | return rt; | |
356 | } | |
701e46d0 | 357 | |
358 | rtx | |
359 | gen_rtx_SUBREG (mode, reg, offset) | |
360 | enum machine_mode mode; | |
361 | rtx reg; | |
362 | int offset; | |
363 | { | |
364 | /* This is the most common failure type. | |
365 | Catch it early so we can see who does it. */ | |
366 | if ((offset % GET_MODE_SIZE (mode)) != 0) | |
367 | abort (); | |
368 | ||
369 | /* This check isn't usable right now because combine will | |
370 | throw arbitrary crap like a CALL into a SUBREG in | |
371 | gen_lowpart_for_combine so we must just eat it. */ | |
372 | #if 0 | |
373 | /* Check for this too. */ | |
374 | if (offset >= GET_MODE_SIZE (GET_MODE (reg))) | |
375 | abort (); | |
376 | #endif | |
377 | return gen_rtx_fmt_ei (SUBREG, mode, reg, offset); | |
378 | } | |
379 | ||
380 | /* Generate a SUBREG representing the least-significant part | |
381 | * of REG if MODE is smaller than mode of REG, otherwise | |
6312a35e | 382 | * paradoxical SUBREG. */ |
701e46d0 | 383 | rtx |
384 | gen_lowpart_SUBREG (mode, reg) | |
385 | enum machine_mode mode; | |
386 | rtx reg; | |
387 | { | |
388 | enum machine_mode inmode; | |
701e46d0 | 389 | |
390 | inmode = GET_MODE (reg); | |
391 | if (inmode == VOIDmode) | |
392 | inmode = mode; | |
81802af6 | 393 | return gen_rtx_SUBREG (mode, reg, |
394 | subreg_lowpart_offset (mode, inmode)); | |
701e46d0 | 395 | } |
7014838c | 396 | \f |
15bbde2b | 397 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
398 | ** | |
399 | ** This routine generates an RTX of the size specified by | |
400 | ** <code>, which is an RTX code. The RTX structure is initialized | |
401 | ** from the arguments <element1> through <elementn>, which are | |
402 | ** interpreted according to the specific RTX type's format. The | |
403 | ** special machine mode associated with the rtx (if any) is specified | |
404 | ** in <mode>. | |
405 | ** | |
fc92fa61 | 406 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
15bbde2b | 407 | ** rtx it will generate. For example, the following rtx structure: |
408 | ** | |
409 | ** (plus:QI (mem:QI (reg:SI 1)) | |
410 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
411 | ** | |
412 | ** ...would be generated by the following C code: | |
413 | ** | |
d823ba47 | 414 | ** gen_rtx (PLUS, QImode, |
15bbde2b | 415 | ** gen_rtx (MEM, QImode, |
416 | ** gen_rtx (REG, SImode, 1)), | |
417 | ** gen_rtx (MEM, QImode, | |
418 | ** gen_rtx (PLUS, SImode, | |
419 | ** gen_rtx (REG, SImode, 2), | |
420 | ** gen_rtx (REG, SImode, 3)))), | |
421 | */ | |
422 | ||
423 | /*VARARGS2*/ | |
424 | rtx | |
621f6678 | 425 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
15bbde2b | 426 | { |
15bbde2b | 427 | register int i; /* Array indices... */ |
d2ca078f | 428 | register const char *fmt; /* Current rtx's format... */ |
15bbde2b | 429 | register rtx rt_val; /* RTX to return to caller... */ |
430 | ||
0903457a | 431 | VA_OPEN (p, mode); |
432 | VA_FIXEDARG (p, enum rtx_code, code); | |
433 | VA_FIXEDARG (p, enum machine_mode, mode); | |
15bbde2b | 434 | |
67f2a2eb | 435 | switch (code) |
15bbde2b | 436 | { |
67f2a2eb | 437 | case CONST_INT: |
438 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
439 | break; | |
440 | ||
441 | case CONST_DOUBLE: | |
442 | { | |
443 | rtx arg0 = va_arg (p, rtx); | |
444 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
445 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
446 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
447 | } | |
448 | break; | |
449 | ||
450 | case REG: | |
451 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
452 | break; | |
453 | ||
454 | case MEM: | |
455 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
456 | break; | |
457 | ||
458 | default: | |
15bbde2b | 459 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
460 | rt_val->mode = mode; /* Store the machine mode... */ | |
461 | ||
462 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
463 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
464 | { | |
465 | switch (*fmt++) | |
466 | { | |
467 | case '0': /* Unused field. */ | |
468 | break; | |
469 | ||
470 | case 'i': /* An integer? */ | |
471 | XINT (rt_val, i) = va_arg (p, int); | |
472 | break; | |
473 | ||
b572011e | 474 | case 'w': /* A wide integer? */ |
475 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
476 | break; | |
477 | ||
15bbde2b | 478 | case 's': /* A string? */ |
479 | XSTR (rt_val, i) = va_arg (p, char *); | |
480 | break; | |
481 | ||
482 | case 'e': /* An expression? */ | |
483 | case 'u': /* An insn? Same except when printing. */ | |
484 | XEXP (rt_val, i) = va_arg (p, rtx); | |
485 | break; | |
486 | ||
487 | case 'E': /* An RTX vector? */ | |
488 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
489 | break; | |
490 | ||
a3426c4c | 491 | case 'b': /* A bitmap? */ |
492 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
493 | break; | |
494 | ||
495 | case 't': /* A tree? */ | |
496 | XTREE (rt_val, i) = va_arg (p, tree); | |
497 | break; | |
498 | ||
15bbde2b | 499 | default: |
fc92fa61 | 500 | abort (); |
15bbde2b | 501 | } |
502 | } | |
67f2a2eb | 503 | break; |
15bbde2b | 504 | } |
67f2a2eb | 505 | |
0903457a | 506 | VA_CLOSE (p); |
67f2a2eb | 507 | return rt_val; |
15bbde2b | 508 | } |
509 | ||
510 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
511 | ** | |
512 | ** This routine creates an rtvec and stores within it the | |
513 | ** pointers to rtx's which are its arguments. | |
514 | */ | |
515 | ||
516 | /*VARARGS1*/ | |
517 | rtvec | |
621f6678 | 518 | gen_rtvec VPARAMS ((int n, ...)) |
15bbde2b | 519 | { |
7ad77798 | 520 | int i, save_n; |
15bbde2b | 521 | rtx *vector; |
522 | ||
0903457a | 523 | VA_OPEN (p, n); |
524 | VA_FIXEDARG (p, int, n); | |
15bbde2b | 525 | |
526 | if (n == 0) | |
527 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
528 | ||
529 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
e5fcd76a | 530 | |
15bbde2b | 531 | for (i = 0; i < n; i++) |
532 | vector[i] = va_arg (p, rtx); | |
7ad77798 | 533 | |
534 | /* The definition of VA_* in K&R C causes `n' to go out of scope. */ | |
535 | save_n = n; | |
0903457a | 536 | VA_CLOSE (p); |
15bbde2b | 537 | |
7ad77798 | 538 | return gen_rtvec_v (save_n, vector); |
15bbde2b | 539 | } |
540 | ||
541 | rtvec | |
542 | gen_rtvec_v (n, argp) | |
543 | int n; | |
544 | rtx *argp; | |
545 | { | |
546 | register int i; | |
547 | register rtvec rt_val; | |
548 | ||
549 | if (n == 0) | |
550 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
551 | ||
552 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
553 | ||
554 | for (i = 0; i < n; i++) | |
a4070a91 | 555 | rt_val->elem[i] = *argp++; |
15bbde2b | 556 | |
557 | return rt_val; | |
558 | } | |
fbaa9422 | 559 | |
15bbde2b | 560 | \f |
561 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
562 | This pseudo is assigned the next sequential register number. */ | |
563 | ||
564 | rtx | |
565 | gen_reg_rtx (mode) | |
566 | enum machine_mode mode; | |
567 | { | |
08513b52 | 568 | struct function *f = cfun; |
15bbde2b | 569 | register rtx val; |
570 | ||
9e519b97 | 571 | /* Don't let anything called after initial flow analysis create new |
572 | registers. */ | |
573 | if (no_new_pseudos) | |
15bbde2b | 574 | abort (); |
575 | ||
316bc009 | 576 | if (generating_concat_p |
577 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
578 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
76c37538 | 579 | { |
580 | /* For complex modes, don't make a single pseudo. | |
581 | Instead, make a CONCAT of two pseudos. | |
582 | This allows noncontiguous allocation of the real and imaginary parts, | |
583 | which makes much better code. Besides, allocating DCmode | |
584 | pseudos overstrains reload on some machines like the 386. */ | |
585 | rtx realpart, imagpart; | |
586 | int size = GET_MODE_UNIT_SIZE (mode); | |
587 | enum machine_mode partmode | |
588 | = mode_for_size (size * BITS_PER_UNIT, | |
589 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
590 | ? MODE_FLOAT : MODE_INT), | |
591 | 0); | |
592 | ||
593 | realpart = gen_reg_rtx (partmode); | |
594 | imagpart = gen_reg_rtx (partmode); | |
3ad7bb1c | 595 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
76c37538 | 596 | } |
597 | ||
e61a0a7f | 598 | /* Make sure regno_pointer_align and regno_reg_rtx are large enough |
599 | to have an element for this pseudo reg number. */ | |
15bbde2b | 600 | |
e61a0a7f | 601 | if (reg_rtx_no == f->emit->regno_pointer_align_length) |
15bbde2b | 602 | { |
e61a0a7f | 603 | int old_size = f->emit->regno_pointer_align_length; |
15bbde2b | 604 | rtx *new1; |
26df1c5e | 605 | char *new; |
26df1c5e | 606 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
0a893c29 | 607 | memset (new + old_size, 0, old_size); |
4491f79f | 608 | f->emit->regno_pointer_align = (unsigned char *) new; |
0a893c29 | 609 | |
26df1c5e | 610 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
611 | old_size * 2 * sizeof (rtx)); | |
0a893c29 | 612 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
15bbde2b | 613 | regno_reg_rtx = new1; |
614 | ||
e61a0a7f | 615 | f->emit->regno_pointer_align_length = old_size * 2; |
15bbde2b | 616 | } |
617 | ||
22cf44bc | 618 | val = gen_raw_REG (mode, reg_rtx_no); |
15bbde2b | 619 | regno_reg_rtx[reg_rtx_no++] = val; |
620 | return val; | |
621 | } | |
622 | ||
de8ecfb5 | 623 | /* Identify REG (which may be a CONCAT) as a user register. */ |
624 | ||
625 | void | |
626 | mark_user_reg (reg) | |
627 | rtx reg; | |
628 | { | |
629 | if (GET_CODE (reg) == CONCAT) | |
630 | { | |
631 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
632 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
633 | } | |
634 | else if (GET_CODE (reg) == REG) | |
635 | REG_USERVAR_P (reg) = 1; | |
636 | else | |
637 | abort (); | |
638 | } | |
639 | ||
d4c332ff | 640 | /* Identify REG as a probable pointer register and show its alignment |
641 | as ALIGN, if nonzero. */ | |
15bbde2b | 642 | |
643 | void | |
d4c332ff | 644 | mark_reg_pointer (reg, align) |
15bbde2b | 645 | rtx reg; |
d4c332ff | 646 | int align; |
15bbde2b | 647 | { |
e61a0a7f | 648 | if (! REG_POINTER (reg)) |
612409a6 | 649 | { |
e61a0a7f | 650 | REG_POINTER (reg) = 1; |
d4c332ff | 651 | |
612409a6 | 652 | if (align) |
653 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
654 | } | |
655 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
656 | /* We can no-longer be sure just how aligned this pointer is */ | |
d4c332ff | 657 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
15bbde2b | 658 | } |
659 | ||
660 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
661 | ||
662 | int | |
663 | max_reg_num () | |
664 | { | |
665 | return reg_rtx_no; | |
666 | } | |
667 | ||
668 | /* Return 1 + the largest label number used so far in the current function. */ | |
669 | ||
670 | int | |
671 | max_label_num () | |
672 | { | |
673 | if (last_label_num && label_num == base_label_num) | |
674 | return last_label_num; | |
675 | return label_num; | |
676 | } | |
677 | ||
678 | /* Return first label number used in this function (if any were used). */ | |
679 | ||
680 | int | |
681 | get_first_label_num () | |
682 | { | |
683 | return first_label_num; | |
684 | } | |
685 | \f | |
701e46d0 | 686 | /* Return the final regno of X, which is a SUBREG of a hard |
687 | register. */ | |
688 | int | |
689 | subreg_hard_regno (x, check_mode) | |
690 | register rtx x; | |
691 | int check_mode; | |
692 | { | |
693 | enum machine_mode mode = GET_MODE (x); | |
694 | unsigned int byte_offset, base_regno, final_regno; | |
695 | rtx reg = SUBREG_REG (x); | |
696 | ||
697 | /* This is where we attempt to catch illegal subregs | |
698 | created by the compiler. */ | |
699 | if (GET_CODE (x) != SUBREG | |
700 | || GET_CODE (reg) != REG) | |
701 | abort (); | |
702 | base_regno = REGNO (reg); | |
703 | if (base_regno >= FIRST_PSEUDO_REGISTER) | |
704 | abort (); | |
475fa9bd | 705 | if (check_mode && ! HARD_REGNO_MODE_OK (base_regno, GET_MODE (reg))) |
701e46d0 | 706 | abort (); |
707 | ||
708 | /* Catch non-congruent offsets too. */ | |
709 | byte_offset = SUBREG_BYTE (x); | |
710 | if ((byte_offset % GET_MODE_SIZE (mode)) != 0) | |
711 | abort (); | |
712 | ||
713 | final_regno = subreg_regno (x); | |
714 | ||
715 | return final_regno; | |
716 | } | |
717 | ||
15bbde2b | 718 | /* Return a value representing some low-order bits of X, where the number |
719 | of low-order bits is given by MODE. Note that no conversion is done | |
d823ba47 | 720 | between floating-point and fixed-point values, rather, the bit |
15bbde2b | 721 | representation is returned. |
722 | ||
723 | This function handles the cases in common between gen_lowpart, below, | |
724 | and two variants in cse.c and combine.c. These are the cases that can | |
725 | be safely handled at all points in the compilation. | |
726 | ||
727 | If this is not a case we can handle, return 0. */ | |
728 | ||
729 | rtx | |
730 | gen_lowpart_common (mode, x) | |
731 | enum machine_mode mode; | |
732 | register rtx x; | |
733 | { | |
701e46d0 | 734 | int msize = GET_MODE_SIZE (mode); |
735 | int xsize = GET_MODE_SIZE (GET_MODE (x)); | |
736 | int offset = 0; | |
15bbde2b | 737 | |
738 | if (GET_MODE (x) == mode) | |
739 | return x; | |
740 | ||
741 | /* MODE must occupy no more words than the mode of X. */ | |
742 | if (GET_MODE (x) != VOIDmode | |
701e46d0 | 743 | && ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
744 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
15bbde2b | 745 | return 0; |
746 | ||
81802af6 | 747 | offset = subreg_lowpart_offset (mode, GET_MODE (x)); |
15bbde2b | 748 | |
749 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
64115b39 | 750 | && (GET_MODE_CLASS (mode) == MODE_INT |
751 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
15bbde2b | 752 | { |
753 | /* If we are getting the low-order part of something that has been | |
754 | sign- or zero-extended, we can either just use the object being | |
755 | extended or make a narrower extension. If we want an even smaller | |
756 | piece than the size of the object being extended, call ourselves | |
757 | recursively. | |
758 | ||
759 | This case is used mostly by combine and cse. */ | |
760 | ||
761 | if (GET_MODE (XEXP (x, 0)) == mode) | |
762 | return XEXP (x, 0); | |
763 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
764 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
765 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3ad7bb1c | 766 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
15bbde2b | 767 | } |
3c27c2b2 | 768 | else if (GET_CODE (x) == SUBREG || GET_CODE (x) == REG |
769 | || GET_CODE (x) == CONCAT) | |
81802af6 | 770 | return simplify_gen_subreg (mode, x, GET_MODE (x), offset); |
15bbde2b | 771 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
772 | from the low-order part of the constant. */ | |
64115b39 | 773 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
774 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
775 | && GET_MODE (x) == VOIDmode | |
15bbde2b | 776 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
99e0010b | 777 | { |
778 | /* If MODE is twice the host word size, X is already the desired | |
779 | representation. Otherwise, if MODE is wider than a word, we can't | |
b3b27b2a | 780 | do this. If MODE is exactly a word, return just one CONST_INT. */ |
99e0010b | 781 | |
d347deeb | 782 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
99e0010b | 783 | return x; |
b572011e | 784 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
99e0010b | 785 | return 0; |
b572011e | 786 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
99e0010b | 787 | return (GET_CODE (x) == CONST_INT ? x |
b572011e | 788 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
99e0010b | 789 | else |
790 | { | |
a0d52dee | 791 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
b572011e | 792 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
793 | : CONST_DOUBLE_LOW (x)); | |
99e0010b | 794 | |
a0d52dee | 795 | /* Sign extend to HOST_WIDE_INT. */ |
b3b27b2a | 796 | val = trunc_int_for_mode (val, mode); |
99e0010b | 797 | |
798 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
b572011e | 799 | : GEN_INT (val)); |
99e0010b | 800 | } |
801 | } | |
15bbde2b | 802 | |
c8971cad | 803 | #ifndef REAL_ARITHMETIC |
4a307dd5 | 804 | /* If X is an integral constant but we want it in floating-point, it |
805 | must be the case that we have a union of an integer and a floating-point | |
806 | value. If the machine-parameters allow it, simulate that union here | |
d823ba47 | 807 | and return the result. The two-word and single-word cases are |
414a3664 | 808 | different. */ |
4a307dd5 | 809 | |
f51cb679 | 810 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 811 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
f51cb679 | 812 | || flag_pretend_float) |
4a307dd5 | 813 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
414a3664 | 814 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
815 | && GET_CODE (x) == CONST_INT | |
b572011e | 816 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
414a3664 | 817 | { |
b572011e | 818 | union {HOST_WIDE_INT i; float d; } u; |
414a3664 | 819 | |
820 | u.i = INTVAL (x); | |
715907c0 | 821 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
414a3664 | 822 | } |
414a3664 | 823 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 824 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
414a3664 | 825 | || flag_pretend_float) |
826 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
827 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
4a307dd5 | 828 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
829 | && GET_MODE (x) == VOIDmode | |
b572011e | 830 | && (sizeof (double) * HOST_BITS_PER_CHAR |
831 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
4a307dd5 | 832 | { |
b572011e | 833 | union {HOST_WIDE_INT i[2]; double d; } u; |
834 | HOST_WIDE_INT low, high; | |
4a307dd5 | 835 | |
836 | if (GET_CODE (x) == CONST_INT) | |
b572011e | 837 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
4a307dd5 | 838 | else |
839 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
840 | ||
841 | #ifdef HOST_WORDS_BIG_ENDIAN | |
842 | u.i[0] = high, u.i[1] = low; | |
843 | #else | |
844 | u.i[0] = low, u.i[1] = high; | |
845 | #endif | |
846 | ||
715907c0 | 847 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
4a307dd5 | 848 | } |
e21bed9e | 849 | |
f51cb679 | 850 | /* Similarly, if this is converting a floating-point value into a |
851 | single-word integer. Only do this is the host and target parameters are | |
852 | compatible. */ | |
853 | ||
854 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
b572011e | 855 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
f51cb679 | 856 | || flag_pretend_float) |
64115b39 | 857 | && (GET_MODE_CLASS (mode) == MODE_INT |
858 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
f51cb679 | 859 | && GET_CODE (x) == CONST_DOUBLE |
860 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
861 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
701e46d0 | 862 | return constant_subword (x, (offset / UNITS_PER_WORD), GET_MODE (x)); |
f51cb679 | 863 | |
4a307dd5 | 864 | /* Similarly, if this is converting a floating-point value into a |
865 | two-word integer, we can do this one word at a time and make an | |
866 | integer. Only do this is the host and target parameters are | |
867 | compatible. */ | |
868 | ||
f51cb679 | 869 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 870 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
f51cb679 | 871 | || flag_pretend_float) |
64115b39 | 872 | && (GET_MODE_CLASS (mode) == MODE_INT |
6ff0332a | 873 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
4a307dd5 | 874 | && GET_CODE (x) == CONST_DOUBLE |
875 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
876 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
877 | { | |
701e46d0 | 878 | rtx lowpart, highpart; |
879 | ||
880 | lowpart = constant_subword (x, | |
881 | (offset / UNITS_PER_WORD) + WORDS_BIG_ENDIAN, | |
882 | GET_MODE (x)); | |
883 | highpart = constant_subword (x, | |
884 | (offset / UNITS_PER_WORD) + (! WORDS_BIG_ENDIAN), | |
885 | GET_MODE (x)); | |
4a307dd5 | 886 | if (lowpart && GET_CODE (lowpart) == CONST_INT |
887 | && highpart && GET_CODE (highpart) == CONST_INT) | |
888 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
889 | } | |
c8971cad | 890 | #else /* ifndef REAL_ARITHMETIC */ |
891 | ||
892 | /* When we have a FP emulator, we can handle all conversions between | |
893 | FP and integer operands. This simplifies reload because it | |
894 | doesn't have to deal with constructs like (subreg:DI | |
895 | (const_double:SF ...)) or (subreg:DF (const_int ...)). */ | |
7547817f | 896 | /* Single-precision floats are always 32-bits and double-precision |
897 | floats are always 64-bits. */ | |
c8971cad | 898 | |
3c27c2b2 | 899 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7547817f | 900 | && GET_MODE_BITSIZE (mode) == 32 |
c8971cad | 901 | && GET_CODE (x) == CONST_INT) |
3c27c2b2 | 902 | { |
c8971cad | 903 | REAL_VALUE_TYPE r; |
904 | HOST_WIDE_INT i; | |
905 | ||
906 | i = INTVAL (x); | |
907 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
908 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
3c27c2b2 | 909 | } |
910 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7547817f | 911 | && GET_MODE_BITSIZE (mode) == 64 |
c8971cad | 912 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
913 | && GET_MODE (x) == VOIDmode) | |
914 | { | |
915 | REAL_VALUE_TYPE r; | |
916 | HOST_WIDE_INT i[2]; | |
917 | HOST_WIDE_INT low, high; | |
918 | ||
919 | if (GET_CODE (x) == CONST_INT) | |
920 | { | |
921 | low = INTVAL (x); | |
922 | high = low >> (HOST_BITS_PER_WIDE_INT - 1); | |
923 | } | |
924 | else | |
925 | { | |
d823ba47 | 926 | low = CONST_DOUBLE_LOW (x); |
c8971cad | 927 | high = CONST_DOUBLE_HIGH (x); |
928 | } | |
929 | ||
930 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the | |
931 | target machine. */ | |
932 | if (WORDS_BIG_ENDIAN) | |
933 | i[0] = high, i[1] = low; | |
934 | else | |
935 | i[0] = low, i[1] = high; | |
936 | ||
937 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
938 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
939 | } | |
940 | else if ((GET_MODE_CLASS (mode) == MODE_INT | |
941 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
942 | && GET_CODE (x) == CONST_DOUBLE | |
943 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
944 | { | |
945 | REAL_VALUE_TYPE r; | |
946 | long i[4]; /* Only the low 32 bits of each 'long' are used. */ | |
947 | int endian = WORDS_BIG_ENDIAN ? 1 : 0; | |
948 | ||
949 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
7547817f | 950 | switch (GET_MODE_BITSIZE (GET_MODE (x))) |
c8971cad | 951 | { |
7547817f | 952 | case 32: |
c8971cad | 953 | REAL_VALUE_TO_TARGET_SINGLE (r, i[endian]); |
a774762c | 954 | i[1 - endian] = 0; |
c8971cad | 955 | break; |
7547817f | 956 | case 64: |
c8971cad | 957 | REAL_VALUE_TO_TARGET_DOUBLE (r, i); |
958 | break; | |
7547817f | 959 | case 96: |
3f980cf7 | 960 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i + endian); |
961 | i[3-3*endian] = 0; | |
3c27c2b2 | 962 | break; |
7547817f | 963 | case 128: |
c8971cad | 964 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i); |
965 | break; | |
966 | default: | |
a774762c | 967 | abort (); |
c8971cad | 968 | } |
969 | ||
970 | /* Now, pack the 32-bit elements of the array into a CONST_DOUBLE | |
971 | and return it. */ | |
972 | #if HOST_BITS_PER_WIDE_INT == 32 | |
a774762c | 973 | return immed_double_const (i[endian], i[1 - endian], mode); |
c8971cad | 974 | #else |
83e32a86 | 975 | { |
976 | int c; | |
977 | ||
978 | if (HOST_BITS_PER_WIDE_INT != 64) | |
a774762c | 979 | abort (); |
980 | ||
83e32a86 | 981 | for (c = 0; c < 4; c++) |
a774762c | 982 | i[c] &= ~ (0L); |
3f980cf7 | 983 | |
7547817f | 984 | switch (GET_MODE_BITSIZE (GET_MODE (x))) |
3f980cf7 | 985 | { |
7547817f | 986 | case 32: |
987 | case 64: | |
3f980cf7 | 988 | return immed_double_const (((unsigned long) i[endian]) | |
989 | (((HOST_WIDE_INT) i[1-endian]) << 32), | |
990 | 0, mode); | |
7547817f | 991 | case 96: |
992 | case 128: | |
3f980cf7 | 993 | return immed_double_const (((unsigned long) i[endian*3]) | |
994 | (((HOST_WIDE_INT) i[1+endian]) << 32), | |
995 | ((unsigned long) i[2-endian]) | | |
996 | (((HOST_WIDE_INT) i[3-endian*3]) << 32), | |
997 | mode); | |
3c27c2b2 | 998 | default: |
999 | abort (); | |
3f980cf7 | 1000 | } |
83e32a86 | 1001 | } |
c8971cad | 1002 | #endif |
1003 | } | |
1004 | #endif /* ifndef REAL_ARITHMETIC */ | |
4a307dd5 | 1005 | |
15bbde2b | 1006 | /* Otherwise, we can't do this. */ |
1007 | return 0; | |
1008 | } | |
1009 | \f | |
568f439b | 1010 | /* Return the real part (which has mode MODE) of a complex value X. |
1011 | This always comes at the low address in memory. */ | |
1012 | ||
1013 | rtx | |
1014 | gen_realpart (mode, x) | |
1015 | enum machine_mode mode; | |
1016 | register rtx x; | |
1017 | { | |
81802af6 | 1018 | if (WORDS_BIG_ENDIAN |
1019 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
1020 | && REG_P (x) | |
1021 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
f060a027 | 1022 | internal_error |
1023 | ("Can't access real part of complex value in hard register"); | |
0864dc1b | 1024 | else if (WORDS_BIG_ENDIAN) |
568f439b | 1025 | return gen_highpart (mode, x); |
1026 | else | |
1027 | return gen_lowpart (mode, x); | |
1028 | } | |
1029 | ||
1030 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
1031 | This always comes at the high address in memory. */ | |
1032 | ||
1033 | rtx | |
1034 | gen_imagpart (mode, x) | |
1035 | enum machine_mode mode; | |
1036 | register rtx x; | |
1037 | { | |
81802af6 | 1038 | if (WORDS_BIG_ENDIAN) |
568f439b | 1039 | return gen_lowpart (mode, x); |
701e46d0 | 1040 | else if (! WORDS_BIG_ENDIAN |
ea9a92b6 | 1041 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD |
1042 | && REG_P (x) | |
1043 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
f060a027 | 1044 | internal_error |
1045 | ("can't access imaginary part of complex value in hard register"); | |
568f439b | 1046 | else |
1047 | return gen_highpart (mode, x); | |
1048 | } | |
48c70a46 | 1049 | |
1050 | /* Return 1 iff X, assumed to be a SUBREG, | |
1051 | refers to the real part of the complex value in its containing reg. | |
1052 | Complex values are always stored with the real part in the first word, | |
1053 | regardless of WORDS_BIG_ENDIAN. */ | |
1054 | ||
1055 | int | |
1056 | subreg_realpart_p (x) | |
1057 | rtx x; | |
1058 | { | |
1059 | if (GET_CODE (x) != SUBREG) | |
1060 | abort (); | |
1061 | ||
701e46d0 | 1062 | return ((unsigned int) SUBREG_BYTE (x) |
02e7a332 | 1063 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); |
48c70a46 | 1064 | } |
568f439b | 1065 | \f |
15bbde2b | 1066 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1067 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1068 | least-significant part of X. | |
1069 | MODE specifies how big a part of X to return; | |
1070 | it usually should not be larger than a word. | |
1071 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1072 | ||
1073 | rtx | |
1074 | gen_lowpart (mode, x) | |
1075 | enum machine_mode mode; | |
1076 | register rtx x; | |
1077 | { | |
1078 | rtx result = gen_lowpart_common (mode, x); | |
1079 | ||
1080 | if (result) | |
1081 | return result; | |
365c9063 | 1082 | else if (GET_CODE (x) == REG) |
1083 | { | |
1084 | /* Must be a hard reg that's not valid in MODE. */ | |
1085 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1086 | if (result == 0) | |
1087 | abort (); | |
314d6ec8 | 1088 | return result; |
365c9063 | 1089 | } |
15bbde2b | 1090 | else if (GET_CODE (x) == MEM) |
1091 | { | |
1092 | /* The only additional case we can do is MEM. */ | |
1093 | register int offset = 0; | |
1094 | if (WORDS_BIG_ENDIAN) | |
1095 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1096 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1097 | ||
1098 | if (BYTES_BIG_ENDIAN) | |
1099 | /* Adjust the address so that the address-after-the-data | |
1100 | is unchanged. */ | |
1101 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1102 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1103 | ||
e513d163 | 1104 | return adjust_address (x, mode, offset); |
15bbde2b | 1105 | } |
0dbd1c74 | 1106 | else if (GET_CODE (x) == ADDRESSOF) |
1107 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
15bbde2b | 1108 | else |
1109 | abort (); | |
1110 | } | |
1111 | ||
d823ba47 | 1112 | /* Like `gen_lowpart', but refer to the most significant part. |
d56d0ca2 | 1113 | This is used to access the imaginary part of a complex number. */ |
1114 | ||
1115 | rtx | |
1116 | gen_highpart (mode, x) | |
1117 | enum machine_mode mode; | |
1118 | register rtx x; | |
1119 | { | |
701e46d0 | 1120 | unsigned int msize = GET_MODE_SIZE (mode); |
81802af6 | 1121 | rtx result; |
701e46d0 | 1122 | |
d56d0ca2 | 1123 | /* This case loses if X is a subreg. To catch bugs early, |
1124 | complain if an invalid MODE is used even in other cases. */ | |
701e46d0 | 1125 | if (msize > UNITS_PER_WORD |
1126 | && msize != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
d56d0ca2 | 1127 | abort (); |
701e46d0 | 1128 | |
81802af6 | 1129 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1130 | subreg_highpart_offset (mode, GET_MODE (x))); | |
a8c36ab2 | 1131 | |
1132 | /* simplify_gen_subreg is not guaranteed to return a valid operand for | |
1133 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1134 | emitting code if necessary to do so. */ | |
1135 | if (GET_CODE (result) == MEM) | |
1136 | result = validize_mem (result); | |
1137 | ||
81802af6 | 1138 | if (!result) |
1139 | abort (); | |
1140 | return result; | |
1141 | } | |
704fcf2b | 1142 | |
1143 | /* Like gen_highpart_mode, but accept mode of EXP operand in case EXP can | |
1144 | be VOIDmode constant. */ | |
1145 | rtx | |
1146 | gen_highpart_mode (outermode, innermode, exp) | |
1147 | enum machine_mode outermode, innermode; | |
1148 | rtx exp; | |
1149 | { | |
1150 | if (GET_MODE (exp) != VOIDmode) | |
1151 | { | |
1152 | if (GET_MODE (exp) != innermode) | |
1153 | abort (); | |
1154 | return gen_highpart (outermode, exp); | |
1155 | } | |
1156 | return simplify_gen_subreg (outermode, exp, innermode, | |
1157 | subreg_highpart_offset (outermode, innermode)); | |
1158 | } | |
81802af6 | 1159 | /* Return offset in bytes to get OUTERMODE low part |
1160 | of the value in mode INNERMODE stored in memory in target format. */ | |
10ef59ac | 1161 | |
81802af6 | 1162 | unsigned int |
1163 | subreg_lowpart_offset (outermode, innermode) | |
1164 | enum machine_mode outermode, innermode; | |
1165 | { | |
1166 | unsigned int offset = 0; | |
1167 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
10ef59ac | 1168 | |
81802af6 | 1169 | if (difference > 0) |
d56d0ca2 | 1170 | { |
81802af6 | 1171 | if (WORDS_BIG_ENDIAN) |
1172 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1173 | if (BYTES_BIG_ENDIAN) | |
1174 | offset += difference % UNITS_PER_WORD; | |
d56d0ca2 | 1175 | } |
701e46d0 | 1176 | |
81802af6 | 1177 | return offset; |
d56d0ca2 | 1178 | } |
64ab453f | 1179 | |
81802af6 | 1180 | /* Return offset in bytes to get OUTERMODE high part |
1181 | of the value in mode INNERMODE stored in memory in target format. */ | |
1182 | unsigned int | |
1183 | subreg_highpart_offset (outermode, innermode) | |
64ab453f | 1184 | enum machine_mode outermode, innermode; |
64ab453f | 1185 | { |
1186 | unsigned int offset = 0; | |
1187 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1188 | ||
81802af6 | 1189 | if (GET_MODE_SIZE (innermode) < GET_MODE_SIZE (outermode)) |
1190 | abort (); | |
1191 | ||
64ab453f | 1192 | if (difference > 0) |
1193 | { | |
81802af6 | 1194 | if (! WORDS_BIG_ENDIAN) |
64ab453f | 1195 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
81802af6 | 1196 | if (! BYTES_BIG_ENDIAN) |
64ab453f | 1197 | offset += difference % UNITS_PER_WORD; |
1198 | } | |
1199 | ||
81802af6 | 1200 | return offset; |
64ab453f | 1201 | } |
d56d0ca2 | 1202 | |
15bbde2b | 1203 | /* Return 1 iff X, assumed to be a SUBREG, |
1204 | refers to the least significant part of its containing reg. | |
1205 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1206 | ||
1207 | int | |
1208 | subreg_lowpart_p (x) | |
1209 | rtx x; | |
1210 | { | |
1211 | if (GET_CODE (x) != SUBREG) | |
1212 | return 1; | |
7e14c1bf | 1213 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1214 | return 0; | |
15bbde2b | 1215 | |
81802af6 | 1216 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1217 | == SUBREG_BYTE (x)); | |
15bbde2b | 1218 | } |
1219 | \f | |
15bbde2b | 1220 | |
701e46d0 | 1221 | /* Helper routine for all the constant cases of operand_subword. |
1222 | Some places invoke this directly. */ | |
15bbde2b | 1223 | |
1224 | rtx | |
701e46d0 | 1225 | constant_subword (op, offset, mode) |
15bbde2b | 1226 | rtx op; |
701e46d0 | 1227 | int offset; |
15bbde2b | 1228 | enum machine_mode mode; |
1229 | { | |
b572011e | 1230 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; |
701e46d0 | 1231 | HOST_WIDE_INT val; |
15bbde2b | 1232 | |
1233 | /* If OP is already an integer word, return it. */ | |
1234 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1235 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1236 | return op; | |
1237 | ||
fc92fa61 | 1238 | #ifdef REAL_ARITHMETIC |
915c336f | 1239 | /* The output is some bits, the width of the target machine's word. |
1240 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1241 | host can't. */ | |
0477aa9f | 1242 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
fc92fa61 | 1243 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
48509d90 | 1244 | && GET_MODE_BITSIZE (mode) == 64 |
fc92fa61 | 1245 | && GET_CODE (op) == CONST_DOUBLE) |
1246 | { | |
0477aa9f | 1247 | long k[2]; |
fc92fa61 | 1248 | REAL_VALUE_TYPE rv; |
1249 | ||
1250 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1251 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
48509d90 | 1252 | |
0477aa9f | 1253 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
48509d90 | 1254 | which the words are written depends on the word endianness. |
48509d90 | 1255 | ??? This is a potential portability problem and should |
cd1091f4 | 1256 | be fixed at some point. |
1257 | ||
1258 | We must excercise caution with the sign bit. By definition there | |
1259 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1260 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1261 | So we explicitly mask and sign-extend as necessary. */ | |
0477aa9f | 1262 | if (BITS_PER_WORD == 32) |
cd1091f4 | 1263 | { |
701e46d0 | 1264 | val = k[offset]; |
cd1091f4 | 1265 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1266 | return GEN_INT (val); | |
1267 | } | |
1268 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
701e46d0 | 1269 | else if (BITS_PER_WORD >= 64 && offset == 0) |
cd1091f4 | 1270 | { |
1271 | val = k[! WORDS_BIG_ENDIAN]; | |
1272 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1273 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1274 | return GEN_INT (val); | |
1275 | } | |
0477aa9f | 1276 | #endif |
de8de626 | 1277 | else if (BITS_PER_WORD == 16) |
1278 | { | |
701e46d0 | 1279 | val = k[offset >> 1]; |
1280 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) | |
cd1091f4 | 1281 | val >>= 16; |
bfc60c50 | 1282 | val = ((val & 0xffff) ^ 0x8000) - 0x8000; |
cd1091f4 | 1283 | return GEN_INT (val); |
de8de626 | 1284 | } |
48509d90 | 1285 | else |
1286 | abort (); | |
fc92fa61 | 1287 | } |
61f41e95 | 1288 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1289 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1290 | && GET_MODE_BITSIZE (mode) > 64 | |
1291 | && GET_CODE (op) == CONST_DOUBLE) | |
915c336f | 1292 | { |
1293 | long k[4]; | |
1294 | REAL_VALUE_TYPE rv; | |
61f41e95 | 1295 | |
915c336f | 1296 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1297 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
61f41e95 | 1298 | |
915c336f | 1299 | if (BITS_PER_WORD == 32) |
1300 | { | |
701e46d0 | 1301 | val = k[offset]; |
915c336f | 1302 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1303 | return GEN_INT (val); | |
1304 | } | |
1305 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
701e46d0 | 1306 | else if (BITS_PER_WORD >= 64 && offset <= 1) |
915c336f | 1307 | { |
701e46d0 | 1308 | val = k[offset * 2 + ! WORDS_BIG_ENDIAN]; |
915c336f | 1309 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; |
701e46d0 | 1310 | val |= (HOST_WIDE_INT) k[offset * 2 + WORDS_BIG_ENDIAN] & 0xffffffff; |
915c336f | 1311 | return GEN_INT (val); |
1312 | } | |
1313 | #endif | |
1314 | else | |
1315 | abort (); | |
1316 | } | |
fc92fa61 | 1317 | #else /* no REAL_ARITHMETIC */ |
15bbde2b | 1318 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 1319 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
15bbde2b | 1320 | || flag_pretend_float) |
1321 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1322 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1323 | && GET_CODE (op) == CONST_DOUBLE) | |
35bb04fc | 1324 | { |
1325 | /* The constant is stored in the host's word-ordering, | |
1326 | but we want to access it in the target's word-ordering. Some | |
1327 | compilers don't like a conditional inside macro args, so we have two | |
1328 | copies of the return. */ | |
06683233 | 1329 | #ifdef HOST_WORDS_BIG_ENDIAN |
701e46d0 | 1330 | return GEN_INT (offset == WORDS_BIG_ENDIAN |
35bb04fc | 1331 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); |
06683233 | 1332 | #else |
701e46d0 | 1333 | return GEN_INT (offset != WORDS_BIG_ENDIAN |
35bb04fc | 1334 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); |
06683233 | 1335 | #endif |
35bb04fc | 1336 | } |
fc92fa61 | 1337 | #endif /* no REAL_ARITHMETIC */ |
15bbde2b | 1338 | |
1339 | /* Single word float is a little harder, since single- and double-word | |
1340 | values often do not have the same high-order bits. We have already | |
1341 | verified that we want the only defined word of the single-word value. */ | |
fc92fa61 | 1342 | #ifdef REAL_ARITHMETIC |
0477aa9f | 1343 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
48509d90 | 1344 | && GET_MODE_BITSIZE (mode) == 32 |
fc92fa61 | 1345 | && GET_CODE (op) == CONST_DOUBLE) |
1346 | { | |
0477aa9f | 1347 | long l; |
fc92fa61 | 1348 | REAL_VALUE_TYPE rv; |
1349 | ||
1350 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1351 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
587a9fdf | 1352 | |
cd1091f4 | 1353 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1354 | val = l; | |
1355 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
eb294a2f | 1356 | |
587a9fdf | 1357 | if (BITS_PER_WORD == 16) |
1358 | { | |
701e46d0 | 1359 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) |
cd1091f4 | 1360 | val >>= 16; |
bfc60c50 | 1361 | val = ((val & 0xffff) ^ 0x8000) - 0x8000; |
587a9fdf | 1362 | } |
cd1091f4 | 1363 | |
1364 | return GEN_INT (val); | |
fc92fa61 | 1365 | } |
1366 | #else | |
15bbde2b | 1367 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 1368 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
15bbde2b | 1369 | || flag_pretend_float) |
dc611f66 | 1370 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
15bbde2b | 1371 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1372 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1373 | && GET_CODE (op) == CONST_DOUBLE) | |
1374 | { | |
1375 | double d; | |
b572011e | 1376 | union {float f; HOST_WIDE_INT i; } u; |
15bbde2b | 1377 | |
1378 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1379 | ||
1380 | u.f = d; | |
b572011e | 1381 | return GEN_INT (u.i); |
15bbde2b | 1382 | } |
dc611f66 | 1383 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1384 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1385 | || flag_pretend_float) | |
1386 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1387 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1388 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1389 | && GET_CODE (op) == CONST_DOUBLE) | |
1390 | { | |
1391 | double d; | |
1392 | union {double d; HOST_WIDE_INT i; } u; | |
1393 | ||
1394 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1395 | ||
1396 | u.d = d; | |
1397 | return GEN_INT (u.i); | |
1398 | } | |
fc92fa61 | 1399 | #endif /* no REAL_ARITHMETIC */ |
d823ba47 | 1400 | |
15bbde2b | 1401 | /* The only remaining cases that we can handle are integers. |
1402 | Convert to proper endianness now since these cases need it. | |
d823ba47 | 1403 | At this point, offset == 0 means the low-order word. |
15bbde2b | 1404 | |
870288ea | 1405 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1406 | in general. However, if OP is (const_int 0), we can just return | |
1407 | it for any word. */ | |
1408 | ||
1409 | if (op == const0_rtx) | |
1410 | return op; | |
15bbde2b | 1411 | |
1412 | if (GET_MODE_CLASS (mode) != MODE_INT | |
870288ea | 1413 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
5c1fd70d | 1414 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
15bbde2b | 1415 | return 0; |
1416 | ||
1417 | if (WORDS_BIG_ENDIAN) | |
701e46d0 | 1418 | offset = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - offset; |
15bbde2b | 1419 | |
1420 | /* Find out which word on the host machine this value is in and get | |
1421 | it from the constant. */ | |
701e46d0 | 1422 | val = (offset / size_ratio == 0 |
15bbde2b | 1423 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) |
1424 | : (GET_CODE (op) == CONST_INT | |
1425 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1426 | ||
5418f2a8 | 1427 | /* Get the value we want into the low bits of val. */ |
b572011e | 1428 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
701e46d0 | 1429 | val = ((val >> ((offset % size_ratio) * BITS_PER_WORD))); |
5418f2a8 | 1430 | |
b2345915 | 1431 | val = trunc_int_for_mode (val, word_mode); |
15bbde2b | 1432 | |
b572011e | 1433 | return GEN_INT (val); |
15bbde2b | 1434 | } |
1435 | ||
701e46d0 | 1436 | /* Return subword OFFSET of operand OP. |
1437 | The word number, OFFSET, is interpreted as the word number starting | |
1438 | at the low-order address. OFFSET 0 is the low-order word if not | |
1439 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1440 | ||
1441 | If we cannot extract the required word, we return zero. Otherwise, | |
1442 | an rtx corresponding to the requested word will be returned. | |
1443 | ||
1444 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1445 | reload has completed, a valid address will always be returned. After | |
1446 | reload, if a valid address cannot be returned, we return zero. | |
1447 | ||
1448 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1449 | it is the responsibility of the caller. | |
1450 | ||
1451 | MODE is the mode of OP in case it is a CONST_INT. | |
1452 | ||
1453 | ??? This is still rather broken for some cases. The problem for the | |
1454 | moment is that all callers of this thing provide no 'goal mode' to | |
1455 | tell us to work with. This exists because all callers were written | |
84e81e84 | 1456 | in a word based SUBREG world. |
1457 | Now use of this function can be deprecated by simplify_subreg in most | |
1458 | cases. | |
1459 | */ | |
701e46d0 | 1460 | |
1461 | rtx | |
1462 | operand_subword (op, offset, validate_address, mode) | |
1463 | rtx op; | |
1464 | unsigned int offset; | |
1465 | int validate_address; | |
1466 | enum machine_mode mode; | |
1467 | { | |
1468 | if (mode == VOIDmode) | |
1469 | mode = GET_MODE (op); | |
1470 | ||
1471 | if (mode == VOIDmode) | |
1472 | abort (); | |
1473 | ||
6312a35e | 1474 | /* If OP is narrower than a word, fail. */ |
701e46d0 | 1475 | if (mode != BLKmode |
1476 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1477 | return 0; | |
1478 | ||
6312a35e | 1479 | /* If we want a word outside OP, return zero. */ |
701e46d0 | 1480 | if (mode != BLKmode |
1481 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1482 | return const0_rtx; | |
1483 | ||
701e46d0 | 1484 | /* Form a new MEM at the requested address. */ |
1485 | if (GET_CODE (op) == MEM) | |
1486 | { | |
e4e86ec5 | 1487 | rtx new = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
701e46d0 | 1488 | |
e4e86ec5 | 1489 | if (! validate_address) |
1490 | return new; | |
1491 | ||
1492 | else if (reload_completed) | |
701e46d0 | 1493 | { |
e4e86ec5 | 1494 | if (! strict_memory_address_p (word_mode, XEXP (new, 0))) |
1495 | return 0; | |
701e46d0 | 1496 | } |
e4e86ec5 | 1497 | else |
1498 | return replace_equiv_address (new, XEXP (new, 0)); | |
701e46d0 | 1499 | } |
1500 | ||
84e81e84 | 1501 | /* Rest can be handled by simplify_subreg. */ |
1502 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
701e46d0 | 1503 | } |
1504 | ||
15bbde2b | 1505 | /* Similar to `operand_subword', but never return 0. If we can't extract |
1506 | the required subword, put OP into a register and try again. If that fails, | |
d823ba47 | 1507 | abort. We always validate the address in this case. |
15bbde2b | 1508 | |
1509 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1510 | ||
1511 | rtx | |
701e46d0 | 1512 | operand_subword_force (op, offset, mode) |
15bbde2b | 1513 | rtx op; |
701e46d0 | 1514 | unsigned int offset; |
15bbde2b | 1515 | enum machine_mode mode; |
1516 | { | |
701e46d0 | 1517 | rtx result = operand_subword (op, offset, 1, mode); |
15bbde2b | 1518 | |
1519 | if (result) | |
1520 | return result; | |
1521 | ||
1522 | if (mode != BLKmode && mode != VOIDmode) | |
ac825d29 | 1523 | { |
1524 | /* If this is a register which can not be accessed by words, copy it | |
1525 | to a pseudo register. */ | |
1526 | if (GET_CODE (op) == REG) | |
1527 | op = copy_to_reg (op); | |
1528 | else | |
1529 | op = force_reg (mode, op); | |
1530 | } | |
15bbde2b | 1531 | |
701e46d0 | 1532 | result = operand_subword (op, offset, 1, mode); |
15bbde2b | 1533 | if (result == 0) |
1534 | abort (); | |
1535 | ||
1536 | return result; | |
1537 | } | |
1538 | \f | |
1539 | /* Given a compare instruction, swap the operands. | |
1540 | A test instruction is changed into a compare of 0 against the operand. */ | |
1541 | ||
1542 | void | |
1543 | reverse_comparison (insn) | |
1544 | rtx insn; | |
1545 | { | |
1546 | rtx body = PATTERN (insn); | |
1547 | rtx comp; | |
1548 | ||
1549 | if (GET_CODE (body) == SET) | |
1550 | comp = SET_SRC (body); | |
1551 | else | |
1552 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1553 | ||
1554 | if (GET_CODE (comp) == COMPARE) | |
1555 | { | |
1556 | rtx op0 = XEXP (comp, 0); | |
1557 | rtx op1 = XEXP (comp, 1); | |
1558 | XEXP (comp, 0) = op1; | |
1559 | XEXP (comp, 1) = op0; | |
1560 | } | |
1561 | else | |
1562 | { | |
7014838c | 1563 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1564 | CONST0_RTX (GET_MODE (comp)), comp); | |
15bbde2b | 1565 | if (GET_CODE (body) == SET) |
1566 | SET_SRC (body) = new; | |
1567 | else | |
1568 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1569 | } | |
1570 | } | |
1571 | \f | |
1572 | /* Return a memory reference like MEMREF, but with its mode changed | |
1573 | to MODE and its address changed to ADDR. | |
1574 | (VOIDmode means don't change the mode. | |
e4e86ec5 | 1575 | NULL for ADDR means don't change the address.) |
1576 | VALIDATE is nonzero if the returned memory location is required to be | |
1577 | valid. */ | |
15bbde2b | 1578 | |
1579 | rtx | |
e4e86ec5 | 1580 | change_address_1 (memref, mode, addr, validate) |
15bbde2b | 1581 | rtx memref; |
1582 | enum machine_mode mode; | |
1583 | rtx addr; | |
e4e86ec5 | 1584 | int validate; |
15bbde2b | 1585 | { |
1586 | rtx new; | |
1587 | ||
1588 | if (GET_CODE (memref) != MEM) | |
1589 | abort (); | |
1590 | if (mode == VOIDmode) | |
1591 | mode = GET_MODE (memref); | |
1592 | if (addr == 0) | |
1593 | addr = XEXP (memref, 0); | |
1594 | ||
e4e86ec5 | 1595 | if (validate) |
15bbde2b | 1596 | { |
e4e86ec5 | 1597 | if (reload_in_progress || reload_completed) |
1598 | { | |
1599 | if (! memory_address_p (mode, addr)) | |
1600 | abort (); | |
1601 | } | |
1602 | else | |
1603 | addr = memory_address (mode, addr); | |
15bbde2b | 1604 | } |
d823ba47 | 1605 | |
e8976cd7 | 1606 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1607 | return memref; | |
1608 | ||
3ad7bb1c | 1609 | new = gen_rtx_MEM (mode, addr); |
6a0934dd | 1610 | MEM_COPY_ATTRIBUTES (new, memref); |
15bbde2b | 1611 | return new; |
1612 | } | |
537ffcfc | 1613 | |
e513d163 | 1614 | /* Return a memory reference like MEMREF, but with its mode changed |
1615 | to MODE and its address offset by OFFSET bytes. */ | |
1616 | ||
1617 | rtx | |
1618 | adjust_address (memref, mode, offset) | |
1619 | rtx memref; | |
1620 | enum machine_mode mode; | |
1621 | HOST_WIDE_INT offset; | |
1622 | { | |
1623 | /* For now, this is just a wrapper for change_address, but eventually | |
1624 | will do memref tracking. */ | |
fb257ae6 | 1625 | rtx addr = XEXP (memref, 0); |
1626 | ||
6cc60c4d | 1627 | /* ??? Prefer to create garbage instead of creating shared rtl. */ |
1628 | addr = copy_rtx (addr); | |
1629 | ||
9c5033bb | 1630 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the |
fb257ae6 | 1631 | object, we can merge it into the LO_SUM. */ |
1632 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
9c5033bb | 1633 | && offset >= 0 |
eca1c9c0 | 1634 | && (unsigned HOST_WIDE_INT) offset |
1635 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
dc556e72 | 1636 | addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0), |
fb257ae6 | 1637 | plus_constant (XEXP (addr, 1), offset)); |
1638 | else | |
1639 | addr = plus_constant (addr, offset); | |
1640 | ||
1641 | return change_address (memref, mode, addr); | |
e513d163 | 1642 | } |
537ffcfc | 1643 | |
e4e86ec5 | 1644 | /* Likewise, but the reference is not required to be valid. */ |
1645 | ||
1646 | rtx | |
1647 | adjust_address_nv (memref, mode, offset) | |
1648 | rtx memref; | |
1649 | enum machine_mode mode; | |
1650 | HOST_WIDE_INT offset; | |
1651 | { | |
1652 | /* For now, this is just a wrapper for change_address, but eventually | |
1653 | will do memref tracking. */ | |
fb257ae6 | 1654 | rtx addr = XEXP (memref, 0); |
1655 | ||
1656 | /* If MEMREF is a LO_SUM and the offset is within the size of the | |
1657 | object, we can merge it into the LO_SUM. */ | |
1658 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
9c5033bb | 1659 | && offset >= 0 |
eca1c9c0 | 1660 | && (unsigned HOST_WIDE_INT) offset |
1661 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
fb257ae6 | 1662 | addr = gen_rtx_LO_SUM (mode, XEXP (addr, 0), |
1663 | plus_constant (XEXP (addr, 1), offset)); | |
1664 | else | |
1665 | addr = plus_constant (addr, offset); | |
1666 | ||
1667 | return change_address_1 (memref, mode, addr, 0); | |
e4e86ec5 | 1668 | } |
1669 | ||
537ffcfc | 1670 | /* Return a memory reference like MEMREF, but with its address changed to |
1671 | ADDR. The caller is asserting that the actual piece of memory pointed | |
1672 | to is the same, just the form of the address is being changed, such as | |
1673 | by putting something into a register. */ | |
1674 | ||
1675 | rtx | |
1676 | replace_equiv_address (memref, addr) | |
1677 | rtx memref; | |
1678 | rtx addr; | |
1679 | { | |
1680 | /* For now, this is just a wrapper for change_address, but eventually | |
1681 | will do memref tracking. */ | |
1682 | return change_address (memref, VOIDmode, addr); | |
1683 | } | |
e4e86ec5 | 1684 | /* Likewise, but the reference is not required to be valid. */ |
1685 | ||
1686 | rtx | |
1687 | replace_equiv_address_nv (memref, addr) | |
1688 | rtx memref; | |
1689 | rtx addr; | |
1690 | { | |
1691 | /* For now, this is just a wrapper for change_address, but eventually | |
1692 | will do memref tracking. */ | |
1693 | return change_address_1 (memref, VOIDmode, addr, 0); | |
1694 | } | |
15bbde2b | 1695 | \f |
1696 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1697 | ||
1698 | rtx | |
1699 | gen_label_rtx () | |
1700 | { | |
649d8da6 | 1701 | register rtx label; |
1702 | ||
b54842d8 | 1703 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
4679ade3 | 1704 | NULL_RTX, label_num++, NULL, NULL); |
649d8da6 | 1705 | |
15bbde2b | 1706 | LABEL_NUSES (label) = 0; |
bfee5366 | 1707 | LABEL_ALTERNATE_NAME (label) = NULL; |
15bbde2b | 1708 | return label; |
1709 | } | |
1710 | \f | |
1711 | /* For procedure integration. */ | |
1712 | ||
15bbde2b | 1713 | /* Install new pointers to the first and last insns in the chain. |
d4c332ff | 1714 | Also, set cur_insn_uid to one higher than the last in use. |
15bbde2b | 1715 | Used for an inline-procedure after copying the insn chain. */ |
1716 | ||
1717 | void | |
1718 | set_new_first_and_last_insn (first, last) | |
1719 | rtx first, last; | |
1720 | { | |
d4c332ff | 1721 | rtx insn; |
1722 | ||
15bbde2b | 1723 | first_insn = first; |
1724 | last_insn = last; | |
d4c332ff | 1725 | cur_insn_uid = 0; |
1726 | ||
1727 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1728 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1729 | ||
1730 | cur_insn_uid++; | |
15bbde2b | 1731 | } |
1732 | ||
1733 | /* Set the range of label numbers found in the current function. | |
1734 | This is used when belatedly compiling an inline function. */ | |
1735 | ||
1736 | void | |
1737 | set_new_first_and_last_label_num (first, last) | |
1738 | int first, last; | |
1739 | { | |
1740 | base_label_num = label_num; | |
1741 | first_label_num = first; | |
1742 | last_label_num = last; | |
1743 | } | |
0a893c29 | 1744 | |
1745 | /* Set the last label number found in the current function. | |
1746 | This is used when belatedly compiling an inline function. */ | |
15bbde2b | 1747 | |
1748 | void | |
0a893c29 | 1749 | set_new_last_label_num (last) |
1750 | int last; | |
15bbde2b | 1751 | { |
0a893c29 | 1752 | base_label_num = label_num; |
1753 | last_label_num = last; | |
15bbde2b | 1754 | } |
0a893c29 | 1755 | \f |
15bbde2b | 1756 | /* Restore all variables describing the current status from the structure *P. |
1757 | This is used after a nested function. */ | |
1758 | ||
1759 | void | |
1760 | restore_emit_status (p) | |
c5b89159 | 1761 | struct function *p ATTRIBUTE_UNUSED; |
15bbde2b | 1762 | { |
bb9d6298 | 1763 | last_label_num = 0; |
0a893c29 | 1764 | clear_emit_caches (); |
15bbde2b | 1765 | } |
26df1c5e | 1766 | |
c788feb1 | 1767 | /* Clear out all parts of the state in F that can safely be discarded |
26df1c5e | 1768 | after the function has been compiled, to let garbage collection |
a57bcb3b | 1769 | reclaim the memory. */ |
c788feb1 | 1770 | |
26df1c5e | 1771 | void |
a57bcb3b | 1772 | free_emit_status (f) |
26df1c5e | 1773 | struct function *f; |
1774 | { | |
1775 | free (f->emit->x_regno_reg_rtx); | |
26df1c5e | 1776 | free (f->emit->regno_pointer_align); |
3c3bb268 | 1777 | free (f->emit); |
1778 | f->emit = NULL; | |
26df1c5e | 1779 | } |
15bbde2b | 1780 | \f |
d823ba47 | 1781 | /* Go through all the RTL insn bodies and copy any invalid shared |
2d96a59a | 1782 | structure. This routine should only be called once. */ |
15bbde2b | 1783 | |
1784 | void | |
2d96a59a | 1785 | unshare_all_rtl (fndecl, insn) |
1786 | tree fndecl; | |
1787 | rtx insn; | |
15bbde2b | 1788 | { |
2d96a59a | 1789 | tree decl; |
15bbde2b | 1790 | |
2d96a59a | 1791 | /* Make sure that virtual parameters are not shared. */ |
1792 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
0e8e37b2 | 1793 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); |
2d96a59a | 1794 | |
72ec8878 | 1795 | /* Make sure that virtual stack slots are not shared. */ |
1796 | unshare_all_decls (DECL_INITIAL (fndecl)); | |
1797 | ||
2d96a59a | 1798 | /* Unshare just about everything else. */ |
1799 | unshare_all_rtl_1 (insn); | |
d823ba47 | 1800 | |
15bbde2b | 1801 | /* Make sure the addresses of stack slots found outside the insn chain |
1802 | (such as, in DECL_RTL of a variable) are not shared | |
1803 | with the insn chain. | |
1804 | ||
1805 | This special care is necessary when the stack slot MEM does not | |
1806 | actually appear in the insn chain. If it does appear, its address | |
1807 | is unshared from all else at that point. */ | |
45733446 | 1808 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
15bbde2b | 1809 | } |
1810 | ||
d823ba47 | 1811 | /* Go through all the RTL insn bodies and copy any invalid shared |
2d96a59a | 1812 | structure, again. This is a fairly expensive thing to do so it |
1813 | should be done sparingly. */ | |
1814 | ||
1815 | void | |
1816 | unshare_all_rtl_again (insn) | |
1817 | rtx insn; | |
1818 | { | |
1819 | rtx p; | |
5244079b | 1820 | tree decl; |
1821 | ||
2d96a59a | 1822 | for (p = insn; p; p = NEXT_INSN (p)) |
9204e736 | 1823 | if (INSN_P (p)) |
2d96a59a | 1824 | { |
1825 | reset_used_flags (PATTERN (p)); | |
1826 | reset_used_flags (REG_NOTES (p)); | |
1827 | reset_used_flags (LOG_LINKS (p)); | |
1828 | } | |
5244079b | 1829 | |
01dc9f0c | 1830 | /* Make sure that virtual stack slots are not shared. */ |
1831 | reset_used_decls (DECL_INITIAL (cfun->decl)); | |
1832 | ||
5244079b | 1833 | /* Make sure that virtual parameters are not shared. */ |
1834 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
1835 | reset_used_flags (DECL_RTL (decl)); | |
1836 | ||
1837 | reset_used_flags (stack_slot_list); | |
1838 | ||
1839 | unshare_all_rtl (cfun->decl, insn); | |
2d96a59a | 1840 | } |
1841 | ||
1842 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1843 | Assumes the mark bits are cleared at entry. */ | |
1844 | ||
1845 | static void | |
1846 | unshare_all_rtl_1 (insn) | |
1847 | rtx insn; | |
1848 | { | |
1849 | for (; insn; insn = NEXT_INSN (insn)) | |
9204e736 | 1850 | if (INSN_P (insn)) |
2d96a59a | 1851 | { |
1852 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1853 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1854 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1855 | } | |
1856 | } | |
1857 | ||
72ec8878 | 1858 | /* Go through all virtual stack slots of a function and copy any |
1859 | shared structure. */ | |
1860 | static void | |
1861 | unshare_all_decls (blk) | |
1862 | tree blk; | |
1863 | { | |
1864 | tree t; | |
1865 | ||
1866 | /* Copy shared decls. */ | |
1867 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
0e8e37b2 | 1868 | if (DECL_RTL_SET_P (t)) |
1869 | SET_DECL_RTL (t, copy_rtx_if_shared (DECL_RTL (t))); | |
72ec8878 | 1870 | |
1871 | /* Now process sub-blocks. */ | |
1872 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1873 | unshare_all_decls (t); | |
1874 | } | |
1875 | ||
01dc9f0c | 1876 | /* Go through all virtual stack slots of a function and mark them as |
6312a35e | 1877 | not shared. */ |
01dc9f0c | 1878 | static void |
1879 | reset_used_decls (blk) | |
1880 | tree blk; | |
1881 | { | |
1882 | tree t; | |
1883 | ||
1884 | /* Mark decls. */ | |
1885 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
0e8e37b2 | 1886 | if (DECL_RTL_SET_P (t)) |
1887 | reset_used_flags (DECL_RTL (t)); | |
01dc9f0c | 1888 | |
1889 | /* Now process sub-blocks. */ | |
1890 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1891 | reset_used_decls (t); | |
1892 | } | |
1893 | ||
15bbde2b | 1894 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1895 | Recursively does the same for subexpressions. */ | |
1896 | ||
1897 | rtx | |
1898 | copy_rtx_if_shared (orig) | |
1899 | rtx orig; | |
1900 | { | |
1901 | register rtx x = orig; | |
1902 | register int i; | |
1903 | register enum rtx_code code; | |
d2ca078f | 1904 | register const char *format_ptr; |
15bbde2b | 1905 | int copied = 0; |
1906 | ||
1907 | if (x == 0) | |
1908 | return 0; | |
1909 | ||
1910 | code = GET_CODE (x); | |
1911 | ||
1912 | /* These types may be freely shared. */ | |
1913 | ||
1914 | switch (code) | |
1915 | { | |
1916 | case REG: | |
1917 | case QUEUED: | |
1918 | case CONST_INT: | |
1919 | case CONST_DOUBLE: | |
1920 | case SYMBOL_REF: | |
1921 | case CODE_LABEL: | |
1922 | case PC: | |
1923 | case CC0: | |
1924 | case SCRATCH: | |
a92771b8 | 1925 | /* SCRATCH must be shared because they represent distinct values. */ |
15bbde2b | 1926 | return x; |
1927 | ||
f63d12e3 | 1928 | case CONST: |
1929 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
1930 | a LABEL_REF, it isn't sharable. */ | |
1931 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1932 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1933 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1934 | return x; | |
1935 | break; | |
1936 | ||
15bbde2b | 1937 | case INSN: |
1938 | case JUMP_INSN: | |
1939 | case CALL_INSN: | |
1940 | case NOTE: | |
15bbde2b | 1941 | case BARRIER: |
1942 | /* The chain of insns is not being copied. */ | |
1943 | return x; | |
1944 | ||
1945 | case MEM: | |
baf55c37 | 1946 | /* A MEM is allowed to be shared if its address is constant. |
1947 | ||
d823ba47 | 1948 | We used to allow sharing of MEMs which referenced |
baf55c37 | 1949 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but |
1950 | that can lose. instantiate_virtual_regs will not unshare | |
1951 | the MEMs, and combine may change the structure of the address | |
1952 | because it looks safe and profitable in one context, but | |
1953 | in some other context it creates unrecognizable RTL. */ | |
1954 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
15bbde2b | 1955 | return x; |
1956 | ||
0dbd1c74 | 1957 | break; |
1958 | ||
1959 | default: | |
1960 | break; | |
15bbde2b | 1961 | } |
1962 | ||
1963 | /* This rtx may not be shared. If it has already been seen, | |
1964 | replace it with a copy of itself. */ | |
1965 | ||
1966 | if (x->used) | |
1967 | { | |
1968 | register rtx copy; | |
1969 | ||
1970 | copy = rtx_alloc (code); | |
b1b63592 | 1971 | memcpy (copy, x, |
748e6d74 | 1972 | (sizeof (*copy) - sizeof (copy->fld) |
1973 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
15bbde2b | 1974 | x = copy; |
1975 | copied = 1; | |
1976 | } | |
1977 | x->used = 1; | |
1978 | ||
1979 | /* Now scan the subexpressions recursively. | |
1980 | We can store any replaced subexpressions directly into X | |
1981 | since we know X is not shared! Any vectors in X | |
1982 | must be copied if X was copied. */ | |
1983 | ||
1984 | format_ptr = GET_RTX_FORMAT (code); | |
1985 | ||
1986 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1987 | { | |
1988 | switch (*format_ptr++) | |
1989 | { | |
1990 | case 'e': | |
1991 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
1992 | break; | |
1993 | ||
1994 | case 'E': | |
1995 | if (XVEC (x, i) != NULL) | |
1996 | { | |
1997 | register int j; | |
ffe0869b | 1998 | int len = XVECLEN (x, i); |
15bbde2b | 1999 | |
ffe0869b | 2000 | if (copied && len > 0) |
a4070a91 | 2001 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
ffe0869b | 2002 | for (j = 0; j < len; j++) |
2003 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
15bbde2b | 2004 | } |
2005 | break; | |
2006 | } | |
2007 | } | |
2008 | return x; | |
2009 | } | |
2010 | ||
2011 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2012 | to look for shared sub-parts. */ | |
2013 | ||
2014 | void | |
2015 | reset_used_flags (x) | |
2016 | rtx x; | |
2017 | { | |
2018 | register int i, j; | |
2019 | register enum rtx_code code; | |
d2ca078f | 2020 | register const char *format_ptr; |
15bbde2b | 2021 | |
2022 | if (x == 0) | |
2023 | return; | |
2024 | ||
2025 | code = GET_CODE (x); | |
2026 | ||
c3418f42 | 2027 | /* These types may be freely shared so we needn't do any resetting |
15bbde2b | 2028 | for them. */ |
2029 | ||
2030 | switch (code) | |
2031 | { | |
2032 | case REG: | |
2033 | case QUEUED: | |
2034 | case CONST_INT: | |
2035 | case CONST_DOUBLE: | |
2036 | case SYMBOL_REF: | |
2037 | case CODE_LABEL: | |
2038 | case PC: | |
2039 | case CC0: | |
2040 | return; | |
2041 | ||
2042 | case INSN: | |
2043 | case JUMP_INSN: | |
2044 | case CALL_INSN: | |
2045 | case NOTE: | |
2046 | case LABEL_REF: | |
2047 | case BARRIER: | |
2048 | /* The chain of insns is not being copied. */ | |
2049 | return; | |
d823ba47 | 2050 | |
0dbd1c74 | 2051 | default: |
2052 | break; | |
15bbde2b | 2053 | } |
2054 | ||
2055 | x->used = 0; | |
2056 | ||
2057 | format_ptr = GET_RTX_FORMAT (code); | |
2058 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2059 | { | |
2060 | switch (*format_ptr++) | |
2061 | { | |
2062 | case 'e': | |
2063 | reset_used_flags (XEXP (x, i)); | |
2064 | break; | |
2065 | ||
2066 | case 'E': | |
2067 | for (j = 0; j < XVECLEN (x, i); j++) | |
2068 | reset_used_flags (XVECEXP (x, i, j)); | |
2069 | break; | |
2070 | } | |
2071 | } | |
2072 | } | |
2073 | \f | |
2074 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2075 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2076 | OTHER must be valid as a SET_DEST. */ | |
2077 | ||
2078 | rtx | |
2079 | make_safe_from (x, other) | |
2080 | rtx x, other; | |
2081 | { | |
2082 | while (1) | |
2083 | switch (GET_CODE (other)) | |
2084 | { | |
2085 | case SUBREG: | |
2086 | other = SUBREG_REG (other); | |
2087 | break; | |
2088 | case STRICT_LOW_PART: | |
2089 | case SIGN_EXTEND: | |
2090 | case ZERO_EXTEND: | |
2091 | other = XEXP (other, 0); | |
2092 | break; | |
2093 | default: | |
2094 | goto done; | |
2095 | } | |
2096 | done: | |
2097 | if ((GET_CODE (other) == MEM | |
2098 | && ! CONSTANT_P (x) | |
2099 | && GET_CODE (x) != REG | |
2100 | && GET_CODE (x) != SUBREG) | |
2101 | || (GET_CODE (other) == REG | |
2102 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
2103 | || reg_mentioned_p (other, x)))) | |
2104 | { | |
2105 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2106 | emit_move_insn (temp, x); | |
2107 | return temp; | |
2108 | } | |
2109 | return x; | |
2110 | } | |
2111 | \f | |
2112 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2113 | ||
2114 | /* Return the first insn of the current sequence or current function. */ | |
2115 | ||
2116 | rtx | |
2117 | get_insns () | |
2118 | { | |
2119 | return first_insn; | |
2120 | } | |
2121 | ||
2122 | /* Return the last insn emitted in current sequence or current function. */ | |
2123 | ||
2124 | rtx | |
2125 | get_last_insn () | |
2126 | { | |
2127 | return last_insn; | |
2128 | } | |
2129 | ||
2130 | /* Specify a new insn as the last in the chain. */ | |
2131 | ||
2132 | void | |
2133 | set_last_insn (insn) | |
2134 | rtx insn; | |
2135 | { | |
2136 | if (NEXT_INSN (insn) != 0) | |
2137 | abort (); | |
2138 | last_insn = insn; | |
2139 | } | |
2140 | ||
2141 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2142 | ||
2143 | rtx | |
2144 | get_last_insn_anywhere () | |
2145 | { | |
2146 | struct sequence_stack *stack; | |
2147 | if (last_insn) | |
2148 | return last_insn; | |
0a893c29 | 2149 | for (stack = seq_stack; stack; stack = stack->next) |
15bbde2b | 2150 | if (stack->last != 0) |
2151 | return stack->last; | |
2152 | return 0; | |
2153 | } | |
2154 | ||
2155 | /* Return a number larger than any instruction's uid in this function. */ | |
2156 | ||
2157 | int | |
2158 | get_max_uid () | |
2159 | { | |
2160 | return cur_insn_uid; | |
2161 | } | |
90b89d2c | 2162 | |
214d02d0 | 2163 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2164 | ||
90b89d2c | 2165 | void |
214d02d0 | 2166 | renumber_insns (stream) |
2167 | FILE *stream; | |
90b89d2c | 2168 | { |
2169 | rtx insn; | |
90b89d2c | 2170 | |
214d02d0 | 2171 | /* If we're not supposed to renumber instructions, don't. */ |
2172 | if (!flag_renumber_insns) | |
2173 | return; | |
2174 | ||
90b89d2c | 2175 | /* If there aren't that many instructions, then it's not really |
2176 | worth renumbering them. */ | |
214d02d0 | 2177 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
90b89d2c | 2178 | return; |
2179 | ||
2180 | cur_insn_uid = 1; | |
2181 | ||
2182 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
214d02d0 | 2183 | { |
2184 | if (stream) | |
d823ba47 | 2185 | fprintf (stream, "Renumbering insn %d to %d\n", |
214d02d0 | 2186 | INSN_UID (insn), cur_insn_uid); |
2187 | INSN_UID (insn) = cur_insn_uid++; | |
2188 | } | |
90b89d2c | 2189 | } |
15bbde2b | 2190 | \f |
2191 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2192 | of the sequence. */ | |
2193 | ||
2194 | rtx | |
2195 | next_insn (insn) | |
2196 | rtx insn; | |
2197 | { | |
2198 | if (insn) | |
2199 | { | |
2200 | insn = NEXT_INSN (insn); | |
2201 | if (insn && GET_CODE (insn) == INSN | |
2202 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2203 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2204 | } | |
2205 | ||
2206 | return insn; | |
2207 | } | |
2208 | ||
2209 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2210 | of the sequence. */ | |
2211 | ||
2212 | rtx | |
2213 | previous_insn (insn) | |
2214 | rtx insn; | |
2215 | { | |
2216 | if (insn) | |
2217 | { | |
2218 | insn = PREV_INSN (insn); | |
2219 | if (insn && GET_CODE (insn) == INSN | |
2220 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2221 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2222 | } | |
2223 | ||
2224 | return insn; | |
2225 | } | |
2226 | ||
2227 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2228 | look inside SEQUENCEs. */ | |
2229 | ||
2230 | rtx | |
2231 | next_nonnote_insn (insn) | |
2232 | rtx insn; | |
2233 | { | |
2234 | while (insn) | |
2235 | { | |
2236 | insn = NEXT_INSN (insn); | |
2237 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2238 | break; | |
2239 | } | |
2240 | ||
2241 | return insn; | |
2242 | } | |
2243 | ||
2244 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2245 | not look inside SEQUENCEs. */ | |
2246 | ||
2247 | rtx | |
2248 | prev_nonnote_insn (insn) | |
2249 | rtx insn; | |
2250 | { | |
2251 | while (insn) | |
2252 | { | |
2253 | insn = PREV_INSN (insn); | |
2254 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2255 | break; | |
2256 | } | |
2257 | ||
2258 | return insn; | |
2259 | } | |
2260 | ||
2261 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2262 | or 0, if there is none. This routine does not look inside | |
a92771b8 | 2263 | SEQUENCEs. */ |
15bbde2b | 2264 | |
2265 | rtx | |
2266 | next_real_insn (insn) | |
2267 | rtx insn; | |
2268 | { | |
2269 | while (insn) | |
2270 | { | |
2271 | insn = NEXT_INSN (insn); | |
2272 | if (insn == 0 || GET_CODE (insn) == INSN | |
2273 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2274 | break; | |
2275 | } | |
2276 | ||
2277 | return insn; | |
2278 | } | |
2279 | ||
2280 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2281 | or 0, if there is none. This routine does not look inside | |
2282 | SEQUENCEs. */ | |
2283 | ||
2284 | rtx | |
2285 | prev_real_insn (insn) | |
2286 | rtx insn; | |
2287 | { | |
2288 | while (insn) | |
2289 | { | |
2290 | insn = PREV_INSN (insn); | |
2291 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2292 | || GET_CODE (insn) == JUMP_INSN) | |
2293 | break; | |
2294 | } | |
2295 | ||
2296 | return insn; | |
2297 | } | |
2298 | ||
2299 | /* Find the next insn after INSN that really does something. This routine | |
2300 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2301 | same as next_real_insn. */ | |
2302 | ||
2215ca0d | 2303 | int |
2304 | active_insn_p (insn) | |
2305 | rtx insn; | |
2306 | { | |
2307 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2308 | || (GET_CODE (insn) == INSN | |
2309 | && (! reload_completed | |
2310 | || (GET_CODE (PATTERN (insn)) != USE | |
2311 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2312 | } | |
2313 | ||
15bbde2b | 2314 | rtx |
2315 | next_active_insn (insn) | |
2316 | rtx insn; | |
2317 | { | |
2318 | while (insn) | |
2319 | { | |
2320 | insn = NEXT_INSN (insn); | |
2215ca0d | 2321 | if (insn == 0 || active_insn_p (insn)) |
15bbde2b | 2322 | break; |
2323 | } | |
2324 | ||
2325 | return insn; | |
2326 | } | |
2327 | ||
2328 | /* Find the last insn before INSN that really does something. This routine | |
2329 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2330 | same as prev_real_insn. */ | |
2331 | ||
2332 | rtx | |
2333 | prev_active_insn (insn) | |
2334 | rtx insn; | |
2335 | { | |
2336 | while (insn) | |
2337 | { | |
2338 | insn = PREV_INSN (insn); | |
2215ca0d | 2339 | if (insn == 0 || active_insn_p (insn)) |
15bbde2b | 2340 | break; |
2341 | } | |
2342 | ||
2343 | return insn; | |
2344 | } | |
2345 | ||
2346 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2347 | ||
2348 | rtx | |
2349 | next_label (insn) | |
2350 | rtx insn; | |
2351 | { | |
2352 | while (insn) | |
2353 | { | |
2354 | insn = NEXT_INSN (insn); | |
2355 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2356 | break; | |
2357 | } | |
2358 | ||
2359 | return insn; | |
2360 | } | |
2361 | ||
2362 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2363 | ||
2364 | rtx | |
2365 | prev_label (insn) | |
2366 | rtx insn; | |
2367 | { | |
2368 | while (insn) | |
2369 | { | |
2370 | insn = PREV_INSN (insn); | |
2371 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2372 | break; | |
2373 | } | |
2374 | ||
2375 | return insn; | |
2376 | } | |
2377 | \f | |
2378 | #ifdef HAVE_cc0 | |
b15e0bba | 2379 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2380 | and REG_CC_USER notes so we can find it. */ | |
2381 | ||
2382 | void | |
2383 | link_cc0_insns (insn) | |
2384 | rtx insn; | |
2385 | { | |
2386 | rtx user = next_nonnote_insn (insn); | |
2387 | ||
2388 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2389 | user = XVECEXP (PATTERN (user), 0, 0); | |
2390 | ||
7014838c | 2391 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2392 | REG_NOTES (user)); | |
3ad7bb1c | 2393 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
b15e0bba | 2394 | } |
2395 | ||
15bbde2b | 2396 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2397 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2398 | applied to the result of this function should yield INSN). | |
2399 | ||
2400 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2401 | is present, it contains the insn that uses CC0. | |
2402 | ||
2403 | Return 0 if we can't find the insn. */ | |
2404 | ||
2405 | rtx | |
2406 | next_cc0_user (insn) | |
2407 | rtx insn; | |
2408 | { | |
b572011e | 2409 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
15bbde2b | 2410 | |
2411 | if (note) | |
2412 | return XEXP (note, 0); | |
2413 | ||
2414 | insn = next_nonnote_insn (insn); | |
2415 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2416 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2417 | ||
9204e736 | 2418 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
15bbde2b | 2419 | return insn; |
2420 | ||
2421 | return 0; | |
2422 | } | |
2423 | ||
2424 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2425 | note, it is the previous insn. */ | |
2426 | ||
2427 | rtx | |
2428 | prev_cc0_setter (insn) | |
2429 | rtx insn; | |
2430 | { | |
b572011e | 2431 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
15bbde2b | 2432 | |
2433 | if (note) | |
2434 | return XEXP (note, 0); | |
2435 | ||
2436 | insn = prev_nonnote_insn (insn); | |
2437 | if (! sets_cc0_p (PATTERN (insn))) | |
2438 | abort (); | |
2439 | ||
2440 | return insn; | |
2441 | } | |
2442 | #endif | |
344dc2fa | 2443 | |
2444 | /* Increment the label uses for all labels present in rtx. */ | |
2445 | ||
2446 | static void | |
2447 | mark_label_nuses(x) | |
2448 | rtx x; | |
2449 | { | |
2450 | register enum rtx_code code; | |
2451 | register int i, j; | |
2452 | register const char *fmt; | |
2453 | ||
2454 | code = GET_CODE (x); | |
2455 | if (code == LABEL_REF) | |
2456 | LABEL_NUSES (XEXP (x, 0))++; | |
2457 | ||
2458 | fmt = GET_RTX_FORMAT (code); | |
2459 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2460 | { | |
2461 | if (fmt[i] == 'e') | |
2462 | mark_label_nuses (XEXP (x, i)); | |
2463 | else if (fmt[i] == 'E') | |
2464 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2465 | mark_label_nuses (XVECEXP (x, i, j)); | |
2466 | } | |
2467 | } | |
2468 | ||
15bbde2b | 2469 | \f |
2470 | /* Try splitting insns that can be split for better scheduling. | |
2471 | PAT is the pattern which might split. | |
2472 | TRIAL is the insn providing PAT. | |
0e69a50a | 2473 | LAST is non-zero if we should return the last insn of the sequence produced. |
15bbde2b | 2474 | |
2475 | If this routine succeeds in splitting, it returns the first or last | |
0e69a50a | 2476 | replacement insn depending on the value of LAST. Otherwise, it |
15bbde2b | 2477 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2478 | ||
2479 | rtx | |
0e69a50a | 2480 | try_split (pat, trial, last) |
15bbde2b | 2481 | rtx pat, trial; |
0e69a50a | 2482 | int last; |
15bbde2b | 2483 | { |
2484 | rtx before = PREV_INSN (trial); | |
2485 | rtx after = NEXT_INSN (trial); | |
15bbde2b | 2486 | int has_barrier = 0; |
2487 | rtx tem; | |
3cd757b1 | 2488 | rtx note, seq; |
2489 | int probability; | |
2490 | ||
2491 | if (any_condjump_p (trial) | |
2492 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
2493 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
2494 | probability = split_branch_probability; | |
2495 | ||
2496 | seq = split_insns (pat, trial); | |
2497 | ||
2498 | split_branch_probability = -1; | |
15bbde2b | 2499 | |
2500 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2501 | We may need to handle this specially. */ | |
2502 | if (after && GET_CODE (after) == BARRIER) | |
2503 | { | |
2504 | has_barrier = 1; | |
2505 | after = NEXT_INSN (after); | |
2506 | } | |
2507 | ||
2508 | if (seq) | |
2509 | { | |
2510 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2511 | The latter case will normally arise only when being done so that | |
2512 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2513 | if (GET_CODE (seq) == SEQUENCE) | |
2514 | { | |
3cd757b1 | 2515 | int i, njumps = 0; |
5bb27a4b | 2516 | rtx eh_note; |
d823ba47 | 2517 | |
2518 | /* Avoid infinite loop if any insn of the result matches | |
5262c253 | 2519 | the original pattern. */ |
2520 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
d823ba47 | 2521 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN |
5262c253 | 2522 | && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat)) |
d823ba47 | 2523 | return trial; |
5262c253 | 2524 | |
5377f687 | 2525 | /* Mark labels. */ |
2526 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2527 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
3cd757b1 | 2528 | { |
2529 | rtx insn = XVECEXP (seq, 0, i); | |
2530 | mark_jump_label (PATTERN (insn), | |
2531 | XVECEXP (seq, 0, i), 0); | |
2532 | njumps++; | |
2533 | if (probability != -1 | |
2534 | && any_condjump_p (insn) | |
2535 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2536 | { | |
2537 | /* We can preserve the REG_BR_PROB notes only if exactly | |
2538 | one jump is created, otherwise the machinde description | |
2539 | is responsible for this step using | |
2540 | split_branch_probability variable. */ | |
2541 | if (njumps != 1) | |
2542 | abort (); | |
2543 | REG_NOTES (insn) | |
2544 | = gen_rtx_EXPR_LIST (REG_BR_PROB, | |
2545 | GEN_INT (probability), | |
2546 | REG_NOTES (insn)); | |
2547 | } | |
2548 | } | |
1b3a64a8 | 2549 | /* If we are splitting a CALL_INSN, look for the CALL_INSN |
2550 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
2551 | if (GET_CODE (trial) == CALL_INSN) | |
2552 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2553 | if (GET_CODE (XVECEXP (seq, 0, i)) == CALL_INSN) | |
2554 | CALL_INSN_FUNCTION_USAGE (XVECEXP (seq, 0, i)) | |
2555 | = CALL_INSN_FUNCTION_USAGE (trial); | |
2556 | ||
5bb27a4b | 2557 | /* Copy EH notes. */ |
2558 | if ((eh_note = find_reg_note (trial, REG_EH_REGION, NULL_RTX))) | |
2559 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2560 | { | |
2561 | rtx insn = XVECEXP (seq, 0, i); | |
2562 | if (GET_CODE (insn) == CALL_INSN | |
d823ba47 | 2563 | || (flag_non_call_exceptions |
5bb27a4b | 2564 | && may_trap_p (PATTERN (insn)))) |
d823ba47 | 2565 | REG_NOTES (insn) |
5bb27a4b | 2566 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), |
2567 | REG_NOTES (insn)); | |
2568 | } | |
2569 | ||
344dc2fa | 2570 | /* If there are LABELS inside the split insns increment the |
2571 | usage count so we don't delete the label. */ | |
2572 | if (GET_CODE (trial) == INSN) | |
2573 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2574 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN) | |
2575 | mark_label_nuses (PATTERN (XVECEXP (seq, 0, i))); | |
2576 | ||
9dda7915 | 2577 | tem = emit_insn_after (seq, trial); |
15bbde2b | 2578 | |
2579 | delete_insn (trial); | |
2580 | if (has_barrier) | |
2581 | emit_barrier_after (tem); | |
0e69a50a | 2582 | |
2583 | /* Recursively call try_split for each new insn created; by the | |
2584 | time control returns here that insn will be fully split, so | |
2585 | set LAST and continue from the insn after the one returned. | |
06343e77 | 2586 | We can't use next_active_insn here since AFTER may be a note. |
ab6683d6 | 2587 | Ignore deleted insns, which can be occur if not optimizing. */ |
9204e736 | 2588 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) |
2589 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
06343e77 | 2590 | tem = try_split (PATTERN (tem), tem, 1); |
15bbde2b | 2591 | } |
2592 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2593 | else if (rtx_equal_p (seq, pat)) | |
2594 | return trial; | |
2595 | else | |
2596 | { | |
2597 | PATTERN (trial) = seq; | |
2598 | INSN_CODE (trial) = -1; | |
0e69a50a | 2599 | try_split (seq, trial, last); |
15bbde2b | 2600 | } |
2601 | ||
0e69a50a | 2602 | /* Return either the first or the last insn, depending on which was |
2603 | requested. */ | |
d823ba47 | 2604 | return last |
3cd757b1 | 2605 | ? (after ? PREV_INSN (after) : last_insn) |
2606 | : NEXT_INSN (before); | |
15bbde2b | 2607 | } |
2608 | ||
2609 | return trial; | |
2610 | } | |
2611 | \f | |
2612 | /* Make and return an INSN rtx, initializing all its slots. | |
6a84e367 | 2613 | Store PATTERN in the pattern slots. */ |
15bbde2b | 2614 | |
2615 | rtx | |
6a84e367 | 2616 | make_insn_raw (pattern) |
15bbde2b | 2617 | rtx pattern; |
15bbde2b | 2618 | { |
2619 | register rtx insn; | |
2620 | ||
d7c47c0e | 2621 | insn = rtx_alloc (INSN); |
15bbde2b | 2622 | |
575333f9 | 2623 | INSN_UID (insn) = cur_insn_uid++; |
15bbde2b | 2624 | PATTERN (insn) = pattern; |
2625 | INSN_CODE (insn) = -1; | |
fc92fa61 | 2626 | LOG_LINKS (insn) = NULL; |
2627 | REG_NOTES (insn) = NULL; | |
15bbde2b | 2628 | |
fe7f701d | 2629 | #ifdef ENABLE_RTL_CHECKING |
2630 | if (insn | |
9204e736 | 2631 | && INSN_P (insn) |
fe7f701d | 2632 | && (returnjump_p (insn) |
2633 | || (GET_CODE (insn) == SET | |
2634 | && SET_DEST (insn) == pc_rtx))) | |
2635 | { | |
2636 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2637 | debug_rtx (insn); | |
2638 | } | |
2639 | #endif | |
d823ba47 | 2640 | |
15bbde2b | 2641 | return insn; |
2642 | } | |
2643 | ||
2644 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2645 | ||
2646 | static rtx | |
6a84e367 | 2647 | make_jump_insn_raw (pattern) |
15bbde2b | 2648 | rtx pattern; |
15bbde2b | 2649 | { |
2650 | register rtx insn; | |
2651 | ||
6a84e367 | 2652 | insn = rtx_alloc (JUMP_INSN); |
fc92fa61 | 2653 | INSN_UID (insn) = cur_insn_uid++; |
15bbde2b | 2654 | |
2655 | PATTERN (insn) = pattern; | |
2656 | INSN_CODE (insn) = -1; | |
fc92fa61 | 2657 | LOG_LINKS (insn) = NULL; |
2658 | REG_NOTES (insn) = NULL; | |
2659 | JUMP_LABEL (insn) = NULL; | |
15bbde2b | 2660 | |
2661 | return insn; | |
2662 | } | |
6e911104 | 2663 | |
2664 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2665 | ||
2666 | static rtx | |
2667 | make_call_insn_raw (pattern) | |
2668 | rtx pattern; | |
2669 | { | |
2670 | register rtx insn; | |
2671 | ||
2672 | insn = rtx_alloc (CALL_INSN); | |
2673 | INSN_UID (insn) = cur_insn_uid++; | |
2674 | ||
2675 | PATTERN (insn) = pattern; | |
2676 | INSN_CODE (insn) = -1; | |
2677 | LOG_LINKS (insn) = NULL; | |
2678 | REG_NOTES (insn) = NULL; | |
2679 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2680 | ||
2681 | return insn; | |
2682 | } | |
15bbde2b | 2683 | \f |
2684 | /* Add INSN to the end of the doubly-linked list. | |
2685 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2686 | ||
2687 | void | |
2688 | add_insn (insn) | |
2689 | register rtx insn; | |
2690 | { | |
2691 | PREV_INSN (insn) = last_insn; | |
2692 | NEXT_INSN (insn) = 0; | |
2693 | ||
2694 | if (NULL != last_insn) | |
2695 | NEXT_INSN (last_insn) = insn; | |
2696 | ||
2697 | if (NULL == first_insn) | |
2698 | first_insn = insn; | |
2699 | ||
2700 | last_insn = insn; | |
2701 | } | |
2702 | ||
312de84d | 2703 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2704 | the next should be the only functions called to insert an insn once | |
f65c10c0 | 2705 | delay slots have been filled since only they know how to update a |
312de84d | 2706 | SEQUENCE. */ |
15bbde2b | 2707 | |
2708 | void | |
2709 | add_insn_after (insn, after) | |
2710 | rtx insn, after; | |
2711 | { | |
2712 | rtx next = NEXT_INSN (after); | |
9dda7915 | 2713 | basic_block bb; |
15bbde2b | 2714 | |
9ea33026 | 2715 | if (optimize && INSN_DELETED_P (after)) |
f65c10c0 | 2716 | abort (); |
2717 | ||
15bbde2b | 2718 | NEXT_INSN (insn) = next; |
2719 | PREV_INSN (insn) = after; | |
2720 | ||
2721 | if (next) | |
2722 | { | |
2723 | PREV_INSN (next) = insn; | |
2724 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2725 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2726 | } | |
2727 | else if (last_insn == after) | |
2728 | last_insn = insn; | |
2729 | else | |
2730 | { | |
0a893c29 | 2731 | struct sequence_stack *stack = seq_stack; |
15bbde2b | 2732 | /* Scan all pending sequences too. */ |
2733 | for (; stack; stack = stack->next) | |
2734 | if (after == stack->last) | |
398f4855 | 2735 | { |
2736 | stack->last = insn; | |
2737 | break; | |
2738 | } | |
312de84d | 2739 | |
2740 | if (stack == 0) | |
2741 | abort (); | |
15bbde2b | 2742 | } |
2743 | ||
9dda7915 | 2744 | if (basic_block_for_insn |
2745 | && (unsigned int)INSN_UID (after) < basic_block_for_insn->num_elements | |
2746 | && (bb = BLOCK_FOR_INSN (after))) | |
2747 | { | |
2748 | set_block_for_insn (insn, bb); | |
2749 | /* Should not happen as first in the BB is always | |
2750 | eigther NOTE or LABEL. */ | |
2751 | if (bb->end == after | |
2752 | /* Avoid clobbering of structure when creating new BB. */ | |
2753 | && GET_CODE (insn) != BARRIER | |
2754 | && (GET_CODE (insn) != NOTE | |
2755 | || NOTE_LINE_NUMBER (insn) != NOTE_INSN_BASIC_BLOCK)) | |
2756 | bb->end = insn; | |
2757 | } | |
2758 | ||
15bbde2b | 2759 | NEXT_INSN (after) = insn; |
2760 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2761 | { | |
2762 | rtx sequence = PATTERN (after); | |
2763 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2764 | } | |
2765 | } | |
2766 | ||
312de84d | 2767 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2768 | the previous should be the only functions called to insert an insn once | |
f65c10c0 | 2769 | delay slots have been filled since only they know how to update a |
312de84d | 2770 | SEQUENCE. */ |
2771 | ||
2772 | void | |
2773 | add_insn_before (insn, before) | |
2774 | rtx insn, before; | |
2775 | { | |
2776 | rtx prev = PREV_INSN (before); | |
9dda7915 | 2777 | basic_block bb; |
312de84d | 2778 | |
9ea33026 | 2779 | if (optimize && INSN_DELETED_P (before)) |
f65c10c0 | 2780 | abort (); |
2781 | ||
312de84d | 2782 | PREV_INSN (insn) = prev; |
2783 | NEXT_INSN (insn) = before; | |
2784 | ||
2785 | if (prev) | |
2786 | { | |
2787 | NEXT_INSN (prev) = insn; | |
2788 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2789 | { | |
2790 | rtx sequence = PATTERN (prev); | |
2791 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2792 | } | |
2793 | } | |
2794 | else if (first_insn == before) | |
2795 | first_insn = insn; | |
2796 | else | |
2797 | { | |
0a893c29 | 2798 | struct sequence_stack *stack = seq_stack; |
312de84d | 2799 | /* Scan all pending sequences too. */ |
2800 | for (; stack; stack = stack->next) | |
2801 | if (before == stack->first) | |
398f4855 | 2802 | { |
2803 | stack->first = insn; | |
2804 | break; | |
2805 | } | |
312de84d | 2806 | |
2807 | if (stack == 0) | |
2808 | abort (); | |
2809 | } | |
2810 | ||
9dda7915 | 2811 | if (basic_block_for_insn |
2812 | && (unsigned int)INSN_UID (before) < basic_block_for_insn->num_elements | |
2813 | && (bb = BLOCK_FOR_INSN (before))) | |
2814 | { | |
2815 | set_block_for_insn (insn, bb); | |
2816 | /* Should not happen as first in the BB is always | |
2817 | eigther NOTE or LABEl. */ | |
2818 | if (bb->head == insn | |
2819 | /* Avoid clobbering of structure when creating new BB. */ | |
2820 | && GET_CODE (insn) != BARRIER | |
2821 | && (GET_CODE (insn) != NOTE | |
2822 | || NOTE_LINE_NUMBER (insn) != NOTE_INSN_BASIC_BLOCK)) | |
2823 | abort (); | |
2824 | } | |
2825 | ||
312de84d | 2826 | PREV_INSN (before) = insn; |
2827 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2828 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2829 | } | |
2830 | ||
7ddcf2bf | 2831 | /* Remove an insn from its doubly-linked list. This function knows how |
2832 | to handle sequences. */ | |
2833 | void | |
2834 | remove_insn (insn) | |
2835 | rtx insn; | |
2836 | { | |
2837 | rtx next = NEXT_INSN (insn); | |
2838 | rtx prev = PREV_INSN (insn); | |
2839 | if (prev) | |
2840 | { | |
2841 | NEXT_INSN (prev) = next; | |
2842 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2843 | { | |
2844 | rtx sequence = PATTERN (prev); | |
2845 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2846 | } | |
2847 | } | |
2848 | else if (first_insn == insn) | |
2849 | first_insn = next; | |
2850 | else | |
2851 | { | |
0a893c29 | 2852 | struct sequence_stack *stack = seq_stack; |
7ddcf2bf | 2853 | /* Scan all pending sequences too. */ |
2854 | for (; stack; stack = stack->next) | |
2855 | if (insn == stack->first) | |
2856 | { | |
2857 | stack->first = next; | |
2858 | break; | |
2859 | } | |
2860 | ||
2861 | if (stack == 0) | |
2862 | abort (); | |
2863 | } | |
2864 | ||
2865 | if (next) | |
2866 | { | |
2867 | PREV_INSN (next) = prev; | |
2868 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2869 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2870 | } | |
2871 | else if (last_insn == insn) | |
2872 | last_insn = prev; | |
2873 | else | |
2874 | { | |
0a893c29 | 2875 | struct sequence_stack *stack = seq_stack; |
7ddcf2bf | 2876 | /* Scan all pending sequences too. */ |
2877 | for (; stack; stack = stack->next) | |
2878 | if (insn == stack->last) | |
2879 | { | |
2880 | stack->last = prev; | |
2881 | break; | |
2882 | } | |
2883 | ||
2884 | if (stack == 0) | |
2885 | abort (); | |
2886 | } | |
2887 | } | |
2888 | ||
15bbde2b | 2889 | /* Delete all insns made since FROM. |
2890 | FROM becomes the new last instruction. */ | |
2891 | ||
2892 | void | |
2893 | delete_insns_since (from) | |
2894 | rtx from; | |
2895 | { | |
2896 | if (from == 0) | |
2897 | first_insn = 0; | |
2898 | else | |
2899 | NEXT_INSN (from) = 0; | |
2900 | last_insn = from; | |
2901 | } | |
2902 | ||
34e2ddcd | 2903 | /* This function is deprecated, please use sequences instead. |
2904 | ||
2905 | Move a consecutive bunch of insns to a different place in the chain. | |
15bbde2b | 2906 | The insns to be moved are those between FROM and TO. |
2907 | They are moved to a new position after the insn AFTER. | |
2908 | AFTER must not be FROM or TO or any insn in between. | |
2909 | ||
2910 | This function does not know about SEQUENCEs and hence should not be | |
2911 | called after delay-slot filling has been done. */ | |
2912 | ||
2913 | void | |
9dda7915 | 2914 | reorder_insns_nobb (from, to, after) |
15bbde2b | 2915 | rtx from, to, after; |
2916 | { | |
2917 | /* Splice this bunch out of where it is now. */ | |
2918 | if (PREV_INSN (from)) | |
2919 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2920 | if (NEXT_INSN (to)) | |
2921 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2922 | if (last_insn == to) | |
2923 | last_insn = PREV_INSN (from); | |
2924 | if (first_insn == from) | |
2925 | first_insn = NEXT_INSN (to); | |
2926 | ||
2927 | /* Make the new neighbors point to it and it to them. */ | |
2928 | if (NEXT_INSN (after)) | |
2929 | PREV_INSN (NEXT_INSN (after)) = to; | |
2930 | ||
2931 | NEXT_INSN (to) = NEXT_INSN (after); | |
2932 | PREV_INSN (from) = after; | |
2933 | NEXT_INSN (after) = from; | |
2934 | if (after == last_insn) | |
2935 | last_insn = to; | |
2936 | } | |
2937 | ||
9dda7915 | 2938 | /* Same as function above, but take care to update BB boundaries. */ |
2939 | void | |
2940 | reorder_insns (from, to, after) | |
2941 | rtx from, to, after; | |
2942 | { | |
2943 | rtx prev = PREV_INSN (from); | |
2944 | basic_block bb, bb2; | |
2945 | ||
2946 | reorder_insns_nobb (from, to, after); | |
2947 | ||
2948 | if (basic_block_for_insn | |
2949 | && (unsigned int)INSN_UID (after) < basic_block_for_insn->num_elements | |
2950 | && (bb = BLOCK_FOR_INSN (after))) | |
2951 | { | |
2952 | rtx x; | |
2953 | ||
2954 | if (basic_block_for_insn | |
2955 | && (unsigned int)INSN_UID (from) < basic_block_for_insn->num_elements | |
2956 | && (bb2 = BLOCK_FOR_INSN (from))) | |
2957 | { | |
2958 | if (bb2->end == to) | |
2959 | bb2->end = prev; | |
2960 | } | |
2961 | ||
2962 | if (bb->end == after) | |
2963 | bb->end = to; | |
2964 | ||
2965 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
2966 | set_block_for_insn (x, bb); | |
2967 | } | |
2968 | } | |
2969 | ||
15bbde2b | 2970 | /* Return the line note insn preceding INSN. */ |
2971 | ||
2972 | static rtx | |
2973 | find_line_note (insn) | |
2974 | rtx insn; | |
2975 | { | |
2976 | if (no_line_numbers) | |
2977 | return 0; | |
2978 | ||
2979 | for (; insn; insn = PREV_INSN (insn)) | |
2980 | if (GET_CODE (insn) == NOTE | |
2981 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2982 | break; | |
2983 | ||
2984 | return insn; | |
2985 | } | |
2986 | ||
2987 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2988 | of the moved insns when debugging. This may insert a note between AFTER | |
2989 | and FROM, and another one after TO. */ | |
2990 | ||
2991 | void | |
2992 | reorder_insns_with_line_notes (from, to, after) | |
2993 | rtx from, to, after; | |
2994 | { | |
2995 | rtx from_line = find_line_note (from); | |
2996 | rtx after_line = find_line_note (after); | |
2997 | ||
2998 | reorder_insns (from, to, after); | |
2999 | ||
3000 | if (from_line == after_line) | |
3001 | return; | |
3002 | ||
3003 | if (from_line) | |
3004 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3005 | NOTE_LINE_NUMBER (from_line), | |
3006 | after); | |
3007 | if (after_line) | |
3008 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3009 | NOTE_LINE_NUMBER (after_line), | |
3010 | to); | |
3011 | } | |
90b89d2c | 3012 | |
0a78547b | 3013 | /* Remove unnecessary notes from the instruction stream. */ |
90b89d2c | 3014 | |
3015 | void | |
0a78547b | 3016 | remove_unnecessary_notes () |
90b89d2c | 3017 | { |
92cfc4a8 | 3018 | rtx block_stack = NULL_RTX; |
3019 | rtx eh_stack = NULL_RTX; | |
90b89d2c | 3020 | rtx insn; |
3021 | rtx next; | |
92cfc4a8 | 3022 | rtx tmp; |
90b89d2c | 3023 | |
f1ab82be | 3024 | /* We must not remove the first instruction in the function because |
3025 | the compiler depends on the first instruction being a note. */ | |
90b89d2c | 3026 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
3027 | { | |
3028 | /* Remember what's next. */ | |
3029 | next = NEXT_INSN (insn); | |
3030 | ||
3031 | /* We're only interested in notes. */ | |
3032 | if (GET_CODE (insn) != NOTE) | |
3033 | continue; | |
3034 | ||
92cfc4a8 | 3035 | switch (NOTE_LINE_NUMBER (insn)) |
5846cb0f | 3036 | { |
92cfc4a8 | 3037 | case NOTE_INSN_DELETED: |
3038 | remove_insn (insn); | |
3039 | break; | |
3040 | ||
3041 | case NOTE_INSN_EH_REGION_BEG: | |
3042 | eh_stack = alloc_INSN_LIST (insn, eh_stack); | |
3043 | break; | |
3044 | ||
3045 | case NOTE_INSN_EH_REGION_END: | |
3046 | /* Too many end notes. */ | |
3047 | if (eh_stack == NULL_RTX) | |
3048 | abort (); | |
3049 | /* Mismatched nesting. */ | |
3050 | if (NOTE_EH_HANDLER (XEXP (eh_stack, 0)) != NOTE_EH_HANDLER (insn)) | |
3051 | abort (); | |
3052 | tmp = eh_stack; | |
3053 | eh_stack = XEXP (eh_stack, 1); | |
3054 | free_INSN_LIST_node (tmp); | |
3055 | break; | |
3056 | ||
3057 | case NOTE_INSN_BLOCK_BEG: | |
3058 | /* By now, all notes indicating lexical blocks should have | |
3059 | NOTE_BLOCK filled in. */ | |
3060 | if (NOTE_BLOCK (insn) == NULL_TREE) | |
3061 | abort (); | |
3062 | block_stack = alloc_INSN_LIST (insn, block_stack); | |
3063 | break; | |
3064 | ||
3065 | case NOTE_INSN_BLOCK_END: | |
3066 | /* Too many end notes. */ | |
3067 | if (block_stack == NULL_RTX) | |
3068 | abort (); | |
3069 | /* Mismatched nesting. */ | |
3070 | if (NOTE_BLOCK (XEXP (block_stack, 0)) != NOTE_BLOCK (insn)) | |
3071 | abort (); | |
3072 | tmp = block_stack; | |
3073 | block_stack = XEXP (block_stack, 1); | |
3074 | free_INSN_LIST_node (tmp); | |
3075 | ||
5846cb0f | 3076 | /* Scan back to see if there are any non-note instructions |
3077 | between INSN and the beginning of this block. If not, | |
3078 | then there is no PC range in the generated code that will | |
3079 | actually be in this block, so there's no point in | |
3080 | remembering the existence of the block. */ | |
92cfc4a8 | 3081 | for (tmp = PREV_INSN (insn); tmp ; tmp = PREV_INSN (tmp)) |
5846cb0f | 3082 | { |
3083 | /* This block contains a real instruction. Note that we | |
3084 | don't include labels; if the only thing in the block | |
3085 | is a label, then there are still no PC values that | |
3086 | lie within the block. */ | |
92cfc4a8 | 3087 | if (INSN_P (tmp)) |
5846cb0f | 3088 | break; |
3089 | ||
3090 | /* We're only interested in NOTEs. */ | |
92cfc4a8 | 3091 | if (GET_CODE (tmp) != NOTE) |
5846cb0f | 3092 | continue; |
3093 | ||
92cfc4a8 | 3094 | if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_BEG) |
5846cb0f | 3095 | { |
b29760a8 | 3096 | /* We just verified that this BLOCK matches us with |
3097 | the block_stack check above. Never delete the | |
3098 | BLOCK for the outermost scope of the function; we | |
3099 | can refer to names from that scope even if the | |
3100 | block notes are messed up. */ | |
3101 | if (! is_body_block (NOTE_BLOCK (insn)) | |
3102 | && (*debug_hooks->ignore_block) (NOTE_BLOCK (insn))) | |
e33dbbdf | 3103 | { |
92cfc4a8 | 3104 | remove_insn (tmp); |
e33dbbdf | 3105 | remove_insn (insn); |
3106 | } | |
5846cb0f | 3107 | break; |
3108 | } | |
92cfc4a8 | 3109 | else if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_END) |
5846cb0f | 3110 | /* There's a nested block. We need to leave the |
3111 | current block in place since otherwise the debugger | |
3112 | wouldn't be able to show symbols from our block in | |
3113 | the nested block. */ | |
3114 | break; | |
3115 | } | |
3116 | } | |
90b89d2c | 3117 | } |
92cfc4a8 | 3118 | |
3119 | /* Too many begin notes. */ | |
3120 | if (block_stack || eh_stack) | |
3121 | abort (); | |
90b89d2c | 3122 | } |
3123 | ||
15bbde2b | 3124 | \f |
3125 | /* Emit an insn of given code and pattern | |
3126 | at a specified place within the doubly-linked list. */ | |
3127 | ||
3128 | /* Make an instruction with body PATTERN | |
3129 | and output it before the instruction BEFORE. */ | |
3130 | ||
3131 | rtx | |
3132 | emit_insn_before (pattern, before) | |
3133 | register rtx pattern, before; | |
3134 | { | |
3135 | register rtx insn = before; | |
3136 | ||
3137 | if (GET_CODE (pattern) == SEQUENCE) | |
3138 | { | |
3139 | register int i; | |
3140 | ||
3141 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3142 | { | |
3143 | insn = XVECEXP (pattern, 0, i); | |
312de84d | 3144 | add_insn_before (insn, before); |
15bbde2b | 3145 | } |
15bbde2b | 3146 | } |
3147 | else | |
3148 | { | |
6a84e367 | 3149 | insn = make_insn_raw (pattern); |
312de84d | 3150 | add_insn_before (insn, before); |
15bbde2b | 3151 | } |
3152 | ||
3153 | return insn; | |
3154 | } | |
3155 | ||
3156 | /* Make an instruction with body PATTERN and code JUMP_INSN | |
3157 | and output it before the instruction BEFORE. */ | |
3158 | ||
3159 | rtx | |
3160 | emit_jump_insn_before (pattern, before) | |
3161 | register rtx pattern, before; | |
3162 | { | |
3163 | register rtx insn; | |
3164 | ||
3165 | if (GET_CODE (pattern) == SEQUENCE) | |
3166 | insn = emit_insn_before (pattern, before); | |
3167 | else | |
3168 | { | |
8f060628 | 3169 | insn = make_jump_insn_raw (pattern); |
312de84d | 3170 | add_insn_before (insn, before); |
15bbde2b | 3171 | } |
3172 | ||
3173 | return insn; | |
3174 | } | |
3175 | ||
3176 | /* Make an instruction with body PATTERN and code CALL_INSN | |
3177 | and output it before the instruction BEFORE. */ | |
3178 | ||
3179 | rtx | |
3180 | emit_call_insn_before (pattern, before) | |
3181 | register rtx pattern, before; | |
3182 | { | |
6e911104 | 3183 | register rtx insn; |
3184 | ||
3185 | if (GET_CODE (pattern) == SEQUENCE) | |
3186 | insn = emit_insn_before (pattern, before); | |
3187 | else | |
3188 | { | |
3189 | insn = make_call_insn_raw (pattern); | |
312de84d | 3190 | add_insn_before (insn, before); |
6e911104 | 3191 | PUT_CODE (insn, CALL_INSN); |
3192 | } | |
3193 | ||
15bbde2b | 3194 | return insn; |
3195 | } | |
3196 | ||
3197 | /* Make an insn of code BARRIER | |
71caadc0 | 3198 | and output it before the insn BEFORE. */ |
15bbde2b | 3199 | |
3200 | rtx | |
3201 | emit_barrier_before (before) | |
3202 | register rtx before; | |
3203 | { | |
3204 | register rtx insn = rtx_alloc (BARRIER); | |
3205 | ||
3206 | INSN_UID (insn) = cur_insn_uid++; | |
3207 | ||
312de84d | 3208 | add_insn_before (insn, before); |
15bbde2b | 3209 | return insn; |
3210 | } | |
3211 | ||
71caadc0 | 3212 | /* Emit the label LABEL before the insn BEFORE. */ |
3213 | ||
3214 | rtx | |
3215 | emit_label_before (label, before) | |
3216 | rtx label, before; | |
3217 | { | |
3218 | /* This can be called twice for the same label as a result of the | |
3219 | confusion that follows a syntax error! So make it harmless. */ | |
3220 | if (INSN_UID (label) == 0) | |
3221 | { | |
3222 | INSN_UID (label) = cur_insn_uid++; | |
3223 | add_insn_before (label, before); | |
3224 | } | |
3225 | ||
3226 | return label; | |
3227 | } | |
3228 | ||
15bbde2b | 3229 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
3230 | ||
3231 | rtx | |
3232 | emit_note_before (subtype, before) | |
3233 | int subtype; | |
3234 | rtx before; | |
3235 | { | |
3236 | register rtx note = rtx_alloc (NOTE); | |
3237 | INSN_UID (note) = cur_insn_uid++; | |
3238 | NOTE_SOURCE_FILE (note) = 0; | |
3239 | NOTE_LINE_NUMBER (note) = subtype; | |
3240 | ||
312de84d | 3241 | add_insn_before (note, before); |
15bbde2b | 3242 | return note; |
3243 | } | |
3244 | \f | |
3245 | /* Make an insn of code INSN with body PATTERN | |
3246 | and output it after the insn AFTER. */ | |
3247 | ||
3248 | rtx | |
3249 | emit_insn_after (pattern, after) | |
3250 | register rtx pattern, after; | |
3251 | { | |
3252 | register rtx insn = after; | |
3253 | ||
3254 | if (GET_CODE (pattern) == SEQUENCE) | |
3255 | { | |
3256 | register int i; | |
3257 | ||
3258 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3259 | { | |
3260 | insn = XVECEXP (pattern, 0, i); | |
3261 | add_insn_after (insn, after); | |
3262 | after = insn; | |
3263 | } | |
15bbde2b | 3264 | } |
3265 | else | |
3266 | { | |
6a84e367 | 3267 | insn = make_insn_raw (pattern); |
15bbde2b | 3268 | add_insn_after (insn, after); |
3269 | } | |
3270 | ||
3271 | return insn; | |
3272 | } | |
3273 | ||
1bea98fb | 3274 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
3275 | as to act as if this insn were at FROM. */ | |
3276 | ||
3277 | void | |
3278 | emit_insn_after_with_line_notes (pattern, after, from) | |
3279 | rtx pattern, after, from; | |
3280 | { | |
3281 | rtx from_line = find_line_note (from); | |
3282 | rtx after_line = find_line_note (after); | |
3283 | rtx insn = emit_insn_after (pattern, after); | |
3284 | ||
3285 | if (from_line) | |
3286 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3287 | NOTE_LINE_NUMBER (from_line), | |
3288 | after); | |
3289 | ||
3290 | if (after_line) | |
3291 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3292 | NOTE_LINE_NUMBER (after_line), | |
3293 | insn); | |
3294 | } | |
3295 | ||
15bbde2b | 3296 | /* Make an insn of code JUMP_INSN with body PATTERN |
3297 | and output it after the insn AFTER. */ | |
3298 | ||
3299 | rtx | |
3300 | emit_jump_insn_after (pattern, after) | |
3301 | register rtx pattern, after; | |
3302 | { | |
3303 | register rtx insn; | |
3304 | ||
3305 | if (GET_CODE (pattern) == SEQUENCE) | |
3306 | insn = emit_insn_after (pattern, after); | |
3307 | else | |
3308 | { | |
8f060628 | 3309 | insn = make_jump_insn_raw (pattern); |
15bbde2b | 3310 | add_insn_after (insn, after); |
3311 | } | |
3312 | ||
3313 | return insn; | |
3314 | } | |
3315 | ||
3316 | /* Make an insn of code BARRIER | |
3317 | and output it after the insn AFTER. */ | |
3318 | ||
3319 | rtx | |
3320 | emit_barrier_after (after) | |
3321 | register rtx after; | |
3322 | { | |
3323 | register rtx insn = rtx_alloc (BARRIER); | |
3324 | ||
3325 | INSN_UID (insn) = cur_insn_uid++; | |
3326 | ||
3327 | add_insn_after (insn, after); | |
3328 | return insn; | |
3329 | } | |
3330 | ||
3331 | /* Emit the label LABEL after the insn AFTER. */ | |
3332 | ||
3333 | rtx | |
3334 | emit_label_after (label, after) | |
3335 | rtx label, after; | |
3336 | { | |
3337 | /* This can be called twice for the same label | |
3338 | as a result of the confusion that follows a syntax error! | |
3339 | So make it harmless. */ | |
3340 | if (INSN_UID (label) == 0) | |
3341 | { | |
3342 | INSN_UID (label) = cur_insn_uid++; | |
3343 | add_insn_after (label, after); | |
3344 | } | |
3345 | ||
3346 | return label; | |
3347 | } | |
3348 | ||
3349 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3350 | ||
3351 | rtx | |
3352 | emit_note_after (subtype, after) | |
3353 | int subtype; | |
3354 | rtx after; | |
3355 | { | |
3356 | register rtx note = rtx_alloc (NOTE); | |
3357 | INSN_UID (note) = cur_insn_uid++; | |
3358 | NOTE_SOURCE_FILE (note) = 0; | |
3359 | NOTE_LINE_NUMBER (note) = subtype; | |
3360 | add_insn_after (note, after); | |
3361 | return note; | |
3362 | } | |
3363 | ||
3364 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3365 | ||
3366 | rtx | |
3367 | emit_line_note_after (file, line, after) | |
9a356c3c | 3368 | const char *file; |
15bbde2b | 3369 | int line; |
3370 | rtx after; | |
3371 | { | |
3372 | register rtx note; | |
3373 | ||
3374 | if (no_line_numbers && line > 0) | |
3375 | { | |
3376 | cur_insn_uid++; | |
3377 | return 0; | |
3378 | } | |
3379 | ||
3380 | note = rtx_alloc (NOTE); | |
3381 | INSN_UID (note) = cur_insn_uid++; | |
3382 | NOTE_SOURCE_FILE (note) = file; | |
3383 | NOTE_LINE_NUMBER (note) = line; | |
3384 | add_insn_after (note, after); | |
3385 | return note; | |
3386 | } | |
3387 | \f | |
3388 | /* Make an insn of code INSN with pattern PATTERN | |
3389 | and add it to the end of the doubly-linked list. | |
3390 | If PATTERN is a SEQUENCE, take the elements of it | |
3391 | and emit an insn for each element. | |
3392 | ||
3393 | Returns the last insn emitted. */ | |
3394 | ||
3395 | rtx | |
3396 | emit_insn (pattern) | |
3397 | rtx pattern; | |
3398 | { | |
3399 | rtx insn = last_insn; | |
3400 | ||
3401 | if (GET_CODE (pattern) == SEQUENCE) | |
3402 | { | |
3403 | register int i; | |
3404 | ||
3405 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3406 | { | |
3407 | insn = XVECEXP (pattern, 0, i); | |
3408 | add_insn (insn); | |
3409 | } | |
15bbde2b | 3410 | } |
3411 | else | |
3412 | { | |
6a84e367 | 3413 | insn = make_insn_raw (pattern); |
15bbde2b | 3414 | add_insn (insn); |
3415 | } | |
3416 | ||
3417 | return insn; | |
3418 | } | |
3419 | ||
3420 | /* Emit the insns in a chain starting with INSN. | |
3421 | Return the last insn emitted. */ | |
3422 | ||
3423 | rtx | |
3424 | emit_insns (insn) | |
3425 | rtx insn; | |
3426 | { | |
3427 | rtx last = 0; | |
3428 | ||
3429 | while (insn) | |
3430 | { | |
3431 | rtx next = NEXT_INSN (insn); | |
3432 | add_insn (insn); | |
3433 | last = insn; | |
3434 | insn = next; | |
3435 | } | |
3436 | ||
3437 | return last; | |
3438 | } | |
3439 | ||
3440 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3441 | the insn BEFORE. Return the last insn emitted. */ | |
3442 | ||
3443 | rtx | |
3444 | emit_insns_before (insn, before) | |
3445 | rtx insn; | |
3446 | rtx before; | |
3447 | { | |
3448 | rtx last = 0; | |
3449 | ||
3450 | while (insn) | |
3451 | { | |
3452 | rtx next = NEXT_INSN (insn); | |
312de84d | 3453 | add_insn_before (insn, before); |
15bbde2b | 3454 | last = insn; |
3455 | insn = next; | |
3456 | } | |
3457 | ||
3458 | return last; | |
3459 | } | |
3460 | ||
b36b07d8 | 3461 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3462 | the insn AFTER. Return the last insn emitted. */ | |
3463 | ||
3464 | rtx | |
3465 | emit_insns_after (first, after) | |
3466 | register rtx first; | |
3467 | register rtx after; | |
3468 | { | |
3469 | register rtx last; | |
3470 | register rtx after_after; | |
9dda7915 | 3471 | basic_block bb; |
b36b07d8 | 3472 | |
3473 | if (!after) | |
3474 | abort (); | |
3475 | ||
3476 | if (!first) | |
3477 | return first; | |
3478 | ||
9dda7915 | 3479 | if (basic_block_for_insn |
3480 | && (unsigned int)INSN_UID (after) < basic_block_for_insn->num_elements | |
3481 | && (bb = BLOCK_FOR_INSN (after))) | |
3482 | { | |
3483 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3484 | set_block_for_insn (last, bb); | |
3485 | set_block_for_insn (last, bb); | |
3486 | if (bb->end == after) | |
3487 | bb->end = last; | |
3488 | } | |
3489 | else | |
3490 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3491 | continue; | |
b36b07d8 | 3492 | |
3493 | after_after = NEXT_INSN (after); | |
3494 | ||
3495 | NEXT_INSN (after) = first; | |
3496 | PREV_INSN (first) = after; | |
3497 | NEXT_INSN (last) = after_after; | |
3498 | if (after_after) | |
3499 | PREV_INSN (after_after) = last; | |
3500 | ||
0c905390 | 3501 | if (after == last_insn) |
3502 | last_insn = last; | |
b36b07d8 | 3503 | return last; |
3504 | } | |
3505 | ||
15bbde2b | 3506 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3507 | and add it to the end of the doubly-linked list. */ | |
3508 | ||
3509 | rtx | |
3510 | emit_jump_insn (pattern) | |
3511 | rtx pattern; | |
3512 | { | |
3513 | if (GET_CODE (pattern) == SEQUENCE) | |
3514 | return emit_insn (pattern); | |
3515 | else | |
3516 | { | |
8f060628 | 3517 | register rtx insn = make_jump_insn_raw (pattern); |
15bbde2b | 3518 | add_insn (insn); |
3519 | return insn; | |
3520 | } | |
3521 | } | |
3522 | ||
3523 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3524 | and add it to the end of the doubly-linked list. */ | |
3525 | ||
3526 | rtx | |
3527 | emit_call_insn (pattern) | |
3528 | rtx pattern; | |
3529 | { | |
3530 | if (GET_CODE (pattern) == SEQUENCE) | |
3531 | return emit_insn (pattern); | |
3532 | else | |
3533 | { | |
6e911104 | 3534 | register rtx insn = make_call_insn_raw (pattern); |
15bbde2b | 3535 | add_insn (insn); |
3536 | PUT_CODE (insn, CALL_INSN); | |
3537 | return insn; | |
3538 | } | |
3539 | } | |
3540 | ||
3541 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3542 | ||
3543 | rtx | |
3544 | emit_label (label) | |
3545 | rtx label; | |
3546 | { | |
3547 | /* This can be called twice for the same label | |
3548 | as a result of the confusion that follows a syntax error! | |
3549 | So make it harmless. */ | |
3550 | if (INSN_UID (label) == 0) | |
3551 | { | |
3552 | INSN_UID (label) = cur_insn_uid++; | |
3553 | add_insn (label); | |
3554 | } | |
3555 | return label; | |
3556 | } | |
3557 | ||
3558 | /* Make an insn of code BARRIER | |
3559 | and add it to the end of the doubly-linked list. */ | |
3560 | ||
3561 | rtx | |
3562 | emit_barrier () | |
3563 | { | |
3564 | register rtx barrier = rtx_alloc (BARRIER); | |
3565 | INSN_UID (barrier) = cur_insn_uid++; | |
3566 | add_insn (barrier); | |
3567 | return barrier; | |
3568 | } | |
3569 | ||
3570 | /* Make an insn of code NOTE | |
3571 | with data-fields specified by FILE and LINE | |
3572 | and add it to the end of the doubly-linked list, | |
3573 | but only if line-numbers are desired for debugging info. */ | |
3574 | ||
3575 | rtx | |
3576 | emit_line_note (file, line) | |
9a356c3c | 3577 | const char *file; |
15bbde2b | 3578 | int line; |
3579 | { | |
21b005ed | 3580 | set_file_and_line_for_stmt (file, line); |
15bbde2b | 3581 | |
3582 | #if 0 | |
3583 | if (no_line_numbers) | |
3584 | return 0; | |
3585 | #endif | |
3586 | ||
3587 | return emit_note (file, line); | |
3588 | } | |
3589 | ||
3590 | /* Make an insn of code NOTE | |
3591 | with data-fields specified by FILE and LINE | |
3592 | and add it to the end of the doubly-linked list. | |
3593 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3594 | ||
3595 | rtx | |
3596 | emit_note (file, line) | |
9a356c3c | 3597 | const char *file; |
15bbde2b | 3598 | int line; |
3599 | { | |
3600 | register rtx note; | |
3601 | ||
3602 | if (line > 0) | |
3603 | { | |
3604 | if (file && last_filename && !strcmp (file, last_filename) | |
3605 | && line == last_linenum) | |
3606 | return 0; | |
3607 | last_filename = file; | |
3608 | last_linenum = line; | |
3609 | } | |
3610 | ||
3611 | if (no_line_numbers && line > 0) | |
3612 | { | |
3613 | cur_insn_uid++; | |
3614 | return 0; | |
3615 | } | |
3616 | ||
3617 | note = rtx_alloc (NOTE); | |
3618 | INSN_UID (note) = cur_insn_uid++; | |
3619 | NOTE_SOURCE_FILE (note) = file; | |
3620 | NOTE_LINE_NUMBER (note) = line; | |
3621 | add_insn (note); | |
3622 | return note; | |
3623 | } | |
3624 | ||
8d54063f | 3625 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
15bbde2b | 3626 | |
3627 | rtx | |
3628 | emit_line_note_force (file, line) | |
9a356c3c | 3629 | const char *file; |
15bbde2b | 3630 | int line; |
3631 | { | |
3632 | last_linenum = -1; | |
3633 | return emit_line_note (file, line); | |
3634 | } | |
3635 | ||
3636 | /* Cause next statement to emit a line note even if the line number | |
3637 | has not changed. This is used at the beginning of a function. */ | |
3638 | ||
3639 | void | |
3640 | force_next_line_note () | |
3641 | { | |
3642 | last_linenum = -1; | |
3643 | } | |
f1934a33 | 3644 | |
3645 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
6312a35e | 3646 | note of this type already exists, remove it first. */ |
f1934a33 | 3647 | |
d823ba47 | 3648 | void |
f1934a33 | 3649 | set_unique_reg_note (insn, kind, datum) |
3650 | rtx insn; | |
3651 | enum reg_note kind; | |
3652 | rtx datum; | |
3653 | { | |
3654 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3655 | ||
3656 | /* First remove the note if there already is one. */ | |
d823ba47 | 3657 | if (note) |
f1934a33 | 3658 | remove_note (insn, note); |
3659 | ||
3660 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3661 | } | |
15bbde2b | 3662 | \f |
3663 | /* Return an indication of which type of insn should have X as a body. | |
3664 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3665 | ||
3666 | enum rtx_code | |
3667 | classify_insn (x) | |
3668 | rtx x; | |
3669 | { | |
3670 | if (GET_CODE (x) == CODE_LABEL) | |
3671 | return CODE_LABEL; | |
3672 | if (GET_CODE (x) == CALL) | |
3673 | return CALL_INSN; | |
3674 | if (GET_CODE (x) == RETURN) | |
3675 | return JUMP_INSN; | |
3676 | if (GET_CODE (x) == SET) | |
3677 | { | |
3678 | if (SET_DEST (x) == pc_rtx) | |
3679 | return JUMP_INSN; | |
3680 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3681 | return CALL_INSN; | |
3682 | else | |
3683 | return INSN; | |
3684 | } | |
3685 | if (GET_CODE (x) == PARALLEL) | |
3686 | { | |
3687 | register int j; | |
3688 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3689 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3690 | return CALL_INSN; | |
3691 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3692 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3693 | return JUMP_INSN; | |
3694 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3695 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3696 | return CALL_INSN; | |
3697 | } | |
3698 | return INSN; | |
3699 | } | |
3700 | ||
3701 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3702 | If X is a label, it is simply added into the insn chain. */ | |
3703 | ||
3704 | rtx | |
3705 | emit (x) | |
3706 | rtx x; | |
3707 | { | |
3708 | enum rtx_code code = classify_insn (x); | |
3709 | ||
3710 | if (code == CODE_LABEL) | |
3711 | return emit_label (x); | |
3712 | else if (code == INSN) | |
3713 | return emit_insn (x); | |
3714 | else if (code == JUMP_INSN) | |
3715 | { | |
3716 | register rtx insn = emit_jump_insn (x); | |
b2816317 | 3717 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
15bbde2b | 3718 | return emit_barrier (); |
3719 | return insn; | |
3720 | } | |
3721 | else if (code == CALL_INSN) | |
3722 | return emit_call_insn (x); | |
3723 | else | |
3724 | abort (); | |
3725 | } | |
3726 | \f | |
b49854c6 | 3727 | /* Begin emitting insns to a sequence which can be packaged in an |
3728 | RTL_EXPR. If this sequence will contain something that might cause | |
3729 | the compiler to pop arguments to function calls (because those | |
3730 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3731 | details), use do_pending_stack_adjust before calling this function. | |
3732 | That will ensure that the deferred pops are not accidentally | |
9588521d | 3733 | emitted in the middle of this sequence. */ |
15bbde2b | 3734 | |
3735 | void | |
3736 | start_sequence () | |
3737 | { | |
3738 | struct sequence_stack *tem; | |
3739 | ||
1bfd55c5 | 3740 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
15bbde2b | 3741 | |
0a893c29 | 3742 | tem->next = seq_stack; |
15bbde2b | 3743 | tem->first = first_insn; |
3744 | tem->last = last_insn; | |
961819fb | 3745 | tem->sequence_rtl_expr = seq_rtl_expr; |
15bbde2b | 3746 | |
0a893c29 | 3747 | seq_stack = tem; |
15bbde2b | 3748 | |
3749 | first_insn = 0; | |
3750 | last_insn = 0; | |
3751 | } | |
3752 | ||
961819fb | 3753 | /* Similarly, but indicate that this sequence will be placed in T, an |
3754 | RTL_EXPR. See the documentation for start_sequence for more | |
3755 | information about how to use this function. */ | |
3756 | ||
3757 | void | |
3758 | start_sequence_for_rtl_expr (t) | |
3759 | tree t; | |
3760 | { | |
3761 | start_sequence (); | |
3762 | ||
3763 | seq_rtl_expr = t; | |
3764 | } | |
3765 | ||
b49854c6 | 3766 | /* Set up the insn chain starting with FIRST as the current sequence, |
3767 | saving the previously current one. See the documentation for | |
3768 | start_sequence for more information about how to use this function. */ | |
15bbde2b | 3769 | |
3770 | void | |
3771 | push_to_sequence (first) | |
3772 | rtx first; | |
3773 | { | |
3774 | rtx last; | |
3775 | ||
3776 | start_sequence (); | |
3777 | ||
3778 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3779 | ||
3780 | first_insn = first; | |
3781 | last_insn = last; | |
3782 | } | |
3783 | ||
78147e84 | 3784 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3785 | ||
3786 | void | |
3787 | push_to_full_sequence (first, last) | |
3788 | rtx first, last; | |
3789 | { | |
3790 | start_sequence (); | |
3791 | first_insn = first; | |
3792 | last_insn = last; | |
3793 | /* We really should have the end of the insn chain here. */ | |
3794 | if (last && NEXT_INSN (last)) | |
3795 | abort (); | |
3796 | } | |
3797 | ||
ab74c92f | 3798 | /* Set up the outer-level insn chain |
3799 | as the current sequence, saving the previously current one. */ | |
3800 | ||
3801 | void | |
3802 | push_topmost_sequence () | |
3803 | { | |
2041cfd9 | 3804 | struct sequence_stack *stack, *top = NULL; |
ab74c92f | 3805 | |
3806 | start_sequence (); | |
3807 | ||
0a893c29 | 3808 | for (stack = seq_stack; stack; stack = stack->next) |
ab74c92f | 3809 | top = stack; |
3810 | ||
3811 | first_insn = top->first; | |
3812 | last_insn = top->last; | |
961819fb | 3813 | seq_rtl_expr = top->sequence_rtl_expr; |
ab74c92f | 3814 | } |
3815 | ||
3816 | /* After emitting to the outer-level insn chain, update the outer-level | |
3817 | insn chain, and restore the previous saved state. */ | |
3818 | ||
3819 | void | |
3820 | pop_topmost_sequence () | |
3821 | { | |
2041cfd9 | 3822 | struct sequence_stack *stack, *top = NULL; |
ab74c92f | 3823 | |
0a893c29 | 3824 | for (stack = seq_stack; stack; stack = stack->next) |
ab74c92f | 3825 | top = stack; |
3826 | ||
3827 | top->first = first_insn; | |
3828 | top->last = last_insn; | |
961819fb | 3829 | /* ??? Why don't we save seq_rtl_expr here? */ |
ab74c92f | 3830 | |
3831 | end_sequence (); | |
3832 | } | |
3833 | ||
15bbde2b | 3834 | /* After emitting to a sequence, restore previous saved state. |
3835 | ||
b49854c6 | 3836 | To get the contents of the sequence just made, you must call |
d823ba47 | 3837 | `gen_sequence' *before* calling here. |
b49854c6 | 3838 | |
3839 | If the compiler might have deferred popping arguments while | |
3840 | generating this sequence, and this sequence will not be immediately | |
3841 | inserted into the instruction stream, use do_pending_stack_adjust | |
3842 | before calling gen_sequence. That will ensure that the deferred | |
3843 | pops are inserted into this sequence, and not into some random | |
3844 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3845 | information about deferred popping of arguments. */ | |
15bbde2b | 3846 | |
3847 | void | |
3848 | end_sequence () | |
3849 | { | |
0a893c29 | 3850 | struct sequence_stack *tem = seq_stack; |
15bbde2b | 3851 | |
3852 | first_insn = tem->first; | |
3853 | last_insn = tem->last; | |
961819fb | 3854 | seq_rtl_expr = tem->sequence_rtl_expr; |
0a893c29 | 3855 | seq_stack = tem->next; |
15bbde2b | 3856 | |
1bfd55c5 | 3857 | free (tem); |
15bbde2b | 3858 | } |
3859 | ||
78147e84 | 3860 | /* This works like end_sequence, but records the old sequence in FIRST |
3861 | and LAST. */ | |
3862 | ||
3863 | void | |
3864 | end_full_sequence (first, last) | |
3865 | rtx *first, *last; | |
3866 | { | |
3867 | *first = first_insn; | |
3868 | *last = last_insn; | |
3869 | end_sequence(); | |
3870 | } | |
3871 | ||
15bbde2b | 3872 | /* Return 1 if currently emitting into a sequence. */ |
3873 | ||
3874 | int | |
3875 | in_sequence_p () | |
3876 | { | |
0a893c29 | 3877 | return seq_stack != 0; |
15bbde2b | 3878 | } |
3879 | ||
3880 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3881 | to the current sequence. | |
3882 | ||
3883 | This is how the gen_... function from a DEFINE_EXPAND | |
3884 | constructs the SEQUENCE that it returns. */ | |
3885 | ||
3886 | rtx | |
3887 | gen_sequence () | |
3888 | { | |
3889 | rtx result; | |
3890 | rtx tem; | |
15bbde2b | 3891 | int i; |
3892 | int len; | |
3893 | ||
3894 | /* Count the insns in the chain. */ | |
3895 | len = 0; | |
3896 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3897 | len++; | |
3898 | ||
88bbcaa6 | 3899 | /* If only one insn, return it rather than a SEQUENCE. |
15bbde2b | 3900 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
d823ba47 | 3901 | the case of an empty list.) |
88bbcaa6 | 3902 | We only return the pattern of an insn if its code is INSN and it |
3903 | has no notes. This ensures that no information gets lost. */ | |
15bbde2b | 3904 | if (len == 1 |
447a9eb9 | 3905 | && ! RTX_FRAME_RELATED_P (first_insn) |
88bbcaa6 | 3906 | && GET_CODE (first_insn) == INSN |
6312a35e | 3907 | /* Don't throw away any reg notes. */ |
88bbcaa6 | 3908 | && REG_NOTES (first_insn) == 0) |
d7c47c0e | 3909 | return PATTERN (first_insn); |
15bbde2b | 3910 | |
d7c47c0e | 3911 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
15bbde2b | 3912 | |
3913 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3914 | XVECEXP (result, 0, i) = tem; | |
3915 | ||
3916 | return result; | |
3917 | } | |
3918 | \f | |
02ebfa52 | 3919 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3920 | ||
3921 | void | |
0a893c29 | 3922 | init_virtual_regs (es) |
3923 | struct emit_status *es; | |
02ebfa52 | 3924 | { |
0a893c29 | 3925 | rtx *ptr = es->x_regno_reg_rtx; |
3926 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3927 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3928 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3929 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3930 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3931 | } | |
3932 | ||
3933 | void | |
3934 | clear_emit_caches () | |
3935 | { | |
3936 | int i; | |
3937 | ||
3938 | /* Clear the start_sequence/gen_sequence cache. */ | |
0a893c29 | 3939 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3940 | sequence_result[i] = 0; | |
3941 | free_insn = 0; | |
02ebfa52 | 3942 | } |
928d57e3 | 3943 | \f |
3944 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3945 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3946 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3947 | static int copy_insn_n_scratches; | |
3948 | ||
3949 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3950 | copied an ASM_OPERANDS. | |
3951 | In that case, it is the original input-operand vector. */ | |
3952 | static rtvec orig_asm_operands_vector; | |
3953 | ||
3954 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3955 | copied an ASM_OPERANDS. | |
3956 | In that case, it is the copied input-operand vector. */ | |
3957 | static rtvec copy_asm_operands_vector; | |
3958 | ||
3959 | /* Likewise for the constraints vector. */ | |
3960 | static rtvec orig_asm_constraints_vector; | |
3961 | static rtvec copy_asm_constraints_vector; | |
3962 | ||
3963 | /* Recursively create a new copy of an rtx for copy_insn. | |
3964 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3965 | ASM_OPERANDs properly. | |
3966 | Normally, this function is not used directly; use copy_insn as front end. | |
3967 | However, you could first copy an insn pattern with copy_insn and then use | |
3968 | this function afterwards to properly copy any REG_NOTEs containing | |
3969 | SCRATCHes. */ | |
3970 | ||
3971 | rtx | |
3972 | copy_insn_1 (orig) | |
3973 | register rtx orig; | |
3974 | { | |
3975 | register rtx copy; | |
3976 | register int i, j; | |
3977 | register RTX_CODE code; | |
90bf951c | 3978 | register const char *format_ptr; |
928d57e3 | 3979 | |
3980 | code = GET_CODE (orig); | |
3981 | ||
3982 | switch (code) | |
3983 | { | |
3984 | case REG: | |
3985 | case QUEUED: | |
3986 | case CONST_INT: | |
3987 | case CONST_DOUBLE: | |
3988 | case SYMBOL_REF: | |
3989 | case CODE_LABEL: | |
3990 | case PC: | |
3991 | case CC0: | |
3992 | case ADDRESSOF: | |
3993 | return orig; | |
3994 | ||
3995 | case SCRATCH: | |
3996 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3997 | if (copy_insn_scratch_in[i] == orig) | |
3998 | return copy_insn_scratch_out[i]; | |
3999 | break; | |
4000 | ||
4001 | case CONST: | |
4002 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
4003 | a LABEL_REF, it isn't sharable. */ | |
4004 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
4005 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
4006 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
4007 | return orig; | |
4008 | break; | |
d823ba47 | 4009 | |
928d57e3 | 4010 | /* A MEM with a constant address is not sharable. The problem is that |
4011 | the constant address may need to be reloaded. If the mem is shared, | |
4012 | then reloading one copy of this mem will cause all copies to appear | |
4013 | to have been reloaded. */ | |
4014 | ||
4015 | default: | |
4016 | break; | |
4017 | } | |
4018 | ||
4019 | copy = rtx_alloc (code); | |
4020 | ||
4021 | /* Copy the various flags, and other information. We assume that | |
4022 | all fields need copying, and then clear the fields that should | |
4023 | not be copied. That is the sensible default behavior, and forces | |
4024 | us to explicitly document why we are *not* copying a flag. */ | |
4025 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
4026 | ||
4027 | /* We do not copy the USED flag, which is used as a mark bit during | |
4028 | walks over the RTL. */ | |
4029 | copy->used = 0; | |
4030 | ||
4031 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
4032 | if (GET_RTX_CLASS (code) == 'i') | |
4033 | { | |
4034 | copy->jump = 0; | |
4035 | copy->call = 0; | |
4036 | copy->frame_related = 0; | |
4037 | } | |
d823ba47 | 4038 | |
928d57e3 | 4039 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
4040 | ||
4041 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
4042 | { | |
d925550d | 4043 | copy->fld[i] = orig->fld[i]; |
928d57e3 | 4044 | switch (*format_ptr++) |
4045 | { | |
4046 | case 'e': | |
928d57e3 | 4047 | if (XEXP (orig, i) != NULL) |
4048 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
4049 | break; | |
4050 | ||
928d57e3 | 4051 | case 'E': |
4052 | case 'V': | |
928d57e3 | 4053 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
4054 | XVEC (copy, i) = copy_asm_constraints_vector; | |
4055 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
4056 | XVEC (copy, i) = copy_asm_operands_vector; | |
4057 | else if (XVEC (orig, i) != NULL) | |
4058 | { | |
4059 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
4060 | for (j = 0; j < XVECLEN (copy, i); j++) | |
4061 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
4062 | } | |
4063 | break; | |
4064 | ||
928d57e3 | 4065 | case 't': |
928d57e3 | 4066 | case 'w': |
928d57e3 | 4067 | case 'i': |
928d57e3 | 4068 | case 's': |
4069 | case 'S': | |
d925550d | 4070 | case 'u': |
4071 | case '0': | |
4072 | /* These are left unchanged. */ | |
928d57e3 | 4073 | break; |
4074 | ||
4075 | default: | |
4076 | abort (); | |
4077 | } | |
4078 | } | |
4079 | ||
4080 | if (code == SCRATCH) | |
4081 | { | |
4082 | i = copy_insn_n_scratches++; | |
4083 | if (i >= MAX_RECOG_OPERANDS) | |
4084 | abort (); | |
4085 | copy_insn_scratch_in[i] = orig; | |
4086 | copy_insn_scratch_out[i] = copy; | |
4087 | } | |
4088 | else if (code == ASM_OPERANDS) | |
4089 | { | |
d91f2122 | 4090 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
4091 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
4092 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
4093 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
928d57e3 | 4094 | } |
4095 | ||
4096 | return copy; | |
4097 | } | |
4098 | ||
4099 | /* Create a new copy of an rtx. | |
4100 | This function differs from copy_rtx in that it handles SCRATCHes and | |
4101 | ASM_OPERANDs properly. | |
4102 | INSN doesn't really have to be a full INSN; it could be just the | |
4103 | pattern. */ | |
4104 | rtx | |
4105 | copy_insn (insn) | |
4106 | rtx insn; | |
4107 | { | |
4108 | copy_insn_n_scratches = 0; | |
4109 | orig_asm_operands_vector = 0; | |
4110 | orig_asm_constraints_vector = 0; | |
4111 | copy_asm_operands_vector = 0; | |
4112 | copy_asm_constraints_vector = 0; | |
4113 | return copy_insn_1 (insn); | |
4114 | } | |
02ebfa52 | 4115 | |
15bbde2b | 4116 | /* Initialize data structures and variables in this file |
4117 | before generating rtl for each function. */ | |
4118 | ||
4119 | void | |
4120 | init_emit () | |
4121 | { | |
08513b52 | 4122 | struct function *f = cfun; |
15bbde2b | 4123 | |
0a893c29 | 4124 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
15bbde2b | 4125 | first_insn = NULL; |
4126 | last_insn = NULL; | |
961819fb | 4127 | seq_rtl_expr = NULL; |
15bbde2b | 4128 | cur_insn_uid = 1; |
4129 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
4130 | last_linenum = 0; | |
4131 | last_filename = 0; | |
4132 | first_label_num = label_num; | |
4133 | last_label_num = 0; | |
0a893c29 | 4134 | seq_stack = NULL; |
15bbde2b | 4135 | |
0a893c29 | 4136 | clear_emit_caches (); |
15bbde2b | 4137 | |
4138 | /* Init the tables that describe all the pseudo regs. */ | |
4139 | ||
e61a0a7f | 4140 | f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
15bbde2b | 4141 | |
0a893c29 | 4142 | f->emit->regno_pointer_align |
e61a0a7f | 4143 | = (unsigned char *) xcalloc (f->emit->regno_pointer_align_length, |
4491f79f | 4144 | sizeof (unsigned char)); |
d4c332ff | 4145 | |
d823ba47 | 4146 | regno_reg_rtx |
e61a0a7f | 4147 | = (rtx *) xcalloc (f->emit->regno_pointer_align_length * sizeof (rtx), |
1bfd55c5 | 4148 | sizeof (rtx)); |
15bbde2b | 4149 | |
4150 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
0a893c29 | 4151 | init_virtual_regs (f->emit); |
888e0d33 | 4152 | |
4153 | /* Indicate that the virtual registers and stack locations are | |
4154 | all pointers. */ | |
e61a0a7f | 4155 | REG_POINTER (stack_pointer_rtx) = 1; |
4156 | REG_POINTER (frame_pointer_rtx) = 1; | |
4157 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
4158 | REG_POINTER (arg_pointer_rtx) = 1; | |
888e0d33 | 4159 | |
e61a0a7f | 4160 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
4161 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
4162 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
4163 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
4164 | REG_POINTER (virtual_cfa_rtx) = 1; | |
89525da0 | 4165 | |
d4c332ff | 4166 | #ifdef STACK_BOUNDARY |
80909c64 | 4167 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
4168 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
4169 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
4170 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
4171 | ||
4172 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
4173 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
4174 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
4175 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
4176 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
d4c332ff | 4177 | #endif |
4178 | ||
89525da0 | 4179 | #ifdef INIT_EXPANDERS |
4180 | INIT_EXPANDERS; | |
4181 | #endif | |
15bbde2b | 4182 | } |
4183 | ||
a7b0c170 | 4184 | /* Mark SS for GC. */ |
4185 | ||
4186 | static void | |
4187 | mark_sequence_stack (ss) | |
4188 | struct sequence_stack *ss; | |
4189 | { | |
4190 | while (ss) | |
4191 | { | |
4192 | ggc_mark_rtx (ss->first); | |
961819fb | 4193 | ggc_mark_tree (ss->sequence_rtl_expr); |
a7b0c170 | 4194 | ss = ss->next; |
4195 | } | |
4196 | } | |
4197 | ||
4198 | /* Mark ES for GC. */ | |
4199 | ||
4200 | void | |
3c3bb268 | 4201 | mark_emit_status (es) |
a7b0c170 | 4202 | struct emit_status *es; |
4203 | { | |
4204 | rtx *r; | |
4205 | int i; | |
4206 | ||
4207 | if (es == 0) | |
4208 | return; | |
4209 | ||
e61a0a7f | 4210 | for (i = es->regno_pointer_align_length, r = es->x_regno_reg_rtx; |
a7b0c170 | 4211 | i > 0; --i, ++r) |
4212 | ggc_mark_rtx (*r); | |
4213 | ||
4214 | mark_sequence_stack (es->sequence_stack); | |
961819fb | 4215 | ggc_mark_tree (es->sequence_rtl_expr); |
a7b0c170 | 4216 | ggc_mark_rtx (es->x_first_insn); |
4217 | } | |
4218 | ||
15bbde2b | 4219 | /* Create some permanent unique rtl objects shared between all functions. |
4220 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
4221 | ||
4222 | void | |
4223 | init_emit_once (line_numbers) | |
4224 | int line_numbers; | |
4225 | { | |
4226 | int i; | |
4227 | enum machine_mode mode; | |
9e042f31 | 4228 | enum machine_mode double_mode; |
15bbde2b | 4229 | |
77695070 | 4230 | /* Initialize the CONST_INT hash table. */ |
d823ba47 | 4231 | const_int_htab = htab_create (37, const_int_htab_hash, |
77695070 | 4232 | const_int_htab_eq, NULL); |
d823ba47 | 4233 | ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab), |
77695070 | 4234 | rtx_htab_mark); |
4235 | ||
15bbde2b | 4236 | no_line_numbers = ! line_numbers; |
4237 | ||
71d7daa2 | 4238 | /* Compute the word and byte modes. */ |
4239 | ||
4240 | byte_mode = VOIDmode; | |
4241 | word_mode = VOIDmode; | |
4242 | double_mode = VOIDmode; | |
4243 | ||
4244 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4245 | mode = GET_MODE_WIDER_MODE (mode)) | |
4246 | { | |
4247 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
4248 | && byte_mode == VOIDmode) | |
4249 | byte_mode = mode; | |
4250 | ||
4251 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
4252 | && word_mode == VOIDmode) | |
4253 | word_mode = mode; | |
4254 | } | |
4255 | ||
71d7daa2 | 4256 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; |
4257 | mode = GET_MODE_WIDER_MODE (mode)) | |
4258 | { | |
4259 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
4260 | && double_mode == VOIDmode) | |
4261 | double_mode = mode; | |
4262 | } | |
4263 | ||
4264 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
4265 | ||
57c097d5 | 4266 | /* Assign register numbers to the globally defined register rtx. |
4267 | This must be done at runtime because the register number field | |
4268 | is in a union and some compilers can't initialize unions. */ | |
4269 | ||
4270 | pc_rtx = gen_rtx (PC, VOIDmode); | |
4271 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
22cf44bc | 4272 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
4273 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
57c097d5 | 4274 | if (hard_frame_pointer_rtx == 0) |
d823ba47 | 4275 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, |
22cf44bc | 4276 | HARD_FRAME_POINTER_REGNUM); |
57c097d5 | 4277 | if (arg_pointer_rtx == 0) |
22cf44bc | 4278 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); |
d823ba47 | 4279 | virtual_incoming_args_rtx = |
22cf44bc | 4280 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); |
d823ba47 | 4281 | virtual_stack_vars_rtx = |
22cf44bc | 4282 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); |
d823ba47 | 4283 | virtual_stack_dynamic_rtx = |
22cf44bc | 4284 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); |
d823ba47 | 4285 | virtual_outgoing_args_rtx = |
4286 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
22cf44bc | 4287 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); |
57c097d5 | 4288 | |
4289 | /* These rtx must be roots if GC is enabled. */ | |
d7c47c0e | 4290 | ggc_add_rtx_root (global_rtl, GR_MAX); |
57c097d5 | 4291 | |
57c097d5 | 4292 | #ifdef INIT_EXPANDERS |
ab5beff9 | 4293 | /* This is to initialize {init|mark|free}_machine_status before the first |
4294 | call to push_function_context_to. This is needed by the Chill front | |
4295 | end which calls push_function_context_to before the first cal to | |
57c097d5 | 4296 | init_function_start. */ |
4297 | INIT_EXPANDERS; | |
4298 | #endif | |
4299 | ||
15bbde2b | 4300 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
4301 | ||
7014838c | 4302 | /* Don't use gen_rtx here since gen_rtx in this case |
4303 | tries to use these variables. */ | |
15bbde2b | 4304 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
d823ba47 | 4305 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
57c097d5 | 4306 | gen_rtx_raw_CONST_INT (VOIDmode, i); |
d7c47c0e | 4307 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); |
15bbde2b | 4308 | |
1a60f06a | 4309 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
4310 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
57c097d5 | 4311 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
1a60f06a | 4312 | else |
3ad7bb1c | 4313 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
15bbde2b | 4314 | |
9e042f31 | 4315 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
4316 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
4317 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
4318 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
15bbde2b | 4319 | |
4320 | for (i = 0; i <= 2; i++) | |
4321 | { | |
4322 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4323 | mode = GET_MODE_WIDER_MODE (mode)) | |
4324 | { | |
4325 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4326 | union real_extract u; | |
4327 | ||
fd781f88 | 4328 | /* Zero any holes in a structure. */ |
4329 | memset ((char *) &u, 0, sizeof u); | |
15bbde2b | 4330 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4331 | ||
fd781f88 | 4332 | /* Avoid trailing garbage in the rtx. */ |
4333 | if (sizeof (u) < sizeof (HOST_WIDE_INT)) | |
4334 | CONST_DOUBLE_LOW (tem) = 0; | |
4335 | if (sizeof (u) < 2 * sizeof (HOST_WIDE_INT)) | |
4336 | CONST_DOUBLE_HIGH (tem) = 0; | |
4337 | ||
b1b63592 | 4338 | memcpy (&CONST_DOUBLE_LOW (tem), &u, sizeof u); |
15bbde2b | 4339 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
791ceafe | 4340 | CONST_DOUBLE_CHAIN (tem) = NULL_RTX; |
15bbde2b | 4341 | PUT_MODE (tem, mode); |
4342 | ||
4343 | const_tiny_rtx[i][(int) mode] = tem; | |
4344 | } | |
4345 | ||
b572011e | 4346 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
15bbde2b | 4347 | |
4348 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4349 | mode = GET_MODE_WIDER_MODE (mode)) | |
b572011e | 4350 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
7540dcc4 | 4351 | |
4352 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4353 | mode != VOIDmode; | |
4354 | mode = GET_MODE_WIDER_MODE (mode)) | |
4355 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
15bbde2b | 4356 | } |
4357 | ||
0fd4500a | 4358 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
4359 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
4360 | const_tiny_rtx[0][i] = const0_rtx; | |
15bbde2b | 4361 | |
065336b4 | 4362 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
4363 | if (STORE_FLAG_VALUE == 1) | |
4364 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
4365 | ||
3098b2d3 | 4366 | /* For bounded pointers, `&const_tiny_rtx[0][0]' is not the same as |
4367 | `(rtx *) const_tiny_rtx'. The former has bounds that only cover | |
4368 | `const_tiny_rtx[0]', whereas the latter has bounds that cover all. */ | |
4369 | ggc_add_rtx_root ((rtx *) const_tiny_rtx, sizeof const_tiny_rtx / sizeof (rtx)); | |
c788feb1 | 4370 | ggc_add_rtx_root (&const_true_rtx, 1); |
f4bffa58 | 4371 | |
4372 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4373 | return_address_pointer_rtx | |
22cf44bc | 4374 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); |
f4bffa58 | 4375 | #endif |
4376 | ||
4377 | #ifdef STRUCT_VALUE | |
4378 | struct_value_rtx = STRUCT_VALUE; | |
4379 | #else | |
4380 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4381 | #endif | |
4382 | ||
4383 | #ifdef STRUCT_VALUE_INCOMING | |
4384 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4385 | #else | |
4386 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4387 | struct_value_incoming_rtx | |
4388 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4389 | #else | |
4390 | struct_value_incoming_rtx = struct_value_rtx; | |
4391 | #endif | |
4392 | #endif | |
4393 | ||
4394 | #ifdef STATIC_CHAIN_REGNUM | |
4395 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4396 | ||
4397 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4398 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4399 | static_chain_incoming_rtx | |
4400 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4401 | else | |
4402 | #endif | |
4403 | static_chain_incoming_rtx = static_chain_rtx; | |
4404 | #endif | |
4405 | ||
4406 | #ifdef STATIC_CHAIN | |
4407 | static_chain_rtx = STATIC_CHAIN; | |
4408 | ||
4409 | #ifdef STATIC_CHAIN_INCOMING | |
4410 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4411 | #else | |
4412 | static_chain_incoming_rtx = static_chain_rtx; | |
4413 | #endif | |
4414 | #endif | |
4415 | ||
14e6e4d4 | 4416 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
4417 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
f4bffa58 | 4418 | |
521dd524 | 4419 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4420 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4421 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4422 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4423 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4424 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
15bbde2b | 4425 | } |
ac6c481d | 4426 | \f |
4427 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4428 | switch / case handling in stmt.c to give proper line numbers in | |
4429 | warnings about unreachable code. */ | |
4430 | ||
4431 | int | |
4432 | force_line_numbers () | |
4433 | { | |
4434 | int old = no_line_numbers; | |
4435 | ||
4436 | no_line_numbers = 0; | |
4437 | if (old) | |
4438 | force_next_line_note (); | |
4439 | return old; | |
4440 | } | |
4441 | ||
4442 | void | |
4443 | restore_line_number_status (old_value) | |
4444 | int old_value; | |
4445 | { | |
4446 | no_line_numbers = old_value; | |
4447 | } |