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23b2ce53 | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ef58a523 JL |
2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
23b2ce53 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
670ee920 | 39 | #include "system.h" |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
23b2ce53 | 49 | #include "insn-config.h" |
e9a25f70 | 50 | #include "recog.h" |
23b2ce53 | 51 | #include "real.h" |
ca695ac9 | 52 | #include "obstack.h" |
0dfa1860 | 53 | #include "bitmap.h" |
a05924f9 | 54 | #include "basic-block.h" |
87ff9c8e | 55 | #include "ggc.h" |
ca695ac9 | 56 | |
1d445e9e ILT |
57 | /* Commonly used modes. */ |
58 | ||
0f41302f MS |
59 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
60 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 61 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 62 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 63 | |
23b2ce53 RS |
64 | |
65 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
66 | in the entire compilation a unique label number. */ | |
67 | ||
68 | static int label_num = 1; | |
69 | ||
23b2ce53 RS |
70 | /* Highest label number in current function. |
71 | Zero means use the value of label_num instead. | |
72 | This is nonzero only when belatedly compiling an inline function. */ | |
73 | ||
74 | static int last_label_num; | |
75 | ||
76 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
77 | If label_num has not changed since then, last_label_num is valid. */ | |
78 | ||
79 | static int base_label_num; | |
80 | ||
81 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
82 | ||
83 | static int no_line_numbers; | |
84 | ||
85 | /* Commonly used rtx's, so that we only need space for one copy. | |
86 | These are initialized once for the entire compilation. | |
87 | All of these except perhaps the floating-point CONST_DOUBLEs | |
88 | are unique; no other rtx-object will be equal to any of these. */ | |
89 | ||
5da077de | 90 | rtx global_rtl[GR_MAX]; |
23b2ce53 RS |
91 | |
92 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
93 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
94 | record a copy of const[012]_rtx. */ | |
95 | ||
96 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
97 | ||
68d75312 JC |
98 | rtx const_true_rtx; |
99 | ||
23b2ce53 RS |
100 | REAL_VALUE_TYPE dconst0; |
101 | REAL_VALUE_TYPE dconst1; | |
102 | REAL_VALUE_TYPE dconst2; | |
103 | REAL_VALUE_TYPE dconstm1; | |
104 | ||
105 | /* All references to the following fixed hard registers go through | |
106 | these unique rtl objects. On machines where the frame-pointer and | |
107 | arg-pointer are the same register, they use the same unique object. | |
108 | ||
109 | After register allocation, other rtl objects which used to be pseudo-regs | |
110 | may be clobbered to refer to the frame-pointer register. | |
111 | But references that were originally to the frame-pointer can be | |
112 | distinguished from the others because they contain frame_pointer_rtx. | |
113 | ||
ac6f08b0 DE |
114 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
115 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
116 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
117 | register elimination hard_frame_pointer_rtx should always be used. | |
118 | On machines where the two registers are same (most) then these are the | |
119 | same. | |
120 | ||
23b2ce53 RS |
121 | In an inline procedure, the stack and frame pointer rtxs may not be |
122 | used for anything else. */ | |
23b2ce53 RS |
123 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
124 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
125 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
126 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
127 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
128 | ||
a4417a86 JW |
129 | /* This is used to implement __builtin_return_address for some machines. |
130 | See for instance the MIPS port. */ | |
131 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
132 | ||
23b2ce53 RS |
133 | /* We make one copy of (const_int C) where C is in |
134 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
135 | to save space during the compilation and simplify comparisons of | |
136 | integers. */ | |
137 | ||
5da077de | 138 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 139 | |
23b2ce53 RS |
140 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
141 | shortly thrown away. We use two mechanisms to prevent this waste: | |
142 | ||
a3770a81 RH |
143 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
144 | rtvec for use by gen_sequence. One entry for each size is | |
145 | sufficient because most cases are calls to gen_sequence followed by | |
146 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
147 | sequence is destructive on the insn in it anyway and hence can't be | |
148 | redone. | |
23b2ce53 RS |
149 | |
150 | We do not bother to save this cached data over nested function calls. | |
151 | Instead, we just reinitialize them. */ | |
152 | ||
153 | #define SEQUENCE_RESULT_SIZE 5 | |
154 | ||
23b2ce53 RS |
155 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
156 | ||
0f41302f | 157 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
43127294 RK |
158 | static rtx free_insn; |
159 | ||
01d939e8 BS |
160 | #define first_insn (cfun->emit->x_first_insn) |
161 | #define last_insn (cfun->emit->x_last_insn) | |
162 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
163 | #define last_linenum (cfun->emit->x_last_linenum) | |
164 | #define last_filename (cfun->emit->x_last_filename) | |
165 | #define first_label_num (cfun->emit->x_first_label_num) | |
23b2ce53 | 166 | |
da43a810 BS |
167 | /* This is where the pointer to the obstack being used for RTL is stored. */ |
168 | extern struct obstack *rtl_obstack; | |
169 | ||
711d877c KG |
170 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
171 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
172 | static rtx find_line_note PARAMS ((rtx)); | |
173 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
d1b81779 | 174 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
ca695ac9 | 175 | \f |
c5c76735 JL |
176 | /* There are some RTL codes that require special attention; the generation |
177 | functions do the raw handling. If you add to this list, modify | |
178 | special_rtx in gengenrtl.c as well. */ | |
179 | ||
3b80f6ca RH |
180 | rtx |
181 | gen_rtx_CONST_INT (mode, arg) | |
182 | enum machine_mode mode; | |
183 | HOST_WIDE_INT arg; | |
184 | { | |
185 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) | |
5da077de | 186 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
187 | |
188 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
189 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
190 | return const_true_rtx; | |
191 | #endif | |
192 | ||
193 | return gen_rtx_raw_CONST_INT (mode, arg); | |
194 | } | |
195 | ||
0133b7d9 RH |
196 | /* CONST_DOUBLEs needs special handling because its length is known |
197 | only at run-time. */ | |
198 | rtx | |
199 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
200 | enum machine_mode mode; | |
201 | rtx arg0; | |
202 | HOST_WIDE_INT arg1, arg2; | |
203 | { | |
204 | rtx r = rtx_alloc (CONST_DOUBLE); | |
2454beaf RH |
205 | int i; |
206 | ||
0133b7d9 RH |
207 | PUT_MODE (r, mode); |
208 | XEXP (r, 0) = arg0; | |
ef178af3 | 209 | X0EXP (r, 1) = NULL_RTX; |
2454beaf RH |
210 | XWINT (r, 2) = arg1; |
211 | XWINT (r, 3) = arg2; | |
212 | ||
213 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
214 | XWINT (r, i) = 0; | |
215 | ||
0133b7d9 RH |
216 | return r; |
217 | } | |
218 | ||
3b80f6ca RH |
219 | rtx |
220 | gen_rtx_REG (mode, regno) | |
221 | enum machine_mode mode; | |
222 | int regno; | |
223 | { | |
224 | /* In case the MD file explicitly references the frame pointer, have | |
225 | all such references point to the same frame pointer. This is | |
226 | used during frame pointer elimination to distinguish the explicit | |
227 | references to these registers from pseudos that happened to be | |
228 | assigned to them. | |
229 | ||
230 | If we have eliminated the frame pointer or arg pointer, we will | |
231 | be using it as a normal register, for example as a spill | |
232 | register. In such cases, we might be accessing it in a mode that | |
233 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
234 | ||
235 | Also don't do this when we are making new REGs in reload, since | |
236 | we don't want to get confused with the real pointers. */ | |
237 | ||
238 | if (mode == Pmode && !reload_in_progress) | |
239 | { | |
bcb33994 | 240 | if (regno == FRAME_POINTER_REGNUM) |
3b80f6ca RH |
241 | return frame_pointer_rtx; |
242 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
bcb33994 | 243 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3b80f6ca RH |
244 | return hard_frame_pointer_rtx; |
245 | #endif | |
246 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 247 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
248 | return arg_pointer_rtx; |
249 | #endif | |
250 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 251 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
252 | return return_address_pointer_rtx; |
253 | #endif | |
bcb33994 | 254 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
255 | return stack_pointer_rtx; |
256 | } | |
257 | ||
258 | return gen_rtx_raw_REG (mode, regno); | |
259 | } | |
260 | ||
41472af8 MM |
261 | rtx |
262 | gen_rtx_MEM (mode, addr) | |
263 | enum machine_mode mode; | |
264 | rtx addr; | |
265 | { | |
266 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
267 | ||
268 | /* This field is not cleared by the mere allocation of the rtx, so | |
269 | we clear it here. */ | |
270 | MEM_ALIAS_SET (rt) = 0; | |
271 | ||
272 | return rt; | |
273 | } | |
c5c76735 | 274 | \f |
23b2ce53 RS |
275 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
276 | ** | |
277 | ** This routine generates an RTX of the size specified by | |
278 | ** <code>, which is an RTX code. The RTX structure is initialized | |
279 | ** from the arguments <element1> through <elementn>, which are | |
280 | ** interpreted according to the specific RTX type's format. The | |
281 | ** special machine mode associated with the rtx (if any) is specified | |
282 | ** in <mode>. | |
283 | ** | |
1632afca | 284 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
285 | ** rtx it will generate. For example, the following rtx structure: |
286 | ** | |
287 | ** (plus:QI (mem:QI (reg:SI 1)) | |
288 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
289 | ** | |
290 | ** ...would be generated by the following C code: | |
291 | ** | |
292 | ** gen_rtx (PLUS, QImode, | |
293 | ** gen_rtx (MEM, QImode, | |
294 | ** gen_rtx (REG, SImode, 1)), | |
295 | ** gen_rtx (MEM, QImode, | |
296 | ** gen_rtx (PLUS, SImode, | |
297 | ** gen_rtx (REG, SImode, 2), | |
298 | ** gen_rtx (REG, SImode, 3)))), | |
299 | */ | |
300 | ||
301 | /*VARARGS2*/ | |
302 | rtx | |
711d877c | 303 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
23b2ce53 | 304 | { |
5148a72b | 305 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
306 | enum rtx_code code; |
307 | enum machine_mode mode; | |
4f90e4a0 RK |
308 | #endif |
309 | va_list p; | |
23b2ce53 | 310 | register int i; /* Array indices... */ |
6f7d635c | 311 | register const char *fmt; /* Current rtx's format... */ |
23b2ce53 RS |
312 | register rtx rt_val; /* RTX to return to caller... */ |
313 | ||
4f90e4a0 RK |
314 | VA_START (p, mode); |
315 | ||
5148a72b | 316 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
317 | code = va_arg (p, enum rtx_code); |
318 | mode = va_arg (p, enum machine_mode); | |
4f90e4a0 | 319 | #endif |
23b2ce53 | 320 | |
0133b7d9 | 321 | switch (code) |
23b2ce53 | 322 | { |
0133b7d9 RH |
323 | case CONST_INT: |
324 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
325 | break; | |
326 | ||
327 | case CONST_DOUBLE: | |
328 | { | |
329 | rtx arg0 = va_arg (p, rtx); | |
330 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
331 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
332 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
333 | } | |
334 | break; | |
335 | ||
336 | case REG: | |
337 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
338 | break; | |
339 | ||
340 | case MEM: | |
341 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
342 | break; | |
343 | ||
344 | default: | |
23b2ce53 RS |
345 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
346 | rt_val->mode = mode; /* Store the machine mode... */ | |
347 | ||
348 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
349 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
350 | { | |
351 | switch (*fmt++) | |
352 | { | |
353 | case '0': /* Unused field. */ | |
354 | break; | |
355 | ||
356 | case 'i': /* An integer? */ | |
357 | XINT (rt_val, i) = va_arg (p, int); | |
358 | break; | |
359 | ||
906c4e36 RK |
360 | case 'w': /* A wide integer? */ |
361 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
362 | break; | |
363 | ||
23b2ce53 RS |
364 | case 's': /* A string? */ |
365 | XSTR (rt_val, i) = va_arg (p, char *); | |
366 | break; | |
367 | ||
368 | case 'e': /* An expression? */ | |
369 | case 'u': /* An insn? Same except when printing. */ | |
370 | XEXP (rt_val, i) = va_arg (p, rtx); | |
371 | break; | |
372 | ||
373 | case 'E': /* An RTX vector? */ | |
374 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
375 | break; | |
376 | ||
0dfa1860 MM |
377 | case 'b': /* A bitmap? */ |
378 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
379 | break; | |
380 | ||
381 | case 't': /* A tree? */ | |
382 | XTREE (rt_val, i) = va_arg (p, tree); | |
383 | break; | |
384 | ||
23b2ce53 | 385 | default: |
1632afca | 386 | abort (); |
23b2ce53 RS |
387 | } |
388 | } | |
0133b7d9 | 389 | break; |
23b2ce53 | 390 | } |
0133b7d9 | 391 | |
23b2ce53 | 392 | va_end (p); |
0133b7d9 | 393 | return rt_val; |
23b2ce53 RS |
394 | } |
395 | ||
396 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
397 | ** | |
398 | ** This routine creates an rtvec and stores within it the | |
399 | ** pointers to rtx's which are its arguments. | |
400 | */ | |
401 | ||
402 | /*VARARGS1*/ | |
403 | rtvec | |
711d877c | 404 | gen_rtvec VPARAMS ((int n, ...)) |
23b2ce53 | 405 | { |
5148a72b | 406 | #ifndef ANSI_PROTOTYPES |
4f90e4a0 RK |
407 | int n; |
408 | #endif | |
409 | int i; | |
23b2ce53 RS |
410 | va_list p; |
411 | rtx *vector; | |
412 | ||
4f90e4a0 RK |
413 | VA_START (p, n); |
414 | ||
5148a72b | 415 | #ifndef ANSI_PROTOTYPES |
23b2ce53 | 416 | n = va_arg (p, int); |
4f90e4a0 | 417 | #endif |
23b2ce53 RS |
418 | |
419 | if (n == 0) | |
420 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
421 | ||
422 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 423 | |
23b2ce53 RS |
424 | for (i = 0; i < n; i++) |
425 | vector[i] = va_arg (p, rtx); | |
426 | va_end (p); | |
427 | ||
428 | return gen_rtvec_v (n, vector); | |
429 | } | |
430 | ||
431 | rtvec | |
432 | gen_rtvec_v (n, argp) | |
433 | int n; | |
434 | rtx *argp; | |
435 | { | |
436 | register int i; | |
437 | register rtvec rt_val; | |
438 | ||
439 | if (n == 0) | |
440 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
441 | ||
442 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
443 | ||
444 | for (i = 0; i < n; i++) | |
8f985ec4 | 445 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
446 | |
447 | return rt_val; | |
448 | } | |
ba444f92 | 449 | |
23b2ce53 RS |
450 | \f |
451 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
452 | This pseudo is assigned the next sequential register number. */ | |
453 | ||
454 | rtx | |
455 | gen_reg_rtx (mode) | |
456 | enum machine_mode mode; | |
457 | { | |
01d939e8 | 458 | struct function *f = cfun; |
23b2ce53 RS |
459 | register rtx val; |
460 | ||
f1db3576 JL |
461 | /* Don't let anything called after initial flow analysis create new |
462 | registers. */ | |
463 | if (no_new_pseudos) | |
23b2ce53 RS |
464 | abort (); |
465 | ||
fc84e8a8 RS |
466 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
467 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
468 | { | |
469 | /* For complex modes, don't make a single pseudo. | |
470 | Instead, make a CONCAT of two pseudos. | |
471 | This allows noncontiguous allocation of the real and imaginary parts, | |
472 | which makes much better code. Besides, allocating DCmode | |
473 | pseudos overstrains reload on some machines like the 386. */ | |
474 | rtx realpart, imagpart; | |
475 | int size = GET_MODE_UNIT_SIZE (mode); | |
476 | enum machine_mode partmode | |
477 | = mode_for_size (size * BITS_PER_UNIT, | |
478 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
479 | ? MODE_FLOAT : MODE_INT), | |
480 | 0); | |
481 | ||
482 | realpart = gen_reg_rtx (partmode); | |
483 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 484 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
485 | } |
486 | ||
23b2ce53 RS |
487 | /* Make sure regno_pointer_flag and regno_reg_rtx are large |
488 | enough to have an element for this pseudo reg number. */ | |
489 | ||
49ad7cfa | 490 | if (reg_rtx_no == f->emit->regno_pointer_flag_length) |
23b2ce53 | 491 | { |
49ad7cfa | 492 | int old_size = f->emit->regno_pointer_flag_length; |
23b2ce53 | 493 | rtx *new1; |
e2ecd91c BS |
494 | char *new; |
495 | new = xrealloc (f->emit->regno_pointer_flag, old_size * 2); | |
49ad7cfa BS |
496 | memset (new + old_size, 0, old_size); |
497 | f->emit->regno_pointer_flag = new; | |
498 | ||
e2ecd91c | 499 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa BS |
500 | memset (new + old_size, 0, old_size); |
501 | f->emit->regno_pointer_align = new; | |
502 | ||
e2ecd91c BS |
503 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
504 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 505 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
506 | regno_reg_rtx = new1; |
507 | ||
49ad7cfa | 508 | f->emit->regno_pointer_flag_length = old_size * 2; |
23b2ce53 RS |
509 | } |
510 | ||
3b80f6ca | 511 | val = gen_rtx_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
512 | regno_reg_rtx[reg_rtx_no++] = val; |
513 | return val; | |
514 | } | |
515 | ||
754fdcca RK |
516 | /* Identify REG (which may be a CONCAT) as a user register. */ |
517 | ||
518 | void | |
519 | mark_user_reg (reg) | |
520 | rtx reg; | |
521 | { | |
522 | if (GET_CODE (reg) == CONCAT) | |
523 | { | |
524 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
525 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
526 | } | |
527 | else if (GET_CODE (reg) == REG) | |
528 | REG_USERVAR_P (reg) = 1; | |
529 | else | |
530 | abort (); | |
531 | } | |
532 | ||
86fe05e0 RK |
533 | /* Identify REG as a probable pointer register and show its alignment |
534 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
535 | |
536 | void | |
86fe05e0 | 537 | mark_reg_pointer (reg, align) |
23b2ce53 | 538 | rtx reg; |
86fe05e0 | 539 | int align; |
23b2ce53 | 540 | { |
00995e78 RE |
541 | if (! REGNO_POINTER_FLAG (REGNO (reg))) |
542 | { | |
543 | REGNO_POINTER_FLAG (REGNO (reg)) = 1; | |
86fe05e0 | 544 | |
00995e78 RE |
545 | if (align) |
546 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
547 | } | |
548 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
549 | /* We can no-longer be sure just how aligned this pointer is */ | |
86fe05e0 | 550 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
551 | } |
552 | ||
553 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
554 | ||
555 | int | |
556 | max_reg_num () | |
557 | { | |
558 | return reg_rtx_no; | |
559 | } | |
560 | ||
561 | /* Return 1 + the largest label number used so far in the current function. */ | |
562 | ||
563 | int | |
564 | max_label_num () | |
565 | { | |
566 | if (last_label_num && label_num == base_label_num) | |
567 | return last_label_num; | |
568 | return label_num; | |
569 | } | |
570 | ||
571 | /* Return first label number used in this function (if any were used). */ | |
572 | ||
573 | int | |
574 | get_first_label_num () | |
575 | { | |
576 | return first_label_num; | |
577 | } | |
578 | \f | |
579 | /* Return a value representing some low-order bits of X, where the number | |
580 | of low-order bits is given by MODE. Note that no conversion is done | |
581 | between floating-point and fixed-point values, rather, the bit | |
582 | representation is returned. | |
583 | ||
584 | This function handles the cases in common between gen_lowpart, below, | |
585 | and two variants in cse.c and combine.c. These are the cases that can | |
586 | be safely handled at all points in the compilation. | |
587 | ||
588 | If this is not a case we can handle, return 0. */ | |
589 | ||
590 | rtx | |
591 | gen_lowpart_common (mode, x) | |
592 | enum machine_mode mode; | |
593 | register rtx x; | |
594 | { | |
595 | int word = 0; | |
596 | ||
597 | if (GET_MODE (x) == mode) | |
598 | return x; | |
599 | ||
600 | /* MODE must occupy no more words than the mode of X. */ | |
601 | if (GET_MODE (x) != VOIDmode | |
602 | && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD | |
603 | > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1)) | |
604 | / UNITS_PER_WORD))) | |
605 | return 0; | |
606 | ||
607 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
608 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
609 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
610 | / UNITS_PER_WORD); | |
611 | ||
612 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
613 | && (GET_MODE_CLASS (mode) == MODE_INT |
614 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
615 | { |
616 | /* If we are getting the low-order part of something that has been | |
617 | sign- or zero-extended, we can either just use the object being | |
618 | extended or make a narrower extension. If we want an even smaller | |
619 | piece than the size of the object being extended, call ourselves | |
620 | recursively. | |
621 | ||
622 | This case is used mostly by combine and cse. */ | |
623 | ||
624 | if (GET_MODE (XEXP (x, 0)) == mode) | |
625 | return XEXP (x, 0); | |
626 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
627 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
628 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3b80f6ca | 629 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 RS |
630 | } |
631 | else if (GET_CODE (x) == SUBREG | |
632 | && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
633 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) | |
634 | return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0 | |
635 | ? SUBREG_REG (x) | |
3b80f6ca | 636 | : gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + word)); |
23b2ce53 RS |
637 | else if (GET_CODE (x) == REG) |
638 | { | |
4901a643 RH |
639 | /* Let the backend decide how many registers to skip. This is needed |
640 | in particular for Sparc64 where fp regs are smaller than a word. */ | |
641 | /* ??? Note that subregs are now ambiguous, in that those against | |
642 | pseudos are sized by the Word Size, while those against hard | |
643 | regs are sized by the underlying register size. Better would be | |
644 | to always interpret the subreg offset parameter as bytes or bits. */ | |
645 | ||
646 | if (WORDS_BIG_ENDIAN && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
647 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) | |
648 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
649 | ||
23b2ce53 | 650 | /* If the register is not valid for MODE, return 0. If we don't |
674d5d8b RK |
651 | do this, there is no way to fix up the resulting REG later. |
652 | But we do do this if the current REG is not valid for its | |
653 | mode. This latter is a kludge, but is required due to the | |
654 | way that parameters are passed on some machines, most | |
655 | notably Sparc. */ | |
23b2ce53 | 656 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
674d5d8b RK |
657 | && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode) |
658 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
23b2ce53 RS |
659 | return 0; |
660 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
661 | /* integrate.c can't handle parts of a return value register. */ | |
662 | && (! REG_FUNCTION_VALUE_P (x) | |
cb00f51a | 663 | || ! rtx_equal_function_value_matters) |
aff48bca JL |
664 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
665 | && ! (GET_MODE_SIZE (mode) != GET_MODE_SIZE (GET_MODE (x)) | |
666 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT | |
667 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT | |
668 | && (TEST_HARD_REG_BIT | |
669 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
670 | REGNO (x)))) | |
671 | #endif | |
cb00f51a RK |
672 | /* We want to keep the stack, frame, and arg pointers |
673 | special. */ | |
65e8fe02 | 674 | && x != frame_pointer_rtx |
cb00f51a | 675 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 676 | && x != arg_pointer_rtx |
cb00f51a | 677 | #endif |
65e8fe02 | 678 | && x != stack_pointer_rtx) |
3b80f6ca | 679 | return gen_rtx_REG (mode, REGNO (x) + word); |
23b2ce53 | 680 | else |
3b80f6ca | 681 | return gen_rtx_SUBREG (mode, x, word); |
23b2ce53 | 682 | } |
23b2ce53 RS |
683 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
684 | from the low-order part of the constant. */ | |
83e9c679 RK |
685 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
686 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
687 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 688 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
689 | { |
690 | /* If MODE is twice the host word size, X is already the desired | |
691 | representation. Otherwise, if MODE is wider than a word, we can't | |
692 | do this. If MODE is exactly a word, return just one CONST_INT. | |
693 | If MODE is smaller than a word, clear the bits that don't belong | |
694 | in our mode, unless they and our sign bit are all one. So we get | |
695 | either a reasonable negative value or a reasonable unsigned value | |
696 | for this mode. */ | |
697 | ||
a8dd0e73 | 698 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 699 | return x; |
906c4e36 | 700 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 701 | return 0; |
906c4e36 | 702 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 703 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 704 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
705 | else |
706 | { | |
27eef9ce | 707 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
1a5b457d | 708 | int width = GET_MODE_BITSIZE (mode); |
906c4e36 RK |
709 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
710 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 711 | |
27eef9ce JC |
712 | /* Sign extend to HOST_WIDE_INT. */ |
713 | val = val << (HOST_BITS_PER_WIDE_INT - width) >> (HOST_BITS_PER_WIDE_INT - width); | |
1a5b457d RK |
714 | |
715 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 716 | : GEN_INT (val)); |
1a5b457d RK |
717 | } |
718 | } | |
23b2ce53 | 719 | |
8aada4ad RK |
720 | /* If X is an integral constant but we want it in floating-point, it |
721 | must be the case that we have a union of an integer and a floating-point | |
722 | value. If the machine-parameters allow it, simulate that union here | |
d6020413 RK |
723 | and return the result. The two-word and single-word cases are |
724 | different. */ | |
8aada4ad | 725 | |
b3bf132d | 726 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 727 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 728 | || flag_pretend_float) |
8aada4ad | 729 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
d6020413 RK |
730 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
731 | && GET_CODE (x) == CONST_INT | |
906c4e36 | 732 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
b6a524cb RS |
733 | #ifdef REAL_ARITHMETIC |
734 | { | |
735 | REAL_VALUE_TYPE r; | |
736 | HOST_WIDE_INT i; | |
737 | ||
738 | i = INTVAL (x); | |
739 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
53596fba | 740 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
741 | } |
742 | #else | |
d6020413 | 743 | { |
906c4e36 | 744 | union {HOST_WIDE_INT i; float d; } u; |
d6020413 RK |
745 | |
746 | u.i = INTVAL (x); | |
53596fba | 747 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
d6020413 | 748 | } |
b6a524cb | 749 | #endif |
d6020413 | 750 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 751 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
d6020413 RK |
752 | || flag_pretend_float) |
753 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
754 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
8aada4ad RK |
755 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
756 | && GET_MODE (x) == VOIDmode | |
906c4e36 RK |
757 | && (sizeof (double) * HOST_BITS_PER_CHAR |
758 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
b6a524cb RS |
759 | #ifdef REAL_ARITHMETIC |
760 | { | |
761 | REAL_VALUE_TYPE r; | |
762 | HOST_WIDE_INT i[2]; | |
763 | HOST_WIDE_INT low, high; | |
764 | ||
765 | if (GET_CODE (x) == CONST_INT) | |
766 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); | |
767 | else | |
768 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
769 | ||
8698cce3 | 770 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the |
0f41302f | 771 | target machine. */ |
8698cce3 RK |
772 | if (WORDS_BIG_ENDIAN) |
773 | i[0] = high, i[1] = low; | |
774 | else | |
775 | i[0] = low, i[1] = high; | |
b6a524cb RS |
776 | |
777 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
53596fba | 778 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
779 | } |
780 | #else | |
8aada4ad | 781 | { |
906c4e36 RK |
782 | union {HOST_WIDE_INT i[2]; double d; } u; |
783 | HOST_WIDE_INT low, high; | |
8aada4ad RK |
784 | |
785 | if (GET_CODE (x) == CONST_INT) | |
906c4e36 | 786 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
8aada4ad RK |
787 | else |
788 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
789 | ||
790 | #ifdef HOST_WORDS_BIG_ENDIAN | |
791 | u.i[0] = high, u.i[1] = low; | |
792 | #else | |
793 | u.i[0] = low, u.i[1] = high; | |
794 | #endif | |
795 | ||
53596fba | 796 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
8aada4ad | 797 | } |
b6a524cb | 798 | #endif |
a6a503ed JW |
799 | |
800 | /* We need an extra case for machines where HOST_BITS_PER_WIDE_INT is the | |
4926b75a JL |
801 | same as sizeof (double) or when sizeof (float) is larger than the |
802 | size of a word on the target machine. */ | |
a6a503ed | 803 | #ifdef REAL_ARITHMETIC |
4926b75a | 804 | else if (mode == SFmode && GET_CODE (x) == CONST_INT) |
a6a503ed JW |
805 | { |
806 | REAL_VALUE_TYPE r; | |
807 | HOST_WIDE_INT i; | |
808 | ||
809 | i = INTVAL (x); | |
810 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
811 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
812 | } | |
8fc4af0f JJ |
813 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
814 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
815 | || flag_pretend_float) | |
816 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
817 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
818 | && GET_CODE (x) == CONST_INT | |
819 | && (sizeof (double) * HOST_BITS_PER_CHAR | |
820 | == HOST_BITS_PER_WIDE_INT)) | |
821 | { | |
822 | REAL_VALUE_TYPE r; | |
823 | HOST_WIDE_INT i; | |
824 | ||
825 | i = INTVAL (x); | |
826 | r = REAL_VALUE_FROM_TARGET_DOUBLE (&i); | |
827 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
828 | } | |
a6a503ed JW |
829 | #endif |
830 | ||
b3bf132d RK |
831 | /* Similarly, if this is converting a floating-point value into a |
832 | single-word integer. Only do this is the host and target parameters are | |
833 | compatible. */ | |
834 | ||
835 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
906c4e36 | 836 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 837 | || flag_pretend_float) |
83e9c679 RK |
838 | && (GET_MODE_CLASS (mode) == MODE_INT |
839 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
b3bf132d RK |
840 | && GET_CODE (x) == CONST_DOUBLE |
841 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
842 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
a80586cc | 843 | return operand_subword (x, word, 0, GET_MODE (x)); |
b3bf132d | 844 | |
8aada4ad RK |
845 | /* Similarly, if this is converting a floating-point value into a |
846 | two-word integer, we can do this one word at a time and make an | |
847 | integer. Only do this is the host and target parameters are | |
848 | compatible. */ | |
849 | ||
b3bf132d | 850 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 851 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 852 | || flag_pretend_float) |
83e9c679 | 853 | && (GET_MODE_CLASS (mode) == MODE_INT |
f5a2fb25 | 854 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
8aada4ad RK |
855 | && GET_CODE (x) == CONST_DOUBLE |
856 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
857 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
858 | { | |
a80586cc RK |
859 | rtx lowpart |
860 | = operand_subword (x, word + WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
861 | rtx highpart | |
862 | = operand_subword (x, word + ! WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
8aada4ad RK |
863 | |
864 | if (lowpart && GET_CODE (lowpart) == CONST_INT | |
865 | && highpart && GET_CODE (highpart) == CONST_INT) | |
866 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
867 | } | |
868 | ||
23b2ce53 RS |
869 | /* Otherwise, we can't do this. */ |
870 | return 0; | |
871 | } | |
872 | \f | |
280194b0 RS |
873 | /* Return the real part (which has mode MODE) of a complex value X. |
874 | This always comes at the low address in memory. */ | |
875 | ||
876 | rtx | |
877 | gen_realpart (mode, x) | |
878 | enum machine_mode mode; | |
879 | register rtx x; | |
880 | { | |
dc139c90 RK |
881 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
882 | return XEXP (x, 0); | |
40c0c3cf JL |
883 | else if (WORDS_BIG_ENDIAN |
884 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
885 | && REG_P (x) | |
886 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
887 | fatal ("Unable to access real part of complex value in a hard register on this target"); | |
dc139c90 | 888 | else if (WORDS_BIG_ENDIAN) |
280194b0 RS |
889 | return gen_highpart (mode, x); |
890 | else | |
891 | return gen_lowpart (mode, x); | |
892 | } | |
893 | ||
894 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
895 | This always comes at the high address in memory. */ | |
896 | ||
897 | rtx | |
898 | gen_imagpart (mode, x) | |
899 | enum machine_mode mode; | |
900 | register rtx x; | |
901 | { | |
dc139c90 RK |
902 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
903 | return XEXP (x, 1); | |
904 | else if (WORDS_BIG_ENDIAN) | |
280194b0 | 905 | return gen_lowpart (mode, x); |
40c0c3cf JL |
906 | else if (!WORDS_BIG_ENDIAN |
907 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
908 | && REG_P (x) | |
909 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
910 | fatal ("Unable to access imaginary part of complex value in a hard register on this target"); | |
280194b0 RS |
911 | else |
912 | return gen_highpart (mode, x); | |
913 | } | |
81284a6a JW |
914 | |
915 | /* Return 1 iff X, assumed to be a SUBREG, | |
916 | refers to the real part of the complex value in its containing reg. | |
917 | Complex values are always stored with the real part in the first word, | |
918 | regardless of WORDS_BIG_ENDIAN. */ | |
919 | ||
920 | int | |
921 | subreg_realpart_p (x) | |
922 | rtx x; | |
923 | { | |
924 | if (GET_CODE (x) != SUBREG) | |
925 | abort (); | |
926 | ||
770ae6cc RK |
927 | return ((unsigned int) SUBREG_WORD (x) * UNITS_PER_WORD |
928 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); | |
81284a6a | 929 | } |
280194b0 | 930 | \f |
23b2ce53 RS |
931 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
932 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
933 | least-significant part of X. | |
934 | MODE specifies how big a part of X to return; | |
935 | it usually should not be larger than a word. | |
936 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
937 | ||
938 | rtx | |
939 | gen_lowpart (mode, x) | |
940 | enum machine_mode mode; | |
941 | register rtx x; | |
942 | { | |
943 | rtx result = gen_lowpart_common (mode, x); | |
944 | ||
945 | if (result) | |
946 | return result; | |
ea8262b0 RK |
947 | else if (GET_CODE (x) == REG) |
948 | { | |
949 | /* Must be a hard reg that's not valid in MODE. */ | |
950 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
951 | if (result == 0) | |
952 | abort (); | |
72c3833b | 953 | return result; |
ea8262b0 | 954 | } |
23b2ce53 RS |
955 | else if (GET_CODE (x) == MEM) |
956 | { | |
957 | /* The only additional case we can do is MEM. */ | |
958 | register int offset = 0; | |
959 | if (WORDS_BIG_ENDIAN) | |
960 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
961 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
962 | ||
963 | if (BYTES_BIG_ENDIAN) | |
964 | /* Adjust the address so that the address-after-the-data | |
965 | is unchanged. */ | |
966 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
967 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
968 | ||
969 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
970 | } | |
e9a25f70 JL |
971 | else if (GET_CODE (x) == ADDRESSOF) |
972 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
23b2ce53 RS |
973 | else |
974 | abort (); | |
975 | } | |
976 | ||
ccba022b RS |
977 | /* Like `gen_lowpart', but refer to the most significant part. |
978 | This is used to access the imaginary part of a complex number. */ | |
979 | ||
980 | rtx | |
981 | gen_highpart (mode, x) | |
982 | enum machine_mode mode; | |
983 | register rtx x; | |
984 | { | |
985 | /* This case loses if X is a subreg. To catch bugs early, | |
986 | complain if an invalid MODE is used even in other cases. */ | |
987 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
988 | && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
989 | abort (); | |
990 | if (GET_CODE (x) == CONST_DOUBLE | |
1632afca | 991 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
ccba022b RS |
992 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
993 | #endif | |
994 | ) | |
3b80f6ca | 995 | return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); |
ccba022b | 996 | else if (GET_CODE (x) == CONST_INT) |
27eef9ce JC |
997 | { |
998 | if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD) | |
999 | return const0_rtx; | |
1000 | return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD)); | |
1001 | } | |
ccba022b RS |
1002 | else if (GET_CODE (x) == MEM) |
1003 | { | |
1004 | register int offset = 0; | |
8698cce3 RK |
1005 | if (! WORDS_BIG_ENDIAN) |
1006 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1007 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1008 | ||
1009 | if (! BYTES_BIG_ENDIAN | |
1010 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
ccba022b RS |
1011 | offset -= (GET_MODE_SIZE (mode) |
1012 | - MIN (UNITS_PER_WORD, | |
1013 | GET_MODE_SIZE (GET_MODE (x)))); | |
8698cce3 | 1014 | |
ccba022b RS |
1015 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
1016 | } | |
1017 | else if (GET_CODE (x) == SUBREG) | |
1018 | { | |
1019 | /* The only time this should occur is when we are looking at a | |
1020 | multi-word item with a SUBREG whose mode is the same as that of the | |
1021 | item. It isn't clear what we would do if it wasn't. */ | |
1022 | if (SUBREG_WORD (x) != 0) | |
1023 | abort (); | |
1024 | return gen_highpart (mode, SUBREG_REG (x)); | |
1025 | } | |
1026 | else if (GET_CODE (x) == REG) | |
1027 | { | |
6cca74ab | 1028 | int word; |
ccba022b | 1029 | |
4901a643 RH |
1030 | /* Let the backend decide how many registers to skip. This is needed |
1031 | in particular for sparc64 where fp regs are smaller than a word. */ | |
1032 | /* ??? Note that subregs are now ambiguous, in that those against | |
6cca74ab | 1033 | pseudos are sized by the word size, while those against hard |
4901a643 RH |
1034 | regs are sized by the underlying register size. Better would be |
1035 | to always interpret the subreg offset parameter as bytes or bits. */ | |
1036 | ||
6cca74ab GM |
1037 | if (WORDS_BIG_ENDIAN) |
1038 | word = 0; | |
1039 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
4901a643 RH |
1040 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) |
1041 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
6cca74ab GM |
1042 | else |
1043 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
1044 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
1045 | / UNITS_PER_WORD); | |
3e4a14ef | 1046 | |
cb00f51a | 1047 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
0f41302f | 1048 | /* integrate.c can't handle parts of a return value register. */ |
4badc528 RS |
1049 | && (! REG_FUNCTION_VALUE_P (x) |
1050 | || ! rtx_equal_function_value_matters) | |
cb00f51a | 1051 | /* We want to keep the stack, frame, and arg pointers special. */ |
65e8fe02 | 1052 | && x != frame_pointer_rtx |
cb00f51a | 1053 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1054 | && x != arg_pointer_rtx |
cb00f51a | 1055 | #endif |
65e8fe02 | 1056 | && x != stack_pointer_rtx) |
3b80f6ca | 1057 | return gen_rtx_REG (mode, REGNO (x) + word); |
ccba022b | 1058 | else |
3b80f6ca | 1059 | return gen_rtx_SUBREG (mode, x, word); |
ccba022b RS |
1060 | } |
1061 | else | |
1062 | abort (); | |
1063 | } | |
1064 | ||
23b2ce53 RS |
1065 | /* Return 1 iff X, assumed to be a SUBREG, |
1066 | refers to the least significant part of its containing reg. | |
1067 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1068 | ||
1069 | int | |
1070 | subreg_lowpart_p (x) | |
1071 | rtx x; | |
1072 | { | |
1073 | if (GET_CODE (x) != SUBREG) | |
1074 | return 1; | |
a3a03040 RK |
1075 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1076 | return 0; | |
23b2ce53 RS |
1077 | |
1078 | if (WORDS_BIG_ENDIAN | |
1079 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD) | |
1080 | return (SUBREG_WORD (x) | |
1081 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1082 | - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)) | |
1083 | / UNITS_PER_WORD)); | |
1084 | ||
1085 | return SUBREG_WORD (x) == 0; | |
1086 | } | |
1087 | \f | |
1088 | /* Return subword I of operand OP. | |
1089 | The word number, I, is interpreted as the word number starting at the | |
1090 | low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN, | |
1091 | otherwise it is the high-order word. | |
1092 | ||
1093 | If we cannot extract the required word, we return zero. Otherwise, an | |
1094 | rtx corresponding to the requested word will be returned. | |
1095 | ||
1096 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1097 | reload has completed, a valid address will always be returned. After | |
1098 | reload, if a valid address cannot be returned, we return zero. | |
1099 | ||
1100 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1101 | it is the responsibility of the caller. | |
1102 | ||
1103 | MODE is the mode of OP in case it is a CONST_INT. */ | |
1104 | ||
1105 | rtx | |
1106 | operand_subword (op, i, validate_address, mode) | |
1107 | rtx op; | |
770ae6cc | 1108 | unsigned int i; |
23b2ce53 RS |
1109 | int validate_address; |
1110 | enum machine_mode mode; | |
1111 | { | |
906c4e36 RK |
1112 | HOST_WIDE_INT val; |
1113 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; | |
23b2ce53 RS |
1114 | |
1115 | if (mode == VOIDmode) | |
1116 | mode = GET_MODE (op); | |
1117 | ||
1118 | if (mode == VOIDmode) | |
1119 | abort (); | |
1120 | ||
0003feb2 | 1121 | /* If OP is narrower than a word, fail. */ |
23b2ce53 | 1122 | if (mode != BLKmode |
0003feb2 | 1123 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) |
23b2ce53 | 1124 | return 0; |
0003feb2 VM |
1125 | |
1126 | /* If we want a word outside OP, return zero. */ | |
1127 | if (mode != BLKmode | |
1128 | && (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1129 | return const0_rtx; | |
23b2ce53 RS |
1130 | |
1131 | /* If OP is already an integer word, return it. */ | |
1132 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1133 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1134 | return op; | |
1135 | ||
1136 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1137 | if (GET_CODE (op) == REG) | |
1138 | { | |
227d6ce0 JL |
1139 | /* ??? There is a potential problem with this code. It does not |
1140 | properly handle extractions of a subword from a hard register | |
1141 | that is larger than word_mode. Presumably the check for | |
1142 | HARD_REGNO_MODE_OK catches these most of these cases. */ | |
1143 | ||
1144 | /* If OP is a hard register, but OP + I is not a hard register, | |
1145 | then extracting a subword is impossible. | |
1146 | ||
1147 | For example, consider if OP is the last hard register and it is | |
1148 | larger than word_mode. If we wanted word N (for N > 0) because a | |
1149 | part of that hard register was known to contain a useful value, | |
1150 | then OP + I would refer to a pseudo, not the hard register we | |
1151 | actually wanted. */ | |
1152 | if (REGNO (op) < FIRST_PSEUDO_REGISTER | |
1153 | && REGNO (op) + i >= FIRST_PSEUDO_REGISTER) | |
1154 | return 0; | |
1155 | ||
1156 | /* If the register is not valid for MODE, return 0. Note we | |
1157 | have to check both OP and OP + I since they may refer to | |
1158 | different parts of the register file. | |
1159 | ||
1160 | Consider if OP refers to the last 96bit FP register and we want | |
1161 | subword 3 because that subword is known to contain a value we | |
1162 | needed. */ | |
23b2ce53 | 1163 | if (REGNO (op) < FIRST_PSEUDO_REGISTER |
227d6ce0 JL |
1164 | && (! HARD_REGNO_MODE_OK (REGNO (op), word_mode) |
1165 | || ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode))) | |
23b2ce53 RS |
1166 | return 0; |
1167 | else if (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1168 | || (REG_FUNCTION_VALUE_P (op) | |
cb00f51a RK |
1169 | && rtx_equal_function_value_matters) |
1170 | /* We want to keep the stack, frame, and arg pointers | |
1171 | special. */ | |
65e8fe02 | 1172 | || op == frame_pointer_rtx |
cb00f51a | 1173 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1174 | || op == arg_pointer_rtx |
cb00f51a | 1175 | #endif |
65e8fe02 | 1176 | || op == stack_pointer_rtx) |
3b80f6ca | 1177 | return gen_rtx_SUBREG (word_mode, op, i); |
23b2ce53 | 1178 | else |
3b80f6ca | 1179 | return gen_rtx_REG (word_mode, REGNO (op) + i); |
23b2ce53 RS |
1180 | } |
1181 | else if (GET_CODE (op) == SUBREG) | |
3b80f6ca | 1182 | return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), i + SUBREG_WORD (op)); |
fc84e8a8 RS |
1183 | else if (GET_CODE (op) == CONCAT) |
1184 | { | |
770ae6cc RK |
1185 | unsigned int partwords |
1186 | = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1187 | ||
fc84e8a8 RS |
1188 | if (i < partwords) |
1189 | return operand_subword (XEXP (op, 0), i, validate_address, mode); | |
1190 | return operand_subword (XEXP (op, 1), i - partwords, | |
1191 | validate_address, mode); | |
1192 | } | |
23b2ce53 RS |
1193 | |
1194 | /* Form a new MEM at the requested address. */ | |
1195 | if (GET_CODE (op) == MEM) | |
1196 | { | |
1197 | rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD); | |
1198 | rtx new; | |
1199 | ||
1200 | if (validate_address) | |
1201 | { | |
1202 | if (reload_completed) | |
1203 | { | |
1204 | if (! strict_memory_address_p (word_mode, addr)) | |
1205 | return 0; | |
1206 | } | |
1207 | else | |
1208 | addr = memory_address (word_mode, addr); | |
1209 | } | |
1210 | ||
3b80f6ca | 1211 | new = gen_rtx_MEM (word_mode, addr); |
23b2ce53 | 1212 | |
c6df88cb | 1213 | MEM_COPY_ATTRIBUTES (new, op); |
23b2ce53 | 1214 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); |
d3707adb | 1215 | MEM_ALIAS_SET (new) = MEM_ALIAS_SET (op); |
23b2ce53 RS |
1216 | |
1217 | return new; | |
1218 | } | |
1219 | ||
1220 | /* The only remaining cases are when OP is a constant. If the host and | |
1221 | target floating formats are the same, handling two-word floating | |
7677ffa4 | 1222 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} |
9847c2f6 RK |
1223 | are defined as returning one or two 32 bit values, respectively, |
1224 | and not values of BITS_PER_WORD bits. */ | |
1632afca | 1225 | #ifdef REAL_ARITHMETIC |
5495cc55 RH |
1226 | /* The output is some bits, the width of the target machine's word. |
1227 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1228 | host can't. */ | |
9847c2f6 | 1229 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1632afca | 1230 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1231 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1232 | && GET_CODE (op) == CONST_DOUBLE) |
1233 | { | |
9847c2f6 | 1234 | long k[2]; |
1632afca RS |
1235 | REAL_VALUE_TYPE rv; |
1236 | ||
1237 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1238 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1239 | |
9847c2f6 | 1240 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 | 1241 | which the words are written depends on the word endianness. |
7677ffa4 | 1242 | ??? This is a potential portability problem and should |
7cae975e RH |
1243 | be fixed at some point. |
1244 | ||
1245 | We must excercise caution with the sign bit. By definition there | |
1246 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1247 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1248 | So we explicitly mask and sign-extend as necessary. */ | |
9847c2f6 | 1249 | if (BITS_PER_WORD == 32) |
7cae975e RH |
1250 | { |
1251 | val = k[i]; | |
1252 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1253 | return GEN_INT (val); | |
1254 | } | |
1255 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
9847c2f6 | 1256 | else if (BITS_PER_WORD >= 64 && i == 0) |
7cae975e RH |
1257 | { |
1258 | val = k[! WORDS_BIG_ENDIAN]; | |
1259 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1260 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1261 | return GEN_INT (val); | |
1262 | } | |
9847c2f6 | 1263 | #endif |
47b34d40 JW |
1264 | else if (BITS_PER_WORD == 16) |
1265 | { | |
7cae975e RH |
1266 | val = k[i >> 1]; |
1267 | if ((i & 1) == !WORDS_BIG_ENDIAN) | |
1268 | val >>= 16; | |
1269 | val &= 0xffff; | |
1270 | return GEN_INT (val); | |
47b34d40 | 1271 | } |
7677ffa4 RK |
1272 | else |
1273 | abort (); | |
1632afca | 1274 | } |
a5559dbc RE |
1275 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1276 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1277 | && GET_MODE_BITSIZE (mode) > 64 | |
1278 | && GET_CODE (op) == CONST_DOUBLE) | |
5495cc55 RH |
1279 | { |
1280 | long k[4]; | |
1281 | REAL_VALUE_TYPE rv; | |
a5559dbc | 1282 | |
5495cc55 RH |
1283 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1284 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
a5559dbc | 1285 | |
5495cc55 RH |
1286 | if (BITS_PER_WORD == 32) |
1287 | { | |
1288 | val = k[i]; | |
1289 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1290 | return GEN_INT (val); | |
1291 | } | |
1292 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1293 | else if (BITS_PER_WORD >= 64 && i <= 1) | |
1294 | { | |
1295 | val = k[i*2 + ! WORDS_BIG_ENDIAN]; | |
1296 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1297 | val |= (HOST_WIDE_INT) k[i*2 + WORDS_BIG_ENDIAN] & 0xffffffff; | |
1298 | return GEN_INT (val); | |
1299 | } | |
1300 | #endif | |
1301 | else | |
1302 | abort (); | |
1303 | } | |
1632afca | 1304 | #else /* no REAL_ARITHMETIC */ |
23b2ce53 | 1305 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1306 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1307 | || flag_pretend_float) |
1308 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1309 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1310 | && GET_CODE (op) == CONST_DOUBLE) | |
7529ac93 CH |
1311 | { |
1312 | /* The constant is stored in the host's word-ordering, | |
1313 | but we want to access it in the target's word-ordering. Some | |
1314 | compilers don't like a conditional inside macro args, so we have two | |
1315 | copies of the return. */ | |
2fe02d7e | 1316 | #ifdef HOST_WORDS_BIG_ENDIAN |
7529ac93 CH |
1317 | return GEN_INT (i == WORDS_BIG_ENDIAN |
1318 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1319 | #else |
7529ac93 CH |
1320 | return GEN_INT (i != WORDS_BIG_ENDIAN |
1321 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1322 | #endif |
7529ac93 | 1323 | } |
1632afca | 1324 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1325 | |
1326 | /* Single word float is a little harder, since single- and double-word | |
1327 | values often do not have the same high-order bits. We have already | |
1328 | verified that we want the only defined word of the single-word value. */ | |
1632afca | 1329 | #ifdef REAL_ARITHMETIC |
9847c2f6 | 1330 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1331 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1332 | && GET_CODE (op) == CONST_DOUBLE) |
1333 | { | |
9847c2f6 | 1334 | long l; |
1632afca RS |
1335 | REAL_VALUE_TYPE rv; |
1336 | ||
1337 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1338 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
aa2ae679 | 1339 | |
7cae975e RH |
1340 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1341 | val = l; | |
1342 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
b5a3eb84 | 1343 | |
aa2ae679 JL |
1344 | if (BITS_PER_WORD == 16) |
1345 | { | |
7cae975e RH |
1346 | if ((i & 1) == !WORDS_BIG_ENDIAN) |
1347 | val >>= 16; | |
1348 | val &= 0xffff; | |
aa2ae679 | 1349 | } |
7cae975e RH |
1350 | |
1351 | return GEN_INT (val); | |
1632afca RS |
1352 | } |
1353 | #else | |
23b2ce53 | 1354 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1355 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 | 1356 | || flag_pretend_float) |
e01a2cec | 1357 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
23b2ce53 RS |
1358 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1359 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1360 | && GET_CODE (op) == CONST_DOUBLE) | |
1361 | { | |
1362 | double d; | |
906c4e36 | 1363 | union {float f; HOST_WIDE_INT i; } u; |
23b2ce53 RS |
1364 | |
1365 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1366 | ||
1367 | u.f = d; | |
906c4e36 | 1368 | return GEN_INT (u.i); |
23b2ce53 | 1369 | } |
e01a2cec RK |
1370 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1371 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1372 | || flag_pretend_float) | |
1373 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1374 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1375 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1376 | && GET_CODE (op) == CONST_DOUBLE) | |
1377 | { | |
1378 | double d; | |
1379 | union {double d; HOST_WIDE_INT i; } u; | |
1380 | ||
1381 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1382 | ||
1383 | u.d = d; | |
1384 | return GEN_INT (u.i); | |
1385 | } | |
1632afca | 1386 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1387 | |
1388 | /* The only remaining cases that we can handle are integers. | |
1389 | Convert to proper endianness now since these cases need it. | |
1390 | At this point, i == 0 means the low-order word. | |
1391 | ||
2d4f57f8 RK |
1392 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1393 | in general. However, if OP is (const_int 0), we can just return | |
1394 | it for any word. */ | |
1395 | ||
1396 | if (op == const0_rtx) | |
1397 | return op; | |
23b2ce53 RS |
1398 | |
1399 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1400 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1401 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1402 | return 0; |
1403 | ||
1404 | if (WORDS_BIG_ENDIAN) | |
1405 | i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i; | |
1406 | ||
1407 | /* Find out which word on the host machine this value is in and get | |
1408 | it from the constant. */ | |
1409 | val = (i / size_ratio == 0 | |
1410 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) | |
1411 | : (GET_CODE (op) == CONST_INT | |
1412 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1413 | ||
3f518020 | 1414 | /* Get the value we want into the low bits of val. */ |
906c4e36 | 1415 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
3f518020 JL |
1416 | val = ((val >> ((i % size_ratio) * BITS_PER_WORD))); |
1417 | ||
7e4ce834 | 1418 | val = trunc_int_for_mode (val, word_mode); |
23b2ce53 | 1419 | |
906c4e36 | 1420 | return GEN_INT (val); |
23b2ce53 RS |
1421 | } |
1422 | ||
1423 | /* Similar to `operand_subword', but never return 0. If we can't extract | |
1424 | the required subword, put OP into a register and try again. If that fails, | |
1425 | abort. We always validate the address in this case. It is not valid | |
1426 | to call this function after reload; it is mostly meant for RTL | |
1427 | generation. | |
1428 | ||
1429 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1430 | ||
1431 | rtx | |
1432 | operand_subword_force (op, i, mode) | |
1433 | rtx op; | |
770ae6cc | 1434 | unsigned int i; |
23b2ce53 RS |
1435 | enum machine_mode mode; |
1436 | { | |
1437 | rtx result = operand_subword (op, i, 1, mode); | |
1438 | ||
1439 | if (result) | |
1440 | return result; | |
1441 | ||
1442 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1443 | { |
1444 | /* If this is a register which can not be accessed by words, copy it | |
1445 | to a pseudo register. */ | |
1446 | if (GET_CODE (op) == REG) | |
1447 | op = copy_to_reg (op); | |
1448 | else | |
1449 | op = force_reg (mode, op); | |
1450 | } | |
23b2ce53 RS |
1451 | |
1452 | result = operand_subword (op, i, 1, mode); | |
1453 | if (result == 0) | |
1454 | abort (); | |
1455 | ||
1456 | return result; | |
1457 | } | |
1458 | \f | |
1459 | /* Given a compare instruction, swap the operands. | |
1460 | A test instruction is changed into a compare of 0 against the operand. */ | |
1461 | ||
1462 | void | |
1463 | reverse_comparison (insn) | |
1464 | rtx insn; | |
1465 | { | |
1466 | rtx body = PATTERN (insn); | |
1467 | rtx comp; | |
1468 | ||
1469 | if (GET_CODE (body) == SET) | |
1470 | comp = SET_SRC (body); | |
1471 | else | |
1472 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1473 | ||
1474 | if (GET_CODE (comp) == COMPARE) | |
1475 | { | |
1476 | rtx op0 = XEXP (comp, 0); | |
1477 | rtx op1 = XEXP (comp, 1); | |
1478 | XEXP (comp, 0) = op1; | |
1479 | XEXP (comp, 1) = op0; | |
1480 | } | |
1481 | else | |
1482 | { | |
c5c76735 JL |
1483 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1484 | CONST0_RTX (GET_MODE (comp)), comp); | |
23b2ce53 RS |
1485 | if (GET_CODE (body) == SET) |
1486 | SET_SRC (body) = new; | |
1487 | else | |
1488 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1489 | } | |
1490 | } | |
1491 | \f | |
1492 | /* Return a memory reference like MEMREF, but with its mode changed | |
1493 | to MODE and its address changed to ADDR. | |
1494 | (VOIDmode means don't change the mode. | |
1495 | NULL for ADDR means don't change the address.) */ | |
1496 | ||
1497 | rtx | |
1498 | change_address (memref, mode, addr) | |
1499 | rtx memref; | |
1500 | enum machine_mode mode; | |
1501 | rtx addr; | |
1502 | { | |
1503 | rtx new; | |
1504 | ||
1505 | if (GET_CODE (memref) != MEM) | |
1506 | abort (); | |
1507 | if (mode == VOIDmode) | |
1508 | mode = GET_MODE (memref); | |
1509 | if (addr == 0) | |
1510 | addr = XEXP (memref, 0); | |
1511 | ||
1512 | /* If reload is in progress or has completed, ADDR must be valid. | |
1513 | Otherwise, we can call memory_address to make it valid. */ | |
1514 | if (reload_completed || reload_in_progress) | |
1515 | { | |
1516 | if (! memory_address_p (mode, addr)) | |
1517 | abort (); | |
1518 | } | |
1519 | else | |
1520 | addr = memory_address (mode, addr); | |
1521 | ||
9b04c6a8 RK |
1522 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1523 | return memref; | |
1524 | ||
3b80f6ca | 1525 | new = gen_rtx_MEM (mode, addr); |
23b2ce53 | 1526 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (memref); |
c6df88cb | 1527 | MEM_COPY_ATTRIBUTES (new, memref); |
d3707adb | 1528 | MEM_ALIAS_SET (new) = MEM_ALIAS_SET (memref); |
23b2ce53 RS |
1529 | return new; |
1530 | } | |
1531 | \f | |
1532 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1533 | ||
1534 | rtx | |
1535 | gen_label_rtx () | |
1536 | { | |
ca695ac9 JB |
1537 | register rtx label; |
1538 | ||
b93a436e | 1539 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
8cd0faaf | 1540 | NULL_RTX, label_num++, NULL_PTR, NULL_PTR); |
ca695ac9 | 1541 | |
23b2ce53 | 1542 | LABEL_NUSES (label) = 0; |
8cd0faaf | 1543 | LABEL_ALTERNATE_NAME (label) = NULL; |
23b2ce53 RS |
1544 | return label; |
1545 | } | |
1546 | \f | |
1547 | /* For procedure integration. */ | |
1548 | ||
23b2ce53 | 1549 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 1550 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
1551 | Used for an inline-procedure after copying the insn chain. */ |
1552 | ||
1553 | void | |
1554 | set_new_first_and_last_insn (first, last) | |
1555 | rtx first, last; | |
1556 | { | |
86fe05e0 RK |
1557 | rtx insn; |
1558 | ||
23b2ce53 RS |
1559 | first_insn = first; |
1560 | last_insn = last; | |
86fe05e0 RK |
1561 | cur_insn_uid = 0; |
1562 | ||
1563 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1564 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1565 | ||
1566 | cur_insn_uid++; | |
23b2ce53 RS |
1567 | } |
1568 | ||
1569 | /* Set the range of label numbers found in the current function. | |
1570 | This is used when belatedly compiling an inline function. */ | |
1571 | ||
1572 | void | |
1573 | set_new_first_and_last_label_num (first, last) | |
1574 | int first, last; | |
1575 | { | |
1576 | base_label_num = label_num; | |
1577 | first_label_num = first; | |
1578 | last_label_num = last; | |
1579 | } | |
49ad7cfa BS |
1580 | |
1581 | /* Set the last label number found in the current function. | |
1582 | This is used when belatedly compiling an inline function. */ | |
23b2ce53 RS |
1583 | |
1584 | void | |
49ad7cfa BS |
1585 | set_new_last_label_num (last) |
1586 | int last; | |
23b2ce53 | 1587 | { |
49ad7cfa BS |
1588 | base_label_num = label_num; |
1589 | last_label_num = last; | |
23b2ce53 | 1590 | } |
49ad7cfa | 1591 | \f |
23b2ce53 RS |
1592 | /* Restore all variables describing the current status from the structure *P. |
1593 | This is used after a nested function. */ | |
1594 | ||
1595 | void | |
1596 | restore_emit_status (p) | |
272df862 | 1597 | struct function *p ATTRIBUTE_UNUSED; |
23b2ce53 | 1598 | { |
457a2d9c | 1599 | last_label_num = 0; |
49ad7cfa | 1600 | clear_emit_caches (); |
23b2ce53 | 1601 | } |
e2ecd91c | 1602 | |
21cd906e | 1603 | /* Clear out all parts of the state in F that can safely be discarded |
e2ecd91c | 1604 | after the function has been compiled, to let garbage collection |
0a8a198c | 1605 | reclaim the memory. */ |
21cd906e | 1606 | |
e2ecd91c | 1607 | void |
0a8a198c | 1608 | free_emit_status (f) |
e2ecd91c BS |
1609 | struct function *f; |
1610 | { | |
1611 | free (f->emit->x_regno_reg_rtx); | |
1612 | free (f->emit->regno_pointer_flag); | |
1613 | free (f->emit->regno_pointer_align); | |
fa51b01b RH |
1614 | free (f->emit); |
1615 | f->emit = NULL; | |
e2ecd91c | 1616 | } |
23b2ce53 | 1617 | \f |
d1b81779 GK |
1618 | /* Go through all the RTL insn bodies and copy any invalid shared |
1619 | structure. This routine should only be called once. */ | |
23b2ce53 RS |
1620 | |
1621 | void | |
d1b81779 GK |
1622 | unshare_all_rtl (fndecl, insn) |
1623 | tree fndecl; | |
1624 | rtx insn; | |
23b2ce53 | 1625 | { |
d1b81779 | 1626 | tree decl; |
23b2ce53 | 1627 | |
d1b81779 GK |
1628 | /* Make sure that virtual parameters are not shared. */ |
1629 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
1630 | { | |
1631 | copy_rtx_if_shared (DECL_RTL (decl)); | |
1632 | } | |
1633 | ||
1634 | /* Unshare just about everything else. */ | |
1635 | unshare_all_rtl_1 (insn); | |
1636 | ||
23b2ce53 RS |
1637 | /* Make sure the addresses of stack slots found outside the insn chain |
1638 | (such as, in DECL_RTL of a variable) are not shared | |
1639 | with the insn chain. | |
1640 | ||
1641 | This special care is necessary when the stack slot MEM does not | |
1642 | actually appear in the insn chain. If it does appear, its address | |
1643 | is unshared from all else at that point. */ | |
23b2ce53 RS |
1644 | copy_rtx_if_shared (stack_slot_list); |
1645 | } | |
1646 | ||
d1b81779 GK |
1647 | /* Go through all the RTL insn bodies and copy any invalid shared |
1648 | structure, again. This is a fairly expensive thing to do so it | |
1649 | should be done sparingly. */ | |
1650 | ||
1651 | void | |
1652 | unshare_all_rtl_again (insn) | |
1653 | rtx insn; | |
1654 | { | |
1655 | rtx p; | |
1656 | for (p = insn; p; p = NEXT_INSN (p)) | |
1657 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
1658 | { | |
1659 | reset_used_flags (PATTERN (p)); | |
1660 | reset_used_flags (REG_NOTES (p)); | |
1661 | reset_used_flags (LOG_LINKS (p)); | |
1662 | } | |
1663 | unshare_all_rtl_1 (insn); | |
1664 | } | |
1665 | ||
1666 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1667 | Assumes the mark bits are cleared at entry. */ | |
1668 | ||
1669 | static void | |
1670 | unshare_all_rtl_1 (insn) | |
1671 | rtx insn; | |
1672 | { | |
1673 | for (; insn; insn = NEXT_INSN (insn)) | |
1674 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1675 | { | |
1676 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1677 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1678 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1679 | } | |
1680 | } | |
1681 | ||
23b2ce53 RS |
1682 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1683 | Recursively does the same for subexpressions. */ | |
1684 | ||
1685 | rtx | |
1686 | copy_rtx_if_shared (orig) | |
1687 | rtx orig; | |
1688 | { | |
1689 | register rtx x = orig; | |
1690 | register int i; | |
1691 | register enum rtx_code code; | |
6f7d635c | 1692 | register const char *format_ptr; |
23b2ce53 RS |
1693 | int copied = 0; |
1694 | ||
1695 | if (x == 0) | |
1696 | return 0; | |
1697 | ||
1698 | code = GET_CODE (x); | |
1699 | ||
1700 | /* These types may be freely shared. */ | |
1701 | ||
1702 | switch (code) | |
1703 | { | |
1704 | case REG: | |
1705 | case QUEUED: | |
1706 | case CONST_INT: | |
1707 | case CONST_DOUBLE: | |
1708 | case SYMBOL_REF: | |
1709 | case CODE_LABEL: | |
1710 | case PC: | |
1711 | case CC0: | |
1712 | case SCRATCH: | |
0f41302f | 1713 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
1714 | return x; |
1715 | ||
b851ea09 RK |
1716 | case CONST: |
1717 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
1718 | a LABEL_REF, it isn't sharable. */ | |
1719 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1720 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1721 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1722 | return x; | |
1723 | break; | |
1724 | ||
23b2ce53 RS |
1725 | case INSN: |
1726 | case JUMP_INSN: | |
1727 | case CALL_INSN: | |
1728 | case NOTE: | |
23b2ce53 RS |
1729 | case BARRIER: |
1730 | /* The chain of insns is not being copied. */ | |
1731 | return x; | |
1732 | ||
1733 | case MEM: | |
83512665 JL |
1734 | /* A MEM is allowed to be shared if its address is constant. |
1735 | ||
1736 | We used to allow sharing of MEMs which referenced | |
1737 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but | |
1738 | that can lose. instantiate_virtual_regs will not unshare | |
1739 | the MEMs, and combine may change the structure of the address | |
1740 | because it looks safe and profitable in one context, but | |
1741 | in some other context it creates unrecognizable RTL. */ | |
1742 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
23b2ce53 RS |
1743 | return x; |
1744 | ||
e9a25f70 JL |
1745 | break; |
1746 | ||
1747 | default: | |
1748 | break; | |
23b2ce53 RS |
1749 | } |
1750 | ||
1751 | /* This rtx may not be shared. If it has already been seen, | |
1752 | replace it with a copy of itself. */ | |
1753 | ||
1754 | if (x->used) | |
1755 | { | |
1756 | register rtx copy; | |
1757 | ||
1758 | copy = rtx_alloc (code); | |
4c9a05bc RK |
1759 | bcopy ((char *) x, (char *) copy, |
1760 | (sizeof (*copy) - sizeof (copy->fld) | |
1761 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
1762 | x = copy; |
1763 | copied = 1; | |
1764 | } | |
1765 | x->used = 1; | |
1766 | ||
1767 | /* Now scan the subexpressions recursively. | |
1768 | We can store any replaced subexpressions directly into X | |
1769 | since we know X is not shared! Any vectors in X | |
1770 | must be copied if X was copied. */ | |
1771 | ||
1772 | format_ptr = GET_RTX_FORMAT (code); | |
1773 | ||
1774 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1775 | { | |
1776 | switch (*format_ptr++) | |
1777 | { | |
1778 | case 'e': | |
1779 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
1780 | break; | |
1781 | ||
1782 | case 'E': | |
1783 | if (XVEC (x, i) != NULL) | |
1784 | { | |
1785 | register int j; | |
f0722107 | 1786 | int len = XVECLEN (x, i); |
23b2ce53 | 1787 | |
f0722107 | 1788 | if (copied && len > 0) |
8f985ec4 | 1789 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
f0722107 RS |
1790 | for (j = 0; j < len; j++) |
1791 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
1792 | } |
1793 | break; | |
1794 | } | |
1795 | } | |
1796 | return x; | |
1797 | } | |
1798 | ||
1799 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
1800 | to look for shared sub-parts. */ | |
1801 | ||
1802 | void | |
1803 | reset_used_flags (x) | |
1804 | rtx x; | |
1805 | { | |
1806 | register int i, j; | |
1807 | register enum rtx_code code; | |
6f7d635c | 1808 | register const char *format_ptr; |
23b2ce53 RS |
1809 | |
1810 | if (x == 0) | |
1811 | return; | |
1812 | ||
1813 | code = GET_CODE (x); | |
1814 | ||
9faa82d8 | 1815 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
1816 | for them. */ |
1817 | ||
1818 | switch (code) | |
1819 | { | |
1820 | case REG: | |
1821 | case QUEUED: | |
1822 | case CONST_INT: | |
1823 | case CONST_DOUBLE: | |
1824 | case SYMBOL_REF: | |
1825 | case CODE_LABEL: | |
1826 | case PC: | |
1827 | case CC0: | |
1828 | return; | |
1829 | ||
1830 | case INSN: | |
1831 | case JUMP_INSN: | |
1832 | case CALL_INSN: | |
1833 | case NOTE: | |
1834 | case LABEL_REF: | |
1835 | case BARRIER: | |
1836 | /* The chain of insns is not being copied. */ | |
1837 | return; | |
e9a25f70 JL |
1838 | |
1839 | default: | |
1840 | break; | |
23b2ce53 RS |
1841 | } |
1842 | ||
1843 | x->used = 0; | |
1844 | ||
1845 | format_ptr = GET_RTX_FORMAT (code); | |
1846 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1847 | { | |
1848 | switch (*format_ptr++) | |
1849 | { | |
1850 | case 'e': | |
1851 | reset_used_flags (XEXP (x, i)); | |
1852 | break; | |
1853 | ||
1854 | case 'E': | |
1855 | for (j = 0; j < XVECLEN (x, i); j++) | |
1856 | reset_used_flags (XVECEXP (x, i, j)); | |
1857 | break; | |
1858 | } | |
1859 | } | |
1860 | } | |
1861 | \f | |
1862 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
1863 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
1864 | OTHER must be valid as a SET_DEST. */ | |
1865 | ||
1866 | rtx | |
1867 | make_safe_from (x, other) | |
1868 | rtx x, other; | |
1869 | { | |
1870 | while (1) | |
1871 | switch (GET_CODE (other)) | |
1872 | { | |
1873 | case SUBREG: | |
1874 | other = SUBREG_REG (other); | |
1875 | break; | |
1876 | case STRICT_LOW_PART: | |
1877 | case SIGN_EXTEND: | |
1878 | case ZERO_EXTEND: | |
1879 | other = XEXP (other, 0); | |
1880 | break; | |
1881 | default: | |
1882 | goto done; | |
1883 | } | |
1884 | done: | |
1885 | if ((GET_CODE (other) == MEM | |
1886 | && ! CONSTANT_P (x) | |
1887 | && GET_CODE (x) != REG | |
1888 | && GET_CODE (x) != SUBREG) | |
1889 | || (GET_CODE (other) == REG | |
1890 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
1891 | || reg_mentioned_p (other, x)))) | |
1892 | { | |
1893 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
1894 | emit_move_insn (temp, x); | |
1895 | return temp; | |
1896 | } | |
1897 | return x; | |
1898 | } | |
1899 | \f | |
1900 | /* Emission of insns (adding them to the doubly-linked list). */ | |
1901 | ||
1902 | /* Return the first insn of the current sequence or current function. */ | |
1903 | ||
1904 | rtx | |
1905 | get_insns () | |
1906 | { | |
1907 | return first_insn; | |
1908 | } | |
1909 | ||
1910 | /* Return the last insn emitted in current sequence or current function. */ | |
1911 | ||
1912 | rtx | |
1913 | get_last_insn () | |
1914 | { | |
1915 | return last_insn; | |
1916 | } | |
1917 | ||
1918 | /* Specify a new insn as the last in the chain. */ | |
1919 | ||
1920 | void | |
1921 | set_last_insn (insn) | |
1922 | rtx insn; | |
1923 | { | |
1924 | if (NEXT_INSN (insn) != 0) | |
1925 | abort (); | |
1926 | last_insn = insn; | |
1927 | } | |
1928 | ||
1929 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
1930 | ||
1931 | rtx | |
1932 | get_last_insn_anywhere () | |
1933 | { | |
1934 | struct sequence_stack *stack; | |
1935 | if (last_insn) | |
1936 | return last_insn; | |
49ad7cfa | 1937 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
1938 | if (stack->last != 0) |
1939 | return stack->last; | |
1940 | return 0; | |
1941 | } | |
1942 | ||
1943 | /* Return a number larger than any instruction's uid in this function. */ | |
1944 | ||
1945 | int | |
1946 | get_max_uid () | |
1947 | { | |
1948 | return cur_insn_uid; | |
1949 | } | |
aeeeda03 | 1950 | |
673b5311 MM |
1951 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
1952 | ||
aeeeda03 | 1953 | void |
673b5311 MM |
1954 | renumber_insns (stream) |
1955 | FILE *stream; | |
aeeeda03 MM |
1956 | { |
1957 | rtx insn; | |
aeeeda03 | 1958 | |
673b5311 MM |
1959 | /* If we're not supposed to renumber instructions, don't. */ |
1960 | if (!flag_renumber_insns) | |
1961 | return; | |
1962 | ||
aeeeda03 MM |
1963 | /* If there aren't that many instructions, then it's not really |
1964 | worth renumbering them. */ | |
673b5311 | 1965 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
aeeeda03 MM |
1966 | return; |
1967 | ||
1968 | cur_insn_uid = 1; | |
1969 | ||
1970 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
673b5311 MM |
1971 | { |
1972 | if (stream) | |
1973 | fprintf (stream, "Renumbering insn %d to %d\n", | |
1974 | INSN_UID (insn), cur_insn_uid); | |
1975 | INSN_UID (insn) = cur_insn_uid++; | |
1976 | } | |
aeeeda03 | 1977 | } |
23b2ce53 RS |
1978 | \f |
1979 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
1980 | of the sequence. */ | |
1981 | ||
1982 | rtx | |
1983 | next_insn (insn) | |
1984 | rtx insn; | |
1985 | { | |
1986 | if (insn) | |
1987 | { | |
1988 | insn = NEXT_INSN (insn); | |
1989 | if (insn && GET_CODE (insn) == INSN | |
1990 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
1991 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
1992 | } | |
1993 | ||
1994 | return insn; | |
1995 | } | |
1996 | ||
1997 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
1998 | of the sequence. */ | |
1999 | ||
2000 | rtx | |
2001 | previous_insn (insn) | |
2002 | rtx insn; | |
2003 | { | |
2004 | if (insn) | |
2005 | { | |
2006 | insn = PREV_INSN (insn); | |
2007 | if (insn && GET_CODE (insn) == INSN | |
2008 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2009 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2010 | } | |
2011 | ||
2012 | return insn; | |
2013 | } | |
2014 | ||
2015 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2016 | look inside SEQUENCEs. */ | |
2017 | ||
2018 | rtx | |
2019 | next_nonnote_insn (insn) | |
2020 | rtx insn; | |
2021 | { | |
2022 | while (insn) | |
2023 | { | |
2024 | insn = NEXT_INSN (insn); | |
2025 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2026 | break; | |
2027 | } | |
2028 | ||
2029 | return insn; | |
2030 | } | |
2031 | ||
2032 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2033 | not look inside SEQUENCEs. */ | |
2034 | ||
2035 | rtx | |
2036 | prev_nonnote_insn (insn) | |
2037 | rtx insn; | |
2038 | { | |
2039 | while (insn) | |
2040 | { | |
2041 | insn = PREV_INSN (insn); | |
2042 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2043 | break; | |
2044 | } | |
2045 | ||
2046 | return insn; | |
2047 | } | |
2048 | ||
2049 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2050 | or 0, if there is none. This routine does not look inside | |
0f41302f | 2051 | SEQUENCEs. */ |
23b2ce53 RS |
2052 | |
2053 | rtx | |
2054 | next_real_insn (insn) | |
2055 | rtx insn; | |
2056 | { | |
2057 | while (insn) | |
2058 | { | |
2059 | insn = NEXT_INSN (insn); | |
2060 | if (insn == 0 || GET_CODE (insn) == INSN | |
2061 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2062 | break; | |
2063 | } | |
2064 | ||
2065 | return insn; | |
2066 | } | |
2067 | ||
2068 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2069 | or 0, if there is none. This routine does not look inside | |
2070 | SEQUENCEs. */ | |
2071 | ||
2072 | rtx | |
2073 | prev_real_insn (insn) | |
2074 | rtx insn; | |
2075 | { | |
2076 | while (insn) | |
2077 | { | |
2078 | insn = PREV_INSN (insn); | |
2079 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2080 | || GET_CODE (insn) == JUMP_INSN) | |
2081 | break; | |
2082 | } | |
2083 | ||
2084 | return insn; | |
2085 | } | |
2086 | ||
2087 | /* Find the next insn after INSN that really does something. This routine | |
2088 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2089 | same as next_real_insn. */ | |
2090 | ||
69732dcb RH |
2091 | int |
2092 | active_insn_p (insn) | |
2093 | rtx insn; | |
2094 | { | |
2095 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2096 | || (GET_CODE (insn) == INSN | |
2097 | && (! reload_completed | |
2098 | || (GET_CODE (PATTERN (insn)) != USE | |
2099 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2100 | } | |
2101 | ||
23b2ce53 RS |
2102 | rtx |
2103 | next_active_insn (insn) | |
2104 | rtx insn; | |
2105 | { | |
2106 | while (insn) | |
2107 | { | |
2108 | insn = NEXT_INSN (insn); | |
69732dcb | 2109 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2110 | break; |
2111 | } | |
2112 | ||
2113 | return insn; | |
2114 | } | |
2115 | ||
2116 | /* Find the last insn before INSN that really does something. This routine | |
2117 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2118 | same as prev_real_insn. */ | |
2119 | ||
2120 | rtx | |
2121 | prev_active_insn (insn) | |
2122 | rtx insn; | |
2123 | { | |
2124 | while (insn) | |
2125 | { | |
2126 | insn = PREV_INSN (insn); | |
69732dcb | 2127 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2128 | break; |
2129 | } | |
2130 | ||
2131 | return insn; | |
2132 | } | |
2133 | ||
2134 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2135 | ||
2136 | rtx | |
2137 | next_label (insn) | |
2138 | rtx insn; | |
2139 | { | |
2140 | while (insn) | |
2141 | { | |
2142 | insn = NEXT_INSN (insn); | |
2143 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2144 | break; | |
2145 | } | |
2146 | ||
2147 | return insn; | |
2148 | } | |
2149 | ||
2150 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2151 | ||
2152 | rtx | |
2153 | prev_label (insn) | |
2154 | rtx insn; | |
2155 | { | |
2156 | while (insn) | |
2157 | { | |
2158 | insn = PREV_INSN (insn); | |
2159 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2160 | break; | |
2161 | } | |
2162 | ||
2163 | return insn; | |
2164 | } | |
2165 | \f | |
2166 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
2167 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2168 | and REG_CC_USER notes so we can find it. */ | |
2169 | ||
2170 | void | |
2171 | link_cc0_insns (insn) | |
2172 | rtx insn; | |
2173 | { | |
2174 | rtx user = next_nonnote_insn (insn); | |
2175 | ||
2176 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2177 | user = XVECEXP (PATTERN (user), 0, 0); | |
2178 | ||
c5c76735 JL |
2179 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2180 | REG_NOTES (user)); | |
3b80f6ca | 2181 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
2182 | } |
2183 | ||
23b2ce53 RS |
2184 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2185 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2186 | applied to the result of this function should yield INSN). | |
2187 | ||
2188 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2189 | is present, it contains the insn that uses CC0. | |
2190 | ||
2191 | Return 0 if we can't find the insn. */ | |
2192 | ||
2193 | rtx | |
2194 | next_cc0_user (insn) | |
2195 | rtx insn; | |
2196 | { | |
906c4e36 | 2197 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
2198 | |
2199 | if (note) | |
2200 | return XEXP (note, 0); | |
2201 | ||
2202 | insn = next_nonnote_insn (insn); | |
2203 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2204 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2205 | ||
2206 | if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2207 | && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
2208 | return insn; | |
2209 | ||
2210 | return 0; | |
2211 | } | |
2212 | ||
2213 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2214 | note, it is the previous insn. */ | |
2215 | ||
2216 | rtx | |
2217 | prev_cc0_setter (insn) | |
2218 | rtx insn; | |
2219 | { | |
906c4e36 | 2220 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
2221 | |
2222 | if (note) | |
2223 | return XEXP (note, 0); | |
2224 | ||
2225 | insn = prev_nonnote_insn (insn); | |
2226 | if (! sets_cc0_p (PATTERN (insn))) | |
2227 | abort (); | |
2228 | ||
2229 | return insn; | |
2230 | } | |
2231 | #endif | |
2232 | \f | |
2233 | /* Try splitting insns that can be split for better scheduling. | |
2234 | PAT is the pattern which might split. | |
2235 | TRIAL is the insn providing PAT. | |
11147ebe | 2236 | LAST is non-zero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
2237 | |
2238 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 2239 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
2240 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2241 | ||
2242 | rtx | |
11147ebe | 2243 | try_split (pat, trial, last) |
23b2ce53 | 2244 | rtx pat, trial; |
11147ebe | 2245 | int last; |
23b2ce53 RS |
2246 | { |
2247 | rtx before = PREV_INSN (trial); | |
2248 | rtx after = NEXT_INSN (trial); | |
2249 | rtx seq = split_insns (pat, trial); | |
2250 | int has_barrier = 0; | |
2251 | rtx tem; | |
2252 | ||
2253 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2254 | We may need to handle this specially. */ | |
2255 | if (after && GET_CODE (after) == BARRIER) | |
2256 | { | |
2257 | has_barrier = 1; | |
2258 | after = NEXT_INSN (after); | |
2259 | } | |
2260 | ||
2261 | if (seq) | |
2262 | { | |
2263 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2264 | The latter case will normally arise only when being done so that | |
2265 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2266 | if (GET_CODE (seq) == SEQUENCE) | |
2267 | { | |
2268 | /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in | |
2269 | SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero, | |
2270 | increment the usage count so we don't delete the label. */ | |
2271 | int i; | |
2272 | ||
2273 | if (GET_CODE (trial) == JUMP_INSN) | |
2274 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2275 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2276 | { | |
2277 | JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial); | |
2278 | ||
2279 | if (JUMP_LABEL (trial)) | |
2280 | LABEL_NUSES (JUMP_LABEL (trial))++; | |
2281 | } | |
2282 | ||
2283 | tem = emit_insn_after (seq, before); | |
2284 | ||
2285 | delete_insn (trial); | |
2286 | if (has_barrier) | |
2287 | emit_barrier_after (tem); | |
11147ebe RK |
2288 | |
2289 | /* Recursively call try_split for each new insn created; by the | |
2290 | time control returns here that insn will be fully split, so | |
2291 | set LAST and continue from the insn after the one returned. | |
f4a3cd05 | 2292 | We can't use next_active_insn here since AFTER may be a note. |
23886015 | 2293 | Ignore deleted insns, which can be occur if not optimizing. */ |
11147ebe RK |
2294 | for (tem = NEXT_INSN (before); tem != after; |
2295 | tem = NEXT_INSN (tem)) | |
23886015 RH |
2296 | if (! INSN_DELETED_P (tem) |
2297 | && GET_RTX_CLASS (GET_CODE (tem)) == 'i') | |
f4a3cd05 | 2298 | tem = try_split (PATTERN (tem), tem, 1); |
23b2ce53 RS |
2299 | } |
2300 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2301 | else if (rtx_equal_p (seq, pat)) | |
2302 | return trial; | |
2303 | else | |
2304 | { | |
2305 | PATTERN (trial) = seq; | |
2306 | INSN_CODE (trial) = -1; | |
11147ebe | 2307 | try_split (seq, trial, last); |
23b2ce53 RS |
2308 | } |
2309 | ||
11147ebe RK |
2310 | /* Return either the first or the last insn, depending on which was |
2311 | requested. */ | |
ba52f355 CP |
2312 | return last |
2313 | ? (after ? prev_active_insn (after) : last_insn) | |
2314 | : next_active_insn (before); | |
23b2ce53 RS |
2315 | } |
2316 | ||
2317 | return trial; | |
2318 | } | |
2319 | \f | |
2320 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 2321 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
2322 | |
2323 | rtx | |
4b1f5e8c | 2324 | make_insn_raw (pattern) |
23b2ce53 | 2325 | rtx pattern; |
23b2ce53 RS |
2326 | { |
2327 | register rtx insn; | |
2328 | ||
43127294 | 2329 | /* If in RTL generation phase, see if FREE_INSN can be used. */ |
a3770a81 | 2330 | if (!ggc_p && free_insn != 0 && rtx_equal_function_value_matters) |
43127294 RK |
2331 | { |
2332 | insn = free_insn; | |
2333 | free_insn = NEXT_INSN (free_insn); | |
2334 | PUT_CODE (insn, INSN); | |
2335 | } | |
2336 | else | |
2337 | insn = rtx_alloc (INSN); | |
23b2ce53 | 2338 | |
43127294 | 2339 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2340 | PATTERN (insn) = pattern; |
2341 | INSN_CODE (insn) = -1; | |
1632afca RS |
2342 | LOG_LINKS (insn) = NULL; |
2343 | REG_NOTES (insn) = NULL; | |
23b2ce53 | 2344 | |
47984720 NC |
2345 | #ifdef ENABLE_RTL_CHECKING |
2346 | if (insn | |
2347 | && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2348 | && (returnjump_p (insn) | |
2349 | || (GET_CODE (insn) == SET | |
2350 | && SET_DEST (insn) == pc_rtx))) | |
2351 | { | |
2352 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2353 | debug_rtx (insn); | |
2354 | } | |
2355 | #endif | |
2356 | ||
23b2ce53 RS |
2357 | return insn; |
2358 | } | |
2359 | ||
2360 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2361 | ||
2362 | static rtx | |
4b1f5e8c | 2363 | make_jump_insn_raw (pattern) |
23b2ce53 | 2364 | rtx pattern; |
23b2ce53 RS |
2365 | { |
2366 | register rtx insn; | |
2367 | ||
4b1f5e8c | 2368 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 2369 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2370 | |
2371 | PATTERN (insn) = pattern; | |
2372 | INSN_CODE (insn) = -1; | |
1632afca RS |
2373 | LOG_LINKS (insn) = NULL; |
2374 | REG_NOTES (insn) = NULL; | |
2375 | JUMP_LABEL (insn) = NULL; | |
23b2ce53 RS |
2376 | |
2377 | return insn; | |
2378 | } | |
aff507f4 RK |
2379 | |
2380 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2381 | ||
2382 | static rtx | |
2383 | make_call_insn_raw (pattern) | |
2384 | rtx pattern; | |
2385 | { | |
2386 | register rtx insn; | |
2387 | ||
2388 | insn = rtx_alloc (CALL_INSN); | |
2389 | INSN_UID (insn) = cur_insn_uid++; | |
2390 | ||
2391 | PATTERN (insn) = pattern; | |
2392 | INSN_CODE (insn) = -1; | |
2393 | LOG_LINKS (insn) = NULL; | |
2394 | REG_NOTES (insn) = NULL; | |
2395 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2396 | ||
2397 | return insn; | |
2398 | } | |
23b2ce53 RS |
2399 | \f |
2400 | /* Add INSN to the end of the doubly-linked list. | |
2401 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2402 | ||
2403 | void | |
2404 | add_insn (insn) | |
2405 | register rtx insn; | |
2406 | { | |
2407 | PREV_INSN (insn) = last_insn; | |
2408 | NEXT_INSN (insn) = 0; | |
2409 | ||
2410 | if (NULL != last_insn) | |
2411 | NEXT_INSN (last_insn) = insn; | |
2412 | ||
2413 | if (NULL == first_insn) | |
2414 | first_insn = insn; | |
2415 | ||
2416 | last_insn = insn; | |
2417 | } | |
2418 | ||
a0ae8e8d RK |
2419 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2420 | the next should be the only functions called to insert an insn once | |
ba213285 | 2421 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 2422 | SEQUENCE. */ |
23b2ce53 RS |
2423 | |
2424 | void | |
2425 | add_insn_after (insn, after) | |
2426 | rtx insn, after; | |
2427 | { | |
2428 | rtx next = NEXT_INSN (after); | |
2429 | ||
6782074d | 2430 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
2431 | abort (); |
2432 | ||
23b2ce53 RS |
2433 | NEXT_INSN (insn) = next; |
2434 | PREV_INSN (insn) = after; | |
2435 | ||
2436 | if (next) | |
2437 | { | |
2438 | PREV_INSN (next) = insn; | |
2439 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2440 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2441 | } | |
2442 | else if (last_insn == after) | |
2443 | last_insn = insn; | |
2444 | else | |
2445 | { | |
49ad7cfa | 2446 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
2447 | /* Scan all pending sequences too. */ |
2448 | for (; stack; stack = stack->next) | |
2449 | if (after == stack->last) | |
fef0509b RK |
2450 | { |
2451 | stack->last = insn; | |
2452 | break; | |
2453 | } | |
a0ae8e8d RK |
2454 | |
2455 | if (stack == 0) | |
2456 | abort (); | |
23b2ce53 RS |
2457 | } |
2458 | ||
2459 | NEXT_INSN (after) = insn; | |
2460 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2461 | { | |
2462 | rtx sequence = PATTERN (after); | |
2463 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2464 | } | |
2465 | } | |
2466 | ||
a0ae8e8d RK |
2467 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2468 | the previous should be the only functions called to insert an insn once | |
ba213285 | 2469 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
2470 | SEQUENCE. */ |
2471 | ||
2472 | void | |
2473 | add_insn_before (insn, before) | |
2474 | rtx insn, before; | |
2475 | { | |
2476 | rtx prev = PREV_INSN (before); | |
2477 | ||
6782074d | 2478 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
2479 | abort (); |
2480 | ||
a0ae8e8d RK |
2481 | PREV_INSN (insn) = prev; |
2482 | NEXT_INSN (insn) = before; | |
2483 | ||
2484 | if (prev) | |
2485 | { | |
2486 | NEXT_INSN (prev) = insn; | |
2487 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2488 | { | |
2489 | rtx sequence = PATTERN (prev); | |
2490 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2491 | } | |
2492 | } | |
2493 | else if (first_insn == before) | |
2494 | first_insn = insn; | |
2495 | else | |
2496 | { | |
49ad7cfa | 2497 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
2498 | /* Scan all pending sequences too. */ |
2499 | for (; stack; stack = stack->next) | |
2500 | if (before == stack->first) | |
fef0509b RK |
2501 | { |
2502 | stack->first = insn; | |
2503 | break; | |
2504 | } | |
a0ae8e8d RK |
2505 | |
2506 | if (stack == 0) | |
2507 | abort (); | |
2508 | } | |
2509 | ||
2510 | PREV_INSN (before) = insn; | |
2511 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2512 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2513 | } | |
2514 | ||
89e99eea DB |
2515 | /* Remove an insn from its doubly-linked list. This function knows how |
2516 | to handle sequences. */ | |
2517 | void | |
2518 | remove_insn (insn) | |
2519 | rtx insn; | |
2520 | { | |
2521 | rtx next = NEXT_INSN (insn); | |
2522 | rtx prev = PREV_INSN (insn); | |
2523 | if (prev) | |
2524 | { | |
2525 | NEXT_INSN (prev) = next; | |
2526 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2527 | { | |
2528 | rtx sequence = PATTERN (prev); | |
2529 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2530 | } | |
2531 | } | |
2532 | else if (first_insn == insn) | |
2533 | first_insn = next; | |
2534 | else | |
2535 | { | |
49ad7cfa | 2536 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2537 | /* Scan all pending sequences too. */ |
2538 | for (; stack; stack = stack->next) | |
2539 | if (insn == stack->first) | |
2540 | { | |
2541 | stack->first = next; | |
2542 | break; | |
2543 | } | |
2544 | ||
2545 | if (stack == 0) | |
2546 | abort (); | |
2547 | } | |
2548 | ||
2549 | if (next) | |
2550 | { | |
2551 | PREV_INSN (next) = prev; | |
2552 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2553 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2554 | } | |
2555 | else if (last_insn == insn) | |
2556 | last_insn = prev; | |
2557 | else | |
2558 | { | |
49ad7cfa | 2559 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2560 | /* Scan all pending sequences too. */ |
2561 | for (; stack; stack = stack->next) | |
2562 | if (insn == stack->last) | |
2563 | { | |
2564 | stack->last = prev; | |
2565 | break; | |
2566 | } | |
2567 | ||
2568 | if (stack == 0) | |
2569 | abort (); | |
2570 | } | |
2571 | } | |
2572 | ||
23b2ce53 RS |
2573 | /* Delete all insns made since FROM. |
2574 | FROM becomes the new last instruction. */ | |
2575 | ||
2576 | void | |
2577 | delete_insns_since (from) | |
2578 | rtx from; | |
2579 | { | |
2580 | if (from == 0) | |
2581 | first_insn = 0; | |
2582 | else | |
2583 | NEXT_INSN (from) = 0; | |
2584 | last_insn = from; | |
2585 | } | |
2586 | ||
5dab5552 MS |
2587 | /* This function is deprecated, please use sequences instead. |
2588 | ||
2589 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
2590 | The insns to be moved are those between FROM and TO. |
2591 | They are moved to a new position after the insn AFTER. | |
2592 | AFTER must not be FROM or TO or any insn in between. | |
2593 | ||
2594 | This function does not know about SEQUENCEs and hence should not be | |
2595 | called after delay-slot filling has been done. */ | |
2596 | ||
2597 | void | |
2598 | reorder_insns (from, to, after) | |
2599 | rtx from, to, after; | |
2600 | { | |
2601 | /* Splice this bunch out of where it is now. */ | |
2602 | if (PREV_INSN (from)) | |
2603 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2604 | if (NEXT_INSN (to)) | |
2605 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2606 | if (last_insn == to) | |
2607 | last_insn = PREV_INSN (from); | |
2608 | if (first_insn == from) | |
2609 | first_insn = NEXT_INSN (to); | |
2610 | ||
2611 | /* Make the new neighbors point to it and it to them. */ | |
2612 | if (NEXT_INSN (after)) | |
2613 | PREV_INSN (NEXT_INSN (after)) = to; | |
2614 | ||
2615 | NEXT_INSN (to) = NEXT_INSN (after); | |
2616 | PREV_INSN (from) = after; | |
2617 | NEXT_INSN (after) = from; | |
2618 | if (after == last_insn) | |
2619 | last_insn = to; | |
2620 | } | |
2621 | ||
2622 | /* Return the line note insn preceding INSN. */ | |
2623 | ||
2624 | static rtx | |
2625 | find_line_note (insn) | |
2626 | rtx insn; | |
2627 | { | |
2628 | if (no_line_numbers) | |
2629 | return 0; | |
2630 | ||
2631 | for (; insn; insn = PREV_INSN (insn)) | |
2632 | if (GET_CODE (insn) == NOTE | |
2633 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2634 | break; | |
2635 | ||
2636 | return insn; | |
2637 | } | |
2638 | ||
2639 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2640 | of the moved insns when debugging. This may insert a note between AFTER | |
2641 | and FROM, and another one after TO. */ | |
2642 | ||
2643 | void | |
2644 | reorder_insns_with_line_notes (from, to, after) | |
2645 | rtx from, to, after; | |
2646 | { | |
2647 | rtx from_line = find_line_note (from); | |
2648 | rtx after_line = find_line_note (after); | |
2649 | ||
2650 | reorder_insns (from, to, after); | |
2651 | ||
2652 | if (from_line == after_line) | |
2653 | return; | |
2654 | ||
2655 | if (from_line) | |
2656 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2657 | NOTE_LINE_NUMBER (from_line), | |
2658 | after); | |
2659 | if (after_line) | |
2660 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2661 | NOTE_LINE_NUMBER (after_line), | |
2662 | to); | |
2663 | } | |
aeeeda03 MM |
2664 | |
2665 | /* Remove unncessary notes from the instruction stream. */ | |
2666 | ||
2667 | void | |
2668 | remove_unncessary_notes () | |
2669 | { | |
2670 | rtx insn; | |
2671 | rtx next; | |
aeeeda03 | 2672 | |
116eebd6 MM |
2673 | /* We must not remove the first instruction in the function because |
2674 | the compiler depends on the first instruction being a note. */ | |
aeeeda03 MM |
2675 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
2676 | { | |
2677 | /* Remember what's next. */ | |
2678 | next = NEXT_INSN (insn); | |
2679 | ||
2680 | /* We're only interested in notes. */ | |
2681 | if (GET_CODE (insn) != NOTE) | |
2682 | continue; | |
2683 | ||
116eebd6 MM |
2684 | /* By now, all notes indicating lexical blocks should have |
2685 | NOTE_BLOCK filled in. */ | |
2686 | if ((NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG | |
2687 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) | |
2688 | && NOTE_BLOCK (insn) == NULL_TREE) | |
2689 | abort (); | |
2690 | ||
2691 | /* Remove NOTE_INSN_DELETED notes. */ | |
aeeeda03 MM |
2692 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) |
2693 | remove_insn (insn); | |
18c038b9 MM |
2694 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) |
2695 | { | |
2696 | /* Scan back to see if there are any non-note instructions | |
2697 | between INSN and the beginning of this block. If not, | |
2698 | then there is no PC range in the generated code that will | |
2699 | actually be in this block, so there's no point in | |
2700 | remembering the existence of the block. */ | |
2701 | rtx prev; | |
2702 | ||
2703 | for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev)) | |
2704 | { | |
2705 | /* This block contains a real instruction. Note that we | |
2706 | don't include labels; if the only thing in the block | |
2707 | is a label, then there are still no PC values that | |
2708 | lie within the block. */ | |
2709 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i') | |
2710 | break; | |
2711 | ||
2712 | /* We're only interested in NOTEs. */ | |
2713 | if (GET_CODE (prev) != NOTE) | |
2714 | continue; | |
2715 | ||
2716 | if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_BEG) | |
2717 | { | |
2718 | /* If the BLOCKs referred to by these notes don't | |
2719 | match, then something is wrong with our BLOCK | |
2720 | nesting structure. */ | |
2721 | if (NOTE_BLOCK (prev) != NOTE_BLOCK (insn)) | |
2722 | abort (); | |
fcd7f76b | 2723 | |
deb5e280 JM |
2724 | /* Never delete the BLOCK for the outermost scope |
2725 | of the function; we can refer to names from | |
2726 | that scope even if the block notes are messed up. */ | |
2727 | if (! is_body_block (NOTE_BLOCK (insn))) | |
2728 | { | |
2729 | debug_ignore_block (NOTE_BLOCK (insn)); | |
2730 | ||
2731 | remove_insn (prev); | |
2732 | remove_insn (insn); | |
2733 | } | |
18c038b9 MM |
2734 | break; |
2735 | } | |
2736 | else if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_END) | |
2737 | /* There's a nested block. We need to leave the | |
2738 | current block in place since otherwise the debugger | |
2739 | wouldn't be able to show symbols from our block in | |
2740 | the nested block. */ | |
2741 | break; | |
2742 | } | |
2743 | } | |
aeeeda03 MM |
2744 | } |
2745 | } | |
2746 | ||
23b2ce53 RS |
2747 | \f |
2748 | /* Emit an insn of given code and pattern | |
2749 | at a specified place within the doubly-linked list. */ | |
2750 | ||
2751 | /* Make an instruction with body PATTERN | |
2752 | and output it before the instruction BEFORE. */ | |
2753 | ||
2754 | rtx | |
2755 | emit_insn_before (pattern, before) | |
2756 | register rtx pattern, before; | |
2757 | { | |
2758 | register rtx insn = before; | |
2759 | ||
2760 | if (GET_CODE (pattern) == SEQUENCE) | |
2761 | { | |
2762 | register int i; | |
2763 | ||
2764 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2765 | { | |
2766 | insn = XVECEXP (pattern, 0, i); | |
a0ae8e8d | 2767 | add_insn_before (insn, before); |
23b2ce53 | 2768 | } |
a3770a81 | 2769 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
2770 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
2771 | } | |
2772 | else | |
2773 | { | |
4b1f5e8c | 2774 | insn = make_insn_raw (pattern); |
a0ae8e8d | 2775 | add_insn_before (insn, before); |
23b2ce53 RS |
2776 | } |
2777 | ||
2778 | return insn; | |
2779 | } | |
2780 | ||
a05924f9 JH |
2781 | /* Similar to emit_insn_before, but update basic block boundaries as well. */ |
2782 | ||
2783 | rtx | |
2784 | emit_block_insn_before (pattern, before, block) | |
2785 | rtx pattern, before; | |
2786 | basic_block block; | |
2787 | { | |
2788 | rtx prev = PREV_INSN (before); | |
2789 | rtx r = emit_insn_before (pattern, before); | |
2790 | if (block && block->head == before) | |
2791 | block->head = NEXT_INSN (prev); | |
2792 | return r; | |
2793 | } | |
2794 | ||
23b2ce53 RS |
2795 | /* Make an instruction with body PATTERN and code JUMP_INSN |
2796 | and output it before the instruction BEFORE. */ | |
2797 | ||
2798 | rtx | |
2799 | emit_jump_insn_before (pattern, before) | |
2800 | register rtx pattern, before; | |
2801 | { | |
2802 | register rtx insn; | |
2803 | ||
2804 | if (GET_CODE (pattern) == SEQUENCE) | |
2805 | insn = emit_insn_before (pattern, before); | |
2806 | else | |
2807 | { | |
85cf32bc | 2808 | insn = make_jump_insn_raw (pattern); |
a0ae8e8d | 2809 | add_insn_before (insn, before); |
23b2ce53 RS |
2810 | } |
2811 | ||
2812 | return insn; | |
2813 | } | |
2814 | ||
2815 | /* Make an instruction with body PATTERN and code CALL_INSN | |
2816 | and output it before the instruction BEFORE. */ | |
2817 | ||
2818 | rtx | |
2819 | emit_call_insn_before (pattern, before) | |
2820 | register rtx pattern, before; | |
2821 | { | |
aff507f4 RK |
2822 | register rtx insn; |
2823 | ||
2824 | if (GET_CODE (pattern) == SEQUENCE) | |
2825 | insn = emit_insn_before (pattern, before); | |
2826 | else | |
2827 | { | |
2828 | insn = make_call_insn_raw (pattern); | |
a0ae8e8d | 2829 | add_insn_before (insn, before); |
aff507f4 RK |
2830 | PUT_CODE (insn, CALL_INSN); |
2831 | } | |
2832 | ||
23b2ce53 RS |
2833 | return insn; |
2834 | } | |
2835 | ||
2836 | /* Make an insn of code BARRIER | |
e881bb1b | 2837 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
2838 | |
2839 | rtx | |
2840 | emit_barrier_before (before) | |
2841 | register rtx before; | |
2842 | { | |
2843 | register rtx insn = rtx_alloc (BARRIER); | |
2844 | ||
2845 | INSN_UID (insn) = cur_insn_uid++; | |
2846 | ||
a0ae8e8d | 2847 | add_insn_before (insn, before); |
23b2ce53 RS |
2848 | return insn; |
2849 | } | |
2850 | ||
e881bb1b RH |
2851 | /* Emit the label LABEL before the insn BEFORE. */ |
2852 | ||
2853 | rtx | |
2854 | emit_label_before (label, before) | |
2855 | rtx label, before; | |
2856 | { | |
2857 | /* This can be called twice for the same label as a result of the | |
2858 | confusion that follows a syntax error! So make it harmless. */ | |
2859 | if (INSN_UID (label) == 0) | |
2860 | { | |
2861 | INSN_UID (label) = cur_insn_uid++; | |
2862 | add_insn_before (label, before); | |
2863 | } | |
2864 | ||
2865 | return label; | |
2866 | } | |
2867 | ||
23b2ce53 RS |
2868 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
2869 | ||
2870 | rtx | |
2871 | emit_note_before (subtype, before) | |
2872 | int subtype; | |
2873 | rtx before; | |
2874 | { | |
2875 | register rtx note = rtx_alloc (NOTE); | |
2876 | INSN_UID (note) = cur_insn_uid++; | |
2877 | NOTE_SOURCE_FILE (note) = 0; | |
2878 | NOTE_LINE_NUMBER (note) = subtype; | |
2879 | ||
a0ae8e8d | 2880 | add_insn_before (note, before); |
23b2ce53 RS |
2881 | return note; |
2882 | } | |
2883 | \f | |
2884 | /* Make an insn of code INSN with body PATTERN | |
2885 | and output it after the insn AFTER. */ | |
2886 | ||
2887 | rtx | |
2888 | emit_insn_after (pattern, after) | |
2889 | register rtx pattern, after; | |
2890 | { | |
2891 | register rtx insn = after; | |
2892 | ||
2893 | if (GET_CODE (pattern) == SEQUENCE) | |
2894 | { | |
2895 | register int i; | |
2896 | ||
2897 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2898 | { | |
2899 | insn = XVECEXP (pattern, 0, i); | |
2900 | add_insn_after (insn, after); | |
2901 | after = insn; | |
2902 | } | |
a3770a81 | 2903 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
2904 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
2905 | } | |
2906 | else | |
2907 | { | |
4b1f5e8c | 2908 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
2909 | add_insn_after (insn, after); |
2910 | } | |
2911 | ||
2912 | return insn; | |
2913 | } | |
2914 | ||
255680cf RK |
2915 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
2916 | as to act as if this insn were at FROM. */ | |
2917 | ||
2918 | void | |
2919 | emit_insn_after_with_line_notes (pattern, after, from) | |
2920 | rtx pattern, after, from; | |
2921 | { | |
2922 | rtx from_line = find_line_note (from); | |
2923 | rtx after_line = find_line_note (after); | |
2924 | rtx insn = emit_insn_after (pattern, after); | |
2925 | ||
2926 | if (from_line) | |
2927 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2928 | NOTE_LINE_NUMBER (from_line), | |
2929 | after); | |
2930 | ||
2931 | if (after_line) | |
2932 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2933 | NOTE_LINE_NUMBER (after_line), | |
2934 | insn); | |
2935 | } | |
2936 | ||
a05924f9 JH |
2937 | /* Similar to emit_insn_after, but update basic block boundaries as well. */ |
2938 | ||
2939 | rtx | |
2940 | emit_block_insn_after (pattern, after, block) | |
2941 | rtx pattern, after; | |
2942 | basic_block block; | |
2943 | { | |
2944 | rtx r = emit_insn_after (pattern, after); | |
2945 | if (block && block->end == after) | |
2946 | block->end = r; | |
2947 | return r; | |
2948 | } | |
2949 | ||
23b2ce53 RS |
2950 | /* Make an insn of code JUMP_INSN with body PATTERN |
2951 | and output it after the insn AFTER. */ | |
2952 | ||
2953 | rtx | |
2954 | emit_jump_insn_after (pattern, after) | |
2955 | register rtx pattern, after; | |
2956 | { | |
2957 | register rtx insn; | |
2958 | ||
2959 | if (GET_CODE (pattern) == SEQUENCE) | |
2960 | insn = emit_insn_after (pattern, after); | |
2961 | else | |
2962 | { | |
85cf32bc | 2963 | insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
2964 | add_insn_after (insn, after); |
2965 | } | |
2966 | ||
2967 | return insn; | |
2968 | } | |
2969 | ||
2970 | /* Make an insn of code BARRIER | |
2971 | and output it after the insn AFTER. */ | |
2972 | ||
2973 | rtx | |
2974 | emit_barrier_after (after) | |
2975 | register rtx after; | |
2976 | { | |
2977 | register rtx insn = rtx_alloc (BARRIER); | |
2978 | ||
2979 | INSN_UID (insn) = cur_insn_uid++; | |
2980 | ||
2981 | add_insn_after (insn, after); | |
2982 | return insn; | |
2983 | } | |
2984 | ||
2985 | /* Emit the label LABEL after the insn AFTER. */ | |
2986 | ||
2987 | rtx | |
2988 | emit_label_after (label, after) | |
2989 | rtx label, after; | |
2990 | { | |
2991 | /* This can be called twice for the same label | |
2992 | as a result of the confusion that follows a syntax error! | |
2993 | So make it harmless. */ | |
2994 | if (INSN_UID (label) == 0) | |
2995 | { | |
2996 | INSN_UID (label) = cur_insn_uid++; | |
2997 | add_insn_after (label, after); | |
2998 | } | |
2999 | ||
3000 | return label; | |
3001 | } | |
3002 | ||
3003 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3004 | ||
3005 | rtx | |
3006 | emit_note_after (subtype, after) | |
3007 | int subtype; | |
3008 | rtx after; | |
3009 | { | |
3010 | register rtx note = rtx_alloc (NOTE); | |
3011 | INSN_UID (note) = cur_insn_uid++; | |
3012 | NOTE_SOURCE_FILE (note) = 0; | |
3013 | NOTE_LINE_NUMBER (note) = subtype; | |
3014 | add_insn_after (note, after); | |
3015 | return note; | |
3016 | } | |
3017 | ||
3018 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3019 | ||
3020 | rtx | |
3021 | emit_line_note_after (file, line, after) | |
3cce094d | 3022 | const char *file; |
23b2ce53 RS |
3023 | int line; |
3024 | rtx after; | |
3025 | { | |
3026 | register rtx note; | |
3027 | ||
3028 | if (no_line_numbers && line > 0) | |
3029 | { | |
3030 | cur_insn_uid++; | |
3031 | return 0; | |
3032 | } | |
3033 | ||
3034 | note = rtx_alloc (NOTE); | |
3035 | INSN_UID (note) = cur_insn_uid++; | |
3036 | NOTE_SOURCE_FILE (note) = file; | |
3037 | NOTE_LINE_NUMBER (note) = line; | |
3038 | add_insn_after (note, after); | |
3039 | return note; | |
3040 | } | |
3041 | \f | |
3042 | /* Make an insn of code INSN with pattern PATTERN | |
3043 | and add it to the end of the doubly-linked list. | |
3044 | If PATTERN is a SEQUENCE, take the elements of it | |
3045 | and emit an insn for each element. | |
3046 | ||
3047 | Returns the last insn emitted. */ | |
3048 | ||
3049 | rtx | |
3050 | emit_insn (pattern) | |
3051 | rtx pattern; | |
3052 | { | |
3053 | rtx insn = last_insn; | |
3054 | ||
3055 | if (GET_CODE (pattern) == SEQUENCE) | |
3056 | { | |
3057 | register int i; | |
3058 | ||
3059 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3060 | { | |
3061 | insn = XVECEXP (pattern, 0, i); | |
3062 | add_insn (insn); | |
3063 | } | |
a3770a81 | 3064 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
3065 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
3066 | } | |
3067 | else | |
3068 | { | |
4b1f5e8c | 3069 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3070 | add_insn (insn); |
3071 | } | |
3072 | ||
3073 | return insn; | |
3074 | } | |
3075 | ||
3076 | /* Emit the insns in a chain starting with INSN. | |
3077 | Return the last insn emitted. */ | |
3078 | ||
3079 | rtx | |
3080 | emit_insns (insn) | |
3081 | rtx insn; | |
3082 | { | |
3083 | rtx last = 0; | |
3084 | ||
3085 | while (insn) | |
3086 | { | |
3087 | rtx next = NEXT_INSN (insn); | |
3088 | add_insn (insn); | |
3089 | last = insn; | |
3090 | insn = next; | |
3091 | } | |
3092 | ||
3093 | return last; | |
3094 | } | |
3095 | ||
3096 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3097 | the insn BEFORE. Return the last insn emitted. */ | |
3098 | ||
3099 | rtx | |
3100 | emit_insns_before (insn, before) | |
3101 | rtx insn; | |
3102 | rtx before; | |
3103 | { | |
3104 | rtx last = 0; | |
3105 | ||
3106 | while (insn) | |
3107 | { | |
3108 | rtx next = NEXT_INSN (insn); | |
a0ae8e8d | 3109 | add_insn_before (insn, before); |
23b2ce53 RS |
3110 | last = insn; |
3111 | insn = next; | |
3112 | } | |
3113 | ||
3114 | return last; | |
3115 | } | |
3116 | ||
e0a5c5eb RS |
3117 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3118 | the insn AFTER. Return the last insn emitted. */ | |
3119 | ||
3120 | rtx | |
3121 | emit_insns_after (first, after) | |
3122 | register rtx first; | |
3123 | register rtx after; | |
3124 | { | |
3125 | register rtx last; | |
3126 | register rtx after_after; | |
3127 | ||
3128 | if (!after) | |
3129 | abort (); | |
3130 | ||
3131 | if (!first) | |
3132 | return first; | |
3133 | ||
3134 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3135 | continue; | |
3136 | ||
3137 | after_after = NEXT_INSN (after); | |
3138 | ||
3139 | NEXT_INSN (after) = first; | |
3140 | PREV_INSN (first) = after; | |
3141 | NEXT_INSN (last) = after_after; | |
3142 | if (after_after) | |
3143 | PREV_INSN (after_after) = last; | |
3144 | ||
c4d990db RS |
3145 | if (after == last_insn) |
3146 | last_insn = last; | |
e0a5c5eb RS |
3147 | return last; |
3148 | } | |
3149 | ||
23b2ce53 RS |
3150 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3151 | and add it to the end of the doubly-linked list. */ | |
3152 | ||
3153 | rtx | |
3154 | emit_jump_insn (pattern) | |
3155 | rtx pattern; | |
3156 | { | |
3157 | if (GET_CODE (pattern) == SEQUENCE) | |
3158 | return emit_insn (pattern); | |
3159 | else | |
3160 | { | |
85cf32bc | 3161 | register rtx insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3162 | add_insn (insn); |
3163 | return insn; | |
3164 | } | |
3165 | } | |
3166 | ||
3167 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3168 | and add it to the end of the doubly-linked list. */ | |
3169 | ||
3170 | rtx | |
3171 | emit_call_insn (pattern) | |
3172 | rtx pattern; | |
3173 | { | |
3174 | if (GET_CODE (pattern) == SEQUENCE) | |
3175 | return emit_insn (pattern); | |
3176 | else | |
3177 | { | |
aff507f4 | 3178 | register rtx insn = make_call_insn_raw (pattern); |
23b2ce53 RS |
3179 | add_insn (insn); |
3180 | PUT_CODE (insn, CALL_INSN); | |
3181 | return insn; | |
3182 | } | |
3183 | } | |
3184 | ||
3185 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3186 | ||
3187 | rtx | |
3188 | emit_label (label) | |
3189 | rtx label; | |
3190 | { | |
3191 | /* This can be called twice for the same label | |
3192 | as a result of the confusion that follows a syntax error! | |
3193 | So make it harmless. */ | |
3194 | if (INSN_UID (label) == 0) | |
3195 | { | |
3196 | INSN_UID (label) = cur_insn_uid++; | |
3197 | add_insn (label); | |
3198 | } | |
3199 | return label; | |
3200 | } | |
3201 | ||
3202 | /* Make an insn of code BARRIER | |
3203 | and add it to the end of the doubly-linked list. */ | |
3204 | ||
3205 | rtx | |
3206 | emit_barrier () | |
3207 | { | |
3208 | register rtx barrier = rtx_alloc (BARRIER); | |
3209 | INSN_UID (barrier) = cur_insn_uid++; | |
3210 | add_insn (barrier); | |
3211 | return barrier; | |
3212 | } | |
3213 | ||
3214 | /* Make an insn of code NOTE | |
3215 | with data-fields specified by FILE and LINE | |
3216 | and add it to the end of the doubly-linked list, | |
3217 | but only if line-numbers are desired for debugging info. */ | |
3218 | ||
3219 | rtx | |
3220 | emit_line_note (file, line) | |
3cce094d | 3221 | const char *file; |
23b2ce53 RS |
3222 | int line; |
3223 | { | |
3f1d071b | 3224 | set_file_and_line_for_stmt (file, line); |
23b2ce53 RS |
3225 | |
3226 | #if 0 | |
3227 | if (no_line_numbers) | |
3228 | return 0; | |
3229 | #endif | |
3230 | ||
3231 | return emit_note (file, line); | |
3232 | } | |
3233 | ||
3234 | /* Make an insn of code NOTE | |
3235 | with data-fields specified by FILE and LINE | |
3236 | and add it to the end of the doubly-linked list. | |
3237 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3238 | ||
3239 | rtx | |
3240 | emit_note (file, line) | |
3cce094d | 3241 | const char *file; |
23b2ce53 RS |
3242 | int line; |
3243 | { | |
3244 | register rtx note; | |
3245 | ||
3246 | if (line > 0) | |
3247 | { | |
3248 | if (file && last_filename && !strcmp (file, last_filename) | |
3249 | && line == last_linenum) | |
3250 | return 0; | |
3251 | last_filename = file; | |
3252 | last_linenum = line; | |
3253 | } | |
3254 | ||
3255 | if (no_line_numbers && line > 0) | |
3256 | { | |
3257 | cur_insn_uid++; | |
3258 | return 0; | |
3259 | } | |
3260 | ||
3261 | note = rtx_alloc (NOTE); | |
3262 | INSN_UID (note) = cur_insn_uid++; | |
3263 | NOTE_SOURCE_FILE (note) = file; | |
3264 | NOTE_LINE_NUMBER (note) = line; | |
3265 | add_insn (note); | |
3266 | return note; | |
3267 | } | |
3268 | ||
fe77a034 | 3269 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
23b2ce53 RS |
3270 | |
3271 | rtx | |
3272 | emit_line_note_force (file, line) | |
3cce094d | 3273 | const char *file; |
23b2ce53 RS |
3274 | int line; |
3275 | { | |
3276 | last_linenum = -1; | |
3277 | return emit_line_note (file, line); | |
3278 | } | |
3279 | ||
3280 | /* Cause next statement to emit a line note even if the line number | |
3281 | has not changed. This is used at the beginning of a function. */ | |
3282 | ||
3283 | void | |
3284 | force_next_line_note () | |
3285 | { | |
3286 | last_linenum = -1; | |
3287 | } | |
87b47c85 AM |
3288 | |
3289 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
3290 | note of this type already exists, remove it first. */ | |
3291 | ||
3292 | void | |
3293 | set_unique_reg_note (insn, kind, datum) | |
3294 | rtx insn; | |
3295 | enum reg_note kind; | |
3296 | rtx datum; | |
3297 | { | |
3298 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3299 | ||
3300 | /* First remove the note if there already is one. */ | |
3301 | if (note) | |
3302 | remove_note (insn, note); | |
3303 | ||
3304 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3305 | } | |
23b2ce53 RS |
3306 | \f |
3307 | /* Return an indication of which type of insn should have X as a body. | |
3308 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3309 | ||
3310 | enum rtx_code | |
3311 | classify_insn (x) | |
3312 | rtx x; | |
3313 | { | |
3314 | if (GET_CODE (x) == CODE_LABEL) | |
3315 | return CODE_LABEL; | |
3316 | if (GET_CODE (x) == CALL) | |
3317 | return CALL_INSN; | |
3318 | if (GET_CODE (x) == RETURN) | |
3319 | return JUMP_INSN; | |
3320 | if (GET_CODE (x) == SET) | |
3321 | { | |
3322 | if (SET_DEST (x) == pc_rtx) | |
3323 | return JUMP_INSN; | |
3324 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3325 | return CALL_INSN; | |
3326 | else | |
3327 | return INSN; | |
3328 | } | |
3329 | if (GET_CODE (x) == PARALLEL) | |
3330 | { | |
3331 | register int j; | |
3332 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3333 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3334 | return CALL_INSN; | |
3335 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3336 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3337 | return JUMP_INSN; | |
3338 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3339 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3340 | return CALL_INSN; | |
3341 | } | |
3342 | return INSN; | |
3343 | } | |
3344 | ||
3345 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3346 | If X is a label, it is simply added into the insn chain. */ | |
3347 | ||
3348 | rtx | |
3349 | emit (x) | |
3350 | rtx x; | |
3351 | { | |
3352 | enum rtx_code code = classify_insn (x); | |
3353 | ||
3354 | if (code == CODE_LABEL) | |
3355 | return emit_label (x); | |
3356 | else if (code == INSN) | |
3357 | return emit_insn (x); | |
3358 | else if (code == JUMP_INSN) | |
3359 | { | |
3360 | register rtx insn = emit_jump_insn (x); | |
3361 | if (simplejump_p (insn) || GET_CODE (x) == RETURN) | |
3362 | return emit_barrier (); | |
3363 | return insn; | |
3364 | } | |
3365 | else if (code == CALL_INSN) | |
3366 | return emit_call_insn (x); | |
3367 | else | |
3368 | abort (); | |
3369 | } | |
3370 | \f | |
5c7a310f MM |
3371 | /* Begin emitting insns to a sequence which can be packaged in an |
3372 | RTL_EXPR. If this sequence will contain something that might cause | |
3373 | the compiler to pop arguments to function calls (because those | |
3374 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3375 | details), use do_pending_stack_adjust before calling this function. | |
3376 | That will ensure that the deferred pops are not accidentally | |
3377 | emitted in the middel of this sequence. */ | |
23b2ce53 RS |
3378 | |
3379 | void | |
3380 | start_sequence () | |
3381 | { | |
3382 | struct sequence_stack *tem; | |
3383 | ||
a3770a81 | 3384 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
23b2ce53 | 3385 | |
49ad7cfa | 3386 | tem->next = seq_stack; |
23b2ce53 RS |
3387 | tem->first = first_insn; |
3388 | tem->last = last_insn; | |
591ccf92 | 3389 | tem->sequence_rtl_expr = seq_rtl_expr; |
23b2ce53 | 3390 | |
49ad7cfa | 3391 | seq_stack = tem; |
23b2ce53 RS |
3392 | |
3393 | first_insn = 0; | |
3394 | last_insn = 0; | |
3395 | } | |
3396 | ||
591ccf92 MM |
3397 | /* Similarly, but indicate that this sequence will be placed in T, an |
3398 | RTL_EXPR. See the documentation for start_sequence for more | |
3399 | information about how to use this function. */ | |
3400 | ||
3401 | void | |
3402 | start_sequence_for_rtl_expr (t) | |
3403 | tree t; | |
3404 | { | |
3405 | start_sequence (); | |
3406 | ||
3407 | seq_rtl_expr = t; | |
3408 | } | |
3409 | ||
5c7a310f MM |
3410 | /* Set up the insn chain starting with FIRST as the current sequence, |
3411 | saving the previously current one. See the documentation for | |
3412 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
3413 | |
3414 | void | |
3415 | push_to_sequence (first) | |
3416 | rtx first; | |
3417 | { | |
3418 | rtx last; | |
3419 | ||
3420 | start_sequence (); | |
3421 | ||
3422 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3423 | ||
3424 | first_insn = first; | |
3425 | last_insn = last; | |
3426 | } | |
3427 | ||
c14f7160 ML |
3428 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3429 | ||
3430 | void | |
3431 | push_to_full_sequence (first, last) | |
3432 | rtx first, last; | |
3433 | { | |
3434 | start_sequence (); | |
3435 | first_insn = first; | |
3436 | last_insn = last; | |
3437 | /* We really should have the end of the insn chain here. */ | |
3438 | if (last && NEXT_INSN (last)) | |
3439 | abort (); | |
3440 | } | |
3441 | ||
f15ae3a1 TW |
3442 | /* Set up the outer-level insn chain |
3443 | as the current sequence, saving the previously current one. */ | |
3444 | ||
3445 | void | |
3446 | push_topmost_sequence () | |
3447 | { | |
aefdd5ab | 3448 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
3449 | |
3450 | start_sequence (); | |
3451 | ||
49ad7cfa | 3452 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3453 | top = stack; |
3454 | ||
3455 | first_insn = top->first; | |
3456 | last_insn = top->last; | |
591ccf92 | 3457 | seq_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
3458 | } |
3459 | ||
3460 | /* After emitting to the outer-level insn chain, update the outer-level | |
3461 | insn chain, and restore the previous saved state. */ | |
3462 | ||
3463 | void | |
3464 | pop_topmost_sequence () | |
3465 | { | |
aefdd5ab | 3466 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 3467 | |
49ad7cfa | 3468 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3469 | top = stack; |
3470 | ||
3471 | top->first = first_insn; | |
3472 | top->last = last_insn; | |
591ccf92 | 3473 | /* ??? Why don't we save seq_rtl_expr here? */ |
f15ae3a1 TW |
3474 | |
3475 | end_sequence (); | |
3476 | } | |
3477 | ||
23b2ce53 RS |
3478 | /* After emitting to a sequence, restore previous saved state. |
3479 | ||
5c7a310f MM |
3480 | To get the contents of the sequence just made, you must call |
3481 | `gen_sequence' *before* calling here. | |
3482 | ||
3483 | If the compiler might have deferred popping arguments while | |
3484 | generating this sequence, and this sequence will not be immediately | |
3485 | inserted into the instruction stream, use do_pending_stack_adjust | |
3486 | before calling gen_sequence. That will ensure that the deferred | |
3487 | pops are inserted into this sequence, and not into some random | |
3488 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3489 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
3490 | |
3491 | void | |
3492 | end_sequence () | |
3493 | { | |
49ad7cfa | 3494 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
3495 | |
3496 | first_insn = tem->first; | |
3497 | last_insn = tem->last; | |
591ccf92 | 3498 | seq_rtl_expr = tem->sequence_rtl_expr; |
49ad7cfa | 3499 | seq_stack = tem->next; |
23b2ce53 | 3500 | |
a3770a81 | 3501 | free (tem); |
23b2ce53 RS |
3502 | } |
3503 | ||
c14f7160 ML |
3504 | /* This works like end_sequence, but records the old sequence in FIRST |
3505 | and LAST. */ | |
3506 | ||
3507 | void | |
3508 | end_full_sequence (first, last) | |
3509 | rtx *first, *last; | |
3510 | { | |
3511 | *first = first_insn; | |
3512 | *last = last_insn; | |
3513 | end_sequence(); | |
3514 | } | |
3515 | ||
23b2ce53 RS |
3516 | /* Return 1 if currently emitting into a sequence. */ |
3517 | ||
3518 | int | |
3519 | in_sequence_p () | |
3520 | { | |
49ad7cfa | 3521 | return seq_stack != 0; |
23b2ce53 RS |
3522 | } |
3523 | ||
3524 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3525 | to the current sequence. | |
3526 | ||
3527 | This is how the gen_... function from a DEFINE_EXPAND | |
3528 | constructs the SEQUENCE that it returns. */ | |
3529 | ||
3530 | rtx | |
3531 | gen_sequence () | |
3532 | { | |
3533 | rtx result; | |
3534 | rtx tem; | |
23b2ce53 RS |
3535 | int i; |
3536 | int len; | |
3537 | ||
3538 | /* Count the insns in the chain. */ | |
3539 | len = 0; | |
3540 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3541 | len++; | |
3542 | ||
ee265800 | 3543 | /* If only one insn, return it rather than a SEQUENCE. |
23b2ce53 | 3544 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
ee265800 AH |
3545 | the case of an empty list.) |
3546 | We only return the pattern of an insn if its code is INSN and it | |
3547 | has no notes. This ensures that no information gets lost. */ | |
23b2ce53 | 3548 | if (len == 1 |
ca55abae | 3549 | && ! RTX_FRAME_RELATED_P (first_insn) |
ee265800 AH |
3550 | && GET_CODE (first_insn) == INSN |
3551 | /* Don't throw away any reg notes. */ | |
3552 | && REG_NOTES (first_insn) == 0) | |
43127294 | 3553 | { |
a3770a81 RH |
3554 | if (!ggc_p) |
3555 | { | |
3556 | NEXT_INSN (first_insn) = free_insn; | |
3557 | free_insn = first_insn; | |
3558 | } | |
43127294 RK |
3559 | return PATTERN (first_insn); |
3560 | } | |
23b2ce53 RS |
3561 | |
3562 | /* Put them in a vector. See if we already have a SEQUENCE of the | |
3563 | appropriate length around. */ | |
a3770a81 RH |
3564 | if (!ggc_p && len < SEQUENCE_RESULT_SIZE |
3565 | && (result = sequence_result[len]) != 0) | |
23b2ce53 RS |
3566 | sequence_result[len] = 0; |
3567 | else | |
3568 | { | |
9faa82d8 RK |
3569 | /* Ensure that this rtl goes in saveable_obstack, since we may |
3570 | cache it. */ | |
d508ebba JW |
3571 | push_obstacks_nochange (); |
3572 | rtl_in_saveable_obstack (); | |
3b80f6ca | 3573 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
d508ebba | 3574 | pop_obstacks (); |
23b2ce53 RS |
3575 | } |
3576 | ||
3577 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3578 | XVECEXP (result, 0, i) = tem; | |
3579 | ||
3580 | return result; | |
3581 | } | |
3582 | \f | |
59ec66dc MM |
3583 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3584 | ||
3585 | void | |
49ad7cfa BS |
3586 | init_virtual_regs (es) |
3587 | struct emit_status *es; | |
59ec66dc | 3588 | { |
49ad7cfa BS |
3589 | rtx *ptr = es->x_regno_reg_rtx; |
3590 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3591 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3592 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3593 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3594 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3595 | } | |
3596 | ||
3597 | void | |
3598 | clear_emit_caches () | |
3599 | { | |
3600 | int i; | |
3601 | ||
3602 | /* Clear the start_sequence/gen_sequence cache. */ | |
49ad7cfa BS |
3603 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3604 | sequence_result[i] = 0; | |
3605 | free_insn = 0; | |
59ec66dc | 3606 | } |
da43a810 BS |
3607 | \f |
3608 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3609 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3610 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3611 | static int copy_insn_n_scratches; | |
3612 | ||
3613 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3614 | copied an ASM_OPERANDS. | |
3615 | In that case, it is the original input-operand vector. */ | |
3616 | static rtvec orig_asm_operands_vector; | |
3617 | ||
3618 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3619 | copied an ASM_OPERANDS. | |
3620 | In that case, it is the copied input-operand vector. */ | |
3621 | static rtvec copy_asm_operands_vector; | |
3622 | ||
3623 | /* Likewise for the constraints vector. */ | |
3624 | static rtvec orig_asm_constraints_vector; | |
3625 | static rtvec copy_asm_constraints_vector; | |
3626 | ||
3627 | /* Recursively create a new copy of an rtx for copy_insn. | |
3628 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3629 | ASM_OPERANDs properly. | |
3630 | Normally, this function is not used directly; use copy_insn as front end. | |
3631 | However, you could first copy an insn pattern with copy_insn and then use | |
3632 | this function afterwards to properly copy any REG_NOTEs containing | |
3633 | SCRATCHes. */ | |
3634 | ||
3635 | rtx | |
3636 | copy_insn_1 (orig) | |
3637 | register rtx orig; | |
3638 | { | |
3639 | register rtx copy; | |
3640 | register int i, j; | |
3641 | register RTX_CODE code; | |
4724334a | 3642 | register const char *format_ptr; |
da43a810 BS |
3643 | |
3644 | code = GET_CODE (orig); | |
3645 | ||
3646 | switch (code) | |
3647 | { | |
3648 | case REG: | |
3649 | case QUEUED: | |
3650 | case CONST_INT: | |
3651 | case CONST_DOUBLE: | |
3652 | case SYMBOL_REF: | |
3653 | case CODE_LABEL: | |
3654 | case PC: | |
3655 | case CC0: | |
3656 | case ADDRESSOF: | |
3657 | return orig; | |
3658 | ||
3659 | case SCRATCH: | |
3660 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3661 | if (copy_insn_scratch_in[i] == orig) | |
3662 | return copy_insn_scratch_out[i]; | |
3663 | break; | |
3664 | ||
3665 | case CONST: | |
3666 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
3667 | a LABEL_REF, it isn't sharable. */ | |
3668 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3669 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
3670 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
3671 | return orig; | |
3672 | break; | |
3673 | ||
3674 | /* A MEM with a constant address is not sharable. The problem is that | |
3675 | the constant address may need to be reloaded. If the mem is shared, | |
3676 | then reloading one copy of this mem will cause all copies to appear | |
3677 | to have been reloaded. */ | |
3678 | ||
3679 | default: | |
3680 | break; | |
3681 | } | |
3682 | ||
3683 | copy = rtx_alloc (code); | |
3684 | ||
3685 | /* Copy the various flags, and other information. We assume that | |
3686 | all fields need copying, and then clear the fields that should | |
3687 | not be copied. That is the sensible default behavior, and forces | |
3688 | us to explicitly document why we are *not* copying a flag. */ | |
3689 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
3690 | ||
3691 | /* We do not copy the USED flag, which is used as a mark bit during | |
3692 | walks over the RTL. */ | |
3693 | copy->used = 0; | |
3694 | ||
3695 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
3696 | if (GET_RTX_CLASS (code) == 'i') | |
3697 | { | |
3698 | copy->jump = 0; | |
3699 | copy->call = 0; | |
3700 | copy->frame_related = 0; | |
3701 | } | |
3702 | ||
3703 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
3704 | ||
3705 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
3706 | { | |
e63db8f6 | 3707 | copy->fld[i] = orig->fld[i]; |
da43a810 BS |
3708 | switch (*format_ptr++) |
3709 | { | |
3710 | case 'e': | |
da43a810 BS |
3711 | if (XEXP (orig, i) != NULL) |
3712 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
3713 | break; | |
3714 | ||
da43a810 BS |
3715 | case 'E': |
3716 | case 'V': | |
da43a810 BS |
3717 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
3718 | XVEC (copy, i) = copy_asm_constraints_vector; | |
3719 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
3720 | XVEC (copy, i) = copy_asm_operands_vector; | |
3721 | else if (XVEC (orig, i) != NULL) | |
3722 | { | |
3723 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
3724 | for (j = 0; j < XVECLEN (copy, i); j++) | |
3725 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
3726 | } | |
3727 | break; | |
3728 | ||
3729 | case 'b': | |
3730 | { | |
3731 | bitmap new_bits = BITMAP_OBSTACK_ALLOC (rtl_obstack); | |
3732 | bitmap_copy (new_bits, XBITMAP (orig, i)); | |
3733 | XBITMAP (copy, i) = new_bits; | |
3734 | break; | |
3735 | } | |
3736 | ||
3737 | case 't': | |
da43a810 | 3738 | case 'w': |
da43a810 | 3739 | case 'i': |
da43a810 BS |
3740 | case 's': |
3741 | case 'S': | |
e63db8f6 BS |
3742 | case 'u': |
3743 | case '0': | |
3744 | /* These are left unchanged. */ | |
da43a810 BS |
3745 | break; |
3746 | ||
3747 | default: | |
3748 | abort (); | |
3749 | } | |
3750 | } | |
3751 | ||
3752 | if (code == SCRATCH) | |
3753 | { | |
3754 | i = copy_insn_n_scratches++; | |
3755 | if (i >= MAX_RECOG_OPERANDS) | |
3756 | abort (); | |
3757 | copy_insn_scratch_in[i] = orig; | |
3758 | copy_insn_scratch_out[i] = copy; | |
3759 | } | |
3760 | else if (code == ASM_OPERANDS) | |
3761 | { | |
3762 | orig_asm_operands_vector = XVEC (orig, 3); | |
3763 | copy_asm_operands_vector = XVEC (copy, 3); | |
3764 | orig_asm_constraints_vector = XVEC (orig, 4); | |
3765 | copy_asm_constraints_vector = XVEC (copy, 4); | |
3766 | } | |
3767 | ||
3768 | return copy; | |
3769 | } | |
3770 | ||
3771 | /* Create a new copy of an rtx. | |
3772 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3773 | ASM_OPERANDs properly. | |
3774 | INSN doesn't really have to be a full INSN; it could be just the | |
3775 | pattern. */ | |
3776 | rtx | |
3777 | copy_insn (insn) | |
3778 | rtx insn; | |
3779 | { | |
3780 | copy_insn_n_scratches = 0; | |
3781 | orig_asm_operands_vector = 0; | |
3782 | orig_asm_constraints_vector = 0; | |
3783 | copy_asm_operands_vector = 0; | |
3784 | copy_asm_constraints_vector = 0; | |
3785 | return copy_insn_1 (insn); | |
3786 | } | |
59ec66dc | 3787 | |
23b2ce53 RS |
3788 | /* Initialize data structures and variables in this file |
3789 | before generating rtl for each function. */ | |
3790 | ||
3791 | void | |
3792 | init_emit () | |
3793 | { | |
01d939e8 | 3794 | struct function *f = cfun; |
23b2ce53 | 3795 | |
49ad7cfa | 3796 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
23b2ce53 RS |
3797 | first_insn = NULL; |
3798 | last_insn = NULL; | |
591ccf92 | 3799 | seq_rtl_expr = NULL; |
23b2ce53 RS |
3800 | cur_insn_uid = 1; |
3801 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
3802 | last_linenum = 0; | |
3803 | last_filename = 0; | |
3804 | first_label_num = label_num; | |
3805 | last_label_num = 0; | |
49ad7cfa | 3806 | seq_stack = NULL; |
23b2ce53 | 3807 | |
49ad7cfa | 3808 | clear_emit_caches (); |
23b2ce53 RS |
3809 | |
3810 | /* Init the tables that describe all the pseudo regs. */ | |
3811 | ||
49ad7cfa | 3812 | f->emit->regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 3813 | |
49ad7cfa | 3814 | f->emit->regno_pointer_flag |
a3770a81 | 3815 | = (char *) xcalloc (f->emit->regno_pointer_flag_length, sizeof (char)); |
23b2ce53 | 3816 | |
49ad7cfa | 3817 | f->emit->regno_pointer_align |
a3770a81 RH |
3818 | = (char *) xcalloc (f->emit->regno_pointer_flag_length, |
3819 | sizeof (char)); | |
86fe05e0 | 3820 | |
23b2ce53 | 3821 | regno_reg_rtx |
a3770a81 RH |
3822 | = (rtx *) xcalloc (f->emit->regno_pointer_flag_length * sizeof (rtx), |
3823 | sizeof (rtx)); | |
23b2ce53 RS |
3824 | |
3825 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
49ad7cfa | 3826 | init_virtual_regs (f->emit); |
740ab4a2 RK |
3827 | |
3828 | /* Indicate that the virtual registers and stack locations are | |
3829 | all pointers. */ | |
3830 | REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1; | |
3831 | REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1; | |
15c9248c | 3832 | REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1; |
740ab4a2 RK |
3833 | REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1; |
3834 | ||
3835 | REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1; | |
3836 | REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1; | |
3837 | REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1; | |
3838 | REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1; | |
71038426 | 3839 | REGNO_POINTER_FLAG (VIRTUAL_CFA_REGNUM) = 1; |
5e82e7bd | 3840 | |
86fe05e0 RK |
3841 | #ifdef STACK_BOUNDARY |
3842 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT; | |
3843 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT; | |
3844 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) | |
3845 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3846 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT; | |
3847 | ||
3848 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) | |
3849 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3850 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) | |
3851 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3852 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) | |
3853 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3854 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) | |
3855 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
71038426 | 3856 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = UNITS_PER_WORD; |
86fe05e0 RK |
3857 | #endif |
3858 | ||
5e82e7bd JVA |
3859 | #ifdef INIT_EXPANDERS |
3860 | INIT_EXPANDERS; | |
3861 | #endif | |
23b2ce53 RS |
3862 | } |
3863 | ||
87ff9c8e RH |
3864 | /* Mark SS for GC. */ |
3865 | ||
3866 | static void | |
3867 | mark_sequence_stack (ss) | |
3868 | struct sequence_stack *ss; | |
3869 | { | |
3870 | while (ss) | |
3871 | { | |
3872 | ggc_mark_rtx (ss->first); | |
591ccf92 | 3873 | ggc_mark_tree (ss->sequence_rtl_expr); |
87ff9c8e RH |
3874 | ss = ss->next; |
3875 | } | |
3876 | } | |
3877 | ||
3878 | /* Mark ES for GC. */ | |
3879 | ||
3880 | void | |
fa51b01b | 3881 | mark_emit_status (es) |
87ff9c8e RH |
3882 | struct emit_status *es; |
3883 | { | |
3884 | rtx *r; | |
3885 | int i; | |
3886 | ||
3887 | if (es == 0) | |
3888 | return; | |
3889 | ||
3890 | for (i = es->regno_pointer_flag_length, r = es->x_regno_reg_rtx; | |
3891 | i > 0; --i, ++r) | |
3892 | ggc_mark_rtx (*r); | |
3893 | ||
3894 | mark_sequence_stack (es->sequence_stack); | |
591ccf92 | 3895 | ggc_mark_tree (es->sequence_rtl_expr); |
87ff9c8e RH |
3896 | ggc_mark_rtx (es->x_first_insn); |
3897 | } | |
3898 | ||
23b2ce53 RS |
3899 | /* Create some permanent unique rtl objects shared between all functions. |
3900 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
3901 | ||
3902 | void | |
3903 | init_emit_once (line_numbers) | |
3904 | int line_numbers; | |
3905 | { | |
3906 | int i; | |
3907 | enum machine_mode mode; | |
9ec36da5 | 3908 | enum machine_mode double_mode; |
23b2ce53 RS |
3909 | |
3910 | no_line_numbers = ! line_numbers; | |
3911 | ||
43fa6302 AS |
3912 | /* Compute the word and byte modes. */ |
3913 | ||
3914 | byte_mode = VOIDmode; | |
3915 | word_mode = VOIDmode; | |
3916 | double_mode = VOIDmode; | |
3917 | ||
3918 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
3919 | mode = GET_MODE_WIDER_MODE (mode)) | |
3920 | { | |
3921 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
3922 | && byte_mode == VOIDmode) | |
3923 | byte_mode = mode; | |
3924 | ||
3925 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
3926 | && word_mode == VOIDmode) | |
3927 | word_mode = mode; | |
3928 | } | |
3929 | ||
3930 | #ifndef DOUBLE_TYPE_SIZE | |
3931 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
3932 | #endif | |
3933 | ||
3934 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
3935 | mode = GET_MODE_WIDER_MODE (mode)) | |
3936 | { | |
3937 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
3938 | && double_mode == VOIDmode) | |
3939 | double_mode = mode; | |
3940 | } | |
3941 | ||
3942 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
3943 | ||
5da077de AS |
3944 | /* Assign register numbers to the globally defined register rtx. |
3945 | This must be done at runtime because the register number field | |
3946 | is in a union and some compilers can't initialize unions. */ | |
3947 | ||
3948 | pc_rtx = gen_rtx (PC, VOIDmode); | |
3949 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
3950 | stack_pointer_rtx = gen_rtx_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
3951 | frame_pointer_rtx = gen_rtx_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
3952 | if (hard_frame_pointer_rtx == 0) | |
3953 | hard_frame_pointer_rtx = gen_rtx_raw_REG (Pmode, | |
3954 | HARD_FRAME_POINTER_REGNUM); | |
3955 | if (arg_pointer_rtx == 0) | |
3956 | arg_pointer_rtx = gen_rtx_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
3957 | virtual_incoming_args_rtx = | |
3958 | gen_rtx_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
3959 | virtual_stack_vars_rtx = | |
3960 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
3961 | virtual_stack_dynamic_rtx = | |
3962 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
3963 | virtual_outgoing_args_rtx = | |
3964 | gen_rtx_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
3965 | virtual_cfa_rtx = gen_rtx_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
3966 | ||
3967 | /* These rtx must be roots if GC is enabled. */ | |
3968 | if (ggc_p) | |
3969 | ggc_add_rtx_root (global_rtl, GR_MAX); | |
3970 | ||
5da077de AS |
3971 | #ifdef INIT_EXPANDERS |
3972 | /* This is to initialize save_machine_status and restore_machine_status before | |
3973 | the first call to push_function_context_to. This is needed by the Chill | |
3974 | front end which calls push_function_context_to before the first cal to | |
3975 | init_function_start. */ | |
3976 | INIT_EXPANDERS; | |
3977 | #endif | |
3978 | ||
23b2ce53 RS |
3979 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
3980 | ||
c5c76735 JL |
3981 | /* Don't use gen_rtx here since gen_rtx in this case |
3982 | tries to use these variables. */ | |
23b2ce53 | 3983 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
5da077de AS |
3984 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
3985 | gen_rtx_raw_CONST_INT (VOIDmode, i); | |
3986 | if (ggc_p) | |
3987 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); | |
23b2ce53 | 3988 | |
68d75312 JC |
3989 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
3990 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 3991 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 3992 | else |
3b80f6ca | 3993 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 3994 | |
9ec36da5 JL |
3995 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
3996 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
3997 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
3998 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
23b2ce53 RS |
3999 | |
4000 | for (i = 0; i <= 2; i++) | |
4001 | { | |
4002 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4003 | mode = GET_MODE_WIDER_MODE (mode)) | |
4004 | { | |
4005 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4006 | union real_extract u; | |
4007 | ||
4c9a05bc | 4008 | bzero ((char *) &u, sizeof u); /* Zero any holes in a structure. */ |
23b2ce53 RS |
4009 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4010 | ||
4c9a05bc | 4011 | bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u); |
23b2ce53 RS |
4012 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
4013 | PUT_MODE (tem, mode); | |
4014 | ||
4015 | const_tiny_rtx[i][(int) mode] = tem; | |
4016 | } | |
4017 | ||
906c4e36 | 4018 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
4019 | |
4020 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4021 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 4022 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
4023 | |
4024 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4025 | mode != VOIDmode; | |
4026 | mode = GET_MODE_WIDER_MODE (mode)) | |
4027 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
4028 | } |
4029 | ||
aea87e88 RH |
4030 | for (mode = CCmode; mode < MAX_MACHINE_MODE; ++mode) |
4031 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
4032 | const_tiny_rtx[0][(int) mode] = const0_rtx; | |
23b2ce53 | 4033 | |
d7db6646 | 4034 | ggc_add_rtx_root (&const_tiny_rtx[0][0], sizeof(const_tiny_rtx)/sizeof(rtx)); |
21cd906e | 4035 | ggc_add_rtx_root (&const_true_rtx, 1); |
a7e1e2ac AO |
4036 | |
4037 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4038 | return_address_pointer_rtx | |
4039 | = gen_rtx_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
4040 | #endif | |
4041 | ||
4042 | #ifdef STRUCT_VALUE | |
4043 | struct_value_rtx = STRUCT_VALUE; | |
4044 | #else | |
4045 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4046 | #endif | |
4047 | ||
4048 | #ifdef STRUCT_VALUE_INCOMING | |
4049 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4050 | #else | |
4051 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4052 | struct_value_incoming_rtx | |
4053 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4054 | #else | |
4055 | struct_value_incoming_rtx = struct_value_rtx; | |
4056 | #endif | |
4057 | #endif | |
4058 | ||
4059 | #ifdef STATIC_CHAIN_REGNUM | |
4060 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4061 | ||
4062 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4063 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4064 | static_chain_incoming_rtx | |
4065 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4066 | else | |
4067 | #endif | |
4068 | static_chain_incoming_rtx = static_chain_rtx; | |
4069 | #endif | |
4070 | ||
4071 | #ifdef STATIC_CHAIN | |
4072 | static_chain_rtx = STATIC_CHAIN; | |
4073 | ||
4074 | #ifdef STATIC_CHAIN_INCOMING | |
4075 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4076 | #else | |
4077 | static_chain_incoming_rtx = static_chain_rtx; | |
4078 | #endif | |
4079 | #endif | |
4080 | ||
4081 | #ifdef PIC_OFFSET_TABLE_REGNUM | |
4082 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
4083 | #endif | |
4084 | ||
d7db6646 RH |
4085 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4086 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4087 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4088 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4089 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4090 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
23b2ce53 | 4091 | } |
a11759a3 JR |
4092 | \f |
4093 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4094 | switch / case handling in stmt.c to give proper line numbers in | |
4095 | warnings about unreachable code. */ | |
4096 | ||
4097 | int | |
4098 | force_line_numbers () | |
4099 | { | |
4100 | int old = no_line_numbers; | |
4101 | ||
4102 | no_line_numbers = 0; | |
4103 | if (old) | |
4104 | force_next_line_note (); | |
4105 | return old; | |
4106 | } | |
4107 | ||
4108 | void | |
4109 | restore_line_number_status (old_value) | |
4110 | int old_value; | |
4111 | { | |
4112 | no_line_numbers = old_value; | |
4113 | } |