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15bbde2b | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ddca3e9d | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
15bbde2b | 4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
8d62a21c | 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
15bbde2b | 21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
405711de | 39 | #include "system.h" |
d3b64f2d | 40 | #include "toplev.h" |
15bbde2b | 41 | #include "rtl.h" |
3fd7e17f | 42 | #include "tree.h" |
7953c610 | 43 | #include "tm_p.h" |
15bbde2b | 44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
c6b6c51f | 48 | #include "hard-reg-set.h" |
73f5c1e3 | 49 | #include "hashtab.h" |
15bbde2b | 50 | #include "insn-config.h" |
0dbd1c74 | 51 | #include "recog.h" |
15bbde2b | 52 | #include "real.h" |
649d8da6 | 53 | #include "obstack.h" |
a3426c4c | 54 | #include "bitmap.h" |
f3d96a58 | 55 | #include "basic-block.h" |
a7b0c170 | 56 | #include "ggc.h" |
0e66aa75 | 57 | #include "defaults.h" |
649d8da6 | 58 | |
399d45d3 | 59 | /* Commonly used modes. */ |
60 | ||
a92771b8 | 61 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
62 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9e042f31 | 63 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
a92771b8 | 64 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
399d45d3 | 65 | |
15bbde2b | 66 | |
67 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
68 | in the entire compilation a unique label number. */ | |
69 | ||
70 | static int label_num = 1; | |
71 | ||
15bbde2b | 72 | /* Highest label number in current function. |
73 | Zero means use the value of label_num instead. | |
74 | This is nonzero only when belatedly compiling an inline function. */ | |
75 | ||
76 | static int last_label_num; | |
77 | ||
78 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
79 | If label_num has not changed since then, last_label_num is valid. */ | |
80 | ||
81 | static int base_label_num; | |
82 | ||
83 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
84 | ||
85 | static int no_line_numbers; | |
86 | ||
87 | /* Commonly used rtx's, so that we only need space for one copy. | |
88 | These are initialized once for the entire compilation. | |
89 | All of these except perhaps the floating-point CONST_DOUBLEs | |
90 | are unique; no other rtx-object will be equal to any of these. */ | |
91 | ||
57c097d5 | 92 | rtx global_rtl[GR_MAX]; |
15bbde2b | 93 | |
94 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
95 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
96 | record a copy of const[012]_rtx. */ | |
97 | ||
98 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
99 | ||
1a60f06a | 100 | rtx const_true_rtx; |
101 | ||
15bbde2b | 102 | REAL_VALUE_TYPE dconst0; |
103 | REAL_VALUE_TYPE dconst1; | |
104 | REAL_VALUE_TYPE dconst2; | |
105 | REAL_VALUE_TYPE dconstm1; | |
106 | ||
107 | /* All references to the following fixed hard registers go through | |
108 | these unique rtl objects. On machines where the frame-pointer and | |
109 | arg-pointer are the same register, they use the same unique object. | |
110 | ||
111 | After register allocation, other rtl objects which used to be pseudo-regs | |
112 | may be clobbered to refer to the frame-pointer register. | |
113 | But references that were originally to the frame-pointer can be | |
114 | distinguished from the others because they contain frame_pointer_rtx. | |
115 | ||
90c25824 | 116 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
117 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
118 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
119 | register elimination hard_frame_pointer_rtx should always be used. | |
120 | On machines where the two registers are same (most) then these are the | |
121 | same. | |
122 | ||
15bbde2b | 123 | In an inline procedure, the stack and frame pointer rtxs may not be |
124 | used for anything else. */ | |
15bbde2b | 125 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
126 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
127 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
128 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
129 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
130 | ||
4b0c5859 | 131 | /* This is used to implement __builtin_return_address for some machines. |
132 | See for instance the MIPS port. */ | |
133 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
134 | ||
15bbde2b | 135 | /* We make one copy of (const_int C) where C is in |
136 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
137 | to save space during the compilation and simplify comparisons of | |
138 | integers. */ | |
139 | ||
57c097d5 | 140 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
15bbde2b | 141 | |
73f5c1e3 | 142 | /* A hash table storing CONST_INTs whose absolute value is greater |
143 | than MAX_SAVED_CONST_INT. */ | |
144 | ||
145 | static htab_t const_int_htab; | |
146 | ||
15bbde2b | 147 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
148 | shortly thrown away. We use two mechanisms to prevent this waste: | |
149 | ||
1bfd55c5 | 150 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
151 | rtvec for use by gen_sequence. One entry for each size is | |
152 | sufficient because most cases are calls to gen_sequence followed by | |
153 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
154 | sequence is destructive on the insn in it anyway and hence can't be | |
155 | redone. | |
15bbde2b | 156 | |
157 | We do not bother to save this cached data over nested function calls. | |
158 | Instead, we just reinitialize them. */ | |
159 | ||
160 | #define SEQUENCE_RESULT_SIZE 5 | |
161 | ||
15bbde2b | 162 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
163 | ||
a92771b8 | 164 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
575333f9 | 165 | static rtx free_insn; |
166 | ||
08513b52 | 167 | #define first_insn (cfun->emit->x_first_insn) |
168 | #define last_insn (cfun->emit->x_last_insn) | |
169 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
170 | #define last_linenum (cfun->emit->x_last_linenum) | |
171 | #define last_filename (cfun->emit->x_last_filename) | |
172 | #define first_label_num (cfun->emit->x_first_label_num) | |
15bbde2b | 173 | |
621f6678 | 174 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
175 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
176 | static rtx find_line_note PARAMS ((rtx)); | |
177 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
2d96a59a | 178 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
72ec8878 | 179 | static void unshare_all_decls PARAMS ((tree)); |
01dc9f0c | 180 | static void reset_used_decls PARAMS ((tree)); |
73f5c1e3 | 181 | static hashval_t const_int_htab_hash PARAMS ((const void *)); |
182 | static int const_int_htab_eq PARAMS ((const void *, | |
183 | const void *)); | |
184 | static int rtx_htab_mark_1 PARAMS ((void **, void *)); | |
185 | static void rtx_htab_mark PARAMS ((void *)); | |
186 | ||
649d8da6 | 187 | \f |
73f5c1e3 | 188 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
189 | ||
190 | static hashval_t | |
191 | const_int_htab_hash (x) | |
192 | const void *x; | |
193 | { | |
5e431971 | 194 | return (hashval_t) INTVAL ((const struct rtx_def *) x); |
73f5c1e3 | 195 | } |
196 | ||
197 | /* Returns non-zero if the value represented by X (which is really a | |
198 | CONST_INT) is the same as that given by Y (which is really a | |
199 | HOST_WIDE_INT *). */ | |
200 | ||
201 | static int | |
202 | const_int_htab_eq (x, y) | |
203 | const void *x; | |
204 | const void *y; | |
205 | { | |
5e431971 | 206 | return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y)); |
73f5c1e3 | 207 | } |
208 | ||
209 | /* Mark the hash-table element X (which is really a pointer to an | |
210 | rtx). */ | |
211 | ||
212 | static int | |
213 | rtx_htab_mark_1 (x, data) | |
214 | void **x; | |
215 | void *data ATTRIBUTE_UNUSED; | |
216 | { | |
217 | ggc_mark_rtx (*x); | |
218 | return 1; | |
219 | } | |
220 | ||
221 | /* Mark all the elements of HTAB (which is really an htab_t full of | |
222 | rtxs). */ | |
223 | ||
224 | static void | |
225 | rtx_htab_mark (htab) | |
226 | void *htab; | |
227 | { | |
228 | htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL); | |
229 | } | |
230 | ||
7014838c | 231 | /* There are some RTL codes that require special attention; the generation |
232 | functions do the raw handling. If you add to this list, modify | |
233 | special_rtx in gengenrtl.c as well. */ | |
234 | ||
3ad7bb1c | 235 | rtx |
236 | gen_rtx_CONST_INT (mode, arg) | |
73f5c1e3 | 237 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3ad7bb1c | 238 | HOST_WIDE_INT arg; |
239 | { | |
73f5c1e3 | 240 | void **slot; |
241 | ||
3ad7bb1c | 242 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
57c097d5 | 243 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3ad7bb1c | 244 | |
245 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
246 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
247 | return const_true_rtx; | |
248 | #endif | |
249 | ||
73f5c1e3 | 250 | /* Look up the CONST_INT in the hash table. */ |
2b3dbc20 | 251 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
252 | (hashval_t) arg, INSERT); | |
7f2875d3 | 253 | if (*slot == 0) |
d7c47c0e | 254 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
73f5c1e3 | 255 | |
256 | return (rtx) *slot; | |
3ad7bb1c | 257 | } |
258 | ||
7f2875d3 | 259 | /* CONST_DOUBLEs needs special handling because their length is known |
67f2a2eb | 260 | only at run-time. */ |
7f2875d3 | 261 | |
67f2a2eb | 262 | rtx |
263 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
264 | enum machine_mode mode; | |
265 | rtx arg0; | |
266 | HOST_WIDE_INT arg1, arg2; | |
267 | { | |
268 | rtx r = rtx_alloc (CONST_DOUBLE); | |
4e929432 | 269 | int i; |
270 | ||
67f2a2eb | 271 | PUT_MODE (r, mode); |
272 | XEXP (r, 0) = arg0; | |
25999090 | 273 | X0EXP (r, 1) = NULL_RTX; |
4e929432 | 274 | XWINT (r, 2) = arg1; |
275 | XWINT (r, 3) = arg2; | |
276 | ||
277 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
278 | XWINT (r, i) = 0; | |
279 | ||
67f2a2eb | 280 | return r; |
281 | } | |
282 | ||
3ad7bb1c | 283 | rtx |
284 | gen_rtx_REG (mode, regno) | |
285 | enum machine_mode mode; | |
286 | int regno; | |
287 | { | |
288 | /* In case the MD file explicitly references the frame pointer, have | |
289 | all such references point to the same frame pointer. This is | |
290 | used during frame pointer elimination to distinguish the explicit | |
291 | references to these registers from pseudos that happened to be | |
292 | assigned to them. | |
293 | ||
294 | If we have eliminated the frame pointer or arg pointer, we will | |
295 | be using it as a normal register, for example as a spill | |
296 | register. In such cases, we might be accessing it in a mode that | |
297 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
298 | ||
299 | Also don't do this when we are making new REGs in reload, since | |
300 | we don't want to get confused with the real pointers. */ | |
301 | ||
302 | if (mode == Pmode && !reload_in_progress) | |
303 | { | |
e8b59353 | 304 | if (regno == FRAME_POINTER_REGNUM) |
3ad7bb1c | 305 | return frame_pointer_rtx; |
306 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e8b59353 | 307 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3ad7bb1c | 308 | return hard_frame_pointer_rtx; |
309 | #endif | |
310 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
e8b59353 | 311 | if (regno == ARG_POINTER_REGNUM) |
3ad7bb1c | 312 | return arg_pointer_rtx; |
313 | #endif | |
314 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
e8b59353 | 315 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3ad7bb1c | 316 | return return_address_pointer_rtx; |
317 | #endif | |
e8b59353 | 318 | if (regno == STACK_POINTER_REGNUM) |
3ad7bb1c | 319 | return stack_pointer_rtx; |
320 | } | |
321 | ||
322 | return gen_rtx_raw_REG (mode, regno); | |
323 | } | |
324 | ||
b5ba9f3a | 325 | rtx |
326 | gen_rtx_MEM (mode, addr) | |
327 | enum machine_mode mode; | |
328 | rtx addr; | |
329 | { | |
330 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
331 | ||
332 | /* This field is not cleared by the mere allocation of the rtx, so | |
333 | we clear it here. */ | |
334 | MEM_ALIAS_SET (rt) = 0; | |
335 | ||
336 | return rt; | |
337 | } | |
7014838c | 338 | \f |
15bbde2b | 339 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
340 | ** | |
341 | ** This routine generates an RTX of the size specified by | |
342 | ** <code>, which is an RTX code. The RTX structure is initialized | |
343 | ** from the arguments <element1> through <elementn>, which are | |
344 | ** interpreted according to the specific RTX type's format. The | |
345 | ** special machine mode associated with the rtx (if any) is specified | |
346 | ** in <mode>. | |
347 | ** | |
fc92fa61 | 348 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
15bbde2b | 349 | ** rtx it will generate. For example, the following rtx structure: |
350 | ** | |
351 | ** (plus:QI (mem:QI (reg:SI 1)) | |
352 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
353 | ** | |
354 | ** ...would be generated by the following C code: | |
355 | ** | |
356 | ** gen_rtx (PLUS, QImode, | |
357 | ** gen_rtx (MEM, QImode, | |
358 | ** gen_rtx (REG, SImode, 1)), | |
359 | ** gen_rtx (MEM, QImode, | |
360 | ** gen_rtx (PLUS, SImode, | |
361 | ** gen_rtx (REG, SImode, 2), | |
362 | ** gen_rtx (REG, SImode, 3)))), | |
363 | */ | |
364 | ||
365 | /*VARARGS2*/ | |
366 | rtx | |
621f6678 | 367 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
15bbde2b | 368 | { |
7bca031c | 369 | #ifndef ANSI_PROTOTYPES |
15bbde2b | 370 | enum rtx_code code; |
371 | enum machine_mode mode; | |
e5fcd76a | 372 | #endif |
373 | va_list p; | |
15bbde2b | 374 | register int i; /* Array indices... */ |
d2ca078f | 375 | register const char *fmt; /* Current rtx's format... */ |
15bbde2b | 376 | register rtx rt_val; /* RTX to return to caller... */ |
377 | ||
e5fcd76a | 378 | VA_START (p, mode); |
379 | ||
7bca031c | 380 | #ifndef ANSI_PROTOTYPES |
15bbde2b | 381 | code = va_arg (p, enum rtx_code); |
382 | mode = va_arg (p, enum machine_mode); | |
e5fcd76a | 383 | #endif |
15bbde2b | 384 | |
67f2a2eb | 385 | switch (code) |
15bbde2b | 386 | { |
67f2a2eb | 387 | case CONST_INT: |
388 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
389 | break; | |
390 | ||
391 | case CONST_DOUBLE: | |
392 | { | |
393 | rtx arg0 = va_arg (p, rtx); | |
394 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
395 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
396 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
397 | } | |
398 | break; | |
399 | ||
400 | case REG: | |
401 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
402 | break; | |
403 | ||
404 | case MEM: | |
405 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
406 | break; | |
407 | ||
408 | default: | |
15bbde2b | 409 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
410 | rt_val->mode = mode; /* Store the machine mode... */ | |
411 | ||
412 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
413 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
414 | { | |
415 | switch (*fmt++) | |
416 | { | |
417 | case '0': /* Unused field. */ | |
418 | break; | |
419 | ||
420 | case 'i': /* An integer? */ | |
421 | XINT (rt_val, i) = va_arg (p, int); | |
422 | break; | |
423 | ||
b572011e | 424 | case 'w': /* A wide integer? */ |
425 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
426 | break; | |
427 | ||
15bbde2b | 428 | case 's': /* A string? */ |
429 | XSTR (rt_val, i) = va_arg (p, char *); | |
430 | break; | |
431 | ||
432 | case 'e': /* An expression? */ | |
433 | case 'u': /* An insn? Same except when printing. */ | |
434 | XEXP (rt_val, i) = va_arg (p, rtx); | |
435 | break; | |
436 | ||
437 | case 'E': /* An RTX vector? */ | |
438 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
439 | break; | |
440 | ||
a3426c4c | 441 | case 'b': /* A bitmap? */ |
442 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
443 | break; | |
444 | ||
445 | case 't': /* A tree? */ | |
446 | XTREE (rt_val, i) = va_arg (p, tree); | |
447 | break; | |
448 | ||
15bbde2b | 449 | default: |
fc92fa61 | 450 | abort (); |
15bbde2b | 451 | } |
452 | } | |
67f2a2eb | 453 | break; |
15bbde2b | 454 | } |
67f2a2eb | 455 | |
15bbde2b | 456 | va_end (p); |
67f2a2eb | 457 | return rt_val; |
15bbde2b | 458 | } |
459 | ||
460 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
461 | ** | |
462 | ** This routine creates an rtvec and stores within it the | |
463 | ** pointers to rtx's which are its arguments. | |
464 | */ | |
465 | ||
466 | /*VARARGS1*/ | |
467 | rtvec | |
621f6678 | 468 | gen_rtvec VPARAMS ((int n, ...)) |
15bbde2b | 469 | { |
7bca031c | 470 | #ifndef ANSI_PROTOTYPES |
e5fcd76a | 471 | int n; |
472 | #endif | |
473 | int i; | |
15bbde2b | 474 | va_list p; |
475 | rtx *vector; | |
476 | ||
e5fcd76a | 477 | VA_START (p, n); |
478 | ||
7bca031c | 479 | #ifndef ANSI_PROTOTYPES |
15bbde2b | 480 | n = va_arg (p, int); |
e5fcd76a | 481 | #endif |
15bbde2b | 482 | |
483 | if (n == 0) | |
484 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
485 | ||
486 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
e5fcd76a | 487 | |
15bbde2b | 488 | for (i = 0; i < n; i++) |
489 | vector[i] = va_arg (p, rtx); | |
490 | va_end (p); | |
491 | ||
492 | return gen_rtvec_v (n, vector); | |
493 | } | |
494 | ||
495 | rtvec | |
496 | gen_rtvec_v (n, argp) | |
497 | int n; | |
498 | rtx *argp; | |
499 | { | |
500 | register int i; | |
501 | register rtvec rt_val; | |
502 | ||
503 | if (n == 0) | |
504 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
505 | ||
506 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
507 | ||
508 | for (i = 0; i < n; i++) | |
a4070a91 | 509 | rt_val->elem[i] = *argp++; |
15bbde2b | 510 | |
511 | return rt_val; | |
512 | } | |
fbaa9422 | 513 | |
15bbde2b | 514 | \f |
515 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
516 | This pseudo is assigned the next sequential register number. */ | |
517 | ||
518 | rtx | |
519 | gen_reg_rtx (mode) | |
520 | enum machine_mode mode; | |
521 | { | |
08513b52 | 522 | struct function *f = cfun; |
15bbde2b | 523 | register rtx val; |
524 | ||
9e519b97 | 525 | /* Don't let anything called after initial flow analysis create new |
526 | registers. */ | |
527 | if (no_new_pseudos) | |
15bbde2b | 528 | abort (); |
529 | ||
316bc009 | 530 | if (generating_concat_p |
531 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
532 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
76c37538 | 533 | { |
534 | /* For complex modes, don't make a single pseudo. | |
535 | Instead, make a CONCAT of two pseudos. | |
536 | This allows noncontiguous allocation of the real and imaginary parts, | |
537 | which makes much better code. Besides, allocating DCmode | |
538 | pseudos overstrains reload on some machines like the 386. */ | |
539 | rtx realpart, imagpart; | |
540 | int size = GET_MODE_UNIT_SIZE (mode); | |
541 | enum machine_mode partmode | |
542 | = mode_for_size (size * BITS_PER_UNIT, | |
543 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
544 | ? MODE_FLOAT : MODE_INT), | |
545 | 0); | |
546 | ||
547 | realpart = gen_reg_rtx (partmode); | |
548 | imagpart = gen_reg_rtx (partmode); | |
3ad7bb1c | 549 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
76c37538 | 550 | } |
551 | ||
15bbde2b | 552 | /* Make sure regno_pointer_flag and regno_reg_rtx are large |
553 | enough to have an element for this pseudo reg number. */ | |
554 | ||
0a893c29 | 555 | if (reg_rtx_no == f->emit->regno_pointer_flag_length) |
15bbde2b | 556 | { |
0a893c29 | 557 | int old_size = f->emit->regno_pointer_flag_length; |
15bbde2b | 558 | rtx *new1; |
26df1c5e | 559 | char *new; |
560 | new = xrealloc (f->emit->regno_pointer_flag, old_size * 2); | |
0a893c29 | 561 | memset (new + old_size, 0, old_size); |
562 | f->emit->regno_pointer_flag = new; | |
563 | ||
26df1c5e | 564 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
0a893c29 | 565 | memset (new + old_size, 0, old_size); |
4491f79f | 566 | f->emit->regno_pointer_align = (unsigned char *) new; |
0a893c29 | 567 | |
26df1c5e | 568 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
569 | old_size * 2 * sizeof (rtx)); | |
0a893c29 | 570 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
15bbde2b | 571 | regno_reg_rtx = new1; |
572 | ||
0a893c29 | 573 | f->emit->regno_pointer_flag_length = old_size * 2; |
15bbde2b | 574 | } |
575 | ||
3ad7bb1c | 576 | val = gen_rtx_raw_REG (mode, reg_rtx_no); |
15bbde2b | 577 | regno_reg_rtx[reg_rtx_no++] = val; |
578 | return val; | |
579 | } | |
580 | ||
de8ecfb5 | 581 | /* Identify REG (which may be a CONCAT) as a user register. */ |
582 | ||
583 | void | |
584 | mark_user_reg (reg) | |
585 | rtx reg; | |
586 | { | |
587 | if (GET_CODE (reg) == CONCAT) | |
588 | { | |
589 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
590 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
591 | } | |
592 | else if (GET_CODE (reg) == REG) | |
593 | REG_USERVAR_P (reg) = 1; | |
594 | else | |
595 | abort (); | |
596 | } | |
597 | ||
d4c332ff | 598 | /* Identify REG as a probable pointer register and show its alignment |
599 | as ALIGN, if nonzero. */ | |
15bbde2b | 600 | |
601 | void | |
d4c332ff | 602 | mark_reg_pointer (reg, align) |
15bbde2b | 603 | rtx reg; |
d4c332ff | 604 | int align; |
15bbde2b | 605 | { |
612409a6 | 606 | if (! REGNO_POINTER_FLAG (REGNO (reg))) |
607 | { | |
608 | REGNO_POINTER_FLAG (REGNO (reg)) = 1; | |
d4c332ff | 609 | |
612409a6 | 610 | if (align) |
611 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
612 | } | |
613 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
614 | /* We can no-longer be sure just how aligned this pointer is */ | |
d4c332ff | 615 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
15bbde2b | 616 | } |
617 | ||
618 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
619 | ||
620 | int | |
621 | max_reg_num () | |
622 | { | |
623 | return reg_rtx_no; | |
624 | } | |
625 | ||
626 | /* Return 1 + the largest label number used so far in the current function. */ | |
627 | ||
628 | int | |
629 | max_label_num () | |
630 | { | |
631 | if (last_label_num && label_num == base_label_num) | |
632 | return last_label_num; | |
633 | return label_num; | |
634 | } | |
635 | ||
636 | /* Return first label number used in this function (if any were used). */ | |
637 | ||
638 | int | |
639 | get_first_label_num () | |
640 | { | |
641 | return first_label_num; | |
642 | } | |
643 | \f | |
644 | /* Return a value representing some low-order bits of X, where the number | |
645 | of low-order bits is given by MODE. Note that no conversion is done | |
646 | between floating-point and fixed-point values, rather, the bit | |
647 | representation is returned. | |
648 | ||
649 | This function handles the cases in common between gen_lowpart, below, | |
650 | and two variants in cse.c and combine.c. These are the cases that can | |
651 | be safely handled at all points in the compilation. | |
652 | ||
653 | If this is not a case we can handle, return 0. */ | |
654 | ||
655 | rtx | |
656 | gen_lowpart_common (mode, x) | |
657 | enum machine_mode mode; | |
658 | register rtx x; | |
659 | { | |
660 | int word = 0; | |
661 | ||
662 | if (GET_MODE (x) == mode) | |
663 | return x; | |
664 | ||
665 | /* MODE must occupy no more words than the mode of X. */ | |
666 | if (GET_MODE (x) != VOIDmode | |
667 | && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD | |
668 | > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1)) | |
669 | / UNITS_PER_WORD))) | |
670 | return 0; | |
671 | ||
672 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
673 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
674 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
675 | / UNITS_PER_WORD); | |
676 | ||
677 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
64115b39 | 678 | && (GET_MODE_CLASS (mode) == MODE_INT |
679 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
15bbde2b | 680 | { |
681 | /* If we are getting the low-order part of something that has been | |
682 | sign- or zero-extended, we can either just use the object being | |
683 | extended or make a narrower extension. If we want an even smaller | |
684 | piece than the size of the object being extended, call ourselves | |
685 | recursively. | |
686 | ||
687 | This case is used mostly by combine and cse. */ | |
688 | ||
689 | if (GET_MODE (XEXP (x, 0)) == mode) | |
690 | return XEXP (x, 0); | |
691 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
692 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
693 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3ad7bb1c | 694 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
15bbde2b | 695 | } |
696 | else if (GET_CODE (x) == SUBREG | |
8a7af1a8 | 697 | && (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) |
698 | || GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
15bbde2b | 699 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) |
700 | return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0 | |
701 | ? SUBREG_REG (x) | |
3ad7bb1c | 702 | : gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + word)); |
15bbde2b | 703 | else if (GET_CODE (x) == REG) |
704 | { | |
cfff67e2 | 705 | /* Let the backend decide how many registers to skip. This is needed |
706 | in particular for Sparc64 where fp regs are smaller than a word. */ | |
707 | /* ??? Note that subregs are now ambiguous, in that those against | |
708 | pseudos are sized by the Word Size, while those against hard | |
709 | regs are sized by the underlying register size. Better would be | |
710 | to always interpret the subreg offset parameter as bytes or bits. */ | |
711 | ||
712 | if (WORDS_BIG_ENDIAN && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
713 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) | |
714 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
715 | ||
15bbde2b | 716 | /* If the register is not valid for MODE, return 0. If we don't |
c84a933e | 717 | do this, there is no way to fix up the resulting REG later. |
718 | But we do do this if the current REG is not valid for its | |
719 | mode. This latter is a kludge, but is required due to the | |
720 | way that parameters are passed on some machines, most | |
721 | notably Sparc. */ | |
15bbde2b | 722 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
c84a933e | 723 | && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode) |
724 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
15bbde2b | 725 | return 0; |
726 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
727 | /* integrate.c can't handle parts of a return value register. */ | |
728 | && (! REG_FUNCTION_VALUE_P (x) | |
8dc5a78e | 729 | || ! rtx_equal_function_value_matters) |
c5af420e | 730 | #ifdef CLASS_CANNOT_CHANGE_MODE |
731 | && ! (CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (x)) | |
c6b6c51f | 732 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT |
733 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT | |
734 | && (TEST_HARD_REG_BIT | |
c5af420e | 735 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], |
c6b6c51f | 736 | REGNO (x)))) |
737 | #endif | |
8dc5a78e | 738 | /* We want to keep the stack, frame, and arg pointers |
739 | special. */ | |
c1c63d0b | 740 | && x != frame_pointer_rtx |
8dc5a78e | 741 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
c1c63d0b | 742 | && x != arg_pointer_rtx |
8dc5a78e | 743 | #endif |
c1c63d0b | 744 | && x != stack_pointer_rtx) |
3ad7bb1c | 745 | return gen_rtx_REG (mode, REGNO (x) + word); |
15bbde2b | 746 | else |
3ad7bb1c | 747 | return gen_rtx_SUBREG (mode, x, word); |
15bbde2b | 748 | } |
15bbde2b | 749 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
750 | from the low-order part of the constant. */ | |
64115b39 | 751 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
752 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
753 | && GET_MODE (x) == VOIDmode | |
15bbde2b | 754 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
99e0010b | 755 | { |
756 | /* If MODE is twice the host word size, X is already the desired | |
757 | representation. Otherwise, if MODE is wider than a word, we can't | |
b3b27b2a | 758 | do this. If MODE is exactly a word, return just one CONST_INT. */ |
99e0010b | 759 | |
d347deeb | 760 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
99e0010b | 761 | return x; |
b572011e | 762 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
99e0010b | 763 | return 0; |
b572011e | 764 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
99e0010b | 765 | return (GET_CODE (x) == CONST_INT ? x |
b572011e | 766 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
99e0010b | 767 | else |
768 | { | |
a0d52dee | 769 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
b572011e | 770 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
771 | : CONST_DOUBLE_LOW (x)); | |
99e0010b | 772 | |
a0d52dee | 773 | /* Sign extend to HOST_WIDE_INT. */ |
b3b27b2a | 774 | val = trunc_int_for_mode (val, mode); |
99e0010b | 775 | |
776 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
b572011e | 777 | : GEN_INT (val)); |
99e0010b | 778 | } |
779 | } | |
15bbde2b | 780 | |
c8971cad | 781 | #ifndef REAL_ARITHMETIC |
4a307dd5 | 782 | /* If X is an integral constant but we want it in floating-point, it |
783 | must be the case that we have a union of an integer and a floating-point | |
784 | value. If the machine-parameters allow it, simulate that union here | |
414a3664 | 785 | and return the result. The two-word and single-word cases are |
786 | different. */ | |
4a307dd5 | 787 | |
f51cb679 | 788 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 789 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
f51cb679 | 790 | || flag_pretend_float) |
4a307dd5 | 791 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
414a3664 | 792 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
793 | && GET_CODE (x) == CONST_INT | |
b572011e | 794 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
414a3664 | 795 | { |
b572011e | 796 | union {HOST_WIDE_INT i; float d; } u; |
414a3664 | 797 | |
798 | u.i = INTVAL (x); | |
715907c0 | 799 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
414a3664 | 800 | } |
414a3664 | 801 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 802 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
414a3664 | 803 | || flag_pretend_float) |
804 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
805 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
4a307dd5 | 806 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
807 | && GET_MODE (x) == VOIDmode | |
b572011e | 808 | && (sizeof (double) * HOST_BITS_PER_CHAR |
809 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
4a307dd5 | 810 | { |
b572011e | 811 | union {HOST_WIDE_INT i[2]; double d; } u; |
812 | HOST_WIDE_INT low, high; | |
4a307dd5 | 813 | |
814 | if (GET_CODE (x) == CONST_INT) | |
b572011e | 815 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
4a307dd5 | 816 | else |
817 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
818 | ||
819 | #ifdef HOST_WORDS_BIG_ENDIAN | |
820 | u.i[0] = high, u.i[1] = low; | |
821 | #else | |
822 | u.i[0] = low, u.i[1] = high; | |
823 | #endif | |
824 | ||
715907c0 | 825 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
4a307dd5 | 826 | } |
e21bed9e | 827 | |
f51cb679 | 828 | /* Similarly, if this is converting a floating-point value into a |
829 | single-word integer. Only do this is the host and target parameters are | |
830 | compatible. */ | |
831 | ||
832 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
b572011e | 833 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
f51cb679 | 834 | || flag_pretend_float) |
64115b39 | 835 | && (GET_MODE_CLASS (mode) == MODE_INT |
836 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
f51cb679 | 837 | && GET_CODE (x) == CONST_DOUBLE |
838 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
839 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
ff2f5877 | 840 | return operand_subword (x, word, 0, GET_MODE (x)); |
f51cb679 | 841 | |
4a307dd5 | 842 | /* Similarly, if this is converting a floating-point value into a |
843 | two-word integer, we can do this one word at a time and make an | |
844 | integer. Only do this is the host and target parameters are | |
845 | compatible. */ | |
846 | ||
f51cb679 | 847 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 848 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
f51cb679 | 849 | || flag_pretend_float) |
64115b39 | 850 | && (GET_MODE_CLASS (mode) == MODE_INT |
6ff0332a | 851 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
4a307dd5 | 852 | && GET_CODE (x) == CONST_DOUBLE |
853 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
854 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
855 | { | |
ff2f5877 | 856 | rtx lowpart |
857 | = operand_subword (x, word + WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
858 | rtx highpart | |
859 | = operand_subword (x, word + ! WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
4a307dd5 | 860 | |
861 | if (lowpart && GET_CODE (lowpart) == CONST_INT | |
862 | && highpart && GET_CODE (highpart) == CONST_INT) | |
863 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
864 | } | |
c8971cad | 865 | #else /* ifndef REAL_ARITHMETIC */ |
866 | ||
867 | /* When we have a FP emulator, we can handle all conversions between | |
868 | FP and integer operands. This simplifies reload because it | |
869 | doesn't have to deal with constructs like (subreg:DI | |
870 | (const_double:SF ...)) or (subreg:DF (const_int ...)). */ | |
871 | ||
872 | else if (mode == SFmode | |
873 | && GET_CODE (x) == CONST_INT) | |
874 | { | |
875 | REAL_VALUE_TYPE r; | |
876 | HOST_WIDE_INT i; | |
877 | ||
878 | i = INTVAL (x); | |
879 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
880 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
881 | } | |
882 | else if (mode == DFmode | |
883 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
884 | && GET_MODE (x) == VOIDmode) | |
885 | { | |
886 | REAL_VALUE_TYPE r; | |
887 | HOST_WIDE_INT i[2]; | |
888 | HOST_WIDE_INT low, high; | |
889 | ||
890 | if (GET_CODE (x) == CONST_INT) | |
891 | { | |
892 | low = INTVAL (x); | |
893 | high = low >> (HOST_BITS_PER_WIDE_INT - 1); | |
894 | } | |
895 | else | |
896 | { | |
897 | low = CONST_DOUBLE_LOW (x); | |
898 | high = CONST_DOUBLE_HIGH (x); | |
899 | } | |
900 | ||
901 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the | |
902 | target machine. */ | |
903 | if (WORDS_BIG_ENDIAN) | |
904 | i[0] = high, i[1] = low; | |
905 | else | |
906 | i[0] = low, i[1] = high; | |
907 | ||
908 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
909 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
910 | } | |
911 | else if ((GET_MODE_CLASS (mode) == MODE_INT | |
912 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
913 | && GET_CODE (x) == CONST_DOUBLE | |
914 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
915 | { | |
916 | REAL_VALUE_TYPE r; | |
917 | long i[4]; /* Only the low 32 bits of each 'long' are used. */ | |
918 | int endian = WORDS_BIG_ENDIAN ? 1 : 0; | |
919 | ||
920 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
921 | switch (GET_MODE (x)) | |
922 | { | |
923 | case SFmode: | |
924 | REAL_VALUE_TO_TARGET_SINGLE (r, i[endian]); | |
a774762c | 925 | i[1 - endian] = 0; |
c8971cad | 926 | break; |
927 | case DFmode: | |
928 | REAL_VALUE_TO_TARGET_DOUBLE (r, i); | |
929 | break; | |
930 | #if LONG_DOUBLE_TYPE_SIZE == 96 | |
931 | case XFmode: | |
3f980cf7 | 932 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i + endian); |
933 | i[3-3*endian] = 0; | |
c8971cad | 934 | #else |
935 | case TFmode: | |
c8971cad | 936 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i); |
3f980cf7 | 937 | #endif |
c8971cad | 938 | break; |
939 | default: | |
a774762c | 940 | abort (); |
c8971cad | 941 | } |
942 | ||
943 | /* Now, pack the 32-bit elements of the array into a CONST_DOUBLE | |
944 | and return it. */ | |
945 | #if HOST_BITS_PER_WIDE_INT == 32 | |
a774762c | 946 | return immed_double_const (i[endian], i[1 - endian], mode); |
c8971cad | 947 | #else |
83e32a86 | 948 | { |
949 | int c; | |
950 | ||
951 | if (HOST_BITS_PER_WIDE_INT != 64) | |
a774762c | 952 | abort (); |
953 | ||
83e32a86 | 954 | for (c = 0; c < 4; c++) |
a774762c | 955 | i[c] &= ~ (0L); |
3f980cf7 | 956 | |
957 | switch (GET_MODE (x)) | |
958 | { | |
959 | case SFmode: | |
960 | case DFmode: | |
961 | return immed_double_const (((unsigned long) i[endian]) | | |
962 | (((HOST_WIDE_INT) i[1-endian]) << 32), | |
963 | 0, mode); | |
964 | default: | |
965 | return immed_double_const (((unsigned long) i[endian*3]) | | |
966 | (((HOST_WIDE_INT) i[1+endian]) << 32), | |
967 | ((unsigned long) i[2-endian]) | | |
968 | (((HOST_WIDE_INT) i[3-endian*3]) << 32), | |
969 | mode); | |
970 | } | |
83e32a86 | 971 | } |
c8971cad | 972 | #endif |
973 | } | |
974 | #endif /* ifndef REAL_ARITHMETIC */ | |
4a307dd5 | 975 | |
15bbde2b | 976 | /* Otherwise, we can't do this. */ |
977 | return 0; | |
978 | } | |
979 | \f | |
568f439b | 980 | /* Return the real part (which has mode MODE) of a complex value X. |
981 | This always comes at the low address in memory. */ | |
982 | ||
983 | rtx | |
984 | gen_realpart (mode, x) | |
985 | enum machine_mode mode; | |
986 | register rtx x; | |
987 | { | |
0864dc1b | 988 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
989 | return XEXP (x, 0); | |
ea9a92b6 | 990 | else if (WORDS_BIG_ENDIAN |
991 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
992 | && REG_P (x) | |
993 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
994 | fatal ("Unable to access real part of complex value in a hard register on this target"); | |
0864dc1b | 995 | else if (WORDS_BIG_ENDIAN) |
568f439b | 996 | return gen_highpart (mode, x); |
997 | else | |
998 | return gen_lowpart (mode, x); | |
999 | } | |
1000 | ||
1001 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
1002 | This always comes at the high address in memory. */ | |
1003 | ||
1004 | rtx | |
1005 | gen_imagpart (mode, x) | |
1006 | enum machine_mode mode; | |
1007 | register rtx x; | |
1008 | { | |
0864dc1b | 1009 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
1010 | return XEXP (x, 1); | |
1011 | else if (WORDS_BIG_ENDIAN) | |
568f439b | 1012 | return gen_lowpart (mode, x); |
ea9a92b6 | 1013 | else if (!WORDS_BIG_ENDIAN |
1014 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
1015 | && REG_P (x) | |
1016 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1017 | fatal ("Unable to access imaginary part of complex value in a hard register on this target"); | |
568f439b | 1018 | else |
1019 | return gen_highpart (mode, x); | |
1020 | } | |
48c70a46 | 1021 | |
1022 | /* Return 1 iff X, assumed to be a SUBREG, | |
1023 | refers to the real part of the complex value in its containing reg. | |
1024 | Complex values are always stored with the real part in the first word, | |
1025 | regardless of WORDS_BIG_ENDIAN. */ | |
1026 | ||
1027 | int | |
1028 | subreg_realpart_p (x) | |
1029 | rtx x; | |
1030 | { | |
1031 | if (GET_CODE (x) != SUBREG) | |
1032 | abort (); | |
1033 | ||
02e7a332 | 1034 | return ((unsigned int) SUBREG_WORD (x) * UNITS_PER_WORD |
1035 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); | |
48c70a46 | 1036 | } |
568f439b | 1037 | \f |
15bbde2b | 1038 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1039 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1040 | least-significant part of X. | |
1041 | MODE specifies how big a part of X to return; | |
1042 | it usually should not be larger than a word. | |
1043 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1044 | ||
1045 | rtx | |
1046 | gen_lowpart (mode, x) | |
1047 | enum machine_mode mode; | |
1048 | register rtx x; | |
1049 | { | |
1050 | rtx result = gen_lowpart_common (mode, x); | |
1051 | ||
1052 | if (result) | |
1053 | return result; | |
365c9063 | 1054 | else if (GET_CODE (x) == REG) |
1055 | { | |
1056 | /* Must be a hard reg that's not valid in MODE. */ | |
1057 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1058 | if (result == 0) | |
1059 | abort (); | |
314d6ec8 | 1060 | return result; |
365c9063 | 1061 | } |
15bbde2b | 1062 | else if (GET_CODE (x) == MEM) |
1063 | { | |
1064 | /* The only additional case we can do is MEM. */ | |
1065 | register int offset = 0; | |
1066 | if (WORDS_BIG_ENDIAN) | |
1067 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1068 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1069 | ||
1070 | if (BYTES_BIG_ENDIAN) | |
1071 | /* Adjust the address so that the address-after-the-data | |
1072 | is unchanged. */ | |
1073 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1074 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1075 | ||
1076 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
1077 | } | |
0dbd1c74 | 1078 | else if (GET_CODE (x) == ADDRESSOF) |
1079 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
15bbde2b | 1080 | else |
1081 | abort (); | |
1082 | } | |
1083 | ||
d56d0ca2 | 1084 | /* Like `gen_lowpart', but refer to the most significant part. |
1085 | This is used to access the imaginary part of a complex number. */ | |
1086 | ||
1087 | rtx | |
1088 | gen_highpart (mode, x) | |
1089 | enum machine_mode mode; | |
1090 | register rtx x; | |
1091 | { | |
1092 | /* This case loses if X is a subreg. To catch bugs early, | |
1093 | complain if an invalid MODE is used even in other cases. */ | |
1094 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
1095 | && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
1096 | abort (); | |
1097 | if (GET_CODE (x) == CONST_DOUBLE | |
fc92fa61 | 1098 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
d56d0ca2 | 1099 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
1100 | #endif | |
1101 | ) | |
3ad7bb1c | 1102 | return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); |
d56d0ca2 | 1103 | else if (GET_CODE (x) == CONST_INT) |
a0d52dee | 1104 | { |
1105 | if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD) | |
1106 | return const0_rtx; | |
1107 | return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD)); | |
1108 | } | |
d56d0ca2 | 1109 | else if (GET_CODE (x) == MEM) |
1110 | { | |
1111 | register int offset = 0; | |
10ef59ac | 1112 | if (! WORDS_BIG_ENDIAN) |
1113 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1114 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1115 | ||
1116 | if (! BYTES_BIG_ENDIAN | |
1117 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
d56d0ca2 | 1118 | offset -= (GET_MODE_SIZE (mode) |
1119 | - MIN (UNITS_PER_WORD, | |
1120 | GET_MODE_SIZE (GET_MODE (x)))); | |
10ef59ac | 1121 | |
d56d0ca2 | 1122 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
1123 | } | |
1124 | else if (GET_CODE (x) == SUBREG) | |
1125 | { | |
1126 | /* The only time this should occur is when we are looking at a | |
1127 | multi-word item with a SUBREG whose mode is the same as that of the | |
1128 | item. It isn't clear what we would do if it wasn't. */ | |
1129 | if (SUBREG_WORD (x) != 0) | |
1130 | abort (); | |
1131 | return gen_highpart (mode, SUBREG_REG (x)); | |
1132 | } | |
1133 | else if (GET_CODE (x) == REG) | |
1134 | { | |
6ec4ccb1 | 1135 | int word; |
d56d0ca2 | 1136 | |
cfff67e2 | 1137 | /* Let the backend decide how many registers to skip. This is needed |
1138 | in particular for sparc64 where fp regs are smaller than a word. */ | |
1139 | /* ??? Note that subregs are now ambiguous, in that those against | |
6ec4ccb1 | 1140 | pseudos are sized by the word size, while those against hard |
cfff67e2 | 1141 | regs are sized by the underlying register size. Better would be |
1142 | to always interpret the subreg offset parameter as bytes or bits. */ | |
1143 | ||
6ec4ccb1 | 1144 | if (WORDS_BIG_ENDIAN) |
1145 | word = 0; | |
1146 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
cfff67e2 | 1147 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) |
1148 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
6ec4ccb1 | 1149 | else |
1150 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
1151 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
1152 | / UNITS_PER_WORD); | |
e484899c | 1153 | |
8dc5a78e | 1154 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
a92771b8 | 1155 | /* integrate.c can't handle parts of a return value register. */ |
baeb2e0e | 1156 | && (! REG_FUNCTION_VALUE_P (x) |
1157 | || ! rtx_equal_function_value_matters) | |
8dc5a78e | 1158 | /* We want to keep the stack, frame, and arg pointers special. */ |
c1c63d0b | 1159 | && x != frame_pointer_rtx |
8dc5a78e | 1160 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
c1c63d0b | 1161 | && x != arg_pointer_rtx |
8dc5a78e | 1162 | #endif |
c1c63d0b | 1163 | && x != stack_pointer_rtx) |
3ad7bb1c | 1164 | return gen_rtx_REG (mode, REGNO (x) + word); |
d56d0ca2 | 1165 | else |
3ad7bb1c | 1166 | return gen_rtx_SUBREG (mode, x, word); |
d56d0ca2 | 1167 | } |
1168 | else | |
1169 | abort (); | |
1170 | } | |
1171 | ||
15bbde2b | 1172 | /* Return 1 iff X, assumed to be a SUBREG, |
1173 | refers to the least significant part of its containing reg. | |
1174 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1175 | ||
1176 | int | |
1177 | subreg_lowpart_p (x) | |
1178 | rtx x; | |
1179 | { | |
1180 | if (GET_CODE (x) != SUBREG) | |
1181 | return 1; | |
7e14c1bf | 1182 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1183 | return 0; | |
15bbde2b | 1184 | |
1185 | if (WORDS_BIG_ENDIAN | |
1186 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD) | |
1187 | return (SUBREG_WORD (x) | |
1188 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1189 | - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)) | |
1190 | / UNITS_PER_WORD)); | |
1191 | ||
1192 | return SUBREG_WORD (x) == 0; | |
1193 | } | |
1194 | \f | |
1195 | /* Return subword I of operand OP. | |
1196 | The word number, I, is interpreted as the word number starting at the | |
1197 | low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN, | |
1198 | otherwise it is the high-order word. | |
1199 | ||
1200 | If we cannot extract the required word, we return zero. Otherwise, an | |
1201 | rtx corresponding to the requested word will be returned. | |
1202 | ||
1203 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1204 | reload has completed, a valid address will always be returned. After | |
1205 | reload, if a valid address cannot be returned, we return zero. | |
1206 | ||
1207 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1208 | it is the responsibility of the caller. | |
1209 | ||
1210 | MODE is the mode of OP in case it is a CONST_INT. */ | |
1211 | ||
1212 | rtx | |
1213 | operand_subword (op, i, validate_address, mode) | |
1214 | rtx op; | |
02e7a332 | 1215 | unsigned int i; |
15bbde2b | 1216 | int validate_address; |
1217 | enum machine_mode mode; | |
1218 | { | |
b572011e | 1219 | HOST_WIDE_INT val; |
1220 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; | |
15bbde2b | 1221 | |
1222 | if (mode == VOIDmode) | |
1223 | mode = GET_MODE (op); | |
1224 | ||
1225 | if (mode == VOIDmode) | |
1226 | abort (); | |
1227 | ||
10c64b6a | 1228 | /* If OP is narrower than a word, fail. */ |
15bbde2b | 1229 | if (mode != BLKmode |
10c64b6a | 1230 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) |
15bbde2b | 1231 | return 0; |
10c64b6a | 1232 | |
1233 | /* If we want a word outside OP, return zero. */ | |
1234 | if (mode != BLKmode | |
1235 | && (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1236 | return const0_rtx; | |
15bbde2b | 1237 | |
1238 | /* If OP is already an integer word, return it. */ | |
1239 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1240 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1241 | return op; | |
1242 | ||
1243 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1244 | if (GET_CODE (op) == REG) | |
1245 | { | |
ab0f6ce8 | 1246 | /* ??? There is a potential problem with this code. It does not |
1247 | properly handle extractions of a subword from a hard register | |
1248 | that is larger than word_mode. Presumably the check for | |
1249 | HARD_REGNO_MODE_OK catches these most of these cases. */ | |
1250 | ||
1251 | /* If OP is a hard register, but OP + I is not a hard register, | |
1252 | then extracting a subword is impossible. | |
1253 | ||
1254 | For example, consider if OP is the last hard register and it is | |
1255 | larger than word_mode. If we wanted word N (for N > 0) because a | |
1256 | part of that hard register was known to contain a useful value, | |
1257 | then OP + I would refer to a pseudo, not the hard register we | |
1258 | actually wanted. */ | |
1259 | if (REGNO (op) < FIRST_PSEUDO_REGISTER | |
1260 | && REGNO (op) + i >= FIRST_PSEUDO_REGISTER) | |
1261 | return 0; | |
1262 | ||
1263 | /* If the register is not valid for MODE, return 0. Note we | |
1264 | have to check both OP and OP + I since they may refer to | |
1265 | different parts of the register file. | |
1266 | ||
1267 | Consider if OP refers to the last 96bit FP register and we want | |
1268 | subword 3 because that subword is known to contain a value we | |
1269 | needed. */ | |
15bbde2b | 1270 | if (REGNO (op) < FIRST_PSEUDO_REGISTER |
ab0f6ce8 | 1271 | && (! HARD_REGNO_MODE_OK (REGNO (op), word_mode) |
1272 | || ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode))) | |
15bbde2b | 1273 | return 0; |
1274 | else if (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1275 | || (REG_FUNCTION_VALUE_P (op) | |
8dc5a78e | 1276 | && rtx_equal_function_value_matters) |
1277 | /* We want to keep the stack, frame, and arg pointers | |
1278 | special. */ | |
c1c63d0b | 1279 | || op == frame_pointer_rtx |
8dc5a78e | 1280 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
c1c63d0b | 1281 | || op == arg_pointer_rtx |
8dc5a78e | 1282 | #endif |
c1c63d0b | 1283 | || op == stack_pointer_rtx) |
3ad7bb1c | 1284 | return gen_rtx_SUBREG (word_mode, op, i); |
15bbde2b | 1285 | else |
3ad7bb1c | 1286 | return gen_rtx_REG (word_mode, REGNO (op) + i); |
15bbde2b | 1287 | } |
1288 | else if (GET_CODE (op) == SUBREG) | |
3ad7bb1c | 1289 | return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), i + SUBREG_WORD (op)); |
76c37538 | 1290 | else if (GET_CODE (op) == CONCAT) |
1291 | { | |
02e7a332 | 1292 | unsigned int partwords |
1293 | = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1294 | ||
76c37538 | 1295 | if (i < partwords) |
1296 | return operand_subword (XEXP (op, 0), i, validate_address, mode); | |
1297 | return operand_subword (XEXP (op, 1), i - partwords, | |
1298 | validate_address, mode); | |
1299 | } | |
15bbde2b | 1300 | |
1301 | /* Form a new MEM at the requested address. */ | |
1302 | if (GET_CODE (op) == MEM) | |
1303 | { | |
1304 | rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD); | |
1305 | rtx new; | |
1306 | ||
1307 | if (validate_address) | |
1308 | { | |
1309 | if (reload_completed) | |
1310 | { | |
1311 | if (! strict_memory_address_p (word_mode, addr)) | |
1312 | return 0; | |
1313 | } | |
1314 | else | |
1315 | addr = memory_address (word_mode, addr); | |
1316 | } | |
1317 | ||
3ad7bb1c | 1318 | new = gen_rtx_MEM (word_mode, addr); |
6a0934dd | 1319 | MEM_COPY_ATTRIBUTES (new, op); |
15bbde2b | 1320 | return new; |
1321 | } | |
1322 | ||
1323 | /* The only remaining cases are when OP is a constant. If the host and | |
1324 | target floating formats are the same, handling two-word floating | |
48509d90 | 1325 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} |
0477aa9f | 1326 | are defined as returning one or two 32 bit values, respectively, |
1327 | and not values of BITS_PER_WORD bits. */ | |
fc92fa61 | 1328 | #ifdef REAL_ARITHMETIC |
915c336f | 1329 | /* The output is some bits, the width of the target machine's word. |
1330 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1331 | host can't. */ | |
0477aa9f | 1332 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
fc92fa61 | 1333 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
48509d90 | 1334 | && GET_MODE_BITSIZE (mode) == 64 |
fc92fa61 | 1335 | && GET_CODE (op) == CONST_DOUBLE) |
1336 | { | |
0477aa9f | 1337 | long k[2]; |
fc92fa61 | 1338 | REAL_VALUE_TYPE rv; |
1339 | ||
1340 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1341 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
48509d90 | 1342 | |
0477aa9f | 1343 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
48509d90 | 1344 | which the words are written depends on the word endianness. |
48509d90 | 1345 | ??? This is a potential portability problem and should |
cd1091f4 | 1346 | be fixed at some point. |
1347 | ||
1348 | We must excercise caution with the sign bit. By definition there | |
1349 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1350 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1351 | So we explicitly mask and sign-extend as necessary. */ | |
0477aa9f | 1352 | if (BITS_PER_WORD == 32) |
cd1091f4 | 1353 | { |
1354 | val = k[i]; | |
1355 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1356 | return GEN_INT (val); | |
1357 | } | |
1358 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
0477aa9f | 1359 | else if (BITS_PER_WORD >= 64 && i == 0) |
cd1091f4 | 1360 | { |
1361 | val = k[! WORDS_BIG_ENDIAN]; | |
1362 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1363 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1364 | return GEN_INT (val); | |
1365 | } | |
0477aa9f | 1366 | #endif |
de8de626 | 1367 | else if (BITS_PER_WORD == 16) |
1368 | { | |
cd1091f4 | 1369 | val = k[i >> 1]; |
1370 | if ((i & 1) == !WORDS_BIG_ENDIAN) | |
1371 | val >>= 16; | |
1372 | val &= 0xffff; | |
1373 | return GEN_INT (val); | |
de8de626 | 1374 | } |
48509d90 | 1375 | else |
1376 | abort (); | |
fc92fa61 | 1377 | } |
61f41e95 | 1378 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1379 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1380 | && GET_MODE_BITSIZE (mode) > 64 | |
1381 | && GET_CODE (op) == CONST_DOUBLE) | |
915c336f | 1382 | { |
1383 | long k[4]; | |
1384 | REAL_VALUE_TYPE rv; | |
61f41e95 | 1385 | |
915c336f | 1386 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1387 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
61f41e95 | 1388 | |
915c336f | 1389 | if (BITS_PER_WORD == 32) |
1390 | { | |
1391 | val = k[i]; | |
1392 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1393 | return GEN_INT (val); | |
1394 | } | |
1395 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1396 | else if (BITS_PER_WORD >= 64 && i <= 1) | |
1397 | { | |
1398 | val = k[i*2 + ! WORDS_BIG_ENDIAN]; | |
1399 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1400 | val |= (HOST_WIDE_INT) k[i*2 + WORDS_BIG_ENDIAN] & 0xffffffff; | |
1401 | return GEN_INT (val); | |
1402 | } | |
1403 | #endif | |
1404 | else | |
1405 | abort (); | |
1406 | } | |
fc92fa61 | 1407 | #else /* no REAL_ARITHMETIC */ |
15bbde2b | 1408 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 1409 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
15bbde2b | 1410 | || flag_pretend_float) |
1411 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1412 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1413 | && GET_CODE (op) == CONST_DOUBLE) | |
35bb04fc | 1414 | { |
1415 | /* The constant is stored in the host's word-ordering, | |
1416 | but we want to access it in the target's word-ordering. Some | |
1417 | compilers don't like a conditional inside macro args, so we have two | |
1418 | copies of the return. */ | |
06683233 | 1419 | #ifdef HOST_WORDS_BIG_ENDIAN |
35bb04fc | 1420 | return GEN_INT (i == WORDS_BIG_ENDIAN |
1421 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
06683233 | 1422 | #else |
35bb04fc | 1423 | return GEN_INT (i != WORDS_BIG_ENDIAN |
1424 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
06683233 | 1425 | #endif |
35bb04fc | 1426 | } |
fc92fa61 | 1427 | #endif /* no REAL_ARITHMETIC */ |
15bbde2b | 1428 | |
1429 | /* Single word float is a little harder, since single- and double-word | |
1430 | values often do not have the same high-order bits. We have already | |
1431 | verified that we want the only defined word of the single-word value. */ | |
fc92fa61 | 1432 | #ifdef REAL_ARITHMETIC |
0477aa9f | 1433 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
48509d90 | 1434 | && GET_MODE_BITSIZE (mode) == 32 |
fc92fa61 | 1435 | && GET_CODE (op) == CONST_DOUBLE) |
1436 | { | |
0477aa9f | 1437 | long l; |
fc92fa61 | 1438 | REAL_VALUE_TYPE rv; |
1439 | ||
1440 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1441 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
587a9fdf | 1442 | |
cd1091f4 | 1443 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1444 | val = l; | |
1445 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
eb294a2f | 1446 | |
587a9fdf | 1447 | if (BITS_PER_WORD == 16) |
1448 | { | |
cd1091f4 | 1449 | if ((i & 1) == !WORDS_BIG_ENDIAN) |
1450 | val >>= 16; | |
1451 | val &= 0xffff; | |
587a9fdf | 1452 | } |
cd1091f4 | 1453 | |
1454 | return GEN_INT (val); | |
fc92fa61 | 1455 | } |
1456 | #else | |
15bbde2b | 1457 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
b572011e | 1458 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
15bbde2b | 1459 | || flag_pretend_float) |
dc611f66 | 1460 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
15bbde2b | 1461 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1462 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1463 | && GET_CODE (op) == CONST_DOUBLE) | |
1464 | { | |
1465 | double d; | |
b572011e | 1466 | union {float f; HOST_WIDE_INT i; } u; |
15bbde2b | 1467 | |
1468 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1469 | ||
1470 | u.f = d; | |
b572011e | 1471 | return GEN_INT (u.i); |
15bbde2b | 1472 | } |
dc611f66 | 1473 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1474 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1475 | || flag_pretend_float) | |
1476 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1477 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1478 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1479 | && GET_CODE (op) == CONST_DOUBLE) | |
1480 | { | |
1481 | double d; | |
1482 | union {double d; HOST_WIDE_INT i; } u; | |
1483 | ||
1484 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1485 | ||
1486 | u.d = d; | |
1487 | return GEN_INT (u.i); | |
1488 | } | |
fc92fa61 | 1489 | #endif /* no REAL_ARITHMETIC */ |
15bbde2b | 1490 | |
1491 | /* The only remaining cases that we can handle are integers. | |
1492 | Convert to proper endianness now since these cases need it. | |
1493 | At this point, i == 0 means the low-order word. | |
1494 | ||
870288ea | 1495 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1496 | in general. However, if OP is (const_int 0), we can just return | |
1497 | it for any word. */ | |
1498 | ||
1499 | if (op == const0_rtx) | |
1500 | return op; | |
15bbde2b | 1501 | |
1502 | if (GET_MODE_CLASS (mode) != MODE_INT | |
870288ea | 1503 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
5c1fd70d | 1504 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
15bbde2b | 1505 | return 0; |
1506 | ||
1507 | if (WORDS_BIG_ENDIAN) | |
1508 | i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i; | |
1509 | ||
1510 | /* Find out which word on the host machine this value is in and get | |
1511 | it from the constant. */ | |
1512 | val = (i / size_ratio == 0 | |
1513 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) | |
1514 | : (GET_CODE (op) == CONST_INT | |
1515 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1516 | ||
5418f2a8 | 1517 | /* Get the value we want into the low bits of val. */ |
b572011e | 1518 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
5418f2a8 | 1519 | val = ((val >> ((i % size_ratio) * BITS_PER_WORD))); |
1520 | ||
b2345915 | 1521 | val = trunc_int_for_mode (val, word_mode); |
15bbde2b | 1522 | |
b572011e | 1523 | return GEN_INT (val); |
15bbde2b | 1524 | } |
1525 | ||
1526 | /* Similar to `operand_subword', but never return 0. If we can't extract | |
1527 | the required subword, put OP into a register and try again. If that fails, | |
1528 | abort. We always validate the address in this case. It is not valid | |
1529 | to call this function after reload; it is mostly meant for RTL | |
1530 | generation. | |
1531 | ||
1532 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1533 | ||
1534 | rtx | |
1535 | operand_subword_force (op, i, mode) | |
1536 | rtx op; | |
02e7a332 | 1537 | unsigned int i; |
15bbde2b | 1538 | enum machine_mode mode; |
1539 | { | |
1540 | rtx result = operand_subword (op, i, 1, mode); | |
1541 | ||
1542 | if (result) | |
1543 | return result; | |
1544 | ||
1545 | if (mode != BLKmode && mode != VOIDmode) | |
ac825d29 | 1546 | { |
1547 | /* If this is a register which can not be accessed by words, copy it | |
1548 | to a pseudo register. */ | |
1549 | if (GET_CODE (op) == REG) | |
1550 | op = copy_to_reg (op); | |
1551 | else | |
1552 | op = force_reg (mode, op); | |
1553 | } | |
15bbde2b | 1554 | |
1555 | result = operand_subword (op, i, 1, mode); | |
1556 | if (result == 0) | |
1557 | abort (); | |
1558 | ||
1559 | return result; | |
1560 | } | |
1561 | \f | |
1562 | /* Given a compare instruction, swap the operands. | |
1563 | A test instruction is changed into a compare of 0 against the operand. */ | |
1564 | ||
1565 | void | |
1566 | reverse_comparison (insn) | |
1567 | rtx insn; | |
1568 | { | |
1569 | rtx body = PATTERN (insn); | |
1570 | rtx comp; | |
1571 | ||
1572 | if (GET_CODE (body) == SET) | |
1573 | comp = SET_SRC (body); | |
1574 | else | |
1575 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1576 | ||
1577 | if (GET_CODE (comp) == COMPARE) | |
1578 | { | |
1579 | rtx op0 = XEXP (comp, 0); | |
1580 | rtx op1 = XEXP (comp, 1); | |
1581 | XEXP (comp, 0) = op1; | |
1582 | XEXP (comp, 1) = op0; | |
1583 | } | |
1584 | else | |
1585 | { | |
7014838c | 1586 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1587 | CONST0_RTX (GET_MODE (comp)), comp); | |
15bbde2b | 1588 | if (GET_CODE (body) == SET) |
1589 | SET_SRC (body) = new; | |
1590 | else | |
1591 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1592 | } | |
1593 | } | |
1594 | \f | |
1595 | /* Return a memory reference like MEMREF, but with its mode changed | |
1596 | to MODE and its address changed to ADDR. | |
1597 | (VOIDmode means don't change the mode. | |
1598 | NULL for ADDR means don't change the address.) */ | |
1599 | ||
1600 | rtx | |
1601 | change_address (memref, mode, addr) | |
1602 | rtx memref; | |
1603 | enum machine_mode mode; | |
1604 | rtx addr; | |
1605 | { | |
1606 | rtx new; | |
1607 | ||
1608 | if (GET_CODE (memref) != MEM) | |
1609 | abort (); | |
1610 | if (mode == VOIDmode) | |
1611 | mode = GET_MODE (memref); | |
1612 | if (addr == 0) | |
1613 | addr = XEXP (memref, 0); | |
1614 | ||
1615 | /* If reload is in progress or has completed, ADDR must be valid. | |
1616 | Otherwise, we can call memory_address to make it valid. */ | |
1617 | if (reload_completed || reload_in_progress) | |
1618 | { | |
1619 | if (! memory_address_p (mode, addr)) | |
1620 | abort (); | |
1621 | } | |
1622 | else | |
1623 | addr = memory_address (mode, addr); | |
1624 | ||
e8976cd7 | 1625 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1626 | return memref; | |
1627 | ||
3ad7bb1c | 1628 | new = gen_rtx_MEM (mode, addr); |
6a0934dd | 1629 | MEM_COPY_ATTRIBUTES (new, memref); |
15bbde2b | 1630 | return new; |
1631 | } | |
1632 | \f | |
1633 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1634 | ||
1635 | rtx | |
1636 | gen_label_rtx () | |
1637 | { | |
649d8da6 | 1638 | register rtx label; |
1639 | ||
b54842d8 | 1640 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
bfee5366 | 1641 | NULL_RTX, label_num++, NULL_PTR, NULL_PTR); |
649d8da6 | 1642 | |
15bbde2b | 1643 | LABEL_NUSES (label) = 0; |
bfee5366 | 1644 | LABEL_ALTERNATE_NAME (label) = NULL; |
15bbde2b | 1645 | return label; |
1646 | } | |
1647 | \f | |
1648 | /* For procedure integration. */ | |
1649 | ||
15bbde2b | 1650 | /* Install new pointers to the first and last insns in the chain. |
d4c332ff | 1651 | Also, set cur_insn_uid to one higher than the last in use. |
15bbde2b | 1652 | Used for an inline-procedure after copying the insn chain. */ |
1653 | ||
1654 | void | |
1655 | set_new_first_and_last_insn (first, last) | |
1656 | rtx first, last; | |
1657 | { | |
d4c332ff | 1658 | rtx insn; |
1659 | ||
15bbde2b | 1660 | first_insn = first; |
1661 | last_insn = last; | |
d4c332ff | 1662 | cur_insn_uid = 0; |
1663 | ||
1664 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1665 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1666 | ||
1667 | cur_insn_uid++; | |
15bbde2b | 1668 | } |
1669 | ||
1670 | /* Set the range of label numbers found in the current function. | |
1671 | This is used when belatedly compiling an inline function. */ | |
1672 | ||
1673 | void | |
1674 | set_new_first_and_last_label_num (first, last) | |
1675 | int first, last; | |
1676 | { | |
1677 | base_label_num = label_num; | |
1678 | first_label_num = first; | |
1679 | last_label_num = last; | |
1680 | } | |
0a893c29 | 1681 | |
1682 | /* Set the last label number found in the current function. | |
1683 | This is used when belatedly compiling an inline function. */ | |
15bbde2b | 1684 | |
1685 | void | |
0a893c29 | 1686 | set_new_last_label_num (last) |
1687 | int last; | |
15bbde2b | 1688 | { |
0a893c29 | 1689 | base_label_num = label_num; |
1690 | last_label_num = last; | |
15bbde2b | 1691 | } |
0a893c29 | 1692 | \f |
15bbde2b | 1693 | /* Restore all variables describing the current status from the structure *P. |
1694 | This is used after a nested function. */ | |
1695 | ||
1696 | void | |
1697 | restore_emit_status (p) | |
c5b89159 | 1698 | struct function *p ATTRIBUTE_UNUSED; |
15bbde2b | 1699 | { |
bb9d6298 | 1700 | last_label_num = 0; |
0a893c29 | 1701 | clear_emit_caches (); |
15bbde2b | 1702 | } |
26df1c5e | 1703 | |
c788feb1 | 1704 | /* Clear out all parts of the state in F that can safely be discarded |
26df1c5e | 1705 | after the function has been compiled, to let garbage collection |
a57bcb3b | 1706 | reclaim the memory. */ |
c788feb1 | 1707 | |
26df1c5e | 1708 | void |
a57bcb3b | 1709 | free_emit_status (f) |
26df1c5e | 1710 | struct function *f; |
1711 | { | |
1712 | free (f->emit->x_regno_reg_rtx); | |
1713 | free (f->emit->regno_pointer_flag); | |
1714 | free (f->emit->regno_pointer_align); | |
3c3bb268 | 1715 | free (f->emit); |
1716 | f->emit = NULL; | |
26df1c5e | 1717 | } |
15bbde2b | 1718 | \f |
2d96a59a | 1719 | /* Go through all the RTL insn bodies and copy any invalid shared |
1720 | structure. This routine should only be called once. */ | |
15bbde2b | 1721 | |
1722 | void | |
2d96a59a | 1723 | unshare_all_rtl (fndecl, insn) |
1724 | tree fndecl; | |
1725 | rtx insn; | |
15bbde2b | 1726 | { |
2d96a59a | 1727 | tree decl; |
15bbde2b | 1728 | |
2d96a59a | 1729 | /* Make sure that virtual parameters are not shared. */ |
1730 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
45733446 | 1731 | DECL_RTL (decl) = copy_rtx_if_shared (DECL_RTL (decl)); |
2d96a59a | 1732 | |
72ec8878 | 1733 | /* Make sure that virtual stack slots are not shared. */ |
1734 | unshare_all_decls (DECL_INITIAL (fndecl)); | |
1735 | ||
2d96a59a | 1736 | /* Unshare just about everything else. */ |
1737 | unshare_all_rtl_1 (insn); | |
1738 | ||
15bbde2b | 1739 | /* Make sure the addresses of stack slots found outside the insn chain |
1740 | (such as, in DECL_RTL of a variable) are not shared | |
1741 | with the insn chain. | |
1742 | ||
1743 | This special care is necessary when the stack slot MEM does not | |
1744 | actually appear in the insn chain. If it does appear, its address | |
1745 | is unshared from all else at that point. */ | |
45733446 | 1746 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
15bbde2b | 1747 | } |
1748 | ||
2d96a59a | 1749 | /* Go through all the RTL insn bodies and copy any invalid shared |
1750 | structure, again. This is a fairly expensive thing to do so it | |
1751 | should be done sparingly. */ | |
1752 | ||
1753 | void | |
1754 | unshare_all_rtl_again (insn) | |
1755 | rtx insn; | |
1756 | { | |
1757 | rtx p; | |
5244079b | 1758 | tree decl; |
1759 | ||
2d96a59a | 1760 | for (p = insn; p; p = NEXT_INSN (p)) |
9204e736 | 1761 | if (INSN_P (p)) |
2d96a59a | 1762 | { |
1763 | reset_used_flags (PATTERN (p)); | |
1764 | reset_used_flags (REG_NOTES (p)); | |
1765 | reset_used_flags (LOG_LINKS (p)); | |
1766 | } | |
5244079b | 1767 | |
01dc9f0c | 1768 | /* Make sure that virtual stack slots are not shared. */ |
1769 | reset_used_decls (DECL_INITIAL (cfun->decl)); | |
1770 | ||
5244079b | 1771 | /* Make sure that virtual parameters are not shared. */ |
1772 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
1773 | reset_used_flags (DECL_RTL (decl)); | |
1774 | ||
1775 | reset_used_flags (stack_slot_list); | |
1776 | ||
1777 | unshare_all_rtl (cfun->decl, insn); | |
2d96a59a | 1778 | } |
1779 | ||
1780 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1781 | Assumes the mark bits are cleared at entry. */ | |
1782 | ||
1783 | static void | |
1784 | unshare_all_rtl_1 (insn) | |
1785 | rtx insn; | |
1786 | { | |
1787 | for (; insn; insn = NEXT_INSN (insn)) | |
9204e736 | 1788 | if (INSN_P (insn)) |
2d96a59a | 1789 | { |
1790 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1791 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1792 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1793 | } | |
1794 | } | |
1795 | ||
72ec8878 | 1796 | /* Go through all virtual stack slots of a function and copy any |
1797 | shared structure. */ | |
1798 | static void | |
1799 | unshare_all_decls (blk) | |
1800 | tree blk; | |
1801 | { | |
1802 | tree t; | |
1803 | ||
1804 | /* Copy shared decls. */ | |
1805 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
01dc9f0c | 1806 | DECL_RTL (t) = copy_rtx_if_shared (DECL_RTL (t)); |
72ec8878 | 1807 | |
1808 | /* Now process sub-blocks. */ | |
1809 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1810 | unshare_all_decls (t); | |
1811 | } | |
1812 | ||
01dc9f0c | 1813 | /* Go through all virtual stack slots of a function and mark them as |
1814 | not shared. */ | |
1815 | static void | |
1816 | reset_used_decls (blk) | |
1817 | tree blk; | |
1818 | { | |
1819 | tree t; | |
1820 | ||
1821 | /* Mark decls. */ | |
1822 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
1823 | reset_used_flags (DECL_RTL (t)); | |
1824 | ||
1825 | /* Now process sub-blocks. */ | |
1826 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1827 | reset_used_decls (t); | |
1828 | } | |
1829 | ||
15bbde2b | 1830 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1831 | Recursively does the same for subexpressions. */ | |
1832 | ||
1833 | rtx | |
1834 | copy_rtx_if_shared (orig) | |
1835 | rtx orig; | |
1836 | { | |
1837 | register rtx x = orig; | |
1838 | register int i; | |
1839 | register enum rtx_code code; | |
d2ca078f | 1840 | register const char *format_ptr; |
15bbde2b | 1841 | int copied = 0; |
1842 | ||
1843 | if (x == 0) | |
1844 | return 0; | |
1845 | ||
1846 | code = GET_CODE (x); | |
1847 | ||
1848 | /* These types may be freely shared. */ | |
1849 | ||
1850 | switch (code) | |
1851 | { | |
1852 | case REG: | |
1853 | case QUEUED: | |
1854 | case CONST_INT: | |
1855 | case CONST_DOUBLE: | |
1856 | case SYMBOL_REF: | |
1857 | case CODE_LABEL: | |
1858 | case PC: | |
1859 | case CC0: | |
1860 | case SCRATCH: | |
a92771b8 | 1861 | /* SCRATCH must be shared because they represent distinct values. */ |
15bbde2b | 1862 | return x; |
1863 | ||
f63d12e3 | 1864 | case CONST: |
1865 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
1866 | a LABEL_REF, it isn't sharable. */ | |
1867 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1868 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1869 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1870 | return x; | |
1871 | break; | |
1872 | ||
15bbde2b | 1873 | case INSN: |
1874 | case JUMP_INSN: | |
1875 | case CALL_INSN: | |
1876 | case NOTE: | |
15bbde2b | 1877 | case BARRIER: |
1878 | /* The chain of insns is not being copied. */ | |
1879 | return x; | |
1880 | ||
1881 | case MEM: | |
baf55c37 | 1882 | /* A MEM is allowed to be shared if its address is constant. |
1883 | ||
1884 | We used to allow sharing of MEMs which referenced | |
1885 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but | |
1886 | that can lose. instantiate_virtual_regs will not unshare | |
1887 | the MEMs, and combine may change the structure of the address | |
1888 | because it looks safe and profitable in one context, but | |
1889 | in some other context it creates unrecognizable RTL. */ | |
1890 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
15bbde2b | 1891 | return x; |
1892 | ||
0dbd1c74 | 1893 | break; |
1894 | ||
1895 | default: | |
1896 | break; | |
15bbde2b | 1897 | } |
1898 | ||
1899 | /* This rtx may not be shared. If it has already been seen, | |
1900 | replace it with a copy of itself. */ | |
1901 | ||
1902 | if (x->used) | |
1903 | { | |
1904 | register rtx copy; | |
1905 | ||
1906 | copy = rtx_alloc (code); | |
748e6d74 | 1907 | bcopy ((char *) x, (char *) copy, |
1908 | (sizeof (*copy) - sizeof (copy->fld) | |
1909 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
15bbde2b | 1910 | x = copy; |
1911 | copied = 1; | |
1912 | } | |
1913 | x->used = 1; | |
1914 | ||
1915 | /* Now scan the subexpressions recursively. | |
1916 | We can store any replaced subexpressions directly into X | |
1917 | since we know X is not shared! Any vectors in X | |
1918 | must be copied if X was copied. */ | |
1919 | ||
1920 | format_ptr = GET_RTX_FORMAT (code); | |
1921 | ||
1922 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1923 | { | |
1924 | switch (*format_ptr++) | |
1925 | { | |
1926 | case 'e': | |
1927 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
1928 | break; | |
1929 | ||
1930 | case 'E': | |
1931 | if (XVEC (x, i) != NULL) | |
1932 | { | |
1933 | register int j; | |
ffe0869b | 1934 | int len = XVECLEN (x, i); |
15bbde2b | 1935 | |
ffe0869b | 1936 | if (copied && len > 0) |
a4070a91 | 1937 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
ffe0869b | 1938 | for (j = 0; j < len; j++) |
1939 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
15bbde2b | 1940 | } |
1941 | break; | |
1942 | } | |
1943 | } | |
1944 | return x; | |
1945 | } | |
1946 | ||
1947 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
1948 | to look for shared sub-parts. */ | |
1949 | ||
1950 | void | |
1951 | reset_used_flags (x) | |
1952 | rtx x; | |
1953 | { | |
1954 | register int i, j; | |
1955 | register enum rtx_code code; | |
d2ca078f | 1956 | register const char *format_ptr; |
15bbde2b | 1957 | |
1958 | if (x == 0) | |
1959 | return; | |
1960 | ||
1961 | code = GET_CODE (x); | |
1962 | ||
c3418f42 | 1963 | /* These types may be freely shared so we needn't do any resetting |
15bbde2b | 1964 | for them. */ |
1965 | ||
1966 | switch (code) | |
1967 | { | |
1968 | case REG: | |
1969 | case QUEUED: | |
1970 | case CONST_INT: | |
1971 | case CONST_DOUBLE: | |
1972 | case SYMBOL_REF: | |
1973 | case CODE_LABEL: | |
1974 | case PC: | |
1975 | case CC0: | |
1976 | return; | |
1977 | ||
1978 | case INSN: | |
1979 | case JUMP_INSN: | |
1980 | case CALL_INSN: | |
1981 | case NOTE: | |
1982 | case LABEL_REF: | |
1983 | case BARRIER: | |
1984 | /* The chain of insns is not being copied. */ | |
1985 | return; | |
0dbd1c74 | 1986 | |
1987 | default: | |
1988 | break; | |
15bbde2b | 1989 | } |
1990 | ||
1991 | x->used = 0; | |
1992 | ||
1993 | format_ptr = GET_RTX_FORMAT (code); | |
1994 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1995 | { | |
1996 | switch (*format_ptr++) | |
1997 | { | |
1998 | case 'e': | |
1999 | reset_used_flags (XEXP (x, i)); | |
2000 | break; | |
2001 | ||
2002 | case 'E': | |
2003 | for (j = 0; j < XVECLEN (x, i); j++) | |
2004 | reset_used_flags (XVECEXP (x, i, j)); | |
2005 | break; | |
2006 | } | |
2007 | } | |
2008 | } | |
2009 | \f | |
2010 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2011 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2012 | OTHER must be valid as a SET_DEST. */ | |
2013 | ||
2014 | rtx | |
2015 | make_safe_from (x, other) | |
2016 | rtx x, other; | |
2017 | { | |
2018 | while (1) | |
2019 | switch (GET_CODE (other)) | |
2020 | { | |
2021 | case SUBREG: | |
2022 | other = SUBREG_REG (other); | |
2023 | break; | |
2024 | case STRICT_LOW_PART: | |
2025 | case SIGN_EXTEND: | |
2026 | case ZERO_EXTEND: | |
2027 | other = XEXP (other, 0); | |
2028 | break; | |
2029 | default: | |
2030 | goto done; | |
2031 | } | |
2032 | done: | |
2033 | if ((GET_CODE (other) == MEM | |
2034 | && ! CONSTANT_P (x) | |
2035 | && GET_CODE (x) != REG | |
2036 | && GET_CODE (x) != SUBREG) | |
2037 | || (GET_CODE (other) == REG | |
2038 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
2039 | || reg_mentioned_p (other, x)))) | |
2040 | { | |
2041 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2042 | emit_move_insn (temp, x); | |
2043 | return temp; | |
2044 | } | |
2045 | return x; | |
2046 | } | |
2047 | \f | |
2048 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2049 | ||
2050 | /* Return the first insn of the current sequence or current function. */ | |
2051 | ||
2052 | rtx | |
2053 | get_insns () | |
2054 | { | |
2055 | return first_insn; | |
2056 | } | |
2057 | ||
2058 | /* Return the last insn emitted in current sequence or current function. */ | |
2059 | ||
2060 | rtx | |
2061 | get_last_insn () | |
2062 | { | |
2063 | return last_insn; | |
2064 | } | |
2065 | ||
2066 | /* Specify a new insn as the last in the chain. */ | |
2067 | ||
2068 | void | |
2069 | set_last_insn (insn) | |
2070 | rtx insn; | |
2071 | { | |
2072 | if (NEXT_INSN (insn) != 0) | |
2073 | abort (); | |
2074 | last_insn = insn; | |
2075 | } | |
2076 | ||
2077 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2078 | ||
2079 | rtx | |
2080 | get_last_insn_anywhere () | |
2081 | { | |
2082 | struct sequence_stack *stack; | |
2083 | if (last_insn) | |
2084 | return last_insn; | |
0a893c29 | 2085 | for (stack = seq_stack; stack; stack = stack->next) |
15bbde2b | 2086 | if (stack->last != 0) |
2087 | return stack->last; | |
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | /* Return a number larger than any instruction's uid in this function. */ | |
2092 | ||
2093 | int | |
2094 | get_max_uid () | |
2095 | { | |
2096 | return cur_insn_uid; | |
2097 | } | |
90b89d2c | 2098 | |
214d02d0 | 2099 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2100 | ||
90b89d2c | 2101 | void |
214d02d0 | 2102 | renumber_insns (stream) |
2103 | FILE *stream; | |
90b89d2c | 2104 | { |
2105 | rtx insn; | |
90b89d2c | 2106 | |
214d02d0 | 2107 | /* If we're not supposed to renumber instructions, don't. */ |
2108 | if (!flag_renumber_insns) | |
2109 | return; | |
2110 | ||
90b89d2c | 2111 | /* If there aren't that many instructions, then it's not really |
2112 | worth renumbering them. */ | |
214d02d0 | 2113 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
90b89d2c | 2114 | return; |
2115 | ||
2116 | cur_insn_uid = 1; | |
2117 | ||
2118 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
214d02d0 | 2119 | { |
2120 | if (stream) | |
2121 | fprintf (stream, "Renumbering insn %d to %d\n", | |
2122 | INSN_UID (insn), cur_insn_uid); | |
2123 | INSN_UID (insn) = cur_insn_uid++; | |
2124 | } | |
90b89d2c | 2125 | } |
15bbde2b | 2126 | \f |
2127 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2128 | of the sequence. */ | |
2129 | ||
2130 | rtx | |
2131 | next_insn (insn) | |
2132 | rtx insn; | |
2133 | { | |
2134 | if (insn) | |
2135 | { | |
2136 | insn = NEXT_INSN (insn); | |
2137 | if (insn && GET_CODE (insn) == INSN | |
2138 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2139 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2140 | } | |
2141 | ||
2142 | return insn; | |
2143 | } | |
2144 | ||
2145 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2146 | of the sequence. */ | |
2147 | ||
2148 | rtx | |
2149 | previous_insn (insn) | |
2150 | rtx insn; | |
2151 | { | |
2152 | if (insn) | |
2153 | { | |
2154 | insn = PREV_INSN (insn); | |
2155 | if (insn && GET_CODE (insn) == INSN | |
2156 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2157 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2158 | } | |
2159 | ||
2160 | return insn; | |
2161 | } | |
2162 | ||
2163 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2164 | look inside SEQUENCEs. */ | |
2165 | ||
2166 | rtx | |
2167 | next_nonnote_insn (insn) | |
2168 | rtx insn; | |
2169 | { | |
2170 | while (insn) | |
2171 | { | |
2172 | insn = NEXT_INSN (insn); | |
2173 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2174 | break; | |
2175 | } | |
2176 | ||
2177 | return insn; | |
2178 | } | |
2179 | ||
2180 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2181 | not look inside SEQUENCEs. */ | |
2182 | ||
2183 | rtx | |
2184 | prev_nonnote_insn (insn) | |
2185 | rtx insn; | |
2186 | { | |
2187 | while (insn) | |
2188 | { | |
2189 | insn = PREV_INSN (insn); | |
2190 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2191 | break; | |
2192 | } | |
2193 | ||
2194 | return insn; | |
2195 | } | |
2196 | ||
2197 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2198 | or 0, if there is none. This routine does not look inside | |
a92771b8 | 2199 | SEQUENCEs. */ |
15bbde2b | 2200 | |
2201 | rtx | |
2202 | next_real_insn (insn) | |
2203 | rtx insn; | |
2204 | { | |
2205 | while (insn) | |
2206 | { | |
2207 | insn = NEXT_INSN (insn); | |
2208 | if (insn == 0 || GET_CODE (insn) == INSN | |
2209 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2210 | break; | |
2211 | } | |
2212 | ||
2213 | return insn; | |
2214 | } | |
2215 | ||
2216 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2217 | or 0, if there is none. This routine does not look inside | |
2218 | SEQUENCEs. */ | |
2219 | ||
2220 | rtx | |
2221 | prev_real_insn (insn) | |
2222 | rtx insn; | |
2223 | { | |
2224 | while (insn) | |
2225 | { | |
2226 | insn = PREV_INSN (insn); | |
2227 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2228 | || GET_CODE (insn) == JUMP_INSN) | |
2229 | break; | |
2230 | } | |
2231 | ||
2232 | return insn; | |
2233 | } | |
2234 | ||
2235 | /* Find the next insn after INSN that really does something. This routine | |
2236 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2237 | same as next_real_insn. */ | |
2238 | ||
2215ca0d | 2239 | int |
2240 | active_insn_p (insn) | |
2241 | rtx insn; | |
2242 | { | |
2243 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2244 | || (GET_CODE (insn) == INSN | |
2245 | && (! reload_completed | |
2246 | || (GET_CODE (PATTERN (insn)) != USE | |
2247 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2248 | } | |
2249 | ||
15bbde2b | 2250 | rtx |
2251 | next_active_insn (insn) | |
2252 | rtx insn; | |
2253 | { | |
2254 | while (insn) | |
2255 | { | |
2256 | insn = NEXT_INSN (insn); | |
2215ca0d | 2257 | if (insn == 0 || active_insn_p (insn)) |
15bbde2b | 2258 | break; |
2259 | } | |
2260 | ||
2261 | return insn; | |
2262 | } | |
2263 | ||
2264 | /* Find the last insn before INSN that really does something. This routine | |
2265 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2266 | same as prev_real_insn. */ | |
2267 | ||
2268 | rtx | |
2269 | prev_active_insn (insn) | |
2270 | rtx insn; | |
2271 | { | |
2272 | while (insn) | |
2273 | { | |
2274 | insn = PREV_INSN (insn); | |
2215ca0d | 2275 | if (insn == 0 || active_insn_p (insn)) |
15bbde2b | 2276 | break; |
2277 | } | |
2278 | ||
2279 | return insn; | |
2280 | } | |
2281 | ||
2282 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2283 | ||
2284 | rtx | |
2285 | next_label (insn) | |
2286 | rtx insn; | |
2287 | { | |
2288 | while (insn) | |
2289 | { | |
2290 | insn = NEXT_INSN (insn); | |
2291 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2292 | break; | |
2293 | } | |
2294 | ||
2295 | return insn; | |
2296 | } | |
2297 | ||
2298 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2299 | ||
2300 | rtx | |
2301 | prev_label (insn) | |
2302 | rtx insn; | |
2303 | { | |
2304 | while (insn) | |
2305 | { | |
2306 | insn = PREV_INSN (insn); | |
2307 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2308 | break; | |
2309 | } | |
2310 | ||
2311 | return insn; | |
2312 | } | |
2313 | \f | |
2314 | #ifdef HAVE_cc0 | |
b15e0bba | 2315 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2316 | and REG_CC_USER notes so we can find it. */ | |
2317 | ||
2318 | void | |
2319 | link_cc0_insns (insn) | |
2320 | rtx insn; | |
2321 | { | |
2322 | rtx user = next_nonnote_insn (insn); | |
2323 | ||
2324 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2325 | user = XVECEXP (PATTERN (user), 0, 0); | |
2326 | ||
7014838c | 2327 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2328 | REG_NOTES (user)); | |
3ad7bb1c | 2329 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
b15e0bba | 2330 | } |
2331 | ||
15bbde2b | 2332 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2333 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2334 | applied to the result of this function should yield INSN). | |
2335 | ||
2336 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2337 | is present, it contains the insn that uses CC0. | |
2338 | ||
2339 | Return 0 if we can't find the insn. */ | |
2340 | ||
2341 | rtx | |
2342 | next_cc0_user (insn) | |
2343 | rtx insn; | |
2344 | { | |
b572011e | 2345 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
15bbde2b | 2346 | |
2347 | if (note) | |
2348 | return XEXP (note, 0); | |
2349 | ||
2350 | insn = next_nonnote_insn (insn); | |
2351 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2352 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2353 | ||
9204e736 | 2354 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
15bbde2b | 2355 | return insn; |
2356 | ||
2357 | return 0; | |
2358 | } | |
2359 | ||
2360 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2361 | note, it is the previous insn. */ | |
2362 | ||
2363 | rtx | |
2364 | prev_cc0_setter (insn) | |
2365 | rtx insn; | |
2366 | { | |
b572011e | 2367 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
15bbde2b | 2368 | |
2369 | if (note) | |
2370 | return XEXP (note, 0); | |
2371 | ||
2372 | insn = prev_nonnote_insn (insn); | |
2373 | if (! sets_cc0_p (PATTERN (insn))) | |
2374 | abort (); | |
2375 | ||
2376 | return insn; | |
2377 | } | |
2378 | #endif | |
2379 | \f | |
2380 | /* Try splitting insns that can be split for better scheduling. | |
2381 | PAT is the pattern which might split. | |
2382 | TRIAL is the insn providing PAT. | |
0e69a50a | 2383 | LAST is non-zero if we should return the last insn of the sequence produced. |
15bbde2b | 2384 | |
2385 | If this routine succeeds in splitting, it returns the first or last | |
0e69a50a | 2386 | replacement insn depending on the value of LAST. Otherwise, it |
15bbde2b | 2387 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2388 | ||
2389 | rtx | |
0e69a50a | 2390 | try_split (pat, trial, last) |
15bbde2b | 2391 | rtx pat, trial; |
0e69a50a | 2392 | int last; |
15bbde2b | 2393 | { |
2394 | rtx before = PREV_INSN (trial); | |
2395 | rtx after = NEXT_INSN (trial); | |
2396 | rtx seq = split_insns (pat, trial); | |
2397 | int has_barrier = 0; | |
2398 | rtx tem; | |
2399 | ||
2400 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2401 | We may need to handle this specially. */ | |
2402 | if (after && GET_CODE (after) == BARRIER) | |
2403 | { | |
2404 | has_barrier = 1; | |
2405 | after = NEXT_INSN (after); | |
2406 | } | |
2407 | ||
2408 | if (seq) | |
2409 | { | |
2410 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2411 | The latter case will normally arise only when being done so that | |
2412 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2413 | if (GET_CODE (seq) == SEQUENCE) | |
2414 | { | |
5262c253 | 2415 | int i; |
2416 | ||
2417 | /* Avoid infinite loop if any insn of the result matches | |
2418 | the original pattern. */ | |
2419 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2420 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN | |
2421 | && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat)) | |
2422 | return trial; | |
2423 | ||
15bbde2b | 2424 | /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in |
2425 | SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero, | |
2426 | increment the usage count so we don't delete the label. */ | |
15bbde2b | 2427 | |
2428 | if (GET_CODE (trial) == JUMP_INSN) | |
2429 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2430 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2431 | { | |
2432 | JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial); | |
2433 | ||
2434 | if (JUMP_LABEL (trial)) | |
2435 | LABEL_NUSES (JUMP_LABEL (trial))++; | |
2436 | } | |
2437 | ||
2438 | tem = emit_insn_after (seq, before); | |
2439 | ||
2440 | delete_insn (trial); | |
2441 | if (has_barrier) | |
2442 | emit_barrier_after (tem); | |
0e69a50a | 2443 | |
2444 | /* Recursively call try_split for each new insn created; by the | |
2445 | time control returns here that insn will be fully split, so | |
2446 | set LAST and continue from the insn after the one returned. | |
06343e77 | 2447 | We can't use next_active_insn here since AFTER may be a note. |
ab6683d6 | 2448 | Ignore deleted insns, which can be occur if not optimizing. */ |
9204e736 | 2449 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) |
2450 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
06343e77 | 2451 | tem = try_split (PATTERN (tem), tem, 1); |
15bbde2b | 2452 | } |
2453 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2454 | else if (rtx_equal_p (seq, pat)) | |
2455 | return trial; | |
2456 | else | |
2457 | { | |
2458 | PATTERN (trial) = seq; | |
2459 | INSN_CODE (trial) = -1; | |
0e69a50a | 2460 | try_split (seq, trial, last); |
15bbde2b | 2461 | } |
2462 | ||
0e69a50a | 2463 | /* Return either the first or the last insn, depending on which was |
2464 | requested. */ | |
068a89d7 | 2465 | return last |
2466 | ? (after ? prev_active_insn (after) : last_insn) | |
2467 | : next_active_insn (before); | |
15bbde2b | 2468 | } |
2469 | ||
2470 | return trial; | |
2471 | } | |
2472 | \f | |
2473 | /* Make and return an INSN rtx, initializing all its slots. | |
6a84e367 | 2474 | Store PATTERN in the pattern slots. */ |
15bbde2b | 2475 | |
2476 | rtx | |
6a84e367 | 2477 | make_insn_raw (pattern) |
15bbde2b | 2478 | rtx pattern; |
15bbde2b | 2479 | { |
2480 | register rtx insn; | |
2481 | ||
d7c47c0e | 2482 | insn = rtx_alloc (INSN); |
15bbde2b | 2483 | |
575333f9 | 2484 | INSN_UID (insn) = cur_insn_uid++; |
15bbde2b | 2485 | PATTERN (insn) = pattern; |
2486 | INSN_CODE (insn) = -1; | |
fc92fa61 | 2487 | LOG_LINKS (insn) = NULL; |
2488 | REG_NOTES (insn) = NULL; | |
15bbde2b | 2489 | |
fe7f701d | 2490 | #ifdef ENABLE_RTL_CHECKING |
2491 | if (insn | |
9204e736 | 2492 | && INSN_P (insn) |
fe7f701d | 2493 | && (returnjump_p (insn) |
2494 | || (GET_CODE (insn) == SET | |
2495 | && SET_DEST (insn) == pc_rtx))) | |
2496 | { | |
2497 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2498 | debug_rtx (insn); | |
2499 | } | |
2500 | #endif | |
2501 | ||
15bbde2b | 2502 | return insn; |
2503 | } | |
2504 | ||
2505 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2506 | ||
2507 | static rtx | |
6a84e367 | 2508 | make_jump_insn_raw (pattern) |
15bbde2b | 2509 | rtx pattern; |
15bbde2b | 2510 | { |
2511 | register rtx insn; | |
2512 | ||
6a84e367 | 2513 | insn = rtx_alloc (JUMP_INSN); |
fc92fa61 | 2514 | INSN_UID (insn) = cur_insn_uid++; |
15bbde2b | 2515 | |
2516 | PATTERN (insn) = pattern; | |
2517 | INSN_CODE (insn) = -1; | |
fc92fa61 | 2518 | LOG_LINKS (insn) = NULL; |
2519 | REG_NOTES (insn) = NULL; | |
2520 | JUMP_LABEL (insn) = NULL; | |
15bbde2b | 2521 | |
2522 | return insn; | |
2523 | } | |
6e911104 | 2524 | |
2525 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2526 | ||
2527 | static rtx | |
2528 | make_call_insn_raw (pattern) | |
2529 | rtx pattern; | |
2530 | { | |
2531 | register rtx insn; | |
2532 | ||
2533 | insn = rtx_alloc (CALL_INSN); | |
2534 | INSN_UID (insn) = cur_insn_uid++; | |
2535 | ||
2536 | PATTERN (insn) = pattern; | |
2537 | INSN_CODE (insn) = -1; | |
2538 | LOG_LINKS (insn) = NULL; | |
2539 | REG_NOTES (insn) = NULL; | |
2540 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2541 | ||
2542 | return insn; | |
2543 | } | |
15bbde2b | 2544 | \f |
2545 | /* Add INSN to the end of the doubly-linked list. | |
2546 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2547 | ||
2548 | void | |
2549 | add_insn (insn) | |
2550 | register rtx insn; | |
2551 | { | |
2552 | PREV_INSN (insn) = last_insn; | |
2553 | NEXT_INSN (insn) = 0; | |
2554 | ||
2555 | if (NULL != last_insn) | |
2556 | NEXT_INSN (last_insn) = insn; | |
2557 | ||
2558 | if (NULL == first_insn) | |
2559 | first_insn = insn; | |
2560 | ||
2561 | last_insn = insn; | |
2562 | } | |
2563 | ||
312de84d | 2564 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2565 | the next should be the only functions called to insert an insn once | |
f65c10c0 | 2566 | delay slots have been filled since only they know how to update a |
312de84d | 2567 | SEQUENCE. */ |
15bbde2b | 2568 | |
2569 | void | |
2570 | add_insn_after (insn, after) | |
2571 | rtx insn, after; | |
2572 | { | |
2573 | rtx next = NEXT_INSN (after); | |
2574 | ||
9ea33026 | 2575 | if (optimize && INSN_DELETED_P (after)) |
f65c10c0 | 2576 | abort (); |
2577 | ||
15bbde2b | 2578 | NEXT_INSN (insn) = next; |
2579 | PREV_INSN (insn) = after; | |
2580 | ||
2581 | if (next) | |
2582 | { | |
2583 | PREV_INSN (next) = insn; | |
2584 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2585 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2586 | } | |
2587 | else if (last_insn == after) | |
2588 | last_insn = insn; | |
2589 | else | |
2590 | { | |
0a893c29 | 2591 | struct sequence_stack *stack = seq_stack; |
15bbde2b | 2592 | /* Scan all pending sequences too. */ |
2593 | for (; stack; stack = stack->next) | |
2594 | if (after == stack->last) | |
398f4855 | 2595 | { |
2596 | stack->last = insn; | |
2597 | break; | |
2598 | } | |
312de84d | 2599 | |
2600 | if (stack == 0) | |
2601 | abort (); | |
15bbde2b | 2602 | } |
2603 | ||
2604 | NEXT_INSN (after) = insn; | |
2605 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2606 | { | |
2607 | rtx sequence = PATTERN (after); | |
2608 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2609 | } | |
2610 | } | |
2611 | ||
312de84d | 2612 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2613 | the previous should be the only functions called to insert an insn once | |
f65c10c0 | 2614 | delay slots have been filled since only they know how to update a |
312de84d | 2615 | SEQUENCE. */ |
2616 | ||
2617 | void | |
2618 | add_insn_before (insn, before) | |
2619 | rtx insn, before; | |
2620 | { | |
2621 | rtx prev = PREV_INSN (before); | |
2622 | ||
9ea33026 | 2623 | if (optimize && INSN_DELETED_P (before)) |
f65c10c0 | 2624 | abort (); |
2625 | ||
312de84d | 2626 | PREV_INSN (insn) = prev; |
2627 | NEXT_INSN (insn) = before; | |
2628 | ||
2629 | if (prev) | |
2630 | { | |
2631 | NEXT_INSN (prev) = insn; | |
2632 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2633 | { | |
2634 | rtx sequence = PATTERN (prev); | |
2635 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2636 | } | |
2637 | } | |
2638 | else if (first_insn == before) | |
2639 | first_insn = insn; | |
2640 | else | |
2641 | { | |
0a893c29 | 2642 | struct sequence_stack *stack = seq_stack; |
312de84d | 2643 | /* Scan all pending sequences too. */ |
2644 | for (; stack; stack = stack->next) | |
2645 | if (before == stack->first) | |
398f4855 | 2646 | { |
2647 | stack->first = insn; | |
2648 | break; | |
2649 | } | |
312de84d | 2650 | |
2651 | if (stack == 0) | |
2652 | abort (); | |
2653 | } | |
2654 | ||
2655 | PREV_INSN (before) = insn; | |
2656 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2657 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2658 | } | |
2659 | ||
7ddcf2bf | 2660 | /* Remove an insn from its doubly-linked list. This function knows how |
2661 | to handle sequences. */ | |
2662 | void | |
2663 | remove_insn (insn) | |
2664 | rtx insn; | |
2665 | { | |
2666 | rtx next = NEXT_INSN (insn); | |
2667 | rtx prev = PREV_INSN (insn); | |
2668 | if (prev) | |
2669 | { | |
2670 | NEXT_INSN (prev) = next; | |
2671 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2672 | { | |
2673 | rtx sequence = PATTERN (prev); | |
2674 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2675 | } | |
2676 | } | |
2677 | else if (first_insn == insn) | |
2678 | first_insn = next; | |
2679 | else | |
2680 | { | |
0a893c29 | 2681 | struct sequence_stack *stack = seq_stack; |
7ddcf2bf | 2682 | /* Scan all pending sequences too. */ |
2683 | for (; stack; stack = stack->next) | |
2684 | if (insn == stack->first) | |
2685 | { | |
2686 | stack->first = next; | |
2687 | break; | |
2688 | } | |
2689 | ||
2690 | if (stack == 0) | |
2691 | abort (); | |
2692 | } | |
2693 | ||
2694 | if (next) | |
2695 | { | |
2696 | PREV_INSN (next) = prev; | |
2697 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2698 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2699 | } | |
2700 | else if (last_insn == insn) | |
2701 | last_insn = prev; | |
2702 | else | |
2703 | { | |
0a893c29 | 2704 | struct sequence_stack *stack = seq_stack; |
7ddcf2bf | 2705 | /* Scan all pending sequences too. */ |
2706 | for (; stack; stack = stack->next) | |
2707 | if (insn == stack->last) | |
2708 | { | |
2709 | stack->last = prev; | |
2710 | break; | |
2711 | } | |
2712 | ||
2713 | if (stack == 0) | |
2714 | abort (); | |
2715 | } | |
2716 | } | |
2717 | ||
15bbde2b | 2718 | /* Delete all insns made since FROM. |
2719 | FROM becomes the new last instruction. */ | |
2720 | ||
2721 | void | |
2722 | delete_insns_since (from) | |
2723 | rtx from; | |
2724 | { | |
2725 | if (from == 0) | |
2726 | first_insn = 0; | |
2727 | else | |
2728 | NEXT_INSN (from) = 0; | |
2729 | last_insn = from; | |
2730 | } | |
2731 | ||
34e2ddcd | 2732 | /* This function is deprecated, please use sequences instead. |
2733 | ||
2734 | Move a consecutive bunch of insns to a different place in the chain. | |
15bbde2b | 2735 | The insns to be moved are those between FROM and TO. |
2736 | They are moved to a new position after the insn AFTER. | |
2737 | AFTER must not be FROM or TO or any insn in between. | |
2738 | ||
2739 | This function does not know about SEQUENCEs and hence should not be | |
2740 | called after delay-slot filling has been done. */ | |
2741 | ||
2742 | void | |
2743 | reorder_insns (from, to, after) | |
2744 | rtx from, to, after; | |
2745 | { | |
2746 | /* Splice this bunch out of where it is now. */ | |
2747 | if (PREV_INSN (from)) | |
2748 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2749 | if (NEXT_INSN (to)) | |
2750 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2751 | if (last_insn == to) | |
2752 | last_insn = PREV_INSN (from); | |
2753 | if (first_insn == from) | |
2754 | first_insn = NEXT_INSN (to); | |
2755 | ||
2756 | /* Make the new neighbors point to it and it to them. */ | |
2757 | if (NEXT_INSN (after)) | |
2758 | PREV_INSN (NEXT_INSN (after)) = to; | |
2759 | ||
2760 | NEXT_INSN (to) = NEXT_INSN (after); | |
2761 | PREV_INSN (from) = after; | |
2762 | NEXT_INSN (after) = from; | |
2763 | if (after == last_insn) | |
2764 | last_insn = to; | |
2765 | } | |
2766 | ||
2767 | /* Return the line note insn preceding INSN. */ | |
2768 | ||
2769 | static rtx | |
2770 | find_line_note (insn) | |
2771 | rtx insn; | |
2772 | { | |
2773 | if (no_line_numbers) | |
2774 | return 0; | |
2775 | ||
2776 | for (; insn; insn = PREV_INSN (insn)) | |
2777 | if (GET_CODE (insn) == NOTE | |
2778 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2779 | break; | |
2780 | ||
2781 | return insn; | |
2782 | } | |
2783 | ||
2784 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2785 | of the moved insns when debugging. This may insert a note between AFTER | |
2786 | and FROM, and another one after TO. */ | |
2787 | ||
2788 | void | |
2789 | reorder_insns_with_line_notes (from, to, after) | |
2790 | rtx from, to, after; | |
2791 | { | |
2792 | rtx from_line = find_line_note (from); | |
2793 | rtx after_line = find_line_note (after); | |
2794 | ||
2795 | reorder_insns (from, to, after); | |
2796 | ||
2797 | if (from_line == after_line) | |
2798 | return; | |
2799 | ||
2800 | if (from_line) | |
2801 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2802 | NOTE_LINE_NUMBER (from_line), | |
2803 | after); | |
2804 | if (after_line) | |
2805 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2806 | NOTE_LINE_NUMBER (after_line), | |
2807 | to); | |
2808 | } | |
90b89d2c | 2809 | |
0a78547b | 2810 | /* Remove unnecessary notes from the instruction stream. */ |
90b89d2c | 2811 | |
2812 | void | |
0a78547b | 2813 | remove_unnecessary_notes () |
90b89d2c | 2814 | { |
2815 | rtx insn; | |
2816 | rtx next; | |
90b89d2c | 2817 | |
f1ab82be | 2818 | /* We must not remove the first instruction in the function because |
2819 | the compiler depends on the first instruction being a note. */ | |
90b89d2c | 2820 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
2821 | { | |
2822 | /* Remember what's next. */ | |
2823 | next = NEXT_INSN (insn); | |
2824 | ||
2825 | /* We're only interested in notes. */ | |
2826 | if (GET_CODE (insn) != NOTE) | |
2827 | continue; | |
2828 | ||
f1ab82be | 2829 | /* By now, all notes indicating lexical blocks should have |
2830 | NOTE_BLOCK filled in. */ | |
2831 | if ((NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG | |
2832 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) | |
2833 | && NOTE_BLOCK (insn) == NULL_TREE) | |
2834 | abort (); | |
2835 | ||
2836 | /* Remove NOTE_INSN_DELETED notes. */ | |
90b89d2c | 2837 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) |
2838 | remove_insn (insn); | |
5846cb0f | 2839 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) |
2840 | { | |
2841 | /* Scan back to see if there are any non-note instructions | |
2842 | between INSN and the beginning of this block. If not, | |
2843 | then there is no PC range in the generated code that will | |
2844 | actually be in this block, so there's no point in | |
2845 | remembering the existence of the block. */ | |
2846 | rtx prev; | |
2847 | ||
2848 | for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev)) | |
2849 | { | |
2850 | /* This block contains a real instruction. Note that we | |
2851 | don't include labels; if the only thing in the block | |
2852 | is a label, then there are still no PC values that | |
2853 | lie within the block. */ | |
9204e736 | 2854 | if (INSN_P (prev)) |
5846cb0f | 2855 | break; |
2856 | ||
2857 | /* We're only interested in NOTEs. */ | |
2858 | if (GET_CODE (prev) != NOTE) | |
2859 | continue; | |
2860 | ||
2861 | if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_BEG) | |
2862 | { | |
2863 | /* If the BLOCKs referred to by these notes don't | |
2864 | match, then something is wrong with our BLOCK | |
2865 | nesting structure. */ | |
2866 | if (NOTE_BLOCK (prev) != NOTE_BLOCK (insn)) | |
2867 | abort (); | |
ad2fe2cd | 2868 | |
0a78547b | 2869 | if (debug_ignore_block (NOTE_BLOCK (insn))) |
e33dbbdf | 2870 | { |
e33dbbdf | 2871 | remove_insn (prev); |
2872 | remove_insn (insn); | |
2873 | } | |
5846cb0f | 2874 | break; |
2875 | } | |
2876 | else if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_END) | |
2877 | /* There's a nested block. We need to leave the | |
2878 | current block in place since otherwise the debugger | |
2879 | wouldn't be able to show symbols from our block in | |
2880 | the nested block. */ | |
2881 | break; | |
2882 | } | |
2883 | } | |
90b89d2c | 2884 | } |
2885 | } | |
2886 | ||
15bbde2b | 2887 | \f |
2888 | /* Emit an insn of given code and pattern | |
2889 | at a specified place within the doubly-linked list. */ | |
2890 | ||
2891 | /* Make an instruction with body PATTERN | |
2892 | and output it before the instruction BEFORE. */ | |
2893 | ||
2894 | rtx | |
2895 | emit_insn_before (pattern, before) | |
2896 | register rtx pattern, before; | |
2897 | { | |
2898 | register rtx insn = before; | |
2899 | ||
2900 | if (GET_CODE (pattern) == SEQUENCE) | |
2901 | { | |
2902 | register int i; | |
2903 | ||
2904 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2905 | { | |
2906 | insn = XVECEXP (pattern, 0, i); | |
312de84d | 2907 | add_insn_before (insn, before); |
15bbde2b | 2908 | } |
15bbde2b | 2909 | } |
2910 | else | |
2911 | { | |
6a84e367 | 2912 | insn = make_insn_raw (pattern); |
312de84d | 2913 | add_insn_before (insn, before); |
15bbde2b | 2914 | } |
2915 | ||
2916 | return insn; | |
2917 | } | |
2918 | ||
f3d96a58 | 2919 | /* Similar to emit_insn_before, but update basic block boundaries as well. */ |
2920 | ||
2921 | rtx | |
2922 | emit_block_insn_before (pattern, before, block) | |
2923 | rtx pattern, before; | |
2924 | basic_block block; | |
2925 | { | |
2926 | rtx prev = PREV_INSN (before); | |
2927 | rtx r = emit_insn_before (pattern, before); | |
2928 | if (block && block->head == before) | |
2929 | block->head = NEXT_INSN (prev); | |
2930 | return r; | |
2931 | } | |
2932 | ||
15bbde2b | 2933 | /* Make an instruction with body PATTERN and code JUMP_INSN |
2934 | and output it before the instruction BEFORE. */ | |
2935 | ||
2936 | rtx | |
2937 | emit_jump_insn_before (pattern, before) | |
2938 | register rtx pattern, before; | |
2939 | { | |
2940 | register rtx insn; | |
2941 | ||
2942 | if (GET_CODE (pattern) == SEQUENCE) | |
2943 | insn = emit_insn_before (pattern, before); | |
2944 | else | |
2945 | { | |
8f060628 | 2946 | insn = make_jump_insn_raw (pattern); |
312de84d | 2947 | add_insn_before (insn, before); |
15bbde2b | 2948 | } |
2949 | ||
2950 | return insn; | |
2951 | } | |
2952 | ||
2953 | /* Make an instruction with body PATTERN and code CALL_INSN | |
2954 | and output it before the instruction BEFORE. */ | |
2955 | ||
2956 | rtx | |
2957 | emit_call_insn_before (pattern, before) | |
2958 | register rtx pattern, before; | |
2959 | { | |
6e911104 | 2960 | register rtx insn; |
2961 | ||
2962 | if (GET_CODE (pattern) == SEQUENCE) | |
2963 | insn = emit_insn_before (pattern, before); | |
2964 | else | |
2965 | { | |
2966 | insn = make_call_insn_raw (pattern); | |
312de84d | 2967 | add_insn_before (insn, before); |
6e911104 | 2968 | PUT_CODE (insn, CALL_INSN); |
2969 | } | |
2970 | ||
15bbde2b | 2971 | return insn; |
2972 | } | |
2973 | ||
2974 | /* Make an insn of code BARRIER | |
71caadc0 | 2975 | and output it before the insn BEFORE. */ |
15bbde2b | 2976 | |
2977 | rtx | |
2978 | emit_barrier_before (before) | |
2979 | register rtx before; | |
2980 | { | |
2981 | register rtx insn = rtx_alloc (BARRIER); | |
2982 | ||
2983 | INSN_UID (insn) = cur_insn_uid++; | |
2984 | ||
312de84d | 2985 | add_insn_before (insn, before); |
15bbde2b | 2986 | return insn; |
2987 | } | |
2988 | ||
71caadc0 | 2989 | /* Emit the label LABEL before the insn BEFORE. */ |
2990 | ||
2991 | rtx | |
2992 | emit_label_before (label, before) | |
2993 | rtx label, before; | |
2994 | { | |
2995 | /* This can be called twice for the same label as a result of the | |
2996 | confusion that follows a syntax error! So make it harmless. */ | |
2997 | if (INSN_UID (label) == 0) | |
2998 | { | |
2999 | INSN_UID (label) = cur_insn_uid++; | |
3000 | add_insn_before (label, before); | |
3001 | } | |
3002 | ||
3003 | return label; | |
3004 | } | |
3005 | ||
15bbde2b | 3006 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
3007 | ||
3008 | rtx | |
3009 | emit_note_before (subtype, before) | |
3010 | int subtype; | |
3011 | rtx before; | |
3012 | { | |
3013 | register rtx note = rtx_alloc (NOTE); | |
3014 | INSN_UID (note) = cur_insn_uid++; | |
3015 | NOTE_SOURCE_FILE (note) = 0; | |
3016 | NOTE_LINE_NUMBER (note) = subtype; | |
3017 | ||
312de84d | 3018 | add_insn_before (note, before); |
15bbde2b | 3019 | return note; |
3020 | } | |
3021 | \f | |
3022 | /* Make an insn of code INSN with body PATTERN | |
3023 | and output it after the insn AFTER. */ | |
3024 | ||
3025 | rtx | |
3026 | emit_insn_after (pattern, after) | |
3027 | register rtx pattern, after; | |
3028 | { | |
3029 | register rtx insn = after; | |
3030 | ||
3031 | if (GET_CODE (pattern) == SEQUENCE) | |
3032 | { | |
3033 | register int i; | |
3034 | ||
3035 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3036 | { | |
3037 | insn = XVECEXP (pattern, 0, i); | |
3038 | add_insn_after (insn, after); | |
3039 | after = insn; | |
3040 | } | |
15bbde2b | 3041 | } |
3042 | else | |
3043 | { | |
6a84e367 | 3044 | insn = make_insn_raw (pattern); |
15bbde2b | 3045 | add_insn_after (insn, after); |
3046 | } | |
3047 | ||
3048 | return insn; | |
3049 | } | |
3050 | ||
1bea98fb | 3051 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
3052 | as to act as if this insn were at FROM. */ | |
3053 | ||
3054 | void | |
3055 | emit_insn_after_with_line_notes (pattern, after, from) | |
3056 | rtx pattern, after, from; | |
3057 | { | |
3058 | rtx from_line = find_line_note (from); | |
3059 | rtx after_line = find_line_note (after); | |
3060 | rtx insn = emit_insn_after (pattern, after); | |
3061 | ||
3062 | if (from_line) | |
3063 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3064 | NOTE_LINE_NUMBER (from_line), | |
3065 | after); | |
3066 | ||
3067 | if (after_line) | |
3068 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3069 | NOTE_LINE_NUMBER (after_line), | |
3070 | insn); | |
3071 | } | |
3072 | ||
f3d96a58 | 3073 | /* Similar to emit_insn_after, but update basic block boundaries as well. */ |
3074 | ||
3075 | rtx | |
3076 | emit_block_insn_after (pattern, after, block) | |
3077 | rtx pattern, after; | |
3078 | basic_block block; | |
3079 | { | |
3080 | rtx r = emit_insn_after (pattern, after); | |
3081 | if (block && block->end == after) | |
3082 | block->end = r; | |
3083 | return r; | |
3084 | } | |
3085 | ||
15bbde2b | 3086 | /* Make an insn of code JUMP_INSN with body PATTERN |
3087 | and output it after the insn AFTER. */ | |
3088 | ||
3089 | rtx | |
3090 | emit_jump_insn_after (pattern, after) | |
3091 | register rtx pattern, after; | |
3092 | { | |
3093 | register rtx insn; | |
3094 | ||
3095 | if (GET_CODE (pattern) == SEQUENCE) | |
3096 | insn = emit_insn_after (pattern, after); | |
3097 | else | |
3098 | { | |
8f060628 | 3099 | insn = make_jump_insn_raw (pattern); |
15bbde2b | 3100 | add_insn_after (insn, after); |
3101 | } | |
3102 | ||
3103 | return insn; | |
3104 | } | |
3105 | ||
3106 | /* Make an insn of code BARRIER | |
3107 | and output it after the insn AFTER. */ | |
3108 | ||
3109 | rtx | |
3110 | emit_barrier_after (after) | |
3111 | register rtx after; | |
3112 | { | |
3113 | register rtx insn = rtx_alloc (BARRIER); | |
3114 | ||
3115 | INSN_UID (insn) = cur_insn_uid++; | |
3116 | ||
3117 | add_insn_after (insn, after); | |
3118 | return insn; | |
3119 | } | |
3120 | ||
3121 | /* Emit the label LABEL after the insn AFTER. */ | |
3122 | ||
3123 | rtx | |
3124 | emit_label_after (label, after) | |
3125 | rtx label, after; | |
3126 | { | |
3127 | /* This can be called twice for the same label | |
3128 | as a result of the confusion that follows a syntax error! | |
3129 | So make it harmless. */ | |
3130 | if (INSN_UID (label) == 0) | |
3131 | { | |
3132 | INSN_UID (label) = cur_insn_uid++; | |
3133 | add_insn_after (label, after); | |
3134 | } | |
3135 | ||
3136 | return label; | |
3137 | } | |
3138 | ||
3139 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3140 | ||
3141 | rtx | |
3142 | emit_note_after (subtype, after) | |
3143 | int subtype; | |
3144 | rtx after; | |
3145 | { | |
3146 | register rtx note = rtx_alloc (NOTE); | |
3147 | INSN_UID (note) = cur_insn_uid++; | |
3148 | NOTE_SOURCE_FILE (note) = 0; | |
3149 | NOTE_LINE_NUMBER (note) = subtype; | |
3150 | add_insn_after (note, after); | |
3151 | return note; | |
3152 | } | |
3153 | ||
3154 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3155 | ||
3156 | rtx | |
3157 | emit_line_note_after (file, line, after) | |
9a356c3c | 3158 | const char *file; |
15bbde2b | 3159 | int line; |
3160 | rtx after; | |
3161 | { | |
3162 | register rtx note; | |
3163 | ||
3164 | if (no_line_numbers && line > 0) | |
3165 | { | |
3166 | cur_insn_uid++; | |
3167 | return 0; | |
3168 | } | |
3169 | ||
3170 | note = rtx_alloc (NOTE); | |
3171 | INSN_UID (note) = cur_insn_uid++; | |
3172 | NOTE_SOURCE_FILE (note) = file; | |
3173 | NOTE_LINE_NUMBER (note) = line; | |
3174 | add_insn_after (note, after); | |
3175 | return note; | |
3176 | } | |
3177 | \f | |
3178 | /* Make an insn of code INSN with pattern PATTERN | |
3179 | and add it to the end of the doubly-linked list. | |
3180 | If PATTERN is a SEQUENCE, take the elements of it | |
3181 | and emit an insn for each element. | |
3182 | ||
3183 | Returns the last insn emitted. */ | |
3184 | ||
3185 | rtx | |
3186 | emit_insn (pattern) | |
3187 | rtx pattern; | |
3188 | { | |
3189 | rtx insn = last_insn; | |
3190 | ||
3191 | if (GET_CODE (pattern) == SEQUENCE) | |
3192 | { | |
3193 | register int i; | |
3194 | ||
3195 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3196 | { | |
3197 | insn = XVECEXP (pattern, 0, i); | |
3198 | add_insn (insn); | |
3199 | } | |
15bbde2b | 3200 | } |
3201 | else | |
3202 | { | |
6a84e367 | 3203 | insn = make_insn_raw (pattern); |
15bbde2b | 3204 | add_insn (insn); |
3205 | } | |
3206 | ||
3207 | return insn; | |
3208 | } | |
3209 | ||
3210 | /* Emit the insns in a chain starting with INSN. | |
3211 | Return the last insn emitted. */ | |
3212 | ||
3213 | rtx | |
3214 | emit_insns (insn) | |
3215 | rtx insn; | |
3216 | { | |
3217 | rtx last = 0; | |
3218 | ||
3219 | while (insn) | |
3220 | { | |
3221 | rtx next = NEXT_INSN (insn); | |
3222 | add_insn (insn); | |
3223 | last = insn; | |
3224 | insn = next; | |
3225 | } | |
3226 | ||
3227 | return last; | |
3228 | } | |
3229 | ||
3230 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3231 | the insn BEFORE. Return the last insn emitted. */ | |
3232 | ||
3233 | rtx | |
3234 | emit_insns_before (insn, before) | |
3235 | rtx insn; | |
3236 | rtx before; | |
3237 | { | |
3238 | rtx last = 0; | |
3239 | ||
3240 | while (insn) | |
3241 | { | |
3242 | rtx next = NEXT_INSN (insn); | |
312de84d | 3243 | add_insn_before (insn, before); |
15bbde2b | 3244 | last = insn; |
3245 | insn = next; | |
3246 | } | |
3247 | ||
3248 | return last; | |
3249 | } | |
3250 | ||
b36b07d8 | 3251 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3252 | the insn AFTER. Return the last insn emitted. */ | |
3253 | ||
3254 | rtx | |
3255 | emit_insns_after (first, after) | |
3256 | register rtx first; | |
3257 | register rtx after; | |
3258 | { | |
3259 | register rtx last; | |
3260 | register rtx after_after; | |
3261 | ||
3262 | if (!after) | |
3263 | abort (); | |
3264 | ||
3265 | if (!first) | |
3266 | return first; | |
3267 | ||
3268 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3269 | continue; | |
3270 | ||
3271 | after_after = NEXT_INSN (after); | |
3272 | ||
3273 | NEXT_INSN (after) = first; | |
3274 | PREV_INSN (first) = after; | |
3275 | NEXT_INSN (last) = after_after; | |
3276 | if (after_after) | |
3277 | PREV_INSN (after_after) = last; | |
3278 | ||
0c905390 | 3279 | if (after == last_insn) |
3280 | last_insn = last; | |
b36b07d8 | 3281 | return last; |
3282 | } | |
3283 | ||
15bbde2b | 3284 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3285 | and add it to the end of the doubly-linked list. */ | |
3286 | ||
3287 | rtx | |
3288 | emit_jump_insn (pattern) | |
3289 | rtx pattern; | |
3290 | { | |
3291 | if (GET_CODE (pattern) == SEQUENCE) | |
3292 | return emit_insn (pattern); | |
3293 | else | |
3294 | { | |
8f060628 | 3295 | register rtx insn = make_jump_insn_raw (pattern); |
15bbde2b | 3296 | add_insn (insn); |
3297 | return insn; | |
3298 | } | |
3299 | } | |
3300 | ||
3301 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3302 | and add it to the end of the doubly-linked list. */ | |
3303 | ||
3304 | rtx | |
3305 | emit_call_insn (pattern) | |
3306 | rtx pattern; | |
3307 | { | |
3308 | if (GET_CODE (pattern) == SEQUENCE) | |
3309 | return emit_insn (pattern); | |
3310 | else | |
3311 | { | |
6e911104 | 3312 | register rtx insn = make_call_insn_raw (pattern); |
15bbde2b | 3313 | add_insn (insn); |
3314 | PUT_CODE (insn, CALL_INSN); | |
3315 | return insn; | |
3316 | } | |
3317 | } | |
3318 | ||
3319 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3320 | ||
3321 | rtx | |
3322 | emit_label (label) | |
3323 | rtx label; | |
3324 | { | |
3325 | /* This can be called twice for the same label | |
3326 | as a result of the confusion that follows a syntax error! | |
3327 | So make it harmless. */ | |
3328 | if (INSN_UID (label) == 0) | |
3329 | { | |
3330 | INSN_UID (label) = cur_insn_uid++; | |
3331 | add_insn (label); | |
3332 | } | |
3333 | return label; | |
3334 | } | |
3335 | ||
3336 | /* Make an insn of code BARRIER | |
3337 | and add it to the end of the doubly-linked list. */ | |
3338 | ||
3339 | rtx | |
3340 | emit_barrier () | |
3341 | { | |
3342 | register rtx barrier = rtx_alloc (BARRIER); | |
3343 | INSN_UID (barrier) = cur_insn_uid++; | |
3344 | add_insn (barrier); | |
3345 | return barrier; | |
3346 | } | |
3347 | ||
3348 | /* Make an insn of code NOTE | |
3349 | with data-fields specified by FILE and LINE | |
3350 | and add it to the end of the doubly-linked list, | |
3351 | but only if line-numbers are desired for debugging info. */ | |
3352 | ||
3353 | rtx | |
3354 | emit_line_note (file, line) | |
9a356c3c | 3355 | const char *file; |
15bbde2b | 3356 | int line; |
3357 | { | |
21b005ed | 3358 | set_file_and_line_for_stmt (file, line); |
15bbde2b | 3359 | |
3360 | #if 0 | |
3361 | if (no_line_numbers) | |
3362 | return 0; | |
3363 | #endif | |
3364 | ||
3365 | return emit_note (file, line); | |
3366 | } | |
3367 | ||
3368 | /* Make an insn of code NOTE | |
3369 | with data-fields specified by FILE and LINE | |
3370 | and add it to the end of the doubly-linked list. | |
3371 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3372 | ||
3373 | rtx | |
3374 | emit_note (file, line) | |
9a356c3c | 3375 | const char *file; |
15bbde2b | 3376 | int line; |
3377 | { | |
3378 | register rtx note; | |
3379 | ||
3380 | if (line > 0) | |
3381 | { | |
3382 | if (file && last_filename && !strcmp (file, last_filename) | |
3383 | && line == last_linenum) | |
3384 | return 0; | |
3385 | last_filename = file; | |
3386 | last_linenum = line; | |
3387 | } | |
3388 | ||
3389 | if (no_line_numbers && line > 0) | |
3390 | { | |
3391 | cur_insn_uid++; | |
3392 | return 0; | |
3393 | } | |
3394 | ||
3395 | note = rtx_alloc (NOTE); | |
3396 | INSN_UID (note) = cur_insn_uid++; | |
3397 | NOTE_SOURCE_FILE (note) = file; | |
3398 | NOTE_LINE_NUMBER (note) = line; | |
3399 | add_insn (note); | |
3400 | return note; | |
3401 | } | |
3402 | ||
8d54063f | 3403 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
15bbde2b | 3404 | |
3405 | rtx | |
3406 | emit_line_note_force (file, line) | |
9a356c3c | 3407 | const char *file; |
15bbde2b | 3408 | int line; |
3409 | { | |
3410 | last_linenum = -1; | |
3411 | return emit_line_note (file, line); | |
3412 | } | |
3413 | ||
3414 | /* Cause next statement to emit a line note even if the line number | |
3415 | has not changed. This is used at the beginning of a function. */ | |
3416 | ||
3417 | void | |
3418 | force_next_line_note () | |
3419 | { | |
3420 | last_linenum = -1; | |
3421 | } | |
f1934a33 | 3422 | |
3423 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
3424 | note of this type already exists, remove it first. */ | |
3425 | ||
3426 | void | |
3427 | set_unique_reg_note (insn, kind, datum) | |
3428 | rtx insn; | |
3429 | enum reg_note kind; | |
3430 | rtx datum; | |
3431 | { | |
3432 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3433 | ||
3434 | /* First remove the note if there already is one. */ | |
3435 | if (note) | |
3436 | remove_note (insn, note); | |
3437 | ||
3438 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3439 | } | |
15bbde2b | 3440 | \f |
3441 | /* Return an indication of which type of insn should have X as a body. | |
3442 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3443 | ||
3444 | enum rtx_code | |
3445 | classify_insn (x) | |
3446 | rtx x; | |
3447 | { | |
3448 | if (GET_CODE (x) == CODE_LABEL) | |
3449 | return CODE_LABEL; | |
3450 | if (GET_CODE (x) == CALL) | |
3451 | return CALL_INSN; | |
3452 | if (GET_CODE (x) == RETURN) | |
3453 | return JUMP_INSN; | |
3454 | if (GET_CODE (x) == SET) | |
3455 | { | |
3456 | if (SET_DEST (x) == pc_rtx) | |
3457 | return JUMP_INSN; | |
3458 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3459 | return CALL_INSN; | |
3460 | else | |
3461 | return INSN; | |
3462 | } | |
3463 | if (GET_CODE (x) == PARALLEL) | |
3464 | { | |
3465 | register int j; | |
3466 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3467 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3468 | return CALL_INSN; | |
3469 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3470 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3471 | return JUMP_INSN; | |
3472 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3473 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3474 | return CALL_INSN; | |
3475 | } | |
3476 | return INSN; | |
3477 | } | |
3478 | ||
3479 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3480 | If X is a label, it is simply added into the insn chain. */ | |
3481 | ||
3482 | rtx | |
3483 | emit (x) | |
3484 | rtx x; | |
3485 | { | |
3486 | enum rtx_code code = classify_insn (x); | |
3487 | ||
3488 | if (code == CODE_LABEL) | |
3489 | return emit_label (x); | |
3490 | else if (code == INSN) | |
3491 | return emit_insn (x); | |
3492 | else if (code == JUMP_INSN) | |
3493 | { | |
3494 | register rtx insn = emit_jump_insn (x); | |
b2816317 | 3495 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
15bbde2b | 3496 | return emit_barrier (); |
3497 | return insn; | |
3498 | } | |
3499 | else if (code == CALL_INSN) | |
3500 | return emit_call_insn (x); | |
3501 | else | |
3502 | abort (); | |
3503 | } | |
3504 | \f | |
b49854c6 | 3505 | /* Begin emitting insns to a sequence which can be packaged in an |
3506 | RTL_EXPR. If this sequence will contain something that might cause | |
3507 | the compiler to pop arguments to function calls (because those | |
3508 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3509 | details), use do_pending_stack_adjust before calling this function. | |
3510 | That will ensure that the deferred pops are not accidentally | |
9588521d | 3511 | emitted in the middle of this sequence. */ |
15bbde2b | 3512 | |
3513 | void | |
3514 | start_sequence () | |
3515 | { | |
3516 | struct sequence_stack *tem; | |
3517 | ||
1bfd55c5 | 3518 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
15bbde2b | 3519 | |
0a893c29 | 3520 | tem->next = seq_stack; |
15bbde2b | 3521 | tem->first = first_insn; |
3522 | tem->last = last_insn; | |
961819fb | 3523 | tem->sequence_rtl_expr = seq_rtl_expr; |
15bbde2b | 3524 | |
0a893c29 | 3525 | seq_stack = tem; |
15bbde2b | 3526 | |
3527 | first_insn = 0; | |
3528 | last_insn = 0; | |
3529 | } | |
3530 | ||
961819fb | 3531 | /* Similarly, but indicate that this sequence will be placed in T, an |
3532 | RTL_EXPR. See the documentation for start_sequence for more | |
3533 | information about how to use this function. */ | |
3534 | ||
3535 | void | |
3536 | start_sequence_for_rtl_expr (t) | |
3537 | tree t; | |
3538 | { | |
3539 | start_sequence (); | |
3540 | ||
3541 | seq_rtl_expr = t; | |
3542 | } | |
3543 | ||
b49854c6 | 3544 | /* Set up the insn chain starting with FIRST as the current sequence, |
3545 | saving the previously current one. See the documentation for | |
3546 | start_sequence for more information about how to use this function. */ | |
15bbde2b | 3547 | |
3548 | void | |
3549 | push_to_sequence (first) | |
3550 | rtx first; | |
3551 | { | |
3552 | rtx last; | |
3553 | ||
3554 | start_sequence (); | |
3555 | ||
3556 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3557 | ||
3558 | first_insn = first; | |
3559 | last_insn = last; | |
3560 | } | |
3561 | ||
78147e84 | 3562 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3563 | ||
3564 | void | |
3565 | push_to_full_sequence (first, last) | |
3566 | rtx first, last; | |
3567 | { | |
3568 | start_sequence (); | |
3569 | first_insn = first; | |
3570 | last_insn = last; | |
3571 | /* We really should have the end of the insn chain here. */ | |
3572 | if (last && NEXT_INSN (last)) | |
3573 | abort (); | |
3574 | } | |
3575 | ||
ab74c92f | 3576 | /* Set up the outer-level insn chain |
3577 | as the current sequence, saving the previously current one. */ | |
3578 | ||
3579 | void | |
3580 | push_topmost_sequence () | |
3581 | { | |
2041cfd9 | 3582 | struct sequence_stack *stack, *top = NULL; |
ab74c92f | 3583 | |
3584 | start_sequence (); | |
3585 | ||
0a893c29 | 3586 | for (stack = seq_stack; stack; stack = stack->next) |
ab74c92f | 3587 | top = stack; |
3588 | ||
3589 | first_insn = top->first; | |
3590 | last_insn = top->last; | |
961819fb | 3591 | seq_rtl_expr = top->sequence_rtl_expr; |
ab74c92f | 3592 | } |
3593 | ||
3594 | /* After emitting to the outer-level insn chain, update the outer-level | |
3595 | insn chain, and restore the previous saved state. */ | |
3596 | ||
3597 | void | |
3598 | pop_topmost_sequence () | |
3599 | { | |
2041cfd9 | 3600 | struct sequence_stack *stack, *top = NULL; |
ab74c92f | 3601 | |
0a893c29 | 3602 | for (stack = seq_stack; stack; stack = stack->next) |
ab74c92f | 3603 | top = stack; |
3604 | ||
3605 | top->first = first_insn; | |
3606 | top->last = last_insn; | |
961819fb | 3607 | /* ??? Why don't we save seq_rtl_expr here? */ |
ab74c92f | 3608 | |
3609 | end_sequence (); | |
3610 | } | |
3611 | ||
15bbde2b | 3612 | /* After emitting to a sequence, restore previous saved state. |
3613 | ||
b49854c6 | 3614 | To get the contents of the sequence just made, you must call |
3615 | `gen_sequence' *before* calling here. | |
3616 | ||
3617 | If the compiler might have deferred popping arguments while | |
3618 | generating this sequence, and this sequence will not be immediately | |
3619 | inserted into the instruction stream, use do_pending_stack_adjust | |
3620 | before calling gen_sequence. That will ensure that the deferred | |
3621 | pops are inserted into this sequence, and not into some random | |
3622 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3623 | information about deferred popping of arguments. */ | |
15bbde2b | 3624 | |
3625 | void | |
3626 | end_sequence () | |
3627 | { | |
0a893c29 | 3628 | struct sequence_stack *tem = seq_stack; |
15bbde2b | 3629 | |
3630 | first_insn = tem->first; | |
3631 | last_insn = tem->last; | |
961819fb | 3632 | seq_rtl_expr = tem->sequence_rtl_expr; |
0a893c29 | 3633 | seq_stack = tem->next; |
15bbde2b | 3634 | |
1bfd55c5 | 3635 | free (tem); |
15bbde2b | 3636 | } |
3637 | ||
78147e84 | 3638 | /* This works like end_sequence, but records the old sequence in FIRST |
3639 | and LAST. */ | |
3640 | ||
3641 | void | |
3642 | end_full_sequence (first, last) | |
3643 | rtx *first, *last; | |
3644 | { | |
3645 | *first = first_insn; | |
3646 | *last = last_insn; | |
3647 | end_sequence(); | |
3648 | } | |
3649 | ||
15bbde2b | 3650 | /* Return 1 if currently emitting into a sequence. */ |
3651 | ||
3652 | int | |
3653 | in_sequence_p () | |
3654 | { | |
0a893c29 | 3655 | return seq_stack != 0; |
15bbde2b | 3656 | } |
3657 | ||
3658 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3659 | to the current sequence. | |
3660 | ||
3661 | This is how the gen_... function from a DEFINE_EXPAND | |
3662 | constructs the SEQUENCE that it returns. */ | |
3663 | ||
3664 | rtx | |
3665 | gen_sequence () | |
3666 | { | |
3667 | rtx result; | |
3668 | rtx tem; | |
15bbde2b | 3669 | int i; |
3670 | int len; | |
3671 | ||
3672 | /* Count the insns in the chain. */ | |
3673 | len = 0; | |
3674 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3675 | len++; | |
3676 | ||
88bbcaa6 | 3677 | /* If only one insn, return it rather than a SEQUENCE. |
15bbde2b | 3678 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
88bbcaa6 | 3679 | the case of an empty list.) |
3680 | We only return the pattern of an insn if its code is INSN and it | |
3681 | has no notes. This ensures that no information gets lost. */ | |
15bbde2b | 3682 | if (len == 1 |
447a9eb9 | 3683 | && ! RTX_FRAME_RELATED_P (first_insn) |
88bbcaa6 | 3684 | && GET_CODE (first_insn) == INSN |
3685 | /* Don't throw away any reg notes. */ | |
3686 | && REG_NOTES (first_insn) == 0) | |
d7c47c0e | 3687 | return PATTERN (first_insn); |
15bbde2b | 3688 | |
d7c47c0e | 3689 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
15bbde2b | 3690 | |
3691 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3692 | XVECEXP (result, 0, i) = tem; | |
3693 | ||
3694 | return result; | |
3695 | } | |
3696 | \f | |
02ebfa52 | 3697 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3698 | ||
3699 | void | |
0a893c29 | 3700 | init_virtual_regs (es) |
3701 | struct emit_status *es; | |
02ebfa52 | 3702 | { |
0a893c29 | 3703 | rtx *ptr = es->x_regno_reg_rtx; |
3704 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3705 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3706 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3707 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3708 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3709 | } | |
3710 | ||
3711 | void | |
3712 | clear_emit_caches () | |
3713 | { | |
3714 | int i; | |
3715 | ||
3716 | /* Clear the start_sequence/gen_sequence cache. */ | |
0a893c29 | 3717 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3718 | sequence_result[i] = 0; | |
3719 | free_insn = 0; | |
02ebfa52 | 3720 | } |
928d57e3 | 3721 | \f |
3722 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3723 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3724 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3725 | static int copy_insn_n_scratches; | |
3726 | ||
3727 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3728 | copied an ASM_OPERANDS. | |
3729 | In that case, it is the original input-operand vector. */ | |
3730 | static rtvec orig_asm_operands_vector; | |
3731 | ||
3732 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3733 | copied an ASM_OPERANDS. | |
3734 | In that case, it is the copied input-operand vector. */ | |
3735 | static rtvec copy_asm_operands_vector; | |
3736 | ||
3737 | /* Likewise for the constraints vector. */ | |
3738 | static rtvec orig_asm_constraints_vector; | |
3739 | static rtvec copy_asm_constraints_vector; | |
3740 | ||
3741 | /* Recursively create a new copy of an rtx for copy_insn. | |
3742 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3743 | ASM_OPERANDs properly. | |
3744 | Normally, this function is not used directly; use copy_insn as front end. | |
3745 | However, you could first copy an insn pattern with copy_insn and then use | |
3746 | this function afterwards to properly copy any REG_NOTEs containing | |
3747 | SCRATCHes. */ | |
3748 | ||
3749 | rtx | |
3750 | copy_insn_1 (orig) | |
3751 | register rtx orig; | |
3752 | { | |
3753 | register rtx copy; | |
3754 | register int i, j; | |
3755 | register RTX_CODE code; | |
90bf951c | 3756 | register const char *format_ptr; |
928d57e3 | 3757 | |
3758 | code = GET_CODE (orig); | |
3759 | ||
3760 | switch (code) | |
3761 | { | |
3762 | case REG: | |
3763 | case QUEUED: | |
3764 | case CONST_INT: | |
3765 | case CONST_DOUBLE: | |
3766 | case SYMBOL_REF: | |
3767 | case CODE_LABEL: | |
3768 | case PC: | |
3769 | case CC0: | |
3770 | case ADDRESSOF: | |
3771 | return orig; | |
3772 | ||
3773 | case SCRATCH: | |
3774 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3775 | if (copy_insn_scratch_in[i] == orig) | |
3776 | return copy_insn_scratch_out[i]; | |
3777 | break; | |
3778 | ||
3779 | case CONST: | |
3780 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
3781 | a LABEL_REF, it isn't sharable. */ | |
3782 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3783 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
3784 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
3785 | return orig; | |
3786 | break; | |
3787 | ||
3788 | /* A MEM with a constant address is not sharable. The problem is that | |
3789 | the constant address may need to be reloaded. If the mem is shared, | |
3790 | then reloading one copy of this mem will cause all copies to appear | |
3791 | to have been reloaded. */ | |
3792 | ||
3793 | default: | |
3794 | break; | |
3795 | } | |
3796 | ||
3797 | copy = rtx_alloc (code); | |
3798 | ||
3799 | /* Copy the various flags, and other information. We assume that | |
3800 | all fields need copying, and then clear the fields that should | |
3801 | not be copied. That is the sensible default behavior, and forces | |
3802 | us to explicitly document why we are *not* copying a flag. */ | |
3803 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
3804 | ||
3805 | /* We do not copy the USED flag, which is used as a mark bit during | |
3806 | walks over the RTL. */ | |
3807 | copy->used = 0; | |
3808 | ||
3809 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
3810 | if (GET_RTX_CLASS (code) == 'i') | |
3811 | { | |
3812 | copy->jump = 0; | |
3813 | copy->call = 0; | |
3814 | copy->frame_related = 0; | |
3815 | } | |
3816 | ||
3817 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
3818 | ||
3819 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
3820 | { | |
d925550d | 3821 | copy->fld[i] = orig->fld[i]; |
928d57e3 | 3822 | switch (*format_ptr++) |
3823 | { | |
3824 | case 'e': | |
928d57e3 | 3825 | if (XEXP (orig, i) != NULL) |
3826 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
3827 | break; | |
3828 | ||
928d57e3 | 3829 | case 'E': |
3830 | case 'V': | |
928d57e3 | 3831 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
3832 | XVEC (copy, i) = copy_asm_constraints_vector; | |
3833 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
3834 | XVEC (copy, i) = copy_asm_operands_vector; | |
3835 | else if (XVEC (orig, i) != NULL) | |
3836 | { | |
3837 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
3838 | for (j = 0; j < XVECLEN (copy, i); j++) | |
3839 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
3840 | } | |
3841 | break; | |
3842 | ||
928d57e3 | 3843 | case 't': |
928d57e3 | 3844 | case 'w': |
928d57e3 | 3845 | case 'i': |
928d57e3 | 3846 | case 's': |
3847 | case 'S': | |
d925550d | 3848 | case 'u': |
3849 | case '0': | |
3850 | /* These are left unchanged. */ | |
928d57e3 | 3851 | break; |
3852 | ||
3853 | default: | |
3854 | abort (); | |
3855 | } | |
3856 | } | |
3857 | ||
3858 | if (code == SCRATCH) | |
3859 | { | |
3860 | i = copy_insn_n_scratches++; | |
3861 | if (i >= MAX_RECOG_OPERANDS) | |
3862 | abort (); | |
3863 | copy_insn_scratch_in[i] = orig; | |
3864 | copy_insn_scratch_out[i] = copy; | |
3865 | } | |
3866 | else if (code == ASM_OPERANDS) | |
3867 | { | |
d91f2122 | 3868 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
3869 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
3870 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
3871 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
928d57e3 | 3872 | } |
3873 | ||
3874 | return copy; | |
3875 | } | |
3876 | ||
3877 | /* Create a new copy of an rtx. | |
3878 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3879 | ASM_OPERANDs properly. | |
3880 | INSN doesn't really have to be a full INSN; it could be just the | |
3881 | pattern. */ | |
3882 | rtx | |
3883 | copy_insn (insn) | |
3884 | rtx insn; | |
3885 | { | |
3886 | copy_insn_n_scratches = 0; | |
3887 | orig_asm_operands_vector = 0; | |
3888 | orig_asm_constraints_vector = 0; | |
3889 | copy_asm_operands_vector = 0; | |
3890 | copy_asm_constraints_vector = 0; | |
3891 | return copy_insn_1 (insn); | |
3892 | } | |
02ebfa52 | 3893 | |
15bbde2b | 3894 | /* Initialize data structures and variables in this file |
3895 | before generating rtl for each function. */ | |
3896 | ||
3897 | void | |
3898 | init_emit () | |
3899 | { | |
08513b52 | 3900 | struct function *f = cfun; |
15bbde2b | 3901 | |
0a893c29 | 3902 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
15bbde2b | 3903 | first_insn = NULL; |
3904 | last_insn = NULL; | |
961819fb | 3905 | seq_rtl_expr = NULL; |
15bbde2b | 3906 | cur_insn_uid = 1; |
3907 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
3908 | last_linenum = 0; | |
3909 | last_filename = 0; | |
3910 | first_label_num = label_num; | |
3911 | last_label_num = 0; | |
0a893c29 | 3912 | seq_stack = NULL; |
15bbde2b | 3913 | |
0a893c29 | 3914 | clear_emit_caches (); |
15bbde2b | 3915 | |
3916 | /* Init the tables that describe all the pseudo regs. */ | |
3917 | ||
0a893c29 | 3918 | f->emit->regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101; |
15bbde2b | 3919 | |
0a893c29 | 3920 | f->emit->regno_pointer_flag |
1bfd55c5 | 3921 | = (char *) xcalloc (f->emit->regno_pointer_flag_length, sizeof (char)); |
15bbde2b | 3922 | |
0a893c29 | 3923 | f->emit->regno_pointer_align |
4491f79f | 3924 | = (unsigned char *) xcalloc (f->emit->regno_pointer_flag_length, |
3925 | sizeof (unsigned char)); | |
d4c332ff | 3926 | |
15bbde2b | 3927 | regno_reg_rtx |
1bfd55c5 | 3928 | = (rtx *) xcalloc (f->emit->regno_pointer_flag_length * sizeof (rtx), |
3929 | sizeof (rtx)); | |
15bbde2b | 3930 | |
3931 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
0a893c29 | 3932 | init_virtual_regs (f->emit); |
888e0d33 | 3933 | |
3934 | /* Indicate that the virtual registers and stack locations are | |
3935 | all pointers. */ | |
3936 | REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1; | |
3937 | REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1; | |
069b19ee | 3938 | REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1; |
888e0d33 | 3939 | REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1; |
3940 | ||
3941 | REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1; | |
3942 | REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1; | |
3943 | REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1; | |
3944 | REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1; | |
ec37ccb4 | 3945 | REGNO_POINTER_FLAG (VIRTUAL_CFA_REGNUM) = 1; |
89525da0 | 3946 | |
d4c332ff | 3947 | #ifdef STACK_BOUNDARY |
80909c64 | 3948 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
3949 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
3950 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
3951 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
3952 | ||
3953 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
3954 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
3955 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
3956 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
3957 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
d4c332ff | 3958 | #endif |
3959 | ||
89525da0 | 3960 | #ifdef INIT_EXPANDERS |
3961 | INIT_EXPANDERS; | |
3962 | #endif | |
15bbde2b | 3963 | } |
3964 | ||
a7b0c170 | 3965 | /* Mark SS for GC. */ |
3966 | ||
3967 | static void | |
3968 | mark_sequence_stack (ss) | |
3969 | struct sequence_stack *ss; | |
3970 | { | |
3971 | while (ss) | |
3972 | { | |
3973 | ggc_mark_rtx (ss->first); | |
961819fb | 3974 | ggc_mark_tree (ss->sequence_rtl_expr); |
a7b0c170 | 3975 | ss = ss->next; |
3976 | } | |
3977 | } | |
3978 | ||
3979 | /* Mark ES for GC. */ | |
3980 | ||
3981 | void | |
3c3bb268 | 3982 | mark_emit_status (es) |
a7b0c170 | 3983 | struct emit_status *es; |
3984 | { | |
3985 | rtx *r; | |
3986 | int i; | |
3987 | ||
3988 | if (es == 0) | |
3989 | return; | |
3990 | ||
3991 | for (i = es->regno_pointer_flag_length, r = es->x_regno_reg_rtx; | |
3992 | i > 0; --i, ++r) | |
3993 | ggc_mark_rtx (*r); | |
3994 | ||
3995 | mark_sequence_stack (es->sequence_stack); | |
961819fb | 3996 | ggc_mark_tree (es->sequence_rtl_expr); |
a7b0c170 | 3997 | ggc_mark_rtx (es->x_first_insn); |
3998 | } | |
3999 | ||
15bbde2b | 4000 | /* Create some permanent unique rtl objects shared between all functions. |
4001 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
4002 | ||
4003 | void | |
4004 | init_emit_once (line_numbers) | |
4005 | int line_numbers; | |
4006 | { | |
4007 | int i; | |
4008 | enum machine_mode mode; | |
9e042f31 | 4009 | enum machine_mode double_mode; |
15bbde2b | 4010 | |
4011 | no_line_numbers = ! line_numbers; | |
4012 | ||
71d7daa2 | 4013 | /* Compute the word and byte modes. */ |
4014 | ||
4015 | byte_mode = VOIDmode; | |
4016 | word_mode = VOIDmode; | |
4017 | double_mode = VOIDmode; | |
4018 | ||
4019 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4020 | mode = GET_MODE_WIDER_MODE (mode)) | |
4021 | { | |
4022 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
4023 | && byte_mode == VOIDmode) | |
4024 | byte_mode = mode; | |
4025 | ||
4026 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
4027 | && word_mode == VOIDmode) | |
4028 | word_mode = mode; | |
4029 | } | |
4030 | ||
71d7daa2 | 4031 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; |
4032 | mode = GET_MODE_WIDER_MODE (mode)) | |
4033 | { | |
4034 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
4035 | && double_mode == VOIDmode) | |
4036 | double_mode = mode; | |
4037 | } | |
4038 | ||
4039 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
4040 | ||
57c097d5 | 4041 | /* Assign register numbers to the globally defined register rtx. |
4042 | This must be done at runtime because the register number field | |
4043 | is in a union and some compilers can't initialize unions. */ | |
4044 | ||
4045 | pc_rtx = gen_rtx (PC, VOIDmode); | |
4046 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
4047 | stack_pointer_rtx = gen_rtx_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
4048 | frame_pointer_rtx = gen_rtx_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
4049 | if (hard_frame_pointer_rtx == 0) | |
4050 | hard_frame_pointer_rtx = gen_rtx_raw_REG (Pmode, | |
4051 | HARD_FRAME_POINTER_REGNUM); | |
4052 | if (arg_pointer_rtx == 0) | |
4053 | arg_pointer_rtx = gen_rtx_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
4054 | virtual_incoming_args_rtx = | |
4055 | gen_rtx_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
4056 | virtual_stack_vars_rtx = | |
4057 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
4058 | virtual_stack_dynamic_rtx = | |
4059 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
4060 | virtual_outgoing_args_rtx = | |
4061 | gen_rtx_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
4062 | virtual_cfa_rtx = gen_rtx_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
4063 | ||
4064 | /* These rtx must be roots if GC is enabled. */ | |
d7c47c0e | 4065 | ggc_add_rtx_root (global_rtl, GR_MAX); |
57c097d5 | 4066 | |
57c097d5 | 4067 | #ifdef INIT_EXPANDERS |
4068 | /* This is to initialize save_machine_status and restore_machine_status before | |
4069 | the first call to push_function_context_to. This is needed by the Chill | |
4070 | front end which calls push_function_context_to before the first cal to | |
4071 | init_function_start. */ | |
4072 | INIT_EXPANDERS; | |
4073 | #endif | |
4074 | ||
15bbde2b | 4075 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
4076 | ||
7014838c | 4077 | /* Don't use gen_rtx here since gen_rtx in this case |
4078 | tries to use these variables. */ | |
15bbde2b | 4079 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
57c097d5 | 4080 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
4081 | gen_rtx_raw_CONST_INT (VOIDmode, i); | |
d7c47c0e | 4082 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); |
15bbde2b | 4083 | |
1a60f06a | 4084 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
4085 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
57c097d5 | 4086 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
1a60f06a | 4087 | else |
3ad7bb1c | 4088 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
15bbde2b | 4089 | |
9e042f31 | 4090 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
4091 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
4092 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
4093 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
15bbde2b | 4094 | |
4095 | for (i = 0; i <= 2; i++) | |
4096 | { | |
4097 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4098 | mode = GET_MODE_WIDER_MODE (mode)) | |
4099 | { | |
4100 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4101 | union real_extract u; | |
4102 | ||
748e6d74 | 4103 | bzero ((char *) &u, sizeof u); /* Zero any holes in a structure. */ |
15bbde2b | 4104 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4105 | ||
748e6d74 | 4106 | bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u); |
15bbde2b | 4107 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
791ceafe | 4108 | CONST_DOUBLE_CHAIN (tem) = NULL_RTX; |
15bbde2b | 4109 | PUT_MODE (tem, mode); |
4110 | ||
4111 | const_tiny_rtx[i][(int) mode] = tem; | |
4112 | } | |
4113 | ||
b572011e | 4114 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
15bbde2b | 4115 | |
4116 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4117 | mode = GET_MODE_WIDER_MODE (mode)) | |
b572011e | 4118 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
7540dcc4 | 4119 | |
4120 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4121 | mode != VOIDmode; | |
4122 | mode = GET_MODE_WIDER_MODE (mode)) | |
4123 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
15bbde2b | 4124 | } |
4125 | ||
e2fbcc74 | 4126 | for (mode = CCmode; mode < MAX_MACHINE_MODE; ++mode) |
4127 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
4128 | const_tiny_rtx[0][(int) mode] = const0_rtx; | |
15bbde2b | 4129 | |
065336b4 | 4130 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
4131 | if (STORE_FLAG_VALUE == 1) | |
4132 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
4133 | ||
3098b2d3 | 4134 | /* For bounded pointers, `&const_tiny_rtx[0][0]' is not the same as |
4135 | `(rtx *) const_tiny_rtx'. The former has bounds that only cover | |
4136 | `const_tiny_rtx[0]', whereas the latter has bounds that cover all. */ | |
4137 | ggc_add_rtx_root ((rtx *) const_tiny_rtx, sizeof const_tiny_rtx / sizeof (rtx)); | |
c788feb1 | 4138 | ggc_add_rtx_root (&const_true_rtx, 1); |
f4bffa58 | 4139 | |
4140 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4141 | return_address_pointer_rtx | |
4142 | = gen_rtx_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
4143 | #endif | |
4144 | ||
4145 | #ifdef STRUCT_VALUE | |
4146 | struct_value_rtx = STRUCT_VALUE; | |
4147 | #else | |
4148 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4149 | #endif | |
4150 | ||
4151 | #ifdef STRUCT_VALUE_INCOMING | |
4152 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4153 | #else | |
4154 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4155 | struct_value_incoming_rtx | |
4156 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4157 | #else | |
4158 | struct_value_incoming_rtx = struct_value_rtx; | |
4159 | #endif | |
4160 | #endif | |
4161 | ||
4162 | #ifdef STATIC_CHAIN_REGNUM | |
4163 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4164 | ||
4165 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4166 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4167 | static_chain_incoming_rtx | |
4168 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4169 | else | |
4170 | #endif | |
4171 | static_chain_incoming_rtx = static_chain_rtx; | |
4172 | #endif | |
4173 | ||
4174 | #ifdef STATIC_CHAIN | |
4175 | static_chain_rtx = STATIC_CHAIN; | |
4176 | ||
4177 | #ifdef STATIC_CHAIN_INCOMING | |
4178 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4179 | #else | |
4180 | static_chain_incoming_rtx = static_chain_rtx; | |
4181 | #endif | |
4182 | #endif | |
4183 | ||
4184 | #ifdef PIC_OFFSET_TABLE_REGNUM | |
4185 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
4186 | #endif | |
4187 | ||
521dd524 | 4188 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4189 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4190 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4191 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4192 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4193 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
73f5c1e3 | 4194 | |
4195 | /* Initialize the CONST_INT hash table. */ | |
7f2875d3 | 4196 | const_int_htab = htab_create (37, const_int_htab_hash, |
4197 | const_int_htab_eq, NULL); | |
73f5c1e3 | 4198 | ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab), |
4199 | rtx_htab_mark); | |
15bbde2b | 4200 | } |
ac6c481d | 4201 | \f |
4202 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4203 | switch / case handling in stmt.c to give proper line numbers in | |
4204 | warnings about unreachable code. */ | |
4205 | ||
4206 | int | |
4207 | force_line_numbers () | |
4208 | { | |
4209 | int old = no_line_numbers; | |
4210 | ||
4211 | no_line_numbers = 0; | |
4212 | if (old) | |
4213 | force_next_line_note (); | |
4214 | return old; | |
4215 | } | |
4216 | ||
4217 | void | |
4218 | restore_line_number_status (old_value) | |
4219 | int old_value; | |
4220 | { | |
4221 | no_line_numbers = old_value; | |
4222 | } |