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Commit | Line | Data |
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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
09efeca1 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
b6f65e3c | 4 | Free Software Foundation, Inc. |
23b2ce53 | 5 | |
1322177d | 6 | This file is part of GCC. |
23b2ce53 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
23b2ce53 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
23b2ce53 RS |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
f822fcf7 KH |
25 | This file contains support functions for creating rtl expressions |
26 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
27 | |
28 | The patterns of the insns are created by machine-dependent | |
29 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
30 | the machine description. These routines make the individual rtx's |
31 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
32 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
33 | dependent is the kind of rtx's they make and what arguments they |
34 | use. */ | |
23b2ce53 RS |
35 | |
36 | #include "config.h" | |
670ee920 | 37 | #include "system.h" |
4977bab6 ZW |
38 | #include "coretypes.h" |
39 | #include "tm.h" | |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
325217ed | 53 | #include "fixed-value.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
e1772ac0 | 57 | #include "debug.h" |
d23c55c2 | 58 | #include "langhooks.h" |
ef330312 | 59 | #include "tree-pass.h" |
6fb5fa3c | 60 | #include "df.h" |
ca695ac9 | 61 | |
1d445e9e ILT |
62 | /* Commonly used modes. */ |
63 | ||
0f41302f MS |
64 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
65 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 66 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 67 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 68 | |
bd60bab2 JH |
69 | /* Datastructures maintained for currently processed function in RTL form. */ |
70 | ||
3e029763 | 71 | struct rtl_data x_rtl; |
bd60bab2 JH |
72 | |
73 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
74 | Allocated in parallel with regno_pointer_align. | |
75 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal | |
76 | with length attribute nested in top level structures. */ | |
77 | ||
78 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
79 | |
80 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
81 | in the entire compilation a unique label number. */ | |
82 | ||
044b4de3 | 83 | static GTY(()) int label_num = 1; |
23b2ce53 | 84 | |
23b2ce53 RS |
85 | /* Nonzero means do not generate NOTEs for source line numbers. */ |
86 | ||
87 | static int no_line_numbers; | |
88 | ||
89 | /* Commonly used rtx's, so that we only need space for one copy. | |
90 | These are initialized once for the entire compilation. | |
5692c7bc ZW |
91 | All of these are unique; no other rtx-object will be equal to any |
92 | of these. */ | |
23b2ce53 | 93 | |
5da077de | 94 | rtx global_rtl[GR_MAX]; |
23b2ce53 | 95 | |
6cde4876 JL |
96 | /* Commonly used RTL for hard registers. These objects are not necessarily |
97 | unique, so we allocate them separately from global_rtl. They are | |
98 | initialized once per compilation unit, then copied into regno_reg_rtx | |
99 | at the beginning of each function. */ | |
100 | static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
101 | ||
23b2ce53 RS |
102 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
103 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
104 | record a copy of const[012]_rtx. */ | |
105 | ||
106 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
107 | ||
68d75312 JC |
108 | rtx const_true_rtx; |
109 | ||
23b2ce53 RS |
110 | REAL_VALUE_TYPE dconst0; |
111 | REAL_VALUE_TYPE dconst1; | |
112 | REAL_VALUE_TYPE dconst2; | |
113 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 114 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 115 | |
325217ed CF |
116 | /* Record fixed-point constant 0 and 1. */ |
117 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
118 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
119 | ||
23b2ce53 RS |
120 | /* All references to the following fixed hard registers go through |
121 | these unique rtl objects. On machines where the frame-pointer and | |
122 | arg-pointer are the same register, they use the same unique object. | |
123 | ||
124 | After register allocation, other rtl objects which used to be pseudo-regs | |
125 | may be clobbered to refer to the frame-pointer register. | |
126 | But references that were originally to the frame-pointer can be | |
127 | distinguished from the others because they contain frame_pointer_rtx. | |
128 | ||
ac6f08b0 DE |
129 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
130 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
750c9258 | 131 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
ac6f08b0 DE |
132 | register elimination hard_frame_pointer_rtx should always be used. |
133 | On machines where the two registers are same (most) then these are the | |
134 | same. | |
135 | ||
23b2ce53 RS |
136 | In an inline procedure, the stack and frame pointer rtxs may not be |
137 | used for anything else. */ | |
23b2ce53 RS |
138 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ |
139 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
140 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
141 | ||
a4417a86 JW |
142 | /* This is used to implement __builtin_return_address for some machines. |
143 | See for instance the MIPS port. */ | |
144 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
145 | ||
23b2ce53 RS |
146 | /* We make one copy of (const_int C) where C is in |
147 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
148 | to save space during the compilation and simplify comparisons of | |
149 | integers. */ | |
150 | ||
5da077de | 151 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 152 | |
c13e8210 MM |
153 | /* A hash table storing CONST_INTs whose absolute value is greater |
154 | than MAX_SAVED_CONST_INT. */ | |
155 | ||
e2500fed GK |
156 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
157 | htab_t const_int_htab; | |
c13e8210 | 158 | |
173b24b9 | 159 | /* A hash table storing memory attribute structures. */ |
e2500fed GK |
160 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
161 | htab_t mem_attrs_htab; | |
173b24b9 | 162 | |
a560d4d4 JH |
163 | /* A hash table storing register attribute structures. */ |
164 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
165 | htab_t reg_attrs_htab; | |
166 | ||
5692c7bc | 167 | /* A hash table storing all CONST_DOUBLEs. */ |
e2500fed GK |
168 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
169 | htab_t const_double_htab; | |
5692c7bc | 170 | |
091a3ac7 CF |
171 | /* A hash table storing all CONST_FIXEDs. */ |
172 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) | |
173 | htab_t const_fixed_htab; | |
174 | ||
3e029763 JH |
175 | #define first_insn (crtl->emit.x_first_insn) |
176 | #define last_insn (crtl->emit.x_last_insn) | |
177 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) | |
178 | #define last_location (crtl->emit.x_last_location) | |
179 | #define first_label_num (crtl->emit.x_first_label_num) | |
23b2ce53 | 180 | |
502b8322 | 181 | static rtx make_call_insn_raw (rtx); |
502b8322 | 182 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); |
5eb2a9f2 | 183 | static void set_used_decls (tree); |
502b8322 AJ |
184 | static void mark_label_nuses (rtx); |
185 | static hashval_t const_int_htab_hash (const void *); | |
186 | static int const_int_htab_eq (const void *, const void *); | |
187 | static hashval_t const_double_htab_hash (const void *); | |
188 | static int const_double_htab_eq (const void *, const void *); | |
189 | static rtx lookup_const_double (rtx); | |
091a3ac7 CF |
190 | static hashval_t const_fixed_htab_hash (const void *); |
191 | static int const_fixed_htab_eq (const void *, const void *); | |
192 | static rtx lookup_const_fixed (rtx); | |
502b8322 AJ |
193 | static hashval_t mem_attrs_htab_hash (const void *); |
194 | static int mem_attrs_htab_eq (const void *, const void *); | |
4862826d | 195 | static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int, |
502b8322 AJ |
196 | enum machine_mode); |
197 | static hashval_t reg_attrs_htab_hash (const void *); | |
198 | static int reg_attrs_htab_eq (const void *, const void *); | |
199 | static reg_attrs *get_reg_attrs (tree, int); | |
200 | static tree component_ref_for_mem_expr (tree); | |
a73b091d | 201 | static rtx gen_const_vector (enum machine_mode, int); |
32b32b16 | 202 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 203 | |
6b24c259 JH |
204 | /* Probability of the conditional branch currently proceeded by try_split. |
205 | Set to -1 otherwise. */ | |
206 | int split_branch_probability = -1; | |
ca695ac9 | 207 | \f |
c13e8210 MM |
208 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
209 | ||
210 | static hashval_t | |
502b8322 | 211 | const_int_htab_hash (const void *x) |
c13e8210 | 212 | { |
f7d504c2 | 213 | return (hashval_t) INTVAL ((const_rtx) x); |
c13e8210 MM |
214 | } |
215 | ||
cc2902df | 216 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
217 | CONST_INT) is the same as that given by Y (which is really a |
218 | HOST_WIDE_INT *). */ | |
219 | ||
220 | static int | |
502b8322 | 221 | const_int_htab_eq (const void *x, const void *y) |
c13e8210 | 222 | { |
f7d504c2 | 223 | return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y)); |
5692c7bc ZW |
224 | } |
225 | ||
226 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
227 | static hashval_t | |
502b8322 | 228 | const_double_htab_hash (const void *x) |
5692c7bc | 229 | { |
f7d504c2 | 230 | const_rtx const value = (const_rtx) x; |
46b33600 | 231 | hashval_t h; |
5692c7bc | 232 | |
46b33600 RH |
233 | if (GET_MODE (value) == VOIDmode) |
234 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
235 | else | |
fe352c29 | 236 | { |
15c812e3 | 237 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
238 | /* MODE is used in the comparison, so it should be in the hash. */ |
239 | h ^= GET_MODE (value); | |
240 | } | |
5692c7bc ZW |
241 | return h; |
242 | } | |
243 | ||
cc2902df | 244 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc ZW |
245 | is the same as that represented by Y (really a ...) */ |
246 | static int | |
502b8322 | 247 | const_double_htab_eq (const void *x, const void *y) |
5692c7bc | 248 | { |
f7d504c2 | 249 | const_rtx const a = (const_rtx)x, b = (const_rtx)y; |
5692c7bc ZW |
250 | |
251 | if (GET_MODE (a) != GET_MODE (b)) | |
252 | return 0; | |
8580f7a0 RH |
253 | if (GET_MODE (a) == VOIDmode) |
254 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
255 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
256 | else | |
257 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
258 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
259 | } |
260 | ||
091a3ac7 CF |
261 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
262 | ||
263 | static hashval_t | |
264 | const_fixed_htab_hash (const void *x) | |
265 | { | |
3101faab | 266 | const_rtx const value = (const_rtx) x; |
091a3ac7 CF |
267 | hashval_t h; |
268 | ||
269 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
270 | /* MODE is used in the comparison, so it should be in the hash. */ | |
271 | h ^= GET_MODE (value); | |
272 | return h; | |
273 | } | |
274 | ||
275 | /* Returns nonzero if the value represented by X (really a ...) | |
276 | is the same as that represented by Y (really a ...). */ | |
277 | ||
278 | static int | |
279 | const_fixed_htab_eq (const void *x, const void *y) | |
280 | { | |
3101faab | 281 | const_rtx const a = (const_rtx) x, b = (const_rtx) y; |
091a3ac7 CF |
282 | |
283 | if (GET_MODE (a) != GET_MODE (b)) | |
284 | return 0; | |
285 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
286 | } | |
287 | ||
173b24b9 RK |
288 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
289 | ||
290 | static hashval_t | |
502b8322 | 291 | mem_attrs_htab_hash (const void *x) |
173b24b9 | 292 | { |
f7d504c2 | 293 | const mem_attrs *const p = (const mem_attrs *) x; |
173b24b9 RK |
294 | |
295 | return (p->alias ^ (p->align * 1000) | |
296 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) | |
297 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
78b76d08 | 298 | ^ (size_t) iterative_hash_expr (p->expr, 0)); |
173b24b9 RK |
299 | } |
300 | ||
cc2902df | 301 | /* Returns nonzero if the value represented by X (which is really a |
173b24b9 RK |
302 | mem_attrs *) is the same as that given by Y (which is also really a |
303 | mem_attrs *). */ | |
c13e8210 MM |
304 | |
305 | static int | |
502b8322 | 306 | mem_attrs_htab_eq (const void *x, const void *y) |
c13e8210 | 307 | { |
741ac903 KG |
308 | const mem_attrs *const p = (const mem_attrs *) x; |
309 | const mem_attrs *const q = (const mem_attrs *) y; | |
173b24b9 | 310 | |
78b76d08 SB |
311 | return (p->alias == q->alias && p->offset == q->offset |
312 | && p->size == q->size && p->align == q->align | |
313 | && (p->expr == q->expr | |
314 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
315 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
316 | } |
317 | ||
173b24b9 | 318 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
10b76d73 RK |
319 | one identical to it is not already in the table. We are doing this for |
320 | MEM of mode MODE. */ | |
173b24b9 RK |
321 | |
322 | static mem_attrs * | |
4862826d | 323 | get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size, |
502b8322 | 324 | unsigned int align, enum machine_mode mode) |
173b24b9 RK |
325 | { |
326 | mem_attrs attrs; | |
327 | void **slot; | |
328 | ||
bb056a77 OH |
329 | /* If everything is the default, we can just return zero. |
330 | This must match what the corresponding MEM_* macros return when the | |
331 | field is not present. */ | |
998d7deb | 332 | if (alias == 0 && expr == 0 && offset == 0 |
10b76d73 RK |
333 | && (size == 0 |
334 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
bb056a77 OH |
335 | && (STRICT_ALIGNMENT && mode != BLKmode |
336 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
10b76d73 RK |
337 | return 0; |
338 | ||
173b24b9 | 339 | attrs.alias = alias; |
998d7deb | 340 | attrs.expr = expr; |
173b24b9 RK |
341 | attrs.offset = offset; |
342 | attrs.size = size; | |
343 | attrs.align = align; | |
344 | ||
345 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
346 | if (*slot == 0) | |
347 | { | |
348 | *slot = ggc_alloc (sizeof (mem_attrs)); | |
349 | memcpy (*slot, &attrs, sizeof (mem_attrs)); | |
350 | } | |
351 | ||
1b4572a8 | 352 | return (mem_attrs *) *slot; |
c13e8210 MM |
353 | } |
354 | ||
a560d4d4 JH |
355 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
356 | ||
357 | static hashval_t | |
502b8322 | 358 | reg_attrs_htab_hash (const void *x) |
a560d4d4 | 359 | { |
741ac903 | 360 | const reg_attrs *const p = (const reg_attrs *) x; |
a560d4d4 JH |
361 | |
362 | return ((p->offset * 1000) ^ (long) p->decl); | |
363 | } | |
364 | ||
6356f892 | 365 | /* Returns nonzero if the value represented by X (which is really a |
a560d4d4 JH |
366 | reg_attrs *) is the same as that given by Y (which is also really a |
367 | reg_attrs *). */ | |
368 | ||
369 | static int | |
502b8322 | 370 | reg_attrs_htab_eq (const void *x, const void *y) |
a560d4d4 | 371 | { |
741ac903 KG |
372 | const reg_attrs *const p = (const reg_attrs *) x; |
373 | const reg_attrs *const q = (const reg_attrs *) y; | |
a560d4d4 JH |
374 | |
375 | return (p->decl == q->decl && p->offset == q->offset); | |
376 | } | |
377 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
378 | one identical to it is not already in the table. We are doing this for | |
379 | MEM of mode MODE. */ | |
380 | ||
381 | static reg_attrs * | |
502b8322 | 382 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
383 | { |
384 | reg_attrs attrs; | |
385 | void **slot; | |
386 | ||
387 | /* If everything is the default, we can just return zero. */ | |
388 | if (decl == 0 && offset == 0) | |
389 | return 0; | |
390 | ||
391 | attrs.decl = decl; | |
392 | attrs.offset = offset; | |
393 | ||
394 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
395 | if (*slot == 0) | |
396 | { | |
397 | *slot = ggc_alloc (sizeof (reg_attrs)); | |
398 | memcpy (*slot, &attrs, sizeof (reg_attrs)); | |
399 | } | |
400 | ||
1b4572a8 | 401 | return (reg_attrs *) *slot; |
a560d4d4 JH |
402 | } |
403 | ||
6fb5fa3c DB |
404 | |
405 | #if !HAVE_blockage | |
406 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule | |
407 | across this insn. */ | |
408 | ||
409 | rtx | |
410 | gen_blockage (void) | |
411 | { | |
412 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
413 | MEM_VOLATILE_P (x) = true; | |
414 | return x; | |
415 | } | |
416 | #endif | |
417 | ||
418 | ||
08394eef BS |
419 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
420 | don't attempt to share with the various global pieces of rtl (such as | |
421 | frame_pointer_rtx). */ | |
422 | ||
423 | rtx | |
502b8322 | 424 | gen_raw_REG (enum machine_mode mode, int regno) |
08394eef BS |
425 | { |
426 | rtx x = gen_rtx_raw_REG (mode, regno); | |
427 | ORIGINAL_REGNO (x) = regno; | |
428 | return x; | |
429 | } | |
430 | ||
c5c76735 JL |
431 | /* There are some RTL codes that require special attention; the generation |
432 | functions do the raw handling. If you add to this list, modify | |
433 | special_rtx in gengenrtl.c as well. */ | |
434 | ||
3b80f6ca | 435 | rtx |
502b8322 | 436 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca | 437 | { |
c13e8210 MM |
438 | void **slot; |
439 | ||
3b80f6ca | 440 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 441 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
442 | |
443 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
444 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
445 | return const_true_rtx; | |
446 | #endif | |
447 | ||
c13e8210 | 448 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
449 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
450 | (hashval_t) arg, INSERT); | |
29105cea | 451 | if (*slot == 0) |
1f8f4a0b | 452 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
453 | |
454 | return (rtx) *slot; | |
3b80f6ca RH |
455 | } |
456 | ||
2496c7bd | 457 | rtx |
502b8322 | 458 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2496c7bd LB |
459 | { |
460 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
461 | } | |
462 | ||
5692c7bc ZW |
463 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
464 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
465 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
466 | ||
467 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
468 | hash table. If so, return its counterpart; otherwise add it | |
469 | to the hash table and return it. */ | |
470 | static rtx | |
502b8322 | 471 | lookup_const_double (rtx real) |
5692c7bc ZW |
472 | { |
473 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
474 | if (*slot == 0) | |
475 | *slot = real; | |
476 | ||
477 | return (rtx) *slot; | |
478 | } | |
29105cea | 479 | |
5692c7bc ZW |
480 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
481 | VALUE in mode MODE. */ | |
0133b7d9 | 482 | rtx |
502b8322 | 483 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
0133b7d9 | 484 | { |
5692c7bc ZW |
485 | rtx real = rtx_alloc (CONST_DOUBLE); |
486 | PUT_MODE (real, mode); | |
487 | ||
9e254451 | 488 | real->u.rv = value; |
5692c7bc ZW |
489 | |
490 | return lookup_const_double (real); | |
491 | } | |
492 | ||
091a3ac7 CF |
493 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
494 | hash table. If so, return its counterpart; otherwise add it | |
495 | to the hash table and return it. */ | |
496 | ||
497 | static rtx | |
498 | lookup_const_fixed (rtx fixed) | |
499 | { | |
500 | void **slot = htab_find_slot (const_fixed_htab, fixed, INSERT); | |
501 | if (*slot == 0) | |
502 | *slot = fixed; | |
503 | ||
504 | return (rtx) *slot; | |
505 | } | |
506 | ||
507 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
508 | VALUE in mode MODE. */ | |
509 | ||
510 | rtx | |
511 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, enum machine_mode mode) | |
512 | { | |
513 | rtx fixed = rtx_alloc (CONST_FIXED); | |
514 | PUT_MODE (fixed, mode); | |
515 | ||
516 | fixed->u.fv = value; | |
517 | ||
518 | return lookup_const_fixed (fixed); | |
519 | } | |
520 | ||
5692c7bc ZW |
521 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
522 | of ints: I0 is the low-order word and I1 is the high-order word. | |
523 | Do not use this routine for non-integer modes; convert to | |
524 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
525 | ||
526 | rtx | |
502b8322 | 527 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
5692c7bc ZW |
528 | { |
529 | rtx value; | |
530 | unsigned int i; | |
531 | ||
65acccdd ZD |
532 | /* There are the following cases (note that there are no modes with |
533 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT): | |
534 | ||
535 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
536 | gen_int_mode. | |
537 | 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of | |
538 | the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only | |
539 | from copies of the sign bit, and sign of i0 and i1 are the same), then | |
540 | we return a CONST_INT for i0. | |
541 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ | |
5692c7bc ZW |
542 | if (mode != VOIDmode) |
543 | { | |
5b0264cb NS |
544 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
545 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
546 | /* We can get a 0 for an error mark. */ | |
547 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
548 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT); | |
5692c7bc | 549 | |
65acccdd ZD |
550 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
551 | return gen_int_mode (i0, mode); | |
552 | ||
553 | gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT); | |
5692c7bc ZW |
554 | } |
555 | ||
556 | /* If this integer fits in one word, return a CONST_INT. */ | |
557 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
558 | return GEN_INT (i0); | |
559 | ||
560 | /* We use VOIDmode for integers. */ | |
561 | value = rtx_alloc (CONST_DOUBLE); | |
562 | PUT_MODE (value, VOIDmode); | |
563 | ||
564 | CONST_DOUBLE_LOW (value) = i0; | |
565 | CONST_DOUBLE_HIGH (value) = i1; | |
566 | ||
567 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
568 | XWINT (value, i) = 0; | |
569 | ||
570 | return lookup_const_double (value); | |
0133b7d9 RH |
571 | } |
572 | ||
3b80f6ca | 573 | rtx |
502b8322 | 574 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3b80f6ca RH |
575 | { |
576 | /* In case the MD file explicitly references the frame pointer, have | |
577 | all such references point to the same frame pointer. This is | |
578 | used during frame pointer elimination to distinguish the explicit | |
579 | references to these registers from pseudos that happened to be | |
580 | assigned to them. | |
581 | ||
582 | If we have eliminated the frame pointer or arg pointer, we will | |
583 | be using it as a normal register, for example as a spill | |
584 | register. In such cases, we might be accessing it in a mode that | |
585 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
586 | ||
587 | Also don't do this when we are making new REGs in reload, since | |
588 | we don't want to get confused with the real pointers. */ | |
589 | ||
590 | if (mode == Pmode && !reload_in_progress) | |
591 | { | |
e10c79fe LB |
592 | if (regno == FRAME_POINTER_REGNUM |
593 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
594 | return frame_pointer_rtx; |
595 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e10c79fe LB |
596 | if (regno == HARD_FRAME_POINTER_REGNUM |
597 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
598 | return hard_frame_pointer_rtx; |
599 | #endif | |
600 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 601 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
602 | return arg_pointer_rtx; |
603 | #endif | |
604 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 605 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
606 | return return_address_pointer_rtx; |
607 | #endif | |
fc555370 | 608 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
2d67bd7b | 609 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 610 | return pic_offset_table_rtx; |
bcb33994 | 611 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
612 | return stack_pointer_rtx; |
613 | } | |
614 | ||
006a94b0 | 615 | #if 0 |
6cde4876 | 616 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
617 | an existing entry in that table to avoid useless generation of RTL. |
618 | ||
619 | This code is disabled for now until we can fix the various backends | |
620 | which depend on having non-shared hard registers in some cases. Long | |
621 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
622 | on the amount of useless RTL that gets generated. |
623 | ||
624 | We'll also need to fix some code that runs after reload that wants to | |
625 | set ORIGINAL_REGNO. */ | |
626 | ||
6cde4876 JL |
627 | if (cfun |
628 | && cfun->emit | |
629 | && regno_reg_rtx | |
630 | && regno < FIRST_PSEUDO_REGISTER | |
631 | && reg_raw_mode[regno] == mode) | |
632 | return regno_reg_rtx[regno]; | |
006a94b0 | 633 | #endif |
6cde4876 | 634 | |
08394eef | 635 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
636 | } |
637 | ||
41472af8 | 638 | rtx |
502b8322 | 639 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
41472af8 MM |
640 | { |
641 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
642 | ||
643 | /* This field is not cleared by the mere allocation of the rtx, so | |
644 | we clear it here. */ | |
173b24b9 | 645 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
646 | |
647 | return rt; | |
648 | } | |
ddef6bc7 | 649 | |
542a8afa RH |
650 | /* Generate a memory referring to non-trapping constant memory. */ |
651 | ||
652 | rtx | |
653 | gen_const_mem (enum machine_mode mode, rtx addr) | |
654 | { | |
655 | rtx mem = gen_rtx_MEM (mode, addr); | |
656 | MEM_READONLY_P (mem) = 1; | |
657 | MEM_NOTRAP_P (mem) = 1; | |
658 | return mem; | |
659 | } | |
660 | ||
bf877a76 R |
661 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
662 | save areas. */ | |
663 | ||
664 | rtx | |
665 | gen_frame_mem (enum machine_mode mode, rtx addr) | |
666 | { | |
667 | rtx mem = gen_rtx_MEM (mode, addr); | |
668 | MEM_NOTRAP_P (mem) = 1; | |
669 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
670 | return mem; | |
671 | } | |
672 | ||
673 | /* Generate a MEM referring to a temporary use of the stack, not part | |
674 | of the fixed stack frame. For example, something which is pushed | |
675 | by a target splitter. */ | |
676 | rtx | |
677 | gen_tmp_stack_mem (enum machine_mode mode, rtx addr) | |
678 | { | |
679 | rtx mem = gen_rtx_MEM (mode, addr); | |
680 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 681 | if (!cfun->calls_alloca) |
bf877a76 R |
682 | set_mem_alias_set (mem, get_frame_alias_set ()); |
683 | return mem; | |
684 | } | |
685 | ||
beb72684 RH |
686 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
687 | this construct would be valid, and false otherwise. */ | |
688 | ||
689 | bool | |
690 | validate_subreg (enum machine_mode omode, enum machine_mode imode, | |
ed7a4b4b | 691 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 692 | { |
beb72684 RH |
693 | unsigned int isize = GET_MODE_SIZE (imode); |
694 | unsigned int osize = GET_MODE_SIZE (omode); | |
695 | ||
696 | /* All subregs must be aligned. */ | |
697 | if (offset % osize != 0) | |
698 | return false; | |
699 | ||
700 | /* The subreg offset cannot be outside the inner object. */ | |
701 | if (offset >= isize) | |
702 | return false; | |
703 | ||
704 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
705 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
706 | Generally, backends are doing something sketchy but it'll take time to | |
707 | fix them all. */ | |
708 | if (omode == word_mode) | |
709 | ; | |
710 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
711 | is the culprit here, and not the backends. */ | |
712 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
713 | ; | |
714 | /* Allow component subregs of complex and vector. Though given the below | |
715 | extraction rules, it's not always clear what that means. */ | |
716 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
717 | && GET_MODE_INNER (imode) == omode) | |
718 | ; | |
719 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
720 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
721 | represent this. It's questionable if this ought to be represented at | |
722 | all -- why can't this all be hidden in post-reload splitters that make | |
723 | arbitrarily mode changes to the registers themselves. */ | |
724 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
725 | ; | |
726 | /* Subregs involving floating point modes are not allowed to | |
727 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
728 | (subreg:SI (reg:DF) 0) isn't. */ | |
729 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
730 | { | |
731 | if (isize != osize) | |
732 | return false; | |
733 | } | |
ddef6bc7 | 734 | |
beb72684 RH |
735 | /* Paradoxical subregs must have offset zero. */ |
736 | if (osize > isize) | |
737 | return offset == 0; | |
738 | ||
739 | /* This is a normal subreg. Verify that the offset is representable. */ | |
740 | ||
741 | /* For hard registers, we already have most of these rules collected in | |
742 | subreg_offset_representable_p. */ | |
743 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
744 | { | |
745 | unsigned int regno = REGNO (reg); | |
746 | ||
747 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
748 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
749 | && GET_MODE_INNER (imode) == omode) | |
750 | ; | |
751 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
752 | return false; | |
ddef6bc7 | 753 | #endif |
beb72684 RH |
754 | |
755 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
756 | } | |
757 | ||
758 | /* For pseudo registers, we want most of the same checks. Namely: | |
759 | If the register no larger than a word, the subreg must be lowpart. | |
760 | If the register is larger than a word, the subreg must be the lowpart | |
761 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
762 | Given that we've already checked mode/offset alignment, we only have | |
763 | to check subword subregs here. */ | |
764 | if (osize < UNITS_PER_WORD) | |
765 | { | |
766 | enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; | |
767 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); | |
768 | if (offset % UNITS_PER_WORD != low_off) | |
769 | return false; | |
770 | } | |
771 | return true; | |
772 | } | |
773 | ||
774 | rtx | |
775 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) | |
776 | { | |
777 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 778 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
779 | } |
780 | ||
173b24b9 RK |
781 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
782 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
783 | ||
ddef6bc7 | 784 | rtx |
502b8322 | 785 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
ddef6bc7 JJ |
786 | { |
787 | enum machine_mode inmode; | |
ddef6bc7 JJ |
788 | |
789 | inmode = GET_MODE (reg); | |
790 | if (inmode == VOIDmode) | |
791 | inmode = mode; | |
e0e08ac2 JH |
792 | return gen_rtx_SUBREG (mode, reg, |
793 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 794 | } |
c5c76735 | 795 | \f |
23b2ce53 | 796 | |
80379f51 PB |
797 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
798 | ||
23b2ce53 | 799 | rtvec |
e34d07f2 | 800 | gen_rtvec (int n, ...) |
23b2ce53 | 801 | { |
80379f51 PB |
802 | int i; |
803 | rtvec rt_val; | |
e34d07f2 | 804 | va_list p; |
23b2ce53 | 805 | |
e34d07f2 | 806 | va_start (p, n); |
23b2ce53 | 807 | |
80379f51 | 808 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 809 | if (n == 0) |
80379f51 | 810 | return NULL_RTVEC; |
23b2ce53 | 811 | |
80379f51 | 812 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 813 | |
23b2ce53 | 814 | for (i = 0; i < n; i++) |
80379f51 | 815 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 816 | |
e34d07f2 | 817 | va_end (p); |
80379f51 | 818 | return rt_val; |
23b2ce53 RS |
819 | } |
820 | ||
821 | rtvec | |
502b8322 | 822 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 823 | { |
b3694847 SS |
824 | int i; |
825 | rtvec rt_val; | |
23b2ce53 | 826 | |
80379f51 | 827 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 828 | if (n == 0) |
80379f51 | 829 | return NULL_RTVEC; |
23b2ce53 | 830 | |
80379f51 | 831 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
832 | |
833 | for (i = 0; i < n; i++) | |
8f985ec4 | 834 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
835 | |
836 | return rt_val; | |
837 | } | |
838 | \f | |
38ae7651 RS |
839 | /* Return the number of bytes between the start of an OUTER_MODE |
840 | in-memory value and the start of an INNER_MODE in-memory value, | |
841 | given that the former is a lowpart of the latter. It may be a | |
842 | paradoxical lowpart, in which case the offset will be negative | |
843 | on big-endian targets. */ | |
844 | ||
845 | int | |
846 | byte_lowpart_offset (enum machine_mode outer_mode, | |
847 | enum machine_mode inner_mode) | |
848 | { | |
849 | if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)) | |
850 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
851 | else | |
852 | return -subreg_lowpart_offset (inner_mode, outer_mode); | |
853 | } | |
854 | \f | |
23b2ce53 RS |
855 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
856 | This pseudo is assigned the next sequential register number. */ | |
857 | ||
858 | rtx | |
502b8322 | 859 | gen_reg_rtx (enum machine_mode mode) |
23b2ce53 | 860 | { |
b3694847 | 861 | rtx val; |
2e3f842f | 862 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 863 | |
f8335a4f | 864 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 865 | |
2e3f842f L |
866 | /* If a virtual register with bigger mode alignment is generated, |
867 | increase stack alignment estimation because it might be spilled | |
868 | to stack later. */ | |
869 | if (SUPPORTS_STACK_ALIGNMENT | |
870 | && crtl->stack_alignment_estimated < align | |
871 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
872 | { |
873 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
874 | if (crtl->stack_alignment_estimated < min_align) | |
875 | crtl->stack_alignment_estimated = min_align; | |
876 | } | |
2e3f842f | 877 | |
1b3d8f8a GK |
878 | if (generating_concat_p |
879 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
880 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
881 | { |
882 | /* For complex modes, don't make a single pseudo. | |
883 | Instead, make a CONCAT of two pseudos. | |
884 | This allows noncontiguous allocation of the real and imaginary parts, | |
885 | which makes much better code. Besides, allocating DCmode | |
886 | pseudos overstrains reload on some machines like the 386. */ | |
887 | rtx realpart, imagpart; | |
27e58a70 | 888 | enum machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
889 | |
890 | realpart = gen_reg_rtx (partmode); | |
891 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 892 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
893 | } |
894 | ||
a560d4d4 | 895 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 896 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 897 | |
3e029763 | 898 | if (reg_rtx_no == crtl->emit.regno_pointer_align_length) |
23b2ce53 | 899 | { |
3e029763 | 900 | int old_size = crtl->emit.regno_pointer_align_length; |
60564289 | 901 | char *tmp; |
0d4903b8 | 902 | rtx *new1; |
0d4903b8 | 903 | |
60564289 KG |
904 | tmp = XRESIZEVEC (char, crtl->emit.regno_pointer_align, old_size * 2); |
905 | memset (tmp + old_size, 0, old_size); | |
906 | crtl->emit.regno_pointer_align = (unsigned char *) tmp; | |
49ad7cfa | 907 | |
1b4572a8 | 908 | new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, old_size * 2); |
49ad7cfa | 909 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
910 | regno_reg_rtx = new1; |
911 | ||
3e029763 | 912 | crtl->emit.regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
913 | } |
914 | ||
08394eef | 915 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
916 | regno_reg_rtx[reg_rtx_no++] = val; |
917 | return val; | |
918 | } | |
919 | ||
38ae7651 RS |
920 | /* Update NEW with the same attributes as REG, but with OFFSET added |
921 | to the REG_OFFSET. */ | |
a560d4d4 | 922 | |
e53a16e7 | 923 | static void |
60564289 | 924 | update_reg_offset (rtx new_rtx, rtx reg, int offset) |
a560d4d4 | 925 | { |
60564289 | 926 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 927 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
928 | } |
929 | ||
38ae7651 RS |
930 | /* Generate a register with same attributes as REG, but with OFFSET |
931 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
932 | |
933 | rtx | |
934 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, | |
935 | int offset) | |
936 | { | |
60564289 | 937 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 938 | |
60564289 KG |
939 | update_reg_offset (new_rtx, reg, offset); |
940 | return new_rtx; | |
e53a16e7 ILT |
941 | } |
942 | ||
943 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 944 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
945 | |
946 | rtx | |
947 | gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset) | |
948 | { | |
60564289 | 949 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 950 | |
60564289 KG |
951 | update_reg_offset (new_rtx, reg, offset); |
952 | return new_rtx; | |
a560d4d4 JH |
953 | } |
954 | ||
38ae7651 RS |
955 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
956 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
957 | |
958 | void | |
38ae7651 | 959 | adjust_reg_mode (rtx reg, enum machine_mode mode) |
a560d4d4 | 960 | { |
38ae7651 RS |
961 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
962 | PUT_MODE (reg, mode); | |
963 | } | |
964 | ||
965 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
966 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
967 | ||
968 | void | |
969 | set_reg_attrs_from_value (rtx reg, rtx x) | |
970 | { | |
971 | int offset; | |
972 | ||
923ba36f JJ |
973 | /* Hard registers can be reused for multiple purposes within the same |
974 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
975 | on them is wrong. */ | |
976 | if (HARD_REGISTER_P (reg)) | |
977 | return; | |
978 | ||
38ae7651 | 979 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
980 | if (MEM_P (x)) |
981 | { | |
481683e1 | 982 | if (MEM_OFFSET (x) && CONST_INT_P (MEM_OFFSET (x))) |
46b71b03 PB |
983 | REG_ATTRS (reg) |
984 | = get_reg_attrs (MEM_EXPR (x), INTVAL (MEM_OFFSET (x)) + offset); | |
985 | if (MEM_POINTER (x)) | |
0a317111 | 986 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
987 | } |
988 | else if (REG_P (x)) | |
989 | { | |
990 | if (REG_ATTRS (x)) | |
991 | update_reg_offset (reg, x, offset); | |
992 | if (REG_POINTER (x)) | |
993 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); | |
994 | } | |
995 | } | |
996 | ||
997 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
998 | and attributes from X. */ | |
999 | ||
1000 | rtx | |
1001 | gen_reg_rtx_and_attrs (rtx x) | |
1002 | { | |
1003 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1004 | set_reg_attrs_from_value (reg, x); | |
1005 | return reg; | |
a560d4d4 JH |
1006 | } |
1007 | ||
9d18e06b JZ |
1008 | /* Set the register attributes for registers contained in PARM_RTX. |
1009 | Use needed values from memory attributes of MEM. */ | |
1010 | ||
1011 | void | |
502b8322 | 1012 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1013 | { |
f8cfc6aa | 1014 | if (REG_P (parm_rtx)) |
38ae7651 | 1015 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1016 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1017 | { | |
1018 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1019 | parameter goes both on the stack and in registers. */ | |
1020 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1021 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1022 | { | |
1023 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1024 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1025 | REG_ATTRS (XEXP (x, 0)) |
1026 | = get_reg_attrs (MEM_EXPR (mem), | |
1027 | INTVAL (XEXP (x, 1))); | |
1028 | } | |
1029 | } | |
1030 | } | |
1031 | ||
38ae7651 RS |
1032 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1033 | decl T. */ | |
a560d4d4 | 1034 | |
4e3825db | 1035 | void |
38ae7651 RS |
1036 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1037 | { | |
1038 | if (GET_CODE (x) == SUBREG) | |
fbe6ec81 | 1039 | { |
38ae7651 RS |
1040 | gcc_assert (subreg_lowpart_p (x)); |
1041 | x = SUBREG_REG (x); | |
fbe6ec81 | 1042 | } |
f8cfc6aa | 1043 | if (REG_P (x)) |
38ae7651 RS |
1044 | REG_ATTRS (x) |
1045 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
726612d2 | 1046 | DECL_MODE (t))); |
a560d4d4 JH |
1047 | if (GET_CODE (x) == CONCAT) |
1048 | { | |
1049 | if (REG_P (XEXP (x, 0))) | |
1050 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1051 | if (REG_P (XEXP (x, 1))) | |
1052 | REG_ATTRS (XEXP (x, 1)) | |
1053 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1054 | } | |
1055 | if (GET_CODE (x) == PARALLEL) | |
1056 | { | |
d4afac5b JZ |
1057 | int i, start; |
1058 | ||
1059 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1060 | both on the stack and in registers. */ | |
1061 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1062 | start = 0; | |
1063 | else | |
1064 | start = 1; | |
1065 | ||
1066 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1067 | { |
1068 | rtx y = XVECEXP (x, 0, i); | |
1069 | if (REG_P (XEXP (y, 0))) | |
1070 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1071 | } | |
1072 | } | |
1073 | } | |
1074 | ||
38ae7651 RS |
1075 | /* Assign the RTX X to declaration T. */ |
1076 | ||
1077 | void | |
1078 | set_decl_rtl (tree t, rtx x) | |
1079 | { | |
1080 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1081 | if (x) | |
1082 | set_reg_attrs_for_decl_rtl (t, x); | |
1083 | } | |
1084 | ||
5141868d RS |
1085 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1086 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1087 | |
1088 | void | |
5141868d | 1089 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1090 | { |
1091 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1092 | if (x && !by_reference_p) |
38ae7651 RS |
1093 | set_reg_attrs_for_decl_rtl (t, x); |
1094 | } | |
1095 | ||
754fdcca RK |
1096 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1097 | ||
1098 | void | |
502b8322 | 1099 | mark_user_reg (rtx reg) |
754fdcca RK |
1100 | { |
1101 | if (GET_CODE (reg) == CONCAT) | |
1102 | { | |
1103 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1104 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1105 | } | |
754fdcca | 1106 | else |
5b0264cb NS |
1107 | { |
1108 | gcc_assert (REG_P (reg)); | |
1109 | REG_USERVAR_P (reg) = 1; | |
1110 | } | |
754fdcca RK |
1111 | } |
1112 | ||
86fe05e0 RK |
1113 | /* Identify REG as a probable pointer register and show its alignment |
1114 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1115 | |
1116 | void | |
502b8322 | 1117 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1118 | { |
3502dc9c | 1119 | if (! REG_POINTER (reg)) |
00995e78 | 1120 | { |
3502dc9c | 1121 | REG_POINTER (reg) = 1; |
86fe05e0 | 1122 | |
00995e78 RE |
1123 | if (align) |
1124 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1125 | } | |
1126 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1127 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1128 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1129 | } |
1130 | ||
1131 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1132 | ||
1133 | int | |
502b8322 | 1134 | max_reg_num (void) |
23b2ce53 RS |
1135 | { |
1136 | return reg_rtx_no; | |
1137 | } | |
1138 | ||
1139 | /* Return 1 + the largest label number used so far in the current function. */ | |
1140 | ||
1141 | int | |
502b8322 | 1142 | max_label_num (void) |
23b2ce53 | 1143 | { |
23b2ce53 RS |
1144 | return label_num; |
1145 | } | |
1146 | ||
1147 | /* Return first label number used in this function (if any were used). */ | |
1148 | ||
1149 | int | |
502b8322 | 1150 | get_first_label_num (void) |
23b2ce53 RS |
1151 | { |
1152 | return first_label_num; | |
1153 | } | |
6de9cd9a DN |
1154 | |
1155 | /* If the rtx for label was created during the expansion of a nested | |
1156 | function, then first_label_num won't include this label number. | |
fa10beec | 1157 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1158 | |
1159 | void | |
1160 | maybe_set_first_label_num (rtx x) | |
1161 | { | |
1162 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1163 | first_label_num = CODE_LABEL_NUMBER (x); | |
1164 | } | |
23b2ce53 RS |
1165 | \f |
1166 | /* Return a value representing some low-order bits of X, where the number | |
1167 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1168 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1169 | representation is returned. |
1170 | ||
1171 | This function handles the cases in common between gen_lowpart, below, | |
1172 | and two variants in cse.c and combine.c. These are the cases that can | |
1173 | be safely handled at all points in the compilation. | |
1174 | ||
1175 | If this is not a case we can handle, return 0. */ | |
1176 | ||
1177 | rtx | |
502b8322 | 1178 | gen_lowpart_common (enum machine_mode mode, rtx x) |
23b2ce53 | 1179 | { |
ddef6bc7 | 1180 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1181 | int xsize; |
ddef6bc7 | 1182 | int offset = 0; |
550d1387 GK |
1183 | enum machine_mode innermode; |
1184 | ||
1185 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1186 | so we have to make one up. Yuk. */ | |
1187 | innermode = GET_MODE (x); | |
481683e1 | 1188 | if (CONST_INT_P (x) |
db487452 | 1189 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) |
550d1387 GK |
1190 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1191 | else if (innermode == VOIDmode) | |
1192 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0); | |
1193 | ||
1194 | xsize = GET_MODE_SIZE (innermode); | |
1195 | ||
5b0264cb | 1196 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1197 | |
550d1387 | 1198 | if (innermode == mode) |
23b2ce53 RS |
1199 | return x; |
1200 | ||
1201 | /* MODE must occupy no more words than the mode of X. */ | |
550d1387 GK |
1202 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1203 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
23b2ce53 RS |
1204 | return 0; |
1205 | ||
53501a19 | 1206 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
3d8bf70f | 1207 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
53501a19 BS |
1208 | return 0; |
1209 | ||
550d1387 | 1210 | offset = subreg_lowpart_offset (mode, innermode); |
23b2ce53 RS |
1211 | |
1212 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1213 | && (GET_MODE_CLASS (mode) == MODE_INT |
1214 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1215 | { |
1216 | /* If we are getting the low-order part of something that has been | |
1217 | sign- or zero-extended, we can either just use the object being | |
1218 | extended or make a narrower extension. If we want an even smaller | |
1219 | piece than the size of the object being extended, call ourselves | |
1220 | recursively. | |
1221 | ||
1222 | This case is used mostly by combine and cse. */ | |
1223 | ||
1224 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1225 | return XEXP (x, 0); | |
550d1387 | 1226 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
23b2ce53 | 1227 | return gen_lowpart_common (mode, XEXP (x, 0)); |
550d1387 | 1228 | else if (msize < xsize) |
3b80f6ca | 1229 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1230 | } |
f8cfc6aa | 1231 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
550d1387 | 1232 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
481683e1 | 1233 | || GET_CODE (x) == CONST_DOUBLE || CONST_INT_P (x)) |
550d1387 | 1234 | return simplify_gen_subreg (mode, x, innermode, offset); |
8aada4ad | 1235 | |
23b2ce53 RS |
1236 | /* Otherwise, we can't do this. */ |
1237 | return 0; | |
1238 | } | |
1239 | \f | |
ccba022b | 1240 | rtx |
502b8322 | 1241 | gen_highpart (enum machine_mode mode, rtx x) |
ccba022b | 1242 | { |
ddef6bc7 | 1243 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1244 | rtx result; |
ddef6bc7 | 1245 | |
ccba022b RS |
1246 | /* This case loses if X is a subreg. To catch bugs early, |
1247 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1248 | gcc_assert (msize <= UNITS_PER_WORD |
1249 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1250 | |
e0e08ac2 JH |
1251 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1252 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb NS |
1253 | gcc_assert (result); |
1254 | ||
09482e0d JW |
1255 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1256 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1257 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1258 | if (MEM_P (result)) |
1259 | { | |
1260 | result = validize_mem (result); | |
1261 | gcc_assert (result); | |
1262 | } | |
1263 | ||
e0e08ac2 JH |
1264 | return result; |
1265 | } | |
5222e470 | 1266 | |
26d249eb | 1267 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1268 | be VOIDmode constant. */ |
1269 | rtx | |
502b8322 | 1270 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
5222e470 JH |
1271 | { |
1272 | if (GET_MODE (exp) != VOIDmode) | |
1273 | { | |
5b0264cb | 1274 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1275 | return gen_highpart (outermode, exp); |
1276 | } | |
1277 | return simplify_gen_subreg (outermode, exp, innermode, | |
1278 | subreg_highpart_offset (outermode, innermode)); | |
1279 | } | |
68252e27 | 1280 | |
38ae7651 | 1281 | /* Return the SUBREG_BYTE for an OUTERMODE lowpart of an INNERMODE value. */ |
8698cce3 | 1282 | |
e0e08ac2 | 1283 | unsigned int |
502b8322 | 1284 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
e0e08ac2 JH |
1285 | { |
1286 | unsigned int offset = 0; | |
1287 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1288 | |
e0e08ac2 | 1289 | if (difference > 0) |
ccba022b | 1290 | { |
e0e08ac2 JH |
1291 | if (WORDS_BIG_ENDIAN) |
1292 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1293 | if (BYTES_BIG_ENDIAN) | |
1294 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1295 | } |
ddef6bc7 | 1296 | |
e0e08ac2 | 1297 | return offset; |
ccba022b | 1298 | } |
eea50aa0 | 1299 | |
e0e08ac2 JH |
1300 | /* Return offset in bytes to get OUTERMODE high part |
1301 | of the value in mode INNERMODE stored in memory in target format. */ | |
1302 | unsigned int | |
502b8322 | 1303 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
eea50aa0 JH |
1304 | { |
1305 | unsigned int offset = 0; | |
1306 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1307 | ||
5b0264cb | 1308 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
e0e08ac2 | 1309 | |
eea50aa0 JH |
1310 | if (difference > 0) |
1311 | { | |
e0e08ac2 | 1312 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1313 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1314 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1315 | offset += difference % UNITS_PER_WORD; |
1316 | } | |
1317 | ||
e0e08ac2 | 1318 | return offset; |
eea50aa0 | 1319 | } |
ccba022b | 1320 | |
23b2ce53 RS |
1321 | /* Return 1 iff X, assumed to be a SUBREG, |
1322 | refers to the least significant part of its containing reg. | |
1323 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1324 | ||
1325 | int | |
fa233e34 | 1326 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1327 | { |
1328 | if (GET_CODE (x) != SUBREG) | |
1329 | return 1; | |
a3a03040 RK |
1330 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1331 | return 0; | |
23b2ce53 | 1332 | |
e0e08ac2 JH |
1333 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1334 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1335 | } |
1336 | \f | |
ddef6bc7 JJ |
1337 | /* Return subword OFFSET of operand OP. |
1338 | The word number, OFFSET, is interpreted as the word number starting | |
1339 | at the low-order address. OFFSET 0 is the low-order word if not | |
1340 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1341 | ||
1342 | If we cannot extract the required word, we return zero. Otherwise, | |
1343 | an rtx corresponding to the requested word will be returned. | |
1344 | ||
1345 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1346 | reload has completed, a valid address will always be returned. After | |
1347 | reload, if a valid address cannot be returned, we return zero. | |
1348 | ||
1349 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1350 | it is the responsibility of the caller. | |
1351 | ||
1352 | MODE is the mode of OP in case it is a CONST_INT. | |
1353 | ||
1354 | ??? This is still rather broken for some cases. The problem for the | |
1355 | moment is that all callers of this thing provide no 'goal mode' to | |
1356 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1357 | in a word based SUBREG world. |
1358 | Now use of this function can be deprecated by simplify_subreg in most | |
1359 | cases. | |
1360 | */ | |
ddef6bc7 JJ |
1361 | |
1362 | rtx | |
502b8322 | 1363 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
ddef6bc7 JJ |
1364 | { |
1365 | if (mode == VOIDmode) | |
1366 | mode = GET_MODE (op); | |
1367 | ||
5b0264cb | 1368 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1369 | |
30f7a378 | 1370 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1371 | if (mode != BLKmode |
1372 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1373 | return 0; | |
1374 | ||
30f7a378 | 1375 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1376 | if (mode != BLKmode |
1377 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1378 | return const0_rtx; | |
1379 | ||
ddef6bc7 | 1380 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1381 | if (MEM_P (op)) |
ddef6bc7 | 1382 | { |
60564289 | 1383 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1384 | |
f1ec5147 | 1385 | if (! validate_address) |
60564289 | 1386 | return new_rtx; |
f1ec5147 RK |
1387 | |
1388 | else if (reload_completed) | |
ddef6bc7 | 1389 | { |
60564289 | 1390 | if (! strict_memory_address_p (word_mode, XEXP (new_rtx, 0))) |
f1ec5147 | 1391 | return 0; |
ddef6bc7 | 1392 | } |
f1ec5147 | 1393 | else |
60564289 | 1394 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1395 | } |
1396 | ||
0631e0bf JH |
1397 | /* Rest can be handled by simplify_subreg. */ |
1398 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1399 | } |
1400 | ||
535a42b1 NS |
1401 | /* Similar to `operand_subword', but never return 0. If we can't |
1402 | extract the required subword, put OP into a register and try again. | |
1403 | The second attempt must succeed. We always validate the address in | |
1404 | this case. | |
23b2ce53 RS |
1405 | |
1406 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1407 | ||
1408 | rtx | |
502b8322 | 1409 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
23b2ce53 | 1410 | { |
ddef6bc7 | 1411 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1412 | |
1413 | if (result) | |
1414 | return result; | |
1415 | ||
1416 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1417 | { |
1418 | /* If this is a register which can not be accessed by words, copy it | |
1419 | to a pseudo register. */ | |
f8cfc6aa | 1420 | if (REG_P (op)) |
77e6b0eb JC |
1421 | op = copy_to_reg (op); |
1422 | else | |
1423 | op = force_reg (mode, op); | |
1424 | } | |
23b2ce53 | 1425 | |
ddef6bc7 | 1426 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1427 | gcc_assert (result); |
23b2ce53 RS |
1428 | |
1429 | return result; | |
1430 | } | |
1431 | \f | |
998d7deb RH |
1432 | /* Within a MEM_EXPR, we care about either (1) a component ref of a decl, |
1433 | or (2) a component ref of something variable. Represent the later with | |
1434 | a NULL expression. */ | |
1435 | ||
1436 | static tree | |
502b8322 | 1437 | component_ref_for_mem_expr (tree ref) |
998d7deb RH |
1438 | { |
1439 | tree inner = TREE_OPERAND (ref, 0); | |
1440 | ||
1441 | if (TREE_CODE (inner) == COMPONENT_REF) | |
1442 | inner = component_ref_for_mem_expr (inner); | |
c56e3582 RK |
1443 | else |
1444 | { | |
c56e3582 | 1445 | /* Now remove any conversions: they don't change what the underlying |
6fce44af | 1446 | object is. Likewise for SAVE_EXPR. */ |
1043771b | 1447 | while (CONVERT_EXPR_P (inner) |
c56e3582 | 1448 | || TREE_CODE (inner) == VIEW_CONVERT_EXPR |
6fce44af RK |
1449 | || TREE_CODE (inner) == SAVE_EXPR) |
1450 | inner = TREE_OPERAND (inner, 0); | |
c56e3582 RK |
1451 | |
1452 | if (! DECL_P (inner)) | |
1453 | inner = NULL_TREE; | |
1454 | } | |
998d7deb | 1455 | |
4e3825db MM |
1456 | if (inner == TREE_OPERAND (ref, 0) |
1457 | /* Don't leak SSA-names in the third operand. */ | |
1458 | && (!TREE_OPERAND (ref, 2) | |
1459 | || TREE_CODE (TREE_OPERAND (ref, 2)) != SSA_NAME)) | |
998d7deb RH |
1460 | return ref; |
1461 | else | |
3244e67d RS |
1462 | return build3 (COMPONENT_REF, TREE_TYPE (ref), inner, |
1463 | TREE_OPERAND (ref, 1), NULL_TREE); | |
998d7deb | 1464 | } |
173b24b9 | 1465 | |
2b3493c8 AK |
1466 | /* Returns 1 if both MEM_EXPR can be considered equal |
1467 | and 0 otherwise. */ | |
1468 | ||
1469 | int | |
4f588890 | 1470 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1471 | { |
1472 | if (expr1 == expr2) | |
1473 | return 1; | |
1474 | ||
1475 | if (! expr1 || ! expr2) | |
1476 | return 0; | |
1477 | ||
1478 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1479 | return 0; | |
1480 | ||
1481 | if (TREE_CODE (expr1) == COMPONENT_REF) | |
1482 | return | |
1483 | mem_expr_equal_p (TREE_OPERAND (expr1, 0), | |
1484 | TREE_OPERAND (expr2, 0)) | |
1485 | && mem_expr_equal_p (TREE_OPERAND (expr1, 1), /* field decl */ | |
1486 | TREE_OPERAND (expr2, 1)); | |
1487 | ||
1b096a0a | 1488 | if (INDIRECT_REF_P (expr1)) |
2b3493c8 AK |
1489 | return mem_expr_equal_p (TREE_OPERAND (expr1, 0), |
1490 | TREE_OPERAND (expr2, 0)); | |
2b3493c8 | 1491 | |
5b0264cb | 1492 | /* ARRAY_REFs, ARRAY_RANGE_REFs and BIT_FIELD_REFs should already |
2b3493c8 | 1493 | have been resolved here. */ |
5b0264cb NS |
1494 | gcc_assert (DECL_P (expr1)); |
1495 | ||
1496 | /* Decls with different pointers can't be equal. */ | |
1497 | return 0; | |
2b3493c8 AK |
1498 | } |
1499 | ||
805903b5 JJ |
1500 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1501 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1502 | -1 if not known. */ | |
1503 | ||
1504 | int | |
d9223014 | 1505 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1506 | { |
1507 | tree expr; | |
1508 | unsigned HOST_WIDE_INT offset; | |
1509 | ||
1510 | /* This function can't use | |
1511 | if (!MEM_EXPR (mem) || !MEM_OFFSET (mem) | |
1512 | || !CONST_INT_P (MEM_OFFSET (mem)) | |
1513 | || (get_object_alignment (MEM_EXPR (mem), MEM_ALIGN (mem), align) | |
1514 | < align)) | |
1515 | return -1; | |
1516 | else | |
1517 | return (- INTVAL (MEM_OFFSET (mem))) & (align / BITS_PER_UNIT - 1); | |
1518 | for two reasons: | |
1519 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1520 | for <variable>. get_inner_reference doesn't handle it and | |
1521 | even if it did, the alignment in that case needs to be determined | |
1522 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1523 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1524 | isn't sufficiently aligned, the object it is in might be. */ | |
1525 | gcc_assert (MEM_P (mem)); | |
1526 | expr = MEM_EXPR (mem); | |
1527 | if (expr == NULL_TREE | |
1528 | || MEM_OFFSET (mem) == NULL_RTX | |
1529 | || !CONST_INT_P (MEM_OFFSET (mem))) | |
1530 | return -1; | |
1531 | ||
1532 | offset = INTVAL (MEM_OFFSET (mem)); | |
1533 | if (DECL_P (expr)) | |
1534 | { | |
1535 | if (DECL_ALIGN (expr) < align) | |
1536 | return -1; | |
1537 | } | |
1538 | else if (INDIRECT_REF_P (expr)) | |
1539 | { | |
1540 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1541 | return -1; | |
1542 | } | |
1543 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1544 | { | |
1545 | while (1) | |
1546 | { | |
1547 | tree inner = TREE_OPERAND (expr, 0); | |
1548 | tree field = TREE_OPERAND (expr, 1); | |
1549 | tree byte_offset = component_ref_field_offset (expr); | |
1550 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1551 | ||
1552 | if (!byte_offset | |
1553 | || !host_integerp (byte_offset, 1) | |
1554 | || !host_integerp (bit_offset, 1)) | |
1555 | return -1; | |
1556 | ||
1557 | offset += tree_low_cst (byte_offset, 1); | |
1558 | offset += tree_low_cst (bit_offset, 1) / BITS_PER_UNIT; | |
1559 | ||
1560 | if (inner == NULL_TREE) | |
1561 | { | |
1562 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1563 | < (unsigned int) align) | |
1564 | return -1; | |
1565 | break; | |
1566 | } | |
1567 | else if (DECL_P (inner)) | |
1568 | { | |
1569 | if (DECL_ALIGN (inner) < align) | |
1570 | return -1; | |
1571 | break; | |
1572 | } | |
1573 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1574 | return -1; | |
1575 | expr = inner; | |
1576 | } | |
1577 | } | |
1578 | else | |
1579 | return -1; | |
1580 | ||
1581 | return offset & ((align / BITS_PER_UNIT) - 1); | |
1582 | } | |
1583 | ||
6926c713 | 1584 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1585 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1586 | if we are making a new object of this type. BITPOS is nonzero if |
1587 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1588 | |
1589 | void | |
502b8322 AJ |
1590 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1591 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1592 | { |
4862826d | 1593 | alias_set_type alias = MEM_ALIAS_SET (ref); |
998d7deb | 1594 | tree expr = MEM_EXPR (ref); |
8ac61af7 RK |
1595 | rtx offset = MEM_OFFSET (ref); |
1596 | rtx size = MEM_SIZE (ref); | |
1597 | unsigned int align = MEM_ALIGN (ref); | |
6f1087be | 1598 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 RK |
1599 | tree type; |
1600 | ||
1601 | /* It can happen that type_for_mode was given a mode for which there | |
1602 | is no language-level type. In which case it returns NULL, which | |
1603 | we can see here. */ | |
1604 | if (t == NULL_TREE) | |
1605 | return; | |
1606 | ||
1607 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1608 | if (type == error_mark_node) |
1609 | return; | |
173b24b9 | 1610 | |
173b24b9 RK |
1611 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1612 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1613 | info. Callers should not set DECL_RTL until after the call to | |
1614 | set_mem_attributes. */ | |
5b0264cb | 1615 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1616 | |
738cc472 | 1617 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 RK |
1618 | front-end routine) and use it. */ |
1619 | alias = get_alias_set (t); | |
173b24b9 | 1620 | |
a5e9c810 | 1621 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
07cb6e8c JM |
1622 | MEM_IN_STRUCT_P (ref) |
1623 | = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE; | |
f8ad8d7c | 1624 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1625 | |
8ac61af7 RK |
1626 | /* If we are making an object of this type, or if this is a DECL, we know |
1627 | that it is a scalar if the type is not an aggregate. */ | |
07cb6e8c JM |
1628 | if ((objectp || DECL_P (t)) |
1629 | && ! AGGREGATE_TYPE_P (type) | |
1630 | && TREE_CODE (type) != COMPLEX_TYPE) | |
173b24b9 RK |
1631 | MEM_SCALAR_P (ref) = 1; |
1632 | ||
c3d32120 RK |
1633 | /* We can set the alignment from the type if we are making an object, |
1634 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
7ccf35ed DN |
1635 | if (objectp || TREE_CODE (t) == INDIRECT_REF |
1636 | || TREE_CODE (t) == ALIGN_INDIRECT_REF | |
1637 | || TYPE_ALIGN_OK (type)) | |
c3d32120 | 1638 | align = MAX (align, TYPE_ALIGN (type)); |
7ccf35ed DN |
1639 | else |
1640 | if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF) | |
1641 | { | |
1642 | if (integer_zerop (TREE_OPERAND (t, 1))) | |
1643 | /* We don't know anything about the alignment. */ | |
1644 | align = BITS_PER_UNIT; | |
1645 | else | |
1646 | align = tree_low_cst (TREE_OPERAND (t, 1), 1); | |
1647 | } | |
40c0668b | 1648 | |
738cc472 RK |
1649 | /* If the size is known, we can set that. */ |
1650 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
8ac61af7 | 1651 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
738cc472 | 1652 | |
80965c18 RK |
1653 | /* If T is not a type, we may be able to deduce some more information about |
1654 | the expression. */ | |
1655 | if (! TYPE_P (t)) | |
8ac61af7 | 1656 | { |
8476af98 | 1657 | tree base; |
df96b059 | 1658 | bool align_computed = false; |
389fdba0 | 1659 | |
8ac61af7 RK |
1660 | if (TREE_THIS_VOLATILE (t)) |
1661 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1662 | |
c56e3582 RK |
1663 | /* Now remove any conversions: they don't change what the underlying |
1664 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 1665 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
1666 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
1667 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1668 | t = TREE_OPERAND (t, 0); |
1669 | ||
8476af98 RH |
1670 | /* We may look through structure-like accesses for the purposes of |
1671 | examining TREE_THIS_NOTRAP, but not array-like accesses. */ | |
1672 | base = t; | |
1673 | while (TREE_CODE (base) == COMPONENT_REF | |
1674 | || TREE_CODE (base) == REALPART_EXPR | |
1675 | || TREE_CODE (base) == IMAGPART_EXPR | |
1676 | || TREE_CODE (base) == BIT_FIELD_REF) | |
1677 | base = TREE_OPERAND (base, 0); | |
1678 | ||
1679 | if (DECL_P (base)) | |
1680 | { | |
1681 | if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS)) | |
1682 | MEM_NOTRAP_P (ref) = !DECL_WEAK (base); | |
1683 | else | |
1684 | MEM_NOTRAP_P (ref) = 1; | |
1685 | } | |
1686 | else | |
1687 | MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base); | |
1688 | ||
1689 | base = get_base_address (base); | |
1690 | if (base && DECL_P (base) | |
1691 | && TREE_READONLY (base) | |
1692 | && (TREE_STATIC (base) || DECL_EXTERNAL (base))) | |
1693 | { | |
1694 | tree base_type = TREE_TYPE (base); | |
1695 | gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type)) | |
1696 | || DECL_ARTIFICIAL (base)); | |
1697 | MEM_READONLY_P (ref) = 1; | |
1698 | } | |
1699 | ||
2039d7aa RH |
1700 | /* If this expression uses it's parent's alias set, mark it such |
1701 | that we won't change it. */ | |
1702 | if (component_uses_parent_alias_set (t)) | |
10b76d73 RK |
1703 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1704 | ||
8ac61af7 RK |
1705 | /* If this is a decl, set the attributes of the MEM from it. */ |
1706 | if (DECL_P (t)) | |
1707 | { | |
998d7deb RH |
1708 | expr = t; |
1709 | offset = const0_rtx; | |
6f1087be | 1710 | apply_bitpos = bitpos; |
8ac61af7 RK |
1711 | size = (DECL_SIZE_UNIT (t) |
1712 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1713 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
68252e27 | 1714 | align = DECL_ALIGN (t); |
df96b059 | 1715 | align_computed = true; |
8ac61af7 RK |
1716 | } |
1717 | ||
40c0668b | 1718 | /* If this is a constant, we know the alignment. */ |
6615c446 | 1719 | else if (CONSTANT_CLASS_P (t)) |
9ddfb1a7 RK |
1720 | { |
1721 | align = TYPE_ALIGN (type); | |
1722 | #ifdef CONSTANT_ALIGNMENT | |
1723 | align = CONSTANT_ALIGNMENT (t, align); | |
1724 | #endif | |
df96b059 | 1725 | align_computed = true; |
9ddfb1a7 | 1726 | } |
998d7deb RH |
1727 | |
1728 | /* If this is a field reference and not a bit-field, record it. */ | |
fa10beec | 1729 | /* ??? There is some information that can be gleaned from bit-fields, |
998d7deb RH |
1730 | such as the word offset in the structure that might be modified. |
1731 | But skip it for now. */ | |
1732 | else if (TREE_CODE (t) == COMPONENT_REF | |
1733 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1734 | { | |
1735 | expr = component_ref_for_mem_expr (t); | |
1736 | offset = const0_rtx; | |
6f1087be | 1737 | apply_bitpos = bitpos; |
998d7deb RH |
1738 | /* ??? Any reason the field size would be different than |
1739 | the size we got from the type? */ | |
1740 | } | |
1741 | ||
1742 | /* If this is an array reference, look for an outer field reference. */ | |
1743 | else if (TREE_CODE (t) == ARRAY_REF) | |
1744 | { | |
1745 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1746 | /* We can't modify t, because we use it at the end of the |
1747 | function. */ | |
1748 | tree t2 = t; | |
998d7deb RH |
1749 | |
1750 | do | |
1751 | { | |
1b1838b6 | 1752 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1753 | tree low_bound = array_ref_low_bound (t2); |
1754 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1755 | |
1756 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1757 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1758 | index, then convert to sizetype and multiply by the size of |
1759 | the array element. */ | |
1760 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1761 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1762 | index, low_bound); | |
2567406a | 1763 | |
44de5aeb | 1764 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1765 | size_binop (MULT_EXPR, |
1766 | fold_convert (sizetype, | |
1767 | index), | |
44de5aeb RK |
1768 | unit_size), |
1769 | off_tree); | |
1b1838b6 | 1770 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1771 | } |
1b1838b6 | 1772 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1773 | |
1b1838b6 | 1774 | if (DECL_P (t2)) |
c67a1cf6 | 1775 | { |
1b1838b6 | 1776 | expr = t2; |
40cb04f1 | 1777 | offset = NULL; |
c67a1cf6 | 1778 | if (host_integerp (off_tree, 1)) |
40cb04f1 RH |
1779 | { |
1780 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1781 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1b1838b6 | 1782 | align = DECL_ALIGN (t2); |
fc555370 | 1783 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
40cb04f1 | 1784 | align = aoff; |
df96b059 | 1785 | align_computed = true; |
40cb04f1 | 1786 | offset = GEN_INT (ioff); |
6f1087be | 1787 | apply_bitpos = bitpos; |
40cb04f1 | 1788 | } |
c67a1cf6 | 1789 | } |
1b1838b6 | 1790 | else if (TREE_CODE (t2) == COMPONENT_REF) |
998d7deb | 1791 | { |
1b1838b6 | 1792 | expr = component_ref_for_mem_expr (t2); |
998d7deb | 1793 | if (host_integerp (off_tree, 1)) |
6f1087be RH |
1794 | { |
1795 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1796 | apply_bitpos = bitpos; | |
1797 | } | |
998d7deb RH |
1798 | /* ??? Any reason the field size would be different than |
1799 | the size we got from the type? */ | |
1800 | } | |
c67a1cf6 | 1801 | else if (flag_argument_noalias > 1 |
1b096a0a | 1802 | && (INDIRECT_REF_P (t2)) |
1b1838b6 | 1803 | && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL) |
c67a1cf6 | 1804 | { |
1b1838b6 | 1805 | expr = t2; |
c67a1cf6 RH |
1806 | offset = NULL; |
1807 | } | |
1808 | } | |
1809 | ||
1810 | /* If this is a Fortran indirect argument reference, record the | |
1811 | parameter decl. */ | |
1812 | else if (flag_argument_noalias > 1 | |
1b096a0a | 1813 | && (INDIRECT_REF_P (t)) |
c67a1cf6 RH |
1814 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) |
1815 | { | |
1816 | expr = t; | |
1817 | offset = NULL; | |
998d7deb | 1818 | } |
df96b059 JJ |
1819 | |
1820 | if (!align_computed && !INDIRECT_REF_P (t)) | |
1821 | { | |
1822 | unsigned int obj_align | |
1823 | = get_object_alignment (t, align, BIGGEST_ALIGNMENT); | |
1824 | align = MAX (align, obj_align); | |
1825 | } | |
8ac61af7 RK |
1826 | } |
1827 | ||
15c812e3 | 1828 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
1829 | bit position offset. Similarly, increase the size of the accessed |
1830 | object to contain the negative offset. */ | |
6f1087be | 1831 | if (apply_bitpos) |
8c317c5f RH |
1832 | { |
1833 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
1834 | if (size) | |
1835 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
1836 | } | |
6f1087be | 1837 | |
7ccf35ed DN |
1838 | if (TREE_CODE (t) == ALIGN_INDIRECT_REF) |
1839 | { | |
fa10beec | 1840 | /* Force EXPR and OFFSET to NULL, since we don't know exactly what |
7ccf35ed DN |
1841 | we're overlapping. */ |
1842 | offset = NULL; | |
1843 | expr = NULL; | |
1844 | } | |
1845 | ||
8ac61af7 | 1846 | /* Now set the attributes we computed above. */ |
10b76d73 | 1847 | MEM_ATTRS (ref) |
998d7deb | 1848 | = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref)); |
8ac61af7 RK |
1849 | |
1850 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
1851 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
738cc472 RK |
1852 | return; |
1853 | ||
8ac61af7 RK |
1854 | /* If it is a reference into an aggregate, this is part of an aggregate. |
1855 | Otherwise we don't know. */ | |
173b24b9 RK |
1856 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
1857 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
1858 | || TREE_CODE (t) == BIT_FIELD_REF) | |
1859 | MEM_IN_STRUCT_P (ref) = 1; | |
1860 | } | |
1861 | ||
6f1087be | 1862 | void |
502b8322 | 1863 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
1864 | { |
1865 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
1866 | } | |
1867 | ||
173b24b9 RK |
1868 | /* Set the alias set of MEM to SET. */ |
1869 | ||
1870 | void | |
4862826d | 1871 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 1872 | { |
68252e27 | 1873 | #ifdef ENABLE_CHECKING |
173b24b9 | 1874 | /* If the new and old alias sets don't conflict, something is wrong. */ |
5b0264cb | 1875 | gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
173b24b9 RK |
1876 | #endif |
1877 | ||
998d7deb | 1878 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
10b76d73 RK |
1879 | MEM_SIZE (mem), MEM_ALIGN (mem), |
1880 | GET_MODE (mem)); | |
173b24b9 | 1881 | } |
738cc472 | 1882 | |
d022d93e | 1883 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
1884 | |
1885 | void | |
502b8322 | 1886 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 1887 | { |
998d7deb | 1888 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
10b76d73 RK |
1889 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
1890 | GET_MODE (mem)); | |
738cc472 | 1891 | } |
1285011e | 1892 | |
998d7deb | 1893 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
1894 | |
1895 | void | |
502b8322 | 1896 | set_mem_expr (rtx mem, tree expr) |
1285011e RK |
1897 | { |
1898 | MEM_ATTRS (mem) | |
998d7deb | 1899 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
1285011e RK |
1900 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); |
1901 | } | |
998d7deb RH |
1902 | |
1903 | /* Set the offset of MEM to OFFSET. */ | |
1904 | ||
1905 | void | |
502b8322 | 1906 | set_mem_offset (rtx mem, rtx offset) |
998d7deb RH |
1907 | { |
1908 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1909 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
1910 | GET_MODE (mem)); | |
35aff10b AM |
1911 | } |
1912 | ||
1913 | /* Set the size of MEM to SIZE. */ | |
1914 | ||
1915 | void | |
502b8322 | 1916 | set_mem_size (rtx mem, rtx size) |
35aff10b AM |
1917 | { |
1918 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1919 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
1920 | GET_MODE (mem)); | |
998d7deb | 1921 | } |
173b24b9 | 1922 | \f |
738cc472 RK |
1923 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
1924 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
1925 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
1926 | returned memory location is required to be valid. The memory | |
1927 | attributes are not changed. */ | |
23b2ce53 | 1928 | |
738cc472 | 1929 | static rtx |
502b8322 | 1930 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
23b2ce53 | 1931 | { |
60564289 | 1932 | rtx new_rtx; |
23b2ce53 | 1933 | |
5b0264cb | 1934 | gcc_assert (MEM_P (memref)); |
23b2ce53 RS |
1935 | if (mode == VOIDmode) |
1936 | mode = GET_MODE (memref); | |
1937 | if (addr == 0) | |
1938 | addr = XEXP (memref, 0); | |
a74ff877 JH |
1939 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
1940 | && (!validate || memory_address_p (mode, addr))) | |
1941 | return memref; | |
23b2ce53 | 1942 | |
f1ec5147 | 1943 | if (validate) |
23b2ce53 | 1944 | { |
f1ec5147 | 1945 | if (reload_in_progress || reload_completed) |
5b0264cb | 1946 | gcc_assert (memory_address_p (mode, addr)); |
f1ec5147 RK |
1947 | else |
1948 | addr = memory_address (mode, addr); | |
23b2ce53 | 1949 | } |
750c9258 | 1950 | |
9b04c6a8 RK |
1951 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1952 | return memref; | |
1953 | ||
60564289 KG |
1954 | new_rtx = gen_rtx_MEM (mode, addr); |
1955 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
1956 | return new_rtx; | |
23b2ce53 | 1957 | } |
792760b9 | 1958 | |
738cc472 RK |
1959 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
1960 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
1961 | |
1962 | rtx | |
502b8322 | 1963 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
f4ef873c | 1964 | { |
60564289 KG |
1965 | rtx new_rtx = change_address_1 (memref, mode, addr, 1), size; |
1966 | enum machine_mode mmode = GET_MODE (new_rtx); | |
4e44c1ef JJ |
1967 | unsigned int align; |
1968 | ||
1969 | size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)); | |
1970 | align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode); | |
c2f7bcc3 | 1971 | |
fdb1c7b3 | 1972 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 1973 | if (new_rtx == memref) |
4e44c1ef JJ |
1974 | { |
1975 | if (MEM_ATTRS (memref) == 0 | |
1976 | || (MEM_EXPR (memref) == NULL | |
1977 | && MEM_OFFSET (memref) == NULL | |
1978 | && MEM_SIZE (memref) == size | |
1979 | && MEM_ALIGN (memref) == align)) | |
60564289 | 1980 | return new_rtx; |
4e44c1ef | 1981 | |
60564289 KG |
1982 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
1983 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 1984 | } |
fdb1c7b3 | 1985 | |
60564289 | 1986 | MEM_ATTRS (new_rtx) |
4e44c1ef | 1987 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, mmode); |
823e3574 | 1988 | |
60564289 | 1989 | return new_rtx; |
f4ef873c | 1990 | } |
792760b9 | 1991 | |
738cc472 RK |
1992 | /* Return a memory reference like MEMREF, but with its mode changed |
1993 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 JJ |
1994 | nonzero, the memory address is forced to be valid. |
1995 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
1996 | and caller is responsible for adjusting MEMREF base register. */ | |
f1ec5147 RK |
1997 | |
1998 | rtx | |
502b8322 AJ |
1999 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
2000 | int validate, int adjust) | |
f1ec5147 | 2001 | { |
823e3574 | 2002 | rtx addr = XEXP (memref, 0); |
60564289 | 2003 | rtx new_rtx; |
738cc472 | 2004 | rtx memoffset = MEM_OFFSET (memref); |
10b76d73 | 2005 | rtx size = 0; |
738cc472 | 2006 | unsigned int memalign = MEM_ALIGN (memref); |
a6fe9ed4 | 2007 | int pbits; |
823e3574 | 2008 | |
fdb1c7b3 JH |
2009 | /* If there are no changes, just return the original memory reference. */ |
2010 | if (mode == GET_MODE (memref) && !offset | |
2011 | && (!validate || memory_address_p (mode, addr))) | |
2012 | return memref; | |
2013 | ||
d14419e4 | 2014 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2015 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2016 | (plus (plus reg reg) const_int) -- so do this always. */ |
2017 | addr = copy_rtx (addr); | |
2018 | ||
a6fe9ed4 JM |
2019 | /* Convert a possibly large offset to a signed value within the |
2020 | range of the target address space. */ | |
2021 | pbits = GET_MODE_BITSIZE (Pmode); | |
2022 | if (HOST_BITS_PER_WIDE_INT > pbits) | |
2023 | { | |
2024 | int shift = HOST_BITS_PER_WIDE_INT - pbits; | |
2025 | offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift)) | |
2026 | >> shift); | |
2027 | } | |
2028 | ||
4a78c787 RH |
2029 | if (adjust) |
2030 | { | |
2031 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2032 | object, we can merge it into the LO_SUM. */ | |
2033 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
2034 | && offset >= 0 | |
2035 | && (unsigned HOST_WIDE_INT) offset | |
2036 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
2037 | addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0), | |
2038 | plus_constant (XEXP (addr, 1), offset)); | |
2039 | else | |
2040 | addr = plus_constant (addr, offset); | |
2041 | } | |
823e3574 | 2042 | |
60564289 | 2043 | new_rtx = change_address_1 (memref, mode, addr, validate); |
738cc472 | 2044 | |
09efeca1 PB |
2045 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2046 | but this would destroy memref's MEM_ATTRS. */ | |
2047 | if (new_rtx == memref && offset != 0) | |
2048 | new_rtx = copy_rtx (new_rtx); | |
2049 | ||
738cc472 RK |
2050 | /* Compute the new values of the memory attributes due to this adjustment. |
2051 | We add the offsets and update the alignment. */ | |
2052 | if (memoffset) | |
2053 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
2054 | ||
03bf2c23 RK |
2055 | /* Compute the new alignment by taking the MIN of the alignment and the |
2056 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2057 | if zero. */ | |
2058 | if (offset != 0) | |
3bf1e984 RK |
2059 | memalign |
2060 | = MIN (memalign, | |
2061 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
738cc472 | 2062 | |
10b76d73 | 2063 | /* We can compute the size in a number of ways. */ |
60564289 KG |
2064 | if (GET_MODE (new_rtx) != BLKmode) |
2065 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new_rtx))); | |
10b76d73 RK |
2066 | else if (MEM_SIZE (memref)) |
2067 | size = plus_constant (MEM_SIZE (memref), -offset); | |
2068 | ||
60564289 KG |
2069 | MEM_ATTRS (new_rtx) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
2070 | memoffset, size, memalign, GET_MODE (new_rtx)); | |
738cc472 RK |
2071 | |
2072 | /* At some point, we should validate that this offset is within the object, | |
2073 | if all the appropriate values are known. */ | |
60564289 | 2074 | return new_rtx; |
f1ec5147 RK |
2075 | } |
2076 | ||
630036c6 JJ |
2077 | /* Return a memory reference like MEMREF, but with its mode changed |
2078 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2079 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2080 | nonzero, the memory address is forced to be valid. */ |
2081 | ||
2082 | rtx | |
502b8322 AJ |
2083 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
2084 | HOST_WIDE_INT offset, int validate) | |
630036c6 JJ |
2085 | { |
2086 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
2087 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
2088 | } | |
2089 | ||
8ac61af7 RK |
2090 | /* Return a memory reference like MEMREF, but whose address is changed by |
2091 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2092 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2093 | |
2094 | rtx | |
502b8322 | 2095 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2096 | { |
60564289 | 2097 | rtx new_rtx, addr = XEXP (memref, 0); |
e3c8ea67 | 2098 | |
60564289 | 2099 | new_rtx = simplify_gen_binary (PLUS, Pmode, addr, offset); |
e3c8ea67 | 2100 | |
68252e27 | 2101 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2102 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2103 | |
2104 | However, if we did go and rearrange things, we can wind up not | |
2105 | being able to recognize the magic around pic_offset_table_rtx. | |
2106 | This stuff is fragile, and is yet another example of why it is | |
2107 | bad to expose PIC machinery too early. */ | |
60564289 | 2108 | if (! memory_address_p (GET_MODE (memref), new_rtx) |
e3c8ea67 RH |
2109 | && GET_CODE (addr) == PLUS |
2110 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2111 | { | |
2112 | addr = force_reg (GET_MODE (addr), addr); | |
60564289 | 2113 | new_rtx = simplify_gen_binary (PLUS, Pmode, addr, offset); |
e3c8ea67 RH |
2114 | } |
2115 | ||
60564289 KG |
2116 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
2117 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1); | |
0d4903b8 | 2118 | |
fdb1c7b3 | 2119 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2120 | if (new_rtx == memref) |
2121 | return new_rtx; | |
fdb1c7b3 | 2122 | |
0d4903b8 RK |
2123 | /* Update the alignment to reflect the offset. Reset the offset, which |
2124 | we don't know. */ | |
60564289 | 2125 | MEM_ATTRS (new_rtx) |
2cc2d4bb | 2126 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, |
9ceca302 | 2127 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
60564289 KG |
2128 | GET_MODE (new_rtx)); |
2129 | return new_rtx; | |
0d4903b8 | 2130 | } |
68252e27 | 2131 | |
792760b9 RK |
2132 | /* Return a memory reference like MEMREF, but with its address changed to |
2133 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2134 | to is the same, just the form of the address is being changed, such as | |
2135 | by putting something into a register. */ | |
2136 | ||
2137 | rtx | |
502b8322 | 2138 | replace_equiv_address (rtx memref, rtx addr) |
792760b9 | 2139 | { |
738cc472 RK |
2140 | /* change_address_1 copies the memory attribute structure without change |
2141 | and that's exactly what we want here. */ | |
40c0668b | 2142 | update_temp_slot_address (XEXP (memref, 0), addr); |
738cc472 | 2143 | return change_address_1 (memref, VOIDmode, addr, 1); |
792760b9 | 2144 | } |
738cc472 | 2145 | |
f1ec5147 RK |
2146 | /* Likewise, but the reference is not required to be valid. */ |
2147 | ||
2148 | rtx | |
502b8322 | 2149 | replace_equiv_address_nv (rtx memref, rtx addr) |
f1ec5147 | 2150 | { |
f1ec5147 RK |
2151 | return change_address_1 (memref, VOIDmode, addr, 0); |
2152 | } | |
e7dfe4bb RH |
2153 | |
2154 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2155 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2156 | cannot issue QImode memory operations and have to use SImode memory | |
2157 | operations plus masking logic. */ | |
2158 | ||
2159 | rtx | |
502b8322 | 2160 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb | 2161 | { |
60564289 KG |
2162 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1); |
2163 | tree expr = MEM_EXPR (new_rtx); | |
2164 | rtx memoffset = MEM_OFFSET (new_rtx); | |
e7dfe4bb RH |
2165 | unsigned int size = GET_MODE_SIZE (mode); |
2166 | ||
fdb1c7b3 | 2167 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2168 | if (new_rtx == memref) |
2169 | return new_rtx; | |
fdb1c7b3 | 2170 | |
e7dfe4bb RH |
2171 | /* If we don't know what offset we were at within the expression, then |
2172 | we can't know if we've overstepped the bounds. */ | |
fa1591cb | 2173 | if (! memoffset) |
e7dfe4bb RH |
2174 | expr = NULL_TREE; |
2175 | ||
2176 | while (expr) | |
2177 | { | |
2178 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2179 | { | |
2180 | tree field = TREE_OPERAND (expr, 1); | |
44de5aeb | 2181 | tree offset = component_ref_field_offset (expr); |
e7dfe4bb RH |
2182 | |
2183 | if (! DECL_SIZE_UNIT (field)) | |
2184 | { | |
2185 | expr = NULL_TREE; | |
2186 | break; | |
2187 | } | |
2188 | ||
2189 | /* Is the field at least as large as the access? If so, ok, | |
2190 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2191 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2192 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
e7dfe4bb RH |
2193 | && INTVAL (memoffset) >= 0) |
2194 | break; | |
2195 | ||
44de5aeb | 2196 | if (! host_integerp (offset, 1)) |
e7dfe4bb RH |
2197 | { |
2198 | expr = NULL_TREE; | |
2199 | break; | |
2200 | } | |
2201 | ||
2202 | expr = TREE_OPERAND (expr, 0); | |
44de5aeb RK |
2203 | memoffset |
2204 | = (GEN_INT (INTVAL (memoffset) | |
2205 | + tree_low_cst (offset, 1) | |
2206 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2207 | / BITS_PER_UNIT))); | |
e7dfe4bb RH |
2208 | } |
2209 | /* Similarly for the decl. */ | |
2210 | else if (DECL_P (expr) | |
2211 | && DECL_SIZE_UNIT (expr) | |
45f79783 | 2212 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
e7dfe4bb RH |
2213 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2214 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2215 | break; | |
2216 | else | |
2217 | { | |
2218 | /* The widened memory access overflows the expression, which means | |
2219 | that it could alias another expression. Zap it. */ | |
2220 | expr = NULL_TREE; | |
2221 | break; | |
2222 | } | |
2223 | } | |
2224 | ||
2225 | if (! expr) | |
2226 | memoffset = NULL_RTX; | |
2227 | ||
2228 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2229 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2230 | ||
60564289 KG |
2231 | MEM_ATTRS (new_rtx) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), |
2232 | MEM_ALIGN (new_rtx), mode); | |
e7dfe4bb | 2233 | |
60564289 | 2234 | return new_rtx; |
e7dfe4bb | 2235 | } |
23b2ce53 | 2236 | \f |
f6129d66 RH |
2237 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2238 | static GTY(()) tree spill_slot_decl; | |
2239 | ||
3d7e23f6 RH |
2240 | tree |
2241 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2242 | { |
2243 | tree d = spill_slot_decl; | |
2244 | rtx rd; | |
2245 | ||
3d7e23f6 | 2246 | if (d || !force_build_p) |
f6129d66 RH |
2247 | return d; |
2248 | ||
c2255bc4 AH |
2249 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2250 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2251 | DECL_ARTIFICIAL (d) = 1; |
2252 | DECL_IGNORED_P (d) = 1; | |
2253 | TREE_USED (d) = 1; | |
2254 | TREE_THIS_NOTRAP (d) = 1; | |
2255 | spill_slot_decl = d; | |
2256 | ||
2257 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2258 | MEM_NOTRAP_P (rd) = 1; | |
2259 | MEM_ATTRS (rd) = get_mem_attrs (new_alias_set (), d, const0_rtx, | |
2260 | NULL_RTX, 0, BLKmode); | |
2261 | SET_DECL_RTL (d, rd); | |
2262 | ||
2263 | return d; | |
2264 | } | |
2265 | ||
2266 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2267 | attributes as appropriate for a register allocator spill slot. | |
2268 | These slots are not aliasable by other memory. We arrange for | |
2269 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2270 | work properly in the case of shared spill slots. */ | |
2271 | ||
2272 | void | |
2273 | set_mem_attrs_for_spill (rtx mem) | |
2274 | { | |
2275 | alias_set_type alias; | |
2276 | rtx addr, offset; | |
2277 | tree expr; | |
2278 | ||
3d7e23f6 | 2279 | expr = get_spill_slot_decl (true); |
f6129d66 RH |
2280 | alias = MEM_ALIAS_SET (DECL_RTL (expr)); |
2281 | ||
2282 | /* We expect the incoming memory to be of the form: | |
2283 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2284 | with perhaps the plus missing for offset = 0. */ | |
2285 | addr = XEXP (mem, 0); | |
2286 | offset = const0_rtx; | |
2287 | if (GET_CODE (addr) == PLUS | |
481683e1 | 2288 | && CONST_INT_P (XEXP (addr, 1))) |
f6129d66 RH |
2289 | offset = XEXP (addr, 1); |
2290 | ||
2291 | MEM_ATTRS (mem) = get_mem_attrs (alias, expr, offset, | |
2292 | MEM_SIZE (mem), MEM_ALIGN (mem), | |
2293 | GET_MODE (mem)); | |
2294 | MEM_NOTRAP_P (mem) = 1; | |
2295 | } | |
2296 | \f | |
23b2ce53 RS |
2297 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2298 | ||
2299 | rtx | |
502b8322 | 2300 | gen_label_rtx (void) |
23b2ce53 | 2301 | { |
0dc36574 | 2302 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
502b8322 | 2303 | NULL, label_num++, NULL); |
23b2ce53 RS |
2304 | } |
2305 | \f | |
2306 | /* For procedure integration. */ | |
2307 | ||
23b2ce53 | 2308 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2309 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2310 | Used for an inline-procedure after copying the insn chain. */ |
2311 | ||
2312 | void | |
502b8322 | 2313 | set_new_first_and_last_insn (rtx first, rtx last) |
23b2ce53 | 2314 | { |
86fe05e0 RK |
2315 | rtx insn; |
2316 | ||
23b2ce53 RS |
2317 | first_insn = first; |
2318 | last_insn = last; | |
86fe05e0 RK |
2319 | cur_insn_uid = 0; |
2320 | ||
2321 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2322 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2323 | ||
2324 | cur_insn_uid++; | |
23b2ce53 | 2325 | } |
23b2ce53 | 2326 | \f |
750c9258 | 2327 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2328 | structure. This routine should only be called once. */ |
23b2ce53 | 2329 | |
fd743bc1 | 2330 | static void |
b4aaa77b | 2331 | unshare_all_rtl_1 (rtx insn) |
23b2ce53 | 2332 | { |
d1b81779 | 2333 | /* Unshare just about everything else. */ |
2c07f13b | 2334 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2335 | |
23b2ce53 RS |
2336 | /* Make sure the addresses of stack slots found outside the insn chain |
2337 | (such as, in DECL_RTL of a variable) are not shared | |
2338 | with the insn chain. | |
2339 | ||
2340 | This special care is necessary when the stack slot MEM does not | |
2341 | actually appear in the insn chain. If it does appear, its address | |
2342 | is unshared from all else at that point. */ | |
242b0ce6 | 2343 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
2344 | } |
2345 | ||
750c9258 | 2346 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2347 | structure, again. This is a fairly expensive thing to do so it |
2348 | should be done sparingly. */ | |
2349 | ||
2350 | void | |
502b8322 | 2351 | unshare_all_rtl_again (rtx insn) |
d1b81779 GK |
2352 | { |
2353 | rtx p; | |
624c87aa RE |
2354 | tree decl; |
2355 | ||
d1b81779 | 2356 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2357 | if (INSN_P (p)) |
d1b81779 GK |
2358 | { |
2359 | reset_used_flags (PATTERN (p)); | |
2360 | reset_used_flags (REG_NOTES (p)); | |
d1b81779 | 2361 | } |
624c87aa | 2362 | |
2d4aecb3 | 2363 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2364 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2365 | |
624c87aa RE |
2366 | /* Make sure that virtual parameters are not shared. */ |
2367 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
5eb2a9f2 | 2368 | set_used_flags (DECL_RTL (decl)); |
624c87aa RE |
2369 | |
2370 | reset_used_flags (stack_slot_list); | |
2371 | ||
b4aaa77b | 2372 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2373 | } |
2374 | ||
c2924966 | 2375 | unsigned int |
fd743bc1 PB |
2376 | unshare_all_rtl (void) |
2377 | { | |
b4aaa77b | 2378 | unshare_all_rtl_1 (get_insns ()); |
c2924966 | 2379 | return 0; |
d1b81779 GK |
2380 | } |
2381 | ||
8ddbbcae | 2382 | struct rtl_opt_pass pass_unshare_all_rtl = |
ef330312 | 2383 | { |
8ddbbcae JH |
2384 | { |
2385 | RTL_PASS, | |
defb77dc | 2386 | "unshare", /* name */ |
ef330312 PB |
2387 | NULL, /* gate */ |
2388 | unshare_all_rtl, /* execute */ | |
2389 | NULL, /* sub */ | |
2390 | NULL, /* next */ | |
2391 | 0, /* static_pass_number */ | |
7072a650 | 2392 | TV_NONE, /* tv_id */ |
ef330312 PB |
2393 | 0, /* properties_required */ |
2394 | 0, /* properties_provided */ | |
2395 | 0, /* properties_destroyed */ | |
2396 | 0, /* todo_flags_start */ | |
8ddbbcae JH |
2397 | TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */ |
2398 | } | |
ef330312 PB |
2399 | }; |
2400 | ||
2401 | ||
2c07f13b JH |
2402 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2403 | Recursively does the same for subexpressions. */ | |
2404 | ||
2405 | static void | |
2406 | verify_rtx_sharing (rtx orig, rtx insn) | |
2407 | { | |
2408 | rtx x = orig; | |
2409 | int i; | |
2410 | enum rtx_code code; | |
2411 | const char *format_ptr; | |
2412 | ||
2413 | if (x == 0) | |
2414 | return; | |
2415 | ||
2416 | code = GET_CODE (x); | |
2417 | ||
2418 | /* These types may be freely shared. */ | |
2419 | ||
2420 | switch (code) | |
2421 | { | |
2422 | case REG: | |
2c07f13b JH |
2423 | case CONST_INT: |
2424 | case CONST_DOUBLE: | |
091a3ac7 | 2425 | case CONST_FIXED: |
2c07f13b JH |
2426 | case CONST_VECTOR: |
2427 | case SYMBOL_REF: | |
2428 | case LABEL_REF: | |
2429 | case CODE_LABEL: | |
2430 | case PC: | |
2431 | case CC0: | |
2432 | case SCRATCH: | |
2c07f13b | 2433 | return; |
3e89ed8d JH |
2434 | /* SCRATCH must be shared because they represent distinct values. */ |
2435 | case CLOBBER: | |
2436 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2437 | return; | |
2438 | break; | |
2c07f13b JH |
2439 | |
2440 | case CONST: | |
6fb5fa3c | 2441 | if (shared_const_p (orig)) |
2c07f13b JH |
2442 | return; |
2443 | break; | |
2444 | ||
2445 | case MEM: | |
2446 | /* A MEM is allowed to be shared if its address is constant. */ | |
2447 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2448 | || reload_completed || reload_in_progress) | |
2449 | return; | |
2450 | ||
2451 | break; | |
2452 | ||
2453 | default: | |
2454 | break; | |
2455 | } | |
2456 | ||
2457 | /* This rtx may not be shared. If it has already been seen, | |
2458 | replace it with a copy of itself. */ | |
1a2caa7a | 2459 | #ifdef ENABLE_CHECKING |
2c07f13b JH |
2460 | if (RTX_FLAG (x, used)) |
2461 | { | |
ab532386 | 2462 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2463 | debug_rtx (insn); |
ab532386 | 2464 | error ("shared rtx"); |
2c07f13b | 2465 | debug_rtx (x); |
ab532386 | 2466 | internal_error ("internal consistency failure"); |
2c07f13b | 2467 | } |
1a2caa7a NS |
2468 | #endif |
2469 | gcc_assert (!RTX_FLAG (x, used)); | |
2470 | ||
2c07f13b JH |
2471 | RTX_FLAG (x, used) = 1; |
2472 | ||
6614fd40 | 2473 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2474 | |
2475 | format_ptr = GET_RTX_FORMAT (code); | |
2476 | ||
2477 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2478 | { | |
2479 | switch (*format_ptr++) | |
2480 | { | |
2481 | case 'e': | |
2482 | verify_rtx_sharing (XEXP (x, i), insn); | |
2483 | break; | |
2484 | ||
2485 | case 'E': | |
2486 | if (XVEC (x, i) != NULL) | |
2487 | { | |
2488 | int j; | |
2489 | int len = XVECLEN (x, i); | |
2490 | ||
2491 | for (j = 0; j < len; j++) | |
2492 | { | |
1a2caa7a NS |
2493 | /* We allow sharing of ASM_OPERANDS inside single |
2494 | instruction. */ | |
2c07f13b | 2495 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2496 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2497 | == ASM_OPERANDS)) | |
2c07f13b JH |
2498 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2499 | else | |
2500 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2501 | } | |
2502 | } | |
2503 | break; | |
2504 | } | |
2505 | } | |
2506 | return; | |
2507 | } | |
2508 | ||
ba228239 | 2509 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2c07f13b JH |
2510 | sharing in between the subexpressions. */ |
2511 | ||
2512 | void | |
2513 | verify_rtl_sharing (void) | |
2514 | { | |
2515 | rtx p; | |
2516 | ||
2517 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2518 | if (INSN_P (p)) | |
2519 | { | |
2520 | reset_used_flags (PATTERN (p)); | |
2521 | reset_used_flags (REG_NOTES (p)); | |
2954a813 KK |
2522 | if (GET_CODE (PATTERN (p)) == SEQUENCE) |
2523 | { | |
2524 | int i; | |
2525 | rtx q, sequence = PATTERN (p); | |
2526 | ||
2527 | for (i = 0; i < XVECLEN (sequence, 0); i++) | |
2528 | { | |
2529 | q = XVECEXP (sequence, 0, i); | |
2530 | gcc_assert (INSN_P (q)); | |
2531 | reset_used_flags (PATTERN (q)); | |
2532 | reset_used_flags (REG_NOTES (q)); | |
2954a813 KK |
2533 | } |
2534 | } | |
2c07f13b JH |
2535 | } |
2536 | ||
2537 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2538 | if (INSN_P (p)) | |
2539 | { | |
2540 | verify_rtx_sharing (PATTERN (p), p); | |
2541 | verify_rtx_sharing (REG_NOTES (p), p); | |
2c07f13b JH |
2542 | } |
2543 | } | |
2544 | ||
d1b81779 GK |
2545 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2546 | Assumes the mark bits are cleared at entry. */ | |
2547 | ||
2c07f13b JH |
2548 | void |
2549 | unshare_all_rtl_in_chain (rtx insn) | |
d1b81779 GK |
2550 | { |
2551 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2552 | if (INSN_P (insn)) |
d1b81779 GK |
2553 | { |
2554 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2555 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
d1b81779 GK |
2556 | } |
2557 | } | |
2558 | ||
2d4aecb3 | 2559 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2560 | shared. We never replace the DECL_RTLs themselves with a copy, |
2561 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2562 | expressions in the instruction stream. | |
2563 | ||
2564 | Note that reload may convert pseudo registers into memories in-place. | |
2565 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2566 | reset the used flags on MEMs in the instruction stream, we must set | |
2567 | them again on MEMs that appear in DECL_RTLs. */ | |
2568 | ||
2d4aecb3 | 2569 | static void |
5eb2a9f2 | 2570 | set_used_decls (tree blk) |
2d4aecb3 AO |
2571 | { |
2572 | tree t; | |
2573 | ||
2574 | /* Mark decls. */ | |
2575 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c | 2576 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2577 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2578 | |
2579 | /* Now process sub-blocks. */ | |
87caf699 | 2580 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 2581 | set_used_decls (t); |
2d4aecb3 AO |
2582 | } |
2583 | ||
23b2ce53 | 2584 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2585 | Recursively does the same for subexpressions. Uses |
2586 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2587 | |
2588 | rtx | |
502b8322 | 2589 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2590 | { |
32b32b16 AP |
2591 | copy_rtx_if_shared_1 (&orig); |
2592 | return orig; | |
2593 | } | |
2594 | ||
ff954f39 AP |
2595 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2596 | use. Recursively does the same for subexpressions. */ | |
2597 | ||
32b32b16 AP |
2598 | static void |
2599 | copy_rtx_if_shared_1 (rtx *orig1) | |
2600 | { | |
2601 | rtx x; | |
b3694847 SS |
2602 | int i; |
2603 | enum rtx_code code; | |
32b32b16 | 2604 | rtx *last_ptr; |
b3694847 | 2605 | const char *format_ptr; |
23b2ce53 | 2606 | int copied = 0; |
32b32b16 AP |
2607 | int length; |
2608 | ||
2609 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2610 | repeat: | |
2611 | x = *orig1; | |
23b2ce53 RS |
2612 | |
2613 | if (x == 0) | |
32b32b16 | 2614 | return; |
23b2ce53 RS |
2615 | |
2616 | code = GET_CODE (x); | |
2617 | ||
2618 | /* These types may be freely shared. */ | |
2619 | ||
2620 | switch (code) | |
2621 | { | |
2622 | case REG: | |
23b2ce53 RS |
2623 | case CONST_INT: |
2624 | case CONST_DOUBLE: | |
091a3ac7 | 2625 | case CONST_FIXED: |
69ef87e2 | 2626 | case CONST_VECTOR: |
23b2ce53 | 2627 | case SYMBOL_REF: |
2c07f13b | 2628 | case LABEL_REF: |
23b2ce53 RS |
2629 | case CODE_LABEL: |
2630 | case PC: | |
2631 | case CC0: | |
2632 | case SCRATCH: | |
0f41302f | 2633 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 2634 | return; |
3e89ed8d JH |
2635 | case CLOBBER: |
2636 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2637 | return; | |
2638 | break; | |
23b2ce53 | 2639 | |
b851ea09 | 2640 | case CONST: |
6fb5fa3c | 2641 | if (shared_const_p (x)) |
32b32b16 | 2642 | return; |
b851ea09 RK |
2643 | break; |
2644 | ||
23b2ce53 RS |
2645 | case INSN: |
2646 | case JUMP_INSN: | |
2647 | case CALL_INSN: | |
2648 | case NOTE: | |
23b2ce53 RS |
2649 | case BARRIER: |
2650 | /* The chain of insns is not being copied. */ | |
32b32b16 | 2651 | return; |
23b2ce53 | 2652 | |
e9a25f70 JL |
2653 | default: |
2654 | break; | |
23b2ce53 RS |
2655 | } |
2656 | ||
2657 | /* This rtx may not be shared. If it has already been seen, | |
2658 | replace it with a copy of itself. */ | |
2659 | ||
2adc7f12 | 2660 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2661 | { |
aacd3885 | 2662 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
2663 | copied = 1; |
2664 | } | |
2adc7f12 | 2665 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
2666 | |
2667 | /* Now scan the subexpressions recursively. | |
2668 | We can store any replaced subexpressions directly into X | |
2669 | since we know X is not shared! Any vectors in X | |
2670 | must be copied if X was copied. */ | |
2671 | ||
2672 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2673 | length = GET_RTX_LENGTH (code); |
2674 | last_ptr = NULL; | |
2675 | ||
2676 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2677 | { |
2678 | switch (*format_ptr++) | |
2679 | { | |
2680 | case 'e': | |
32b32b16 AP |
2681 | if (last_ptr) |
2682 | copy_rtx_if_shared_1 (last_ptr); | |
2683 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
2684 | break; |
2685 | ||
2686 | case 'E': | |
2687 | if (XVEC (x, i) != NULL) | |
2688 | { | |
b3694847 | 2689 | int j; |
f0722107 | 2690 | int len = XVECLEN (x, i); |
32b32b16 | 2691 | |
6614fd40 KH |
2692 | /* Copy the vector iff I copied the rtx and the length |
2693 | is nonzero. */ | |
f0722107 | 2694 | if (copied && len > 0) |
8f985ec4 | 2695 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
32b32b16 | 2696 | |
5d3cc252 | 2697 | /* Call recursively on all inside the vector. */ |
f0722107 | 2698 | for (j = 0; j < len; j++) |
32b32b16 AP |
2699 | { |
2700 | if (last_ptr) | |
2701 | copy_rtx_if_shared_1 (last_ptr); | |
2702 | last_ptr = &XVECEXP (x, i, j); | |
2703 | } | |
23b2ce53 RS |
2704 | } |
2705 | break; | |
2706 | } | |
2707 | } | |
32b32b16 AP |
2708 | *orig1 = x; |
2709 | if (last_ptr) | |
2710 | { | |
2711 | orig1 = last_ptr; | |
2712 | goto repeat; | |
2713 | } | |
2714 | return; | |
23b2ce53 RS |
2715 | } |
2716 | ||
2717 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2718 | to look for shared sub-parts. */ | |
2719 | ||
2720 | void | |
502b8322 | 2721 | reset_used_flags (rtx x) |
23b2ce53 | 2722 | { |
b3694847 SS |
2723 | int i, j; |
2724 | enum rtx_code code; | |
2725 | const char *format_ptr; | |
32b32b16 | 2726 | int length; |
23b2ce53 | 2727 | |
32b32b16 AP |
2728 | /* Repeat is used to turn tail-recursion into iteration. */ |
2729 | repeat: | |
23b2ce53 RS |
2730 | if (x == 0) |
2731 | return; | |
2732 | ||
2733 | code = GET_CODE (x); | |
2734 | ||
9faa82d8 | 2735 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2736 | for them. */ |
2737 | ||
2738 | switch (code) | |
2739 | { | |
2740 | case REG: | |
23b2ce53 RS |
2741 | case CONST_INT: |
2742 | case CONST_DOUBLE: | |
091a3ac7 | 2743 | case CONST_FIXED: |
69ef87e2 | 2744 | case CONST_VECTOR: |
23b2ce53 RS |
2745 | case SYMBOL_REF: |
2746 | case CODE_LABEL: | |
2747 | case PC: | |
2748 | case CC0: | |
2749 | return; | |
2750 | ||
2751 | case INSN: | |
2752 | case JUMP_INSN: | |
2753 | case CALL_INSN: | |
2754 | case NOTE: | |
2755 | case LABEL_REF: | |
2756 | case BARRIER: | |
2757 | /* The chain of insns is not being copied. */ | |
2758 | return; | |
750c9258 | 2759 | |
e9a25f70 JL |
2760 | default: |
2761 | break; | |
23b2ce53 RS |
2762 | } |
2763 | ||
2adc7f12 | 2764 | RTX_FLAG (x, used) = 0; |
23b2ce53 RS |
2765 | |
2766 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2767 | length = GET_RTX_LENGTH (code); |
2768 | ||
2769 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2770 | { |
2771 | switch (*format_ptr++) | |
2772 | { | |
2773 | case 'e': | |
32b32b16 AP |
2774 | if (i == length-1) |
2775 | { | |
2776 | x = XEXP (x, i); | |
2777 | goto repeat; | |
2778 | } | |
23b2ce53 RS |
2779 | reset_used_flags (XEXP (x, i)); |
2780 | break; | |
2781 | ||
2782 | case 'E': | |
2783 | for (j = 0; j < XVECLEN (x, i); j++) | |
2784 | reset_used_flags (XVECEXP (x, i, j)); | |
2785 | break; | |
2786 | } | |
2787 | } | |
2788 | } | |
2c07f13b JH |
2789 | |
2790 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used | |
2791 | to look for shared sub-parts. */ | |
2792 | ||
2793 | void | |
2794 | set_used_flags (rtx x) | |
2795 | { | |
2796 | int i, j; | |
2797 | enum rtx_code code; | |
2798 | const char *format_ptr; | |
2799 | ||
2800 | if (x == 0) | |
2801 | return; | |
2802 | ||
2803 | code = GET_CODE (x); | |
2804 | ||
2805 | /* These types may be freely shared so we needn't do any resetting | |
2806 | for them. */ | |
2807 | ||
2808 | switch (code) | |
2809 | { | |
2810 | case REG: | |
2c07f13b JH |
2811 | case CONST_INT: |
2812 | case CONST_DOUBLE: | |
091a3ac7 | 2813 | case CONST_FIXED: |
2c07f13b JH |
2814 | case CONST_VECTOR: |
2815 | case SYMBOL_REF: | |
2816 | case CODE_LABEL: | |
2817 | case PC: | |
2818 | case CC0: | |
2819 | return; | |
2820 | ||
2821 | case INSN: | |
2822 | case JUMP_INSN: | |
2823 | case CALL_INSN: | |
2824 | case NOTE: | |
2825 | case LABEL_REF: | |
2826 | case BARRIER: | |
2827 | /* The chain of insns is not being copied. */ | |
2828 | return; | |
2829 | ||
2830 | default: | |
2831 | break; | |
2832 | } | |
2833 | ||
2834 | RTX_FLAG (x, used) = 1; | |
2835 | ||
2836 | format_ptr = GET_RTX_FORMAT (code); | |
2837 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2838 | { | |
2839 | switch (*format_ptr++) | |
2840 | { | |
2841 | case 'e': | |
2842 | set_used_flags (XEXP (x, i)); | |
2843 | break; | |
2844 | ||
2845 | case 'E': | |
2846 | for (j = 0; j < XVECLEN (x, i); j++) | |
2847 | set_used_flags (XVECEXP (x, i, j)); | |
2848 | break; | |
2849 | } | |
2850 | } | |
2851 | } | |
23b2ce53 RS |
2852 | \f |
2853 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2854 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2855 | OTHER must be valid as a SET_DEST. */ | |
2856 | ||
2857 | rtx | |
502b8322 | 2858 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
2859 | { |
2860 | while (1) | |
2861 | switch (GET_CODE (other)) | |
2862 | { | |
2863 | case SUBREG: | |
2864 | other = SUBREG_REG (other); | |
2865 | break; | |
2866 | case STRICT_LOW_PART: | |
2867 | case SIGN_EXTEND: | |
2868 | case ZERO_EXTEND: | |
2869 | other = XEXP (other, 0); | |
2870 | break; | |
2871 | default: | |
2872 | goto done; | |
2873 | } | |
2874 | done: | |
3c0cb5de | 2875 | if ((MEM_P (other) |
23b2ce53 | 2876 | && ! CONSTANT_P (x) |
f8cfc6aa | 2877 | && !REG_P (x) |
23b2ce53 | 2878 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 2879 | || (REG_P (other) |
23b2ce53 RS |
2880 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
2881 | || reg_mentioned_p (other, x)))) | |
2882 | { | |
2883 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2884 | emit_move_insn (temp, x); | |
2885 | return temp; | |
2886 | } | |
2887 | return x; | |
2888 | } | |
2889 | \f | |
2890 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2891 | ||
2892 | /* Return the first insn of the current sequence or current function. */ | |
2893 | ||
2894 | rtx | |
502b8322 | 2895 | get_insns (void) |
23b2ce53 RS |
2896 | { |
2897 | return first_insn; | |
2898 | } | |
2899 | ||
3dec4024 JH |
2900 | /* Specify a new insn as the first in the chain. */ |
2901 | ||
2902 | void | |
502b8322 | 2903 | set_first_insn (rtx insn) |
3dec4024 | 2904 | { |
5b0264cb | 2905 | gcc_assert (!PREV_INSN (insn)); |
3dec4024 JH |
2906 | first_insn = insn; |
2907 | } | |
2908 | ||
23b2ce53 RS |
2909 | /* Return the last insn emitted in current sequence or current function. */ |
2910 | ||
2911 | rtx | |
502b8322 | 2912 | get_last_insn (void) |
23b2ce53 RS |
2913 | { |
2914 | return last_insn; | |
2915 | } | |
2916 | ||
2917 | /* Specify a new insn as the last in the chain. */ | |
2918 | ||
2919 | void | |
502b8322 | 2920 | set_last_insn (rtx insn) |
23b2ce53 | 2921 | { |
5b0264cb | 2922 | gcc_assert (!NEXT_INSN (insn)); |
23b2ce53 RS |
2923 | last_insn = insn; |
2924 | } | |
2925 | ||
2926 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2927 | ||
2928 | rtx | |
502b8322 | 2929 | get_last_insn_anywhere (void) |
23b2ce53 RS |
2930 | { |
2931 | struct sequence_stack *stack; | |
2932 | if (last_insn) | |
2933 | return last_insn; | |
49ad7cfa | 2934 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2935 | if (stack->last != 0) |
2936 | return stack->last; | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2a496e8b JDA |
2940 | /* Return the first nonnote insn emitted in current sequence or current |
2941 | function. This routine looks inside SEQUENCEs. */ | |
2942 | ||
2943 | rtx | |
502b8322 | 2944 | get_first_nonnote_insn (void) |
2a496e8b | 2945 | { |
91373fe8 JDA |
2946 | rtx insn = first_insn; |
2947 | ||
2948 | if (insn) | |
2949 | { | |
2950 | if (NOTE_P (insn)) | |
2951 | for (insn = next_insn (insn); | |
2952 | insn && NOTE_P (insn); | |
2953 | insn = next_insn (insn)) | |
2954 | continue; | |
2955 | else | |
2956 | { | |
2ca202e7 | 2957 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2958 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2959 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2960 | } | |
2961 | } | |
2a496e8b JDA |
2962 | |
2963 | return insn; | |
2964 | } | |
2965 | ||
2966 | /* Return the last nonnote insn emitted in current sequence or current | |
2967 | function. This routine looks inside SEQUENCEs. */ | |
2968 | ||
2969 | rtx | |
502b8322 | 2970 | get_last_nonnote_insn (void) |
2a496e8b | 2971 | { |
91373fe8 JDA |
2972 | rtx insn = last_insn; |
2973 | ||
2974 | if (insn) | |
2975 | { | |
2976 | if (NOTE_P (insn)) | |
2977 | for (insn = previous_insn (insn); | |
2978 | insn && NOTE_P (insn); | |
2979 | insn = previous_insn (insn)) | |
2980 | continue; | |
2981 | else | |
2982 | { | |
2ca202e7 | 2983 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2984 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2985 | insn = XVECEXP (PATTERN (insn), 0, | |
2986 | XVECLEN (PATTERN (insn), 0) - 1); | |
2987 | } | |
2988 | } | |
2a496e8b JDA |
2989 | |
2990 | return insn; | |
2991 | } | |
2992 | ||
23b2ce53 RS |
2993 | /* Return a number larger than any instruction's uid in this function. */ |
2994 | ||
2995 | int | |
502b8322 | 2996 | get_max_uid (void) |
23b2ce53 RS |
2997 | { |
2998 | return cur_insn_uid; | |
2999 | } | |
3000 | \f | |
3001 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
3002 | of the sequence. */ | |
3003 | ||
3004 | rtx | |
502b8322 | 3005 | next_insn (rtx insn) |
23b2ce53 | 3006 | { |
75547801 KG |
3007 | if (insn) |
3008 | { | |
3009 | insn = NEXT_INSN (insn); | |
3010 | if (insn && NONJUMP_INSN_P (insn) | |
3011 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3012 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3013 | } | |
23b2ce53 | 3014 | |
75547801 | 3015 | return insn; |
23b2ce53 RS |
3016 | } |
3017 | ||
3018 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3019 | of the sequence. */ | |
3020 | ||
3021 | rtx | |
502b8322 | 3022 | previous_insn (rtx insn) |
23b2ce53 | 3023 | { |
75547801 KG |
3024 | if (insn) |
3025 | { | |
3026 | insn = PREV_INSN (insn); | |
3027 | if (insn && NONJUMP_INSN_P (insn) | |
3028 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3029 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
3030 | } | |
23b2ce53 | 3031 | |
75547801 | 3032 | return insn; |
23b2ce53 RS |
3033 | } |
3034 | ||
3035 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3036 | look inside SEQUENCEs. */ | |
3037 | ||
3038 | rtx | |
502b8322 | 3039 | next_nonnote_insn (rtx insn) |
23b2ce53 | 3040 | { |
75547801 KG |
3041 | while (insn) |
3042 | { | |
3043 | insn = NEXT_INSN (insn); | |
3044 | if (insn == 0 || !NOTE_P (insn)) | |
3045 | break; | |
3046 | } | |
23b2ce53 | 3047 | |
75547801 | 3048 | return insn; |
23b2ce53 RS |
3049 | } |
3050 | ||
3051 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
3052 | not look inside SEQUENCEs. */ | |
3053 | ||
3054 | rtx | |
502b8322 | 3055 | prev_nonnote_insn (rtx insn) |
23b2ce53 | 3056 | { |
75547801 KG |
3057 | while (insn) |
3058 | { | |
3059 | insn = PREV_INSN (insn); | |
3060 | if (insn == 0 || !NOTE_P (insn)) | |
3061 | break; | |
3062 | } | |
23b2ce53 | 3063 | |
75547801 | 3064 | return insn; |
23b2ce53 RS |
3065 | } |
3066 | ||
3067 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
3068 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3069 | SEQUENCEs. */ |
23b2ce53 RS |
3070 | |
3071 | rtx | |
502b8322 | 3072 | next_real_insn (rtx insn) |
23b2ce53 | 3073 | { |
75547801 KG |
3074 | while (insn) |
3075 | { | |
3076 | insn = NEXT_INSN (insn); | |
3077 | if (insn == 0 || INSN_P (insn)) | |
3078 | break; | |
3079 | } | |
23b2ce53 | 3080 | |
75547801 | 3081 | return insn; |
23b2ce53 RS |
3082 | } |
3083 | ||
3084 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3085 | or 0, if there is none. This routine does not look inside | |
3086 | SEQUENCEs. */ | |
3087 | ||
3088 | rtx | |
502b8322 | 3089 | prev_real_insn (rtx insn) |
23b2ce53 | 3090 | { |
75547801 KG |
3091 | while (insn) |
3092 | { | |
3093 | insn = PREV_INSN (insn); | |
3094 | if (insn == 0 || INSN_P (insn)) | |
3095 | break; | |
3096 | } | |
23b2ce53 | 3097 | |
75547801 | 3098 | return insn; |
23b2ce53 RS |
3099 | } |
3100 | ||
ee960939 OH |
3101 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3102 | This routine does not look inside SEQUENCEs. */ | |
3103 | ||
3104 | rtx | |
502b8322 | 3105 | last_call_insn (void) |
ee960939 OH |
3106 | { |
3107 | rtx insn; | |
3108 | ||
3109 | for (insn = get_last_insn (); | |
4b4bf941 | 3110 | insn && !CALL_P (insn); |
ee960939 OH |
3111 | insn = PREV_INSN (insn)) |
3112 | ; | |
3113 | ||
3114 | return insn; | |
3115 | } | |
3116 | ||
23b2ce53 RS |
3117 | /* Find the next insn after INSN that really does something. This routine |
3118 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3119 | same as next_real_insn. */ | |
3120 | ||
69732dcb | 3121 | int |
4f588890 | 3122 | active_insn_p (const_rtx insn) |
69732dcb | 3123 | { |
4b4bf941 JQ |
3124 | return (CALL_P (insn) || JUMP_P (insn) |
3125 | || (NONJUMP_INSN_P (insn) | |
23b8ba81 RH |
3126 | && (! reload_completed |
3127 | || (GET_CODE (PATTERN (insn)) != USE | |
3128 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3129 | } |
3130 | ||
23b2ce53 | 3131 | rtx |
502b8322 | 3132 | next_active_insn (rtx insn) |
23b2ce53 | 3133 | { |
75547801 KG |
3134 | while (insn) |
3135 | { | |
3136 | insn = NEXT_INSN (insn); | |
3137 | if (insn == 0 || active_insn_p (insn)) | |
3138 | break; | |
3139 | } | |
23b2ce53 | 3140 | |
75547801 | 3141 | return insn; |
23b2ce53 RS |
3142 | } |
3143 | ||
3144 | /* Find the last insn before INSN that really does something. This routine | |
3145 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3146 | same as prev_real_insn. */ | |
3147 | ||
3148 | rtx | |
502b8322 | 3149 | prev_active_insn (rtx insn) |
23b2ce53 | 3150 | { |
75547801 KG |
3151 | while (insn) |
3152 | { | |
3153 | insn = PREV_INSN (insn); | |
3154 | if (insn == 0 || active_insn_p (insn)) | |
3155 | break; | |
3156 | } | |
23b2ce53 | 3157 | |
75547801 | 3158 | return insn; |
23b2ce53 RS |
3159 | } |
3160 | ||
3161 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
3162 | ||
3163 | rtx | |
502b8322 | 3164 | next_label (rtx insn) |
23b2ce53 | 3165 | { |
75547801 KG |
3166 | while (insn) |
3167 | { | |
3168 | insn = NEXT_INSN (insn); | |
3169 | if (insn == 0 || LABEL_P (insn)) | |
3170 | break; | |
3171 | } | |
23b2ce53 | 3172 | |
75547801 | 3173 | return insn; |
23b2ce53 RS |
3174 | } |
3175 | ||
3176 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
3177 | ||
3178 | rtx | |
502b8322 | 3179 | prev_label (rtx insn) |
23b2ce53 | 3180 | { |
75547801 KG |
3181 | while (insn) |
3182 | { | |
3183 | insn = PREV_INSN (insn); | |
3184 | if (insn == 0 || LABEL_P (insn)) | |
3185 | break; | |
3186 | } | |
23b2ce53 | 3187 | |
75547801 | 3188 | return insn; |
23b2ce53 | 3189 | } |
6c2511d3 RS |
3190 | |
3191 | /* Return the last label to mark the same position as LABEL. Return null | |
3192 | if LABEL itself is null. */ | |
3193 | ||
3194 | rtx | |
3195 | skip_consecutive_labels (rtx label) | |
3196 | { | |
3197 | rtx insn; | |
3198 | ||
3199 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | |
3200 | if (LABEL_P (insn)) | |
3201 | label = insn; | |
3202 | ||
3203 | return label; | |
3204 | } | |
23b2ce53 RS |
3205 | \f |
3206 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
3207 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3208 | and REG_CC_USER notes so we can find it. */ | |
3209 | ||
3210 | void | |
502b8322 | 3211 | link_cc0_insns (rtx insn) |
c572e5ba JVA |
3212 | { |
3213 | rtx user = next_nonnote_insn (insn); | |
3214 | ||
4b4bf941 | 3215 | if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE) |
c572e5ba JVA |
3216 | user = XVECEXP (PATTERN (user), 0, 0); |
3217 | ||
65c5f2a6 ILT |
3218 | add_reg_note (user, REG_CC_SETTER, insn); |
3219 | add_reg_note (insn, REG_CC_USER, user); | |
c572e5ba JVA |
3220 | } |
3221 | ||
23b2ce53 RS |
3222 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3223 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3224 | applied to the result of this function should yield INSN). | |
3225 | ||
3226 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3227 | is present, it contains the insn that uses CC0. | |
3228 | ||
3229 | Return 0 if we can't find the insn. */ | |
3230 | ||
3231 | rtx | |
502b8322 | 3232 | next_cc0_user (rtx insn) |
23b2ce53 | 3233 | { |
906c4e36 | 3234 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3235 | |
3236 | if (note) | |
3237 | return XEXP (note, 0); | |
3238 | ||
3239 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3240 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
23b2ce53 RS |
3241 | insn = XVECEXP (PATTERN (insn), 0, 0); |
3242 | ||
2c3c49de | 3243 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
3244 | return insn; |
3245 | ||
3246 | return 0; | |
3247 | } | |
3248 | ||
3249 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3250 | note, it is the previous insn. */ | |
3251 | ||
3252 | rtx | |
502b8322 | 3253 | prev_cc0_setter (rtx insn) |
23b2ce53 | 3254 | { |
906c4e36 | 3255 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3256 | |
3257 | if (note) | |
3258 | return XEXP (note, 0); | |
3259 | ||
3260 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3261 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 RS |
3262 | |
3263 | return insn; | |
3264 | } | |
3265 | #endif | |
e5bef2e4 | 3266 | |
594f8779 RZ |
3267 | #ifdef AUTO_INC_DEC |
3268 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3269 | ||
3270 | static int | |
3271 | find_auto_inc (rtx *xp, void *data) | |
3272 | { | |
3273 | rtx x = *xp; | |
5ead67f6 | 3274 | rtx reg = (rtx) data; |
594f8779 RZ |
3275 | |
3276 | if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC) | |
3277 | return 0; | |
3278 | ||
3279 | switch (GET_CODE (x)) | |
3280 | { | |
3281 | case PRE_DEC: | |
3282 | case PRE_INC: | |
3283 | case POST_DEC: | |
3284 | case POST_INC: | |
3285 | case PRE_MODIFY: | |
3286 | case POST_MODIFY: | |
3287 | if (rtx_equal_p (reg, XEXP (x, 0))) | |
3288 | return 1; | |
3289 | break; | |
3290 | ||
3291 | default: | |
3292 | gcc_unreachable (); | |
3293 | } | |
3294 | return -1; | |
3295 | } | |
3296 | #endif | |
3297 | ||
e5bef2e4 HB |
3298 | /* Increment the label uses for all labels present in rtx. */ |
3299 | ||
3300 | static void | |
502b8322 | 3301 | mark_label_nuses (rtx x) |
e5bef2e4 | 3302 | { |
b3694847 SS |
3303 | enum rtx_code code; |
3304 | int i, j; | |
3305 | const char *fmt; | |
e5bef2e4 HB |
3306 | |
3307 | code = GET_CODE (x); | |
7537fc90 | 3308 | if (code == LABEL_REF && LABEL_P (XEXP (x, 0))) |
e5bef2e4 HB |
3309 | LABEL_NUSES (XEXP (x, 0))++; |
3310 | ||
3311 | fmt = GET_RTX_FORMAT (code); | |
3312 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3313 | { | |
3314 | if (fmt[i] == 'e') | |
0fb7aeda | 3315 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3316 | else if (fmt[i] == 'E') |
0fb7aeda | 3317 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3318 | mark_label_nuses (XVECEXP (x, i, j)); |
3319 | } | |
3320 | } | |
3321 | ||
23b2ce53 RS |
3322 | \f |
3323 | /* Try splitting insns that can be split for better scheduling. | |
3324 | PAT is the pattern which might split. | |
3325 | TRIAL is the insn providing PAT. | |
cc2902df | 3326 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3327 | |
3328 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3329 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3330 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3331 | ||
3332 | rtx | |
502b8322 | 3333 | try_split (rtx pat, rtx trial, int last) |
23b2ce53 RS |
3334 | { |
3335 | rtx before = PREV_INSN (trial); | |
3336 | rtx after = NEXT_INSN (trial); | |
23b2ce53 | 3337 | int has_barrier = 0; |
4a8cae83 | 3338 | rtx note, seq, tem; |
6b24c259 | 3339 | int probability; |
599aedd9 RH |
3340 | rtx insn_last, insn; |
3341 | int njumps = 0; | |
6b24c259 | 3342 | |
cd9c1ca8 RH |
3343 | /* We're not good at redistributing frame information. */ |
3344 | if (RTX_FRAME_RELATED_P (trial)) | |
3345 | return trial; | |
3346 | ||
6b24c259 JH |
3347 | if (any_condjump_p (trial) |
3348 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3349 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3350 | probability = split_branch_probability; | |
3351 | ||
3352 | seq = split_insns (pat, trial); | |
3353 | ||
3354 | split_branch_probability = -1; | |
23b2ce53 RS |
3355 | |
3356 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3357 | We may need to handle this specially. */ | |
4b4bf941 | 3358 | if (after && BARRIER_P (after)) |
23b2ce53 RS |
3359 | { |
3360 | has_barrier = 1; | |
3361 | after = NEXT_INSN (after); | |
3362 | } | |
3363 | ||
599aedd9 RH |
3364 | if (!seq) |
3365 | return trial; | |
3366 | ||
3367 | /* Avoid infinite loop if any insn of the result matches | |
3368 | the original pattern. */ | |
3369 | insn_last = seq; | |
3370 | while (1) | |
23b2ce53 | 3371 | { |
599aedd9 RH |
3372 | if (INSN_P (insn_last) |
3373 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3374 | return trial; | |
3375 | if (!NEXT_INSN (insn_last)) | |
3376 | break; | |
3377 | insn_last = NEXT_INSN (insn_last); | |
3378 | } | |
750c9258 | 3379 | |
6fb5fa3c DB |
3380 | /* We will be adding the new sequence to the function. The splitters |
3381 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3382 | unshare_all_rtl_in_chain (seq); | |
3383 | ||
599aedd9 RH |
3384 | /* Mark labels. */ |
3385 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3386 | { | |
4b4bf941 | 3387 | if (JUMP_P (insn)) |
599aedd9 RH |
3388 | { |
3389 | mark_jump_label (PATTERN (insn), insn, 0); | |
3390 | njumps++; | |
3391 | if (probability != -1 | |
3392 | && any_condjump_p (insn) | |
3393 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3394 | { |
599aedd9 RH |
3395 | /* We can preserve the REG_BR_PROB notes only if exactly |
3396 | one jump is created, otherwise the machine description | |
3397 | is responsible for this step using | |
3398 | split_branch_probability variable. */ | |
5b0264cb | 3399 | gcc_assert (njumps == 1); |
65c5f2a6 | 3400 | add_reg_note (insn, REG_BR_PROB, GEN_INT (probability)); |
2f937369 | 3401 | } |
599aedd9 RH |
3402 | } |
3403 | } | |
3404 | ||
3405 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3406 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
4b4bf941 | 3407 | if (CALL_P (trial)) |
599aedd9 RH |
3408 | { |
3409 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3410 | if (CALL_P (insn)) |
599aedd9 | 3411 | { |
f6a1f3f6 RH |
3412 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3413 | while (*p) | |
3414 | p = &XEXP (*p, 1); | |
3415 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
599aedd9 RH |
3416 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3417 | } | |
3418 | } | |
4b5e8abe | 3419 | |
599aedd9 RH |
3420 | /* Copy notes, particularly those related to the CFG. */ |
3421 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3422 | { | |
3423 | switch (REG_NOTE_KIND (note)) | |
3424 | { | |
3425 | case REG_EH_REGION: | |
594f8779 | 3426 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3427 | { |
4b4bf941 | 3428 | if (CALL_P (insn) |
d3a583b1 | 3429 | || (flag_non_call_exceptions && INSN_P (insn) |
599aedd9 | 3430 | && may_trap_p (PATTERN (insn)))) |
65c5f2a6 | 3431 | add_reg_note (insn, REG_EH_REGION, XEXP (note, 0)); |
2f937369 | 3432 | } |
599aedd9 | 3433 | break; |
216183ce | 3434 | |
599aedd9 RH |
3435 | case REG_NORETURN: |
3436 | case REG_SETJMP: | |
594f8779 | 3437 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3438 | { |
4b4bf941 | 3439 | if (CALL_P (insn)) |
65c5f2a6 | 3440 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3441 | } |
599aedd9 | 3442 | break; |
d6e95df8 | 3443 | |
599aedd9 | 3444 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3445 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3446 | { |
4b4bf941 | 3447 | if (JUMP_P (insn)) |
65c5f2a6 | 3448 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3449 | } |
599aedd9 | 3450 | break; |
e5bef2e4 | 3451 | |
594f8779 RZ |
3452 | #ifdef AUTO_INC_DEC |
3453 | case REG_INC: | |
3454 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3455 | { | |
3456 | rtx reg = XEXP (note, 0); | |
3457 | if (!FIND_REG_INC_NOTE (insn, reg) | |
3458 | && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0) | |
65c5f2a6 | 3459 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3460 | } |
3461 | break; | |
3462 | #endif | |
3463 | ||
599aedd9 RH |
3464 | default: |
3465 | break; | |
23b2ce53 | 3466 | } |
599aedd9 RH |
3467 | } |
3468 | ||
3469 | /* If there are LABELS inside the split insns increment the | |
3470 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3471 | if (INSN_P (trial)) |
599aedd9 RH |
3472 | { |
3473 | insn = insn_last; | |
3474 | while (insn != NULL_RTX) | |
23b2ce53 | 3475 | { |
cf7c4aa6 | 3476 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3477 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3478 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3479 | |
599aedd9 RH |
3480 | insn = PREV_INSN (insn); |
3481 | } | |
23b2ce53 RS |
3482 | } |
3483 | ||
0435312e | 3484 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
599aedd9 RH |
3485 | |
3486 | delete_insn (trial); | |
3487 | if (has_barrier) | |
3488 | emit_barrier_after (tem); | |
3489 | ||
3490 | /* Recursively call try_split for each new insn created; by the | |
3491 | time control returns here that insn will be fully split, so | |
3492 | set LAST and continue from the insn after the one returned. | |
3493 | We can't use next_active_insn here since AFTER may be a note. | |
3494 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3495 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3496 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3497 | tem = try_split (PATTERN (tem), tem, 1); | |
3498 | ||
3499 | /* Return either the first or the last insn, depending on which was | |
3500 | requested. */ | |
3501 | return last | |
3502 | ? (after ? PREV_INSN (after) : last_insn) | |
3503 | : NEXT_INSN (before); | |
23b2ce53 RS |
3504 | } |
3505 | \f | |
3506 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3507 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
3508 | |
3509 | rtx | |
502b8322 | 3510 | make_insn_raw (rtx pattern) |
23b2ce53 | 3511 | { |
b3694847 | 3512 | rtx insn; |
23b2ce53 | 3513 | |
1f8f4a0b | 3514 | insn = rtx_alloc (INSN); |
23b2ce53 | 3515 | |
43127294 | 3516 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3517 | PATTERN (insn) = pattern; |
3518 | INSN_CODE (insn) = -1; | |
1632afca | 3519 | REG_NOTES (insn) = NULL; |
55e092c4 | 3520 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3521 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3522 | |
47984720 NC |
3523 | #ifdef ENABLE_RTL_CHECKING |
3524 | if (insn | |
2c3c49de | 3525 | && INSN_P (insn) |
47984720 NC |
3526 | && (returnjump_p (insn) |
3527 | || (GET_CODE (insn) == SET | |
3528 | && SET_DEST (insn) == pc_rtx))) | |
3529 | { | |
d4ee4d25 | 3530 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3531 | debug_rtx (insn); |
3532 | } | |
3533 | #endif | |
750c9258 | 3534 | |
23b2ce53 RS |
3535 | return insn; |
3536 | } | |
3537 | ||
2f937369 | 3538 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3539 | |
38109dab | 3540 | rtx |
502b8322 | 3541 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3542 | { |
b3694847 | 3543 | rtx insn; |
23b2ce53 | 3544 | |
4b1f5e8c | 3545 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 3546 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3547 | |
3548 | PATTERN (insn) = pattern; | |
3549 | INSN_CODE (insn) = -1; | |
1632afca RS |
3550 | REG_NOTES (insn) = NULL; |
3551 | JUMP_LABEL (insn) = NULL; | |
55e092c4 | 3552 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3553 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3554 | |
3555 | return insn; | |
3556 | } | |
aff507f4 | 3557 | |
2f937369 | 3558 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 RK |
3559 | |
3560 | static rtx | |
502b8322 | 3561 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3562 | { |
b3694847 | 3563 | rtx insn; |
aff507f4 RK |
3564 | |
3565 | insn = rtx_alloc (CALL_INSN); | |
3566 | INSN_UID (insn) = cur_insn_uid++; | |
3567 | ||
3568 | PATTERN (insn) = pattern; | |
3569 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3570 | REG_NOTES (insn) = NULL; |
3571 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
55e092c4 | 3572 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3573 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3574 | |
3575 | return insn; | |
3576 | } | |
23b2ce53 RS |
3577 | \f |
3578 | /* Add INSN to the end of the doubly-linked list. | |
3579 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3580 | ||
3581 | void | |
502b8322 | 3582 | add_insn (rtx insn) |
23b2ce53 RS |
3583 | { |
3584 | PREV_INSN (insn) = last_insn; | |
3585 | NEXT_INSN (insn) = 0; | |
3586 | ||
3587 | if (NULL != last_insn) | |
3588 | NEXT_INSN (last_insn) = insn; | |
3589 | ||
3590 | if (NULL == first_insn) | |
3591 | first_insn = insn; | |
3592 | ||
3593 | last_insn = insn; | |
3594 | } | |
3595 | ||
a0ae8e8d RK |
3596 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3597 | the next should be the only functions called to insert an insn once | |
ba213285 | 3598 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 3599 | SEQUENCE. */ |
23b2ce53 RS |
3600 | |
3601 | void | |
6fb5fa3c | 3602 | add_insn_after (rtx insn, rtx after, basic_block bb) |
23b2ce53 RS |
3603 | { |
3604 | rtx next = NEXT_INSN (after); | |
3605 | ||
5b0264cb | 3606 | gcc_assert (!optimize || !INSN_DELETED_P (after)); |
ba213285 | 3607 | |
23b2ce53 RS |
3608 | NEXT_INSN (insn) = next; |
3609 | PREV_INSN (insn) = after; | |
3610 | ||
3611 | if (next) | |
3612 | { | |
3613 | PREV_INSN (next) = insn; | |
4b4bf941 | 3614 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
23b2ce53 RS |
3615 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; |
3616 | } | |
3617 | else if (last_insn == after) | |
3618 | last_insn = insn; | |
3619 | else | |
3620 | { | |
49ad7cfa | 3621 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
3622 | /* Scan all pending sequences too. */ |
3623 | for (; stack; stack = stack->next) | |
3624 | if (after == stack->last) | |
fef0509b RK |
3625 | { |
3626 | stack->last = insn; | |
3627 | break; | |
3628 | } | |
a0ae8e8d | 3629 | |
5b0264cb | 3630 | gcc_assert (stack); |
23b2ce53 RS |
3631 | } |
3632 | ||
4b4bf941 JQ |
3633 | if (!BARRIER_P (after) |
3634 | && !BARRIER_P (insn) | |
3c030e88 JH |
3635 | && (bb = BLOCK_FOR_INSN (after))) |
3636 | { | |
3637 | set_block_for_insn (insn, bb); | |
38c1593d | 3638 | if (INSN_P (insn)) |
6fb5fa3c | 3639 | df_insn_rescan (insn); |
3c030e88 | 3640 | /* Should not happen as first in the BB is always |
a1f300c0 | 3641 | either NOTE or LABEL. */ |
a813c111 | 3642 | if (BB_END (bb) == after |
3c030e88 | 3643 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 3644 | && !BARRIER_P (insn) |
a38e7aa5 | 3645 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
a813c111 | 3646 | BB_END (bb) = insn; |
3c030e88 JH |
3647 | } |
3648 | ||
23b2ce53 | 3649 | NEXT_INSN (after) = insn; |
4b4bf941 | 3650 | if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE) |
23b2ce53 RS |
3651 | { |
3652 | rtx sequence = PATTERN (after); | |
3653 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3654 | } | |
3655 | } | |
3656 | ||
a0ae8e8d | 3657 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
6fb5fa3c DB |
3658 | the previous should be the only functions called to insert an insn |
3659 | once delay slots have been filled since only they know how to | |
3660 | update a SEQUENCE. If BB is NULL, an attempt is made to infer the | |
3661 | bb from before. */ | |
a0ae8e8d RK |
3662 | |
3663 | void | |
6fb5fa3c | 3664 | add_insn_before (rtx insn, rtx before, basic_block bb) |
a0ae8e8d RK |
3665 | { |
3666 | rtx prev = PREV_INSN (before); | |
3667 | ||
5b0264cb | 3668 | gcc_assert (!optimize || !INSN_DELETED_P (before)); |
ba213285 | 3669 | |
a0ae8e8d RK |
3670 | PREV_INSN (insn) = prev; |
3671 | NEXT_INSN (insn) = before; | |
3672 | ||
3673 | if (prev) | |
3674 | { | |
3675 | NEXT_INSN (prev) = insn; | |
4b4bf941 | 3676 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
a0ae8e8d RK |
3677 | { |
3678 | rtx sequence = PATTERN (prev); | |
3679 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3680 | } | |
3681 | } | |
3682 | else if (first_insn == before) | |
3683 | first_insn = insn; | |
3684 | else | |
3685 | { | |
49ad7cfa | 3686 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
3687 | /* Scan all pending sequences too. */ |
3688 | for (; stack; stack = stack->next) | |
3689 | if (before == stack->first) | |
fef0509b RK |
3690 | { |
3691 | stack->first = insn; | |
3692 | break; | |
3693 | } | |
a0ae8e8d | 3694 | |
5b0264cb | 3695 | gcc_assert (stack); |
a0ae8e8d RK |
3696 | } |
3697 | ||
6fb5fa3c DB |
3698 | if (!bb |
3699 | && !BARRIER_P (before) | |
3700 | && !BARRIER_P (insn)) | |
3701 | bb = BLOCK_FOR_INSN (before); | |
3702 | ||
3703 | if (bb) | |
3c030e88 JH |
3704 | { |
3705 | set_block_for_insn (insn, bb); | |
38c1593d | 3706 | if (INSN_P (insn)) |
6fb5fa3c | 3707 | df_insn_rescan (insn); |
5b0264cb | 3708 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 3709 | LABEL. */ |
5b0264cb NS |
3710 | gcc_assert (BB_HEAD (bb) != insn |
3711 | /* Avoid clobbering of structure when creating new BB. */ | |
3712 | || BARRIER_P (insn) | |
a38e7aa5 | 3713 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 JH |
3714 | } |
3715 | ||
a0ae8e8d | 3716 | PREV_INSN (before) = insn; |
4b4bf941 | 3717 | if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE) |
a0ae8e8d RK |
3718 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; |
3719 | } | |
3720 | ||
6fb5fa3c DB |
3721 | |
3722 | /* Replace insn with an deleted instruction note. */ | |
3723 | ||
0ce2b299 EB |
3724 | void |
3725 | set_insn_deleted (rtx insn) | |
6fb5fa3c DB |
3726 | { |
3727 | df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn)); | |
3728 | PUT_CODE (insn, NOTE); | |
3729 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
3730 | } | |
3731 | ||
3732 | ||
89e99eea DB |
3733 | /* Remove an insn from its doubly-linked list. This function knows how |
3734 | to handle sequences. */ | |
3735 | void | |
502b8322 | 3736 | remove_insn (rtx insn) |
89e99eea DB |
3737 | { |
3738 | rtx next = NEXT_INSN (insn); | |
3739 | rtx prev = PREV_INSN (insn); | |
53c17031 JH |
3740 | basic_block bb; |
3741 | ||
6fb5fa3c DB |
3742 | /* Later in the code, the block will be marked dirty. */ |
3743 | df_insn_delete (NULL, INSN_UID (insn)); | |
3744 | ||
89e99eea DB |
3745 | if (prev) |
3746 | { | |
3747 | NEXT_INSN (prev) = next; | |
4b4bf941 | 3748 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea DB |
3749 | { |
3750 | rtx sequence = PATTERN (prev); | |
3751 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3752 | } | |
3753 | } | |
3754 | else if (first_insn == insn) | |
3755 | first_insn = next; | |
3756 | else | |
3757 | { | |
49ad7cfa | 3758 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3759 | /* Scan all pending sequences too. */ |
3760 | for (; stack; stack = stack->next) | |
3761 | if (insn == stack->first) | |
3762 | { | |
3763 | stack->first = next; | |
3764 | break; | |
3765 | } | |
3766 | ||
5b0264cb | 3767 | gcc_assert (stack); |
89e99eea DB |
3768 | } |
3769 | ||
3770 | if (next) | |
3771 | { | |
3772 | PREV_INSN (next) = prev; | |
4b4bf941 | 3773 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
89e99eea DB |
3774 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; |
3775 | } | |
3776 | else if (last_insn == insn) | |
3777 | last_insn = prev; | |
3778 | else | |
3779 | { | |
49ad7cfa | 3780 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3781 | /* Scan all pending sequences too. */ |
3782 | for (; stack; stack = stack->next) | |
3783 | if (insn == stack->last) | |
3784 | { | |
3785 | stack->last = prev; | |
3786 | break; | |
3787 | } | |
3788 | ||
5b0264cb | 3789 | gcc_assert (stack); |
89e99eea | 3790 | } |
4b4bf941 | 3791 | if (!BARRIER_P (insn) |
53c17031 JH |
3792 | && (bb = BLOCK_FOR_INSN (insn))) |
3793 | { | |
38c1593d | 3794 | if (INSN_P (insn)) |
6fb5fa3c | 3795 | df_set_bb_dirty (bb); |
a813c111 | 3796 | if (BB_HEAD (bb) == insn) |
53c17031 | 3797 | { |
3bf1e984 RK |
3798 | /* Never ever delete the basic block note without deleting whole |
3799 | basic block. */ | |
5b0264cb | 3800 | gcc_assert (!NOTE_P (insn)); |
a813c111 | 3801 | BB_HEAD (bb) = next; |
53c17031 | 3802 | } |
a813c111 SB |
3803 | if (BB_END (bb) == insn) |
3804 | BB_END (bb) = prev; | |
53c17031 | 3805 | } |
89e99eea DB |
3806 | } |
3807 | ||
ee960939 OH |
3808 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3809 | ||
3810 | void | |
502b8322 | 3811 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 3812 | { |
5b0264cb | 3813 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
3814 | |
3815 | /* Put the register usage information on the CALL. If there is already | |
3816 | some usage information, put ours at the end. */ | |
3817 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3818 | { | |
3819 | rtx link; | |
3820 | ||
3821 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3822 | link = XEXP (link, 1)) | |
3823 | ; | |
3824 | ||
3825 | XEXP (link, 1) = call_fusage; | |
3826 | } | |
3827 | else | |
3828 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3829 | } | |
3830 | ||
23b2ce53 RS |
3831 | /* Delete all insns made since FROM. |
3832 | FROM becomes the new last instruction. */ | |
3833 | ||
3834 | void | |
502b8322 | 3835 | delete_insns_since (rtx from) |
23b2ce53 RS |
3836 | { |
3837 | if (from == 0) | |
3838 | first_insn = 0; | |
3839 | else | |
3840 | NEXT_INSN (from) = 0; | |
3841 | last_insn = from; | |
3842 | } | |
3843 | ||
5dab5552 MS |
3844 | /* This function is deprecated, please use sequences instead. |
3845 | ||
3846 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
3847 | The insns to be moved are those between FROM and TO. |
3848 | They are moved to a new position after the insn AFTER. | |
3849 | AFTER must not be FROM or TO or any insn in between. | |
3850 | ||
3851 | This function does not know about SEQUENCEs and hence should not be | |
3852 | called after delay-slot filling has been done. */ | |
3853 | ||
3854 | void | |
502b8322 | 3855 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
23b2ce53 RS |
3856 | { |
3857 | /* Splice this bunch out of where it is now. */ | |
3858 | if (PREV_INSN (from)) | |
3859 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3860 | if (NEXT_INSN (to)) | |
3861 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
3862 | if (last_insn == to) | |
3863 | last_insn = PREV_INSN (from); | |
3864 | if (first_insn == from) | |
3865 | first_insn = NEXT_INSN (to); | |
3866 | ||
3867 | /* Make the new neighbors point to it and it to them. */ | |
3868 | if (NEXT_INSN (after)) | |
3869 | PREV_INSN (NEXT_INSN (after)) = to; | |
3870 | ||
3871 | NEXT_INSN (to) = NEXT_INSN (after); | |
3872 | PREV_INSN (from) = after; | |
3873 | NEXT_INSN (after) = from; | |
3874 | if (after == last_insn) | |
3875 | last_insn = to; | |
3876 | } | |
3877 | ||
3c030e88 JH |
3878 | /* Same as function above, but take care to update BB boundaries. */ |
3879 | void | |
502b8322 | 3880 | reorder_insns (rtx from, rtx to, rtx after) |
3c030e88 JH |
3881 | { |
3882 | rtx prev = PREV_INSN (from); | |
3883 | basic_block bb, bb2; | |
3884 | ||
3885 | reorder_insns_nobb (from, to, after); | |
3886 | ||
4b4bf941 | 3887 | if (!BARRIER_P (after) |
3c030e88 JH |
3888 | && (bb = BLOCK_FOR_INSN (after))) |
3889 | { | |
3890 | rtx x; | |
6fb5fa3c | 3891 | df_set_bb_dirty (bb); |
68252e27 | 3892 | |
4b4bf941 | 3893 | if (!BARRIER_P (from) |
3c030e88 JH |
3894 | && (bb2 = BLOCK_FOR_INSN (from))) |
3895 | { | |
a813c111 SB |
3896 | if (BB_END (bb2) == to) |
3897 | BB_END (bb2) = prev; | |
6fb5fa3c | 3898 | df_set_bb_dirty (bb2); |
3c030e88 JH |
3899 | } |
3900 | ||
a813c111 SB |
3901 | if (BB_END (bb) == after) |
3902 | BB_END (bb) = to; | |
3c030e88 JH |
3903 | |
3904 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 3905 | if (!BARRIER_P (x)) |
63642d5a | 3906 | df_insn_change_bb (x, bb); |
3c030e88 JH |
3907 | } |
3908 | } | |
3909 | ||
23b2ce53 | 3910 | \f |
2f937369 DM |
3911 | /* Emit insn(s) of given code and pattern |
3912 | at a specified place within the doubly-linked list. | |
23b2ce53 | 3913 | |
2f937369 DM |
3914 | All of the emit_foo global entry points accept an object |
3915 | X which is either an insn list or a PATTERN of a single | |
3916 | instruction. | |
23b2ce53 | 3917 | |
2f937369 DM |
3918 | There are thus a few canonical ways to generate code and |
3919 | emit it at a specific place in the instruction stream. For | |
3920 | example, consider the instruction named SPOT and the fact that | |
3921 | we would like to emit some instructions before SPOT. We might | |
3922 | do it like this: | |
23b2ce53 | 3923 | |
2f937369 DM |
3924 | start_sequence (); |
3925 | ... emit the new instructions ... | |
3926 | insns_head = get_insns (); | |
3927 | end_sequence (); | |
23b2ce53 | 3928 | |
2f937369 | 3929 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 3930 | |
2f937369 DM |
3931 | It used to be common to generate SEQUENCE rtl instead, but that |
3932 | is a relic of the past which no longer occurs. The reason is that | |
3933 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
3934 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 3935 | |
2f937369 | 3936 | /* Make X be output before the instruction BEFORE. */ |
23b2ce53 RS |
3937 | |
3938 | rtx | |
6fb5fa3c | 3939 | emit_insn_before_noloc (rtx x, rtx before, basic_block bb) |
23b2ce53 | 3940 | { |
2f937369 | 3941 | rtx last = before; |
b3694847 | 3942 | rtx insn; |
23b2ce53 | 3943 | |
5b0264cb | 3944 | gcc_assert (before); |
2f937369 DM |
3945 | |
3946 | if (x == NULL_RTX) | |
3947 | return last; | |
3948 | ||
3949 | switch (GET_CODE (x)) | |
23b2ce53 | 3950 | { |
2f937369 DM |
3951 | case INSN: |
3952 | case JUMP_INSN: | |
3953 | case CALL_INSN: | |
3954 | case CODE_LABEL: | |
3955 | case BARRIER: | |
3956 | case NOTE: | |
3957 | insn = x; | |
3958 | while (insn) | |
3959 | { | |
3960 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 3961 | add_insn_before (insn, before, bb); |
2f937369 DM |
3962 | last = insn; |
3963 | insn = next; | |
3964 | } | |
3965 | break; | |
3966 | ||
3967 | #ifdef ENABLE_RTL_CHECKING | |
3968 | case SEQUENCE: | |
5b0264cb | 3969 | gcc_unreachable (); |
2f937369 DM |
3970 | break; |
3971 | #endif | |
3972 | ||
3973 | default: | |
3974 | last = make_insn_raw (x); | |
6fb5fa3c | 3975 | add_insn_before (last, before, bb); |
2f937369 | 3976 | break; |
23b2ce53 RS |
3977 | } |
3978 | ||
2f937369 | 3979 | return last; |
23b2ce53 RS |
3980 | } |
3981 | ||
2f937369 | 3982 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
3983 | and output it before the instruction BEFORE. */ |
3984 | ||
3985 | rtx | |
a7102479 | 3986 | emit_jump_insn_before_noloc (rtx x, rtx before) |
23b2ce53 | 3987 | { |
d950dee3 | 3988 | rtx insn, last = NULL_RTX; |
aff507f4 | 3989 | |
5b0264cb | 3990 | gcc_assert (before); |
2f937369 DM |
3991 | |
3992 | switch (GET_CODE (x)) | |
aff507f4 | 3993 | { |
2f937369 DM |
3994 | case INSN: |
3995 | case JUMP_INSN: | |
3996 | case CALL_INSN: | |
3997 | case CODE_LABEL: | |
3998 | case BARRIER: | |
3999 | case NOTE: | |
4000 | insn = x; | |
4001 | while (insn) | |
4002 | { | |
4003 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4004 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4005 | last = insn; |
4006 | insn = next; | |
4007 | } | |
4008 | break; | |
4009 | ||
4010 | #ifdef ENABLE_RTL_CHECKING | |
4011 | case SEQUENCE: | |
5b0264cb | 4012 | gcc_unreachable (); |
2f937369 DM |
4013 | break; |
4014 | #endif | |
4015 | ||
4016 | default: | |
4017 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4018 | add_insn_before (last, before, NULL); |
2f937369 | 4019 | break; |
aff507f4 RK |
4020 | } |
4021 | ||
2f937369 | 4022 | return last; |
23b2ce53 RS |
4023 | } |
4024 | ||
2f937369 | 4025 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4026 | and output it before the instruction BEFORE. */ |
4027 | ||
4028 | rtx | |
a7102479 | 4029 | emit_call_insn_before_noloc (rtx x, rtx before) |
969d70ca | 4030 | { |
d950dee3 | 4031 | rtx last = NULL_RTX, insn; |
969d70ca | 4032 | |
5b0264cb | 4033 | gcc_assert (before); |
2f937369 DM |
4034 | |
4035 | switch (GET_CODE (x)) | |
969d70ca | 4036 | { |
2f937369 DM |
4037 | case INSN: |
4038 | case JUMP_INSN: | |
4039 | case CALL_INSN: | |
4040 | case CODE_LABEL: | |
4041 | case BARRIER: | |
4042 | case NOTE: | |
4043 | insn = x; | |
4044 | while (insn) | |
4045 | { | |
4046 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4047 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4048 | last = insn; |
4049 | insn = next; | |
4050 | } | |
4051 | break; | |
4052 | ||
4053 | #ifdef ENABLE_RTL_CHECKING | |
4054 | case SEQUENCE: | |
5b0264cb | 4055 | gcc_unreachable (); |
2f937369 DM |
4056 | break; |
4057 | #endif | |
4058 | ||
4059 | default: | |
4060 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4061 | add_insn_before (last, before, NULL); |
2f937369 | 4062 | break; |
969d70ca JH |
4063 | } |
4064 | ||
2f937369 | 4065 | return last; |
969d70ca JH |
4066 | } |
4067 | ||
23b2ce53 | 4068 | /* Make an insn of code BARRIER |
e881bb1b | 4069 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
4070 | |
4071 | rtx | |
502b8322 | 4072 | emit_barrier_before (rtx before) |
23b2ce53 | 4073 | { |
b3694847 | 4074 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4075 | |
4076 | INSN_UID (insn) = cur_insn_uid++; | |
4077 | ||
6fb5fa3c | 4078 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4079 | return insn; |
4080 | } | |
4081 | ||
e881bb1b RH |
4082 | /* Emit the label LABEL before the insn BEFORE. */ |
4083 | ||
4084 | rtx | |
502b8322 | 4085 | emit_label_before (rtx label, rtx before) |
e881bb1b RH |
4086 | { |
4087 | /* This can be called twice for the same label as a result of the | |
4088 | confusion that follows a syntax error! So make it harmless. */ | |
4089 | if (INSN_UID (label) == 0) | |
4090 | { | |
4091 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4092 | add_insn_before (label, before, NULL); |
e881bb1b RH |
4093 | } |
4094 | ||
4095 | return label; | |
4096 | } | |
4097 | ||
23b2ce53 RS |
4098 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
4099 | ||
4100 | rtx | |
a38e7aa5 | 4101 | emit_note_before (enum insn_note subtype, rtx before) |
23b2ce53 | 4102 | { |
b3694847 | 4103 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4104 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4105 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4106 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4107 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
23b2ce53 | 4108 | |
6fb5fa3c | 4109 | add_insn_before (note, before, NULL); |
23b2ce53 RS |
4110 | return note; |
4111 | } | |
4112 | \f | |
2f937369 DM |
4113 | /* Helper for emit_insn_after, handles lists of instructions |
4114 | efficiently. */ | |
23b2ce53 | 4115 | |
2f937369 | 4116 | static rtx |
6fb5fa3c | 4117 | emit_insn_after_1 (rtx first, rtx after, basic_block bb) |
23b2ce53 | 4118 | { |
2f937369 DM |
4119 | rtx last; |
4120 | rtx after_after; | |
6fb5fa3c DB |
4121 | if (!bb && !BARRIER_P (after)) |
4122 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4123 | |
6fb5fa3c | 4124 | if (bb) |
23b2ce53 | 4125 | { |
6fb5fa3c | 4126 | df_set_bb_dirty (bb); |
2f937369 | 4127 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4128 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4129 | { |
4130 | set_block_for_insn (last, bb); | |
4131 | df_insn_rescan (last); | |
4132 | } | |
4b4bf941 | 4133 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4134 | { |
4135 | set_block_for_insn (last, bb); | |
4136 | df_insn_rescan (last); | |
4137 | } | |
a813c111 SB |
4138 | if (BB_END (bb) == after) |
4139 | BB_END (bb) = last; | |
23b2ce53 RS |
4140 | } |
4141 | else | |
2f937369 DM |
4142 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4143 | continue; | |
4144 | ||
4145 | after_after = NEXT_INSN (after); | |
4146 | ||
4147 | NEXT_INSN (after) = first; | |
4148 | PREV_INSN (first) = after; | |
4149 | NEXT_INSN (last) = after_after; | |
4150 | if (after_after) | |
4151 | PREV_INSN (after_after) = last; | |
4152 | ||
4153 | if (after == last_insn) | |
4154 | last_insn = last; | |
e855c69d | 4155 | |
2f937369 DM |
4156 | return last; |
4157 | } | |
4158 | ||
6fb5fa3c DB |
4159 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4160 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
2f937369 DM |
4161 | |
4162 | rtx | |
6fb5fa3c | 4163 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
2f937369 DM |
4164 | { |
4165 | rtx last = after; | |
4166 | ||
5b0264cb | 4167 | gcc_assert (after); |
2f937369 DM |
4168 | |
4169 | if (x == NULL_RTX) | |
4170 | return last; | |
4171 | ||
4172 | switch (GET_CODE (x)) | |
23b2ce53 | 4173 | { |
2f937369 DM |
4174 | case INSN: |
4175 | case JUMP_INSN: | |
4176 | case CALL_INSN: | |
4177 | case CODE_LABEL: | |
4178 | case BARRIER: | |
4179 | case NOTE: | |
6fb5fa3c | 4180 | last = emit_insn_after_1 (x, after, bb); |
2f937369 DM |
4181 | break; |
4182 | ||
4183 | #ifdef ENABLE_RTL_CHECKING | |
4184 | case SEQUENCE: | |
5b0264cb | 4185 | gcc_unreachable (); |
2f937369 DM |
4186 | break; |
4187 | #endif | |
4188 | ||
4189 | default: | |
4190 | last = make_insn_raw (x); | |
6fb5fa3c | 4191 | add_insn_after (last, after, bb); |
2f937369 | 4192 | break; |
23b2ce53 RS |
4193 | } |
4194 | ||
2f937369 | 4195 | return last; |
23b2ce53 RS |
4196 | } |
4197 | ||
255680cf | 4198 | |
2f937369 | 4199 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4200 | and output it after the insn AFTER. */ |
4201 | ||
4202 | rtx | |
a7102479 | 4203 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4204 | { |
2f937369 | 4205 | rtx last; |
23b2ce53 | 4206 | |
5b0264cb | 4207 | gcc_assert (after); |
2f937369 DM |
4208 | |
4209 | switch (GET_CODE (x)) | |
23b2ce53 | 4210 | { |
2f937369 DM |
4211 | case INSN: |
4212 | case JUMP_INSN: | |
4213 | case CALL_INSN: | |
4214 | case CODE_LABEL: | |
4215 | case BARRIER: | |
4216 | case NOTE: | |
6fb5fa3c | 4217 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4218 | break; |
4219 | ||
4220 | #ifdef ENABLE_RTL_CHECKING | |
4221 | case SEQUENCE: | |
5b0264cb | 4222 | gcc_unreachable (); |
2f937369 DM |
4223 | break; |
4224 | #endif | |
4225 | ||
4226 | default: | |
4227 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4228 | add_insn_after (last, after, NULL); |
2f937369 | 4229 | break; |
23b2ce53 RS |
4230 | } |
4231 | ||
2f937369 DM |
4232 | return last; |
4233 | } | |
4234 | ||
4235 | /* Make an instruction with body X and code CALL_INSN | |
4236 | and output it after the instruction AFTER. */ | |
4237 | ||
4238 | rtx | |
a7102479 | 4239 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 DM |
4240 | { |
4241 | rtx last; | |
4242 | ||
5b0264cb | 4243 | gcc_assert (after); |
2f937369 DM |
4244 | |
4245 | switch (GET_CODE (x)) | |
4246 | { | |
4247 | case INSN: | |
4248 | case JUMP_INSN: | |
4249 | case CALL_INSN: | |
4250 | case CODE_LABEL: | |
4251 | case BARRIER: | |
4252 | case NOTE: | |
6fb5fa3c | 4253 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4254 | break; |
4255 | ||
4256 | #ifdef ENABLE_RTL_CHECKING | |
4257 | case SEQUENCE: | |
5b0264cb | 4258 | gcc_unreachable (); |
2f937369 DM |
4259 | break; |
4260 | #endif | |
4261 | ||
4262 | default: | |
4263 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4264 | add_insn_after (last, after, NULL); |
2f937369 DM |
4265 | break; |
4266 | } | |
4267 | ||
4268 | return last; | |
23b2ce53 RS |
4269 | } |
4270 | ||
4271 | /* Make an insn of code BARRIER | |
4272 | and output it after the insn AFTER. */ | |
4273 | ||
4274 | rtx | |
502b8322 | 4275 | emit_barrier_after (rtx after) |
23b2ce53 | 4276 | { |
b3694847 | 4277 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4278 | |
4279 | INSN_UID (insn) = cur_insn_uid++; | |
4280 | ||
6fb5fa3c | 4281 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4282 | return insn; |
4283 | } | |
4284 | ||
4285 | /* Emit the label LABEL after the insn AFTER. */ | |
4286 | ||
4287 | rtx | |
502b8322 | 4288 | emit_label_after (rtx label, rtx after) |
23b2ce53 RS |
4289 | { |
4290 | /* This can be called twice for the same label | |
4291 | as a result of the confusion that follows a syntax error! | |
4292 | So make it harmless. */ | |
4293 | if (INSN_UID (label) == 0) | |
4294 | { | |
4295 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4296 | add_insn_after (label, after, NULL); |
23b2ce53 RS |
4297 | } |
4298 | ||
4299 | return label; | |
4300 | } | |
4301 | ||
4302 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4303 | ||
4304 | rtx | |
a38e7aa5 | 4305 | emit_note_after (enum insn_note subtype, rtx after) |
23b2ce53 | 4306 | { |
b3694847 | 4307 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4308 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4309 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4310 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4311 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
6fb5fa3c | 4312 | add_insn_after (note, after, NULL); |
23b2ce53 RS |
4313 | return note; |
4314 | } | |
23b2ce53 | 4315 | \f |
a7102479 | 4316 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4317 | rtx |
502b8322 | 4318 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4319 | { |
6fb5fa3c | 4320 | rtx last = emit_insn_after_noloc (pattern, after, NULL); |
0d682900 | 4321 | |
a7102479 | 4322 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4323 | return last; |
4324 | ||
2f937369 DM |
4325 | after = NEXT_INSN (after); |
4326 | while (1) | |
4327 | { | |
a7102479 | 4328 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4329 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4330 | if (after == last) |
4331 | break; | |
4332 | after = NEXT_INSN (after); | |
4333 | } | |
0d682900 JH |
4334 | return last; |
4335 | } | |
4336 | ||
a7102479 JH |
4337 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4338 | rtx | |
4339 | emit_insn_after (rtx pattern, rtx after) | |
4340 | { | |
4341 | if (INSN_P (after)) | |
4342 | return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4343 | else | |
6fb5fa3c | 4344 | return emit_insn_after_noloc (pattern, after, NULL); |
a7102479 JH |
4345 | } |
4346 | ||
4347 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4348 | rtx |
502b8322 | 4349 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4350 | { |
a7102479 | 4351 | rtx last = emit_jump_insn_after_noloc (pattern, after); |
2f937369 | 4352 | |
a7102479 | 4353 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4354 | return last; |
4355 | ||
2f937369 DM |
4356 | after = NEXT_INSN (after); |
4357 | while (1) | |
4358 | { | |
a7102479 | 4359 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4360 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4361 | if (after == last) |
4362 | break; | |
4363 | after = NEXT_INSN (after); | |
4364 | } | |
0d682900 JH |
4365 | return last; |
4366 | } | |
4367 | ||
a7102479 JH |
4368 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4369 | rtx | |
4370 | emit_jump_insn_after (rtx pattern, rtx after) | |
4371 | { | |
4372 | if (INSN_P (after)) | |
4373 | return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4374 | else | |
4375 | return emit_jump_insn_after_noloc (pattern, after); | |
4376 | } | |
4377 | ||
4378 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4379 | rtx |
502b8322 | 4380 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4381 | { |
a7102479 | 4382 | rtx last = emit_call_insn_after_noloc (pattern, after); |
2f937369 | 4383 | |
a7102479 | 4384 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4385 | return last; |
4386 | ||
2f937369 DM |
4387 | after = NEXT_INSN (after); |
4388 | while (1) | |
4389 | { | |
a7102479 | 4390 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4391 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4392 | if (after == last) |
4393 | break; | |
4394 | after = NEXT_INSN (after); | |
4395 | } | |
0d682900 JH |
4396 | return last; |
4397 | } | |
4398 | ||
a7102479 JH |
4399 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4400 | rtx | |
4401 | emit_call_insn_after (rtx pattern, rtx after) | |
4402 | { | |
4403 | if (INSN_P (after)) | |
4404 | return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4405 | else | |
4406 | return emit_call_insn_after_noloc (pattern, after); | |
4407 | } | |
4408 | ||
4409 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4410 | rtx |
502b8322 | 4411 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
0d682900 JH |
4412 | { |
4413 | rtx first = PREV_INSN (before); | |
6fb5fa3c | 4414 | rtx last = emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4415 | |
4416 | if (pattern == NULL_RTX || !loc) | |
4417 | return last; | |
4418 | ||
26cb3993 JH |
4419 | if (!first) |
4420 | first = get_insns (); | |
4421 | else | |
4422 | first = NEXT_INSN (first); | |
a7102479 JH |
4423 | while (1) |
4424 | { | |
4425 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4426 | INSN_LOCATOR (first) = loc; | |
4427 | if (first == last) | |
4428 | break; | |
4429 | first = NEXT_INSN (first); | |
4430 | } | |
4431 | return last; | |
4432 | } | |
4433 | ||
4434 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4435 | rtx | |
4436 | emit_insn_before (rtx pattern, rtx before) | |
4437 | { | |
4438 | if (INSN_P (before)) | |
4439 | return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4440 | else | |
6fb5fa3c | 4441 | return emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4442 | } |
4443 | ||
4444 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4445 | rtx | |
4446 | emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4447 | { | |
4448 | rtx first = PREV_INSN (before); | |
4449 | rtx last = emit_jump_insn_before_noloc (pattern, before); | |
4450 | ||
4451 | if (pattern == NULL_RTX) | |
4452 | return last; | |
4453 | ||
4454 | first = NEXT_INSN (first); | |
4455 | while (1) | |
4456 | { | |
4457 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4458 | INSN_LOCATOR (first) = loc; | |
4459 | if (first == last) | |
4460 | break; | |
4461 | first = NEXT_INSN (first); | |
4462 | } | |
4463 | return last; | |
4464 | } | |
4465 | ||
4466 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4467 | rtx | |
4468 | emit_jump_insn_before (rtx pattern, rtx before) | |
4469 | { | |
4470 | if (INSN_P (before)) | |
4471 | return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4472 | else | |
4473 | return emit_jump_insn_before_noloc (pattern, before); | |
4474 | } | |
4475 | ||
4476 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4477 | rtx | |
4478 | emit_call_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4479 | { | |
4480 | rtx first = PREV_INSN (before); | |
4481 | rtx last = emit_call_insn_before_noloc (pattern, before); | |
0d682900 | 4482 | |
dd3adcf8 DJ |
4483 | if (pattern == NULL_RTX) |
4484 | return last; | |
4485 | ||
2f937369 DM |
4486 | first = NEXT_INSN (first); |
4487 | while (1) | |
4488 | { | |
a7102479 | 4489 | if (active_insn_p (first) && !INSN_LOCATOR (first)) |
0435312e | 4490 | INSN_LOCATOR (first) = loc; |
2f937369 DM |
4491 | if (first == last) |
4492 | break; | |
4493 | first = NEXT_INSN (first); | |
4494 | } | |
0d682900 JH |
4495 | return last; |
4496 | } | |
a7102479 JH |
4497 | |
4498 | /* like emit_call_insn_before_noloc, | |
4499 | but set insn_locator according to before. */ | |
4500 | rtx | |
4501 | emit_call_insn_before (rtx pattern, rtx before) | |
4502 | { | |
4503 | if (INSN_P (before)) | |
4504 | return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4505 | else | |
4506 | return emit_call_insn_before_noloc (pattern, before); | |
4507 | } | |
0d682900 | 4508 | \f |
2f937369 DM |
4509 | /* Take X and emit it at the end of the doubly-linked |
4510 | INSN list. | |
23b2ce53 RS |
4511 | |
4512 | Returns the last insn emitted. */ | |
4513 | ||
4514 | rtx | |
502b8322 | 4515 | emit_insn (rtx x) |
23b2ce53 | 4516 | { |
2f937369 DM |
4517 | rtx last = last_insn; |
4518 | rtx insn; | |
23b2ce53 | 4519 | |
2f937369 DM |
4520 | if (x == NULL_RTX) |
4521 | return last; | |
23b2ce53 | 4522 | |
2f937369 DM |
4523 | switch (GET_CODE (x)) |
4524 | { | |
4525 | case INSN: | |
4526 | case JUMP_INSN: | |
4527 | case CALL_INSN: | |
4528 | case CODE_LABEL: | |
4529 | case BARRIER: | |
4530 | case NOTE: | |
4531 | insn = x; | |
4532 | while (insn) | |
23b2ce53 | 4533 | { |
2f937369 | 4534 | rtx next = NEXT_INSN (insn); |
23b2ce53 | 4535 | add_insn (insn); |
2f937369 DM |
4536 | last = insn; |
4537 | insn = next; | |
23b2ce53 | 4538 | } |
2f937369 | 4539 | break; |
23b2ce53 | 4540 | |
2f937369 DM |
4541 | #ifdef ENABLE_RTL_CHECKING |
4542 | case SEQUENCE: | |
5b0264cb | 4543 | gcc_unreachable (); |
2f937369 DM |
4544 | break; |
4545 | #endif | |
23b2ce53 | 4546 | |
2f937369 DM |
4547 | default: |
4548 | last = make_insn_raw (x); | |
4549 | add_insn (last); | |
4550 | break; | |
23b2ce53 RS |
4551 | } |
4552 | ||
4553 | return last; | |
4554 | } | |
4555 | ||
2f937369 DM |
4556 | /* Make an insn of code JUMP_INSN with pattern X |
4557 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4558 | |
4559 | rtx | |
502b8322 | 4560 | emit_jump_insn (rtx x) |
23b2ce53 | 4561 | { |
d950dee3 | 4562 | rtx last = NULL_RTX, insn; |
23b2ce53 | 4563 | |
2f937369 | 4564 | switch (GET_CODE (x)) |
23b2ce53 | 4565 | { |
2f937369 DM |
4566 | case INSN: |
4567 | case JUMP_INSN: | |
4568 | case CALL_INSN: | |
4569 | case CODE_LABEL: | |
4570 | case BARRIER: | |
4571 | case NOTE: | |
4572 | insn = x; | |
4573 | while (insn) | |
4574 | { | |
4575 | rtx next = NEXT_INSN (insn); | |
4576 | add_insn (insn); | |
4577 | last = insn; | |
4578 | insn = next; | |
4579 | } | |
4580 | break; | |
e0a5c5eb | 4581 | |
2f937369 DM |
4582 | #ifdef ENABLE_RTL_CHECKING |
4583 | case SEQUENCE: | |
5b0264cb | 4584 | gcc_unreachable (); |
2f937369 DM |
4585 | break; |
4586 | #endif | |
e0a5c5eb | 4587 | |
2f937369 DM |
4588 | default: |
4589 | last = make_jump_insn_raw (x); | |
4590 | add_insn (last); | |
4591 | break; | |
3c030e88 | 4592 | } |
e0a5c5eb RS |
4593 | |
4594 | return last; | |
4595 | } | |
4596 | ||
2f937369 | 4597 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
4598 | and add it to the end of the doubly-linked list. */ |
4599 | ||
4600 | rtx | |
502b8322 | 4601 | emit_call_insn (rtx x) |
23b2ce53 | 4602 | { |
2f937369 DM |
4603 | rtx insn; |
4604 | ||
4605 | switch (GET_CODE (x)) | |
23b2ce53 | 4606 | { |
2f937369 DM |
4607 | case INSN: |
4608 | case JUMP_INSN: | |
4609 | case CALL_INSN: | |
4610 | case CODE_LABEL: | |
4611 | case BARRIER: | |
4612 | case NOTE: | |
4613 | insn = emit_insn (x); | |
4614 | break; | |
23b2ce53 | 4615 | |
2f937369 DM |
4616 | #ifdef ENABLE_RTL_CHECKING |
4617 | case SEQUENCE: | |
5b0264cb | 4618 | gcc_unreachable (); |
2f937369 DM |
4619 | break; |
4620 | #endif | |
23b2ce53 | 4621 | |
2f937369 DM |
4622 | default: |
4623 | insn = make_call_insn_raw (x); | |
23b2ce53 | 4624 | add_insn (insn); |
2f937369 | 4625 | break; |
23b2ce53 | 4626 | } |
2f937369 DM |
4627 | |
4628 | return insn; | |
23b2ce53 RS |
4629 | } |
4630 | ||
4631 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4632 | ||
4633 | rtx | |
502b8322 | 4634 | emit_label (rtx label) |
23b2ce53 RS |
4635 | { |
4636 | /* This can be called twice for the same label | |
4637 | as a result of the confusion that follows a syntax error! | |
4638 | So make it harmless. */ | |
4639 | if (INSN_UID (label) == 0) | |
4640 | { | |
4641 | INSN_UID (label) = cur_insn_uid++; | |
4642 | add_insn (label); | |
4643 | } | |
4644 | return label; | |
4645 | } | |
4646 | ||
4647 | /* Make an insn of code BARRIER | |
4648 | and add it to the end of the doubly-linked list. */ | |
4649 | ||
4650 | rtx | |
502b8322 | 4651 | emit_barrier (void) |
23b2ce53 | 4652 | { |
b3694847 | 4653 | rtx barrier = rtx_alloc (BARRIER); |
23b2ce53 RS |
4654 | INSN_UID (barrier) = cur_insn_uid++; |
4655 | add_insn (barrier); | |
4656 | return barrier; | |
4657 | } | |
4658 | ||
5f2fc772 | 4659 | /* Emit a copy of note ORIG. */ |
502b8322 | 4660 | |
5f2fc772 NS |
4661 | rtx |
4662 | emit_note_copy (rtx orig) | |
4663 | { | |
4664 | rtx note; | |
4665 | ||
5f2fc772 NS |
4666 | note = rtx_alloc (NOTE); |
4667 | ||
4668 | INSN_UID (note) = cur_insn_uid++; | |
4669 | NOTE_DATA (note) = NOTE_DATA (orig); | |
a38e7aa5 | 4670 | NOTE_KIND (note) = NOTE_KIND (orig); |
5f2fc772 NS |
4671 | BLOCK_FOR_INSN (note) = NULL; |
4672 | add_insn (note); | |
4673 | ||
2e040219 | 4674 | return note; |
23b2ce53 RS |
4675 | } |
4676 | ||
2e040219 NS |
4677 | /* Make an insn of code NOTE or type NOTE_NO |
4678 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4679 | |
4680 | rtx | |
a38e7aa5 | 4681 | emit_note (enum insn_note kind) |
23b2ce53 | 4682 | { |
b3694847 | 4683 | rtx note; |
23b2ce53 | 4684 | |
23b2ce53 RS |
4685 | note = rtx_alloc (NOTE); |
4686 | INSN_UID (note) = cur_insn_uid++; | |
a38e7aa5 | 4687 | NOTE_KIND (note) = kind; |
dd107e66 | 4688 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ba4f7968 | 4689 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
4690 | add_insn (note); |
4691 | return note; | |
4692 | } | |
4693 | ||
c41c1387 RS |
4694 | /* Emit a clobber of lvalue X. */ |
4695 | ||
4696 | rtx | |
4697 | emit_clobber (rtx x) | |
4698 | { | |
4699 | /* CONCATs should not appear in the insn stream. */ | |
4700 | if (GET_CODE (x) == CONCAT) | |
4701 | { | |
4702 | emit_clobber (XEXP (x, 0)); | |
4703 | return emit_clobber (XEXP (x, 1)); | |
4704 | } | |
4705 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
4706 | } | |
4707 | ||
4708 | /* Return a sequence of insns to clobber lvalue X. */ | |
4709 | ||
4710 | rtx | |
4711 | gen_clobber (rtx x) | |
4712 | { | |
4713 | rtx seq; | |
4714 | ||
4715 | start_sequence (); | |
4716 | emit_clobber (x); | |
4717 | seq = get_insns (); | |
4718 | end_sequence (); | |
4719 | return seq; | |
4720 | } | |
4721 | ||
4722 | /* Emit a use of rvalue X. */ | |
4723 | ||
4724 | rtx | |
4725 | emit_use (rtx x) | |
4726 | { | |
4727 | /* CONCATs should not appear in the insn stream. */ | |
4728 | if (GET_CODE (x) == CONCAT) | |
4729 | { | |
4730 | emit_use (XEXP (x, 0)); | |
4731 | return emit_use (XEXP (x, 1)); | |
4732 | } | |
4733 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
4734 | } | |
4735 | ||
4736 | /* Return a sequence of insns to use rvalue X. */ | |
4737 | ||
4738 | rtx | |
4739 | gen_use (rtx x) | |
4740 | { | |
4741 | rtx seq; | |
4742 | ||
4743 | start_sequence (); | |
4744 | emit_use (x); | |
4745 | seq = get_insns (); | |
4746 | end_sequence (); | |
4747 | return seq; | |
4748 | } | |
4749 | ||
23b2ce53 | 4750 | /* Cause next statement to emit a line note even if the line number |
0cea056b | 4751 | has not changed. */ |
23b2ce53 RS |
4752 | |
4753 | void | |
502b8322 | 4754 | force_next_line_note (void) |
23b2ce53 | 4755 | { |
6773e15f | 4756 | last_location = -1; |
23b2ce53 | 4757 | } |
87b47c85 AM |
4758 | |
4759 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
30f7a378 | 4760 | note of this type already exists, remove it first. */ |
87b47c85 | 4761 | |
3d238248 | 4762 | rtx |
502b8322 | 4763 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
4764 | { |
4765 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
4766 | ||
52488da1 JW |
4767 | switch (kind) |
4768 | { | |
4769 | case REG_EQUAL: | |
4770 | case REG_EQUIV: | |
4771 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
4772 | has multiple sets (some callers assume single_set | |
4773 | means the insn only has one set, when in fact it | |
4774 | means the insn only has one * useful * set). */ | |
4775 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
4776 | { | |
5b0264cb | 4777 | gcc_assert (!note); |
52488da1 JW |
4778 | return NULL_RTX; |
4779 | } | |
4780 | ||
4781 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
4782 | It serves no useful purpose and breaks eliminate_regs. */ | |
4783 | if (GET_CODE (datum) == ASM_OPERANDS) | |
4784 | return NULL_RTX; | |
6fb5fa3c DB |
4785 | |
4786 | if (note) | |
4787 | { | |
4788 | XEXP (note, 0) = datum; | |
4789 | df_notes_rescan (insn); | |
4790 | return note; | |
4791 | } | |
52488da1 JW |
4792 | break; |
4793 | ||
4794 | default: | |
6fb5fa3c DB |
4795 | if (note) |
4796 | { | |
4797 | XEXP (note, 0) = datum; | |
4798 | return note; | |
4799 | } | |
52488da1 JW |
4800 | break; |
4801 | } | |
3d238248 | 4802 | |
65c5f2a6 | 4803 | add_reg_note (insn, kind, datum); |
6fb5fa3c DB |
4804 | |
4805 | switch (kind) | |
3d238248 | 4806 | { |
6fb5fa3c DB |
4807 | case REG_EQUAL: |
4808 | case REG_EQUIV: | |
4809 | df_notes_rescan (insn); | |
4810 | break; | |
4811 | default: | |
4812 | break; | |
3d238248 | 4813 | } |
87b47c85 | 4814 | |
3d238248 | 4815 | return REG_NOTES (insn); |
87b47c85 | 4816 | } |
23b2ce53 RS |
4817 | \f |
4818 | /* Return an indication of which type of insn should have X as a body. | |
4819 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
4820 | ||
d78db459 | 4821 | static enum rtx_code |
502b8322 | 4822 | classify_insn (rtx x) |
23b2ce53 | 4823 | { |
4b4bf941 | 4824 | if (LABEL_P (x)) |
23b2ce53 RS |
4825 | return CODE_LABEL; |
4826 | if (GET_CODE (x) == CALL) | |
4827 | return CALL_INSN; | |
4828 | if (GET_CODE (x) == RETURN) | |
4829 | return JUMP_INSN; | |
4830 | if (GET_CODE (x) == SET) | |
4831 | { | |
4832 | if (SET_DEST (x) == pc_rtx) | |
4833 | return JUMP_INSN; | |
4834 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
4835 | return CALL_INSN; | |
4836 | else | |
4837 | return INSN; | |
4838 | } | |
4839 | if (GET_CODE (x) == PARALLEL) | |
4840 | { | |
b3694847 | 4841 | int j; |
23b2ce53 RS |
4842 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
4843 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
4844 | return CALL_INSN; | |
4845 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4846 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
4847 | return JUMP_INSN; | |
4848 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4849 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
4850 | return CALL_INSN; | |
4851 | } | |
4852 | return INSN; | |
4853 | } | |
4854 | ||
4855 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
4856 | If X is a label, it is simply added into the insn chain. */ | |
4857 | ||
4858 | rtx | |
502b8322 | 4859 | emit (rtx x) |
23b2ce53 RS |
4860 | { |
4861 | enum rtx_code code = classify_insn (x); | |
4862 | ||
5b0264cb | 4863 | switch (code) |
23b2ce53 | 4864 | { |
5b0264cb NS |
4865 | case CODE_LABEL: |
4866 | return emit_label (x); | |
4867 | case INSN: | |
4868 | return emit_insn (x); | |
4869 | case JUMP_INSN: | |
4870 | { | |
4871 | rtx insn = emit_jump_insn (x); | |
4872 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) | |
4873 | return emit_barrier (); | |
4874 | return insn; | |
4875 | } | |
4876 | case CALL_INSN: | |
4877 | return emit_call_insn (x); | |
4878 | default: | |
4879 | gcc_unreachable (); | |
23b2ce53 | 4880 | } |
23b2ce53 RS |
4881 | } |
4882 | \f | |
e2500fed | 4883 | /* Space for free sequence stack entries. */ |
1431042e | 4884 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 4885 | |
4dfa0342 RH |
4886 | /* Begin emitting insns to a sequence. If this sequence will contain |
4887 | something that might cause the compiler to pop arguments to function | |
4888 | calls (because those pops have previously been deferred; see | |
4889 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
4890 | before calling this function. That will ensure that the deferred | |
4891 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
4892 | |
4893 | void | |
502b8322 | 4894 | start_sequence (void) |
23b2ce53 RS |
4895 | { |
4896 | struct sequence_stack *tem; | |
4897 | ||
e2500fed GK |
4898 | if (free_sequence_stack != NULL) |
4899 | { | |
4900 | tem = free_sequence_stack; | |
4901 | free_sequence_stack = tem->next; | |
4902 | } | |
4903 | else | |
1b4572a8 | 4904 | tem = GGC_NEW (struct sequence_stack); |
23b2ce53 | 4905 | |
49ad7cfa | 4906 | tem->next = seq_stack; |
23b2ce53 RS |
4907 | tem->first = first_insn; |
4908 | tem->last = last_insn; | |
4909 | ||
49ad7cfa | 4910 | seq_stack = tem; |
23b2ce53 RS |
4911 | |
4912 | first_insn = 0; | |
4913 | last_insn = 0; | |
4914 | } | |
4915 | ||
5c7a310f MM |
4916 | /* Set up the insn chain starting with FIRST as the current sequence, |
4917 | saving the previously current one. See the documentation for | |
4918 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
4919 | |
4920 | void | |
502b8322 | 4921 | push_to_sequence (rtx first) |
23b2ce53 RS |
4922 | { |
4923 | rtx last; | |
4924 | ||
4925 | start_sequence (); | |
4926 | ||
4927 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
4928 | ||
4929 | first_insn = first; | |
4930 | last_insn = last; | |
4931 | } | |
4932 | ||
bb27eeda SE |
4933 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
4934 | looping through the list. */ | |
4935 | ||
4936 | void | |
4937 | push_to_sequence2 (rtx first, rtx last) | |
4938 | { | |
4939 | start_sequence (); | |
4940 | ||
4941 | first_insn = first; | |
4942 | last_insn = last; | |
4943 | } | |
4944 | ||
f15ae3a1 TW |
4945 | /* Set up the outer-level insn chain |
4946 | as the current sequence, saving the previously current one. */ | |
4947 | ||
4948 | void | |
502b8322 | 4949 | push_topmost_sequence (void) |
f15ae3a1 | 4950 | { |
aefdd5ab | 4951 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
4952 | |
4953 | start_sequence (); | |
4954 | ||
49ad7cfa | 4955 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
4956 | top = stack; |
4957 | ||
4958 | first_insn = top->first; | |
4959 | last_insn = top->last; | |
4960 | } | |
4961 | ||
4962 | /* After emitting to the outer-level insn chain, update the outer-level | |
4963 | insn chain, and restore the previous saved state. */ | |
4964 | ||
4965 | void | |
502b8322 | 4966 | pop_topmost_sequence (void) |
f15ae3a1 | 4967 | { |
aefdd5ab | 4968 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 4969 | |
49ad7cfa | 4970 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
4971 | top = stack; |
4972 | ||
4973 | top->first = first_insn; | |
4974 | top->last = last_insn; | |
4975 | ||
4976 | end_sequence (); | |
4977 | } | |
4978 | ||
23b2ce53 RS |
4979 | /* After emitting to a sequence, restore previous saved state. |
4980 | ||
5c7a310f | 4981 | To get the contents of the sequence just made, you must call |
2f937369 | 4982 | `get_insns' *before* calling here. |
5c7a310f MM |
4983 | |
4984 | If the compiler might have deferred popping arguments while | |
4985 | generating this sequence, and this sequence will not be immediately | |
4986 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 4987 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
4988 | pops are inserted into this sequence, and not into some random |
4989 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
4990 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
4991 | |
4992 | void | |
502b8322 | 4993 | end_sequence (void) |
23b2ce53 | 4994 | { |
49ad7cfa | 4995 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
4996 | |
4997 | first_insn = tem->first; | |
4998 | last_insn = tem->last; | |
49ad7cfa | 4999 | seq_stack = tem->next; |
23b2ce53 | 5000 | |
e2500fed GK |
5001 | memset (tem, 0, sizeof (*tem)); |
5002 | tem->next = free_sequence_stack; | |
5003 | free_sequence_stack = tem; | |
23b2ce53 RS |
5004 | } |
5005 | ||
5006 | /* Return 1 if currently emitting into a sequence. */ | |
5007 | ||
5008 | int | |
502b8322 | 5009 | in_sequence_p (void) |
23b2ce53 | 5010 | { |
49ad7cfa | 5011 | return seq_stack != 0; |
23b2ce53 | 5012 | } |
23b2ce53 | 5013 | \f |
59ec66dc MM |
5014 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5015 | ||
2bbdec73 | 5016 | static void |
bd60bab2 | 5017 | init_virtual_regs (void) |
59ec66dc | 5018 | { |
bd60bab2 JH |
5019 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5020 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5021 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5022 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5023 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
49ad7cfa BS |
5024 | } |
5025 | ||
da43a810 BS |
5026 | \f |
5027 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5028 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5029 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5030 | static int copy_insn_n_scratches; | |
5031 | ||
5032 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5033 | copied an ASM_OPERANDS. | |
5034 | In that case, it is the original input-operand vector. */ | |
5035 | static rtvec orig_asm_operands_vector; | |
5036 | ||
5037 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5038 | copied an ASM_OPERANDS. | |
5039 | In that case, it is the copied input-operand vector. */ | |
5040 | static rtvec copy_asm_operands_vector; | |
5041 | ||
5042 | /* Likewise for the constraints vector. */ | |
5043 | static rtvec orig_asm_constraints_vector; | |
5044 | static rtvec copy_asm_constraints_vector; | |
5045 | ||
5046 | /* Recursively create a new copy of an rtx for copy_insn. | |
5047 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5048 | ASM_OPERANDs properly. | |
5049 | Normally, this function is not used directly; use copy_insn as front end. | |
5050 | However, you could first copy an insn pattern with copy_insn and then use | |
5051 | this function afterwards to properly copy any REG_NOTEs containing | |
5052 | SCRATCHes. */ | |
5053 | ||
5054 | rtx | |
502b8322 | 5055 | copy_insn_1 (rtx orig) |
da43a810 | 5056 | { |
b3694847 SS |
5057 | rtx copy; |
5058 | int i, j; | |
5059 | RTX_CODE code; | |
5060 | const char *format_ptr; | |
da43a810 | 5061 | |
cd9c1ca8 RH |
5062 | if (orig == NULL) |
5063 | return NULL; | |
5064 | ||
da43a810 BS |
5065 | code = GET_CODE (orig); |
5066 | ||
5067 | switch (code) | |
5068 | { | |
5069 | case REG: | |
da43a810 BS |
5070 | case CONST_INT: |
5071 | case CONST_DOUBLE: | |
091a3ac7 | 5072 | case CONST_FIXED: |
69ef87e2 | 5073 | case CONST_VECTOR: |
da43a810 BS |
5074 | case SYMBOL_REF: |
5075 | case CODE_LABEL: | |
5076 | case PC: | |
5077 | case CC0: | |
da43a810 | 5078 | return orig; |
3e89ed8d JH |
5079 | case CLOBBER: |
5080 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER) | |
5081 | return orig; | |
5082 | break; | |
da43a810 BS |
5083 | |
5084 | case SCRATCH: | |
5085 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5086 | if (copy_insn_scratch_in[i] == orig) | |
5087 | return copy_insn_scratch_out[i]; | |
5088 | break; | |
5089 | ||
5090 | case CONST: | |
6fb5fa3c | 5091 | if (shared_const_p (orig)) |
da43a810 BS |
5092 | return orig; |
5093 | break; | |
750c9258 | 5094 | |
da43a810 BS |
5095 | /* A MEM with a constant address is not sharable. The problem is that |
5096 | the constant address may need to be reloaded. If the mem is shared, | |
5097 | then reloading one copy of this mem will cause all copies to appear | |
5098 | to have been reloaded. */ | |
5099 | ||
5100 | default: | |
5101 | break; | |
5102 | } | |
5103 | ||
aacd3885 RS |
5104 | /* Copy the various flags, fields, and other information. We assume |
5105 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5106 | not be copied. That is the sensible default behavior, and forces |
5107 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5108 | copy = shallow_copy_rtx (orig); |
da43a810 BS |
5109 | |
5110 | /* We do not copy the USED flag, which is used as a mark bit during | |
5111 | walks over the RTL. */ | |
2adc7f12 | 5112 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5113 | |
5114 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
ec8e098d | 5115 | if (INSN_P (orig)) |
da43a810 | 5116 | { |
2adc7f12 JJ |
5117 | RTX_FLAG (copy, jump) = 0; |
5118 | RTX_FLAG (copy, call) = 0; | |
5119 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5120 | } |
750c9258 | 5121 | |
da43a810 BS |
5122 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5123 | ||
5124 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5125 | switch (*format_ptr++) |
5126 | { | |
5127 | case 'e': | |
5128 | if (XEXP (orig, i) != NULL) | |
5129 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5130 | break; | |
da43a810 | 5131 | |
aacd3885 RS |
5132 | case 'E': |
5133 | case 'V': | |
5134 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5135 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5136 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5137 | XVEC (copy, i) = copy_asm_operands_vector; | |
5138 | else if (XVEC (orig, i) != NULL) | |
5139 | { | |
5140 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5141 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5142 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5143 | } | |
5144 | break; | |
da43a810 | 5145 | |
aacd3885 RS |
5146 | case 't': |
5147 | case 'w': | |
5148 | case 'i': | |
5149 | case 's': | |
5150 | case 'S': | |
5151 | case 'u': | |
5152 | case '0': | |
5153 | /* These are left unchanged. */ | |
5154 | break; | |
da43a810 | 5155 | |
aacd3885 RS |
5156 | default: |
5157 | gcc_unreachable (); | |
5158 | } | |
da43a810 BS |
5159 | |
5160 | if (code == SCRATCH) | |
5161 | { | |
5162 | i = copy_insn_n_scratches++; | |
5b0264cb | 5163 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5164 | copy_insn_scratch_in[i] = orig; |
5165 | copy_insn_scratch_out[i] = copy; | |
5166 | } | |
5167 | else if (code == ASM_OPERANDS) | |
5168 | { | |
6462bb43 AO |
5169 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5170 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5171 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5172 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5173 | } |
5174 | ||
5175 | return copy; | |
5176 | } | |
5177 | ||
5178 | /* Create a new copy of an rtx. | |
5179 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5180 | ASM_OPERANDs properly. | |
5181 | INSN doesn't really have to be a full INSN; it could be just the | |
5182 | pattern. */ | |
5183 | rtx | |
502b8322 | 5184 | copy_insn (rtx insn) |
da43a810 BS |
5185 | { |
5186 | copy_insn_n_scratches = 0; | |
5187 | orig_asm_operands_vector = 0; | |
5188 | orig_asm_constraints_vector = 0; | |
5189 | copy_asm_operands_vector = 0; | |
5190 | copy_asm_constraints_vector = 0; | |
5191 | return copy_insn_1 (insn); | |
5192 | } | |
59ec66dc | 5193 | |
23b2ce53 RS |
5194 | /* Initialize data structures and variables in this file |
5195 | before generating rtl for each function. */ | |
5196 | ||
5197 | void | |
502b8322 | 5198 | init_emit (void) |
23b2ce53 | 5199 | { |
23b2ce53 RS |
5200 | first_insn = NULL; |
5201 | last_insn = NULL; | |
5202 | cur_insn_uid = 1; | |
5203 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
6773e15f | 5204 | last_location = UNKNOWN_LOCATION; |
23b2ce53 | 5205 | first_label_num = label_num; |
49ad7cfa | 5206 | seq_stack = NULL; |
23b2ce53 | 5207 | |
23b2ce53 RS |
5208 | /* Init the tables that describe all the pseudo regs. */ |
5209 | ||
3e029763 | 5210 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5211 | |
3e029763 | 5212 | crtl->emit.regno_pointer_align |
1b4572a8 | 5213 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5214 | |
750c9258 | 5215 | regno_reg_rtx |
1b4572a8 | 5216 | = GGC_NEWVEC (rtx, crtl->emit.regno_pointer_align_length); |
0d4903b8 | 5217 | |
e50126e8 | 5218 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 JL |
5219 | memcpy (regno_reg_rtx, |
5220 | static_regno_reg_rtx, | |
5221 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); | |
e50126e8 | 5222 | |
23b2ce53 | 5223 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5224 | init_virtual_regs (); |
740ab4a2 RK |
5225 | |
5226 | /* Indicate that the virtual registers and stack locations are | |
5227 | all pointers. */ | |
3502dc9c JDA |
5228 | REG_POINTER (stack_pointer_rtx) = 1; |
5229 | REG_POINTER (frame_pointer_rtx) = 1; | |
5230 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5231 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5232 | |
3502dc9c JDA |
5233 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5234 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5235 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5236 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5237 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5238 | |
86fe05e0 | 5239 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5240 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5241 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5242 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5243 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5244 | ||
5245 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5246 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5247 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5248 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5249 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5250 | #endif |
5251 | ||
5e82e7bd JVA |
5252 | #ifdef INIT_EXPANDERS |
5253 | INIT_EXPANDERS; | |
5254 | #endif | |
23b2ce53 RS |
5255 | } |
5256 | ||
a73b091d | 5257 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
69ef87e2 AH |
5258 | |
5259 | static rtx | |
a73b091d | 5260 | gen_const_vector (enum machine_mode mode, int constant) |
69ef87e2 AH |
5261 | { |
5262 | rtx tem; | |
5263 | rtvec v; | |
5264 | int units, i; | |
5265 | enum machine_mode inner; | |
5266 | ||
5267 | units = GET_MODE_NUNITS (mode); | |
5268 | inner = GET_MODE_INNER (mode); | |
5269 | ||
15ed7b52 JG |
5270 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5271 | ||
69ef87e2 AH |
5272 | v = rtvec_alloc (units); |
5273 | ||
a73b091d JW |
5274 | /* We need to call this function after we set the scalar const_tiny_rtx |
5275 | entries. */ | |
5276 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
69ef87e2 AH |
5277 | |
5278 | for (i = 0; i < units; ++i) | |
a73b091d | 5279 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
69ef87e2 | 5280 | |
a06e3c40 | 5281 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5282 | return tem; |
5283 | } | |
5284 | ||
a06e3c40 | 5285 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5286 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5287 | rtx |
502b8322 | 5288 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
a06e3c40 | 5289 | { |
a73b091d JW |
5290 | enum machine_mode inner = GET_MODE_INNER (mode); |
5291 | int nunits = GET_MODE_NUNITS (mode); | |
5292 | rtx x; | |
a06e3c40 R |
5293 | int i; |
5294 | ||
a73b091d JW |
5295 | /* Check to see if all of the elements have the same value. */ |
5296 | x = RTVEC_ELT (v, nunits - 1); | |
5297 | for (i = nunits - 2; i >= 0; i--) | |
5298 | if (RTVEC_ELT (v, i) != x) | |
5299 | break; | |
5300 | ||
5301 | /* If the values are all the same, check to see if we can use one of the | |
5302 | standard constant vectors. */ | |
5303 | if (i == -1) | |
5304 | { | |
5305 | if (x == CONST0_RTX (inner)) | |
5306 | return CONST0_RTX (mode); | |
5307 | else if (x == CONST1_RTX (inner)) | |
5308 | return CONST1_RTX (mode); | |
5309 | } | |
5310 | ||
5311 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5312 | } |
5313 | ||
b5deb7b6 SL |
5314 | /* Initialise global register information required by all functions. */ |
5315 | ||
5316 | void | |
5317 | init_emit_regs (void) | |
5318 | { | |
5319 | int i; | |
5320 | ||
5321 | /* Reset register attributes */ | |
5322 | htab_empty (reg_attrs_htab); | |
5323 | ||
5324 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5325 | init_reg_modes_target (); | |
5326 | ||
5327 | /* Assign register numbers to the globally defined register rtx. */ | |
5328 | pc_rtx = gen_rtx_PC (VOIDmode); | |
5329 | cc0_rtx = gen_rtx_CC0 (VOIDmode); | |
5330 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
5331 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5332 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5333 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5334 | virtual_incoming_args_rtx = | |
5335 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5336 | virtual_stack_vars_rtx = | |
5337 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5338 | virtual_stack_dynamic_rtx = | |
5339 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5340 | virtual_outgoing_args_rtx = | |
5341 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5342 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
5343 | ||
5344 | /* Initialize RTL for commonly used hard registers. These are | |
5345 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5346 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5347 | static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); | |
5348 | ||
5349 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5350 | return_address_pointer_rtx | |
5351 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5352 | #endif | |
5353 | ||
5354 | #ifdef STATIC_CHAIN_REGNUM | |
5355 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
5356 | ||
5357 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
5358 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
5359 | static_chain_incoming_rtx | |
5360 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
5361 | else | |
5362 | #endif | |
5363 | static_chain_incoming_rtx = static_chain_rtx; | |
5364 | #endif | |
5365 | ||
5366 | #ifdef STATIC_CHAIN | |
5367 | static_chain_rtx = STATIC_CHAIN; | |
5368 | ||
5369 | #ifdef STATIC_CHAIN_INCOMING | |
5370 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
5371 | #else | |
5372 | static_chain_incoming_rtx = static_chain_rtx; | |
5373 | #endif | |
5374 | #endif | |
5375 | ||
5376 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
5377 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
5378 | else | |
5379 | pic_offset_table_rtx = NULL_RTX; | |
5380 | } | |
5381 | ||
23b2ce53 RS |
5382 | /* Create some permanent unique rtl objects shared between all functions. |
5383 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
5384 | ||
5385 | void | |
502b8322 | 5386 | init_emit_once (int line_numbers) |
23b2ce53 RS |
5387 | { |
5388 | int i; | |
5389 | enum machine_mode mode; | |
9ec36da5 | 5390 | enum machine_mode double_mode; |
23b2ce53 | 5391 | |
091a3ac7 CF |
5392 | /* Initialize the CONST_INT, CONST_DOUBLE, CONST_FIXED, and memory attribute |
5393 | hash tables. */ | |
17211ab5 GK |
5394 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5395 | const_int_htab_eq, NULL); | |
173b24b9 | 5396 | |
17211ab5 GK |
5397 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5398 | const_double_htab_eq, NULL); | |
5692c7bc | 5399 | |
091a3ac7 CF |
5400 | const_fixed_htab = htab_create_ggc (37, const_fixed_htab_hash, |
5401 | const_fixed_htab_eq, NULL); | |
5402 | ||
17211ab5 GK |
5403 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5404 | mem_attrs_htab_eq, NULL); | |
a560d4d4 JH |
5405 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5406 | reg_attrs_htab_eq, NULL); | |
67673f5c | 5407 | |
23b2ce53 RS |
5408 | no_line_numbers = ! line_numbers; |
5409 | ||
43fa6302 AS |
5410 | /* Compute the word and byte modes. */ |
5411 | ||
5412 | byte_mode = VOIDmode; | |
5413 | word_mode = VOIDmode; | |
5414 | double_mode = VOIDmode; | |
5415 | ||
15ed7b52 JG |
5416 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5417 | mode != VOIDmode; | |
43fa6302 AS |
5418 | mode = GET_MODE_WIDER_MODE (mode)) |
5419 | { | |
5420 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5421 | && byte_mode == VOIDmode) | |
5422 | byte_mode = mode; | |
5423 | ||
5424 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5425 | && word_mode == VOIDmode) | |
5426 | word_mode = mode; | |
5427 | } | |
5428 | ||
15ed7b52 JG |
5429 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5430 | mode != VOIDmode; | |
43fa6302 AS |
5431 | mode = GET_MODE_WIDER_MODE (mode)) |
5432 | { | |
5433 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5434 | && double_mode == VOIDmode) | |
5435 | double_mode = mode; | |
5436 | } | |
5437 | ||
5438 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5439 | ||
5da077de | 5440 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5441 | /* This is to initialize {init|mark|free}_machine_status before the first |
5442 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5443 | end which calls push_function_context_to before the first call to |
5da077de AS |
5444 | init_function_start. */ |
5445 | INIT_EXPANDERS; | |
5446 | #endif | |
5447 | ||
23b2ce53 RS |
5448 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5449 | ||
a2a8cc44 | 5450 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 5451 | tries to use these variables. */ |
23b2ce53 | 5452 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5453 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5454 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5455 | |
68d75312 JC |
5456 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5457 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5458 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5459 | else |
3b80f6ca | 5460 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5461 | |
5692c7bc ZW |
5462 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5463 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5464 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
aefa9d43 KG |
5465 | |
5466 | dconstm1 = dconst1; | |
5467 | dconstm1.sign = 1; | |
03f2ea93 RS |
5468 | |
5469 | dconsthalf = dconst1; | |
1e92bbb9 | 5470 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 5471 | |
f7657db9 | 5472 | for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++) |
23b2ce53 | 5473 | { |
aefa9d43 | 5474 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
5475 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
5476 | ||
15ed7b52 JG |
5477 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5478 | mode != VOIDmode; | |
5479 | mode = GET_MODE_WIDER_MODE (mode)) | |
5480 | const_tiny_rtx[i][(int) mode] = | |
5481 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5482 | ||
5483 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5484 | mode != VOIDmode; | |
23b2ce53 | 5485 | mode = GET_MODE_WIDER_MODE (mode)) |
5692c7bc ZW |
5486 | const_tiny_rtx[i][(int) mode] = |
5487 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5488 | |
906c4e36 | 5489 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 5490 | |
15ed7b52 JG |
5491 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5492 | mode != VOIDmode; | |
23b2ce53 | 5493 | mode = GET_MODE_WIDER_MODE (mode)) |
906c4e36 | 5494 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
5495 | |
5496 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5497 | mode != VOIDmode; | |
5498 | mode = GET_MODE_WIDER_MODE (mode)) | |
5499 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
5500 | } |
5501 | ||
e90721b1 AP |
5502 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5503 | mode != VOIDmode; | |
5504 | mode = GET_MODE_WIDER_MODE (mode)) | |
5505 | { | |
5506 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5507 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5508 | } | |
5509 | ||
5510 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5511 | mode != VOIDmode; | |
5512 | mode = GET_MODE_WIDER_MODE (mode)) | |
5513 | { | |
5514 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5515 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5516 | } | |
5517 | ||
69ef87e2 AH |
5518 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5519 | mode != VOIDmode; | |
5520 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5521 | { |
5522 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5523 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5524 | } | |
69ef87e2 AH |
5525 | |
5526 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5527 | mode != VOIDmode; | |
5528 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5529 | { |
5530 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5531 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5532 | } | |
69ef87e2 | 5533 | |
325217ed CF |
5534 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
5535 | mode != VOIDmode; | |
5536 | mode = GET_MODE_WIDER_MODE (mode)) | |
5537 | { | |
5538 | FCONST0(mode).data.high = 0; | |
5539 | FCONST0(mode).data.low = 0; | |
5540 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5541 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5542 | FCONST0 (mode), mode); | |
325217ed CF |
5543 | } |
5544 | ||
5545 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
5546 | mode != VOIDmode; | |
5547 | mode = GET_MODE_WIDER_MODE (mode)) | |
5548 | { | |
5549 | FCONST0(mode).data.high = 0; | |
5550 | FCONST0(mode).data.low = 0; | |
5551 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5552 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5553 | FCONST0 (mode), mode); | |
325217ed CF |
5554 | } |
5555 | ||
5556 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
5557 | mode != VOIDmode; | |
5558 | mode = GET_MODE_WIDER_MODE (mode)) | |
5559 | { | |
5560 | FCONST0(mode).data.high = 0; | |
5561 | FCONST0(mode).data.low = 0; | |
5562 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5563 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5564 | FCONST0 (mode), mode); | |
325217ed CF |
5565 | |
5566 | /* We store the value 1. */ | |
5567 | FCONST1(mode).data.high = 0; | |
5568 | FCONST1(mode).data.low = 0; | |
5569 | FCONST1(mode).mode = mode; | |
5570 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5571 | 2 * HOST_BITS_PER_WIDE_INT, | |
5572 | &FCONST1(mode).data.low, | |
5573 | &FCONST1(mode).data.high, | |
5574 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5575 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5576 | FCONST1 (mode), mode); | |
325217ed CF |
5577 | } |
5578 | ||
5579 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
5580 | mode != VOIDmode; | |
5581 | mode = GET_MODE_WIDER_MODE (mode)) | |
5582 | { | |
5583 | FCONST0(mode).data.high = 0; | |
5584 | FCONST0(mode).data.low = 0; | |
5585 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5586 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5587 | FCONST0 (mode), mode); | |
325217ed CF |
5588 | |
5589 | /* We store the value 1. */ | |
5590 | FCONST1(mode).data.high = 0; | |
5591 | FCONST1(mode).data.low = 0; | |
5592 | FCONST1(mode).mode = mode; | |
5593 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5594 | 2 * HOST_BITS_PER_WIDE_INT, | |
5595 | &FCONST1(mode).data.low, | |
5596 | &FCONST1(mode).data.high, | |
5597 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5598 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5599 | FCONST1 (mode), mode); | |
5600 | } | |
5601 | ||
5602 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT); | |
5603 | mode != VOIDmode; | |
5604 | mode = GET_MODE_WIDER_MODE (mode)) | |
5605 | { | |
5606 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5607 | } | |
5608 | ||
5609 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT); | |
5610 | mode != VOIDmode; | |
5611 | mode = GET_MODE_WIDER_MODE (mode)) | |
5612 | { | |
5613 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5614 | } | |
5615 | ||
5616 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM); | |
5617 | mode != VOIDmode; | |
5618 | mode = GET_MODE_WIDER_MODE (mode)) | |
5619 | { | |
5620 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5621 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5622 | } | |
5623 | ||
5624 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM); | |
5625 | mode != VOIDmode; | |
5626 | mode = GET_MODE_WIDER_MODE (mode)) | |
5627 | { | |
5628 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5629 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
5630 | } |
5631 | ||
dbbbbf3b JDA |
5632 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5633 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5634 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 5635 | |
f0417c82 RH |
5636 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5637 | if (STORE_FLAG_VALUE == 1) | |
5638 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
23b2ce53 | 5639 | } |
a11759a3 | 5640 | \f |
969d70ca JH |
5641 | /* Produce exact duplicate of insn INSN after AFTER. |
5642 | Care updating of libcall regions if present. */ | |
5643 | ||
5644 | rtx | |
502b8322 | 5645 | emit_copy_of_insn_after (rtx insn, rtx after) |
969d70ca | 5646 | { |
60564289 | 5647 | rtx new_rtx, link; |
969d70ca JH |
5648 | |
5649 | switch (GET_CODE (insn)) | |
5650 | { | |
5651 | case INSN: | |
60564289 | 5652 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5653 | break; |
5654 | ||
5655 | case JUMP_INSN: | |
60564289 | 5656 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5657 | break; |
5658 | ||
5659 | case CALL_INSN: | |
60564289 | 5660 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 5661 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 5662 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 5663 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
5664 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
5665 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
5666 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
5667 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) | |
becfd6e5 | 5668 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
5669 | break; |
5670 | ||
5671 | default: | |
5b0264cb | 5672 | gcc_unreachable (); |
969d70ca JH |
5673 | } |
5674 | ||
5675 | /* Update LABEL_NUSES. */ | |
60564289 | 5676 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 5677 | |
60564289 | 5678 | INSN_LOCATOR (new_rtx) = INSN_LOCATOR (insn); |
ba4f7968 | 5679 | |
0a3d71f5 JW |
5680 | /* If the old insn is frame related, then so is the new one. This is |
5681 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
5682 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 5683 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 5684 | |
cf7c4aa6 HPN |
5685 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
5686 | will make them. REG_LABEL_TARGETs are created there too, but are | |
5687 | supposed to be sticky, so we copy them. */ | |
969d70ca | 5688 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 5689 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca JH |
5690 | { |
5691 | if (GET_CODE (link) == EXPR_LIST) | |
60564289 | 5692 | add_reg_note (new_rtx, REG_NOTE_KIND (link), |
65c5f2a6 | 5693 | copy_insn_1 (XEXP (link, 0))); |
969d70ca | 5694 | else |
60564289 | 5695 | add_reg_note (new_rtx, REG_NOTE_KIND (link), XEXP (link, 0)); |
969d70ca JH |
5696 | } |
5697 | ||
60564289 KG |
5698 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
5699 | return new_rtx; | |
969d70ca | 5700 | } |
e2500fed | 5701 | |
1431042e | 5702 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d JH |
5703 | rtx |
5704 | gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno) | |
5705 | { | |
5706 | if (hard_reg_clobbers[mode][regno]) | |
5707 | return hard_reg_clobbers[mode][regno]; | |
5708 | else | |
5709 | return (hard_reg_clobbers[mode][regno] = | |
5710 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
5711 | } | |
5712 | ||
e2500fed | 5713 | #include "gt-emit-rtl.h" |