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Commit | Line | Data |
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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
09efeca1 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
b6f65e3c | 4 | Free Software Foundation, Inc. |
23b2ce53 | 5 | |
1322177d | 6 | This file is part of GCC. |
23b2ce53 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
23b2ce53 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
23b2ce53 RS |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
f822fcf7 KH |
25 | This file contains support functions for creating rtl expressions |
26 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
27 | |
28 | The patterns of the insns are created by machine-dependent | |
29 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
30 | the machine description. These routines make the individual rtx's |
31 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
32 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
33 | dependent is the kind of rtx's they make and what arguments they |
34 | use. */ | |
23b2ce53 RS |
35 | |
36 | #include "config.h" | |
670ee920 | 37 | #include "system.h" |
4977bab6 ZW |
38 | #include "coretypes.h" |
39 | #include "tm.h" | |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
325217ed | 53 | #include "fixed-value.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
e1772ac0 | 57 | #include "debug.h" |
d23c55c2 | 58 | #include "langhooks.h" |
ef330312 | 59 | #include "tree-pass.h" |
6fb5fa3c | 60 | #include "df.h" |
b5b8b0ac | 61 | #include "params.h" |
ca695ac9 | 62 | |
1d445e9e ILT |
63 | /* Commonly used modes. */ |
64 | ||
0f41302f MS |
65 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
66 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 67 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 68 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 69 | |
bd60bab2 JH |
70 | /* Datastructures maintained for currently processed function in RTL form. */ |
71 | ||
3e029763 | 72 | struct rtl_data x_rtl; |
bd60bab2 JH |
73 | |
74 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
75 | Allocated in parallel with regno_pointer_align. | |
76 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal | |
77 | with length attribute nested in top level structures. */ | |
78 | ||
79 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
80 | |
81 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
82 | in the entire compilation a unique label number. */ | |
83 | ||
044b4de3 | 84 | static GTY(()) int label_num = 1; |
23b2ce53 | 85 | |
23b2ce53 RS |
86 | /* Nonzero means do not generate NOTEs for source line numbers. */ |
87 | ||
88 | static int no_line_numbers; | |
89 | ||
90 | /* Commonly used rtx's, so that we only need space for one copy. | |
91 | These are initialized once for the entire compilation. | |
5692c7bc ZW |
92 | All of these are unique; no other rtx-object will be equal to any |
93 | of these. */ | |
23b2ce53 | 94 | |
5da077de | 95 | rtx global_rtl[GR_MAX]; |
23b2ce53 | 96 | |
6cde4876 JL |
97 | /* Commonly used RTL for hard registers. These objects are not necessarily |
98 | unique, so we allocate them separately from global_rtl. They are | |
99 | initialized once per compilation unit, then copied into regno_reg_rtx | |
100 | at the beginning of each function. */ | |
101 | static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
102 | ||
23b2ce53 RS |
103 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
104 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
105 | record a copy of const[012]_rtx. */ | |
106 | ||
107 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
108 | ||
68d75312 JC |
109 | rtx const_true_rtx; |
110 | ||
23b2ce53 RS |
111 | REAL_VALUE_TYPE dconst0; |
112 | REAL_VALUE_TYPE dconst1; | |
113 | REAL_VALUE_TYPE dconst2; | |
114 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 115 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 116 | |
325217ed CF |
117 | /* Record fixed-point constant 0 and 1. */ |
118 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
119 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
120 | ||
23b2ce53 RS |
121 | /* All references to the following fixed hard registers go through |
122 | these unique rtl objects. On machines where the frame-pointer and | |
123 | arg-pointer are the same register, they use the same unique object. | |
124 | ||
125 | After register allocation, other rtl objects which used to be pseudo-regs | |
126 | may be clobbered to refer to the frame-pointer register. | |
127 | But references that were originally to the frame-pointer can be | |
128 | distinguished from the others because they contain frame_pointer_rtx. | |
129 | ||
ac6f08b0 DE |
130 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
131 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
750c9258 | 132 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
ac6f08b0 DE |
133 | register elimination hard_frame_pointer_rtx should always be used. |
134 | On machines where the two registers are same (most) then these are the | |
135 | same. | |
136 | ||
23b2ce53 RS |
137 | In an inline procedure, the stack and frame pointer rtxs may not be |
138 | used for anything else. */ | |
23b2ce53 RS |
139 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ |
140 | ||
a4417a86 JW |
141 | /* This is used to implement __builtin_return_address for some machines. |
142 | See for instance the MIPS port. */ | |
143 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
144 | ||
23b2ce53 RS |
145 | /* We make one copy of (const_int C) where C is in |
146 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
147 | to save space during the compilation and simplify comparisons of | |
148 | integers. */ | |
149 | ||
5da077de | 150 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 151 | |
c13e8210 MM |
152 | /* A hash table storing CONST_INTs whose absolute value is greater |
153 | than MAX_SAVED_CONST_INT. */ | |
154 | ||
e2500fed GK |
155 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
156 | htab_t const_int_htab; | |
c13e8210 | 157 | |
173b24b9 | 158 | /* A hash table storing memory attribute structures. */ |
e2500fed GK |
159 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
160 | htab_t mem_attrs_htab; | |
173b24b9 | 161 | |
a560d4d4 JH |
162 | /* A hash table storing register attribute structures. */ |
163 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
164 | htab_t reg_attrs_htab; | |
165 | ||
5692c7bc | 166 | /* A hash table storing all CONST_DOUBLEs. */ |
e2500fed GK |
167 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
168 | htab_t const_double_htab; | |
5692c7bc | 169 | |
091a3ac7 CF |
170 | /* A hash table storing all CONST_FIXEDs. */ |
171 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) | |
172 | htab_t const_fixed_htab; | |
173 | ||
3e029763 JH |
174 | #define first_insn (crtl->emit.x_first_insn) |
175 | #define last_insn (crtl->emit.x_last_insn) | |
176 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) | |
b5b8b0ac | 177 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 JH |
178 | #define last_location (crtl->emit.x_last_location) |
179 | #define first_label_num (crtl->emit.x_first_label_num) | |
23b2ce53 | 180 | |
502b8322 | 181 | static rtx make_call_insn_raw (rtx); |
502b8322 | 182 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); |
5eb2a9f2 | 183 | static void set_used_decls (tree); |
502b8322 AJ |
184 | static void mark_label_nuses (rtx); |
185 | static hashval_t const_int_htab_hash (const void *); | |
186 | static int const_int_htab_eq (const void *, const void *); | |
187 | static hashval_t const_double_htab_hash (const void *); | |
188 | static int const_double_htab_eq (const void *, const void *); | |
189 | static rtx lookup_const_double (rtx); | |
091a3ac7 CF |
190 | static hashval_t const_fixed_htab_hash (const void *); |
191 | static int const_fixed_htab_eq (const void *, const void *); | |
192 | static rtx lookup_const_fixed (rtx); | |
502b8322 AJ |
193 | static hashval_t mem_attrs_htab_hash (const void *); |
194 | static int mem_attrs_htab_eq (const void *, const void *); | |
4862826d | 195 | static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int, |
502b8322 AJ |
196 | enum machine_mode); |
197 | static hashval_t reg_attrs_htab_hash (const void *); | |
198 | static int reg_attrs_htab_eq (const void *, const void *); | |
199 | static reg_attrs *get_reg_attrs (tree, int); | |
a73b091d | 200 | static rtx gen_const_vector (enum machine_mode, int); |
32b32b16 | 201 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 202 | |
6b24c259 JH |
203 | /* Probability of the conditional branch currently proceeded by try_split. |
204 | Set to -1 otherwise. */ | |
205 | int split_branch_probability = -1; | |
ca695ac9 | 206 | \f |
c13e8210 MM |
207 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
208 | ||
209 | static hashval_t | |
502b8322 | 210 | const_int_htab_hash (const void *x) |
c13e8210 | 211 | { |
f7d504c2 | 212 | return (hashval_t) INTVAL ((const_rtx) x); |
c13e8210 MM |
213 | } |
214 | ||
cc2902df | 215 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
216 | CONST_INT) is the same as that given by Y (which is really a |
217 | HOST_WIDE_INT *). */ | |
218 | ||
219 | static int | |
502b8322 | 220 | const_int_htab_eq (const void *x, const void *y) |
c13e8210 | 221 | { |
f7d504c2 | 222 | return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y)); |
5692c7bc ZW |
223 | } |
224 | ||
225 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
226 | static hashval_t | |
502b8322 | 227 | const_double_htab_hash (const void *x) |
5692c7bc | 228 | { |
f7d504c2 | 229 | const_rtx const value = (const_rtx) x; |
46b33600 | 230 | hashval_t h; |
5692c7bc | 231 | |
46b33600 RH |
232 | if (GET_MODE (value) == VOIDmode) |
233 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
234 | else | |
fe352c29 | 235 | { |
15c812e3 | 236 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
237 | /* MODE is used in the comparison, so it should be in the hash. */ |
238 | h ^= GET_MODE (value); | |
239 | } | |
5692c7bc ZW |
240 | return h; |
241 | } | |
242 | ||
cc2902df | 243 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc ZW |
244 | is the same as that represented by Y (really a ...) */ |
245 | static int | |
502b8322 | 246 | const_double_htab_eq (const void *x, const void *y) |
5692c7bc | 247 | { |
f7d504c2 | 248 | const_rtx const a = (const_rtx)x, b = (const_rtx)y; |
5692c7bc ZW |
249 | |
250 | if (GET_MODE (a) != GET_MODE (b)) | |
251 | return 0; | |
8580f7a0 RH |
252 | if (GET_MODE (a) == VOIDmode) |
253 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
254 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
255 | else | |
256 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
257 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
258 | } |
259 | ||
091a3ac7 CF |
260 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
261 | ||
262 | static hashval_t | |
263 | const_fixed_htab_hash (const void *x) | |
264 | { | |
3101faab | 265 | const_rtx const value = (const_rtx) x; |
091a3ac7 CF |
266 | hashval_t h; |
267 | ||
268 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
269 | /* MODE is used in the comparison, so it should be in the hash. */ | |
270 | h ^= GET_MODE (value); | |
271 | return h; | |
272 | } | |
273 | ||
274 | /* Returns nonzero if the value represented by X (really a ...) | |
275 | is the same as that represented by Y (really a ...). */ | |
276 | ||
277 | static int | |
278 | const_fixed_htab_eq (const void *x, const void *y) | |
279 | { | |
3101faab | 280 | const_rtx const a = (const_rtx) x, b = (const_rtx) y; |
091a3ac7 CF |
281 | |
282 | if (GET_MODE (a) != GET_MODE (b)) | |
283 | return 0; | |
284 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
285 | } | |
286 | ||
173b24b9 RK |
287 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
288 | ||
289 | static hashval_t | |
502b8322 | 290 | mem_attrs_htab_hash (const void *x) |
173b24b9 | 291 | { |
f7d504c2 | 292 | const mem_attrs *const p = (const mem_attrs *) x; |
173b24b9 RK |
293 | |
294 | return (p->alias ^ (p->align * 1000) | |
295 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) | |
296 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
78b76d08 | 297 | ^ (size_t) iterative_hash_expr (p->expr, 0)); |
173b24b9 RK |
298 | } |
299 | ||
cc2902df | 300 | /* Returns nonzero if the value represented by X (which is really a |
173b24b9 RK |
301 | mem_attrs *) is the same as that given by Y (which is also really a |
302 | mem_attrs *). */ | |
c13e8210 MM |
303 | |
304 | static int | |
502b8322 | 305 | mem_attrs_htab_eq (const void *x, const void *y) |
c13e8210 | 306 | { |
741ac903 KG |
307 | const mem_attrs *const p = (const mem_attrs *) x; |
308 | const mem_attrs *const q = (const mem_attrs *) y; | |
173b24b9 | 309 | |
78b76d08 SB |
310 | return (p->alias == q->alias && p->offset == q->offset |
311 | && p->size == q->size && p->align == q->align | |
312 | && (p->expr == q->expr | |
313 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
314 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
315 | } |
316 | ||
173b24b9 | 317 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
10b76d73 RK |
318 | one identical to it is not already in the table. We are doing this for |
319 | MEM of mode MODE. */ | |
173b24b9 RK |
320 | |
321 | static mem_attrs * | |
4862826d | 322 | get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size, |
502b8322 | 323 | unsigned int align, enum machine_mode mode) |
173b24b9 RK |
324 | { |
325 | mem_attrs attrs; | |
326 | void **slot; | |
327 | ||
bb056a77 OH |
328 | /* If everything is the default, we can just return zero. |
329 | This must match what the corresponding MEM_* macros return when the | |
330 | field is not present. */ | |
998d7deb | 331 | if (alias == 0 && expr == 0 && offset == 0 |
10b76d73 RK |
332 | && (size == 0 |
333 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
bb056a77 OH |
334 | && (STRICT_ALIGNMENT && mode != BLKmode |
335 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
10b76d73 RK |
336 | return 0; |
337 | ||
173b24b9 | 338 | attrs.alias = alias; |
998d7deb | 339 | attrs.expr = expr; |
173b24b9 RK |
340 | attrs.offset = offset; |
341 | attrs.size = size; | |
342 | attrs.align = align; | |
343 | ||
344 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
345 | if (*slot == 0) | |
346 | { | |
347 | *slot = ggc_alloc (sizeof (mem_attrs)); | |
348 | memcpy (*slot, &attrs, sizeof (mem_attrs)); | |
349 | } | |
350 | ||
1b4572a8 | 351 | return (mem_attrs *) *slot; |
c13e8210 MM |
352 | } |
353 | ||
a560d4d4 JH |
354 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
355 | ||
356 | static hashval_t | |
502b8322 | 357 | reg_attrs_htab_hash (const void *x) |
a560d4d4 | 358 | { |
741ac903 | 359 | const reg_attrs *const p = (const reg_attrs *) x; |
a560d4d4 JH |
360 | |
361 | return ((p->offset * 1000) ^ (long) p->decl); | |
362 | } | |
363 | ||
6356f892 | 364 | /* Returns nonzero if the value represented by X (which is really a |
a560d4d4 JH |
365 | reg_attrs *) is the same as that given by Y (which is also really a |
366 | reg_attrs *). */ | |
367 | ||
368 | static int | |
502b8322 | 369 | reg_attrs_htab_eq (const void *x, const void *y) |
a560d4d4 | 370 | { |
741ac903 KG |
371 | const reg_attrs *const p = (const reg_attrs *) x; |
372 | const reg_attrs *const q = (const reg_attrs *) y; | |
a560d4d4 JH |
373 | |
374 | return (p->decl == q->decl && p->offset == q->offset); | |
375 | } | |
376 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
377 | one identical to it is not already in the table. We are doing this for | |
378 | MEM of mode MODE. */ | |
379 | ||
380 | static reg_attrs * | |
502b8322 | 381 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
382 | { |
383 | reg_attrs attrs; | |
384 | void **slot; | |
385 | ||
386 | /* If everything is the default, we can just return zero. */ | |
387 | if (decl == 0 && offset == 0) | |
388 | return 0; | |
389 | ||
390 | attrs.decl = decl; | |
391 | attrs.offset = offset; | |
392 | ||
393 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
394 | if (*slot == 0) | |
395 | { | |
396 | *slot = ggc_alloc (sizeof (reg_attrs)); | |
397 | memcpy (*slot, &attrs, sizeof (reg_attrs)); | |
398 | } | |
399 | ||
1b4572a8 | 400 | return (reg_attrs *) *slot; |
a560d4d4 JH |
401 | } |
402 | ||
6fb5fa3c DB |
403 | |
404 | #if !HAVE_blockage | |
405 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule | |
406 | across this insn. */ | |
407 | ||
408 | rtx | |
409 | gen_blockage (void) | |
410 | { | |
411 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
412 | MEM_VOLATILE_P (x) = true; | |
413 | return x; | |
414 | } | |
415 | #endif | |
416 | ||
417 | ||
08394eef BS |
418 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
419 | don't attempt to share with the various global pieces of rtl (such as | |
420 | frame_pointer_rtx). */ | |
421 | ||
422 | rtx | |
502b8322 | 423 | gen_raw_REG (enum machine_mode mode, int regno) |
08394eef BS |
424 | { |
425 | rtx x = gen_rtx_raw_REG (mode, regno); | |
426 | ORIGINAL_REGNO (x) = regno; | |
427 | return x; | |
428 | } | |
429 | ||
c5c76735 JL |
430 | /* There are some RTL codes that require special attention; the generation |
431 | functions do the raw handling. If you add to this list, modify | |
432 | special_rtx in gengenrtl.c as well. */ | |
433 | ||
3b80f6ca | 434 | rtx |
502b8322 | 435 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca | 436 | { |
c13e8210 MM |
437 | void **slot; |
438 | ||
3b80f6ca | 439 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 440 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
441 | |
442 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
443 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
444 | return const_true_rtx; | |
445 | #endif | |
446 | ||
c13e8210 | 447 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
448 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
449 | (hashval_t) arg, INSERT); | |
29105cea | 450 | if (*slot == 0) |
1f8f4a0b | 451 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
452 | |
453 | return (rtx) *slot; | |
3b80f6ca RH |
454 | } |
455 | ||
2496c7bd | 456 | rtx |
502b8322 | 457 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2496c7bd LB |
458 | { |
459 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
460 | } | |
461 | ||
5692c7bc ZW |
462 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
463 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
464 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
465 | ||
466 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
467 | hash table. If so, return its counterpart; otherwise add it | |
468 | to the hash table and return it. */ | |
469 | static rtx | |
502b8322 | 470 | lookup_const_double (rtx real) |
5692c7bc ZW |
471 | { |
472 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
473 | if (*slot == 0) | |
474 | *slot = real; | |
475 | ||
476 | return (rtx) *slot; | |
477 | } | |
29105cea | 478 | |
5692c7bc ZW |
479 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
480 | VALUE in mode MODE. */ | |
0133b7d9 | 481 | rtx |
502b8322 | 482 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
0133b7d9 | 483 | { |
5692c7bc ZW |
484 | rtx real = rtx_alloc (CONST_DOUBLE); |
485 | PUT_MODE (real, mode); | |
486 | ||
9e254451 | 487 | real->u.rv = value; |
5692c7bc ZW |
488 | |
489 | return lookup_const_double (real); | |
490 | } | |
491 | ||
091a3ac7 CF |
492 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
493 | hash table. If so, return its counterpart; otherwise add it | |
494 | to the hash table and return it. */ | |
495 | ||
496 | static rtx | |
497 | lookup_const_fixed (rtx fixed) | |
498 | { | |
499 | void **slot = htab_find_slot (const_fixed_htab, fixed, INSERT); | |
500 | if (*slot == 0) | |
501 | *slot = fixed; | |
502 | ||
503 | return (rtx) *slot; | |
504 | } | |
505 | ||
506 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
507 | VALUE in mode MODE. */ | |
508 | ||
509 | rtx | |
510 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, enum machine_mode mode) | |
511 | { | |
512 | rtx fixed = rtx_alloc (CONST_FIXED); | |
513 | PUT_MODE (fixed, mode); | |
514 | ||
515 | fixed->u.fv = value; | |
516 | ||
517 | return lookup_const_fixed (fixed); | |
518 | } | |
519 | ||
5692c7bc ZW |
520 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
521 | of ints: I0 is the low-order word and I1 is the high-order word. | |
522 | Do not use this routine for non-integer modes; convert to | |
523 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
524 | ||
525 | rtx | |
502b8322 | 526 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
5692c7bc ZW |
527 | { |
528 | rtx value; | |
529 | unsigned int i; | |
530 | ||
65acccdd ZD |
531 | /* There are the following cases (note that there are no modes with |
532 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT): | |
533 | ||
534 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
535 | gen_int_mode. | |
536 | 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of | |
537 | the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only | |
538 | from copies of the sign bit, and sign of i0 and i1 are the same), then | |
539 | we return a CONST_INT for i0. | |
540 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ | |
5692c7bc ZW |
541 | if (mode != VOIDmode) |
542 | { | |
5b0264cb NS |
543 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
544 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
545 | /* We can get a 0 for an error mark. */ | |
546 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
547 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT); | |
5692c7bc | 548 | |
65acccdd ZD |
549 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
550 | return gen_int_mode (i0, mode); | |
551 | ||
552 | gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT); | |
5692c7bc ZW |
553 | } |
554 | ||
555 | /* If this integer fits in one word, return a CONST_INT. */ | |
556 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
557 | return GEN_INT (i0); | |
558 | ||
559 | /* We use VOIDmode for integers. */ | |
560 | value = rtx_alloc (CONST_DOUBLE); | |
561 | PUT_MODE (value, VOIDmode); | |
562 | ||
563 | CONST_DOUBLE_LOW (value) = i0; | |
564 | CONST_DOUBLE_HIGH (value) = i1; | |
565 | ||
566 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
567 | XWINT (value, i) = 0; | |
568 | ||
569 | return lookup_const_double (value); | |
0133b7d9 RH |
570 | } |
571 | ||
3b80f6ca | 572 | rtx |
502b8322 | 573 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3b80f6ca RH |
574 | { |
575 | /* In case the MD file explicitly references the frame pointer, have | |
576 | all such references point to the same frame pointer. This is | |
577 | used during frame pointer elimination to distinguish the explicit | |
578 | references to these registers from pseudos that happened to be | |
579 | assigned to them. | |
580 | ||
581 | If we have eliminated the frame pointer or arg pointer, we will | |
582 | be using it as a normal register, for example as a spill | |
583 | register. In such cases, we might be accessing it in a mode that | |
584 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
585 | ||
586 | Also don't do this when we are making new REGs in reload, since | |
587 | we don't want to get confused with the real pointers. */ | |
588 | ||
589 | if (mode == Pmode && !reload_in_progress) | |
590 | { | |
e10c79fe LB |
591 | if (regno == FRAME_POINTER_REGNUM |
592 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
593 | return frame_pointer_rtx; |
594 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e10c79fe LB |
595 | if (regno == HARD_FRAME_POINTER_REGNUM |
596 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
597 | return hard_frame_pointer_rtx; |
598 | #endif | |
599 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 600 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
601 | return arg_pointer_rtx; |
602 | #endif | |
603 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 604 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
605 | return return_address_pointer_rtx; |
606 | #endif | |
fc555370 | 607 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
2d67bd7b | 608 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 609 | return pic_offset_table_rtx; |
bcb33994 | 610 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
611 | return stack_pointer_rtx; |
612 | } | |
613 | ||
006a94b0 | 614 | #if 0 |
6cde4876 | 615 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
616 | an existing entry in that table to avoid useless generation of RTL. |
617 | ||
618 | This code is disabled for now until we can fix the various backends | |
619 | which depend on having non-shared hard registers in some cases. Long | |
620 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
621 | on the amount of useless RTL that gets generated. |
622 | ||
623 | We'll also need to fix some code that runs after reload that wants to | |
624 | set ORIGINAL_REGNO. */ | |
625 | ||
6cde4876 JL |
626 | if (cfun |
627 | && cfun->emit | |
628 | && regno_reg_rtx | |
629 | && regno < FIRST_PSEUDO_REGISTER | |
630 | && reg_raw_mode[regno] == mode) | |
631 | return regno_reg_rtx[regno]; | |
006a94b0 | 632 | #endif |
6cde4876 | 633 | |
08394eef | 634 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
635 | } |
636 | ||
41472af8 | 637 | rtx |
502b8322 | 638 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
41472af8 MM |
639 | { |
640 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
641 | ||
642 | /* This field is not cleared by the mere allocation of the rtx, so | |
643 | we clear it here. */ | |
173b24b9 | 644 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
645 | |
646 | return rt; | |
647 | } | |
ddef6bc7 | 648 | |
542a8afa RH |
649 | /* Generate a memory referring to non-trapping constant memory. */ |
650 | ||
651 | rtx | |
652 | gen_const_mem (enum machine_mode mode, rtx addr) | |
653 | { | |
654 | rtx mem = gen_rtx_MEM (mode, addr); | |
655 | MEM_READONLY_P (mem) = 1; | |
656 | MEM_NOTRAP_P (mem) = 1; | |
657 | return mem; | |
658 | } | |
659 | ||
bf877a76 R |
660 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
661 | save areas. */ | |
662 | ||
663 | rtx | |
664 | gen_frame_mem (enum machine_mode mode, rtx addr) | |
665 | { | |
666 | rtx mem = gen_rtx_MEM (mode, addr); | |
667 | MEM_NOTRAP_P (mem) = 1; | |
668 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
669 | return mem; | |
670 | } | |
671 | ||
672 | /* Generate a MEM referring to a temporary use of the stack, not part | |
673 | of the fixed stack frame. For example, something which is pushed | |
674 | by a target splitter. */ | |
675 | rtx | |
676 | gen_tmp_stack_mem (enum machine_mode mode, rtx addr) | |
677 | { | |
678 | rtx mem = gen_rtx_MEM (mode, addr); | |
679 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 680 | if (!cfun->calls_alloca) |
bf877a76 R |
681 | set_mem_alias_set (mem, get_frame_alias_set ()); |
682 | return mem; | |
683 | } | |
684 | ||
beb72684 RH |
685 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
686 | this construct would be valid, and false otherwise. */ | |
687 | ||
688 | bool | |
689 | validate_subreg (enum machine_mode omode, enum machine_mode imode, | |
ed7a4b4b | 690 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 691 | { |
beb72684 RH |
692 | unsigned int isize = GET_MODE_SIZE (imode); |
693 | unsigned int osize = GET_MODE_SIZE (omode); | |
694 | ||
695 | /* All subregs must be aligned. */ | |
696 | if (offset % osize != 0) | |
697 | return false; | |
698 | ||
699 | /* The subreg offset cannot be outside the inner object. */ | |
700 | if (offset >= isize) | |
701 | return false; | |
702 | ||
703 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
704 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
705 | Generally, backends are doing something sketchy but it'll take time to | |
706 | fix them all. */ | |
707 | if (omode == word_mode) | |
708 | ; | |
709 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
710 | is the culprit here, and not the backends. */ | |
711 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
712 | ; | |
713 | /* Allow component subregs of complex and vector. Though given the below | |
714 | extraction rules, it's not always clear what that means. */ | |
715 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
716 | && GET_MODE_INNER (imode) == omode) | |
717 | ; | |
718 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
719 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
720 | represent this. It's questionable if this ought to be represented at | |
721 | all -- why can't this all be hidden in post-reload splitters that make | |
722 | arbitrarily mode changes to the registers themselves. */ | |
723 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
724 | ; | |
725 | /* Subregs involving floating point modes are not allowed to | |
726 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
727 | (subreg:SI (reg:DF) 0) isn't. */ | |
728 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
729 | { | |
730 | if (isize != osize) | |
731 | return false; | |
732 | } | |
ddef6bc7 | 733 | |
beb72684 RH |
734 | /* Paradoxical subregs must have offset zero. */ |
735 | if (osize > isize) | |
736 | return offset == 0; | |
737 | ||
738 | /* This is a normal subreg. Verify that the offset is representable. */ | |
739 | ||
740 | /* For hard registers, we already have most of these rules collected in | |
741 | subreg_offset_representable_p. */ | |
742 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
743 | { | |
744 | unsigned int regno = REGNO (reg); | |
745 | ||
746 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
747 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
748 | && GET_MODE_INNER (imode) == omode) | |
749 | ; | |
750 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
751 | return false; | |
ddef6bc7 | 752 | #endif |
beb72684 RH |
753 | |
754 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
755 | } | |
756 | ||
757 | /* For pseudo registers, we want most of the same checks. Namely: | |
758 | If the register no larger than a word, the subreg must be lowpart. | |
759 | If the register is larger than a word, the subreg must be the lowpart | |
760 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
761 | Given that we've already checked mode/offset alignment, we only have | |
762 | to check subword subregs here. */ | |
763 | if (osize < UNITS_PER_WORD) | |
764 | { | |
765 | enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; | |
766 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); | |
767 | if (offset % UNITS_PER_WORD != low_off) | |
768 | return false; | |
769 | } | |
770 | return true; | |
771 | } | |
772 | ||
773 | rtx | |
774 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) | |
775 | { | |
776 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 777 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
778 | } |
779 | ||
173b24b9 RK |
780 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
781 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
782 | ||
ddef6bc7 | 783 | rtx |
502b8322 | 784 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
ddef6bc7 JJ |
785 | { |
786 | enum machine_mode inmode; | |
ddef6bc7 JJ |
787 | |
788 | inmode = GET_MODE (reg); | |
789 | if (inmode == VOIDmode) | |
790 | inmode = mode; | |
e0e08ac2 JH |
791 | return gen_rtx_SUBREG (mode, reg, |
792 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 793 | } |
c5c76735 | 794 | \f |
23b2ce53 | 795 | |
80379f51 PB |
796 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
797 | ||
23b2ce53 | 798 | rtvec |
e34d07f2 | 799 | gen_rtvec (int n, ...) |
23b2ce53 | 800 | { |
80379f51 PB |
801 | int i; |
802 | rtvec rt_val; | |
e34d07f2 | 803 | va_list p; |
23b2ce53 | 804 | |
e34d07f2 | 805 | va_start (p, n); |
23b2ce53 | 806 | |
80379f51 | 807 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 808 | if (n == 0) |
80379f51 | 809 | return NULL_RTVEC; |
23b2ce53 | 810 | |
80379f51 | 811 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 812 | |
23b2ce53 | 813 | for (i = 0; i < n; i++) |
80379f51 | 814 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 815 | |
e34d07f2 | 816 | va_end (p); |
80379f51 | 817 | return rt_val; |
23b2ce53 RS |
818 | } |
819 | ||
820 | rtvec | |
502b8322 | 821 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 822 | { |
b3694847 SS |
823 | int i; |
824 | rtvec rt_val; | |
23b2ce53 | 825 | |
80379f51 | 826 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 827 | if (n == 0) |
80379f51 | 828 | return NULL_RTVEC; |
23b2ce53 | 829 | |
80379f51 | 830 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
831 | |
832 | for (i = 0; i < n; i++) | |
8f985ec4 | 833 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
834 | |
835 | return rt_val; | |
836 | } | |
837 | \f | |
38ae7651 RS |
838 | /* Return the number of bytes between the start of an OUTER_MODE |
839 | in-memory value and the start of an INNER_MODE in-memory value, | |
840 | given that the former is a lowpart of the latter. It may be a | |
841 | paradoxical lowpart, in which case the offset will be negative | |
842 | on big-endian targets. */ | |
843 | ||
844 | int | |
845 | byte_lowpart_offset (enum machine_mode outer_mode, | |
846 | enum machine_mode inner_mode) | |
847 | { | |
848 | if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)) | |
849 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
850 | else | |
851 | return -subreg_lowpart_offset (inner_mode, outer_mode); | |
852 | } | |
853 | \f | |
23b2ce53 RS |
854 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
855 | This pseudo is assigned the next sequential register number. */ | |
856 | ||
857 | rtx | |
502b8322 | 858 | gen_reg_rtx (enum machine_mode mode) |
23b2ce53 | 859 | { |
b3694847 | 860 | rtx val; |
2e3f842f | 861 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 862 | |
f8335a4f | 863 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 864 | |
2e3f842f L |
865 | /* If a virtual register with bigger mode alignment is generated, |
866 | increase stack alignment estimation because it might be spilled | |
867 | to stack later. */ | |
868 | if (SUPPORTS_STACK_ALIGNMENT | |
869 | && crtl->stack_alignment_estimated < align | |
870 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
871 | { |
872 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
873 | if (crtl->stack_alignment_estimated < min_align) | |
874 | crtl->stack_alignment_estimated = min_align; | |
875 | } | |
2e3f842f | 876 | |
1b3d8f8a GK |
877 | if (generating_concat_p |
878 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
879 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
880 | { |
881 | /* For complex modes, don't make a single pseudo. | |
882 | Instead, make a CONCAT of two pseudos. | |
883 | This allows noncontiguous allocation of the real and imaginary parts, | |
884 | which makes much better code. Besides, allocating DCmode | |
885 | pseudos overstrains reload on some machines like the 386. */ | |
886 | rtx realpart, imagpart; | |
27e58a70 | 887 | enum machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
888 | |
889 | realpart = gen_reg_rtx (partmode); | |
890 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 891 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
892 | } |
893 | ||
a560d4d4 | 894 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 895 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 896 | |
3e029763 | 897 | if (reg_rtx_no == crtl->emit.regno_pointer_align_length) |
23b2ce53 | 898 | { |
3e029763 | 899 | int old_size = crtl->emit.regno_pointer_align_length; |
60564289 | 900 | char *tmp; |
0d4903b8 | 901 | rtx *new1; |
0d4903b8 | 902 | |
60564289 KG |
903 | tmp = XRESIZEVEC (char, crtl->emit.regno_pointer_align, old_size * 2); |
904 | memset (tmp + old_size, 0, old_size); | |
905 | crtl->emit.regno_pointer_align = (unsigned char *) tmp; | |
49ad7cfa | 906 | |
1b4572a8 | 907 | new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, old_size * 2); |
49ad7cfa | 908 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
909 | regno_reg_rtx = new1; |
910 | ||
3e029763 | 911 | crtl->emit.regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
912 | } |
913 | ||
08394eef | 914 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
915 | regno_reg_rtx[reg_rtx_no++] = val; |
916 | return val; | |
917 | } | |
918 | ||
38ae7651 RS |
919 | /* Update NEW with the same attributes as REG, but with OFFSET added |
920 | to the REG_OFFSET. */ | |
a560d4d4 | 921 | |
e53a16e7 | 922 | static void |
60564289 | 923 | update_reg_offset (rtx new_rtx, rtx reg, int offset) |
a560d4d4 | 924 | { |
60564289 | 925 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 926 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
927 | } |
928 | ||
38ae7651 RS |
929 | /* Generate a register with same attributes as REG, but with OFFSET |
930 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
931 | |
932 | rtx | |
933 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, | |
934 | int offset) | |
935 | { | |
60564289 | 936 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 937 | |
60564289 KG |
938 | update_reg_offset (new_rtx, reg, offset); |
939 | return new_rtx; | |
e53a16e7 ILT |
940 | } |
941 | ||
942 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 943 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
944 | |
945 | rtx | |
946 | gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset) | |
947 | { | |
60564289 | 948 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 949 | |
60564289 KG |
950 | update_reg_offset (new_rtx, reg, offset); |
951 | return new_rtx; | |
a560d4d4 JH |
952 | } |
953 | ||
38ae7651 RS |
954 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
955 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
956 | |
957 | void | |
38ae7651 | 958 | adjust_reg_mode (rtx reg, enum machine_mode mode) |
a560d4d4 | 959 | { |
38ae7651 RS |
960 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
961 | PUT_MODE (reg, mode); | |
962 | } | |
963 | ||
964 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
965 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
966 | ||
967 | void | |
968 | set_reg_attrs_from_value (rtx reg, rtx x) | |
969 | { | |
970 | int offset; | |
971 | ||
923ba36f JJ |
972 | /* Hard registers can be reused for multiple purposes within the same |
973 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
974 | on them is wrong. */ | |
975 | if (HARD_REGISTER_P (reg)) | |
976 | return; | |
977 | ||
38ae7651 | 978 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
979 | if (MEM_P (x)) |
980 | { | |
481683e1 | 981 | if (MEM_OFFSET (x) && CONST_INT_P (MEM_OFFSET (x))) |
46b71b03 PB |
982 | REG_ATTRS (reg) |
983 | = get_reg_attrs (MEM_EXPR (x), INTVAL (MEM_OFFSET (x)) + offset); | |
984 | if (MEM_POINTER (x)) | |
0a317111 | 985 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
986 | } |
987 | else if (REG_P (x)) | |
988 | { | |
989 | if (REG_ATTRS (x)) | |
990 | update_reg_offset (reg, x, offset); | |
991 | if (REG_POINTER (x)) | |
992 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); | |
993 | } | |
994 | } | |
995 | ||
996 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
997 | and attributes from X. */ | |
998 | ||
999 | rtx | |
1000 | gen_reg_rtx_and_attrs (rtx x) | |
1001 | { | |
1002 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1003 | set_reg_attrs_from_value (reg, x); | |
1004 | return reg; | |
a560d4d4 JH |
1005 | } |
1006 | ||
9d18e06b JZ |
1007 | /* Set the register attributes for registers contained in PARM_RTX. |
1008 | Use needed values from memory attributes of MEM. */ | |
1009 | ||
1010 | void | |
502b8322 | 1011 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1012 | { |
f8cfc6aa | 1013 | if (REG_P (parm_rtx)) |
38ae7651 | 1014 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1015 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1016 | { | |
1017 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1018 | parameter goes both on the stack and in registers. */ | |
1019 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1020 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1021 | { | |
1022 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1023 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1024 | REG_ATTRS (XEXP (x, 0)) |
1025 | = get_reg_attrs (MEM_EXPR (mem), | |
1026 | INTVAL (XEXP (x, 1))); | |
1027 | } | |
1028 | } | |
1029 | } | |
1030 | ||
38ae7651 RS |
1031 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1032 | decl T. */ | |
a560d4d4 | 1033 | |
4e3825db | 1034 | void |
38ae7651 RS |
1035 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1036 | { | |
1037 | if (GET_CODE (x) == SUBREG) | |
fbe6ec81 | 1038 | { |
38ae7651 RS |
1039 | gcc_assert (subreg_lowpart_p (x)); |
1040 | x = SUBREG_REG (x); | |
fbe6ec81 | 1041 | } |
f8cfc6aa | 1042 | if (REG_P (x)) |
38ae7651 RS |
1043 | REG_ATTRS (x) |
1044 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
726612d2 | 1045 | DECL_MODE (t))); |
a560d4d4 JH |
1046 | if (GET_CODE (x) == CONCAT) |
1047 | { | |
1048 | if (REG_P (XEXP (x, 0))) | |
1049 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1050 | if (REG_P (XEXP (x, 1))) | |
1051 | REG_ATTRS (XEXP (x, 1)) | |
1052 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1053 | } | |
1054 | if (GET_CODE (x) == PARALLEL) | |
1055 | { | |
d4afac5b JZ |
1056 | int i, start; |
1057 | ||
1058 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1059 | both on the stack and in registers. */ | |
1060 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1061 | start = 0; | |
1062 | else | |
1063 | start = 1; | |
1064 | ||
1065 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1066 | { |
1067 | rtx y = XVECEXP (x, 0, i); | |
1068 | if (REG_P (XEXP (y, 0))) | |
1069 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1070 | } | |
1071 | } | |
1072 | } | |
1073 | ||
38ae7651 RS |
1074 | /* Assign the RTX X to declaration T. */ |
1075 | ||
1076 | void | |
1077 | set_decl_rtl (tree t, rtx x) | |
1078 | { | |
1079 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1080 | if (x) | |
1081 | set_reg_attrs_for_decl_rtl (t, x); | |
1082 | } | |
1083 | ||
5141868d RS |
1084 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1085 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1086 | |
1087 | void | |
5141868d | 1088 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1089 | { |
1090 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1091 | if (x && !by_reference_p) |
38ae7651 RS |
1092 | set_reg_attrs_for_decl_rtl (t, x); |
1093 | } | |
1094 | ||
754fdcca RK |
1095 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1096 | ||
1097 | void | |
502b8322 | 1098 | mark_user_reg (rtx reg) |
754fdcca RK |
1099 | { |
1100 | if (GET_CODE (reg) == CONCAT) | |
1101 | { | |
1102 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1103 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1104 | } | |
754fdcca | 1105 | else |
5b0264cb NS |
1106 | { |
1107 | gcc_assert (REG_P (reg)); | |
1108 | REG_USERVAR_P (reg) = 1; | |
1109 | } | |
754fdcca RK |
1110 | } |
1111 | ||
86fe05e0 RK |
1112 | /* Identify REG as a probable pointer register and show its alignment |
1113 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1114 | |
1115 | void | |
502b8322 | 1116 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1117 | { |
3502dc9c | 1118 | if (! REG_POINTER (reg)) |
00995e78 | 1119 | { |
3502dc9c | 1120 | REG_POINTER (reg) = 1; |
86fe05e0 | 1121 | |
00995e78 RE |
1122 | if (align) |
1123 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1124 | } | |
1125 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1126 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1127 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1128 | } |
1129 | ||
1130 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1131 | ||
1132 | int | |
502b8322 | 1133 | max_reg_num (void) |
23b2ce53 RS |
1134 | { |
1135 | return reg_rtx_no; | |
1136 | } | |
1137 | ||
1138 | /* Return 1 + the largest label number used so far in the current function. */ | |
1139 | ||
1140 | int | |
502b8322 | 1141 | max_label_num (void) |
23b2ce53 | 1142 | { |
23b2ce53 RS |
1143 | return label_num; |
1144 | } | |
1145 | ||
1146 | /* Return first label number used in this function (if any were used). */ | |
1147 | ||
1148 | int | |
502b8322 | 1149 | get_first_label_num (void) |
23b2ce53 RS |
1150 | { |
1151 | return first_label_num; | |
1152 | } | |
6de9cd9a DN |
1153 | |
1154 | /* If the rtx for label was created during the expansion of a nested | |
1155 | function, then first_label_num won't include this label number. | |
fa10beec | 1156 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1157 | |
1158 | void | |
1159 | maybe_set_first_label_num (rtx x) | |
1160 | { | |
1161 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1162 | first_label_num = CODE_LABEL_NUMBER (x); | |
1163 | } | |
23b2ce53 RS |
1164 | \f |
1165 | /* Return a value representing some low-order bits of X, where the number | |
1166 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1167 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1168 | representation is returned. |
1169 | ||
1170 | This function handles the cases in common between gen_lowpart, below, | |
1171 | and two variants in cse.c and combine.c. These are the cases that can | |
1172 | be safely handled at all points in the compilation. | |
1173 | ||
1174 | If this is not a case we can handle, return 0. */ | |
1175 | ||
1176 | rtx | |
502b8322 | 1177 | gen_lowpart_common (enum machine_mode mode, rtx x) |
23b2ce53 | 1178 | { |
ddef6bc7 | 1179 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1180 | int xsize; |
ddef6bc7 | 1181 | int offset = 0; |
550d1387 GK |
1182 | enum machine_mode innermode; |
1183 | ||
1184 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1185 | so we have to make one up. Yuk. */ | |
1186 | innermode = GET_MODE (x); | |
481683e1 | 1187 | if (CONST_INT_P (x) |
db487452 | 1188 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) |
550d1387 GK |
1189 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1190 | else if (innermode == VOIDmode) | |
1191 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0); | |
1192 | ||
1193 | xsize = GET_MODE_SIZE (innermode); | |
1194 | ||
5b0264cb | 1195 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1196 | |
550d1387 | 1197 | if (innermode == mode) |
23b2ce53 RS |
1198 | return x; |
1199 | ||
1200 | /* MODE must occupy no more words than the mode of X. */ | |
550d1387 GK |
1201 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1202 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
23b2ce53 RS |
1203 | return 0; |
1204 | ||
53501a19 | 1205 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
3d8bf70f | 1206 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
53501a19 BS |
1207 | return 0; |
1208 | ||
550d1387 | 1209 | offset = subreg_lowpart_offset (mode, innermode); |
23b2ce53 RS |
1210 | |
1211 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1212 | && (GET_MODE_CLASS (mode) == MODE_INT |
1213 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1214 | { |
1215 | /* If we are getting the low-order part of something that has been | |
1216 | sign- or zero-extended, we can either just use the object being | |
1217 | extended or make a narrower extension. If we want an even smaller | |
1218 | piece than the size of the object being extended, call ourselves | |
1219 | recursively. | |
1220 | ||
1221 | This case is used mostly by combine and cse. */ | |
1222 | ||
1223 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1224 | return XEXP (x, 0); | |
550d1387 | 1225 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
23b2ce53 | 1226 | return gen_lowpart_common (mode, XEXP (x, 0)); |
550d1387 | 1227 | else if (msize < xsize) |
3b80f6ca | 1228 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1229 | } |
f8cfc6aa | 1230 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
550d1387 | 1231 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
481683e1 | 1232 | || GET_CODE (x) == CONST_DOUBLE || CONST_INT_P (x)) |
550d1387 | 1233 | return simplify_gen_subreg (mode, x, innermode, offset); |
8aada4ad | 1234 | |
23b2ce53 RS |
1235 | /* Otherwise, we can't do this. */ |
1236 | return 0; | |
1237 | } | |
1238 | \f | |
ccba022b | 1239 | rtx |
502b8322 | 1240 | gen_highpart (enum machine_mode mode, rtx x) |
ccba022b | 1241 | { |
ddef6bc7 | 1242 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1243 | rtx result; |
ddef6bc7 | 1244 | |
ccba022b RS |
1245 | /* This case loses if X is a subreg. To catch bugs early, |
1246 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1247 | gcc_assert (msize <= UNITS_PER_WORD |
1248 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1249 | |
e0e08ac2 JH |
1250 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1251 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb NS |
1252 | gcc_assert (result); |
1253 | ||
09482e0d JW |
1254 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1255 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1256 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1257 | if (MEM_P (result)) |
1258 | { | |
1259 | result = validize_mem (result); | |
1260 | gcc_assert (result); | |
1261 | } | |
1262 | ||
e0e08ac2 JH |
1263 | return result; |
1264 | } | |
5222e470 | 1265 | |
26d249eb | 1266 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1267 | be VOIDmode constant. */ |
1268 | rtx | |
502b8322 | 1269 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
5222e470 JH |
1270 | { |
1271 | if (GET_MODE (exp) != VOIDmode) | |
1272 | { | |
5b0264cb | 1273 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1274 | return gen_highpart (outermode, exp); |
1275 | } | |
1276 | return simplify_gen_subreg (outermode, exp, innermode, | |
1277 | subreg_highpart_offset (outermode, innermode)); | |
1278 | } | |
68252e27 | 1279 | |
38ae7651 | 1280 | /* Return the SUBREG_BYTE for an OUTERMODE lowpart of an INNERMODE value. */ |
8698cce3 | 1281 | |
e0e08ac2 | 1282 | unsigned int |
502b8322 | 1283 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
e0e08ac2 JH |
1284 | { |
1285 | unsigned int offset = 0; | |
1286 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1287 | |
e0e08ac2 | 1288 | if (difference > 0) |
ccba022b | 1289 | { |
e0e08ac2 JH |
1290 | if (WORDS_BIG_ENDIAN) |
1291 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1292 | if (BYTES_BIG_ENDIAN) | |
1293 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1294 | } |
ddef6bc7 | 1295 | |
e0e08ac2 | 1296 | return offset; |
ccba022b | 1297 | } |
eea50aa0 | 1298 | |
e0e08ac2 JH |
1299 | /* Return offset in bytes to get OUTERMODE high part |
1300 | of the value in mode INNERMODE stored in memory in target format. */ | |
1301 | unsigned int | |
502b8322 | 1302 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
eea50aa0 JH |
1303 | { |
1304 | unsigned int offset = 0; | |
1305 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1306 | ||
5b0264cb | 1307 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
e0e08ac2 | 1308 | |
eea50aa0 JH |
1309 | if (difference > 0) |
1310 | { | |
e0e08ac2 | 1311 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1312 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1313 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1314 | offset += difference % UNITS_PER_WORD; |
1315 | } | |
1316 | ||
e0e08ac2 | 1317 | return offset; |
eea50aa0 | 1318 | } |
ccba022b | 1319 | |
23b2ce53 RS |
1320 | /* Return 1 iff X, assumed to be a SUBREG, |
1321 | refers to the least significant part of its containing reg. | |
1322 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1323 | ||
1324 | int | |
fa233e34 | 1325 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1326 | { |
1327 | if (GET_CODE (x) != SUBREG) | |
1328 | return 1; | |
a3a03040 RK |
1329 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1330 | return 0; | |
23b2ce53 | 1331 | |
e0e08ac2 JH |
1332 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1333 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1334 | } |
1335 | \f | |
ddef6bc7 JJ |
1336 | /* Return subword OFFSET of operand OP. |
1337 | The word number, OFFSET, is interpreted as the word number starting | |
1338 | at the low-order address. OFFSET 0 is the low-order word if not | |
1339 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1340 | ||
1341 | If we cannot extract the required word, we return zero. Otherwise, | |
1342 | an rtx corresponding to the requested word will be returned. | |
1343 | ||
1344 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1345 | reload has completed, a valid address will always be returned. After | |
1346 | reload, if a valid address cannot be returned, we return zero. | |
1347 | ||
1348 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1349 | it is the responsibility of the caller. | |
1350 | ||
1351 | MODE is the mode of OP in case it is a CONST_INT. | |
1352 | ||
1353 | ??? This is still rather broken for some cases. The problem for the | |
1354 | moment is that all callers of this thing provide no 'goal mode' to | |
1355 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1356 | in a word based SUBREG world. |
1357 | Now use of this function can be deprecated by simplify_subreg in most | |
1358 | cases. | |
1359 | */ | |
ddef6bc7 JJ |
1360 | |
1361 | rtx | |
502b8322 | 1362 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
ddef6bc7 JJ |
1363 | { |
1364 | if (mode == VOIDmode) | |
1365 | mode = GET_MODE (op); | |
1366 | ||
5b0264cb | 1367 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1368 | |
30f7a378 | 1369 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1370 | if (mode != BLKmode |
1371 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1372 | return 0; | |
1373 | ||
30f7a378 | 1374 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1375 | if (mode != BLKmode |
1376 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1377 | return const0_rtx; | |
1378 | ||
ddef6bc7 | 1379 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1380 | if (MEM_P (op)) |
ddef6bc7 | 1381 | { |
60564289 | 1382 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1383 | |
f1ec5147 | 1384 | if (! validate_address) |
60564289 | 1385 | return new_rtx; |
f1ec5147 RK |
1386 | |
1387 | else if (reload_completed) | |
ddef6bc7 | 1388 | { |
60564289 | 1389 | if (! strict_memory_address_p (word_mode, XEXP (new_rtx, 0))) |
f1ec5147 | 1390 | return 0; |
ddef6bc7 | 1391 | } |
f1ec5147 | 1392 | else |
60564289 | 1393 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1394 | } |
1395 | ||
0631e0bf JH |
1396 | /* Rest can be handled by simplify_subreg. */ |
1397 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1398 | } |
1399 | ||
535a42b1 NS |
1400 | /* Similar to `operand_subword', but never return 0. If we can't |
1401 | extract the required subword, put OP into a register and try again. | |
1402 | The second attempt must succeed. We always validate the address in | |
1403 | this case. | |
23b2ce53 RS |
1404 | |
1405 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1406 | ||
1407 | rtx | |
502b8322 | 1408 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
23b2ce53 | 1409 | { |
ddef6bc7 | 1410 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1411 | |
1412 | if (result) | |
1413 | return result; | |
1414 | ||
1415 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1416 | { |
1417 | /* If this is a register which can not be accessed by words, copy it | |
1418 | to a pseudo register. */ | |
f8cfc6aa | 1419 | if (REG_P (op)) |
77e6b0eb JC |
1420 | op = copy_to_reg (op); |
1421 | else | |
1422 | op = force_reg (mode, op); | |
1423 | } | |
23b2ce53 | 1424 | |
ddef6bc7 | 1425 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1426 | gcc_assert (result); |
23b2ce53 RS |
1427 | |
1428 | return result; | |
1429 | } | |
1430 | \f | |
2b3493c8 AK |
1431 | /* Returns 1 if both MEM_EXPR can be considered equal |
1432 | and 0 otherwise. */ | |
1433 | ||
1434 | int | |
4f588890 | 1435 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1436 | { |
1437 | if (expr1 == expr2) | |
1438 | return 1; | |
1439 | ||
1440 | if (! expr1 || ! expr2) | |
1441 | return 0; | |
1442 | ||
1443 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1444 | return 0; | |
1445 | ||
55b34b5f | 1446 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1447 | } |
1448 | ||
805903b5 JJ |
1449 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1450 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1451 | -1 if not known. */ | |
1452 | ||
1453 | int | |
d9223014 | 1454 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1455 | { |
1456 | tree expr; | |
1457 | unsigned HOST_WIDE_INT offset; | |
1458 | ||
1459 | /* This function can't use | |
1460 | if (!MEM_EXPR (mem) || !MEM_OFFSET (mem) | |
1461 | || !CONST_INT_P (MEM_OFFSET (mem)) | |
1462 | || (get_object_alignment (MEM_EXPR (mem), MEM_ALIGN (mem), align) | |
1463 | < align)) | |
1464 | return -1; | |
1465 | else | |
1466 | return (- INTVAL (MEM_OFFSET (mem))) & (align / BITS_PER_UNIT - 1); | |
1467 | for two reasons: | |
1468 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1469 | for <variable>. get_inner_reference doesn't handle it and | |
1470 | even if it did, the alignment in that case needs to be determined | |
1471 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1472 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1473 | isn't sufficiently aligned, the object it is in might be. */ | |
1474 | gcc_assert (MEM_P (mem)); | |
1475 | expr = MEM_EXPR (mem); | |
1476 | if (expr == NULL_TREE | |
1477 | || MEM_OFFSET (mem) == NULL_RTX | |
1478 | || !CONST_INT_P (MEM_OFFSET (mem))) | |
1479 | return -1; | |
1480 | ||
1481 | offset = INTVAL (MEM_OFFSET (mem)); | |
1482 | if (DECL_P (expr)) | |
1483 | { | |
1484 | if (DECL_ALIGN (expr) < align) | |
1485 | return -1; | |
1486 | } | |
1487 | else if (INDIRECT_REF_P (expr)) | |
1488 | { | |
1489 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1490 | return -1; | |
1491 | } | |
1492 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1493 | { | |
1494 | while (1) | |
1495 | { | |
1496 | tree inner = TREE_OPERAND (expr, 0); | |
1497 | tree field = TREE_OPERAND (expr, 1); | |
1498 | tree byte_offset = component_ref_field_offset (expr); | |
1499 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1500 | ||
1501 | if (!byte_offset | |
1502 | || !host_integerp (byte_offset, 1) | |
1503 | || !host_integerp (bit_offset, 1)) | |
1504 | return -1; | |
1505 | ||
1506 | offset += tree_low_cst (byte_offset, 1); | |
1507 | offset += tree_low_cst (bit_offset, 1) / BITS_PER_UNIT; | |
1508 | ||
1509 | if (inner == NULL_TREE) | |
1510 | { | |
1511 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1512 | < (unsigned int) align) | |
1513 | return -1; | |
1514 | break; | |
1515 | } | |
1516 | else if (DECL_P (inner)) | |
1517 | { | |
1518 | if (DECL_ALIGN (inner) < align) | |
1519 | return -1; | |
1520 | break; | |
1521 | } | |
1522 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1523 | return -1; | |
1524 | expr = inner; | |
1525 | } | |
1526 | } | |
1527 | else | |
1528 | return -1; | |
1529 | ||
1530 | return offset & ((align / BITS_PER_UNIT) - 1); | |
1531 | } | |
1532 | ||
6926c713 | 1533 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1534 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1535 | if we are making a new object of this type. BITPOS is nonzero if |
1536 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1537 | |
1538 | void | |
502b8322 AJ |
1539 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1540 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1541 | { |
4862826d | 1542 | alias_set_type alias = MEM_ALIAS_SET (ref); |
998d7deb | 1543 | tree expr = MEM_EXPR (ref); |
8ac61af7 RK |
1544 | rtx offset = MEM_OFFSET (ref); |
1545 | rtx size = MEM_SIZE (ref); | |
1546 | unsigned int align = MEM_ALIGN (ref); | |
6f1087be | 1547 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 RK |
1548 | tree type; |
1549 | ||
1550 | /* It can happen that type_for_mode was given a mode for which there | |
1551 | is no language-level type. In which case it returns NULL, which | |
1552 | we can see here. */ | |
1553 | if (t == NULL_TREE) | |
1554 | return; | |
1555 | ||
1556 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1557 | if (type == error_mark_node) |
1558 | return; | |
173b24b9 | 1559 | |
173b24b9 RK |
1560 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1561 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1562 | info. Callers should not set DECL_RTL until after the call to | |
1563 | set_mem_attributes. */ | |
5b0264cb | 1564 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1565 | |
738cc472 | 1566 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 RK |
1567 | front-end routine) and use it. */ |
1568 | alias = get_alias_set (t); | |
173b24b9 | 1569 | |
a5e9c810 | 1570 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
07cb6e8c JM |
1571 | MEM_IN_STRUCT_P (ref) |
1572 | = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE; | |
f8ad8d7c | 1573 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1574 | |
8ac61af7 RK |
1575 | /* If we are making an object of this type, or if this is a DECL, we know |
1576 | that it is a scalar if the type is not an aggregate. */ | |
07cb6e8c JM |
1577 | if ((objectp || DECL_P (t)) |
1578 | && ! AGGREGATE_TYPE_P (type) | |
1579 | && TREE_CODE (type) != COMPLEX_TYPE) | |
173b24b9 RK |
1580 | MEM_SCALAR_P (ref) = 1; |
1581 | ||
c3d32120 RK |
1582 | /* We can set the alignment from the type if we are making an object, |
1583 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
7ccf35ed DN |
1584 | if (objectp || TREE_CODE (t) == INDIRECT_REF |
1585 | || TREE_CODE (t) == ALIGN_INDIRECT_REF | |
1586 | || TYPE_ALIGN_OK (type)) | |
c3d32120 | 1587 | align = MAX (align, TYPE_ALIGN (type)); |
7ccf35ed DN |
1588 | else |
1589 | if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF) | |
1590 | { | |
1591 | if (integer_zerop (TREE_OPERAND (t, 1))) | |
1592 | /* We don't know anything about the alignment. */ | |
1593 | align = BITS_PER_UNIT; | |
1594 | else | |
1595 | align = tree_low_cst (TREE_OPERAND (t, 1), 1); | |
1596 | } | |
40c0668b | 1597 | |
738cc472 RK |
1598 | /* If the size is known, we can set that. */ |
1599 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
8ac61af7 | 1600 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
738cc472 | 1601 | |
80965c18 RK |
1602 | /* If T is not a type, we may be able to deduce some more information about |
1603 | the expression. */ | |
1604 | if (! TYPE_P (t)) | |
8ac61af7 | 1605 | { |
8476af98 | 1606 | tree base; |
df96b059 | 1607 | bool align_computed = false; |
389fdba0 | 1608 | |
8ac61af7 RK |
1609 | if (TREE_THIS_VOLATILE (t)) |
1610 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1611 | |
c56e3582 RK |
1612 | /* Now remove any conversions: they don't change what the underlying |
1613 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 1614 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
1615 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
1616 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1617 | t = TREE_OPERAND (t, 0); |
1618 | ||
8476af98 RH |
1619 | /* We may look through structure-like accesses for the purposes of |
1620 | examining TREE_THIS_NOTRAP, but not array-like accesses. */ | |
1621 | base = t; | |
1622 | while (TREE_CODE (base) == COMPONENT_REF | |
1623 | || TREE_CODE (base) == REALPART_EXPR | |
1624 | || TREE_CODE (base) == IMAGPART_EXPR | |
1625 | || TREE_CODE (base) == BIT_FIELD_REF) | |
1626 | base = TREE_OPERAND (base, 0); | |
1627 | ||
1628 | if (DECL_P (base)) | |
1629 | { | |
1630 | if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS)) | |
1631 | MEM_NOTRAP_P (ref) = !DECL_WEAK (base); | |
1632 | else | |
1633 | MEM_NOTRAP_P (ref) = 1; | |
1634 | } | |
1635 | else | |
1636 | MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base); | |
1637 | ||
1638 | base = get_base_address (base); | |
1639 | if (base && DECL_P (base) | |
1640 | && TREE_READONLY (base) | |
1641 | && (TREE_STATIC (base) || DECL_EXTERNAL (base))) | |
1642 | { | |
1643 | tree base_type = TREE_TYPE (base); | |
1644 | gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type)) | |
1645 | || DECL_ARTIFICIAL (base)); | |
1646 | MEM_READONLY_P (ref) = 1; | |
1647 | } | |
1648 | ||
2039d7aa RH |
1649 | /* If this expression uses it's parent's alias set, mark it such |
1650 | that we won't change it. */ | |
1651 | if (component_uses_parent_alias_set (t)) | |
10b76d73 RK |
1652 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1653 | ||
8ac61af7 RK |
1654 | /* If this is a decl, set the attributes of the MEM from it. */ |
1655 | if (DECL_P (t)) | |
1656 | { | |
998d7deb RH |
1657 | expr = t; |
1658 | offset = const0_rtx; | |
6f1087be | 1659 | apply_bitpos = bitpos; |
8ac61af7 RK |
1660 | size = (DECL_SIZE_UNIT (t) |
1661 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1662 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
68252e27 | 1663 | align = DECL_ALIGN (t); |
df96b059 | 1664 | align_computed = true; |
8ac61af7 RK |
1665 | } |
1666 | ||
40c0668b | 1667 | /* If this is a constant, we know the alignment. */ |
6615c446 | 1668 | else if (CONSTANT_CLASS_P (t)) |
9ddfb1a7 RK |
1669 | { |
1670 | align = TYPE_ALIGN (type); | |
1671 | #ifdef CONSTANT_ALIGNMENT | |
1672 | align = CONSTANT_ALIGNMENT (t, align); | |
1673 | #endif | |
df96b059 | 1674 | align_computed = true; |
9ddfb1a7 | 1675 | } |
998d7deb RH |
1676 | |
1677 | /* If this is a field reference and not a bit-field, record it. */ | |
fa10beec | 1678 | /* ??? There is some information that can be gleaned from bit-fields, |
998d7deb RH |
1679 | such as the word offset in the structure that might be modified. |
1680 | But skip it for now. */ | |
1681 | else if (TREE_CODE (t) == COMPONENT_REF | |
1682 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1683 | { | |
55b34b5f | 1684 | expr = t; |
998d7deb | 1685 | offset = const0_rtx; |
6f1087be | 1686 | apply_bitpos = bitpos; |
998d7deb RH |
1687 | /* ??? Any reason the field size would be different than |
1688 | the size we got from the type? */ | |
1689 | } | |
1690 | ||
1691 | /* If this is an array reference, look for an outer field reference. */ | |
1692 | else if (TREE_CODE (t) == ARRAY_REF) | |
1693 | { | |
1694 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1695 | /* We can't modify t, because we use it at the end of the |
1696 | function. */ | |
1697 | tree t2 = t; | |
998d7deb RH |
1698 | |
1699 | do | |
1700 | { | |
1b1838b6 | 1701 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1702 | tree low_bound = array_ref_low_bound (t2); |
1703 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1704 | |
1705 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1706 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1707 | index, then convert to sizetype and multiply by the size of |
1708 | the array element. */ | |
1709 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1710 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1711 | index, low_bound); | |
2567406a | 1712 | |
44de5aeb | 1713 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1714 | size_binop (MULT_EXPR, |
1715 | fold_convert (sizetype, | |
1716 | index), | |
44de5aeb RK |
1717 | unit_size), |
1718 | off_tree); | |
1b1838b6 | 1719 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1720 | } |
1b1838b6 | 1721 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1722 | |
1b1838b6 | 1723 | if (DECL_P (t2)) |
c67a1cf6 | 1724 | { |
1b1838b6 | 1725 | expr = t2; |
40cb04f1 | 1726 | offset = NULL; |
c67a1cf6 | 1727 | if (host_integerp (off_tree, 1)) |
40cb04f1 RH |
1728 | { |
1729 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1730 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1b1838b6 | 1731 | align = DECL_ALIGN (t2); |
fc555370 | 1732 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
40cb04f1 | 1733 | align = aoff; |
df96b059 | 1734 | align_computed = true; |
40cb04f1 | 1735 | offset = GEN_INT (ioff); |
6f1087be | 1736 | apply_bitpos = bitpos; |
40cb04f1 | 1737 | } |
c67a1cf6 | 1738 | } |
1b1838b6 | 1739 | else if (TREE_CODE (t2) == COMPONENT_REF) |
998d7deb | 1740 | { |
55b34b5f RG |
1741 | expr = t2; |
1742 | offset = NULL; | |
998d7deb | 1743 | if (host_integerp (off_tree, 1)) |
6f1087be RH |
1744 | { |
1745 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1746 | apply_bitpos = bitpos; | |
1747 | } | |
998d7deb RH |
1748 | /* ??? Any reason the field size would be different than |
1749 | the size we got from the type? */ | |
1750 | } | |
c67a1cf6 | 1751 | else if (flag_argument_noalias > 1 |
1b096a0a | 1752 | && (INDIRECT_REF_P (t2)) |
1b1838b6 | 1753 | && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL) |
c67a1cf6 | 1754 | { |
1b1838b6 | 1755 | expr = t2; |
c67a1cf6 RH |
1756 | offset = NULL; |
1757 | } | |
1758 | } | |
1759 | ||
1760 | /* If this is a Fortran indirect argument reference, record the | |
1761 | parameter decl. */ | |
1762 | else if (flag_argument_noalias > 1 | |
1b096a0a | 1763 | && (INDIRECT_REF_P (t)) |
c67a1cf6 RH |
1764 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) |
1765 | { | |
1766 | expr = t; | |
1767 | offset = NULL; | |
998d7deb | 1768 | } |
df96b059 JJ |
1769 | |
1770 | if (!align_computed && !INDIRECT_REF_P (t)) | |
1771 | { | |
1772 | unsigned int obj_align | |
1773 | = get_object_alignment (t, align, BIGGEST_ALIGNMENT); | |
1774 | align = MAX (align, obj_align); | |
1775 | } | |
8ac61af7 RK |
1776 | } |
1777 | ||
15c812e3 | 1778 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
1779 | bit position offset. Similarly, increase the size of the accessed |
1780 | object to contain the negative offset. */ | |
6f1087be | 1781 | if (apply_bitpos) |
8c317c5f RH |
1782 | { |
1783 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
1784 | if (size) | |
1785 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
1786 | } | |
6f1087be | 1787 | |
7ccf35ed DN |
1788 | if (TREE_CODE (t) == ALIGN_INDIRECT_REF) |
1789 | { | |
fa10beec | 1790 | /* Force EXPR and OFFSET to NULL, since we don't know exactly what |
7ccf35ed DN |
1791 | we're overlapping. */ |
1792 | offset = NULL; | |
1793 | expr = NULL; | |
1794 | } | |
1795 | ||
8ac61af7 | 1796 | /* Now set the attributes we computed above. */ |
10b76d73 | 1797 | MEM_ATTRS (ref) |
998d7deb | 1798 | = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref)); |
8ac61af7 RK |
1799 | |
1800 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
1801 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
738cc472 RK |
1802 | return; |
1803 | ||
8ac61af7 RK |
1804 | /* If it is a reference into an aggregate, this is part of an aggregate. |
1805 | Otherwise we don't know. */ | |
173b24b9 RK |
1806 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
1807 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
1808 | || TREE_CODE (t) == BIT_FIELD_REF) | |
1809 | MEM_IN_STRUCT_P (ref) = 1; | |
1810 | } | |
1811 | ||
6f1087be | 1812 | void |
502b8322 | 1813 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
1814 | { |
1815 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
1816 | } | |
1817 | ||
173b24b9 RK |
1818 | /* Set the alias set of MEM to SET. */ |
1819 | ||
1820 | void | |
4862826d | 1821 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 1822 | { |
68252e27 | 1823 | #ifdef ENABLE_CHECKING |
173b24b9 | 1824 | /* If the new and old alias sets don't conflict, something is wrong. */ |
5b0264cb | 1825 | gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
173b24b9 RK |
1826 | #endif |
1827 | ||
998d7deb | 1828 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
10b76d73 RK |
1829 | MEM_SIZE (mem), MEM_ALIGN (mem), |
1830 | GET_MODE (mem)); | |
173b24b9 | 1831 | } |
738cc472 | 1832 | |
d022d93e | 1833 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
1834 | |
1835 | void | |
502b8322 | 1836 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 1837 | { |
998d7deb | 1838 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
10b76d73 RK |
1839 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
1840 | GET_MODE (mem)); | |
738cc472 | 1841 | } |
1285011e | 1842 | |
998d7deb | 1843 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
1844 | |
1845 | void | |
502b8322 | 1846 | set_mem_expr (rtx mem, tree expr) |
1285011e RK |
1847 | { |
1848 | MEM_ATTRS (mem) | |
998d7deb | 1849 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
1285011e RK |
1850 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); |
1851 | } | |
998d7deb RH |
1852 | |
1853 | /* Set the offset of MEM to OFFSET. */ | |
1854 | ||
1855 | void | |
502b8322 | 1856 | set_mem_offset (rtx mem, rtx offset) |
998d7deb RH |
1857 | { |
1858 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1859 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
1860 | GET_MODE (mem)); | |
35aff10b AM |
1861 | } |
1862 | ||
1863 | /* Set the size of MEM to SIZE. */ | |
1864 | ||
1865 | void | |
502b8322 | 1866 | set_mem_size (rtx mem, rtx size) |
35aff10b AM |
1867 | { |
1868 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1869 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
1870 | GET_MODE (mem)); | |
998d7deb | 1871 | } |
173b24b9 | 1872 | \f |
738cc472 RK |
1873 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
1874 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
1875 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
1876 | returned memory location is required to be valid. The memory | |
1877 | attributes are not changed. */ | |
23b2ce53 | 1878 | |
738cc472 | 1879 | static rtx |
502b8322 | 1880 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
23b2ce53 | 1881 | { |
60564289 | 1882 | rtx new_rtx; |
23b2ce53 | 1883 | |
5b0264cb | 1884 | gcc_assert (MEM_P (memref)); |
23b2ce53 RS |
1885 | if (mode == VOIDmode) |
1886 | mode = GET_MODE (memref); | |
1887 | if (addr == 0) | |
1888 | addr = XEXP (memref, 0); | |
a74ff877 JH |
1889 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
1890 | && (!validate || memory_address_p (mode, addr))) | |
1891 | return memref; | |
23b2ce53 | 1892 | |
f1ec5147 | 1893 | if (validate) |
23b2ce53 | 1894 | { |
f1ec5147 | 1895 | if (reload_in_progress || reload_completed) |
5b0264cb | 1896 | gcc_assert (memory_address_p (mode, addr)); |
f1ec5147 RK |
1897 | else |
1898 | addr = memory_address (mode, addr); | |
23b2ce53 | 1899 | } |
750c9258 | 1900 | |
9b04c6a8 RK |
1901 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1902 | return memref; | |
1903 | ||
60564289 KG |
1904 | new_rtx = gen_rtx_MEM (mode, addr); |
1905 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
1906 | return new_rtx; | |
23b2ce53 | 1907 | } |
792760b9 | 1908 | |
738cc472 RK |
1909 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
1910 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
1911 | |
1912 | rtx | |
502b8322 | 1913 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
f4ef873c | 1914 | { |
60564289 KG |
1915 | rtx new_rtx = change_address_1 (memref, mode, addr, 1), size; |
1916 | enum machine_mode mmode = GET_MODE (new_rtx); | |
4e44c1ef JJ |
1917 | unsigned int align; |
1918 | ||
1919 | size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)); | |
1920 | align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode); | |
c2f7bcc3 | 1921 | |
fdb1c7b3 | 1922 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 1923 | if (new_rtx == memref) |
4e44c1ef JJ |
1924 | { |
1925 | if (MEM_ATTRS (memref) == 0 | |
1926 | || (MEM_EXPR (memref) == NULL | |
1927 | && MEM_OFFSET (memref) == NULL | |
1928 | && MEM_SIZE (memref) == size | |
1929 | && MEM_ALIGN (memref) == align)) | |
60564289 | 1930 | return new_rtx; |
4e44c1ef | 1931 | |
60564289 KG |
1932 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
1933 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 1934 | } |
fdb1c7b3 | 1935 | |
60564289 | 1936 | MEM_ATTRS (new_rtx) |
4e44c1ef | 1937 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, mmode); |
823e3574 | 1938 | |
60564289 | 1939 | return new_rtx; |
f4ef873c | 1940 | } |
792760b9 | 1941 | |
738cc472 RK |
1942 | /* Return a memory reference like MEMREF, but with its mode changed |
1943 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 JJ |
1944 | nonzero, the memory address is forced to be valid. |
1945 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
1946 | and caller is responsible for adjusting MEMREF base register. */ | |
f1ec5147 RK |
1947 | |
1948 | rtx | |
502b8322 AJ |
1949 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
1950 | int validate, int adjust) | |
f1ec5147 | 1951 | { |
823e3574 | 1952 | rtx addr = XEXP (memref, 0); |
60564289 | 1953 | rtx new_rtx; |
738cc472 | 1954 | rtx memoffset = MEM_OFFSET (memref); |
10b76d73 | 1955 | rtx size = 0; |
738cc472 | 1956 | unsigned int memalign = MEM_ALIGN (memref); |
a6fe9ed4 | 1957 | int pbits; |
823e3574 | 1958 | |
fdb1c7b3 JH |
1959 | /* If there are no changes, just return the original memory reference. */ |
1960 | if (mode == GET_MODE (memref) && !offset | |
1961 | && (!validate || memory_address_p (mode, addr))) | |
1962 | return memref; | |
1963 | ||
d14419e4 | 1964 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 1965 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
1966 | (plus (plus reg reg) const_int) -- so do this always. */ |
1967 | addr = copy_rtx (addr); | |
1968 | ||
a6fe9ed4 JM |
1969 | /* Convert a possibly large offset to a signed value within the |
1970 | range of the target address space. */ | |
1971 | pbits = GET_MODE_BITSIZE (Pmode); | |
1972 | if (HOST_BITS_PER_WIDE_INT > pbits) | |
1973 | { | |
1974 | int shift = HOST_BITS_PER_WIDE_INT - pbits; | |
1975 | offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift)) | |
1976 | >> shift); | |
1977 | } | |
1978 | ||
4a78c787 RH |
1979 | if (adjust) |
1980 | { | |
1981 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
1982 | object, we can merge it into the LO_SUM. */ | |
1983 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
1984 | && offset >= 0 | |
1985 | && (unsigned HOST_WIDE_INT) offset | |
1986 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
1987 | addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0), | |
1988 | plus_constant (XEXP (addr, 1), offset)); | |
1989 | else | |
1990 | addr = plus_constant (addr, offset); | |
1991 | } | |
823e3574 | 1992 | |
60564289 | 1993 | new_rtx = change_address_1 (memref, mode, addr, validate); |
738cc472 | 1994 | |
09efeca1 PB |
1995 | /* If the address is a REG, change_address_1 rightfully returns memref, |
1996 | but this would destroy memref's MEM_ATTRS. */ | |
1997 | if (new_rtx == memref && offset != 0) | |
1998 | new_rtx = copy_rtx (new_rtx); | |
1999 | ||
738cc472 RK |
2000 | /* Compute the new values of the memory attributes due to this adjustment. |
2001 | We add the offsets and update the alignment. */ | |
2002 | if (memoffset) | |
2003 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
2004 | ||
03bf2c23 RK |
2005 | /* Compute the new alignment by taking the MIN of the alignment and the |
2006 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2007 | if zero. */ | |
2008 | if (offset != 0) | |
3bf1e984 RK |
2009 | memalign |
2010 | = MIN (memalign, | |
2011 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
738cc472 | 2012 | |
10b76d73 | 2013 | /* We can compute the size in a number of ways. */ |
60564289 KG |
2014 | if (GET_MODE (new_rtx) != BLKmode) |
2015 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new_rtx))); | |
10b76d73 RK |
2016 | else if (MEM_SIZE (memref)) |
2017 | size = plus_constant (MEM_SIZE (memref), -offset); | |
2018 | ||
60564289 KG |
2019 | MEM_ATTRS (new_rtx) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
2020 | memoffset, size, memalign, GET_MODE (new_rtx)); | |
738cc472 RK |
2021 | |
2022 | /* At some point, we should validate that this offset is within the object, | |
2023 | if all the appropriate values are known. */ | |
60564289 | 2024 | return new_rtx; |
f1ec5147 RK |
2025 | } |
2026 | ||
630036c6 JJ |
2027 | /* Return a memory reference like MEMREF, but with its mode changed |
2028 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2029 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2030 | nonzero, the memory address is forced to be valid. */ |
2031 | ||
2032 | rtx | |
502b8322 AJ |
2033 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
2034 | HOST_WIDE_INT offset, int validate) | |
630036c6 JJ |
2035 | { |
2036 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
2037 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
2038 | } | |
2039 | ||
8ac61af7 RK |
2040 | /* Return a memory reference like MEMREF, but whose address is changed by |
2041 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2042 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2043 | |
2044 | rtx | |
502b8322 | 2045 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2046 | { |
60564289 | 2047 | rtx new_rtx, addr = XEXP (memref, 0); |
e3c8ea67 | 2048 | |
60564289 | 2049 | new_rtx = simplify_gen_binary (PLUS, Pmode, addr, offset); |
e3c8ea67 | 2050 | |
68252e27 | 2051 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2052 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2053 | |
2054 | However, if we did go and rearrange things, we can wind up not | |
2055 | being able to recognize the magic around pic_offset_table_rtx. | |
2056 | This stuff is fragile, and is yet another example of why it is | |
2057 | bad to expose PIC machinery too early. */ | |
60564289 | 2058 | if (! memory_address_p (GET_MODE (memref), new_rtx) |
e3c8ea67 RH |
2059 | && GET_CODE (addr) == PLUS |
2060 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2061 | { | |
2062 | addr = force_reg (GET_MODE (addr), addr); | |
60564289 | 2063 | new_rtx = simplify_gen_binary (PLUS, Pmode, addr, offset); |
e3c8ea67 RH |
2064 | } |
2065 | ||
60564289 KG |
2066 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
2067 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1); | |
0d4903b8 | 2068 | |
fdb1c7b3 | 2069 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2070 | if (new_rtx == memref) |
2071 | return new_rtx; | |
fdb1c7b3 | 2072 | |
0d4903b8 RK |
2073 | /* Update the alignment to reflect the offset. Reset the offset, which |
2074 | we don't know. */ | |
60564289 | 2075 | MEM_ATTRS (new_rtx) |
2cc2d4bb | 2076 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, |
9ceca302 | 2077 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
60564289 KG |
2078 | GET_MODE (new_rtx)); |
2079 | return new_rtx; | |
0d4903b8 | 2080 | } |
68252e27 | 2081 | |
792760b9 RK |
2082 | /* Return a memory reference like MEMREF, but with its address changed to |
2083 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2084 | to is the same, just the form of the address is being changed, such as | |
2085 | by putting something into a register. */ | |
2086 | ||
2087 | rtx | |
502b8322 | 2088 | replace_equiv_address (rtx memref, rtx addr) |
792760b9 | 2089 | { |
738cc472 RK |
2090 | /* change_address_1 copies the memory attribute structure without change |
2091 | and that's exactly what we want here. */ | |
40c0668b | 2092 | update_temp_slot_address (XEXP (memref, 0), addr); |
738cc472 | 2093 | return change_address_1 (memref, VOIDmode, addr, 1); |
792760b9 | 2094 | } |
738cc472 | 2095 | |
f1ec5147 RK |
2096 | /* Likewise, but the reference is not required to be valid. */ |
2097 | ||
2098 | rtx | |
502b8322 | 2099 | replace_equiv_address_nv (rtx memref, rtx addr) |
f1ec5147 | 2100 | { |
f1ec5147 RK |
2101 | return change_address_1 (memref, VOIDmode, addr, 0); |
2102 | } | |
e7dfe4bb RH |
2103 | |
2104 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2105 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2106 | cannot issue QImode memory operations and have to use SImode memory | |
2107 | operations plus masking logic. */ | |
2108 | ||
2109 | rtx | |
502b8322 | 2110 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb | 2111 | { |
60564289 KG |
2112 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1); |
2113 | tree expr = MEM_EXPR (new_rtx); | |
2114 | rtx memoffset = MEM_OFFSET (new_rtx); | |
e7dfe4bb RH |
2115 | unsigned int size = GET_MODE_SIZE (mode); |
2116 | ||
fdb1c7b3 | 2117 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2118 | if (new_rtx == memref) |
2119 | return new_rtx; | |
fdb1c7b3 | 2120 | |
e7dfe4bb RH |
2121 | /* If we don't know what offset we were at within the expression, then |
2122 | we can't know if we've overstepped the bounds. */ | |
fa1591cb | 2123 | if (! memoffset) |
e7dfe4bb RH |
2124 | expr = NULL_TREE; |
2125 | ||
2126 | while (expr) | |
2127 | { | |
2128 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2129 | { | |
2130 | tree field = TREE_OPERAND (expr, 1); | |
44de5aeb | 2131 | tree offset = component_ref_field_offset (expr); |
e7dfe4bb RH |
2132 | |
2133 | if (! DECL_SIZE_UNIT (field)) | |
2134 | { | |
2135 | expr = NULL_TREE; | |
2136 | break; | |
2137 | } | |
2138 | ||
2139 | /* Is the field at least as large as the access? If so, ok, | |
2140 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2141 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2142 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
e7dfe4bb RH |
2143 | && INTVAL (memoffset) >= 0) |
2144 | break; | |
2145 | ||
44de5aeb | 2146 | if (! host_integerp (offset, 1)) |
e7dfe4bb RH |
2147 | { |
2148 | expr = NULL_TREE; | |
2149 | break; | |
2150 | } | |
2151 | ||
2152 | expr = TREE_OPERAND (expr, 0); | |
44de5aeb RK |
2153 | memoffset |
2154 | = (GEN_INT (INTVAL (memoffset) | |
2155 | + tree_low_cst (offset, 1) | |
2156 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2157 | / BITS_PER_UNIT))); | |
e7dfe4bb RH |
2158 | } |
2159 | /* Similarly for the decl. */ | |
2160 | else if (DECL_P (expr) | |
2161 | && DECL_SIZE_UNIT (expr) | |
45f79783 | 2162 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
e7dfe4bb RH |
2163 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2164 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2165 | break; | |
2166 | else | |
2167 | { | |
2168 | /* The widened memory access overflows the expression, which means | |
2169 | that it could alias another expression. Zap it. */ | |
2170 | expr = NULL_TREE; | |
2171 | break; | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | if (! expr) | |
2176 | memoffset = NULL_RTX; | |
2177 | ||
2178 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2179 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2180 | ||
60564289 KG |
2181 | MEM_ATTRS (new_rtx) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), |
2182 | MEM_ALIGN (new_rtx), mode); | |
e7dfe4bb | 2183 | |
60564289 | 2184 | return new_rtx; |
e7dfe4bb | 2185 | } |
23b2ce53 | 2186 | \f |
f6129d66 RH |
2187 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2188 | static GTY(()) tree spill_slot_decl; | |
2189 | ||
3d7e23f6 RH |
2190 | tree |
2191 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2192 | { |
2193 | tree d = spill_slot_decl; | |
2194 | rtx rd; | |
2195 | ||
3d7e23f6 | 2196 | if (d || !force_build_p) |
f6129d66 RH |
2197 | return d; |
2198 | ||
c2255bc4 AH |
2199 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2200 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2201 | DECL_ARTIFICIAL (d) = 1; |
2202 | DECL_IGNORED_P (d) = 1; | |
2203 | TREE_USED (d) = 1; | |
2204 | TREE_THIS_NOTRAP (d) = 1; | |
2205 | spill_slot_decl = d; | |
2206 | ||
2207 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2208 | MEM_NOTRAP_P (rd) = 1; | |
2209 | MEM_ATTRS (rd) = get_mem_attrs (new_alias_set (), d, const0_rtx, | |
2210 | NULL_RTX, 0, BLKmode); | |
2211 | SET_DECL_RTL (d, rd); | |
2212 | ||
2213 | return d; | |
2214 | } | |
2215 | ||
2216 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2217 | attributes as appropriate for a register allocator spill slot. | |
2218 | These slots are not aliasable by other memory. We arrange for | |
2219 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2220 | work properly in the case of shared spill slots. */ | |
2221 | ||
2222 | void | |
2223 | set_mem_attrs_for_spill (rtx mem) | |
2224 | { | |
2225 | alias_set_type alias; | |
2226 | rtx addr, offset; | |
2227 | tree expr; | |
2228 | ||
3d7e23f6 | 2229 | expr = get_spill_slot_decl (true); |
f6129d66 RH |
2230 | alias = MEM_ALIAS_SET (DECL_RTL (expr)); |
2231 | ||
2232 | /* We expect the incoming memory to be of the form: | |
2233 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2234 | with perhaps the plus missing for offset = 0. */ | |
2235 | addr = XEXP (mem, 0); | |
2236 | offset = const0_rtx; | |
2237 | if (GET_CODE (addr) == PLUS | |
481683e1 | 2238 | && CONST_INT_P (XEXP (addr, 1))) |
f6129d66 RH |
2239 | offset = XEXP (addr, 1); |
2240 | ||
2241 | MEM_ATTRS (mem) = get_mem_attrs (alias, expr, offset, | |
2242 | MEM_SIZE (mem), MEM_ALIGN (mem), | |
2243 | GET_MODE (mem)); | |
2244 | MEM_NOTRAP_P (mem) = 1; | |
2245 | } | |
2246 | \f | |
23b2ce53 RS |
2247 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2248 | ||
2249 | rtx | |
502b8322 | 2250 | gen_label_rtx (void) |
23b2ce53 | 2251 | { |
0dc36574 | 2252 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
502b8322 | 2253 | NULL, label_num++, NULL); |
23b2ce53 RS |
2254 | } |
2255 | \f | |
2256 | /* For procedure integration. */ | |
2257 | ||
23b2ce53 | 2258 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2259 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2260 | Used for an inline-procedure after copying the insn chain. */ |
2261 | ||
2262 | void | |
502b8322 | 2263 | set_new_first_and_last_insn (rtx first, rtx last) |
23b2ce53 | 2264 | { |
86fe05e0 RK |
2265 | rtx insn; |
2266 | ||
23b2ce53 RS |
2267 | first_insn = first; |
2268 | last_insn = last; | |
86fe05e0 RK |
2269 | cur_insn_uid = 0; |
2270 | ||
b5b8b0ac AO |
2271 | if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS) |
2272 | { | |
2273 | int debug_count = 0; | |
2274 | ||
2275 | cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1; | |
2276 | cur_debug_insn_uid = 0; | |
2277 | ||
2278 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2279 | if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID) | |
2280 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); | |
2281 | else | |
2282 | { | |
2283 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2284 | if (DEBUG_INSN_P (insn)) | |
2285 | debug_count++; | |
2286 | } | |
2287 | ||
2288 | if (debug_count) | |
2289 | cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count; | |
2290 | else | |
2291 | cur_debug_insn_uid++; | |
2292 | } | |
2293 | else | |
2294 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2295 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2296 | |
2297 | cur_insn_uid++; | |
23b2ce53 | 2298 | } |
23b2ce53 | 2299 | \f |
750c9258 | 2300 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2301 | structure. This routine should only be called once. */ |
23b2ce53 | 2302 | |
fd743bc1 | 2303 | static void |
b4aaa77b | 2304 | unshare_all_rtl_1 (rtx insn) |
23b2ce53 | 2305 | { |
d1b81779 | 2306 | /* Unshare just about everything else. */ |
2c07f13b | 2307 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2308 | |
23b2ce53 RS |
2309 | /* Make sure the addresses of stack slots found outside the insn chain |
2310 | (such as, in DECL_RTL of a variable) are not shared | |
2311 | with the insn chain. | |
2312 | ||
2313 | This special care is necessary when the stack slot MEM does not | |
2314 | actually appear in the insn chain. If it does appear, its address | |
2315 | is unshared from all else at that point. */ | |
242b0ce6 | 2316 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
2317 | } |
2318 | ||
750c9258 | 2319 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2320 | structure, again. This is a fairly expensive thing to do so it |
2321 | should be done sparingly. */ | |
2322 | ||
2323 | void | |
502b8322 | 2324 | unshare_all_rtl_again (rtx insn) |
d1b81779 GK |
2325 | { |
2326 | rtx p; | |
624c87aa RE |
2327 | tree decl; |
2328 | ||
d1b81779 | 2329 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2330 | if (INSN_P (p)) |
d1b81779 GK |
2331 | { |
2332 | reset_used_flags (PATTERN (p)); | |
2333 | reset_used_flags (REG_NOTES (p)); | |
d1b81779 | 2334 | } |
624c87aa | 2335 | |
2d4aecb3 | 2336 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2337 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2338 | |
624c87aa RE |
2339 | /* Make sure that virtual parameters are not shared. */ |
2340 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
5eb2a9f2 | 2341 | set_used_flags (DECL_RTL (decl)); |
624c87aa RE |
2342 | |
2343 | reset_used_flags (stack_slot_list); | |
2344 | ||
b4aaa77b | 2345 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2346 | } |
2347 | ||
c2924966 | 2348 | unsigned int |
fd743bc1 PB |
2349 | unshare_all_rtl (void) |
2350 | { | |
b4aaa77b | 2351 | unshare_all_rtl_1 (get_insns ()); |
c2924966 | 2352 | return 0; |
d1b81779 GK |
2353 | } |
2354 | ||
8ddbbcae | 2355 | struct rtl_opt_pass pass_unshare_all_rtl = |
ef330312 | 2356 | { |
8ddbbcae JH |
2357 | { |
2358 | RTL_PASS, | |
defb77dc | 2359 | "unshare", /* name */ |
ef330312 PB |
2360 | NULL, /* gate */ |
2361 | unshare_all_rtl, /* execute */ | |
2362 | NULL, /* sub */ | |
2363 | NULL, /* next */ | |
2364 | 0, /* static_pass_number */ | |
7072a650 | 2365 | TV_NONE, /* tv_id */ |
ef330312 PB |
2366 | 0, /* properties_required */ |
2367 | 0, /* properties_provided */ | |
2368 | 0, /* properties_destroyed */ | |
2369 | 0, /* todo_flags_start */ | |
8ddbbcae JH |
2370 | TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */ |
2371 | } | |
ef330312 PB |
2372 | }; |
2373 | ||
2374 | ||
2c07f13b JH |
2375 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2376 | Recursively does the same for subexpressions. */ | |
2377 | ||
2378 | static void | |
2379 | verify_rtx_sharing (rtx orig, rtx insn) | |
2380 | { | |
2381 | rtx x = orig; | |
2382 | int i; | |
2383 | enum rtx_code code; | |
2384 | const char *format_ptr; | |
2385 | ||
2386 | if (x == 0) | |
2387 | return; | |
2388 | ||
2389 | code = GET_CODE (x); | |
2390 | ||
2391 | /* These types may be freely shared. */ | |
2392 | ||
2393 | switch (code) | |
2394 | { | |
2395 | case REG: | |
2c07f13b JH |
2396 | case CONST_INT: |
2397 | case CONST_DOUBLE: | |
091a3ac7 | 2398 | case CONST_FIXED: |
2c07f13b JH |
2399 | case CONST_VECTOR: |
2400 | case SYMBOL_REF: | |
2401 | case LABEL_REF: | |
2402 | case CODE_LABEL: | |
2403 | case PC: | |
2404 | case CC0: | |
2405 | case SCRATCH: | |
2c07f13b | 2406 | return; |
3e89ed8d JH |
2407 | /* SCRATCH must be shared because they represent distinct values. */ |
2408 | case CLOBBER: | |
2409 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2410 | return; | |
2411 | break; | |
2c07f13b JH |
2412 | |
2413 | case CONST: | |
6fb5fa3c | 2414 | if (shared_const_p (orig)) |
2c07f13b JH |
2415 | return; |
2416 | break; | |
2417 | ||
2418 | case MEM: | |
2419 | /* A MEM is allowed to be shared if its address is constant. */ | |
2420 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2421 | || reload_completed || reload_in_progress) | |
2422 | return; | |
2423 | ||
2424 | break; | |
2425 | ||
2426 | default: | |
2427 | break; | |
2428 | } | |
2429 | ||
2430 | /* This rtx may not be shared. If it has already been seen, | |
2431 | replace it with a copy of itself. */ | |
1a2caa7a | 2432 | #ifdef ENABLE_CHECKING |
2c07f13b JH |
2433 | if (RTX_FLAG (x, used)) |
2434 | { | |
ab532386 | 2435 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2436 | debug_rtx (insn); |
ab532386 | 2437 | error ("shared rtx"); |
2c07f13b | 2438 | debug_rtx (x); |
ab532386 | 2439 | internal_error ("internal consistency failure"); |
2c07f13b | 2440 | } |
1a2caa7a NS |
2441 | #endif |
2442 | gcc_assert (!RTX_FLAG (x, used)); | |
2443 | ||
2c07f13b JH |
2444 | RTX_FLAG (x, used) = 1; |
2445 | ||
6614fd40 | 2446 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2447 | |
2448 | format_ptr = GET_RTX_FORMAT (code); | |
2449 | ||
2450 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2451 | { | |
2452 | switch (*format_ptr++) | |
2453 | { | |
2454 | case 'e': | |
2455 | verify_rtx_sharing (XEXP (x, i), insn); | |
2456 | break; | |
2457 | ||
2458 | case 'E': | |
2459 | if (XVEC (x, i) != NULL) | |
2460 | { | |
2461 | int j; | |
2462 | int len = XVECLEN (x, i); | |
2463 | ||
2464 | for (j = 0; j < len; j++) | |
2465 | { | |
1a2caa7a NS |
2466 | /* We allow sharing of ASM_OPERANDS inside single |
2467 | instruction. */ | |
2c07f13b | 2468 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2469 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2470 | == ASM_OPERANDS)) | |
2c07f13b JH |
2471 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2472 | else | |
2473 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2474 | } | |
2475 | } | |
2476 | break; | |
2477 | } | |
2478 | } | |
2479 | return; | |
2480 | } | |
2481 | ||
ba228239 | 2482 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2c07f13b JH |
2483 | sharing in between the subexpressions. */ |
2484 | ||
2485 | void | |
2486 | verify_rtl_sharing (void) | |
2487 | { | |
2488 | rtx p; | |
2489 | ||
2490 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2491 | if (INSN_P (p)) | |
2492 | { | |
2493 | reset_used_flags (PATTERN (p)); | |
2494 | reset_used_flags (REG_NOTES (p)); | |
2954a813 KK |
2495 | if (GET_CODE (PATTERN (p)) == SEQUENCE) |
2496 | { | |
2497 | int i; | |
2498 | rtx q, sequence = PATTERN (p); | |
2499 | ||
2500 | for (i = 0; i < XVECLEN (sequence, 0); i++) | |
2501 | { | |
2502 | q = XVECEXP (sequence, 0, i); | |
2503 | gcc_assert (INSN_P (q)); | |
2504 | reset_used_flags (PATTERN (q)); | |
2505 | reset_used_flags (REG_NOTES (q)); | |
2954a813 KK |
2506 | } |
2507 | } | |
2c07f13b JH |
2508 | } |
2509 | ||
2510 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2511 | if (INSN_P (p)) | |
2512 | { | |
2513 | verify_rtx_sharing (PATTERN (p), p); | |
2514 | verify_rtx_sharing (REG_NOTES (p), p); | |
2c07f13b JH |
2515 | } |
2516 | } | |
2517 | ||
d1b81779 GK |
2518 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2519 | Assumes the mark bits are cleared at entry. */ | |
2520 | ||
2c07f13b JH |
2521 | void |
2522 | unshare_all_rtl_in_chain (rtx insn) | |
d1b81779 GK |
2523 | { |
2524 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2525 | if (INSN_P (insn)) |
d1b81779 GK |
2526 | { |
2527 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2528 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
d1b81779 GK |
2529 | } |
2530 | } | |
2531 | ||
2d4aecb3 | 2532 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2533 | shared. We never replace the DECL_RTLs themselves with a copy, |
2534 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2535 | expressions in the instruction stream. | |
2536 | ||
2537 | Note that reload may convert pseudo registers into memories in-place. | |
2538 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2539 | reset the used flags on MEMs in the instruction stream, we must set | |
2540 | them again on MEMs that appear in DECL_RTLs. */ | |
2541 | ||
2d4aecb3 | 2542 | static void |
5eb2a9f2 | 2543 | set_used_decls (tree blk) |
2d4aecb3 AO |
2544 | { |
2545 | tree t; | |
2546 | ||
2547 | /* Mark decls. */ | |
2548 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c | 2549 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2550 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2551 | |
2552 | /* Now process sub-blocks. */ | |
87caf699 | 2553 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 2554 | set_used_decls (t); |
2d4aecb3 AO |
2555 | } |
2556 | ||
23b2ce53 | 2557 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2558 | Recursively does the same for subexpressions. Uses |
2559 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2560 | |
2561 | rtx | |
502b8322 | 2562 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2563 | { |
32b32b16 AP |
2564 | copy_rtx_if_shared_1 (&orig); |
2565 | return orig; | |
2566 | } | |
2567 | ||
ff954f39 AP |
2568 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2569 | use. Recursively does the same for subexpressions. */ | |
2570 | ||
32b32b16 AP |
2571 | static void |
2572 | copy_rtx_if_shared_1 (rtx *orig1) | |
2573 | { | |
2574 | rtx x; | |
b3694847 SS |
2575 | int i; |
2576 | enum rtx_code code; | |
32b32b16 | 2577 | rtx *last_ptr; |
b3694847 | 2578 | const char *format_ptr; |
23b2ce53 | 2579 | int copied = 0; |
32b32b16 AP |
2580 | int length; |
2581 | ||
2582 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2583 | repeat: | |
2584 | x = *orig1; | |
23b2ce53 RS |
2585 | |
2586 | if (x == 0) | |
32b32b16 | 2587 | return; |
23b2ce53 RS |
2588 | |
2589 | code = GET_CODE (x); | |
2590 | ||
2591 | /* These types may be freely shared. */ | |
2592 | ||
2593 | switch (code) | |
2594 | { | |
2595 | case REG: | |
23b2ce53 RS |
2596 | case CONST_INT: |
2597 | case CONST_DOUBLE: | |
091a3ac7 | 2598 | case CONST_FIXED: |
69ef87e2 | 2599 | case CONST_VECTOR: |
23b2ce53 | 2600 | case SYMBOL_REF: |
2c07f13b | 2601 | case LABEL_REF: |
23b2ce53 RS |
2602 | case CODE_LABEL: |
2603 | case PC: | |
2604 | case CC0: | |
2605 | case SCRATCH: | |
0f41302f | 2606 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 2607 | return; |
3e89ed8d JH |
2608 | case CLOBBER: |
2609 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2610 | return; | |
2611 | break; | |
23b2ce53 | 2612 | |
b851ea09 | 2613 | case CONST: |
6fb5fa3c | 2614 | if (shared_const_p (x)) |
32b32b16 | 2615 | return; |
b851ea09 RK |
2616 | break; |
2617 | ||
b5b8b0ac | 2618 | case DEBUG_INSN: |
23b2ce53 RS |
2619 | case INSN: |
2620 | case JUMP_INSN: | |
2621 | case CALL_INSN: | |
2622 | case NOTE: | |
23b2ce53 RS |
2623 | case BARRIER: |
2624 | /* The chain of insns is not being copied. */ | |
32b32b16 | 2625 | return; |
23b2ce53 | 2626 | |
e9a25f70 JL |
2627 | default: |
2628 | break; | |
23b2ce53 RS |
2629 | } |
2630 | ||
2631 | /* This rtx may not be shared. If it has already been seen, | |
2632 | replace it with a copy of itself. */ | |
2633 | ||
2adc7f12 | 2634 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2635 | { |
aacd3885 | 2636 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
2637 | copied = 1; |
2638 | } | |
2adc7f12 | 2639 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
2640 | |
2641 | /* Now scan the subexpressions recursively. | |
2642 | We can store any replaced subexpressions directly into X | |
2643 | since we know X is not shared! Any vectors in X | |
2644 | must be copied if X was copied. */ | |
2645 | ||
2646 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2647 | length = GET_RTX_LENGTH (code); |
2648 | last_ptr = NULL; | |
2649 | ||
2650 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2651 | { |
2652 | switch (*format_ptr++) | |
2653 | { | |
2654 | case 'e': | |
32b32b16 AP |
2655 | if (last_ptr) |
2656 | copy_rtx_if_shared_1 (last_ptr); | |
2657 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
2658 | break; |
2659 | ||
2660 | case 'E': | |
2661 | if (XVEC (x, i) != NULL) | |
2662 | { | |
b3694847 | 2663 | int j; |
f0722107 | 2664 | int len = XVECLEN (x, i); |
32b32b16 | 2665 | |
6614fd40 KH |
2666 | /* Copy the vector iff I copied the rtx and the length |
2667 | is nonzero. */ | |
f0722107 | 2668 | if (copied && len > 0) |
8f985ec4 | 2669 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
32b32b16 | 2670 | |
5d3cc252 | 2671 | /* Call recursively on all inside the vector. */ |
f0722107 | 2672 | for (j = 0; j < len; j++) |
32b32b16 AP |
2673 | { |
2674 | if (last_ptr) | |
2675 | copy_rtx_if_shared_1 (last_ptr); | |
2676 | last_ptr = &XVECEXP (x, i, j); | |
2677 | } | |
23b2ce53 RS |
2678 | } |
2679 | break; | |
2680 | } | |
2681 | } | |
32b32b16 AP |
2682 | *orig1 = x; |
2683 | if (last_ptr) | |
2684 | { | |
2685 | orig1 = last_ptr; | |
2686 | goto repeat; | |
2687 | } | |
2688 | return; | |
23b2ce53 RS |
2689 | } |
2690 | ||
2691 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2692 | to look for shared sub-parts. */ | |
2693 | ||
2694 | void | |
502b8322 | 2695 | reset_used_flags (rtx x) |
23b2ce53 | 2696 | { |
b3694847 SS |
2697 | int i, j; |
2698 | enum rtx_code code; | |
2699 | const char *format_ptr; | |
32b32b16 | 2700 | int length; |
23b2ce53 | 2701 | |
32b32b16 AP |
2702 | /* Repeat is used to turn tail-recursion into iteration. */ |
2703 | repeat: | |
23b2ce53 RS |
2704 | if (x == 0) |
2705 | return; | |
2706 | ||
2707 | code = GET_CODE (x); | |
2708 | ||
9faa82d8 | 2709 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2710 | for them. */ |
2711 | ||
2712 | switch (code) | |
2713 | { | |
2714 | case REG: | |
23b2ce53 RS |
2715 | case CONST_INT: |
2716 | case CONST_DOUBLE: | |
091a3ac7 | 2717 | case CONST_FIXED: |
69ef87e2 | 2718 | case CONST_VECTOR: |
23b2ce53 RS |
2719 | case SYMBOL_REF: |
2720 | case CODE_LABEL: | |
2721 | case PC: | |
2722 | case CC0: | |
2723 | return; | |
2724 | ||
b5b8b0ac | 2725 | case DEBUG_INSN: |
23b2ce53 RS |
2726 | case INSN: |
2727 | case JUMP_INSN: | |
2728 | case CALL_INSN: | |
2729 | case NOTE: | |
2730 | case LABEL_REF: | |
2731 | case BARRIER: | |
2732 | /* The chain of insns is not being copied. */ | |
2733 | return; | |
750c9258 | 2734 | |
e9a25f70 JL |
2735 | default: |
2736 | break; | |
23b2ce53 RS |
2737 | } |
2738 | ||
2adc7f12 | 2739 | RTX_FLAG (x, used) = 0; |
23b2ce53 RS |
2740 | |
2741 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2742 | length = GET_RTX_LENGTH (code); |
2743 | ||
2744 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2745 | { |
2746 | switch (*format_ptr++) | |
2747 | { | |
2748 | case 'e': | |
32b32b16 AP |
2749 | if (i == length-1) |
2750 | { | |
2751 | x = XEXP (x, i); | |
2752 | goto repeat; | |
2753 | } | |
23b2ce53 RS |
2754 | reset_used_flags (XEXP (x, i)); |
2755 | break; | |
2756 | ||
2757 | case 'E': | |
2758 | for (j = 0; j < XVECLEN (x, i); j++) | |
2759 | reset_used_flags (XVECEXP (x, i, j)); | |
2760 | break; | |
2761 | } | |
2762 | } | |
2763 | } | |
2c07f13b JH |
2764 | |
2765 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used | |
2766 | to look for shared sub-parts. */ | |
2767 | ||
2768 | void | |
2769 | set_used_flags (rtx x) | |
2770 | { | |
2771 | int i, j; | |
2772 | enum rtx_code code; | |
2773 | const char *format_ptr; | |
2774 | ||
2775 | if (x == 0) | |
2776 | return; | |
2777 | ||
2778 | code = GET_CODE (x); | |
2779 | ||
2780 | /* These types may be freely shared so we needn't do any resetting | |
2781 | for them. */ | |
2782 | ||
2783 | switch (code) | |
2784 | { | |
2785 | case REG: | |
2c07f13b JH |
2786 | case CONST_INT: |
2787 | case CONST_DOUBLE: | |
091a3ac7 | 2788 | case CONST_FIXED: |
2c07f13b JH |
2789 | case CONST_VECTOR: |
2790 | case SYMBOL_REF: | |
2791 | case CODE_LABEL: | |
2792 | case PC: | |
2793 | case CC0: | |
2794 | return; | |
2795 | ||
b5b8b0ac | 2796 | case DEBUG_INSN: |
2c07f13b JH |
2797 | case INSN: |
2798 | case JUMP_INSN: | |
2799 | case CALL_INSN: | |
2800 | case NOTE: | |
2801 | case LABEL_REF: | |
2802 | case BARRIER: | |
2803 | /* The chain of insns is not being copied. */ | |
2804 | return; | |
2805 | ||
2806 | default: | |
2807 | break; | |
2808 | } | |
2809 | ||
2810 | RTX_FLAG (x, used) = 1; | |
2811 | ||
2812 | format_ptr = GET_RTX_FORMAT (code); | |
2813 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2814 | { | |
2815 | switch (*format_ptr++) | |
2816 | { | |
2817 | case 'e': | |
2818 | set_used_flags (XEXP (x, i)); | |
2819 | break; | |
2820 | ||
2821 | case 'E': | |
2822 | for (j = 0; j < XVECLEN (x, i); j++) | |
2823 | set_used_flags (XVECEXP (x, i, j)); | |
2824 | break; | |
2825 | } | |
2826 | } | |
2827 | } | |
23b2ce53 RS |
2828 | \f |
2829 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2830 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2831 | OTHER must be valid as a SET_DEST. */ | |
2832 | ||
2833 | rtx | |
502b8322 | 2834 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
2835 | { |
2836 | while (1) | |
2837 | switch (GET_CODE (other)) | |
2838 | { | |
2839 | case SUBREG: | |
2840 | other = SUBREG_REG (other); | |
2841 | break; | |
2842 | case STRICT_LOW_PART: | |
2843 | case SIGN_EXTEND: | |
2844 | case ZERO_EXTEND: | |
2845 | other = XEXP (other, 0); | |
2846 | break; | |
2847 | default: | |
2848 | goto done; | |
2849 | } | |
2850 | done: | |
3c0cb5de | 2851 | if ((MEM_P (other) |
23b2ce53 | 2852 | && ! CONSTANT_P (x) |
f8cfc6aa | 2853 | && !REG_P (x) |
23b2ce53 | 2854 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 2855 | || (REG_P (other) |
23b2ce53 RS |
2856 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
2857 | || reg_mentioned_p (other, x)))) | |
2858 | { | |
2859 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2860 | emit_move_insn (temp, x); | |
2861 | return temp; | |
2862 | } | |
2863 | return x; | |
2864 | } | |
2865 | \f | |
2866 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2867 | ||
2868 | /* Return the first insn of the current sequence or current function. */ | |
2869 | ||
2870 | rtx | |
502b8322 | 2871 | get_insns (void) |
23b2ce53 RS |
2872 | { |
2873 | return first_insn; | |
2874 | } | |
2875 | ||
3dec4024 JH |
2876 | /* Specify a new insn as the first in the chain. */ |
2877 | ||
2878 | void | |
502b8322 | 2879 | set_first_insn (rtx insn) |
3dec4024 | 2880 | { |
5b0264cb | 2881 | gcc_assert (!PREV_INSN (insn)); |
3dec4024 JH |
2882 | first_insn = insn; |
2883 | } | |
2884 | ||
23b2ce53 RS |
2885 | /* Return the last insn emitted in current sequence or current function. */ |
2886 | ||
2887 | rtx | |
502b8322 | 2888 | get_last_insn (void) |
23b2ce53 RS |
2889 | { |
2890 | return last_insn; | |
2891 | } | |
2892 | ||
2893 | /* Specify a new insn as the last in the chain. */ | |
2894 | ||
2895 | void | |
502b8322 | 2896 | set_last_insn (rtx insn) |
23b2ce53 | 2897 | { |
5b0264cb | 2898 | gcc_assert (!NEXT_INSN (insn)); |
23b2ce53 RS |
2899 | last_insn = insn; |
2900 | } | |
2901 | ||
2902 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2903 | ||
2904 | rtx | |
502b8322 | 2905 | get_last_insn_anywhere (void) |
23b2ce53 RS |
2906 | { |
2907 | struct sequence_stack *stack; | |
2908 | if (last_insn) | |
2909 | return last_insn; | |
49ad7cfa | 2910 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2911 | if (stack->last != 0) |
2912 | return stack->last; | |
2913 | return 0; | |
2914 | } | |
2915 | ||
2a496e8b JDA |
2916 | /* Return the first nonnote insn emitted in current sequence or current |
2917 | function. This routine looks inside SEQUENCEs. */ | |
2918 | ||
2919 | rtx | |
502b8322 | 2920 | get_first_nonnote_insn (void) |
2a496e8b | 2921 | { |
91373fe8 JDA |
2922 | rtx insn = first_insn; |
2923 | ||
2924 | if (insn) | |
2925 | { | |
2926 | if (NOTE_P (insn)) | |
2927 | for (insn = next_insn (insn); | |
2928 | insn && NOTE_P (insn); | |
2929 | insn = next_insn (insn)) | |
2930 | continue; | |
2931 | else | |
2932 | { | |
2ca202e7 | 2933 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2934 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2935 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2936 | } | |
2937 | } | |
2a496e8b JDA |
2938 | |
2939 | return insn; | |
2940 | } | |
2941 | ||
2942 | /* Return the last nonnote insn emitted in current sequence or current | |
2943 | function. This routine looks inside SEQUENCEs. */ | |
2944 | ||
2945 | rtx | |
502b8322 | 2946 | get_last_nonnote_insn (void) |
2a496e8b | 2947 | { |
91373fe8 JDA |
2948 | rtx insn = last_insn; |
2949 | ||
2950 | if (insn) | |
2951 | { | |
2952 | if (NOTE_P (insn)) | |
2953 | for (insn = previous_insn (insn); | |
2954 | insn && NOTE_P (insn); | |
2955 | insn = previous_insn (insn)) | |
2956 | continue; | |
2957 | else | |
2958 | { | |
2ca202e7 | 2959 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2960 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2961 | insn = XVECEXP (PATTERN (insn), 0, | |
2962 | XVECLEN (PATTERN (insn), 0) - 1); | |
2963 | } | |
2964 | } | |
2a496e8b JDA |
2965 | |
2966 | return insn; | |
2967 | } | |
2968 | ||
23b2ce53 RS |
2969 | /* Return a number larger than any instruction's uid in this function. */ |
2970 | ||
2971 | int | |
502b8322 | 2972 | get_max_uid (void) |
23b2ce53 RS |
2973 | { |
2974 | return cur_insn_uid; | |
2975 | } | |
b5b8b0ac AO |
2976 | |
2977 | /* Return the number of actual (non-debug) insns emitted in this | |
2978 | function. */ | |
2979 | ||
2980 | int | |
2981 | get_max_insn_count (void) | |
2982 | { | |
2983 | int n = cur_insn_uid; | |
2984 | ||
2985 | /* The table size must be stable across -g, to avoid codegen | |
2986 | differences due to debug insns, and not be affected by | |
2987 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
2988 | debugging of -fcompare-debug failures. */ | |
2989 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
2990 | n -= cur_debug_insn_uid; | |
2991 | else | |
2992 | n -= MIN_NONDEBUG_INSN_UID; | |
2993 | ||
2994 | return n; | |
2995 | } | |
2996 | ||
23b2ce53 RS |
2997 | \f |
2998 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2999 | of the sequence. */ | |
3000 | ||
3001 | rtx | |
502b8322 | 3002 | next_insn (rtx insn) |
23b2ce53 | 3003 | { |
75547801 KG |
3004 | if (insn) |
3005 | { | |
3006 | insn = NEXT_INSN (insn); | |
3007 | if (insn && NONJUMP_INSN_P (insn) | |
3008 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3009 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3010 | } | |
23b2ce53 | 3011 | |
75547801 | 3012 | return insn; |
23b2ce53 RS |
3013 | } |
3014 | ||
3015 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3016 | of the sequence. */ | |
3017 | ||
3018 | rtx | |
502b8322 | 3019 | previous_insn (rtx insn) |
23b2ce53 | 3020 | { |
75547801 KG |
3021 | if (insn) |
3022 | { | |
3023 | insn = PREV_INSN (insn); | |
3024 | if (insn && NONJUMP_INSN_P (insn) | |
3025 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3026 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
3027 | } | |
23b2ce53 | 3028 | |
75547801 | 3029 | return insn; |
23b2ce53 RS |
3030 | } |
3031 | ||
3032 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3033 | look inside SEQUENCEs. */ | |
3034 | ||
3035 | rtx | |
502b8322 | 3036 | next_nonnote_insn (rtx insn) |
23b2ce53 | 3037 | { |
75547801 KG |
3038 | while (insn) |
3039 | { | |
3040 | insn = NEXT_INSN (insn); | |
3041 | if (insn == 0 || !NOTE_P (insn)) | |
3042 | break; | |
3043 | } | |
23b2ce53 | 3044 | |
75547801 | 3045 | return insn; |
23b2ce53 RS |
3046 | } |
3047 | ||
1e211590 DD |
3048 | /* Return the next insn after INSN that is not a NOTE, but stop the |
3049 | search before we enter another basic block. This routine does not | |
3050 | look inside SEQUENCEs. */ | |
3051 | ||
3052 | rtx | |
3053 | next_nonnote_insn_bb (rtx insn) | |
3054 | { | |
3055 | while (insn) | |
3056 | { | |
3057 | insn = NEXT_INSN (insn); | |
3058 | if (insn == 0 || !NOTE_P (insn)) | |
3059 | break; | |
3060 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3061 | return NULL_RTX; | |
3062 | } | |
3063 | ||
3064 | return insn; | |
3065 | } | |
3066 | ||
23b2ce53 RS |
3067 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3068 | not look inside SEQUENCEs. */ | |
3069 | ||
3070 | rtx | |
502b8322 | 3071 | prev_nonnote_insn (rtx insn) |
23b2ce53 | 3072 | { |
75547801 KG |
3073 | while (insn) |
3074 | { | |
3075 | insn = PREV_INSN (insn); | |
3076 | if (insn == 0 || !NOTE_P (insn)) | |
3077 | break; | |
3078 | } | |
23b2ce53 | 3079 | |
75547801 | 3080 | return insn; |
23b2ce53 RS |
3081 | } |
3082 | ||
896aa4ea DD |
3083 | /* Return the previous insn before INSN that is not a NOTE, but stop |
3084 | the search before we enter another basic block. This routine does | |
3085 | not look inside SEQUENCEs. */ | |
3086 | ||
3087 | rtx | |
3088 | prev_nonnote_insn_bb (rtx insn) | |
3089 | { | |
3090 | while (insn) | |
3091 | { | |
3092 | insn = PREV_INSN (insn); | |
3093 | if (insn == 0 || !NOTE_P (insn)) | |
3094 | break; | |
3095 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3096 | return NULL_RTX; | |
3097 | } | |
3098 | ||
3099 | return insn; | |
3100 | } | |
3101 | ||
b5b8b0ac AO |
3102 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3103 | routine does not look inside SEQUENCEs. */ | |
3104 | ||
3105 | rtx | |
3106 | next_nondebug_insn (rtx insn) | |
3107 | { | |
3108 | while (insn) | |
3109 | { | |
3110 | insn = NEXT_INSN (insn); | |
3111 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3112 | break; | |
3113 | } | |
3114 | ||
3115 | return insn; | |
3116 | } | |
3117 | ||
3118 | /* Return the previous insn before INSN that is not a DEBUG_INSN. | |
3119 | This routine does not look inside SEQUENCEs. */ | |
3120 | ||
3121 | rtx | |
3122 | prev_nondebug_insn (rtx insn) | |
3123 | { | |
3124 | while (insn) | |
3125 | { | |
3126 | insn = PREV_INSN (insn); | |
3127 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3128 | break; | |
3129 | } | |
3130 | ||
3131 | return insn; | |
3132 | } | |
3133 | ||
23b2ce53 RS |
3134 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3135 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3136 | SEQUENCEs. */ |
23b2ce53 RS |
3137 | |
3138 | rtx | |
502b8322 | 3139 | next_real_insn (rtx insn) |
23b2ce53 | 3140 | { |
75547801 KG |
3141 | while (insn) |
3142 | { | |
3143 | insn = NEXT_INSN (insn); | |
3144 | if (insn == 0 || INSN_P (insn)) | |
3145 | break; | |
3146 | } | |
23b2ce53 | 3147 | |
75547801 | 3148 | return insn; |
23b2ce53 RS |
3149 | } |
3150 | ||
3151 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3152 | or 0, if there is none. This routine does not look inside | |
3153 | SEQUENCEs. */ | |
3154 | ||
3155 | rtx | |
502b8322 | 3156 | prev_real_insn (rtx insn) |
23b2ce53 | 3157 | { |
75547801 KG |
3158 | while (insn) |
3159 | { | |
3160 | insn = PREV_INSN (insn); | |
3161 | if (insn == 0 || INSN_P (insn)) | |
3162 | break; | |
3163 | } | |
23b2ce53 | 3164 | |
75547801 | 3165 | return insn; |
23b2ce53 RS |
3166 | } |
3167 | ||
ee960939 OH |
3168 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3169 | This routine does not look inside SEQUENCEs. */ | |
3170 | ||
3171 | rtx | |
502b8322 | 3172 | last_call_insn (void) |
ee960939 OH |
3173 | { |
3174 | rtx insn; | |
3175 | ||
3176 | for (insn = get_last_insn (); | |
4b4bf941 | 3177 | insn && !CALL_P (insn); |
ee960939 OH |
3178 | insn = PREV_INSN (insn)) |
3179 | ; | |
3180 | ||
3181 | return insn; | |
3182 | } | |
3183 | ||
23b2ce53 RS |
3184 | /* Find the next insn after INSN that really does something. This routine |
3185 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3186 | same as next_real_insn. */ | |
3187 | ||
69732dcb | 3188 | int |
4f588890 | 3189 | active_insn_p (const_rtx insn) |
69732dcb | 3190 | { |
4b4bf941 JQ |
3191 | return (CALL_P (insn) || JUMP_P (insn) |
3192 | || (NONJUMP_INSN_P (insn) | |
23b8ba81 RH |
3193 | && (! reload_completed |
3194 | || (GET_CODE (PATTERN (insn)) != USE | |
3195 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3196 | } |
3197 | ||
23b2ce53 | 3198 | rtx |
502b8322 | 3199 | next_active_insn (rtx insn) |
23b2ce53 | 3200 | { |
75547801 KG |
3201 | while (insn) |
3202 | { | |
3203 | insn = NEXT_INSN (insn); | |
3204 | if (insn == 0 || active_insn_p (insn)) | |
3205 | break; | |
3206 | } | |
23b2ce53 | 3207 | |
75547801 | 3208 | return insn; |
23b2ce53 RS |
3209 | } |
3210 | ||
3211 | /* Find the last insn before INSN that really does something. This routine | |
3212 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3213 | same as prev_real_insn. */ | |
3214 | ||
3215 | rtx | |
502b8322 | 3216 | prev_active_insn (rtx insn) |
23b2ce53 | 3217 | { |
75547801 KG |
3218 | while (insn) |
3219 | { | |
3220 | insn = PREV_INSN (insn); | |
3221 | if (insn == 0 || active_insn_p (insn)) | |
3222 | break; | |
3223 | } | |
23b2ce53 | 3224 | |
75547801 | 3225 | return insn; |
23b2ce53 RS |
3226 | } |
3227 | ||
3228 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
3229 | ||
3230 | rtx | |
502b8322 | 3231 | next_label (rtx insn) |
23b2ce53 | 3232 | { |
75547801 KG |
3233 | while (insn) |
3234 | { | |
3235 | insn = NEXT_INSN (insn); | |
3236 | if (insn == 0 || LABEL_P (insn)) | |
3237 | break; | |
3238 | } | |
23b2ce53 | 3239 | |
75547801 | 3240 | return insn; |
23b2ce53 RS |
3241 | } |
3242 | ||
3243 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
3244 | ||
3245 | rtx | |
502b8322 | 3246 | prev_label (rtx insn) |
23b2ce53 | 3247 | { |
75547801 KG |
3248 | while (insn) |
3249 | { | |
3250 | insn = PREV_INSN (insn); | |
3251 | if (insn == 0 || LABEL_P (insn)) | |
3252 | break; | |
3253 | } | |
23b2ce53 | 3254 | |
75547801 | 3255 | return insn; |
23b2ce53 | 3256 | } |
6c2511d3 RS |
3257 | |
3258 | /* Return the last label to mark the same position as LABEL. Return null | |
3259 | if LABEL itself is null. */ | |
3260 | ||
3261 | rtx | |
3262 | skip_consecutive_labels (rtx label) | |
3263 | { | |
3264 | rtx insn; | |
3265 | ||
3266 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | |
3267 | if (LABEL_P (insn)) | |
3268 | label = insn; | |
3269 | ||
3270 | return label; | |
3271 | } | |
23b2ce53 RS |
3272 | \f |
3273 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
3274 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3275 | and REG_CC_USER notes so we can find it. */ | |
3276 | ||
3277 | void | |
502b8322 | 3278 | link_cc0_insns (rtx insn) |
c572e5ba JVA |
3279 | { |
3280 | rtx user = next_nonnote_insn (insn); | |
3281 | ||
4b4bf941 | 3282 | if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE) |
c572e5ba JVA |
3283 | user = XVECEXP (PATTERN (user), 0, 0); |
3284 | ||
65c5f2a6 ILT |
3285 | add_reg_note (user, REG_CC_SETTER, insn); |
3286 | add_reg_note (insn, REG_CC_USER, user); | |
c572e5ba JVA |
3287 | } |
3288 | ||
23b2ce53 RS |
3289 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3290 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3291 | applied to the result of this function should yield INSN). | |
3292 | ||
3293 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3294 | is present, it contains the insn that uses CC0. | |
3295 | ||
3296 | Return 0 if we can't find the insn. */ | |
3297 | ||
3298 | rtx | |
502b8322 | 3299 | next_cc0_user (rtx insn) |
23b2ce53 | 3300 | { |
906c4e36 | 3301 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3302 | |
3303 | if (note) | |
3304 | return XEXP (note, 0); | |
3305 | ||
3306 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3307 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
23b2ce53 RS |
3308 | insn = XVECEXP (PATTERN (insn), 0, 0); |
3309 | ||
2c3c49de | 3310 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
3311 | return insn; |
3312 | ||
3313 | return 0; | |
3314 | } | |
3315 | ||
3316 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3317 | note, it is the previous insn. */ | |
3318 | ||
3319 | rtx | |
502b8322 | 3320 | prev_cc0_setter (rtx insn) |
23b2ce53 | 3321 | { |
906c4e36 | 3322 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3323 | |
3324 | if (note) | |
3325 | return XEXP (note, 0); | |
3326 | ||
3327 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3328 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 RS |
3329 | |
3330 | return insn; | |
3331 | } | |
3332 | #endif | |
e5bef2e4 | 3333 | |
594f8779 RZ |
3334 | #ifdef AUTO_INC_DEC |
3335 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3336 | ||
3337 | static int | |
3338 | find_auto_inc (rtx *xp, void *data) | |
3339 | { | |
3340 | rtx x = *xp; | |
5ead67f6 | 3341 | rtx reg = (rtx) data; |
594f8779 RZ |
3342 | |
3343 | if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC) | |
3344 | return 0; | |
3345 | ||
3346 | switch (GET_CODE (x)) | |
3347 | { | |
3348 | case PRE_DEC: | |
3349 | case PRE_INC: | |
3350 | case POST_DEC: | |
3351 | case POST_INC: | |
3352 | case PRE_MODIFY: | |
3353 | case POST_MODIFY: | |
3354 | if (rtx_equal_p (reg, XEXP (x, 0))) | |
3355 | return 1; | |
3356 | break; | |
3357 | ||
3358 | default: | |
3359 | gcc_unreachable (); | |
3360 | } | |
3361 | return -1; | |
3362 | } | |
3363 | #endif | |
3364 | ||
e5bef2e4 HB |
3365 | /* Increment the label uses for all labels present in rtx. */ |
3366 | ||
3367 | static void | |
502b8322 | 3368 | mark_label_nuses (rtx x) |
e5bef2e4 | 3369 | { |
b3694847 SS |
3370 | enum rtx_code code; |
3371 | int i, j; | |
3372 | const char *fmt; | |
e5bef2e4 HB |
3373 | |
3374 | code = GET_CODE (x); | |
7537fc90 | 3375 | if (code == LABEL_REF && LABEL_P (XEXP (x, 0))) |
e5bef2e4 HB |
3376 | LABEL_NUSES (XEXP (x, 0))++; |
3377 | ||
3378 | fmt = GET_RTX_FORMAT (code); | |
3379 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3380 | { | |
3381 | if (fmt[i] == 'e') | |
0fb7aeda | 3382 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3383 | else if (fmt[i] == 'E') |
0fb7aeda | 3384 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3385 | mark_label_nuses (XVECEXP (x, i, j)); |
3386 | } | |
3387 | } | |
3388 | ||
23b2ce53 RS |
3389 | \f |
3390 | /* Try splitting insns that can be split for better scheduling. | |
3391 | PAT is the pattern which might split. | |
3392 | TRIAL is the insn providing PAT. | |
cc2902df | 3393 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3394 | |
3395 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3396 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3397 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3398 | ||
3399 | rtx | |
502b8322 | 3400 | try_split (rtx pat, rtx trial, int last) |
23b2ce53 RS |
3401 | { |
3402 | rtx before = PREV_INSN (trial); | |
3403 | rtx after = NEXT_INSN (trial); | |
23b2ce53 | 3404 | int has_barrier = 0; |
4a8cae83 | 3405 | rtx note, seq, tem; |
6b24c259 | 3406 | int probability; |
599aedd9 RH |
3407 | rtx insn_last, insn; |
3408 | int njumps = 0; | |
6b24c259 | 3409 | |
cd9c1ca8 RH |
3410 | /* We're not good at redistributing frame information. */ |
3411 | if (RTX_FRAME_RELATED_P (trial)) | |
3412 | return trial; | |
3413 | ||
6b24c259 JH |
3414 | if (any_condjump_p (trial) |
3415 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3416 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3417 | probability = split_branch_probability; | |
3418 | ||
3419 | seq = split_insns (pat, trial); | |
3420 | ||
3421 | split_branch_probability = -1; | |
23b2ce53 RS |
3422 | |
3423 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3424 | We may need to handle this specially. */ | |
4b4bf941 | 3425 | if (after && BARRIER_P (after)) |
23b2ce53 RS |
3426 | { |
3427 | has_barrier = 1; | |
3428 | after = NEXT_INSN (after); | |
3429 | } | |
3430 | ||
599aedd9 RH |
3431 | if (!seq) |
3432 | return trial; | |
3433 | ||
3434 | /* Avoid infinite loop if any insn of the result matches | |
3435 | the original pattern. */ | |
3436 | insn_last = seq; | |
3437 | while (1) | |
23b2ce53 | 3438 | { |
599aedd9 RH |
3439 | if (INSN_P (insn_last) |
3440 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3441 | return trial; | |
3442 | if (!NEXT_INSN (insn_last)) | |
3443 | break; | |
3444 | insn_last = NEXT_INSN (insn_last); | |
3445 | } | |
750c9258 | 3446 | |
6fb5fa3c DB |
3447 | /* We will be adding the new sequence to the function. The splitters |
3448 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3449 | unshare_all_rtl_in_chain (seq); | |
3450 | ||
599aedd9 RH |
3451 | /* Mark labels. */ |
3452 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3453 | { | |
4b4bf941 | 3454 | if (JUMP_P (insn)) |
599aedd9 RH |
3455 | { |
3456 | mark_jump_label (PATTERN (insn), insn, 0); | |
3457 | njumps++; | |
3458 | if (probability != -1 | |
3459 | && any_condjump_p (insn) | |
3460 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3461 | { |
599aedd9 RH |
3462 | /* We can preserve the REG_BR_PROB notes only if exactly |
3463 | one jump is created, otherwise the machine description | |
3464 | is responsible for this step using | |
3465 | split_branch_probability variable. */ | |
5b0264cb | 3466 | gcc_assert (njumps == 1); |
65c5f2a6 | 3467 | add_reg_note (insn, REG_BR_PROB, GEN_INT (probability)); |
2f937369 | 3468 | } |
599aedd9 RH |
3469 | } |
3470 | } | |
3471 | ||
3472 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3473 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
4b4bf941 | 3474 | if (CALL_P (trial)) |
599aedd9 RH |
3475 | { |
3476 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3477 | if (CALL_P (insn)) |
599aedd9 | 3478 | { |
f6a1f3f6 RH |
3479 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3480 | while (*p) | |
3481 | p = &XEXP (*p, 1); | |
3482 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
599aedd9 RH |
3483 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3484 | } | |
3485 | } | |
4b5e8abe | 3486 | |
599aedd9 RH |
3487 | /* Copy notes, particularly those related to the CFG. */ |
3488 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3489 | { | |
3490 | switch (REG_NOTE_KIND (note)) | |
3491 | { | |
3492 | case REG_EH_REGION: | |
1d65f45c | 3493 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3494 | break; |
216183ce | 3495 | |
599aedd9 RH |
3496 | case REG_NORETURN: |
3497 | case REG_SETJMP: | |
594f8779 | 3498 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3499 | { |
4b4bf941 | 3500 | if (CALL_P (insn)) |
65c5f2a6 | 3501 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3502 | } |
599aedd9 | 3503 | break; |
d6e95df8 | 3504 | |
599aedd9 | 3505 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3506 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3507 | { |
4b4bf941 | 3508 | if (JUMP_P (insn)) |
65c5f2a6 | 3509 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3510 | } |
599aedd9 | 3511 | break; |
e5bef2e4 | 3512 | |
594f8779 RZ |
3513 | #ifdef AUTO_INC_DEC |
3514 | case REG_INC: | |
3515 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3516 | { | |
3517 | rtx reg = XEXP (note, 0); | |
3518 | if (!FIND_REG_INC_NOTE (insn, reg) | |
3519 | && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0) | |
65c5f2a6 | 3520 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3521 | } |
3522 | break; | |
3523 | #endif | |
3524 | ||
599aedd9 RH |
3525 | default: |
3526 | break; | |
23b2ce53 | 3527 | } |
599aedd9 RH |
3528 | } |
3529 | ||
3530 | /* If there are LABELS inside the split insns increment the | |
3531 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3532 | if (INSN_P (trial)) |
599aedd9 RH |
3533 | { |
3534 | insn = insn_last; | |
3535 | while (insn != NULL_RTX) | |
23b2ce53 | 3536 | { |
cf7c4aa6 | 3537 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3538 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3539 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3540 | |
599aedd9 RH |
3541 | insn = PREV_INSN (insn); |
3542 | } | |
23b2ce53 RS |
3543 | } |
3544 | ||
0435312e | 3545 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
599aedd9 RH |
3546 | |
3547 | delete_insn (trial); | |
3548 | if (has_barrier) | |
3549 | emit_barrier_after (tem); | |
3550 | ||
3551 | /* Recursively call try_split for each new insn created; by the | |
3552 | time control returns here that insn will be fully split, so | |
3553 | set LAST and continue from the insn after the one returned. | |
3554 | We can't use next_active_insn here since AFTER may be a note. | |
3555 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3556 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3557 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3558 | tem = try_split (PATTERN (tem), tem, 1); | |
3559 | ||
3560 | /* Return either the first or the last insn, depending on which was | |
3561 | requested. */ | |
3562 | return last | |
3563 | ? (after ? PREV_INSN (after) : last_insn) | |
3564 | : NEXT_INSN (before); | |
23b2ce53 RS |
3565 | } |
3566 | \f | |
3567 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3568 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
3569 | |
3570 | rtx | |
502b8322 | 3571 | make_insn_raw (rtx pattern) |
23b2ce53 | 3572 | { |
b3694847 | 3573 | rtx insn; |
23b2ce53 | 3574 | |
1f8f4a0b | 3575 | insn = rtx_alloc (INSN); |
23b2ce53 | 3576 | |
43127294 | 3577 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3578 | PATTERN (insn) = pattern; |
3579 | INSN_CODE (insn) = -1; | |
1632afca | 3580 | REG_NOTES (insn) = NULL; |
55e092c4 | 3581 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3582 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3583 | |
47984720 NC |
3584 | #ifdef ENABLE_RTL_CHECKING |
3585 | if (insn | |
2c3c49de | 3586 | && INSN_P (insn) |
47984720 NC |
3587 | && (returnjump_p (insn) |
3588 | || (GET_CODE (insn) == SET | |
3589 | && SET_DEST (insn) == pc_rtx))) | |
3590 | { | |
d4ee4d25 | 3591 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3592 | debug_rtx (insn); |
3593 | } | |
3594 | #endif | |
750c9258 | 3595 | |
23b2ce53 RS |
3596 | return insn; |
3597 | } | |
3598 | ||
b5b8b0ac AO |
3599 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
3600 | ||
3601 | rtx | |
3602 | make_debug_insn_raw (rtx pattern) | |
3603 | { | |
3604 | rtx insn; | |
3605 | ||
3606 | insn = rtx_alloc (DEBUG_INSN); | |
3607 | INSN_UID (insn) = cur_debug_insn_uid++; | |
3608 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3609 | INSN_UID (insn) = cur_insn_uid++; | |
3610 | ||
3611 | PATTERN (insn) = pattern; | |
3612 | INSN_CODE (insn) = -1; | |
3613 | REG_NOTES (insn) = NULL; | |
3614 | INSN_LOCATOR (insn) = curr_insn_locator (); | |
3615 | BLOCK_FOR_INSN (insn) = NULL; | |
3616 | ||
3617 | return insn; | |
3618 | } | |
3619 | ||
2f937369 | 3620 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3621 | |
38109dab | 3622 | rtx |
502b8322 | 3623 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3624 | { |
b3694847 | 3625 | rtx insn; |
23b2ce53 | 3626 | |
4b1f5e8c | 3627 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 3628 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3629 | |
3630 | PATTERN (insn) = pattern; | |
3631 | INSN_CODE (insn) = -1; | |
1632afca RS |
3632 | REG_NOTES (insn) = NULL; |
3633 | JUMP_LABEL (insn) = NULL; | |
55e092c4 | 3634 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3635 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3636 | |
3637 | return insn; | |
3638 | } | |
aff507f4 | 3639 | |
2f937369 | 3640 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 RK |
3641 | |
3642 | static rtx | |
502b8322 | 3643 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3644 | { |
b3694847 | 3645 | rtx insn; |
aff507f4 RK |
3646 | |
3647 | insn = rtx_alloc (CALL_INSN); | |
3648 | INSN_UID (insn) = cur_insn_uid++; | |
3649 | ||
3650 | PATTERN (insn) = pattern; | |
3651 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3652 | REG_NOTES (insn) = NULL; |
3653 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
55e092c4 | 3654 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3655 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3656 | |
3657 | return insn; | |
3658 | } | |
23b2ce53 RS |
3659 | \f |
3660 | /* Add INSN to the end of the doubly-linked list. | |
3661 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3662 | ||
3663 | void | |
502b8322 | 3664 | add_insn (rtx insn) |
23b2ce53 RS |
3665 | { |
3666 | PREV_INSN (insn) = last_insn; | |
3667 | NEXT_INSN (insn) = 0; | |
3668 | ||
3669 | if (NULL != last_insn) | |
3670 | NEXT_INSN (last_insn) = insn; | |
3671 | ||
3672 | if (NULL == first_insn) | |
3673 | first_insn = insn; | |
3674 | ||
3675 | last_insn = insn; | |
3676 | } | |
3677 | ||
a0ae8e8d RK |
3678 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3679 | the next should be the only functions called to insert an insn once | |
ba213285 | 3680 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 3681 | SEQUENCE. */ |
23b2ce53 RS |
3682 | |
3683 | void | |
6fb5fa3c | 3684 | add_insn_after (rtx insn, rtx after, basic_block bb) |
23b2ce53 RS |
3685 | { |
3686 | rtx next = NEXT_INSN (after); | |
3687 | ||
5b0264cb | 3688 | gcc_assert (!optimize || !INSN_DELETED_P (after)); |
ba213285 | 3689 | |
23b2ce53 RS |
3690 | NEXT_INSN (insn) = next; |
3691 | PREV_INSN (insn) = after; | |
3692 | ||
3693 | if (next) | |
3694 | { | |
3695 | PREV_INSN (next) = insn; | |
4b4bf941 | 3696 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
23b2ce53 RS |
3697 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; |
3698 | } | |
3699 | else if (last_insn == after) | |
3700 | last_insn = insn; | |
3701 | else | |
3702 | { | |
49ad7cfa | 3703 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
3704 | /* Scan all pending sequences too. */ |
3705 | for (; stack; stack = stack->next) | |
3706 | if (after == stack->last) | |
fef0509b RK |
3707 | { |
3708 | stack->last = insn; | |
3709 | break; | |
3710 | } | |
a0ae8e8d | 3711 | |
5b0264cb | 3712 | gcc_assert (stack); |
23b2ce53 RS |
3713 | } |
3714 | ||
4b4bf941 JQ |
3715 | if (!BARRIER_P (after) |
3716 | && !BARRIER_P (insn) | |
3c030e88 JH |
3717 | && (bb = BLOCK_FOR_INSN (after))) |
3718 | { | |
3719 | set_block_for_insn (insn, bb); | |
38c1593d | 3720 | if (INSN_P (insn)) |
6fb5fa3c | 3721 | df_insn_rescan (insn); |
3c030e88 | 3722 | /* Should not happen as first in the BB is always |
a1f300c0 | 3723 | either NOTE or LABEL. */ |
a813c111 | 3724 | if (BB_END (bb) == after |
3c030e88 | 3725 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 3726 | && !BARRIER_P (insn) |
a38e7aa5 | 3727 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
a813c111 | 3728 | BB_END (bb) = insn; |
3c030e88 JH |
3729 | } |
3730 | ||
23b2ce53 | 3731 | NEXT_INSN (after) = insn; |
4b4bf941 | 3732 | if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE) |
23b2ce53 RS |
3733 | { |
3734 | rtx sequence = PATTERN (after); | |
3735 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3736 | } | |
3737 | } | |
3738 | ||
a0ae8e8d | 3739 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
6fb5fa3c DB |
3740 | the previous should be the only functions called to insert an insn |
3741 | once delay slots have been filled since only they know how to | |
3742 | update a SEQUENCE. If BB is NULL, an attempt is made to infer the | |
3743 | bb from before. */ | |
a0ae8e8d RK |
3744 | |
3745 | void | |
6fb5fa3c | 3746 | add_insn_before (rtx insn, rtx before, basic_block bb) |
a0ae8e8d RK |
3747 | { |
3748 | rtx prev = PREV_INSN (before); | |
3749 | ||
5b0264cb | 3750 | gcc_assert (!optimize || !INSN_DELETED_P (before)); |
ba213285 | 3751 | |
a0ae8e8d RK |
3752 | PREV_INSN (insn) = prev; |
3753 | NEXT_INSN (insn) = before; | |
3754 | ||
3755 | if (prev) | |
3756 | { | |
3757 | NEXT_INSN (prev) = insn; | |
4b4bf941 | 3758 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
a0ae8e8d RK |
3759 | { |
3760 | rtx sequence = PATTERN (prev); | |
3761 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3762 | } | |
3763 | } | |
3764 | else if (first_insn == before) | |
3765 | first_insn = insn; | |
3766 | else | |
3767 | { | |
49ad7cfa | 3768 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
3769 | /* Scan all pending sequences too. */ |
3770 | for (; stack; stack = stack->next) | |
3771 | if (before == stack->first) | |
fef0509b RK |
3772 | { |
3773 | stack->first = insn; | |
3774 | break; | |
3775 | } | |
a0ae8e8d | 3776 | |
5b0264cb | 3777 | gcc_assert (stack); |
a0ae8e8d RK |
3778 | } |
3779 | ||
6fb5fa3c DB |
3780 | if (!bb |
3781 | && !BARRIER_P (before) | |
3782 | && !BARRIER_P (insn)) | |
3783 | bb = BLOCK_FOR_INSN (before); | |
3784 | ||
3785 | if (bb) | |
3c030e88 JH |
3786 | { |
3787 | set_block_for_insn (insn, bb); | |
38c1593d | 3788 | if (INSN_P (insn)) |
6fb5fa3c | 3789 | df_insn_rescan (insn); |
5b0264cb | 3790 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 3791 | LABEL. */ |
5b0264cb NS |
3792 | gcc_assert (BB_HEAD (bb) != insn |
3793 | /* Avoid clobbering of structure when creating new BB. */ | |
3794 | || BARRIER_P (insn) | |
a38e7aa5 | 3795 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 JH |
3796 | } |
3797 | ||
a0ae8e8d | 3798 | PREV_INSN (before) = insn; |
4b4bf941 | 3799 | if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE) |
a0ae8e8d RK |
3800 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; |
3801 | } | |
3802 | ||
6fb5fa3c DB |
3803 | |
3804 | /* Replace insn with an deleted instruction note. */ | |
3805 | ||
0ce2b299 EB |
3806 | void |
3807 | set_insn_deleted (rtx insn) | |
6fb5fa3c DB |
3808 | { |
3809 | df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn)); | |
3810 | PUT_CODE (insn, NOTE); | |
3811 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
3812 | } | |
3813 | ||
3814 | ||
89e99eea DB |
3815 | /* Remove an insn from its doubly-linked list. This function knows how |
3816 | to handle sequences. */ | |
3817 | void | |
502b8322 | 3818 | remove_insn (rtx insn) |
89e99eea DB |
3819 | { |
3820 | rtx next = NEXT_INSN (insn); | |
3821 | rtx prev = PREV_INSN (insn); | |
53c17031 JH |
3822 | basic_block bb; |
3823 | ||
6fb5fa3c DB |
3824 | /* Later in the code, the block will be marked dirty. */ |
3825 | df_insn_delete (NULL, INSN_UID (insn)); | |
3826 | ||
89e99eea DB |
3827 | if (prev) |
3828 | { | |
3829 | NEXT_INSN (prev) = next; | |
4b4bf941 | 3830 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea DB |
3831 | { |
3832 | rtx sequence = PATTERN (prev); | |
3833 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3834 | } | |
3835 | } | |
3836 | else if (first_insn == insn) | |
3837 | first_insn = next; | |
3838 | else | |
3839 | { | |
49ad7cfa | 3840 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3841 | /* Scan all pending sequences too. */ |
3842 | for (; stack; stack = stack->next) | |
3843 | if (insn == stack->first) | |
3844 | { | |
3845 | stack->first = next; | |
3846 | break; | |
3847 | } | |
3848 | ||
5b0264cb | 3849 | gcc_assert (stack); |
89e99eea DB |
3850 | } |
3851 | ||
3852 | if (next) | |
3853 | { | |
3854 | PREV_INSN (next) = prev; | |
4b4bf941 | 3855 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
89e99eea DB |
3856 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; |
3857 | } | |
3858 | else if (last_insn == insn) | |
3859 | last_insn = prev; | |
3860 | else | |
3861 | { | |
49ad7cfa | 3862 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3863 | /* Scan all pending sequences too. */ |
3864 | for (; stack; stack = stack->next) | |
3865 | if (insn == stack->last) | |
3866 | { | |
3867 | stack->last = prev; | |
3868 | break; | |
3869 | } | |
3870 | ||
5b0264cb | 3871 | gcc_assert (stack); |
89e99eea | 3872 | } |
4b4bf941 | 3873 | if (!BARRIER_P (insn) |
53c17031 JH |
3874 | && (bb = BLOCK_FOR_INSN (insn))) |
3875 | { | |
38c1593d | 3876 | if (INSN_P (insn)) |
6fb5fa3c | 3877 | df_set_bb_dirty (bb); |
a813c111 | 3878 | if (BB_HEAD (bb) == insn) |
53c17031 | 3879 | { |
3bf1e984 RK |
3880 | /* Never ever delete the basic block note without deleting whole |
3881 | basic block. */ | |
5b0264cb | 3882 | gcc_assert (!NOTE_P (insn)); |
a813c111 | 3883 | BB_HEAD (bb) = next; |
53c17031 | 3884 | } |
a813c111 SB |
3885 | if (BB_END (bb) == insn) |
3886 | BB_END (bb) = prev; | |
53c17031 | 3887 | } |
89e99eea DB |
3888 | } |
3889 | ||
ee960939 OH |
3890 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3891 | ||
3892 | void | |
502b8322 | 3893 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 3894 | { |
5b0264cb | 3895 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
3896 | |
3897 | /* Put the register usage information on the CALL. If there is already | |
3898 | some usage information, put ours at the end. */ | |
3899 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3900 | { | |
3901 | rtx link; | |
3902 | ||
3903 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3904 | link = XEXP (link, 1)) | |
3905 | ; | |
3906 | ||
3907 | XEXP (link, 1) = call_fusage; | |
3908 | } | |
3909 | else | |
3910 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3911 | } | |
3912 | ||
23b2ce53 RS |
3913 | /* Delete all insns made since FROM. |
3914 | FROM becomes the new last instruction. */ | |
3915 | ||
3916 | void | |
502b8322 | 3917 | delete_insns_since (rtx from) |
23b2ce53 RS |
3918 | { |
3919 | if (from == 0) | |
3920 | first_insn = 0; | |
3921 | else | |
3922 | NEXT_INSN (from) = 0; | |
3923 | last_insn = from; | |
3924 | } | |
3925 | ||
5dab5552 MS |
3926 | /* This function is deprecated, please use sequences instead. |
3927 | ||
3928 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
3929 | The insns to be moved are those between FROM and TO. |
3930 | They are moved to a new position after the insn AFTER. | |
3931 | AFTER must not be FROM or TO or any insn in between. | |
3932 | ||
3933 | This function does not know about SEQUENCEs and hence should not be | |
3934 | called after delay-slot filling has been done. */ | |
3935 | ||
3936 | void | |
502b8322 | 3937 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
23b2ce53 RS |
3938 | { |
3939 | /* Splice this bunch out of where it is now. */ | |
3940 | if (PREV_INSN (from)) | |
3941 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3942 | if (NEXT_INSN (to)) | |
3943 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
3944 | if (last_insn == to) | |
3945 | last_insn = PREV_INSN (from); | |
3946 | if (first_insn == from) | |
3947 | first_insn = NEXT_INSN (to); | |
3948 | ||
3949 | /* Make the new neighbors point to it and it to them. */ | |
3950 | if (NEXT_INSN (after)) | |
3951 | PREV_INSN (NEXT_INSN (after)) = to; | |
3952 | ||
3953 | NEXT_INSN (to) = NEXT_INSN (after); | |
3954 | PREV_INSN (from) = after; | |
3955 | NEXT_INSN (after) = from; | |
3956 | if (after == last_insn) | |
3957 | last_insn = to; | |
3958 | } | |
3959 | ||
3c030e88 JH |
3960 | /* Same as function above, but take care to update BB boundaries. */ |
3961 | void | |
502b8322 | 3962 | reorder_insns (rtx from, rtx to, rtx after) |
3c030e88 JH |
3963 | { |
3964 | rtx prev = PREV_INSN (from); | |
3965 | basic_block bb, bb2; | |
3966 | ||
3967 | reorder_insns_nobb (from, to, after); | |
3968 | ||
4b4bf941 | 3969 | if (!BARRIER_P (after) |
3c030e88 JH |
3970 | && (bb = BLOCK_FOR_INSN (after))) |
3971 | { | |
3972 | rtx x; | |
6fb5fa3c | 3973 | df_set_bb_dirty (bb); |
68252e27 | 3974 | |
4b4bf941 | 3975 | if (!BARRIER_P (from) |
3c030e88 JH |
3976 | && (bb2 = BLOCK_FOR_INSN (from))) |
3977 | { | |
a813c111 SB |
3978 | if (BB_END (bb2) == to) |
3979 | BB_END (bb2) = prev; | |
6fb5fa3c | 3980 | df_set_bb_dirty (bb2); |
3c030e88 JH |
3981 | } |
3982 | ||
a813c111 SB |
3983 | if (BB_END (bb) == after) |
3984 | BB_END (bb) = to; | |
3c030e88 JH |
3985 | |
3986 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 3987 | if (!BARRIER_P (x)) |
63642d5a | 3988 | df_insn_change_bb (x, bb); |
3c030e88 JH |
3989 | } |
3990 | } | |
3991 | ||
23b2ce53 | 3992 | \f |
2f937369 DM |
3993 | /* Emit insn(s) of given code and pattern |
3994 | at a specified place within the doubly-linked list. | |
23b2ce53 | 3995 | |
2f937369 DM |
3996 | All of the emit_foo global entry points accept an object |
3997 | X which is either an insn list or a PATTERN of a single | |
3998 | instruction. | |
23b2ce53 | 3999 | |
2f937369 DM |
4000 | There are thus a few canonical ways to generate code and |
4001 | emit it at a specific place in the instruction stream. For | |
4002 | example, consider the instruction named SPOT and the fact that | |
4003 | we would like to emit some instructions before SPOT. We might | |
4004 | do it like this: | |
23b2ce53 | 4005 | |
2f937369 DM |
4006 | start_sequence (); |
4007 | ... emit the new instructions ... | |
4008 | insns_head = get_insns (); | |
4009 | end_sequence (); | |
23b2ce53 | 4010 | |
2f937369 | 4011 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4012 | |
2f937369 DM |
4013 | It used to be common to generate SEQUENCE rtl instead, but that |
4014 | is a relic of the past which no longer occurs. The reason is that | |
4015 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4016 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4017 | |
2f937369 | 4018 | /* Make X be output before the instruction BEFORE. */ |
23b2ce53 RS |
4019 | |
4020 | rtx | |
6fb5fa3c | 4021 | emit_insn_before_noloc (rtx x, rtx before, basic_block bb) |
23b2ce53 | 4022 | { |
2f937369 | 4023 | rtx last = before; |
b3694847 | 4024 | rtx insn; |
23b2ce53 | 4025 | |
5b0264cb | 4026 | gcc_assert (before); |
2f937369 DM |
4027 | |
4028 | if (x == NULL_RTX) | |
4029 | return last; | |
4030 | ||
4031 | switch (GET_CODE (x)) | |
23b2ce53 | 4032 | { |
b5b8b0ac | 4033 | case DEBUG_INSN: |
2f937369 DM |
4034 | case INSN: |
4035 | case JUMP_INSN: | |
4036 | case CALL_INSN: | |
4037 | case CODE_LABEL: | |
4038 | case BARRIER: | |
4039 | case NOTE: | |
4040 | insn = x; | |
4041 | while (insn) | |
4042 | { | |
4043 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4044 | add_insn_before (insn, before, bb); |
2f937369 DM |
4045 | last = insn; |
4046 | insn = next; | |
4047 | } | |
4048 | break; | |
4049 | ||
4050 | #ifdef ENABLE_RTL_CHECKING | |
4051 | case SEQUENCE: | |
5b0264cb | 4052 | gcc_unreachable (); |
2f937369 DM |
4053 | break; |
4054 | #endif | |
4055 | ||
4056 | default: | |
4057 | last = make_insn_raw (x); | |
6fb5fa3c | 4058 | add_insn_before (last, before, bb); |
2f937369 | 4059 | break; |
23b2ce53 RS |
4060 | } |
4061 | ||
2f937369 | 4062 | return last; |
23b2ce53 RS |
4063 | } |
4064 | ||
2f937369 | 4065 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4066 | and output it before the instruction BEFORE. */ |
4067 | ||
4068 | rtx | |
a7102479 | 4069 | emit_jump_insn_before_noloc (rtx x, rtx before) |
23b2ce53 | 4070 | { |
d950dee3 | 4071 | rtx insn, last = NULL_RTX; |
aff507f4 | 4072 | |
5b0264cb | 4073 | gcc_assert (before); |
2f937369 DM |
4074 | |
4075 | switch (GET_CODE (x)) | |
aff507f4 | 4076 | { |
b5b8b0ac | 4077 | case DEBUG_INSN: |
2f937369 DM |
4078 | case INSN: |
4079 | case JUMP_INSN: | |
4080 | case CALL_INSN: | |
4081 | case CODE_LABEL: | |
4082 | case BARRIER: | |
4083 | case NOTE: | |
4084 | insn = x; | |
4085 | while (insn) | |
4086 | { | |
4087 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4088 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4089 | last = insn; |
4090 | insn = next; | |
4091 | } | |
4092 | break; | |
4093 | ||
4094 | #ifdef ENABLE_RTL_CHECKING | |
4095 | case SEQUENCE: | |
5b0264cb | 4096 | gcc_unreachable (); |
2f937369 DM |
4097 | break; |
4098 | #endif | |
4099 | ||
4100 | default: | |
4101 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4102 | add_insn_before (last, before, NULL); |
2f937369 | 4103 | break; |
aff507f4 RK |
4104 | } |
4105 | ||
2f937369 | 4106 | return last; |
23b2ce53 RS |
4107 | } |
4108 | ||
2f937369 | 4109 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4110 | and output it before the instruction BEFORE. */ |
4111 | ||
4112 | rtx | |
a7102479 | 4113 | emit_call_insn_before_noloc (rtx x, rtx before) |
969d70ca | 4114 | { |
d950dee3 | 4115 | rtx last = NULL_RTX, insn; |
969d70ca | 4116 | |
5b0264cb | 4117 | gcc_assert (before); |
2f937369 DM |
4118 | |
4119 | switch (GET_CODE (x)) | |
969d70ca | 4120 | { |
b5b8b0ac | 4121 | case DEBUG_INSN: |
2f937369 DM |
4122 | case INSN: |
4123 | case JUMP_INSN: | |
4124 | case CALL_INSN: | |
4125 | case CODE_LABEL: | |
4126 | case BARRIER: | |
4127 | case NOTE: | |
4128 | insn = x; | |
4129 | while (insn) | |
4130 | { | |
4131 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4132 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4133 | last = insn; |
4134 | insn = next; | |
4135 | } | |
4136 | break; | |
4137 | ||
4138 | #ifdef ENABLE_RTL_CHECKING | |
4139 | case SEQUENCE: | |
5b0264cb | 4140 | gcc_unreachable (); |
2f937369 DM |
4141 | break; |
4142 | #endif | |
4143 | ||
4144 | default: | |
4145 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4146 | add_insn_before (last, before, NULL); |
2f937369 | 4147 | break; |
969d70ca JH |
4148 | } |
4149 | ||
2f937369 | 4150 | return last; |
969d70ca JH |
4151 | } |
4152 | ||
b5b8b0ac AO |
4153 | /* Make an instruction with body X and code DEBUG_INSN |
4154 | and output it before the instruction BEFORE. */ | |
4155 | ||
4156 | rtx | |
4157 | emit_debug_insn_before_noloc (rtx x, rtx before) | |
4158 | { | |
4159 | rtx last = NULL_RTX, insn; | |
4160 | ||
4161 | gcc_assert (before); | |
4162 | ||
4163 | switch (GET_CODE (x)) | |
4164 | { | |
4165 | case DEBUG_INSN: | |
4166 | case INSN: | |
4167 | case JUMP_INSN: | |
4168 | case CALL_INSN: | |
4169 | case CODE_LABEL: | |
4170 | case BARRIER: | |
4171 | case NOTE: | |
4172 | insn = x; | |
4173 | while (insn) | |
4174 | { | |
4175 | rtx next = NEXT_INSN (insn); | |
4176 | add_insn_before (insn, before, NULL); | |
4177 | last = insn; | |
4178 | insn = next; | |
4179 | } | |
4180 | break; | |
4181 | ||
4182 | #ifdef ENABLE_RTL_CHECKING | |
4183 | case SEQUENCE: | |
4184 | gcc_unreachable (); | |
4185 | break; | |
4186 | #endif | |
4187 | ||
4188 | default: | |
4189 | last = make_debug_insn_raw (x); | |
4190 | add_insn_before (last, before, NULL); | |
4191 | break; | |
4192 | } | |
4193 | ||
4194 | return last; | |
4195 | } | |
4196 | ||
23b2ce53 | 4197 | /* Make an insn of code BARRIER |
e881bb1b | 4198 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
4199 | |
4200 | rtx | |
502b8322 | 4201 | emit_barrier_before (rtx before) |
23b2ce53 | 4202 | { |
b3694847 | 4203 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4204 | |
4205 | INSN_UID (insn) = cur_insn_uid++; | |
4206 | ||
6fb5fa3c | 4207 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4208 | return insn; |
4209 | } | |
4210 | ||
e881bb1b RH |
4211 | /* Emit the label LABEL before the insn BEFORE. */ |
4212 | ||
4213 | rtx | |
502b8322 | 4214 | emit_label_before (rtx label, rtx before) |
e881bb1b RH |
4215 | { |
4216 | /* This can be called twice for the same label as a result of the | |
4217 | confusion that follows a syntax error! So make it harmless. */ | |
4218 | if (INSN_UID (label) == 0) | |
4219 | { | |
4220 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4221 | add_insn_before (label, before, NULL); |
e881bb1b RH |
4222 | } |
4223 | ||
4224 | return label; | |
4225 | } | |
4226 | ||
23b2ce53 RS |
4227 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
4228 | ||
4229 | rtx | |
a38e7aa5 | 4230 | emit_note_before (enum insn_note subtype, rtx before) |
23b2ce53 | 4231 | { |
b3694847 | 4232 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4233 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4234 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4235 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4236 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
23b2ce53 | 4237 | |
6fb5fa3c | 4238 | add_insn_before (note, before, NULL); |
23b2ce53 RS |
4239 | return note; |
4240 | } | |
4241 | \f | |
2f937369 DM |
4242 | /* Helper for emit_insn_after, handles lists of instructions |
4243 | efficiently. */ | |
23b2ce53 | 4244 | |
2f937369 | 4245 | static rtx |
6fb5fa3c | 4246 | emit_insn_after_1 (rtx first, rtx after, basic_block bb) |
23b2ce53 | 4247 | { |
2f937369 DM |
4248 | rtx last; |
4249 | rtx after_after; | |
6fb5fa3c DB |
4250 | if (!bb && !BARRIER_P (after)) |
4251 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4252 | |
6fb5fa3c | 4253 | if (bb) |
23b2ce53 | 4254 | { |
6fb5fa3c | 4255 | df_set_bb_dirty (bb); |
2f937369 | 4256 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4257 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4258 | { |
4259 | set_block_for_insn (last, bb); | |
4260 | df_insn_rescan (last); | |
4261 | } | |
4b4bf941 | 4262 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4263 | { |
4264 | set_block_for_insn (last, bb); | |
4265 | df_insn_rescan (last); | |
4266 | } | |
a813c111 SB |
4267 | if (BB_END (bb) == after) |
4268 | BB_END (bb) = last; | |
23b2ce53 RS |
4269 | } |
4270 | else | |
2f937369 DM |
4271 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4272 | continue; | |
4273 | ||
4274 | after_after = NEXT_INSN (after); | |
4275 | ||
4276 | NEXT_INSN (after) = first; | |
4277 | PREV_INSN (first) = after; | |
4278 | NEXT_INSN (last) = after_after; | |
4279 | if (after_after) | |
4280 | PREV_INSN (after_after) = last; | |
4281 | ||
4282 | if (after == last_insn) | |
4283 | last_insn = last; | |
e855c69d | 4284 | |
2f937369 DM |
4285 | return last; |
4286 | } | |
4287 | ||
6fb5fa3c DB |
4288 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4289 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
2f937369 DM |
4290 | |
4291 | rtx | |
6fb5fa3c | 4292 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
2f937369 DM |
4293 | { |
4294 | rtx last = after; | |
4295 | ||
5b0264cb | 4296 | gcc_assert (after); |
2f937369 DM |
4297 | |
4298 | if (x == NULL_RTX) | |
4299 | return last; | |
4300 | ||
4301 | switch (GET_CODE (x)) | |
23b2ce53 | 4302 | { |
b5b8b0ac | 4303 | case DEBUG_INSN: |
2f937369 DM |
4304 | case INSN: |
4305 | case JUMP_INSN: | |
4306 | case CALL_INSN: | |
4307 | case CODE_LABEL: | |
4308 | case BARRIER: | |
4309 | case NOTE: | |
6fb5fa3c | 4310 | last = emit_insn_after_1 (x, after, bb); |
2f937369 DM |
4311 | break; |
4312 | ||
4313 | #ifdef ENABLE_RTL_CHECKING | |
4314 | case SEQUENCE: | |
5b0264cb | 4315 | gcc_unreachable (); |
2f937369 DM |
4316 | break; |
4317 | #endif | |
4318 | ||
4319 | default: | |
4320 | last = make_insn_raw (x); | |
6fb5fa3c | 4321 | add_insn_after (last, after, bb); |
2f937369 | 4322 | break; |
23b2ce53 RS |
4323 | } |
4324 | ||
2f937369 | 4325 | return last; |
23b2ce53 RS |
4326 | } |
4327 | ||
255680cf | 4328 | |
2f937369 | 4329 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4330 | and output it after the insn AFTER. */ |
4331 | ||
4332 | rtx | |
a7102479 | 4333 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4334 | { |
2f937369 | 4335 | rtx last; |
23b2ce53 | 4336 | |
5b0264cb | 4337 | gcc_assert (after); |
2f937369 DM |
4338 | |
4339 | switch (GET_CODE (x)) | |
23b2ce53 | 4340 | { |
b5b8b0ac | 4341 | case DEBUG_INSN: |
2f937369 DM |
4342 | case INSN: |
4343 | case JUMP_INSN: | |
4344 | case CALL_INSN: | |
4345 | case CODE_LABEL: | |
4346 | case BARRIER: | |
4347 | case NOTE: | |
6fb5fa3c | 4348 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4349 | break; |
4350 | ||
4351 | #ifdef ENABLE_RTL_CHECKING | |
4352 | case SEQUENCE: | |
5b0264cb | 4353 | gcc_unreachable (); |
2f937369 DM |
4354 | break; |
4355 | #endif | |
4356 | ||
4357 | default: | |
4358 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4359 | add_insn_after (last, after, NULL); |
2f937369 | 4360 | break; |
23b2ce53 RS |
4361 | } |
4362 | ||
2f937369 DM |
4363 | return last; |
4364 | } | |
4365 | ||
4366 | /* Make an instruction with body X and code CALL_INSN | |
4367 | and output it after the instruction AFTER. */ | |
4368 | ||
4369 | rtx | |
a7102479 | 4370 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 DM |
4371 | { |
4372 | rtx last; | |
4373 | ||
5b0264cb | 4374 | gcc_assert (after); |
2f937369 DM |
4375 | |
4376 | switch (GET_CODE (x)) | |
4377 | { | |
b5b8b0ac | 4378 | case DEBUG_INSN: |
2f937369 DM |
4379 | case INSN: |
4380 | case JUMP_INSN: | |
4381 | case CALL_INSN: | |
4382 | case CODE_LABEL: | |
4383 | case BARRIER: | |
4384 | case NOTE: | |
6fb5fa3c | 4385 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4386 | break; |
4387 | ||
4388 | #ifdef ENABLE_RTL_CHECKING | |
4389 | case SEQUENCE: | |
5b0264cb | 4390 | gcc_unreachable (); |
2f937369 DM |
4391 | break; |
4392 | #endif | |
4393 | ||
4394 | default: | |
4395 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4396 | add_insn_after (last, after, NULL); |
2f937369 DM |
4397 | break; |
4398 | } | |
4399 | ||
4400 | return last; | |
23b2ce53 RS |
4401 | } |
4402 | ||
b5b8b0ac AO |
4403 | /* Make an instruction with body X and code CALL_INSN |
4404 | and output it after the instruction AFTER. */ | |
4405 | ||
4406 | rtx | |
4407 | emit_debug_insn_after_noloc (rtx x, rtx after) | |
4408 | { | |
4409 | rtx last; | |
4410 | ||
4411 | gcc_assert (after); | |
4412 | ||
4413 | switch (GET_CODE (x)) | |
4414 | { | |
4415 | case DEBUG_INSN: | |
4416 | case INSN: | |
4417 | case JUMP_INSN: | |
4418 | case CALL_INSN: | |
4419 | case CODE_LABEL: | |
4420 | case BARRIER: | |
4421 | case NOTE: | |
4422 | last = emit_insn_after_1 (x, after, NULL); | |
4423 | break; | |
4424 | ||
4425 | #ifdef ENABLE_RTL_CHECKING | |
4426 | case SEQUENCE: | |
4427 | gcc_unreachable (); | |
4428 | break; | |
4429 | #endif | |
4430 | ||
4431 | default: | |
4432 | last = make_debug_insn_raw (x); | |
4433 | add_insn_after (last, after, NULL); | |
4434 | break; | |
4435 | } | |
4436 | ||
4437 | return last; | |
4438 | } | |
4439 | ||
23b2ce53 RS |
4440 | /* Make an insn of code BARRIER |
4441 | and output it after the insn AFTER. */ | |
4442 | ||
4443 | rtx | |
502b8322 | 4444 | emit_barrier_after (rtx after) |
23b2ce53 | 4445 | { |
b3694847 | 4446 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4447 | |
4448 | INSN_UID (insn) = cur_insn_uid++; | |
4449 | ||
6fb5fa3c | 4450 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4451 | return insn; |
4452 | } | |
4453 | ||
4454 | /* Emit the label LABEL after the insn AFTER. */ | |
4455 | ||
4456 | rtx | |
502b8322 | 4457 | emit_label_after (rtx label, rtx after) |
23b2ce53 RS |
4458 | { |
4459 | /* This can be called twice for the same label | |
4460 | as a result of the confusion that follows a syntax error! | |
4461 | So make it harmless. */ | |
4462 | if (INSN_UID (label) == 0) | |
4463 | { | |
4464 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4465 | add_insn_after (label, after, NULL); |
23b2ce53 RS |
4466 | } |
4467 | ||
4468 | return label; | |
4469 | } | |
4470 | ||
4471 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4472 | ||
4473 | rtx | |
a38e7aa5 | 4474 | emit_note_after (enum insn_note subtype, rtx after) |
23b2ce53 | 4475 | { |
b3694847 | 4476 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4477 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4478 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4479 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4480 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
6fb5fa3c | 4481 | add_insn_after (note, after, NULL); |
23b2ce53 RS |
4482 | return note; |
4483 | } | |
23b2ce53 | 4484 | \f |
a7102479 | 4485 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4486 | rtx |
502b8322 | 4487 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4488 | { |
6fb5fa3c | 4489 | rtx last = emit_insn_after_noloc (pattern, after, NULL); |
0d682900 | 4490 | |
a7102479 | 4491 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4492 | return last; |
4493 | ||
2f937369 DM |
4494 | after = NEXT_INSN (after); |
4495 | while (1) | |
4496 | { | |
a7102479 | 4497 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4498 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4499 | if (after == last) |
4500 | break; | |
4501 | after = NEXT_INSN (after); | |
4502 | } | |
0d682900 JH |
4503 | return last; |
4504 | } | |
4505 | ||
a7102479 JH |
4506 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4507 | rtx | |
4508 | emit_insn_after (rtx pattern, rtx after) | |
4509 | { | |
b5b8b0ac AO |
4510 | rtx prev = after; |
4511 | ||
4512 | while (DEBUG_INSN_P (prev)) | |
4513 | prev = PREV_INSN (prev); | |
4514 | ||
4515 | if (INSN_P (prev)) | |
4516 | return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (prev)); | |
a7102479 | 4517 | else |
6fb5fa3c | 4518 | return emit_insn_after_noloc (pattern, after, NULL); |
a7102479 JH |
4519 | } |
4520 | ||
4521 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4522 | rtx |
502b8322 | 4523 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4524 | { |
a7102479 | 4525 | rtx last = emit_jump_insn_after_noloc (pattern, after); |
2f937369 | 4526 | |
a7102479 | 4527 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4528 | return last; |
4529 | ||
2f937369 DM |
4530 | after = NEXT_INSN (after); |
4531 | while (1) | |
4532 | { | |
a7102479 | 4533 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4534 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4535 | if (after == last) |
4536 | break; | |
4537 | after = NEXT_INSN (after); | |
4538 | } | |
0d682900 JH |
4539 | return last; |
4540 | } | |
4541 | ||
a7102479 JH |
4542 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4543 | rtx | |
4544 | emit_jump_insn_after (rtx pattern, rtx after) | |
4545 | { | |
b5b8b0ac AO |
4546 | rtx prev = after; |
4547 | ||
4548 | while (DEBUG_INSN_P (prev)) | |
4549 | prev = PREV_INSN (prev); | |
4550 | ||
4551 | if (INSN_P (prev)) | |
4552 | return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (prev)); | |
a7102479 JH |
4553 | else |
4554 | return emit_jump_insn_after_noloc (pattern, after); | |
4555 | } | |
4556 | ||
4557 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4558 | rtx |
502b8322 | 4559 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4560 | { |
a7102479 | 4561 | rtx last = emit_call_insn_after_noloc (pattern, after); |
2f937369 | 4562 | |
a7102479 | 4563 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4564 | return last; |
4565 | ||
2f937369 DM |
4566 | after = NEXT_INSN (after); |
4567 | while (1) | |
4568 | { | |
a7102479 | 4569 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4570 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4571 | if (after == last) |
4572 | break; | |
4573 | after = NEXT_INSN (after); | |
4574 | } | |
0d682900 JH |
4575 | return last; |
4576 | } | |
4577 | ||
a7102479 JH |
4578 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4579 | rtx | |
4580 | emit_call_insn_after (rtx pattern, rtx after) | |
4581 | { | |
b5b8b0ac AO |
4582 | rtx prev = after; |
4583 | ||
4584 | while (DEBUG_INSN_P (prev)) | |
4585 | prev = PREV_INSN (prev); | |
4586 | ||
4587 | if (INSN_P (prev)) | |
4588 | return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (prev)); | |
a7102479 JH |
4589 | else |
4590 | return emit_call_insn_after_noloc (pattern, after); | |
4591 | } | |
4592 | ||
b5b8b0ac AO |
4593 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
4594 | rtx | |
4595 | emit_debug_insn_after_setloc (rtx pattern, rtx after, int loc) | |
4596 | { | |
4597 | rtx last = emit_debug_insn_after_noloc (pattern, after); | |
4598 | ||
4599 | if (pattern == NULL_RTX || !loc) | |
4600 | return last; | |
4601 | ||
4602 | after = NEXT_INSN (after); | |
4603 | while (1) | |
4604 | { | |
4605 | if (active_insn_p (after) && !INSN_LOCATOR (after)) | |
4606 | INSN_LOCATOR (after) = loc; | |
4607 | if (after == last) | |
4608 | break; | |
4609 | after = NEXT_INSN (after); | |
4610 | } | |
4611 | return last; | |
4612 | } | |
4613 | ||
4614 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ | |
4615 | rtx | |
4616 | emit_debug_insn_after (rtx pattern, rtx after) | |
4617 | { | |
4618 | if (INSN_P (after)) | |
4619 | return emit_debug_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4620 | else | |
4621 | return emit_debug_insn_after_noloc (pattern, after); | |
4622 | } | |
4623 | ||
a7102479 | 4624 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4625 | rtx |
502b8322 | 4626 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
0d682900 JH |
4627 | { |
4628 | rtx first = PREV_INSN (before); | |
6fb5fa3c | 4629 | rtx last = emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4630 | |
4631 | if (pattern == NULL_RTX || !loc) | |
4632 | return last; | |
4633 | ||
26cb3993 JH |
4634 | if (!first) |
4635 | first = get_insns (); | |
4636 | else | |
4637 | first = NEXT_INSN (first); | |
a7102479 JH |
4638 | while (1) |
4639 | { | |
4640 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4641 | INSN_LOCATOR (first) = loc; | |
4642 | if (first == last) | |
4643 | break; | |
4644 | first = NEXT_INSN (first); | |
4645 | } | |
4646 | return last; | |
4647 | } | |
4648 | ||
4649 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4650 | rtx | |
4651 | emit_insn_before (rtx pattern, rtx before) | |
4652 | { | |
b5b8b0ac AO |
4653 | rtx next = before; |
4654 | ||
4655 | while (DEBUG_INSN_P (next)) | |
4656 | next = PREV_INSN (next); | |
4657 | ||
4658 | if (INSN_P (next)) | |
4659 | return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (next)); | |
a7102479 | 4660 | else |
6fb5fa3c | 4661 | return emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4662 | } |
4663 | ||
4664 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4665 | rtx | |
4666 | emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4667 | { | |
4668 | rtx first = PREV_INSN (before); | |
4669 | rtx last = emit_jump_insn_before_noloc (pattern, before); | |
4670 | ||
4671 | if (pattern == NULL_RTX) | |
4672 | return last; | |
4673 | ||
4674 | first = NEXT_INSN (first); | |
4675 | while (1) | |
4676 | { | |
4677 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4678 | INSN_LOCATOR (first) = loc; | |
4679 | if (first == last) | |
4680 | break; | |
4681 | first = NEXT_INSN (first); | |
4682 | } | |
4683 | return last; | |
4684 | } | |
4685 | ||
4686 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4687 | rtx | |
4688 | emit_jump_insn_before (rtx pattern, rtx before) | |
4689 | { | |
b5b8b0ac AO |
4690 | rtx next = before; |
4691 | ||
4692 | while (DEBUG_INSN_P (next)) | |
4693 | next = PREV_INSN (next); | |
4694 | ||
4695 | if (INSN_P (next)) | |
4696 | return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (next)); | |
a7102479 JH |
4697 | else |
4698 | return emit_jump_insn_before_noloc (pattern, before); | |
4699 | } | |
4700 | ||
4701 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4702 | rtx | |
4703 | emit_call_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4704 | { | |
4705 | rtx first = PREV_INSN (before); | |
4706 | rtx last = emit_call_insn_before_noloc (pattern, before); | |
0d682900 | 4707 | |
dd3adcf8 DJ |
4708 | if (pattern == NULL_RTX) |
4709 | return last; | |
4710 | ||
2f937369 DM |
4711 | first = NEXT_INSN (first); |
4712 | while (1) | |
4713 | { | |
a7102479 | 4714 | if (active_insn_p (first) && !INSN_LOCATOR (first)) |
0435312e | 4715 | INSN_LOCATOR (first) = loc; |
2f937369 DM |
4716 | if (first == last) |
4717 | break; | |
4718 | first = NEXT_INSN (first); | |
4719 | } | |
0d682900 JH |
4720 | return last; |
4721 | } | |
a7102479 JH |
4722 | |
4723 | /* like emit_call_insn_before_noloc, | |
4724 | but set insn_locator according to before. */ | |
4725 | rtx | |
4726 | emit_call_insn_before (rtx pattern, rtx before) | |
4727 | { | |
b5b8b0ac AO |
4728 | rtx next = before; |
4729 | ||
4730 | while (DEBUG_INSN_P (next)) | |
4731 | next = PREV_INSN (next); | |
4732 | ||
4733 | if (INSN_P (next)) | |
4734 | return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (next)); | |
a7102479 JH |
4735 | else |
4736 | return emit_call_insn_before_noloc (pattern, before); | |
4737 | } | |
b5b8b0ac AO |
4738 | |
4739 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4740 | rtx | |
4741 | emit_debug_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4742 | { | |
4743 | rtx first = PREV_INSN (before); | |
4744 | rtx last = emit_debug_insn_before_noloc (pattern, before); | |
4745 | ||
4746 | if (pattern == NULL_RTX) | |
4747 | return last; | |
4748 | ||
4749 | first = NEXT_INSN (first); | |
4750 | while (1) | |
4751 | { | |
4752 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4753 | INSN_LOCATOR (first) = loc; | |
4754 | if (first == last) | |
4755 | break; | |
4756 | first = NEXT_INSN (first); | |
4757 | } | |
4758 | return last; | |
4759 | } | |
4760 | ||
4761 | /* like emit_debug_insn_before_noloc, | |
4762 | but set insn_locator according to before. */ | |
4763 | rtx | |
4764 | emit_debug_insn_before (rtx pattern, rtx before) | |
4765 | { | |
4766 | if (INSN_P (before)) | |
4767 | return emit_debug_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4768 | else | |
4769 | return emit_debug_insn_before_noloc (pattern, before); | |
4770 | } | |
0d682900 | 4771 | \f |
2f937369 DM |
4772 | /* Take X and emit it at the end of the doubly-linked |
4773 | INSN list. | |
23b2ce53 RS |
4774 | |
4775 | Returns the last insn emitted. */ | |
4776 | ||
4777 | rtx | |
502b8322 | 4778 | emit_insn (rtx x) |
23b2ce53 | 4779 | { |
2f937369 DM |
4780 | rtx last = last_insn; |
4781 | rtx insn; | |
23b2ce53 | 4782 | |
2f937369 DM |
4783 | if (x == NULL_RTX) |
4784 | return last; | |
23b2ce53 | 4785 | |
2f937369 DM |
4786 | switch (GET_CODE (x)) |
4787 | { | |
b5b8b0ac | 4788 | case DEBUG_INSN: |
2f937369 DM |
4789 | case INSN: |
4790 | case JUMP_INSN: | |
4791 | case CALL_INSN: | |
4792 | case CODE_LABEL: | |
4793 | case BARRIER: | |
4794 | case NOTE: | |
4795 | insn = x; | |
4796 | while (insn) | |
23b2ce53 | 4797 | { |
2f937369 | 4798 | rtx next = NEXT_INSN (insn); |
23b2ce53 | 4799 | add_insn (insn); |
2f937369 DM |
4800 | last = insn; |
4801 | insn = next; | |
23b2ce53 | 4802 | } |
2f937369 | 4803 | break; |
23b2ce53 | 4804 | |
2f937369 DM |
4805 | #ifdef ENABLE_RTL_CHECKING |
4806 | case SEQUENCE: | |
5b0264cb | 4807 | gcc_unreachable (); |
2f937369 DM |
4808 | break; |
4809 | #endif | |
23b2ce53 | 4810 | |
2f937369 DM |
4811 | default: |
4812 | last = make_insn_raw (x); | |
4813 | add_insn (last); | |
4814 | break; | |
23b2ce53 RS |
4815 | } |
4816 | ||
4817 | return last; | |
4818 | } | |
4819 | ||
b5b8b0ac AO |
4820 | /* Make an insn of code DEBUG_INSN with pattern X |
4821 | and add it to the end of the doubly-linked list. */ | |
4822 | ||
4823 | rtx | |
4824 | emit_debug_insn (rtx x) | |
4825 | { | |
4826 | rtx last = last_insn; | |
4827 | rtx insn; | |
4828 | ||
4829 | if (x == NULL_RTX) | |
4830 | return last; | |
4831 | ||
4832 | switch (GET_CODE (x)) | |
4833 | { | |
4834 | case DEBUG_INSN: | |
4835 | case INSN: | |
4836 | case JUMP_INSN: | |
4837 | case CALL_INSN: | |
4838 | case CODE_LABEL: | |
4839 | case BARRIER: | |
4840 | case NOTE: | |
4841 | insn = x; | |
4842 | while (insn) | |
4843 | { | |
4844 | rtx next = NEXT_INSN (insn); | |
4845 | add_insn (insn); | |
4846 | last = insn; | |
4847 | insn = next; | |
4848 | } | |
4849 | break; | |
4850 | ||
4851 | #ifdef ENABLE_RTL_CHECKING | |
4852 | case SEQUENCE: | |
4853 | gcc_unreachable (); | |
4854 | break; | |
4855 | #endif | |
4856 | ||
4857 | default: | |
4858 | last = make_debug_insn_raw (x); | |
4859 | add_insn (last); | |
4860 | break; | |
4861 | } | |
4862 | ||
4863 | return last; | |
4864 | } | |
4865 | ||
2f937369 DM |
4866 | /* Make an insn of code JUMP_INSN with pattern X |
4867 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4868 | |
4869 | rtx | |
502b8322 | 4870 | emit_jump_insn (rtx x) |
23b2ce53 | 4871 | { |
d950dee3 | 4872 | rtx last = NULL_RTX, insn; |
23b2ce53 | 4873 | |
2f937369 | 4874 | switch (GET_CODE (x)) |
23b2ce53 | 4875 | { |
b5b8b0ac | 4876 | case DEBUG_INSN: |
2f937369 DM |
4877 | case INSN: |
4878 | case JUMP_INSN: | |
4879 | case CALL_INSN: | |
4880 | case CODE_LABEL: | |
4881 | case BARRIER: | |
4882 | case NOTE: | |
4883 | insn = x; | |
4884 | while (insn) | |
4885 | { | |
4886 | rtx next = NEXT_INSN (insn); | |
4887 | add_insn (insn); | |
4888 | last = insn; | |
4889 | insn = next; | |
4890 | } | |
4891 | break; | |
e0a5c5eb | 4892 | |
2f937369 DM |
4893 | #ifdef ENABLE_RTL_CHECKING |
4894 | case SEQUENCE: | |
5b0264cb | 4895 | gcc_unreachable (); |
2f937369 DM |
4896 | break; |
4897 | #endif | |
e0a5c5eb | 4898 | |
2f937369 DM |
4899 | default: |
4900 | last = make_jump_insn_raw (x); | |
4901 | add_insn (last); | |
4902 | break; | |
3c030e88 | 4903 | } |
e0a5c5eb RS |
4904 | |
4905 | return last; | |
4906 | } | |
4907 | ||
2f937369 | 4908 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
4909 | and add it to the end of the doubly-linked list. */ |
4910 | ||
4911 | rtx | |
502b8322 | 4912 | emit_call_insn (rtx x) |
23b2ce53 | 4913 | { |
2f937369 DM |
4914 | rtx insn; |
4915 | ||
4916 | switch (GET_CODE (x)) | |
23b2ce53 | 4917 | { |
b5b8b0ac | 4918 | case DEBUG_INSN: |
2f937369 DM |
4919 | case INSN: |
4920 | case JUMP_INSN: | |
4921 | case CALL_INSN: | |
4922 | case CODE_LABEL: | |
4923 | case BARRIER: | |
4924 | case NOTE: | |
4925 | insn = emit_insn (x); | |
4926 | break; | |
23b2ce53 | 4927 | |
2f937369 DM |
4928 | #ifdef ENABLE_RTL_CHECKING |
4929 | case SEQUENCE: | |
5b0264cb | 4930 | gcc_unreachable (); |
2f937369 DM |
4931 | break; |
4932 | #endif | |
23b2ce53 | 4933 | |
2f937369 DM |
4934 | default: |
4935 | insn = make_call_insn_raw (x); | |
23b2ce53 | 4936 | add_insn (insn); |
2f937369 | 4937 | break; |
23b2ce53 | 4938 | } |
2f937369 DM |
4939 | |
4940 | return insn; | |
23b2ce53 RS |
4941 | } |
4942 | ||
4943 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4944 | ||
4945 | rtx | |
502b8322 | 4946 | emit_label (rtx label) |
23b2ce53 RS |
4947 | { |
4948 | /* This can be called twice for the same label | |
4949 | as a result of the confusion that follows a syntax error! | |
4950 | So make it harmless. */ | |
4951 | if (INSN_UID (label) == 0) | |
4952 | { | |
4953 | INSN_UID (label) = cur_insn_uid++; | |
4954 | add_insn (label); | |
4955 | } | |
4956 | return label; | |
4957 | } | |
4958 | ||
4959 | /* Make an insn of code BARRIER | |
4960 | and add it to the end of the doubly-linked list. */ | |
4961 | ||
4962 | rtx | |
502b8322 | 4963 | emit_barrier (void) |
23b2ce53 | 4964 | { |
b3694847 | 4965 | rtx barrier = rtx_alloc (BARRIER); |
23b2ce53 RS |
4966 | INSN_UID (barrier) = cur_insn_uid++; |
4967 | add_insn (barrier); | |
4968 | return barrier; | |
4969 | } | |
4970 | ||
5f2fc772 | 4971 | /* Emit a copy of note ORIG. */ |
502b8322 | 4972 | |
5f2fc772 NS |
4973 | rtx |
4974 | emit_note_copy (rtx orig) | |
4975 | { | |
4976 | rtx note; | |
4977 | ||
5f2fc772 NS |
4978 | note = rtx_alloc (NOTE); |
4979 | ||
4980 | INSN_UID (note) = cur_insn_uid++; | |
4981 | NOTE_DATA (note) = NOTE_DATA (orig); | |
a38e7aa5 | 4982 | NOTE_KIND (note) = NOTE_KIND (orig); |
5f2fc772 NS |
4983 | BLOCK_FOR_INSN (note) = NULL; |
4984 | add_insn (note); | |
4985 | ||
2e040219 | 4986 | return note; |
23b2ce53 RS |
4987 | } |
4988 | ||
2e040219 NS |
4989 | /* Make an insn of code NOTE or type NOTE_NO |
4990 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4991 | |
4992 | rtx | |
a38e7aa5 | 4993 | emit_note (enum insn_note kind) |
23b2ce53 | 4994 | { |
b3694847 | 4995 | rtx note; |
23b2ce53 | 4996 | |
23b2ce53 RS |
4997 | note = rtx_alloc (NOTE); |
4998 | INSN_UID (note) = cur_insn_uid++; | |
a38e7aa5 | 4999 | NOTE_KIND (note) = kind; |
dd107e66 | 5000 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ba4f7968 | 5001 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
5002 | add_insn (note); |
5003 | return note; | |
5004 | } | |
5005 | ||
c41c1387 RS |
5006 | /* Emit a clobber of lvalue X. */ |
5007 | ||
5008 | rtx | |
5009 | emit_clobber (rtx x) | |
5010 | { | |
5011 | /* CONCATs should not appear in the insn stream. */ | |
5012 | if (GET_CODE (x) == CONCAT) | |
5013 | { | |
5014 | emit_clobber (XEXP (x, 0)); | |
5015 | return emit_clobber (XEXP (x, 1)); | |
5016 | } | |
5017 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
5018 | } | |
5019 | ||
5020 | /* Return a sequence of insns to clobber lvalue X. */ | |
5021 | ||
5022 | rtx | |
5023 | gen_clobber (rtx x) | |
5024 | { | |
5025 | rtx seq; | |
5026 | ||
5027 | start_sequence (); | |
5028 | emit_clobber (x); | |
5029 | seq = get_insns (); | |
5030 | end_sequence (); | |
5031 | return seq; | |
5032 | } | |
5033 | ||
5034 | /* Emit a use of rvalue X. */ | |
5035 | ||
5036 | rtx | |
5037 | emit_use (rtx x) | |
5038 | { | |
5039 | /* CONCATs should not appear in the insn stream. */ | |
5040 | if (GET_CODE (x) == CONCAT) | |
5041 | { | |
5042 | emit_use (XEXP (x, 0)); | |
5043 | return emit_use (XEXP (x, 1)); | |
5044 | } | |
5045 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
5046 | } | |
5047 | ||
5048 | /* Return a sequence of insns to use rvalue X. */ | |
5049 | ||
5050 | rtx | |
5051 | gen_use (rtx x) | |
5052 | { | |
5053 | rtx seq; | |
5054 | ||
5055 | start_sequence (); | |
5056 | emit_use (x); | |
5057 | seq = get_insns (); | |
5058 | end_sequence (); | |
5059 | return seq; | |
5060 | } | |
5061 | ||
23b2ce53 | 5062 | /* Cause next statement to emit a line note even if the line number |
0cea056b | 5063 | has not changed. */ |
23b2ce53 RS |
5064 | |
5065 | void | |
502b8322 | 5066 | force_next_line_note (void) |
23b2ce53 | 5067 | { |
6773e15f | 5068 | last_location = -1; |
23b2ce53 | 5069 | } |
87b47c85 AM |
5070 | |
5071 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
30f7a378 | 5072 | note of this type already exists, remove it first. */ |
87b47c85 | 5073 | |
3d238248 | 5074 | rtx |
502b8322 | 5075 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
5076 | { |
5077 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
5078 | ||
52488da1 JW |
5079 | switch (kind) |
5080 | { | |
5081 | case REG_EQUAL: | |
5082 | case REG_EQUIV: | |
5083 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
5084 | has multiple sets (some callers assume single_set | |
5085 | means the insn only has one set, when in fact it | |
5086 | means the insn only has one * useful * set). */ | |
5087 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
5088 | { | |
5b0264cb | 5089 | gcc_assert (!note); |
52488da1 JW |
5090 | return NULL_RTX; |
5091 | } | |
5092 | ||
5093 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
5094 | It serves no useful purpose and breaks eliminate_regs. */ | |
5095 | if (GET_CODE (datum) == ASM_OPERANDS) | |
5096 | return NULL_RTX; | |
6fb5fa3c DB |
5097 | |
5098 | if (note) | |
5099 | { | |
5100 | XEXP (note, 0) = datum; | |
5101 | df_notes_rescan (insn); | |
5102 | return note; | |
5103 | } | |
52488da1 JW |
5104 | break; |
5105 | ||
5106 | default: | |
6fb5fa3c DB |
5107 | if (note) |
5108 | { | |
5109 | XEXP (note, 0) = datum; | |
5110 | return note; | |
5111 | } | |
52488da1 JW |
5112 | break; |
5113 | } | |
3d238248 | 5114 | |
65c5f2a6 | 5115 | add_reg_note (insn, kind, datum); |
6fb5fa3c DB |
5116 | |
5117 | switch (kind) | |
3d238248 | 5118 | { |
6fb5fa3c DB |
5119 | case REG_EQUAL: |
5120 | case REG_EQUIV: | |
5121 | df_notes_rescan (insn); | |
5122 | break; | |
5123 | default: | |
5124 | break; | |
3d238248 | 5125 | } |
87b47c85 | 5126 | |
3d238248 | 5127 | return REG_NOTES (insn); |
87b47c85 | 5128 | } |
23b2ce53 RS |
5129 | \f |
5130 | /* Return an indication of which type of insn should have X as a body. | |
5131 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
5132 | ||
d78db459 | 5133 | static enum rtx_code |
502b8322 | 5134 | classify_insn (rtx x) |
23b2ce53 | 5135 | { |
4b4bf941 | 5136 | if (LABEL_P (x)) |
23b2ce53 RS |
5137 | return CODE_LABEL; |
5138 | if (GET_CODE (x) == CALL) | |
5139 | return CALL_INSN; | |
5140 | if (GET_CODE (x) == RETURN) | |
5141 | return JUMP_INSN; | |
5142 | if (GET_CODE (x) == SET) | |
5143 | { | |
5144 | if (SET_DEST (x) == pc_rtx) | |
5145 | return JUMP_INSN; | |
5146 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
5147 | return CALL_INSN; | |
5148 | else | |
5149 | return INSN; | |
5150 | } | |
5151 | if (GET_CODE (x) == PARALLEL) | |
5152 | { | |
b3694847 | 5153 | int j; |
23b2ce53 RS |
5154 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
5155 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
5156 | return CALL_INSN; | |
5157 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
5158 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
5159 | return JUMP_INSN; | |
5160 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
5161 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
5162 | return CALL_INSN; | |
5163 | } | |
5164 | return INSN; | |
5165 | } | |
5166 | ||
5167 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
5168 | If X is a label, it is simply added into the insn chain. */ | |
5169 | ||
5170 | rtx | |
502b8322 | 5171 | emit (rtx x) |
23b2ce53 RS |
5172 | { |
5173 | enum rtx_code code = classify_insn (x); | |
5174 | ||
5b0264cb | 5175 | switch (code) |
23b2ce53 | 5176 | { |
5b0264cb NS |
5177 | case CODE_LABEL: |
5178 | return emit_label (x); | |
5179 | case INSN: | |
5180 | return emit_insn (x); | |
5181 | case JUMP_INSN: | |
5182 | { | |
5183 | rtx insn = emit_jump_insn (x); | |
5184 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) | |
5185 | return emit_barrier (); | |
5186 | return insn; | |
5187 | } | |
5188 | case CALL_INSN: | |
5189 | return emit_call_insn (x); | |
b5b8b0ac AO |
5190 | case DEBUG_INSN: |
5191 | return emit_debug_insn (x); | |
5b0264cb NS |
5192 | default: |
5193 | gcc_unreachable (); | |
23b2ce53 | 5194 | } |
23b2ce53 RS |
5195 | } |
5196 | \f | |
e2500fed | 5197 | /* Space for free sequence stack entries. */ |
1431042e | 5198 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 5199 | |
4dfa0342 RH |
5200 | /* Begin emitting insns to a sequence. If this sequence will contain |
5201 | something that might cause the compiler to pop arguments to function | |
5202 | calls (because those pops have previously been deferred; see | |
5203 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
5204 | before calling this function. That will ensure that the deferred | |
5205 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
5206 | |
5207 | void | |
502b8322 | 5208 | start_sequence (void) |
23b2ce53 RS |
5209 | { |
5210 | struct sequence_stack *tem; | |
5211 | ||
e2500fed GK |
5212 | if (free_sequence_stack != NULL) |
5213 | { | |
5214 | tem = free_sequence_stack; | |
5215 | free_sequence_stack = tem->next; | |
5216 | } | |
5217 | else | |
1b4572a8 | 5218 | tem = GGC_NEW (struct sequence_stack); |
23b2ce53 | 5219 | |
49ad7cfa | 5220 | tem->next = seq_stack; |
23b2ce53 RS |
5221 | tem->first = first_insn; |
5222 | tem->last = last_insn; | |
5223 | ||
49ad7cfa | 5224 | seq_stack = tem; |
23b2ce53 RS |
5225 | |
5226 | first_insn = 0; | |
5227 | last_insn = 0; | |
5228 | } | |
5229 | ||
5c7a310f MM |
5230 | /* Set up the insn chain starting with FIRST as the current sequence, |
5231 | saving the previously current one. See the documentation for | |
5232 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5233 | |
5234 | void | |
502b8322 | 5235 | push_to_sequence (rtx first) |
23b2ce53 RS |
5236 | { |
5237 | rtx last; | |
5238 | ||
5239 | start_sequence (); | |
5240 | ||
5241 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
5242 | ||
5243 | first_insn = first; | |
5244 | last_insn = last; | |
5245 | } | |
5246 | ||
bb27eeda SE |
5247 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5248 | looping through the list. */ | |
5249 | ||
5250 | void | |
5251 | push_to_sequence2 (rtx first, rtx last) | |
5252 | { | |
5253 | start_sequence (); | |
5254 | ||
5255 | first_insn = first; | |
5256 | last_insn = last; | |
5257 | } | |
5258 | ||
f15ae3a1 TW |
5259 | /* Set up the outer-level insn chain |
5260 | as the current sequence, saving the previously current one. */ | |
5261 | ||
5262 | void | |
502b8322 | 5263 | push_topmost_sequence (void) |
f15ae3a1 | 5264 | { |
aefdd5ab | 5265 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
5266 | |
5267 | start_sequence (); | |
5268 | ||
49ad7cfa | 5269 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
5270 | top = stack; |
5271 | ||
5272 | first_insn = top->first; | |
5273 | last_insn = top->last; | |
5274 | } | |
5275 | ||
5276 | /* After emitting to the outer-level insn chain, update the outer-level | |
5277 | insn chain, and restore the previous saved state. */ | |
5278 | ||
5279 | void | |
502b8322 | 5280 | pop_topmost_sequence (void) |
f15ae3a1 | 5281 | { |
aefdd5ab | 5282 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 5283 | |
49ad7cfa | 5284 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
5285 | top = stack; |
5286 | ||
5287 | top->first = first_insn; | |
5288 | top->last = last_insn; | |
5289 | ||
5290 | end_sequence (); | |
5291 | } | |
5292 | ||
23b2ce53 RS |
5293 | /* After emitting to a sequence, restore previous saved state. |
5294 | ||
5c7a310f | 5295 | To get the contents of the sequence just made, you must call |
2f937369 | 5296 | `get_insns' *before* calling here. |
5c7a310f MM |
5297 | |
5298 | If the compiler might have deferred popping arguments while | |
5299 | generating this sequence, and this sequence will not be immediately | |
5300 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5301 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5302 | pops are inserted into this sequence, and not into some random |
5303 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5304 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5305 | |
5306 | void | |
502b8322 | 5307 | end_sequence (void) |
23b2ce53 | 5308 | { |
49ad7cfa | 5309 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
5310 | |
5311 | first_insn = tem->first; | |
5312 | last_insn = tem->last; | |
49ad7cfa | 5313 | seq_stack = tem->next; |
23b2ce53 | 5314 | |
e2500fed GK |
5315 | memset (tem, 0, sizeof (*tem)); |
5316 | tem->next = free_sequence_stack; | |
5317 | free_sequence_stack = tem; | |
23b2ce53 RS |
5318 | } |
5319 | ||
5320 | /* Return 1 if currently emitting into a sequence. */ | |
5321 | ||
5322 | int | |
502b8322 | 5323 | in_sequence_p (void) |
23b2ce53 | 5324 | { |
49ad7cfa | 5325 | return seq_stack != 0; |
23b2ce53 | 5326 | } |
23b2ce53 | 5327 | \f |
59ec66dc MM |
5328 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5329 | ||
2bbdec73 | 5330 | static void |
bd60bab2 | 5331 | init_virtual_regs (void) |
59ec66dc | 5332 | { |
bd60bab2 JH |
5333 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5334 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5335 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5336 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5337 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
49ad7cfa BS |
5338 | } |
5339 | ||
da43a810 BS |
5340 | \f |
5341 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5342 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5343 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5344 | static int copy_insn_n_scratches; | |
5345 | ||
5346 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5347 | copied an ASM_OPERANDS. | |
5348 | In that case, it is the original input-operand vector. */ | |
5349 | static rtvec orig_asm_operands_vector; | |
5350 | ||
5351 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5352 | copied an ASM_OPERANDS. | |
5353 | In that case, it is the copied input-operand vector. */ | |
5354 | static rtvec copy_asm_operands_vector; | |
5355 | ||
5356 | /* Likewise for the constraints vector. */ | |
5357 | static rtvec orig_asm_constraints_vector; | |
5358 | static rtvec copy_asm_constraints_vector; | |
5359 | ||
5360 | /* Recursively create a new copy of an rtx for copy_insn. | |
5361 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5362 | ASM_OPERANDs properly. | |
5363 | Normally, this function is not used directly; use copy_insn as front end. | |
5364 | However, you could first copy an insn pattern with copy_insn and then use | |
5365 | this function afterwards to properly copy any REG_NOTEs containing | |
5366 | SCRATCHes. */ | |
5367 | ||
5368 | rtx | |
502b8322 | 5369 | copy_insn_1 (rtx orig) |
da43a810 | 5370 | { |
b3694847 SS |
5371 | rtx copy; |
5372 | int i, j; | |
5373 | RTX_CODE code; | |
5374 | const char *format_ptr; | |
da43a810 | 5375 | |
cd9c1ca8 RH |
5376 | if (orig == NULL) |
5377 | return NULL; | |
5378 | ||
da43a810 BS |
5379 | code = GET_CODE (orig); |
5380 | ||
5381 | switch (code) | |
5382 | { | |
5383 | case REG: | |
da43a810 BS |
5384 | case CONST_INT: |
5385 | case CONST_DOUBLE: | |
091a3ac7 | 5386 | case CONST_FIXED: |
69ef87e2 | 5387 | case CONST_VECTOR: |
da43a810 BS |
5388 | case SYMBOL_REF: |
5389 | case CODE_LABEL: | |
5390 | case PC: | |
5391 | case CC0: | |
da43a810 | 5392 | return orig; |
3e89ed8d JH |
5393 | case CLOBBER: |
5394 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER) | |
5395 | return orig; | |
5396 | break; | |
da43a810 BS |
5397 | |
5398 | case SCRATCH: | |
5399 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5400 | if (copy_insn_scratch_in[i] == orig) | |
5401 | return copy_insn_scratch_out[i]; | |
5402 | break; | |
5403 | ||
5404 | case CONST: | |
6fb5fa3c | 5405 | if (shared_const_p (orig)) |
da43a810 BS |
5406 | return orig; |
5407 | break; | |
750c9258 | 5408 | |
da43a810 BS |
5409 | /* A MEM with a constant address is not sharable. The problem is that |
5410 | the constant address may need to be reloaded. If the mem is shared, | |
5411 | then reloading one copy of this mem will cause all copies to appear | |
5412 | to have been reloaded. */ | |
5413 | ||
5414 | default: | |
5415 | break; | |
5416 | } | |
5417 | ||
aacd3885 RS |
5418 | /* Copy the various flags, fields, and other information. We assume |
5419 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5420 | not be copied. That is the sensible default behavior, and forces |
5421 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5422 | copy = shallow_copy_rtx (orig); |
da43a810 BS |
5423 | |
5424 | /* We do not copy the USED flag, which is used as a mark bit during | |
5425 | walks over the RTL. */ | |
2adc7f12 | 5426 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5427 | |
5428 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
ec8e098d | 5429 | if (INSN_P (orig)) |
da43a810 | 5430 | { |
2adc7f12 JJ |
5431 | RTX_FLAG (copy, jump) = 0; |
5432 | RTX_FLAG (copy, call) = 0; | |
5433 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5434 | } |
750c9258 | 5435 | |
da43a810 BS |
5436 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5437 | ||
5438 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5439 | switch (*format_ptr++) |
5440 | { | |
5441 | case 'e': | |
5442 | if (XEXP (orig, i) != NULL) | |
5443 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5444 | break; | |
da43a810 | 5445 | |
aacd3885 RS |
5446 | case 'E': |
5447 | case 'V': | |
5448 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5449 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5450 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5451 | XVEC (copy, i) = copy_asm_operands_vector; | |
5452 | else if (XVEC (orig, i) != NULL) | |
5453 | { | |
5454 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5455 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5456 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5457 | } | |
5458 | break; | |
da43a810 | 5459 | |
aacd3885 RS |
5460 | case 't': |
5461 | case 'w': | |
5462 | case 'i': | |
5463 | case 's': | |
5464 | case 'S': | |
5465 | case 'u': | |
5466 | case '0': | |
5467 | /* These are left unchanged. */ | |
5468 | break; | |
da43a810 | 5469 | |
aacd3885 RS |
5470 | default: |
5471 | gcc_unreachable (); | |
5472 | } | |
da43a810 BS |
5473 | |
5474 | if (code == SCRATCH) | |
5475 | { | |
5476 | i = copy_insn_n_scratches++; | |
5b0264cb | 5477 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5478 | copy_insn_scratch_in[i] = orig; |
5479 | copy_insn_scratch_out[i] = copy; | |
5480 | } | |
5481 | else if (code == ASM_OPERANDS) | |
5482 | { | |
6462bb43 AO |
5483 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5484 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5485 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5486 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5487 | } |
5488 | ||
5489 | return copy; | |
5490 | } | |
5491 | ||
5492 | /* Create a new copy of an rtx. | |
5493 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5494 | ASM_OPERANDs properly. | |
5495 | INSN doesn't really have to be a full INSN; it could be just the | |
5496 | pattern. */ | |
5497 | rtx | |
502b8322 | 5498 | copy_insn (rtx insn) |
da43a810 BS |
5499 | { |
5500 | copy_insn_n_scratches = 0; | |
5501 | orig_asm_operands_vector = 0; | |
5502 | orig_asm_constraints_vector = 0; | |
5503 | copy_asm_operands_vector = 0; | |
5504 | copy_asm_constraints_vector = 0; | |
5505 | return copy_insn_1 (insn); | |
5506 | } | |
59ec66dc | 5507 | |
23b2ce53 RS |
5508 | /* Initialize data structures and variables in this file |
5509 | before generating rtl for each function. */ | |
5510 | ||
5511 | void | |
502b8322 | 5512 | init_emit (void) |
23b2ce53 | 5513 | { |
23b2ce53 RS |
5514 | first_insn = NULL; |
5515 | last_insn = NULL; | |
b5b8b0ac AO |
5516 | if (MIN_NONDEBUG_INSN_UID) |
5517 | cur_insn_uid = MIN_NONDEBUG_INSN_UID; | |
5518 | else | |
5519 | cur_insn_uid = 1; | |
5520 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5521 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
6773e15f | 5522 | last_location = UNKNOWN_LOCATION; |
23b2ce53 | 5523 | first_label_num = label_num; |
49ad7cfa | 5524 | seq_stack = NULL; |
23b2ce53 | 5525 | |
23b2ce53 RS |
5526 | /* Init the tables that describe all the pseudo regs. */ |
5527 | ||
3e029763 | 5528 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5529 | |
3e029763 | 5530 | crtl->emit.regno_pointer_align |
1b4572a8 | 5531 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5532 | |
750c9258 | 5533 | regno_reg_rtx |
1b4572a8 | 5534 | = GGC_NEWVEC (rtx, crtl->emit.regno_pointer_align_length); |
0d4903b8 | 5535 | |
e50126e8 | 5536 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 JL |
5537 | memcpy (regno_reg_rtx, |
5538 | static_regno_reg_rtx, | |
5539 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); | |
e50126e8 | 5540 | |
23b2ce53 | 5541 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5542 | init_virtual_regs (); |
740ab4a2 RK |
5543 | |
5544 | /* Indicate that the virtual registers and stack locations are | |
5545 | all pointers. */ | |
3502dc9c JDA |
5546 | REG_POINTER (stack_pointer_rtx) = 1; |
5547 | REG_POINTER (frame_pointer_rtx) = 1; | |
5548 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5549 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5550 | |
3502dc9c JDA |
5551 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5552 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5553 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5554 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5555 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5556 | |
86fe05e0 | 5557 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5558 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5559 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5560 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5561 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5562 | ||
5563 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5564 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5565 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5566 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5567 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5568 | #endif |
5569 | ||
5e82e7bd JVA |
5570 | #ifdef INIT_EXPANDERS |
5571 | INIT_EXPANDERS; | |
5572 | #endif | |
23b2ce53 RS |
5573 | } |
5574 | ||
a73b091d | 5575 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
69ef87e2 AH |
5576 | |
5577 | static rtx | |
a73b091d | 5578 | gen_const_vector (enum machine_mode mode, int constant) |
69ef87e2 AH |
5579 | { |
5580 | rtx tem; | |
5581 | rtvec v; | |
5582 | int units, i; | |
5583 | enum machine_mode inner; | |
5584 | ||
5585 | units = GET_MODE_NUNITS (mode); | |
5586 | inner = GET_MODE_INNER (mode); | |
5587 | ||
15ed7b52 JG |
5588 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5589 | ||
69ef87e2 AH |
5590 | v = rtvec_alloc (units); |
5591 | ||
a73b091d JW |
5592 | /* We need to call this function after we set the scalar const_tiny_rtx |
5593 | entries. */ | |
5594 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
69ef87e2 AH |
5595 | |
5596 | for (i = 0; i < units; ++i) | |
a73b091d | 5597 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
69ef87e2 | 5598 | |
a06e3c40 | 5599 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5600 | return tem; |
5601 | } | |
5602 | ||
a06e3c40 | 5603 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5604 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5605 | rtx |
502b8322 | 5606 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
a06e3c40 | 5607 | { |
a73b091d JW |
5608 | enum machine_mode inner = GET_MODE_INNER (mode); |
5609 | int nunits = GET_MODE_NUNITS (mode); | |
5610 | rtx x; | |
a06e3c40 R |
5611 | int i; |
5612 | ||
a73b091d JW |
5613 | /* Check to see if all of the elements have the same value. */ |
5614 | x = RTVEC_ELT (v, nunits - 1); | |
5615 | for (i = nunits - 2; i >= 0; i--) | |
5616 | if (RTVEC_ELT (v, i) != x) | |
5617 | break; | |
5618 | ||
5619 | /* If the values are all the same, check to see if we can use one of the | |
5620 | standard constant vectors. */ | |
5621 | if (i == -1) | |
5622 | { | |
5623 | if (x == CONST0_RTX (inner)) | |
5624 | return CONST0_RTX (mode); | |
5625 | else if (x == CONST1_RTX (inner)) | |
5626 | return CONST1_RTX (mode); | |
5627 | } | |
5628 | ||
5629 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5630 | } |
5631 | ||
b5deb7b6 SL |
5632 | /* Initialise global register information required by all functions. */ |
5633 | ||
5634 | void | |
5635 | init_emit_regs (void) | |
5636 | { | |
5637 | int i; | |
5638 | ||
5639 | /* Reset register attributes */ | |
5640 | htab_empty (reg_attrs_htab); | |
5641 | ||
5642 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5643 | init_reg_modes_target (); | |
5644 | ||
5645 | /* Assign register numbers to the globally defined register rtx. */ | |
5646 | pc_rtx = gen_rtx_PC (VOIDmode); | |
5647 | cc0_rtx = gen_rtx_CC0 (VOIDmode); | |
5648 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
5649 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5650 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5651 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5652 | virtual_incoming_args_rtx = | |
5653 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5654 | virtual_stack_vars_rtx = | |
5655 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5656 | virtual_stack_dynamic_rtx = | |
5657 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5658 | virtual_outgoing_args_rtx = | |
5659 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5660 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
5661 | ||
5662 | /* Initialize RTL for commonly used hard registers. These are | |
5663 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5664 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5665 | static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); | |
5666 | ||
5667 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5668 | return_address_pointer_rtx | |
5669 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5670 | #endif | |
5671 | ||
b5deb7b6 SL |
5672 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
5673 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
5674 | else | |
5675 | pic_offset_table_rtx = NULL_RTX; | |
5676 | } | |
5677 | ||
23b2ce53 RS |
5678 | /* Create some permanent unique rtl objects shared between all functions. |
5679 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
5680 | ||
5681 | void | |
502b8322 | 5682 | init_emit_once (int line_numbers) |
23b2ce53 RS |
5683 | { |
5684 | int i; | |
5685 | enum machine_mode mode; | |
9ec36da5 | 5686 | enum machine_mode double_mode; |
23b2ce53 | 5687 | |
091a3ac7 CF |
5688 | /* Initialize the CONST_INT, CONST_DOUBLE, CONST_FIXED, and memory attribute |
5689 | hash tables. */ | |
17211ab5 GK |
5690 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5691 | const_int_htab_eq, NULL); | |
173b24b9 | 5692 | |
17211ab5 GK |
5693 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5694 | const_double_htab_eq, NULL); | |
5692c7bc | 5695 | |
091a3ac7 CF |
5696 | const_fixed_htab = htab_create_ggc (37, const_fixed_htab_hash, |
5697 | const_fixed_htab_eq, NULL); | |
5698 | ||
17211ab5 GK |
5699 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5700 | mem_attrs_htab_eq, NULL); | |
a560d4d4 JH |
5701 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5702 | reg_attrs_htab_eq, NULL); | |
67673f5c | 5703 | |
23b2ce53 RS |
5704 | no_line_numbers = ! line_numbers; |
5705 | ||
43fa6302 AS |
5706 | /* Compute the word and byte modes. */ |
5707 | ||
5708 | byte_mode = VOIDmode; | |
5709 | word_mode = VOIDmode; | |
5710 | double_mode = VOIDmode; | |
5711 | ||
15ed7b52 JG |
5712 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5713 | mode != VOIDmode; | |
43fa6302 AS |
5714 | mode = GET_MODE_WIDER_MODE (mode)) |
5715 | { | |
5716 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5717 | && byte_mode == VOIDmode) | |
5718 | byte_mode = mode; | |
5719 | ||
5720 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5721 | && word_mode == VOIDmode) | |
5722 | word_mode = mode; | |
5723 | } | |
5724 | ||
15ed7b52 JG |
5725 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5726 | mode != VOIDmode; | |
43fa6302 AS |
5727 | mode = GET_MODE_WIDER_MODE (mode)) |
5728 | { | |
5729 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5730 | && double_mode == VOIDmode) | |
5731 | double_mode = mode; | |
5732 | } | |
5733 | ||
5734 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5735 | ||
5da077de | 5736 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5737 | /* This is to initialize {init|mark|free}_machine_status before the first |
5738 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5739 | end which calls push_function_context_to before the first call to |
5da077de AS |
5740 | init_function_start. */ |
5741 | INIT_EXPANDERS; | |
5742 | #endif | |
5743 | ||
23b2ce53 RS |
5744 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5745 | ||
a2a8cc44 | 5746 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 5747 | tries to use these variables. */ |
23b2ce53 | 5748 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5749 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5750 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5751 | |
68d75312 JC |
5752 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5753 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5754 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5755 | else |
3b80f6ca | 5756 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5757 | |
5692c7bc ZW |
5758 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5759 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5760 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
aefa9d43 KG |
5761 | |
5762 | dconstm1 = dconst1; | |
5763 | dconstm1.sign = 1; | |
03f2ea93 RS |
5764 | |
5765 | dconsthalf = dconst1; | |
1e92bbb9 | 5766 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 5767 | |
f7657db9 | 5768 | for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++) |
23b2ce53 | 5769 | { |
aefa9d43 | 5770 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
5771 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
5772 | ||
15ed7b52 JG |
5773 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5774 | mode != VOIDmode; | |
5775 | mode = GET_MODE_WIDER_MODE (mode)) | |
5776 | const_tiny_rtx[i][(int) mode] = | |
5777 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5778 | ||
5779 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5780 | mode != VOIDmode; | |
23b2ce53 | 5781 | mode = GET_MODE_WIDER_MODE (mode)) |
5692c7bc ZW |
5782 | const_tiny_rtx[i][(int) mode] = |
5783 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5784 | |
906c4e36 | 5785 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 5786 | |
15ed7b52 JG |
5787 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5788 | mode != VOIDmode; | |
23b2ce53 | 5789 | mode = GET_MODE_WIDER_MODE (mode)) |
906c4e36 | 5790 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
5791 | |
5792 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5793 | mode != VOIDmode; | |
5794 | mode = GET_MODE_WIDER_MODE (mode)) | |
5795 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
5796 | } |
5797 | ||
e90721b1 AP |
5798 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5799 | mode != VOIDmode; | |
5800 | mode = GET_MODE_WIDER_MODE (mode)) | |
5801 | { | |
5802 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5803 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5804 | } | |
5805 | ||
5806 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5807 | mode != VOIDmode; | |
5808 | mode = GET_MODE_WIDER_MODE (mode)) | |
5809 | { | |
5810 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5811 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5812 | } | |
5813 | ||
69ef87e2 AH |
5814 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5815 | mode != VOIDmode; | |
5816 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5817 | { |
5818 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5819 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5820 | } | |
69ef87e2 AH |
5821 | |
5822 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5823 | mode != VOIDmode; | |
5824 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5825 | { |
5826 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5827 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5828 | } | |
69ef87e2 | 5829 | |
325217ed CF |
5830 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
5831 | mode != VOIDmode; | |
5832 | mode = GET_MODE_WIDER_MODE (mode)) | |
5833 | { | |
5834 | FCONST0(mode).data.high = 0; | |
5835 | FCONST0(mode).data.low = 0; | |
5836 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5837 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5838 | FCONST0 (mode), mode); | |
325217ed CF |
5839 | } |
5840 | ||
5841 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
5842 | mode != VOIDmode; | |
5843 | mode = GET_MODE_WIDER_MODE (mode)) | |
5844 | { | |
5845 | FCONST0(mode).data.high = 0; | |
5846 | FCONST0(mode).data.low = 0; | |
5847 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5848 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5849 | FCONST0 (mode), mode); | |
325217ed CF |
5850 | } |
5851 | ||
5852 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
5853 | mode != VOIDmode; | |
5854 | mode = GET_MODE_WIDER_MODE (mode)) | |
5855 | { | |
5856 | FCONST0(mode).data.high = 0; | |
5857 | FCONST0(mode).data.low = 0; | |
5858 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5859 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5860 | FCONST0 (mode), mode); | |
325217ed CF |
5861 | |
5862 | /* We store the value 1. */ | |
5863 | FCONST1(mode).data.high = 0; | |
5864 | FCONST1(mode).data.low = 0; | |
5865 | FCONST1(mode).mode = mode; | |
5866 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5867 | 2 * HOST_BITS_PER_WIDE_INT, | |
5868 | &FCONST1(mode).data.low, | |
5869 | &FCONST1(mode).data.high, | |
5870 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5871 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5872 | FCONST1 (mode), mode); | |
325217ed CF |
5873 | } |
5874 | ||
5875 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
5876 | mode != VOIDmode; | |
5877 | mode = GET_MODE_WIDER_MODE (mode)) | |
5878 | { | |
5879 | FCONST0(mode).data.high = 0; | |
5880 | FCONST0(mode).data.low = 0; | |
5881 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5882 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5883 | FCONST0 (mode), mode); | |
325217ed CF |
5884 | |
5885 | /* We store the value 1. */ | |
5886 | FCONST1(mode).data.high = 0; | |
5887 | FCONST1(mode).data.low = 0; | |
5888 | FCONST1(mode).mode = mode; | |
5889 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5890 | 2 * HOST_BITS_PER_WIDE_INT, | |
5891 | &FCONST1(mode).data.low, | |
5892 | &FCONST1(mode).data.high, | |
5893 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5894 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5895 | FCONST1 (mode), mode); | |
5896 | } | |
5897 | ||
5898 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT); | |
5899 | mode != VOIDmode; | |
5900 | mode = GET_MODE_WIDER_MODE (mode)) | |
5901 | { | |
5902 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5903 | } | |
5904 | ||
5905 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT); | |
5906 | mode != VOIDmode; | |
5907 | mode = GET_MODE_WIDER_MODE (mode)) | |
5908 | { | |
5909 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5910 | } | |
5911 | ||
5912 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM); | |
5913 | mode != VOIDmode; | |
5914 | mode = GET_MODE_WIDER_MODE (mode)) | |
5915 | { | |
5916 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5917 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5918 | } | |
5919 | ||
5920 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM); | |
5921 | mode != VOIDmode; | |
5922 | mode = GET_MODE_WIDER_MODE (mode)) | |
5923 | { | |
5924 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5925 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
5926 | } |
5927 | ||
dbbbbf3b JDA |
5928 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5929 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5930 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 5931 | |
f0417c82 RH |
5932 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5933 | if (STORE_FLAG_VALUE == 1) | |
5934 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
23b2ce53 | 5935 | } |
a11759a3 | 5936 | \f |
969d70ca JH |
5937 | /* Produce exact duplicate of insn INSN after AFTER. |
5938 | Care updating of libcall regions if present. */ | |
5939 | ||
5940 | rtx | |
502b8322 | 5941 | emit_copy_of_insn_after (rtx insn, rtx after) |
969d70ca | 5942 | { |
60564289 | 5943 | rtx new_rtx, link; |
969d70ca JH |
5944 | |
5945 | switch (GET_CODE (insn)) | |
5946 | { | |
5947 | case INSN: | |
60564289 | 5948 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5949 | break; |
5950 | ||
5951 | case JUMP_INSN: | |
60564289 | 5952 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5953 | break; |
5954 | ||
b5b8b0ac AO |
5955 | case DEBUG_INSN: |
5956 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
5957 | break; | |
5958 | ||
969d70ca | 5959 | case CALL_INSN: |
60564289 | 5960 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 5961 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 5962 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 5963 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
5964 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
5965 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
5966 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
5967 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) | |
becfd6e5 | 5968 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
5969 | break; |
5970 | ||
5971 | default: | |
5b0264cb | 5972 | gcc_unreachable (); |
969d70ca JH |
5973 | } |
5974 | ||
5975 | /* Update LABEL_NUSES. */ | |
60564289 | 5976 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 5977 | |
60564289 | 5978 | INSN_LOCATOR (new_rtx) = INSN_LOCATOR (insn); |
ba4f7968 | 5979 | |
0a3d71f5 JW |
5980 | /* If the old insn is frame related, then so is the new one. This is |
5981 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
5982 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 5983 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 5984 | |
cf7c4aa6 HPN |
5985 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
5986 | will make them. REG_LABEL_TARGETs are created there too, but are | |
5987 | supposed to be sticky, so we copy them. */ | |
969d70ca | 5988 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 5989 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca JH |
5990 | { |
5991 | if (GET_CODE (link) == EXPR_LIST) | |
60564289 | 5992 | add_reg_note (new_rtx, REG_NOTE_KIND (link), |
65c5f2a6 | 5993 | copy_insn_1 (XEXP (link, 0))); |
969d70ca | 5994 | else |
60564289 | 5995 | add_reg_note (new_rtx, REG_NOTE_KIND (link), XEXP (link, 0)); |
969d70ca JH |
5996 | } |
5997 | ||
60564289 KG |
5998 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
5999 | return new_rtx; | |
969d70ca | 6000 | } |
e2500fed | 6001 | |
1431042e | 6002 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d JH |
6003 | rtx |
6004 | gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno) | |
6005 | { | |
6006 | if (hard_reg_clobbers[mode][regno]) | |
6007 | return hard_reg_clobbers[mode][regno]; | |
6008 | else | |
6009 | return (hard_reg_clobbers[mode][regno] = | |
6010 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
6011 | } | |
6012 | ||
e2500fed | 6013 | #include "gt-emit-rtl.h" |