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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
5624e564 | 2 | Copyright (C) 1987-2015 Free Software Foundation, Inc. |
23b2ce53 | 3 | |
1322177d | 4 | This file is part of GCC. |
23b2ce53 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
23b2ce53 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
23b2ce53 RS |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
19 | |
20 | ||
21 | /* Middle-to-low level generation of rtx code and insns. | |
22 | ||
f822fcf7 KH |
23 | This file contains support functions for creating rtl expressions |
24 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
25 | |
26 | The patterns of the insns are created by machine-dependent | |
27 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
28 | the machine description. These routines make the individual rtx's |
29 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
30 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
31 | dependent is the kind of rtx's they make and what arguments they |
32 | use. */ | |
23b2ce53 RS |
33 | |
34 | #include "config.h" | |
670ee920 | 35 | #include "system.h" |
4977bab6 ZW |
36 | #include "coretypes.h" |
37 | #include "tm.h" | |
718f9c0f | 38 | #include "diagnostic-core.h" |
23b2ce53 | 39 | #include "rtl.h" |
40e23961 MC |
40 | #include "alias.h" |
41 | #include "symtab.h" | |
a25c7971 | 42 | #include "tree.h" |
40e23961 | 43 | #include "fold-const.h" |
d8a2d370 | 44 | #include "varasm.h" |
60393bbc | 45 | #include "predict.h" |
83685514 | 46 | #include "hard-reg-set.h" |
23b2ce53 | 47 | #include "function.h" |
60393bbc AM |
48 | #include "cfgrtl.h" |
49 | #include "basic-block.h" | |
50 | #include "tree-eh.h" | |
51 | #include "tm_p.h" | |
52 | #include "flags.h" | |
d8a2d370 | 53 | #include "stringpool.h" |
36566b39 PK |
54 | #include "insn-config.h" |
55 | #include "expmed.h" | |
56 | #include "dojump.h" | |
57 | #include "explow.h" | |
58 | #include "calls.h" | |
59 | #include "emit-rtl.h" | |
60 | #include "stmt.h" | |
23b2ce53 RS |
61 | #include "expr.h" |
62 | #include "regs.h" | |
e9a25f70 | 63 | #include "recog.h" |
0dfa1860 | 64 | #include "bitmap.h" |
e1772ac0 | 65 | #include "debug.h" |
d23c55c2 | 66 | #include "langhooks.h" |
6fb5fa3c | 67 | #include "df.h" |
b5b8b0ac | 68 | #include "params.h" |
d4ebfa65 | 69 | #include "target.h" |
9b2b7279 | 70 | #include "builtins.h" |
9021b8ec | 71 | #include "rtl-iter.h" |
ca695ac9 | 72 | |
5fb0e246 RS |
73 | struct target_rtl default_target_rtl; |
74 | #if SWITCHABLE_TARGET | |
75 | struct target_rtl *this_target_rtl = &default_target_rtl; | |
76 | #endif | |
77 | ||
78 | #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx) | |
79 | ||
1d445e9e ILT |
80 | /* Commonly used modes. */ |
81 | ||
ef4bddc2 RS |
82 | machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
83 | machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
84 | machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ | |
85 | machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ | |
1d445e9e | 86 | |
bd60bab2 JH |
87 | /* Datastructures maintained for currently processed function in RTL form. */ |
88 | ||
3e029763 | 89 | struct rtl_data x_rtl; |
bd60bab2 JH |
90 | |
91 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
b8698a0f | 92 | Allocated in parallel with regno_pointer_align. |
bd60bab2 JH |
93 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal |
94 | with length attribute nested in top level structures. */ | |
95 | ||
96 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
97 | |
98 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
99 | in the entire compilation a unique label number. */ | |
100 | ||
044b4de3 | 101 | static GTY(()) int label_num = 1; |
23b2ce53 | 102 | |
23b2ce53 RS |
103 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
104 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
e7c82a99 JJ |
105 | record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX |
106 | is set only for MODE_INT and MODE_VECTOR_INT modes. */ | |
23b2ce53 | 107 | |
e7c82a99 | 108 | rtx const_tiny_rtx[4][(int) MAX_MACHINE_MODE]; |
23b2ce53 | 109 | |
68d75312 JC |
110 | rtx const_true_rtx; |
111 | ||
23b2ce53 RS |
112 | REAL_VALUE_TYPE dconst0; |
113 | REAL_VALUE_TYPE dconst1; | |
114 | REAL_VALUE_TYPE dconst2; | |
115 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 116 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 117 | |
325217ed CF |
118 | /* Record fixed-point constant 0 and 1. */ |
119 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
120 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
121 | ||
23b2ce53 RS |
122 | /* We make one copy of (const_int C) where C is in |
123 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
124 | to save space during the compilation and simplify comparisons of | |
125 | integers. */ | |
126 | ||
5da077de | 127 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 128 | |
ca4adc91 RS |
129 | /* Standard pieces of rtx, to be substituted directly into things. */ |
130 | rtx pc_rtx; | |
131 | rtx ret_rtx; | |
132 | rtx simple_return_rtx; | |
133 | rtx cc0_rtx; | |
134 | ||
1476d1bd MM |
135 | /* Marker used for denoting an INSN, which should never be accessed (i.e., |
136 | this pointer should normally never be dereferenced), but is required to be | |
137 | distinct from NULL_RTX. Currently used by peephole2 pass. */ | |
138 | rtx_insn *invalid_insn_rtx; | |
139 | ||
c13e8210 MM |
140 | /* A hash table storing CONST_INTs whose absolute value is greater |
141 | than MAX_SAVED_CONST_INT. */ | |
142 | ||
6c907cff | 143 | struct const_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
144 | { |
145 | typedef HOST_WIDE_INT compare_type; | |
146 | ||
147 | static hashval_t hash (rtx i); | |
148 | static bool equal (rtx i, HOST_WIDE_INT h); | |
149 | }; | |
c13e8210 | 150 | |
aebf76a2 TS |
151 | static GTY ((cache)) hash_table<const_int_hasher> *const_int_htab; |
152 | ||
6c907cff | 153 | struct const_wide_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
154 | { |
155 | static hashval_t hash (rtx x); | |
156 | static bool equal (rtx x, rtx y); | |
157 | }; | |
158 | ||
159 | static GTY ((cache)) hash_table<const_wide_int_hasher> *const_wide_int_htab; | |
807e902e | 160 | |
a560d4d4 | 161 | /* A hash table storing register attribute structures. */ |
6c907cff | 162 | struct reg_attr_hasher : ggc_cache_ptr_hash<reg_attrs> |
aebf76a2 TS |
163 | { |
164 | static hashval_t hash (reg_attrs *x); | |
165 | static bool equal (reg_attrs *a, reg_attrs *b); | |
166 | }; | |
167 | ||
168 | static GTY ((cache)) hash_table<reg_attr_hasher> *reg_attrs_htab; | |
a560d4d4 | 169 | |
5692c7bc | 170 | /* A hash table storing all CONST_DOUBLEs. */ |
6c907cff | 171 | struct const_double_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
172 | { |
173 | static hashval_t hash (rtx x); | |
174 | static bool equal (rtx x, rtx y); | |
175 | }; | |
176 | ||
177 | static GTY ((cache)) hash_table<const_double_hasher> *const_double_htab; | |
5692c7bc | 178 | |
091a3ac7 | 179 | /* A hash table storing all CONST_FIXEDs. */ |
6c907cff | 180 | struct const_fixed_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
181 | { |
182 | static hashval_t hash (rtx x); | |
183 | static bool equal (rtx x, rtx y); | |
184 | }; | |
185 | ||
186 | static GTY ((cache)) hash_table<const_fixed_hasher> *const_fixed_htab; | |
091a3ac7 | 187 | |
3e029763 | 188 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) |
b5b8b0ac | 189 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 | 190 | #define first_label_num (crtl->emit.x_first_label_num) |
23b2ce53 | 191 | |
5eb2a9f2 | 192 | static void set_used_decls (tree); |
502b8322 | 193 | static void mark_label_nuses (rtx); |
807e902e | 194 | #if TARGET_SUPPORTS_WIDE_INT |
807e902e KZ |
195 | static rtx lookup_const_wide_int (rtx); |
196 | #endif | |
502b8322 | 197 | static rtx lookup_const_double (rtx); |
091a3ac7 | 198 | static rtx lookup_const_fixed (rtx); |
502b8322 | 199 | static reg_attrs *get_reg_attrs (tree, int); |
ef4bddc2 | 200 | static rtx gen_const_vector (machine_mode, int); |
32b32b16 | 201 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 202 | |
6b24c259 JH |
203 | /* Probability of the conditional branch currently proceeded by try_split. |
204 | Set to -1 otherwise. */ | |
205 | int split_branch_probability = -1; | |
ca695ac9 | 206 | \f |
c13e8210 MM |
207 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
208 | ||
aebf76a2 TS |
209 | hashval_t |
210 | const_int_hasher::hash (rtx x) | |
c13e8210 | 211 | { |
aebf76a2 | 212 | return (hashval_t) INTVAL (x); |
c13e8210 MM |
213 | } |
214 | ||
cc2902df | 215 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
216 | CONST_INT) is the same as that given by Y (which is really a |
217 | HOST_WIDE_INT *). */ | |
218 | ||
aebf76a2 TS |
219 | bool |
220 | const_int_hasher::equal (rtx x, HOST_WIDE_INT y) | |
c13e8210 | 221 | { |
aebf76a2 | 222 | return (INTVAL (x) == y); |
5692c7bc ZW |
223 | } |
224 | ||
807e902e KZ |
225 | #if TARGET_SUPPORTS_WIDE_INT |
226 | /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */ | |
227 | ||
aebf76a2 TS |
228 | hashval_t |
229 | const_wide_int_hasher::hash (rtx x) | |
807e902e KZ |
230 | { |
231 | int i; | |
d7ca26e4 | 232 | unsigned HOST_WIDE_INT hash = 0; |
aebf76a2 | 233 | const_rtx xr = x; |
807e902e KZ |
234 | |
235 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
236 | hash += CONST_WIDE_INT_ELT (xr, i); | |
237 | ||
238 | return (hashval_t) hash; | |
239 | } | |
240 | ||
241 | /* Returns nonzero if the value represented by X (which is really a | |
242 | CONST_WIDE_INT) is the same as that given by Y (which is really a | |
243 | CONST_WIDE_INT). */ | |
244 | ||
aebf76a2 TS |
245 | bool |
246 | const_wide_int_hasher::equal (rtx x, rtx y) | |
807e902e KZ |
247 | { |
248 | int i; | |
aebf76a2 TS |
249 | const_rtx xr = x; |
250 | const_rtx yr = y; | |
807e902e | 251 | if (CONST_WIDE_INT_NUNITS (xr) != CONST_WIDE_INT_NUNITS (yr)) |
aebf76a2 | 252 | return false; |
807e902e KZ |
253 | |
254 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
255 | if (CONST_WIDE_INT_ELT (xr, i) != CONST_WIDE_INT_ELT (yr, i)) | |
aebf76a2 | 256 | return false; |
807e902e | 257 | |
aebf76a2 | 258 | return true; |
807e902e KZ |
259 | } |
260 | #endif | |
261 | ||
5692c7bc | 262 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ |
aebf76a2 TS |
263 | hashval_t |
264 | const_double_hasher::hash (rtx x) | |
5692c7bc | 265 | { |
aebf76a2 | 266 | const_rtx const value = x; |
46b33600 | 267 | hashval_t h; |
5692c7bc | 268 | |
807e902e | 269 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (value) == VOIDmode) |
46b33600 RH |
270 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); |
271 | else | |
fe352c29 | 272 | { |
15c812e3 | 273 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
274 | /* MODE is used in the comparison, so it should be in the hash. */ |
275 | h ^= GET_MODE (value); | |
276 | } | |
5692c7bc ZW |
277 | return h; |
278 | } | |
279 | ||
cc2902df | 280 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc | 281 | is the same as that represented by Y (really a ...) */ |
aebf76a2 TS |
282 | bool |
283 | const_double_hasher::equal (rtx x, rtx y) | |
5692c7bc | 284 | { |
aebf76a2 | 285 | const_rtx const a = x, b = y; |
5692c7bc ZW |
286 | |
287 | if (GET_MODE (a) != GET_MODE (b)) | |
288 | return 0; | |
807e902e | 289 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (a) == VOIDmode) |
8580f7a0 RH |
290 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) |
291 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
292 | else | |
293 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
294 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
295 | } |
296 | ||
091a3ac7 CF |
297 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
298 | ||
aebf76a2 TS |
299 | hashval_t |
300 | const_fixed_hasher::hash (rtx x) | |
091a3ac7 | 301 | { |
aebf76a2 | 302 | const_rtx const value = x; |
091a3ac7 CF |
303 | hashval_t h; |
304 | ||
305 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
306 | /* MODE is used in the comparison, so it should be in the hash. */ | |
307 | h ^= GET_MODE (value); | |
308 | return h; | |
309 | } | |
310 | ||
aebf76a2 TS |
311 | /* Returns nonzero if the value represented by X is the same as that |
312 | represented by Y. */ | |
091a3ac7 | 313 | |
aebf76a2 TS |
314 | bool |
315 | const_fixed_hasher::equal (rtx x, rtx y) | |
091a3ac7 | 316 | { |
aebf76a2 | 317 | const_rtx const a = x, b = y; |
091a3ac7 CF |
318 | |
319 | if (GET_MODE (a) != GET_MODE (b)) | |
320 | return 0; | |
321 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
322 | } | |
323 | ||
f12144dd | 324 | /* Return true if the given memory attributes are equal. */ |
c13e8210 | 325 | |
96b3c03f | 326 | bool |
f12144dd | 327 | mem_attrs_eq_p (const struct mem_attrs *p, const struct mem_attrs *q) |
c13e8210 | 328 | { |
96b3c03f RB |
329 | if (p == q) |
330 | return true; | |
331 | if (!p || !q) | |
332 | return false; | |
754c3d5d RS |
333 | return (p->alias == q->alias |
334 | && p->offset_known_p == q->offset_known_p | |
335 | && (!p->offset_known_p || p->offset == q->offset) | |
336 | && p->size_known_p == q->size_known_p | |
337 | && (!p->size_known_p || p->size == q->size) | |
338 | && p->align == q->align | |
09e881c9 | 339 | && p->addrspace == q->addrspace |
78b76d08 SB |
340 | && (p->expr == q->expr |
341 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
342 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
343 | } |
344 | ||
f12144dd | 345 | /* Set MEM's memory attributes so that they are the same as ATTRS. */ |
10b76d73 | 346 | |
f12144dd RS |
347 | static void |
348 | set_mem_attrs (rtx mem, mem_attrs *attrs) | |
349 | { | |
f12144dd RS |
350 | /* If everything is the default, we can just clear the attributes. */ |
351 | if (mem_attrs_eq_p (attrs, mode_mem_attrs[(int) GET_MODE (mem)])) | |
352 | { | |
353 | MEM_ATTRS (mem) = 0; | |
354 | return; | |
355 | } | |
173b24b9 | 356 | |
84053e02 RB |
357 | if (!MEM_ATTRS (mem) |
358 | || !mem_attrs_eq_p (attrs, MEM_ATTRS (mem))) | |
173b24b9 | 359 | { |
766090c2 | 360 | MEM_ATTRS (mem) = ggc_alloc<mem_attrs> (); |
84053e02 | 361 | memcpy (MEM_ATTRS (mem), attrs, sizeof (mem_attrs)); |
173b24b9 | 362 | } |
c13e8210 MM |
363 | } |
364 | ||
a560d4d4 JH |
365 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
366 | ||
aebf76a2 TS |
367 | hashval_t |
368 | reg_attr_hasher::hash (reg_attrs *x) | |
a560d4d4 | 369 | { |
aebf76a2 | 370 | const reg_attrs *const p = x; |
a560d4d4 | 371 | |
9841210f | 372 | return ((p->offset * 1000) ^ (intptr_t) p->decl); |
a560d4d4 JH |
373 | } |
374 | ||
aebf76a2 TS |
375 | /* Returns nonzero if the value represented by X is the same as that given by |
376 | Y. */ | |
a560d4d4 | 377 | |
aebf76a2 TS |
378 | bool |
379 | reg_attr_hasher::equal (reg_attrs *x, reg_attrs *y) | |
a560d4d4 | 380 | { |
aebf76a2 TS |
381 | const reg_attrs *const p = x; |
382 | const reg_attrs *const q = y; | |
a560d4d4 JH |
383 | |
384 | return (p->decl == q->decl && p->offset == q->offset); | |
385 | } | |
386 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
387 | one identical to it is not already in the table. We are doing this for | |
388 | MEM of mode MODE. */ | |
389 | ||
390 | static reg_attrs * | |
502b8322 | 391 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
392 | { |
393 | reg_attrs attrs; | |
a560d4d4 JH |
394 | |
395 | /* If everything is the default, we can just return zero. */ | |
396 | if (decl == 0 && offset == 0) | |
397 | return 0; | |
398 | ||
399 | attrs.decl = decl; | |
400 | attrs.offset = offset; | |
401 | ||
aebf76a2 | 402 | reg_attrs **slot = reg_attrs_htab->find_slot (&attrs, INSERT); |
a560d4d4 JH |
403 | if (*slot == 0) |
404 | { | |
766090c2 | 405 | *slot = ggc_alloc<reg_attrs> (); |
a560d4d4 JH |
406 | memcpy (*slot, &attrs, sizeof (reg_attrs)); |
407 | } | |
408 | ||
aebf76a2 | 409 | return *slot; |
a560d4d4 JH |
410 | } |
411 | ||
6fb5fa3c DB |
412 | |
413 | #if !HAVE_blockage | |
adddc347 HPN |
414 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule, |
415 | and to block register equivalences to be seen across this insn. */ | |
6fb5fa3c DB |
416 | |
417 | rtx | |
418 | gen_blockage (void) | |
419 | { | |
420 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
421 | MEM_VOLATILE_P (x) = true; | |
422 | return x; | |
423 | } | |
424 | #endif | |
425 | ||
426 | ||
8deccbb7 RS |
427 | /* Set the mode and register number of X to MODE and REGNO. */ |
428 | ||
429 | void | |
430 | set_mode_and_regno (rtx x, machine_mode mode, unsigned int regno) | |
431 | { | |
9188b286 RS |
432 | unsigned int nregs = (HARD_REGISTER_NUM_P (regno) |
433 | ? hard_regno_nregs[regno][mode] | |
434 | : 1); | |
8deccbb7 | 435 | PUT_MODE_RAW (x, mode); |
9188b286 | 436 | set_regno_raw (x, regno, nregs); |
8deccbb7 RS |
437 | } |
438 | ||
08394eef BS |
439 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
440 | don't attempt to share with the various global pieces of rtl (such as | |
441 | frame_pointer_rtx). */ | |
442 | ||
443 | rtx | |
8deccbb7 | 444 | gen_raw_REG (machine_mode mode, unsigned int regno) |
08394eef | 445 | { |
2d44c7de | 446 | rtx x = rtx_alloc_stat (REG MEM_STAT_INFO); |
8deccbb7 | 447 | set_mode_and_regno (x, mode, regno); |
9fccb335 | 448 | REG_ATTRS (x) = NULL; |
08394eef BS |
449 | ORIGINAL_REGNO (x) = regno; |
450 | return x; | |
451 | } | |
452 | ||
c5c76735 JL |
453 | /* There are some RTL codes that require special attention; the generation |
454 | functions do the raw handling. If you add to this list, modify | |
455 | special_rtx in gengenrtl.c as well. */ | |
456 | ||
38e60c55 | 457 | rtx_expr_list * |
ef4bddc2 | 458 | gen_rtx_EXPR_LIST (machine_mode mode, rtx expr, rtx expr_list) |
38e60c55 DM |
459 | { |
460 | return as_a <rtx_expr_list *> (gen_rtx_fmt_ee (EXPR_LIST, mode, expr, | |
461 | expr_list)); | |
462 | } | |
463 | ||
a756c6be | 464 | rtx_insn_list * |
ef4bddc2 | 465 | gen_rtx_INSN_LIST (machine_mode mode, rtx insn, rtx insn_list) |
a756c6be DM |
466 | { |
467 | return as_a <rtx_insn_list *> (gen_rtx_fmt_ue (INSN_LIST, mode, insn, | |
468 | insn_list)); | |
469 | } | |
470 | ||
d6e1e8b8 | 471 | rtx_insn * |
ef4bddc2 | 472 | gen_rtx_INSN (machine_mode mode, rtx_insn *prev_insn, rtx_insn *next_insn, |
d6e1e8b8 DM |
473 | basic_block bb, rtx pattern, int location, int code, |
474 | rtx reg_notes) | |
475 | { | |
476 | return as_a <rtx_insn *> (gen_rtx_fmt_uuBeiie (INSN, mode, | |
477 | prev_insn, next_insn, | |
478 | bb, pattern, location, code, | |
479 | reg_notes)); | |
480 | } | |
481 | ||
3b80f6ca | 482 | rtx |
ef4bddc2 | 483 | gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca RH |
484 | { |
485 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) | |
5da077de | 486 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
487 | |
488 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
489 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
490 | return const_true_rtx; | |
491 | #endif | |
492 | ||
c13e8210 | 493 | /* Look up the CONST_INT in the hash table. */ |
aebf76a2 TS |
494 | rtx *slot = const_int_htab->find_slot_with_hash (arg, (hashval_t) arg, |
495 | INSERT); | |
29105cea | 496 | if (*slot == 0) |
1f8f4a0b | 497 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 | 498 | |
aebf76a2 | 499 | return *slot; |
3b80f6ca RH |
500 | } |
501 | ||
2496c7bd | 502 | rtx |
ef4bddc2 | 503 | gen_int_mode (HOST_WIDE_INT c, machine_mode mode) |
2496c7bd LB |
504 | { |
505 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
506 | } | |
507 | ||
5692c7bc ZW |
508 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
509 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
510 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
511 | ||
512 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
513 | hash table. If so, return its counterpart; otherwise add it | |
514 | to the hash table and return it. */ | |
515 | static rtx | |
502b8322 | 516 | lookup_const_double (rtx real) |
5692c7bc | 517 | { |
aebf76a2 | 518 | rtx *slot = const_double_htab->find_slot (real, INSERT); |
5692c7bc ZW |
519 | if (*slot == 0) |
520 | *slot = real; | |
521 | ||
aebf76a2 | 522 | return *slot; |
5692c7bc | 523 | } |
29105cea | 524 | |
5692c7bc ZW |
525 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
526 | VALUE in mode MODE. */ | |
0133b7d9 | 527 | rtx |
ef4bddc2 | 528 | const_double_from_real_value (REAL_VALUE_TYPE value, machine_mode mode) |
0133b7d9 | 529 | { |
5692c7bc ZW |
530 | rtx real = rtx_alloc (CONST_DOUBLE); |
531 | PUT_MODE (real, mode); | |
532 | ||
9e254451 | 533 | real->u.rv = value; |
5692c7bc ZW |
534 | |
535 | return lookup_const_double (real); | |
536 | } | |
537 | ||
091a3ac7 CF |
538 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
539 | hash table. If so, return its counterpart; otherwise add it | |
540 | to the hash table and return it. */ | |
541 | ||
542 | static rtx | |
543 | lookup_const_fixed (rtx fixed) | |
544 | { | |
aebf76a2 | 545 | rtx *slot = const_fixed_htab->find_slot (fixed, INSERT); |
091a3ac7 CF |
546 | if (*slot == 0) |
547 | *slot = fixed; | |
548 | ||
aebf76a2 | 549 | return *slot; |
091a3ac7 CF |
550 | } |
551 | ||
552 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
553 | VALUE in mode MODE. */ | |
554 | ||
555 | rtx | |
ef4bddc2 | 556 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, machine_mode mode) |
091a3ac7 CF |
557 | { |
558 | rtx fixed = rtx_alloc (CONST_FIXED); | |
559 | PUT_MODE (fixed, mode); | |
560 | ||
561 | fixed->u.fv = value; | |
562 | ||
563 | return lookup_const_fixed (fixed); | |
564 | } | |
565 | ||
807e902e | 566 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
3e93ff81 AS |
567 | /* Constructs double_int from rtx CST. */ |
568 | ||
569 | double_int | |
570 | rtx_to_double_int (const_rtx cst) | |
571 | { | |
572 | double_int r; | |
573 | ||
574 | if (CONST_INT_P (cst)) | |
27bcd47c | 575 | r = double_int::from_shwi (INTVAL (cst)); |
48175537 | 576 | else if (CONST_DOUBLE_AS_INT_P (cst)) |
3e93ff81 AS |
577 | { |
578 | r.low = CONST_DOUBLE_LOW (cst); | |
579 | r.high = CONST_DOUBLE_HIGH (cst); | |
580 | } | |
581 | else | |
582 | gcc_unreachable (); | |
583 | ||
584 | return r; | |
585 | } | |
807e902e | 586 | #endif |
3e93ff81 | 587 | |
807e902e KZ |
588 | #if TARGET_SUPPORTS_WIDE_INT |
589 | /* Determine whether CONST_WIDE_INT WINT already exists in the hash table. | |
590 | If so, return its counterpart; otherwise add it to the hash table and | |
591 | return it. */ | |
3e93ff81 | 592 | |
807e902e KZ |
593 | static rtx |
594 | lookup_const_wide_int (rtx wint) | |
595 | { | |
aebf76a2 | 596 | rtx *slot = const_wide_int_htab->find_slot (wint, INSERT); |
807e902e KZ |
597 | if (*slot == 0) |
598 | *slot = wint; | |
599 | ||
aebf76a2 | 600 | return *slot; |
807e902e KZ |
601 | } |
602 | #endif | |
603 | ||
604 | /* Return an rtx constant for V, given that the constant has mode MODE. | |
605 | The returned rtx will be a CONST_INT if V fits, otherwise it will be | |
606 | a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT | |
607 | (if TARGET_SUPPORTS_WIDE_INT). */ | |
54fb1ae0 AS |
608 | |
609 | rtx | |
ef4bddc2 | 610 | immed_wide_int_const (const wide_int_ref &v, machine_mode mode) |
54fb1ae0 | 611 | { |
807e902e KZ |
612 | unsigned int len = v.get_len (); |
613 | unsigned int prec = GET_MODE_PRECISION (mode); | |
614 | ||
615 | /* Allow truncation but not extension since we do not know if the | |
616 | number is signed or unsigned. */ | |
617 | gcc_assert (prec <= v.get_precision ()); | |
618 | ||
619 | if (len < 2 || prec <= HOST_BITS_PER_WIDE_INT) | |
620 | return gen_int_mode (v.elt (0), mode); | |
621 | ||
622 | #if TARGET_SUPPORTS_WIDE_INT | |
623 | { | |
624 | unsigned int i; | |
625 | rtx value; | |
626 | unsigned int blocks_needed | |
627 | = (prec + HOST_BITS_PER_WIDE_INT - 1) / HOST_BITS_PER_WIDE_INT; | |
628 | ||
629 | if (len > blocks_needed) | |
630 | len = blocks_needed; | |
631 | ||
632 | value = const_wide_int_alloc (len); | |
633 | ||
634 | /* It is so tempting to just put the mode in here. Must control | |
635 | myself ... */ | |
636 | PUT_MODE (value, VOIDmode); | |
637 | CWI_PUT_NUM_ELEM (value, len); | |
638 | ||
639 | for (i = 0; i < len; i++) | |
640 | CONST_WIDE_INT_ELT (value, i) = v.elt (i); | |
641 | ||
642 | return lookup_const_wide_int (value); | |
643 | } | |
644 | #else | |
645 | return immed_double_const (v.elt (0), v.elt (1), mode); | |
646 | #endif | |
54fb1ae0 AS |
647 | } |
648 | ||
807e902e | 649 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
5692c7bc ZW |
650 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
651 | of ints: I0 is the low-order word and I1 is the high-order word. | |
49ab6098 | 652 | For values that are larger than HOST_BITS_PER_DOUBLE_INT, the |
929e10f4 MS |
653 | implied upper bits are copies of the high bit of i1. The value |
654 | itself is neither signed nor unsigned. Do not use this routine for | |
655 | non-integer modes; convert to REAL_VALUE_TYPE and use | |
656 | CONST_DOUBLE_FROM_REAL_VALUE. */ | |
5692c7bc ZW |
657 | |
658 | rtx | |
ef4bddc2 | 659 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, machine_mode mode) |
5692c7bc ZW |
660 | { |
661 | rtx value; | |
662 | unsigned int i; | |
663 | ||
65acccdd | 664 | /* There are the following cases (note that there are no modes with |
49ab6098 | 665 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT): |
65acccdd ZD |
666 | |
667 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
668 | gen_int_mode. | |
929e10f4 MS |
669 | 2) If the value of the integer fits into HOST_WIDE_INT anyway |
670 | (i.e., i1 consists only from copies of the sign bit, and sign | |
671 | of i0 and i1 are the same), then we return a CONST_INT for i0. | |
65acccdd | 672 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ |
5692c7bc ZW |
673 | if (mode != VOIDmode) |
674 | { | |
5b0264cb NS |
675 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
676 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
677 | /* We can get a 0 for an error mark. */ | |
678 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
d5e254e1 IE |
679 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT |
680 | || GET_MODE_CLASS (mode) == MODE_POINTER_BOUNDS); | |
5692c7bc | 681 | |
65acccdd ZD |
682 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
683 | return gen_int_mode (i0, mode); | |
5692c7bc ZW |
684 | } |
685 | ||
686 | /* If this integer fits in one word, return a CONST_INT. */ | |
687 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
688 | return GEN_INT (i0); | |
689 | ||
690 | /* We use VOIDmode for integers. */ | |
691 | value = rtx_alloc (CONST_DOUBLE); | |
692 | PUT_MODE (value, VOIDmode); | |
693 | ||
694 | CONST_DOUBLE_LOW (value) = i0; | |
695 | CONST_DOUBLE_HIGH (value) = i1; | |
696 | ||
697 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
698 | XWINT (value, i) = 0; | |
699 | ||
700 | return lookup_const_double (value); | |
0133b7d9 | 701 | } |
807e902e | 702 | #endif |
0133b7d9 | 703 | |
3b80f6ca | 704 | rtx |
ef4bddc2 | 705 | gen_rtx_REG (machine_mode mode, unsigned int regno) |
3b80f6ca RH |
706 | { |
707 | /* In case the MD file explicitly references the frame pointer, have | |
708 | all such references point to the same frame pointer. This is | |
709 | used during frame pointer elimination to distinguish the explicit | |
710 | references to these registers from pseudos that happened to be | |
711 | assigned to them. | |
712 | ||
713 | If we have eliminated the frame pointer or arg pointer, we will | |
714 | be using it as a normal register, for example as a spill | |
715 | register. In such cases, we might be accessing it in a mode that | |
716 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
717 | ||
718 | Also don't do this when we are making new REGs in reload, since | |
719 | we don't want to get confused with the real pointers. */ | |
720 | ||
55a2c322 | 721 | if (mode == Pmode && !reload_in_progress && !lra_in_progress) |
3b80f6ca | 722 | { |
e10c79fe LB |
723 | if (regno == FRAME_POINTER_REGNUM |
724 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca | 725 | return frame_pointer_rtx; |
c3e08036 TS |
726 | |
727 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER | |
728 | && regno == HARD_FRAME_POINTER_REGNUM | |
e10c79fe | 729 | && (!reload_completed || frame_pointer_needed)) |
3b80f6ca | 730 | return hard_frame_pointer_rtx; |
3f393fc6 TS |
731 | #if !HARD_FRAME_POINTER_IS_ARG_POINTER |
732 | if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
733 | && regno == ARG_POINTER_REGNUM) | |
3b80f6ca RH |
734 | return arg_pointer_rtx; |
735 | #endif | |
736 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 737 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
738 | return return_address_pointer_rtx; |
739 | #endif | |
fc555370 | 740 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
bf9412cd | 741 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM |
2d67bd7b | 742 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 743 | return pic_offset_table_rtx; |
bcb33994 | 744 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
745 | return stack_pointer_rtx; |
746 | } | |
747 | ||
006a94b0 | 748 | #if 0 |
6cde4876 | 749 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
750 | an existing entry in that table to avoid useless generation of RTL. |
751 | ||
752 | This code is disabled for now until we can fix the various backends | |
753 | which depend on having non-shared hard registers in some cases. Long | |
754 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
755 | on the amount of useless RTL that gets generated. |
756 | ||
757 | We'll also need to fix some code that runs after reload that wants to | |
758 | set ORIGINAL_REGNO. */ | |
759 | ||
6cde4876 JL |
760 | if (cfun |
761 | && cfun->emit | |
762 | && regno_reg_rtx | |
763 | && regno < FIRST_PSEUDO_REGISTER | |
764 | && reg_raw_mode[regno] == mode) | |
765 | return regno_reg_rtx[regno]; | |
006a94b0 | 766 | #endif |
6cde4876 | 767 | |
08394eef | 768 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
769 | } |
770 | ||
41472af8 | 771 | rtx |
ef4bddc2 | 772 | gen_rtx_MEM (machine_mode mode, rtx addr) |
41472af8 MM |
773 | { |
774 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
775 | ||
776 | /* This field is not cleared by the mere allocation of the rtx, so | |
777 | we clear it here. */ | |
173b24b9 | 778 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
779 | |
780 | return rt; | |
781 | } | |
ddef6bc7 | 782 | |
542a8afa RH |
783 | /* Generate a memory referring to non-trapping constant memory. */ |
784 | ||
785 | rtx | |
ef4bddc2 | 786 | gen_const_mem (machine_mode mode, rtx addr) |
542a8afa RH |
787 | { |
788 | rtx mem = gen_rtx_MEM (mode, addr); | |
789 | MEM_READONLY_P (mem) = 1; | |
790 | MEM_NOTRAP_P (mem) = 1; | |
791 | return mem; | |
792 | } | |
793 | ||
bf877a76 R |
794 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
795 | save areas. */ | |
796 | ||
797 | rtx | |
ef4bddc2 | 798 | gen_frame_mem (machine_mode mode, rtx addr) |
bf877a76 R |
799 | { |
800 | rtx mem = gen_rtx_MEM (mode, addr); | |
801 | MEM_NOTRAP_P (mem) = 1; | |
802 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
803 | return mem; | |
804 | } | |
805 | ||
806 | /* Generate a MEM referring to a temporary use of the stack, not part | |
807 | of the fixed stack frame. For example, something which is pushed | |
808 | by a target splitter. */ | |
809 | rtx | |
ef4bddc2 | 810 | gen_tmp_stack_mem (machine_mode mode, rtx addr) |
bf877a76 R |
811 | { |
812 | rtx mem = gen_rtx_MEM (mode, addr); | |
813 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 814 | if (!cfun->calls_alloca) |
bf877a76 R |
815 | set_mem_alias_set (mem, get_frame_alias_set ()); |
816 | return mem; | |
817 | } | |
818 | ||
beb72684 RH |
819 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
820 | this construct would be valid, and false otherwise. */ | |
821 | ||
822 | bool | |
ef4bddc2 | 823 | validate_subreg (machine_mode omode, machine_mode imode, |
ed7a4b4b | 824 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 825 | { |
beb72684 RH |
826 | unsigned int isize = GET_MODE_SIZE (imode); |
827 | unsigned int osize = GET_MODE_SIZE (omode); | |
828 | ||
829 | /* All subregs must be aligned. */ | |
830 | if (offset % osize != 0) | |
831 | return false; | |
832 | ||
833 | /* The subreg offset cannot be outside the inner object. */ | |
834 | if (offset >= isize) | |
835 | return false; | |
836 | ||
837 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
838 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
839 | Generally, backends are doing something sketchy but it'll take time to | |
840 | fix them all. */ | |
841 | if (omode == word_mode) | |
842 | ; | |
843 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
844 | is the culprit here, and not the backends. */ | |
845 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
846 | ; | |
847 | /* Allow component subregs of complex and vector. Though given the below | |
848 | extraction rules, it's not always clear what that means. */ | |
849 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
850 | && GET_MODE_INNER (imode) == omode) | |
851 | ; | |
852 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
853 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
854 | represent this. It's questionable if this ought to be represented at | |
855 | all -- why can't this all be hidden in post-reload splitters that make | |
856 | arbitrarily mode changes to the registers themselves. */ | |
857 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
858 | ; | |
859 | /* Subregs involving floating point modes are not allowed to | |
860 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
861 | (subreg:SI (reg:DF) 0) isn't. */ | |
862 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
863 | { | |
55a2c322 VM |
864 | if (! (isize == osize |
865 | /* LRA can use subreg to store a floating point value in | |
866 | an integer mode. Although the floating point and the | |
867 | integer modes need the same number of hard registers, | |
868 | the size of floating point mode can be less than the | |
869 | integer mode. LRA also uses subregs for a register | |
870 | should be used in different mode in on insn. */ | |
871 | || lra_in_progress)) | |
beb72684 RH |
872 | return false; |
873 | } | |
ddef6bc7 | 874 | |
beb72684 RH |
875 | /* Paradoxical subregs must have offset zero. */ |
876 | if (osize > isize) | |
877 | return offset == 0; | |
878 | ||
879 | /* This is a normal subreg. Verify that the offset is representable. */ | |
880 | ||
881 | /* For hard registers, we already have most of these rules collected in | |
882 | subreg_offset_representable_p. */ | |
883 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
884 | { | |
885 | unsigned int regno = REGNO (reg); | |
886 | ||
887 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
888 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
889 | && GET_MODE_INNER (imode) == omode) | |
890 | ; | |
891 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
892 | return false; | |
ddef6bc7 | 893 | #endif |
beb72684 RH |
894 | |
895 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
896 | } | |
897 | ||
898 | /* For pseudo registers, we want most of the same checks. Namely: | |
899 | If the register no larger than a word, the subreg must be lowpart. | |
900 | If the register is larger than a word, the subreg must be the lowpart | |
901 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
902 | Given that we've already checked mode/offset alignment, we only have | |
903 | to check subword subregs here. */ | |
55a2c322 VM |
904 | if (osize < UNITS_PER_WORD |
905 | && ! (lra_in_progress && (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)))) | |
beb72684 | 906 | { |
ef4bddc2 | 907 | machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; |
beb72684 RH |
908 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); |
909 | if (offset % UNITS_PER_WORD != low_off) | |
910 | return false; | |
911 | } | |
912 | return true; | |
913 | } | |
914 | ||
915 | rtx | |
ef4bddc2 | 916 | gen_rtx_SUBREG (machine_mode mode, rtx reg, int offset) |
beb72684 RH |
917 | { |
918 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 919 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
920 | } |
921 | ||
173b24b9 RK |
922 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
923 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
924 | ||
ddef6bc7 | 925 | rtx |
ef4bddc2 | 926 | gen_lowpart_SUBREG (machine_mode mode, rtx reg) |
ddef6bc7 | 927 | { |
ef4bddc2 | 928 | machine_mode inmode; |
ddef6bc7 JJ |
929 | |
930 | inmode = GET_MODE (reg); | |
931 | if (inmode == VOIDmode) | |
932 | inmode = mode; | |
e0e08ac2 JH |
933 | return gen_rtx_SUBREG (mode, reg, |
934 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 935 | } |
fcc74520 RS |
936 | |
937 | rtx | |
ef4bddc2 | 938 | gen_rtx_VAR_LOCATION (machine_mode mode, tree decl, rtx loc, |
fcc74520 RS |
939 | enum var_init_status status) |
940 | { | |
941 | rtx x = gen_rtx_fmt_te (VAR_LOCATION, mode, decl, loc); | |
942 | PAT_VAR_LOCATION_STATUS (x) = status; | |
943 | return x; | |
944 | } | |
c5c76735 | 945 | \f |
23b2ce53 | 946 | |
80379f51 PB |
947 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
948 | ||
23b2ce53 | 949 | rtvec |
e34d07f2 | 950 | gen_rtvec (int n, ...) |
23b2ce53 | 951 | { |
80379f51 PB |
952 | int i; |
953 | rtvec rt_val; | |
e34d07f2 | 954 | va_list p; |
23b2ce53 | 955 | |
e34d07f2 | 956 | va_start (p, n); |
23b2ce53 | 957 | |
80379f51 | 958 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 959 | if (n == 0) |
0edf1bb2 JL |
960 | { |
961 | va_end (p); | |
962 | return NULL_RTVEC; | |
963 | } | |
23b2ce53 | 964 | |
80379f51 | 965 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 966 | |
23b2ce53 | 967 | for (i = 0; i < n; i++) |
80379f51 | 968 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 969 | |
e34d07f2 | 970 | va_end (p); |
80379f51 | 971 | return rt_val; |
23b2ce53 RS |
972 | } |
973 | ||
974 | rtvec | |
502b8322 | 975 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 976 | { |
b3694847 SS |
977 | int i; |
978 | rtvec rt_val; | |
23b2ce53 | 979 | |
80379f51 | 980 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 981 | if (n == 0) |
80379f51 | 982 | return NULL_RTVEC; |
23b2ce53 | 983 | |
80379f51 | 984 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
985 | |
986 | for (i = 0; i < n; i++) | |
8f985ec4 | 987 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
988 | |
989 | return rt_val; | |
990 | } | |
e6eda746 DM |
991 | |
992 | rtvec | |
993 | gen_rtvec_v (int n, rtx_insn **argp) | |
994 | { | |
995 | int i; | |
996 | rtvec rt_val; | |
997 | ||
998 | /* Don't allocate an empty rtvec... */ | |
999 | if (n == 0) | |
1000 | return NULL_RTVEC; | |
1001 | ||
1002 | rt_val = rtvec_alloc (n); | |
1003 | ||
1004 | for (i = 0; i < n; i++) | |
1005 | rt_val->elem[i] = *argp++; | |
1006 | ||
1007 | return rt_val; | |
1008 | } | |
1009 | ||
23b2ce53 | 1010 | \f |
38ae7651 RS |
1011 | /* Return the number of bytes between the start of an OUTER_MODE |
1012 | in-memory value and the start of an INNER_MODE in-memory value, | |
1013 | given that the former is a lowpart of the latter. It may be a | |
1014 | paradoxical lowpart, in which case the offset will be negative | |
1015 | on big-endian targets. */ | |
1016 | ||
1017 | int | |
ef4bddc2 RS |
1018 | byte_lowpart_offset (machine_mode outer_mode, |
1019 | machine_mode inner_mode) | |
38ae7651 RS |
1020 | { |
1021 | if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)) | |
1022 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
1023 | else | |
1024 | return -subreg_lowpart_offset (inner_mode, outer_mode); | |
1025 | } | |
1026 | \f | |
23b2ce53 RS |
1027 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
1028 | This pseudo is assigned the next sequential register number. */ | |
1029 | ||
1030 | rtx | |
ef4bddc2 | 1031 | gen_reg_rtx (machine_mode mode) |
23b2ce53 | 1032 | { |
b3694847 | 1033 | rtx val; |
2e3f842f | 1034 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 1035 | |
f8335a4f | 1036 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 1037 | |
2e3f842f L |
1038 | /* If a virtual register with bigger mode alignment is generated, |
1039 | increase stack alignment estimation because it might be spilled | |
1040 | to stack later. */ | |
b8698a0f | 1041 | if (SUPPORTS_STACK_ALIGNMENT |
2e3f842f L |
1042 | && crtl->stack_alignment_estimated < align |
1043 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
1044 | { |
1045 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
1046 | if (crtl->stack_alignment_estimated < min_align) | |
1047 | crtl->stack_alignment_estimated = min_align; | |
1048 | } | |
2e3f842f | 1049 | |
1b3d8f8a GK |
1050 | if (generating_concat_p |
1051 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
1052 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
1053 | { |
1054 | /* For complex modes, don't make a single pseudo. | |
1055 | Instead, make a CONCAT of two pseudos. | |
1056 | This allows noncontiguous allocation of the real and imaginary parts, | |
1057 | which makes much better code. Besides, allocating DCmode | |
1058 | pseudos overstrains reload on some machines like the 386. */ | |
1059 | rtx realpart, imagpart; | |
ef4bddc2 | 1060 | machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
1061 | |
1062 | realpart = gen_reg_rtx (partmode); | |
1063 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 1064 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
1065 | } |
1066 | ||
004a7e45 UB |
1067 | /* Do not call gen_reg_rtx with uninitialized crtl. */ |
1068 | gcc_assert (crtl->emit.regno_pointer_align_length); | |
1069 | ||
a560d4d4 | 1070 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 1071 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 1072 | |
3e029763 | 1073 | if (reg_rtx_no == crtl->emit.regno_pointer_align_length) |
23b2ce53 | 1074 | { |
3e029763 | 1075 | int old_size = crtl->emit.regno_pointer_align_length; |
60564289 | 1076 | char *tmp; |
0d4903b8 | 1077 | rtx *new1; |
0d4903b8 | 1078 | |
60564289 KG |
1079 | tmp = XRESIZEVEC (char, crtl->emit.regno_pointer_align, old_size * 2); |
1080 | memset (tmp + old_size, 0, old_size); | |
1081 | crtl->emit.regno_pointer_align = (unsigned char *) tmp; | |
49ad7cfa | 1082 | |
1b4572a8 | 1083 | new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, old_size * 2); |
49ad7cfa | 1084 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
1085 | regno_reg_rtx = new1; |
1086 | ||
3e029763 | 1087 | crtl->emit.regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
1088 | } |
1089 | ||
08394eef | 1090 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
1091 | regno_reg_rtx[reg_rtx_no++] = val; |
1092 | return val; | |
1093 | } | |
1094 | ||
a698cc03 JL |
1095 | /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */ |
1096 | ||
1097 | bool | |
1098 | reg_is_parm_p (rtx reg) | |
1099 | { | |
1100 | tree decl; | |
1101 | ||
1102 | gcc_assert (REG_P (reg)); | |
1103 | decl = REG_EXPR (reg); | |
1104 | return (decl && TREE_CODE (decl) == PARM_DECL); | |
1105 | } | |
1106 | ||
38ae7651 RS |
1107 | /* Update NEW with the same attributes as REG, but with OFFSET added |
1108 | to the REG_OFFSET. */ | |
a560d4d4 | 1109 | |
e53a16e7 | 1110 | static void |
60564289 | 1111 | update_reg_offset (rtx new_rtx, rtx reg, int offset) |
a560d4d4 | 1112 | { |
60564289 | 1113 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 1114 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
1115 | } |
1116 | ||
38ae7651 RS |
1117 | /* Generate a register with same attributes as REG, but with OFFSET |
1118 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
1119 | |
1120 | rtx | |
ef4bddc2 | 1121 | gen_rtx_REG_offset (rtx reg, machine_mode mode, unsigned int regno, |
e53a16e7 ILT |
1122 | int offset) |
1123 | { | |
60564289 | 1124 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 1125 | |
60564289 KG |
1126 | update_reg_offset (new_rtx, reg, offset); |
1127 | return new_rtx; | |
e53a16e7 ILT |
1128 | } |
1129 | ||
1130 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 1131 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
1132 | |
1133 | rtx | |
ef4bddc2 | 1134 | gen_reg_rtx_offset (rtx reg, machine_mode mode, int offset) |
e53a16e7 | 1135 | { |
60564289 | 1136 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 1137 | |
60564289 KG |
1138 | update_reg_offset (new_rtx, reg, offset); |
1139 | return new_rtx; | |
a560d4d4 JH |
1140 | } |
1141 | ||
38ae7651 RS |
1142 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
1143 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
1144 | |
1145 | void | |
ef4bddc2 | 1146 | adjust_reg_mode (rtx reg, machine_mode mode) |
a560d4d4 | 1147 | { |
38ae7651 RS |
1148 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
1149 | PUT_MODE (reg, mode); | |
1150 | } | |
1151 | ||
1152 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
1153 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
1154 | ||
1155 | void | |
1156 | set_reg_attrs_from_value (rtx reg, rtx x) | |
1157 | { | |
1158 | int offset; | |
de6f3f7a L |
1159 | bool can_be_reg_pointer = true; |
1160 | ||
1161 | /* Don't call mark_reg_pointer for incompatible pointer sign | |
1162 | extension. */ | |
1163 | while (GET_CODE (x) == SIGN_EXTEND | |
1164 | || GET_CODE (x) == ZERO_EXTEND | |
1165 | || GET_CODE (x) == TRUNCATE | |
1166 | || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x))) | |
1167 | { | |
1168 | #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) | |
1169 | if ((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED) | |
1170 | || (GET_CODE (x) != SIGN_EXTEND && ! POINTERS_EXTEND_UNSIGNED)) | |
1171 | can_be_reg_pointer = false; | |
1172 | #endif | |
1173 | x = XEXP (x, 0); | |
1174 | } | |
38ae7651 | 1175 | |
923ba36f JJ |
1176 | /* Hard registers can be reused for multiple purposes within the same |
1177 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
1178 | on them is wrong. */ | |
1179 | if (HARD_REGISTER_P (reg)) | |
1180 | return; | |
1181 | ||
38ae7651 | 1182 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
1183 | if (MEM_P (x)) |
1184 | { | |
527210c4 RS |
1185 | if (MEM_OFFSET_KNOWN_P (x)) |
1186 | REG_ATTRS (reg) = get_reg_attrs (MEM_EXPR (x), | |
1187 | MEM_OFFSET (x) + offset); | |
de6f3f7a | 1188 | if (can_be_reg_pointer && MEM_POINTER (x)) |
0a317111 | 1189 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
1190 | } |
1191 | else if (REG_P (x)) | |
1192 | { | |
1193 | if (REG_ATTRS (x)) | |
1194 | update_reg_offset (reg, x, offset); | |
de6f3f7a | 1195 | if (can_be_reg_pointer && REG_POINTER (x)) |
46b71b03 PB |
1196 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); |
1197 | } | |
1198 | } | |
1199 | ||
1200 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
1201 | and attributes from X. */ | |
1202 | ||
1203 | rtx | |
1204 | gen_reg_rtx_and_attrs (rtx x) | |
1205 | { | |
1206 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1207 | set_reg_attrs_from_value (reg, x); | |
1208 | return reg; | |
a560d4d4 JH |
1209 | } |
1210 | ||
9d18e06b JZ |
1211 | /* Set the register attributes for registers contained in PARM_RTX. |
1212 | Use needed values from memory attributes of MEM. */ | |
1213 | ||
1214 | void | |
502b8322 | 1215 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1216 | { |
f8cfc6aa | 1217 | if (REG_P (parm_rtx)) |
38ae7651 | 1218 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1219 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1220 | { | |
1221 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1222 | parameter goes both on the stack and in registers. */ | |
1223 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1224 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1225 | { | |
1226 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1227 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1228 | REG_ATTRS (XEXP (x, 0)) |
1229 | = get_reg_attrs (MEM_EXPR (mem), | |
1230 | INTVAL (XEXP (x, 1))); | |
1231 | } | |
1232 | } | |
1233 | } | |
1234 | ||
38ae7651 RS |
1235 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1236 | decl T. */ | |
a560d4d4 | 1237 | |
4e3825db | 1238 | void |
38ae7651 RS |
1239 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1240 | { | |
1241 | if (GET_CODE (x) == SUBREG) | |
fbe6ec81 | 1242 | { |
38ae7651 RS |
1243 | gcc_assert (subreg_lowpart_p (x)); |
1244 | x = SUBREG_REG (x); | |
fbe6ec81 | 1245 | } |
f8cfc6aa | 1246 | if (REG_P (x)) |
38ae7651 RS |
1247 | REG_ATTRS (x) |
1248 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
0f9f9784 | 1249 | DECL_MODE (t))); |
a560d4d4 JH |
1250 | if (GET_CODE (x) == CONCAT) |
1251 | { | |
1252 | if (REG_P (XEXP (x, 0))) | |
1253 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1254 | if (REG_P (XEXP (x, 1))) | |
1255 | REG_ATTRS (XEXP (x, 1)) | |
1256 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1257 | } | |
1258 | if (GET_CODE (x) == PARALLEL) | |
1259 | { | |
d4afac5b JZ |
1260 | int i, start; |
1261 | ||
1262 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1263 | both on the stack and in registers. */ | |
1264 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1265 | start = 0; | |
1266 | else | |
1267 | start = 1; | |
1268 | ||
1269 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1270 | { |
1271 | rtx y = XVECEXP (x, 0, i); | |
1272 | if (REG_P (XEXP (y, 0))) | |
1273 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1274 | } | |
1275 | } | |
1276 | } | |
1277 | ||
38ae7651 RS |
1278 | /* Assign the RTX X to declaration T. */ |
1279 | ||
1280 | void | |
1281 | set_decl_rtl (tree t, rtx x) | |
1282 | { | |
1283 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1284 | if (x) | |
1285 | set_reg_attrs_for_decl_rtl (t, x); | |
1286 | } | |
1287 | ||
5141868d RS |
1288 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1289 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1290 | |
1291 | void | |
5141868d | 1292 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1293 | { |
1294 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1295 | if (x && !by_reference_p) |
38ae7651 RS |
1296 | set_reg_attrs_for_decl_rtl (t, x); |
1297 | } | |
1298 | ||
754fdcca RK |
1299 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1300 | ||
1301 | void | |
502b8322 | 1302 | mark_user_reg (rtx reg) |
754fdcca RK |
1303 | { |
1304 | if (GET_CODE (reg) == CONCAT) | |
1305 | { | |
1306 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1307 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1308 | } | |
754fdcca | 1309 | else |
5b0264cb NS |
1310 | { |
1311 | gcc_assert (REG_P (reg)); | |
1312 | REG_USERVAR_P (reg) = 1; | |
1313 | } | |
754fdcca RK |
1314 | } |
1315 | ||
86fe05e0 RK |
1316 | /* Identify REG as a probable pointer register and show its alignment |
1317 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1318 | |
1319 | void | |
502b8322 | 1320 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1321 | { |
3502dc9c | 1322 | if (! REG_POINTER (reg)) |
00995e78 | 1323 | { |
3502dc9c | 1324 | REG_POINTER (reg) = 1; |
86fe05e0 | 1325 | |
00995e78 RE |
1326 | if (align) |
1327 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1328 | } | |
1329 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1330 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1331 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1332 | } |
1333 | ||
1334 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1335 | ||
1336 | int | |
502b8322 | 1337 | max_reg_num (void) |
23b2ce53 RS |
1338 | { |
1339 | return reg_rtx_no; | |
1340 | } | |
1341 | ||
1342 | /* Return 1 + the largest label number used so far in the current function. */ | |
1343 | ||
1344 | int | |
502b8322 | 1345 | max_label_num (void) |
23b2ce53 | 1346 | { |
23b2ce53 RS |
1347 | return label_num; |
1348 | } | |
1349 | ||
1350 | /* Return first label number used in this function (if any were used). */ | |
1351 | ||
1352 | int | |
502b8322 | 1353 | get_first_label_num (void) |
23b2ce53 RS |
1354 | { |
1355 | return first_label_num; | |
1356 | } | |
6de9cd9a DN |
1357 | |
1358 | /* If the rtx for label was created during the expansion of a nested | |
1359 | function, then first_label_num won't include this label number. | |
fa10beec | 1360 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1361 | |
1362 | void | |
1363 | maybe_set_first_label_num (rtx x) | |
1364 | { | |
1365 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1366 | first_label_num = CODE_LABEL_NUMBER (x); | |
1367 | } | |
23b2ce53 RS |
1368 | \f |
1369 | /* Return a value representing some low-order bits of X, where the number | |
1370 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1371 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1372 | representation is returned. |
1373 | ||
1374 | This function handles the cases in common between gen_lowpart, below, | |
1375 | and two variants in cse.c and combine.c. These are the cases that can | |
1376 | be safely handled at all points in the compilation. | |
1377 | ||
1378 | If this is not a case we can handle, return 0. */ | |
1379 | ||
1380 | rtx | |
ef4bddc2 | 1381 | gen_lowpart_common (machine_mode mode, rtx x) |
23b2ce53 | 1382 | { |
ddef6bc7 | 1383 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1384 | int xsize; |
ddef6bc7 | 1385 | int offset = 0; |
ef4bddc2 | 1386 | machine_mode innermode; |
550d1387 GK |
1387 | |
1388 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1389 | so we have to make one up. Yuk. */ | |
1390 | innermode = GET_MODE (x); | |
481683e1 | 1391 | if (CONST_INT_P (x) |
db487452 | 1392 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) |
550d1387 GK |
1393 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1394 | else if (innermode == VOIDmode) | |
49ab6098 | 1395 | innermode = mode_for_size (HOST_BITS_PER_DOUBLE_INT, MODE_INT, 0); |
b8698a0f | 1396 | |
550d1387 GK |
1397 | xsize = GET_MODE_SIZE (innermode); |
1398 | ||
5b0264cb | 1399 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1400 | |
550d1387 | 1401 | if (innermode == mode) |
23b2ce53 RS |
1402 | return x; |
1403 | ||
1404 | /* MODE must occupy no more words than the mode of X. */ | |
550d1387 GK |
1405 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1406 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
23b2ce53 RS |
1407 | return 0; |
1408 | ||
53501a19 | 1409 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
3d8bf70f | 1410 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
53501a19 BS |
1411 | return 0; |
1412 | ||
550d1387 | 1413 | offset = subreg_lowpart_offset (mode, innermode); |
23b2ce53 RS |
1414 | |
1415 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1416 | && (GET_MODE_CLASS (mode) == MODE_INT |
1417 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1418 | { |
1419 | /* If we are getting the low-order part of something that has been | |
1420 | sign- or zero-extended, we can either just use the object being | |
1421 | extended or make a narrower extension. If we want an even smaller | |
1422 | piece than the size of the object being extended, call ourselves | |
1423 | recursively. | |
1424 | ||
1425 | This case is used mostly by combine and cse. */ | |
1426 | ||
1427 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1428 | return XEXP (x, 0); | |
550d1387 | 1429 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
23b2ce53 | 1430 | return gen_lowpart_common (mode, XEXP (x, 0)); |
550d1387 | 1431 | else if (msize < xsize) |
3b80f6ca | 1432 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1433 | } |
f8cfc6aa | 1434 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
550d1387 | 1435 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
33ffb5c5 | 1436 | || CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)) |
550d1387 | 1437 | return simplify_gen_subreg (mode, x, innermode, offset); |
8aada4ad | 1438 | |
23b2ce53 RS |
1439 | /* Otherwise, we can't do this. */ |
1440 | return 0; | |
1441 | } | |
1442 | \f | |
ccba022b | 1443 | rtx |
ef4bddc2 | 1444 | gen_highpart (machine_mode mode, rtx x) |
ccba022b | 1445 | { |
ddef6bc7 | 1446 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1447 | rtx result; |
ddef6bc7 | 1448 | |
ccba022b RS |
1449 | /* This case loses if X is a subreg. To catch bugs early, |
1450 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1451 | gcc_assert (msize <= UNITS_PER_WORD |
1452 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1453 | |
e0e08ac2 JH |
1454 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1455 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb | 1456 | gcc_assert (result); |
b8698a0f | 1457 | |
09482e0d JW |
1458 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1459 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1460 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1461 | if (MEM_P (result)) |
1462 | { | |
1463 | result = validize_mem (result); | |
1464 | gcc_assert (result); | |
1465 | } | |
b8698a0f | 1466 | |
e0e08ac2 JH |
1467 | return result; |
1468 | } | |
5222e470 | 1469 | |
26d249eb | 1470 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1471 | be VOIDmode constant. */ |
1472 | rtx | |
ef4bddc2 | 1473 | gen_highpart_mode (machine_mode outermode, machine_mode innermode, rtx exp) |
5222e470 JH |
1474 | { |
1475 | if (GET_MODE (exp) != VOIDmode) | |
1476 | { | |
5b0264cb | 1477 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1478 | return gen_highpart (outermode, exp); |
1479 | } | |
1480 | return simplify_gen_subreg (outermode, exp, innermode, | |
1481 | subreg_highpart_offset (outermode, innermode)); | |
1482 | } | |
68252e27 | 1483 | |
38ae7651 | 1484 | /* Return the SUBREG_BYTE for an OUTERMODE lowpart of an INNERMODE value. */ |
8698cce3 | 1485 | |
e0e08ac2 | 1486 | unsigned int |
ef4bddc2 | 1487 | subreg_lowpart_offset (machine_mode outermode, machine_mode innermode) |
e0e08ac2 JH |
1488 | { |
1489 | unsigned int offset = 0; | |
1490 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1491 | |
e0e08ac2 | 1492 | if (difference > 0) |
ccba022b | 1493 | { |
e0e08ac2 JH |
1494 | if (WORDS_BIG_ENDIAN) |
1495 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1496 | if (BYTES_BIG_ENDIAN) | |
1497 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1498 | } |
ddef6bc7 | 1499 | |
e0e08ac2 | 1500 | return offset; |
ccba022b | 1501 | } |
eea50aa0 | 1502 | |
e0e08ac2 JH |
1503 | /* Return offset in bytes to get OUTERMODE high part |
1504 | of the value in mode INNERMODE stored in memory in target format. */ | |
1505 | unsigned int | |
ef4bddc2 | 1506 | subreg_highpart_offset (machine_mode outermode, machine_mode innermode) |
eea50aa0 JH |
1507 | { |
1508 | unsigned int offset = 0; | |
1509 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1510 | ||
5b0264cb | 1511 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
e0e08ac2 | 1512 | |
eea50aa0 JH |
1513 | if (difference > 0) |
1514 | { | |
e0e08ac2 | 1515 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1516 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1517 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1518 | offset += difference % UNITS_PER_WORD; |
1519 | } | |
1520 | ||
e0e08ac2 | 1521 | return offset; |
eea50aa0 | 1522 | } |
ccba022b | 1523 | |
23b2ce53 RS |
1524 | /* Return 1 iff X, assumed to be a SUBREG, |
1525 | refers to the least significant part of its containing reg. | |
1526 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1527 | ||
1528 | int | |
fa233e34 | 1529 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1530 | { |
1531 | if (GET_CODE (x) != SUBREG) | |
1532 | return 1; | |
a3a03040 RK |
1533 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1534 | return 0; | |
23b2ce53 | 1535 | |
e0e08ac2 JH |
1536 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1537 | == SUBREG_BYTE (x)); | |
23b2ce53 | 1538 | } |
6a4bdc79 BS |
1539 | |
1540 | /* Return true if X is a paradoxical subreg, false otherwise. */ | |
1541 | bool | |
1542 | paradoxical_subreg_p (const_rtx x) | |
1543 | { | |
1544 | if (GET_CODE (x) != SUBREG) | |
1545 | return false; | |
1546 | return (GET_MODE_PRECISION (GET_MODE (x)) | |
1547 | > GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x)))); | |
1548 | } | |
23b2ce53 | 1549 | \f |
ddef6bc7 JJ |
1550 | /* Return subword OFFSET of operand OP. |
1551 | The word number, OFFSET, is interpreted as the word number starting | |
1552 | at the low-order address. OFFSET 0 is the low-order word if not | |
1553 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1554 | ||
1555 | If we cannot extract the required word, we return zero. Otherwise, | |
1556 | an rtx corresponding to the requested word will be returned. | |
1557 | ||
1558 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1559 | reload has completed, a valid address will always be returned. After | |
1560 | reload, if a valid address cannot be returned, we return zero. | |
1561 | ||
1562 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1563 | it is the responsibility of the caller. | |
1564 | ||
1565 | MODE is the mode of OP in case it is a CONST_INT. | |
1566 | ||
1567 | ??? This is still rather broken for some cases. The problem for the | |
1568 | moment is that all callers of this thing provide no 'goal mode' to | |
1569 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1570 | in a word based SUBREG world. |
1571 | Now use of this function can be deprecated by simplify_subreg in most | |
1572 | cases. | |
1573 | */ | |
ddef6bc7 JJ |
1574 | |
1575 | rtx | |
ef4bddc2 | 1576 | operand_subword (rtx op, unsigned int offset, int validate_address, machine_mode mode) |
ddef6bc7 JJ |
1577 | { |
1578 | if (mode == VOIDmode) | |
1579 | mode = GET_MODE (op); | |
1580 | ||
5b0264cb | 1581 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1582 | |
30f7a378 | 1583 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1584 | if (mode != BLKmode |
1585 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1586 | return 0; | |
1587 | ||
30f7a378 | 1588 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1589 | if (mode != BLKmode |
1590 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1591 | return const0_rtx; | |
1592 | ||
ddef6bc7 | 1593 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1594 | if (MEM_P (op)) |
ddef6bc7 | 1595 | { |
60564289 | 1596 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1597 | |
f1ec5147 | 1598 | if (! validate_address) |
60564289 | 1599 | return new_rtx; |
f1ec5147 RK |
1600 | |
1601 | else if (reload_completed) | |
ddef6bc7 | 1602 | { |
09e881c9 BE |
1603 | if (! strict_memory_address_addr_space_p (word_mode, |
1604 | XEXP (new_rtx, 0), | |
1605 | MEM_ADDR_SPACE (op))) | |
f1ec5147 | 1606 | return 0; |
ddef6bc7 | 1607 | } |
f1ec5147 | 1608 | else |
60564289 | 1609 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1610 | } |
1611 | ||
0631e0bf JH |
1612 | /* Rest can be handled by simplify_subreg. */ |
1613 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1614 | } |
1615 | ||
535a42b1 NS |
1616 | /* Similar to `operand_subword', but never return 0. If we can't |
1617 | extract the required subword, put OP into a register and try again. | |
1618 | The second attempt must succeed. We always validate the address in | |
1619 | this case. | |
23b2ce53 RS |
1620 | |
1621 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1622 | ||
1623 | rtx | |
ef4bddc2 | 1624 | operand_subword_force (rtx op, unsigned int offset, machine_mode mode) |
23b2ce53 | 1625 | { |
ddef6bc7 | 1626 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1627 | |
1628 | if (result) | |
1629 | return result; | |
1630 | ||
1631 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1632 | { |
1633 | /* If this is a register which can not be accessed by words, copy it | |
1634 | to a pseudo register. */ | |
f8cfc6aa | 1635 | if (REG_P (op)) |
77e6b0eb JC |
1636 | op = copy_to_reg (op); |
1637 | else | |
1638 | op = force_reg (mode, op); | |
1639 | } | |
23b2ce53 | 1640 | |
ddef6bc7 | 1641 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1642 | gcc_assert (result); |
23b2ce53 RS |
1643 | |
1644 | return result; | |
1645 | } | |
1646 | \f | |
2b3493c8 AK |
1647 | /* Returns 1 if both MEM_EXPR can be considered equal |
1648 | and 0 otherwise. */ | |
1649 | ||
1650 | int | |
4f588890 | 1651 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1652 | { |
1653 | if (expr1 == expr2) | |
1654 | return 1; | |
1655 | ||
1656 | if (! expr1 || ! expr2) | |
1657 | return 0; | |
1658 | ||
1659 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1660 | return 0; | |
1661 | ||
55b34b5f | 1662 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1663 | } |
1664 | ||
805903b5 JJ |
1665 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1666 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1667 | -1 if not known. */ | |
1668 | ||
1669 | int | |
d9223014 | 1670 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1671 | { |
1672 | tree expr; | |
1673 | unsigned HOST_WIDE_INT offset; | |
1674 | ||
1675 | /* This function can't use | |
527210c4 | 1676 | if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem) |
e80c2726 | 1677 | || (MAX (MEM_ALIGN (mem), |
0eb77834 | 1678 | MAX (align, get_object_alignment (MEM_EXPR (mem)))) |
805903b5 JJ |
1679 | < align)) |
1680 | return -1; | |
1681 | else | |
527210c4 | 1682 | return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1); |
805903b5 JJ |
1683 | for two reasons: |
1684 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1685 | for <variable>. get_inner_reference doesn't handle it and | |
1686 | even if it did, the alignment in that case needs to be determined | |
1687 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1688 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1689 | isn't sufficiently aligned, the object it is in might be. */ | |
1690 | gcc_assert (MEM_P (mem)); | |
1691 | expr = MEM_EXPR (mem); | |
527210c4 | 1692 | if (expr == NULL_TREE || !MEM_OFFSET_KNOWN_P (mem)) |
805903b5 JJ |
1693 | return -1; |
1694 | ||
527210c4 | 1695 | offset = MEM_OFFSET (mem); |
805903b5 JJ |
1696 | if (DECL_P (expr)) |
1697 | { | |
1698 | if (DECL_ALIGN (expr) < align) | |
1699 | return -1; | |
1700 | } | |
1701 | else if (INDIRECT_REF_P (expr)) | |
1702 | { | |
1703 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1704 | return -1; | |
1705 | } | |
1706 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1707 | { | |
1708 | while (1) | |
1709 | { | |
1710 | tree inner = TREE_OPERAND (expr, 0); | |
1711 | tree field = TREE_OPERAND (expr, 1); | |
1712 | tree byte_offset = component_ref_field_offset (expr); | |
1713 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1714 | ||
1715 | if (!byte_offset | |
cc269bb6 RS |
1716 | || !tree_fits_uhwi_p (byte_offset) |
1717 | || !tree_fits_uhwi_p (bit_offset)) | |
805903b5 JJ |
1718 | return -1; |
1719 | ||
ae7e9ddd RS |
1720 | offset += tree_to_uhwi (byte_offset); |
1721 | offset += tree_to_uhwi (bit_offset) / BITS_PER_UNIT; | |
805903b5 JJ |
1722 | |
1723 | if (inner == NULL_TREE) | |
1724 | { | |
1725 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1726 | < (unsigned int) align) | |
1727 | return -1; | |
1728 | break; | |
1729 | } | |
1730 | else if (DECL_P (inner)) | |
1731 | { | |
1732 | if (DECL_ALIGN (inner) < align) | |
1733 | return -1; | |
1734 | break; | |
1735 | } | |
1736 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1737 | return -1; | |
1738 | expr = inner; | |
1739 | } | |
1740 | } | |
1741 | else | |
1742 | return -1; | |
1743 | ||
1744 | return offset & ((align / BITS_PER_UNIT) - 1); | |
1745 | } | |
1746 | ||
6926c713 | 1747 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1748 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1749 | if we are making a new object of this type. BITPOS is nonzero if |
1750 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1751 | |
1752 | void | |
502b8322 AJ |
1753 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1754 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1755 | { |
6f1087be | 1756 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 | 1757 | tree type; |
f12144dd | 1758 | struct mem_attrs attrs, *defattrs, *refattrs; |
f18a7b25 | 1759 | addr_space_t as; |
173b24b9 RK |
1760 | |
1761 | /* It can happen that type_for_mode was given a mode for which there | |
1762 | is no language-level type. In which case it returns NULL, which | |
1763 | we can see here. */ | |
1764 | if (t == NULL_TREE) | |
1765 | return; | |
1766 | ||
1767 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1768 | if (type == error_mark_node) |
1769 | return; | |
173b24b9 | 1770 | |
173b24b9 RK |
1771 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1772 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1773 | info. Callers should not set DECL_RTL until after the call to | |
1774 | set_mem_attributes. */ | |
5b0264cb | 1775 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1776 | |
f12144dd RS |
1777 | memset (&attrs, 0, sizeof (attrs)); |
1778 | ||
738cc472 | 1779 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 | 1780 | front-end routine) and use it. */ |
f12144dd | 1781 | attrs.alias = get_alias_set (t); |
173b24b9 | 1782 | |
a5e9c810 | 1783 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
f8ad8d7c | 1784 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1785 | |
268f7033 | 1786 | /* Default values from pre-existing memory attributes if present. */ |
f12144dd RS |
1787 | refattrs = MEM_ATTRS (ref); |
1788 | if (refattrs) | |
268f7033 UW |
1789 | { |
1790 | /* ??? Can this ever happen? Calling this routine on a MEM that | |
1791 | already carries memory attributes should probably be invalid. */ | |
f12144dd | 1792 | attrs.expr = refattrs->expr; |
754c3d5d | 1793 | attrs.offset_known_p = refattrs->offset_known_p; |
f12144dd | 1794 | attrs.offset = refattrs->offset; |
754c3d5d | 1795 | attrs.size_known_p = refattrs->size_known_p; |
f12144dd RS |
1796 | attrs.size = refattrs->size; |
1797 | attrs.align = refattrs->align; | |
268f7033 UW |
1798 | } |
1799 | ||
1800 | /* Otherwise, default values from the mode of the MEM reference. */ | |
f12144dd | 1801 | else |
268f7033 | 1802 | { |
f12144dd RS |
1803 | defattrs = mode_mem_attrs[(int) GET_MODE (ref)]; |
1804 | gcc_assert (!defattrs->expr); | |
754c3d5d | 1805 | gcc_assert (!defattrs->offset_known_p); |
f12144dd | 1806 | |
268f7033 | 1807 | /* Respect mode size. */ |
754c3d5d | 1808 | attrs.size_known_p = defattrs->size_known_p; |
f12144dd | 1809 | attrs.size = defattrs->size; |
268f7033 UW |
1810 | /* ??? Is this really necessary? We probably should always get |
1811 | the size from the type below. */ | |
1812 | ||
1813 | /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type; | |
1814 | if T is an object, always compute the object alignment below. */ | |
f12144dd RS |
1815 | if (TYPE_P (t)) |
1816 | attrs.align = defattrs->align; | |
1817 | else | |
1818 | attrs.align = BITS_PER_UNIT; | |
268f7033 UW |
1819 | /* ??? If T is a type, respecting mode alignment may *also* be wrong |
1820 | e.g. if the type carries an alignment attribute. Should we be | |
1821 | able to simply always use TYPE_ALIGN? */ | |
1822 | } | |
1823 | ||
c3d32120 RK |
1824 | /* We can set the alignment from the type if we are making an object, |
1825 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
a80903ff | 1826 | if (objectp || TREE_CODE (t) == INDIRECT_REF || TYPE_ALIGN_OK (type)) |
f12144dd | 1827 | attrs.align = MAX (attrs.align, TYPE_ALIGN (type)); |
a80903ff | 1828 | |
738cc472 | 1829 | /* If the size is known, we can set that. */ |
a787ccc3 | 1830 | tree new_size = TYPE_SIZE_UNIT (type); |
738cc472 | 1831 | |
30b0317c RB |
1832 | /* The address-space is that of the type. */ |
1833 | as = TYPE_ADDR_SPACE (type); | |
1834 | ||
80965c18 RK |
1835 | /* If T is not a type, we may be able to deduce some more information about |
1836 | the expression. */ | |
1837 | if (! TYPE_P (t)) | |
8ac61af7 | 1838 | { |
8476af98 | 1839 | tree base; |
389fdba0 | 1840 | |
8ac61af7 RK |
1841 | if (TREE_THIS_VOLATILE (t)) |
1842 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1843 | |
c56e3582 RK |
1844 | /* Now remove any conversions: they don't change what the underlying |
1845 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 1846 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
1847 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
1848 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1849 | t = TREE_OPERAND (t, 0); |
1850 | ||
4994da65 RG |
1851 | /* Note whether this expression can trap. */ |
1852 | MEM_NOTRAP_P (ref) = !tree_could_trap_p (t); | |
1853 | ||
1854 | base = get_base_address (t); | |
f18a7b25 MJ |
1855 | if (base) |
1856 | { | |
1857 | if (DECL_P (base) | |
1858 | && TREE_READONLY (base) | |
1859 | && (TREE_STATIC (base) || DECL_EXTERNAL (base)) | |
1860 | && !TREE_THIS_VOLATILE (base)) | |
1861 | MEM_READONLY_P (ref) = 1; | |
1862 | ||
1863 | /* Mark static const strings readonly as well. */ | |
1864 | if (TREE_CODE (base) == STRING_CST | |
1865 | && TREE_READONLY (base) | |
1866 | && TREE_STATIC (base)) | |
1867 | MEM_READONLY_P (ref) = 1; | |
1868 | ||
30b0317c | 1869 | /* Address-space information is on the base object. */ |
f18a7b25 MJ |
1870 | if (TREE_CODE (base) == MEM_REF |
1871 | || TREE_CODE (base) == TARGET_MEM_REF) | |
1872 | as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base, | |
1873 | 0)))); | |
1874 | else | |
1875 | as = TYPE_ADDR_SPACE (TREE_TYPE (base)); | |
1876 | } | |
ba30e50d | 1877 | |
2039d7aa RH |
1878 | /* If this expression uses it's parent's alias set, mark it such |
1879 | that we won't change it. */ | |
b4ada065 | 1880 | if (component_uses_parent_alias_set_from (t) != NULL_TREE) |
10b76d73 RK |
1881 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1882 | ||
8ac61af7 RK |
1883 | /* If this is a decl, set the attributes of the MEM from it. */ |
1884 | if (DECL_P (t)) | |
1885 | { | |
f12144dd | 1886 | attrs.expr = t; |
754c3d5d RS |
1887 | attrs.offset_known_p = true; |
1888 | attrs.offset = 0; | |
6f1087be | 1889 | apply_bitpos = bitpos; |
a787ccc3 | 1890 | new_size = DECL_SIZE_UNIT (t); |
8ac61af7 RK |
1891 | } |
1892 | ||
30b0317c | 1893 | /* ??? If we end up with a constant here do record a MEM_EXPR. */ |
6615c446 | 1894 | else if (CONSTANT_CLASS_P (t)) |
30b0317c | 1895 | ; |
998d7deb | 1896 | |
a787ccc3 RS |
1897 | /* If this is a field reference, record it. */ |
1898 | else if (TREE_CODE (t) == COMPONENT_REF) | |
998d7deb | 1899 | { |
f12144dd | 1900 | attrs.expr = t; |
754c3d5d RS |
1901 | attrs.offset_known_p = true; |
1902 | attrs.offset = 0; | |
6f1087be | 1903 | apply_bitpos = bitpos; |
a787ccc3 RS |
1904 | if (DECL_BIT_FIELD (TREE_OPERAND (t, 1))) |
1905 | new_size = DECL_SIZE_UNIT (TREE_OPERAND (t, 1)); | |
998d7deb RH |
1906 | } |
1907 | ||
1908 | /* If this is an array reference, look for an outer field reference. */ | |
1909 | else if (TREE_CODE (t) == ARRAY_REF) | |
1910 | { | |
1911 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1912 | /* We can't modify t, because we use it at the end of the |
1913 | function. */ | |
1914 | tree t2 = t; | |
998d7deb RH |
1915 | |
1916 | do | |
1917 | { | |
1b1838b6 | 1918 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1919 | tree low_bound = array_ref_low_bound (t2); |
1920 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1921 | |
1922 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1923 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1924 | index, then convert to sizetype and multiply by the size of |
1925 | the array element. */ | |
1926 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1927 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1928 | index, low_bound); | |
2567406a | 1929 | |
44de5aeb | 1930 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1931 | size_binop (MULT_EXPR, |
1932 | fold_convert (sizetype, | |
1933 | index), | |
44de5aeb RK |
1934 | unit_size), |
1935 | off_tree); | |
1b1838b6 | 1936 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1937 | } |
1b1838b6 | 1938 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1939 | |
30b0317c RB |
1940 | if (DECL_P (t2) |
1941 | || TREE_CODE (t2) == COMPONENT_REF) | |
998d7deb | 1942 | { |
f12144dd | 1943 | attrs.expr = t2; |
754c3d5d | 1944 | attrs.offset_known_p = false; |
cc269bb6 | 1945 | if (tree_fits_uhwi_p (off_tree)) |
6f1087be | 1946 | { |
754c3d5d | 1947 | attrs.offset_known_p = true; |
ae7e9ddd | 1948 | attrs.offset = tree_to_uhwi (off_tree); |
6f1087be RH |
1949 | apply_bitpos = bitpos; |
1950 | } | |
998d7deb | 1951 | } |
30b0317c | 1952 | /* Else do not record a MEM_EXPR. */ |
c67a1cf6 RH |
1953 | } |
1954 | ||
56c47f22 | 1955 | /* If this is an indirect reference, record it. */ |
70f34814 | 1956 | else if (TREE_CODE (t) == MEM_REF |
be1ac4ec | 1957 | || TREE_CODE (t) == TARGET_MEM_REF) |
56c47f22 | 1958 | { |
f12144dd | 1959 | attrs.expr = t; |
754c3d5d RS |
1960 | attrs.offset_known_p = true; |
1961 | attrs.offset = 0; | |
56c47f22 RG |
1962 | apply_bitpos = bitpos; |
1963 | } | |
1964 | ||
30b0317c RB |
1965 | /* Compute the alignment. */ |
1966 | unsigned int obj_align; | |
1967 | unsigned HOST_WIDE_INT obj_bitpos; | |
1968 | get_object_alignment_1 (t, &obj_align, &obj_bitpos); | |
1969 | obj_bitpos = (obj_bitpos - bitpos) & (obj_align - 1); | |
1970 | if (obj_bitpos != 0) | |
1971 | obj_align = (obj_bitpos & -obj_bitpos); | |
1972 | attrs.align = MAX (attrs.align, obj_align); | |
8ac61af7 RK |
1973 | } |
1974 | ||
cc269bb6 | 1975 | if (tree_fits_uhwi_p (new_size)) |
a787ccc3 RS |
1976 | { |
1977 | attrs.size_known_p = true; | |
ae7e9ddd | 1978 | attrs.size = tree_to_uhwi (new_size); |
a787ccc3 RS |
1979 | } |
1980 | ||
15c812e3 | 1981 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
1982 | bit position offset. Similarly, increase the size of the accessed |
1983 | object to contain the negative offset. */ | |
6f1087be | 1984 | if (apply_bitpos) |
8c317c5f | 1985 | { |
754c3d5d RS |
1986 | gcc_assert (attrs.offset_known_p); |
1987 | attrs.offset -= apply_bitpos / BITS_PER_UNIT; | |
1988 | if (attrs.size_known_p) | |
1989 | attrs.size += apply_bitpos / BITS_PER_UNIT; | |
8c317c5f | 1990 | } |
6f1087be | 1991 | |
8ac61af7 | 1992 | /* Now set the attributes we computed above. */ |
f18a7b25 | 1993 | attrs.addrspace = as; |
f12144dd | 1994 | set_mem_attrs (ref, &attrs); |
173b24b9 RK |
1995 | } |
1996 | ||
6f1087be | 1997 | void |
502b8322 | 1998 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
1999 | { |
2000 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
2001 | } | |
2002 | ||
173b24b9 RK |
2003 | /* Set the alias set of MEM to SET. */ |
2004 | ||
2005 | void | |
4862826d | 2006 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 2007 | { |
f12144dd RS |
2008 | struct mem_attrs attrs; |
2009 | ||
173b24b9 | 2010 | /* If the new and old alias sets don't conflict, something is wrong. */ |
77a74ed7 | 2011 | gcc_checking_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
f12144dd RS |
2012 | attrs = *get_mem_attrs (mem); |
2013 | attrs.alias = set; | |
2014 | set_mem_attrs (mem, &attrs); | |
09e881c9 BE |
2015 | } |
2016 | ||
2017 | /* Set the address space of MEM to ADDRSPACE (target-defined). */ | |
2018 | ||
2019 | void | |
2020 | set_mem_addr_space (rtx mem, addr_space_t addrspace) | |
2021 | { | |
f12144dd RS |
2022 | struct mem_attrs attrs; |
2023 | ||
2024 | attrs = *get_mem_attrs (mem); | |
2025 | attrs.addrspace = addrspace; | |
2026 | set_mem_attrs (mem, &attrs); | |
173b24b9 | 2027 | } |
738cc472 | 2028 | |
d022d93e | 2029 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
2030 | |
2031 | void | |
502b8322 | 2032 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 2033 | { |
f12144dd RS |
2034 | struct mem_attrs attrs; |
2035 | ||
2036 | attrs = *get_mem_attrs (mem); | |
2037 | attrs.align = align; | |
2038 | set_mem_attrs (mem, &attrs); | |
738cc472 | 2039 | } |
1285011e | 2040 | |
998d7deb | 2041 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
2042 | |
2043 | void | |
502b8322 | 2044 | set_mem_expr (rtx mem, tree expr) |
1285011e | 2045 | { |
f12144dd RS |
2046 | struct mem_attrs attrs; |
2047 | ||
2048 | attrs = *get_mem_attrs (mem); | |
2049 | attrs.expr = expr; | |
2050 | set_mem_attrs (mem, &attrs); | |
1285011e | 2051 | } |
998d7deb RH |
2052 | |
2053 | /* Set the offset of MEM to OFFSET. */ | |
2054 | ||
2055 | void | |
527210c4 | 2056 | set_mem_offset (rtx mem, HOST_WIDE_INT offset) |
998d7deb | 2057 | { |
f12144dd RS |
2058 | struct mem_attrs attrs; |
2059 | ||
2060 | attrs = *get_mem_attrs (mem); | |
754c3d5d RS |
2061 | attrs.offset_known_p = true; |
2062 | attrs.offset = offset; | |
527210c4 RS |
2063 | set_mem_attrs (mem, &attrs); |
2064 | } | |
2065 | ||
2066 | /* Clear the offset of MEM. */ | |
2067 | ||
2068 | void | |
2069 | clear_mem_offset (rtx mem) | |
2070 | { | |
2071 | struct mem_attrs attrs; | |
2072 | ||
2073 | attrs = *get_mem_attrs (mem); | |
754c3d5d | 2074 | attrs.offset_known_p = false; |
f12144dd | 2075 | set_mem_attrs (mem, &attrs); |
35aff10b AM |
2076 | } |
2077 | ||
2078 | /* Set the size of MEM to SIZE. */ | |
2079 | ||
2080 | void | |
f5541398 | 2081 | set_mem_size (rtx mem, HOST_WIDE_INT size) |
35aff10b | 2082 | { |
f12144dd RS |
2083 | struct mem_attrs attrs; |
2084 | ||
2085 | attrs = *get_mem_attrs (mem); | |
754c3d5d RS |
2086 | attrs.size_known_p = true; |
2087 | attrs.size = size; | |
f5541398 RS |
2088 | set_mem_attrs (mem, &attrs); |
2089 | } | |
2090 | ||
2091 | /* Clear the size of MEM. */ | |
2092 | ||
2093 | void | |
2094 | clear_mem_size (rtx mem) | |
2095 | { | |
2096 | struct mem_attrs attrs; | |
2097 | ||
2098 | attrs = *get_mem_attrs (mem); | |
754c3d5d | 2099 | attrs.size_known_p = false; |
f12144dd | 2100 | set_mem_attrs (mem, &attrs); |
998d7deb | 2101 | } |
173b24b9 | 2102 | \f |
738cc472 RK |
2103 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
2104 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
2105 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
23b33725 RS |
2106 | returned memory location is required to be valid. INPLACE is true if any |
2107 | changes can be made directly to MEMREF or false if MEMREF must be treated | |
2108 | as immutable. | |
2109 | ||
2110 | The memory attributes are not changed. */ | |
23b2ce53 | 2111 | |
738cc472 | 2112 | static rtx |
ef4bddc2 | 2113 | change_address_1 (rtx memref, machine_mode mode, rtx addr, int validate, |
23b33725 | 2114 | bool inplace) |
23b2ce53 | 2115 | { |
09e881c9 | 2116 | addr_space_t as; |
60564289 | 2117 | rtx new_rtx; |
23b2ce53 | 2118 | |
5b0264cb | 2119 | gcc_assert (MEM_P (memref)); |
09e881c9 | 2120 | as = MEM_ADDR_SPACE (memref); |
23b2ce53 RS |
2121 | if (mode == VOIDmode) |
2122 | mode = GET_MODE (memref); | |
2123 | if (addr == 0) | |
2124 | addr = XEXP (memref, 0); | |
a74ff877 | 2125 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
09e881c9 | 2126 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
a74ff877 | 2127 | return memref; |
23b2ce53 | 2128 | |
91c5ee5b VM |
2129 | /* Don't validate address for LRA. LRA can make the address valid |
2130 | by itself in most efficient way. */ | |
2131 | if (validate && !lra_in_progress) | |
23b2ce53 | 2132 | { |
f1ec5147 | 2133 | if (reload_in_progress || reload_completed) |
09e881c9 | 2134 | gcc_assert (memory_address_addr_space_p (mode, addr, as)); |
f1ec5147 | 2135 | else |
09e881c9 | 2136 | addr = memory_address_addr_space (mode, addr, as); |
23b2ce53 | 2137 | } |
750c9258 | 2138 | |
9b04c6a8 RK |
2139 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
2140 | return memref; | |
2141 | ||
23b33725 RS |
2142 | if (inplace) |
2143 | { | |
2144 | XEXP (memref, 0) = addr; | |
2145 | return memref; | |
2146 | } | |
2147 | ||
60564289 KG |
2148 | new_rtx = gen_rtx_MEM (mode, addr); |
2149 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
2150 | return new_rtx; | |
23b2ce53 | 2151 | } |
792760b9 | 2152 | |
738cc472 RK |
2153 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
2154 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
2155 | |
2156 | rtx | |
ef4bddc2 | 2157 | change_address (rtx memref, machine_mode mode, rtx addr) |
f4ef873c | 2158 | { |
23b33725 | 2159 | rtx new_rtx = change_address_1 (memref, mode, addr, 1, false); |
ef4bddc2 | 2160 | machine_mode mmode = GET_MODE (new_rtx); |
f12144dd | 2161 | struct mem_attrs attrs, *defattrs; |
4e44c1ef | 2162 | |
f12144dd RS |
2163 | attrs = *get_mem_attrs (memref); |
2164 | defattrs = mode_mem_attrs[(int) mmode]; | |
754c3d5d RS |
2165 | attrs.expr = NULL_TREE; |
2166 | attrs.offset_known_p = false; | |
2167 | attrs.size_known_p = defattrs->size_known_p; | |
f12144dd RS |
2168 | attrs.size = defattrs->size; |
2169 | attrs.align = defattrs->align; | |
c2f7bcc3 | 2170 | |
fdb1c7b3 | 2171 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 2172 | if (new_rtx == memref) |
4e44c1ef | 2173 | { |
f12144dd | 2174 | if (mem_attrs_eq_p (get_mem_attrs (memref), &attrs)) |
60564289 | 2175 | return new_rtx; |
4e44c1ef | 2176 | |
60564289 KG |
2177 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
2178 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 2179 | } |
fdb1c7b3 | 2180 | |
f12144dd | 2181 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2182 | return new_rtx; |
f4ef873c | 2183 | } |
792760b9 | 2184 | |
738cc472 RK |
2185 | /* Return a memory reference like MEMREF, but with its mode changed |
2186 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 | 2187 | nonzero, the memory address is forced to be valid. |
5ef0b50d EB |
2188 | If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS |
2189 | and the caller is responsible for adjusting MEMREF base register. | |
2190 | If ADJUST_OBJECT is zero, the underlying object associated with the | |
2191 | memory reference is left unchanged and the caller is responsible for | |
2192 | dealing with it. Otherwise, if the new memory reference is outside | |
5f2cbd0d RS |
2193 | the underlying object, even partially, then the object is dropped. |
2194 | SIZE, if nonzero, is the size of an access in cases where MODE | |
2195 | has no inherent size. */ | |
f1ec5147 RK |
2196 | |
2197 | rtx | |
ef4bddc2 | 2198 | adjust_address_1 (rtx memref, machine_mode mode, HOST_WIDE_INT offset, |
5f2cbd0d RS |
2199 | int validate, int adjust_address, int adjust_object, |
2200 | HOST_WIDE_INT size) | |
f1ec5147 | 2201 | { |
823e3574 | 2202 | rtx addr = XEXP (memref, 0); |
60564289 | 2203 | rtx new_rtx; |
ef4bddc2 | 2204 | machine_mode address_mode; |
a6fe9ed4 | 2205 | int pbits; |
0207fa90 | 2206 | struct mem_attrs attrs = *get_mem_attrs (memref), *defattrs; |
f12144dd | 2207 | unsigned HOST_WIDE_INT max_align; |
0207fa90 | 2208 | #ifdef POINTERS_EXTEND_UNSIGNED |
ef4bddc2 | 2209 | machine_mode pointer_mode |
0207fa90 EB |
2210 | = targetm.addr_space.pointer_mode (attrs.addrspace); |
2211 | #endif | |
823e3574 | 2212 | |
ee88e690 EB |
2213 | /* VOIDmode means no mode change for change_address_1. */ |
2214 | if (mode == VOIDmode) | |
2215 | mode = GET_MODE (memref); | |
2216 | ||
5f2cbd0d RS |
2217 | /* Take the size of non-BLKmode accesses from the mode. */ |
2218 | defattrs = mode_mem_attrs[(int) mode]; | |
2219 | if (defattrs->size_known_p) | |
2220 | size = defattrs->size; | |
2221 | ||
fdb1c7b3 JH |
2222 | /* If there are no changes, just return the original memory reference. */ |
2223 | if (mode == GET_MODE (memref) && !offset | |
5f2cbd0d | 2224 | && (size == 0 || (attrs.size_known_p && attrs.size == size)) |
f12144dd RS |
2225 | && (!validate || memory_address_addr_space_p (mode, addr, |
2226 | attrs.addrspace))) | |
fdb1c7b3 JH |
2227 | return memref; |
2228 | ||
d14419e4 | 2229 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2230 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2231 | (plus (plus reg reg) const_int) -- so do this always. */ |
2232 | addr = copy_rtx (addr); | |
2233 | ||
a6fe9ed4 JM |
2234 | /* Convert a possibly large offset to a signed value within the |
2235 | range of the target address space. */ | |
372d6395 | 2236 | address_mode = get_address_mode (memref); |
d4ebfa65 | 2237 | pbits = GET_MODE_BITSIZE (address_mode); |
a6fe9ed4 JM |
2238 | if (HOST_BITS_PER_WIDE_INT > pbits) |
2239 | { | |
2240 | int shift = HOST_BITS_PER_WIDE_INT - pbits; | |
2241 | offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift)) | |
2242 | >> shift); | |
2243 | } | |
2244 | ||
5ef0b50d | 2245 | if (adjust_address) |
4a78c787 RH |
2246 | { |
2247 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2248 | object, we can merge it into the LO_SUM. */ | |
2249 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
2250 | && offset >= 0 | |
2251 | && (unsigned HOST_WIDE_INT) offset | |
2252 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
d4ebfa65 | 2253 | addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0), |
0a81f074 RS |
2254 | plus_constant (address_mode, |
2255 | XEXP (addr, 1), offset)); | |
0207fa90 EB |
2256 | #ifdef POINTERS_EXTEND_UNSIGNED |
2257 | /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid | |
2258 | in that mode, we merge it into the ZERO_EXTEND. We take advantage of | |
2259 | the fact that pointers are not allowed to overflow. */ | |
2260 | else if (POINTERS_EXTEND_UNSIGNED > 0 | |
2261 | && GET_CODE (addr) == ZERO_EXTEND | |
2262 | && GET_MODE (XEXP (addr, 0)) == pointer_mode | |
2263 | && trunc_int_for_mode (offset, pointer_mode) == offset) | |
2264 | addr = gen_rtx_ZERO_EXTEND (address_mode, | |
2265 | plus_constant (pointer_mode, | |
2266 | XEXP (addr, 0), offset)); | |
2267 | #endif | |
4a78c787 | 2268 | else |
0a81f074 | 2269 | addr = plus_constant (address_mode, addr, offset); |
4a78c787 | 2270 | } |
823e3574 | 2271 | |
23b33725 | 2272 | new_rtx = change_address_1 (memref, mode, addr, validate, false); |
738cc472 | 2273 | |
09efeca1 PB |
2274 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2275 | but this would destroy memref's MEM_ATTRS. */ | |
2276 | if (new_rtx == memref && offset != 0) | |
2277 | new_rtx = copy_rtx (new_rtx); | |
2278 | ||
5ef0b50d EB |
2279 | /* Conservatively drop the object if we don't know where we start from. */ |
2280 | if (adjust_object && (!attrs.offset_known_p || !attrs.size_known_p)) | |
2281 | { | |
2282 | attrs.expr = NULL_TREE; | |
2283 | attrs.alias = 0; | |
2284 | } | |
2285 | ||
738cc472 RK |
2286 | /* Compute the new values of the memory attributes due to this adjustment. |
2287 | We add the offsets and update the alignment. */ | |
754c3d5d | 2288 | if (attrs.offset_known_p) |
5ef0b50d EB |
2289 | { |
2290 | attrs.offset += offset; | |
2291 | ||
2292 | /* Drop the object if the new left end is not within its bounds. */ | |
2293 | if (adjust_object && attrs.offset < 0) | |
2294 | { | |
2295 | attrs.expr = NULL_TREE; | |
2296 | attrs.alias = 0; | |
2297 | } | |
2298 | } | |
738cc472 | 2299 | |
03bf2c23 RK |
2300 | /* Compute the new alignment by taking the MIN of the alignment and the |
2301 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2302 | if zero. */ | |
2303 | if (offset != 0) | |
f12144dd RS |
2304 | { |
2305 | max_align = (offset & -offset) * BITS_PER_UNIT; | |
2306 | attrs.align = MIN (attrs.align, max_align); | |
2307 | } | |
738cc472 | 2308 | |
5f2cbd0d | 2309 | if (size) |
754c3d5d | 2310 | { |
5ef0b50d | 2311 | /* Drop the object if the new right end is not within its bounds. */ |
5f2cbd0d | 2312 | if (adjust_object && (offset + size) > attrs.size) |
5ef0b50d EB |
2313 | { |
2314 | attrs.expr = NULL_TREE; | |
2315 | attrs.alias = 0; | |
2316 | } | |
754c3d5d | 2317 | attrs.size_known_p = true; |
5f2cbd0d | 2318 | attrs.size = size; |
754c3d5d RS |
2319 | } |
2320 | else if (attrs.size_known_p) | |
5ef0b50d | 2321 | { |
5f2cbd0d | 2322 | gcc_assert (!adjust_object); |
5ef0b50d | 2323 | attrs.size -= offset; |
5f2cbd0d RS |
2324 | /* ??? The store_by_pieces machinery generates negative sizes, |
2325 | so don't assert for that here. */ | |
5ef0b50d | 2326 | } |
10b76d73 | 2327 | |
f12144dd | 2328 | set_mem_attrs (new_rtx, &attrs); |
738cc472 | 2329 | |
60564289 | 2330 | return new_rtx; |
f1ec5147 RK |
2331 | } |
2332 | ||
630036c6 JJ |
2333 | /* Return a memory reference like MEMREF, but with its mode changed |
2334 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2335 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2336 | nonzero, the memory address is forced to be valid. */ |
2337 | ||
2338 | rtx | |
ef4bddc2 | 2339 | adjust_automodify_address_1 (rtx memref, machine_mode mode, rtx addr, |
502b8322 | 2340 | HOST_WIDE_INT offset, int validate) |
630036c6 | 2341 | { |
23b33725 | 2342 | memref = change_address_1 (memref, VOIDmode, addr, validate, false); |
5f2cbd0d | 2343 | return adjust_address_1 (memref, mode, offset, validate, 0, 0, 0); |
630036c6 JJ |
2344 | } |
2345 | ||
8ac61af7 RK |
2346 | /* Return a memory reference like MEMREF, but whose address is changed by |
2347 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2348 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2349 | |
2350 | rtx | |
502b8322 | 2351 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2352 | { |
60564289 | 2353 | rtx new_rtx, addr = XEXP (memref, 0); |
ef4bddc2 | 2354 | machine_mode address_mode; |
754c3d5d | 2355 | struct mem_attrs attrs, *defattrs; |
e3c8ea67 | 2356 | |
f12144dd | 2357 | attrs = *get_mem_attrs (memref); |
372d6395 | 2358 | address_mode = get_address_mode (memref); |
d4ebfa65 | 2359 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 | 2360 | |
68252e27 | 2361 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2362 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2363 | |
2364 | However, if we did go and rearrange things, we can wind up not | |
2365 | being able to recognize the magic around pic_offset_table_rtx. | |
2366 | This stuff is fragile, and is yet another example of why it is | |
2367 | bad to expose PIC machinery too early. */ | |
f12144dd RS |
2368 | if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, |
2369 | attrs.addrspace) | |
e3c8ea67 RH |
2370 | && GET_CODE (addr) == PLUS |
2371 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2372 | { | |
2373 | addr = force_reg (GET_MODE (addr), addr); | |
d4ebfa65 | 2374 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 RH |
2375 | } |
2376 | ||
60564289 | 2377 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
23b33725 | 2378 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1, false); |
0d4903b8 | 2379 | |
fdb1c7b3 | 2380 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2381 | if (new_rtx == memref) |
2382 | return new_rtx; | |
fdb1c7b3 | 2383 | |
0d4903b8 RK |
2384 | /* Update the alignment to reflect the offset. Reset the offset, which |
2385 | we don't know. */ | |
754c3d5d RS |
2386 | defattrs = mode_mem_attrs[(int) GET_MODE (new_rtx)]; |
2387 | attrs.offset_known_p = false; | |
2388 | attrs.size_known_p = defattrs->size_known_p; | |
2389 | attrs.size = defattrs->size; | |
f12144dd RS |
2390 | attrs.align = MIN (attrs.align, pow2 * BITS_PER_UNIT); |
2391 | set_mem_attrs (new_rtx, &attrs); | |
60564289 | 2392 | return new_rtx; |
0d4903b8 | 2393 | } |
68252e27 | 2394 | |
792760b9 RK |
2395 | /* Return a memory reference like MEMREF, but with its address changed to |
2396 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2397 | to is the same, just the form of the address is being changed, such as | |
23b33725 RS |
2398 | by putting something into a register. INPLACE is true if any changes |
2399 | can be made directly to MEMREF or false if MEMREF must be treated as | |
2400 | immutable. */ | |
792760b9 RK |
2401 | |
2402 | rtx | |
23b33725 | 2403 | replace_equiv_address (rtx memref, rtx addr, bool inplace) |
792760b9 | 2404 | { |
738cc472 RK |
2405 | /* change_address_1 copies the memory attribute structure without change |
2406 | and that's exactly what we want here. */ | |
40c0668b | 2407 | update_temp_slot_address (XEXP (memref, 0), addr); |
23b33725 | 2408 | return change_address_1 (memref, VOIDmode, addr, 1, inplace); |
792760b9 | 2409 | } |
738cc472 | 2410 | |
f1ec5147 RK |
2411 | /* Likewise, but the reference is not required to be valid. */ |
2412 | ||
2413 | rtx | |
23b33725 | 2414 | replace_equiv_address_nv (rtx memref, rtx addr, bool inplace) |
f1ec5147 | 2415 | { |
23b33725 | 2416 | return change_address_1 (memref, VOIDmode, addr, 0, inplace); |
f1ec5147 | 2417 | } |
e7dfe4bb RH |
2418 | |
2419 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2420 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2421 | cannot issue QImode memory operations and have to use SImode memory | |
2422 | operations plus masking logic. */ | |
2423 | ||
2424 | rtx | |
ef4bddc2 | 2425 | widen_memory_access (rtx memref, machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb | 2426 | { |
5f2cbd0d | 2427 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1, 0, 0); |
f12144dd | 2428 | struct mem_attrs attrs; |
e7dfe4bb RH |
2429 | unsigned int size = GET_MODE_SIZE (mode); |
2430 | ||
fdb1c7b3 | 2431 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2432 | if (new_rtx == memref) |
2433 | return new_rtx; | |
fdb1c7b3 | 2434 | |
f12144dd RS |
2435 | attrs = *get_mem_attrs (new_rtx); |
2436 | ||
e7dfe4bb RH |
2437 | /* If we don't know what offset we were at within the expression, then |
2438 | we can't know if we've overstepped the bounds. */ | |
754c3d5d | 2439 | if (! attrs.offset_known_p) |
f12144dd | 2440 | attrs.expr = NULL_TREE; |
e7dfe4bb | 2441 | |
f12144dd | 2442 | while (attrs.expr) |
e7dfe4bb | 2443 | { |
f12144dd | 2444 | if (TREE_CODE (attrs.expr) == COMPONENT_REF) |
e7dfe4bb | 2445 | { |
f12144dd RS |
2446 | tree field = TREE_OPERAND (attrs.expr, 1); |
2447 | tree offset = component_ref_field_offset (attrs.expr); | |
e7dfe4bb RH |
2448 | |
2449 | if (! DECL_SIZE_UNIT (field)) | |
2450 | { | |
f12144dd | 2451 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2452 | break; |
2453 | } | |
2454 | ||
2455 | /* Is the field at least as large as the access? If so, ok, | |
2456 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2457 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2458 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
754c3d5d | 2459 | && attrs.offset >= 0) |
e7dfe4bb RH |
2460 | break; |
2461 | ||
cc269bb6 | 2462 | if (! tree_fits_uhwi_p (offset)) |
e7dfe4bb | 2463 | { |
f12144dd | 2464 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2465 | break; |
2466 | } | |
2467 | ||
f12144dd | 2468 | attrs.expr = TREE_OPERAND (attrs.expr, 0); |
ae7e9ddd RS |
2469 | attrs.offset += tree_to_uhwi (offset); |
2470 | attrs.offset += (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field)) | |
754c3d5d | 2471 | / BITS_PER_UNIT); |
e7dfe4bb RH |
2472 | } |
2473 | /* Similarly for the decl. */ | |
f12144dd RS |
2474 | else if (DECL_P (attrs.expr) |
2475 | && DECL_SIZE_UNIT (attrs.expr) | |
2476 | && TREE_CODE (DECL_SIZE_UNIT (attrs.expr)) == INTEGER_CST | |
2477 | && compare_tree_int (DECL_SIZE_UNIT (attrs.expr), size) >= 0 | |
754c3d5d | 2478 | && (! attrs.offset_known_p || attrs.offset >= 0)) |
e7dfe4bb RH |
2479 | break; |
2480 | else | |
2481 | { | |
2482 | /* The widened memory access overflows the expression, which means | |
2483 | that it could alias another expression. Zap it. */ | |
f12144dd | 2484 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2485 | break; |
2486 | } | |
2487 | } | |
2488 | ||
f12144dd | 2489 | if (! attrs.expr) |
754c3d5d | 2490 | attrs.offset_known_p = false; |
e7dfe4bb RH |
2491 | |
2492 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2493 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
f12144dd | 2494 | attrs.alias = 0; |
754c3d5d RS |
2495 | attrs.size_known_p = true; |
2496 | attrs.size = size; | |
f12144dd | 2497 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2498 | return new_rtx; |
e7dfe4bb | 2499 | } |
23b2ce53 | 2500 | \f |
f6129d66 RH |
2501 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2502 | static GTY(()) tree spill_slot_decl; | |
2503 | ||
3d7e23f6 RH |
2504 | tree |
2505 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2506 | { |
2507 | tree d = spill_slot_decl; | |
2508 | rtx rd; | |
f12144dd | 2509 | struct mem_attrs attrs; |
f6129d66 | 2510 | |
3d7e23f6 | 2511 | if (d || !force_build_p) |
f6129d66 RH |
2512 | return d; |
2513 | ||
c2255bc4 AH |
2514 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2515 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2516 | DECL_ARTIFICIAL (d) = 1; |
2517 | DECL_IGNORED_P (d) = 1; | |
2518 | TREE_USED (d) = 1; | |
f6129d66 RH |
2519 | spill_slot_decl = d; |
2520 | ||
2521 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2522 | MEM_NOTRAP_P (rd) = 1; | |
f12144dd RS |
2523 | attrs = *mode_mem_attrs[(int) BLKmode]; |
2524 | attrs.alias = new_alias_set (); | |
2525 | attrs.expr = d; | |
2526 | set_mem_attrs (rd, &attrs); | |
f6129d66 RH |
2527 | SET_DECL_RTL (d, rd); |
2528 | ||
2529 | return d; | |
2530 | } | |
2531 | ||
2532 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2533 | attributes as appropriate for a register allocator spill slot. | |
2534 | These slots are not aliasable by other memory. We arrange for | |
2535 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2536 | work properly in the case of shared spill slots. */ | |
2537 | ||
2538 | void | |
2539 | set_mem_attrs_for_spill (rtx mem) | |
2540 | { | |
f12144dd RS |
2541 | struct mem_attrs attrs; |
2542 | rtx addr; | |
f6129d66 | 2543 | |
f12144dd RS |
2544 | attrs = *get_mem_attrs (mem); |
2545 | attrs.expr = get_spill_slot_decl (true); | |
2546 | attrs.alias = MEM_ALIAS_SET (DECL_RTL (attrs.expr)); | |
2547 | attrs.addrspace = ADDR_SPACE_GENERIC; | |
f6129d66 RH |
2548 | |
2549 | /* We expect the incoming memory to be of the form: | |
2550 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2551 | with perhaps the plus missing for offset = 0. */ | |
2552 | addr = XEXP (mem, 0); | |
754c3d5d RS |
2553 | attrs.offset_known_p = true; |
2554 | attrs.offset = 0; | |
f6129d66 | 2555 | if (GET_CODE (addr) == PLUS |
481683e1 | 2556 | && CONST_INT_P (XEXP (addr, 1))) |
754c3d5d | 2557 | attrs.offset = INTVAL (XEXP (addr, 1)); |
f6129d66 | 2558 | |
f12144dd | 2559 | set_mem_attrs (mem, &attrs); |
f6129d66 RH |
2560 | MEM_NOTRAP_P (mem) = 1; |
2561 | } | |
2562 | \f | |
23b2ce53 RS |
2563 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2564 | ||
7dcc3ab5 | 2565 | rtx_code_label * |
502b8322 | 2566 | gen_label_rtx (void) |
23b2ce53 | 2567 | { |
7dcc3ab5 DM |
2568 | return as_a <rtx_code_label *> ( |
2569 | gen_rtx_CODE_LABEL (VOIDmode, NULL_RTX, NULL_RTX, | |
2570 | NULL, label_num++, NULL)); | |
23b2ce53 RS |
2571 | } |
2572 | \f | |
2573 | /* For procedure integration. */ | |
2574 | ||
23b2ce53 | 2575 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2576 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2577 | Used for an inline-procedure after copying the insn chain. */ |
2578 | ||
2579 | void | |
fee3e72c | 2580 | set_new_first_and_last_insn (rtx_insn *first, rtx_insn *last) |
23b2ce53 | 2581 | { |
fee3e72c | 2582 | rtx_insn *insn; |
86fe05e0 | 2583 | |
5936d944 JH |
2584 | set_first_insn (first); |
2585 | set_last_insn (last); | |
86fe05e0 RK |
2586 | cur_insn_uid = 0; |
2587 | ||
b5b8b0ac AO |
2588 | if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS) |
2589 | { | |
2590 | int debug_count = 0; | |
2591 | ||
2592 | cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1; | |
2593 | cur_debug_insn_uid = 0; | |
2594 | ||
2595 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2596 | if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID) | |
2597 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); | |
2598 | else | |
2599 | { | |
2600 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2601 | if (DEBUG_INSN_P (insn)) | |
2602 | debug_count++; | |
2603 | } | |
2604 | ||
2605 | if (debug_count) | |
2606 | cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count; | |
2607 | else | |
2608 | cur_debug_insn_uid++; | |
2609 | } | |
2610 | else | |
2611 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2612 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2613 | |
2614 | cur_insn_uid++; | |
23b2ce53 | 2615 | } |
23b2ce53 | 2616 | \f |
750c9258 | 2617 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2618 | structure. This routine should only be called once. */ |
23b2ce53 | 2619 | |
fd743bc1 | 2620 | static void |
6bb9bf63 | 2621 | unshare_all_rtl_1 (rtx_insn *insn) |
23b2ce53 | 2622 | { |
d1b81779 | 2623 | /* Unshare just about everything else. */ |
2c07f13b | 2624 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2625 | |
23b2ce53 RS |
2626 | /* Make sure the addresses of stack slots found outside the insn chain |
2627 | (such as, in DECL_RTL of a variable) are not shared | |
2628 | with the insn chain. | |
2629 | ||
2630 | This special care is necessary when the stack slot MEM does not | |
2631 | actually appear in the insn chain. If it does appear, its address | |
2632 | is unshared from all else at that point. */ | |
0f4783c7 DM |
2633 | stack_slot_list = safe_as_a <rtx_expr_list *> ( |
2634 | copy_rtx_if_shared (stack_slot_list)); | |
23b2ce53 RS |
2635 | } |
2636 | ||
750c9258 | 2637 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2638 | structure, again. This is a fairly expensive thing to do so it |
2639 | should be done sparingly. */ | |
2640 | ||
2641 | void | |
6bb9bf63 | 2642 | unshare_all_rtl_again (rtx_insn *insn) |
d1b81779 | 2643 | { |
6bb9bf63 | 2644 | rtx_insn *p; |
624c87aa RE |
2645 | tree decl; |
2646 | ||
d1b81779 | 2647 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2648 | if (INSN_P (p)) |
d1b81779 GK |
2649 | { |
2650 | reset_used_flags (PATTERN (p)); | |
2651 | reset_used_flags (REG_NOTES (p)); | |
776bebcd JJ |
2652 | if (CALL_P (p)) |
2653 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (p)); | |
d1b81779 | 2654 | } |
624c87aa | 2655 | |
2d4aecb3 | 2656 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2657 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2658 | |
624c87aa | 2659 | /* Make sure that virtual parameters are not shared. */ |
910ad8de | 2660 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) |
5eb2a9f2 | 2661 | set_used_flags (DECL_RTL (decl)); |
624c87aa RE |
2662 | |
2663 | reset_used_flags (stack_slot_list); | |
2664 | ||
b4aaa77b | 2665 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2666 | } |
2667 | ||
c2924966 | 2668 | unsigned int |
fd743bc1 PB |
2669 | unshare_all_rtl (void) |
2670 | { | |
b4aaa77b | 2671 | unshare_all_rtl_1 (get_insns ()); |
c2924966 | 2672 | return 0; |
d1b81779 GK |
2673 | } |
2674 | ||
ef330312 | 2675 | |
2c07f13b JH |
2676 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2677 | Recursively does the same for subexpressions. */ | |
2678 | ||
2679 | static void | |
2680 | verify_rtx_sharing (rtx orig, rtx insn) | |
2681 | { | |
2682 | rtx x = orig; | |
2683 | int i; | |
2684 | enum rtx_code code; | |
2685 | const char *format_ptr; | |
2686 | ||
2687 | if (x == 0) | |
2688 | return; | |
2689 | ||
2690 | code = GET_CODE (x); | |
2691 | ||
2692 | /* These types may be freely shared. */ | |
2693 | ||
2694 | switch (code) | |
2695 | { | |
2696 | case REG: | |
0ca5af51 AO |
2697 | case DEBUG_EXPR: |
2698 | case VALUE: | |
d8116890 | 2699 | CASE_CONST_ANY: |
2c07f13b JH |
2700 | case SYMBOL_REF: |
2701 | case LABEL_REF: | |
2702 | case CODE_LABEL: | |
2703 | case PC: | |
2704 | case CC0: | |
3810076b | 2705 | case RETURN: |
26898771 | 2706 | case SIMPLE_RETURN: |
2c07f13b | 2707 | case SCRATCH: |
3e89ed8d | 2708 | /* SCRATCH must be shared because they represent distinct values. */ |
c5c5ba89 | 2709 | return; |
3e89ed8d | 2710 | case CLOBBER: |
c5c5ba89 JH |
2711 | /* Share clobbers of hard registers (like cc0), but do not share pseudo reg |
2712 | clobbers or clobbers of hard registers that originated as pseudos. | |
2713 | This is needed to allow safe register renaming. */ | |
2714 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2715 | && ORIGINAL_REGNO (XEXP (x, 0)) == REGNO (XEXP (x, 0))) | |
3e89ed8d JH |
2716 | return; |
2717 | break; | |
2c07f13b JH |
2718 | |
2719 | case CONST: | |
6fb5fa3c | 2720 | if (shared_const_p (orig)) |
2c07f13b JH |
2721 | return; |
2722 | break; | |
2723 | ||
2724 | case MEM: | |
2725 | /* A MEM is allowed to be shared if its address is constant. */ | |
2726 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2727 | || reload_completed || reload_in_progress) | |
2728 | return; | |
2729 | ||
2730 | break; | |
2731 | ||
2732 | default: | |
2733 | break; | |
2734 | } | |
2735 | ||
2736 | /* This rtx may not be shared. If it has already been seen, | |
2737 | replace it with a copy of itself. */ | |
1a2caa7a | 2738 | #ifdef ENABLE_CHECKING |
2c07f13b JH |
2739 | if (RTX_FLAG (x, used)) |
2740 | { | |
ab532386 | 2741 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2742 | debug_rtx (insn); |
ab532386 | 2743 | error ("shared rtx"); |
2c07f13b | 2744 | debug_rtx (x); |
ab532386 | 2745 | internal_error ("internal consistency failure"); |
2c07f13b | 2746 | } |
1a2caa7a NS |
2747 | #endif |
2748 | gcc_assert (!RTX_FLAG (x, used)); | |
b8698a0f | 2749 | |
2c07f13b JH |
2750 | RTX_FLAG (x, used) = 1; |
2751 | ||
6614fd40 | 2752 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2753 | |
2754 | format_ptr = GET_RTX_FORMAT (code); | |
2755 | ||
2756 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2757 | { | |
2758 | switch (*format_ptr++) | |
2759 | { | |
2760 | case 'e': | |
2761 | verify_rtx_sharing (XEXP (x, i), insn); | |
2762 | break; | |
2763 | ||
2764 | case 'E': | |
2765 | if (XVEC (x, i) != NULL) | |
2766 | { | |
2767 | int j; | |
2768 | int len = XVECLEN (x, i); | |
2769 | ||
2770 | for (j = 0; j < len; j++) | |
2771 | { | |
1a2caa7a NS |
2772 | /* We allow sharing of ASM_OPERANDS inside single |
2773 | instruction. */ | |
2c07f13b | 2774 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2775 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2776 | == ASM_OPERANDS)) | |
2c07f13b JH |
2777 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2778 | else | |
2779 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2780 | } | |
2781 | } | |
2782 | break; | |
2783 | } | |
2784 | } | |
2785 | return; | |
2786 | } | |
2787 | ||
0e0f87d4 SB |
2788 | /* Reset used-flags for INSN. */ |
2789 | ||
2790 | static void | |
2791 | reset_insn_used_flags (rtx insn) | |
2792 | { | |
2793 | gcc_assert (INSN_P (insn)); | |
2794 | reset_used_flags (PATTERN (insn)); | |
2795 | reset_used_flags (REG_NOTES (insn)); | |
2796 | if (CALL_P (insn)) | |
2797 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn)); | |
2798 | } | |
2799 | ||
a24243a0 | 2800 | /* Go through all the RTL insn bodies and clear all the USED bits. */ |
2c07f13b | 2801 | |
a24243a0 AK |
2802 | static void |
2803 | reset_all_used_flags (void) | |
2c07f13b | 2804 | { |
dc01c3d1 | 2805 | rtx_insn *p; |
2c07f13b JH |
2806 | |
2807 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2808 | if (INSN_P (p)) | |
2809 | { | |
0e0f87d4 SB |
2810 | rtx pat = PATTERN (p); |
2811 | if (GET_CODE (pat) != SEQUENCE) | |
2812 | reset_insn_used_flags (p); | |
2813 | else | |
2954a813 | 2814 | { |
0e0f87d4 SB |
2815 | gcc_assert (REG_NOTES (p) == NULL); |
2816 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
2817 | { |
2818 | rtx insn = XVECEXP (pat, 0, i); | |
2819 | if (INSN_P (insn)) | |
2820 | reset_insn_used_flags (insn); | |
2821 | } | |
2954a813 | 2822 | } |
2c07f13b | 2823 | } |
a24243a0 AK |
2824 | } |
2825 | ||
0e0f87d4 SB |
2826 | /* Verify sharing in INSN. */ |
2827 | ||
2828 | static void | |
2829 | verify_insn_sharing (rtx insn) | |
2830 | { | |
2831 | gcc_assert (INSN_P (insn)); | |
2832 | reset_used_flags (PATTERN (insn)); | |
2833 | reset_used_flags (REG_NOTES (insn)); | |
2834 | if (CALL_P (insn)) | |
2835 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn)); | |
2836 | } | |
2837 | ||
a24243a0 AK |
2838 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2839 | sharing in between the subexpressions. */ | |
2840 | ||
2841 | DEBUG_FUNCTION void | |
2842 | verify_rtl_sharing (void) | |
2843 | { | |
dc01c3d1 | 2844 | rtx_insn *p; |
a24243a0 AK |
2845 | |
2846 | timevar_push (TV_VERIFY_RTL_SHARING); | |
2847 | ||
2848 | reset_all_used_flags (); | |
2c07f13b JH |
2849 | |
2850 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2851 | if (INSN_P (p)) | |
2852 | { | |
0e0f87d4 SB |
2853 | rtx pat = PATTERN (p); |
2854 | if (GET_CODE (pat) != SEQUENCE) | |
2855 | verify_insn_sharing (p); | |
2856 | else | |
2857 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
2858 | { |
2859 | rtx insn = XVECEXP (pat, 0, i); | |
2860 | if (INSN_P (insn)) | |
2861 | verify_insn_sharing (insn); | |
2862 | } | |
2c07f13b | 2863 | } |
a222c01a | 2864 | |
a24243a0 AK |
2865 | reset_all_used_flags (); |
2866 | ||
a222c01a | 2867 | timevar_pop (TV_VERIFY_RTL_SHARING); |
2c07f13b JH |
2868 | } |
2869 | ||
d1b81779 GK |
2870 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2871 | Assumes the mark bits are cleared at entry. */ | |
2872 | ||
2c07f13b | 2873 | void |
dc01c3d1 | 2874 | unshare_all_rtl_in_chain (rtx_insn *insn) |
d1b81779 GK |
2875 | { |
2876 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2877 | if (INSN_P (insn)) |
d1b81779 GK |
2878 | { |
2879 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2880 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
776bebcd JJ |
2881 | if (CALL_P (insn)) |
2882 | CALL_INSN_FUNCTION_USAGE (insn) | |
2883 | = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn)); | |
d1b81779 GK |
2884 | } |
2885 | } | |
2886 | ||
2d4aecb3 | 2887 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2888 | shared. We never replace the DECL_RTLs themselves with a copy, |
2889 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2890 | expressions in the instruction stream. | |
2891 | ||
2892 | Note that reload may convert pseudo registers into memories in-place. | |
2893 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2894 | reset the used flags on MEMs in the instruction stream, we must set | |
2895 | them again on MEMs that appear in DECL_RTLs. */ | |
2896 | ||
2d4aecb3 | 2897 | static void |
5eb2a9f2 | 2898 | set_used_decls (tree blk) |
2d4aecb3 AO |
2899 | { |
2900 | tree t; | |
2901 | ||
2902 | /* Mark decls. */ | |
910ad8de | 2903 | for (t = BLOCK_VARS (blk); t; t = DECL_CHAIN (t)) |
19e7881c | 2904 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2905 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2906 | |
2907 | /* Now process sub-blocks. */ | |
87caf699 | 2908 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 2909 | set_used_decls (t); |
2d4aecb3 AO |
2910 | } |
2911 | ||
23b2ce53 | 2912 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2913 | Recursively does the same for subexpressions. Uses |
2914 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2915 | |
2916 | rtx | |
502b8322 | 2917 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2918 | { |
32b32b16 AP |
2919 | copy_rtx_if_shared_1 (&orig); |
2920 | return orig; | |
2921 | } | |
2922 | ||
ff954f39 AP |
2923 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2924 | use. Recursively does the same for subexpressions. */ | |
2925 | ||
32b32b16 AP |
2926 | static void |
2927 | copy_rtx_if_shared_1 (rtx *orig1) | |
2928 | { | |
2929 | rtx x; | |
b3694847 SS |
2930 | int i; |
2931 | enum rtx_code code; | |
32b32b16 | 2932 | rtx *last_ptr; |
b3694847 | 2933 | const char *format_ptr; |
23b2ce53 | 2934 | int copied = 0; |
32b32b16 AP |
2935 | int length; |
2936 | ||
2937 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2938 | repeat: | |
2939 | x = *orig1; | |
23b2ce53 RS |
2940 | |
2941 | if (x == 0) | |
32b32b16 | 2942 | return; |
23b2ce53 RS |
2943 | |
2944 | code = GET_CODE (x); | |
2945 | ||
2946 | /* These types may be freely shared. */ | |
2947 | ||
2948 | switch (code) | |
2949 | { | |
2950 | case REG: | |
0ca5af51 AO |
2951 | case DEBUG_EXPR: |
2952 | case VALUE: | |
d8116890 | 2953 | CASE_CONST_ANY: |
23b2ce53 | 2954 | case SYMBOL_REF: |
2c07f13b | 2955 | case LABEL_REF: |
23b2ce53 RS |
2956 | case CODE_LABEL: |
2957 | case PC: | |
2958 | case CC0: | |
276e0224 | 2959 | case RETURN: |
26898771 | 2960 | case SIMPLE_RETURN: |
23b2ce53 | 2961 | case SCRATCH: |
0f41302f | 2962 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 2963 | return; |
3e89ed8d | 2964 | case CLOBBER: |
c5c5ba89 JH |
2965 | /* Share clobbers of hard registers (like cc0), but do not share pseudo reg |
2966 | clobbers or clobbers of hard registers that originated as pseudos. | |
2967 | This is needed to allow safe register renaming. */ | |
2968 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2969 | && ORIGINAL_REGNO (XEXP (x, 0)) == REGNO (XEXP (x, 0))) | |
3e89ed8d JH |
2970 | return; |
2971 | break; | |
23b2ce53 | 2972 | |
b851ea09 | 2973 | case CONST: |
6fb5fa3c | 2974 | if (shared_const_p (x)) |
32b32b16 | 2975 | return; |
b851ea09 RK |
2976 | break; |
2977 | ||
b5b8b0ac | 2978 | case DEBUG_INSN: |
23b2ce53 RS |
2979 | case INSN: |
2980 | case JUMP_INSN: | |
2981 | case CALL_INSN: | |
2982 | case NOTE: | |
23b2ce53 RS |
2983 | case BARRIER: |
2984 | /* The chain of insns is not being copied. */ | |
32b32b16 | 2985 | return; |
23b2ce53 | 2986 | |
e9a25f70 JL |
2987 | default: |
2988 | break; | |
23b2ce53 RS |
2989 | } |
2990 | ||
2991 | /* This rtx may not be shared. If it has already been seen, | |
2992 | replace it with a copy of itself. */ | |
2993 | ||
2adc7f12 | 2994 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2995 | { |
aacd3885 | 2996 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
2997 | copied = 1; |
2998 | } | |
2adc7f12 | 2999 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
3000 | |
3001 | /* Now scan the subexpressions recursively. | |
3002 | We can store any replaced subexpressions directly into X | |
3003 | since we know X is not shared! Any vectors in X | |
3004 | must be copied if X was copied. */ | |
3005 | ||
3006 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
3007 | length = GET_RTX_LENGTH (code); |
3008 | last_ptr = NULL; | |
b8698a0f | 3009 | |
32b32b16 | 3010 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3011 | { |
3012 | switch (*format_ptr++) | |
3013 | { | |
3014 | case 'e': | |
32b32b16 AP |
3015 | if (last_ptr) |
3016 | copy_rtx_if_shared_1 (last_ptr); | |
3017 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
3018 | break; |
3019 | ||
3020 | case 'E': | |
3021 | if (XVEC (x, i) != NULL) | |
3022 | { | |
b3694847 | 3023 | int j; |
f0722107 | 3024 | int len = XVECLEN (x, i); |
b8698a0f | 3025 | |
6614fd40 KH |
3026 | /* Copy the vector iff I copied the rtx and the length |
3027 | is nonzero. */ | |
f0722107 | 3028 | if (copied && len > 0) |
8f985ec4 | 3029 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
b8698a0f | 3030 | |
5d3cc252 | 3031 | /* Call recursively on all inside the vector. */ |
f0722107 | 3032 | for (j = 0; j < len; j++) |
32b32b16 AP |
3033 | { |
3034 | if (last_ptr) | |
3035 | copy_rtx_if_shared_1 (last_ptr); | |
3036 | last_ptr = &XVECEXP (x, i, j); | |
3037 | } | |
23b2ce53 RS |
3038 | } |
3039 | break; | |
3040 | } | |
3041 | } | |
32b32b16 AP |
3042 | *orig1 = x; |
3043 | if (last_ptr) | |
3044 | { | |
3045 | orig1 = last_ptr; | |
3046 | goto repeat; | |
3047 | } | |
3048 | return; | |
23b2ce53 RS |
3049 | } |
3050 | ||
76369a82 | 3051 | /* Set the USED bit in X and its non-shareable subparts to FLAG. */ |
23b2ce53 | 3052 | |
76369a82 NF |
3053 | static void |
3054 | mark_used_flags (rtx x, int flag) | |
23b2ce53 | 3055 | { |
b3694847 SS |
3056 | int i, j; |
3057 | enum rtx_code code; | |
3058 | const char *format_ptr; | |
32b32b16 | 3059 | int length; |
23b2ce53 | 3060 | |
32b32b16 AP |
3061 | /* Repeat is used to turn tail-recursion into iteration. */ |
3062 | repeat: | |
23b2ce53 RS |
3063 | if (x == 0) |
3064 | return; | |
3065 | ||
3066 | code = GET_CODE (x); | |
3067 | ||
9faa82d8 | 3068 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
3069 | for them. */ |
3070 | ||
3071 | switch (code) | |
3072 | { | |
3073 | case REG: | |
0ca5af51 AO |
3074 | case DEBUG_EXPR: |
3075 | case VALUE: | |
d8116890 | 3076 | CASE_CONST_ANY: |
23b2ce53 RS |
3077 | case SYMBOL_REF: |
3078 | case CODE_LABEL: | |
3079 | case PC: | |
3080 | case CC0: | |
276e0224 | 3081 | case RETURN: |
26898771 | 3082 | case SIMPLE_RETURN: |
23b2ce53 RS |
3083 | return; |
3084 | ||
b5b8b0ac | 3085 | case DEBUG_INSN: |
23b2ce53 RS |
3086 | case INSN: |
3087 | case JUMP_INSN: | |
3088 | case CALL_INSN: | |
3089 | case NOTE: | |
3090 | case LABEL_REF: | |
3091 | case BARRIER: | |
3092 | /* The chain of insns is not being copied. */ | |
3093 | return; | |
750c9258 | 3094 | |
e9a25f70 JL |
3095 | default: |
3096 | break; | |
23b2ce53 RS |
3097 | } |
3098 | ||
76369a82 | 3099 | RTX_FLAG (x, used) = flag; |
23b2ce53 RS |
3100 | |
3101 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 | 3102 | length = GET_RTX_LENGTH (code); |
b8698a0f | 3103 | |
32b32b16 | 3104 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3105 | { |
3106 | switch (*format_ptr++) | |
3107 | { | |
3108 | case 'e': | |
32b32b16 AP |
3109 | if (i == length-1) |
3110 | { | |
3111 | x = XEXP (x, i); | |
3112 | goto repeat; | |
3113 | } | |
76369a82 | 3114 | mark_used_flags (XEXP (x, i), flag); |
23b2ce53 RS |
3115 | break; |
3116 | ||
3117 | case 'E': | |
3118 | for (j = 0; j < XVECLEN (x, i); j++) | |
76369a82 | 3119 | mark_used_flags (XVECEXP (x, i, j), flag); |
23b2ce53 RS |
3120 | break; |
3121 | } | |
3122 | } | |
3123 | } | |
2c07f13b | 3124 | |
76369a82 | 3125 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used |
2c07f13b JH |
3126 | to look for shared sub-parts. */ |
3127 | ||
3128 | void | |
76369a82 | 3129 | reset_used_flags (rtx x) |
2c07f13b | 3130 | { |
76369a82 NF |
3131 | mark_used_flags (x, 0); |
3132 | } | |
2c07f13b | 3133 | |
76369a82 NF |
3134 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used |
3135 | to look for shared sub-parts. */ | |
2c07f13b | 3136 | |
76369a82 NF |
3137 | void |
3138 | set_used_flags (rtx x) | |
3139 | { | |
3140 | mark_used_flags (x, 1); | |
2c07f13b | 3141 | } |
23b2ce53 RS |
3142 | \f |
3143 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
3144 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
3145 | OTHER must be valid as a SET_DEST. */ | |
3146 | ||
3147 | rtx | |
502b8322 | 3148 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
3149 | { |
3150 | while (1) | |
3151 | switch (GET_CODE (other)) | |
3152 | { | |
3153 | case SUBREG: | |
3154 | other = SUBREG_REG (other); | |
3155 | break; | |
3156 | case STRICT_LOW_PART: | |
3157 | case SIGN_EXTEND: | |
3158 | case ZERO_EXTEND: | |
3159 | other = XEXP (other, 0); | |
3160 | break; | |
3161 | default: | |
3162 | goto done; | |
3163 | } | |
3164 | done: | |
3c0cb5de | 3165 | if ((MEM_P (other) |
23b2ce53 | 3166 | && ! CONSTANT_P (x) |
f8cfc6aa | 3167 | && !REG_P (x) |
23b2ce53 | 3168 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 3169 | || (REG_P (other) |
23b2ce53 RS |
3170 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
3171 | || reg_mentioned_p (other, x)))) | |
3172 | { | |
3173 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
3174 | emit_move_insn (temp, x); | |
3175 | return temp; | |
3176 | } | |
3177 | return x; | |
3178 | } | |
3179 | \f | |
3180 | /* Emission of insns (adding them to the doubly-linked list). */ | |
3181 | ||
23b2ce53 RS |
3182 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ |
3183 | ||
db76cf1e | 3184 | rtx_insn * |
502b8322 | 3185 | get_last_insn_anywhere (void) |
23b2ce53 | 3186 | { |
614d5bd8 AM |
3187 | struct sequence_stack *seq; |
3188 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
3189 | if (seq->last != 0) | |
3190 | return seq->last; | |
23b2ce53 RS |
3191 | return 0; |
3192 | } | |
3193 | ||
2a496e8b JDA |
3194 | /* Return the first nonnote insn emitted in current sequence or current |
3195 | function. This routine looks inside SEQUENCEs. */ | |
3196 | ||
e4685bc8 | 3197 | rtx_insn * |
502b8322 | 3198 | get_first_nonnote_insn (void) |
2a496e8b | 3199 | { |
dc01c3d1 | 3200 | rtx_insn *insn = get_insns (); |
91373fe8 JDA |
3201 | |
3202 | if (insn) | |
3203 | { | |
3204 | if (NOTE_P (insn)) | |
3205 | for (insn = next_insn (insn); | |
3206 | insn && NOTE_P (insn); | |
3207 | insn = next_insn (insn)) | |
3208 | continue; | |
3209 | else | |
3210 | { | |
2ca202e7 | 3211 | if (NONJUMP_INSN_P (insn) |
91373fe8 | 3212 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
dc01c3d1 | 3213 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
91373fe8 JDA |
3214 | } |
3215 | } | |
2a496e8b JDA |
3216 | |
3217 | return insn; | |
3218 | } | |
3219 | ||
3220 | /* Return the last nonnote insn emitted in current sequence or current | |
3221 | function. This routine looks inside SEQUENCEs. */ | |
3222 | ||
e4685bc8 | 3223 | rtx_insn * |
502b8322 | 3224 | get_last_nonnote_insn (void) |
2a496e8b | 3225 | { |
dc01c3d1 | 3226 | rtx_insn *insn = get_last_insn (); |
91373fe8 JDA |
3227 | |
3228 | if (insn) | |
3229 | { | |
3230 | if (NOTE_P (insn)) | |
3231 | for (insn = previous_insn (insn); | |
3232 | insn && NOTE_P (insn); | |
3233 | insn = previous_insn (insn)) | |
3234 | continue; | |
3235 | else | |
3236 | { | |
dc01c3d1 DM |
3237 | if (NONJUMP_INSN_P (insn)) |
3238 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3239 | insn = seq->insn (seq->len () - 1); | |
91373fe8 JDA |
3240 | } |
3241 | } | |
2a496e8b JDA |
3242 | |
3243 | return insn; | |
3244 | } | |
3245 | ||
b5b8b0ac AO |
3246 | /* Return the number of actual (non-debug) insns emitted in this |
3247 | function. */ | |
3248 | ||
3249 | int | |
3250 | get_max_insn_count (void) | |
3251 | { | |
3252 | int n = cur_insn_uid; | |
3253 | ||
3254 | /* The table size must be stable across -g, to avoid codegen | |
3255 | differences due to debug insns, and not be affected by | |
3256 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
3257 | debugging of -fcompare-debug failures. */ | |
3258 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3259 | n -= cur_debug_insn_uid; | |
3260 | else | |
3261 | n -= MIN_NONDEBUG_INSN_UID; | |
3262 | ||
3263 | return n; | |
3264 | } | |
3265 | ||
23b2ce53 RS |
3266 | \f |
3267 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
3268 | of the sequence. */ | |
3269 | ||
eb51c837 | 3270 | rtx_insn * |
4ce524a1 | 3271 | next_insn (rtx_insn *insn) |
23b2ce53 | 3272 | { |
75547801 KG |
3273 | if (insn) |
3274 | { | |
3275 | insn = NEXT_INSN (insn); | |
3276 | if (insn && NONJUMP_INSN_P (insn) | |
3277 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
dc01c3d1 | 3278 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
75547801 | 3279 | } |
23b2ce53 | 3280 | |
dc01c3d1 | 3281 | return insn; |
23b2ce53 RS |
3282 | } |
3283 | ||
3284 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3285 | of the sequence. */ | |
3286 | ||
eb51c837 | 3287 | rtx_insn * |
4ce524a1 | 3288 | previous_insn (rtx_insn *insn) |
23b2ce53 | 3289 | { |
75547801 KG |
3290 | if (insn) |
3291 | { | |
3292 | insn = PREV_INSN (insn); | |
dc01c3d1 DM |
3293 | if (insn && NONJUMP_INSN_P (insn)) |
3294 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3295 | insn = seq->insn (seq->len () - 1); | |
75547801 | 3296 | } |
23b2ce53 | 3297 | |
dc01c3d1 | 3298 | return insn; |
23b2ce53 RS |
3299 | } |
3300 | ||
3301 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3302 | look inside SEQUENCEs. */ | |
3303 | ||
eb51c837 | 3304 | rtx_insn * |
dc01c3d1 | 3305 | next_nonnote_insn (rtx uncast_insn) |
23b2ce53 | 3306 | { |
dc01c3d1 | 3307 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
75547801 KG |
3308 | while (insn) |
3309 | { | |
3310 | insn = NEXT_INSN (insn); | |
3311 | if (insn == 0 || !NOTE_P (insn)) | |
3312 | break; | |
3313 | } | |
23b2ce53 | 3314 | |
dc01c3d1 | 3315 | return insn; |
23b2ce53 RS |
3316 | } |
3317 | ||
1e211590 DD |
3318 | /* Return the next insn after INSN that is not a NOTE, but stop the |
3319 | search before we enter another basic block. This routine does not | |
3320 | look inside SEQUENCEs. */ | |
3321 | ||
eb51c837 | 3322 | rtx_insn * |
e4685bc8 | 3323 | next_nonnote_insn_bb (rtx_insn *insn) |
1e211590 DD |
3324 | { |
3325 | while (insn) | |
3326 | { | |
3327 | insn = NEXT_INSN (insn); | |
3328 | if (insn == 0 || !NOTE_P (insn)) | |
3329 | break; | |
3330 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
eb51c837 | 3331 | return NULL; |
1e211590 DD |
3332 | } |
3333 | ||
dc01c3d1 | 3334 | return insn; |
1e211590 DD |
3335 | } |
3336 | ||
23b2ce53 RS |
3337 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3338 | not look inside SEQUENCEs. */ | |
3339 | ||
eb51c837 | 3340 | rtx_insn * |
dc01c3d1 | 3341 | prev_nonnote_insn (rtx uncast_insn) |
23b2ce53 | 3342 | { |
dc01c3d1 DM |
3343 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3344 | ||
75547801 KG |
3345 | while (insn) |
3346 | { | |
3347 | insn = PREV_INSN (insn); | |
3348 | if (insn == 0 || !NOTE_P (insn)) | |
3349 | break; | |
3350 | } | |
23b2ce53 | 3351 | |
dc01c3d1 | 3352 | return insn; |
23b2ce53 RS |
3353 | } |
3354 | ||
896aa4ea DD |
3355 | /* Return the previous insn before INSN that is not a NOTE, but stop |
3356 | the search before we enter another basic block. This routine does | |
3357 | not look inside SEQUENCEs. */ | |
3358 | ||
eb51c837 | 3359 | rtx_insn * |
dc01c3d1 | 3360 | prev_nonnote_insn_bb (rtx uncast_insn) |
896aa4ea | 3361 | { |
dc01c3d1 DM |
3362 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3363 | ||
896aa4ea DD |
3364 | while (insn) |
3365 | { | |
3366 | insn = PREV_INSN (insn); | |
3367 | if (insn == 0 || !NOTE_P (insn)) | |
3368 | break; | |
3369 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
eb51c837 | 3370 | return NULL; |
896aa4ea DD |
3371 | } |
3372 | ||
dc01c3d1 | 3373 | return insn; |
896aa4ea DD |
3374 | } |
3375 | ||
b5b8b0ac AO |
3376 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3377 | routine does not look inside SEQUENCEs. */ | |
3378 | ||
eb51c837 | 3379 | rtx_insn * |
dc01c3d1 | 3380 | next_nondebug_insn (rtx uncast_insn) |
b5b8b0ac | 3381 | { |
dc01c3d1 DM |
3382 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3383 | ||
b5b8b0ac AO |
3384 | while (insn) |
3385 | { | |
3386 | insn = NEXT_INSN (insn); | |
3387 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3388 | break; | |
3389 | } | |
3390 | ||
dc01c3d1 | 3391 | return insn; |
b5b8b0ac AO |
3392 | } |
3393 | ||
3394 | /* Return the previous insn before INSN that is not a DEBUG_INSN. | |
3395 | This routine does not look inside SEQUENCEs. */ | |
3396 | ||
eb51c837 | 3397 | rtx_insn * |
dc01c3d1 | 3398 | prev_nondebug_insn (rtx uncast_insn) |
b5b8b0ac | 3399 | { |
dc01c3d1 DM |
3400 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3401 | ||
b5b8b0ac AO |
3402 | while (insn) |
3403 | { | |
3404 | insn = PREV_INSN (insn); | |
3405 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3406 | break; | |
3407 | } | |
3408 | ||
dc01c3d1 | 3409 | return insn; |
b5b8b0ac AO |
3410 | } |
3411 | ||
f0fc0803 JJ |
3412 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN. |
3413 | This routine does not look inside SEQUENCEs. */ | |
3414 | ||
eb51c837 | 3415 | rtx_insn * |
dc01c3d1 | 3416 | next_nonnote_nondebug_insn (rtx uncast_insn) |
f0fc0803 | 3417 | { |
dc01c3d1 DM |
3418 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3419 | ||
f0fc0803 JJ |
3420 | while (insn) |
3421 | { | |
3422 | insn = NEXT_INSN (insn); | |
3423 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) | |
3424 | break; | |
3425 | } | |
3426 | ||
dc01c3d1 | 3427 | return insn; |
f0fc0803 JJ |
3428 | } |
3429 | ||
3430 | /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN. | |
3431 | This routine does not look inside SEQUENCEs. */ | |
3432 | ||
eb51c837 | 3433 | rtx_insn * |
dc01c3d1 | 3434 | prev_nonnote_nondebug_insn (rtx uncast_insn) |
f0fc0803 | 3435 | { |
dc01c3d1 DM |
3436 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3437 | ||
f0fc0803 JJ |
3438 | while (insn) |
3439 | { | |
3440 | insn = PREV_INSN (insn); | |
3441 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) | |
3442 | break; | |
3443 | } | |
3444 | ||
dc01c3d1 | 3445 | return insn; |
f0fc0803 JJ |
3446 | } |
3447 | ||
23b2ce53 RS |
3448 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3449 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3450 | SEQUENCEs. */ |
23b2ce53 | 3451 | |
eb51c837 | 3452 | rtx_insn * |
dc01c3d1 | 3453 | next_real_insn (rtx uncast_insn) |
23b2ce53 | 3454 | { |
dc01c3d1 DM |
3455 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3456 | ||
75547801 KG |
3457 | while (insn) |
3458 | { | |
3459 | insn = NEXT_INSN (insn); | |
3460 | if (insn == 0 || INSN_P (insn)) | |
3461 | break; | |
3462 | } | |
23b2ce53 | 3463 | |
dc01c3d1 | 3464 | return insn; |
23b2ce53 RS |
3465 | } |
3466 | ||
3467 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3468 | or 0, if there is none. This routine does not look inside | |
3469 | SEQUENCEs. */ | |
3470 | ||
eb51c837 | 3471 | rtx_insn * |
dc01c3d1 | 3472 | prev_real_insn (rtx uncast_insn) |
23b2ce53 | 3473 | { |
dc01c3d1 DM |
3474 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3475 | ||
75547801 KG |
3476 | while (insn) |
3477 | { | |
3478 | insn = PREV_INSN (insn); | |
3479 | if (insn == 0 || INSN_P (insn)) | |
3480 | break; | |
3481 | } | |
23b2ce53 | 3482 | |
dc01c3d1 | 3483 | return insn; |
23b2ce53 RS |
3484 | } |
3485 | ||
ee960939 OH |
3486 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3487 | This routine does not look inside SEQUENCEs. */ | |
3488 | ||
049cfc4a | 3489 | rtx_call_insn * |
502b8322 | 3490 | last_call_insn (void) |
ee960939 | 3491 | { |
049cfc4a | 3492 | rtx_insn *insn; |
ee960939 OH |
3493 | |
3494 | for (insn = get_last_insn (); | |
4b4bf941 | 3495 | insn && !CALL_P (insn); |
ee960939 OH |
3496 | insn = PREV_INSN (insn)) |
3497 | ; | |
3498 | ||
049cfc4a | 3499 | return safe_as_a <rtx_call_insn *> (insn); |
ee960939 OH |
3500 | } |
3501 | ||
23b2ce53 | 3502 | /* Find the next insn after INSN that really does something. This routine |
9c517bf3 AK |
3503 | does not look inside SEQUENCEs. After reload this also skips over |
3504 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3505 | |
69732dcb | 3506 | int |
4f588890 | 3507 | active_insn_p (const_rtx insn) |
69732dcb | 3508 | { |
4b4bf941 | 3509 | return (CALL_P (insn) || JUMP_P (insn) |
39718607 | 3510 | || JUMP_TABLE_DATA_P (insn) /* FIXME */ |
4b4bf941 | 3511 | || (NONJUMP_INSN_P (insn) |
23b8ba81 RH |
3512 | && (! reload_completed |
3513 | || (GET_CODE (PATTERN (insn)) != USE | |
3514 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3515 | } |
3516 | ||
eb51c837 | 3517 | rtx_insn * |
dc01c3d1 | 3518 | next_active_insn (rtx uncast_insn) |
23b2ce53 | 3519 | { |
dc01c3d1 DM |
3520 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3521 | ||
75547801 KG |
3522 | while (insn) |
3523 | { | |
3524 | insn = NEXT_INSN (insn); | |
3525 | if (insn == 0 || active_insn_p (insn)) | |
3526 | break; | |
3527 | } | |
23b2ce53 | 3528 | |
dc01c3d1 | 3529 | return insn; |
23b2ce53 RS |
3530 | } |
3531 | ||
3532 | /* Find the last insn before INSN that really does something. This routine | |
9c517bf3 AK |
3533 | does not look inside SEQUENCEs. After reload this also skips over |
3534 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3535 | |
eb51c837 | 3536 | rtx_insn * |
dc01c3d1 | 3537 | prev_active_insn (rtx uncast_insn) |
23b2ce53 | 3538 | { |
dc01c3d1 DM |
3539 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3540 | ||
75547801 KG |
3541 | while (insn) |
3542 | { | |
3543 | insn = PREV_INSN (insn); | |
3544 | if (insn == 0 || active_insn_p (insn)) | |
3545 | break; | |
3546 | } | |
23b2ce53 | 3547 | |
dc01c3d1 | 3548 | return insn; |
23b2ce53 | 3549 | } |
23b2ce53 | 3550 | \f |
23b2ce53 RS |
3551 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3552 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3553 | applied to the result of this function should yield INSN). | |
3554 | ||
3555 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3556 | is present, it contains the insn that uses CC0. | |
3557 | ||
3558 | Return 0 if we can't find the insn. */ | |
3559 | ||
75b46023 | 3560 | rtx_insn * |
dc01c3d1 | 3561 | next_cc0_user (rtx uncast_insn) |
23b2ce53 | 3562 | { |
dc01c3d1 DM |
3563 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3564 | ||
906c4e36 | 3565 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3566 | |
3567 | if (note) | |
75b46023 | 3568 | return safe_as_a <rtx_insn *> (XEXP (note, 0)); |
23b2ce53 RS |
3569 | |
3570 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3571 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
dc01c3d1 | 3572 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
23b2ce53 | 3573 | |
2c3c49de | 3574 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
dc01c3d1 | 3575 | return insn; |
23b2ce53 RS |
3576 | |
3577 | return 0; | |
3578 | } | |
3579 | ||
3580 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3581 | note, it is the previous insn. */ | |
3582 | ||
75b46023 | 3583 | rtx_insn * |
5c8db5b4 | 3584 | prev_cc0_setter (rtx_insn *insn) |
23b2ce53 | 3585 | { |
906c4e36 | 3586 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3587 | |
3588 | if (note) | |
75b46023 | 3589 | return safe_as_a <rtx_insn *> (XEXP (note, 0)); |
23b2ce53 RS |
3590 | |
3591 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3592 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 | 3593 | |
dc01c3d1 | 3594 | return insn; |
23b2ce53 | 3595 | } |
e5bef2e4 | 3596 | |
594f8779 RZ |
3597 | #ifdef AUTO_INC_DEC |
3598 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3599 | ||
3600 | static int | |
9021b8ec | 3601 | find_auto_inc (const_rtx x, const_rtx reg) |
594f8779 | 3602 | { |
9021b8ec RS |
3603 | subrtx_iterator::array_type array; |
3604 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
594f8779 | 3605 | { |
9021b8ec RS |
3606 | const_rtx x = *iter; |
3607 | if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC | |
3608 | && rtx_equal_p (reg, XEXP (x, 0))) | |
3609 | return true; | |
594f8779 | 3610 | } |
9021b8ec | 3611 | return false; |
594f8779 RZ |
3612 | } |
3613 | #endif | |
3614 | ||
e5bef2e4 HB |
3615 | /* Increment the label uses for all labels present in rtx. */ |
3616 | ||
3617 | static void | |
502b8322 | 3618 | mark_label_nuses (rtx x) |
e5bef2e4 | 3619 | { |
b3694847 SS |
3620 | enum rtx_code code; |
3621 | int i, j; | |
3622 | const char *fmt; | |
e5bef2e4 HB |
3623 | |
3624 | code = GET_CODE (x); | |
a827d9b1 DM |
3625 | if (code == LABEL_REF && LABEL_P (LABEL_REF_LABEL (x))) |
3626 | LABEL_NUSES (LABEL_REF_LABEL (x))++; | |
e5bef2e4 HB |
3627 | |
3628 | fmt = GET_RTX_FORMAT (code); | |
3629 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3630 | { | |
3631 | if (fmt[i] == 'e') | |
0fb7aeda | 3632 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3633 | else if (fmt[i] == 'E') |
0fb7aeda | 3634 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3635 | mark_label_nuses (XVECEXP (x, i, j)); |
3636 | } | |
3637 | } | |
3638 | ||
23b2ce53 RS |
3639 | \f |
3640 | /* Try splitting insns that can be split for better scheduling. | |
3641 | PAT is the pattern which might split. | |
3642 | TRIAL is the insn providing PAT. | |
cc2902df | 3643 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3644 | |
3645 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3646 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3647 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3648 | ||
53f04688 | 3649 | rtx_insn * |
bb5c4956 | 3650 | try_split (rtx pat, rtx_insn *trial, int last) |
23b2ce53 | 3651 | { |
53f04688 DM |
3652 | rtx_insn *before = PREV_INSN (trial); |
3653 | rtx_insn *after = NEXT_INSN (trial); | |
dc01c3d1 DM |
3654 | rtx note; |
3655 | rtx_insn *seq, *tem; | |
6b24c259 | 3656 | int probability; |
dc01c3d1 | 3657 | rtx_insn *insn_last, *insn; |
599aedd9 | 3658 | int njumps = 0; |
e67d1102 | 3659 | rtx_insn *call_insn = NULL; |
6b24c259 | 3660 | |
cd9c1ca8 RH |
3661 | /* We're not good at redistributing frame information. */ |
3662 | if (RTX_FRAME_RELATED_P (trial)) | |
dc01c3d1 | 3663 | return trial; |
cd9c1ca8 | 3664 | |
6b24c259 JH |
3665 | if (any_condjump_p (trial) |
3666 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
e5af9ddd | 3667 | split_branch_probability = XINT (note, 0); |
6b24c259 JH |
3668 | probability = split_branch_probability; |
3669 | ||
bb5c4956 | 3670 | seq = split_insns (pat, trial); |
6b24c259 JH |
3671 | |
3672 | split_branch_probability = -1; | |
23b2ce53 | 3673 | |
599aedd9 | 3674 | if (!seq) |
dc01c3d1 | 3675 | return trial; |
599aedd9 RH |
3676 | |
3677 | /* Avoid infinite loop if any insn of the result matches | |
3678 | the original pattern. */ | |
3679 | insn_last = seq; | |
3680 | while (1) | |
23b2ce53 | 3681 | { |
599aedd9 RH |
3682 | if (INSN_P (insn_last) |
3683 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
dc01c3d1 | 3684 | return trial; |
599aedd9 RH |
3685 | if (!NEXT_INSN (insn_last)) |
3686 | break; | |
3687 | insn_last = NEXT_INSN (insn_last); | |
3688 | } | |
750c9258 | 3689 | |
6fb5fa3c DB |
3690 | /* We will be adding the new sequence to the function. The splitters |
3691 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3692 | unshare_all_rtl_in_chain (seq); | |
3693 | ||
339ba33b | 3694 | /* Mark labels and copy flags. */ |
599aedd9 RH |
3695 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) |
3696 | { | |
4b4bf941 | 3697 | if (JUMP_P (insn)) |
599aedd9 | 3698 | { |
339ba33b RS |
3699 | if (JUMP_P (trial)) |
3700 | CROSSING_JUMP_P (insn) = CROSSING_JUMP_P (trial); | |
599aedd9 RH |
3701 | mark_jump_label (PATTERN (insn), insn, 0); |
3702 | njumps++; | |
3703 | if (probability != -1 | |
3704 | && any_condjump_p (insn) | |
3705 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3706 | { |
599aedd9 RH |
3707 | /* We can preserve the REG_BR_PROB notes only if exactly |
3708 | one jump is created, otherwise the machine description | |
3709 | is responsible for this step using | |
3710 | split_branch_probability variable. */ | |
5b0264cb | 3711 | gcc_assert (njumps == 1); |
e5af9ddd | 3712 | add_int_reg_note (insn, REG_BR_PROB, probability); |
2f937369 | 3713 | } |
599aedd9 RH |
3714 | } |
3715 | } | |
3716 | ||
3717 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
65712d5c | 3718 | in SEQ and copy any additional information across. */ |
4b4bf941 | 3719 | if (CALL_P (trial)) |
599aedd9 RH |
3720 | { |
3721 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3722 | if (CALL_P (insn)) |
599aedd9 | 3723 | { |
dc01c3d1 DM |
3724 | rtx_insn *next; |
3725 | rtx *p; | |
65712d5c | 3726 | |
4f660b15 RO |
3727 | gcc_assert (call_insn == NULL_RTX); |
3728 | call_insn = insn; | |
3729 | ||
65712d5c RS |
3730 | /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the |
3731 | target may have explicitly specified. */ | |
3732 | p = &CALL_INSN_FUNCTION_USAGE (insn); | |
f6a1f3f6 RH |
3733 | while (*p) |
3734 | p = &XEXP (*p, 1); | |
3735 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
65712d5c RS |
3736 | |
3737 | /* If the old call was a sibling call, the new one must | |
3738 | be too. */ | |
599aedd9 | 3739 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
65712d5c RS |
3740 | |
3741 | /* If the new call is the last instruction in the sequence, | |
3742 | it will effectively replace the old call in-situ. Otherwise | |
3743 | we must move any following NOTE_INSN_CALL_ARG_LOCATION note | |
3744 | so that it comes immediately after the new call. */ | |
3745 | if (NEXT_INSN (insn)) | |
65f3dedb RS |
3746 | for (next = NEXT_INSN (trial); |
3747 | next && NOTE_P (next); | |
3748 | next = NEXT_INSN (next)) | |
3749 | if (NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) | |
65712d5c RS |
3750 | { |
3751 | remove_insn (next); | |
3752 | add_insn_after (next, insn, NULL); | |
65f3dedb | 3753 | break; |
65712d5c | 3754 | } |
599aedd9 RH |
3755 | } |
3756 | } | |
4b5e8abe | 3757 | |
599aedd9 RH |
3758 | /* Copy notes, particularly those related to the CFG. */ |
3759 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3760 | { | |
3761 | switch (REG_NOTE_KIND (note)) | |
3762 | { | |
3763 | case REG_EH_REGION: | |
1d65f45c | 3764 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3765 | break; |
216183ce | 3766 | |
599aedd9 RH |
3767 | case REG_NORETURN: |
3768 | case REG_SETJMP: | |
0a35513e | 3769 | case REG_TM: |
594f8779 | 3770 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3771 | { |
4b4bf941 | 3772 | if (CALL_P (insn)) |
65c5f2a6 | 3773 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3774 | } |
599aedd9 | 3775 | break; |
d6e95df8 | 3776 | |
599aedd9 | 3777 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3778 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3779 | { |
4b4bf941 | 3780 | if (JUMP_P (insn)) |
65c5f2a6 | 3781 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3782 | } |
599aedd9 | 3783 | break; |
e5bef2e4 | 3784 | |
594f8779 RZ |
3785 | #ifdef AUTO_INC_DEC |
3786 | case REG_INC: | |
3787 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3788 | { | |
3789 | rtx reg = XEXP (note, 0); | |
3790 | if (!FIND_REG_INC_NOTE (insn, reg) | |
9021b8ec | 3791 | && find_auto_inc (PATTERN (insn), reg)) |
65c5f2a6 | 3792 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3793 | } |
3794 | break; | |
3795 | #endif | |
3796 | ||
9a08d230 | 3797 | case REG_ARGS_SIZE: |
e5b51ca0 | 3798 | fixup_args_size_notes (NULL, insn_last, INTVAL (XEXP (note, 0))); |
9a08d230 RH |
3799 | break; |
3800 | ||
4f660b15 RO |
3801 | case REG_CALL_DECL: |
3802 | gcc_assert (call_insn != NULL_RTX); | |
3803 | add_reg_note (call_insn, REG_NOTE_KIND (note), XEXP (note, 0)); | |
3804 | break; | |
3805 | ||
599aedd9 RH |
3806 | default: |
3807 | break; | |
23b2ce53 | 3808 | } |
599aedd9 RH |
3809 | } |
3810 | ||
3811 | /* If there are LABELS inside the split insns increment the | |
3812 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3813 | if (INSN_P (trial)) |
599aedd9 RH |
3814 | { |
3815 | insn = insn_last; | |
3816 | while (insn != NULL_RTX) | |
23b2ce53 | 3817 | { |
cf7c4aa6 | 3818 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3819 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3820 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3821 | |
599aedd9 RH |
3822 | insn = PREV_INSN (insn); |
3823 | } | |
23b2ce53 RS |
3824 | } |
3825 | ||
5368224f | 3826 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATION (trial)); |
599aedd9 RH |
3827 | |
3828 | delete_insn (trial); | |
599aedd9 RH |
3829 | |
3830 | /* Recursively call try_split for each new insn created; by the | |
3831 | time control returns here that insn will be fully split, so | |
3832 | set LAST and continue from the insn after the one returned. | |
3833 | We can't use next_active_insn here since AFTER may be a note. | |
3834 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3835 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
4654c0cf | 3836 | if (! tem->deleted () && INSN_P (tem)) |
599aedd9 RH |
3837 | tem = try_split (PATTERN (tem), tem, 1); |
3838 | ||
3839 | /* Return either the first or the last insn, depending on which was | |
3840 | requested. */ | |
3841 | return last | |
5936d944 | 3842 | ? (after ? PREV_INSN (after) : get_last_insn ()) |
599aedd9 | 3843 | : NEXT_INSN (before); |
23b2ce53 RS |
3844 | } |
3845 | \f | |
3846 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3847 | Store PATTERN in the pattern slots. */ |
23b2ce53 | 3848 | |
167b9fae | 3849 | rtx_insn * |
502b8322 | 3850 | make_insn_raw (rtx pattern) |
23b2ce53 | 3851 | { |
167b9fae | 3852 | rtx_insn *insn; |
23b2ce53 | 3853 | |
167b9fae | 3854 | insn = as_a <rtx_insn *> (rtx_alloc (INSN)); |
23b2ce53 | 3855 | |
43127294 | 3856 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3857 | PATTERN (insn) = pattern; |
3858 | INSN_CODE (insn) = -1; | |
1632afca | 3859 | REG_NOTES (insn) = NULL; |
5368224f | 3860 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3861 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3862 | |
47984720 NC |
3863 | #ifdef ENABLE_RTL_CHECKING |
3864 | if (insn | |
2c3c49de | 3865 | && INSN_P (insn) |
47984720 NC |
3866 | && (returnjump_p (insn) |
3867 | || (GET_CODE (insn) == SET | |
3868 | && SET_DEST (insn) == pc_rtx))) | |
3869 | { | |
d4ee4d25 | 3870 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3871 | debug_rtx (insn); |
3872 | } | |
3873 | #endif | |
750c9258 | 3874 | |
23b2ce53 RS |
3875 | return insn; |
3876 | } | |
3877 | ||
b5b8b0ac AO |
3878 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
3879 | ||
167b9fae | 3880 | static rtx_insn * |
b5b8b0ac AO |
3881 | make_debug_insn_raw (rtx pattern) |
3882 | { | |
167b9fae | 3883 | rtx_debug_insn *insn; |
b5b8b0ac | 3884 | |
167b9fae | 3885 | insn = as_a <rtx_debug_insn *> (rtx_alloc (DEBUG_INSN)); |
b5b8b0ac AO |
3886 | INSN_UID (insn) = cur_debug_insn_uid++; |
3887 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3888 | INSN_UID (insn) = cur_insn_uid++; | |
3889 | ||
3890 | PATTERN (insn) = pattern; | |
3891 | INSN_CODE (insn) = -1; | |
3892 | REG_NOTES (insn) = NULL; | |
5368224f | 3893 | INSN_LOCATION (insn) = curr_insn_location (); |
b5b8b0ac AO |
3894 | BLOCK_FOR_INSN (insn) = NULL; |
3895 | ||
3896 | return insn; | |
3897 | } | |
3898 | ||
2f937369 | 3899 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3900 | |
167b9fae | 3901 | static rtx_insn * |
502b8322 | 3902 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3903 | { |
167b9fae | 3904 | rtx_jump_insn *insn; |
23b2ce53 | 3905 | |
167b9fae | 3906 | insn = as_a <rtx_jump_insn *> (rtx_alloc (JUMP_INSN)); |
1632afca | 3907 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3908 | |
3909 | PATTERN (insn) = pattern; | |
3910 | INSN_CODE (insn) = -1; | |
1632afca RS |
3911 | REG_NOTES (insn) = NULL; |
3912 | JUMP_LABEL (insn) = NULL; | |
5368224f | 3913 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3914 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3915 | |
3916 | return insn; | |
3917 | } | |
aff507f4 | 3918 | |
2f937369 | 3919 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 | 3920 | |
167b9fae | 3921 | static rtx_insn * |
502b8322 | 3922 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3923 | { |
167b9fae | 3924 | rtx_call_insn *insn; |
aff507f4 | 3925 | |
167b9fae | 3926 | insn = as_a <rtx_call_insn *> (rtx_alloc (CALL_INSN)); |
aff507f4 RK |
3927 | INSN_UID (insn) = cur_insn_uid++; |
3928 | ||
3929 | PATTERN (insn) = pattern; | |
3930 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3931 | REG_NOTES (insn) = NULL; |
3932 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
5368224f | 3933 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3934 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3935 | |
3936 | return insn; | |
3937 | } | |
96fba521 SB |
3938 | |
3939 | /* Like `make_insn_raw' but make a NOTE instead of an insn. */ | |
3940 | ||
66e8df53 | 3941 | static rtx_note * |
96fba521 SB |
3942 | make_note_raw (enum insn_note subtype) |
3943 | { | |
3944 | /* Some notes are never created this way at all. These notes are | |
3945 | only created by patching out insns. */ | |
3946 | gcc_assert (subtype != NOTE_INSN_DELETED_LABEL | |
3947 | && subtype != NOTE_INSN_DELETED_DEBUG_LABEL); | |
3948 | ||
66e8df53 | 3949 | rtx_note *note = as_a <rtx_note *> (rtx_alloc (NOTE)); |
96fba521 SB |
3950 | INSN_UID (note) = cur_insn_uid++; |
3951 | NOTE_KIND (note) = subtype; | |
3952 | BLOCK_FOR_INSN (note) = NULL; | |
3953 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); | |
3954 | return note; | |
3955 | } | |
23b2ce53 | 3956 | \f |
96fba521 SB |
3957 | /* Add INSN to the end of the doubly-linked list, between PREV and NEXT. |
3958 | INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects, | |
3959 | but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */ | |
3960 | ||
3961 | static inline void | |
9152e0aa | 3962 | link_insn_into_chain (rtx_insn *insn, rtx_insn *prev, rtx_insn *next) |
96fba521 | 3963 | { |
0f82e5c9 DM |
3964 | SET_PREV_INSN (insn) = prev; |
3965 | SET_NEXT_INSN (insn) = next; | |
96fba521 SB |
3966 | if (prev != NULL) |
3967 | { | |
0f82e5c9 | 3968 | SET_NEXT_INSN (prev) = insn; |
96fba521 SB |
3969 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
3970 | { | |
e6eda746 DM |
3971 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
3972 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = insn; | |
96fba521 SB |
3973 | } |
3974 | } | |
3975 | if (next != NULL) | |
3976 | { | |
0f82e5c9 | 3977 | SET_PREV_INSN (next) = insn; |
96fba521 | 3978 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
3979 | { |
3980 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
3981 | SET_PREV_INSN (sequence->insn (0)) = insn; | |
3982 | } | |
96fba521 | 3983 | } |
3ccb989e SB |
3984 | |
3985 | if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3986 | { | |
e6eda746 DM |
3987 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (insn)); |
3988 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
3989 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
3ccb989e | 3990 | } |
96fba521 SB |
3991 | } |
3992 | ||
23b2ce53 RS |
3993 | /* Add INSN to the end of the doubly-linked list. |
3994 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3995 | ||
3996 | void | |
9152e0aa | 3997 | add_insn (rtx_insn *insn) |
23b2ce53 | 3998 | { |
9152e0aa | 3999 | rtx_insn *prev = get_last_insn (); |
96fba521 | 4000 | link_insn_into_chain (insn, prev, NULL); |
5936d944 JH |
4001 | if (NULL == get_insns ()) |
4002 | set_first_insn (insn); | |
5936d944 | 4003 | set_last_insn (insn); |
23b2ce53 RS |
4004 | } |
4005 | ||
96fba521 | 4006 | /* Add INSN into the doubly-linked list after insn AFTER. */ |
23b2ce53 | 4007 | |
96fba521 | 4008 | static void |
9152e0aa | 4009 | add_insn_after_nobb (rtx_insn *insn, rtx_insn *after) |
23b2ce53 | 4010 | { |
9152e0aa | 4011 | rtx_insn *next = NEXT_INSN (after); |
23b2ce53 | 4012 | |
4654c0cf | 4013 | gcc_assert (!optimize || !after->deleted ()); |
ba213285 | 4014 | |
96fba521 | 4015 | link_insn_into_chain (insn, after, next); |
23b2ce53 | 4016 | |
96fba521 | 4017 | if (next == NULL) |
23b2ce53 | 4018 | { |
614d5bd8 AM |
4019 | struct sequence_stack *seq; |
4020 | ||
4021 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4022 | if (after == seq->last) | |
4023 | { | |
4024 | seq->last = insn; | |
4025 | break; | |
4026 | } | |
23b2ce53 | 4027 | } |
96fba521 SB |
4028 | } |
4029 | ||
4030 | /* Add INSN into the doubly-linked list before insn BEFORE. */ | |
4031 | ||
4032 | static void | |
9152e0aa | 4033 | add_insn_before_nobb (rtx_insn *insn, rtx_insn *before) |
96fba521 | 4034 | { |
9152e0aa | 4035 | rtx_insn *prev = PREV_INSN (before); |
96fba521 | 4036 | |
4654c0cf | 4037 | gcc_assert (!optimize || !before->deleted ()); |
96fba521 SB |
4038 | |
4039 | link_insn_into_chain (insn, prev, before); | |
4040 | ||
4041 | if (prev == NULL) | |
23b2ce53 | 4042 | { |
614d5bd8 | 4043 | struct sequence_stack *seq; |
a0ae8e8d | 4044 | |
614d5bd8 AM |
4045 | for (seq = get_current_sequence (); seq; seq = seq->next) |
4046 | if (before == seq->first) | |
4047 | { | |
4048 | seq->first = insn; | |
4049 | break; | |
4050 | } | |
4051 | ||
4052 | gcc_assert (seq); | |
23b2ce53 | 4053 | } |
96fba521 SB |
4054 | } |
4055 | ||
4056 | /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN. | |
4057 | If BB is NULL, an attempt is made to infer the bb from before. | |
4058 | ||
4059 | This and the next function should be the only functions called | |
4060 | to insert an insn once delay slots have been filled since only | |
4061 | they know how to update a SEQUENCE. */ | |
23b2ce53 | 4062 | |
96fba521 | 4063 | void |
9152e0aa | 4064 | add_insn_after (rtx uncast_insn, rtx uncast_after, basic_block bb) |
96fba521 | 4065 | { |
1130d5e3 | 4066 | rtx_insn *insn = as_a <rtx_insn *> (uncast_insn); |
9152e0aa | 4067 | rtx_insn *after = as_a <rtx_insn *> (uncast_after); |
96fba521 | 4068 | add_insn_after_nobb (insn, after); |
4b4bf941 JQ |
4069 | if (!BARRIER_P (after) |
4070 | && !BARRIER_P (insn) | |
3c030e88 JH |
4071 | && (bb = BLOCK_FOR_INSN (after))) |
4072 | { | |
4073 | set_block_for_insn (insn, bb); | |
38c1593d | 4074 | if (INSN_P (insn)) |
6fb5fa3c | 4075 | df_insn_rescan (insn); |
3c030e88 | 4076 | /* Should not happen as first in the BB is always |
a1f300c0 | 4077 | either NOTE or LABEL. */ |
a813c111 | 4078 | if (BB_END (bb) == after |
3c030e88 | 4079 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 4080 | && !BARRIER_P (insn) |
a38e7aa5 | 4081 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
1130d5e3 | 4082 | BB_END (bb) = insn; |
3c030e88 | 4083 | } |
23b2ce53 RS |
4084 | } |
4085 | ||
96fba521 SB |
4086 | /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN. |
4087 | If BB is NULL, an attempt is made to infer the bb from before. | |
4088 | ||
4089 | This and the previous function should be the only functions called | |
4090 | to insert an insn once delay slots have been filled since only | |
4091 | they know how to update a SEQUENCE. */ | |
a0ae8e8d RK |
4092 | |
4093 | void | |
9152e0aa | 4094 | add_insn_before (rtx uncast_insn, rtx uncast_before, basic_block bb) |
a0ae8e8d | 4095 | { |
9152e0aa DM |
4096 | rtx_insn *insn = as_a <rtx_insn *> (uncast_insn); |
4097 | rtx_insn *before = as_a <rtx_insn *> (uncast_before); | |
96fba521 | 4098 | add_insn_before_nobb (insn, before); |
a0ae8e8d | 4099 | |
b8698a0f | 4100 | if (!bb |
6fb5fa3c DB |
4101 | && !BARRIER_P (before) |
4102 | && !BARRIER_P (insn)) | |
4103 | bb = BLOCK_FOR_INSN (before); | |
4104 | ||
4105 | if (bb) | |
3c030e88 JH |
4106 | { |
4107 | set_block_for_insn (insn, bb); | |
38c1593d | 4108 | if (INSN_P (insn)) |
6fb5fa3c | 4109 | df_insn_rescan (insn); |
5b0264cb | 4110 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 4111 | LABEL. */ |
5b0264cb NS |
4112 | gcc_assert (BB_HEAD (bb) != insn |
4113 | /* Avoid clobbering of structure when creating new BB. */ | |
4114 | || BARRIER_P (insn) | |
a38e7aa5 | 4115 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 | 4116 | } |
a0ae8e8d RK |
4117 | } |
4118 | ||
6fb5fa3c DB |
4119 | /* Replace insn with an deleted instruction note. */ |
4120 | ||
0ce2b299 EB |
4121 | void |
4122 | set_insn_deleted (rtx insn) | |
6fb5fa3c | 4123 | { |
39718607 | 4124 | if (INSN_P (insn)) |
b2908ba6 | 4125 | df_insn_delete (as_a <rtx_insn *> (insn)); |
6fb5fa3c DB |
4126 | PUT_CODE (insn, NOTE); |
4127 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
4128 | } | |
4129 | ||
4130 | ||
1f397f45 SB |
4131 | /* Unlink INSN from the insn chain. |
4132 | ||
4133 | This function knows how to handle sequences. | |
4134 | ||
4135 | This function does not invalidate data flow information associated with | |
4136 | INSN (i.e. does not call df_insn_delete). That makes this function | |
4137 | usable for only disconnecting an insn from the chain, and re-emit it | |
4138 | elsewhere later. | |
4139 | ||
4140 | To later insert INSN elsewhere in the insn chain via add_insn and | |
4141 | similar functions, PREV_INSN and NEXT_INSN must be nullified by | |
4142 | the caller. Nullifying them here breaks many insn chain walks. | |
4143 | ||
4144 | To really delete an insn and related DF information, use delete_insn. */ | |
4145 | ||
89e99eea | 4146 | void |
dc01c3d1 | 4147 | remove_insn (rtx uncast_insn) |
89e99eea | 4148 | { |
dc01c3d1 | 4149 | rtx_insn *insn = as_a <rtx_insn *> (uncast_insn); |
1130d5e3 DM |
4150 | rtx_insn *next = NEXT_INSN (insn); |
4151 | rtx_insn *prev = PREV_INSN (insn); | |
53c17031 JH |
4152 | basic_block bb; |
4153 | ||
89e99eea DB |
4154 | if (prev) |
4155 | { | |
0f82e5c9 | 4156 | SET_NEXT_INSN (prev) = next; |
4b4bf941 | 4157 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea | 4158 | { |
e6eda746 DM |
4159 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4160 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
89e99eea DB |
4161 | } |
4162 | } | |
89e99eea DB |
4163 | else |
4164 | { | |
614d5bd8 AM |
4165 | struct sequence_stack *seq; |
4166 | ||
4167 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4168 | if (insn == seq->first) | |
89e99eea | 4169 | { |
614d5bd8 | 4170 | seq->first = next; |
89e99eea DB |
4171 | break; |
4172 | } | |
4173 | ||
614d5bd8 | 4174 | gcc_assert (seq); |
89e99eea DB |
4175 | } |
4176 | ||
4177 | if (next) | |
4178 | { | |
0f82e5c9 | 4179 | SET_PREV_INSN (next) = prev; |
4b4bf941 | 4180 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4181 | { |
4182 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4183 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4184 | } | |
89e99eea | 4185 | } |
89e99eea DB |
4186 | else |
4187 | { | |
614d5bd8 AM |
4188 | struct sequence_stack *seq; |
4189 | ||
4190 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4191 | if (insn == seq->last) | |
89e99eea | 4192 | { |
614d5bd8 | 4193 | seq->last = prev; |
89e99eea DB |
4194 | break; |
4195 | } | |
4196 | ||
614d5bd8 | 4197 | gcc_assert (seq); |
89e99eea | 4198 | } |
80eb8028 | 4199 | |
80eb8028 | 4200 | /* Fix up basic block boundaries, if necessary. */ |
4b4bf941 | 4201 | if (!BARRIER_P (insn) |
53c17031 JH |
4202 | && (bb = BLOCK_FOR_INSN (insn))) |
4203 | { | |
a813c111 | 4204 | if (BB_HEAD (bb) == insn) |
53c17031 | 4205 | { |
3bf1e984 RK |
4206 | /* Never ever delete the basic block note without deleting whole |
4207 | basic block. */ | |
5b0264cb | 4208 | gcc_assert (!NOTE_P (insn)); |
1130d5e3 | 4209 | BB_HEAD (bb) = next; |
53c17031 | 4210 | } |
a813c111 | 4211 | if (BB_END (bb) == insn) |
1130d5e3 | 4212 | BB_END (bb) = prev; |
53c17031 | 4213 | } |
89e99eea DB |
4214 | } |
4215 | ||
ee960939 OH |
4216 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
4217 | ||
4218 | void | |
502b8322 | 4219 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 4220 | { |
5b0264cb | 4221 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
4222 | |
4223 | /* Put the register usage information on the CALL. If there is already | |
4224 | some usage information, put ours at the end. */ | |
4225 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
4226 | { | |
4227 | rtx link; | |
4228 | ||
4229 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
4230 | link = XEXP (link, 1)) | |
4231 | ; | |
4232 | ||
4233 | XEXP (link, 1) = call_fusage; | |
4234 | } | |
4235 | else | |
4236 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
4237 | } | |
4238 | ||
23b2ce53 RS |
4239 | /* Delete all insns made since FROM. |
4240 | FROM becomes the new last instruction. */ | |
4241 | ||
4242 | void | |
fee3e72c | 4243 | delete_insns_since (rtx_insn *from) |
23b2ce53 RS |
4244 | { |
4245 | if (from == 0) | |
5936d944 | 4246 | set_first_insn (0); |
23b2ce53 | 4247 | else |
0f82e5c9 | 4248 | SET_NEXT_INSN (from) = 0; |
5936d944 | 4249 | set_last_insn (from); |
23b2ce53 RS |
4250 | } |
4251 | ||
5dab5552 MS |
4252 | /* This function is deprecated, please use sequences instead. |
4253 | ||
4254 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
4255 | The insns to be moved are those between FROM and TO. |
4256 | They are moved to a new position after the insn AFTER. | |
4257 | AFTER must not be FROM or TO or any insn in between. | |
4258 | ||
4259 | This function does not know about SEQUENCEs and hence should not be | |
4260 | called after delay-slot filling has been done. */ | |
4261 | ||
4262 | void | |
fee3e72c | 4263 | reorder_insns_nobb (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
23b2ce53 | 4264 | { |
4f8344eb | 4265 | #ifdef ENABLE_CHECKING |
fee3e72c | 4266 | rtx_insn *x; |
4f8344eb HPN |
4267 | for (x = from; x != to; x = NEXT_INSN (x)) |
4268 | gcc_assert (after != x); | |
4269 | gcc_assert (after != to); | |
4270 | #endif | |
4271 | ||
23b2ce53 RS |
4272 | /* Splice this bunch out of where it is now. */ |
4273 | if (PREV_INSN (from)) | |
0f82e5c9 | 4274 | SET_NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); |
23b2ce53 | 4275 | if (NEXT_INSN (to)) |
0f82e5c9 | 4276 | SET_PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); |
5936d944 JH |
4277 | if (get_last_insn () == to) |
4278 | set_last_insn (PREV_INSN (from)); | |
4279 | if (get_insns () == from) | |
4280 | set_first_insn (NEXT_INSN (to)); | |
23b2ce53 RS |
4281 | |
4282 | /* Make the new neighbors point to it and it to them. */ | |
4283 | if (NEXT_INSN (after)) | |
0f82e5c9 | 4284 | SET_PREV_INSN (NEXT_INSN (after)) = to; |
23b2ce53 | 4285 | |
0f82e5c9 DM |
4286 | SET_NEXT_INSN (to) = NEXT_INSN (after); |
4287 | SET_PREV_INSN (from) = after; | |
4288 | SET_NEXT_INSN (after) = from; | |
c3284718 | 4289 | if (after == get_last_insn ()) |
5936d944 | 4290 | set_last_insn (to); |
23b2ce53 RS |
4291 | } |
4292 | ||
3c030e88 JH |
4293 | /* Same as function above, but take care to update BB boundaries. */ |
4294 | void | |
ac9d2d2c | 4295 | reorder_insns (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
3c030e88 | 4296 | { |
ac9d2d2c | 4297 | rtx_insn *prev = PREV_INSN (from); |
3c030e88 JH |
4298 | basic_block bb, bb2; |
4299 | ||
4300 | reorder_insns_nobb (from, to, after); | |
4301 | ||
4b4bf941 | 4302 | if (!BARRIER_P (after) |
3c030e88 JH |
4303 | && (bb = BLOCK_FOR_INSN (after))) |
4304 | { | |
b2908ba6 | 4305 | rtx_insn *x; |
6fb5fa3c | 4306 | df_set_bb_dirty (bb); |
68252e27 | 4307 | |
4b4bf941 | 4308 | if (!BARRIER_P (from) |
3c030e88 JH |
4309 | && (bb2 = BLOCK_FOR_INSN (from))) |
4310 | { | |
a813c111 | 4311 | if (BB_END (bb2) == to) |
1130d5e3 | 4312 | BB_END (bb2) = prev; |
6fb5fa3c | 4313 | df_set_bb_dirty (bb2); |
3c030e88 JH |
4314 | } |
4315 | ||
a813c111 | 4316 | if (BB_END (bb) == after) |
1130d5e3 | 4317 | BB_END (bb) = to; |
3c030e88 JH |
4318 | |
4319 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 4320 | if (!BARRIER_P (x)) |
63642d5a | 4321 | df_insn_change_bb (x, bb); |
3c030e88 JH |
4322 | } |
4323 | } | |
4324 | ||
23b2ce53 | 4325 | \f |
2f937369 DM |
4326 | /* Emit insn(s) of given code and pattern |
4327 | at a specified place within the doubly-linked list. | |
23b2ce53 | 4328 | |
2f937369 DM |
4329 | All of the emit_foo global entry points accept an object |
4330 | X which is either an insn list or a PATTERN of a single | |
4331 | instruction. | |
23b2ce53 | 4332 | |
2f937369 DM |
4333 | There are thus a few canonical ways to generate code and |
4334 | emit it at a specific place in the instruction stream. For | |
4335 | example, consider the instruction named SPOT and the fact that | |
4336 | we would like to emit some instructions before SPOT. We might | |
4337 | do it like this: | |
23b2ce53 | 4338 | |
2f937369 DM |
4339 | start_sequence (); |
4340 | ... emit the new instructions ... | |
4341 | insns_head = get_insns (); | |
4342 | end_sequence (); | |
23b2ce53 | 4343 | |
2f937369 | 4344 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4345 | |
2f937369 DM |
4346 | It used to be common to generate SEQUENCE rtl instead, but that |
4347 | is a relic of the past which no longer occurs. The reason is that | |
4348 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4349 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4350 | |
cd459bf8 | 4351 | static rtx_insn * |
5f02387d | 4352 | emit_pattern_before_noloc (rtx x, rtx before, rtx last, basic_block bb, |
167b9fae | 4353 | rtx_insn *(*make_raw) (rtx)) |
23b2ce53 | 4354 | { |
167b9fae | 4355 | rtx_insn *insn; |
23b2ce53 | 4356 | |
5b0264cb | 4357 | gcc_assert (before); |
2f937369 DM |
4358 | |
4359 | if (x == NULL_RTX) | |
cd459bf8 | 4360 | return safe_as_a <rtx_insn *> (last); |
2f937369 DM |
4361 | |
4362 | switch (GET_CODE (x)) | |
23b2ce53 | 4363 | { |
b5b8b0ac | 4364 | case DEBUG_INSN: |
2f937369 DM |
4365 | case INSN: |
4366 | case JUMP_INSN: | |
4367 | case CALL_INSN: | |
4368 | case CODE_LABEL: | |
4369 | case BARRIER: | |
4370 | case NOTE: | |
167b9fae | 4371 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
4372 | while (insn) |
4373 | { | |
167b9fae | 4374 | rtx_insn *next = NEXT_INSN (insn); |
6fb5fa3c | 4375 | add_insn_before (insn, before, bb); |
2f937369 DM |
4376 | last = insn; |
4377 | insn = next; | |
4378 | } | |
4379 | break; | |
4380 | ||
4381 | #ifdef ENABLE_RTL_CHECKING | |
4382 | case SEQUENCE: | |
5b0264cb | 4383 | gcc_unreachable (); |
2f937369 DM |
4384 | break; |
4385 | #endif | |
4386 | ||
4387 | default: | |
5f02387d | 4388 | last = (*make_raw) (x); |
6fb5fa3c | 4389 | add_insn_before (last, before, bb); |
2f937369 | 4390 | break; |
23b2ce53 RS |
4391 | } |
4392 | ||
cd459bf8 | 4393 | return safe_as_a <rtx_insn *> (last); |
23b2ce53 RS |
4394 | } |
4395 | ||
5f02387d NF |
4396 | /* Make X be output before the instruction BEFORE. */ |
4397 | ||
cd459bf8 | 4398 | rtx_insn * |
596f2b17 | 4399 | emit_insn_before_noloc (rtx x, rtx_insn *before, basic_block bb) |
5f02387d NF |
4400 | { |
4401 | return emit_pattern_before_noloc (x, before, before, bb, make_insn_raw); | |
4402 | } | |
4403 | ||
2f937369 | 4404 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4405 | and output it before the instruction BEFORE. */ |
4406 | ||
1476d1bd | 4407 | rtx_jump_insn * |
596f2b17 | 4408 | emit_jump_insn_before_noloc (rtx x, rtx_insn *before) |
23b2ce53 | 4409 | { |
1476d1bd MM |
4410 | return as_a <rtx_jump_insn *> ( |
4411 | emit_pattern_before_noloc (x, before, NULL_RTX, NULL, | |
4412 | make_jump_insn_raw)); | |
23b2ce53 RS |
4413 | } |
4414 | ||
2f937369 | 4415 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4416 | and output it before the instruction BEFORE. */ |
4417 | ||
cd459bf8 | 4418 | rtx_insn * |
596f2b17 | 4419 | emit_call_insn_before_noloc (rtx x, rtx_insn *before) |
969d70ca | 4420 | { |
5f02387d NF |
4421 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4422 | make_call_insn_raw); | |
969d70ca JH |
4423 | } |
4424 | ||
b5b8b0ac AO |
4425 | /* Make an instruction with body X and code DEBUG_INSN |
4426 | and output it before the instruction BEFORE. */ | |
4427 | ||
cd459bf8 | 4428 | rtx_insn * |
b5b8b0ac AO |
4429 | emit_debug_insn_before_noloc (rtx x, rtx before) |
4430 | { | |
5f02387d NF |
4431 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4432 | make_debug_insn_raw); | |
b5b8b0ac AO |
4433 | } |
4434 | ||
23b2ce53 | 4435 | /* Make an insn of code BARRIER |
e881bb1b | 4436 | and output it before the insn BEFORE. */ |
23b2ce53 | 4437 | |
cd459bf8 | 4438 | rtx_barrier * |
502b8322 | 4439 | emit_barrier_before (rtx before) |
23b2ce53 | 4440 | { |
cd459bf8 | 4441 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4442 | |
4443 | INSN_UID (insn) = cur_insn_uid++; | |
4444 | ||
6fb5fa3c | 4445 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4446 | return insn; |
4447 | } | |
4448 | ||
e881bb1b RH |
4449 | /* Emit the label LABEL before the insn BEFORE. */ |
4450 | ||
1476d1bd | 4451 | rtx_code_label * |
596f2b17 | 4452 | emit_label_before (rtx label, rtx_insn *before) |
e881bb1b | 4453 | { |
468660d3 SB |
4454 | gcc_checking_assert (INSN_UID (label) == 0); |
4455 | INSN_UID (label) = cur_insn_uid++; | |
4456 | add_insn_before (label, before, NULL); | |
1476d1bd | 4457 | return as_a <rtx_code_label *> (label); |
e881bb1b | 4458 | } |
23b2ce53 | 4459 | \f |
2f937369 DM |
4460 | /* Helper for emit_insn_after, handles lists of instructions |
4461 | efficiently. */ | |
23b2ce53 | 4462 | |
e6eda746 DM |
4463 | static rtx_insn * |
4464 | emit_insn_after_1 (rtx_insn *first, rtx uncast_after, basic_block bb) | |
23b2ce53 | 4465 | { |
e6eda746 | 4466 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
1130d5e3 DM |
4467 | rtx_insn *last; |
4468 | rtx_insn *after_after; | |
6fb5fa3c DB |
4469 | if (!bb && !BARRIER_P (after)) |
4470 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4471 | |
6fb5fa3c | 4472 | if (bb) |
23b2ce53 | 4473 | { |
6fb5fa3c | 4474 | df_set_bb_dirty (bb); |
2f937369 | 4475 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4476 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4477 | { |
4478 | set_block_for_insn (last, bb); | |
4479 | df_insn_rescan (last); | |
4480 | } | |
4b4bf941 | 4481 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4482 | { |
4483 | set_block_for_insn (last, bb); | |
4484 | df_insn_rescan (last); | |
4485 | } | |
a813c111 | 4486 | if (BB_END (bb) == after) |
1130d5e3 | 4487 | BB_END (bb) = last; |
23b2ce53 RS |
4488 | } |
4489 | else | |
2f937369 DM |
4490 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4491 | continue; | |
4492 | ||
4493 | after_after = NEXT_INSN (after); | |
4494 | ||
0f82e5c9 DM |
4495 | SET_NEXT_INSN (after) = first; |
4496 | SET_PREV_INSN (first) = after; | |
4497 | SET_NEXT_INSN (last) = after_after; | |
2f937369 | 4498 | if (after_after) |
0f82e5c9 | 4499 | SET_PREV_INSN (after_after) = last; |
2f937369 | 4500 | |
c3284718 | 4501 | if (after == get_last_insn ()) |
5936d944 | 4502 | set_last_insn (last); |
e855c69d | 4503 | |
2f937369 DM |
4504 | return last; |
4505 | } | |
4506 | ||
cd459bf8 | 4507 | static rtx_insn * |
e6eda746 | 4508 | emit_pattern_after_noloc (rtx x, rtx uncast_after, basic_block bb, |
167b9fae | 4509 | rtx_insn *(*make_raw)(rtx)) |
2f937369 | 4510 | { |
e6eda746 DM |
4511 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
4512 | rtx_insn *last = after; | |
2f937369 | 4513 | |
5b0264cb | 4514 | gcc_assert (after); |
2f937369 DM |
4515 | |
4516 | if (x == NULL_RTX) | |
e6eda746 | 4517 | return last; |
2f937369 DM |
4518 | |
4519 | switch (GET_CODE (x)) | |
23b2ce53 | 4520 | { |
b5b8b0ac | 4521 | case DEBUG_INSN: |
2f937369 DM |
4522 | case INSN: |
4523 | case JUMP_INSN: | |
4524 | case CALL_INSN: | |
4525 | case CODE_LABEL: | |
4526 | case BARRIER: | |
4527 | case NOTE: | |
1130d5e3 | 4528 | last = emit_insn_after_1 (as_a <rtx_insn *> (x), after, bb); |
2f937369 DM |
4529 | break; |
4530 | ||
4531 | #ifdef ENABLE_RTL_CHECKING | |
4532 | case SEQUENCE: | |
5b0264cb | 4533 | gcc_unreachable (); |
2f937369 DM |
4534 | break; |
4535 | #endif | |
4536 | ||
4537 | default: | |
5f02387d | 4538 | last = (*make_raw) (x); |
6fb5fa3c | 4539 | add_insn_after (last, after, bb); |
2f937369 | 4540 | break; |
23b2ce53 RS |
4541 | } |
4542 | ||
e6eda746 | 4543 | return last; |
23b2ce53 RS |
4544 | } |
4545 | ||
5f02387d NF |
4546 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4547 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
4548 | ||
cd459bf8 | 4549 | rtx_insn * |
5f02387d NF |
4550 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
4551 | { | |
4552 | return emit_pattern_after_noloc (x, after, bb, make_insn_raw); | |
4553 | } | |
4554 | ||
255680cf | 4555 | |
2f937369 | 4556 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4557 | and output it after the insn AFTER. */ |
4558 | ||
1476d1bd | 4559 | rtx_jump_insn * |
a7102479 | 4560 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4561 | { |
1476d1bd MM |
4562 | return as_a <rtx_jump_insn *> ( |
4563 | emit_pattern_after_noloc (x, after, NULL, make_jump_insn_raw)); | |
2f937369 DM |
4564 | } |
4565 | ||
4566 | /* Make an instruction with body X and code CALL_INSN | |
4567 | and output it after the instruction AFTER. */ | |
4568 | ||
cd459bf8 | 4569 | rtx_insn * |
a7102479 | 4570 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 | 4571 | { |
5f02387d | 4572 | return emit_pattern_after_noloc (x, after, NULL, make_call_insn_raw); |
23b2ce53 RS |
4573 | } |
4574 | ||
b5b8b0ac AO |
4575 | /* Make an instruction with body X and code CALL_INSN |
4576 | and output it after the instruction AFTER. */ | |
4577 | ||
cd459bf8 | 4578 | rtx_insn * |
b5b8b0ac AO |
4579 | emit_debug_insn_after_noloc (rtx x, rtx after) |
4580 | { | |
5f02387d | 4581 | return emit_pattern_after_noloc (x, after, NULL, make_debug_insn_raw); |
b5b8b0ac AO |
4582 | } |
4583 | ||
23b2ce53 RS |
4584 | /* Make an insn of code BARRIER |
4585 | and output it after the insn AFTER. */ | |
4586 | ||
cd459bf8 | 4587 | rtx_barrier * |
502b8322 | 4588 | emit_barrier_after (rtx after) |
23b2ce53 | 4589 | { |
cd459bf8 | 4590 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4591 | |
4592 | INSN_UID (insn) = cur_insn_uid++; | |
4593 | ||
6fb5fa3c | 4594 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4595 | return insn; |
4596 | } | |
4597 | ||
4598 | /* Emit the label LABEL after the insn AFTER. */ | |
4599 | ||
cd459bf8 | 4600 | rtx_insn * |
596f2b17 | 4601 | emit_label_after (rtx label, rtx_insn *after) |
23b2ce53 | 4602 | { |
468660d3 SB |
4603 | gcc_checking_assert (INSN_UID (label) == 0); |
4604 | INSN_UID (label) = cur_insn_uid++; | |
4605 | add_insn_after (label, after, NULL); | |
cd459bf8 | 4606 | return as_a <rtx_insn *> (label); |
23b2ce53 | 4607 | } |
96fba521 SB |
4608 | \f |
4609 | /* Notes require a bit of special handling: Some notes need to have their | |
4610 | BLOCK_FOR_INSN set, others should never have it set, and some should | |
4611 | have it set or clear depending on the context. */ | |
4612 | ||
4613 | /* Return true iff a note of kind SUBTYPE should be emitted with routines | |
4614 | that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the | |
4615 | caller is asked to emit a note before BB_HEAD, or after BB_END. */ | |
4616 | ||
4617 | static bool | |
4618 | note_outside_basic_block_p (enum insn_note subtype, bool on_bb_boundary_p) | |
4619 | { | |
4620 | switch (subtype) | |
4621 | { | |
4622 | /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */ | |
4623 | case NOTE_INSN_SWITCH_TEXT_SECTIONS: | |
4624 | return true; | |
4625 | ||
4626 | /* Notes for var tracking and EH region markers can appear between or | |
4627 | inside basic blocks. If the caller is emitting on the basic block | |
4628 | boundary, do not set BLOCK_FOR_INSN on the new note. */ | |
4629 | case NOTE_INSN_VAR_LOCATION: | |
4630 | case NOTE_INSN_CALL_ARG_LOCATION: | |
4631 | case NOTE_INSN_EH_REGION_BEG: | |
4632 | case NOTE_INSN_EH_REGION_END: | |
4633 | return on_bb_boundary_p; | |
4634 | ||
4635 | /* Otherwise, BLOCK_FOR_INSN must be set. */ | |
4636 | default: | |
4637 | return false; | |
4638 | } | |
4639 | } | |
23b2ce53 RS |
4640 | |
4641 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4642 | ||
66e8df53 | 4643 | rtx_note * |
589e43f9 | 4644 | emit_note_after (enum insn_note subtype, rtx_insn *after) |
23b2ce53 | 4645 | { |
66e8df53 | 4646 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4647 | basic_block bb = BARRIER_P (after) ? NULL : BLOCK_FOR_INSN (after); |
4648 | bool on_bb_boundary_p = (bb != NULL && BB_END (bb) == after); | |
4649 | ||
4650 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4651 | add_insn_after_nobb (note, after); | |
4652 | else | |
4653 | add_insn_after (note, after, bb); | |
4654 | return note; | |
4655 | } | |
4656 | ||
4657 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ | |
4658 | ||
66e8df53 | 4659 | rtx_note * |
89b6250d | 4660 | emit_note_before (enum insn_note subtype, rtx_insn *before) |
96fba521 | 4661 | { |
66e8df53 | 4662 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4663 | basic_block bb = BARRIER_P (before) ? NULL : BLOCK_FOR_INSN (before); |
4664 | bool on_bb_boundary_p = (bb != NULL && BB_HEAD (bb) == before); | |
4665 | ||
4666 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4667 | add_insn_before_nobb (note, before); | |
4668 | else | |
4669 | add_insn_before (note, before, bb); | |
23b2ce53 RS |
4670 | return note; |
4671 | } | |
23b2ce53 | 4672 | \f |
e8110d6f NF |
4673 | /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC. |
4674 | MAKE_RAW indicates how to turn PATTERN into a real insn. */ | |
4675 | ||
cd459bf8 | 4676 | static rtx_insn * |
dc01c3d1 | 4677 | emit_pattern_after_setloc (rtx pattern, rtx uncast_after, int loc, |
167b9fae | 4678 | rtx_insn *(*make_raw) (rtx)) |
0d682900 | 4679 | { |
dc01c3d1 | 4680 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
e67d1102 | 4681 | rtx_insn *last = emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
0d682900 | 4682 | |
a7102479 | 4683 | if (pattern == NULL_RTX || !loc) |
e67d1102 | 4684 | return last; |
dd3adcf8 | 4685 | |
2f937369 DM |
4686 | after = NEXT_INSN (after); |
4687 | while (1) | |
4688 | { | |
20d4397a EB |
4689 | if (active_insn_p (after) |
4690 | && !JUMP_TABLE_DATA_P (after) /* FIXME */ | |
4691 | && !INSN_LOCATION (after)) | |
5368224f | 4692 | INSN_LOCATION (after) = loc; |
2f937369 DM |
4693 | if (after == last) |
4694 | break; | |
4695 | after = NEXT_INSN (after); | |
4696 | } | |
e67d1102 | 4697 | return last; |
0d682900 JH |
4698 | } |
4699 | ||
e8110d6f NF |
4700 | /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN |
4701 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after | |
4702 | any DEBUG_INSNs. */ | |
4703 | ||
cd459bf8 | 4704 | static rtx_insn * |
dc01c3d1 | 4705 | emit_pattern_after (rtx pattern, rtx uncast_after, bool skip_debug_insns, |
167b9fae | 4706 | rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4707 | { |
dc01c3d1 DM |
4708 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
4709 | rtx_insn *prev = after; | |
b5b8b0ac | 4710 | |
e8110d6f NF |
4711 | if (skip_debug_insns) |
4712 | while (DEBUG_INSN_P (prev)) | |
4713 | prev = PREV_INSN (prev); | |
b5b8b0ac AO |
4714 | |
4715 | if (INSN_P (prev)) | |
5368224f | 4716 | return emit_pattern_after_setloc (pattern, after, INSN_LOCATION (prev), |
e8110d6f | 4717 | make_raw); |
a7102479 | 4718 | else |
e8110d6f | 4719 | return emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
a7102479 JH |
4720 | } |
4721 | ||
5368224f | 4722 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4723 | rtx_insn * |
e8110d6f | 4724 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4725 | { |
e8110d6f NF |
4726 | return emit_pattern_after_setloc (pattern, after, loc, make_insn_raw); |
4727 | } | |
2f937369 | 4728 | |
5368224f | 4729 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4730 | rtx_insn * |
e8110d6f NF |
4731 | emit_insn_after (rtx pattern, rtx after) |
4732 | { | |
4733 | return emit_pattern_after (pattern, after, true, make_insn_raw); | |
4734 | } | |
dd3adcf8 | 4735 | |
5368224f | 4736 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4737 | rtx_jump_insn * |
e8110d6f NF |
4738 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
4739 | { | |
1476d1bd MM |
4740 | return as_a <rtx_jump_insn *> ( |
4741 | emit_pattern_after_setloc (pattern, after, loc, make_jump_insn_raw)); | |
0d682900 JH |
4742 | } |
4743 | ||
5368224f | 4744 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
1476d1bd | 4745 | rtx_jump_insn * |
a7102479 JH |
4746 | emit_jump_insn_after (rtx pattern, rtx after) |
4747 | { | |
1476d1bd MM |
4748 | return as_a <rtx_jump_insn *> ( |
4749 | emit_pattern_after (pattern, after, true, make_jump_insn_raw)); | |
a7102479 JH |
4750 | } |
4751 | ||
5368224f | 4752 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4753 | rtx_insn * |
502b8322 | 4754 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4755 | { |
e8110d6f | 4756 | return emit_pattern_after_setloc (pattern, after, loc, make_call_insn_raw); |
0d682900 JH |
4757 | } |
4758 | ||
5368224f | 4759 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4760 | rtx_insn * |
a7102479 JH |
4761 | emit_call_insn_after (rtx pattern, rtx after) |
4762 | { | |
e8110d6f | 4763 | return emit_pattern_after (pattern, after, true, make_call_insn_raw); |
a7102479 JH |
4764 | } |
4765 | ||
5368224f | 4766 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4767 | rtx_insn * |
b5b8b0ac AO |
4768 | emit_debug_insn_after_setloc (rtx pattern, rtx after, int loc) |
4769 | { | |
e8110d6f | 4770 | return emit_pattern_after_setloc (pattern, after, loc, make_debug_insn_raw); |
b5b8b0ac AO |
4771 | } |
4772 | ||
5368224f | 4773 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4774 | rtx_insn * |
b5b8b0ac AO |
4775 | emit_debug_insn_after (rtx pattern, rtx after) |
4776 | { | |
e8110d6f | 4777 | return emit_pattern_after (pattern, after, false, make_debug_insn_raw); |
b5b8b0ac AO |
4778 | } |
4779 | ||
e8110d6f NF |
4780 | /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC. |
4781 | MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP | |
4782 | indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN, | |
4783 | CALL_INSN, etc. */ | |
4784 | ||
cd459bf8 | 4785 | static rtx_insn * |
dc01c3d1 | 4786 | emit_pattern_before_setloc (rtx pattern, rtx uncast_before, int loc, bool insnp, |
167b9fae | 4787 | rtx_insn *(*make_raw) (rtx)) |
0d682900 | 4788 | { |
dc01c3d1 DM |
4789 | rtx_insn *before = as_a <rtx_insn *> (uncast_before); |
4790 | rtx_insn *first = PREV_INSN (before); | |
4791 | rtx_insn *last = emit_pattern_before_noloc (pattern, before, | |
4792 | insnp ? before : NULL_RTX, | |
4793 | NULL, make_raw); | |
a7102479 JH |
4794 | |
4795 | if (pattern == NULL_RTX || !loc) | |
dc01c3d1 | 4796 | return last; |
a7102479 | 4797 | |
26cb3993 JH |
4798 | if (!first) |
4799 | first = get_insns (); | |
4800 | else | |
4801 | first = NEXT_INSN (first); | |
a7102479 JH |
4802 | while (1) |
4803 | { | |
20d4397a EB |
4804 | if (active_insn_p (first) |
4805 | && !JUMP_TABLE_DATA_P (first) /* FIXME */ | |
4806 | && !INSN_LOCATION (first)) | |
5368224f | 4807 | INSN_LOCATION (first) = loc; |
a7102479 JH |
4808 | if (first == last) |
4809 | break; | |
4810 | first = NEXT_INSN (first); | |
4811 | } | |
dc01c3d1 | 4812 | return last; |
a7102479 JH |
4813 | } |
4814 | ||
e8110d6f NF |
4815 | /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN |
4816 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert | |
4817 | before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an | |
4818 | INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */ | |
4819 | ||
cd459bf8 | 4820 | static rtx_insn * |
dc01c3d1 | 4821 | emit_pattern_before (rtx pattern, rtx uncast_before, bool skip_debug_insns, |
167b9fae | 4822 | bool insnp, rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4823 | { |
dc01c3d1 DM |
4824 | rtx_insn *before = safe_as_a <rtx_insn *> (uncast_before); |
4825 | rtx_insn *next = before; | |
b5b8b0ac | 4826 | |
e8110d6f NF |
4827 | if (skip_debug_insns) |
4828 | while (DEBUG_INSN_P (next)) | |
4829 | next = PREV_INSN (next); | |
b5b8b0ac AO |
4830 | |
4831 | if (INSN_P (next)) | |
5368224f | 4832 | return emit_pattern_before_setloc (pattern, before, INSN_LOCATION (next), |
e8110d6f | 4833 | insnp, make_raw); |
a7102479 | 4834 | else |
e8110d6f NF |
4835 | return emit_pattern_before_noloc (pattern, before, |
4836 | insnp ? before : NULL_RTX, | |
4837 | NULL, make_raw); | |
a7102479 JH |
4838 | } |
4839 | ||
5368224f | 4840 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4841 | rtx_insn * |
596f2b17 | 4842 | emit_insn_before_setloc (rtx pattern, rtx_insn *before, int loc) |
a7102479 | 4843 | { |
e8110d6f NF |
4844 | return emit_pattern_before_setloc (pattern, before, loc, true, |
4845 | make_insn_raw); | |
4846 | } | |
a7102479 | 4847 | |
5368224f | 4848 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
cd459bf8 | 4849 | rtx_insn * |
e8110d6f NF |
4850 | emit_insn_before (rtx pattern, rtx before) |
4851 | { | |
4852 | return emit_pattern_before (pattern, before, true, true, make_insn_raw); | |
4853 | } | |
a7102479 | 4854 | |
5368224f | 4855 | /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4856 | rtx_jump_insn * |
596f2b17 | 4857 | emit_jump_insn_before_setloc (rtx pattern, rtx_insn *before, int loc) |
e8110d6f | 4858 | { |
1476d1bd MM |
4859 | return as_a <rtx_jump_insn *> ( |
4860 | emit_pattern_before_setloc (pattern, before, loc, false, | |
4861 | make_jump_insn_raw)); | |
a7102479 JH |
4862 | } |
4863 | ||
5368224f | 4864 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
1476d1bd | 4865 | rtx_jump_insn * |
a7102479 JH |
4866 | emit_jump_insn_before (rtx pattern, rtx before) |
4867 | { | |
1476d1bd MM |
4868 | return as_a <rtx_jump_insn *> ( |
4869 | emit_pattern_before (pattern, before, true, false, | |
4870 | make_jump_insn_raw)); | |
a7102479 JH |
4871 | } |
4872 | ||
5368224f | 4873 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4874 | rtx_insn * |
596f2b17 | 4875 | emit_call_insn_before_setloc (rtx pattern, rtx_insn *before, int loc) |
a7102479 | 4876 | { |
e8110d6f NF |
4877 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4878 | make_call_insn_raw); | |
0d682900 | 4879 | } |
a7102479 | 4880 | |
e8110d6f | 4881 | /* Like emit_call_insn_before_noloc, |
5368224f | 4882 | but set insn_location according to BEFORE. */ |
cd459bf8 | 4883 | rtx_insn * |
596f2b17 | 4884 | emit_call_insn_before (rtx pattern, rtx_insn *before) |
a7102479 | 4885 | { |
e8110d6f NF |
4886 | return emit_pattern_before (pattern, before, true, false, |
4887 | make_call_insn_raw); | |
a7102479 | 4888 | } |
b5b8b0ac | 4889 | |
5368224f | 4890 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4891 | rtx_insn * |
b5b8b0ac AO |
4892 | emit_debug_insn_before_setloc (rtx pattern, rtx before, int loc) |
4893 | { | |
e8110d6f NF |
4894 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4895 | make_debug_insn_raw); | |
b5b8b0ac AO |
4896 | } |
4897 | ||
e8110d6f | 4898 | /* Like emit_debug_insn_before_noloc, |
5368224f | 4899 | but set insn_location according to BEFORE. */ |
cd459bf8 | 4900 | rtx_insn * |
3a6216b0 | 4901 | emit_debug_insn_before (rtx pattern, rtx_insn *before) |
b5b8b0ac | 4902 | { |
e8110d6f NF |
4903 | return emit_pattern_before (pattern, before, false, false, |
4904 | make_debug_insn_raw); | |
b5b8b0ac | 4905 | } |
0d682900 | 4906 | \f |
2f937369 DM |
4907 | /* Take X and emit it at the end of the doubly-linked |
4908 | INSN list. | |
23b2ce53 RS |
4909 | |
4910 | Returns the last insn emitted. */ | |
4911 | ||
cd459bf8 | 4912 | rtx_insn * |
502b8322 | 4913 | emit_insn (rtx x) |
23b2ce53 | 4914 | { |
cd459bf8 DM |
4915 | rtx_insn *last = get_last_insn (); |
4916 | rtx_insn *insn; | |
23b2ce53 | 4917 | |
2f937369 DM |
4918 | if (x == NULL_RTX) |
4919 | return last; | |
23b2ce53 | 4920 | |
2f937369 DM |
4921 | switch (GET_CODE (x)) |
4922 | { | |
b5b8b0ac | 4923 | case DEBUG_INSN: |
2f937369 DM |
4924 | case INSN: |
4925 | case JUMP_INSN: | |
4926 | case CALL_INSN: | |
4927 | case CODE_LABEL: | |
4928 | case BARRIER: | |
4929 | case NOTE: | |
cd459bf8 | 4930 | insn = as_a <rtx_insn *> (x); |
2f937369 | 4931 | while (insn) |
23b2ce53 | 4932 | { |
cd459bf8 | 4933 | rtx_insn *next = NEXT_INSN (insn); |
23b2ce53 | 4934 | add_insn (insn); |
2f937369 DM |
4935 | last = insn; |
4936 | insn = next; | |
23b2ce53 | 4937 | } |
2f937369 | 4938 | break; |
23b2ce53 | 4939 | |
2f937369 | 4940 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 4941 | case JUMP_TABLE_DATA: |
2f937369 | 4942 | case SEQUENCE: |
5b0264cb | 4943 | gcc_unreachable (); |
2f937369 DM |
4944 | break; |
4945 | #endif | |
23b2ce53 | 4946 | |
2f937369 DM |
4947 | default: |
4948 | last = make_insn_raw (x); | |
4949 | add_insn (last); | |
4950 | break; | |
23b2ce53 RS |
4951 | } |
4952 | ||
4953 | return last; | |
4954 | } | |
4955 | ||
b5b8b0ac AO |
4956 | /* Make an insn of code DEBUG_INSN with pattern X |
4957 | and add it to the end of the doubly-linked list. */ | |
4958 | ||
cd459bf8 | 4959 | rtx_insn * |
b5b8b0ac AO |
4960 | emit_debug_insn (rtx x) |
4961 | { | |
cd459bf8 DM |
4962 | rtx_insn *last = get_last_insn (); |
4963 | rtx_insn *insn; | |
b5b8b0ac AO |
4964 | |
4965 | if (x == NULL_RTX) | |
4966 | return last; | |
4967 | ||
4968 | switch (GET_CODE (x)) | |
4969 | { | |
4970 | case DEBUG_INSN: | |
4971 | case INSN: | |
4972 | case JUMP_INSN: | |
4973 | case CALL_INSN: | |
4974 | case CODE_LABEL: | |
4975 | case BARRIER: | |
4976 | case NOTE: | |
cd459bf8 | 4977 | insn = as_a <rtx_insn *> (x); |
b5b8b0ac AO |
4978 | while (insn) |
4979 | { | |
cd459bf8 | 4980 | rtx_insn *next = NEXT_INSN (insn); |
b5b8b0ac AO |
4981 | add_insn (insn); |
4982 | last = insn; | |
4983 | insn = next; | |
4984 | } | |
4985 | break; | |
4986 | ||
4987 | #ifdef ENABLE_RTL_CHECKING | |
39718607 | 4988 | case JUMP_TABLE_DATA: |
b5b8b0ac AO |
4989 | case SEQUENCE: |
4990 | gcc_unreachable (); | |
4991 | break; | |
4992 | #endif | |
4993 | ||
4994 | default: | |
4995 | last = make_debug_insn_raw (x); | |
4996 | add_insn (last); | |
4997 | break; | |
4998 | } | |
4999 | ||
5000 | return last; | |
5001 | } | |
5002 | ||
2f937369 DM |
5003 | /* Make an insn of code JUMP_INSN with pattern X |
5004 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5005 | |
cd459bf8 | 5006 | rtx_insn * |
502b8322 | 5007 | emit_jump_insn (rtx x) |
23b2ce53 | 5008 | { |
cd459bf8 DM |
5009 | rtx_insn *last = NULL; |
5010 | rtx_insn *insn; | |
23b2ce53 | 5011 | |
2f937369 | 5012 | switch (GET_CODE (x)) |
23b2ce53 | 5013 | { |
b5b8b0ac | 5014 | case DEBUG_INSN: |
2f937369 DM |
5015 | case INSN: |
5016 | case JUMP_INSN: | |
5017 | case CALL_INSN: | |
5018 | case CODE_LABEL: | |
5019 | case BARRIER: | |
5020 | case NOTE: | |
cd459bf8 | 5021 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
5022 | while (insn) |
5023 | { | |
cd459bf8 | 5024 | rtx_insn *next = NEXT_INSN (insn); |
2f937369 DM |
5025 | add_insn (insn); |
5026 | last = insn; | |
5027 | insn = next; | |
5028 | } | |
5029 | break; | |
e0a5c5eb | 5030 | |
2f937369 | 5031 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 5032 | case JUMP_TABLE_DATA: |
2f937369 | 5033 | case SEQUENCE: |
5b0264cb | 5034 | gcc_unreachable (); |
2f937369 DM |
5035 | break; |
5036 | #endif | |
e0a5c5eb | 5037 | |
2f937369 DM |
5038 | default: |
5039 | last = make_jump_insn_raw (x); | |
5040 | add_insn (last); | |
5041 | break; | |
3c030e88 | 5042 | } |
e0a5c5eb RS |
5043 | |
5044 | return last; | |
5045 | } | |
5046 | ||
2f937369 | 5047 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
5048 | and add it to the end of the doubly-linked list. */ |
5049 | ||
cd459bf8 | 5050 | rtx_insn * |
502b8322 | 5051 | emit_call_insn (rtx x) |
23b2ce53 | 5052 | { |
cd459bf8 | 5053 | rtx_insn *insn; |
2f937369 DM |
5054 | |
5055 | switch (GET_CODE (x)) | |
23b2ce53 | 5056 | { |
b5b8b0ac | 5057 | case DEBUG_INSN: |
2f937369 DM |
5058 | case INSN: |
5059 | case JUMP_INSN: | |
5060 | case CALL_INSN: | |
5061 | case CODE_LABEL: | |
5062 | case BARRIER: | |
5063 | case NOTE: | |
5064 | insn = emit_insn (x); | |
5065 | break; | |
23b2ce53 | 5066 | |
2f937369 DM |
5067 | #ifdef ENABLE_RTL_CHECKING |
5068 | case SEQUENCE: | |
39718607 | 5069 | case JUMP_TABLE_DATA: |
5b0264cb | 5070 | gcc_unreachable (); |
2f937369 DM |
5071 | break; |
5072 | #endif | |
23b2ce53 | 5073 | |
2f937369 DM |
5074 | default: |
5075 | insn = make_call_insn_raw (x); | |
23b2ce53 | 5076 | add_insn (insn); |
2f937369 | 5077 | break; |
23b2ce53 | 5078 | } |
2f937369 DM |
5079 | |
5080 | return insn; | |
23b2ce53 RS |
5081 | } |
5082 | ||
5083 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
5084 | ||
1476d1bd MM |
5085 | rtx_code_label * |
5086 | emit_label (rtx uncast_label) | |
23b2ce53 | 5087 | { |
1476d1bd MM |
5088 | rtx_code_label *label = as_a <rtx_code_label *> (uncast_label); |
5089 | ||
468660d3 SB |
5090 | gcc_checking_assert (INSN_UID (label) == 0); |
5091 | INSN_UID (label) = cur_insn_uid++; | |
1476d1bd MM |
5092 | add_insn (label); |
5093 | return label; | |
23b2ce53 RS |
5094 | } |
5095 | ||
39718607 SB |
5096 | /* Make an insn of code JUMP_TABLE_DATA |
5097 | and add it to the end of the doubly-linked list. */ | |
5098 | ||
4598afdd | 5099 | rtx_jump_table_data * |
39718607 SB |
5100 | emit_jump_table_data (rtx table) |
5101 | { | |
4598afdd DM |
5102 | rtx_jump_table_data *jump_table_data = |
5103 | as_a <rtx_jump_table_data *> (rtx_alloc (JUMP_TABLE_DATA)); | |
39718607 SB |
5104 | INSN_UID (jump_table_data) = cur_insn_uid++; |
5105 | PATTERN (jump_table_data) = table; | |
5106 | BLOCK_FOR_INSN (jump_table_data) = NULL; | |
5107 | add_insn (jump_table_data); | |
5108 | return jump_table_data; | |
5109 | } | |
5110 | ||
23b2ce53 RS |
5111 | /* Make an insn of code BARRIER |
5112 | and add it to the end of the doubly-linked list. */ | |
5113 | ||
cd459bf8 | 5114 | rtx_barrier * |
502b8322 | 5115 | emit_barrier (void) |
23b2ce53 | 5116 | { |
cd459bf8 | 5117 | rtx_barrier *barrier = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
5118 | INSN_UID (barrier) = cur_insn_uid++; |
5119 | add_insn (barrier); | |
5120 | return barrier; | |
5121 | } | |
5122 | ||
5f2fc772 | 5123 | /* Emit a copy of note ORIG. */ |
502b8322 | 5124 | |
66e8df53 DM |
5125 | rtx_note * |
5126 | emit_note_copy (rtx_note *orig) | |
5f2fc772 | 5127 | { |
96fba521 | 5128 | enum insn_note kind = (enum insn_note) NOTE_KIND (orig); |
66e8df53 | 5129 | rtx_note *note = make_note_raw (kind); |
5f2fc772 | 5130 | NOTE_DATA (note) = NOTE_DATA (orig); |
5f2fc772 | 5131 | add_insn (note); |
2e040219 | 5132 | return note; |
23b2ce53 RS |
5133 | } |
5134 | ||
2e040219 NS |
5135 | /* Make an insn of code NOTE or type NOTE_NO |
5136 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5137 | |
66e8df53 | 5138 | rtx_note * |
a38e7aa5 | 5139 | emit_note (enum insn_note kind) |
23b2ce53 | 5140 | { |
66e8df53 | 5141 | rtx_note *note = make_note_raw (kind); |
23b2ce53 RS |
5142 | add_insn (note); |
5143 | return note; | |
5144 | } | |
5145 | ||
c41c1387 RS |
5146 | /* Emit a clobber of lvalue X. */ |
5147 | ||
cd459bf8 | 5148 | rtx_insn * |
c41c1387 RS |
5149 | emit_clobber (rtx x) |
5150 | { | |
5151 | /* CONCATs should not appear in the insn stream. */ | |
5152 | if (GET_CODE (x) == CONCAT) | |
5153 | { | |
5154 | emit_clobber (XEXP (x, 0)); | |
5155 | return emit_clobber (XEXP (x, 1)); | |
5156 | } | |
5157 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
5158 | } | |
5159 | ||
5160 | /* Return a sequence of insns to clobber lvalue X. */ | |
5161 | ||
cd459bf8 | 5162 | rtx_insn * |
c41c1387 RS |
5163 | gen_clobber (rtx x) |
5164 | { | |
cd459bf8 | 5165 | rtx_insn *seq; |
c41c1387 RS |
5166 | |
5167 | start_sequence (); | |
5168 | emit_clobber (x); | |
5169 | seq = get_insns (); | |
5170 | end_sequence (); | |
5171 | return seq; | |
5172 | } | |
5173 | ||
5174 | /* Emit a use of rvalue X. */ | |
5175 | ||
cd459bf8 | 5176 | rtx_insn * |
c41c1387 RS |
5177 | emit_use (rtx x) |
5178 | { | |
5179 | /* CONCATs should not appear in the insn stream. */ | |
5180 | if (GET_CODE (x) == CONCAT) | |
5181 | { | |
5182 | emit_use (XEXP (x, 0)); | |
5183 | return emit_use (XEXP (x, 1)); | |
5184 | } | |
5185 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
5186 | } | |
5187 | ||
5188 | /* Return a sequence of insns to use rvalue X. */ | |
5189 | ||
cd459bf8 | 5190 | rtx_insn * |
c41c1387 RS |
5191 | gen_use (rtx x) |
5192 | { | |
cd459bf8 | 5193 | rtx_insn *seq; |
c41c1387 RS |
5194 | |
5195 | start_sequence (); | |
5196 | emit_use (x); | |
5197 | seq = get_insns (); | |
5198 | end_sequence (); | |
5199 | return seq; | |
5200 | } | |
5201 | ||
c8912e53 RS |
5202 | /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction. |
5203 | Return the set in INSN that such notes describe, or NULL if the notes | |
5204 | have no meaning for INSN. */ | |
5205 | ||
5206 | rtx | |
5207 | set_for_reg_notes (rtx insn) | |
5208 | { | |
5209 | rtx pat, reg; | |
5210 | ||
5211 | if (!INSN_P (insn)) | |
5212 | return NULL_RTX; | |
5213 | ||
5214 | pat = PATTERN (insn); | |
5215 | if (GET_CODE (pat) == PARALLEL) | |
5216 | { | |
5217 | /* We do not use single_set because that ignores SETs of unused | |
5218 | registers. REG_EQUAL and REG_EQUIV notes really do require the | |
5219 | PARALLEL to have a single SET. */ | |
5220 | if (multiple_sets (insn)) | |
5221 | return NULL_RTX; | |
5222 | pat = XVECEXP (pat, 0, 0); | |
5223 | } | |
5224 | ||
5225 | if (GET_CODE (pat) != SET) | |
5226 | return NULL_RTX; | |
5227 | ||
5228 | reg = SET_DEST (pat); | |
5229 | ||
5230 | /* Notes apply to the contents of a STRICT_LOW_PART. */ | |
5231 | if (GET_CODE (reg) == STRICT_LOW_PART) | |
5232 | reg = XEXP (reg, 0); | |
5233 | ||
5234 | /* Check that we have a register. */ | |
5235 | if (!(REG_P (reg) || GET_CODE (reg) == SUBREG)) | |
5236 | return NULL_RTX; | |
5237 | ||
5238 | return pat; | |
5239 | } | |
5240 | ||
87b47c85 | 5241 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a |
30f7a378 | 5242 | note of this type already exists, remove it first. */ |
87b47c85 | 5243 | |
3d238248 | 5244 | rtx |
502b8322 | 5245 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
5246 | { |
5247 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
5248 | ||
52488da1 JW |
5249 | switch (kind) |
5250 | { | |
5251 | case REG_EQUAL: | |
5252 | case REG_EQUIV: | |
c8912e53 RS |
5253 | if (!set_for_reg_notes (insn)) |
5254 | return NULL_RTX; | |
52488da1 JW |
5255 | |
5256 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
5257 | It serves no useful purpose and breaks eliminate_regs. */ | |
5258 | if (GET_CODE (datum) == ASM_OPERANDS) | |
5259 | return NULL_RTX; | |
109374e2 RS |
5260 | |
5261 | /* Notes with side effects are dangerous. Even if the side-effect | |
5262 | initially mirrors one in PATTERN (INSN), later optimizations | |
5263 | might alter the way that the final register value is calculated | |
5264 | and so move or alter the side-effect in some way. The note would | |
5265 | then no longer be a valid substitution for SET_SRC. */ | |
5266 | if (side_effects_p (datum)) | |
5267 | return NULL_RTX; | |
52488da1 JW |
5268 | break; |
5269 | ||
5270 | default: | |
5271 | break; | |
5272 | } | |
3d238248 | 5273 | |
c8912e53 RS |
5274 | if (note) |
5275 | XEXP (note, 0) = datum; | |
5276 | else | |
5277 | { | |
5278 | add_reg_note (insn, kind, datum); | |
5279 | note = REG_NOTES (insn); | |
5280 | } | |
6fb5fa3c DB |
5281 | |
5282 | switch (kind) | |
3d238248 | 5283 | { |
6fb5fa3c DB |
5284 | case REG_EQUAL: |
5285 | case REG_EQUIV: | |
b2908ba6 | 5286 | df_notes_rescan (as_a <rtx_insn *> (insn)); |
6fb5fa3c DB |
5287 | break; |
5288 | default: | |
5289 | break; | |
3d238248 | 5290 | } |
87b47c85 | 5291 | |
c8912e53 | 5292 | return note; |
87b47c85 | 5293 | } |
7543f918 JR |
5294 | |
5295 | /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */ | |
5296 | rtx | |
5297 | set_dst_reg_note (rtx insn, enum reg_note kind, rtx datum, rtx dst) | |
5298 | { | |
c8912e53 | 5299 | rtx set = set_for_reg_notes (insn); |
7543f918 JR |
5300 | |
5301 | if (set && SET_DEST (set) == dst) | |
5302 | return set_unique_reg_note (insn, kind, datum); | |
5303 | return NULL_RTX; | |
5304 | } | |
23b2ce53 | 5305 | \f |
23b2ce53 RS |
5306 | /* Emit the rtl pattern X as an appropriate kind of insn. |
5307 | If X is a label, it is simply added into the insn chain. */ | |
5308 | ||
cd459bf8 | 5309 | rtx_insn * |
502b8322 | 5310 | emit (rtx x) |
23b2ce53 RS |
5311 | { |
5312 | enum rtx_code code = classify_insn (x); | |
5313 | ||
5b0264cb | 5314 | switch (code) |
23b2ce53 | 5315 | { |
5b0264cb NS |
5316 | case CODE_LABEL: |
5317 | return emit_label (x); | |
5318 | case INSN: | |
5319 | return emit_insn (x); | |
5320 | case JUMP_INSN: | |
5321 | { | |
cd459bf8 | 5322 | rtx_insn *insn = emit_jump_insn (x); |
5b0264cb NS |
5323 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
5324 | return emit_barrier (); | |
5325 | return insn; | |
5326 | } | |
5327 | case CALL_INSN: | |
5328 | return emit_call_insn (x); | |
b5b8b0ac AO |
5329 | case DEBUG_INSN: |
5330 | return emit_debug_insn (x); | |
5b0264cb NS |
5331 | default: |
5332 | gcc_unreachable (); | |
23b2ce53 | 5333 | } |
23b2ce53 RS |
5334 | } |
5335 | \f | |
e2500fed | 5336 | /* Space for free sequence stack entries. */ |
1431042e | 5337 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 5338 | |
4dfa0342 RH |
5339 | /* Begin emitting insns to a sequence. If this sequence will contain |
5340 | something that might cause the compiler to pop arguments to function | |
5341 | calls (because those pops have previously been deferred; see | |
5342 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
5343 | before calling this function. That will ensure that the deferred | |
5344 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
5345 | |
5346 | void | |
502b8322 | 5347 | start_sequence (void) |
23b2ce53 RS |
5348 | { |
5349 | struct sequence_stack *tem; | |
5350 | ||
e2500fed GK |
5351 | if (free_sequence_stack != NULL) |
5352 | { | |
5353 | tem = free_sequence_stack; | |
5354 | free_sequence_stack = tem->next; | |
5355 | } | |
5356 | else | |
766090c2 | 5357 | tem = ggc_alloc<sequence_stack> (); |
23b2ce53 | 5358 | |
614d5bd8 | 5359 | tem->next = get_current_sequence ()->next; |
5936d944 JH |
5360 | tem->first = get_insns (); |
5361 | tem->last = get_last_insn (); | |
614d5bd8 | 5362 | get_current_sequence ()->next = tem; |
23b2ce53 | 5363 | |
5936d944 JH |
5364 | set_first_insn (0); |
5365 | set_last_insn (0); | |
23b2ce53 RS |
5366 | } |
5367 | ||
5c7a310f MM |
5368 | /* Set up the insn chain starting with FIRST as the current sequence, |
5369 | saving the previously current one. See the documentation for | |
5370 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5371 | |
5372 | void | |
fee3e72c | 5373 | push_to_sequence (rtx_insn *first) |
23b2ce53 | 5374 | { |
fee3e72c | 5375 | rtx_insn *last; |
23b2ce53 RS |
5376 | |
5377 | start_sequence (); | |
5378 | ||
e84a58ff EB |
5379 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)) |
5380 | ; | |
23b2ce53 | 5381 | |
5936d944 JH |
5382 | set_first_insn (first); |
5383 | set_last_insn (last); | |
23b2ce53 RS |
5384 | } |
5385 | ||
bb27eeda SE |
5386 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5387 | looping through the list. */ | |
5388 | ||
5389 | void | |
fee3e72c | 5390 | push_to_sequence2 (rtx_insn *first, rtx_insn *last) |
bb27eeda SE |
5391 | { |
5392 | start_sequence (); | |
5393 | ||
5936d944 JH |
5394 | set_first_insn (first); |
5395 | set_last_insn (last); | |
bb27eeda SE |
5396 | } |
5397 | ||
f15ae3a1 TW |
5398 | /* Set up the outer-level insn chain |
5399 | as the current sequence, saving the previously current one. */ | |
5400 | ||
5401 | void | |
502b8322 | 5402 | push_topmost_sequence (void) |
f15ae3a1 | 5403 | { |
614d5bd8 | 5404 | struct sequence_stack *top; |
f15ae3a1 TW |
5405 | |
5406 | start_sequence (); | |
5407 | ||
614d5bd8 | 5408 | top = get_topmost_sequence (); |
5936d944 JH |
5409 | set_first_insn (top->first); |
5410 | set_last_insn (top->last); | |
f15ae3a1 TW |
5411 | } |
5412 | ||
5413 | /* After emitting to the outer-level insn chain, update the outer-level | |
5414 | insn chain, and restore the previous saved state. */ | |
5415 | ||
5416 | void | |
502b8322 | 5417 | pop_topmost_sequence (void) |
f15ae3a1 | 5418 | { |
614d5bd8 | 5419 | struct sequence_stack *top; |
f15ae3a1 | 5420 | |
614d5bd8 | 5421 | top = get_topmost_sequence (); |
5936d944 JH |
5422 | top->first = get_insns (); |
5423 | top->last = get_last_insn (); | |
f15ae3a1 TW |
5424 | |
5425 | end_sequence (); | |
5426 | } | |
5427 | ||
23b2ce53 RS |
5428 | /* After emitting to a sequence, restore previous saved state. |
5429 | ||
5c7a310f | 5430 | To get the contents of the sequence just made, you must call |
2f937369 | 5431 | `get_insns' *before* calling here. |
5c7a310f MM |
5432 | |
5433 | If the compiler might have deferred popping arguments while | |
5434 | generating this sequence, and this sequence will not be immediately | |
5435 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5436 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5437 | pops are inserted into this sequence, and not into some random |
5438 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5439 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5440 | |
5441 | void | |
502b8322 | 5442 | end_sequence (void) |
23b2ce53 | 5443 | { |
614d5bd8 | 5444 | struct sequence_stack *tem = get_current_sequence ()->next; |
23b2ce53 | 5445 | |
5936d944 JH |
5446 | set_first_insn (tem->first); |
5447 | set_last_insn (tem->last); | |
614d5bd8 | 5448 | get_current_sequence ()->next = tem->next; |
23b2ce53 | 5449 | |
e2500fed GK |
5450 | memset (tem, 0, sizeof (*tem)); |
5451 | tem->next = free_sequence_stack; | |
5452 | free_sequence_stack = tem; | |
23b2ce53 RS |
5453 | } |
5454 | ||
5455 | /* Return 1 if currently emitting into a sequence. */ | |
5456 | ||
5457 | int | |
502b8322 | 5458 | in_sequence_p (void) |
23b2ce53 | 5459 | { |
614d5bd8 | 5460 | return get_current_sequence ()->next != 0; |
23b2ce53 | 5461 | } |
23b2ce53 | 5462 | \f |
59ec66dc MM |
5463 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5464 | ||
2bbdec73 | 5465 | static void |
bd60bab2 | 5466 | init_virtual_regs (void) |
59ec66dc | 5467 | { |
bd60bab2 JH |
5468 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5469 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5470 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5471 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5472 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
32990d5b JJ |
5473 | regno_reg_rtx[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM] |
5474 | = virtual_preferred_stack_boundary_rtx; | |
49ad7cfa BS |
5475 | } |
5476 | ||
da43a810 BS |
5477 | \f |
5478 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5479 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5480 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5481 | static int copy_insn_n_scratches; | |
5482 | ||
5483 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5484 | copied an ASM_OPERANDS. | |
5485 | In that case, it is the original input-operand vector. */ | |
5486 | static rtvec orig_asm_operands_vector; | |
5487 | ||
5488 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5489 | copied an ASM_OPERANDS. | |
5490 | In that case, it is the copied input-operand vector. */ | |
5491 | static rtvec copy_asm_operands_vector; | |
5492 | ||
5493 | /* Likewise for the constraints vector. */ | |
5494 | static rtvec orig_asm_constraints_vector; | |
5495 | static rtvec copy_asm_constraints_vector; | |
5496 | ||
5497 | /* Recursively create a new copy of an rtx for copy_insn. | |
5498 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5499 | ASM_OPERANDs properly. | |
5500 | Normally, this function is not used directly; use copy_insn as front end. | |
5501 | However, you could first copy an insn pattern with copy_insn and then use | |
5502 | this function afterwards to properly copy any REG_NOTEs containing | |
5503 | SCRATCHes. */ | |
5504 | ||
5505 | rtx | |
502b8322 | 5506 | copy_insn_1 (rtx orig) |
da43a810 | 5507 | { |
b3694847 SS |
5508 | rtx copy; |
5509 | int i, j; | |
5510 | RTX_CODE code; | |
5511 | const char *format_ptr; | |
da43a810 | 5512 | |
cd9c1ca8 RH |
5513 | if (orig == NULL) |
5514 | return NULL; | |
5515 | ||
da43a810 BS |
5516 | code = GET_CODE (orig); |
5517 | ||
5518 | switch (code) | |
5519 | { | |
5520 | case REG: | |
a52a87c3 | 5521 | case DEBUG_EXPR: |
d8116890 | 5522 | CASE_CONST_ANY: |
da43a810 BS |
5523 | case SYMBOL_REF: |
5524 | case CODE_LABEL: | |
5525 | case PC: | |
5526 | case CC0: | |
276e0224 | 5527 | case RETURN: |
26898771 | 5528 | case SIMPLE_RETURN: |
da43a810 | 5529 | return orig; |
3e89ed8d | 5530 | case CLOBBER: |
c5c5ba89 JH |
5531 | /* Share clobbers of hard registers (like cc0), but do not share pseudo reg |
5532 | clobbers or clobbers of hard registers that originated as pseudos. | |
5533 | This is needed to allow safe register renaming. */ | |
5534 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER | |
5535 | && ORIGINAL_REGNO (XEXP (orig, 0)) == REGNO (XEXP (orig, 0))) | |
3e89ed8d JH |
5536 | return orig; |
5537 | break; | |
da43a810 BS |
5538 | |
5539 | case SCRATCH: | |
5540 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5541 | if (copy_insn_scratch_in[i] == orig) | |
5542 | return copy_insn_scratch_out[i]; | |
5543 | break; | |
5544 | ||
5545 | case CONST: | |
6fb5fa3c | 5546 | if (shared_const_p (orig)) |
da43a810 BS |
5547 | return orig; |
5548 | break; | |
750c9258 | 5549 | |
da43a810 BS |
5550 | /* A MEM with a constant address is not sharable. The problem is that |
5551 | the constant address may need to be reloaded. If the mem is shared, | |
5552 | then reloading one copy of this mem will cause all copies to appear | |
5553 | to have been reloaded. */ | |
5554 | ||
5555 | default: | |
5556 | break; | |
5557 | } | |
5558 | ||
aacd3885 RS |
5559 | /* Copy the various flags, fields, and other information. We assume |
5560 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5561 | not be copied. That is the sensible default behavior, and forces |
5562 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5563 | copy = shallow_copy_rtx (orig); |
da43a810 BS |
5564 | |
5565 | /* We do not copy the USED flag, which is used as a mark bit during | |
5566 | walks over the RTL. */ | |
2adc7f12 | 5567 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5568 | |
5569 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
ec8e098d | 5570 | if (INSN_P (orig)) |
da43a810 | 5571 | { |
2adc7f12 JJ |
5572 | RTX_FLAG (copy, jump) = 0; |
5573 | RTX_FLAG (copy, call) = 0; | |
5574 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5575 | } |
750c9258 | 5576 | |
da43a810 BS |
5577 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5578 | ||
5579 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5580 | switch (*format_ptr++) |
5581 | { | |
5582 | case 'e': | |
5583 | if (XEXP (orig, i) != NULL) | |
5584 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5585 | break; | |
da43a810 | 5586 | |
aacd3885 RS |
5587 | case 'E': |
5588 | case 'V': | |
5589 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5590 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5591 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5592 | XVEC (copy, i) = copy_asm_operands_vector; | |
5593 | else if (XVEC (orig, i) != NULL) | |
5594 | { | |
5595 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5596 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5597 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5598 | } | |
5599 | break; | |
da43a810 | 5600 | |
aacd3885 RS |
5601 | case 't': |
5602 | case 'w': | |
5603 | case 'i': | |
5604 | case 's': | |
5605 | case 'S': | |
5606 | case 'u': | |
5607 | case '0': | |
5608 | /* These are left unchanged. */ | |
5609 | break; | |
da43a810 | 5610 | |
aacd3885 RS |
5611 | default: |
5612 | gcc_unreachable (); | |
5613 | } | |
da43a810 BS |
5614 | |
5615 | if (code == SCRATCH) | |
5616 | { | |
5617 | i = copy_insn_n_scratches++; | |
5b0264cb | 5618 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5619 | copy_insn_scratch_in[i] = orig; |
5620 | copy_insn_scratch_out[i] = copy; | |
5621 | } | |
5622 | else if (code == ASM_OPERANDS) | |
5623 | { | |
6462bb43 AO |
5624 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5625 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5626 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5627 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5628 | } |
5629 | ||
5630 | return copy; | |
5631 | } | |
5632 | ||
5633 | /* Create a new copy of an rtx. | |
5634 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5635 | ASM_OPERANDs properly. | |
5636 | INSN doesn't really have to be a full INSN; it could be just the | |
5637 | pattern. */ | |
5638 | rtx | |
502b8322 | 5639 | copy_insn (rtx insn) |
da43a810 BS |
5640 | { |
5641 | copy_insn_n_scratches = 0; | |
5642 | orig_asm_operands_vector = 0; | |
5643 | orig_asm_constraints_vector = 0; | |
5644 | copy_asm_operands_vector = 0; | |
5645 | copy_asm_constraints_vector = 0; | |
5646 | return copy_insn_1 (insn); | |
5647 | } | |
59ec66dc | 5648 | |
8e383849 JR |
5649 | /* Return a copy of INSN that can be used in a SEQUENCE delay slot, |
5650 | on that assumption that INSN itself remains in its original place. */ | |
5651 | ||
f8f0516e DM |
5652 | rtx_insn * |
5653 | copy_delay_slot_insn (rtx_insn *insn) | |
8e383849 JR |
5654 | { |
5655 | /* Copy INSN with its rtx_code, all its notes, location etc. */ | |
f8f0516e | 5656 | insn = as_a <rtx_insn *> (copy_rtx (insn)); |
8e383849 JR |
5657 | INSN_UID (insn) = cur_insn_uid++; |
5658 | return insn; | |
5659 | } | |
5660 | ||
23b2ce53 RS |
5661 | /* Initialize data structures and variables in this file |
5662 | before generating rtl for each function. */ | |
5663 | ||
5664 | void | |
502b8322 | 5665 | init_emit (void) |
23b2ce53 | 5666 | { |
5936d944 JH |
5667 | set_first_insn (NULL); |
5668 | set_last_insn (NULL); | |
b5b8b0ac AO |
5669 | if (MIN_NONDEBUG_INSN_UID) |
5670 | cur_insn_uid = MIN_NONDEBUG_INSN_UID; | |
5671 | else | |
5672 | cur_insn_uid = 1; | |
5673 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5674 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
23b2ce53 | 5675 | first_label_num = label_num; |
614d5bd8 | 5676 | get_current_sequence ()->next = NULL; |
23b2ce53 | 5677 | |
23b2ce53 RS |
5678 | /* Init the tables that describe all the pseudo regs. */ |
5679 | ||
3e029763 | 5680 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5681 | |
3e029763 | 5682 | crtl->emit.regno_pointer_align |
1b4572a8 | 5683 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5684 | |
766090c2 | 5685 | regno_reg_rtx = ggc_vec_alloc<rtx> (crtl->emit.regno_pointer_align_length); |
0d4903b8 | 5686 | |
e50126e8 | 5687 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 | 5688 | memcpy (regno_reg_rtx, |
5fb0e246 | 5689 | initial_regno_reg_rtx, |
6cde4876 | 5690 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
e50126e8 | 5691 | |
23b2ce53 | 5692 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5693 | init_virtual_regs (); |
740ab4a2 RK |
5694 | |
5695 | /* Indicate that the virtual registers and stack locations are | |
5696 | all pointers. */ | |
3502dc9c JDA |
5697 | REG_POINTER (stack_pointer_rtx) = 1; |
5698 | REG_POINTER (frame_pointer_rtx) = 1; | |
5699 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5700 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5701 | |
3502dc9c JDA |
5702 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5703 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5704 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5705 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5706 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5707 | |
86fe05e0 | 5708 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5709 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5710 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5711 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5712 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5713 | ||
5714 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5715 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5716 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5717 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5718 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5719 | #endif |
5720 | ||
5e82e7bd JVA |
5721 | #ifdef INIT_EXPANDERS |
5722 | INIT_EXPANDERS; | |
5723 | #endif | |
23b2ce53 RS |
5724 | } |
5725 | ||
a73b091d | 5726 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
69ef87e2 AH |
5727 | |
5728 | static rtx | |
ef4bddc2 | 5729 | gen_const_vector (machine_mode mode, int constant) |
69ef87e2 AH |
5730 | { |
5731 | rtx tem; | |
5732 | rtvec v; | |
5733 | int units, i; | |
ef4bddc2 | 5734 | machine_mode inner; |
69ef87e2 AH |
5735 | |
5736 | units = GET_MODE_NUNITS (mode); | |
5737 | inner = GET_MODE_INNER (mode); | |
5738 | ||
15ed7b52 JG |
5739 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5740 | ||
69ef87e2 AH |
5741 | v = rtvec_alloc (units); |
5742 | ||
a73b091d JW |
5743 | /* We need to call this function after we set the scalar const_tiny_rtx |
5744 | entries. */ | |
5745 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
69ef87e2 AH |
5746 | |
5747 | for (i = 0; i < units; ++i) | |
a73b091d | 5748 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
69ef87e2 | 5749 | |
a06e3c40 | 5750 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5751 | return tem; |
5752 | } | |
5753 | ||
a06e3c40 | 5754 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5755 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5756 | rtx |
ef4bddc2 | 5757 | gen_rtx_CONST_VECTOR (machine_mode mode, rtvec v) |
a06e3c40 | 5758 | { |
ef4bddc2 | 5759 | machine_mode inner = GET_MODE_INNER (mode); |
a73b091d JW |
5760 | int nunits = GET_MODE_NUNITS (mode); |
5761 | rtx x; | |
a06e3c40 R |
5762 | int i; |
5763 | ||
a73b091d JW |
5764 | /* Check to see if all of the elements have the same value. */ |
5765 | x = RTVEC_ELT (v, nunits - 1); | |
5766 | for (i = nunits - 2; i >= 0; i--) | |
5767 | if (RTVEC_ELT (v, i) != x) | |
5768 | break; | |
5769 | ||
5770 | /* If the values are all the same, check to see if we can use one of the | |
5771 | standard constant vectors. */ | |
5772 | if (i == -1) | |
5773 | { | |
5774 | if (x == CONST0_RTX (inner)) | |
5775 | return CONST0_RTX (mode); | |
5776 | else if (x == CONST1_RTX (inner)) | |
5777 | return CONST1_RTX (mode); | |
e7c82a99 JJ |
5778 | else if (x == CONSTM1_RTX (inner)) |
5779 | return CONSTM1_RTX (mode); | |
a73b091d JW |
5780 | } |
5781 | ||
5782 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5783 | } |
5784 | ||
b5deb7b6 SL |
5785 | /* Initialise global register information required by all functions. */ |
5786 | ||
5787 | void | |
5788 | init_emit_regs (void) | |
5789 | { | |
5790 | int i; | |
ef4bddc2 | 5791 | machine_mode mode; |
1c3f523e | 5792 | mem_attrs *attrs; |
b5deb7b6 SL |
5793 | |
5794 | /* Reset register attributes */ | |
aebf76a2 | 5795 | reg_attrs_htab->empty (); |
b5deb7b6 SL |
5796 | |
5797 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5798 | init_reg_modes_target (); | |
5799 | ||
5800 | /* Assign register numbers to the globally defined register rtx. */ | |
b5deb7b6 SL |
5801 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
5802 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5803 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5804 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5805 | virtual_incoming_args_rtx = | |
5806 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5807 | virtual_stack_vars_rtx = | |
5808 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5809 | virtual_stack_dynamic_rtx = | |
5810 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5811 | virtual_outgoing_args_rtx = | |
5812 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5813 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
32990d5b JJ |
5814 | virtual_preferred_stack_boundary_rtx = |
5815 | gen_raw_REG (Pmode, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM); | |
b5deb7b6 SL |
5816 | |
5817 | /* Initialize RTL for commonly used hard registers. These are | |
5818 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5819 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5fb0e246 | 5820 | initial_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); |
b5deb7b6 SL |
5821 | |
5822 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5823 | return_address_pointer_rtx | |
5824 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5825 | #endif | |
5826 | ||
ca72dad5 | 5827 | pic_offset_table_rtx = NULL_RTX; |
b5deb7b6 SL |
5828 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
5829 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
1c3f523e RS |
5830 | |
5831 | for (i = 0; i < (int) MAX_MACHINE_MODE; i++) | |
5832 | { | |
ef4bddc2 | 5833 | mode = (machine_mode) i; |
766090c2 | 5834 | attrs = ggc_cleared_alloc<mem_attrs> (); |
1c3f523e RS |
5835 | attrs->align = BITS_PER_UNIT; |
5836 | attrs->addrspace = ADDR_SPACE_GENERIC; | |
5837 | if (mode != BLKmode) | |
5838 | { | |
754c3d5d RS |
5839 | attrs->size_known_p = true; |
5840 | attrs->size = GET_MODE_SIZE (mode); | |
1c3f523e RS |
5841 | if (STRICT_ALIGNMENT) |
5842 | attrs->align = GET_MODE_ALIGNMENT (mode); | |
5843 | } | |
5844 | mode_mem_attrs[i] = attrs; | |
5845 | } | |
b5deb7b6 SL |
5846 | } |
5847 | ||
aa3a12d6 RS |
5848 | /* Initialize global machine_mode variables. */ |
5849 | ||
5850 | void | |
5851 | init_derived_machine_modes (void) | |
5852 | { | |
5853 | byte_mode = VOIDmode; | |
5854 | word_mode = VOIDmode; | |
5855 | ||
ef4bddc2 | 5856 | for (machine_mode mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
aa3a12d6 RS |
5857 | mode != VOIDmode; |
5858 | mode = GET_MODE_WIDER_MODE (mode)) | |
5859 | { | |
5860 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5861 | && byte_mode == VOIDmode) | |
5862 | byte_mode = mode; | |
5863 | ||
5864 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5865 | && word_mode == VOIDmode) | |
5866 | word_mode = mode; | |
5867 | } | |
5868 | ||
5869 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5870 | } | |
5871 | ||
2d888286 | 5872 | /* Create some permanent unique rtl objects shared between all functions. */ |
23b2ce53 RS |
5873 | |
5874 | void | |
2d888286 | 5875 | init_emit_once (void) |
23b2ce53 RS |
5876 | { |
5877 | int i; | |
ef4bddc2 RS |
5878 | machine_mode mode; |
5879 | machine_mode double_mode; | |
23b2ce53 | 5880 | |
807e902e KZ |
5881 | /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE, |
5882 | CONST_FIXED, and memory attribute hash tables. */ | |
aebf76a2 | 5883 | const_int_htab = hash_table<const_int_hasher>::create_ggc (37); |
173b24b9 | 5884 | |
807e902e | 5885 | #if TARGET_SUPPORTS_WIDE_INT |
aebf76a2 | 5886 | const_wide_int_htab = hash_table<const_wide_int_hasher>::create_ggc (37); |
807e902e | 5887 | #endif |
aebf76a2 | 5888 | const_double_htab = hash_table<const_double_hasher>::create_ggc (37); |
5692c7bc | 5889 | |
aebf76a2 | 5890 | const_fixed_htab = hash_table<const_fixed_hasher>::create_ggc (37); |
091a3ac7 | 5891 | |
aebf76a2 | 5892 | reg_attrs_htab = hash_table<reg_attr_hasher>::create_ggc (37); |
67673f5c | 5893 | |
5da077de | 5894 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5895 | /* This is to initialize {init|mark|free}_machine_status before the first |
5896 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5897 | end which calls push_function_context_to before the first call to |
5da077de AS |
5898 | init_function_start. */ |
5899 | INIT_EXPANDERS; | |
5900 | #endif | |
5901 | ||
23b2ce53 RS |
5902 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5903 | ||
a2a8cc44 | 5904 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 5905 | tries to use these variables. */ |
23b2ce53 | 5906 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5907 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5908 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5909 | |
68d75312 JC |
5910 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5911 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5912 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5913 | else |
3b80f6ca | 5914 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5915 | |
aa3a12d6 RS |
5916 | double_mode = mode_for_size (DOUBLE_TYPE_SIZE, MODE_FLOAT, 0); |
5917 | ||
807e902e KZ |
5918 | real_from_integer (&dconst0, double_mode, 0, SIGNED); |
5919 | real_from_integer (&dconst1, double_mode, 1, SIGNED); | |
5920 | real_from_integer (&dconst2, double_mode, 2, SIGNED); | |
aefa9d43 KG |
5921 | |
5922 | dconstm1 = dconst1; | |
5923 | dconstm1.sign = 1; | |
03f2ea93 RS |
5924 | |
5925 | dconsthalf = dconst1; | |
1e92bbb9 | 5926 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 5927 | |
e7c82a99 | 5928 | for (i = 0; i < 3; i++) |
23b2ce53 | 5929 | { |
aefa9d43 | 5930 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
5931 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
5932 | ||
15ed7b52 JG |
5933 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5934 | mode != VOIDmode; | |
5935 | mode = GET_MODE_WIDER_MODE (mode)) | |
5936 | const_tiny_rtx[i][(int) mode] = | |
5937 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5938 | ||
5939 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5940 | mode != VOIDmode; | |
23b2ce53 | 5941 | mode = GET_MODE_WIDER_MODE (mode)) |
5692c7bc ZW |
5942 | const_tiny_rtx[i][(int) mode] = |
5943 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5944 | |
906c4e36 | 5945 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 5946 | |
15ed7b52 JG |
5947 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5948 | mode != VOIDmode; | |
23b2ce53 | 5949 | mode = GET_MODE_WIDER_MODE (mode)) |
906c4e36 | 5950 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 | 5951 | |
ede6c734 MS |
5952 | for (mode = MIN_MODE_PARTIAL_INT; |
5953 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 5954 | mode = (machine_mode)((int)(mode) + 1)) |
33d3e559 | 5955 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
23b2ce53 RS |
5956 | } |
5957 | ||
e7c82a99 JJ |
5958 | const_tiny_rtx[3][(int) VOIDmode] = constm1_rtx; |
5959 | ||
5960 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
5961 | mode != VOIDmode; | |
5962 | mode = GET_MODE_WIDER_MODE (mode)) | |
5963 | const_tiny_rtx[3][(int) mode] = constm1_rtx; | |
5964 | ||
ede6c734 MS |
5965 | for (mode = MIN_MODE_PARTIAL_INT; |
5966 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 5967 | mode = (machine_mode)((int)(mode) + 1)) |
c8a89d2a BS |
5968 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
5969 | ||
e90721b1 AP |
5970 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5971 | mode != VOIDmode; | |
5972 | mode = GET_MODE_WIDER_MODE (mode)) | |
5973 | { | |
5974 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5975 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5976 | } | |
5977 | ||
5978 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5979 | mode != VOIDmode; | |
5980 | mode = GET_MODE_WIDER_MODE (mode)) | |
5981 | { | |
5982 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5983 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5984 | } | |
5985 | ||
69ef87e2 AH |
5986 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5987 | mode != VOIDmode; | |
5988 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5989 | { |
5990 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5991 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
e7c82a99 | 5992 | const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3); |
a73b091d | 5993 | } |
69ef87e2 AH |
5994 | |
5995 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5996 | mode != VOIDmode; | |
5997 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5998 | { |
5999 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6000 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6001 | } | |
69ef87e2 | 6002 | |
325217ed CF |
6003 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
6004 | mode != VOIDmode; | |
6005 | mode = GET_MODE_WIDER_MODE (mode)) | |
6006 | { | |
c3284718 RS |
6007 | FCONST0 (mode).data.high = 0; |
6008 | FCONST0 (mode).data.low = 0; | |
6009 | FCONST0 (mode).mode = mode; | |
091a3ac7 CF |
6010 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
6011 | FCONST0 (mode), mode); | |
325217ed CF |
6012 | } |
6013 | ||
6014 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
6015 | mode != VOIDmode; | |
6016 | mode = GET_MODE_WIDER_MODE (mode)) | |
6017 | { | |
c3284718 RS |
6018 | FCONST0 (mode).data.high = 0; |
6019 | FCONST0 (mode).data.low = 0; | |
6020 | FCONST0 (mode).mode = mode; | |
091a3ac7 CF |
6021 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
6022 | FCONST0 (mode), mode); | |
325217ed CF |
6023 | } |
6024 | ||
6025 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
6026 | mode != VOIDmode; | |
6027 | mode = GET_MODE_WIDER_MODE (mode)) | |
6028 | { | |
c3284718 RS |
6029 | FCONST0 (mode).data.high = 0; |
6030 | FCONST0 (mode).data.low = 0; | |
6031 | FCONST0 (mode).mode = mode; | |
091a3ac7 CF |
6032 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
6033 | FCONST0 (mode), mode); | |
325217ed CF |
6034 | |
6035 | /* We store the value 1. */ | |
c3284718 RS |
6036 | FCONST1 (mode).data.high = 0; |
6037 | FCONST1 (mode).data.low = 0; | |
6038 | FCONST1 (mode).mode = mode; | |
6039 | FCONST1 (mode).data | |
9be0ac8c LC |
6040 | = double_int_one.lshift (GET_MODE_FBIT (mode), |
6041 | HOST_BITS_PER_DOUBLE_INT, | |
6042 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
6043 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
6044 | FCONST1 (mode), mode); | |
325217ed CF |
6045 | } |
6046 | ||
6047 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
6048 | mode != VOIDmode; | |
6049 | mode = GET_MODE_WIDER_MODE (mode)) | |
6050 | { | |
c3284718 RS |
6051 | FCONST0 (mode).data.high = 0; |
6052 | FCONST0 (mode).data.low = 0; | |
6053 | FCONST0 (mode).mode = mode; | |
091a3ac7 CF |
6054 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
6055 | FCONST0 (mode), mode); | |
325217ed CF |
6056 | |
6057 | /* We store the value 1. */ | |
c3284718 RS |
6058 | FCONST1 (mode).data.high = 0; |
6059 | FCONST1 (mode).data.low = 0; | |
6060 | FCONST1 (mode).mode = mode; | |
6061 | FCONST1 (mode).data | |
9be0ac8c LC |
6062 | = double_int_one.lshift (GET_MODE_FBIT (mode), |
6063 | HOST_BITS_PER_DOUBLE_INT, | |
6064 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
6065 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
6066 | FCONST1 (mode), mode); | |
6067 | } | |
6068 | ||
6069 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT); | |
6070 | mode != VOIDmode; | |
6071 | mode = GET_MODE_WIDER_MODE (mode)) | |
6072 | { | |
6073 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6074 | } | |
6075 | ||
6076 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT); | |
6077 | mode != VOIDmode; | |
6078 | mode = GET_MODE_WIDER_MODE (mode)) | |
6079 | { | |
6080 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6081 | } | |
6082 | ||
6083 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM); | |
6084 | mode != VOIDmode; | |
6085 | mode = GET_MODE_WIDER_MODE (mode)) | |
6086 | { | |
6087 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6088 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6089 | } | |
6090 | ||
6091 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM); | |
6092 | mode != VOIDmode; | |
6093 | mode = GET_MODE_WIDER_MODE (mode)) | |
6094 | { | |
6095 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6096 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
6097 | } |
6098 | ||
dbbbbf3b | 6099 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
ef4bddc2 | 6100 | if (GET_MODE_CLASS ((machine_mode) i) == MODE_CC) |
dbbbbf3b | 6101 | const_tiny_rtx[0][i] = const0_rtx; |
23b2ce53 | 6102 | |
f0417c82 RH |
6103 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
6104 | if (STORE_FLAG_VALUE == 1) | |
6105 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
ca4adc91 | 6106 | |
d5e254e1 IE |
6107 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_POINTER_BOUNDS); |
6108 | mode != VOIDmode; | |
6109 | mode = GET_MODE_WIDER_MODE (mode)) | |
6110 | { | |
6111 | wide_int wi_zero = wi::zero (GET_MODE_PRECISION (mode)); | |
6112 | const_tiny_rtx[0][mode] = immed_wide_int_const (wi_zero, mode); | |
6113 | } | |
6114 | ||
ca4adc91 RS |
6115 | pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); |
6116 | ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | |
6117 | simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); | |
6118 | cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode); | |
1476d1bd MM |
6119 | invalid_insn_rtx = gen_rtx_INSN (VOIDmode, |
6120 | /*prev_insn=*/NULL, | |
6121 | /*next_insn=*/NULL, | |
6122 | /*bb=*/NULL, | |
6123 | /*pattern=*/NULL_RTX, | |
6124 | /*location=*/-1, | |
6125 | CODE_FOR_nothing, | |
6126 | /*reg_notes=*/NULL_RTX); | |
23b2ce53 | 6127 | } |
a11759a3 | 6128 | \f |
969d70ca JH |
6129 | /* Produce exact duplicate of insn INSN after AFTER. |
6130 | Care updating of libcall regions if present. */ | |
6131 | ||
cd459bf8 | 6132 | rtx_insn * |
a1950df3 | 6133 | emit_copy_of_insn_after (rtx_insn *insn, rtx_insn *after) |
969d70ca | 6134 | { |
cd459bf8 DM |
6135 | rtx_insn *new_rtx; |
6136 | rtx link; | |
969d70ca JH |
6137 | |
6138 | switch (GET_CODE (insn)) | |
6139 | { | |
6140 | case INSN: | |
60564289 | 6141 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
6142 | break; |
6143 | ||
6144 | case JUMP_INSN: | |
60564289 | 6145 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
ec27069c | 6146 | CROSSING_JUMP_P (new_rtx) = CROSSING_JUMP_P (insn); |
969d70ca JH |
6147 | break; |
6148 | ||
b5b8b0ac AO |
6149 | case DEBUG_INSN: |
6150 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
6151 | break; | |
6152 | ||
969d70ca | 6153 | case CALL_INSN: |
60564289 | 6154 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 6155 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 6156 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 6157 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
6158 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
6159 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
6160 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
b8698a0f | 6161 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) |
becfd6e5 | 6162 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
6163 | break; |
6164 | ||
6165 | default: | |
5b0264cb | 6166 | gcc_unreachable (); |
969d70ca JH |
6167 | } |
6168 | ||
6169 | /* Update LABEL_NUSES. */ | |
60564289 | 6170 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 6171 | |
5368224f | 6172 | INSN_LOCATION (new_rtx) = INSN_LOCATION (insn); |
ba4f7968 | 6173 | |
0a3d71f5 JW |
6174 | /* If the old insn is frame related, then so is the new one. This is |
6175 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
6176 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 6177 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 6178 | |
cf7c4aa6 HPN |
6179 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
6180 | will make them. REG_LABEL_TARGETs are created there too, but are | |
6181 | supposed to be sticky, so we copy them. */ | |
969d70ca | 6182 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 6183 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca JH |
6184 | { |
6185 | if (GET_CODE (link) == EXPR_LIST) | |
60564289 | 6186 | add_reg_note (new_rtx, REG_NOTE_KIND (link), |
65c5f2a6 | 6187 | copy_insn_1 (XEXP (link, 0))); |
969d70ca | 6188 | else |
e5af9ddd | 6189 | add_shallow_copy_of_reg_note (new_rtx, link); |
969d70ca JH |
6190 | } |
6191 | ||
60564289 KG |
6192 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
6193 | return new_rtx; | |
969d70ca | 6194 | } |
e2500fed | 6195 | |
1431042e | 6196 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d | 6197 | rtx |
ef4bddc2 | 6198 | gen_hard_reg_clobber (machine_mode mode, unsigned int regno) |
3e89ed8d JH |
6199 | { |
6200 | if (hard_reg_clobbers[mode][regno]) | |
6201 | return hard_reg_clobbers[mode][regno]; | |
6202 | else | |
6203 | return (hard_reg_clobbers[mode][regno] = | |
6204 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
6205 | } | |
6206 | ||
5368224f DC |
6207 | location_t prologue_location; |
6208 | location_t epilogue_location; | |
78bde837 SB |
6209 | |
6210 | /* Hold current location information and last location information, so the | |
6211 | datastructures are built lazily only when some instructions in given | |
6212 | place are needed. */ | |
3a50da34 | 6213 | static location_t curr_location; |
78bde837 | 6214 | |
5368224f | 6215 | /* Allocate insn location datastructure. */ |
78bde837 | 6216 | void |
5368224f | 6217 | insn_locations_init (void) |
78bde837 | 6218 | { |
5368224f | 6219 | prologue_location = epilogue_location = 0; |
78bde837 | 6220 | curr_location = UNKNOWN_LOCATION; |
78bde837 SB |
6221 | } |
6222 | ||
6223 | /* At the end of emit stage, clear current location. */ | |
6224 | void | |
5368224f | 6225 | insn_locations_finalize (void) |
78bde837 | 6226 | { |
5368224f DC |
6227 | epilogue_location = curr_location; |
6228 | curr_location = UNKNOWN_LOCATION; | |
78bde837 SB |
6229 | } |
6230 | ||
6231 | /* Set current location. */ | |
6232 | void | |
5368224f | 6233 | set_curr_insn_location (location_t location) |
78bde837 | 6234 | { |
78bde837 SB |
6235 | curr_location = location; |
6236 | } | |
6237 | ||
6238 | /* Get current location. */ | |
6239 | location_t | |
5368224f | 6240 | curr_insn_location (void) |
78bde837 SB |
6241 | { |
6242 | return curr_location; | |
6243 | } | |
6244 | ||
78bde837 SB |
6245 | /* Return lexical scope block insn belongs to. */ |
6246 | tree | |
a1950df3 | 6247 | insn_scope (const rtx_insn *insn) |
78bde837 | 6248 | { |
5368224f | 6249 | return LOCATION_BLOCK (INSN_LOCATION (insn)); |
78bde837 SB |
6250 | } |
6251 | ||
6252 | /* Return line number of the statement that produced this insn. */ | |
6253 | int | |
a1950df3 | 6254 | insn_line (const rtx_insn *insn) |
78bde837 | 6255 | { |
5368224f | 6256 | return LOCATION_LINE (INSN_LOCATION (insn)); |
78bde837 SB |
6257 | } |
6258 | ||
6259 | /* Return source file of the statement that produced this insn. */ | |
6260 | const char * | |
a1950df3 | 6261 | insn_file (const rtx_insn *insn) |
78bde837 | 6262 | { |
5368224f | 6263 | return LOCATION_FILE (INSN_LOCATION (insn)); |
78bde837 | 6264 | } |
8930883e | 6265 | |
ffa4602f EB |
6266 | /* Return expanded location of the statement that produced this insn. */ |
6267 | expanded_location | |
a1950df3 | 6268 | insn_location (const rtx_insn *insn) |
ffa4602f EB |
6269 | { |
6270 | return expand_location (INSN_LOCATION (insn)); | |
6271 | } | |
6272 | ||
8930883e MK |
6273 | /* Return true if memory model MODEL requires a pre-operation (release-style) |
6274 | barrier or a post-operation (acquire-style) barrier. While not universal, | |
6275 | this function matches behavior of several targets. */ | |
6276 | ||
6277 | bool | |
6278 | need_atomic_barrier_p (enum memmodel model, bool pre) | |
6279 | { | |
40ad260d | 6280 | switch (model & MEMMODEL_BASE_MASK) |
8930883e MK |
6281 | { |
6282 | case MEMMODEL_RELAXED: | |
6283 | case MEMMODEL_CONSUME: | |
6284 | return false; | |
6285 | case MEMMODEL_RELEASE: | |
6286 | return pre; | |
6287 | case MEMMODEL_ACQUIRE: | |
6288 | return !pre; | |
6289 | case MEMMODEL_ACQ_REL: | |
6290 | case MEMMODEL_SEQ_CST: | |
6291 | return true; | |
6292 | default: | |
6293 | gcc_unreachable (); | |
6294 | } | |
6295 | } | |
6296 | \f | |
e2500fed | 6297 | #include "gt-emit-rtl.h" |