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bccafa26 | 1 | /* Emit RTL for the GCC expander. |
ddca3e9d | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
1a6a0f2a | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
535664e3 | 4 | Free Software Foundation, Inc. |
15bbde2b | 5 | |
f12b58b3 | 6 | This file is part of GCC. |
15bbde2b | 7 | |
f12b58b3 | 8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 10 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 11 | version. |
15bbde2b | 12 | |
f12b58b3 | 13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
15bbde2b | 17 | |
18 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
15bbde2b | 21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
74efa612 | 25 | This file contains support functions for creating rtl expressions |
26 | and manipulating them in the doubly-linked chain of insns. | |
15bbde2b | 27 | |
28 | The patterns of the insns are created by machine-dependent | |
29 | routines in insn-emit.c, which is generated automatically from | |
74efa612 | 30 | the machine description. These routines make the individual rtx's |
31 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
32 | which are automatically generated from rtl.def; what is machine | |
8fd5918e | 33 | dependent is the kind of rtx's they make and what arguments they |
34 | use. */ | |
15bbde2b | 35 | |
36 | #include "config.h" | |
405711de | 37 | #include "system.h" |
805e22b2 | 38 | #include "coretypes.h" |
39 | #include "tm.h" | |
d3b64f2d | 40 | #include "toplev.h" |
15bbde2b | 41 | #include "rtl.h" |
3fd7e17f | 42 | #include "tree.h" |
7953c610 | 43 | #include "tm_p.h" |
15bbde2b | 44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
c6b6c51f | 48 | #include "hard-reg-set.h" |
73f5c1e3 | 49 | #include "hashtab.h" |
15bbde2b | 50 | #include "insn-config.h" |
0dbd1c74 | 51 | #include "recog.h" |
15bbde2b | 52 | #include "real.h" |
06f0b99c | 53 | #include "fixed-value.h" |
a3426c4c | 54 | #include "bitmap.h" |
f3d96a58 | 55 | #include "basic-block.h" |
a7b0c170 | 56 | #include "ggc.h" |
b29760a8 | 57 | #include "debug.h" |
b0278d39 | 58 | #include "langhooks.h" |
77fce4cd | 59 | #include "tree-pass.h" |
3072d30e | 60 | #include "df.h" |
649d8da6 | 61 | |
399d45d3 | 62 | /* Commonly used modes. */ |
63 | ||
a92771b8 | 64 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
65 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9e042f31 | 66 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
a92771b8 | 67 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
399d45d3 | 68 | |
15bbde2b | 69 | |
70 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
71 | in the entire compilation a unique label number. */ | |
72 | ||
9105005a | 73 | static GTY(()) int label_num = 1; |
15bbde2b | 74 | |
15bbde2b | 75 | /* Nonzero means do not generate NOTEs for source line numbers. */ |
76 | ||
77 | static int no_line_numbers; | |
78 | ||
79 | /* Commonly used rtx's, so that we only need space for one copy. | |
80 | These are initialized once for the entire compilation. | |
2ff23ed0 | 81 | All of these are unique; no other rtx-object will be equal to any |
82 | of these. */ | |
15bbde2b | 83 | |
57c097d5 | 84 | rtx global_rtl[GR_MAX]; |
15bbde2b | 85 | |
90295bd2 | 86 | /* Commonly used RTL for hard registers. These objects are not necessarily |
87 | unique, so we allocate them separately from global_rtl. They are | |
88 | initialized once per compilation unit, then copied into regno_reg_rtx | |
89 | at the beginning of each function. */ | |
90 | static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
91 | ||
15bbde2b | 92 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
93 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
94 | record a copy of const[012]_rtx. */ | |
95 | ||
96 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
97 | ||
1a60f06a | 98 | rtx const_true_rtx; |
99 | ||
15bbde2b | 100 | REAL_VALUE_TYPE dconst0; |
101 | REAL_VALUE_TYPE dconst1; | |
102 | REAL_VALUE_TYPE dconst2; | |
8918c507 | 103 | REAL_VALUE_TYPE dconst3; |
104 | REAL_VALUE_TYPE dconst10; | |
15bbde2b | 105 | REAL_VALUE_TYPE dconstm1; |
77e89269 | 106 | REAL_VALUE_TYPE dconstm2; |
107 | REAL_VALUE_TYPE dconsthalf; | |
8918c507 | 108 | REAL_VALUE_TYPE dconstthird; |
2e7ca27b | 109 | REAL_VALUE_TYPE dconstsqrt2; |
79082756 | 110 | REAL_VALUE_TYPE dconste; |
15bbde2b | 111 | |
06f0b99c | 112 | /* Record fixed-point constant 0 and 1. */ |
113 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
114 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
115 | ||
15bbde2b | 116 | /* All references to the following fixed hard registers go through |
117 | these unique rtl objects. On machines where the frame-pointer and | |
118 | arg-pointer are the same register, they use the same unique object. | |
119 | ||
120 | After register allocation, other rtl objects which used to be pseudo-regs | |
121 | may be clobbered to refer to the frame-pointer register. | |
122 | But references that were originally to the frame-pointer can be | |
123 | distinguished from the others because they contain frame_pointer_rtx. | |
124 | ||
90c25824 | 125 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
126 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
d823ba47 | 127 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
90c25824 | 128 | register elimination hard_frame_pointer_rtx should always be used. |
129 | On machines where the two registers are same (most) then these are the | |
130 | same. | |
131 | ||
15bbde2b | 132 | In an inline procedure, the stack and frame pointer rtxs may not be |
133 | used for anything else. */ | |
15bbde2b | 134 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ |
135 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
136 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
137 | ||
4b0c5859 | 138 | /* This is used to implement __builtin_return_address for some machines. |
139 | See for instance the MIPS port. */ | |
140 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
141 | ||
15bbde2b | 142 | /* We make one copy of (const_int C) where C is in |
143 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
144 | to save space during the compilation and simplify comparisons of | |
145 | integers. */ | |
146 | ||
57c097d5 | 147 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
15bbde2b | 148 | |
73f5c1e3 | 149 | /* A hash table storing CONST_INTs whose absolute value is greater |
150 | than MAX_SAVED_CONST_INT. */ | |
151 | ||
1f3233d1 | 152 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
153 | htab_t const_int_htab; | |
73f5c1e3 | 154 | |
c6259b83 | 155 | /* A hash table storing memory attribute structures. */ |
1f3233d1 | 156 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
157 | htab_t mem_attrs_htab; | |
c6259b83 | 158 | |
ca74b940 | 159 | /* A hash table storing register attribute structures. */ |
160 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
161 | htab_t reg_attrs_htab; | |
162 | ||
2ff23ed0 | 163 | /* A hash table storing all CONST_DOUBLEs. */ |
1f3233d1 | 164 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
165 | htab_t const_double_htab; | |
2ff23ed0 | 166 | |
08513b52 | 167 | #define first_insn (cfun->emit->x_first_insn) |
168 | #define last_insn (cfun->emit->x_last_insn) | |
169 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
0a3b3d88 | 170 | #define last_location (cfun->emit->x_last_location) |
08513b52 | 171 | #define first_label_num (cfun->emit->x_first_label_num) |
15bbde2b | 172 | |
35cb5232 | 173 | static rtx make_call_insn_raw (rtx); |
35cb5232 | 174 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); |
265be050 | 175 | static void set_used_decls (tree); |
35cb5232 | 176 | static void mark_label_nuses (rtx); |
177 | static hashval_t const_int_htab_hash (const void *); | |
178 | static int const_int_htab_eq (const void *, const void *); | |
179 | static hashval_t const_double_htab_hash (const void *); | |
180 | static int const_double_htab_eq (const void *, const void *); | |
181 | static rtx lookup_const_double (rtx); | |
182 | static hashval_t mem_attrs_htab_hash (const void *); | |
183 | static int mem_attrs_htab_eq (const void *, const void *); | |
32c2fdea | 184 | static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int, |
35cb5232 | 185 | enum machine_mode); |
186 | static hashval_t reg_attrs_htab_hash (const void *); | |
187 | static int reg_attrs_htab_eq (const void *, const void *); | |
188 | static reg_attrs *get_reg_attrs (tree, int); | |
189 | static tree component_ref_for_mem_expr (tree); | |
6e68dcb2 | 190 | static rtx gen_const_vector (enum machine_mode, int); |
0e0727c4 | 191 | static void copy_rtx_if_shared_1 (rtx *orig); |
73f5c1e3 | 192 | |
3cd757b1 | 193 | /* Probability of the conditional branch currently proceeded by try_split. |
194 | Set to -1 otherwise. */ | |
195 | int split_branch_probability = -1; | |
649d8da6 | 196 | \f |
73f5c1e3 | 197 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
198 | ||
199 | static hashval_t | |
35cb5232 | 200 | const_int_htab_hash (const void *x) |
73f5c1e3 | 201 | { |
dd9b9fc5 | 202 | return (hashval_t) INTVAL ((const_rtx) x); |
73f5c1e3 | 203 | } |
204 | ||
6ef828f9 | 205 | /* Returns nonzero if the value represented by X (which is really a |
73f5c1e3 | 206 | CONST_INT) is the same as that given by Y (which is really a |
207 | HOST_WIDE_INT *). */ | |
208 | ||
209 | static int | |
35cb5232 | 210 | const_int_htab_eq (const void *x, const void *y) |
73f5c1e3 | 211 | { |
dd9b9fc5 | 212 | return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y)); |
2ff23ed0 | 213 | } |
214 | ||
215 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
216 | static hashval_t | |
35cb5232 | 217 | const_double_htab_hash (const void *x) |
2ff23ed0 | 218 | { |
dd9b9fc5 | 219 | const_rtx const value = (const_rtx) x; |
3393215f | 220 | hashval_t h; |
2ff23ed0 | 221 | |
3393215f | 222 | if (GET_MODE (value) == VOIDmode) |
223 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
224 | else | |
a5760913 | 225 | { |
e2e205b3 | 226 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
a5760913 | 227 | /* MODE is used in the comparison, so it should be in the hash. */ |
228 | h ^= GET_MODE (value); | |
229 | } | |
2ff23ed0 | 230 | return h; |
231 | } | |
232 | ||
6ef828f9 | 233 | /* Returns nonzero if the value represented by X (really a ...) |
2ff23ed0 | 234 | is the same as that represented by Y (really a ...) */ |
235 | static int | |
35cb5232 | 236 | const_double_htab_eq (const void *x, const void *y) |
2ff23ed0 | 237 | { |
dd9b9fc5 | 238 | const_rtx const a = (const_rtx)x, b = (const_rtx)y; |
2ff23ed0 | 239 | |
240 | if (GET_MODE (a) != GET_MODE (b)) | |
241 | return 0; | |
f82a103d | 242 | if (GET_MODE (a) == VOIDmode) |
243 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
244 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
245 | else | |
246 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
247 | CONST_DOUBLE_REAL_VALUE (b)); | |
73f5c1e3 | 248 | } |
249 | ||
c6259b83 | 250 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
251 | ||
252 | static hashval_t | |
35cb5232 | 253 | mem_attrs_htab_hash (const void *x) |
c6259b83 | 254 | { |
dd9b9fc5 | 255 | const mem_attrs *const p = (const mem_attrs *) x; |
c6259b83 | 256 | |
257 | return (p->alias ^ (p->align * 1000) | |
258 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) | |
259 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
2f16183e | 260 | ^ (size_t) iterative_hash_expr (p->expr, 0)); |
c6259b83 | 261 | } |
262 | ||
6ef828f9 | 263 | /* Returns nonzero if the value represented by X (which is really a |
c6259b83 | 264 | mem_attrs *) is the same as that given by Y (which is also really a |
265 | mem_attrs *). */ | |
73f5c1e3 | 266 | |
267 | static int | |
35cb5232 | 268 | mem_attrs_htab_eq (const void *x, const void *y) |
73f5c1e3 | 269 | { |
aae87fc3 | 270 | const mem_attrs *const p = (const mem_attrs *) x; |
271 | const mem_attrs *const q = (const mem_attrs *) y; | |
c6259b83 | 272 | |
2f16183e | 273 | return (p->alias == q->alias && p->offset == q->offset |
274 | && p->size == q->size && p->align == q->align | |
275 | && (p->expr == q->expr | |
276 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
277 | && operand_equal_p (p->expr, q->expr, 0)))); | |
73f5c1e3 | 278 | } |
279 | ||
c6259b83 | 280 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
5cc193e7 | 281 | one identical to it is not already in the table. We are doing this for |
282 | MEM of mode MODE. */ | |
c6259b83 | 283 | |
284 | static mem_attrs * | |
32c2fdea | 285 | get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size, |
35cb5232 | 286 | unsigned int align, enum machine_mode mode) |
c6259b83 | 287 | { |
288 | mem_attrs attrs; | |
289 | void **slot; | |
290 | ||
d5c80165 | 291 | /* If everything is the default, we can just return zero. |
292 | This must match what the corresponding MEM_* macros return when the | |
293 | field is not present. */ | |
b10dbbca | 294 | if (alias == 0 && expr == 0 && offset == 0 |
5cc193e7 | 295 | && (size == 0 |
296 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
d5c80165 | 297 | && (STRICT_ALIGNMENT && mode != BLKmode |
298 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
5cc193e7 | 299 | return 0; |
300 | ||
c6259b83 | 301 | attrs.alias = alias; |
b10dbbca | 302 | attrs.expr = expr; |
c6259b83 | 303 | attrs.offset = offset; |
304 | attrs.size = size; | |
305 | attrs.align = align; | |
306 | ||
307 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
308 | if (*slot == 0) | |
309 | { | |
310 | *slot = ggc_alloc (sizeof (mem_attrs)); | |
311 | memcpy (*slot, &attrs, sizeof (mem_attrs)); | |
312 | } | |
313 | ||
314 | return *slot; | |
73f5c1e3 | 315 | } |
316 | ||
ca74b940 | 317 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
318 | ||
319 | static hashval_t | |
35cb5232 | 320 | reg_attrs_htab_hash (const void *x) |
ca74b940 | 321 | { |
aae87fc3 | 322 | const reg_attrs *const p = (const reg_attrs *) x; |
ca74b940 | 323 | |
324 | return ((p->offset * 1000) ^ (long) p->decl); | |
325 | } | |
326 | ||
7ef5b942 | 327 | /* Returns nonzero if the value represented by X (which is really a |
ca74b940 | 328 | reg_attrs *) is the same as that given by Y (which is also really a |
329 | reg_attrs *). */ | |
330 | ||
331 | static int | |
35cb5232 | 332 | reg_attrs_htab_eq (const void *x, const void *y) |
ca74b940 | 333 | { |
aae87fc3 | 334 | const reg_attrs *const p = (const reg_attrs *) x; |
335 | const reg_attrs *const q = (const reg_attrs *) y; | |
ca74b940 | 336 | |
337 | return (p->decl == q->decl && p->offset == q->offset); | |
338 | } | |
339 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
340 | one identical to it is not already in the table. We are doing this for | |
341 | MEM of mode MODE. */ | |
342 | ||
343 | static reg_attrs * | |
35cb5232 | 344 | get_reg_attrs (tree decl, int offset) |
ca74b940 | 345 | { |
346 | reg_attrs attrs; | |
347 | void **slot; | |
348 | ||
349 | /* If everything is the default, we can just return zero. */ | |
350 | if (decl == 0 && offset == 0) | |
351 | return 0; | |
352 | ||
353 | attrs.decl = decl; | |
354 | attrs.offset = offset; | |
355 | ||
356 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
357 | if (*slot == 0) | |
358 | { | |
359 | *slot = ggc_alloc (sizeof (reg_attrs)); | |
360 | memcpy (*slot, &attrs, sizeof (reg_attrs)); | |
361 | } | |
362 | ||
363 | return *slot; | |
364 | } | |
365 | ||
3072d30e | 366 | |
367 | #if !HAVE_blockage | |
368 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule | |
369 | across this insn. */ | |
370 | ||
371 | rtx | |
372 | gen_blockage (void) | |
373 | { | |
374 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
375 | MEM_VOLATILE_P (x) = true; | |
376 | return x; | |
377 | } | |
378 | #endif | |
379 | ||
380 | ||
22cf44bc | 381 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
382 | don't attempt to share with the various global pieces of rtl (such as | |
383 | frame_pointer_rtx). */ | |
384 | ||
385 | rtx | |
35cb5232 | 386 | gen_raw_REG (enum machine_mode mode, int regno) |
22cf44bc | 387 | { |
388 | rtx x = gen_rtx_raw_REG (mode, regno); | |
389 | ORIGINAL_REGNO (x) = regno; | |
390 | return x; | |
391 | } | |
392 | ||
7014838c | 393 | /* There are some RTL codes that require special attention; the generation |
394 | functions do the raw handling. If you add to this list, modify | |
395 | special_rtx in gengenrtl.c as well. */ | |
396 | ||
3ad7bb1c | 397 | rtx |
35cb5232 | 398 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3ad7bb1c | 399 | { |
73f5c1e3 | 400 | void **slot; |
401 | ||
3ad7bb1c | 402 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
57c097d5 | 403 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3ad7bb1c | 404 | |
405 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
406 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
407 | return const_true_rtx; | |
408 | #endif | |
409 | ||
73f5c1e3 | 410 | /* Look up the CONST_INT in the hash table. */ |
2b3dbc20 | 411 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
412 | (hashval_t) arg, INSERT); | |
7f2875d3 | 413 | if (*slot == 0) |
d7c47c0e | 414 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
73f5c1e3 | 415 | |
416 | return (rtx) *slot; | |
3ad7bb1c | 417 | } |
418 | ||
2d232d05 | 419 | rtx |
35cb5232 | 420 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2d232d05 | 421 | { |
422 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
423 | } | |
424 | ||
2ff23ed0 | 425 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
426 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
427 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
428 | ||
429 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
430 | hash table. If so, return its counterpart; otherwise add it | |
431 | to the hash table and return it. */ | |
432 | static rtx | |
35cb5232 | 433 | lookup_const_double (rtx real) |
2ff23ed0 | 434 | { |
435 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
436 | if (*slot == 0) | |
437 | *slot = real; | |
438 | ||
439 | return (rtx) *slot; | |
440 | } | |
7f2875d3 | 441 | |
2ff23ed0 | 442 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
443 | VALUE in mode MODE. */ | |
67f2a2eb | 444 | rtx |
35cb5232 | 445 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
67f2a2eb | 446 | { |
2ff23ed0 | 447 | rtx real = rtx_alloc (CONST_DOUBLE); |
448 | PUT_MODE (real, mode); | |
449 | ||
e8aaae4e | 450 | real->u.rv = value; |
2ff23ed0 | 451 | |
452 | return lookup_const_double (real); | |
453 | } | |
454 | ||
455 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair | |
456 | of ints: I0 is the low-order word and I1 is the high-order word. | |
457 | Do not use this routine for non-integer modes; convert to | |
458 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
459 | ||
460 | rtx | |
35cb5232 | 461 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
2ff23ed0 | 462 | { |
463 | rtx value; | |
464 | unsigned int i; | |
465 | ||
b1ca4af4 | 466 | /* There are the following cases (note that there are no modes with |
467 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT): | |
468 | ||
469 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
470 | gen_int_mode. | |
471 | 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of | |
472 | the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only | |
473 | from copies of the sign bit, and sign of i0 and i1 are the same), then | |
474 | we return a CONST_INT for i0. | |
475 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ | |
2ff23ed0 | 476 | if (mode != VOIDmode) |
477 | { | |
611234b4 | 478 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
479 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
480 | /* We can get a 0 for an error mark. */ | |
481 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
482 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT); | |
2ff23ed0 | 483 | |
b1ca4af4 | 484 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
485 | return gen_int_mode (i0, mode); | |
486 | ||
487 | gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT); | |
2ff23ed0 | 488 | } |
489 | ||
490 | /* If this integer fits in one word, return a CONST_INT. */ | |
491 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
492 | return GEN_INT (i0); | |
493 | ||
494 | /* We use VOIDmode for integers. */ | |
495 | value = rtx_alloc (CONST_DOUBLE); | |
496 | PUT_MODE (value, VOIDmode); | |
497 | ||
498 | CONST_DOUBLE_LOW (value) = i0; | |
499 | CONST_DOUBLE_HIGH (value) = i1; | |
500 | ||
501 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
502 | XWINT (value, i) = 0; | |
503 | ||
504 | return lookup_const_double (value); | |
67f2a2eb | 505 | } |
506 | ||
3ad7bb1c | 507 | rtx |
35cb5232 | 508 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3ad7bb1c | 509 | { |
510 | /* In case the MD file explicitly references the frame pointer, have | |
511 | all such references point to the same frame pointer. This is | |
512 | used during frame pointer elimination to distinguish the explicit | |
513 | references to these registers from pseudos that happened to be | |
514 | assigned to them. | |
515 | ||
516 | If we have eliminated the frame pointer or arg pointer, we will | |
517 | be using it as a normal register, for example as a spill | |
518 | register. In such cases, we might be accessing it in a mode that | |
519 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
520 | ||
521 | Also don't do this when we are making new REGs in reload, since | |
522 | we don't want to get confused with the real pointers. */ | |
523 | ||
524 | if (mode == Pmode && !reload_in_progress) | |
525 | { | |
71801afc | 526 | if (regno == FRAME_POINTER_REGNUM |
527 | && (!reload_completed || frame_pointer_needed)) | |
3ad7bb1c | 528 | return frame_pointer_rtx; |
529 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
71801afc | 530 | if (regno == HARD_FRAME_POINTER_REGNUM |
531 | && (!reload_completed || frame_pointer_needed)) | |
3ad7bb1c | 532 | return hard_frame_pointer_rtx; |
533 | #endif | |
534 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
e8b59353 | 535 | if (regno == ARG_POINTER_REGNUM) |
3ad7bb1c | 536 | return arg_pointer_rtx; |
537 | #endif | |
538 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
e8b59353 | 539 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3ad7bb1c | 540 | return return_address_pointer_rtx; |
541 | #endif | |
3473aefe | 542 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
6ea47475 | 543 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
d4c5e26d | 544 | return pic_offset_table_rtx; |
e8b59353 | 545 | if (regno == STACK_POINTER_REGNUM) |
3ad7bb1c | 546 | return stack_pointer_rtx; |
547 | } | |
548 | ||
32b53d83 | 549 | #if 0 |
90295bd2 | 550 | /* If the per-function register table has been set up, try to re-use |
32b53d83 | 551 | an existing entry in that table to avoid useless generation of RTL. |
552 | ||
553 | This code is disabled for now until we can fix the various backends | |
554 | which depend on having non-shared hard registers in some cases. Long | |
555 | term we want to re-enable this code as it can significantly cut down | |
71801afc | 556 | on the amount of useless RTL that gets generated. |
557 | ||
558 | We'll also need to fix some code that runs after reload that wants to | |
559 | set ORIGINAL_REGNO. */ | |
560 | ||
90295bd2 | 561 | if (cfun |
562 | && cfun->emit | |
563 | && regno_reg_rtx | |
564 | && regno < FIRST_PSEUDO_REGISTER | |
565 | && reg_raw_mode[regno] == mode) | |
566 | return regno_reg_rtx[regno]; | |
32b53d83 | 567 | #endif |
90295bd2 | 568 | |
22cf44bc | 569 | return gen_raw_REG (mode, regno); |
3ad7bb1c | 570 | } |
571 | ||
b5ba9f3a | 572 | rtx |
35cb5232 | 573 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
b5ba9f3a | 574 | { |
575 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
576 | ||
577 | /* This field is not cleared by the mere allocation of the rtx, so | |
578 | we clear it here. */ | |
c6259b83 | 579 | MEM_ATTRS (rt) = 0; |
b5ba9f3a | 580 | |
581 | return rt; | |
582 | } | |
701e46d0 | 583 | |
e265a6da | 584 | /* Generate a memory referring to non-trapping constant memory. */ |
585 | ||
586 | rtx | |
587 | gen_const_mem (enum machine_mode mode, rtx addr) | |
588 | { | |
589 | rtx mem = gen_rtx_MEM (mode, addr); | |
590 | MEM_READONLY_P (mem) = 1; | |
591 | MEM_NOTRAP_P (mem) = 1; | |
592 | return mem; | |
593 | } | |
594 | ||
00060fc2 | 595 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
596 | save areas. */ | |
597 | ||
598 | rtx | |
599 | gen_frame_mem (enum machine_mode mode, rtx addr) | |
600 | { | |
601 | rtx mem = gen_rtx_MEM (mode, addr); | |
602 | MEM_NOTRAP_P (mem) = 1; | |
603 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
604 | return mem; | |
605 | } | |
606 | ||
607 | /* Generate a MEM referring to a temporary use of the stack, not part | |
608 | of the fixed stack frame. For example, something which is pushed | |
609 | by a target splitter. */ | |
610 | rtx | |
611 | gen_tmp_stack_mem (enum machine_mode mode, rtx addr) | |
612 | { | |
613 | rtx mem = gen_rtx_MEM (mode, addr); | |
614 | MEM_NOTRAP_P (mem) = 1; | |
615 | if (!current_function_calls_alloca) | |
616 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
617 | return mem; | |
618 | } | |
619 | ||
2166bbaa | 620 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
621 | this construct would be valid, and false otherwise. */ | |
622 | ||
623 | bool | |
624 | validate_subreg (enum machine_mode omode, enum machine_mode imode, | |
625 | rtx reg, unsigned int offset) | |
701e46d0 | 626 | { |
2166bbaa | 627 | unsigned int isize = GET_MODE_SIZE (imode); |
628 | unsigned int osize = GET_MODE_SIZE (omode); | |
629 | ||
630 | /* All subregs must be aligned. */ | |
631 | if (offset % osize != 0) | |
632 | return false; | |
633 | ||
634 | /* The subreg offset cannot be outside the inner object. */ | |
635 | if (offset >= isize) | |
636 | return false; | |
637 | ||
638 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
639 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
640 | Generally, backends are doing something sketchy but it'll take time to | |
641 | fix them all. */ | |
642 | if (omode == word_mode) | |
643 | ; | |
644 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
645 | is the culprit here, and not the backends. */ | |
646 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
647 | ; | |
648 | /* Allow component subregs of complex and vector. Though given the below | |
649 | extraction rules, it's not always clear what that means. */ | |
650 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
651 | && GET_MODE_INNER (imode) == omode) | |
652 | ; | |
653 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
654 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
655 | represent this. It's questionable if this ought to be represented at | |
656 | all -- why can't this all be hidden in post-reload splitters that make | |
657 | arbitrarily mode changes to the registers themselves. */ | |
658 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
659 | ; | |
660 | /* Subregs involving floating point modes are not allowed to | |
661 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
662 | (subreg:SI (reg:DF) 0) isn't. */ | |
663 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
664 | { | |
665 | if (isize != osize) | |
666 | return false; | |
667 | } | |
701e46d0 | 668 | |
2166bbaa | 669 | /* Paradoxical subregs must have offset zero. */ |
670 | if (osize > isize) | |
671 | return offset == 0; | |
672 | ||
673 | /* This is a normal subreg. Verify that the offset is representable. */ | |
674 | ||
675 | /* For hard registers, we already have most of these rules collected in | |
676 | subreg_offset_representable_p. */ | |
677 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
678 | { | |
679 | unsigned int regno = REGNO (reg); | |
680 | ||
681 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
682 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
683 | && GET_MODE_INNER (imode) == omode) | |
684 | ; | |
685 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
686 | return false; | |
701e46d0 | 687 | #endif |
2166bbaa | 688 | |
689 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
690 | } | |
691 | ||
692 | /* For pseudo registers, we want most of the same checks. Namely: | |
693 | If the register no larger than a word, the subreg must be lowpart. | |
694 | If the register is larger than a word, the subreg must be the lowpart | |
695 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
696 | Given that we've already checked mode/offset alignment, we only have | |
697 | to check subword subregs here. */ | |
698 | if (osize < UNITS_PER_WORD) | |
699 | { | |
700 | enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; | |
701 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); | |
702 | if (offset % UNITS_PER_WORD != low_off) | |
703 | return false; | |
704 | } | |
705 | return true; | |
706 | } | |
707 | ||
708 | rtx | |
709 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) | |
710 | { | |
711 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
2ff23ed0 | 712 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
701e46d0 | 713 | } |
714 | ||
c6259b83 | 715 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
716 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
717 | ||
701e46d0 | 718 | rtx |
35cb5232 | 719 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
701e46d0 | 720 | { |
721 | enum machine_mode inmode; | |
701e46d0 | 722 | |
723 | inmode = GET_MODE (reg); | |
724 | if (inmode == VOIDmode) | |
725 | inmode = mode; | |
81802af6 | 726 | return gen_rtx_SUBREG (mode, reg, |
727 | subreg_lowpart_offset (mode, inmode)); | |
701e46d0 | 728 | } |
7014838c | 729 | \f |
15bbde2b | 730 | /* gen_rtvec (n, [rt1, ..., rtn]) |
731 | ** | |
732 | ** This routine creates an rtvec and stores within it the | |
733 | ** pointers to rtx's which are its arguments. | |
734 | */ | |
735 | ||
736 | /*VARARGS1*/ | |
737 | rtvec | |
ee582a61 | 738 | gen_rtvec (int n, ...) |
15bbde2b | 739 | { |
7ad77798 | 740 | int i, save_n; |
15bbde2b | 741 | rtx *vector; |
ee582a61 | 742 | va_list p; |
15bbde2b | 743 | |
ee582a61 | 744 | va_start (p, n); |
15bbde2b | 745 | |
746 | if (n == 0) | |
747 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
748 | ||
f0af5a88 | 749 | vector = alloca (n * sizeof (rtx)); |
e5fcd76a | 750 | |
15bbde2b | 751 | for (i = 0; i < n; i++) |
752 | vector[i] = va_arg (p, rtx); | |
7ad77798 | 753 | |
754 | /* The definition of VA_* in K&R C causes `n' to go out of scope. */ | |
755 | save_n = n; | |
ee582a61 | 756 | va_end (p); |
15bbde2b | 757 | |
7ad77798 | 758 | return gen_rtvec_v (save_n, vector); |
15bbde2b | 759 | } |
760 | ||
761 | rtvec | |
35cb5232 | 762 | gen_rtvec_v (int n, rtx *argp) |
15bbde2b | 763 | { |
19cb6b50 | 764 | int i; |
765 | rtvec rt_val; | |
15bbde2b | 766 | |
767 | if (n == 0) | |
768 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
769 | ||
770 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
771 | ||
772 | for (i = 0; i < n; i++) | |
a4070a91 | 773 | rt_val->elem[i] = *argp++; |
15bbde2b | 774 | |
775 | return rt_val; | |
776 | } | |
777 | \f | |
778 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
779 | This pseudo is assigned the next sequential register number. */ | |
780 | ||
781 | rtx | |
35cb5232 | 782 | gen_reg_rtx (enum machine_mode mode) |
15bbde2b | 783 | { |
08513b52 | 784 | struct function *f = cfun; |
19cb6b50 | 785 | rtx val; |
15bbde2b | 786 | |
1b7ff857 | 787 | gcc_assert (can_create_pseudo_p ()); |
15bbde2b | 788 | |
316bc009 | 789 | if (generating_concat_p |
790 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
791 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
76c37538 | 792 | { |
793 | /* For complex modes, don't make a single pseudo. | |
794 | Instead, make a CONCAT of two pseudos. | |
795 | This allows noncontiguous allocation of the real and imaginary parts, | |
796 | which makes much better code. Besides, allocating DCmode | |
797 | pseudos overstrains reload on some machines like the 386. */ | |
798 | rtx realpart, imagpart; | |
e9e12845 | 799 | enum machine_mode partmode = GET_MODE_INNER (mode); |
76c37538 | 800 | |
801 | realpart = gen_reg_rtx (partmode); | |
802 | imagpart = gen_reg_rtx (partmode); | |
3ad7bb1c | 803 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
76c37538 | 804 | } |
805 | ||
ca74b940 | 806 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
fcdc122e | 807 | enough to have an element for this pseudo reg number. */ |
15bbde2b | 808 | |
e61a0a7f | 809 | if (reg_rtx_no == f->emit->regno_pointer_align_length) |
15bbde2b | 810 | { |
e61a0a7f | 811 | int old_size = f->emit->regno_pointer_align_length; |
26df1c5e | 812 | char *new; |
fcdc122e | 813 | rtx *new1; |
fcdc122e | 814 | |
1f3233d1 | 815 | new = ggc_realloc (f->emit->regno_pointer_align, old_size * 2); |
0a893c29 | 816 | memset (new + old_size, 0, old_size); |
4491f79f | 817 | f->emit->regno_pointer_align = (unsigned char *) new; |
0a893c29 | 818 | |
f0af5a88 | 819 | new1 = ggc_realloc (f->emit->x_regno_reg_rtx, |
820 | old_size * 2 * sizeof (rtx)); | |
0a893c29 | 821 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
15bbde2b | 822 | regno_reg_rtx = new1; |
823 | ||
e61a0a7f | 824 | f->emit->regno_pointer_align_length = old_size * 2; |
15bbde2b | 825 | } |
826 | ||
22cf44bc | 827 | val = gen_raw_REG (mode, reg_rtx_no); |
15bbde2b | 828 | regno_reg_rtx[reg_rtx_no++] = val; |
829 | return val; | |
830 | } | |
831 | ||
1a6a0f2a | 832 | /* Update NEW with the same attributes as REG, but offsetted by OFFSET. |
765f486d | 833 | Do the big endian correction if needed. */ |
ca74b940 | 834 | |
1a6a0f2a | 835 | static void |
836 | update_reg_offset (rtx new, rtx reg, int offset) | |
ca74b940 | 837 | { |
765f486d | 838 | tree decl; |
839 | HOST_WIDE_INT var_size; | |
840 | ||
841 | /* PR middle-end/14084 | |
842 | The problem appears when a variable is stored in a larger register | |
843 | and later it is used in the original mode or some mode in between | |
844 | or some part of variable is accessed. | |
845 | ||
846 | On little endian machines there is no problem because | |
847 | the REG_OFFSET of the start of the variable is the same when | |
848 | accessed in any mode (it is 0). | |
849 | ||
850 | However, this is not true on big endian machines. | |
851 | The offset of the start of the variable is different when accessed | |
852 | in different modes. | |
853 | When we are taking a part of the REG we have to change the OFFSET | |
854 | from offset WRT size of mode of REG to offset WRT size of variable. | |
855 | ||
856 | If we would not do the big endian correction the resulting REG_OFFSET | |
857 | would be larger than the size of the DECL. | |
858 | ||
859 | Examples of correction, for BYTES_BIG_ENDIAN WORDS_BIG_ENDIAN machine: | |
860 | ||
861 | REG.mode MODE DECL size old offset new offset description | |
862 | DI SI 4 4 0 int32 in SImode | |
863 | DI SI 1 4 0 char in SImode | |
864 | DI QI 1 7 0 char in QImode | |
865 | DI QI 4 5 1 1st element in QImode | |
866 | of char[4] | |
867 | DI HI 4 6 2 1st element in HImode | |
868 | of int16[2] | |
869 | ||
870 | If the size of DECL is equal or greater than the size of REG | |
871 | we can't do this correction because the register holds the | |
872 | whole variable or a part of the variable and thus the REG_OFFSET | |
873 | is already correct. */ | |
874 | ||
875 | decl = REG_EXPR (reg); | |
876 | if ((BYTES_BIG_ENDIAN || WORDS_BIG_ENDIAN) | |
877 | && decl != NULL | |
878 | && offset > 0 | |
1a6a0f2a | 879 | && GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (GET_MODE (new)) |
765f486d | 880 | && ((var_size = int_size_in_bytes (TREE_TYPE (decl))) > 0 |
881 | && var_size < GET_MODE_SIZE (GET_MODE (reg)))) | |
882 | { | |
883 | int offset_le; | |
884 | ||
885 | /* Convert machine endian to little endian WRT size of mode of REG. */ | |
886 | if (WORDS_BIG_ENDIAN) | |
887 | offset_le = ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset) | |
888 | / UNITS_PER_WORD) * UNITS_PER_WORD; | |
889 | else | |
890 | offset_le = (offset / UNITS_PER_WORD) * UNITS_PER_WORD; | |
891 | ||
892 | if (BYTES_BIG_ENDIAN) | |
893 | offset_le += ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset) | |
894 | % UNITS_PER_WORD); | |
895 | else | |
896 | offset_le += offset % UNITS_PER_WORD; | |
897 | ||
898 | if (offset_le >= var_size) | |
899 | { | |
900 | /* MODE is wider than the variable so the new reg will cover | |
901 | the whole variable so the resulting OFFSET should be 0. */ | |
902 | offset = 0; | |
903 | } | |
904 | else | |
905 | { | |
906 | /* Convert little endian to machine endian WRT size of variable. */ | |
907 | if (WORDS_BIG_ENDIAN) | |
908 | offset = ((var_size - 1 - offset_le) | |
909 | / UNITS_PER_WORD) * UNITS_PER_WORD; | |
910 | else | |
911 | offset = (offset_le / UNITS_PER_WORD) * UNITS_PER_WORD; | |
912 | ||
913 | if (BYTES_BIG_ENDIAN) | |
914 | offset += ((var_size - 1 - offset_le) | |
915 | % UNITS_PER_WORD); | |
916 | else | |
917 | offset += offset_le % UNITS_PER_WORD; | |
918 | } | |
919 | } | |
920 | ||
ca74b940 | 921 | REG_ATTRS (new) = get_reg_attrs (REG_EXPR (reg), |
35cb5232 | 922 | REG_OFFSET (reg) + offset); |
1a6a0f2a | 923 | } |
924 | ||
925 | /* Generate a register with same attributes as REG, but offsetted by | |
926 | OFFSET. */ | |
927 | ||
928 | rtx | |
929 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, | |
930 | int offset) | |
931 | { | |
932 | rtx new = gen_rtx_REG (mode, regno); | |
933 | ||
934 | update_reg_offset (new, reg, offset); | |
935 | return new; | |
936 | } | |
937 | ||
938 | /* Generate a new pseudo-register with the same attributes as REG, but | |
939 | offsetted by OFFSET. */ | |
940 | ||
941 | rtx | |
942 | gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset) | |
943 | { | |
944 | rtx new = gen_reg_rtx (mode); | |
945 | ||
946 | update_reg_offset (new, reg, offset); | |
ca74b940 | 947 | return new; |
948 | } | |
949 | ||
950 | /* Set the decl for MEM to DECL. */ | |
951 | ||
952 | void | |
35cb5232 | 953 | set_reg_attrs_from_mem (rtx reg, rtx mem) |
ca74b940 | 954 | { |
955 | if (MEM_OFFSET (mem) && GET_CODE (MEM_OFFSET (mem)) == CONST_INT) | |
956 | REG_ATTRS (reg) | |
957 | = get_reg_attrs (MEM_EXPR (mem), INTVAL (MEM_OFFSET (mem))); | |
958 | } | |
959 | ||
263c416c | 960 | /* Set the register attributes for registers contained in PARM_RTX. |
961 | Use needed values from memory attributes of MEM. */ | |
962 | ||
963 | void | |
35cb5232 | 964 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
263c416c | 965 | { |
8ad4c111 | 966 | if (REG_P (parm_rtx)) |
263c416c | 967 | set_reg_attrs_from_mem (parm_rtx, mem); |
968 | else if (GET_CODE (parm_rtx) == PARALLEL) | |
969 | { | |
970 | /* Check for a NULL entry in the first slot, used to indicate that the | |
971 | parameter goes both on the stack and in registers. */ | |
972 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
973 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
974 | { | |
975 | rtx x = XVECEXP (parm_rtx, 0, i); | |
8ad4c111 | 976 | if (REG_P (XEXP (x, 0))) |
263c416c | 977 | REG_ATTRS (XEXP (x, 0)) |
978 | = get_reg_attrs (MEM_EXPR (mem), | |
979 | INTVAL (XEXP (x, 1))); | |
980 | } | |
981 | } | |
982 | } | |
983 | ||
ca74b940 | 984 | /* Assign the RTX X to declaration T. */ |
985 | void | |
35cb5232 | 986 | set_decl_rtl (tree t, rtx x) |
ca74b940 | 987 | { |
5ded8c6f | 988 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; |
ca74b940 | 989 | |
ebfc27f5 | 990 | if (!x) |
991 | return; | |
992 | /* For register, we maintain the reverse information too. */ | |
8ad4c111 | 993 | if (REG_P (x)) |
ebfc27f5 | 994 | REG_ATTRS (x) = get_reg_attrs (t, 0); |
995 | else if (GET_CODE (x) == SUBREG) | |
996 | REG_ATTRS (SUBREG_REG (x)) | |
997 | = get_reg_attrs (t, -SUBREG_BYTE (x)); | |
998 | if (GET_CODE (x) == CONCAT) | |
999 | { | |
1000 | if (REG_P (XEXP (x, 0))) | |
1001 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1002 | if (REG_P (XEXP (x, 1))) | |
1003 | REG_ATTRS (XEXP (x, 1)) | |
1004 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1005 | } | |
1006 | if (GET_CODE (x) == PARALLEL) | |
1007 | { | |
1008 | int i; | |
1009 | for (i = 0; i < XVECLEN (x, 0); i++) | |
1010 | { | |
1011 | rtx y = XVECEXP (x, 0, i); | |
1012 | if (REG_P (XEXP (y, 0))) | |
1013 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1014 | } | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | /* Assign the RTX X to parameter declaration T. */ | |
1019 | void | |
1020 | set_decl_incoming_rtl (tree t, rtx x) | |
1021 | { | |
1022 | DECL_INCOMING_RTL (t) = x; | |
1023 | ||
ca74b940 | 1024 | if (!x) |
1025 | return; | |
917bbcab | 1026 | /* For register, we maintain the reverse information too. */ |
8ad4c111 | 1027 | if (REG_P (x)) |
ca74b940 | 1028 | REG_ATTRS (x) = get_reg_attrs (t, 0); |
1029 | else if (GET_CODE (x) == SUBREG) | |
1030 | REG_ATTRS (SUBREG_REG (x)) | |
1031 | = get_reg_attrs (t, -SUBREG_BYTE (x)); | |
1032 | if (GET_CODE (x) == CONCAT) | |
1033 | { | |
1034 | if (REG_P (XEXP (x, 0))) | |
1035 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1036 | if (REG_P (XEXP (x, 1))) | |
1037 | REG_ATTRS (XEXP (x, 1)) | |
1038 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1039 | } | |
1040 | if (GET_CODE (x) == PARALLEL) | |
1041 | { | |
85d25060 | 1042 | int i, start; |
1043 | ||
1044 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1045 | both on the stack and in registers. */ | |
1046 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1047 | start = 0; | |
1048 | else | |
1049 | start = 1; | |
1050 | ||
1051 | for (i = start; i < XVECLEN (x, 0); i++) | |
ca74b940 | 1052 | { |
1053 | rtx y = XVECEXP (x, 0, i); | |
1054 | if (REG_P (XEXP (y, 0))) | |
1055 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1056 | } | |
1057 | } | |
1058 | } | |
1059 | ||
de8ecfb5 | 1060 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1061 | ||
1062 | void | |
35cb5232 | 1063 | mark_user_reg (rtx reg) |
de8ecfb5 | 1064 | { |
1065 | if (GET_CODE (reg) == CONCAT) | |
1066 | { | |
1067 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1068 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1069 | } | |
de8ecfb5 | 1070 | else |
611234b4 | 1071 | { |
1072 | gcc_assert (REG_P (reg)); | |
1073 | REG_USERVAR_P (reg) = 1; | |
1074 | } | |
de8ecfb5 | 1075 | } |
1076 | ||
d4c332ff | 1077 | /* Identify REG as a probable pointer register and show its alignment |
1078 | as ALIGN, if nonzero. */ | |
15bbde2b | 1079 | |
1080 | void | |
35cb5232 | 1081 | mark_reg_pointer (rtx reg, int align) |
15bbde2b | 1082 | { |
e61a0a7f | 1083 | if (! REG_POINTER (reg)) |
612409a6 | 1084 | { |
e61a0a7f | 1085 | REG_POINTER (reg) = 1; |
d4c332ff | 1086 | |
612409a6 | 1087 | if (align) |
1088 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1089 | } | |
1090 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
8b332087 | 1091 | /* We can no-longer be sure just how aligned this pointer is. */ |
d4c332ff | 1092 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
15bbde2b | 1093 | } |
1094 | ||
1095 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1096 | ||
1097 | int | |
35cb5232 | 1098 | max_reg_num (void) |
15bbde2b | 1099 | { |
1100 | return reg_rtx_no; | |
1101 | } | |
1102 | ||
1103 | /* Return 1 + the largest label number used so far in the current function. */ | |
1104 | ||
1105 | int | |
35cb5232 | 1106 | max_label_num (void) |
15bbde2b | 1107 | { |
15bbde2b | 1108 | return label_num; |
1109 | } | |
1110 | ||
1111 | /* Return first label number used in this function (if any were used). */ | |
1112 | ||
1113 | int | |
35cb5232 | 1114 | get_first_label_num (void) |
15bbde2b | 1115 | { |
1116 | return first_label_num; | |
1117 | } | |
4ee9c684 | 1118 | |
1119 | /* If the rtx for label was created during the expansion of a nested | |
1120 | function, then first_label_num won't include this label number. | |
1121 | Fix this now so that array indicies work later. */ | |
1122 | ||
1123 | void | |
1124 | maybe_set_first_label_num (rtx x) | |
1125 | { | |
1126 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1127 | first_label_num = CODE_LABEL_NUMBER (x); | |
1128 | } | |
15bbde2b | 1129 | \f |
1130 | /* Return a value representing some low-order bits of X, where the number | |
1131 | of low-order bits is given by MODE. Note that no conversion is done | |
d823ba47 | 1132 | between floating-point and fixed-point values, rather, the bit |
15bbde2b | 1133 | representation is returned. |
1134 | ||
1135 | This function handles the cases in common between gen_lowpart, below, | |
1136 | and two variants in cse.c and combine.c. These are the cases that can | |
1137 | be safely handled at all points in the compilation. | |
1138 | ||
1139 | If this is not a case we can handle, return 0. */ | |
1140 | ||
1141 | rtx | |
35cb5232 | 1142 | gen_lowpart_common (enum machine_mode mode, rtx x) |
15bbde2b | 1143 | { |
701e46d0 | 1144 | int msize = GET_MODE_SIZE (mode); |
791172c5 | 1145 | int xsize; |
701e46d0 | 1146 | int offset = 0; |
791172c5 | 1147 | enum machine_mode innermode; |
1148 | ||
1149 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1150 | so we have to make one up. Yuk. */ | |
1151 | innermode = GET_MODE (x); | |
6c799a83 | 1152 | if (GET_CODE (x) == CONST_INT |
1153 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) | |
791172c5 | 1154 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1155 | else if (innermode == VOIDmode) | |
1156 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0); | |
1157 | ||
1158 | xsize = GET_MODE_SIZE (innermode); | |
1159 | ||
611234b4 | 1160 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
15bbde2b | 1161 | |
791172c5 | 1162 | if (innermode == mode) |
15bbde2b | 1163 | return x; |
1164 | ||
1165 | /* MODE must occupy no more words than the mode of X. */ | |
791172c5 | 1166 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1167 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
15bbde2b | 1168 | return 0; |
1169 | ||
9abe1e73 | 1170 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
cee7491d | 1171 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
9abe1e73 | 1172 | return 0; |
1173 | ||
791172c5 | 1174 | offset = subreg_lowpart_offset (mode, innermode); |
15bbde2b | 1175 | |
1176 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
64115b39 | 1177 | && (GET_MODE_CLASS (mode) == MODE_INT |
1178 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
15bbde2b | 1179 | { |
1180 | /* If we are getting the low-order part of something that has been | |
1181 | sign- or zero-extended, we can either just use the object being | |
1182 | extended or make a narrower extension. If we want an even smaller | |
1183 | piece than the size of the object being extended, call ourselves | |
1184 | recursively. | |
1185 | ||
1186 | This case is used mostly by combine and cse. */ | |
1187 | ||
1188 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1189 | return XEXP (x, 0); | |
791172c5 | 1190 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
15bbde2b | 1191 | return gen_lowpart_common (mode, XEXP (x, 0)); |
791172c5 | 1192 | else if (msize < xsize) |
3ad7bb1c | 1193 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
15bbde2b | 1194 | } |
8ad4c111 | 1195 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
791172c5 | 1196 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
1197 | || GET_CODE (x) == CONST_DOUBLE || GET_CODE (x) == CONST_INT) | |
1198 | return simplify_gen_subreg (mode, x, innermode, offset); | |
4a307dd5 | 1199 | |
15bbde2b | 1200 | /* Otherwise, we can't do this. */ |
1201 | return 0; | |
1202 | } | |
1203 | \f | |
d56d0ca2 | 1204 | rtx |
35cb5232 | 1205 | gen_highpart (enum machine_mode mode, rtx x) |
d56d0ca2 | 1206 | { |
701e46d0 | 1207 | unsigned int msize = GET_MODE_SIZE (mode); |
81802af6 | 1208 | rtx result; |
701e46d0 | 1209 | |
d56d0ca2 | 1210 | /* This case loses if X is a subreg. To catch bugs early, |
1211 | complain if an invalid MODE is used even in other cases. */ | |
611234b4 | 1212 | gcc_assert (msize <= UNITS_PER_WORD |
1213 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
701e46d0 | 1214 | |
81802af6 | 1215 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1216 | subreg_highpart_offset (mode, GET_MODE (x))); | |
611234b4 | 1217 | gcc_assert (result); |
1218 | ||
a8c36ab2 | 1219 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1220 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1221 | emitting code if necessary to do so. */ | |
611234b4 | 1222 | if (MEM_P (result)) |
1223 | { | |
1224 | result = validize_mem (result); | |
1225 | gcc_assert (result); | |
1226 | } | |
1227 | ||
81802af6 | 1228 | return result; |
1229 | } | |
704fcf2b | 1230 | |
29d56731 | 1231 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
704fcf2b | 1232 | be VOIDmode constant. */ |
1233 | rtx | |
35cb5232 | 1234 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
704fcf2b | 1235 | { |
1236 | if (GET_MODE (exp) != VOIDmode) | |
1237 | { | |
611234b4 | 1238 | gcc_assert (GET_MODE (exp) == innermode); |
704fcf2b | 1239 | return gen_highpart (outermode, exp); |
1240 | } | |
1241 | return simplify_gen_subreg (outermode, exp, innermode, | |
1242 | subreg_highpart_offset (outermode, innermode)); | |
1243 | } | |
d4c5e26d | 1244 | |
81802af6 | 1245 | /* Return offset in bytes to get OUTERMODE low part |
1246 | of the value in mode INNERMODE stored in memory in target format. */ | |
10ef59ac | 1247 | |
81802af6 | 1248 | unsigned int |
35cb5232 | 1249 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
81802af6 | 1250 | { |
1251 | unsigned int offset = 0; | |
1252 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
10ef59ac | 1253 | |
81802af6 | 1254 | if (difference > 0) |
d56d0ca2 | 1255 | { |
81802af6 | 1256 | if (WORDS_BIG_ENDIAN) |
1257 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1258 | if (BYTES_BIG_ENDIAN) | |
1259 | offset += difference % UNITS_PER_WORD; | |
d56d0ca2 | 1260 | } |
701e46d0 | 1261 | |
81802af6 | 1262 | return offset; |
d56d0ca2 | 1263 | } |
64ab453f | 1264 | |
81802af6 | 1265 | /* Return offset in bytes to get OUTERMODE high part |
1266 | of the value in mode INNERMODE stored in memory in target format. */ | |
1267 | unsigned int | |
35cb5232 | 1268 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
64ab453f | 1269 | { |
1270 | unsigned int offset = 0; | |
1271 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1272 | ||
611234b4 | 1273 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
81802af6 | 1274 | |
64ab453f | 1275 | if (difference > 0) |
1276 | { | |
81802af6 | 1277 | if (! WORDS_BIG_ENDIAN) |
64ab453f | 1278 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
81802af6 | 1279 | if (! BYTES_BIG_ENDIAN) |
64ab453f | 1280 | offset += difference % UNITS_PER_WORD; |
1281 | } | |
1282 | ||
81802af6 | 1283 | return offset; |
64ab453f | 1284 | } |
d56d0ca2 | 1285 | |
15bbde2b | 1286 | /* Return 1 iff X, assumed to be a SUBREG, |
1287 | refers to the least significant part of its containing reg. | |
1288 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1289 | ||
1290 | int | |
b7bf20db | 1291 | subreg_lowpart_p (const_rtx x) |
15bbde2b | 1292 | { |
1293 | if (GET_CODE (x) != SUBREG) | |
1294 | return 1; | |
7e14c1bf | 1295 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1296 | return 0; | |
15bbde2b | 1297 | |
81802af6 | 1298 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1299 | == SUBREG_BYTE (x)); | |
15bbde2b | 1300 | } |
1301 | \f | |
701e46d0 | 1302 | /* Return subword OFFSET of operand OP. |
1303 | The word number, OFFSET, is interpreted as the word number starting | |
1304 | at the low-order address. OFFSET 0 is the low-order word if not | |
1305 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1306 | ||
1307 | If we cannot extract the required word, we return zero. Otherwise, | |
1308 | an rtx corresponding to the requested word will be returned. | |
1309 | ||
1310 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1311 | reload has completed, a valid address will always be returned. After | |
1312 | reload, if a valid address cannot be returned, we return zero. | |
1313 | ||
1314 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1315 | it is the responsibility of the caller. | |
1316 | ||
1317 | MODE is the mode of OP in case it is a CONST_INT. | |
1318 | ||
1319 | ??? This is still rather broken for some cases. The problem for the | |
1320 | moment is that all callers of this thing provide no 'goal mode' to | |
1321 | tell us to work with. This exists because all callers were written | |
84e81e84 | 1322 | in a word based SUBREG world. |
1323 | Now use of this function can be deprecated by simplify_subreg in most | |
1324 | cases. | |
1325 | */ | |
701e46d0 | 1326 | |
1327 | rtx | |
35cb5232 | 1328 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
701e46d0 | 1329 | { |
1330 | if (mode == VOIDmode) | |
1331 | mode = GET_MODE (op); | |
1332 | ||
611234b4 | 1333 | gcc_assert (mode != VOIDmode); |
701e46d0 | 1334 | |
6312a35e | 1335 | /* If OP is narrower than a word, fail. */ |
701e46d0 | 1336 | if (mode != BLKmode |
1337 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1338 | return 0; | |
1339 | ||
6312a35e | 1340 | /* If we want a word outside OP, return zero. */ |
701e46d0 | 1341 | if (mode != BLKmode |
1342 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1343 | return const0_rtx; | |
1344 | ||
701e46d0 | 1345 | /* Form a new MEM at the requested address. */ |
e16ceb8e | 1346 | if (MEM_P (op)) |
701e46d0 | 1347 | { |
e4e86ec5 | 1348 | rtx new = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
701e46d0 | 1349 | |
e4e86ec5 | 1350 | if (! validate_address) |
1351 | return new; | |
1352 | ||
1353 | else if (reload_completed) | |
701e46d0 | 1354 | { |
e4e86ec5 | 1355 | if (! strict_memory_address_p (word_mode, XEXP (new, 0))) |
1356 | return 0; | |
701e46d0 | 1357 | } |
e4e86ec5 | 1358 | else |
1359 | return replace_equiv_address (new, XEXP (new, 0)); | |
701e46d0 | 1360 | } |
1361 | ||
84e81e84 | 1362 | /* Rest can be handled by simplify_subreg. */ |
1363 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
701e46d0 | 1364 | } |
1365 | ||
89f18f73 | 1366 | /* Similar to `operand_subword', but never return 0. If we can't |
1367 | extract the required subword, put OP into a register and try again. | |
1368 | The second attempt must succeed. We always validate the address in | |
1369 | this case. | |
15bbde2b | 1370 | |
1371 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1372 | ||
1373 | rtx | |
35cb5232 | 1374 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
15bbde2b | 1375 | { |
701e46d0 | 1376 | rtx result = operand_subword (op, offset, 1, mode); |
15bbde2b | 1377 | |
1378 | if (result) | |
1379 | return result; | |
1380 | ||
1381 | if (mode != BLKmode && mode != VOIDmode) | |
ac825d29 | 1382 | { |
1383 | /* If this is a register which can not be accessed by words, copy it | |
1384 | to a pseudo register. */ | |
8ad4c111 | 1385 | if (REG_P (op)) |
ac825d29 | 1386 | op = copy_to_reg (op); |
1387 | else | |
1388 | op = force_reg (mode, op); | |
1389 | } | |
15bbde2b | 1390 | |
701e46d0 | 1391 | result = operand_subword (op, offset, 1, mode); |
611234b4 | 1392 | gcc_assert (result); |
15bbde2b | 1393 | |
1394 | return result; | |
1395 | } | |
1396 | \f | |
b10dbbca | 1397 | /* Within a MEM_EXPR, we care about either (1) a component ref of a decl, |
1398 | or (2) a component ref of something variable. Represent the later with | |
1399 | a NULL expression. */ | |
1400 | ||
1401 | static tree | |
35cb5232 | 1402 | component_ref_for_mem_expr (tree ref) |
b10dbbca | 1403 | { |
1404 | tree inner = TREE_OPERAND (ref, 0); | |
1405 | ||
1406 | if (TREE_CODE (inner) == COMPONENT_REF) | |
1407 | inner = component_ref_for_mem_expr (inner); | |
3c00f11c | 1408 | else |
1409 | { | |
3c00f11c | 1410 | /* Now remove any conversions: they don't change what the underlying |
55f9d7dc | 1411 | object is. Likewise for SAVE_EXPR. */ |
3c00f11c | 1412 | while (TREE_CODE (inner) == NOP_EXPR || TREE_CODE (inner) == CONVERT_EXPR |
1413 | || TREE_CODE (inner) == NON_LVALUE_EXPR | |
1414 | || TREE_CODE (inner) == VIEW_CONVERT_EXPR | |
55f9d7dc | 1415 | || TREE_CODE (inner) == SAVE_EXPR) |
1416 | inner = TREE_OPERAND (inner, 0); | |
3c00f11c | 1417 | |
1418 | if (! DECL_P (inner)) | |
1419 | inner = NULL_TREE; | |
1420 | } | |
b10dbbca | 1421 | |
1422 | if (inner == TREE_OPERAND (ref, 0)) | |
1423 | return ref; | |
1424 | else | |
b55f9493 | 1425 | return build3 (COMPONENT_REF, TREE_TYPE (ref), inner, |
1426 | TREE_OPERAND (ref, 1), NULL_TREE); | |
b10dbbca | 1427 | } |
c6259b83 | 1428 | |
b3ff8d90 | 1429 | /* Returns 1 if both MEM_EXPR can be considered equal |
1430 | and 0 otherwise. */ | |
1431 | ||
1432 | int | |
52d07779 | 1433 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
b3ff8d90 | 1434 | { |
1435 | if (expr1 == expr2) | |
1436 | return 1; | |
1437 | ||
1438 | if (! expr1 || ! expr2) | |
1439 | return 0; | |
1440 | ||
1441 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1442 | return 0; | |
1443 | ||
1444 | if (TREE_CODE (expr1) == COMPONENT_REF) | |
1445 | return | |
1446 | mem_expr_equal_p (TREE_OPERAND (expr1, 0), | |
1447 | TREE_OPERAND (expr2, 0)) | |
1448 | && mem_expr_equal_p (TREE_OPERAND (expr1, 1), /* field decl */ | |
1449 | TREE_OPERAND (expr2, 1)); | |
1450 | ||
2a448a75 | 1451 | if (INDIRECT_REF_P (expr1)) |
b3ff8d90 | 1452 | return mem_expr_equal_p (TREE_OPERAND (expr1, 0), |
1453 | TREE_OPERAND (expr2, 0)); | |
b3ff8d90 | 1454 | |
611234b4 | 1455 | /* ARRAY_REFs, ARRAY_RANGE_REFs and BIT_FIELD_REFs should already |
b3ff8d90 | 1456 | have been resolved here. */ |
611234b4 | 1457 | gcc_assert (DECL_P (expr1)); |
1458 | ||
1459 | /* Decls with different pointers can't be equal. */ | |
1460 | return 0; | |
b3ff8d90 | 1461 | } |
1462 | ||
c6259b83 | 1463 | /* Given REF, a MEM, and T, either the type of X or the expression |
1464 | corresponding to REF, set the memory attributes. OBJECTP is nonzero | |
6f717f77 | 1465 | if we are making a new object of this type. BITPOS is nonzero if |
1466 | there is an offset outstanding on T that will be applied later. */ | |
c6259b83 | 1467 | |
1468 | void | |
35cb5232 | 1469 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1470 | HOST_WIDE_INT bitpos) | |
c6259b83 | 1471 | { |
32c2fdea | 1472 | alias_set_type alias = MEM_ALIAS_SET (ref); |
b10dbbca | 1473 | tree expr = MEM_EXPR (ref); |
2a631e19 | 1474 | rtx offset = MEM_OFFSET (ref); |
1475 | rtx size = MEM_SIZE (ref); | |
1476 | unsigned int align = MEM_ALIGN (ref); | |
6f717f77 | 1477 | HOST_WIDE_INT apply_bitpos = 0; |
c6259b83 | 1478 | tree type; |
1479 | ||
1480 | /* It can happen that type_for_mode was given a mode for which there | |
1481 | is no language-level type. In which case it returns NULL, which | |
1482 | we can see here. */ | |
1483 | if (t == NULL_TREE) | |
1484 | return; | |
1485 | ||
1486 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
4ccffa39 | 1487 | if (type == error_mark_node) |
1488 | return; | |
c6259b83 | 1489 | |
c6259b83 | 1490 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1491 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1492 | info. Callers should not set DECL_RTL until after the call to | |
1493 | set_mem_attributes. */ | |
611234b4 | 1494 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
c6259b83 | 1495 | |
96216d37 | 1496 | /* Get the alias set from the expression or type (perhaps using a |
2a631e19 | 1497 | front-end routine) and use it. */ |
1498 | alias = get_alias_set (t); | |
c6259b83 | 1499 | |
fbc6244b | 1500 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
cfefc966 | 1501 | MEM_IN_STRUCT_P (ref) |
1502 | = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE; | |
8d350e69 | 1503 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
c6259b83 | 1504 | |
2a631e19 | 1505 | /* If we are making an object of this type, or if this is a DECL, we know |
1506 | that it is a scalar if the type is not an aggregate. */ | |
cfefc966 | 1507 | if ((objectp || DECL_P (t)) |
1508 | && ! AGGREGATE_TYPE_P (type) | |
1509 | && TREE_CODE (type) != COMPLEX_TYPE) | |
c6259b83 | 1510 | MEM_SCALAR_P (ref) = 1; |
1511 | ||
a9d9ab08 | 1512 | /* We can set the alignment from the type if we are making an object, |
1513 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
b056d812 | 1514 | if (objectp || TREE_CODE (t) == INDIRECT_REF |
1515 | || TREE_CODE (t) == ALIGN_INDIRECT_REF | |
1516 | || TYPE_ALIGN_OK (type)) | |
a9d9ab08 | 1517 | align = MAX (align, TYPE_ALIGN (type)); |
b056d812 | 1518 | else |
1519 | if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF) | |
1520 | { | |
1521 | if (integer_zerop (TREE_OPERAND (t, 1))) | |
1522 | /* We don't know anything about the alignment. */ | |
1523 | align = BITS_PER_UNIT; | |
1524 | else | |
1525 | align = tree_low_cst (TREE_OPERAND (t, 1), 1); | |
1526 | } | |
ecfe4ca9 | 1527 | |
96216d37 | 1528 | /* If the size is known, we can set that. */ |
1529 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
2a631e19 | 1530 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
96216d37 | 1531 | |
579bccf9 | 1532 | /* If T is not a type, we may be able to deduce some more information about |
1533 | the expression. */ | |
1534 | if (! TYPE_P (t)) | |
2a631e19 | 1535 | { |
ae2dd339 | 1536 | tree base; |
b04fab2a | 1537 | |
2a631e19 | 1538 | if (TREE_THIS_VOLATILE (t)) |
1539 | MEM_VOLATILE_P (ref) = 1; | |
c6259b83 | 1540 | |
3c00f11c | 1541 | /* Now remove any conversions: they don't change what the underlying |
1542 | object is. Likewise for SAVE_EXPR. */ | |
2a631e19 | 1543 | while (TREE_CODE (t) == NOP_EXPR || TREE_CODE (t) == CONVERT_EXPR |
3c00f11c | 1544 | || TREE_CODE (t) == NON_LVALUE_EXPR |
1545 | || TREE_CODE (t) == VIEW_CONVERT_EXPR | |
1546 | || TREE_CODE (t) == SAVE_EXPR) | |
2a631e19 | 1547 | t = TREE_OPERAND (t, 0); |
1548 | ||
ae2dd339 | 1549 | /* We may look through structure-like accesses for the purposes of |
1550 | examining TREE_THIS_NOTRAP, but not array-like accesses. */ | |
1551 | base = t; | |
1552 | while (TREE_CODE (base) == COMPONENT_REF | |
1553 | || TREE_CODE (base) == REALPART_EXPR | |
1554 | || TREE_CODE (base) == IMAGPART_EXPR | |
1555 | || TREE_CODE (base) == BIT_FIELD_REF) | |
1556 | base = TREE_OPERAND (base, 0); | |
1557 | ||
1558 | if (DECL_P (base)) | |
1559 | { | |
1560 | if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS)) | |
1561 | MEM_NOTRAP_P (ref) = !DECL_WEAK (base); | |
1562 | else | |
1563 | MEM_NOTRAP_P (ref) = 1; | |
1564 | } | |
1565 | else | |
1566 | MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base); | |
1567 | ||
1568 | base = get_base_address (base); | |
1569 | if (base && DECL_P (base) | |
1570 | && TREE_READONLY (base) | |
1571 | && (TREE_STATIC (base) || DECL_EXTERNAL (base))) | |
1572 | { | |
1573 | tree base_type = TREE_TYPE (base); | |
1574 | gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type)) | |
1575 | || DECL_ARTIFICIAL (base)); | |
1576 | MEM_READONLY_P (ref) = 1; | |
1577 | } | |
1578 | ||
2b02580f | 1579 | /* If this expression uses it's parent's alias set, mark it such |
1580 | that we won't change it. */ | |
1581 | if (component_uses_parent_alias_set (t)) | |
5cc193e7 | 1582 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1583 | ||
2a631e19 | 1584 | /* If this is a decl, set the attributes of the MEM from it. */ |
1585 | if (DECL_P (t)) | |
1586 | { | |
b10dbbca | 1587 | expr = t; |
1588 | offset = const0_rtx; | |
6f717f77 | 1589 | apply_bitpos = bitpos; |
2a631e19 | 1590 | size = (DECL_SIZE_UNIT (t) |
1591 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1592 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
d4c5e26d | 1593 | align = DECL_ALIGN (t); |
2a631e19 | 1594 | } |
1595 | ||
ecfe4ca9 | 1596 | /* If this is a constant, we know the alignment. */ |
ce45a448 | 1597 | else if (CONSTANT_CLASS_P (t)) |
42f6f447 | 1598 | { |
1599 | align = TYPE_ALIGN (type); | |
1600 | #ifdef CONSTANT_ALIGNMENT | |
1601 | align = CONSTANT_ALIGNMENT (t, align); | |
1602 | #endif | |
1603 | } | |
b10dbbca | 1604 | |
1605 | /* If this is a field reference and not a bit-field, record it. */ | |
1606 | /* ??? There is some information that can be gleened from bit-fields, | |
1607 | such as the word offset in the structure that might be modified. | |
1608 | But skip it for now. */ | |
1609 | else if (TREE_CODE (t) == COMPONENT_REF | |
1610 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1611 | { | |
1612 | expr = component_ref_for_mem_expr (t); | |
1613 | offset = const0_rtx; | |
6f717f77 | 1614 | apply_bitpos = bitpos; |
b10dbbca | 1615 | /* ??? Any reason the field size would be different than |
1616 | the size we got from the type? */ | |
1617 | } | |
1618 | ||
1619 | /* If this is an array reference, look for an outer field reference. */ | |
1620 | else if (TREE_CODE (t) == ARRAY_REF) | |
1621 | { | |
1622 | tree off_tree = size_zero_node; | |
6b039979 | 1623 | /* We can't modify t, because we use it at the end of the |
1624 | function. */ | |
1625 | tree t2 = t; | |
b10dbbca | 1626 | |
1627 | do | |
1628 | { | |
6b039979 | 1629 | tree index = TREE_OPERAND (t2, 1); |
6374121b | 1630 | tree low_bound = array_ref_low_bound (t2); |
1631 | tree unit_size = array_ref_element_size (t2); | |
97f8ce30 | 1632 | |
1633 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1634 | First subtract the lower bound, if any, in the type of the | |
6374121b | 1635 | index, then convert to sizetype and multiply by the size of |
1636 | the array element. */ | |
1637 | if (! integer_zerop (low_bound)) | |
faa43f85 | 1638 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1639 | index, low_bound); | |
97f8ce30 | 1640 | |
6374121b | 1641 | off_tree = size_binop (PLUS_EXPR, |
535664e3 | 1642 | size_binop (MULT_EXPR, |
1643 | fold_convert (sizetype, | |
1644 | index), | |
6374121b | 1645 | unit_size), |
1646 | off_tree); | |
6b039979 | 1647 | t2 = TREE_OPERAND (t2, 0); |
b10dbbca | 1648 | } |
6b039979 | 1649 | while (TREE_CODE (t2) == ARRAY_REF); |
b10dbbca | 1650 | |
6b039979 | 1651 | if (DECL_P (t2)) |
2d8fe5d0 | 1652 | { |
6b039979 | 1653 | expr = t2; |
0318dc09 | 1654 | offset = NULL; |
2d8fe5d0 | 1655 | if (host_integerp (off_tree, 1)) |
0318dc09 | 1656 | { |
1657 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1658 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
6b039979 | 1659 | align = DECL_ALIGN (t2); |
3473aefe | 1660 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
0318dc09 | 1661 | align = aoff; |
1662 | offset = GEN_INT (ioff); | |
6f717f77 | 1663 | apply_bitpos = bitpos; |
0318dc09 | 1664 | } |
2d8fe5d0 | 1665 | } |
6b039979 | 1666 | else if (TREE_CODE (t2) == COMPONENT_REF) |
b10dbbca | 1667 | { |
6b039979 | 1668 | expr = component_ref_for_mem_expr (t2); |
b10dbbca | 1669 | if (host_integerp (off_tree, 1)) |
6f717f77 | 1670 | { |
1671 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1672 | apply_bitpos = bitpos; | |
1673 | } | |
b10dbbca | 1674 | /* ??? Any reason the field size would be different than |
1675 | the size we got from the type? */ | |
1676 | } | |
2d8fe5d0 | 1677 | else if (flag_argument_noalias > 1 |
2a448a75 | 1678 | && (INDIRECT_REF_P (t2)) |
6b039979 | 1679 | && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL) |
2d8fe5d0 | 1680 | { |
6b039979 | 1681 | expr = t2; |
2d8fe5d0 | 1682 | offset = NULL; |
1683 | } | |
1684 | } | |
1685 | ||
1686 | /* If this is a Fortran indirect argument reference, record the | |
1687 | parameter decl. */ | |
1688 | else if (flag_argument_noalias > 1 | |
2a448a75 | 1689 | && (INDIRECT_REF_P (t)) |
2d8fe5d0 | 1690 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) |
1691 | { | |
1692 | expr = t; | |
1693 | offset = NULL; | |
b10dbbca | 1694 | } |
2a631e19 | 1695 | } |
1696 | ||
e2e205b3 | 1697 | /* If we modified OFFSET based on T, then subtract the outstanding |
595f1461 | 1698 | bit position offset. Similarly, increase the size of the accessed |
1699 | object to contain the negative offset. */ | |
6f717f77 | 1700 | if (apply_bitpos) |
595f1461 | 1701 | { |
1702 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
1703 | if (size) | |
1704 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
1705 | } | |
6f717f77 | 1706 | |
b056d812 | 1707 | if (TREE_CODE (t) == ALIGN_INDIRECT_REF) |
1708 | { | |
1709 | /* Force EXPR and OFFSE to NULL, since we don't know exactly what | |
1710 | we're overlapping. */ | |
1711 | offset = NULL; | |
1712 | expr = NULL; | |
1713 | } | |
1714 | ||
2a631e19 | 1715 | /* Now set the attributes we computed above. */ |
5cc193e7 | 1716 | MEM_ATTRS (ref) |
b10dbbca | 1717 | = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref)); |
2a631e19 | 1718 | |
1719 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
1720 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
96216d37 | 1721 | return; |
1722 | ||
2a631e19 | 1723 | /* If it is a reference into an aggregate, this is part of an aggregate. |
1724 | Otherwise we don't know. */ | |
c6259b83 | 1725 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
1726 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
1727 | || TREE_CODE (t) == BIT_FIELD_REF) | |
1728 | MEM_IN_STRUCT_P (ref) = 1; | |
1729 | } | |
1730 | ||
6f717f77 | 1731 | void |
35cb5232 | 1732 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f717f77 | 1733 | { |
1734 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
1735 | } | |
1736 | ||
ca74b940 | 1737 | /* Set the decl for MEM to DECL. */ |
1738 | ||
1739 | void | |
35cb5232 | 1740 | set_mem_attrs_from_reg (rtx mem, rtx reg) |
ca74b940 | 1741 | { |
1742 | MEM_ATTRS (mem) | |
1743 | = get_mem_attrs (MEM_ALIAS_SET (mem), REG_EXPR (reg), | |
1744 | GEN_INT (REG_OFFSET (reg)), | |
1745 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); | |
1746 | } | |
1747 | ||
c6259b83 | 1748 | /* Set the alias set of MEM to SET. */ |
1749 | ||
1750 | void | |
32c2fdea | 1751 | set_mem_alias_set (rtx mem, alias_set_type set) |
c6259b83 | 1752 | { |
d4c5e26d | 1753 | #ifdef ENABLE_CHECKING |
c6259b83 | 1754 | /* If the new and old alias sets don't conflict, something is wrong. */ |
611234b4 | 1755 | gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
c6259b83 | 1756 | #endif |
1757 | ||
b10dbbca | 1758 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
5cc193e7 | 1759 | MEM_SIZE (mem), MEM_ALIGN (mem), |
1760 | GET_MODE (mem)); | |
c6259b83 | 1761 | } |
96216d37 | 1762 | |
1c4512da | 1763 | /* Set the alignment of MEM to ALIGN bits. */ |
96216d37 | 1764 | |
1765 | void | |
35cb5232 | 1766 | set_mem_align (rtx mem, unsigned int align) |
96216d37 | 1767 | { |
b10dbbca | 1768 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
5cc193e7 | 1769 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
1770 | GET_MODE (mem)); | |
96216d37 | 1771 | } |
278fe152 | 1772 | |
b10dbbca | 1773 | /* Set the expr for MEM to EXPR. */ |
278fe152 | 1774 | |
1775 | void | |
35cb5232 | 1776 | set_mem_expr (rtx mem, tree expr) |
278fe152 | 1777 | { |
1778 | MEM_ATTRS (mem) | |
b10dbbca | 1779 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
278fe152 | 1780 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); |
1781 | } | |
b10dbbca | 1782 | |
1783 | /* Set the offset of MEM to OFFSET. */ | |
1784 | ||
1785 | void | |
35cb5232 | 1786 | set_mem_offset (rtx mem, rtx offset) |
b10dbbca | 1787 | { |
1788 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1789 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
1790 | GET_MODE (mem)); | |
f0500469 | 1791 | } |
1792 | ||
1793 | /* Set the size of MEM to SIZE. */ | |
1794 | ||
1795 | void | |
35cb5232 | 1796 | set_mem_size (rtx mem, rtx size) |
f0500469 | 1797 | { |
1798 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1799 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
1800 | GET_MODE (mem)); | |
b10dbbca | 1801 | } |
c6259b83 | 1802 | \f |
96216d37 | 1803 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
1804 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
1805 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
1806 | returned memory location is required to be valid. The memory | |
1807 | attributes are not changed. */ | |
15bbde2b | 1808 | |
96216d37 | 1809 | static rtx |
35cb5232 | 1810 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
15bbde2b | 1811 | { |
1812 | rtx new; | |
1813 | ||
611234b4 | 1814 | gcc_assert (MEM_P (memref)); |
15bbde2b | 1815 | if (mode == VOIDmode) |
1816 | mode = GET_MODE (memref); | |
1817 | if (addr == 0) | |
1818 | addr = XEXP (memref, 0); | |
3988ef8b | 1819 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
1820 | && (!validate || memory_address_p (mode, addr))) | |
1821 | return memref; | |
15bbde2b | 1822 | |
e4e86ec5 | 1823 | if (validate) |
15bbde2b | 1824 | { |
e4e86ec5 | 1825 | if (reload_in_progress || reload_completed) |
611234b4 | 1826 | gcc_assert (memory_address_p (mode, addr)); |
e4e86ec5 | 1827 | else |
1828 | addr = memory_address (mode, addr); | |
15bbde2b | 1829 | } |
d823ba47 | 1830 | |
e8976cd7 | 1831 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1832 | return memref; | |
1833 | ||
3ad7bb1c | 1834 | new = gen_rtx_MEM (mode, addr); |
6a0934dd | 1835 | MEM_COPY_ATTRIBUTES (new, memref); |
15bbde2b | 1836 | return new; |
1837 | } | |
537ffcfc | 1838 | |
96216d37 | 1839 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
1840 | way we are changing MEMREF, so we only preserve the alias set. */ | |
e513d163 | 1841 | |
1842 | rtx | |
35cb5232 | 1843 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
e513d163 | 1844 | { |
0ab96142 | 1845 | rtx new = change_address_1 (memref, mode, addr, 1), size; |
96216d37 | 1846 | enum machine_mode mmode = GET_MODE (new); |
0ab96142 | 1847 | unsigned int align; |
1848 | ||
1849 | size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)); | |
1850 | align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode); | |
6cc60c4d | 1851 | |
d28edf0d | 1852 | /* If there are no changes, just return the original memory reference. */ |
1853 | if (new == memref) | |
0ab96142 | 1854 | { |
1855 | if (MEM_ATTRS (memref) == 0 | |
1856 | || (MEM_EXPR (memref) == NULL | |
1857 | && MEM_OFFSET (memref) == NULL | |
1858 | && MEM_SIZE (memref) == size | |
1859 | && MEM_ALIGN (memref) == align)) | |
1860 | return new; | |
1861 | ||
6c231ace | 1862 | new = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
0ab96142 | 1863 | MEM_COPY_ATTRIBUTES (new, memref); |
1864 | } | |
d28edf0d | 1865 | |
96216d37 | 1866 | MEM_ATTRS (new) |
0ab96142 | 1867 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, mmode); |
fb257ae6 | 1868 | |
96216d37 | 1869 | return new; |
e513d163 | 1870 | } |
537ffcfc | 1871 | |
96216d37 | 1872 | /* Return a memory reference like MEMREF, but with its mode changed |
1873 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
bf42c62d | 1874 | nonzero, the memory address is forced to be valid. |
1875 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
1876 | and caller is responsible for adjusting MEMREF base register. */ | |
e4e86ec5 | 1877 | |
1878 | rtx | |
35cb5232 | 1879 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
1880 | int validate, int adjust) | |
e4e86ec5 | 1881 | { |
fb257ae6 | 1882 | rtx addr = XEXP (memref, 0); |
96216d37 | 1883 | rtx new; |
1884 | rtx memoffset = MEM_OFFSET (memref); | |
5cc193e7 | 1885 | rtx size = 0; |
96216d37 | 1886 | unsigned int memalign = MEM_ALIGN (memref); |
fb257ae6 | 1887 | |
d28edf0d | 1888 | /* If there are no changes, just return the original memory reference. */ |
1889 | if (mode == GET_MODE (memref) && !offset | |
1890 | && (!validate || memory_address_p (mode, addr))) | |
1891 | return memref; | |
1892 | ||
e36c3d58 | 1893 | /* ??? Prefer to create garbage instead of creating shared rtl. |
6ef828f9 | 1894 | This may happen even if offset is nonzero -- consider |
e36c3d58 | 1895 | (plus (plus reg reg) const_int) -- so do this always. */ |
1896 | addr = copy_rtx (addr); | |
1897 | ||
cd358719 | 1898 | if (adjust) |
1899 | { | |
1900 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
1901 | object, we can merge it into the LO_SUM. */ | |
1902 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
1903 | && offset >= 0 | |
1904 | && (unsigned HOST_WIDE_INT) offset | |
1905 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
1906 | addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0), | |
1907 | plus_constant (XEXP (addr, 1), offset)); | |
1908 | else | |
1909 | addr = plus_constant (addr, offset); | |
1910 | } | |
fb257ae6 | 1911 | |
96216d37 | 1912 | new = change_address_1 (memref, mode, addr, validate); |
1913 | ||
1914 | /* Compute the new values of the memory attributes due to this adjustment. | |
1915 | We add the offsets and update the alignment. */ | |
1916 | if (memoffset) | |
1917 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
1918 | ||
b8098e5b | 1919 | /* Compute the new alignment by taking the MIN of the alignment and the |
1920 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
1921 | if zero. */ | |
1922 | if (offset != 0) | |
f4aee538 | 1923 | memalign |
1924 | = MIN (memalign, | |
1925 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
96216d37 | 1926 | |
5cc193e7 | 1927 | /* We can compute the size in a number of ways. */ |
2b96c5f6 | 1928 | if (GET_MODE (new) != BLKmode) |
1929 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new))); | |
5cc193e7 | 1930 | else if (MEM_SIZE (memref)) |
1931 | size = plus_constant (MEM_SIZE (memref), -offset); | |
1932 | ||
b10dbbca | 1933 | MEM_ATTRS (new) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
5cc193e7 | 1934 | memoffset, size, memalign, GET_MODE (new)); |
96216d37 | 1935 | |
1936 | /* At some point, we should validate that this offset is within the object, | |
1937 | if all the appropriate values are known. */ | |
1938 | return new; | |
e4e86ec5 | 1939 | } |
1940 | ||
bf42c62d | 1941 | /* Return a memory reference like MEMREF, but with its mode changed |
1942 | to MODE and its address changed to ADDR, which is assumed to be | |
1943 | MEMREF offseted by OFFSET bytes. If VALIDATE is | |
1944 | nonzero, the memory address is forced to be valid. */ | |
1945 | ||
1946 | rtx | |
35cb5232 | 1947 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
1948 | HOST_WIDE_INT offset, int validate) | |
bf42c62d | 1949 | { |
1950 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
1951 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
1952 | } | |
1953 | ||
2a631e19 | 1954 | /* Return a memory reference like MEMREF, but whose address is changed by |
1955 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
1956 | known to be in OFFSET (possibly 1). */ | |
fcdc122e | 1957 | |
1958 | rtx | |
35cb5232 | 1959 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
fcdc122e | 1960 | { |
fac6aae6 | 1961 | rtx new, addr = XEXP (memref, 0); |
1962 | ||
1963 | new = simplify_gen_binary (PLUS, Pmode, addr, offset); | |
1964 | ||
d4c5e26d | 1965 | /* At this point we don't know _why_ the address is invalid. It |
917bbcab | 1966 | could have secondary memory references, multiplies or anything. |
fac6aae6 | 1967 | |
1968 | However, if we did go and rearrange things, we can wind up not | |
1969 | being able to recognize the magic around pic_offset_table_rtx. | |
1970 | This stuff is fragile, and is yet another example of why it is | |
1971 | bad to expose PIC machinery too early. */ | |
1972 | if (! memory_address_p (GET_MODE (memref), new) | |
1973 | && GET_CODE (addr) == PLUS | |
1974 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
1975 | { | |
1976 | addr = force_reg (GET_MODE (addr), addr); | |
1977 | new = simplify_gen_binary (PLUS, Pmode, addr, offset); | |
1978 | } | |
1979 | ||
430816ab | 1980 | update_temp_slot_address (XEXP (memref, 0), new); |
fac6aae6 | 1981 | new = change_address_1 (memref, VOIDmode, new, 1); |
fcdc122e | 1982 | |
d28edf0d | 1983 | /* If there are no changes, just return the original memory reference. */ |
1984 | if (new == memref) | |
1985 | return new; | |
1986 | ||
fcdc122e | 1987 | /* Update the alignment to reflect the offset. Reset the offset, which |
1988 | we don't know. */ | |
80fabb90 | 1989 | MEM_ATTRS (new) |
1990 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, | |
84130727 | 1991 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
80fabb90 | 1992 | GET_MODE (new)); |
fcdc122e | 1993 | return new; |
1994 | } | |
d4c5e26d | 1995 | |
537ffcfc | 1996 | /* Return a memory reference like MEMREF, but with its address changed to |
1997 | ADDR. The caller is asserting that the actual piece of memory pointed | |
1998 | to is the same, just the form of the address is being changed, such as | |
1999 | by putting something into a register. */ | |
2000 | ||
2001 | rtx | |
35cb5232 | 2002 | replace_equiv_address (rtx memref, rtx addr) |
537ffcfc | 2003 | { |
96216d37 | 2004 | /* change_address_1 copies the memory attribute structure without change |
2005 | and that's exactly what we want here. */ | |
ecfe4ca9 | 2006 | update_temp_slot_address (XEXP (memref, 0), addr); |
96216d37 | 2007 | return change_address_1 (memref, VOIDmode, addr, 1); |
537ffcfc | 2008 | } |
96216d37 | 2009 | |
e4e86ec5 | 2010 | /* Likewise, but the reference is not required to be valid. */ |
2011 | ||
2012 | rtx | |
35cb5232 | 2013 | replace_equiv_address_nv (rtx memref, rtx addr) |
e4e86ec5 | 2014 | { |
e4e86ec5 | 2015 | return change_address_1 (memref, VOIDmode, addr, 0); |
2016 | } | |
8259ab07 | 2017 | |
2018 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2019 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2020 | cannot issue QImode memory operations and have to use SImode memory | |
2021 | operations plus masking logic. */ | |
2022 | ||
2023 | rtx | |
35cb5232 | 2024 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
8259ab07 | 2025 | { |
2026 | rtx new = adjust_address_1 (memref, mode, offset, 1, 1); | |
2027 | tree expr = MEM_EXPR (new); | |
2028 | rtx memoffset = MEM_OFFSET (new); | |
2029 | unsigned int size = GET_MODE_SIZE (mode); | |
2030 | ||
d28edf0d | 2031 | /* If there are no changes, just return the original memory reference. */ |
2032 | if (new == memref) | |
2033 | return new; | |
2034 | ||
8259ab07 | 2035 | /* If we don't know what offset we were at within the expression, then |
2036 | we can't know if we've overstepped the bounds. */ | |
22ee087b | 2037 | if (! memoffset) |
8259ab07 | 2038 | expr = NULL_TREE; |
2039 | ||
2040 | while (expr) | |
2041 | { | |
2042 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2043 | { | |
2044 | tree field = TREE_OPERAND (expr, 1); | |
6374121b | 2045 | tree offset = component_ref_field_offset (expr); |
8259ab07 | 2046 | |
2047 | if (! DECL_SIZE_UNIT (field)) | |
2048 | { | |
2049 | expr = NULL_TREE; | |
2050 | break; | |
2051 | } | |
2052 | ||
2053 | /* Is the field at least as large as the access? If so, ok, | |
2054 | otherwise strip back to the containing structure. */ | |
8359cfb4 | 2055 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2056 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
8259ab07 | 2057 | && INTVAL (memoffset) >= 0) |
2058 | break; | |
2059 | ||
6374121b | 2060 | if (! host_integerp (offset, 1)) |
8259ab07 | 2061 | { |
2062 | expr = NULL_TREE; | |
2063 | break; | |
2064 | } | |
2065 | ||
2066 | expr = TREE_OPERAND (expr, 0); | |
6374121b | 2067 | memoffset |
2068 | = (GEN_INT (INTVAL (memoffset) | |
2069 | + tree_low_cst (offset, 1) | |
2070 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2071 | / BITS_PER_UNIT))); | |
8259ab07 | 2072 | } |
2073 | /* Similarly for the decl. */ | |
2074 | else if (DECL_P (expr) | |
2075 | && DECL_SIZE_UNIT (expr) | |
40c4e66e | 2076 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
8259ab07 | 2077 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2078 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2079 | break; | |
2080 | else | |
2081 | { | |
2082 | /* The widened memory access overflows the expression, which means | |
2083 | that it could alias another expression. Zap it. */ | |
2084 | expr = NULL_TREE; | |
2085 | break; | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | if (! expr) | |
2090 | memoffset = NULL_RTX; | |
2091 | ||
2092 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2093 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2094 | ||
2095 | MEM_ATTRS (new) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), | |
2096 | MEM_ALIGN (new), mode); | |
2097 | ||
2098 | return new; | |
2099 | } | |
15bbde2b | 2100 | \f |
2101 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
2102 | ||
2103 | rtx | |
35cb5232 | 2104 | gen_label_rtx (void) |
15bbde2b | 2105 | { |
a7ae1e59 | 2106 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
35cb5232 | 2107 | NULL, label_num++, NULL); |
15bbde2b | 2108 | } |
2109 | \f | |
2110 | /* For procedure integration. */ | |
2111 | ||
15bbde2b | 2112 | /* Install new pointers to the first and last insns in the chain. |
d4c332ff | 2113 | Also, set cur_insn_uid to one higher than the last in use. |
15bbde2b | 2114 | Used for an inline-procedure after copying the insn chain. */ |
2115 | ||
2116 | void | |
35cb5232 | 2117 | set_new_first_and_last_insn (rtx first, rtx last) |
15bbde2b | 2118 | { |
d4c332ff | 2119 | rtx insn; |
2120 | ||
15bbde2b | 2121 | first_insn = first; |
2122 | last_insn = last; | |
d4c332ff | 2123 | cur_insn_uid = 0; |
2124 | ||
2125 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2126 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2127 | ||
2128 | cur_insn_uid++; | |
15bbde2b | 2129 | } |
15bbde2b | 2130 | \f |
d823ba47 | 2131 | /* Go through all the RTL insn bodies and copy any invalid shared |
2d96a59a | 2132 | structure. This routine should only be called once. */ |
15bbde2b | 2133 | |
a40c0eeb | 2134 | static void |
df329266 | 2135 | unshare_all_rtl_1 (rtx insn) |
15bbde2b | 2136 | { |
2d96a59a | 2137 | /* Unshare just about everything else. */ |
1cd4cfea | 2138 | unshare_all_rtl_in_chain (insn); |
d823ba47 | 2139 | |
15bbde2b | 2140 | /* Make sure the addresses of stack slots found outside the insn chain |
2141 | (such as, in DECL_RTL of a variable) are not shared | |
2142 | with the insn chain. | |
2143 | ||
2144 | This special care is necessary when the stack slot MEM does not | |
2145 | actually appear in the insn chain. If it does appear, its address | |
2146 | is unshared from all else at that point. */ | |
45733446 | 2147 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
15bbde2b | 2148 | } |
2149 | ||
d823ba47 | 2150 | /* Go through all the RTL insn bodies and copy any invalid shared |
2d96a59a | 2151 | structure, again. This is a fairly expensive thing to do so it |
2152 | should be done sparingly. */ | |
2153 | ||
2154 | void | |
35cb5232 | 2155 | unshare_all_rtl_again (rtx insn) |
2d96a59a | 2156 | { |
2157 | rtx p; | |
5244079b | 2158 | tree decl; |
2159 | ||
2d96a59a | 2160 | for (p = insn; p; p = NEXT_INSN (p)) |
9204e736 | 2161 | if (INSN_P (p)) |
2d96a59a | 2162 | { |
2163 | reset_used_flags (PATTERN (p)); | |
2164 | reset_used_flags (REG_NOTES (p)); | |
2d96a59a | 2165 | } |
5244079b | 2166 | |
01dc9f0c | 2167 | /* Make sure that virtual stack slots are not shared. */ |
265be050 | 2168 | set_used_decls (DECL_INITIAL (cfun->decl)); |
01dc9f0c | 2169 | |
5244079b | 2170 | /* Make sure that virtual parameters are not shared. */ |
2171 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
265be050 | 2172 | set_used_flags (DECL_RTL (decl)); |
5244079b | 2173 | |
2174 | reset_used_flags (stack_slot_list); | |
2175 | ||
df329266 | 2176 | unshare_all_rtl_1 (insn); |
a40c0eeb | 2177 | } |
2178 | ||
2a1990e9 | 2179 | unsigned int |
a40c0eeb | 2180 | unshare_all_rtl (void) |
2181 | { | |
df329266 | 2182 | unshare_all_rtl_1 (get_insns ()); |
2a1990e9 | 2183 | return 0; |
2d96a59a | 2184 | } |
2185 | ||
77fce4cd | 2186 | struct tree_opt_pass pass_unshare_all_rtl = |
2187 | { | |
228967a9 | 2188 | "unshare", /* name */ |
77fce4cd | 2189 | NULL, /* gate */ |
2190 | unshare_all_rtl, /* execute */ | |
2191 | NULL, /* sub */ | |
2192 | NULL, /* next */ | |
2193 | 0, /* static_pass_number */ | |
2194 | 0, /* tv_id */ | |
2195 | 0, /* properties_required */ | |
2196 | 0, /* properties_provided */ | |
2197 | 0, /* properties_destroyed */ | |
2198 | 0, /* todo_flags_start */ | |
228967a9 | 2199 | TODO_dump_func, /* todo_flags_finish */ |
77fce4cd | 2200 | 0 /* letter */ |
2201 | }; | |
2202 | ||
2203 | ||
1cd4cfea | 2204 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2205 | Recursively does the same for subexpressions. */ | |
2206 | ||
2207 | static void | |
2208 | verify_rtx_sharing (rtx orig, rtx insn) | |
2209 | { | |
2210 | rtx x = orig; | |
2211 | int i; | |
2212 | enum rtx_code code; | |
2213 | const char *format_ptr; | |
2214 | ||
2215 | if (x == 0) | |
2216 | return; | |
2217 | ||
2218 | code = GET_CODE (x); | |
2219 | ||
2220 | /* These types may be freely shared. */ | |
2221 | ||
2222 | switch (code) | |
2223 | { | |
2224 | case REG: | |
1cd4cfea | 2225 | case CONST_INT: |
2226 | case CONST_DOUBLE: | |
2227 | case CONST_VECTOR: | |
2228 | case SYMBOL_REF: | |
2229 | case LABEL_REF: | |
2230 | case CODE_LABEL: | |
2231 | case PC: | |
2232 | case CC0: | |
2233 | case SCRATCH: | |
1cd4cfea | 2234 | return; |
c09425a0 | 2235 | /* SCRATCH must be shared because they represent distinct values. */ |
2236 | case CLOBBER: | |
2237 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2238 | return; | |
2239 | break; | |
1cd4cfea | 2240 | |
2241 | case CONST: | |
3072d30e | 2242 | if (shared_const_p (orig)) |
1cd4cfea | 2243 | return; |
2244 | break; | |
2245 | ||
2246 | case MEM: | |
2247 | /* A MEM is allowed to be shared if its address is constant. */ | |
2248 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2249 | || reload_completed || reload_in_progress) | |
2250 | return; | |
2251 | ||
2252 | break; | |
2253 | ||
2254 | default: | |
2255 | break; | |
2256 | } | |
2257 | ||
2258 | /* This rtx may not be shared. If it has already been seen, | |
2259 | replace it with a copy of itself. */ | |
9cee7c3f | 2260 | #ifdef ENABLE_CHECKING |
1cd4cfea | 2261 | if (RTX_FLAG (x, used)) |
2262 | { | |
0a81f5a0 | 2263 | error ("invalid rtl sharing found in the insn"); |
1cd4cfea | 2264 | debug_rtx (insn); |
0a81f5a0 | 2265 | error ("shared rtx"); |
1cd4cfea | 2266 | debug_rtx (x); |
0a81f5a0 | 2267 | internal_error ("internal consistency failure"); |
1cd4cfea | 2268 | } |
9cee7c3f | 2269 | #endif |
2270 | gcc_assert (!RTX_FLAG (x, used)); | |
2271 | ||
1cd4cfea | 2272 | RTX_FLAG (x, used) = 1; |
2273 | ||
8b332087 | 2274 | /* Now scan the subexpressions recursively. */ |
1cd4cfea | 2275 | |
2276 | format_ptr = GET_RTX_FORMAT (code); | |
2277 | ||
2278 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2279 | { | |
2280 | switch (*format_ptr++) | |
2281 | { | |
2282 | case 'e': | |
2283 | verify_rtx_sharing (XEXP (x, i), insn); | |
2284 | break; | |
2285 | ||
2286 | case 'E': | |
2287 | if (XVEC (x, i) != NULL) | |
2288 | { | |
2289 | int j; | |
2290 | int len = XVECLEN (x, i); | |
2291 | ||
2292 | for (j = 0; j < len; j++) | |
2293 | { | |
9cee7c3f | 2294 | /* We allow sharing of ASM_OPERANDS inside single |
2295 | instruction. */ | |
1cd4cfea | 2296 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
9cee7c3f | 2297 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2298 | == ASM_OPERANDS)) | |
1cd4cfea | 2299 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2300 | else | |
2301 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2302 | } | |
2303 | } | |
2304 | break; | |
2305 | } | |
2306 | } | |
2307 | return; | |
2308 | } | |
2309 | ||
c7bf1374 | 2310 | /* Go through all the RTL insn bodies and check that there is no unexpected |
1cd4cfea | 2311 | sharing in between the subexpressions. */ |
2312 | ||
2313 | void | |
2314 | verify_rtl_sharing (void) | |
2315 | { | |
2316 | rtx p; | |
2317 | ||
2318 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2319 | if (INSN_P (p)) | |
2320 | { | |
2321 | reset_used_flags (PATTERN (p)); | |
2322 | reset_used_flags (REG_NOTES (p)); | |
764f640f | 2323 | if (GET_CODE (PATTERN (p)) == SEQUENCE) |
2324 | { | |
2325 | int i; | |
2326 | rtx q, sequence = PATTERN (p); | |
2327 | ||
2328 | for (i = 0; i < XVECLEN (sequence, 0); i++) | |
2329 | { | |
2330 | q = XVECEXP (sequence, 0, i); | |
2331 | gcc_assert (INSN_P (q)); | |
2332 | reset_used_flags (PATTERN (q)); | |
2333 | reset_used_flags (REG_NOTES (q)); | |
764f640f | 2334 | } |
2335 | } | |
1cd4cfea | 2336 | } |
2337 | ||
2338 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2339 | if (INSN_P (p)) | |
2340 | { | |
2341 | verify_rtx_sharing (PATTERN (p), p); | |
2342 | verify_rtx_sharing (REG_NOTES (p), p); | |
1cd4cfea | 2343 | } |
2344 | } | |
2345 | ||
2d96a59a | 2346 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2347 | Assumes the mark bits are cleared at entry. */ | |
2348 | ||
1cd4cfea | 2349 | void |
2350 | unshare_all_rtl_in_chain (rtx insn) | |
2d96a59a | 2351 | { |
2352 | for (; insn; insn = NEXT_INSN (insn)) | |
9204e736 | 2353 | if (INSN_P (insn)) |
2d96a59a | 2354 | { |
2355 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2356 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
2d96a59a | 2357 | } |
2358 | } | |
2359 | ||
01dc9f0c | 2360 | /* Go through all virtual stack slots of a function and mark them as |
265be050 | 2361 | shared. We never replace the DECL_RTLs themselves with a copy, |
2362 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2363 | expressions in the instruction stream. | |
2364 | ||
2365 | Note that reload may convert pseudo registers into memories in-place. | |
2366 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2367 | reset the used flags on MEMs in the instruction stream, we must set | |
2368 | them again on MEMs that appear in DECL_RTLs. */ | |
2369 | ||
01dc9f0c | 2370 | static void |
265be050 | 2371 | set_used_decls (tree blk) |
01dc9f0c | 2372 | { |
2373 | tree t; | |
2374 | ||
2375 | /* Mark decls. */ | |
2376 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
0e8e37b2 | 2377 | if (DECL_RTL_SET_P (t)) |
265be050 | 2378 | set_used_flags (DECL_RTL (t)); |
01dc9f0c | 2379 | |
2380 | /* Now process sub-blocks. */ | |
2381 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
265be050 | 2382 | set_used_decls (t); |
01dc9f0c | 2383 | } |
2384 | ||
15bbde2b | 2385 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
7ba6ce7a | 2386 | Recursively does the same for subexpressions. Uses |
2387 | copy_rtx_if_shared_1 to reduce stack space. */ | |
15bbde2b | 2388 | |
2389 | rtx | |
35cb5232 | 2390 | copy_rtx_if_shared (rtx orig) |
15bbde2b | 2391 | { |
0e0727c4 | 2392 | copy_rtx_if_shared_1 (&orig); |
2393 | return orig; | |
2394 | } | |
2395 | ||
7ba6ce7a | 2396 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2397 | use. Recursively does the same for subexpressions. */ | |
2398 | ||
0e0727c4 | 2399 | static void |
2400 | copy_rtx_if_shared_1 (rtx *orig1) | |
2401 | { | |
2402 | rtx x; | |
19cb6b50 | 2403 | int i; |
2404 | enum rtx_code code; | |
0e0727c4 | 2405 | rtx *last_ptr; |
19cb6b50 | 2406 | const char *format_ptr; |
15bbde2b | 2407 | int copied = 0; |
0e0727c4 | 2408 | int length; |
2409 | ||
2410 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2411 | repeat: | |
2412 | x = *orig1; | |
15bbde2b | 2413 | |
2414 | if (x == 0) | |
0e0727c4 | 2415 | return; |
15bbde2b | 2416 | |
2417 | code = GET_CODE (x); | |
2418 | ||
2419 | /* These types may be freely shared. */ | |
2420 | ||
2421 | switch (code) | |
2422 | { | |
2423 | case REG: | |
15bbde2b | 2424 | case CONST_INT: |
2425 | case CONST_DOUBLE: | |
886cfd4f | 2426 | case CONST_VECTOR: |
15bbde2b | 2427 | case SYMBOL_REF: |
1cd4cfea | 2428 | case LABEL_REF: |
15bbde2b | 2429 | case CODE_LABEL: |
2430 | case PC: | |
2431 | case CC0: | |
2432 | case SCRATCH: | |
a92771b8 | 2433 | /* SCRATCH must be shared because they represent distinct values. */ |
0e0727c4 | 2434 | return; |
c09425a0 | 2435 | case CLOBBER: |
2436 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2437 | return; | |
2438 | break; | |
15bbde2b | 2439 | |
f63d12e3 | 2440 | case CONST: |
3072d30e | 2441 | if (shared_const_p (x)) |
0e0727c4 | 2442 | return; |
f63d12e3 | 2443 | break; |
2444 | ||
15bbde2b | 2445 | case INSN: |
2446 | case JUMP_INSN: | |
2447 | case CALL_INSN: | |
2448 | case NOTE: | |
15bbde2b | 2449 | case BARRIER: |
2450 | /* The chain of insns is not being copied. */ | |
0e0727c4 | 2451 | return; |
15bbde2b | 2452 | |
0dbd1c74 | 2453 | default: |
2454 | break; | |
15bbde2b | 2455 | } |
2456 | ||
2457 | /* This rtx may not be shared. If it has already been seen, | |
2458 | replace it with a copy of itself. */ | |
2459 | ||
7c25cb91 | 2460 | if (RTX_FLAG (x, used)) |
15bbde2b | 2461 | { |
f2d0e9f1 | 2462 | x = shallow_copy_rtx (x); |
15bbde2b | 2463 | copied = 1; |
2464 | } | |
7c25cb91 | 2465 | RTX_FLAG (x, used) = 1; |
15bbde2b | 2466 | |
2467 | /* Now scan the subexpressions recursively. | |
2468 | We can store any replaced subexpressions directly into X | |
2469 | since we know X is not shared! Any vectors in X | |
2470 | must be copied if X was copied. */ | |
2471 | ||
2472 | format_ptr = GET_RTX_FORMAT (code); | |
0e0727c4 | 2473 | length = GET_RTX_LENGTH (code); |
2474 | last_ptr = NULL; | |
2475 | ||
2476 | for (i = 0; i < length; i++) | |
15bbde2b | 2477 | { |
2478 | switch (*format_ptr++) | |
2479 | { | |
2480 | case 'e': | |
0e0727c4 | 2481 | if (last_ptr) |
2482 | copy_rtx_if_shared_1 (last_ptr); | |
2483 | last_ptr = &XEXP (x, i); | |
15bbde2b | 2484 | break; |
2485 | ||
2486 | case 'E': | |
2487 | if (XVEC (x, i) != NULL) | |
2488 | { | |
19cb6b50 | 2489 | int j; |
ffe0869b | 2490 | int len = XVECLEN (x, i); |
0e0727c4 | 2491 | |
8b332087 | 2492 | /* Copy the vector iff I copied the rtx and the length |
2493 | is nonzero. */ | |
ffe0869b | 2494 | if (copied && len > 0) |
a4070a91 | 2495 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
0e0727c4 | 2496 | |
d632b59a | 2497 | /* Call recursively on all inside the vector. */ |
ffe0869b | 2498 | for (j = 0; j < len; j++) |
0e0727c4 | 2499 | { |
2500 | if (last_ptr) | |
2501 | copy_rtx_if_shared_1 (last_ptr); | |
2502 | last_ptr = &XVECEXP (x, i, j); | |
2503 | } | |
15bbde2b | 2504 | } |
2505 | break; | |
2506 | } | |
2507 | } | |
0e0727c4 | 2508 | *orig1 = x; |
2509 | if (last_ptr) | |
2510 | { | |
2511 | orig1 = last_ptr; | |
2512 | goto repeat; | |
2513 | } | |
2514 | return; | |
15bbde2b | 2515 | } |
2516 | ||
2517 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2518 | to look for shared sub-parts. */ | |
2519 | ||
2520 | void | |
35cb5232 | 2521 | reset_used_flags (rtx x) |
15bbde2b | 2522 | { |
19cb6b50 | 2523 | int i, j; |
2524 | enum rtx_code code; | |
2525 | const char *format_ptr; | |
0e0727c4 | 2526 | int length; |
15bbde2b | 2527 | |
0e0727c4 | 2528 | /* Repeat is used to turn tail-recursion into iteration. */ |
2529 | repeat: | |
15bbde2b | 2530 | if (x == 0) |
2531 | return; | |
2532 | ||
2533 | code = GET_CODE (x); | |
2534 | ||
c3418f42 | 2535 | /* These types may be freely shared so we needn't do any resetting |
15bbde2b | 2536 | for them. */ |
2537 | ||
2538 | switch (code) | |
2539 | { | |
2540 | case REG: | |
15bbde2b | 2541 | case CONST_INT: |
2542 | case CONST_DOUBLE: | |
886cfd4f | 2543 | case CONST_VECTOR: |
15bbde2b | 2544 | case SYMBOL_REF: |
2545 | case CODE_LABEL: | |
2546 | case PC: | |
2547 | case CC0: | |
2548 | return; | |
2549 | ||
2550 | case INSN: | |
2551 | case JUMP_INSN: | |
2552 | case CALL_INSN: | |
2553 | case NOTE: | |
2554 | case LABEL_REF: | |
2555 | case BARRIER: | |
2556 | /* The chain of insns is not being copied. */ | |
2557 | return; | |
d823ba47 | 2558 | |
0dbd1c74 | 2559 | default: |
2560 | break; | |
15bbde2b | 2561 | } |
2562 | ||
7c25cb91 | 2563 | RTX_FLAG (x, used) = 0; |
15bbde2b | 2564 | |
2565 | format_ptr = GET_RTX_FORMAT (code); | |
0e0727c4 | 2566 | length = GET_RTX_LENGTH (code); |
2567 | ||
2568 | for (i = 0; i < length; i++) | |
15bbde2b | 2569 | { |
2570 | switch (*format_ptr++) | |
2571 | { | |
2572 | case 'e': | |
0e0727c4 | 2573 | if (i == length-1) |
2574 | { | |
2575 | x = XEXP (x, i); | |
2576 | goto repeat; | |
2577 | } | |
15bbde2b | 2578 | reset_used_flags (XEXP (x, i)); |
2579 | break; | |
2580 | ||
2581 | case 'E': | |
2582 | for (j = 0; j < XVECLEN (x, i); j++) | |
2583 | reset_used_flags (XVECEXP (x, i, j)); | |
2584 | break; | |
2585 | } | |
2586 | } | |
2587 | } | |
1cd4cfea | 2588 | |
2589 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used | |
2590 | to look for shared sub-parts. */ | |
2591 | ||
2592 | void | |
2593 | set_used_flags (rtx x) | |
2594 | { | |
2595 | int i, j; | |
2596 | enum rtx_code code; | |
2597 | const char *format_ptr; | |
2598 | ||
2599 | if (x == 0) | |
2600 | return; | |
2601 | ||
2602 | code = GET_CODE (x); | |
2603 | ||
2604 | /* These types may be freely shared so we needn't do any resetting | |
2605 | for them. */ | |
2606 | ||
2607 | switch (code) | |
2608 | { | |
2609 | case REG: | |
1cd4cfea | 2610 | case CONST_INT: |
2611 | case CONST_DOUBLE: | |
2612 | case CONST_VECTOR: | |
2613 | case SYMBOL_REF: | |
2614 | case CODE_LABEL: | |
2615 | case PC: | |
2616 | case CC0: | |
2617 | return; | |
2618 | ||
2619 | case INSN: | |
2620 | case JUMP_INSN: | |
2621 | case CALL_INSN: | |
2622 | case NOTE: | |
2623 | case LABEL_REF: | |
2624 | case BARRIER: | |
2625 | /* The chain of insns is not being copied. */ | |
2626 | return; | |
2627 | ||
2628 | default: | |
2629 | break; | |
2630 | } | |
2631 | ||
2632 | RTX_FLAG (x, used) = 1; | |
2633 | ||
2634 | format_ptr = GET_RTX_FORMAT (code); | |
2635 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2636 | { | |
2637 | switch (*format_ptr++) | |
2638 | { | |
2639 | case 'e': | |
2640 | set_used_flags (XEXP (x, i)); | |
2641 | break; | |
2642 | ||
2643 | case 'E': | |
2644 | for (j = 0; j < XVECLEN (x, i); j++) | |
2645 | set_used_flags (XVECEXP (x, i, j)); | |
2646 | break; | |
2647 | } | |
2648 | } | |
2649 | } | |
15bbde2b | 2650 | \f |
2651 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2652 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2653 | OTHER must be valid as a SET_DEST. */ | |
2654 | ||
2655 | rtx | |
35cb5232 | 2656 | make_safe_from (rtx x, rtx other) |
15bbde2b | 2657 | { |
2658 | while (1) | |
2659 | switch (GET_CODE (other)) | |
2660 | { | |
2661 | case SUBREG: | |
2662 | other = SUBREG_REG (other); | |
2663 | break; | |
2664 | case STRICT_LOW_PART: | |
2665 | case SIGN_EXTEND: | |
2666 | case ZERO_EXTEND: | |
2667 | other = XEXP (other, 0); | |
2668 | break; | |
2669 | default: | |
2670 | goto done; | |
2671 | } | |
2672 | done: | |
e16ceb8e | 2673 | if ((MEM_P (other) |
15bbde2b | 2674 | && ! CONSTANT_P (x) |
8ad4c111 | 2675 | && !REG_P (x) |
15bbde2b | 2676 | && GET_CODE (x) != SUBREG) |
8ad4c111 | 2677 | || (REG_P (other) |
15bbde2b | 2678 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
2679 | || reg_mentioned_p (other, x)))) | |
2680 | { | |
2681 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2682 | emit_move_insn (temp, x); | |
2683 | return temp; | |
2684 | } | |
2685 | return x; | |
2686 | } | |
2687 | \f | |
2688 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2689 | ||
2690 | /* Return the first insn of the current sequence or current function. */ | |
2691 | ||
2692 | rtx | |
35cb5232 | 2693 | get_insns (void) |
15bbde2b | 2694 | { |
2695 | return first_insn; | |
2696 | } | |
2697 | ||
fb20d6fa | 2698 | /* Specify a new insn as the first in the chain. */ |
2699 | ||
2700 | void | |
35cb5232 | 2701 | set_first_insn (rtx insn) |
fb20d6fa | 2702 | { |
611234b4 | 2703 | gcc_assert (!PREV_INSN (insn)); |
fb20d6fa | 2704 | first_insn = insn; |
2705 | } | |
2706 | ||
15bbde2b | 2707 | /* Return the last insn emitted in current sequence or current function. */ |
2708 | ||
2709 | rtx | |
35cb5232 | 2710 | get_last_insn (void) |
15bbde2b | 2711 | { |
2712 | return last_insn; | |
2713 | } | |
2714 | ||
2715 | /* Specify a new insn as the last in the chain. */ | |
2716 | ||
2717 | void | |
35cb5232 | 2718 | set_last_insn (rtx insn) |
15bbde2b | 2719 | { |
611234b4 | 2720 | gcc_assert (!NEXT_INSN (insn)); |
15bbde2b | 2721 | last_insn = insn; |
2722 | } | |
2723 | ||
2724 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2725 | ||
2726 | rtx | |
35cb5232 | 2727 | get_last_insn_anywhere (void) |
15bbde2b | 2728 | { |
2729 | struct sequence_stack *stack; | |
2730 | if (last_insn) | |
2731 | return last_insn; | |
0a893c29 | 2732 | for (stack = seq_stack; stack; stack = stack->next) |
15bbde2b | 2733 | if (stack->last != 0) |
2734 | return stack->last; | |
2735 | return 0; | |
2736 | } | |
2737 | ||
70545de4 | 2738 | /* Return the first nonnote insn emitted in current sequence or current |
2739 | function. This routine looks inside SEQUENCEs. */ | |
2740 | ||
2741 | rtx | |
35cb5232 | 2742 | get_first_nonnote_insn (void) |
70545de4 | 2743 | { |
f86e856e | 2744 | rtx insn = first_insn; |
2745 | ||
2746 | if (insn) | |
2747 | { | |
2748 | if (NOTE_P (insn)) | |
2749 | for (insn = next_insn (insn); | |
2750 | insn && NOTE_P (insn); | |
2751 | insn = next_insn (insn)) | |
2752 | continue; | |
2753 | else | |
2754 | { | |
1c14a50e | 2755 | if (NONJUMP_INSN_P (insn) |
f86e856e | 2756 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2757 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2758 | } | |
2759 | } | |
70545de4 | 2760 | |
2761 | return insn; | |
2762 | } | |
2763 | ||
2764 | /* Return the last nonnote insn emitted in current sequence or current | |
2765 | function. This routine looks inside SEQUENCEs. */ | |
2766 | ||
2767 | rtx | |
35cb5232 | 2768 | get_last_nonnote_insn (void) |
70545de4 | 2769 | { |
f86e856e | 2770 | rtx insn = last_insn; |
2771 | ||
2772 | if (insn) | |
2773 | { | |
2774 | if (NOTE_P (insn)) | |
2775 | for (insn = previous_insn (insn); | |
2776 | insn && NOTE_P (insn); | |
2777 | insn = previous_insn (insn)) | |
2778 | continue; | |
2779 | else | |
2780 | { | |
1c14a50e | 2781 | if (NONJUMP_INSN_P (insn) |
f86e856e | 2782 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2783 | insn = XVECEXP (PATTERN (insn), 0, | |
2784 | XVECLEN (PATTERN (insn), 0) - 1); | |
2785 | } | |
2786 | } | |
70545de4 | 2787 | |
2788 | return insn; | |
2789 | } | |
2790 | ||
15bbde2b | 2791 | /* Return a number larger than any instruction's uid in this function. */ |
2792 | ||
2793 | int | |
35cb5232 | 2794 | get_max_uid (void) |
15bbde2b | 2795 | { |
2796 | return cur_insn_uid; | |
2797 | } | |
2798 | \f | |
2799 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2800 | of the sequence. */ | |
2801 | ||
2802 | rtx | |
35cb5232 | 2803 | next_insn (rtx insn) |
15bbde2b | 2804 | { |
2805 | if (insn) | |
2806 | { | |
2807 | insn = NEXT_INSN (insn); | |
6d7dc5b9 | 2808 | if (insn && NONJUMP_INSN_P (insn) |
15bbde2b | 2809 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2810 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2811 | } | |
2812 | ||
2813 | return insn; | |
2814 | } | |
2815 | ||
2816 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2817 | of the sequence. */ | |
2818 | ||
2819 | rtx | |
35cb5232 | 2820 | previous_insn (rtx insn) |
15bbde2b | 2821 | { |
2822 | if (insn) | |
2823 | { | |
2824 | insn = PREV_INSN (insn); | |
6d7dc5b9 | 2825 | if (insn && NONJUMP_INSN_P (insn) |
15bbde2b | 2826 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2827 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2828 | } | |
2829 | ||
2830 | return insn; | |
2831 | } | |
2832 | ||
2833 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2834 | look inside SEQUENCEs. */ | |
2835 | ||
2836 | rtx | |
35cb5232 | 2837 | next_nonnote_insn (rtx insn) |
15bbde2b | 2838 | { |
2839 | while (insn) | |
2840 | { | |
2841 | insn = NEXT_INSN (insn); | |
6d7dc5b9 | 2842 | if (insn == 0 || !NOTE_P (insn)) |
15bbde2b | 2843 | break; |
2844 | } | |
2845 | ||
2846 | return insn; | |
2847 | } | |
2848 | ||
2849 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2850 | not look inside SEQUENCEs. */ | |
2851 | ||
2852 | rtx | |
35cb5232 | 2853 | prev_nonnote_insn (rtx insn) |
15bbde2b | 2854 | { |
2855 | while (insn) | |
2856 | { | |
2857 | insn = PREV_INSN (insn); | |
6d7dc5b9 | 2858 | if (insn == 0 || !NOTE_P (insn)) |
15bbde2b | 2859 | break; |
2860 | } | |
2861 | ||
2862 | return insn; | |
2863 | } | |
2864 | ||
2865 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2866 | or 0, if there is none. This routine does not look inside | |
a92771b8 | 2867 | SEQUENCEs. */ |
15bbde2b | 2868 | |
2869 | rtx | |
35cb5232 | 2870 | next_real_insn (rtx insn) |
15bbde2b | 2871 | { |
2872 | while (insn) | |
2873 | { | |
2874 | insn = NEXT_INSN (insn); | |
e086b176 | 2875 | if (insn == 0 || INSN_P (insn)) |
15bbde2b | 2876 | break; |
2877 | } | |
2878 | ||
2879 | return insn; | |
2880 | } | |
2881 | ||
2882 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2883 | or 0, if there is none. This routine does not look inside | |
2884 | SEQUENCEs. */ | |
2885 | ||
2886 | rtx | |
35cb5232 | 2887 | prev_real_insn (rtx insn) |
15bbde2b | 2888 | { |
2889 | while (insn) | |
2890 | { | |
2891 | insn = PREV_INSN (insn); | |
e086b176 | 2892 | if (insn == 0 || INSN_P (insn)) |
15bbde2b | 2893 | break; |
2894 | } | |
2895 | ||
2896 | return insn; | |
2897 | } | |
2898 | ||
d5f9786f | 2899 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
2900 | This routine does not look inside SEQUENCEs. */ | |
2901 | ||
2902 | rtx | |
35cb5232 | 2903 | last_call_insn (void) |
d5f9786f | 2904 | { |
2905 | rtx insn; | |
2906 | ||
2907 | for (insn = get_last_insn (); | |
6d7dc5b9 | 2908 | insn && !CALL_P (insn); |
d5f9786f | 2909 | insn = PREV_INSN (insn)) |
2910 | ; | |
2911 | ||
2912 | return insn; | |
2913 | } | |
2914 | ||
15bbde2b | 2915 | /* Find the next insn after INSN that really does something. This routine |
2916 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2917 | same as next_real_insn. */ | |
2918 | ||
2215ca0d | 2919 | int |
52d07779 | 2920 | active_insn_p (const_rtx insn) |
2215ca0d | 2921 | { |
6d7dc5b9 | 2922 | return (CALL_P (insn) || JUMP_P (insn) |
2923 | || (NONJUMP_INSN_P (insn) | |
3a66feab | 2924 | && (! reload_completed |
2925 | || (GET_CODE (PATTERN (insn)) != USE | |
2926 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2215ca0d | 2927 | } |
2928 | ||
15bbde2b | 2929 | rtx |
35cb5232 | 2930 | next_active_insn (rtx insn) |
15bbde2b | 2931 | { |
2932 | while (insn) | |
2933 | { | |
2934 | insn = NEXT_INSN (insn); | |
2215ca0d | 2935 | if (insn == 0 || active_insn_p (insn)) |
15bbde2b | 2936 | break; |
2937 | } | |
2938 | ||
2939 | return insn; | |
2940 | } | |
2941 | ||
2942 | /* Find the last insn before INSN that really does something. This routine | |
2943 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2944 | same as prev_real_insn. */ | |
2945 | ||
2946 | rtx | |
35cb5232 | 2947 | prev_active_insn (rtx insn) |
15bbde2b | 2948 | { |
2949 | while (insn) | |
2950 | { | |
2951 | insn = PREV_INSN (insn); | |
2215ca0d | 2952 | if (insn == 0 || active_insn_p (insn)) |
15bbde2b | 2953 | break; |
2954 | } | |
2955 | ||
2956 | return insn; | |
2957 | } | |
2958 | ||
2959 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2960 | ||
2961 | rtx | |
35cb5232 | 2962 | next_label (rtx insn) |
15bbde2b | 2963 | { |
2964 | while (insn) | |
2965 | { | |
2966 | insn = NEXT_INSN (insn); | |
6d7dc5b9 | 2967 | if (insn == 0 || LABEL_P (insn)) |
15bbde2b | 2968 | break; |
2969 | } | |
2970 | ||
2971 | return insn; | |
2972 | } | |
2973 | ||
2974 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2975 | ||
2976 | rtx | |
35cb5232 | 2977 | prev_label (rtx insn) |
15bbde2b | 2978 | { |
2979 | while (insn) | |
2980 | { | |
2981 | insn = PREV_INSN (insn); | |
6d7dc5b9 | 2982 | if (insn == 0 || LABEL_P (insn)) |
15bbde2b | 2983 | break; |
2984 | } | |
2985 | ||
2986 | return insn; | |
2987 | } | |
67c5e2a9 | 2988 | |
2989 | /* Return the last label to mark the same position as LABEL. Return null | |
2990 | if LABEL itself is null. */ | |
2991 | ||
2992 | rtx | |
2993 | skip_consecutive_labels (rtx label) | |
2994 | { | |
2995 | rtx insn; | |
2996 | ||
2997 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | |
2998 | if (LABEL_P (insn)) | |
2999 | label = insn; | |
3000 | ||
3001 | return label; | |
3002 | } | |
15bbde2b | 3003 | \f |
3004 | #ifdef HAVE_cc0 | |
b15e0bba | 3005 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3006 | and REG_CC_USER notes so we can find it. */ | |
3007 | ||
3008 | void | |
35cb5232 | 3009 | link_cc0_insns (rtx insn) |
b15e0bba | 3010 | { |
3011 | rtx user = next_nonnote_insn (insn); | |
3012 | ||
6d7dc5b9 | 3013 | if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE) |
b15e0bba | 3014 | user = XVECEXP (PATTERN (user), 0, 0); |
3015 | ||
7014838c | 3016 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
3017 | REG_NOTES (user)); | |
3ad7bb1c | 3018 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
b15e0bba | 3019 | } |
3020 | ||
15bbde2b | 3021 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3022 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3023 | applied to the result of this function should yield INSN). | |
3024 | ||
3025 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3026 | is present, it contains the insn that uses CC0. | |
3027 | ||
3028 | Return 0 if we can't find the insn. */ | |
3029 | ||
3030 | rtx | |
35cb5232 | 3031 | next_cc0_user (rtx insn) |
15bbde2b | 3032 | { |
b572011e | 3033 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
15bbde2b | 3034 | |
3035 | if (note) | |
3036 | return XEXP (note, 0); | |
3037 | ||
3038 | insn = next_nonnote_insn (insn); | |
6d7dc5b9 | 3039 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
15bbde2b | 3040 | insn = XVECEXP (PATTERN (insn), 0, 0); |
3041 | ||
9204e736 | 3042 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
15bbde2b | 3043 | return insn; |
3044 | ||
3045 | return 0; | |
3046 | } | |
3047 | ||
3048 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3049 | note, it is the previous insn. */ | |
3050 | ||
3051 | rtx | |
35cb5232 | 3052 | prev_cc0_setter (rtx insn) |
15bbde2b | 3053 | { |
b572011e | 3054 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
15bbde2b | 3055 | |
3056 | if (note) | |
3057 | return XEXP (note, 0); | |
3058 | ||
3059 | insn = prev_nonnote_insn (insn); | |
611234b4 | 3060 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
15bbde2b | 3061 | |
3062 | return insn; | |
3063 | } | |
3064 | #endif | |
344dc2fa | 3065 | |
698ff1f0 | 3066 | #ifdef AUTO_INC_DEC |
3067 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3068 | ||
3069 | static int | |
3070 | find_auto_inc (rtx *xp, void *data) | |
3071 | { | |
3072 | rtx x = *xp; | |
3073 | rtx reg = data; | |
3074 | ||
3075 | if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC) | |
3076 | return 0; | |
3077 | ||
3078 | switch (GET_CODE (x)) | |
3079 | { | |
3080 | case PRE_DEC: | |
3081 | case PRE_INC: | |
3082 | case POST_DEC: | |
3083 | case POST_INC: | |
3084 | case PRE_MODIFY: | |
3085 | case POST_MODIFY: | |
3086 | if (rtx_equal_p (reg, XEXP (x, 0))) | |
3087 | return 1; | |
3088 | break; | |
3089 | ||
3090 | default: | |
3091 | gcc_unreachable (); | |
3092 | } | |
3093 | return -1; | |
3094 | } | |
3095 | #endif | |
3096 | ||
344dc2fa | 3097 | /* Increment the label uses for all labels present in rtx. */ |
3098 | ||
3099 | static void | |
35cb5232 | 3100 | mark_label_nuses (rtx x) |
344dc2fa | 3101 | { |
19cb6b50 | 3102 | enum rtx_code code; |
3103 | int i, j; | |
3104 | const char *fmt; | |
344dc2fa | 3105 | |
3106 | code = GET_CODE (x); | |
a030d4a8 | 3107 | if (code == LABEL_REF && LABEL_P (XEXP (x, 0))) |
344dc2fa | 3108 | LABEL_NUSES (XEXP (x, 0))++; |
3109 | ||
3110 | fmt = GET_RTX_FORMAT (code); | |
3111 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3112 | { | |
3113 | if (fmt[i] == 'e') | |
ff385626 | 3114 | mark_label_nuses (XEXP (x, i)); |
344dc2fa | 3115 | else if (fmt[i] == 'E') |
ff385626 | 3116 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
344dc2fa | 3117 | mark_label_nuses (XVECEXP (x, i, j)); |
3118 | } | |
3119 | } | |
3120 | ||
15bbde2b | 3121 | \f |
3122 | /* Try splitting insns that can be split for better scheduling. | |
3123 | PAT is the pattern which might split. | |
3124 | TRIAL is the insn providing PAT. | |
6ef828f9 | 3125 | LAST is nonzero if we should return the last insn of the sequence produced. |
15bbde2b | 3126 | |
3127 | If this routine succeeds in splitting, it returns the first or last | |
0e69a50a | 3128 | replacement insn depending on the value of LAST. Otherwise, it |
15bbde2b | 3129 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3130 | ||
3131 | rtx | |
35cb5232 | 3132 | try_split (rtx pat, rtx trial, int last) |
15bbde2b | 3133 | { |
3134 | rtx before = PREV_INSN (trial); | |
3135 | rtx after = NEXT_INSN (trial); | |
15bbde2b | 3136 | int has_barrier = 0; |
3137 | rtx tem; | |
3cd757b1 | 3138 | rtx note, seq; |
3139 | int probability; | |
e13693ec | 3140 | rtx insn_last, insn; |
3141 | int njumps = 0; | |
3cd757b1 | 3142 | |
3143 | if (any_condjump_p (trial) | |
3144 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3145 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3146 | probability = split_branch_probability; | |
3147 | ||
3148 | seq = split_insns (pat, trial); | |
3149 | ||
3150 | split_branch_probability = -1; | |
15bbde2b | 3151 | |
3152 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3153 | We may need to handle this specially. */ | |
6d7dc5b9 | 3154 | if (after && BARRIER_P (after)) |
15bbde2b | 3155 | { |
3156 | has_barrier = 1; | |
3157 | after = NEXT_INSN (after); | |
3158 | } | |
3159 | ||
e13693ec | 3160 | if (!seq) |
3161 | return trial; | |
3162 | ||
3163 | /* Avoid infinite loop if any insn of the result matches | |
3164 | the original pattern. */ | |
3165 | insn_last = seq; | |
3166 | while (1) | |
15bbde2b | 3167 | { |
e13693ec | 3168 | if (INSN_P (insn_last) |
3169 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3170 | return trial; | |
3171 | if (!NEXT_INSN (insn_last)) | |
3172 | break; | |
3173 | insn_last = NEXT_INSN (insn_last); | |
3174 | } | |
d823ba47 | 3175 | |
3072d30e | 3176 | /* We will be adding the new sequence to the function. The splitters |
3177 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3178 | unshare_all_rtl_in_chain (seq); | |
3179 | ||
e13693ec | 3180 | /* Mark labels. */ |
3181 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3182 | { | |
6d7dc5b9 | 3183 | if (JUMP_P (insn)) |
e13693ec | 3184 | { |
3185 | mark_jump_label (PATTERN (insn), insn, 0); | |
3186 | njumps++; | |
3187 | if (probability != -1 | |
3188 | && any_condjump_p (insn) | |
3189 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
31d3e01c | 3190 | { |
e13693ec | 3191 | /* We can preserve the REG_BR_PROB notes only if exactly |
3192 | one jump is created, otherwise the machine description | |
3193 | is responsible for this step using | |
3194 | split_branch_probability variable. */ | |
611234b4 | 3195 | gcc_assert (njumps == 1); |
e13693ec | 3196 | REG_NOTES (insn) |
3197 | = gen_rtx_EXPR_LIST (REG_BR_PROB, | |
3198 | GEN_INT (probability), | |
3199 | REG_NOTES (insn)); | |
31d3e01c | 3200 | } |
e13693ec | 3201 | } |
3202 | } | |
3203 | ||
3204 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3205 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
6d7dc5b9 | 3206 | if (CALL_P (trial)) |
e13693ec | 3207 | { |
3208 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
6d7dc5b9 | 3209 | if (CALL_P (insn)) |
e13693ec | 3210 | { |
0bb5a6cd | 3211 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3212 | while (*p) | |
3213 | p = &XEXP (*p, 1); | |
3214 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
e13693ec | 3215 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3216 | } | |
3217 | } | |
5262c253 | 3218 | |
e13693ec | 3219 | /* Copy notes, particularly those related to the CFG. */ |
3220 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3221 | { | |
3222 | switch (REG_NOTE_KIND (note)) | |
3223 | { | |
3224 | case REG_EH_REGION: | |
698ff1f0 | 3225 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
31d3e01c | 3226 | { |
6d7dc5b9 | 3227 | if (CALL_P (insn) |
379670b1 | 3228 | || (flag_non_call_exceptions && INSN_P (insn) |
e13693ec | 3229 | && may_trap_p (PATTERN (insn)))) |
3230 | REG_NOTES (insn) | |
3231 | = gen_rtx_EXPR_LIST (REG_EH_REGION, | |
3232 | XEXP (note, 0), | |
3233 | REG_NOTES (insn)); | |
31d3e01c | 3234 | } |
e13693ec | 3235 | break; |
381eb1e7 | 3236 | |
e13693ec | 3237 | case REG_NORETURN: |
3238 | case REG_SETJMP: | |
698ff1f0 | 3239 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
381eb1e7 | 3240 | { |
6d7dc5b9 | 3241 | if (CALL_P (insn)) |
e13693ec | 3242 | REG_NOTES (insn) |
3243 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3244 | XEXP (note, 0), | |
3245 | REG_NOTES (insn)); | |
381eb1e7 | 3246 | } |
e13693ec | 3247 | break; |
5bb27a4b | 3248 | |
e13693ec | 3249 | case REG_NON_LOCAL_GOTO: |
698ff1f0 | 3250 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
31d3e01c | 3251 | { |
6d7dc5b9 | 3252 | if (JUMP_P (insn)) |
e13693ec | 3253 | REG_NOTES (insn) |
3254 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3255 | XEXP (note, 0), | |
3256 | REG_NOTES (insn)); | |
31d3e01c | 3257 | } |
e13693ec | 3258 | break; |
344dc2fa | 3259 | |
698ff1f0 | 3260 | #ifdef AUTO_INC_DEC |
3261 | case REG_INC: | |
3262 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3263 | { | |
3264 | rtx reg = XEXP (note, 0); | |
3265 | if (!FIND_REG_INC_NOTE (insn, reg) | |
3266 | && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0) | |
3267 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, reg, | |
3268 | REG_NOTES (insn)); | |
3269 | } | |
3270 | break; | |
3271 | #endif | |
3272 | ||
e13693ec | 3273 | default: |
3274 | break; | |
15bbde2b | 3275 | } |
e13693ec | 3276 | } |
3277 | ||
3278 | /* If there are LABELS inside the split insns increment the | |
3279 | usage count so we don't delete the label. */ | |
6d7dc5b9 | 3280 | if (NONJUMP_INSN_P (trial)) |
e13693ec | 3281 | { |
3282 | insn = insn_last; | |
3283 | while (insn != NULL_RTX) | |
15bbde2b | 3284 | { |
6d7dc5b9 | 3285 | if (NONJUMP_INSN_P (insn)) |
e13693ec | 3286 | mark_label_nuses (PATTERN (insn)); |
15bbde2b | 3287 | |
e13693ec | 3288 | insn = PREV_INSN (insn); |
3289 | } | |
15bbde2b | 3290 | } |
3291 | ||
13751393 | 3292 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
e13693ec | 3293 | |
3294 | delete_insn (trial); | |
3295 | if (has_barrier) | |
3296 | emit_barrier_after (tem); | |
3297 | ||
3298 | /* Recursively call try_split for each new insn created; by the | |
3299 | time control returns here that insn will be fully split, so | |
3300 | set LAST and continue from the insn after the one returned. | |
3301 | We can't use next_active_insn here since AFTER may be a note. | |
3302 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3303 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3304 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3305 | tem = try_split (PATTERN (tem), tem, 1); | |
3306 | ||
3307 | /* Return either the first or the last insn, depending on which was | |
3308 | requested. */ | |
3309 | return last | |
3310 | ? (after ? PREV_INSN (after) : last_insn) | |
3311 | : NEXT_INSN (before); | |
15bbde2b | 3312 | } |
3313 | \f | |
3314 | /* Make and return an INSN rtx, initializing all its slots. | |
6a84e367 | 3315 | Store PATTERN in the pattern slots. */ |
15bbde2b | 3316 | |
3317 | rtx | |
35cb5232 | 3318 | make_insn_raw (rtx pattern) |
15bbde2b | 3319 | { |
19cb6b50 | 3320 | rtx insn; |
15bbde2b | 3321 | |
d7c47c0e | 3322 | insn = rtx_alloc (INSN); |
15bbde2b | 3323 | |
575333f9 | 3324 | INSN_UID (insn) = cur_insn_uid++; |
15bbde2b | 3325 | PATTERN (insn) = pattern; |
3326 | INSN_CODE (insn) = -1; | |
fc92fa61 | 3327 | REG_NOTES (insn) = NULL; |
375c1c8a | 3328 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ab87d1bc | 3329 | BLOCK_FOR_INSN (insn) = NULL; |
15bbde2b | 3330 | |
fe7f701d | 3331 | #ifdef ENABLE_RTL_CHECKING |
3332 | if (insn | |
9204e736 | 3333 | && INSN_P (insn) |
fe7f701d | 3334 | && (returnjump_p (insn) |
3335 | || (GET_CODE (insn) == SET | |
3336 | && SET_DEST (insn) == pc_rtx))) | |
3337 | { | |
c3ceba8e | 3338 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
fe7f701d | 3339 | debug_rtx (insn); |
3340 | } | |
3341 | #endif | |
d823ba47 | 3342 | |
15bbde2b | 3343 | return insn; |
3344 | } | |
3345 | ||
31d3e01c | 3346 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
15bbde2b | 3347 | |
89140b26 | 3348 | rtx |
35cb5232 | 3349 | make_jump_insn_raw (rtx pattern) |
15bbde2b | 3350 | { |
19cb6b50 | 3351 | rtx insn; |
15bbde2b | 3352 | |
6a84e367 | 3353 | insn = rtx_alloc (JUMP_INSN); |
fc92fa61 | 3354 | INSN_UID (insn) = cur_insn_uid++; |
15bbde2b | 3355 | |
3356 | PATTERN (insn) = pattern; | |
3357 | INSN_CODE (insn) = -1; | |
fc92fa61 | 3358 | REG_NOTES (insn) = NULL; |
3359 | JUMP_LABEL (insn) = NULL; | |
375c1c8a | 3360 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ab87d1bc | 3361 | BLOCK_FOR_INSN (insn) = NULL; |
15bbde2b | 3362 | |
3363 | return insn; | |
3364 | } | |
6e911104 | 3365 | |
31d3e01c | 3366 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
6e911104 | 3367 | |
3368 | static rtx | |
35cb5232 | 3369 | make_call_insn_raw (rtx pattern) |
6e911104 | 3370 | { |
19cb6b50 | 3371 | rtx insn; |
6e911104 | 3372 | |
3373 | insn = rtx_alloc (CALL_INSN); | |
3374 | INSN_UID (insn) = cur_insn_uid++; | |
3375 | ||
3376 | PATTERN (insn) = pattern; | |
3377 | INSN_CODE (insn) = -1; | |
6e911104 | 3378 | REG_NOTES (insn) = NULL; |
3379 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
375c1c8a | 3380 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ab87d1bc | 3381 | BLOCK_FOR_INSN (insn) = NULL; |
6e911104 | 3382 | |
3383 | return insn; | |
3384 | } | |
15bbde2b | 3385 | \f |
3386 | /* Add INSN to the end of the doubly-linked list. | |
3387 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3388 | ||
3389 | void | |
35cb5232 | 3390 | add_insn (rtx insn) |
15bbde2b | 3391 | { |
3392 | PREV_INSN (insn) = last_insn; | |
3393 | NEXT_INSN (insn) = 0; | |
3394 | ||
3395 | if (NULL != last_insn) | |
3396 | NEXT_INSN (last_insn) = insn; | |
3397 | ||
3398 | if (NULL == first_insn) | |
3399 | first_insn = insn; | |
3400 | ||
3401 | last_insn = insn; | |
3402 | } | |
3403 | ||
312de84d | 3404 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3405 | the next should be the only functions called to insert an insn once | |
f65c10c0 | 3406 | delay slots have been filled since only they know how to update a |
312de84d | 3407 | SEQUENCE. */ |
15bbde2b | 3408 | |
3409 | void | |
3072d30e | 3410 | add_insn_after (rtx insn, rtx after, basic_block bb) |
15bbde2b | 3411 | { |
3412 | rtx next = NEXT_INSN (after); | |
3413 | ||
611234b4 | 3414 | gcc_assert (!optimize || !INSN_DELETED_P (after)); |
f65c10c0 | 3415 | |
15bbde2b | 3416 | NEXT_INSN (insn) = next; |
3417 | PREV_INSN (insn) = after; | |
3418 | ||
3419 | if (next) | |
3420 | { | |
3421 | PREV_INSN (next) = insn; | |
6d7dc5b9 | 3422 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
15bbde2b | 3423 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; |
3424 | } | |
3425 | else if (last_insn == after) | |
3426 | last_insn = insn; | |
3427 | else | |
3428 | { | |
0a893c29 | 3429 | struct sequence_stack *stack = seq_stack; |
15bbde2b | 3430 | /* Scan all pending sequences too. */ |
3431 | for (; stack; stack = stack->next) | |
3432 | if (after == stack->last) | |
398f4855 | 3433 | { |
3434 | stack->last = insn; | |
3435 | break; | |
3436 | } | |
312de84d | 3437 | |
611234b4 | 3438 | gcc_assert (stack); |
15bbde2b | 3439 | } |
3440 | ||
6d7dc5b9 | 3441 | if (!BARRIER_P (after) |
3442 | && !BARRIER_P (insn) | |
9dda7915 | 3443 | && (bb = BLOCK_FOR_INSN (after))) |
3444 | { | |
3445 | set_block_for_insn (insn, bb); | |
308f9b79 | 3446 | if (INSN_P (insn)) |
3072d30e | 3447 | df_insn_rescan (insn); |
9dda7915 | 3448 | /* Should not happen as first in the BB is always |
3fb1e43b | 3449 | either NOTE or LABEL. */ |
5496dbfc | 3450 | if (BB_END (bb) == after |
9dda7915 | 3451 | /* Avoid clobbering of structure when creating new BB. */ |
6d7dc5b9 | 3452 | && !BARRIER_P (insn) |
ad4583d9 | 3453 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
5496dbfc | 3454 | BB_END (bb) = insn; |
9dda7915 | 3455 | } |
3456 | ||
15bbde2b | 3457 | NEXT_INSN (after) = insn; |
6d7dc5b9 | 3458 | if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE) |
15bbde2b | 3459 | { |
3460 | rtx sequence = PATTERN (after); | |
3461 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3462 | } | |
3463 | } | |
3464 | ||
312de84d | 3465 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
3072d30e | 3466 | the previous should be the only functions called to insert an insn |
3467 | once delay slots have been filled since only they know how to | |
3468 | update a SEQUENCE. If BB is NULL, an attempt is made to infer the | |
3469 | bb from before. */ | |
312de84d | 3470 | |
3471 | void | |
3072d30e | 3472 | add_insn_before (rtx insn, rtx before, basic_block bb) |
312de84d | 3473 | { |
3474 | rtx prev = PREV_INSN (before); | |
3475 | ||
611234b4 | 3476 | gcc_assert (!optimize || !INSN_DELETED_P (before)); |
f65c10c0 | 3477 | |
312de84d | 3478 | PREV_INSN (insn) = prev; |
3479 | NEXT_INSN (insn) = before; | |
3480 | ||
3481 | if (prev) | |
3482 | { | |
3483 | NEXT_INSN (prev) = insn; | |
6d7dc5b9 | 3484 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
312de84d | 3485 | { |
3486 | rtx sequence = PATTERN (prev); | |
3487 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3488 | } | |
3489 | } | |
3490 | else if (first_insn == before) | |
3491 | first_insn = insn; | |
3492 | else | |
3493 | { | |
0a893c29 | 3494 | struct sequence_stack *stack = seq_stack; |
312de84d | 3495 | /* Scan all pending sequences too. */ |
3496 | for (; stack; stack = stack->next) | |
3497 | if (before == stack->first) | |
398f4855 | 3498 | { |
3499 | stack->first = insn; | |
3500 | break; | |
3501 | } | |
312de84d | 3502 | |
611234b4 | 3503 | gcc_assert (stack); |
312de84d | 3504 | } |
3505 | ||
3072d30e | 3506 | if (!bb |
3507 | && !BARRIER_P (before) | |
3508 | && !BARRIER_P (insn)) | |
3509 | bb = BLOCK_FOR_INSN (before); | |
3510 | ||
3511 | if (bb) | |
9dda7915 | 3512 | { |
3513 | set_block_for_insn (insn, bb); | |
308f9b79 | 3514 | if (INSN_P (insn)) |
3072d30e | 3515 | df_insn_rescan (insn); |
611234b4 | 3516 | /* Should not happen as first in the BB is always either NOTE or |
ba821eb1 | 3517 | LABEL. */ |
611234b4 | 3518 | gcc_assert (BB_HEAD (bb) != insn |
3519 | /* Avoid clobbering of structure when creating new BB. */ | |
3520 | || BARRIER_P (insn) | |
ad4583d9 | 3521 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
9dda7915 | 3522 | } |
3523 | ||
312de84d | 3524 | PREV_INSN (before) = insn; |
6d7dc5b9 | 3525 | if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE) |
312de84d | 3526 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; |
3527 | } | |
3528 | ||
3072d30e | 3529 | |
3530 | /* Replace insn with an deleted instruction note. */ | |
3531 | ||
3532 | void set_insn_deleted (rtx insn) | |
3533 | { | |
3534 | df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn)); | |
3535 | PUT_CODE (insn, NOTE); | |
3536 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
3537 | } | |
3538 | ||
3539 | ||
7ddcf2bf | 3540 | /* Remove an insn from its doubly-linked list. This function knows how |
3541 | to handle sequences. */ | |
3542 | void | |
35cb5232 | 3543 | remove_insn (rtx insn) |
7ddcf2bf | 3544 | { |
3545 | rtx next = NEXT_INSN (insn); | |
3546 | rtx prev = PREV_INSN (insn); | |
e4bf866d | 3547 | basic_block bb; |
3548 | ||
3072d30e | 3549 | /* Later in the code, the block will be marked dirty. */ |
3550 | df_insn_delete (NULL, INSN_UID (insn)); | |
3551 | ||
7ddcf2bf | 3552 | if (prev) |
3553 | { | |
3554 | NEXT_INSN (prev) = next; | |
6d7dc5b9 | 3555 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
7ddcf2bf | 3556 | { |
3557 | rtx sequence = PATTERN (prev); | |
3558 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3559 | } | |
3560 | } | |
3561 | else if (first_insn == insn) | |
3562 | first_insn = next; | |
3563 | else | |
3564 | { | |
0a893c29 | 3565 | struct sequence_stack *stack = seq_stack; |
7ddcf2bf | 3566 | /* Scan all pending sequences too. */ |
3567 | for (; stack; stack = stack->next) | |
3568 | if (insn == stack->first) | |
3569 | { | |
3570 | stack->first = next; | |
3571 | break; | |
3572 | } | |
3573 | ||
611234b4 | 3574 | gcc_assert (stack); |
7ddcf2bf | 3575 | } |
3576 | ||
3577 | if (next) | |
3578 | { | |
3579 | PREV_INSN (next) = prev; | |
6d7dc5b9 | 3580 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
7ddcf2bf | 3581 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; |
3582 | } | |
3583 | else if (last_insn == insn) | |
3584 | last_insn = prev; | |
3585 | else | |
3586 | { | |
0a893c29 | 3587 | struct sequence_stack *stack = seq_stack; |
7ddcf2bf | 3588 | /* Scan all pending sequences too. */ |
3589 | for (; stack; stack = stack->next) | |
3590 | if (insn == stack->last) | |
3591 | { | |
3592 | stack->last = prev; | |
3593 | break; | |
3594 | } | |
3595 | ||
611234b4 | 3596 | gcc_assert (stack); |
7ddcf2bf | 3597 | } |
6d7dc5b9 | 3598 | if (!BARRIER_P (insn) |
e4bf866d | 3599 | && (bb = BLOCK_FOR_INSN (insn))) |
3600 | { | |
308f9b79 | 3601 | if (INSN_P (insn)) |
3072d30e | 3602 | df_set_bb_dirty (bb); |
5496dbfc | 3603 | if (BB_HEAD (bb) == insn) |
e4bf866d | 3604 | { |
f4aee538 | 3605 | /* Never ever delete the basic block note without deleting whole |
3606 | basic block. */ | |
611234b4 | 3607 | gcc_assert (!NOTE_P (insn)); |
5496dbfc | 3608 | BB_HEAD (bb) = next; |
e4bf866d | 3609 | } |
5496dbfc | 3610 | if (BB_END (bb) == insn) |
3611 | BB_END (bb) = prev; | |
e4bf866d | 3612 | } |
7ddcf2bf | 3613 | } |
3614 | ||
d5f9786f | 3615 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3616 | ||
3617 | void | |
35cb5232 | 3618 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
d5f9786f | 3619 | { |
611234b4 | 3620 | gcc_assert (call_insn && CALL_P (call_insn)); |
d5f9786f | 3621 | |
3622 | /* Put the register usage information on the CALL. If there is already | |
3623 | some usage information, put ours at the end. */ | |
3624 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3625 | { | |
3626 | rtx link; | |
3627 | ||
3628 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3629 | link = XEXP (link, 1)) | |
3630 | ; | |
3631 | ||
3632 | XEXP (link, 1) = call_fusage; | |
3633 | } | |
3634 | else | |
3635 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3636 | } | |
3637 | ||
15bbde2b | 3638 | /* Delete all insns made since FROM. |
3639 | FROM becomes the new last instruction. */ | |
3640 | ||
3641 | void | |
35cb5232 | 3642 | delete_insns_since (rtx from) |
15bbde2b | 3643 | { |
3644 | if (from == 0) | |
3645 | first_insn = 0; | |
3646 | else | |
3647 | NEXT_INSN (from) = 0; | |
3648 | last_insn = from; | |
3649 | } | |
3650 | ||
34e2ddcd | 3651 | /* This function is deprecated, please use sequences instead. |
3652 | ||
3653 | Move a consecutive bunch of insns to a different place in the chain. | |
15bbde2b | 3654 | The insns to be moved are those between FROM and TO. |
3655 | They are moved to a new position after the insn AFTER. | |
3656 | AFTER must not be FROM or TO or any insn in between. | |
3657 | ||
3658 | This function does not know about SEQUENCEs and hence should not be | |
3659 | called after delay-slot filling has been done. */ | |
3660 | ||
3661 | void | |
35cb5232 | 3662 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
15bbde2b | 3663 | { |
3664 | /* Splice this bunch out of where it is now. */ | |
3665 | if (PREV_INSN (from)) | |
3666 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3667 | if (NEXT_INSN (to)) | |
3668 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
3669 | if (last_insn == to) | |
3670 | last_insn = PREV_INSN (from); | |
3671 | if (first_insn == from) | |
3672 | first_insn = NEXT_INSN (to); | |
3673 | ||
3674 | /* Make the new neighbors point to it and it to them. */ | |
3675 | if (NEXT_INSN (after)) | |
3676 | PREV_INSN (NEXT_INSN (after)) = to; | |
3677 | ||
3678 | NEXT_INSN (to) = NEXT_INSN (after); | |
3679 | PREV_INSN (from) = after; | |
3680 | NEXT_INSN (after) = from; | |
3681 | if (after == last_insn) | |
3682 | last_insn = to; | |
3683 | } | |
3684 | ||
9dda7915 | 3685 | /* Same as function above, but take care to update BB boundaries. */ |
3686 | void | |
35cb5232 | 3687 | reorder_insns (rtx from, rtx to, rtx after) |
9dda7915 | 3688 | { |
3689 | rtx prev = PREV_INSN (from); | |
3690 | basic_block bb, bb2; | |
3691 | ||
3692 | reorder_insns_nobb (from, to, after); | |
3693 | ||
6d7dc5b9 | 3694 | if (!BARRIER_P (after) |
9dda7915 | 3695 | && (bb = BLOCK_FOR_INSN (after))) |
3696 | { | |
3697 | rtx x; | |
3072d30e | 3698 | df_set_bb_dirty (bb); |
d4c5e26d | 3699 | |
6d7dc5b9 | 3700 | if (!BARRIER_P (from) |
9dda7915 | 3701 | && (bb2 = BLOCK_FOR_INSN (from))) |
3702 | { | |
5496dbfc | 3703 | if (BB_END (bb2) == to) |
3704 | BB_END (bb2) = prev; | |
3072d30e | 3705 | df_set_bb_dirty (bb2); |
9dda7915 | 3706 | } |
3707 | ||
5496dbfc | 3708 | if (BB_END (bb) == after) |
3709 | BB_END (bb) = to; | |
9dda7915 | 3710 | |
3711 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7097dd0c | 3712 | if (!BARRIER_P (x)) |
3072d30e | 3713 | { |
3714 | set_block_for_insn (x, bb); | |
3715 | df_insn_change_bb (x); | |
3716 | } | |
9dda7915 | 3717 | } |
3718 | } | |
3719 | ||
15bbde2b | 3720 | \f |
31d3e01c | 3721 | /* Emit insn(s) of given code and pattern |
3722 | at a specified place within the doubly-linked list. | |
15bbde2b | 3723 | |
31d3e01c | 3724 | All of the emit_foo global entry points accept an object |
3725 | X which is either an insn list or a PATTERN of a single | |
3726 | instruction. | |
15bbde2b | 3727 | |
31d3e01c | 3728 | There are thus a few canonical ways to generate code and |
3729 | emit it at a specific place in the instruction stream. For | |
3730 | example, consider the instruction named SPOT and the fact that | |
3731 | we would like to emit some instructions before SPOT. We might | |
3732 | do it like this: | |
15bbde2b | 3733 | |
31d3e01c | 3734 | start_sequence (); |
3735 | ... emit the new instructions ... | |
3736 | insns_head = get_insns (); | |
3737 | end_sequence (); | |
15bbde2b | 3738 | |
31d3e01c | 3739 | emit_insn_before (insns_head, SPOT); |
15bbde2b | 3740 | |
31d3e01c | 3741 | It used to be common to generate SEQUENCE rtl instead, but that |
3742 | is a relic of the past which no longer occurs. The reason is that | |
3743 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
3744 | generated would almost certainly die right after it was created. */ | |
15bbde2b | 3745 | |
31d3e01c | 3746 | /* Make X be output before the instruction BEFORE. */ |
15bbde2b | 3747 | |
3748 | rtx | |
3072d30e | 3749 | emit_insn_before_noloc (rtx x, rtx before, basic_block bb) |
15bbde2b | 3750 | { |
31d3e01c | 3751 | rtx last = before; |
19cb6b50 | 3752 | rtx insn; |
15bbde2b | 3753 | |
611234b4 | 3754 | gcc_assert (before); |
31d3e01c | 3755 | |
3756 | if (x == NULL_RTX) | |
3757 | return last; | |
3758 | ||
3759 | switch (GET_CODE (x)) | |
15bbde2b | 3760 | { |
31d3e01c | 3761 | case INSN: |
3762 | case JUMP_INSN: | |
3763 | case CALL_INSN: | |
3764 | case CODE_LABEL: | |
3765 | case BARRIER: | |
3766 | case NOTE: | |
3767 | insn = x; | |
3768 | while (insn) | |
3769 | { | |
3770 | rtx next = NEXT_INSN (insn); | |
3072d30e | 3771 | add_insn_before (insn, before, bb); |
31d3e01c | 3772 | last = insn; |
3773 | insn = next; | |
3774 | } | |
3775 | break; | |
3776 | ||
3777 | #ifdef ENABLE_RTL_CHECKING | |
3778 | case SEQUENCE: | |
611234b4 | 3779 | gcc_unreachable (); |
31d3e01c | 3780 | break; |
3781 | #endif | |
3782 | ||
3783 | default: | |
3784 | last = make_insn_raw (x); | |
3072d30e | 3785 | add_insn_before (last, before, bb); |
31d3e01c | 3786 | break; |
15bbde2b | 3787 | } |
3788 | ||
31d3e01c | 3789 | return last; |
15bbde2b | 3790 | } |
3791 | ||
31d3e01c | 3792 | /* Make an instruction with body X and code JUMP_INSN |
15bbde2b | 3793 | and output it before the instruction BEFORE. */ |
3794 | ||
3795 | rtx | |
0891f67c | 3796 | emit_jump_insn_before_noloc (rtx x, rtx before) |
15bbde2b | 3797 | { |
d90b3d04 | 3798 | rtx insn, last = NULL_RTX; |
6e911104 | 3799 | |
611234b4 | 3800 | gcc_assert (before); |
31d3e01c | 3801 | |
3802 | switch (GET_CODE (x)) | |
6e911104 | 3803 | { |
31d3e01c | 3804 | case INSN: |
3805 | case JUMP_INSN: | |
3806 | case CALL_INSN: | |
3807 | case CODE_LABEL: | |
3808 | case BARRIER: | |
3809 | case NOTE: | |
3810 | insn = x; | |
3811 | while (insn) | |
3812 | { | |
3813 | rtx next = NEXT_INSN (insn); | |
3072d30e | 3814 | add_insn_before (insn, before, NULL); |
31d3e01c | 3815 | last = insn; |
3816 | insn = next; | |
3817 | } | |
3818 | break; | |
3819 | ||
3820 | #ifdef ENABLE_RTL_CHECKING | |
3821 | case SEQUENCE: | |
611234b4 | 3822 | gcc_unreachable (); |
31d3e01c | 3823 | break; |
3824 | #endif | |
3825 | ||
3826 | default: | |
3827 | last = make_jump_insn_raw (x); | |
3072d30e | 3828 | add_insn_before (last, before, NULL); |
31d3e01c | 3829 | break; |
6e911104 | 3830 | } |
3831 | ||
31d3e01c | 3832 | return last; |
15bbde2b | 3833 | } |
3834 | ||
31d3e01c | 3835 | /* Make an instruction with body X and code CALL_INSN |
cd0fe062 | 3836 | and output it before the instruction BEFORE. */ |
3837 | ||
3838 | rtx | |
0891f67c | 3839 | emit_call_insn_before_noloc (rtx x, rtx before) |
cd0fe062 | 3840 | { |
d90b3d04 | 3841 | rtx last = NULL_RTX, insn; |
cd0fe062 | 3842 | |
611234b4 | 3843 | gcc_assert (before); |
31d3e01c | 3844 | |
3845 | switch (GET_CODE (x)) | |
cd0fe062 | 3846 | { |
31d3e01c | 3847 | case INSN: |
3848 | case JUMP_INSN: | |
3849 | case CALL_INSN: | |
3850 | case CODE_LABEL: | |
3851 | case BARRIER: | |
3852 | case NOTE: | |
3853 | insn = x; | |
3854 | while (insn) | |
3855 | { | |
3856 | rtx next = NEXT_INSN (insn); | |
3072d30e | 3857 | add_insn_before (insn, before, NULL); |
31d3e01c | 3858 | last = insn; |
3859 | insn = next; | |
3860 | } | |
3861 | break; | |
3862 | ||
3863 | #ifdef ENABLE_RTL_CHECKING | |
3864 | case SEQUENCE: | |
611234b4 | 3865 | gcc_unreachable (); |
31d3e01c | 3866 | break; |
3867 | #endif | |
3868 | ||
3869 | default: | |
3870 | last = make_call_insn_raw (x); | |
3072d30e | 3871 | add_insn_before (last, before, NULL); |
31d3e01c | 3872 | break; |
cd0fe062 | 3873 | } |
3874 | ||
31d3e01c | 3875 | return last; |
cd0fe062 | 3876 | } |
3877 | ||
15bbde2b | 3878 | /* Make an insn of code BARRIER |
71caadc0 | 3879 | and output it before the insn BEFORE. */ |
15bbde2b | 3880 | |
3881 | rtx | |
35cb5232 | 3882 | emit_barrier_before (rtx before) |
15bbde2b | 3883 | { |
19cb6b50 | 3884 | rtx insn = rtx_alloc (BARRIER); |
15bbde2b | 3885 | |
3886 | INSN_UID (insn) = cur_insn_uid++; | |
3887 | ||
3072d30e | 3888 | add_insn_before (insn, before, NULL); |
15bbde2b | 3889 | return insn; |
3890 | } | |
3891 | ||
71caadc0 | 3892 | /* Emit the label LABEL before the insn BEFORE. */ |
3893 | ||
3894 | rtx | |
35cb5232 | 3895 | emit_label_before (rtx label, rtx before) |
71caadc0 | 3896 | { |
3897 | /* This can be called twice for the same label as a result of the | |
3898 | confusion that follows a syntax error! So make it harmless. */ | |
3899 | if (INSN_UID (label) == 0) | |
3900 | { | |
3901 | INSN_UID (label) = cur_insn_uid++; | |
3072d30e | 3902 | add_insn_before (label, before, NULL); |
71caadc0 | 3903 | } |
3904 | ||
3905 | return label; | |
3906 | } | |
3907 | ||
15bbde2b | 3908 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
3909 | ||
3910 | rtx | |
ad4583d9 | 3911 | emit_note_before (enum insn_note subtype, rtx before) |
15bbde2b | 3912 | { |
19cb6b50 | 3913 | rtx note = rtx_alloc (NOTE); |
15bbde2b | 3914 | INSN_UID (note) = cur_insn_uid++; |
ad4583d9 | 3915 | NOTE_KIND (note) = subtype; |
ab87d1bc | 3916 | BLOCK_FOR_INSN (note) = NULL; |
60ad3b0e | 3917 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
15bbde2b | 3918 | |
3072d30e | 3919 | add_insn_before (note, before, NULL); |
15bbde2b | 3920 | return note; |
3921 | } | |
3922 | \f | |
31d3e01c | 3923 | /* Helper for emit_insn_after, handles lists of instructions |
3924 | efficiently. */ | |
15bbde2b | 3925 | |
31d3e01c | 3926 | static rtx |
3072d30e | 3927 | emit_insn_after_1 (rtx first, rtx after, basic_block bb) |
15bbde2b | 3928 | { |
31d3e01c | 3929 | rtx last; |
3930 | rtx after_after; | |
3072d30e | 3931 | if (!bb && !BARRIER_P (after)) |
3932 | bb = BLOCK_FOR_INSN (after); | |
15bbde2b | 3933 | |
3072d30e | 3934 | if (bb) |
15bbde2b | 3935 | { |
3072d30e | 3936 | df_set_bb_dirty (bb); |
31d3e01c | 3937 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
6d7dc5b9 | 3938 | if (!BARRIER_P (last)) |
3072d30e | 3939 | { |
3940 | set_block_for_insn (last, bb); | |
3941 | df_insn_rescan (last); | |
3942 | } | |
6d7dc5b9 | 3943 | if (!BARRIER_P (last)) |
3072d30e | 3944 | { |
3945 | set_block_for_insn (last, bb); | |
3946 | df_insn_rescan (last); | |
3947 | } | |
5496dbfc | 3948 | if (BB_END (bb) == after) |
3949 | BB_END (bb) = last; | |
15bbde2b | 3950 | } |
3951 | else | |
31d3e01c | 3952 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
3953 | continue; | |
3954 | ||
3955 | after_after = NEXT_INSN (after); | |
3956 | ||
3957 | NEXT_INSN (after) = first; | |
3958 | PREV_INSN (first) = after; | |
3959 | NEXT_INSN (last) = after_after; | |
3960 | if (after_after) | |
3961 | PREV_INSN (after_after) = last; | |
3962 | ||
3963 | if (after == last_insn) | |
3964 | last_insn = last; | |
3965 | return last; | |
3966 | } | |
3967 | ||
3072d30e | 3968 | /* Make X be output after the insn AFTER and set the BB of insn. If |
3969 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
31d3e01c | 3970 | |
3971 | rtx | |
3072d30e | 3972 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
31d3e01c | 3973 | { |
3974 | rtx last = after; | |
3975 | ||
611234b4 | 3976 | gcc_assert (after); |
31d3e01c | 3977 | |
3978 | if (x == NULL_RTX) | |
3979 | return last; | |
3980 | ||
3981 | switch (GET_CODE (x)) | |
15bbde2b | 3982 | { |
31d3e01c | 3983 | case INSN: |
3984 | case JUMP_INSN: | |
3985 | case CALL_INSN: | |
3986 | case CODE_LABEL: | |
3987 | case BARRIER: | |
3988 | case NOTE: | |
3072d30e | 3989 | last = emit_insn_after_1 (x, after, bb); |
31d3e01c | 3990 | break; |
3991 | ||
3992 | #ifdef ENABLE_RTL_CHECKING | |
3993 | case SEQUENCE: | |
611234b4 | 3994 | gcc_unreachable (); |
31d3e01c | 3995 | break; |
3996 | #endif | |
3997 | ||
3998 | default: | |
3999 | last = make_insn_raw (x); | |
3072d30e | 4000 | add_insn_after (last, after, bb); |
31d3e01c | 4001 | break; |
15bbde2b | 4002 | } |
4003 | ||
31d3e01c | 4004 | return last; |
15bbde2b | 4005 | } |
4006 | ||
1bea98fb | 4007 | |
31d3e01c | 4008 | /* Make an insn of code JUMP_INSN with body X |
15bbde2b | 4009 | and output it after the insn AFTER. */ |
4010 | ||
4011 | rtx | |
0891f67c | 4012 | emit_jump_insn_after_noloc (rtx x, rtx after) |
15bbde2b | 4013 | { |
31d3e01c | 4014 | rtx last; |
15bbde2b | 4015 | |
611234b4 | 4016 | gcc_assert (after); |
31d3e01c | 4017 | |
4018 | switch (GET_CODE (x)) | |
15bbde2b | 4019 | { |
31d3e01c | 4020 | case INSN: |
4021 | case JUMP_INSN: | |
4022 | case CALL_INSN: | |
4023 | case CODE_LABEL: | |
4024 | case BARRIER: | |
4025 | case NOTE: | |
3072d30e | 4026 | last = emit_insn_after_1 (x, after, NULL); |
31d3e01c | 4027 | break; |
4028 | ||
4029 | #ifdef ENABLE_RTL_CHECKING | |
4030 | case SEQUENCE: | |
611234b4 | 4031 | gcc_unreachable (); |
31d3e01c | 4032 | break; |
4033 | #endif | |
4034 | ||
4035 | default: | |
4036 | last = make_jump_insn_raw (x); | |
3072d30e | 4037 | add_insn_after (last, after, NULL); |
31d3e01c | 4038 | break; |
15bbde2b | 4039 | } |
4040 | ||
31d3e01c | 4041 | return last; |
4042 | } | |
4043 | ||
4044 | /* Make an instruction with body X and code CALL_INSN | |
4045 | and output it after the instruction AFTER. */ | |
4046 | ||
4047 | rtx | |
0891f67c | 4048 | emit_call_insn_after_noloc (rtx x, rtx after) |
31d3e01c | 4049 | { |
4050 | rtx last; | |
4051 | ||
611234b4 | 4052 | gcc_assert (after); |
31d3e01c | 4053 | |
4054 | switch (GET_CODE (x)) | |
4055 | { | |
4056 | case INSN: | |
4057 | case JUMP_INSN: | |
4058 | case CALL_INSN: | |
4059 | case CODE_LABEL: | |
4060 | case BARRIER: | |
4061 | case NOTE: | |
3072d30e | 4062 | last = emit_insn_after_1 (x, after, NULL); |
31d3e01c | 4063 | break; |
4064 | ||
4065 | #ifdef ENABLE_RTL_CHECKING | |
4066 | case SEQUENCE: | |
611234b4 | 4067 | gcc_unreachable (); |
31d3e01c | 4068 | break; |
4069 | #endif | |
4070 | ||
4071 | default: | |
4072 | last = make_call_insn_raw (x); | |
3072d30e | 4073 | add_insn_after (last, after, NULL); |
31d3e01c | 4074 | break; |
4075 | } | |
4076 | ||
4077 | return last; | |
15bbde2b | 4078 | } |
4079 | ||
4080 | /* Make an insn of code BARRIER | |
4081 | and output it after the insn AFTER. */ | |
4082 | ||
4083 | rtx | |
35cb5232 | 4084 | emit_barrier_after (rtx after) |
15bbde2b | 4085 | { |
19cb6b50 | 4086 | rtx insn = rtx_alloc (BARRIER); |
15bbde2b | 4087 | |
4088 | INSN_UID (insn) = cur_insn_uid++; | |
4089 | ||
3072d30e | 4090 | add_insn_after (insn, after, NULL); |
15bbde2b | 4091 | return insn; |
4092 | } | |
4093 | ||
4094 | /* Emit the label LABEL after the insn AFTER. */ | |
4095 | ||
4096 | rtx | |
35cb5232 | 4097 | emit_label_after (rtx label, rtx after) |
15bbde2b | 4098 | { |
4099 | /* This can be called twice for the same label | |
4100 | as a result of the confusion that follows a syntax error! | |
4101 | So make it harmless. */ | |
4102 | if (INSN_UID (label) == 0) | |
4103 | { | |
4104 | INSN_UID (label) = cur_insn_uid++; | |
3072d30e | 4105 | add_insn_after (label, after, NULL); |
15bbde2b | 4106 | } |
4107 | ||
4108 | return label; | |
4109 | } | |
4110 | ||
4111 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4112 | ||
4113 | rtx | |
ad4583d9 | 4114 | emit_note_after (enum insn_note subtype, rtx after) |
15bbde2b | 4115 | { |
19cb6b50 | 4116 | rtx note = rtx_alloc (NOTE); |
15bbde2b | 4117 | INSN_UID (note) = cur_insn_uid++; |
ad4583d9 | 4118 | NOTE_KIND (note) = subtype; |
ab87d1bc | 4119 | BLOCK_FOR_INSN (note) = NULL; |
60ad3b0e | 4120 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
3072d30e | 4121 | add_insn_after (note, after, NULL); |
15bbde2b | 4122 | return note; |
4123 | } | |
15bbde2b | 4124 | \f |
0891f67c | 4125 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
d321a68b | 4126 | rtx |
35cb5232 | 4127 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
d321a68b | 4128 | { |
3072d30e | 4129 | rtx last = emit_insn_after_noloc (pattern, after, NULL); |
d321a68b | 4130 | |
0891f67c | 4131 | if (pattern == NULL_RTX || !loc) |
ca154f3f | 4132 | return last; |
4133 | ||
31d3e01c | 4134 | after = NEXT_INSN (after); |
4135 | while (1) | |
4136 | { | |
0891f67c | 4137 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
13751393 | 4138 | INSN_LOCATOR (after) = loc; |
31d3e01c | 4139 | if (after == last) |
4140 | break; | |
4141 | after = NEXT_INSN (after); | |
4142 | } | |
d321a68b | 4143 | return last; |
4144 | } | |
4145 | ||
0891f67c | 4146 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4147 | rtx | |
4148 | emit_insn_after (rtx pattern, rtx after) | |
4149 | { | |
4150 | if (INSN_P (after)) | |
4151 | return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4152 | else | |
3072d30e | 4153 | return emit_insn_after_noloc (pattern, after, NULL); |
0891f67c | 4154 | } |
4155 | ||
4156 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
d321a68b | 4157 | rtx |
35cb5232 | 4158 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
d321a68b | 4159 | { |
0891f67c | 4160 | rtx last = emit_jump_insn_after_noloc (pattern, after); |
31d3e01c | 4161 | |
0891f67c | 4162 | if (pattern == NULL_RTX || !loc) |
ca154f3f | 4163 | return last; |
4164 | ||
31d3e01c | 4165 | after = NEXT_INSN (after); |
4166 | while (1) | |
4167 | { | |
0891f67c | 4168 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
13751393 | 4169 | INSN_LOCATOR (after) = loc; |
31d3e01c | 4170 | if (after == last) |
4171 | break; | |
4172 | after = NEXT_INSN (after); | |
4173 | } | |
d321a68b | 4174 | return last; |
4175 | } | |
4176 | ||
0891f67c | 4177 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4178 | rtx | |
4179 | emit_jump_insn_after (rtx pattern, rtx after) | |
4180 | { | |
4181 | if (INSN_P (after)) | |
4182 | return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4183 | else | |
4184 | return emit_jump_insn_after_noloc (pattern, after); | |
4185 | } | |
4186 | ||
4187 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
d321a68b | 4188 | rtx |
35cb5232 | 4189 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
d321a68b | 4190 | { |
0891f67c | 4191 | rtx last = emit_call_insn_after_noloc (pattern, after); |
31d3e01c | 4192 | |
0891f67c | 4193 | if (pattern == NULL_RTX || !loc) |
ca154f3f | 4194 | return last; |
4195 | ||
31d3e01c | 4196 | after = NEXT_INSN (after); |
4197 | while (1) | |
4198 | { | |
0891f67c | 4199 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
13751393 | 4200 | INSN_LOCATOR (after) = loc; |
31d3e01c | 4201 | if (after == last) |
4202 | break; | |
4203 | after = NEXT_INSN (after); | |
4204 | } | |
d321a68b | 4205 | return last; |
4206 | } | |
4207 | ||
0891f67c | 4208 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4209 | rtx | |
4210 | emit_call_insn_after (rtx pattern, rtx after) | |
4211 | { | |
4212 | if (INSN_P (after)) | |
4213 | return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4214 | else | |
4215 | return emit_call_insn_after_noloc (pattern, after); | |
4216 | } | |
4217 | ||
4218 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
d321a68b | 4219 | rtx |
35cb5232 | 4220 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
d321a68b | 4221 | { |
4222 | rtx first = PREV_INSN (before); | |
3072d30e | 4223 | rtx last = emit_insn_before_noloc (pattern, before, NULL); |
0891f67c | 4224 | |
4225 | if (pattern == NULL_RTX || !loc) | |
4226 | return last; | |
4227 | ||
4486418e | 4228 | if (!first) |
4229 | first = get_insns (); | |
4230 | else | |
4231 | first = NEXT_INSN (first); | |
0891f67c | 4232 | while (1) |
4233 | { | |
4234 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4235 | INSN_LOCATOR (first) = loc; | |
4236 | if (first == last) | |
4237 | break; | |
4238 | first = NEXT_INSN (first); | |
4239 | } | |
4240 | return last; | |
4241 | } | |
4242 | ||
4243 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4244 | rtx | |
4245 | emit_insn_before (rtx pattern, rtx before) | |
4246 | { | |
4247 | if (INSN_P (before)) | |
4248 | return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4249 | else | |
3072d30e | 4250 | return emit_insn_before_noloc (pattern, before, NULL); |
0891f67c | 4251 | } |
4252 | ||
4253 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4254 | rtx | |
4255 | emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4256 | { | |
4257 | rtx first = PREV_INSN (before); | |
4258 | rtx last = emit_jump_insn_before_noloc (pattern, before); | |
4259 | ||
4260 | if (pattern == NULL_RTX) | |
4261 | return last; | |
4262 | ||
4263 | first = NEXT_INSN (first); | |
4264 | while (1) | |
4265 | { | |
4266 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4267 | INSN_LOCATOR (first) = loc; | |
4268 | if (first == last) | |
4269 | break; | |
4270 | first = NEXT_INSN (first); | |
4271 | } | |
4272 | return last; | |
4273 | } | |
4274 | ||
4275 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4276 | rtx | |
4277 | emit_jump_insn_before (rtx pattern, rtx before) | |
4278 | { | |
4279 | if (INSN_P (before)) | |
4280 | return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4281 | else | |
4282 | return emit_jump_insn_before_noloc (pattern, before); | |
4283 | } | |
4284 | ||
4285 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4286 | rtx | |
4287 | emit_call_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4288 | { | |
4289 | rtx first = PREV_INSN (before); | |
4290 | rtx last = emit_call_insn_before_noloc (pattern, before); | |
d321a68b | 4291 | |
ca154f3f | 4292 | if (pattern == NULL_RTX) |
4293 | return last; | |
4294 | ||
31d3e01c | 4295 | first = NEXT_INSN (first); |
4296 | while (1) | |
4297 | { | |
0891f67c | 4298 | if (active_insn_p (first) && !INSN_LOCATOR (first)) |
13751393 | 4299 | INSN_LOCATOR (first) = loc; |
31d3e01c | 4300 | if (first == last) |
4301 | break; | |
4302 | first = NEXT_INSN (first); | |
4303 | } | |
d321a68b | 4304 | return last; |
4305 | } | |
0891f67c | 4306 | |
4307 | /* like emit_call_insn_before_noloc, | |
4308 | but set insn_locator according to before. */ | |
4309 | rtx | |
4310 | emit_call_insn_before (rtx pattern, rtx before) | |
4311 | { | |
4312 | if (INSN_P (before)) | |
4313 | return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4314 | else | |
4315 | return emit_call_insn_before_noloc (pattern, before); | |
4316 | } | |
d321a68b | 4317 | \f |
31d3e01c | 4318 | /* Take X and emit it at the end of the doubly-linked |
4319 | INSN list. | |
15bbde2b | 4320 | |
4321 | Returns the last insn emitted. */ | |
4322 | ||
4323 | rtx | |
35cb5232 | 4324 | emit_insn (rtx x) |
15bbde2b | 4325 | { |
31d3e01c | 4326 | rtx last = last_insn; |
4327 | rtx insn; | |
15bbde2b | 4328 | |
31d3e01c | 4329 | if (x == NULL_RTX) |
4330 | return last; | |
15bbde2b | 4331 | |
31d3e01c | 4332 | switch (GET_CODE (x)) |
4333 | { | |
4334 | case INSN: | |
4335 | case JUMP_INSN: | |
4336 | case CALL_INSN: | |
4337 | case CODE_LABEL: | |
4338 | case BARRIER: | |
4339 | case NOTE: | |
4340 | insn = x; | |
4341 | while (insn) | |
15bbde2b | 4342 | { |
31d3e01c | 4343 | rtx next = NEXT_INSN (insn); |
15bbde2b | 4344 | add_insn (insn); |
31d3e01c | 4345 | last = insn; |
4346 | insn = next; | |
15bbde2b | 4347 | } |
31d3e01c | 4348 | break; |
15bbde2b | 4349 | |
31d3e01c | 4350 | #ifdef ENABLE_RTL_CHECKING |
4351 | case SEQUENCE: | |
611234b4 | 4352 | gcc_unreachable (); |
31d3e01c | 4353 | break; |
4354 | #endif | |
15bbde2b | 4355 | |
31d3e01c | 4356 | default: |
4357 | last = make_insn_raw (x); | |
4358 | add_insn (last); | |
4359 | break; | |
15bbde2b | 4360 | } |
4361 | ||
4362 | return last; | |
4363 | } | |
4364 | ||
31d3e01c | 4365 | /* Make an insn of code JUMP_INSN with pattern X |
4366 | and add it to the end of the doubly-linked list. */ | |
15bbde2b | 4367 | |
4368 | rtx | |
35cb5232 | 4369 | emit_jump_insn (rtx x) |
15bbde2b | 4370 | { |
d90b3d04 | 4371 | rtx last = NULL_RTX, insn; |
15bbde2b | 4372 | |
31d3e01c | 4373 | switch (GET_CODE (x)) |
15bbde2b | 4374 | { |
31d3e01c | 4375 | case INSN: |
4376 | case JUMP_INSN: | |
4377 | case CALL_INSN: | |
4378 | case CODE_LABEL: | |
4379 | case BARRIER: | |
4380 | case NOTE: | |
4381 | insn = x; | |
4382 | while (insn) | |
4383 | { | |
4384 | rtx next = NEXT_INSN (insn); | |
4385 | add_insn (insn); | |
4386 | last = insn; | |
4387 | insn = next; | |
4388 | } | |
4389 | break; | |
b36b07d8 | 4390 | |
31d3e01c | 4391 | #ifdef ENABLE_RTL_CHECKING |
4392 | case SEQUENCE: | |
611234b4 | 4393 | gcc_unreachable (); |
31d3e01c | 4394 | break; |
4395 | #endif | |
b36b07d8 | 4396 | |
31d3e01c | 4397 | default: |
4398 | last = make_jump_insn_raw (x); | |
4399 | add_insn (last); | |
4400 | break; | |
9dda7915 | 4401 | } |
b36b07d8 | 4402 | |
4403 | return last; | |
4404 | } | |
4405 | ||
31d3e01c | 4406 | /* Make an insn of code CALL_INSN with pattern X |
15bbde2b | 4407 | and add it to the end of the doubly-linked list. */ |
4408 | ||
4409 | rtx | |
35cb5232 | 4410 | emit_call_insn (rtx x) |
15bbde2b | 4411 | { |
31d3e01c | 4412 | rtx insn; |
4413 | ||
4414 | switch (GET_CODE (x)) | |
15bbde2b | 4415 | { |
31d3e01c | 4416 | case INSN: |
4417 | case JUMP_INSN: | |
4418 | case CALL_INSN: | |
4419 | case CODE_LABEL: | |
4420 | case BARRIER: | |
4421 | case NOTE: | |
4422 | insn = emit_insn (x); | |
4423 | break; | |
15bbde2b | 4424 | |
31d3e01c | 4425 | #ifdef ENABLE_RTL_CHECKING |
4426 | case SEQUENCE: | |
611234b4 | 4427 | gcc_unreachable (); |
31d3e01c | 4428 | break; |
4429 | #endif | |
15bbde2b | 4430 | |
31d3e01c | 4431 | default: |
4432 | insn = make_call_insn_raw (x); | |
15bbde2b | 4433 | add_insn (insn); |
31d3e01c | 4434 | break; |
15bbde2b | 4435 | } |
31d3e01c | 4436 | |
4437 | return insn; | |
15bbde2b | 4438 | } |
4439 | ||
4440 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4441 | ||
4442 | rtx | |
35cb5232 | 4443 | emit_label (rtx label) |
15bbde2b | 4444 | { |
4445 | /* This can be called twice for the same label | |
4446 | as a result of the confusion that follows a syntax error! | |
4447 | So make it harmless. */ | |
4448 | if (INSN_UID (label) == 0) | |
4449 | { | |
4450 | INSN_UID (label) = cur_insn_uid++; | |
4451 | add_insn (label); | |
4452 | } | |
4453 | return label; | |
4454 | } | |
4455 | ||
4456 | /* Make an insn of code BARRIER | |
4457 | and add it to the end of the doubly-linked list. */ | |
4458 | ||
4459 | rtx | |
35cb5232 | 4460 | emit_barrier (void) |
15bbde2b | 4461 | { |
19cb6b50 | 4462 | rtx barrier = rtx_alloc (BARRIER); |
15bbde2b | 4463 | INSN_UID (barrier) = cur_insn_uid++; |
4464 | add_insn (barrier); | |
4465 | return barrier; | |
4466 | } | |
4467 | ||
2f57e3d9 | 4468 | /* Emit a copy of note ORIG. */ |
35cb5232 | 4469 | |
2f57e3d9 | 4470 | rtx |
4471 | emit_note_copy (rtx orig) | |
4472 | { | |
4473 | rtx note; | |
4474 | ||
2f57e3d9 | 4475 | note = rtx_alloc (NOTE); |
4476 | ||
4477 | INSN_UID (note) = cur_insn_uid++; | |
4478 | NOTE_DATA (note) = NOTE_DATA (orig); | |
ad4583d9 | 4479 | NOTE_KIND (note) = NOTE_KIND (orig); |
2f57e3d9 | 4480 | BLOCK_FOR_INSN (note) = NULL; |
4481 | add_insn (note); | |
4482 | ||
31b97e8f | 4483 | return note; |
15bbde2b | 4484 | } |
4485 | ||
31b97e8f | 4486 | /* Make an insn of code NOTE or type NOTE_NO |
4487 | and add it to the end of the doubly-linked list. */ | |
15bbde2b | 4488 | |
4489 | rtx | |
ad4583d9 | 4490 | emit_note (enum insn_note kind) |
15bbde2b | 4491 | { |
19cb6b50 | 4492 | rtx note; |
15bbde2b | 4493 | |
15bbde2b | 4494 | note = rtx_alloc (NOTE); |
4495 | INSN_UID (note) = cur_insn_uid++; | |
ad4583d9 | 4496 | NOTE_KIND (note) = kind; |
6c7786cb | 4497 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ab87d1bc | 4498 | BLOCK_FOR_INSN (note) = NULL; |
15bbde2b | 4499 | add_insn (note); |
4500 | return note; | |
4501 | } | |
4502 | ||
15bbde2b | 4503 | /* Cause next statement to emit a line note even if the line number |
bccd9980 | 4504 | has not changed. */ |
15bbde2b | 4505 | |
4506 | void | |
35cb5232 | 4507 | force_next_line_note (void) |
15bbde2b | 4508 | { |
7bd3dcc4 | 4509 | #ifdef USE_MAPPED_LOCATION |
4510 | last_location = -1; | |
4511 | #else | |
0a3b3d88 | 4512 | last_location.line = -1; |
7bd3dcc4 | 4513 | #endif |
15bbde2b | 4514 | } |
f1934a33 | 4515 | |
4516 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
6312a35e | 4517 | note of this type already exists, remove it first. */ |
f1934a33 | 4518 | |
c080d8f0 | 4519 | rtx |
35cb5232 | 4520 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
f1934a33 | 4521 | { |
4522 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3072d30e | 4523 | rtx new_note = NULL; |
f1934a33 | 4524 | |
7e6224ab | 4525 | switch (kind) |
4526 | { | |
4527 | case REG_EQUAL: | |
4528 | case REG_EQUIV: | |
4529 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
4530 | has multiple sets (some callers assume single_set | |
4531 | means the insn only has one set, when in fact it | |
4532 | means the insn only has one * useful * set). */ | |
4533 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
4534 | { | |
611234b4 | 4535 | gcc_assert (!note); |
7e6224ab | 4536 | return NULL_RTX; |
4537 | } | |
4538 | ||
4539 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
4540 | It serves no useful purpose and breaks eliminate_regs. */ | |
4541 | if (GET_CODE (datum) == ASM_OPERANDS) | |
4542 | return NULL_RTX; | |
3072d30e | 4543 | |
4544 | if (note) | |
4545 | { | |
4546 | XEXP (note, 0) = datum; | |
4547 | df_notes_rescan (insn); | |
4548 | return note; | |
4549 | } | |
7e6224ab | 4550 | break; |
4551 | ||
4552 | default: | |
3072d30e | 4553 | if (note) |
4554 | { | |
4555 | XEXP (note, 0) = datum; | |
4556 | return note; | |
4557 | } | |
7e6224ab | 4558 | break; |
4559 | } | |
c080d8f0 | 4560 | |
3072d30e | 4561 | new_note = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); |
4562 | REG_NOTES (insn) = new_note; | |
4563 | ||
4564 | switch (kind) | |
c080d8f0 | 4565 | { |
3072d30e | 4566 | case REG_EQUAL: |
4567 | case REG_EQUIV: | |
4568 | df_notes_rescan (insn); | |
4569 | break; | |
4570 | default: | |
4571 | break; | |
c080d8f0 | 4572 | } |
f1934a33 | 4573 | |
c080d8f0 | 4574 | return REG_NOTES (insn); |
f1934a33 | 4575 | } |
15bbde2b | 4576 | \f |
4577 | /* Return an indication of which type of insn should have X as a body. | |
4578 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
4579 | ||
9b69f75b | 4580 | static enum rtx_code |
35cb5232 | 4581 | classify_insn (rtx x) |
15bbde2b | 4582 | { |
6d7dc5b9 | 4583 | if (LABEL_P (x)) |
15bbde2b | 4584 | return CODE_LABEL; |
4585 | if (GET_CODE (x) == CALL) | |
4586 | return CALL_INSN; | |
4587 | if (GET_CODE (x) == RETURN) | |
4588 | return JUMP_INSN; | |
4589 | if (GET_CODE (x) == SET) | |
4590 | { | |
4591 | if (SET_DEST (x) == pc_rtx) | |
4592 | return JUMP_INSN; | |
4593 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
4594 | return CALL_INSN; | |
4595 | else | |
4596 | return INSN; | |
4597 | } | |
4598 | if (GET_CODE (x) == PARALLEL) | |
4599 | { | |
19cb6b50 | 4600 | int j; |
15bbde2b | 4601 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
4602 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
4603 | return CALL_INSN; | |
4604 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4605 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
4606 | return JUMP_INSN; | |
4607 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4608 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
4609 | return CALL_INSN; | |
4610 | } | |
4611 | return INSN; | |
4612 | } | |
4613 | ||
4614 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
4615 | If X is a label, it is simply added into the insn chain. */ | |
4616 | ||
4617 | rtx | |
35cb5232 | 4618 | emit (rtx x) |
15bbde2b | 4619 | { |
4620 | enum rtx_code code = classify_insn (x); | |
4621 | ||
611234b4 | 4622 | switch (code) |
15bbde2b | 4623 | { |
611234b4 | 4624 | case CODE_LABEL: |
4625 | return emit_label (x); | |
4626 | case INSN: | |
4627 | return emit_insn (x); | |
4628 | case JUMP_INSN: | |
4629 | { | |
4630 | rtx insn = emit_jump_insn (x); | |
4631 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) | |
4632 | return emit_barrier (); | |
4633 | return insn; | |
4634 | } | |
4635 | case CALL_INSN: | |
4636 | return emit_call_insn (x); | |
4637 | default: | |
4638 | gcc_unreachable (); | |
15bbde2b | 4639 | } |
15bbde2b | 4640 | } |
4641 | \f | |
1f3233d1 | 4642 | /* Space for free sequence stack entries. */ |
7035b2ab | 4643 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
1f3233d1 | 4644 | |
735f4358 | 4645 | /* Begin emitting insns to a sequence. If this sequence will contain |
4646 | something that might cause the compiler to pop arguments to function | |
4647 | calls (because those pops have previously been deferred; see | |
4648 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
4649 | before calling this function. That will ensure that the deferred | |
4650 | pops are not accidentally emitted in the middle of this sequence. */ | |
15bbde2b | 4651 | |
4652 | void | |
35cb5232 | 4653 | start_sequence (void) |
15bbde2b | 4654 | { |
4655 | struct sequence_stack *tem; | |
4656 | ||
1f3233d1 | 4657 | if (free_sequence_stack != NULL) |
4658 | { | |
4659 | tem = free_sequence_stack; | |
4660 | free_sequence_stack = tem->next; | |
4661 | } | |
4662 | else | |
f0af5a88 | 4663 | tem = ggc_alloc (sizeof (struct sequence_stack)); |
15bbde2b | 4664 | |
0a893c29 | 4665 | tem->next = seq_stack; |
15bbde2b | 4666 | tem->first = first_insn; |
4667 | tem->last = last_insn; | |
4668 | ||
0a893c29 | 4669 | seq_stack = tem; |
15bbde2b | 4670 | |
4671 | first_insn = 0; | |
4672 | last_insn = 0; | |
4673 | } | |
4674 | ||
b49854c6 | 4675 | /* Set up the insn chain starting with FIRST as the current sequence, |
4676 | saving the previously current one. See the documentation for | |
4677 | start_sequence for more information about how to use this function. */ | |
15bbde2b | 4678 | |
4679 | void | |
35cb5232 | 4680 | push_to_sequence (rtx first) |
15bbde2b | 4681 | { |
4682 | rtx last; | |
4683 | ||
4684 | start_sequence (); | |
4685 | ||
4686 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
4687 | ||
4688 | first_insn = first; | |
4689 | last_insn = last; | |
4690 | } | |
4691 | ||
28bf151d | 4692 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
4693 | looping through the list. */ | |
4694 | ||
4695 | void | |
4696 | push_to_sequence2 (rtx first, rtx last) | |
4697 | { | |
4698 | start_sequence (); | |
4699 | ||
4700 | first_insn = first; | |
4701 | last_insn = last; | |
4702 | } | |
4703 | ||
ab74c92f | 4704 | /* Set up the outer-level insn chain |
4705 | as the current sequence, saving the previously current one. */ | |
4706 | ||
4707 | void | |
35cb5232 | 4708 | push_topmost_sequence (void) |
ab74c92f | 4709 | { |
2041cfd9 | 4710 | struct sequence_stack *stack, *top = NULL; |
ab74c92f | 4711 | |
4712 | start_sequence (); | |
4713 | ||
0a893c29 | 4714 | for (stack = seq_stack; stack; stack = stack->next) |
ab74c92f | 4715 | top = stack; |
4716 | ||
4717 | first_insn = top->first; | |
4718 | last_insn = top->last; | |
4719 | } | |
4720 | ||
4721 | /* After emitting to the outer-level insn chain, update the outer-level | |
4722 | insn chain, and restore the previous saved state. */ | |
4723 | ||
4724 | void | |
35cb5232 | 4725 | pop_topmost_sequence (void) |
ab74c92f | 4726 | { |
2041cfd9 | 4727 | struct sequence_stack *stack, *top = NULL; |
ab74c92f | 4728 | |
0a893c29 | 4729 | for (stack = seq_stack; stack; stack = stack->next) |
ab74c92f | 4730 | top = stack; |
4731 | ||
4732 | top->first = first_insn; | |
4733 | top->last = last_insn; | |
4734 | ||
4735 | end_sequence (); | |
4736 | } | |
4737 | ||
15bbde2b | 4738 | /* After emitting to a sequence, restore previous saved state. |
4739 | ||
b49854c6 | 4740 | To get the contents of the sequence just made, you must call |
31d3e01c | 4741 | `get_insns' *before* calling here. |
b49854c6 | 4742 | |
4743 | If the compiler might have deferred popping arguments while | |
4744 | generating this sequence, and this sequence will not be immediately | |
4745 | inserted into the instruction stream, use do_pending_stack_adjust | |
31d3e01c | 4746 | before calling get_insns. That will ensure that the deferred |
b49854c6 | 4747 | pops are inserted into this sequence, and not into some random |
4748 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
4749 | information about deferred popping of arguments. */ | |
15bbde2b | 4750 | |
4751 | void | |
35cb5232 | 4752 | end_sequence (void) |
15bbde2b | 4753 | { |
0a893c29 | 4754 | struct sequence_stack *tem = seq_stack; |
15bbde2b | 4755 | |
4756 | first_insn = tem->first; | |
4757 | last_insn = tem->last; | |
0a893c29 | 4758 | seq_stack = tem->next; |
15bbde2b | 4759 | |
1f3233d1 | 4760 | memset (tem, 0, sizeof (*tem)); |
4761 | tem->next = free_sequence_stack; | |
4762 | free_sequence_stack = tem; | |
15bbde2b | 4763 | } |
4764 | ||
4765 | /* Return 1 if currently emitting into a sequence. */ | |
4766 | ||
4767 | int | |
35cb5232 | 4768 | in_sequence_p (void) |
15bbde2b | 4769 | { |
0a893c29 | 4770 | return seq_stack != 0; |
15bbde2b | 4771 | } |
15bbde2b | 4772 | \f |
02ebfa52 | 4773 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
4774 | ||
2f3874ce | 4775 | static void |
35cb5232 | 4776 | init_virtual_regs (struct emit_status *es) |
02ebfa52 | 4777 | { |
0a893c29 | 4778 | rtx *ptr = es->x_regno_reg_rtx; |
4779 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
4780 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
4781 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
4782 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
4783 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
4784 | } | |
4785 | ||
928d57e3 | 4786 | \f |
4787 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
4788 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
4789 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
4790 | static int copy_insn_n_scratches; | |
4791 | ||
4792 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
4793 | copied an ASM_OPERANDS. | |
4794 | In that case, it is the original input-operand vector. */ | |
4795 | static rtvec orig_asm_operands_vector; | |
4796 | ||
4797 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
4798 | copied an ASM_OPERANDS. | |
4799 | In that case, it is the copied input-operand vector. */ | |
4800 | static rtvec copy_asm_operands_vector; | |
4801 | ||
4802 | /* Likewise for the constraints vector. */ | |
4803 | static rtvec orig_asm_constraints_vector; | |
4804 | static rtvec copy_asm_constraints_vector; | |
4805 | ||
4806 | /* Recursively create a new copy of an rtx for copy_insn. | |
4807 | This function differs from copy_rtx in that it handles SCRATCHes and | |
4808 | ASM_OPERANDs properly. | |
4809 | Normally, this function is not used directly; use copy_insn as front end. | |
4810 | However, you could first copy an insn pattern with copy_insn and then use | |
4811 | this function afterwards to properly copy any REG_NOTEs containing | |
4812 | SCRATCHes. */ | |
4813 | ||
4814 | rtx | |
35cb5232 | 4815 | copy_insn_1 (rtx orig) |
928d57e3 | 4816 | { |
19cb6b50 | 4817 | rtx copy; |
4818 | int i, j; | |
4819 | RTX_CODE code; | |
4820 | const char *format_ptr; | |
928d57e3 | 4821 | |
4822 | code = GET_CODE (orig); | |
4823 | ||
4824 | switch (code) | |
4825 | { | |
4826 | case REG: | |
928d57e3 | 4827 | case CONST_INT: |
4828 | case CONST_DOUBLE: | |
886cfd4f | 4829 | case CONST_VECTOR: |
928d57e3 | 4830 | case SYMBOL_REF: |
4831 | case CODE_LABEL: | |
4832 | case PC: | |
4833 | case CC0: | |
928d57e3 | 4834 | return orig; |
c09425a0 | 4835 | case CLOBBER: |
4836 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER) | |
4837 | return orig; | |
4838 | break; | |
928d57e3 | 4839 | |
4840 | case SCRATCH: | |
4841 | for (i = 0; i < copy_insn_n_scratches; i++) | |
4842 | if (copy_insn_scratch_in[i] == orig) | |
4843 | return copy_insn_scratch_out[i]; | |
4844 | break; | |
4845 | ||
4846 | case CONST: | |
3072d30e | 4847 | if (shared_const_p (orig)) |
928d57e3 | 4848 | return orig; |
4849 | break; | |
d823ba47 | 4850 | |
928d57e3 | 4851 | /* A MEM with a constant address is not sharable. The problem is that |
4852 | the constant address may need to be reloaded. If the mem is shared, | |
4853 | then reloading one copy of this mem will cause all copies to appear | |
4854 | to have been reloaded. */ | |
4855 | ||
4856 | default: | |
4857 | break; | |
4858 | } | |
4859 | ||
f2d0e9f1 | 4860 | /* Copy the various flags, fields, and other information. We assume |
4861 | that all fields need copying, and then clear the fields that should | |
928d57e3 | 4862 | not be copied. That is the sensible default behavior, and forces |
4863 | us to explicitly document why we are *not* copying a flag. */ | |
f2d0e9f1 | 4864 | copy = shallow_copy_rtx (orig); |
928d57e3 | 4865 | |
4866 | /* We do not copy the USED flag, which is used as a mark bit during | |
4867 | walks over the RTL. */ | |
7c25cb91 | 4868 | RTX_FLAG (copy, used) = 0; |
928d57e3 | 4869 | |
4870 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
6720e96c | 4871 | if (INSN_P (orig)) |
928d57e3 | 4872 | { |
7c25cb91 | 4873 | RTX_FLAG (copy, jump) = 0; |
4874 | RTX_FLAG (copy, call) = 0; | |
4875 | RTX_FLAG (copy, frame_related) = 0; | |
928d57e3 | 4876 | } |
d823ba47 | 4877 | |
928d57e3 | 4878 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
4879 | ||
4880 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
f2d0e9f1 | 4881 | switch (*format_ptr++) |
4882 | { | |
4883 | case 'e': | |
4884 | if (XEXP (orig, i) != NULL) | |
4885 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
4886 | break; | |
928d57e3 | 4887 | |
f2d0e9f1 | 4888 | case 'E': |
4889 | case 'V': | |
4890 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
4891 | XVEC (copy, i) = copy_asm_constraints_vector; | |
4892 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
4893 | XVEC (copy, i) = copy_asm_operands_vector; | |
4894 | else if (XVEC (orig, i) != NULL) | |
4895 | { | |
4896 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
4897 | for (j = 0; j < XVECLEN (copy, i); j++) | |
4898 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
4899 | } | |
4900 | break; | |
928d57e3 | 4901 | |
f2d0e9f1 | 4902 | case 't': |
4903 | case 'w': | |
4904 | case 'i': | |
4905 | case 's': | |
4906 | case 'S': | |
4907 | case 'u': | |
4908 | case '0': | |
4909 | /* These are left unchanged. */ | |
4910 | break; | |
928d57e3 | 4911 | |
f2d0e9f1 | 4912 | default: |
4913 | gcc_unreachable (); | |
4914 | } | |
928d57e3 | 4915 | |
4916 | if (code == SCRATCH) | |
4917 | { | |
4918 | i = copy_insn_n_scratches++; | |
611234b4 | 4919 | gcc_assert (i < MAX_RECOG_OPERANDS); |
928d57e3 | 4920 | copy_insn_scratch_in[i] = orig; |
4921 | copy_insn_scratch_out[i] = copy; | |
4922 | } | |
4923 | else if (code == ASM_OPERANDS) | |
4924 | { | |
d91f2122 | 4925 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
4926 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
4927 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
4928 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
928d57e3 | 4929 | } |
4930 | ||
4931 | return copy; | |
4932 | } | |
4933 | ||
4934 | /* Create a new copy of an rtx. | |
4935 | This function differs from copy_rtx in that it handles SCRATCHes and | |
4936 | ASM_OPERANDs properly. | |
4937 | INSN doesn't really have to be a full INSN; it could be just the | |
4938 | pattern. */ | |
4939 | rtx | |
35cb5232 | 4940 | copy_insn (rtx insn) |
928d57e3 | 4941 | { |
4942 | copy_insn_n_scratches = 0; | |
4943 | orig_asm_operands_vector = 0; | |
4944 | orig_asm_constraints_vector = 0; | |
4945 | copy_asm_operands_vector = 0; | |
4946 | copy_asm_constraints_vector = 0; | |
4947 | return copy_insn_1 (insn); | |
4948 | } | |
02ebfa52 | 4949 | |
15bbde2b | 4950 | /* Initialize data structures and variables in this file |
4951 | before generating rtl for each function. */ | |
4952 | ||
4953 | void | |
35cb5232 | 4954 | init_emit (void) |
15bbde2b | 4955 | { |
08513b52 | 4956 | struct function *f = cfun; |
15bbde2b | 4957 | |
f0af5a88 | 4958 | f->emit = ggc_alloc (sizeof (struct emit_status)); |
15bbde2b | 4959 | first_insn = NULL; |
4960 | last_insn = NULL; | |
4961 | cur_insn_uid = 1; | |
4962 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
7bd3dcc4 | 4963 | last_location = UNKNOWN_LOCATION; |
15bbde2b | 4964 | first_label_num = label_num; |
0a893c29 | 4965 | seq_stack = NULL; |
15bbde2b | 4966 | |
15bbde2b | 4967 | /* Init the tables that describe all the pseudo regs. */ |
4968 | ||
e61a0a7f | 4969 | f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
15bbde2b | 4970 | |
0a893c29 | 4971 | f->emit->regno_pointer_align |
f0af5a88 | 4972 | = ggc_alloc_cleared (f->emit->regno_pointer_align_length |
4973 | * sizeof (unsigned char)); | |
d4c332ff | 4974 | |
d823ba47 | 4975 | regno_reg_rtx |
f0af5a88 | 4976 | = ggc_alloc (f->emit->regno_pointer_align_length * sizeof (rtx)); |
fcdc122e | 4977 | |
936082bb | 4978 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
90295bd2 | 4979 | memcpy (regno_reg_rtx, |
4980 | static_regno_reg_rtx, | |
4981 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); | |
936082bb | 4982 | |
15bbde2b | 4983 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
0a893c29 | 4984 | init_virtual_regs (f->emit); |
888e0d33 | 4985 | |
4986 | /* Indicate that the virtual registers and stack locations are | |
4987 | all pointers. */ | |
e61a0a7f | 4988 | REG_POINTER (stack_pointer_rtx) = 1; |
4989 | REG_POINTER (frame_pointer_rtx) = 1; | |
4990 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
4991 | REG_POINTER (arg_pointer_rtx) = 1; | |
888e0d33 | 4992 | |
e61a0a7f | 4993 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
4994 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
4995 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
4996 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
4997 | REG_POINTER (virtual_cfa_rtx) = 1; | |
89525da0 | 4998 | |
d4c332ff | 4999 | #ifdef STACK_BOUNDARY |
80909c64 | 5000 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5001 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5002 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5003 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5004 | ||
5005 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5006 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5007 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5008 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5009 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
d4c332ff | 5010 | #endif |
5011 | ||
89525da0 | 5012 | #ifdef INIT_EXPANDERS |
5013 | INIT_EXPANDERS; | |
5014 | #endif | |
15bbde2b | 5015 | } |
5016 | ||
6e68dcb2 | 5017 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
886cfd4f | 5018 | |
5019 | static rtx | |
6e68dcb2 | 5020 | gen_const_vector (enum machine_mode mode, int constant) |
886cfd4f | 5021 | { |
5022 | rtx tem; | |
5023 | rtvec v; | |
5024 | int units, i; | |
5025 | enum machine_mode inner; | |
5026 | ||
5027 | units = GET_MODE_NUNITS (mode); | |
5028 | inner = GET_MODE_INNER (mode); | |
5029 | ||
069b07bf | 5030 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5031 | ||
886cfd4f | 5032 | v = rtvec_alloc (units); |
5033 | ||
6e68dcb2 | 5034 | /* We need to call this function after we set the scalar const_tiny_rtx |
5035 | entries. */ | |
5036 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
886cfd4f | 5037 | |
5038 | for (i = 0; i < units; ++i) | |
6e68dcb2 | 5039 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
886cfd4f | 5040 | |
9426b612 | 5041 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
886cfd4f | 5042 | return tem; |
5043 | } | |
5044 | ||
9426b612 | 5045 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
6e68dcb2 | 5046 | all elements are zero, and the one vector when all elements are one. */ |
9426b612 | 5047 | rtx |
35cb5232 | 5048 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
9426b612 | 5049 | { |
6e68dcb2 | 5050 | enum machine_mode inner = GET_MODE_INNER (mode); |
5051 | int nunits = GET_MODE_NUNITS (mode); | |
5052 | rtx x; | |
9426b612 | 5053 | int i; |
5054 | ||
6e68dcb2 | 5055 | /* Check to see if all of the elements have the same value. */ |
5056 | x = RTVEC_ELT (v, nunits - 1); | |
5057 | for (i = nunits - 2; i >= 0; i--) | |
5058 | if (RTVEC_ELT (v, i) != x) | |
5059 | break; | |
5060 | ||
5061 | /* If the values are all the same, check to see if we can use one of the | |
5062 | standard constant vectors. */ | |
5063 | if (i == -1) | |
5064 | { | |
5065 | if (x == CONST0_RTX (inner)) | |
5066 | return CONST0_RTX (mode); | |
5067 | else if (x == CONST1_RTX (inner)) | |
5068 | return CONST1_RTX (mode); | |
5069 | } | |
5070 | ||
5071 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
9426b612 | 5072 | } |
5073 | ||
15bbde2b | 5074 | /* Create some permanent unique rtl objects shared between all functions. |
5075 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
5076 | ||
5077 | void | |
35cb5232 | 5078 | init_emit_once (int line_numbers) |
15bbde2b | 5079 | { |
5080 | int i; | |
5081 | enum machine_mode mode; | |
9e042f31 | 5082 | enum machine_mode double_mode; |
15bbde2b | 5083 | |
7981458e | 5084 | /* We need reg_raw_mode, so initialize the modes now. */ |
c235b58a | 5085 | init_reg_modes_once (); |
5086 | ||
2ff23ed0 | 5087 | /* Initialize the CONST_INT, CONST_DOUBLE, and memory attribute hash |
5088 | tables. */ | |
573aba85 | 5089 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5090 | const_int_htab_eq, NULL); | |
c6259b83 | 5091 | |
573aba85 | 5092 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5093 | const_double_htab_eq, NULL); | |
2ff23ed0 | 5094 | |
573aba85 | 5095 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5096 | mem_attrs_htab_eq, NULL); | |
ca74b940 | 5097 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5098 | reg_attrs_htab_eq, NULL); | |
77695070 | 5099 | |
15bbde2b | 5100 | no_line_numbers = ! line_numbers; |
5101 | ||
71d7daa2 | 5102 | /* Compute the word and byte modes. */ |
5103 | ||
5104 | byte_mode = VOIDmode; | |
5105 | word_mode = VOIDmode; | |
5106 | double_mode = VOIDmode; | |
5107 | ||
069b07bf | 5108 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5109 | mode != VOIDmode; | |
71d7daa2 | 5110 | mode = GET_MODE_WIDER_MODE (mode)) |
5111 | { | |
5112 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5113 | && byte_mode == VOIDmode) | |
5114 | byte_mode = mode; | |
5115 | ||
5116 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5117 | && word_mode == VOIDmode) | |
5118 | word_mode = mode; | |
5119 | } | |
5120 | ||
069b07bf | 5121 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5122 | mode != VOIDmode; | |
71d7daa2 | 5123 | mode = GET_MODE_WIDER_MODE (mode)) |
5124 | { | |
5125 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5126 | && double_mode == VOIDmode) | |
5127 | double_mode = mode; | |
5128 | } | |
5129 | ||
5130 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5131 | ||
57c097d5 | 5132 | /* Assign register numbers to the globally defined register rtx. |
5133 | This must be done at runtime because the register number field | |
5134 | is in a union and some compilers can't initialize unions. */ | |
5135 | ||
27a9551b | 5136 | pc_rtx = gen_rtx_PC (VOIDmode); |
5137 | cc0_rtx = gen_rtx_CC0 (VOIDmode); | |
22cf44bc | 5138 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
5139 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
57c097d5 | 5140 | if (hard_frame_pointer_rtx == 0) |
d823ba47 | 5141 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, |
22cf44bc | 5142 | HARD_FRAME_POINTER_REGNUM); |
57c097d5 | 5143 | if (arg_pointer_rtx == 0) |
22cf44bc | 5144 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); |
d823ba47 | 5145 | virtual_incoming_args_rtx = |
22cf44bc | 5146 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); |
d823ba47 | 5147 | virtual_stack_vars_rtx = |
22cf44bc | 5148 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); |
d823ba47 | 5149 | virtual_stack_dynamic_rtx = |
22cf44bc | 5150 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); |
d823ba47 | 5151 | virtual_outgoing_args_rtx = |
5152 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
22cf44bc | 5153 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); |
57c097d5 | 5154 | |
90295bd2 | 5155 | /* Initialize RTL for commonly used hard registers. These are |
5156 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5157 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5158 | static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); | |
5159 | ||
57c097d5 | 5160 | #ifdef INIT_EXPANDERS |
ab5beff9 | 5161 | /* This is to initialize {init|mark|free}_machine_status before the first |
5162 | call to push_function_context_to. This is needed by the Chill front | |
3fb1e43b | 5163 | end which calls push_function_context_to before the first call to |
57c097d5 | 5164 | init_function_start. */ |
5165 | INIT_EXPANDERS; | |
5166 | #endif | |
5167 | ||
15bbde2b | 5168 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5169 | ||
8fd5918e | 5170 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
7014838c | 5171 | tries to use these variables. */ |
15bbde2b | 5172 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
d823ba47 | 5173 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
a717d5b4 | 5174 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
15bbde2b | 5175 | |
1a60f06a | 5176 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5177 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
57c097d5 | 5178 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
1a60f06a | 5179 | else |
3ad7bb1c | 5180 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
15bbde2b | 5181 | |
2ff23ed0 | 5182 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5183 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5184 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
8918c507 | 5185 | REAL_VALUE_FROM_INT (dconst3, 3, 0, double_mode); |
5186 | REAL_VALUE_FROM_INT (dconst10, 10, 0, double_mode); | |
2ff23ed0 | 5187 | REAL_VALUE_FROM_INT (dconstm1, -1, -1, double_mode); |
77e89269 | 5188 | REAL_VALUE_FROM_INT (dconstm2, -2, -1, double_mode); |
5189 | ||
5190 | dconsthalf = dconst1; | |
9d96125b | 5191 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
15bbde2b | 5192 | |
8918c507 | 5193 | real_arithmetic (&dconstthird, RDIV_EXPR, &dconst1, &dconst3); |
5194 | ||
79082756 | 5195 | /* Initialize mathematical constants for constant folding builtins. |
5196 | These constants need to be given to at least 160 bits precision. */ | |
2e7ca27b | 5197 | real_from_string (&dconstsqrt2, |
5198 | "1.4142135623730950488016887242096980785696718753769480731766797379907"); | |
79082756 | 5199 | real_from_string (&dconste, |
5200 | "2.7182818284590452353602874713526624977572470936999595749669676277241"); | |
5201 | ||
8918c507 | 5202 | for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++) |
15bbde2b | 5203 | { |
badfe841 | 5204 | REAL_VALUE_TYPE *r = |
5205 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); | |
5206 | ||
069b07bf | 5207 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5208 | mode != VOIDmode; | |
5209 | mode = GET_MODE_WIDER_MODE (mode)) | |
5210 | const_tiny_rtx[i][(int) mode] = | |
5211 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5212 | ||
5213 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5214 | mode != VOIDmode; | |
15bbde2b | 5215 | mode = GET_MODE_WIDER_MODE (mode)) |
2ff23ed0 | 5216 | const_tiny_rtx[i][(int) mode] = |
5217 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
15bbde2b | 5218 | |
b572011e | 5219 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
15bbde2b | 5220 | |
069b07bf | 5221 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5222 | mode != VOIDmode; | |
15bbde2b | 5223 | mode = GET_MODE_WIDER_MODE (mode)) |
b572011e | 5224 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
7540dcc4 | 5225 | |
5226 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5227 | mode != VOIDmode; | |
5228 | mode = GET_MODE_WIDER_MODE (mode)) | |
5229 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
15bbde2b | 5230 | } |
5231 | ||
4248fc32 | 5232 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5233 | mode != VOIDmode; | |
5234 | mode = GET_MODE_WIDER_MODE (mode)) | |
5235 | { | |
5236 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5237 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5238 | } | |
5239 | ||
5240 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5241 | mode != VOIDmode; | |
5242 | mode = GET_MODE_WIDER_MODE (mode)) | |
5243 | { | |
5244 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5245 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5246 | } | |
5247 | ||
886cfd4f | 5248 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5249 | mode != VOIDmode; | |
5250 | mode = GET_MODE_WIDER_MODE (mode)) | |
6e68dcb2 | 5251 | { |
5252 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5253 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5254 | } | |
886cfd4f | 5255 | |
5256 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5257 | mode != VOIDmode; | |
5258 | mode = GET_MODE_WIDER_MODE (mode)) | |
6e68dcb2 | 5259 | { |
5260 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5261 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5262 | } | |
886cfd4f | 5263 | |
06f0b99c | 5264 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
5265 | mode != VOIDmode; | |
5266 | mode = GET_MODE_WIDER_MODE (mode)) | |
5267 | { | |
5268 | FCONST0(mode).data.high = 0; | |
5269 | FCONST0(mode).data.low = 0; | |
5270 | FCONST0(mode).mode = mode; | |
5271 | } | |
5272 | ||
5273 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
5274 | mode != VOIDmode; | |
5275 | mode = GET_MODE_WIDER_MODE (mode)) | |
5276 | { | |
5277 | FCONST0(mode).data.high = 0; | |
5278 | FCONST0(mode).data.low = 0; | |
5279 | FCONST0(mode).mode = mode; | |
5280 | } | |
5281 | ||
5282 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
5283 | mode != VOIDmode; | |
5284 | mode = GET_MODE_WIDER_MODE (mode)) | |
5285 | { | |
5286 | FCONST0(mode).data.high = 0; | |
5287 | FCONST0(mode).data.low = 0; | |
5288 | FCONST0(mode).mode = mode; | |
5289 | ||
5290 | /* We store the value 1. */ | |
5291 | FCONST1(mode).data.high = 0; | |
5292 | FCONST1(mode).data.low = 0; | |
5293 | FCONST1(mode).mode = mode; | |
5294 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5295 | 2 * HOST_BITS_PER_WIDE_INT, | |
5296 | &FCONST1(mode).data.low, | |
5297 | &FCONST1(mode).data.high, | |
5298 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
5299 | } | |
5300 | ||
5301 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
5302 | mode != VOIDmode; | |
5303 | mode = GET_MODE_WIDER_MODE (mode)) | |
5304 | { | |
5305 | FCONST0(mode).data.high = 0; | |
5306 | FCONST0(mode).data.low = 0; | |
5307 | FCONST0(mode).mode = mode; | |
5308 | ||
5309 | /* We store the value 1. */ | |
5310 | FCONST1(mode).data.high = 0; | |
5311 | FCONST1(mode).data.low = 0; | |
5312 | FCONST1(mode).mode = mode; | |
5313 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5314 | 2 * HOST_BITS_PER_WIDE_INT, | |
5315 | &FCONST1(mode).data.low, | |
5316 | &FCONST1(mode).data.high, | |
5317 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
5318 | } | |
5319 | ||
0fd4500a | 5320 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5321 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5322 | const_tiny_rtx[0][i] = const0_rtx; | |
15bbde2b | 5323 | |
065336b4 | 5324 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5325 | if (STORE_FLAG_VALUE == 1) | |
5326 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
5327 | ||
f4bffa58 | 5328 | #ifdef RETURN_ADDRESS_POINTER_REGNUM |
5329 | return_address_pointer_rtx | |
22cf44bc | 5330 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); |
f4bffa58 | 5331 | #endif |
5332 | ||
f4bffa58 | 5333 | #ifdef STATIC_CHAIN_REGNUM |
5334 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
5335 | ||
5336 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
5337 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
5338 | static_chain_incoming_rtx | |
5339 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
5340 | else | |
5341 | #endif | |
5342 | static_chain_incoming_rtx = static_chain_rtx; | |
5343 | #endif | |
5344 | ||
5345 | #ifdef STATIC_CHAIN | |
5346 | static_chain_rtx = STATIC_CHAIN; | |
5347 | ||
5348 | #ifdef STATIC_CHAIN_INCOMING | |
5349 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
5350 | #else | |
5351 | static_chain_incoming_rtx = static_chain_rtx; | |
5352 | #endif | |
5353 | #endif | |
5354 | ||
3473aefe | 5355 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
52bcea50 | 5356 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); |
15bbde2b | 5357 | } |
ac6c481d | 5358 | \f |
cd0fe062 | 5359 | /* Produce exact duplicate of insn INSN after AFTER. |
5360 | Care updating of libcall regions if present. */ | |
5361 | ||
5362 | rtx | |
35cb5232 | 5363 | emit_copy_of_insn_after (rtx insn, rtx after) |
cd0fe062 | 5364 | { |
5365 | rtx new; | |
5366 | rtx note1, note2, link; | |
5367 | ||
5368 | switch (GET_CODE (insn)) | |
5369 | { | |
5370 | case INSN: | |
5371 | new = emit_insn_after (copy_insn (PATTERN (insn)), after); | |
5372 | break; | |
5373 | ||
5374 | case JUMP_INSN: | |
5375 | new = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); | |
5376 | break; | |
5377 | ||
5378 | case CALL_INSN: | |
5379 | new = emit_call_insn_after (copy_insn (PATTERN (insn)), after); | |
5380 | if (CALL_INSN_FUNCTION_USAGE (insn)) | |
5381 | CALL_INSN_FUNCTION_USAGE (new) | |
5382 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); | |
5383 | SIBLING_CALL_P (new) = SIBLING_CALL_P (insn); | |
5384 | CONST_OR_PURE_CALL_P (new) = CONST_OR_PURE_CALL_P (insn); | |
5385 | break; | |
5386 | ||
5387 | default: | |
611234b4 | 5388 | gcc_unreachable (); |
cd0fe062 | 5389 | } |
5390 | ||
5391 | /* Update LABEL_NUSES. */ | |
5392 | mark_jump_label (PATTERN (new), new, 0); | |
5393 | ||
13751393 | 5394 | INSN_LOCATOR (new) = INSN_LOCATOR (insn); |
ab87d1bc | 5395 | |
98116afd | 5396 | /* If the old insn is frame related, then so is the new one. This is |
5397 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
5398 | which may be duplicated by the basic block reordering code. */ | |
5399 | RTX_FRAME_RELATED_P (new) = RTX_FRAME_RELATED_P (insn); | |
5400 | ||
cd0fe062 | 5401 | /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will |
5402 | make them. */ | |
5403 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
5404 | if (REG_NOTE_KIND (link) != REG_LABEL) | |
5405 | { | |
5406 | if (GET_CODE (link) == EXPR_LIST) | |
5407 | REG_NOTES (new) | |
3631101e | 5408 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link), |
5409 | copy_insn_1 (XEXP (link, 0)), REG_NOTES (new)); | |
cd0fe062 | 5410 | else |
5411 | REG_NOTES (new) | |
3631101e | 5412 | = gen_rtx_INSN_LIST (REG_NOTE_KIND (link), |
5be6d461 | 5413 | XEXP (link, 0), REG_NOTES (new)); |
cd0fe062 | 5414 | } |
5415 | ||
5416 | /* Fix the libcall sequences. */ | |
5417 | if ((note1 = find_reg_note (new, REG_RETVAL, NULL_RTX)) != NULL) | |
5418 | { | |
5419 | rtx p = new; | |
5420 | while ((note2 = find_reg_note (p, REG_LIBCALL, NULL_RTX)) == NULL) | |
5421 | p = PREV_INSN (p); | |
5422 | XEXP (note1, 0) = p; | |
5423 | XEXP (note2, 0) = new; | |
5424 | } | |
ce07bc35 | 5425 | INSN_CODE (new) = INSN_CODE (insn); |
cd0fe062 | 5426 | return new; |
5427 | } | |
1f3233d1 | 5428 | |
7035b2ab | 5429 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
c09425a0 | 5430 | rtx |
5431 | gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno) | |
5432 | { | |
5433 | if (hard_reg_clobbers[mode][regno]) | |
5434 | return hard_reg_clobbers[mode][regno]; | |
5435 | else | |
5436 | return (hard_reg_clobbers[mode][regno] = | |
5437 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
5438 | } | |
5439 | ||
1f3233d1 | 5440 | #include "gt-emit-rtl.h" |