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23b2ce53 | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
90a74703 | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
23b2ce53 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
670ee920 | 39 | #include "system.h" |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
ca695ac9 | 53 | #include "obstack.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
ca695ac9 | 57 | |
1d445e9e ILT |
58 | /* Commonly used modes. */ |
59 | ||
0f41302f MS |
60 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
61 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 62 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 63 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 64 | |
23b2ce53 RS |
65 | |
66 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
67 | in the entire compilation a unique label number. */ | |
68 | ||
69 | static int label_num = 1; | |
70 | ||
23b2ce53 RS |
71 | /* Highest label number in current function. |
72 | Zero means use the value of label_num instead. | |
73 | This is nonzero only when belatedly compiling an inline function. */ | |
74 | ||
75 | static int last_label_num; | |
76 | ||
77 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
78 | If label_num has not changed since then, last_label_num is valid. */ | |
79 | ||
80 | static int base_label_num; | |
81 | ||
82 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
83 | ||
84 | static int no_line_numbers; | |
85 | ||
86 | /* Commonly used rtx's, so that we only need space for one copy. | |
87 | These are initialized once for the entire compilation. | |
88 | All of these except perhaps the floating-point CONST_DOUBLEs | |
89 | are unique; no other rtx-object will be equal to any of these. */ | |
90 | ||
5da077de | 91 | rtx global_rtl[GR_MAX]; |
23b2ce53 RS |
92 | |
93 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
94 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
95 | record a copy of const[012]_rtx. */ | |
96 | ||
97 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
98 | ||
68d75312 JC |
99 | rtx const_true_rtx; |
100 | ||
23b2ce53 RS |
101 | REAL_VALUE_TYPE dconst0; |
102 | REAL_VALUE_TYPE dconst1; | |
103 | REAL_VALUE_TYPE dconst2; | |
104 | REAL_VALUE_TYPE dconstm1; | |
105 | ||
106 | /* All references to the following fixed hard registers go through | |
107 | these unique rtl objects. On machines where the frame-pointer and | |
108 | arg-pointer are the same register, they use the same unique object. | |
109 | ||
110 | After register allocation, other rtl objects which used to be pseudo-regs | |
111 | may be clobbered to refer to the frame-pointer register. | |
112 | But references that were originally to the frame-pointer can be | |
113 | distinguished from the others because they contain frame_pointer_rtx. | |
114 | ||
ac6f08b0 DE |
115 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
116 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
117 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
118 | register elimination hard_frame_pointer_rtx should always be used. | |
119 | On machines where the two registers are same (most) then these are the | |
120 | same. | |
121 | ||
23b2ce53 RS |
122 | In an inline procedure, the stack and frame pointer rtxs may not be |
123 | used for anything else. */ | |
23b2ce53 RS |
124 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
125 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
126 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
127 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
128 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
129 | ||
a4417a86 JW |
130 | /* This is used to implement __builtin_return_address for some machines. |
131 | See for instance the MIPS port. */ | |
132 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
133 | ||
23b2ce53 RS |
134 | /* We make one copy of (const_int C) where C is in |
135 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
136 | to save space during the compilation and simplify comparisons of | |
137 | integers. */ | |
138 | ||
5da077de | 139 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 140 | |
c13e8210 MM |
141 | /* A hash table storing CONST_INTs whose absolute value is greater |
142 | than MAX_SAVED_CONST_INT. */ | |
143 | ||
144 | static htab_t const_int_htab; | |
145 | ||
23b2ce53 RS |
146 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
147 | shortly thrown away. We use two mechanisms to prevent this waste: | |
148 | ||
a3770a81 RH |
149 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
150 | rtvec for use by gen_sequence. One entry for each size is | |
151 | sufficient because most cases are calls to gen_sequence followed by | |
152 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
153 | sequence is destructive on the insn in it anyway and hence can't be | |
154 | redone. | |
23b2ce53 RS |
155 | |
156 | We do not bother to save this cached data over nested function calls. | |
157 | Instead, we just reinitialize them. */ | |
158 | ||
159 | #define SEQUENCE_RESULT_SIZE 5 | |
160 | ||
23b2ce53 RS |
161 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
162 | ||
0f41302f | 163 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
43127294 RK |
164 | static rtx free_insn; |
165 | ||
01d939e8 BS |
166 | #define first_insn (cfun->emit->x_first_insn) |
167 | #define last_insn (cfun->emit->x_last_insn) | |
168 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
169 | #define last_linenum (cfun->emit->x_last_linenum) | |
170 | #define last_filename (cfun->emit->x_last_filename) | |
171 | #define first_label_num (cfun->emit->x_first_label_num) | |
23b2ce53 | 172 | |
711d877c KG |
173 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
174 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
175 | static rtx find_line_note PARAMS ((rtx)); | |
176 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
d1b81779 | 177 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
5c6df058 | 178 | static void unshare_all_decls PARAMS ((tree)); |
2d4aecb3 | 179 | static void reset_used_decls PARAMS ((tree)); |
c13e8210 MM |
180 | static hashval_t const_int_htab_hash PARAMS ((const void *)); |
181 | static int const_int_htab_eq PARAMS ((const void *, | |
182 | const void *)); | |
183 | static int rtx_htab_mark_1 PARAMS ((void **, void *)); | |
184 | static void rtx_htab_mark PARAMS ((void *)); | |
185 | ||
ca695ac9 | 186 | \f |
c13e8210 MM |
187 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
188 | ||
189 | static hashval_t | |
190 | const_int_htab_hash (x) | |
191 | const void *x; | |
192 | { | |
e77d72cb | 193 | return (hashval_t) INTVAL ((const struct rtx_def *) x); |
c13e8210 MM |
194 | } |
195 | ||
196 | /* Returns non-zero if the value represented by X (which is really a | |
197 | CONST_INT) is the same as that given by Y (which is really a | |
198 | HOST_WIDE_INT *). */ | |
199 | ||
200 | static int | |
201 | const_int_htab_eq (x, y) | |
202 | const void *x; | |
203 | const void *y; | |
204 | { | |
e77d72cb | 205 | return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y)); |
c13e8210 MM |
206 | } |
207 | ||
208 | /* Mark the hash-table element X (which is really a pointer to an | |
209 | rtx). */ | |
210 | ||
211 | static int | |
212 | rtx_htab_mark_1 (x, data) | |
213 | void **x; | |
214 | void *data ATTRIBUTE_UNUSED; | |
215 | { | |
216 | ggc_mark_rtx (*x); | |
217 | return 1; | |
218 | } | |
219 | ||
220 | /* Mark all the elements of HTAB (which is really an htab_t full of | |
221 | rtxs). */ | |
222 | ||
223 | static void | |
224 | rtx_htab_mark (htab) | |
225 | void *htab; | |
226 | { | |
227 | htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL); | |
228 | } | |
229 | ||
08394eef BS |
230 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
231 | don't attempt to share with the various global pieces of rtl (such as | |
232 | frame_pointer_rtx). */ | |
233 | ||
234 | rtx | |
235 | gen_raw_REG (mode, regno) | |
236 | enum machine_mode mode; | |
237 | int regno; | |
238 | { | |
239 | rtx x = gen_rtx_raw_REG (mode, regno); | |
240 | ORIGINAL_REGNO (x) = regno; | |
241 | return x; | |
242 | } | |
243 | ||
c5c76735 JL |
244 | /* There are some RTL codes that require special attention; the generation |
245 | functions do the raw handling. If you add to this list, modify | |
246 | special_rtx in gengenrtl.c as well. */ | |
247 | ||
3b80f6ca RH |
248 | rtx |
249 | gen_rtx_CONST_INT (mode, arg) | |
c13e8210 | 250 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3b80f6ca RH |
251 | HOST_WIDE_INT arg; |
252 | { | |
c13e8210 MM |
253 | void **slot; |
254 | ||
3b80f6ca | 255 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 256 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
257 | |
258 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
259 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
260 | return const_true_rtx; | |
261 | #endif | |
262 | ||
c13e8210 | 263 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
264 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
265 | (hashval_t) arg, INSERT); | |
29105cea | 266 | if (*slot == 0) |
1f8f4a0b | 267 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
268 | |
269 | return (rtx) *slot; | |
3b80f6ca RH |
270 | } |
271 | ||
29105cea | 272 | /* CONST_DOUBLEs needs special handling because their length is known |
0133b7d9 | 273 | only at run-time. */ |
29105cea | 274 | |
0133b7d9 RH |
275 | rtx |
276 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
277 | enum machine_mode mode; | |
278 | rtx arg0; | |
279 | HOST_WIDE_INT arg1, arg2; | |
280 | { | |
281 | rtx r = rtx_alloc (CONST_DOUBLE); | |
2454beaf RH |
282 | int i; |
283 | ||
0133b7d9 RH |
284 | PUT_MODE (r, mode); |
285 | XEXP (r, 0) = arg0; | |
ef178af3 | 286 | X0EXP (r, 1) = NULL_RTX; |
2454beaf RH |
287 | XWINT (r, 2) = arg1; |
288 | XWINT (r, 3) = arg2; | |
289 | ||
290 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
291 | XWINT (r, i) = 0; | |
292 | ||
0133b7d9 RH |
293 | return r; |
294 | } | |
295 | ||
3b80f6ca RH |
296 | rtx |
297 | gen_rtx_REG (mode, regno) | |
298 | enum machine_mode mode; | |
299 | int regno; | |
300 | { | |
301 | /* In case the MD file explicitly references the frame pointer, have | |
302 | all such references point to the same frame pointer. This is | |
303 | used during frame pointer elimination to distinguish the explicit | |
304 | references to these registers from pseudos that happened to be | |
305 | assigned to them. | |
306 | ||
307 | If we have eliminated the frame pointer or arg pointer, we will | |
308 | be using it as a normal register, for example as a spill | |
309 | register. In such cases, we might be accessing it in a mode that | |
310 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
311 | ||
312 | Also don't do this when we are making new REGs in reload, since | |
313 | we don't want to get confused with the real pointers. */ | |
314 | ||
315 | if (mode == Pmode && !reload_in_progress) | |
316 | { | |
bcb33994 | 317 | if (regno == FRAME_POINTER_REGNUM) |
3b80f6ca RH |
318 | return frame_pointer_rtx; |
319 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
bcb33994 | 320 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3b80f6ca RH |
321 | return hard_frame_pointer_rtx; |
322 | #endif | |
323 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 324 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
325 | return arg_pointer_rtx; |
326 | #endif | |
327 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 328 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
329 | return return_address_pointer_rtx; |
330 | #endif | |
bcb33994 | 331 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
332 | return stack_pointer_rtx; |
333 | } | |
334 | ||
08394eef | 335 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
336 | } |
337 | ||
41472af8 MM |
338 | rtx |
339 | gen_rtx_MEM (mode, addr) | |
340 | enum machine_mode mode; | |
341 | rtx addr; | |
342 | { | |
343 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
344 | ||
345 | /* This field is not cleared by the mere allocation of the rtx, so | |
346 | we clear it here. */ | |
347 | MEM_ALIAS_SET (rt) = 0; | |
348 | ||
349 | return rt; | |
350 | } | |
ddef6bc7 JJ |
351 | |
352 | rtx | |
353 | gen_rtx_SUBREG (mode, reg, offset) | |
354 | enum machine_mode mode; | |
355 | rtx reg; | |
356 | int offset; | |
357 | { | |
358 | /* This is the most common failure type. | |
359 | Catch it early so we can see who does it. */ | |
360 | if ((offset % GET_MODE_SIZE (mode)) != 0) | |
361 | abort (); | |
362 | ||
363 | /* This check isn't usable right now because combine will | |
364 | throw arbitrary crap like a CALL into a SUBREG in | |
365 | gen_lowpart_for_combine so we must just eat it. */ | |
366 | #if 0 | |
367 | /* Check for this too. */ | |
368 | if (offset >= GET_MODE_SIZE (GET_MODE (reg))) | |
369 | abort (); | |
370 | #endif | |
371 | return gen_rtx_fmt_ei (SUBREG, mode, reg, offset); | |
372 | } | |
373 | ||
374 | /* Generate a SUBREG representing the least-significant part | |
375 | * of REG if MODE is smaller than mode of REG, otherwise | |
376 | * paradoxical SUBREG. */ | |
377 | rtx | |
378 | gen_lowpart_SUBREG (mode, reg) | |
379 | enum machine_mode mode; | |
380 | rtx reg; | |
381 | { | |
382 | enum machine_mode inmode; | |
383 | int offset; | |
384 | ||
385 | inmode = GET_MODE (reg); | |
386 | if (inmode == VOIDmode) | |
387 | inmode = mode; | |
388 | offset = 0; | |
389 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (inmode) | |
390 | && (WORDS_BIG_ENDIAN || BYTES_BIG_ENDIAN)) | |
391 | { | |
392 | offset = GET_MODE_SIZE (inmode) - GET_MODE_SIZE (mode); | |
393 | if (! BYTES_BIG_ENDIAN) | |
394 | offset = (offset / UNITS_PER_WORD) * UNITS_PER_WORD; | |
395 | else if (! WORDS_BIG_ENDIAN) | |
396 | offset %= UNITS_PER_WORD; | |
397 | } | |
398 | return gen_rtx_SUBREG (mode, reg, offset); | |
399 | } | |
c5c76735 | 400 | \f |
23b2ce53 RS |
401 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
402 | ** | |
403 | ** This routine generates an RTX of the size specified by | |
404 | ** <code>, which is an RTX code. The RTX structure is initialized | |
405 | ** from the arguments <element1> through <elementn>, which are | |
406 | ** interpreted according to the specific RTX type's format. The | |
407 | ** special machine mode associated with the rtx (if any) is specified | |
408 | ** in <mode>. | |
409 | ** | |
1632afca | 410 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
411 | ** rtx it will generate. For example, the following rtx structure: |
412 | ** | |
413 | ** (plus:QI (mem:QI (reg:SI 1)) | |
414 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
415 | ** | |
416 | ** ...would be generated by the following C code: | |
417 | ** | |
418 | ** gen_rtx (PLUS, QImode, | |
419 | ** gen_rtx (MEM, QImode, | |
420 | ** gen_rtx (REG, SImode, 1)), | |
421 | ** gen_rtx (MEM, QImode, | |
422 | ** gen_rtx (PLUS, SImode, | |
423 | ** gen_rtx (REG, SImode, 2), | |
424 | ** gen_rtx (REG, SImode, 3)))), | |
425 | */ | |
426 | ||
427 | /*VARARGS2*/ | |
428 | rtx | |
711d877c | 429 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
23b2ce53 | 430 | { |
5148a72b | 431 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
432 | enum rtx_code code; |
433 | enum machine_mode mode; | |
4f90e4a0 RK |
434 | #endif |
435 | va_list p; | |
23b2ce53 | 436 | register int i; /* Array indices... */ |
6f7d635c | 437 | register const char *fmt; /* Current rtx's format... */ |
23b2ce53 RS |
438 | register rtx rt_val; /* RTX to return to caller... */ |
439 | ||
4f90e4a0 RK |
440 | VA_START (p, mode); |
441 | ||
5148a72b | 442 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
443 | code = va_arg (p, enum rtx_code); |
444 | mode = va_arg (p, enum machine_mode); | |
4f90e4a0 | 445 | #endif |
23b2ce53 | 446 | |
0133b7d9 | 447 | switch (code) |
23b2ce53 | 448 | { |
0133b7d9 RH |
449 | case CONST_INT: |
450 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
451 | break; | |
452 | ||
453 | case CONST_DOUBLE: | |
454 | { | |
455 | rtx arg0 = va_arg (p, rtx); | |
456 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
457 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
458 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
459 | } | |
460 | break; | |
461 | ||
462 | case REG: | |
463 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
464 | break; | |
465 | ||
466 | case MEM: | |
467 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
468 | break; | |
469 | ||
470 | default: | |
23b2ce53 RS |
471 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
472 | rt_val->mode = mode; /* Store the machine mode... */ | |
473 | ||
474 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
475 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
476 | { | |
477 | switch (*fmt++) | |
478 | { | |
479 | case '0': /* Unused field. */ | |
480 | break; | |
481 | ||
482 | case 'i': /* An integer? */ | |
483 | XINT (rt_val, i) = va_arg (p, int); | |
484 | break; | |
485 | ||
906c4e36 RK |
486 | case 'w': /* A wide integer? */ |
487 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
488 | break; | |
489 | ||
23b2ce53 RS |
490 | case 's': /* A string? */ |
491 | XSTR (rt_val, i) = va_arg (p, char *); | |
492 | break; | |
493 | ||
494 | case 'e': /* An expression? */ | |
495 | case 'u': /* An insn? Same except when printing. */ | |
496 | XEXP (rt_val, i) = va_arg (p, rtx); | |
497 | break; | |
498 | ||
499 | case 'E': /* An RTX vector? */ | |
500 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
501 | break; | |
502 | ||
0dfa1860 MM |
503 | case 'b': /* A bitmap? */ |
504 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
505 | break; | |
506 | ||
507 | case 't': /* A tree? */ | |
508 | XTREE (rt_val, i) = va_arg (p, tree); | |
509 | break; | |
510 | ||
23b2ce53 | 511 | default: |
1632afca | 512 | abort (); |
23b2ce53 RS |
513 | } |
514 | } | |
0133b7d9 | 515 | break; |
23b2ce53 | 516 | } |
0133b7d9 | 517 | |
23b2ce53 | 518 | va_end (p); |
0133b7d9 | 519 | return rt_val; |
23b2ce53 RS |
520 | } |
521 | ||
522 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
523 | ** | |
524 | ** This routine creates an rtvec and stores within it the | |
525 | ** pointers to rtx's which are its arguments. | |
526 | */ | |
527 | ||
528 | /*VARARGS1*/ | |
529 | rtvec | |
711d877c | 530 | gen_rtvec VPARAMS ((int n, ...)) |
23b2ce53 | 531 | { |
5148a72b | 532 | #ifndef ANSI_PROTOTYPES |
4f90e4a0 RK |
533 | int n; |
534 | #endif | |
535 | int i; | |
23b2ce53 RS |
536 | va_list p; |
537 | rtx *vector; | |
538 | ||
4f90e4a0 RK |
539 | VA_START (p, n); |
540 | ||
5148a72b | 541 | #ifndef ANSI_PROTOTYPES |
23b2ce53 | 542 | n = va_arg (p, int); |
4f90e4a0 | 543 | #endif |
23b2ce53 RS |
544 | |
545 | if (n == 0) | |
546 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
547 | ||
548 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 549 | |
23b2ce53 RS |
550 | for (i = 0; i < n; i++) |
551 | vector[i] = va_arg (p, rtx); | |
552 | va_end (p); | |
553 | ||
554 | return gen_rtvec_v (n, vector); | |
555 | } | |
556 | ||
557 | rtvec | |
558 | gen_rtvec_v (n, argp) | |
559 | int n; | |
560 | rtx *argp; | |
561 | { | |
562 | register int i; | |
563 | register rtvec rt_val; | |
564 | ||
565 | if (n == 0) | |
566 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
567 | ||
568 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
569 | ||
570 | for (i = 0; i < n; i++) | |
8f985ec4 | 571 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
572 | |
573 | return rt_val; | |
574 | } | |
ba444f92 | 575 | |
23b2ce53 RS |
576 | \f |
577 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
578 | This pseudo is assigned the next sequential register number. */ | |
579 | ||
580 | rtx | |
581 | gen_reg_rtx (mode) | |
582 | enum machine_mode mode; | |
583 | { | |
01d939e8 | 584 | struct function *f = cfun; |
23b2ce53 RS |
585 | register rtx val; |
586 | ||
f1db3576 JL |
587 | /* Don't let anything called after initial flow analysis create new |
588 | registers. */ | |
589 | if (no_new_pseudos) | |
23b2ce53 RS |
590 | abort (); |
591 | ||
1b3d8f8a GK |
592 | if (generating_concat_p |
593 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
594 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
595 | { |
596 | /* For complex modes, don't make a single pseudo. | |
597 | Instead, make a CONCAT of two pseudos. | |
598 | This allows noncontiguous allocation of the real and imaginary parts, | |
599 | which makes much better code. Besides, allocating DCmode | |
600 | pseudos overstrains reload on some machines like the 386. */ | |
601 | rtx realpart, imagpart; | |
602 | int size = GET_MODE_UNIT_SIZE (mode); | |
603 | enum machine_mode partmode | |
604 | = mode_for_size (size * BITS_PER_UNIT, | |
605 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
606 | ? MODE_FLOAT : MODE_INT), | |
607 | 0); | |
608 | ||
609 | realpart = gen_reg_rtx (partmode); | |
610 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 611 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
612 | } |
613 | ||
3502dc9c JDA |
614 | /* Make sure regno_pointer_align and regno_reg_rtx are large enough |
615 | to have an element for this pseudo reg number. */ | |
23b2ce53 | 616 | |
3502dc9c | 617 | if (reg_rtx_no == f->emit->regno_pointer_align_length) |
23b2ce53 | 618 | { |
3502dc9c | 619 | int old_size = f->emit->regno_pointer_align_length; |
23b2ce53 | 620 | rtx *new1; |
e2ecd91c | 621 | char *new; |
e2ecd91c | 622 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa | 623 | memset (new + old_size, 0, old_size); |
f9e158c3 | 624 | f->emit->regno_pointer_align = (unsigned char *) new; |
49ad7cfa | 625 | |
e2ecd91c BS |
626 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
627 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 628 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
629 | regno_reg_rtx = new1; |
630 | ||
3502dc9c | 631 | f->emit->regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
632 | } |
633 | ||
08394eef | 634 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
635 | regno_reg_rtx[reg_rtx_no++] = val; |
636 | return val; | |
637 | } | |
638 | ||
754fdcca RK |
639 | /* Identify REG (which may be a CONCAT) as a user register. */ |
640 | ||
641 | void | |
642 | mark_user_reg (reg) | |
643 | rtx reg; | |
644 | { | |
645 | if (GET_CODE (reg) == CONCAT) | |
646 | { | |
647 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
648 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
649 | } | |
650 | else if (GET_CODE (reg) == REG) | |
651 | REG_USERVAR_P (reg) = 1; | |
652 | else | |
653 | abort (); | |
654 | } | |
655 | ||
86fe05e0 RK |
656 | /* Identify REG as a probable pointer register and show its alignment |
657 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
658 | |
659 | void | |
86fe05e0 | 660 | mark_reg_pointer (reg, align) |
23b2ce53 | 661 | rtx reg; |
86fe05e0 | 662 | int align; |
23b2ce53 | 663 | { |
3502dc9c | 664 | if (! REG_POINTER (reg)) |
00995e78 | 665 | { |
3502dc9c | 666 | REG_POINTER (reg) = 1; |
86fe05e0 | 667 | |
00995e78 RE |
668 | if (align) |
669 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
670 | } | |
671 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
672 | /* We can no-longer be sure just how aligned this pointer is */ | |
86fe05e0 | 673 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
674 | } |
675 | ||
676 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
677 | ||
678 | int | |
679 | max_reg_num () | |
680 | { | |
681 | return reg_rtx_no; | |
682 | } | |
683 | ||
684 | /* Return 1 + the largest label number used so far in the current function. */ | |
685 | ||
686 | int | |
687 | max_label_num () | |
688 | { | |
689 | if (last_label_num && label_num == base_label_num) | |
690 | return last_label_num; | |
691 | return label_num; | |
692 | } | |
693 | ||
694 | /* Return first label number used in this function (if any were used). */ | |
695 | ||
696 | int | |
697 | get_first_label_num () | |
698 | { | |
699 | return first_label_num; | |
700 | } | |
701 | \f | |
ddef6bc7 JJ |
702 | /* Return the final regno of X, which is a SUBREG of a hard |
703 | register. */ | |
704 | int | |
705 | subreg_hard_regno (x, check_mode) | |
706 | register rtx x; | |
707 | int check_mode; | |
708 | { | |
709 | enum machine_mode mode = GET_MODE (x); | |
710 | unsigned int byte_offset, base_regno, final_regno; | |
711 | rtx reg = SUBREG_REG (x); | |
712 | ||
713 | /* This is where we attempt to catch illegal subregs | |
714 | created by the compiler. */ | |
715 | if (GET_CODE (x) != SUBREG | |
716 | || GET_CODE (reg) != REG) | |
717 | abort (); | |
718 | base_regno = REGNO (reg); | |
719 | if (base_regno >= FIRST_PSEUDO_REGISTER) | |
720 | abort (); | |
721 | if (! HARD_REGNO_MODE_OK (base_regno, GET_MODE (reg))) | |
722 | abort (); | |
723 | ||
724 | /* Catch non-congruent offsets too. */ | |
725 | byte_offset = SUBREG_BYTE (x); | |
726 | if ((byte_offset % GET_MODE_SIZE (mode)) != 0) | |
727 | abort (); | |
728 | ||
729 | final_regno = subreg_regno (x); | |
730 | ||
731 | return final_regno; | |
732 | } | |
733 | ||
23b2ce53 RS |
734 | /* Return a value representing some low-order bits of X, where the number |
735 | of low-order bits is given by MODE. Note that no conversion is done | |
736 | between floating-point and fixed-point values, rather, the bit | |
737 | representation is returned. | |
738 | ||
739 | This function handles the cases in common between gen_lowpart, below, | |
740 | and two variants in cse.c and combine.c. These are the cases that can | |
741 | be safely handled at all points in the compilation. | |
742 | ||
743 | If this is not a case we can handle, return 0. */ | |
744 | ||
745 | rtx | |
746 | gen_lowpart_common (mode, x) | |
747 | enum machine_mode mode; | |
748 | register rtx x; | |
749 | { | |
ddef6bc7 JJ |
750 | int msize = GET_MODE_SIZE (mode); |
751 | int xsize = GET_MODE_SIZE (GET_MODE (x)); | |
752 | int offset = 0; | |
23b2ce53 RS |
753 | |
754 | if (GET_MODE (x) == mode) | |
755 | return x; | |
756 | ||
757 | /* MODE must occupy no more words than the mode of X. */ | |
758 | if (GET_MODE (x) != VOIDmode | |
ddef6bc7 JJ |
759 | && ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
760 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
23b2ce53 RS |
761 | return 0; |
762 | ||
ddef6bc7 JJ |
763 | if ((WORDS_BIG_ENDIAN || BYTES_BIG_ENDIAN) |
764 | && xsize > msize) | |
765 | { | |
766 | int difference = xsize - msize; | |
767 | ||
768 | if (WORDS_BIG_ENDIAN) | |
769 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
770 | if (BYTES_BIG_ENDIAN) | |
771 | offset += difference % UNITS_PER_WORD; | |
772 | } | |
23b2ce53 RS |
773 | |
774 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
775 | && (GET_MODE_CLASS (mode) == MODE_INT |
776 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
777 | { |
778 | /* If we are getting the low-order part of something that has been | |
779 | sign- or zero-extended, we can either just use the object being | |
780 | extended or make a narrower extension. If we want an even smaller | |
781 | piece than the size of the object being extended, call ourselves | |
782 | recursively. | |
783 | ||
784 | This case is used mostly by combine and cse. */ | |
785 | ||
786 | if (GET_MODE (XEXP (x, 0)) == mode) | |
787 | return XEXP (x, 0); | |
788 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
789 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
790 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3b80f6ca | 791 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 RS |
792 | } |
793 | else if (GET_CODE (x) == SUBREG | |
ddef6bc7 | 794 | && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD |
23b2ce53 | 795 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) |
ddef6bc7 JJ |
796 | { |
797 | int final_offset; | |
798 | ||
799 | if (GET_MODE (SUBREG_REG (x)) == mode && subreg_lowpart_p (x)) | |
800 | return SUBREG_REG (x); | |
801 | ||
802 | /* When working with SUBREGs the rule is that the byte | |
803 | offset must be a multiple of the SUBREG's mode. */ | |
804 | final_offset = SUBREG_BYTE (x) + offset; | |
805 | final_offset = (final_offset / GET_MODE_SIZE (mode)); | |
806 | final_offset = (final_offset * GET_MODE_SIZE (mode)); | |
807 | return gen_rtx_SUBREG (mode, SUBREG_REG (x), final_offset); | |
808 | } | |
23b2ce53 RS |
809 | else if (GET_CODE (x) == REG) |
810 | { | |
ddef6bc7 JJ |
811 | /* Hard registers are done specially in certain cases. */ |
812 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
813 | { | |
814 | int final_regno = REGNO (x) + | |
815 | subreg_regno_offset (REGNO (x), GET_MODE (x), | |
816 | offset, mode); | |
817 | ||
818 | /* If the final regno is not valid for MODE, punt. */ | |
819 | /* ??? We do allow it if the current REG is not valid for | |
820 | ??? it's mode. It is a kludge to work around how float/complex | |
821 | ??? arguments are passed on 32-bit Sparc and should be fixed. */ | |
822 | if (! HARD_REGNO_MODE_OK (final_regno, mode) | |
823 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
824 | return 0; | |
825 | ||
23b2ce53 | 826 | /* integrate.c can't handle parts of a return value register. */ |
ddef6bc7 | 827 | if ((! REG_FUNCTION_VALUE_P (x) |
cb00f51a | 828 | || ! rtx_equal_function_value_matters) |
02188693 RH |
829 | #ifdef CLASS_CANNOT_CHANGE_MODE |
830 | && ! (CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (x)) | |
aff48bca JL |
831 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT |
832 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT | |
833 | && (TEST_HARD_REG_BIT | |
02188693 | 834 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], |
aff48bca JL |
835 | REGNO (x)))) |
836 | #endif | |
cb00f51a RK |
837 | /* We want to keep the stack, frame, and arg pointers |
838 | special. */ | |
65e8fe02 | 839 | && x != frame_pointer_rtx |
cb00f51a | 840 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 841 | && x != arg_pointer_rtx |
cb00f51a | 842 | #endif |
65e8fe02 | 843 | && x != stack_pointer_rtx) |
ddef6bc7 JJ |
844 | return gen_rtx_REG (mode, final_regno); |
845 | } | |
846 | return gen_rtx_SUBREG (mode, x, offset); | |
23b2ce53 | 847 | } |
23b2ce53 RS |
848 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
849 | from the low-order part of the constant. */ | |
83e9c679 RK |
850 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
851 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
852 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 853 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
854 | { |
855 | /* If MODE is twice the host word size, X is already the desired | |
856 | representation. Otherwise, if MODE is wider than a word, we can't | |
e1389cac | 857 | do this. If MODE is exactly a word, return just one CONST_INT. */ |
1a5b457d | 858 | |
a8dd0e73 | 859 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 860 | return x; |
906c4e36 | 861 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 862 | return 0; |
906c4e36 | 863 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 864 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 865 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
866 | else |
867 | { | |
27eef9ce | 868 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
906c4e36 RK |
869 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
870 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 871 | |
27eef9ce | 872 | /* Sign extend to HOST_WIDE_INT. */ |
e1389cac | 873 | val = trunc_int_for_mode (val, mode); |
1a5b457d RK |
874 | |
875 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 876 | : GEN_INT (val)); |
1a5b457d RK |
877 | } |
878 | } | |
23b2ce53 | 879 | |
a2061c0d | 880 | #ifndef REAL_ARITHMETIC |
8aada4ad RK |
881 | /* If X is an integral constant but we want it in floating-point, it |
882 | must be the case that we have a union of an integer and a floating-point | |
883 | value. If the machine-parameters allow it, simulate that union here | |
d6020413 RK |
884 | and return the result. The two-word and single-word cases are |
885 | different. */ | |
8aada4ad | 886 | |
b3bf132d | 887 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 888 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 889 | || flag_pretend_float) |
8aada4ad | 890 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
d6020413 RK |
891 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
892 | && GET_CODE (x) == CONST_INT | |
906c4e36 | 893 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
d6020413 | 894 | { |
906c4e36 | 895 | union {HOST_WIDE_INT i; float d; } u; |
d6020413 RK |
896 | |
897 | u.i = INTVAL (x); | |
53596fba | 898 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
d6020413 | 899 | } |
d6020413 | 900 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 901 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
d6020413 RK |
902 | || flag_pretend_float) |
903 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
904 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
8aada4ad RK |
905 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
906 | && GET_MODE (x) == VOIDmode | |
906c4e36 RK |
907 | && (sizeof (double) * HOST_BITS_PER_CHAR |
908 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
8aada4ad | 909 | { |
906c4e36 RK |
910 | union {HOST_WIDE_INT i[2]; double d; } u; |
911 | HOST_WIDE_INT low, high; | |
8aada4ad RK |
912 | |
913 | if (GET_CODE (x) == CONST_INT) | |
906c4e36 | 914 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
8aada4ad RK |
915 | else |
916 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
917 | ||
918 | #ifdef HOST_WORDS_BIG_ENDIAN | |
919 | u.i[0] = high, u.i[1] = low; | |
920 | #else | |
921 | u.i[0] = low, u.i[1] = high; | |
922 | #endif | |
923 | ||
53596fba | 924 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
8aada4ad | 925 | } |
a6a503ed | 926 | |
b3bf132d RK |
927 | /* Similarly, if this is converting a floating-point value into a |
928 | single-word integer. Only do this is the host and target parameters are | |
929 | compatible. */ | |
930 | ||
931 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
906c4e36 | 932 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 933 | || flag_pretend_float) |
83e9c679 RK |
934 | && (GET_MODE_CLASS (mode) == MODE_INT |
935 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
b3bf132d RK |
936 | && GET_CODE (x) == CONST_DOUBLE |
937 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
938 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
ddef6bc7 | 939 | return constant_subword (x, (offset / UNITS_PER_WORD), GET_MODE (x)); |
b3bf132d | 940 | |
8aada4ad RK |
941 | /* Similarly, if this is converting a floating-point value into a |
942 | two-word integer, we can do this one word at a time and make an | |
943 | integer. Only do this is the host and target parameters are | |
944 | compatible. */ | |
945 | ||
b3bf132d | 946 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 947 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 948 | || flag_pretend_float) |
83e9c679 | 949 | && (GET_MODE_CLASS (mode) == MODE_INT |
f5a2fb25 | 950 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
8aada4ad RK |
951 | && GET_CODE (x) == CONST_DOUBLE |
952 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
953 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
954 | { | |
ddef6bc7 JJ |
955 | rtx lowpart, highpart; |
956 | ||
957 | lowpart = constant_subword (x, | |
958 | (offset / UNITS_PER_WORD) + WORDS_BIG_ENDIAN, | |
959 | GET_MODE (x)); | |
960 | highpart = constant_subword (x, | |
961 | (offset / UNITS_PER_WORD) + (! WORDS_BIG_ENDIAN), | |
962 | GET_MODE (x)); | |
8aada4ad RK |
963 | if (lowpart && GET_CODE (lowpart) == CONST_INT |
964 | && highpart && GET_CODE (highpart) == CONST_INT) | |
965 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
966 | } | |
a2061c0d GK |
967 | #else /* ifndef REAL_ARITHMETIC */ |
968 | ||
969 | /* When we have a FP emulator, we can handle all conversions between | |
970 | FP and integer operands. This simplifies reload because it | |
971 | doesn't have to deal with constructs like (subreg:DI | |
972 | (const_double:SF ...)) or (subreg:DF (const_int ...)). */ | |
973 | ||
974 | else if (mode == SFmode | |
975 | && GET_CODE (x) == CONST_INT) | |
976 | { | |
977 | REAL_VALUE_TYPE r; | |
978 | HOST_WIDE_INT i; | |
979 | ||
980 | i = INTVAL (x); | |
981 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
982 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
983 | } | |
984 | else if (mode == DFmode | |
985 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
986 | && GET_MODE (x) == VOIDmode) | |
987 | { | |
988 | REAL_VALUE_TYPE r; | |
989 | HOST_WIDE_INT i[2]; | |
990 | HOST_WIDE_INT low, high; | |
991 | ||
992 | if (GET_CODE (x) == CONST_INT) | |
993 | { | |
994 | low = INTVAL (x); | |
995 | high = low >> (HOST_BITS_PER_WIDE_INT - 1); | |
996 | } | |
997 | else | |
998 | { | |
999 | low = CONST_DOUBLE_LOW (x); | |
1000 | high = CONST_DOUBLE_HIGH (x); | |
1001 | } | |
1002 | ||
1003 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the | |
1004 | target machine. */ | |
1005 | if (WORDS_BIG_ENDIAN) | |
1006 | i[0] = high, i[1] = low; | |
1007 | else | |
1008 | i[0] = low, i[1] = high; | |
1009 | ||
1010 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
1011 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
1012 | } | |
1013 | else if ((GET_MODE_CLASS (mode) == MODE_INT | |
1014 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
1015 | && GET_CODE (x) == CONST_DOUBLE | |
1016 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1017 | { | |
1018 | REAL_VALUE_TYPE r; | |
1019 | long i[4]; /* Only the low 32 bits of each 'long' are used. */ | |
1020 | int endian = WORDS_BIG_ENDIAN ? 1 : 0; | |
1021 | ||
1022 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
1023 | switch (GET_MODE (x)) | |
1024 | { | |
1025 | case SFmode: | |
1026 | REAL_VALUE_TO_TARGET_SINGLE (r, i[endian]); | |
1156b23c | 1027 | i[1 - endian] = 0; |
a2061c0d GK |
1028 | break; |
1029 | case DFmode: | |
1030 | REAL_VALUE_TO_TARGET_DOUBLE (r, i); | |
1031 | break; | |
1032 | #if LONG_DOUBLE_TYPE_SIZE == 96 | |
1033 | case XFmode: | |
e389897b JJ |
1034 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i + endian); |
1035 | i[3-3*endian] = 0; | |
a2061c0d GK |
1036 | #else |
1037 | case TFmode: | |
a2061c0d | 1038 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i); |
e389897b | 1039 | #endif |
a2061c0d GK |
1040 | break; |
1041 | default: | |
1156b23c | 1042 | abort (); |
a2061c0d GK |
1043 | } |
1044 | ||
1045 | /* Now, pack the 32-bit elements of the array into a CONST_DOUBLE | |
1046 | and return it. */ | |
1047 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1156b23c | 1048 | return immed_double_const (i[endian], i[1 - endian], mode); |
a2061c0d | 1049 | #else |
50e60bc3 ZW |
1050 | { |
1051 | int c; | |
1052 | ||
1053 | if (HOST_BITS_PER_WIDE_INT != 64) | |
1156b23c RK |
1054 | abort (); |
1055 | ||
50e60bc3 | 1056 | for (c = 0; c < 4; c++) |
1156b23c | 1057 | i[c] &= ~ (0L); |
e389897b JJ |
1058 | |
1059 | switch (GET_MODE (x)) | |
1060 | { | |
1061 | case SFmode: | |
1062 | case DFmode: | |
1063 | return immed_double_const (((unsigned long) i[endian]) | | |
1064 | (((HOST_WIDE_INT) i[1-endian]) << 32), | |
1065 | 0, mode); | |
1066 | default: | |
1067 | return immed_double_const (((unsigned long) i[endian*3]) | | |
1068 | (((HOST_WIDE_INT) i[1+endian]) << 32), | |
1069 | ((unsigned long) i[2-endian]) | | |
1070 | (((HOST_WIDE_INT) i[3-endian*3]) << 32), | |
1071 | mode); | |
1072 | } | |
50e60bc3 | 1073 | } |
a2061c0d GK |
1074 | #endif |
1075 | } | |
1076 | #endif /* ifndef REAL_ARITHMETIC */ | |
8aada4ad | 1077 | |
23b2ce53 RS |
1078 | /* Otherwise, we can't do this. */ |
1079 | return 0; | |
1080 | } | |
1081 | \f | |
280194b0 RS |
1082 | /* Return the real part (which has mode MODE) of a complex value X. |
1083 | This always comes at the low address in memory. */ | |
1084 | ||
1085 | rtx | |
1086 | gen_realpart (mode, x) | |
1087 | enum machine_mode mode; | |
1088 | register rtx x; | |
1089 | { | |
dc139c90 RK |
1090 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
1091 | return XEXP (x, 0); | |
40c0c3cf JL |
1092 | else if (WORDS_BIG_ENDIAN |
1093 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
1094 | && REG_P (x) | |
1095 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
400500c4 RK |
1096 | internal_error |
1097 | ("Can't access real part of complex value in hard register"); | |
dc139c90 | 1098 | else if (WORDS_BIG_ENDIAN) |
280194b0 RS |
1099 | return gen_highpart (mode, x); |
1100 | else | |
1101 | return gen_lowpart (mode, x); | |
1102 | } | |
1103 | ||
1104 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
1105 | This always comes at the high address in memory. */ | |
1106 | ||
1107 | rtx | |
1108 | gen_imagpart (mode, x) | |
1109 | enum machine_mode mode; | |
1110 | register rtx x; | |
1111 | { | |
dc139c90 RK |
1112 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
1113 | return XEXP (x, 1); | |
1114 | else if (WORDS_BIG_ENDIAN) | |
280194b0 | 1115 | return gen_lowpart (mode, x); |
ddef6bc7 | 1116 | else if (! WORDS_BIG_ENDIAN |
40c0c3cf JL |
1117 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD |
1118 | && REG_P (x) | |
1119 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
400500c4 RK |
1120 | internal_error |
1121 | ("can't access imaginary part of complex value in hard register"); | |
280194b0 RS |
1122 | else |
1123 | return gen_highpart (mode, x); | |
1124 | } | |
81284a6a JW |
1125 | |
1126 | /* Return 1 iff X, assumed to be a SUBREG, | |
1127 | refers to the real part of the complex value in its containing reg. | |
1128 | Complex values are always stored with the real part in the first word, | |
1129 | regardless of WORDS_BIG_ENDIAN. */ | |
1130 | ||
1131 | int | |
1132 | subreg_realpart_p (x) | |
1133 | rtx x; | |
1134 | { | |
1135 | if (GET_CODE (x) != SUBREG) | |
1136 | abort (); | |
1137 | ||
ddef6bc7 | 1138 | return ((unsigned int) SUBREG_BYTE (x) |
770ae6cc | 1139 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); |
81284a6a | 1140 | } |
280194b0 | 1141 | \f |
23b2ce53 RS |
1142 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1143 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1144 | least-significant part of X. | |
1145 | MODE specifies how big a part of X to return; | |
1146 | it usually should not be larger than a word. | |
1147 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1148 | ||
1149 | rtx | |
1150 | gen_lowpart (mode, x) | |
1151 | enum machine_mode mode; | |
1152 | register rtx x; | |
1153 | { | |
1154 | rtx result = gen_lowpart_common (mode, x); | |
1155 | ||
1156 | if (result) | |
1157 | return result; | |
ea8262b0 RK |
1158 | else if (GET_CODE (x) == REG) |
1159 | { | |
1160 | /* Must be a hard reg that's not valid in MODE. */ | |
1161 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1162 | if (result == 0) | |
1163 | abort (); | |
72c3833b | 1164 | return result; |
ea8262b0 | 1165 | } |
23b2ce53 RS |
1166 | else if (GET_CODE (x) == MEM) |
1167 | { | |
1168 | /* The only additional case we can do is MEM. */ | |
1169 | register int offset = 0; | |
1170 | if (WORDS_BIG_ENDIAN) | |
1171 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1172 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1173 | ||
1174 | if (BYTES_BIG_ENDIAN) | |
1175 | /* Adjust the address so that the address-after-the-data | |
1176 | is unchanged. */ | |
1177 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1178 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1179 | ||
1180 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
1181 | } | |
e9a25f70 JL |
1182 | else if (GET_CODE (x) == ADDRESSOF) |
1183 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
23b2ce53 RS |
1184 | else |
1185 | abort (); | |
1186 | } | |
1187 | ||
ccba022b RS |
1188 | /* Like `gen_lowpart', but refer to the most significant part. |
1189 | This is used to access the imaginary part of a complex number. */ | |
1190 | ||
1191 | rtx | |
1192 | gen_highpart (mode, x) | |
1193 | enum machine_mode mode; | |
1194 | register rtx x; | |
1195 | { | |
ddef6bc7 JJ |
1196 | unsigned int msize = GET_MODE_SIZE (mode); |
1197 | unsigned int xsize = GET_MODE_SIZE (GET_MODE (x)); | |
1198 | ||
ccba022b RS |
1199 | /* This case loses if X is a subreg. To catch bugs early, |
1200 | complain if an invalid MODE is used even in other cases. */ | |
ddef6bc7 JJ |
1201 | if (msize > UNITS_PER_WORD |
1202 | && msize != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
ccba022b RS |
1203 | abort (); |
1204 | if (GET_CODE (x) == CONST_DOUBLE | |
1632afca | 1205 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
ccba022b RS |
1206 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
1207 | #endif | |
1208 | ) | |
3b80f6ca | 1209 | return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); |
ccba022b | 1210 | else if (GET_CODE (x) == CONST_INT) |
27eef9ce JC |
1211 | { |
1212 | if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD) | |
1213 | return const0_rtx; | |
1214 | return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD)); | |
1215 | } | |
ccba022b RS |
1216 | else if (GET_CODE (x) == MEM) |
1217 | { | |
1218 | register int offset = 0; | |
ddef6bc7 | 1219 | |
8698cce3 | 1220 | if (! WORDS_BIG_ENDIAN) |
ddef6bc7 JJ |
1221 | offset = (MAX (xsize, UNITS_PER_WORD) |
1222 | - MAX (msize, UNITS_PER_WORD)); | |
8698cce3 RK |
1223 | |
1224 | if (! BYTES_BIG_ENDIAN | |
ddef6bc7 JJ |
1225 | && msize < UNITS_PER_WORD) |
1226 | offset -= (msize - MIN (UNITS_PER_WORD, xsize)); | |
8698cce3 | 1227 | |
ccba022b RS |
1228 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
1229 | } | |
1230 | else if (GET_CODE (x) == SUBREG) | |
1231 | { | |
1232 | /* The only time this should occur is when we are looking at a | |
1233 | multi-word item with a SUBREG whose mode is the same as that of the | |
1234 | item. It isn't clear what we would do if it wasn't. */ | |
ddef6bc7 | 1235 | if (SUBREG_BYTE (x) != 0) |
ccba022b RS |
1236 | abort (); |
1237 | return gen_highpart (mode, SUBREG_REG (x)); | |
1238 | } | |
1239 | else if (GET_CODE (x) == REG) | |
1240 | { | |
ddef6bc7 | 1241 | int offset = 0; |
4901a643 | 1242 | |
69295d6d AO |
1243 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) |
1244 | abort (); | |
ddef6bc7 JJ |
1245 | |
1246 | if ((! WORDS_BIG_ENDIAN || ! BYTES_BIG_ENDIAN) | |
1247 | && xsize > msize) | |
1248 | { | |
1249 | int difference = xsize - msize; | |
1250 | ||
1251 | if (! WORDS_BIG_ENDIAN) | |
1252 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1253 | if (! BYTES_BIG_ENDIAN) | |
1254 | offset += difference % UNITS_PER_WORD; | |
1255 | } | |
1256 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1257 | { | |
1258 | int final_regno = REGNO (x) + | |
1259 | subreg_regno_offset (REGNO (x), GET_MODE (x), offset, mode); | |
1260 | ||
1261 | /* integrate.c can't handle parts of a return value register. | |
1262 | ??? Then integrate.c should be fixed! | |
1263 | ??? What about CLASS_CANNOT_CHANGE_SIZE? */ | |
1264 | if ((! REG_FUNCTION_VALUE_P (x) | |
1265 | || ! rtx_equal_function_value_matters) | |
cb00f51a | 1266 | /* We want to keep the stack, frame, and arg pointers special. */ |
ddef6bc7 JJ |
1267 | && x != frame_pointer_rtx |
1268 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
1269 | && x != arg_pointer_rtx | |
cb00f51a | 1270 | #endif |
ddef6bc7 JJ |
1271 | && x != stack_pointer_rtx) |
1272 | return gen_rtx_REG (mode, final_regno); | |
1273 | } | |
1274 | /* Just generate a normal SUBREG. */ | |
1275 | return gen_rtx_SUBREG (mode, x, offset); | |
ccba022b RS |
1276 | } |
1277 | else | |
1278 | abort (); | |
1279 | } | |
1280 | ||
23b2ce53 RS |
1281 | /* Return 1 iff X, assumed to be a SUBREG, |
1282 | refers to the least significant part of its containing reg. | |
1283 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1284 | ||
1285 | int | |
1286 | subreg_lowpart_p (x) | |
1287 | rtx x; | |
1288 | { | |
ddef6bc7 JJ |
1289 | unsigned int offset = 0; |
1290 | int difference = (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1291 | - GET_MODE_SIZE (GET_MODE (x))); | |
1292 | ||
23b2ce53 RS |
1293 | if (GET_CODE (x) != SUBREG) |
1294 | return 1; | |
a3a03040 RK |
1295 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1296 | return 0; | |
23b2ce53 | 1297 | |
ddef6bc7 JJ |
1298 | if (difference > 0) |
1299 | { | |
1300 | if (WORDS_BIG_ENDIAN) | |
1301 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1302 | if (BYTES_BIG_ENDIAN) | |
1303 | offset += difference % UNITS_PER_WORD; | |
1304 | } | |
23b2ce53 | 1305 | |
ddef6bc7 | 1306 | return SUBREG_BYTE (x) == offset; |
23b2ce53 RS |
1307 | } |
1308 | \f | |
23b2ce53 | 1309 | |
ddef6bc7 JJ |
1310 | /* Helper routine for all the constant cases of operand_subword. |
1311 | Some places invoke this directly. */ | |
23b2ce53 RS |
1312 | |
1313 | rtx | |
ddef6bc7 | 1314 | constant_subword (op, offset, mode) |
23b2ce53 | 1315 | rtx op; |
ddef6bc7 | 1316 | int offset; |
23b2ce53 RS |
1317 | enum machine_mode mode; |
1318 | { | |
906c4e36 | 1319 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; |
ddef6bc7 | 1320 | HOST_WIDE_INT val; |
23b2ce53 RS |
1321 | |
1322 | /* If OP is already an integer word, return it. */ | |
1323 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1324 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1325 | return op; | |
1326 | ||
1632afca | 1327 | #ifdef REAL_ARITHMETIC |
5495cc55 RH |
1328 | /* The output is some bits, the width of the target machine's word. |
1329 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1330 | host can't. */ | |
9847c2f6 | 1331 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1632afca | 1332 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1333 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1334 | && GET_CODE (op) == CONST_DOUBLE) |
1335 | { | |
9847c2f6 | 1336 | long k[2]; |
1632afca RS |
1337 | REAL_VALUE_TYPE rv; |
1338 | ||
1339 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1340 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1341 | |
9847c2f6 | 1342 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 | 1343 | which the words are written depends on the word endianness. |
7677ffa4 | 1344 | ??? This is a potential portability problem and should |
7cae975e RH |
1345 | be fixed at some point. |
1346 | ||
1347 | We must excercise caution with the sign bit. By definition there | |
1348 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1349 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1350 | So we explicitly mask and sign-extend as necessary. */ | |
9847c2f6 | 1351 | if (BITS_PER_WORD == 32) |
7cae975e | 1352 | { |
ddef6bc7 | 1353 | val = k[offset]; |
7cae975e RH |
1354 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1355 | return GEN_INT (val); | |
1356 | } | |
1357 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
ddef6bc7 | 1358 | else if (BITS_PER_WORD >= 64 && offset == 0) |
7cae975e RH |
1359 | { |
1360 | val = k[! WORDS_BIG_ENDIAN]; | |
1361 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1362 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1363 | return GEN_INT (val); | |
1364 | } | |
9847c2f6 | 1365 | #endif |
47b34d40 JW |
1366 | else if (BITS_PER_WORD == 16) |
1367 | { | |
ddef6bc7 JJ |
1368 | val = k[offset >> 1]; |
1369 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) | |
7cae975e RH |
1370 | val >>= 16; |
1371 | val &= 0xffff; | |
1372 | return GEN_INT (val); | |
47b34d40 | 1373 | } |
7677ffa4 RK |
1374 | else |
1375 | abort (); | |
1632afca | 1376 | } |
a5559dbc RE |
1377 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1378 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1379 | && GET_MODE_BITSIZE (mode) > 64 | |
1380 | && GET_CODE (op) == CONST_DOUBLE) | |
5495cc55 RH |
1381 | { |
1382 | long k[4]; | |
1383 | REAL_VALUE_TYPE rv; | |
a5559dbc | 1384 | |
5495cc55 RH |
1385 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1386 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
a5559dbc | 1387 | |
5495cc55 RH |
1388 | if (BITS_PER_WORD == 32) |
1389 | { | |
ddef6bc7 | 1390 | val = k[offset]; |
5495cc55 RH |
1391 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1392 | return GEN_INT (val); | |
1393 | } | |
1394 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
ddef6bc7 | 1395 | else if (BITS_PER_WORD >= 64 && offset <= 1) |
5495cc55 | 1396 | { |
ddef6bc7 | 1397 | val = k[offset * 2 + ! WORDS_BIG_ENDIAN]; |
5495cc55 | 1398 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; |
ddef6bc7 | 1399 | val |= (HOST_WIDE_INT) k[offset * 2 + WORDS_BIG_ENDIAN] & 0xffffffff; |
5495cc55 RH |
1400 | return GEN_INT (val); |
1401 | } | |
1402 | #endif | |
1403 | else | |
1404 | abort (); | |
1405 | } | |
1632afca | 1406 | #else /* no REAL_ARITHMETIC */ |
23b2ce53 | 1407 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1408 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1409 | || flag_pretend_float) |
1410 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1411 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1412 | && GET_CODE (op) == CONST_DOUBLE) | |
7529ac93 CH |
1413 | { |
1414 | /* The constant is stored in the host's word-ordering, | |
1415 | but we want to access it in the target's word-ordering. Some | |
1416 | compilers don't like a conditional inside macro args, so we have two | |
1417 | copies of the return. */ | |
2fe02d7e | 1418 | #ifdef HOST_WORDS_BIG_ENDIAN |
ddef6bc7 | 1419 | return GEN_INT (offset == WORDS_BIG_ENDIAN |
7529ac93 | 1420 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); |
2fe02d7e | 1421 | #else |
ddef6bc7 | 1422 | return GEN_INT (offset != WORDS_BIG_ENDIAN |
7529ac93 | 1423 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); |
2fe02d7e | 1424 | #endif |
7529ac93 | 1425 | } |
1632afca | 1426 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1427 | |
1428 | /* Single word float is a little harder, since single- and double-word | |
1429 | values often do not have the same high-order bits. We have already | |
1430 | verified that we want the only defined word of the single-word value. */ | |
1632afca | 1431 | #ifdef REAL_ARITHMETIC |
9847c2f6 | 1432 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1433 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1434 | && GET_CODE (op) == CONST_DOUBLE) |
1435 | { | |
9847c2f6 | 1436 | long l; |
1632afca RS |
1437 | REAL_VALUE_TYPE rv; |
1438 | ||
1439 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1440 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
aa2ae679 | 1441 | |
7cae975e RH |
1442 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1443 | val = l; | |
1444 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
b5a3eb84 | 1445 | |
aa2ae679 JL |
1446 | if (BITS_PER_WORD == 16) |
1447 | { | |
ddef6bc7 | 1448 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) |
7cae975e RH |
1449 | val >>= 16; |
1450 | val &= 0xffff; | |
aa2ae679 | 1451 | } |
7cae975e RH |
1452 | |
1453 | return GEN_INT (val); | |
1632afca RS |
1454 | } |
1455 | #else | |
23b2ce53 | 1456 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1457 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 | 1458 | || flag_pretend_float) |
e01a2cec | 1459 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
23b2ce53 RS |
1460 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1461 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1462 | && GET_CODE (op) == CONST_DOUBLE) | |
1463 | { | |
1464 | double d; | |
906c4e36 | 1465 | union {float f; HOST_WIDE_INT i; } u; |
23b2ce53 RS |
1466 | |
1467 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1468 | ||
1469 | u.f = d; | |
906c4e36 | 1470 | return GEN_INT (u.i); |
23b2ce53 | 1471 | } |
e01a2cec RK |
1472 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1473 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1474 | || flag_pretend_float) | |
1475 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1476 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1477 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1478 | && GET_CODE (op) == CONST_DOUBLE) | |
1479 | { | |
1480 | double d; | |
1481 | union {double d; HOST_WIDE_INT i; } u; | |
1482 | ||
1483 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1484 | ||
1485 | u.d = d; | |
1486 | return GEN_INT (u.i); | |
1487 | } | |
1632afca | 1488 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1489 | |
1490 | /* The only remaining cases that we can handle are integers. | |
1491 | Convert to proper endianness now since these cases need it. | |
ddef6bc7 | 1492 | At this point, offset == 0 means the low-order word. |
23b2ce53 | 1493 | |
2d4f57f8 RK |
1494 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1495 | in general. However, if OP is (const_int 0), we can just return | |
1496 | it for any word. */ | |
1497 | ||
1498 | if (op == const0_rtx) | |
1499 | return op; | |
23b2ce53 RS |
1500 | |
1501 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1502 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1503 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1504 | return 0; |
1505 | ||
1506 | if (WORDS_BIG_ENDIAN) | |
ddef6bc7 | 1507 | offset = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - offset; |
23b2ce53 RS |
1508 | |
1509 | /* Find out which word on the host machine this value is in and get | |
1510 | it from the constant. */ | |
ddef6bc7 | 1511 | val = (offset / size_ratio == 0 |
23b2ce53 RS |
1512 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) |
1513 | : (GET_CODE (op) == CONST_INT | |
1514 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1515 | ||
3f518020 | 1516 | /* Get the value we want into the low bits of val. */ |
906c4e36 | 1517 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
ddef6bc7 | 1518 | val = ((val >> ((offset % size_ratio) * BITS_PER_WORD))); |
3f518020 | 1519 | |
7e4ce834 | 1520 | val = trunc_int_for_mode (val, word_mode); |
23b2ce53 | 1521 | |
906c4e36 | 1522 | return GEN_INT (val); |
23b2ce53 RS |
1523 | } |
1524 | ||
ddef6bc7 JJ |
1525 | /* Return subword OFFSET of operand OP. |
1526 | The word number, OFFSET, is interpreted as the word number starting | |
1527 | at the low-order address. OFFSET 0 is the low-order word if not | |
1528 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1529 | ||
1530 | If we cannot extract the required word, we return zero. Otherwise, | |
1531 | an rtx corresponding to the requested word will be returned. | |
1532 | ||
1533 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1534 | reload has completed, a valid address will always be returned. After | |
1535 | reload, if a valid address cannot be returned, we return zero. | |
1536 | ||
1537 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1538 | it is the responsibility of the caller. | |
1539 | ||
1540 | MODE is the mode of OP in case it is a CONST_INT. | |
1541 | ||
1542 | ??? This is still rather broken for some cases. The problem for the | |
1543 | moment is that all callers of this thing provide no 'goal mode' to | |
1544 | tell us to work with. This exists because all callers were written | |
1545 | in a word based SUBREG world. */ | |
1546 | ||
1547 | rtx | |
1548 | operand_subword (op, offset, validate_address, mode) | |
1549 | rtx op; | |
1550 | unsigned int offset; | |
1551 | int validate_address; | |
1552 | enum machine_mode mode; | |
1553 | { | |
1554 | if (mode == VOIDmode) | |
1555 | mode = GET_MODE (op); | |
1556 | ||
1557 | if (mode == VOIDmode) | |
1558 | abort (); | |
1559 | ||
1560 | /* If OP is narrower than a word, fail. */ | |
1561 | if (mode != BLKmode | |
1562 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1563 | return 0; | |
1564 | ||
1565 | /* If we want a word outside OP, return zero. */ | |
1566 | if (mode != BLKmode | |
1567 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1568 | return const0_rtx; | |
1569 | ||
1570 | switch (GET_CODE (op)) | |
1571 | { | |
1572 | case REG: | |
1573 | case SUBREG: | |
1574 | case CONCAT: | |
1575 | case MEM: | |
1576 | break; | |
1577 | ||
1578 | default: | |
1579 | /* The only remaining cases are when OP is a constant. If the host and | |
1580 | target floating formats are the same, handling two-word floating | |
1581 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} | |
1582 | are defined as returning one or two 32 bit values, respectively, | |
1583 | and not values of BITS_PER_WORD bits. */ | |
1584 | return constant_subword (op, offset, mode); | |
1585 | } | |
1586 | ||
1587 | /* If OP is already an integer word, return it. */ | |
1588 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1589 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1590 | return op; | |
1591 | ||
1592 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1593 | if (GET_CODE (op) == REG) | |
1594 | { | |
1595 | if (REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1596 | { | |
1597 | int final_regno = REGNO (op) + | |
1598 | subreg_regno_offset (REGNO (op), GET_MODE (op), | |
1599 | offset * UNITS_PER_WORD, | |
1600 | word_mode); | |
1601 | ||
1602 | /* If the register is not valid for MODE, return 0. If we don't | |
1603 | do this, there is no way to fix up the resulting REG later. */ | |
1604 | if (! HARD_REGNO_MODE_OK (final_regno, word_mode)) | |
1605 | return 0; | |
1606 | ||
1607 | /* integrate.c can't handle parts of a return value register. | |
1608 | ??? Then integrate.c should be fixed! | |
1609 | ??? What about CLASS_CANNOT_CHANGE_SIZE? */ | |
1610 | if ((! REG_FUNCTION_VALUE_P (op) | |
1611 | || ! rtx_equal_function_value_matters) | |
1612 | /* ??? What about CLASS_CANNOT_CHANGE_SIZE? */ | |
1613 | /* We want to keep the stack, frame, and arg pointers | |
1614 | special. */ | |
1615 | && op != frame_pointer_rtx | |
1616 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
1617 | && op != arg_pointer_rtx | |
1618 | #endif | |
1619 | && op != stack_pointer_rtx) | |
1620 | return gen_rtx_REG (word_mode, final_regno); | |
1621 | } | |
1622 | ||
1623 | /* Just return a normal SUBREG. */ | |
1624 | return gen_rtx_SUBREG (word_mode, op, | |
1625 | (offset * UNITS_PER_WORD)); | |
1626 | } | |
1627 | else if (GET_CODE (op) == SUBREG) | |
1628 | { | |
1629 | int final_offset = ((offset * UNITS_PER_WORD) + SUBREG_BYTE (op)); | |
1630 | ||
1631 | /* When working with SUBREGs the rule is that the byte | |
1632 | offset must be a multiple of the SUBREG's mode. */ | |
1633 | final_offset = (final_offset / GET_MODE_SIZE (word_mode)); | |
1634 | final_offset = (final_offset * GET_MODE_SIZE (word_mode)); | |
1635 | return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), final_offset); | |
1636 | } | |
1637 | else if (GET_CODE (op) == CONCAT) | |
1638 | { | |
1639 | unsigned int partwords = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1640 | if (offset < partwords) | |
1641 | return operand_subword (XEXP (op, 0), offset, validate_address, mode); | |
1642 | return operand_subword (XEXP (op, 1), offset - partwords, | |
1643 | validate_address, mode); | |
1644 | } | |
1645 | ||
1646 | /* Form a new MEM at the requested address. */ | |
1647 | if (GET_CODE (op) == MEM) | |
1648 | { | |
1649 | rtx addr = plus_constant (XEXP (op, 0), (offset * UNITS_PER_WORD)); | |
1650 | rtx new; | |
1651 | ||
1652 | if (validate_address) | |
1653 | { | |
1654 | if (reload_completed) | |
1655 | { | |
1656 | if (! strict_memory_address_p (word_mode, addr)) | |
1657 | return 0; | |
1658 | } | |
1659 | else | |
1660 | addr = memory_address (word_mode, addr); | |
1661 | } | |
1662 | ||
1663 | new = gen_rtx_MEM (word_mode, addr); | |
1664 | MEM_COPY_ATTRIBUTES (new, op); | |
1665 | return new; | |
1666 | } | |
1667 | ||
1668 | /* Unreachable... (famous last words) */ | |
1669 | abort (); | |
1670 | } | |
1671 | ||
23b2ce53 RS |
1672 | /* Similar to `operand_subword', but never return 0. If we can't extract |
1673 | the required subword, put OP into a register and try again. If that fails, | |
ddef6bc7 | 1674 | abort. We always validate the address in this case. |
23b2ce53 RS |
1675 | |
1676 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1677 | ||
1678 | rtx | |
ddef6bc7 | 1679 | operand_subword_force (op, offset, mode) |
23b2ce53 | 1680 | rtx op; |
ddef6bc7 | 1681 | unsigned int offset; |
23b2ce53 RS |
1682 | enum machine_mode mode; |
1683 | { | |
ddef6bc7 | 1684 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1685 | |
1686 | if (result) | |
1687 | return result; | |
1688 | ||
1689 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1690 | { |
1691 | /* If this is a register which can not be accessed by words, copy it | |
1692 | to a pseudo register. */ | |
1693 | if (GET_CODE (op) == REG) | |
1694 | op = copy_to_reg (op); | |
1695 | else | |
1696 | op = force_reg (mode, op); | |
1697 | } | |
23b2ce53 | 1698 | |
ddef6bc7 | 1699 | result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1700 | if (result == 0) |
1701 | abort (); | |
1702 | ||
1703 | return result; | |
1704 | } | |
1705 | \f | |
1706 | /* Given a compare instruction, swap the operands. | |
1707 | A test instruction is changed into a compare of 0 against the operand. */ | |
1708 | ||
1709 | void | |
1710 | reverse_comparison (insn) | |
1711 | rtx insn; | |
1712 | { | |
1713 | rtx body = PATTERN (insn); | |
1714 | rtx comp; | |
1715 | ||
1716 | if (GET_CODE (body) == SET) | |
1717 | comp = SET_SRC (body); | |
1718 | else | |
1719 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1720 | ||
1721 | if (GET_CODE (comp) == COMPARE) | |
1722 | { | |
1723 | rtx op0 = XEXP (comp, 0); | |
1724 | rtx op1 = XEXP (comp, 1); | |
1725 | XEXP (comp, 0) = op1; | |
1726 | XEXP (comp, 1) = op0; | |
1727 | } | |
1728 | else | |
1729 | { | |
c5c76735 JL |
1730 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1731 | CONST0_RTX (GET_MODE (comp)), comp); | |
23b2ce53 RS |
1732 | if (GET_CODE (body) == SET) |
1733 | SET_SRC (body) = new; | |
1734 | else | |
1735 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1736 | } | |
1737 | } | |
1738 | \f | |
1739 | /* Return a memory reference like MEMREF, but with its mode changed | |
1740 | to MODE and its address changed to ADDR. | |
1741 | (VOIDmode means don't change the mode. | |
1742 | NULL for ADDR means don't change the address.) */ | |
1743 | ||
1744 | rtx | |
1745 | change_address (memref, mode, addr) | |
1746 | rtx memref; | |
1747 | enum machine_mode mode; | |
1748 | rtx addr; | |
1749 | { | |
1750 | rtx new; | |
1751 | ||
1752 | if (GET_CODE (memref) != MEM) | |
1753 | abort (); | |
1754 | if (mode == VOIDmode) | |
1755 | mode = GET_MODE (memref); | |
1756 | if (addr == 0) | |
1757 | addr = XEXP (memref, 0); | |
1758 | ||
1759 | /* If reload is in progress or has completed, ADDR must be valid. | |
1760 | Otherwise, we can call memory_address to make it valid. */ | |
1761 | if (reload_completed || reload_in_progress) | |
1762 | { | |
1763 | if (! memory_address_p (mode, addr)) | |
1764 | abort (); | |
1765 | } | |
1766 | else | |
1767 | addr = memory_address (mode, addr); | |
1768 | ||
9b04c6a8 RK |
1769 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1770 | return memref; | |
1771 | ||
3b80f6ca | 1772 | new = gen_rtx_MEM (mode, addr); |
c6df88cb | 1773 | MEM_COPY_ATTRIBUTES (new, memref); |
23b2ce53 RS |
1774 | return new; |
1775 | } | |
1776 | \f | |
1777 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1778 | ||
1779 | rtx | |
1780 | gen_label_rtx () | |
1781 | { | |
ca695ac9 JB |
1782 | register rtx label; |
1783 | ||
b93a436e | 1784 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
8cd0faaf | 1785 | NULL_RTX, label_num++, NULL_PTR, NULL_PTR); |
ca695ac9 | 1786 | |
23b2ce53 | 1787 | LABEL_NUSES (label) = 0; |
8cd0faaf | 1788 | LABEL_ALTERNATE_NAME (label) = NULL; |
23b2ce53 RS |
1789 | return label; |
1790 | } | |
1791 | \f | |
1792 | /* For procedure integration. */ | |
1793 | ||
23b2ce53 | 1794 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 1795 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
1796 | Used for an inline-procedure after copying the insn chain. */ |
1797 | ||
1798 | void | |
1799 | set_new_first_and_last_insn (first, last) | |
1800 | rtx first, last; | |
1801 | { | |
86fe05e0 RK |
1802 | rtx insn; |
1803 | ||
23b2ce53 RS |
1804 | first_insn = first; |
1805 | last_insn = last; | |
86fe05e0 RK |
1806 | cur_insn_uid = 0; |
1807 | ||
1808 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1809 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1810 | ||
1811 | cur_insn_uid++; | |
23b2ce53 RS |
1812 | } |
1813 | ||
1814 | /* Set the range of label numbers found in the current function. | |
1815 | This is used when belatedly compiling an inline function. */ | |
1816 | ||
1817 | void | |
1818 | set_new_first_and_last_label_num (first, last) | |
1819 | int first, last; | |
1820 | { | |
1821 | base_label_num = label_num; | |
1822 | first_label_num = first; | |
1823 | last_label_num = last; | |
1824 | } | |
49ad7cfa BS |
1825 | |
1826 | /* Set the last label number found in the current function. | |
1827 | This is used when belatedly compiling an inline function. */ | |
23b2ce53 RS |
1828 | |
1829 | void | |
49ad7cfa BS |
1830 | set_new_last_label_num (last) |
1831 | int last; | |
23b2ce53 | 1832 | { |
49ad7cfa BS |
1833 | base_label_num = label_num; |
1834 | last_label_num = last; | |
23b2ce53 | 1835 | } |
49ad7cfa | 1836 | \f |
23b2ce53 RS |
1837 | /* Restore all variables describing the current status from the structure *P. |
1838 | This is used after a nested function. */ | |
1839 | ||
1840 | void | |
1841 | restore_emit_status (p) | |
272df862 | 1842 | struct function *p ATTRIBUTE_UNUSED; |
23b2ce53 | 1843 | { |
457a2d9c | 1844 | last_label_num = 0; |
49ad7cfa | 1845 | clear_emit_caches (); |
23b2ce53 | 1846 | } |
e2ecd91c | 1847 | |
21cd906e | 1848 | /* Clear out all parts of the state in F that can safely be discarded |
e2ecd91c | 1849 | after the function has been compiled, to let garbage collection |
0a8a198c | 1850 | reclaim the memory. */ |
21cd906e | 1851 | |
e2ecd91c | 1852 | void |
0a8a198c | 1853 | free_emit_status (f) |
e2ecd91c BS |
1854 | struct function *f; |
1855 | { | |
1856 | free (f->emit->x_regno_reg_rtx); | |
e2ecd91c | 1857 | free (f->emit->regno_pointer_align); |
fa51b01b RH |
1858 | free (f->emit); |
1859 | f->emit = NULL; | |
e2ecd91c | 1860 | } |
23b2ce53 | 1861 | \f |
d1b81779 GK |
1862 | /* Go through all the RTL insn bodies and copy any invalid shared |
1863 | structure. This routine should only be called once. */ | |
23b2ce53 RS |
1864 | |
1865 | void | |
d1b81779 GK |
1866 | unshare_all_rtl (fndecl, insn) |
1867 | tree fndecl; | |
1868 | rtx insn; | |
23b2ce53 | 1869 | { |
d1b81779 | 1870 | tree decl; |
23b2ce53 | 1871 | |
d1b81779 GK |
1872 | /* Make sure that virtual parameters are not shared. */ |
1873 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
19e7881c | 1874 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); |
d1b81779 | 1875 | |
5c6df058 AO |
1876 | /* Make sure that virtual stack slots are not shared. */ |
1877 | unshare_all_decls (DECL_INITIAL (fndecl)); | |
1878 | ||
d1b81779 GK |
1879 | /* Unshare just about everything else. */ |
1880 | unshare_all_rtl_1 (insn); | |
1881 | ||
23b2ce53 RS |
1882 | /* Make sure the addresses of stack slots found outside the insn chain |
1883 | (such as, in DECL_RTL of a variable) are not shared | |
1884 | with the insn chain. | |
1885 | ||
1886 | This special care is necessary when the stack slot MEM does not | |
1887 | actually appear in the insn chain. If it does appear, its address | |
1888 | is unshared from all else at that point. */ | |
242b0ce6 | 1889 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
1890 | } |
1891 | ||
d1b81779 GK |
1892 | /* Go through all the RTL insn bodies and copy any invalid shared |
1893 | structure, again. This is a fairly expensive thing to do so it | |
1894 | should be done sparingly. */ | |
1895 | ||
1896 | void | |
1897 | unshare_all_rtl_again (insn) | |
1898 | rtx insn; | |
1899 | { | |
1900 | rtx p; | |
624c87aa RE |
1901 | tree decl; |
1902 | ||
d1b81779 | 1903 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 1904 | if (INSN_P (p)) |
d1b81779 GK |
1905 | { |
1906 | reset_used_flags (PATTERN (p)); | |
1907 | reset_used_flags (REG_NOTES (p)); | |
1908 | reset_used_flags (LOG_LINKS (p)); | |
1909 | } | |
624c87aa | 1910 | |
2d4aecb3 AO |
1911 | /* Make sure that virtual stack slots are not shared. */ |
1912 | reset_used_decls (DECL_INITIAL (cfun->decl)); | |
1913 | ||
624c87aa RE |
1914 | /* Make sure that virtual parameters are not shared. */ |
1915 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
1916 | reset_used_flags (DECL_RTL (decl)); | |
1917 | ||
1918 | reset_used_flags (stack_slot_list); | |
1919 | ||
1920 | unshare_all_rtl (cfun->decl, insn); | |
d1b81779 GK |
1921 | } |
1922 | ||
1923 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1924 | Assumes the mark bits are cleared at entry. */ | |
1925 | ||
1926 | static void | |
1927 | unshare_all_rtl_1 (insn) | |
1928 | rtx insn; | |
1929 | { | |
1930 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1931 | if (INSN_P (insn)) |
d1b81779 GK |
1932 | { |
1933 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1934 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1935 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1936 | } | |
1937 | } | |
1938 | ||
5c6df058 AO |
1939 | /* Go through all virtual stack slots of a function and copy any |
1940 | shared structure. */ | |
1941 | static void | |
1942 | unshare_all_decls (blk) | |
1943 | tree blk; | |
1944 | { | |
1945 | tree t; | |
1946 | ||
1947 | /* Copy shared decls. */ | |
1948 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c MM |
1949 | if (DECL_RTL_SET_P (t)) |
1950 | SET_DECL_RTL (t, copy_rtx_if_shared (DECL_RTL (t))); | |
5c6df058 AO |
1951 | |
1952 | /* Now process sub-blocks. */ | |
1953 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1954 | unshare_all_decls (t); | |
1955 | } | |
1956 | ||
2d4aecb3 AO |
1957 | /* Go through all virtual stack slots of a function and mark them as |
1958 | not shared. */ | |
1959 | static void | |
1960 | reset_used_decls (blk) | |
1961 | tree blk; | |
1962 | { | |
1963 | tree t; | |
1964 | ||
1965 | /* Mark decls. */ | |
1966 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c MM |
1967 | if (DECL_RTL_SET_P (t)) |
1968 | reset_used_flags (DECL_RTL (t)); | |
2d4aecb3 AO |
1969 | |
1970 | /* Now process sub-blocks. */ | |
1971 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1972 | reset_used_decls (t); | |
1973 | } | |
1974 | ||
23b2ce53 RS |
1975 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1976 | Recursively does the same for subexpressions. */ | |
1977 | ||
1978 | rtx | |
1979 | copy_rtx_if_shared (orig) | |
1980 | rtx orig; | |
1981 | { | |
1982 | register rtx x = orig; | |
1983 | register int i; | |
1984 | register enum rtx_code code; | |
6f7d635c | 1985 | register const char *format_ptr; |
23b2ce53 RS |
1986 | int copied = 0; |
1987 | ||
1988 | if (x == 0) | |
1989 | return 0; | |
1990 | ||
1991 | code = GET_CODE (x); | |
1992 | ||
1993 | /* These types may be freely shared. */ | |
1994 | ||
1995 | switch (code) | |
1996 | { | |
1997 | case REG: | |
1998 | case QUEUED: | |
1999 | case CONST_INT: | |
2000 | case CONST_DOUBLE: | |
2001 | case SYMBOL_REF: | |
2002 | case CODE_LABEL: | |
2003 | case PC: | |
2004 | case CC0: | |
2005 | case SCRATCH: | |
0f41302f | 2006 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
2007 | return x; |
2008 | ||
b851ea09 RK |
2009 | case CONST: |
2010 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
2011 | a LABEL_REF, it isn't sharable. */ | |
2012 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2013 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2014 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
2015 | return x; | |
2016 | break; | |
2017 | ||
23b2ce53 RS |
2018 | case INSN: |
2019 | case JUMP_INSN: | |
2020 | case CALL_INSN: | |
2021 | case NOTE: | |
23b2ce53 RS |
2022 | case BARRIER: |
2023 | /* The chain of insns is not being copied. */ | |
2024 | return x; | |
2025 | ||
2026 | case MEM: | |
83512665 JL |
2027 | /* A MEM is allowed to be shared if its address is constant. |
2028 | ||
2029 | We used to allow sharing of MEMs which referenced | |
2030 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but | |
2031 | that can lose. instantiate_virtual_regs will not unshare | |
2032 | the MEMs, and combine may change the structure of the address | |
2033 | because it looks safe and profitable in one context, but | |
2034 | in some other context it creates unrecognizable RTL. */ | |
2035 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
23b2ce53 RS |
2036 | return x; |
2037 | ||
e9a25f70 JL |
2038 | break; |
2039 | ||
2040 | default: | |
2041 | break; | |
23b2ce53 RS |
2042 | } |
2043 | ||
2044 | /* This rtx may not be shared. If it has already been seen, | |
2045 | replace it with a copy of itself. */ | |
2046 | ||
2047 | if (x->used) | |
2048 | { | |
2049 | register rtx copy; | |
2050 | ||
2051 | copy = rtx_alloc (code); | |
4e135bdd | 2052 | memcpy (copy, x, |
4c9a05bc RK |
2053 | (sizeof (*copy) - sizeof (copy->fld) |
2054 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
2055 | x = copy; |
2056 | copied = 1; | |
2057 | } | |
2058 | x->used = 1; | |
2059 | ||
2060 | /* Now scan the subexpressions recursively. | |
2061 | We can store any replaced subexpressions directly into X | |
2062 | since we know X is not shared! Any vectors in X | |
2063 | must be copied if X was copied. */ | |
2064 | ||
2065 | format_ptr = GET_RTX_FORMAT (code); | |
2066 | ||
2067 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2068 | { | |
2069 | switch (*format_ptr++) | |
2070 | { | |
2071 | case 'e': | |
2072 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
2073 | break; | |
2074 | ||
2075 | case 'E': | |
2076 | if (XVEC (x, i) != NULL) | |
2077 | { | |
2078 | register int j; | |
f0722107 | 2079 | int len = XVECLEN (x, i); |
23b2ce53 | 2080 | |
f0722107 | 2081 | if (copied && len > 0) |
8f985ec4 | 2082 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
f0722107 RS |
2083 | for (j = 0; j < len; j++) |
2084 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
2085 | } |
2086 | break; | |
2087 | } | |
2088 | } | |
2089 | return x; | |
2090 | } | |
2091 | ||
2092 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2093 | to look for shared sub-parts. */ | |
2094 | ||
2095 | void | |
2096 | reset_used_flags (x) | |
2097 | rtx x; | |
2098 | { | |
2099 | register int i, j; | |
2100 | register enum rtx_code code; | |
6f7d635c | 2101 | register const char *format_ptr; |
23b2ce53 RS |
2102 | |
2103 | if (x == 0) | |
2104 | return; | |
2105 | ||
2106 | code = GET_CODE (x); | |
2107 | ||
9faa82d8 | 2108 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2109 | for them. */ |
2110 | ||
2111 | switch (code) | |
2112 | { | |
2113 | case REG: | |
2114 | case QUEUED: | |
2115 | case CONST_INT: | |
2116 | case CONST_DOUBLE: | |
2117 | case SYMBOL_REF: | |
2118 | case CODE_LABEL: | |
2119 | case PC: | |
2120 | case CC0: | |
2121 | return; | |
2122 | ||
2123 | case INSN: | |
2124 | case JUMP_INSN: | |
2125 | case CALL_INSN: | |
2126 | case NOTE: | |
2127 | case LABEL_REF: | |
2128 | case BARRIER: | |
2129 | /* The chain of insns is not being copied. */ | |
2130 | return; | |
e9a25f70 JL |
2131 | |
2132 | default: | |
2133 | break; | |
23b2ce53 RS |
2134 | } |
2135 | ||
2136 | x->used = 0; | |
2137 | ||
2138 | format_ptr = GET_RTX_FORMAT (code); | |
2139 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2140 | { | |
2141 | switch (*format_ptr++) | |
2142 | { | |
2143 | case 'e': | |
2144 | reset_used_flags (XEXP (x, i)); | |
2145 | break; | |
2146 | ||
2147 | case 'E': | |
2148 | for (j = 0; j < XVECLEN (x, i); j++) | |
2149 | reset_used_flags (XVECEXP (x, i, j)); | |
2150 | break; | |
2151 | } | |
2152 | } | |
2153 | } | |
2154 | \f | |
2155 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2156 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2157 | OTHER must be valid as a SET_DEST. */ | |
2158 | ||
2159 | rtx | |
2160 | make_safe_from (x, other) | |
2161 | rtx x, other; | |
2162 | { | |
2163 | while (1) | |
2164 | switch (GET_CODE (other)) | |
2165 | { | |
2166 | case SUBREG: | |
2167 | other = SUBREG_REG (other); | |
2168 | break; | |
2169 | case STRICT_LOW_PART: | |
2170 | case SIGN_EXTEND: | |
2171 | case ZERO_EXTEND: | |
2172 | other = XEXP (other, 0); | |
2173 | break; | |
2174 | default: | |
2175 | goto done; | |
2176 | } | |
2177 | done: | |
2178 | if ((GET_CODE (other) == MEM | |
2179 | && ! CONSTANT_P (x) | |
2180 | && GET_CODE (x) != REG | |
2181 | && GET_CODE (x) != SUBREG) | |
2182 | || (GET_CODE (other) == REG | |
2183 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
2184 | || reg_mentioned_p (other, x)))) | |
2185 | { | |
2186 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2187 | emit_move_insn (temp, x); | |
2188 | return temp; | |
2189 | } | |
2190 | return x; | |
2191 | } | |
2192 | \f | |
2193 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2194 | ||
2195 | /* Return the first insn of the current sequence or current function. */ | |
2196 | ||
2197 | rtx | |
2198 | get_insns () | |
2199 | { | |
2200 | return first_insn; | |
2201 | } | |
2202 | ||
2203 | /* Return the last insn emitted in current sequence or current function. */ | |
2204 | ||
2205 | rtx | |
2206 | get_last_insn () | |
2207 | { | |
2208 | return last_insn; | |
2209 | } | |
2210 | ||
2211 | /* Specify a new insn as the last in the chain. */ | |
2212 | ||
2213 | void | |
2214 | set_last_insn (insn) | |
2215 | rtx insn; | |
2216 | { | |
2217 | if (NEXT_INSN (insn) != 0) | |
2218 | abort (); | |
2219 | last_insn = insn; | |
2220 | } | |
2221 | ||
2222 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2223 | ||
2224 | rtx | |
2225 | get_last_insn_anywhere () | |
2226 | { | |
2227 | struct sequence_stack *stack; | |
2228 | if (last_insn) | |
2229 | return last_insn; | |
49ad7cfa | 2230 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2231 | if (stack->last != 0) |
2232 | return stack->last; | |
2233 | return 0; | |
2234 | } | |
2235 | ||
2236 | /* Return a number larger than any instruction's uid in this function. */ | |
2237 | ||
2238 | int | |
2239 | get_max_uid () | |
2240 | { | |
2241 | return cur_insn_uid; | |
2242 | } | |
aeeeda03 | 2243 | |
673b5311 MM |
2244 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2245 | ||
aeeeda03 | 2246 | void |
673b5311 MM |
2247 | renumber_insns (stream) |
2248 | FILE *stream; | |
aeeeda03 MM |
2249 | { |
2250 | rtx insn; | |
aeeeda03 | 2251 | |
673b5311 MM |
2252 | /* If we're not supposed to renumber instructions, don't. */ |
2253 | if (!flag_renumber_insns) | |
2254 | return; | |
2255 | ||
aeeeda03 MM |
2256 | /* If there aren't that many instructions, then it's not really |
2257 | worth renumbering them. */ | |
673b5311 | 2258 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
aeeeda03 MM |
2259 | return; |
2260 | ||
2261 | cur_insn_uid = 1; | |
2262 | ||
2263 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
673b5311 MM |
2264 | { |
2265 | if (stream) | |
2266 | fprintf (stream, "Renumbering insn %d to %d\n", | |
2267 | INSN_UID (insn), cur_insn_uid); | |
2268 | INSN_UID (insn) = cur_insn_uid++; | |
2269 | } | |
aeeeda03 | 2270 | } |
23b2ce53 RS |
2271 | \f |
2272 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2273 | of the sequence. */ | |
2274 | ||
2275 | rtx | |
2276 | next_insn (insn) | |
2277 | rtx insn; | |
2278 | { | |
2279 | if (insn) | |
2280 | { | |
2281 | insn = NEXT_INSN (insn); | |
2282 | if (insn && GET_CODE (insn) == INSN | |
2283 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2284 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2285 | } | |
2286 | ||
2287 | return insn; | |
2288 | } | |
2289 | ||
2290 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2291 | of the sequence. */ | |
2292 | ||
2293 | rtx | |
2294 | previous_insn (insn) | |
2295 | rtx insn; | |
2296 | { | |
2297 | if (insn) | |
2298 | { | |
2299 | insn = PREV_INSN (insn); | |
2300 | if (insn && GET_CODE (insn) == INSN | |
2301 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2302 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2303 | } | |
2304 | ||
2305 | return insn; | |
2306 | } | |
2307 | ||
2308 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2309 | look inside SEQUENCEs. */ | |
2310 | ||
2311 | rtx | |
2312 | next_nonnote_insn (insn) | |
2313 | rtx insn; | |
2314 | { | |
2315 | while (insn) | |
2316 | { | |
2317 | insn = NEXT_INSN (insn); | |
2318 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2319 | break; | |
2320 | } | |
2321 | ||
2322 | return insn; | |
2323 | } | |
2324 | ||
2325 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2326 | not look inside SEQUENCEs. */ | |
2327 | ||
2328 | rtx | |
2329 | prev_nonnote_insn (insn) | |
2330 | rtx insn; | |
2331 | { | |
2332 | while (insn) | |
2333 | { | |
2334 | insn = PREV_INSN (insn); | |
2335 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2336 | break; | |
2337 | } | |
2338 | ||
2339 | return insn; | |
2340 | } | |
2341 | ||
2342 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2343 | or 0, if there is none. This routine does not look inside | |
0f41302f | 2344 | SEQUENCEs. */ |
23b2ce53 RS |
2345 | |
2346 | rtx | |
2347 | next_real_insn (insn) | |
2348 | rtx insn; | |
2349 | { | |
2350 | while (insn) | |
2351 | { | |
2352 | insn = NEXT_INSN (insn); | |
2353 | if (insn == 0 || GET_CODE (insn) == INSN | |
2354 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2355 | break; | |
2356 | } | |
2357 | ||
2358 | return insn; | |
2359 | } | |
2360 | ||
2361 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2362 | or 0, if there is none. This routine does not look inside | |
2363 | SEQUENCEs. */ | |
2364 | ||
2365 | rtx | |
2366 | prev_real_insn (insn) | |
2367 | rtx insn; | |
2368 | { | |
2369 | while (insn) | |
2370 | { | |
2371 | insn = PREV_INSN (insn); | |
2372 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2373 | || GET_CODE (insn) == JUMP_INSN) | |
2374 | break; | |
2375 | } | |
2376 | ||
2377 | return insn; | |
2378 | } | |
2379 | ||
2380 | /* Find the next insn after INSN that really does something. This routine | |
2381 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2382 | same as next_real_insn. */ | |
2383 | ||
69732dcb RH |
2384 | int |
2385 | active_insn_p (insn) | |
2386 | rtx insn; | |
2387 | { | |
2388 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2389 | || (GET_CODE (insn) == INSN | |
2390 | && (! reload_completed | |
2391 | || (GET_CODE (PATTERN (insn)) != USE | |
2392 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2393 | } | |
2394 | ||
23b2ce53 RS |
2395 | rtx |
2396 | next_active_insn (insn) | |
2397 | rtx insn; | |
2398 | { | |
2399 | while (insn) | |
2400 | { | |
2401 | insn = NEXT_INSN (insn); | |
69732dcb | 2402 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2403 | break; |
2404 | } | |
2405 | ||
2406 | return insn; | |
2407 | } | |
2408 | ||
2409 | /* Find the last insn before INSN that really does something. This routine | |
2410 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2411 | same as prev_real_insn. */ | |
2412 | ||
2413 | rtx | |
2414 | prev_active_insn (insn) | |
2415 | rtx insn; | |
2416 | { | |
2417 | while (insn) | |
2418 | { | |
2419 | insn = PREV_INSN (insn); | |
69732dcb | 2420 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2421 | break; |
2422 | } | |
2423 | ||
2424 | return insn; | |
2425 | } | |
2426 | ||
2427 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2428 | ||
2429 | rtx | |
2430 | next_label (insn) | |
2431 | rtx insn; | |
2432 | { | |
2433 | while (insn) | |
2434 | { | |
2435 | insn = NEXT_INSN (insn); | |
2436 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2437 | break; | |
2438 | } | |
2439 | ||
2440 | return insn; | |
2441 | } | |
2442 | ||
2443 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2444 | ||
2445 | rtx | |
2446 | prev_label (insn) | |
2447 | rtx insn; | |
2448 | { | |
2449 | while (insn) | |
2450 | { | |
2451 | insn = PREV_INSN (insn); | |
2452 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2453 | break; | |
2454 | } | |
2455 | ||
2456 | return insn; | |
2457 | } | |
2458 | \f | |
2459 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
2460 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2461 | and REG_CC_USER notes so we can find it. */ | |
2462 | ||
2463 | void | |
2464 | link_cc0_insns (insn) | |
2465 | rtx insn; | |
2466 | { | |
2467 | rtx user = next_nonnote_insn (insn); | |
2468 | ||
2469 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2470 | user = XVECEXP (PATTERN (user), 0, 0); | |
2471 | ||
c5c76735 JL |
2472 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2473 | REG_NOTES (user)); | |
3b80f6ca | 2474 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
2475 | } |
2476 | ||
23b2ce53 RS |
2477 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2478 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2479 | applied to the result of this function should yield INSN). | |
2480 | ||
2481 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2482 | is present, it contains the insn that uses CC0. | |
2483 | ||
2484 | Return 0 if we can't find the insn. */ | |
2485 | ||
2486 | rtx | |
2487 | next_cc0_user (insn) | |
2488 | rtx insn; | |
2489 | { | |
906c4e36 | 2490 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
2491 | |
2492 | if (note) | |
2493 | return XEXP (note, 0); | |
2494 | ||
2495 | insn = next_nonnote_insn (insn); | |
2496 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2497 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2498 | ||
2c3c49de | 2499 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
2500 | return insn; |
2501 | ||
2502 | return 0; | |
2503 | } | |
2504 | ||
2505 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2506 | note, it is the previous insn. */ | |
2507 | ||
2508 | rtx | |
2509 | prev_cc0_setter (insn) | |
2510 | rtx insn; | |
2511 | { | |
906c4e36 | 2512 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
2513 | |
2514 | if (note) | |
2515 | return XEXP (note, 0); | |
2516 | ||
2517 | insn = prev_nonnote_insn (insn); | |
2518 | if (! sets_cc0_p (PATTERN (insn))) | |
2519 | abort (); | |
2520 | ||
2521 | return insn; | |
2522 | } | |
2523 | #endif | |
2524 | \f | |
2525 | /* Try splitting insns that can be split for better scheduling. | |
2526 | PAT is the pattern which might split. | |
2527 | TRIAL is the insn providing PAT. | |
11147ebe | 2528 | LAST is non-zero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
2529 | |
2530 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 2531 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
2532 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2533 | ||
2534 | rtx | |
11147ebe | 2535 | try_split (pat, trial, last) |
23b2ce53 | 2536 | rtx pat, trial; |
11147ebe | 2537 | int last; |
23b2ce53 RS |
2538 | { |
2539 | rtx before = PREV_INSN (trial); | |
2540 | rtx after = NEXT_INSN (trial); | |
2541 | rtx seq = split_insns (pat, trial); | |
2542 | int has_barrier = 0; | |
2543 | rtx tem; | |
2544 | ||
2545 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2546 | We may need to handle this specially. */ | |
2547 | if (after && GET_CODE (after) == BARRIER) | |
2548 | { | |
2549 | has_barrier = 1; | |
2550 | after = NEXT_INSN (after); | |
2551 | } | |
2552 | ||
2553 | if (seq) | |
2554 | { | |
2555 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2556 | The latter case will normally arise only when being done so that | |
2557 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2558 | if (GET_CODE (seq) == SEQUENCE) | |
2559 | { | |
4b5e8abe CP |
2560 | int i; |
2561 | ||
2562 | /* Avoid infinite loop if any insn of the result matches | |
2563 | the original pattern. */ | |
2564 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2565 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN | |
2566 | && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat)) | |
2567 | return trial; | |
2568 | ||
90a74703 JH |
2569 | /* Mark labels. */ |
2570 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2571 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2572 | mark_jump_label (PATTERN (XVECEXP (seq, 0, i)), | |
2573 | XVECEXP (seq, 0, i), 0, 0); | |
23b2ce53 | 2574 | |
2d01e445 AO |
2575 | /* If we are splitting a CALL_INSN, look for the CALL_INSN |
2576 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
2577 | if (GET_CODE (trial) == CALL_INSN) | |
2578 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2579 | if (GET_CODE (XVECEXP (seq, 0, i)) == CALL_INSN) | |
2580 | CALL_INSN_FUNCTION_USAGE (XVECEXP (seq, 0, i)) | |
2581 | = CALL_INSN_FUNCTION_USAGE (trial); | |
2582 | ||
23b2ce53 RS |
2583 | tem = emit_insn_after (seq, before); |
2584 | ||
2585 | delete_insn (trial); | |
2586 | if (has_barrier) | |
2587 | emit_barrier_after (tem); | |
11147ebe RK |
2588 | |
2589 | /* Recursively call try_split for each new insn created; by the | |
2590 | time control returns here that insn will be fully split, so | |
2591 | set LAST and continue from the insn after the one returned. | |
f4a3cd05 | 2592 | We can't use next_active_insn here since AFTER may be a note. |
23886015 | 2593 | Ignore deleted insns, which can be occur if not optimizing. */ |
2c3c49de RB |
2594 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) |
2595 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
f4a3cd05 | 2596 | tem = try_split (PATTERN (tem), tem, 1); |
23b2ce53 RS |
2597 | } |
2598 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2599 | else if (rtx_equal_p (seq, pat)) | |
2600 | return trial; | |
2601 | else | |
2602 | { | |
2603 | PATTERN (trial) = seq; | |
2604 | INSN_CODE (trial) = -1; | |
11147ebe | 2605 | try_split (seq, trial, last); |
23b2ce53 RS |
2606 | } |
2607 | ||
11147ebe RK |
2608 | /* Return either the first or the last insn, depending on which was |
2609 | requested. */ | |
ba52f355 CP |
2610 | return last |
2611 | ? (after ? prev_active_insn (after) : last_insn) | |
2612 | : next_active_insn (before); | |
23b2ce53 RS |
2613 | } |
2614 | ||
2615 | return trial; | |
2616 | } | |
2617 | \f | |
2618 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 2619 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
2620 | |
2621 | rtx | |
4b1f5e8c | 2622 | make_insn_raw (pattern) |
23b2ce53 | 2623 | rtx pattern; |
23b2ce53 RS |
2624 | { |
2625 | register rtx insn; | |
2626 | ||
1f8f4a0b | 2627 | insn = rtx_alloc (INSN); |
23b2ce53 | 2628 | |
43127294 | 2629 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2630 | PATTERN (insn) = pattern; |
2631 | INSN_CODE (insn) = -1; | |
1632afca RS |
2632 | LOG_LINKS (insn) = NULL; |
2633 | REG_NOTES (insn) = NULL; | |
23b2ce53 | 2634 | |
47984720 NC |
2635 | #ifdef ENABLE_RTL_CHECKING |
2636 | if (insn | |
2c3c49de | 2637 | && INSN_P (insn) |
47984720 NC |
2638 | && (returnjump_p (insn) |
2639 | || (GET_CODE (insn) == SET | |
2640 | && SET_DEST (insn) == pc_rtx))) | |
2641 | { | |
2642 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2643 | debug_rtx (insn); | |
2644 | } | |
2645 | #endif | |
2646 | ||
23b2ce53 RS |
2647 | return insn; |
2648 | } | |
2649 | ||
2650 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2651 | ||
2652 | static rtx | |
4b1f5e8c | 2653 | make_jump_insn_raw (pattern) |
23b2ce53 | 2654 | rtx pattern; |
23b2ce53 RS |
2655 | { |
2656 | register rtx insn; | |
2657 | ||
4b1f5e8c | 2658 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 2659 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2660 | |
2661 | PATTERN (insn) = pattern; | |
2662 | INSN_CODE (insn) = -1; | |
1632afca RS |
2663 | LOG_LINKS (insn) = NULL; |
2664 | REG_NOTES (insn) = NULL; | |
2665 | JUMP_LABEL (insn) = NULL; | |
23b2ce53 RS |
2666 | |
2667 | return insn; | |
2668 | } | |
aff507f4 RK |
2669 | |
2670 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2671 | ||
2672 | static rtx | |
2673 | make_call_insn_raw (pattern) | |
2674 | rtx pattern; | |
2675 | { | |
2676 | register rtx insn; | |
2677 | ||
2678 | insn = rtx_alloc (CALL_INSN); | |
2679 | INSN_UID (insn) = cur_insn_uid++; | |
2680 | ||
2681 | PATTERN (insn) = pattern; | |
2682 | INSN_CODE (insn) = -1; | |
2683 | LOG_LINKS (insn) = NULL; | |
2684 | REG_NOTES (insn) = NULL; | |
2685 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2686 | ||
2687 | return insn; | |
2688 | } | |
23b2ce53 RS |
2689 | \f |
2690 | /* Add INSN to the end of the doubly-linked list. | |
2691 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2692 | ||
2693 | void | |
2694 | add_insn (insn) | |
2695 | register rtx insn; | |
2696 | { | |
2697 | PREV_INSN (insn) = last_insn; | |
2698 | NEXT_INSN (insn) = 0; | |
2699 | ||
2700 | if (NULL != last_insn) | |
2701 | NEXT_INSN (last_insn) = insn; | |
2702 | ||
2703 | if (NULL == first_insn) | |
2704 | first_insn = insn; | |
2705 | ||
2706 | last_insn = insn; | |
2707 | } | |
2708 | ||
a0ae8e8d RK |
2709 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2710 | the next should be the only functions called to insert an insn once | |
ba213285 | 2711 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 2712 | SEQUENCE. */ |
23b2ce53 RS |
2713 | |
2714 | void | |
2715 | add_insn_after (insn, after) | |
2716 | rtx insn, after; | |
2717 | { | |
2718 | rtx next = NEXT_INSN (after); | |
2719 | ||
6782074d | 2720 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
2721 | abort (); |
2722 | ||
23b2ce53 RS |
2723 | NEXT_INSN (insn) = next; |
2724 | PREV_INSN (insn) = after; | |
2725 | ||
2726 | if (next) | |
2727 | { | |
2728 | PREV_INSN (next) = insn; | |
2729 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2730 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2731 | } | |
2732 | else if (last_insn == after) | |
2733 | last_insn = insn; | |
2734 | else | |
2735 | { | |
49ad7cfa | 2736 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
2737 | /* Scan all pending sequences too. */ |
2738 | for (; stack; stack = stack->next) | |
2739 | if (after == stack->last) | |
fef0509b RK |
2740 | { |
2741 | stack->last = insn; | |
2742 | break; | |
2743 | } | |
a0ae8e8d RK |
2744 | |
2745 | if (stack == 0) | |
2746 | abort (); | |
23b2ce53 RS |
2747 | } |
2748 | ||
2749 | NEXT_INSN (after) = insn; | |
2750 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2751 | { | |
2752 | rtx sequence = PATTERN (after); | |
2753 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2754 | } | |
2755 | } | |
2756 | ||
a0ae8e8d RK |
2757 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2758 | the previous should be the only functions called to insert an insn once | |
ba213285 | 2759 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
2760 | SEQUENCE. */ |
2761 | ||
2762 | void | |
2763 | add_insn_before (insn, before) | |
2764 | rtx insn, before; | |
2765 | { | |
2766 | rtx prev = PREV_INSN (before); | |
2767 | ||
6782074d | 2768 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
2769 | abort (); |
2770 | ||
a0ae8e8d RK |
2771 | PREV_INSN (insn) = prev; |
2772 | NEXT_INSN (insn) = before; | |
2773 | ||
2774 | if (prev) | |
2775 | { | |
2776 | NEXT_INSN (prev) = insn; | |
2777 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2778 | { | |
2779 | rtx sequence = PATTERN (prev); | |
2780 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2781 | } | |
2782 | } | |
2783 | else if (first_insn == before) | |
2784 | first_insn = insn; | |
2785 | else | |
2786 | { | |
49ad7cfa | 2787 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
2788 | /* Scan all pending sequences too. */ |
2789 | for (; stack; stack = stack->next) | |
2790 | if (before == stack->first) | |
fef0509b RK |
2791 | { |
2792 | stack->first = insn; | |
2793 | break; | |
2794 | } | |
a0ae8e8d RK |
2795 | |
2796 | if (stack == 0) | |
2797 | abort (); | |
2798 | } | |
2799 | ||
2800 | PREV_INSN (before) = insn; | |
2801 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2802 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2803 | } | |
2804 | ||
89e99eea DB |
2805 | /* Remove an insn from its doubly-linked list. This function knows how |
2806 | to handle sequences. */ | |
2807 | void | |
2808 | remove_insn (insn) | |
2809 | rtx insn; | |
2810 | { | |
2811 | rtx next = NEXT_INSN (insn); | |
2812 | rtx prev = PREV_INSN (insn); | |
2813 | if (prev) | |
2814 | { | |
2815 | NEXT_INSN (prev) = next; | |
2816 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2817 | { | |
2818 | rtx sequence = PATTERN (prev); | |
2819 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2820 | } | |
2821 | } | |
2822 | else if (first_insn == insn) | |
2823 | first_insn = next; | |
2824 | else | |
2825 | { | |
49ad7cfa | 2826 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2827 | /* Scan all pending sequences too. */ |
2828 | for (; stack; stack = stack->next) | |
2829 | if (insn == stack->first) | |
2830 | { | |
2831 | stack->first = next; | |
2832 | break; | |
2833 | } | |
2834 | ||
2835 | if (stack == 0) | |
2836 | abort (); | |
2837 | } | |
2838 | ||
2839 | if (next) | |
2840 | { | |
2841 | PREV_INSN (next) = prev; | |
2842 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2843 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2844 | } | |
2845 | else if (last_insn == insn) | |
2846 | last_insn = prev; | |
2847 | else | |
2848 | { | |
49ad7cfa | 2849 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2850 | /* Scan all pending sequences too. */ |
2851 | for (; stack; stack = stack->next) | |
2852 | if (insn == stack->last) | |
2853 | { | |
2854 | stack->last = prev; | |
2855 | break; | |
2856 | } | |
2857 | ||
2858 | if (stack == 0) | |
2859 | abort (); | |
2860 | } | |
2861 | } | |
2862 | ||
23b2ce53 RS |
2863 | /* Delete all insns made since FROM. |
2864 | FROM becomes the new last instruction. */ | |
2865 | ||
2866 | void | |
2867 | delete_insns_since (from) | |
2868 | rtx from; | |
2869 | { | |
2870 | if (from == 0) | |
2871 | first_insn = 0; | |
2872 | else | |
2873 | NEXT_INSN (from) = 0; | |
2874 | last_insn = from; | |
2875 | } | |
2876 | ||
5dab5552 MS |
2877 | /* This function is deprecated, please use sequences instead. |
2878 | ||
2879 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
2880 | The insns to be moved are those between FROM and TO. |
2881 | They are moved to a new position after the insn AFTER. | |
2882 | AFTER must not be FROM or TO or any insn in between. | |
2883 | ||
2884 | This function does not know about SEQUENCEs and hence should not be | |
2885 | called after delay-slot filling has been done. */ | |
2886 | ||
2887 | void | |
2888 | reorder_insns (from, to, after) | |
2889 | rtx from, to, after; | |
2890 | { | |
2891 | /* Splice this bunch out of where it is now. */ | |
2892 | if (PREV_INSN (from)) | |
2893 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2894 | if (NEXT_INSN (to)) | |
2895 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2896 | if (last_insn == to) | |
2897 | last_insn = PREV_INSN (from); | |
2898 | if (first_insn == from) | |
2899 | first_insn = NEXT_INSN (to); | |
2900 | ||
2901 | /* Make the new neighbors point to it and it to them. */ | |
2902 | if (NEXT_INSN (after)) | |
2903 | PREV_INSN (NEXT_INSN (after)) = to; | |
2904 | ||
2905 | NEXT_INSN (to) = NEXT_INSN (after); | |
2906 | PREV_INSN (from) = after; | |
2907 | NEXT_INSN (after) = from; | |
2908 | if (after == last_insn) | |
2909 | last_insn = to; | |
2910 | } | |
2911 | ||
2912 | /* Return the line note insn preceding INSN. */ | |
2913 | ||
2914 | static rtx | |
2915 | find_line_note (insn) | |
2916 | rtx insn; | |
2917 | { | |
2918 | if (no_line_numbers) | |
2919 | return 0; | |
2920 | ||
2921 | for (; insn; insn = PREV_INSN (insn)) | |
2922 | if (GET_CODE (insn) == NOTE | |
2923 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2924 | break; | |
2925 | ||
2926 | return insn; | |
2927 | } | |
2928 | ||
2929 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2930 | of the moved insns when debugging. This may insert a note between AFTER | |
2931 | and FROM, and another one after TO. */ | |
2932 | ||
2933 | void | |
2934 | reorder_insns_with_line_notes (from, to, after) | |
2935 | rtx from, to, after; | |
2936 | { | |
2937 | rtx from_line = find_line_note (from); | |
2938 | rtx after_line = find_line_note (after); | |
2939 | ||
2940 | reorder_insns (from, to, after); | |
2941 | ||
2942 | if (from_line == after_line) | |
2943 | return; | |
2944 | ||
2945 | if (from_line) | |
2946 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2947 | NOTE_LINE_NUMBER (from_line), | |
2948 | after); | |
2949 | if (after_line) | |
2950 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2951 | NOTE_LINE_NUMBER (after_line), | |
2952 | to); | |
2953 | } | |
aeeeda03 | 2954 | |
64b59a80 | 2955 | /* Remove unnecessary notes from the instruction stream. */ |
aeeeda03 MM |
2956 | |
2957 | void | |
64b59a80 | 2958 | remove_unnecessary_notes () |
aeeeda03 | 2959 | { |
542d73ae RH |
2960 | rtx block_stack = NULL_RTX; |
2961 | rtx eh_stack = NULL_RTX; | |
aeeeda03 MM |
2962 | rtx insn; |
2963 | rtx next; | |
542d73ae | 2964 | rtx tmp; |
aeeeda03 | 2965 | |
116eebd6 MM |
2966 | /* We must not remove the first instruction in the function because |
2967 | the compiler depends on the first instruction being a note. */ | |
aeeeda03 MM |
2968 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
2969 | { | |
2970 | /* Remember what's next. */ | |
2971 | next = NEXT_INSN (insn); | |
2972 | ||
2973 | /* We're only interested in notes. */ | |
2974 | if (GET_CODE (insn) != NOTE) | |
2975 | continue; | |
2976 | ||
542d73ae | 2977 | switch (NOTE_LINE_NUMBER (insn)) |
18c038b9 | 2978 | { |
542d73ae RH |
2979 | case NOTE_INSN_DELETED: |
2980 | remove_insn (insn); | |
2981 | break; | |
2982 | ||
2983 | case NOTE_INSN_EH_REGION_BEG: | |
2984 | eh_stack = alloc_INSN_LIST (insn, eh_stack); | |
2985 | break; | |
2986 | ||
2987 | case NOTE_INSN_EH_REGION_END: | |
2988 | /* Too many end notes. */ | |
2989 | if (eh_stack == NULL_RTX) | |
2990 | abort (); | |
2991 | /* Mismatched nesting. */ | |
2992 | if (NOTE_EH_HANDLER (XEXP (eh_stack, 0)) != NOTE_EH_HANDLER (insn)) | |
2993 | abort (); | |
2994 | tmp = eh_stack; | |
2995 | eh_stack = XEXP (eh_stack, 1); | |
2996 | free_INSN_LIST_node (tmp); | |
2997 | break; | |
2998 | ||
2999 | case NOTE_INSN_BLOCK_BEG: | |
3000 | /* By now, all notes indicating lexical blocks should have | |
3001 | NOTE_BLOCK filled in. */ | |
3002 | if (NOTE_BLOCK (insn) == NULL_TREE) | |
3003 | abort (); | |
3004 | block_stack = alloc_INSN_LIST (insn, block_stack); | |
3005 | break; | |
3006 | ||
3007 | case NOTE_INSN_BLOCK_END: | |
3008 | /* Too many end notes. */ | |
3009 | if (block_stack == NULL_RTX) | |
3010 | abort (); | |
3011 | /* Mismatched nesting. */ | |
3012 | if (NOTE_BLOCK (XEXP (block_stack, 0)) != NOTE_BLOCK (insn)) | |
3013 | abort (); | |
3014 | tmp = block_stack; | |
3015 | block_stack = XEXP (block_stack, 1); | |
3016 | free_INSN_LIST_node (tmp); | |
3017 | ||
18c038b9 MM |
3018 | /* Scan back to see if there are any non-note instructions |
3019 | between INSN and the beginning of this block. If not, | |
3020 | then there is no PC range in the generated code that will | |
3021 | actually be in this block, so there's no point in | |
3022 | remembering the existence of the block. */ | |
542d73ae | 3023 | for (tmp = PREV_INSN (insn); tmp ; tmp = PREV_INSN (tmp)) |
18c038b9 MM |
3024 | { |
3025 | /* This block contains a real instruction. Note that we | |
3026 | don't include labels; if the only thing in the block | |
3027 | is a label, then there are still no PC values that | |
3028 | lie within the block. */ | |
542d73ae | 3029 | if (INSN_P (tmp)) |
18c038b9 MM |
3030 | break; |
3031 | ||
3032 | /* We're only interested in NOTEs. */ | |
542d73ae | 3033 | if (GET_CODE (tmp) != NOTE) |
18c038b9 MM |
3034 | continue; |
3035 | ||
542d73ae | 3036 | if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_BEG) |
18c038b9 | 3037 | { |
542d73ae RH |
3038 | /* We just verified that this BLOCK matches us |
3039 | with the block_stack check above. */ | |
64b59a80 | 3040 | if (debug_ignore_block (NOTE_BLOCK (insn))) |
deb5e280 | 3041 | { |
542d73ae | 3042 | remove_insn (tmp); |
deb5e280 JM |
3043 | remove_insn (insn); |
3044 | } | |
18c038b9 MM |
3045 | break; |
3046 | } | |
542d73ae | 3047 | else if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_END) |
18c038b9 MM |
3048 | /* There's a nested block. We need to leave the |
3049 | current block in place since otherwise the debugger | |
3050 | wouldn't be able to show symbols from our block in | |
3051 | the nested block. */ | |
3052 | break; | |
3053 | } | |
3054 | } | |
aeeeda03 | 3055 | } |
542d73ae RH |
3056 | |
3057 | /* Too many begin notes. */ | |
3058 | if (block_stack || eh_stack) | |
3059 | abort (); | |
aeeeda03 MM |
3060 | } |
3061 | ||
23b2ce53 RS |
3062 | \f |
3063 | /* Emit an insn of given code and pattern | |
3064 | at a specified place within the doubly-linked list. */ | |
3065 | ||
3066 | /* Make an instruction with body PATTERN | |
3067 | and output it before the instruction BEFORE. */ | |
3068 | ||
3069 | rtx | |
3070 | emit_insn_before (pattern, before) | |
3071 | register rtx pattern, before; | |
3072 | { | |
3073 | register rtx insn = before; | |
3074 | ||
3075 | if (GET_CODE (pattern) == SEQUENCE) | |
3076 | { | |
3077 | register int i; | |
3078 | ||
3079 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3080 | { | |
3081 | insn = XVECEXP (pattern, 0, i); | |
a0ae8e8d | 3082 | add_insn_before (insn, before); |
23b2ce53 | 3083 | } |
23b2ce53 RS |
3084 | } |
3085 | else | |
3086 | { | |
4b1f5e8c | 3087 | insn = make_insn_raw (pattern); |
a0ae8e8d | 3088 | add_insn_before (insn, before); |
23b2ce53 RS |
3089 | } |
3090 | ||
3091 | return insn; | |
3092 | } | |
3093 | ||
a05924f9 JH |
3094 | /* Similar to emit_insn_before, but update basic block boundaries as well. */ |
3095 | ||
3096 | rtx | |
3097 | emit_block_insn_before (pattern, before, block) | |
3098 | rtx pattern, before; | |
3099 | basic_block block; | |
3100 | { | |
3101 | rtx prev = PREV_INSN (before); | |
3102 | rtx r = emit_insn_before (pattern, before); | |
3103 | if (block && block->head == before) | |
3104 | block->head = NEXT_INSN (prev); | |
3105 | return r; | |
3106 | } | |
3107 | ||
23b2ce53 RS |
3108 | /* Make an instruction with body PATTERN and code JUMP_INSN |
3109 | and output it before the instruction BEFORE. */ | |
3110 | ||
3111 | rtx | |
3112 | emit_jump_insn_before (pattern, before) | |
3113 | register rtx pattern, before; | |
3114 | { | |
3115 | register rtx insn; | |
3116 | ||
3117 | if (GET_CODE (pattern) == SEQUENCE) | |
3118 | insn = emit_insn_before (pattern, before); | |
3119 | else | |
3120 | { | |
85cf32bc | 3121 | insn = make_jump_insn_raw (pattern); |
a0ae8e8d | 3122 | add_insn_before (insn, before); |
23b2ce53 RS |
3123 | } |
3124 | ||
3125 | return insn; | |
3126 | } | |
3127 | ||
3128 | /* Make an instruction with body PATTERN and code CALL_INSN | |
3129 | and output it before the instruction BEFORE. */ | |
3130 | ||
3131 | rtx | |
3132 | emit_call_insn_before (pattern, before) | |
3133 | register rtx pattern, before; | |
3134 | { | |
aff507f4 RK |
3135 | register rtx insn; |
3136 | ||
3137 | if (GET_CODE (pattern) == SEQUENCE) | |
3138 | insn = emit_insn_before (pattern, before); | |
3139 | else | |
3140 | { | |
3141 | insn = make_call_insn_raw (pattern); | |
a0ae8e8d | 3142 | add_insn_before (insn, before); |
aff507f4 RK |
3143 | PUT_CODE (insn, CALL_INSN); |
3144 | } | |
3145 | ||
23b2ce53 RS |
3146 | return insn; |
3147 | } | |
3148 | ||
3149 | /* Make an insn of code BARRIER | |
e881bb1b | 3150 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
3151 | |
3152 | rtx | |
3153 | emit_barrier_before (before) | |
3154 | register rtx before; | |
3155 | { | |
3156 | register rtx insn = rtx_alloc (BARRIER); | |
3157 | ||
3158 | INSN_UID (insn) = cur_insn_uid++; | |
3159 | ||
a0ae8e8d | 3160 | add_insn_before (insn, before); |
23b2ce53 RS |
3161 | return insn; |
3162 | } | |
3163 | ||
e881bb1b RH |
3164 | /* Emit the label LABEL before the insn BEFORE. */ |
3165 | ||
3166 | rtx | |
3167 | emit_label_before (label, before) | |
3168 | rtx label, before; | |
3169 | { | |
3170 | /* This can be called twice for the same label as a result of the | |
3171 | confusion that follows a syntax error! So make it harmless. */ | |
3172 | if (INSN_UID (label) == 0) | |
3173 | { | |
3174 | INSN_UID (label) = cur_insn_uid++; | |
3175 | add_insn_before (label, before); | |
3176 | } | |
3177 | ||
3178 | return label; | |
3179 | } | |
3180 | ||
23b2ce53 RS |
3181 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
3182 | ||
3183 | rtx | |
3184 | emit_note_before (subtype, before) | |
3185 | int subtype; | |
3186 | rtx before; | |
3187 | { | |
3188 | register rtx note = rtx_alloc (NOTE); | |
3189 | INSN_UID (note) = cur_insn_uid++; | |
3190 | NOTE_SOURCE_FILE (note) = 0; | |
3191 | NOTE_LINE_NUMBER (note) = subtype; | |
3192 | ||
a0ae8e8d | 3193 | add_insn_before (note, before); |
23b2ce53 RS |
3194 | return note; |
3195 | } | |
3196 | \f | |
3197 | /* Make an insn of code INSN with body PATTERN | |
3198 | and output it after the insn AFTER. */ | |
3199 | ||
3200 | rtx | |
3201 | emit_insn_after (pattern, after) | |
3202 | register rtx pattern, after; | |
3203 | { | |
3204 | register rtx insn = after; | |
3205 | ||
3206 | if (GET_CODE (pattern) == SEQUENCE) | |
3207 | { | |
3208 | register int i; | |
3209 | ||
3210 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3211 | { | |
3212 | insn = XVECEXP (pattern, 0, i); | |
3213 | add_insn_after (insn, after); | |
3214 | after = insn; | |
3215 | } | |
23b2ce53 RS |
3216 | } |
3217 | else | |
3218 | { | |
4b1f5e8c | 3219 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3220 | add_insn_after (insn, after); |
3221 | } | |
3222 | ||
3223 | return insn; | |
3224 | } | |
3225 | ||
255680cf RK |
3226 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
3227 | as to act as if this insn were at FROM. */ | |
3228 | ||
3229 | void | |
3230 | emit_insn_after_with_line_notes (pattern, after, from) | |
3231 | rtx pattern, after, from; | |
3232 | { | |
3233 | rtx from_line = find_line_note (from); | |
3234 | rtx after_line = find_line_note (after); | |
3235 | rtx insn = emit_insn_after (pattern, after); | |
3236 | ||
3237 | if (from_line) | |
3238 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3239 | NOTE_LINE_NUMBER (from_line), | |
3240 | after); | |
3241 | ||
3242 | if (after_line) | |
3243 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3244 | NOTE_LINE_NUMBER (after_line), | |
3245 | insn); | |
3246 | } | |
3247 | ||
a05924f9 JH |
3248 | /* Similar to emit_insn_after, but update basic block boundaries as well. */ |
3249 | ||
3250 | rtx | |
3251 | emit_block_insn_after (pattern, after, block) | |
3252 | rtx pattern, after; | |
3253 | basic_block block; | |
3254 | { | |
3255 | rtx r = emit_insn_after (pattern, after); | |
3256 | if (block && block->end == after) | |
3257 | block->end = r; | |
3258 | return r; | |
3259 | } | |
3260 | ||
23b2ce53 RS |
3261 | /* Make an insn of code JUMP_INSN with body PATTERN |
3262 | and output it after the insn AFTER. */ | |
3263 | ||
3264 | rtx | |
3265 | emit_jump_insn_after (pattern, after) | |
3266 | register rtx pattern, after; | |
3267 | { | |
3268 | register rtx insn; | |
3269 | ||
3270 | if (GET_CODE (pattern) == SEQUENCE) | |
3271 | insn = emit_insn_after (pattern, after); | |
3272 | else | |
3273 | { | |
85cf32bc | 3274 | insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3275 | add_insn_after (insn, after); |
3276 | } | |
3277 | ||
3278 | return insn; | |
3279 | } | |
3280 | ||
3281 | /* Make an insn of code BARRIER | |
3282 | and output it after the insn AFTER. */ | |
3283 | ||
3284 | rtx | |
3285 | emit_barrier_after (after) | |
3286 | register rtx after; | |
3287 | { | |
3288 | register rtx insn = rtx_alloc (BARRIER); | |
3289 | ||
3290 | INSN_UID (insn) = cur_insn_uid++; | |
3291 | ||
3292 | add_insn_after (insn, after); | |
3293 | return insn; | |
3294 | } | |
3295 | ||
3296 | /* Emit the label LABEL after the insn AFTER. */ | |
3297 | ||
3298 | rtx | |
3299 | emit_label_after (label, after) | |
3300 | rtx label, after; | |
3301 | { | |
3302 | /* This can be called twice for the same label | |
3303 | as a result of the confusion that follows a syntax error! | |
3304 | So make it harmless. */ | |
3305 | if (INSN_UID (label) == 0) | |
3306 | { | |
3307 | INSN_UID (label) = cur_insn_uid++; | |
3308 | add_insn_after (label, after); | |
3309 | } | |
3310 | ||
3311 | return label; | |
3312 | } | |
3313 | ||
3314 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3315 | ||
3316 | rtx | |
3317 | emit_note_after (subtype, after) | |
3318 | int subtype; | |
3319 | rtx after; | |
3320 | { | |
3321 | register rtx note = rtx_alloc (NOTE); | |
3322 | INSN_UID (note) = cur_insn_uid++; | |
3323 | NOTE_SOURCE_FILE (note) = 0; | |
3324 | NOTE_LINE_NUMBER (note) = subtype; | |
3325 | add_insn_after (note, after); | |
3326 | return note; | |
3327 | } | |
3328 | ||
3329 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3330 | ||
3331 | rtx | |
3332 | emit_line_note_after (file, line, after) | |
3cce094d | 3333 | const char *file; |
23b2ce53 RS |
3334 | int line; |
3335 | rtx after; | |
3336 | { | |
3337 | register rtx note; | |
3338 | ||
3339 | if (no_line_numbers && line > 0) | |
3340 | { | |
3341 | cur_insn_uid++; | |
3342 | return 0; | |
3343 | } | |
3344 | ||
3345 | note = rtx_alloc (NOTE); | |
3346 | INSN_UID (note) = cur_insn_uid++; | |
3347 | NOTE_SOURCE_FILE (note) = file; | |
3348 | NOTE_LINE_NUMBER (note) = line; | |
3349 | add_insn_after (note, after); | |
3350 | return note; | |
3351 | } | |
3352 | \f | |
3353 | /* Make an insn of code INSN with pattern PATTERN | |
3354 | and add it to the end of the doubly-linked list. | |
3355 | If PATTERN is a SEQUENCE, take the elements of it | |
3356 | and emit an insn for each element. | |
3357 | ||
3358 | Returns the last insn emitted. */ | |
3359 | ||
3360 | rtx | |
3361 | emit_insn (pattern) | |
3362 | rtx pattern; | |
3363 | { | |
3364 | rtx insn = last_insn; | |
3365 | ||
3366 | if (GET_CODE (pattern) == SEQUENCE) | |
3367 | { | |
3368 | register int i; | |
3369 | ||
3370 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3371 | { | |
3372 | insn = XVECEXP (pattern, 0, i); | |
3373 | add_insn (insn); | |
3374 | } | |
23b2ce53 RS |
3375 | } |
3376 | else | |
3377 | { | |
4b1f5e8c | 3378 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3379 | add_insn (insn); |
3380 | } | |
3381 | ||
3382 | return insn; | |
3383 | } | |
3384 | ||
3385 | /* Emit the insns in a chain starting with INSN. | |
3386 | Return the last insn emitted. */ | |
3387 | ||
3388 | rtx | |
3389 | emit_insns (insn) | |
3390 | rtx insn; | |
3391 | { | |
3392 | rtx last = 0; | |
3393 | ||
3394 | while (insn) | |
3395 | { | |
3396 | rtx next = NEXT_INSN (insn); | |
3397 | add_insn (insn); | |
3398 | last = insn; | |
3399 | insn = next; | |
3400 | } | |
3401 | ||
3402 | return last; | |
3403 | } | |
3404 | ||
3405 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3406 | the insn BEFORE. Return the last insn emitted. */ | |
3407 | ||
3408 | rtx | |
3409 | emit_insns_before (insn, before) | |
3410 | rtx insn; | |
3411 | rtx before; | |
3412 | { | |
3413 | rtx last = 0; | |
3414 | ||
3415 | while (insn) | |
3416 | { | |
3417 | rtx next = NEXT_INSN (insn); | |
a0ae8e8d | 3418 | add_insn_before (insn, before); |
23b2ce53 RS |
3419 | last = insn; |
3420 | insn = next; | |
3421 | } | |
3422 | ||
3423 | return last; | |
3424 | } | |
3425 | ||
e0a5c5eb RS |
3426 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3427 | the insn AFTER. Return the last insn emitted. */ | |
3428 | ||
3429 | rtx | |
3430 | emit_insns_after (first, after) | |
3431 | register rtx first; | |
3432 | register rtx after; | |
3433 | { | |
3434 | register rtx last; | |
3435 | register rtx after_after; | |
3436 | ||
3437 | if (!after) | |
3438 | abort (); | |
3439 | ||
3440 | if (!first) | |
3441 | return first; | |
3442 | ||
3443 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3444 | continue; | |
3445 | ||
3446 | after_after = NEXT_INSN (after); | |
3447 | ||
3448 | NEXT_INSN (after) = first; | |
3449 | PREV_INSN (first) = after; | |
3450 | NEXT_INSN (last) = after_after; | |
3451 | if (after_after) | |
3452 | PREV_INSN (after_after) = last; | |
3453 | ||
c4d990db RS |
3454 | if (after == last_insn) |
3455 | last_insn = last; | |
e0a5c5eb RS |
3456 | return last; |
3457 | } | |
3458 | ||
23b2ce53 RS |
3459 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3460 | and add it to the end of the doubly-linked list. */ | |
3461 | ||
3462 | rtx | |
3463 | emit_jump_insn (pattern) | |
3464 | rtx pattern; | |
3465 | { | |
3466 | if (GET_CODE (pattern) == SEQUENCE) | |
3467 | return emit_insn (pattern); | |
3468 | else | |
3469 | { | |
85cf32bc | 3470 | register rtx insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3471 | add_insn (insn); |
3472 | return insn; | |
3473 | } | |
3474 | } | |
3475 | ||
3476 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3477 | and add it to the end of the doubly-linked list. */ | |
3478 | ||
3479 | rtx | |
3480 | emit_call_insn (pattern) | |
3481 | rtx pattern; | |
3482 | { | |
3483 | if (GET_CODE (pattern) == SEQUENCE) | |
3484 | return emit_insn (pattern); | |
3485 | else | |
3486 | { | |
aff507f4 | 3487 | register rtx insn = make_call_insn_raw (pattern); |
23b2ce53 RS |
3488 | add_insn (insn); |
3489 | PUT_CODE (insn, CALL_INSN); | |
3490 | return insn; | |
3491 | } | |
3492 | } | |
3493 | ||
3494 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3495 | ||
3496 | rtx | |
3497 | emit_label (label) | |
3498 | rtx label; | |
3499 | { | |
3500 | /* This can be called twice for the same label | |
3501 | as a result of the confusion that follows a syntax error! | |
3502 | So make it harmless. */ | |
3503 | if (INSN_UID (label) == 0) | |
3504 | { | |
3505 | INSN_UID (label) = cur_insn_uid++; | |
3506 | add_insn (label); | |
3507 | } | |
3508 | return label; | |
3509 | } | |
3510 | ||
3511 | /* Make an insn of code BARRIER | |
3512 | and add it to the end of the doubly-linked list. */ | |
3513 | ||
3514 | rtx | |
3515 | emit_barrier () | |
3516 | { | |
3517 | register rtx barrier = rtx_alloc (BARRIER); | |
3518 | INSN_UID (barrier) = cur_insn_uid++; | |
3519 | add_insn (barrier); | |
3520 | return barrier; | |
3521 | } | |
3522 | ||
3523 | /* Make an insn of code NOTE | |
3524 | with data-fields specified by FILE and LINE | |
3525 | and add it to the end of the doubly-linked list, | |
3526 | but only if line-numbers are desired for debugging info. */ | |
3527 | ||
3528 | rtx | |
3529 | emit_line_note (file, line) | |
3cce094d | 3530 | const char *file; |
23b2ce53 RS |
3531 | int line; |
3532 | { | |
3f1d071b | 3533 | set_file_and_line_for_stmt (file, line); |
23b2ce53 RS |
3534 | |
3535 | #if 0 | |
3536 | if (no_line_numbers) | |
3537 | return 0; | |
3538 | #endif | |
3539 | ||
3540 | return emit_note (file, line); | |
3541 | } | |
3542 | ||
3543 | /* Make an insn of code NOTE | |
3544 | with data-fields specified by FILE and LINE | |
3545 | and add it to the end of the doubly-linked list. | |
3546 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3547 | ||
3548 | rtx | |
3549 | emit_note (file, line) | |
3cce094d | 3550 | const char *file; |
23b2ce53 RS |
3551 | int line; |
3552 | { | |
3553 | register rtx note; | |
3554 | ||
3555 | if (line > 0) | |
3556 | { | |
3557 | if (file && last_filename && !strcmp (file, last_filename) | |
3558 | && line == last_linenum) | |
3559 | return 0; | |
3560 | last_filename = file; | |
3561 | last_linenum = line; | |
3562 | } | |
3563 | ||
3564 | if (no_line_numbers && line > 0) | |
3565 | { | |
3566 | cur_insn_uid++; | |
3567 | return 0; | |
3568 | } | |
3569 | ||
3570 | note = rtx_alloc (NOTE); | |
3571 | INSN_UID (note) = cur_insn_uid++; | |
3572 | NOTE_SOURCE_FILE (note) = file; | |
3573 | NOTE_LINE_NUMBER (note) = line; | |
3574 | add_insn (note); | |
3575 | return note; | |
3576 | } | |
3577 | ||
fe77a034 | 3578 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
23b2ce53 RS |
3579 | |
3580 | rtx | |
3581 | emit_line_note_force (file, line) | |
3cce094d | 3582 | const char *file; |
23b2ce53 RS |
3583 | int line; |
3584 | { | |
3585 | last_linenum = -1; | |
3586 | return emit_line_note (file, line); | |
3587 | } | |
3588 | ||
3589 | /* Cause next statement to emit a line note even if the line number | |
3590 | has not changed. This is used at the beginning of a function. */ | |
3591 | ||
3592 | void | |
3593 | force_next_line_note () | |
3594 | { | |
3595 | last_linenum = -1; | |
3596 | } | |
87b47c85 AM |
3597 | |
3598 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
3599 | note of this type already exists, remove it first. */ | |
3600 | ||
3601 | void | |
3602 | set_unique_reg_note (insn, kind, datum) | |
3603 | rtx insn; | |
3604 | enum reg_note kind; | |
3605 | rtx datum; | |
3606 | { | |
3607 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3608 | ||
3609 | /* First remove the note if there already is one. */ | |
3610 | if (note) | |
3611 | remove_note (insn, note); | |
3612 | ||
3613 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3614 | } | |
23b2ce53 RS |
3615 | \f |
3616 | /* Return an indication of which type of insn should have X as a body. | |
3617 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3618 | ||
3619 | enum rtx_code | |
3620 | classify_insn (x) | |
3621 | rtx x; | |
3622 | { | |
3623 | if (GET_CODE (x) == CODE_LABEL) | |
3624 | return CODE_LABEL; | |
3625 | if (GET_CODE (x) == CALL) | |
3626 | return CALL_INSN; | |
3627 | if (GET_CODE (x) == RETURN) | |
3628 | return JUMP_INSN; | |
3629 | if (GET_CODE (x) == SET) | |
3630 | { | |
3631 | if (SET_DEST (x) == pc_rtx) | |
3632 | return JUMP_INSN; | |
3633 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3634 | return CALL_INSN; | |
3635 | else | |
3636 | return INSN; | |
3637 | } | |
3638 | if (GET_CODE (x) == PARALLEL) | |
3639 | { | |
3640 | register int j; | |
3641 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3642 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3643 | return CALL_INSN; | |
3644 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3645 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3646 | return JUMP_INSN; | |
3647 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3648 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3649 | return CALL_INSN; | |
3650 | } | |
3651 | return INSN; | |
3652 | } | |
3653 | ||
3654 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3655 | If X is a label, it is simply added into the insn chain. */ | |
3656 | ||
3657 | rtx | |
3658 | emit (x) | |
3659 | rtx x; | |
3660 | { | |
3661 | enum rtx_code code = classify_insn (x); | |
3662 | ||
3663 | if (code == CODE_LABEL) | |
3664 | return emit_label (x); | |
3665 | else if (code == INSN) | |
3666 | return emit_insn (x); | |
3667 | else if (code == JUMP_INSN) | |
3668 | { | |
3669 | register rtx insn = emit_jump_insn (x); | |
7f1c097d | 3670 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
23b2ce53 RS |
3671 | return emit_barrier (); |
3672 | return insn; | |
3673 | } | |
3674 | else if (code == CALL_INSN) | |
3675 | return emit_call_insn (x); | |
3676 | else | |
3677 | abort (); | |
3678 | } | |
3679 | \f | |
5c7a310f MM |
3680 | /* Begin emitting insns to a sequence which can be packaged in an |
3681 | RTL_EXPR. If this sequence will contain something that might cause | |
3682 | the compiler to pop arguments to function calls (because those | |
3683 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3684 | details), use do_pending_stack_adjust before calling this function. | |
3685 | That will ensure that the deferred pops are not accidentally | |
4eb00163 | 3686 | emitted in the middle of this sequence. */ |
23b2ce53 RS |
3687 | |
3688 | void | |
3689 | start_sequence () | |
3690 | { | |
3691 | struct sequence_stack *tem; | |
3692 | ||
a3770a81 | 3693 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
23b2ce53 | 3694 | |
49ad7cfa | 3695 | tem->next = seq_stack; |
23b2ce53 RS |
3696 | tem->first = first_insn; |
3697 | tem->last = last_insn; | |
591ccf92 | 3698 | tem->sequence_rtl_expr = seq_rtl_expr; |
23b2ce53 | 3699 | |
49ad7cfa | 3700 | seq_stack = tem; |
23b2ce53 RS |
3701 | |
3702 | first_insn = 0; | |
3703 | last_insn = 0; | |
3704 | } | |
3705 | ||
591ccf92 MM |
3706 | /* Similarly, but indicate that this sequence will be placed in T, an |
3707 | RTL_EXPR. See the documentation for start_sequence for more | |
3708 | information about how to use this function. */ | |
3709 | ||
3710 | void | |
3711 | start_sequence_for_rtl_expr (t) | |
3712 | tree t; | |
3713 | { | |
3714 | start_sequence (); | |
3715 | ||
3716 | seq_rtl_expr = t; | |
3717 | } | |
3718 | ||
5c7a310f MM |
3719 | /* Set up the insn chain starting with FIRST as the current sequence, |
3720 | saving the previously current one. See the documentation for | |
3721 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
3722 | |
3723 | void | |
3724 | push_to_sequence (first) | |
3725 | rtx first; | |
3726 | { | |
3727 | rtx last; | |
3728 | ||
3729 | start_sequence (); | |
3730 | ||
3731 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3732 | ||
3733 | first_insn = first; | |
3734 | last_insn = last; | |
3735 | } | |
3736 | ||
c14f7160 ML |
3737 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3738 | ||
3739 | void | |
3740 | push_to_full_sequence (first, last) | |
3741 | rtx first, last; | |
3742 | { | |
3743 | start_sequence (); | |
3744 | first_insn = first; | |
3745 | last_insn = last; | |
3746 | /* We really should have the end of the insn chain here. */ | |
3747 | if (last && NEXT_INSN (last)) | |
3748 | abort (); | |
3749 | } | |
3750 | ||
f15ae3a1 TW |
3751 | /* Set up the outer-level insn chain |
3752 | as the current sequence, saving the previously current one. */ | |
3753 | ||
3754 | void | |
3755 | push_topmost_sequence () | |
3756 | { | |
aefdd5ab | 3757 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
3758 | |
3759 | start_sequence (); | |
3760 | ||
49ad7cfa | 3761 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3762 | top = stack; |
3763 | ||
3764 | first_insn = top->first; | |
3765 | last_insn = top->last; | |
591ccf92 | 3766 | seq_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
3767 | } |
3768 | ||
3769 | /* After emitting to the outer-level insn chain, update the outer-level | |
3770 | insn chain, and restore the previous saved state. */ | |
3771 | ||
3772 | void | |
3773 | pop_topmost_sequence () | |
3774 | { | |
aefdd5ab | 3775 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 3776 | |
49ad7cfa | 3777 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3778 | top = stack; |
3779 | ||
3780 | top->first = first_insn; | |
3781 | top->last = last_insn; | |
591ccf92 | 3782 | /* ??? Why don't we save seq_rtl_expr here? */ |
f15ae3a1 TW |
3783 | |
3784 | end_sequence (); | |
3785 | } | |
3786 | ||
23b2ce53 RS |
3787 | /* After emitting to a sequence, restore previous saved state. |
3788 | ||
5c7a310f MM |
3789 | To get the contents of the sequence just made, you must call |
3790 | `gen_sequence' *before* calling here. | |
3791 | ||
3792 | If the compiler might have deferred popping arguments while | |
3793 | generating this sequence, and this sequence will not be immediately | |
3794 | inserted into the instruction stream, use do_pending_stack_adjust | |
3795 | before calling gen_sequence. That will ensure that the deferred | |
3796 | pops are inserted into this sequence, and not into some random | |
3797 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3798 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
3799 | |
3800 | void | |
3801 | end_sequence () | |
3802 | { | |
49ad7cfa | 3803 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
3804 | |
3805 | first_insn = tem->first; | |
3806 | last_insn = tem->last; | |
591ccf92 | 3807 | seq_rtl_expr = tem->sequence_rtl_expr; |
49ad7cfa | 3808 | seq_stack = tem->next; |
23b2ce53 | 3809 | |
a3770a81 | 3810 | free (tem); |
23b2ce53 RS |
3811 | } |
3812 | ||
c14f7160 ML |
3813 | /* This works like end_sequence, but records the old sequence in FIRST |
3814 | and LAST. */ | |
3815 | ||
3816 | void | |
3817 | end_full_sequence (first, last) | |
3818 | rtx *first, *last; | |
3819 | { | |
3820 | *first = first_insn; | |
3821 | *last = last_insn; | |
3822 | end_sequence(); | |
3823 | } | |
3824 | ||
23b2ce53 RS |
3825 | /* Return 1 if currently emitting into a sequence. */ |
3826 | ||
3827 | int | |
3828 | in_sequence_p () | |
3829 | { | |
49ad7cfa | 3830 | return seq_stack != 0; |
23b2ce53 RS |
3831 | } |
3832 | ||
3833 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3834 | to the current sequence. | |
3835 | ||
3836 | This is how the gen_... function from a DEFINE_EXPAND | |
3837 | constructs the SEQUENCE that it returns. */ | |
3838 | ||
3839 | rtx | |
3840 | gen_sequence () | |
3841 | { | |
3842 | rtx result; | |
3843 | rtx tem; | |
23b2ce53 RS |
3844 | int i; |
3845 | int len; | |
3846 | ||
3847 | /* Count the insns in the chain. */ | |
3848 | len = 0; | |
3849 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3850 | len++; | |
3851 | ||
ee265800 | 3852 | /* If only one insn, return it rather than a SEQUENCE. |
23b2ce53 | 3853 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
ee265800 AH |
3854 | the case of an empty list.) |
3855 | We only return the pattern of an insn if its code is INSN and it | |
3856 | has no notes. This ensures that no information gets lost. */ | |
23b2ce53 | 3857 | if (len == 1 |
ca55abae | 3858 | && ! RTX_FRAME_RELATED_P (first_insn) |
ee265800 AH |
3859 | && GET_CODE (first_insn) == INSN |
3860 | /* Don't throw away any reg notes. */ | |
3861 | && REG_NOTES (first_insn) == 0) | |
1f8f4a0b | 3862 | return PATTERN (first_insn); |
23b2ce53 | 3863 | |
1f8f4a0b | 3864 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
23b2ce53 RS |
3865 | |
3866 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3867 | XVECEXP (result, 0, i) = tem; | |
3868 | ||
3869 | return result; | |
3870 | } | |
3871 | \f | |
59ec66dc MM |
3872 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3873 | ||
3874 | void | |
49ad7cfa BS |
3875 | init_virtual_regs (es) |
3876 | struct emit_status *es; | |
59ec66dc | 3877 | { |
49ad7cfa BS |
3878 | rtx *ptr = es->x_regno_reg_rtx; |
3879 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3880 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3881 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3882 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3883 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3884 | } | |
3885 | ||
3886 | void | |
3887 | clear_emit_caches () | |
3888 | { | |
3889 | int i; | |
3890 | ||
3891 | /* Clear the start_sequence/gen_sequence cache. */ | |
49ad7cfa BS |
3892 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3893 | sequence_result[i] = 0; | |
3894 | free_insn = 0; | |
59ec66dc | 3895 | } |
da43a810 BS |
3896 | \f |
3897 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3898 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3899 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3900 | static int copy_insn_n_scratches; | |
3901 | ||
3902 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3903 | copied an ASM_OPERANDS. | |
3904 | In that case, it is the original input-operand vector. */ | |
3905 | static rtvec orig_asm_operands_vector; | |
3906 | ||
3907 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3908 | copied an ASM_OPERANDS. | |
3909 | In that case, it is the copied input-operand vector. */ | |
3910 | static rtvec copy_asm_operands_vector; | |
3911 | ||
3912 | /* Likewise for the constraints vector. */ | |
3913 | static rtvec orig_asm_constraints_vector; | |
3914 | static rtvec copy_asm_constraints_vector; | |
3915 | ||
3916 | /* Recursively create a new copy of an rtx for copy_insn. | |
3917 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3918 | ASM_OPERANDs properly. | |
3919 | Normally, this function is not used directly; use copy_insn as front end. | |
3920 | However, you could first copy an insn pattern with copy_insn and then use | |
3921 | this function afterwards to properly copy any REG_NOTEs containing | |
3922 | SCRATCHes. */ | |
3923 | ||
3924 | rtx | |
3925 | copy_insn_1 (orig) | |
3926 | register rtx orig; | |
3927 | { | |
3928 | register rtx copy; | |
3929 | register int i, j; | |
3930 | register RTX_CODE code; | |
4724334a | 3931 | register const char *format_ptr; |
da43a810 BS |
3932 | |
3933 | code = GET_CODE (orig); | |
3934 | ||
3935 | switch (code) | |
3936 | { | |
3937 | case REG: | |
3938 | case QUEUED: | |
3939 | case CONST_INT: | |
3940 | case CONST_DOUBLE: | |
3941 | case SYMBOL_REF: | |
3942 | case CODE_LABEL: | |
3943 | case PC: | |
3944 | case CC0: | |
3945 | case ADDRESSOF: | |
3946 | return orig; | |
3947 | ||
3948 | case SCRATCH: | |
3949 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3950 | if (copy_insn_scratch_in[i] == orig) | |
3951 | return copy_insn_scratch_out[i]; | |
3952 | break; | |
3953 | ||
3954 | case CONST: | |
3955 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
3956 | a LABEL_REF, it isn't sharable. */ | |
3957 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3958 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
3959 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
3960 | return orig; | |
3961 | break; | |
3962 | ||
3963 | /* A MEM with a constant address is not sharable. The problem is that | |
3964 | the constant address may need to be reloaded. If the mem is shared, | |
3965 | then reloading one copy of this mem will cause all copies to appear | |
3966 | to have been reloaded. */ | |
3967 | ||
3968 | default: | |
3969 | break; | |
3970 | } | |
3971 | ||
3972 | copy = rtx_alloc (code); | |
3973 | ||
3974 | /* Copy the various flags, and other information. We assume that | |
3975 | all fields need copying, and then clear the fields that should | |
3976 | not be copied. That is the sensible default behavior, and forces | |
3977 | us to explicitly document why we are *not* copying a flag. */ | |
3978 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
3979 | ||
3980 | /* We do not copy the USED flag, which is used as a mark bit during | |
3981 | walks over the RTL. */ | |
3982 | copy->used = 0; | |
3983 | ||
3984 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
3985 | if (GET_RTX_CLASS (code) == 'i') | |
3986 | { | |
3987 | copy->jump = 0; | |
3988 | copy->call = 0; | |
3989 | copy->frame_related = 0; | |
3990 | } | |
3991 | ||
3992 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
3993 | ||
3994 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
3995 | { | |
e63db8f6 | 3996 | copy->fld[i] = orig->fld[i]; |
da43a810 BS |
3997 | switch (*format_ptr++) |
3998 | { | |
3999 | case 'e': | |
da43a810 BS |
4000 | if (XEXP (orig, i) != NULL) |
4001 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
4002 | break; | |
4003 | ||
da43a810 BS |
4004 | case 'E': |
4005 | case 'V': | |
da43a810 BS |
4006 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
4007 | XVEC (copy, i) = copy_asm_constraints_vector; | |
4008 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
4009 | XVEC (copy, i) = copy_asm_operands_vector; | |
4010 | else if (XVEC (orig, i) != NULL) | |
4011 | { | |
4012 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
4013 | for (j = 0; j < XVECLEN (copy, i); j++) | |
4014 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
4015 | } | |
4016 | break; | |
4017 | ||
da43a810 | 4018 | case 't': |
da43a810 | 4019 | case 'w': |
da43a810 | 4020 | case 'i': |
da43a810 BS |
4021 | case 's': |
4022 | case 'S': | |
e63db8f6 BS |
4023 | case 'u': |
4024 | case '0': | |
4025 | /* These are left unchanged. */ | |
da43a810 BS |
4026 | break; |
4027 | ||
4028 | default: | |
4029 | abort (); | |
4030 | } | |
4031 | } | |
4032 | ||
4033 | if (code == SCRATCH) | |
4034 | { | |
4035 | i = copy_insn_n_scratches++; | |
4036 | if (i >= MAX_RECOG_OPERANDS) | |
4037 | abort (); | |
4038 | copy_insn_scratch_in[i] = orig; | |
4039 | copy_insn_scratch_out[i] = copy; | |
4040 | } | |
4041 | else if (code == ASM_OPERANDS) | |
4042 | { | |
6462bb43 AO |
4043 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
4044 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
4045 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
4046 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
4047 | } |
4048 | ||
4049 | return copy; | |
4050 | } | |
4051 | ||
4052 | /* Create a new copy of an rtx. | |
4053 | This function differs from copy_rtx in that it handles SCRATCHes and | |
4054 | ASM_OPERANDs properly. | |
4055 | INSN doesn't really have to be a full INSN; it could be just the | |
4056 | pattern. */ | |
4057 | rtx | |
4058 | copy_insn (insn) | |
4059 | rtx insn; | |
4060 | { | |
4061 | copy_insn_n_scratches = 0; | |
4062 | orig_asm_operands_vector = 0; | |
4063 | orig_asm_constraints_vector = 0; | |
4064 | copy_asm_operands_vector = 0; | |
4065 | copy_asm_constraints_vector = 0; | |
4066 | return copy_insn_1 (insn); | |
4067 | } | |
59ec66dc | 4068 | |
23b2ce53 RS |
4069 | /* Initialize data structures and variables in this file |
4070 | before generating rtl for each function. */ | |
4071 | ||
4072 | void | |
4073 | init_emit () | |
4074 | { | |
01d939e8 | 4075 | struct function *f = cfun; |
23b2ce53 | 4076 | |
49ad7cfa | 4077 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
23b2ce53 RS |
4078 | first_insn = NULL; |
4079 | last_insn = NULL; | |
591ccf92 | 4080 | seq_rtl_expr = NULL; |
23b2ce53 RS |
4081 | cur_insn_uid = 1; |
4082 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
4083 | last_linenum = 0; | |
4084 | last_filename = 0; | |
4085 | first_label_num = label_num; | |
4086 | last_label_num = 0; | |
49ad7cfa | 4087 | seq_stack = NULL; |
23b2ce53 | 4088 | |
49ad7cfa | 4089 | clear_emit_caches (); |
23b2ce53 RS |
4090 | |
4091 | /* Init the tables that describe all the pseudo regs. */ | |
4092 | ||
3502dc9c | 4093 | f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 4094 | |
49ad7cfa | 4095 | f->emit->regno_pointer_align |
3502dc9c | 4096 | = (unsigned char *) xcalloc (f->emit->regno_pointer_align_length, |
f9e158c3 | 4097 | sizeof (unsigned char)); |
86fe05e0 | 4098 | |
23b2ce53 | 4099 | regno_reg_rtx |
3502dc9c | 4100 | = (rtx *) xcalloc (f->emit->regno_pointer_align_length * sizeof (rtx), |
a3770a81 | 4101 | sizeof (rtx)); |
23b2ce53 RS |
4102 | |
4103 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
49ad7cfa | 4104 | init_virtual_regs (f->emit); |
740ab4a2 RK |
4105 | |
4106 | /* Indicate that the virtual registers and stack locations are | |
4107 | all pointers. */ | |
3502dc9c JDA |
4108 | REG_POINTER (stack_pointer_rtx) = 1; |
4109 | REG_POINTER (frame_pointer_rtx) = 1; | |
4110 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
4111 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 4112 | |
3502dc9c JDA |
4113 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
4114 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
4115 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
4116 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
4117 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 4118 | |
86fe05e0 | 4119 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
4120 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
4121 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
4122 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
4123 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
4124 | ||
4125 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
4126 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
4127 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
4128 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
4129 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
4130 | #endif |
4131 | ||
5e82e7bd JVA |
4132 | #ifdef INIT_EXPANDERS |
4133 | INIT_EXPANDERS; | |
4134 | #endif | |
23b2ce53 RS |
4135 | } |
4136 | ||
87ff9c8e RH |
4137 | /* Mark SS for GC. */ |
4138 | ||
4139 | static void | |
4140 | mark_sequence_stack (ss) | |
4141 | struct sequence_stack *ss; | |
4142 | { | |
4143 | while (ss) | |
4144 | { | |
4145 | ggc_mark_rtx (ss->first); | |
591ccf92 | 4146 | ggc_mark_tree (ss->sequence_rtl_expr); |
87ff9c8e RH |
4147 | ss = ss->next; |
4148 | } | |
4149 | } | |
4150 | ||
4151 | /* Mark ES for GC. */ | |
4152 | ||
4153 | void | |
fa51b01b | 4154 | mark_emit_status (es) |
87ff9c8e RH |
4155 | struct emit_status *es; |
4156 | { | |
4157 | rtx *r; | |
4158 | int i; | |
4159 | ||
4160 | if (es == 0) | |
4161 | return; | |
4162 | ||
3502dc9c | 4163 | for (i = es->regno_pointer_align_length, r = es->x_regno_reg_rtx; |
87ff9c8e RH |
4164 | i > 0; --i, ++r) |
4165 | ggc_mark_rtx (*r); | |
4166 | ||
4167 | mark_sequence_stack (es->sequence_stack); | |
591ccf92 | 4168 | ggc_mark_tree (es->sequence_rtl_expr); |
87ff9c8e RH |
4169 | ggc_mark_rtx (es->x_first_insn); |
4170 | } | |
4171 | ||
23b2ce53 RS |
4172 | /* Create some permanent unique rtl objects shared between all functions. |
4173 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
4174 | ||
4175 | void | |
4176 | init_emit_once (line_numbers) | |
4177 | int line_numbers; | |
4178 | { | |
4179 | int i; | |
4180 | enum machine_mode mode; | |
9ec36da5 | 4181 | enum machine_mode double_mode; |
23b2ce53 | 4182 | |
67673f5c MM |
4183 | /* Initialize the CONST_INT hash table. */ |
4184 | const_int_htab = htab_create (37, const_int_htab_hash, | |
4185 | const_int_htab_eq, NULL); | |
4186 | ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab), | |
4187 | rtx_htab_mark); | |
4188 | ||
23b2ce53 RS |
4189 | no_line_numbers = ! line_numbers; |
4190 | ||
43fa6302 AS |
4191 | /* Compute the word and byte modes. */ |
4192 | ||
4193 | byte_mode = VOIDmode; | |
4194 | word_mode = VOIDmode; | |
4195 | double_mode = VOIDmode; | |
4196 | ||
4197 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4198 | mode = GET_MODE_WIDER_MODE (mode)) | |
4199 | { | |
4200 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
4201 | && byte_mode == VOIDmode) | |
4202 | byte_mode = mode; | |
4203 | ||
4204 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
4205 | && word_mode == VOIDmode) | |
4206 | word_mode = mode; | |
4207 | } | |
4208 | ||
43fa6302 AS |
4209 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; |
4210 | mode = GET_MODE_WIDER_MODE (mode)) | |
4211 | { | |
4212 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
4213 | && double_mode == VOIDmode) | |
4214 | double_mode = mode; | |
4215 | } | |
4216 | ||
4217 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
4218 | ||
5da077de AS |
4219 | /* Assign register numbers to the globally defined register rtx. |
4220 | This must be done at runtime because the register number field | |
4221 | is in a union and some compilers can't initialize unions. */ | |
4222 | ||
4223 | pc_rtx = gen_rtx (PC, VOIDmode); | |
4224 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
08394eef BS |
4225 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
4226 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5da077de | 4227 | if (hard_frame_pointer_rtx == 0) |
08394eef BS |
4228 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, |
4229 | HARD_FRAME_POINTER_REGNUM); | |
5da077de | 4230 | if (arg_pointer_rtx == 0) |
08394eef | 4231 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); |
5da077de | 4232 | virtual_incoming_args_rtx = |
08394eef | 4233 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); |
5da077de | 4234 | virtual_stack_vars_rtx = |
08394eef | 4235 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); |
5da077de | 4236 | virtual_stack_dynamic_rtx = |
08394eef | 4237 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); |
5da077de | 4238 | virtual_outgoing_args_rtx = |
08394eef BS |
4239 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); |
4240 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
5da077de AS |
4241 | |
4242 | /* These rtx must be roots if GC is enabled. */ | |
1f8f4a0b | 4243 | ggc_add_rtx_root (global_rtl, GR_MAX); |
5da077de | 4244 | |
5da077de | 4245 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
4246 | /* This is to initialize {init|mark|free}_machine_status before the first |
4247 | call to push_function_context_to. This is needed by the Chill front | |
4248 | end which calls push_function_context_to before the first cal to | |
5da077de AS |
4249 | init_function_start. */ |
4250 | INIT_EXPANDERS; | |
4251 | #endif | |
4252 | ||
23b2ce53 RS |
4253 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
4254 | ||
c5c76735 JL |
4255 | /* Don't use gen_rtx here since gen_rtx in this case |
4256 | tries to use these variables. */ | |
23b2ce53 | 4257 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
5da077de AS |
4258 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
4259 | gen_rtx_raw_CONST_INT (VOIDmode, i); | |
1f8f4a0b | 4260 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); |
23b2ce53 | 4261 | |
68d75312 JC |
4262 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
4263 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 4264 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 4265 | else |
3b80f6ca | 4266 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 4267 | |
9ec36da5 JL |
4268 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
4269 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
4270 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
4271 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
23b2ce53 RS |
4272 | |
4273 | for (i = 0; i <= 2; i++) | |
4274 | { | |
4275 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4276 | mode = GET_MODE_WIDER_MODE (mode)) | |
4277 | { | |
4278 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4279 | union real_extract u; | |
4280 | ||
961192e1 | 4281 | memset ((char *) &u, 0, sizeof u); /* Zero any holes in a structure. */ |
23b2ce53 RS |
4282 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4283 | ||
4e135bdd | 4284 | memcpy (&CONST_DOUBLE_LOW (tem), &u, sizeof u); |
23b2ce53 | 4285 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
f8a83ee3 | 4286 | CONST_DOUBLE_CHAIN (tem) = NULL_RTX; |
23b2ce53 RS |
4287 | PUT_MODE (tem, mode); |
4288 | ||
4289 | const_tiny_rtx[i][(int) mode] = tem; | |
4290 | } | |
4291 | ||
906c4e36 | 4292 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
4293 | |
4294 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4295 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 4296 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
4297 | |
4298 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4299 | mode != VOIDmode; | |
4300 | mode = GET_MODE_WIDER_MODE (mode)) | |
4301 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
4302 | } |
4303 | ||
dbbbbf3b JDA |
4304 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
4305 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
4306 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 4307 | |
f0417c82 RH |
4308 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
4309 | if (STORE_FLAG_VALUE == 1) | |
4310 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
4311 | ||
b6a1cbae GM |
4312 | /* For bounded pointers, `&const_tiny_rtx[0][0]' is not the same as |
4313 | `(rtx *) const_tiny_rtx'. The former has bounds that only cover | |
4314 | `const_tiny_rtx[0]', whereas the latter has bounds that cover all. */ | |
4315 | ggc_add_rtx_root ((rtx *) const_tiny_rtx, sizeof const_tiny_rtx / sizeof (rtx)); | |
21cd906e | 4316 | ggc_add_rtx_root (&const_true_rtx, 1); |
a7e1e2ac AO |
4317 | |
4318 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4319 | return_address_pointer_rtx | |
08394eef | 4320 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); |
a7e1e2ac AO |
4321 | #endif |
4322 | ||
4323 | #ifdef STRUCT_VALUE | |
4324 | struct_value_rtx = STRUCT_VALUE; | |
4325 | #else | |
4326 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4327 | #endif | |
4328 | ||
4329 | #ifdef STRUCT_VALUE_INCOMING | |
4330 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4331 | #else | |
4332 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4333 | struct_value_incoming_rtx | |
4334 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4335 | #else | |
4336 | struct_value_incoming_rtx = struct_value_rtx; | |
4337 | #endif | |
4338 | #endif | |
4339 | ||
4340 | #ifdef STATIC_CHAIN_REGNUM | |
4341 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4342 | ||
4343 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4344 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4345 | static_chain_incoming_rtx | |
4346 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4347 | else | |
4348 | #endif | |
4349 | static_chain_incoming_rtx = static_chain_rtx; | |
4350 | #endif | |
4351 | ||
4352 | #ifdef STATIC_CHAIN | |
4353 | static_chain_rtx = STATIC_CHAIN; | |
4354 | ||
4355 | #ifdef STATIC_CHAIN_INCOMING | |
4356 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4357 | #else | |
4358 | static_chain_incoming_rtx = static_chain_rtx; | |
4359 | #endif | |
4360 | #endif | |
4361 | ||
848e0190 JH |
4362 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
4363 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
a7e1e2ac | 4364 | |
d7db6646 RH |
4365 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4366 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4367 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4368 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4369 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4370 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
23b2ce53 | 4371 | } |
a11759a3 JR |
4372 | \f |
4373 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4374 | switch / case handling in stmt.c to give proper line numbers in | |
4375 | warnings about unreachable code. */ | |
4376 | ||
4377 | int | |
4378 | force_line_numbers () | |
4379 | { | |
4380 | int old = no_line_numbers; | |
4381 | ||
4382 | no_line_numbers = 0; | |
4383 | if (old) | |
4384 | force_next_line_note (); | |
4385 | return old; | |
4386 | } | |
4387 | ||
4388 | void | |
4389 | restore_line_number_status (old_value) | |
4390 | int old_value; | |
4391 | { | |
4392 | no_line_numbers = old_value; | |
4393 | } |