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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
cbe34bb5 | 2 | Copyright (C) 1987-2017 Free Software Foundation, Inc. |
23b2ce53 | 3 | |
1322177d | 4 | This file is part of GCC. |
23b2ce53 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
23b2ce53 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
23b2ce53 RS |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
19 | |
20 | ||
21 | /* Middle-to-low level generation of rtx code and insns. | |
22 | ||
f822fcf7 KH |
23 | This file contains support functions for creating rtl expressions |
24 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
25 | |
26 | The patterns of the insns are created by machine-dependent | |
27 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
28 | the machine description. These routines make the individual rtx's |
29 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
30 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
31 | dependent is the kind of rtx's they make and what arguments they |
32 | use. */ | |
23b2ce53 RS |
33 | |
34 | #include "config.h" | |
670ee920 | 35 | #include "system.h" |
4977bab6 | 36 | #include "coretypes.h" |
4d0cdd0c | 37 | #include "memmodel.h" |
c7131fb2 | 38 | #include "backend.h" |
957060b5 | 39 | #include "target.h" |
23b2ce53 | 40 | #include "rtl.h" |
957060b5 | 41 | #include "tree.h" |
c7131fb2 | 42 | #include "df.h" |
957060b5 AM |
43 | #include "tm_p.h" |
44 | #include "stringpool.h" | |
957060b5 AM |
45 | #include "insn-config.h" |
46 | #include "regs.h" | |
47 | #include "emit-rtl.h" | |
48 | #include "recog.h" | |
c7131fb2 | 49 | #include "diagnostic-core.h" |
40e23961 | 50 | #include "alias.h" |
40e23961 | 51 | #include "fold-const.h" |
d8a2d370 | 52 | #include "varasm.h" |
60393bbc | 53 | #include "cfgrtl.h" |
60393bbc | 54 | #include "tree-eh.h" |
36566b39 | 55 | #include "explow.h" |
23b2ce53 | 56 | #include "expr.h" |
b5b8b0ac | 57 | #include "params.h" |
9b2b7279 | 58 | #include "builtins.h" |
9021b8ec | 59 | #include "rtl-iter.h" |
1f9ceff1 | 60 | #include "stor-layout.h" |
ecf835e9 | 61 | #include "opts.h" |
5fa396ad | 62 | #include "predict.h" |
ca695ac9 | 63 | |
5fb0e246 RS |
64 | struct target_rtl default_target_rtl; |
65 | #if SWITCHABLE_TARGET | |
66 | struct target_rtl *this_target_rtl = &default_target_rtl; | |
67 | #endif | |
68 | ||
69 | #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx) | |
70 | ||
1d445e9e ILT |
71 | /* Commonly used modes. */ |
72 | ||
501623d4 RS |
73 | scalar_int_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
74 | scalar_int_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
75 | scalar_int_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ | |
1d445e9e | 76 | |
bd60bab2 JH |
77 | /* Datastructures maintained for currently processed function in RTL form. */ |
78 | ||
3e029763 | 79 | struct rtl_data x_rtl; |
bd60bab2 JH |
80 | |
81 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
b8698a0f | 82 | Allocated in parallel with regno_pointer_align. |
bd60bab2 JH |
83 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal |
84 | with length attribute nested in top level structures. */ | |
85 | ||
86 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
87 | |
88 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
89 | in the entire compilation a unique label number. */ | |
90 | ||
044b4de3 | 91 | static GTY(()) int label_num = 1; |
23b2ce53 | 92 | |
23b2ce53 RS |
93 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
94 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
e7c82a99 JJ |
95 | record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX |
96 | is set only for MODE_INT and MODE_VECTOR_INT modes. */ | |
23b2ce53 | 97 | |
e7c82a99 | 98 | rtx const_tiny_rtx[4][(int) MAX_MACHINE_MODE]; |
23b2ce53 | 99 | |
68d75312 JC |
100 | rtx const_true_rtx; |
101 | ||
23b2ce53 RS |
102 | REAL_VALUE_TYPE dconst0; |
103 | REAL_VALUE_TYPE dconst1; | |
104 | REAL_VALUE_TYPE dconst2; | |
105 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 106 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 107 | |
325217ed CF |
108 | /* Record fixed-point constant 0 and 1. */ |
109 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
110 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
111 | ||
23b2ce53 RS |
112 | /* We make one copy of (const_int C) where C is in |
113 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
114 | to save space during the compilation and simplify comparisons of | |
115 | integers. */ | |
116 | ||
5da077de | 117 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 118 | |
ca4adc91 RS |
119 | /* Standard pieces of rtx, to be substituted directly into things. */ |
120 | rtx pc_rtx; | |
121 | rtx ret_rtx; | |
122 | rtx simple_return_rtx; | |
123 | rtx cc0_rtx; | |
124 | ||
1476d1bd MM |
125 | /* Marker used for denoting an INSN, which should never be accessed (i.e., |
126 | this pointer should normally never be dereferenced), but is required to be | |
127 | distinct from NULL_RTX. Currently used by peephole2 pass. */ | |
128 | rtx_insn *invalid_insn_rtx; | |
129 | ||
c13e8210 MM |
130 | /* A hash table storing CONST_INTs whose absolute value is greater |
131 | than MAX_SAVED_CONST_INT. */ | |
132 | ||
6c907cff | 133 | struct const_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
134 | { |
135 | typedef HOST_WIDE_INT compare_type; | |
136 | ||
137 | static hashval_t hash (rtx i); | |
138 | static bool equal (rtx i, HOST_WIDE_INT h); | |
139 | }; | |
c13e8210 | 140 | |
aebf76a2 TS |
141 | static GTY ((cache)) hash_table<const_int_hasher> *const_int_htab; |
142 | ||
6c907cff | 143 | struct const_wide_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
144 | { |
145 | static hashval_t hash (rtx x); | |
146 | static bool equal (rtx x, rtx y); | |
147 | }; | |
148 | ||
149 | static GTY ((cache)) hash_table<const_wide_int_hasher> *const_wide_int_htab; | |
807e902e | 150 | |
a560d4d4 | 151 | /* A hash table storing register attribute structures. */ |
6c907cff | 152 | struct reg_attr_hasher : ggc_cache_ptr_hash<reg_attrs> |
aebf76a2 TS |
153 | { |
154 | static hashval_t hash (reg_attrs *x); | |
155 | static bool equal (reg_attrs *a, reg_attrs *b); | |
156 | }; | |
157 | ||
158 | static GTY ((cache)) hash_table<reg_attr_hasher> *reg_attrs_htab; | |
a560d4d4 | 159 | |
5692c7bc | 160 | /* A hash table storing all CONST_DOUBLEs. */ |
6c907cff | 161 | struct const_double_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
162 | { |
163 | static hashval_t hash (rtx x); | |
164 | static bool equal (rtx x, rtx y); | |
165 | }; | |
166 | ||
167 | static GTY ((cache)) hash_table<const_double_hasher> *const_double_htab; | |
5692c7bc | 168 | |
091a3ac7 | 169 | /* A hash table storing all CONST_FIXEDs. */ |
6c907cff | 170 | struct const_fixed_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
171 | { |
172 | static hashval_t hash (rtx x); | |
173 | static bool equal (rtx x, rtx y); | |
174 | }; | |
175 | ||
176 | static GTY ((cache)) hash_table<const_fixed_hasher> *const_fixed_htab; | |
091a3ac7 | 177 | |
3e029763 | 178 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) |
b5b8b0ac | 179 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 | 180 | #define first_label_num (crtl->emit.x_first_label_num) |
23b2ce53 | 181 | |
5eb2a9f2 | 182 | static void set_used_decls (tree); |
502b8322 | 183 | static void mark_label_nuses (rtx); |
807e902e | 184 | #if TARGET_SUPPORTS_WIDE_INT |
807e902e KZ |
185 | static rtx lookup_const_wide_int (rtx); |
186 | #endif | |
502b8322 | 187 | static rtx lookup_const_double (rtx); |
091a3ac7 | 188 | static rtx lookup_const_fixed (rtx); |
502b8322 | 189 | static reg_attrs *get_reg_attrs (tree, int); |
ef4bddc2 | 190 | static rtx gen_const_vector (machine_mode, int); |
32b32b16 | 191 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 192 | |
5fa396ad JH |
193 | /* Probability of the conditional branch currently proceeded by try_split. */ |
194 | profile_probability split_branch_probability; | |
ca695ac9 | 195 | \f |
c13e8210 MM |
196 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
197 | ||
aebf76a2 TS |
198 | hashval_t |
199 | const_int_hasher::hash (rtx x) | |
c13e8210 | 200 | { |
aebf76a2 | 201 | return (hashval_t) INTVAL (x); |
c13e8210 MM |
202 | } |
203 | ||
cc2902df | 204 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
205 | CONST_INT) is the same as that given by Y (which is really a |
206 | HOST_WIDE_INT *). */ | |
207 | ||
aebf76a2 TS |
208 | bool |
209 | const_int_hasher::equal (rtx x, HOST_WIDE_INT y) | |
c13e8210 | 210 | { |
aebf76a2 | 211 | return (INTVAL (x) == y); |
5692c7bc ZW |
212 | } |
213 | ||
807e902e KZ |
214 | #if TARGET_SUPPORTS_WIDE_INT |
215 | /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */ | |
216 | ||
aebf76a2 TS |
217 | hashval_t |
218 | const_wide_int_hasher::hash (rtx x) | |
807e902e KZ |
219 | { |
220 | int i; | |
d7ca26e4 | 221 | unsigned HOST_WIDE_INT hash = 0; |
aebf76a2 | 222 | const_rtx xr = x; |
807e902e KZ |
223 | |
224 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
225 | hash += CONST_WIDE_INT_ELT (xr, i); | |
226 | ||
227 | return (hashval_t) hash; | |
228 | } | |
229 | ||
230 | /* Returns nonzero if the value represented by X (which is really a | |
231 | CONST_WIDE_INT) is the same as that given by Y (which is really a | |
232 | CONST_WIDE_INT). */ | |
233 | ||
aebf76a2 TS |
234 | bool |
235 | const_wide_int_hasher::equal (rtx x, rtx y) | |
807e902e KZ |
236 | { |
237 | int i; | |
aebf76a2 TS |
238 | const_rtx xr = x; |
239 | const_rtx yr = y; | |
807e902e | 240 | if (CONST_WIDE_INT_NUNITS (xr) != CONST_WIDE_INT_NUNITS (yr)) |
aebf76a2 | 241 | return false; |
807e902e KZ |
242 | |
243 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
244 | if (CONST_WIDE_INT_ELT (xr, i) != CONST_WIDE_INT_ELT (yr, i)) | |
aebf76a2 | 245 | return false; |
807e902e | 246 | |
aebf76a2 | 247 | return true; |
807e902e KZ |
248 | } |
249 | #endif | |
250 | ||
5692c7bc | 251 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ |
aebf76a2 TS |
252 | hashval_t |
253 | const_double_hasher::hash (rtx x) | |
5692c7bc | 254 | { |
aebf76a2 | 255 | const_rtx const value = x; |
46b33600 | 256 | hashval_t h; |
5692c7bc | 257 | |
807e902e | 258 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (value) == VOIDmode) |
46b33600 RH |
259 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); |
260 | else | |
fe352c29 | 261 | { |
15c812e3 | 262 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
263 | /* MODE is used in the comparison, so it should be in the hash. */ |
264 | h ^= GET_MODE (value); | |
265 | } | |
5692c7bc ZW |
266 | return h; |
267 | } | |
268 | ||
cc2902df | 269 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc | 270 | is the same as that represented by Y (really a ...) */ |
aebf76a2 TS |
271 | bool |
272 | const_double_hasher::equal (rtx x, rtx y) | |
5692c7bc | 273 | { |
aebf76a2 | 274 | const_rtx const a = x, b = y; |
5692c7bc ZW |
275 | |
276 | if (GET_MODE (a) != GET_MODE (b)) | |
277 | return 0; | |
807e902e | 278 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (a) == VOIDmode) |
8580f7a0 RH |
279 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) |
280 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
281 | else | |
282 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
283 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
284 | } |
285 | ||
091a3ac7 CF |
286 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
287 | ||
aebf76a2 TS |
288 | hashval_t |
289 | const_fixed_hasher::hash (rtx x) | |
091a3ac7 | 290 | { |
aebf76a2 | 291 | const_rtx const value = x; |
091a3ac7 CF |
292 | hashval_t h; |
293 | ||
294 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
295 | /* MODE is used in the comparison, so it should be in the hash. */ | |
296 | h ^= GET_MODE (value); | |
297 | return h; | |
298 | } | |
299 | ||
aebf76a2 TS |
300 | /* Returns nonzero if the value represented by X is the same as that |
301 | represented by Y. */ | |
091a3ac7 | 302 | |
aebf76a2 TS |
303 | bool |
304 | const_fixed_hasher::equal (rtx x, rtx y) | |
091a3ac7 | 305 | { |
aebf76a2 | 306 | const_rtx const a = x, b = y; |
091a3ac7 CF |
307 | |
308 | if (GET_MODE (a) != GET_MODE (b)) | |
309 | return 0; | |
310 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
311 | } | |
312 | ||
f12144dd | 313 | /* Return true if the given memory attributes are equal. */ |
c13e8210 | 314 | |
96b3c03f | 315 | bool |
f12144dd | 316 | mem_attrs_eq_p (const struct mem_attrs *p, const struct mem_attrs *q) |
c13e8210 | 317 | { |
96b3c03f RB |
318 | if (p == q) |
319 | return true; | |
320 | if (!p || !q) | |
321 | return false; | |
754c3d5d RS |
322 | return (p->alias == q->alias |
323 | && p->offset_known_p == q->offset_known_p | |
324 | && (!p->offset_known_p || p->offset == q->offset) | |
325 | && p->size_known_p == q->size_known_p | |
326 | && (!p->size_known_p || p->size == q->size) | |
327 | && p->align == q->align | |
09e881c9 | 328 | && p->addrspace == q->addrspace |
78b76d08 SB |
329 | && (p->expr == q->expr |
330 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
331 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
332 | } |
333 | ||
f12144dd | 334 | /* Set MEM's memory attributes so that they are the same as ATTRS. */ |
10b76d73 | 335 | |
f12144dd RS |
336 | static void |
337 | set_mem_attrs (rtx mem, mem_attrs *attrs) | |
338 | { | |
f12144dd RS |
339 | /* If everything is the default, we can just clear the attributes. */ |
340 | if (mem_attrs_eq_p (attrs, mode_mem_attrs[(int) GET_MODE (mem)])) | |
341 | { | |
342 | MEM_ATTRS (mem) = 0; | |
343 | return; | |
344 | } | |
173b24b9 | 345 | |
84053e02 RB |
346 | if (!MEM_ATTRS (mem) |
347 | || !mem_attrs_eq_p (attrs, MEM_ATTRS (mem))) | |
173b24b9 | 348 | { |
766090c2 | 349 | MEM_ATTRS (mem) = ggc_alloc<mem_attrs> (); |
84053e02 | 350 | memcpy (MEM_ATTRS (mem), attrs, sizeof (mem_attrs)); |
173b24b9 | 351 | } |
c13e8210 MM |
352 | } |
353 | ||
a560d4d4 JH |
354 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
355 | ||
aebf76a2 TS |
356 | hashval_t |
357 | reg_attr_hasher::hash (reg_attrs *x) | |
a560d4d4 | 358 | { |
aebf76a2 | 359 | const reg_attrs *const p = x; |
a560d4d4 | 360 | |
9841210f | 361 | return ((p->offset * 1000) ^ (intptr_t) p->decl); |
a560d4d4 JH |
362 | } |
363 | ||
aebf76a2 TS |
364 | /* Returns nonzero if the value represented by X is the same as that given by |
365 | Y. */ | |
a560d4d4 | 366 | |
aebf76a2 TS |
367 | bool |
368 | reg_attr_hasher::equal (reg_attrs *x, reg_attrs *y) | |
a560d4d4 | 369 | { |
aebf76a2 TS |
370 | const reg_attrs *const p = x; |
371 | const reg_attrs *const q = y; | |
a560d4d4 JH |
372 | |
373 | return (p->decl == q->decl && p->offset == q->offset); | |
374 | } | |
375 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
376 | one identical to it is not already in the table. We are doing this for | |
377 | MEM of mode MODE. */ | |
378 | ||
379 | static reg_attrs * | |
502b8322 | 380 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
381 | { |
382 | reg_attrs attrs; | |
a560d4d4 JH |
383 | |
384 | /* If everything is the default, we can just return zero. */ | |
385 | if (decl == 0 && offset == 0) | |
386 | return 0; | |
387 | ||
388 | attrs.decl = decl; | |
389 | attrs.offset = offset; | |
390 | ||
aebf76a2 | 391 | reg_attrs **slot = reg_attrs_htab->find_slot (&attrs, INSERT); |
a560d4d4 JH |
392 | if (*slot == 0) |
393 | { | |
766090c2 | 394 | *slot = ggc_alloc<reg_attrs> (); |
a560d4d4 JH |
395 | memcpy (*slot, &attrs, sizeof (reg_attrs)); |
396 | } | |
397 | ||
aebf76a2 | 398 | return *slot; |
a560d4d4 JH |
399 | } |
400 | ||
6fb5fa3c DB |
401 | |
402 | #if !HAVE_blockage | |
adddc347 HPN |
403 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule, |
404 | and to block register equivalences to be seen across this insn. */ | |
6fb5fa3c DB |
405 | |
406 | rtx | |
407 | gen_blockage (void) | |
408 | { | |
409 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
410 | MEM_VOLATILE_P (x) = true; | |
411 | return x; | |
412 | } | |
413 | #endif | |
414 | ||
415 | ||
8deccbb7 RS |
416 | /* Set the mode and register number of X to MODE and REGNO. */ |
417 | ||
418 | void | |
419 | set_mode_and_regno (rtx x, machine_mode mode, unsigned int regno) | |
420 | { | |
9188b286 | 421 | unsigned int nregs = (HARD_REGISTER_NUM_P (regno) |
ad474626 | 422 | ? hard_regno_nregs (regno, mode) |
9188b286 | 423 | : 1); |
8deccbb7 | 424 | PUT_MODE_RAW (x, mode); |
9188b286 | 425 | set_regno_raw (x, regno, nregs); |
8deccbb7 RS |
426 | } |
427 | ||
08394eef BS |
428 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
429 | don't attempt to share with the various global pieces of rtl (such as | |
430 | frame_pointer_rtx). */ | |
431 | ||
432 | rtx | |
8deccbb7 | 433 | gen_raw_REG (machine_mode mode, unsigned int regno) |
08394eef | 434 | { |
84c2ad23 | 435 | rtx x = rtx_alloc (REG MEM_STAT_INFO); |
8deccbb7 | 436 | set_mode_and_regno (x, mode, regno); |
9fccb335 | 437 | REG_ATTRS (x) = NULL; |
08394eef BS |
438 | ORIGINAL_REGNO (x) = regno; |
439 | return x; | |
440 | } | |
441 | ||
c5c76735 JL |
442 | /* There are some RTL codes that require special attention; the generation |
443 | functions do the raw handling. If you add to this list, modify | |
444 | special_rtx in gengenrtl.c as well. */ | |
445 | ||
38e60c55 | 446 | rtx_expr_list * |
ef4bddc2 | 447 | gen_rtx_EXPR_LIST (machine_mode mode, rtx expr, rtx expr_list) |
38e60c55 DM |
448 | { |
449 | return as_a <rtx_expr_list *> (gen_rtx_fmt_ee (EXPR_LIST, mode, expr, | |
450 | expr_list)); | |
451 | } | |
452 | ||
a756c6be | 453 | rtx_insn_list * |
ef4bddc2 | 454 | gen_rtx_INSN_LIST (machine_mode mode, rtx insn, rtx insn_list) |
a756c6be DM |
455 | { |
456 | return as_a <rtx_insn_list *> (gen_rtx_fmt_ue (INSN_LIST, mode, insn, | |
457 | insn_list)); | |
458 | } | |
459 | ||
d6e1e8b8 | 460 | rtx_insn * |
ef4bddc2 | 461 | gen_rtx_INSN (machine_mode mode, rtx_insn *prev_insn, rtx_insn *next_insn, |
d6e1e8b8 DM |
462 | basic_block bb, rtx pattern, int location, int code, |
463 | rtx reg_notes) | |
464 | { | |
465 | return as_a <rtx_insn *> (gen_rtx_fmt_uuBeiie (INSN, mode, | |
466 | prev_insn, next_insn, | |
467 | bb, pattern, location, code, | |
468 | reg_notes)); | |
469 | } | |
470 | ||
3b80f6ca | 471 | rtx |
ef4bddc2 | 472 | gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca RH |
473 | { |
474 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) | |
5da077de | 475 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
476 | |
477 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
478 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
479 | return const_true_rtx; | |
480 | #endif | |
481 | ||
c13e8210 | 482 | /* Look up the CONST_INT in the hash table. */ |
aebf76a2 TS |
483 | rtx *slot = const_int_htab->find_slot_with_hash (arg, (hashval_t) arg, |
484 | INSERT); | |
29105cea | 485 | if (*slot == 0) |
1f8f4a0b | 486 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 | 487 | |
aebf76a2 | 488 | return *slot; |
3b80f6ca RH |
489 | } |
490 | ||
2496c7bd | 491 | rtx |
ef4bddc2 | 492 | gen_int_mode (HOST_WIDE_INT c, machine_mode mode) |
2496c7bd LB |
493 | { |
494 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
495 | } | |
496 | ||
5692c7bc ZW |
497 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
498 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
499 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
500 | ||
501 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
502 | hash table. If so, return its counterpart; otherwise add it | |
503 | to the hash table and return it. */ | |
504 | static rtx | |
502b8322 | 505 | lookup_const_double (rtx real) |
5692c7bc | 506 | { |
aebf76a2 | 507 | rtx *slot = const_double_htab->find_slot (real, INSERT); |
5692c7bc ZW |
508 | if (*slot == 0) |
509 | *slot = real; | |
510 | ||
aebf76a2 | 511 | return *slot; |
5692c7bc | 512 | } |
29105cea | 513 | |
5692c7bc ZW |
514 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
515 | VALUE in mode MODE. */ | |
0133b7d9 | 516 | rtx |
ef4bddc2 | 517 | const_double_from_real_value (REAL_VALUE_TYPE value, machine_mode mode) |
0133b7d9 | 518 | { |
5692c7bc ZW |
519 | rtx real = rtx_alloc (CONST_DOUBLE); |
520 | PUT_MODE (real, mode); | |
521 | ||
9e254451 | 522 | real->u.rv = value; |
5692c7bc ZW |
523 | |
524 | return lookup_const_double (real); | |
525 | } | |
526 | ||
091a3ac7 CF |
527 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
528 | hash table. If so, return its counterpart; otherwise add it | |
529 | to the hash table and return it. */ | |
530 | ||
531 | static rtx | |
532 | lookup_const_fixed (rtx fixed) | |
533 | { | |
aebf76a2 | 534 | rtx *slot = const_fixed_htab->find_slot (fixed, INSERT); |
091a3ac7 CF |
535 | if (*slot == 0) |
536 | *slot = fixed; | |
537 | ||
aebf76a2 | 538 | return *slot; |
091a3ac7 CF |
539 | } |
540 | ||
541 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
542 | VALUE in mode MODE. */ | |
543 | ||
544 | rtx | |
ef4bddc2 | 545 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, machine_mode mode) |
091a3ac7 CF |
546 | { |
547 | rtx fixed = rtx_alloc (CONST_FIXED); | |
548 | PUT_MODE (fixed, mode); | |
549 | ||
550 | fixed->u.fv = value; | |
551 | ||
552 | return lookup_const_fixed (fixed); | |
553 | } | |
554 | ||
807e902e | 555 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
3e93ff81 AS |
556 | /* Constructs double_int from rtx CST. */ |
557 | ||
558 | double_int | |
559 | rtx_to_double_int (const_rtx cst) | |
560 | { | |
561 | double_int r; | |
562 | ||
563 | if (CONST_INT_P (cst)) | |
27bcd47c | 564 | r = double_int::from_shwi (INTVAL (cst)); |
48175537 | 565 | else if (CONST_DOUBLE_AS_INT_P (cst)) |
3e93ff81 AS |
566 | { |
567 | r.low = CONST_DOUBLE_LOW (cst); | |
568 | r.high = CONST_DOUBLE_HIGH (cst); | |
569 | } | |
570 | else | |
571 | gcc_unreachable (); | |
572 | ||
573 | return r; | |
574 | } | |
807e902e | 575 | #endif |
3e93ff81 | 576 | |
807e902e KZ |
577 | #if TARGET_SUPPORTS_WIDE_INT |
578 | /* Determine whether CONST_WIDE_INT WINT already exists in the hash table. | |
579 | If so, return its counterpart; otherwise add it to the hash table and | |
580 | return it. */ | |
3e93ff81 | 581 | |
807e902e KZ |
582 | static rtx |
583 | lookup_const_wide_int (rtx wint) | |
584 | { | |
aebf76a2 | 585 | rtx *slot = const_wide_int_htab->find_slot (wint, INSERT); |
807e902e KZ |
586 | if (*slot == 0) |
587 | *slot = wint; | |
588 | ||
aebf76a2 | 589 | return *slot; |
807e902e KZ |
590 | } |
591 | #endif | |
592 | ||
593 | /* Return an rtx constant for V, given that the constant has mode MODE. | |
594 | The returned rtx will be a CONST_INT if V fits, otherwise it will be | |
595 | a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT | |
596 | (if TARGET_SUPPORTS_WIDE_INT). */ | |
54fb1ae0 AS |
597 | |
598 | rtx | |
ef4bddc2 | 599 | immed_wide_int_const (const wide_int_ref &v, machine_mode mode) |
54fb1ae0 | 600 | { |
807e902e | 601 | unsigned int len = v.get_len (); |
db61b7f9 RS |
602 | /* Not scalar_int_mode because we also allow pointer bound modes. */ |
603 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
807e902e KZ |
604 | |
605 | /* Allow truncation but not extension since we do not know if the | |
606 | number is signed or unsigned. */ | |
607 | gcc_assert (prec <= v.get_precision ()); | |
608 | ||
609 | if (len < 2 || prec <= HOST_BITS_PER_WIDE_INT) | |
610 | return gen_int_mode (v.elt (0), mode); | |
611 | ||
612 | #if TARGET_SUPPORTS_WIDE_INT | |
613 | { | |
614 | unsigned int i; | |
615 | rtx value; | |
616 | unsigned int blocks_needed | |
617 | = (prec + HOST_BITS_PER_WIDE_INT - 1) / HOST_BITS_PER_WIDE_INT; | |
618 | ||
619 | if (len > blocks_needed) | |
620 | len = blocks_needed; | |
621 | ||
622 | value = const_wide_int_alloc (len); | |
623 | ||
624 | /* It is so tempting to just put the mode in here. Must control | |
625 | myself ... */ | |
626 | PUT_MODE (value, VOIDmode); | |
627 | CWI_PUT_NUM_ELEM (value, len); | |
628 | ||
629 | for (i = 0; i < len; i++) | |
630 | CONST_WIDE_INT_ELT (value, i) = v.elt (i); | |
631 | ||
632 | return lookup_const_wide_int (value); | |
633 | } | |
634 | #else | |
635 | return immed_double_const (v.elt (0), v.elt (1), mode); | |
636 | #endif | |
54fb1ae0 AS |
637 | } |
638 | ||
807e902e | 639 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
5692c7bc ZW |
640 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
641 | of ints: I0 is the low-order word and I1 is the high-order word. | |
49ab6098 | 642 | For values that are larger than HOST_BITS_PER_DOUBLE_INT, the |
929e10f4 MS |
643 | implied upper bits are copies of the high bit of i1. The value |
644 | itself is neither signed nor unsigned. Do not use this routine for | |
645 | non-integer modes; convert to REAL_VALUE_TYPE and use | |
555affd7 | 646 | const_double_from_real_value. */ |
5692c7bc ZW |
647 | |
648 | rtx | |
ef4bddc2 | 649 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, machine_mode mode) |
5692c7bc ZW |
650 | { |
651 | rtx value; | |
652 | unsigned int i; | |
653 | ||
65acccdd | 654 | /* There are the following cases (note that there are no modes with |
49ab6098 | 655 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT): |
65acccdd ZD |
656 | |
657 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
658 | gen_int_mode. | |
929e10f4 MS |
659 | 2) If the value of the integer fits into HOST_WIDE_INT anyway |
660 | (i.e., i1 consists only from copies of the sign bit, and sign | |
661 | of i0 and i1 are the same), then we return a CONST_INT for i0. | |
65acccdd | 662 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ |
db61b7f9 RS |
663 | scalar_mode smode; |
664 | if (is_a <scalar_mode> (mode, &smode) | |
665 | && GET_MODE_BITSIZE (smode) <= HOST_BITS_PER_WIDE_INT) | |
666 | return gen_int_mode (i0, mode); | |
5692c7bc ZW |
667 | |
668 | /* If this integer fits in one word, return a CONST_INT. */ | |
669 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
670 | return GEN_INT (i0); | |
671 | ||
672 | /* We use VOIDmode for integers. */ | |
673 | value = rtx_alloc (CONST_DOUBLE); | |
674 | PUT_MODE (value, VOIDmode); | |
675 | ||
676 | CONST_DOUBLE_LOW (value) = i0; | |
677 | CONST_DOUBLE_HIGH (value) = i1; | |
678 | ||
679 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
680 | XWINT (value, i) = 0; | |
681 | ||
682 | return lookup_const_double (value); | |
0133b7d9 | 683 | } |
807e902e | 684 | #endif |
0133b7d9 | 685 | |
3b80f6ca | 686 | rtx |
ef4bddc2 | 687 | gen_rtx_REG (machine_mode mode, unsigned int regno) |
3b80f6ca RH |
688 | { |
689 | /* In case the MD file explicitly references the frame pointer, have | |
690 | all such references point to the same frame pointer. This is | |
691 | used during frame pointer elimination to distinguish the explicit | |
692 | references to these registers from pseudos that happened to be | |
693 | assigned to them. | |
694 | ||
695 | If we have eliminated the frame pointer or arg pointer, we will | |
696 | be using it as a normal register, for example as a spill | |
697 | register. In such cases, we might be accessing it in a mode that | |
698 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
699 | ||
700 | Also don't do this when we are making new REGs in reload, since | |
701 | we don't want to get confused with the real pointers. */ | |
702 | ||
55a2c322 | 703 | if (mode == Pmode && !reload_in_progress && !lra_in_progress) |
3b80f6ca | 704 | { |
e10c79fe LB |
705 | if (regno == FRAME_POINTER_REGNUM |
706 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca | 707 | return frame_pointer_rtx; |
c3e08036 TS |
708 | |
709 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER | |
710 | && regno == HARD_FRAME_POINTER_REGNUM | |
e10c79fe | 711 | && (!reload_completed || frame_pointer_needed)) |
3b80f6ca | 712 | return hard_frame_pointer_rtx; |
3f393fc6 TS |
713 | #if !HARD_FRAME_POINTER_IS_ARG_POINTER |
714 | if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
715 | && regno == ARG_POINTER_REGNUM) | |
3b80f6ca RH |
716 | return arg_pointer_rtx; |
717 | #endif | |
718 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 719 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
720 | return return_address_pointer_rtx; |
721 | #endif | |
fc555370 | 722 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
bf9412cd | 723 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM |
2d67bd7b | 724 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 725 | return pic_offset_table_rtx; |
bcb33994 | 726 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
727 | return stack_pointer_rtx; |
728 | } | |
729 | ||
006a94b0 | 730 | #if 0 |
6cde4876 | 731 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
732 | an existing entry in that table to avoid useless generation of RTL. |
733 | ||
734 | This code is disabled for now until we can fix the various backends | |
735 | which depend on having non-shared hard registers in some cases. Long | |
736 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
737 | on the amount of useless RTL that gets generated. |
738 | ||
739 | We'll also need to fix some code that runs after reload that wants to | |
740 | set ORIGINAL_REGNO. */ | |
741 | ||
6cde4876 JL |
742 | if (cfun |
743 | && cfun->emit | |
744 | && regno_reg_rtx | |
745 | && regno < FIRST_PSEUDO_REGISTER | |
746 | && reg_raw_mode[regno] == mode) | |
747 | return regno_reg_rtx[regno]; | |
006a94b0 | 748 | #endif |
6cde4876 | 749 | |
08394eef | 750 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
751 | } |
752 | ||
41472af8 | 753 | rtx |
ef4bddc2 | 754 | gen_rtx_MEM (machine_mode mode, rtx addr) |
41472af8 MM |
755 | { |
756 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
757 | ||
758 | /* This field is not cleared by the mere allocation of the rtx, so | |
759 | we clear it here. */ | |
173b24b9 | 760 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
761 | |
762 | return rt; | |
763 | } | |
ddef6bc7 | 764 | |
542a8afa RH |
765 | /* Generate a memory referring to non-trapping constant memory. */ |
766 | ||
767 | rtx | |
ef4bddc2 | 768 | gen_const_mem (machine_mode mode, rtx addr) |
542a8afa RH |
769 | { |
770 | rtx mem = gen_rtx_MEM (mode, addr); | |
771 | MEM_READONLY_P (mem) = 1; | |
772 | MEM_NOTRAP_P (mem) = 1; | |
773 | return mem; | |
774 | } | |
775 | ||
bf877a76 R |
776 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
777 | save areas. */ | |
778 | ||
779 | rtx | |
ef4bddc2 | 780 | gen_frame_mem (machine_mode mode, rtx addr) |
bf877a76 R |
781 | { |
782 | rtx mem = gen_rtx_MEM (mode, addr); | |
783 | MEM_NOTRAP_P (mem) = 1; | |
784 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
785 | return mem; | |
786 | } | |
787 | ||
788 | /* Generate a MEM referring to a temporary use of the stack, not part | |
789 | of the fixed stack frame. For example, something which is pushed | |
790 | by a target splitter. */ | |
791 | rtx | |
ef4bddc2 | 792 | gen_tmp_stack_mem (machine_mode mode, rtx addr) |
bf877a76 R |
793 | { |
794 | rtx mem = gen_rtx_MEM (mode, addr); | |
795 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 796 | if (!cfun->calls_alloca) |
bf877a76 R |
797 | set_mem_alias_set (mem, get_frame_alias_set ()); |
798 | return mem; | |
799 | } | |
800 | ||
beb72684 RH |
801 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
802 | this construct would be valid, and false otherwise. */ | |
803 | ||
804 | bool | |
ef4bddc2 | 805 | validate_subreg (machine_mode omode, machine_mode imode, |
ed7a4b4b | 806 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 807 | { |
beb72684 RH |
808 | unsigned int isize = GET_MODE_SIZE (imode); |
809 | unsigned int osize = GET_MODE_SIZE (omode); | |
810 | ||
811 | /* All subregs must be aligned. */ | |
812 | if (offset % osize != 0) | |
813 | return false; | |
814 | ||
815 | /* The subreg offset cannot be outside the inner object. */ | |
816 | if (offset >= isize) | |
817 | return false; | |
818 | ||
1eae67f8 RS |
819 | unsigned int regsize = REGMODE_NATURAL_SIZE (imode); |
820 | ||
beb72684 RH |
821 | /* ??? This should not be here. Temporarily continue to allow word_mode |
822 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
823 | Generally, backends are doing something sketchy but it'll take time to | |
824 | fix them all. */ | |
825 | if (omode == word_mode) | |
826 | ; | |
827 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
828 | is the culprit here, and not the backends. */ | |
1eae67f8 | 829 | else if (osize >= regsize && isize >= osize) |
beb72684 RH |
830 | ; |
831 | /* Allow component subregs of complex and vector. Though given the below | |
832 | extraction rules, it's not always clear what that means. */ | |
833 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
834 | && GET_MODE_INNER (imode) == omode) | |
835 | ; | |
836 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
837 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
838 | represent this. It's questionable if this ought to be represented at | |
839 | all -- why can't this all be hidden in post-reload splitters that make | |
840 | arbitrarily mode changes to the registers themselves. */ | |
841 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
842 | ; | |
843 | /* Subregs involving floating point modes are not allowed to | |
844 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
845 | (subreg:SI (reg:DF) 0) isn't. */ | |
846 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
847 | { | |
55a2c322 VM |
848 | if (! (isize == osize |
849 | /* LRA can use subreg to store a floating point value in | |
850 | an integer mode. Although the floating point and the | |
851 | integer modes need the same number of hard registers, | |
852 | the size of floating point mode can be less than the | |
853 | integer mode. LRA also uses subregs for a register | |
854 | should be used in different mode in on insn. */ | |
855 | || lra_in_progress)) | |
beb72684 RH |
856 | return false; |
857 | } | |
ddef6bc7 | 858 | |
beb72684 RH |
859 | /* Paradoxical subregs must have offset zero. */ |
860 | if (osize > isize) | |
861 | return offset == 0; | |
862 | ||
863 | /* This is a normal subreg. Verify that the offset is representable. */ | |
864 | ||
865 | /* For hard registers, we already have most of these rules collected in | |
866 | subreg_offset_representable_p. */ | |
867 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
868 | { | |
869 | unsigned int regno = REGNO (reg); | |
870 | ||
beb72684 RH |
871 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) |
872 | && GET_MODE_INNER (imode) == omode) | |
873 | ; | |
0d803030 | 874 | else if (!REG_CAN_CHANGE_MODE_P (regno, imode, omode)) |
beb72684 | 875 | return false; |
beb72684 RH |
876 | |
877 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
878 | } | |
879 | ||
880 | /* For pseudo registers, we want most of the same checks. Namely: | |
1eae67f8 RS |
881 | |
882 | Assume that the pseudo register will be allocated to hard registers | |
883 | that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE, | |
884 | the remainder must correspond to the lowpart of the containing hard | |
885 | register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset, | |
886 | otherwise it is at the lowest offset. | |
887 | ||
888 | Given that we've already checked the mode and offset alignment, | |
889 | we only have to check subblock subregs here. */ | |
890 | if (osize < regsize | |
55a2c322 | 891 | && ! (lra_in_progress && (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)))) |
beb72684 | 892 | { |
1eae67f8 RS |
893 | unsigned int block_size = MIN (isize, regsize); |
894 | unsigned int offset_within_block = offset % block_size; | |
895 | if (BYTES_BIG_ENDIAN | |
896 | ? offset_within_block != block_size - osize | |
897 | : offset_within_block != 0) | |
beb72684 RH |
898 | return false; |
899 | } | |
900 | return true; | |
901 | } | |
902 | ||
903 | rtx | |
ef4bddc2 | 904 | gen_rtx_SUBREG (machine_mode mode, rtx reg, int offset) |
beb72684 RH |
905 | { |
906 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 907 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
908 | } |
909 | ||
173b24b9 RK |
910 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
911 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
912 | ||
ddef6bc7 | 913 | rtx |
ef4bddc2 | 914 | gen_lowpart_SUBREG (machine_mode mode, rtx reg) |
ddef6bc7 | 915 | { |
ef4bddc2 | 916 | machine_mode inmode; |
ddef6bc7 JJ |
917 | |
918 | inmode = GET_MODE (reg); | |
919 | if (inmode == VOIDmode) | |
920 | inmode = mode; | |
e0e08ac2 JH |
921 | return gen_rtx_SUBREG (mode, reg, |
922 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 923 | } |
fcc74520 RS |
924 | |
925 | rtx | |
ef4bddc2 | 926 | gen_rtx_VAR_LOCATION (machine_mode mode, tree decl, rtx loc, |
fcc74520 RS |
927 | enum var_init_status status) |
928 | { | |
929 | rtx x = gen_rtx_fmt_te (VAR_LOCATION, mode, decl, loc); | |
930 | PAT_VAR_LOCATION_STATUS (x) = status; | |
931 | return x; | |
932 | } | |
c5c76735 | 933 | \f |
23b2ce53 | 934 | |
80379f51 PB |
935 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
936 | ||
23b2ce53 | 937 | rtvec |
e34d07f2 | 938 | gen_rtvec (int n, ...) |
23b2ce53 | 939 | { |
80379f51 PB |
940 | int i; |
941 | rtvec rt_val; | |
e34d07f2 | 942 | va_list p; |
23b2ce53 | 943 | |
e34d07f2 | 944 | va_start (p, n); |
23b2ce53 | 945 | |
80379f51 | 946 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 947 | if (n == 0) |
0edf1bb2 JL |
948 | { |
949 | va_end (p); | |
950 | return NULL_RTVEC; | |
951 | } | |
23b2ce53 | 952 | |
80379f51 | 953 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 954 | |
23b2ce53 | 955 | for (i = 0; i < n; i++) |
80379f51 | 956 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 957 | |
e34d07f2 | 958 | va_end (p); |
80379f51 | 959 | return rt_val; |
23b2ce53 RS |
960 | } |
961 | ||
962 | rtvec | |
502b8322 | 963 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 964 | { |
b3694847 SS |
965 | int i; |
966 | rtvec rt_val; | |
23b2ce53 | 967 | |
80379f51 | 968 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 969 | if (n == 0) |
80379f51 | 970 | return NULL_RTVEC; |
23b2ce53 | 971 | |
80379f51 | 972 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
973 | |
974 | for (i = 0; i < n; i++) | |
8f985ec4 | 975 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
976 | |
977 | return rt_val; | |
978 | } | |
e6eda746 DM |
979 | |
980 | rtvec | |
981 | gen_rtvec_v (int n, rtx_insn **argp) | |
982 | { | |
983 | int i; | |
984 | rtvec rt_val; | |
985 | ||
986 | /* Don't allocate an empty rtvec... */ | |
987 | if (n == 0) | |
988 | return NULL_RTVEC; | |
989 | ||
990 | rt_val = rtvec_alloc (n); | |
991 | ||
992 | for (i = 0; i < n; i++) | |
993 | rt_val->elem[i] = *argp++; | |
994 | ||
995 | return rt_val; | |
996 | } | |
997 | ||
23b2ce53 | 998 | \f |
38ae7651 RS |
999 | /* Return the number of bytes between the start of an OUTER_MODE |
1000 | in-memory value and the start of an INNER_MODE in-memory value, | |
1001 | given that the former is a lowpart of the latter. It may be a | |
1002 | paradoxical lowpart, in which case the offset will be negative | |
1003 | on big-endian targets. */ | |
1004 | ||
1005 | int | |
ef4bddc2 RS |
1006 | byte_lowpart_offset (machine_mode outer_mode, |
1007 | machine_mode inner_mode) | |
38ae7651 | 1008 | { |
03a95621 | 1009 | if (paradoxical_subreg_p (outer_mode, inner_mode)) |
38ae7651 | 1010 | return -subreg_lowpart_offset (inner_mode, outer_mode); |
03a95621 RS |
1011 | else |
1012 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
38ae7651 | 1013 | } |
3d09ba95 RS |
1014 | |
1015 | /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET) | |
1016 | from address X. For paradoxical big-endian subregs this is a | |
1017 | negative value, otherwise it's the same as OFFSET. */ | |
1018 | ||
1019 | int | |
1020 | subreg_memory_offset (machine_mode outer_mode, machine_mode inner_mode, | |
1021 | unsigned int offset) | |
1022 | { | |
1023 | if (paradoxical_subreg_p (outer_mode, inner_mode)) | |
1024 | { | |
1025 | gcc_assert (offset == 0); | |
1026 | return -subreg_lowpart_offset (inner_mode, outer_mode); | |
1027 | } | |
1028 | return offset; | |
1029 | } | |
1030 | ||
1031 | /* As above, but return the offset that existing subreg X would have | |
1032 | if SUBREG_REG (X) were stored in memory. The only significant thing | |
1033 | about the current SUBREG_REG is its mode. */ | |
1034 | ||
1035 | int | |
1036 | subreg_memory_offset (const_rtx x) | |
1037 | { | |
1038 | return subreg_memory_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)), | |
1039 | SUBREG_BYTE (x)); | |
1040 | } | |
38ae7651 | 1041 | \f |
23b2ce53 RS |
1042 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
1043 | This pseudo is assigned the next sequential register number. */ | |
1044 | ||
1045 | rtx | |
ef4bddc2 | 1046 | gen_reg_rtx (machine_mode mode) |
23b2ce53 | 1047 | { |
b3694847 | 1048 | rtx val; |
2e3f842f | 1049 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 1050 | |
f8335a4f | 1051 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 1052 | |
2e3f842f L |
1053 | /* If a virtual register with bigger mode alignment is generated, |
1054 | increase stack alignment estimation because it might be spilled | |
1055 | to stack later. */ | |
b8698a0f | 1056 | if (SUPPORTS_STACK_ALIGNMENT |
2e3f842f L |
1057 | && crtl->stack_alignment_estimated < align |
1058 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
1059 | { |
1060 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
1061 | if (crtl->stack_alignment_estimated < min_align) | |
1062 | crtl->stack_alignment_estimated = min_align; | |
1063 | } | |
2e3f842f | 1064 | |
1b3d8f8a GK |
1065 | if (generating_concat_p |
1066 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
1067 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
1068 | { |
1069 | /* For complex modes, don't make a single pseudo. | |
1070 | Instead, make a CONCAT of two pseudos. | |
1071 | This allows noncontiguous allocation of the real and imaginary parts, | |
1072 | which makes much better code. Besides, allocating DCmode | |
1073 | pseudos overstrains reload on some machines like the 386. */ | |
1074 | rtx realpart, imagpart; | |
ef4bddc2 | 1075 | machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
1076 | |
1077 | realpart = gen_reg_rtx (partmode); | |
1078 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 1079 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
1080 | } |
1081 | ||
004a7e45 UB |
1082 | /* Do not call gen_reg_rtx with uninitialized crtl. */ |
1083 | gcc_assert (crtl->emit.regno_pointer_align_length); | |
1084 | ||
f44986d7 DM |
1085 | crtl->emit.ensure_regno_capacity (); |
1086 | gcc_assert (reg_rtx_no < crtl->emit.regno_pointer_align_length); | |
23b2ce53 | 1087 | |
f44986d7 DM |
1088 | val = gen_raw_REG (mode, reg_rtx_no); |
1089 | regno_reg_rtx[reg_rtx_no++] = val; | |
1090 | return val; | |
1091 | } | |
0d4903b8 | 1092 | |
f44986d7 DM |
1093 | /* Make sure m_regno_pointer_align, and regno_reg_rtx are large |
1094 | enough to have elements in the range 0 <= idx <= reg_rtx_no. */ | |
49ad7cfa | 1095 | |
f44986d7 DM |
1096 | void |
1097 | emit_status::ensure_regno_capacity () | |
1098 | { | |
1099 | int old_size = regno_pointer_align_length; | |
23b2ce53 | 1100 | |
f44986d7 DM |
1101 | if (reg_rtx_no < old_size) |
1102 | return; | |
23b2ce53 | 1103 | |
f44986d7 DM |
1104 | int new_size = old_size * 2; |
1105 | while (reg_rtx_no >= new_size) | |
1106 | new_size *= 2; | |
1107 | ||
1108 | char *tmp = XRESIZEVEC (char, regno_pointer_align, new_size); | |
1109 | memset (tmp + old_size, 0, new_size - old_size); | |
1110 | regno_pointer_align = (unsigned char *) tmp; | |
1111 | ||
1112 | rtx *new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, new_size); | |
1113 | memset (new1 + old_size, 0, (new_size - old_size) * sizeof (rtx)); | |
1114 | regno_reg_rtx = new1; | |
1115 | ||
1116 | crtl->emit.regno_pointer_align_length = new_size; | |
23b2ce53 RS |
1117 | } |
1118 | ||
a698cc03 JL |
1119 | /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */ |
1120 | ||
1121 | bool | |
1122 | reg_is_parm_p (rtx reg) | |
1123 | { | |
1124 | tree decl; | |
1125 | ||
1126 | gcc_assert (REG_P (reg)); | |
1127 | decl = REG_EXPR (reg); | |
1128 | return (decl && TREE_CODE (decl) == PARM_DECL); | |
1129 | } | |
1130 | ||
38ae7651 RS |
1131 | /* Update NEW with the same attributes as REG, but with OFFSET added |
1132 | to the REG_OFFSET. */ | |
a560d4d4 | 1133 | |
e53a16e7 | 1134 | static void |
60564289 | 1135 | update_reg_offset (rtx new_rtx, rtx reg, int offset) |
a560d4d4 | 1136 | { |
60564289 | 1137 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 1138 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
1139 | } |
1140 | ||
38ae7651 RS |
1141 | /* Generate a register with same attributes as REG, but with OFFSET |
1142 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
1143 | |
1144 | rtx | |
ef4bddc2 | 1145 | gen_rtx_REG_offset (rtx reg, machine_mode mode, unsigned int regno, |
e53a16e7 ILT |
1146 | int offset) |
1147 | { | |
60564289 | 1148 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 1149 | |
60564289 KG |
1150 | update_reg_offset (new_rtx, reg, offset); |
1151 | return new_rtx; | |
e53a16e7 ILT |
1152 | } |
1153 | ||
1154 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 1155 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
1156 | |
1157 | rtx | |
ef4bddc2 | 1158 | gen_reg_rtx_offset (rtx reg, machine_mode mode, int offset) |
e53a16e7 | 1159 | { |
60564289 | 1160 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 1161 | |
60564289 KG |
1162 | update_reg_offset (new_rtx, reg, offset); |
1163 | return new_rtx; | |
a560d4d4 JH |
1164 | } |
1165 | ||
38ae7651 RS |
1166 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
1167 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
1168 | |
1169 | void | |
ef4bddc2 | 1170 | adjust_reg_mode (rtx reg, machine_mode mode) |
a560d4d4 | 1171 | { |
38ae7651 RS |
1172 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
1173 | PUT_MODE (reg, mode); | |
1174 | } | |
1175 | ||
1176 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
1177 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
1178 | ||
1179 | void | |
1180 | set_reg_attrs_from_value (rtx reg, rtx x) | |
1181 | { | |
1182 | int offset; | |
de6f3f7a L |
1183 | bool can_be_reg_pointer = true; |
1184 | ||
1185 | /* Don't call mark_reg_pointer for incompatible pointer sign | |
1186 | extension. */ | |
1187 | while (GET_CODE (x) == SIGN_EXTEND | |
1188 | || GET_CODE (x) == ZERO_EXTEND | |
1189 | || GET_CODE (x) == TRUNCATE | |
1190 | || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x))) | |
1191 | { | |
2a870875 RS |
1192 | #if defined(POINTERS_EXTEND_UNSIGNED) |
1193 | if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED) | |
8d8e740c BE |
1194 | || (GET_CODE (x) == ZERO_EXTEND && ! POINTERS_EXTEND_UNSIGNED) |
1195 | || (paradoxical_subreg_p (x) | |
1196 | && ! (SUBREG_PROMOTED_VAR_P (x) | |
1197 | && SUBREG_CHECK_PROMOTED_SIGN (x, | |
1198 | POINTERS_EXTEND_UNSIGNED)))) | |
2a870875 | 1199 | && !targetm.have_ptr_extend ()) |
de6f3f7a L |
1200 | can_be_reg_pointer = false; |
1201 | #endif | |
1202 | x = XEXP (x, 0); | |
1203 | } | |
38ae7651 | 1204 | |
923ba36f JJ |
1205 | /* Hard registers can be reused for multiple purposes within the same |
1206 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
1207 | on them is wrong. */ | |
1208 | if (HARD_REGISTER_P (reg)) | |
1209 | return; | |
1210 | ||
38ae7651 | 1211 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
1212 | if (MEM_P (x)) |
1213 | { | |
527210c4 RS |
1214 | if (MEM_OFFSET_KNOWN_P (x)) |
1215 | REG_ATTRS (reg) = get_reg_attrs (MEM_EXPR (x), | |
1216 | MEM_OFFSET (x) + offset); | |
de6f3f7a | 1217 | if (can_be_reg_pointer && MEM_POINTER (x)) |
0a317111 | 1218 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
1219 | } |
1220 | else if (REG_P (x)) | |
1221 | { | |
1222 | if (REG_ATTRS (x)) | |
1223 | update_reg_offset (reg, x, offset); | |
de6f3f7a | 1224 | if (can_be_reg_pointer && REG_POINTER (x)) |
46b71b03 PB |
1225 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
1230 | and attributes from X. */ | |
1231 | ||
1232 | rtx | |
1233 | gen_reg_rtx_and_attrs (rtx x) | |
1234 | { | |
1235 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1236 | set_reg_attrs_from_value (reg, x); | |
1237 | return reg; | |
a560d4d4 JH |
1238 | } |
1239 | ||
9d18e06b JZ |
1240 | /* Set the register attributes for registers contained in PARM_RTX. |
1241 | Use needed values from memory attributes of MEM. */ | |
1242 | ||
1243 | void | |
502b8322 | 1244 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1245 | { |
f8cfc6aa | 1246 | if (REG_P (parm_rtx)) |
38ae7651 | 1247 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1248 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1249 | { | |
1250 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1251 | parameter goes both on the stack and in registers. */ | |
1252 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1253 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1254 | { | |
1255 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1256 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1257 | REG_ATTRS (XEXP (x, 0)) |
1258 | = get_reg_attrs (MEM_EXPR (mem), | |
1259 | INTVAL (XEXP (x, 1))); | |
1260 | } | |
1261 | } | |
1262 | } | |
1263 | ||
38ae7651 RS |
1264 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1265 | decl T. */ | |
a560d4d4 | 1266 | |
4e3825db | 1267 | void |
38ae7651 RS |
1268 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1269 | { | |
1f9ceff1 AO |
1270 | if (!t) |
1271 | return; | |
1272 | tree tdecl = t; | |
38ae7651 | 1273 | if (GET_CODE (x) == SUBREG) |
fbe6ec81 | 1274 | { |
38ae7651 RS |
1275 | gcc_assert (subreg_lowpart_p (x)); |
1276 | x = SUBREG_REG (x); | |
fbe6ec81 | 1277 | } |
f8cfc6aa | 1278 | if (REG_P (x)) |
38ae7651 RS |
1279 | REG_ATTRS (x) |
1280 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
1f9ceff1 AO |
1281 | DECL_P (tdecl) |
1282 | ? DECL_MODE (tdecl) | |
1283 | : TYPE_MODE (TREE_TYPE (tdecl)))); | |
a560d4d4 JH |
1284 | if (GET_CODE (x) == CONCAT) |
1285 | { | |
1286 | if (REG_P (XEXP (x, 0))) | |
1287 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1288 | if (REG_P (XEXP (x, 1))) | |
1289 | REG_ATTRS (XEXP (x, 1)) | |
1290 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1291 | } | |
1292 | if (GET_CODE (x) == PARALLEL) | |
1293 | { | |
d4afac5b JZ |
1294 | int i, start; |
1295 | ||
1296 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1297 | both on the stack and in registers. */ | |
1298 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1299 | start = 0; | |
1300 | else | |
1301 | start = 1; | |
1302 | ||
1303 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1304 | { |
1305 | rtx y = XVECEXP (x, 0, i); | |
1306 | if (REG_P (XEXP (y, 0))) | |
1307 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1308 | } | |
1309 | } | |
1310 | } | |
1311 | ||
38ae7651 RS |
1312 | /* Assign the RTX X to declaration T. */ |
1313 | ||
1314 | void | |
1315 | set_decl_rtl (tree t, rtx x) | |
1316 | { | |
1317 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1318 | if (x) | |
1319 | set_reg_attrs_for_decl_rtl (t, x); | |
1320 | } | |
1321 | ||
5141868d RS |
1322 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1323 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1324 | |
1325 | void | |
5141868d | 1326 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1327 | { |
1328 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1329 | if (x && !by_reference_p) |
38ae7651 RS |
1330 | set_reg_attrs_for_decl_rtl (t, x); |
1331 | } | |
1332 | ||
754fdcca RK |
1333 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1334 | ||
1335 | void | |
502b8322 | 1336 | mark_user_reg (rtx reg) |
754fdcca RK |
1337 | { |
1338 | if (GET_CODE (reg) == CONCAT) | |
1339 | { | |
1340 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1341 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1342 | } | |
754fdcca | 1343 | else |
5b0264cb NS |
1344 | { |
1345 | gcc_assert (REG_P (reg)); | |
1346 | REG_USERVAR_P (reg) = 1; | |
1347 | } | |
754fdcca RK |
1348 | } |
1349 | ||
86fe05e0 RK |
1350 | /* Identify REG as a probable pointer register and show its alignment |
1351 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1352 | |
1353 | void | |
502b8322 | 1354 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1355 | { |
3502dc9c | 1356 | if (! REG_POINTER (reg)) |
00995e78 | 1357 | { |
3502dc9c | 1358 | REG_POINTER (reg) = 1; |
86fe05e0 | 1359 | |
00995e78 RE |
1360 | if (align) |
1361 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1362 | } | |
1363 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1364 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1365 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1366 | } |
1367 | ||
1368 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1369 | ||
1370 | int | |
502b8322 | 1371 | max_reg_num (void) |
23b2ce53 RS |
1372 | { |
1373 | return reg_rtx_no; | |
1374 | } | |
1375 | ||
1376 | /* Return 1 + the largest label number used so far in the current function. */ | |
1377 | ||
1378 | int | |
502b8322 | 1379 | max_label_num (void) |
23b2ce53 | 1380 | { |
23b2ce53 RS |
1381 | return label_num; |
1382 | } | |
1383 | ||
1384 | /* Return first label number used in this function (if any were used). */ | |
1385 | ||
1386 | int | |
502b8322 | 1387 | get_first_label_num (void) |
23b2ce53 RS |
1388 | { |
1389 | return first_label_num; | |
1390 | } | |
6de9cd9a DN |
1391 | |
1392 | /* If the rtx for label was created during the expansion of a nested | |
1393 | function, then first_label_num won't include this label number. | |
fa10beec | 1394 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1395 | |
1396 | void | |
9aa50db7 | 1397 | maybe_set_first_label_num (rtx_code_label *x) |
6de9cd9a DN |
1398 | { |
1399 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1400 | first_label_num = CODE_LABEL_NUMBER (x); | |
1401 | } | |
51b86113 DM |
1402 | |
1403 | /* For use by the RTL function loader, when mingling with normal | |
1404 | functions. | |
1405 | Ensure that label_num is greater than the label num of X, to avoid | |
1406 | duplicate labels in the generated assembler. */ | |
1407 | ||
1408 | void | |
1409 | maybe_set_max_label_num (rtx_code_label *x) | |
1410 | { | |
1411 | if (CODE_LABEL_NUMBER (x) >= label_num) | |
1412 | label_num = CODE_LABEL_NUMBER (x) + 1; | |
1413 | } | |
1414 | ||
23b2ce53 RS |
1415 | \f |
1416 | /* Return a value representing some low-order bits of X, where the number | |
1417 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1418 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1419 | representation is returned. |
1420 | ||
1421 | This function handles the cases in common between gen_lowpart, below, | |
1422 | and two variants in cse.c and combine.c. These are the cases that can | |
1423 | be safely handled at all points in the compilation. | |
1424 | ||
1425 | If this is not a case we can handle, return 0. */ | |
1426 | ||
1427 | rtx | |
ef4bddc2 | 1428 | gen_lowpart_common (machine_mode mode, rtx x) |
23b2ce53 | 1429 | { |
ddef6bc7 | 1430 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1431 | int xsize; |
ef4bddc2 | 1432 | machine_mode innermode; |
550d1387 GK |
1433 | |
1434 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1435 | so we have to make one up. Yuk. */ | |
1436 | innermode = GET_MODE (x); | |
481683e1 | 1437 | if (CONST_INT_P (x) |
db487452 | 1438 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) |
f4b31647 | 1439 | innermode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require (); |
550d1387 | 1440 | else if (innermode == VOIDmode) |
f4b31647 | 1441 | innermode = int_mode_for_size (HOST_BITS_PER_DOUBLE_INT, 0).require (); |
b8698a0f | 1442 | |
550d1387 GK |
1443 | xsize = GET_MODE_SIZE (innermode); |
1444 | ||
5b0264cb | 1445 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1446 | |
550d1387 | 1447 | if (innermode == mode) |
23b2ce53 RS |
1448 | return x; |
1449 | ||
1eae67f8 RS |
1450 | if (SCALAR_FLOAT_MODE_P (mode)) |
1451 | { | |
1452 | /* Don't allow paradoxical FLOAT_MODE subregs. */ | |
1453 | if (msize > xsize) | |
1454 | return 0; | |
1455 | } | |
1456 | else | |
1457 | { | |
1458 | /* MODE must occupy no more of the underlying registers than X. */ | |
1459 | unsigned int regsize = REGMODE_NATURAL_SIZE (innermode); | |
1460 | unsigned int mregs = CEIL (msize, regsize); | |
1461 | unsigned int xregs = CEIL (xsize, regsize); | |
1462 | if (mregs > xregs) | |
1463 | return 0; | |
1464 | } | |
53501a19 | 1465 | |
54651377 | 1466 | scalar_int_mode int_mode, int_innermode, from_mode; |
23b2ce53 | 1467 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) |
54651377 RS |
1468 | && is_a <scalar_int_mode> (mode, &int_mode) |
1469 | && is_a <scalar_int_mode> (innermode, &int_innermode) | |
1470 | && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &from_mode)) | |
23b2ce53 RS |
1471 | { |
1472 | /* If we are getting the low-order part of something that has been | |
1473 | sign- or zero-extended, we can either just use the object being | |
1474 | extended or make a narrower extension. If we want an even smaller | |
1475 | piece than the size of the object being extended, call ourselves | |
1476 | recursively. | |
1477 | ||
1478 | This case is used mostly by combine and cse. */ | |
1479 | ||
54651377 | 1480 | if (from_mode == int_mode) |
23b2ce53 | 1481 | return XEXP (x, 0); |
54651377 RS |
1482 | else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (from_mode)) |
1483 | return gen_lowpart_common (int_mode, XEXP (x, 0)); | |
1484 | else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode)) | |
1485 | return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0)); | |
23b2ce53 | 1486 | } |
f8cfc6aa | 1487 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
06ec586d | 1488 | || GET_CODE (x) == CONCAT || const_vec_p (x) |
33ffb5c5 | 1489 | || CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)) |
3403a1a9 | 1490 | return lowpart_subreg (mode, x, innermode); |
8aada4ad | 1491 | |
23b2ce53 RS |
1492 | /* Otherwise, we can't do this. */ |
1493 | return 0; | |
1494 | } | |
1495 | \f | |
ccba022b | 1496 | rtx |
ef4bddc2 | 1497 | gen_highpart (machine_mode mode, rtx x) |
ccba022b | 1498 | { |
ddef6bc7 | 1499 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1500 | rtx result; |
ddef6bc7 | 1501 | |
ccba022b RS |
1502 | /* This case loses if X is a subreg. To catch bugs early, |
1503 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1504 | gcc_assert (msize <= UNITS_PER_WORD |
1505 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1506 | |
e0e08ac2 JH |
1507 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1508 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb | 1509 | gcc_assert (result); |
b8698a0f | 1510 | |
09482e0d JW |
1511 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1512 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1513 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1514 | if (MEM_P (result)) |
1515 | { | |
1516 | result = validize_mem (result); | |
1517 | gcc_assert (result); | |
1518 | } | |
b8698a0f | 1519 | |
e0e08ac2 JH |
1520 | return result; |
1521 | } | |
5222e470 | 1522 | |
26d249eb | 1523 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1524 | be VOIDmode constant. */ |
1525 | rtx | |
ef4bddc2 | 1526 | gen_highpart_mode (machine_mode outermode, machine_mode innermode, rtx exp) |
5222e470 JH |
1527 | { |
1528 | if (GET_MODE (exp) != VOIDmode) | |
1529 | { | |
5b0264cb | 1530 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1531 | return gen_highpart (outermode, exp); |
1532 | } | |
1533 | return simplify_gen_subreg (outermode, exp, innermode, | |
1534 | subreg_highpart_offset (outermode, innermode)); | |
1535 | } | |
68252e27 | 1536 | |
33951763 RS |
1537 | /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has |
1538 | OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */ | |
8698cce3 | 1539 | |
e0e08ac2 | 1540 | unsigned int |
33951763 | 1541 | subreg_size_lowpart_offset (unsigned int outer_bytes, unsigned int inner_bytes) |
e0e08ac2 | 1542 | { |
33951763 RS |
1543 | if (outer_bytes > inner_bytes) |
1544 | /* Paradoxical subregs always have a SUBREG_BYTE of 0. */ | |
1545 | return 0; | |
ddef6bc7 | 1546 | |
33951763 RS |
1547 | if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN) |
1548 | return inner_bytes - outer_bytes; | |
1549 | else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN) | |
1550 | return 0; | |
1551 | else | |
1552 | return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, 0); | |
ccba022b | 1553 | } |
eea50aa0 | 1554 | |
33951763 RS |
1555 | /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has |
1556 | OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */ | |
1557 | ||
e0e08ac2 | 1558 | unsigned int |
33951763 RS |
1559 | subreg_size_highpart_offset (unsigned int outer_bytes, |
1560 | unsigned int inner_bytes) | |
eea50aa0 | 1561 | { |
33951763 | 1562 | gcc_assert (inner_bytes >= outer_bytes); |
eea50aa0 | 1563 | |
33951763 RS |
1564 | if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN) |
1565 | return 0; | |
1566 | else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN) | |
1567 | return inner_bytes - outer_bytes; | |
1568 | else | |
1569 | return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, | |
1570 | (inner_bytes - outer_bytes) | |
1571 | * BITS_PER_UNIT); | |
eea50aa0 | 1572 | } |
ccba022b | 1573 | |
23b2ce53 RS |
1574 | /* Return 1 iff X, assumed to be a SUBREG, |
1575 | refers to the least significant part of its containing reg. | |
1576 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1577 | ||
1578 | int | |
fa233e34 | 1579 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1580 | { |
1581 | if (GET_CODE (x) != SUBREG) | |
1582 | return 1; | |
a3a03040 RK |
1583 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1584 | return 0; | |
23b2ce53 | 1585 | |
e0e08ac2 JH |
1586 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1587 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1588 | } |
1589 | \f | |
ddef6bc7 JJ |
1590 | /* Return subword OFFSET of operand OP. |
1591 | The word number, OFFSET, is interpreted as the word number starting | |
1592 | at the low-order address. OFFSET 0 is the low-order word if not | |
1593 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1594 | ||
1595 | If we cannot extract the required word, we return zero. Otherwise, | |
1596 | an rtx corresponding to the requested word will be returned. | |
1597 | ||
1598 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1599 | reload has completed, a valid address will always be returned. After | |
1600 | reload, if a valid address cannot be returned, we return zero. | |
1601 | ||
1602 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1603 | it is the responsibility of the caller. | |
1604 | ||
1605 | MODE is the mode of OP in case it is a CONST_INT. | |
1606 | ||
1607 | ??? This is still rather broken for some cases. The problem for the | |
1608 | moment is that all callers of this thing provide no 'goal mode' to | |
1609 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1610 | in a word based SUBREG world. |
1611 | Now use of this function can be deprecated by simplify_subreg in most | |
1612 | cases. | |
1613 | */ | |
ddef6bc7 JJ |
1614 | |
1615 | rtx | |
ef4bddc2 | 1616 | operand_subword (rtx op, unsigned int offset, int validate_address, machine_mode mode) |
ddef6bc7 JJ |
1617 | { |
1618 | if (mode == VOIDmode) | |
1619 | mode = GET_MODE (op); | |
1620 | ||
5b0264cb | 1621 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1622 | |
30f7a378 | 1623 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1624 | if (mode != BLKmode |
1625 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1626 | return 0; | |
1627 | ||
30f7a378 | 1628 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1629 | if (mode != BLKmode |
1630 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1631 | return const0_rtx; | |
1632 | ||
ddef6bc7 | 1633 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1634 | if (MEM_P (op)) |
ddef6bc7 | 1635 | { |
60564289 | 1636 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1637 | |
f1ec5147 | 1638 | if (! validate_address) |
60564289 | 1639 | return new_rtx; |
f1ec5147 RK |
1640 | |
1641 | else if (reload_completed) | |
ddef6bc7 | 1642 | { |
09e881c9 BE |
1643 | if (! strict_memory_address_addr_space_p (word_mode, |
1644 | XEXP (new_rtx, 0), | |
1645 | MEM_ADDR_SPACE (op))) | |
f1ec5147 | 1646 | return 0; |
ddef6bc7 | 1647 | } |
f1ec5147 | 1648 | else |
60564289 | 1649 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1650 | } |
1651 | ||
0631e0bf JH |
1652 | /* Rest can be handled by simplify_subreg. */ |
1653 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1654 | } |
1655 | ||
535a42b1 NS |
1656 | /* Similar to `operand_subword', but never return 0. If we can't |
1657 | extract the required subword, put OP into a register and try again. | |
1658 | The second attempt must succeed. We always validate the address in | |
1659 | this case. | |
23b2ce53 RS |
1660 | |
1661 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1662 | ||
1663 | rtx | |
ef4bddc2 | 1664 | operand_subword_force (rtx op, unsigned int offset, machine_mode mode) |
23b2ce53 | 1665 | { |
ddef6bc7 | 1666 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1667 | |
1668 | if (result) | |
1669 | return result; | |
1670 | ||
1671 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1672 | { |
1673 | /* If this is a register which can not be accessed by words, copy it | |
1674 | to a pseudo register. */ | |
f8cfc6aa | 1675 | if (REG_P (op)) |
77e6b0eb JC |
1676 | op = copy_to_reg (op); |
1677 | else | |
1678 | op = force_reg (mode, op); | |
1679 | } | |
23b2ce53 | 1680 | |
ddef6bc7 | 1681 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1682 | gcc_assert (result); |
23b2ce53 RS |
1683 | |
1684 | return result; | |
1685 | } | |
1686 | \f | |
2b3493c8 AK |
1687 | /* Returns 1 if both MEM_EXPR can be considered equal |
1688 | and 0 otherwise. */ | |
1689 | ||
1690 | int | |
4f588890 | 1691 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1692 | { |
1693 | if (expr1 == expr2) | |
1694 | return 1; | |
1695 | ||
1696 | if (! expr1 || ! expr2) | |
1697 | return 0; | |
1698 | ||
1699 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1700 | return 0; | |
1701 | ||
55b34b5f | 1702 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1703 | } |
1704 | ||
805903b5 JJ |
1705 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1706 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1707 | -1 if not known. */ | |
1708 | ||
1709 | int | |
d9223014 | 1710 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1711 | { |
1712 | tree expr; | |
1713 | unsigned HOST_WIDE_INT offset; | |
1714 | ||
1715 | /* This function can't use | |
527210c4 | 1716 | if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem) |
e80c2726 | 1717 | || (MAX (MEM_ALIGN (mem), |
0eb77834 | 1718 | MAX (align, get_object_alignment (MEM_EXPR (mem)))) |
805903b5 JJ |
1719 | < align)) |
1720 | return -1; | |
1721 | else | |
527210c4 | 1722 | return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1); |
805903b5 JJ |
1723 | for two reasons: |
1724 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1725 | for <variable>. get_inner_reference doesn't handle it and | |
1726 | even if it did, the alignment in that case needs to be determined | |
1727 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1728 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1729 | isn't sufficiently aligned, the object it is in might be. */ | |
1730 | gcc_assert (MEM_P (mem)); | |
1731 | expr = MEM_EXPR (mem); | |
527210c4 | 1732 | if (expr == NULL_TREE || !MEM_OFFSET_KNOWN_P (mem)) |
805903b5 JJ |
1733 | return -1; |
1734 | ||
527210c4 | 1735 | offset = MEM_OFFSET (mem); |
805903b5 JJ |
1736 | if (DECL_P (expr)) |
1737 | { | |
1738 | if (DECL_ALIGN (expr) < align) | |
1739 | return -1; | |
1740 | } | |
1741 | else if (INDIRECT_REF_P (expr)) | |
1742 | { | |
1743 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1744 | return -1; | |
1745 | } | |
1746 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1747 | { | |
1748 | while (1) | |
1749 | { | |
1750 | tree inner = TREE_OPERAND (expr, 0); | |
1751 | tree field = TREE_OPERAND (expr, 1); | |
1752 | tree byte_offset = component_ref_field_offset (expr); | |
1753 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1754 | ||
1755 | if (!byte_offset | |
cc269bb6 RS |
1756 | || !tree_fits_uhwi_p (byte_offset) |
1757 | || !tree_fits_uhwi_p (bit_offset)) | |
805903b5 JJ |
1758 | return -1; |
1759 | ||
ae7e9ddd RS |
1760 | offset += tree_to_uhwi (byte_offset); |
1761 | offset += tree_to_uhwi (bit_offset) / BITS_PER_UNIT; | |
805903b5 JJ |
1762 | |
1763 | if (inner == NULL_TREE) | |
1764 | { | |
1765 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1766 | < (unsigned int) align) | |
1767 | return -1; | |
1768 | break; | |
1769 | } | |
1770 | else if (DECL_P (inner)) | |
1771 | { | |
1772 | if (DECL_ALIGN (inner) < align) | |
1773 | return -1; | |
1774 | break; | |
1775 | } | |
1776 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1777 | return -1; | |
1778 | expr = inner; | |
1779 | } | |
1780 | } | |
1781 | else | |
1782 | return -1; | |
1783 | ||
1784 | return offset & ((align / BITS_PER_UNIT) - 1); | |
1785 | } | |
1786 | ||
6926c713 | 1787 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1788 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1789 | if we are making a new object of this type. BITPOS is nonzero if |
1790 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1791 | |
1792 | void | |
502b8322 AJ |
1793 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1794 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1795 | { |
6f1087be | 1796 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 | 1797 | tree type; |
f12144dd | 1798 | struct mem_attrs attrs, *defattrs, *refattrs; |
f18a7b25 | 1799 | addr_space_t as; |
173b24b9 RK |
1800 | |
1801 | /* It can happen that type_for_mode was given a mode for which there | |
1802 | is no language-level type. In which case it returns NULL, which | |
1803 | we can see here. */ | |
1804 | if (t == NULL_TREE) | |
1805 | return; | |
1806 | ||
1807 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1808 | if (type == error_mark_node) |
1809 | return; | |
173b24b9 | 1810 | |
173b24b9 RK |
1811 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1812 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1813 | info. Callers should not set DECL_RTL until after the call to | |
1814 | set_mem_attributes. */ | |
5b0264cb | 1815 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1816 | |
f12144dd RS |
1817 | memset (&attrs, 0, sizeof (attrs)); |
1818 | ||
738cc472 | 1819 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 | 1820 | front-end routine) and use it. */ |
f12144dd | 1821 | attrs.alias = get_alias_set (t); |
173b24b9 | 1822 | |
a5e9c810 | 1823 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
f8ad8d7c | 1824 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1825 | |
268f7033 | 1826 | /* Default values from pre-existing memory attributes if present. */ |
f12144dd RS |
1827 | refattrs = MEM_ATTRS (ref); |
1828 | if (refattrs) | |
268f7033 UW |
1829 | { |
1830 | /* ??? Can this ever happen? Calling this routine on a MEM that | |
1831 | already carries memory attributes should probably be invalid. */ | |
f12144dd | 1832 | attrs.expr = refattrs->expr; |
754c3d5d | 1833 | attrs.offset_known_p = refattrs->offset_known_p; |
f12144dd | 1834 | attrs.offset = refattrs->offset; |
754c3d5d | 1835 | attrs.size_known_p = refattrs->size_known_p; |
f12144dd RS |
1836 | attrs.size = refattrs->size; |
1837 | attrs.align = refattrs->align; | |
268f7033 UW |
1838 | } |
1839 | ||
1840 | /* Otherwise, default values from the mode of the MEM reference. */ | |
f12144dd | 1841 | else |
268f7033 | 1842 | { |
f12144dd RS |
1843 | defattrs = mode_mem_attrs[(int) GET_MODE (ref)]; |
1844 | gcc_assert (!defattrs->expr); | |
754c3d5d | 1845 | gcc_assert (!defattrs->offset_known_p); |
f12144dd | 1846 | |
268f7033 | 1847 | /* Respect mode size. */ |
754c3d5d | 1848 | attrs.size_known_p = defattrs->size_known_p; |
f12144dd | 1849 | attrs.size = defattrs->size; |
268f7033 UW |
1850 | /* ??? Is this really necessary? We probably should always get |
1851 | the size from the type below. */ | |
1852 | ||
1853 | /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type; | |
1854 | if T is an object, always compute the object alignment below. */ | |
f12144dd RS |
1855 | if (TYPE_P (t)) |
1856 | attrs.align = defattrs->align; | |
1857 | else | |
1858 | attrs.align = BITS_PER_UNIT; | |
268f7033 UW |
1859 | /* ??? If T is a type, respecting mode alignment may *also* be wrong |
1860 | e.g. if the type carries an alignment attribute. Should we be | |
1861 | able to simply always use TYPE_ALIGN? */ | |
1862 | } | |
1863 | ||
25b75a48 BE |
1864 | /* We can set the alignment from the type if we are making an object or if |
1865 | this is an INDIRECT_REF. */ | |
1866 | if (objectp || TREE_CODE (t) == INDIRECT_REF) | |
f12144dd | 1867 | attrs.align = MAX (attrs.align, TYPE_ALIGN (type)); |
a80903ff | 1868 | |
738cc472 | 1869 | /* If the size is known, we can set that. */ |
a787ccc3 | 1870 | tree new_size = TYPE_SIZE_UNIT (type); |
738cc472 | 1871 | |
30b0317c RB |
1872 | /* The address-space is that of the type. */ |
1873 | as = TYPE_ADDR_SPACE (type); | |
1874 | ||
80965c18 RK |
1875 | /* If T is not a type, we may be able to deduce some more information about |
1876 | the expression. */ | |
1877 | if (! TYPE_P (t)) | |
8ac61af7 | 1878 | { |
8476af98 | 1879 | tree base; |
389fdba0 | 1880 | |
8ac61af7 RK |
1881 | if (TREE_THIS_VOLATILE (t)) |
1882 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1883 | |
c56e3582 RK |
1884 | /* Now remove any conversions: they don't change what the underlying |
1885 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 1886 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
1887 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
1888 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1889 | t = TREE_OPERAND (t, 0); |
1890 | ||
4994da65 RG |
1891 | /* Note whether this expression can trap. */ |
1892 | MEM_NOTRAP_P (ref) = !tree_could_trap_p (t); | |
1893 | ||
1894 | base = get_base_address (t); | |
f18a7b25 MJ |
1895 | if (base) |
1896 | { | |
1897 | if (DECL_P (base) | |
1898 | && TREE_READONLY (base) | |
1899 | && (TREE_STATIC (base) || DECL_EXTERNAL (base)) | |
1900 | && !TREE_THIS_VOLATILE (base)) | |
1901 | MEM_READONLY_P (ref) = 1; | |
1902 | ||
1903 | /* Mark static const strings readonly as well. */ | |
1904 | if (TREE_CODE (base) == STRING_CST | |
1905 | && TREE_READONLY (base) | |
1906 | && TREE_STATIC (base)) | |
1907 | MEM_READONLY_P (ref) = 1; | |
1908 | ||
30b0317c | 1909 | /* Address-space information is on the base object. */ |
f18a7b25 MJ |
1910 | if (TREE_CODE (base) == MEM_REF |
1911 | || TREE_CODE (base) == TARGET_MEM_REF) | |
1912 | as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base, | |
1913 | 0)))); | |
1914 | else | |
1915 | as = TYPE_ADDR_SPACE (TREE_TYPE (base)); | |
1916 | } | |
ba30e50d | 1917 | |
2039d7aa RH |
1918 | /* If this expression uses it's parent's alias set, mark it such |
1919 | that we won't change it. */ | |
b4ada065 | 1920 | if (component_uses_parent_alias_set_from (t) != NULL_TREE) |
10b76d73 RK |
1921 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1922 | ||
8ac61af7 RK |
1923 | /* If this is a decl, set the attributes of the MEM from it. */ |
1924 | if (DECL_P (t)) | |
1925 | { | |
f12144dd | 1926 | attrs.expr = t; |
754c3d5d RS |
1927 | attrs.offset_known_p = true; |
1928 | attrs.offset = 0; | |
6f1087be | 1929 | apply_bitpos = bitpos; |
a787ccc3 | 1930 | new_size = DECL_SIZE_UNIT (t); |
8ac61af7 RK |
1931 | } |
1932 | ||
30b0317c | 1933 | /* ??? If we end up with a constant here do record a MEM_EXPR. */ |
6615c446 | 1934 | else if (CONSTANT_CLASS_P (t)) |
30b0317c | 1935 | ; |
998d7deb | 1936 | |
a787ccc3 RS |
1937 | /* If this is a field reference, record it. */ |
1938 | else if (TREE_CODE (t) == COMPONENT_REF) | |
998d7deb | 1939 | { |
f12144dd | 1940 | attrs.expr = t; |
754c3d5d RS |
1941 | attrs.offset_known_p = true; |
1942 | attrs.offset = 0; | |
6f1087be | 1943 | apply_bitpos = bitpos; |
a787ccc3 RS |
1944 | if (DECL_BIT_FIELD (TREE_OPERAND (t, 1))) |
1945 | new_size = DECL_SIZE_UNIT (TREE_OPERAND (t, 1)); | |
998d7deb RH |
1946 | } |
1947 | ||
1948 | /* If this is an array reference, look for an outer field reference. */ | |
1949 | else if (TREE_CODE (t) == ARRAY_REF) | |
1950 | { | |
1951 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1952 | /* We can't modify t, because we use it at the end of the |
1953 | function. */ | |
1954 | tree t2 = t; | |
998d7deb RH |
1955 | |
1956 | do | |
1957 | { | |
1b1838b6 | 1958 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1959 | tree low_bound = array_ref_low_bound (t2); |
1960 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1961 | |
1962 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1963 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1964 | index, then convert to sizetype and multiply by the size of |
1965 | the array element. */ | |
1966 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1967 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1968 | index, low_bound); | |
2567406a | 1969 | |
44de5aeb | 1970 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1971 | size_binop (MULT_EXPR, |
1972 | fold_convert (sizetype, | |
1973 | index), | |
44de5aeb RK |
1974 | unit_size), |
1975 | off_tree); | |
1b1838b6 | 1976 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1977 | } |
1b1838b6 | 1978 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1979 | |
30b0317c | 1980 | if (DECL_P (t2) |
12ead254 RB |
1981 | || (TREE_CODE (t2) == COMPONENT_REF |
1982 | /* For trailing arrays t2 doesn't have a size that | |
1983 | covers all valid accesses. */ | |
c3e46927 | 1984 | && ! array_at_struct_end_p (t))) |
998d7deb | 1985 | { |
f12144dd | 1986 | attrs.expr = t2; |
754c3d5d | 1987 | attrs.offset_known_p = false; |
cc269bb6 | 1988 | if (tree_fits_uhwi_p (off_tree)) |
6f1087be | 1989 | { |
754c3d5d | 1990 | attrs.offset_known_p = true; |
ae7e9ddd | 1991 | attrs.offset = tree_to_uhwi (off_tree); |
6f1087be RH |
1992 | apply_bitpos = bitpos; |
1993 | } | |
998d7deb | 1994 | } |
30b0317c | 1995 | /* Else do not record a MEM_EXPR. */ |
c67a1cf6 RH |
1996 | } |
1997 | ||
56c47f22 | 1998 | /* If this is an indirect reference, record it. */ |
70f34814 | 1999 | else if (TREE_CODE (t) == MEM_REF |
be1ac4ec | 2000 | || TREE_CODE (t) == TARGET_MEM_REF) |
56c47f22 | 2001 | { |
f12144dd | 2002 | attrs.expr = t; |
754c3d5d RS |
2003 | attrs.offset_known_p = true; |
2004 | attrs.offset = 0; | |
56c47f22 RG |
2005 | apply_bitpos = bitpos; |
2006 | } | |
2007 | ||
30b0317c RB |
2008 | /* Compute the alignment. */ |
2009 | unsigned int obj_align; | |
2010 | unsigned HOST_WIDE_INT obj_bitpos; | |
2011 | get_object_alignment_1 (t, &obj_align, &obj_bitpos); | |
2012 | obj_bitpos = (obj_bitpos - bitpos) & (obj_align - 1); | |
2013 | if (obj_bitpos != 0) | |
146ec50f | 2014 | obj_align = least_bit_hwi (obj_bitpos); |
30b0317c | 2015 | attrs.align = MAX (attrs.align, obj_align); |
8ac61af7 RK |
2016 | } |
2017 | ||
cc269bb6 | 2018 | if (tree_fits_uhwi_p (new_size)) |
a787ccc3 RS |
2019 | { |
2020 | attrs.size_known_p = true; | |
ae7e9ddd | 2021 | attrs.size = tree_to_uhwi (new_size); |
a787ccc3 RS |
2022 | } |
2023 | ||
15c812e3 | 2024 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
2025 | bit position offset. Similarly, increase the size of the accessed |
2026 | object to contain the negative offset. */ | |
6f1087be | 2027 | if (apply_bitpos) |
8c317c5f | 2028 | { |
754c3d5d RS |
2029 | gcc_assert (attrs.offset_known_p); |
2030 | attrs.offset -= apply_bitpos / BITS_PER_UNIT; | |
2031 | if (attrs.size_known_p) | |
2032 | attrs.size += apply_bitpos / BITS_PER_UNIT; | |
8c317c5f | 2033 | } |
6f1087be | 2034 | |
8ac61af7 | 2035 | /* Now set the attributes we computed above. */ |
f18a7b25 | 2036 | attrs.addrspace = as; |
f12144dd | 2037 | set_mem_attrs (ref, &attrs); |
173b24b9 RK |
2038 | } |
2039 | ||
6f1087be | 2040 | void |
502b8322 | 2041 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
2042 | { |
2043 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
2044 | } | |
2045 | ||
173b24b9 RK |
2046 | /* Set the alias set of MEM to SET. */ |
2047 | ||
2048 | void | |
4862826d | 2049 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 2050 | { |
f12144dd RS |
2051 | struct mem_attrs attrs; |
2052 | ||
173b24b9 | 2053 | /* If the new and old alias sets don't conflict, something is wrong. */ |
77a74ed7 | 2054 | gcc_checking_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
f12144dd RS |
2055 | attrs = *get_mem_attrs (mem); |
2056 | attrs.alias = set; | |
2057 | set_mem_attrs (mem, &attrs); | |
09e881c9 BE |
2058 | } |
2059 | ||
2060 | /* Set the address space of MEM to ADDRSPACE (target-defined). */ | |
2061 | ||
2062 | void | |
2063 | set_mem_addr_space (rtx mem, addr_space_t addrspace) | |
2064 | { | |
f12144dd RS |
2065 | struct mem_attrs attrs; |
2066 | ||
2067 | attrs = *get_mem_attrs (mem); | |
2068 | attrs.addrspace = addrspace; | |
2069 | set_mem_attrs (mem, &attrs); | |
173b24b9 | 2070 | } |
738cc472 | 2071 | |
d022d93e | 2072 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
2073 | |
2074 | void | |
502b8322 | 2075 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 2076 | { |
f12144dd RS |
2077 | struct mem_attrs attrs; |
2078 | ||
2079 | attrs = *get_mem_attrs (mem); | |
2080 | attrs.align = align; | |
2081 | set_mem_attrs (mem, &attrs); | |
738cc472 | 2082 | } |
1285011e | 2083 | |
998d7deb | 2084 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
2085 | |
2086 | void | |
502b8322 | 2087 | set_mem_expr (rtx mem, tree expr) |
1285011e | 2088 | { |
f12144dd RS |
2089 | struct mem_attrs attrs; |
2090 | ||
2091 | attrs = *get_mem_attrs (mem); | |
2092 | attrs.expr = expr; | |
2093 | set_mem_attrs (mem, &attrs); | |
1285011e | 2094 | } |
998d7deb RH |
2095 | |
2096 | /* Set the offset of MEM to OFFSET. */ | |
2097 | ||
2098 | void | |
527210c4 | 2099 | set_mem_offset (rtx mem, HOST_WIDE_INT offset) |
998d7deb | 2100 | { |
f12144dd RS |
2101 | struct mem_attrs attrs; |
2102 | ||
2103 | attrs = *get_mem_attrs (mem); | |
754c3d5d RS |
2104 | attrs.offset_known_p = true; |
2105 | attrs.offset = offset; | |
527210c4 RS |
2106 | set_mem_attrs (mem, &attrs); |
2107 | } | |
2108 | ||
2109 | /* Clear the offset of MEM. */ | |
2110 | ||
2111 | void | |
2112 | clear_mem_offset (rtx mem) | |
2113 | { | |
2114 | struct mem_attrs attrs; | |
2115 | ||
2116 | attrs = *get_mem_attrs (mem); | |
754c3d5d | 2117 | attrs.offset_known_p = false; |
f12144dd | 2118 | set_mem_attrs (mem, &attrs); |
35aff10b AM |
2119 | } |
2120 | ||
2121 | /* Set the size of MEM to SIZE. */ | |
2122 | ||
2123 | void | |
f5541398 | 2124 | set_mem_size (rtx mem, HOST_WIDE_INT size) |
35aff10b | 2125 | { |
f12144dd RS |
2126 | struct mem_attrs attrs; |
2127 | ||
2128 | attrs = *get_mem_attrs (mem); | |
754c3d5d RS |
2129 | attrs.size_known_p = true; |
2130 | attrs.size = size; | |
f5541398 RS |
2131 | set_mem_attrs (mem, &attrs); |
2132 | } | |
2133 | ||
2134 | /* Clear the size of MEM. */ | |
2135 | ||
2136 | void | |
2137 | clear_mem_size (rtx mem) | |
2138 | { | |
2139 | struct mem_attrs attrs; | |
2140 | ||
2141 | attrs = *get_mem_attrs (mem); | |
754c3d5d | 2142 | attrs.size_known_p = false; |
f12144dd | 2143 | set_mem_attrs (mem, &attrs); |
998d7deb | 2144 | } |
173b24b9 | 2145 | \f |
738cc472 RK |
2146 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
2147 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
2148 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
23b33725 RS |
2149 | returned memory location is required to be valid. INPLACE is true if any |
2150 | changes can be made directly to MEMREF or false if MEMREF must be treated | |
2151 | as immutable. | |
2152 | ||
2153 | The memory attributes are not changed. */ | |
23b2ce53 | 2154 | |
738cc472 | 2155 | static rtx |
ef4bddc2 | 2156 | change_address_1 (rtx memref, machine_mode mode, rtx addr, int validate, |
23b33725 | 2157 | bool inplace) |
23b2ce53 | 2158 | { |
09e881c9 | 2159 | addr_space_t as; |
60564289 | 2160 | rtx new_rtx; |
23b2ce53 | 2161 | |
5b0264cb | 2162 | gcc_assert (MEM_P (memref)); |
09e881c9 | 2163 | as = MEM_ADDR_SPACE (memref); |
23b2ce53 RS |
2164 | if (mode == VOIDmode) |
2165 | mode = GET_MODE (memref); | |
2166 | if (addr == 0) | |
2167 | addr = XEXP (memref, 0); | |
a74ff877 | 2168 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
09e881c9 | 2169 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
a74ff877 | 2170 | return memref; |
23b2ce53 | 2171 | |
91c5ee5b VM |
2172 | /* Don't validate address for LRA. LRA can make the address valid |
2173 | by itself in most efficient way. */ | |
2174 | if (validate && !lra_in_progress) | |
23b2ce53 | 2175 | { |
f1ec5147 | 2176 | if (reload_in_progress || reload_completed) |
09e881c9 | 2177 | gcc_assert (memory_address_addr_space_p (mode, addr, as)); |
f1ec5147 | 2178 | else |
09e881c9 | 2179 | addr = memory_address_addr_space (mode, addr, as); |
23b2ce53 | 2180 | } |
750c9258 | 2181 | |
9b04c6a8 RK |
2182 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
2183 | return memref; | |
2184 | ||
23b33725 RS |
2185 | if (inplace) |
2186 | { | |
2187 | XEXP (memref, 0) = addr; | |
2188 | return memref; | |
2189 | } | |
2190 | ||
60564289 KG |
2191 | new_rtx = gen_rtx_MEM (mode, addr); |
2192 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
2193 | return new_rtx; | |
23b2ce53 | 2194 | } |
792760b9 | 2195 | |
738cc472 RK |
2196 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
2197 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
2198 | |
2199 | rtx | |
ef4bddc2 | 2200 | change_address (rtx memref, machine_mode mode, rtx addr) |
f4ef873c | 2201 | { |
23b33725 | 2202 | rtx new_rtx = change_address_1 (memref, mode, addr, 1, false); |
ef4bddc2 | 2203 | machine_mode mmode = GET_MODE (new_rtx); |
f12144dd | 2204 | struct mem_attrs attrs, *defattrs; |
4e44c1ef | 2205 | |
f12144dd RS |
2206 | attrs = *get_mem_attrs (memref); |
2207 | defattrs = mode_mem_attrs[(int) mmode]; | |
754c3d5d RS |
2208 | attrs.expr = NULL_TREE; |
2209 | attrs.offset_known_p = false; | |
2210 | attrs.size_known_p = defattrs->size_known_p; | |
f12144dd RS |
2211 | attrs.size = defattrs->size; |
2212 | attrs.align = defattrs->align; | |
c2f7bcc3 | 2213 | |
fdb1c7b3 | 2214 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 2215 | if (new_rtx == memref) |
4e44c1ef | 2216 | { |
f12144dd | 2217 | if (mem_attrs_eq_p (get_mem_attrs (memref), &attrs)) |
60564289 | 2218 | return new_rtx; |
4e44c1ef | 2219 | |
60564289 KG |
2220 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
2221 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 2222 | } |
fdb1c7b3 | 2223 | |
f12144dd | 2224 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2225 | return new_rtx; |
f4ef873c | 2226 | } |
792760b9 | 2227 | |
738cc472 RK |
2228 | /* Return a memory reference like MEMREF, but with its mode changed |
2229 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 | 2230 | nonzero, the memory address is forced to be valid. |
5ef0b50d EB |
2231 | If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS |
2232 | and the caller is responsible for adjusting MEMREF base register. | |
2233 | If ADJUST_OBJECT is zero, the underlying object associated with the | |
2234 | memory reference is left unchanged and the caller is responsible for | |
2235 | dealing with it. Otherwise, if the new memory reference is outside | |
5f2cbd0d RS |
2236 | the underlying object, even partially, then the object is dropped. |
2237 | SIZE, if nonzero, is the size of an access in cases where MODE | |
2238 | has no inherent size. */ | |
f1ec5147 RK |
2239 | |
2240 | rtx | |
ef4bddc2 | 2241 | adjust_address_1 (rtx memref, machine_mode mode, HOST_WIDE_INT offset, |
5f2cbd0d RS |
2242 | int validate, int adjust_address, int adjust_object, |
2243 | HOST_WIDE_INT size) | |
f1ec5147 | 2244 | { |
823e3574 | 2245 | rtx addr = XEXP (memref, 0); |
60564289 | 2246 | rtx new_rtx; |
095a2d76 | 2247 | scalar_int_mode address_mode; |
a6fe9ed4 | 2248 | int pbits; |
0207fa90 | 2249 | struct mem_attrs attrs = *get_mem_attrs (memref), *defattrs; |
f12144dd | 2250 | unsigned HOST_WIDE_INT max_align; |
0207fa90 | 2251 | #ifdef POINTERS_EXTEND_UNSIGNED |
095a2d76 | 2252 | scalar_int_mode pointer_mode |
0207fa90 EB |
2253 | = targetm.addr_space.pointer_mode (attrs.addrspace); |
2254 | #endif | |
823e3574 | 2255 | |
ee88e690 EB |
2256 | /* VOIDmode means no mode change for change_address_1. */ |
2257 | if (mode == VOIDmode) | |
2258 | mode = GET_MODE (memref); | |
2259 | ||
5f2cbd0d RS |
2260 | /* Take the size of non-BLKmode accesses from the mode. */ |
2261 | defattrs = mode_mem_attrs[(int) mode]; | |
2262 | if (defattrs->size_known_p) | |
2263 | size = defattrs->size; | |
2264 | ||
fdb1c7b3 JH |
2265 | /* If there are no changes, just return the original memory reference. */ |
2266 | if (mode == GET_MODE (memref) && !offset | |
5f2cbd0d | 2267 | && (size == 0 || (attrs.size_known_p && attrs.size == size)) |
f12144dd RS |
2268 | && (!validate || memory_address_addr_space_p (mode, addr, |
2269 | attrs.addrspace))) | |
fdb1c7b3 JH |
2270 | return memref; |
2271 | ||
d14419e4 | 2272 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2273 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2274 | (plus (plus reg reg) const_int) -- so do this always. */ |
2275 | addr = copy_rtx (addr); | |
2276 | ||
a6fe9ed4 JM |
2277 | /* Convert a possibly large offset to a signed value within the |
2278 | range of the target address space. */ | |
372d6395 | 2279 | address_mode = get_address_mode (memref); |
d4ebfa65 | 2280 | pbits = GET_MODE_BITSIZE (address_mode); |
a6fe9ed4 JM |
2281 | if (HOST_BITS_PER_WIDE_INT > pbits) |
2282 | { | |
2283 | int shift = HOST_BITS_PER_WIDE_INT - pbits; | |
2284 | offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift)) | |
2285 | >> shift); | |
2286 | } | |
2287 | ||
5ef0b50d | 2288 | if (adjust_address) |
4a78c787 RH |
2289 | { |
2290 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2291 | object, we can merge it into the LO_SUM. */ | |
2292 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
2293 | && offset >= 0 | |
2294 | && (unsigned HOST_WIDE_INT) offset | |
2295 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
d4ebfa65 | 2296 | addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0), |
0a81f074 RS |
2297 | plus_constant (address_mode, |
2298 | XEXP (addr, 1), offset)); | |
0207fa90 EB |
2299 | #ifdef POINTERS_EXTEND_UNSIGNED |
2300 | /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid | |
2301 | in that mode, we merge it into the ZERO_EXTEND. We take advantage of | |
2302 | the fact that pointers are not allowed to overflow. */ | |
2303 | else if (POINTERS_EXTEND_UNSIGNED > 0 | |
2304 | && GET_CODE (addr) == ZERO_EXTEND | |
2305 | && GET_MODE (XEXP (addr, 0)) == pointer_mode | |
2306 | && trunc_int_for_mode (offset, pointer_mode) == offset) | |
2307 | addr = gen_rtx_ZERO_EXTEND (address_mode, | |
2308 | plus_constant (pointer_mode, | |
2309 | XEXP (addr, 0), offset)); | |
2310 | #endif | |
4a78c787 | 2311 | else |
0a81f074 | 2312 | addr = plus_constant (address_mode, addr, offset); |
4a78c787 | 2313 | } |
823e3574 | 2314 | |
23b33725 | 2315 | new_rtx = change_address_1 (memref, mode, addr, validate, false); |
738cc472 | 2316 | |
09efeca1 PB |
2317 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2318 | but this would destroy memref's MEM_ATTRS. */ | |
2319 | if (new_rtx == memref && offset != 0) | |
2320 | new_rtx = copy_rtx (new_rtx); | |
2321 | ||
5ef0b50d EB |
2322 | /* Conservatively drop the object if we don't know where we start from. */ |
2323 | if (adjust_object && (!attrs.offset_known_p || !attrs.size_known_p)) | |
2324 | { | |
2325 | attrs.expr = NULL_TREE; | |
2326 | attrs.alias = 0; | |
2327 | } | |
2328 | ||
738cc472 RK |
2329 | /* Compute the new values of the memory attributes due to this adjustment. |
2330 | We add the offsets and update the alignment. */ | |
754c3d5d | 2331 | if (attrs.offset_known_p) |
5ef0b50d EB |
2332 | { |
2333 | attrs.offset += offset; | |
2334 | ||
2335 | /* Drop the object if the new left end is not within its bounds. */ | |
2336 | if (adjust_object && attrs.offset < 0) | |
2337 | { | |
2338 | attrs.expr = NULL_TREE; | |
2339 | attrs.alias = 0; | |
2340 | } | |
2341 | } | |
738cc472 | 2342 | |
03bf2c23 RK |
2343 | /* Compute the new alignment by taking the MIN of the alignment and the |
2344 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2345 | if zero. */ | |
2346 | if (offset != 0) | |
f12144dd | 2347 | { |
146ec50f | 2348 | max_align = least_bit_hwi (offset) * BITS_PER_UNIT; |
f12144dd RS |
2349 | attrs.align = MIN (attrs.align, max_align); |
2350 | } | |
738cc472 | 2351 | |
5f2cbd0d | 2352 | if (size) |
754c3d5d | 2353 | { |
5ef0b50d | 2354 | /* Drop the object if the new right end is not within its bounds. */ |
5f2cbd0d | 2355 | if (adjust_object && (offset + size) > attrs.size) |
5ef0b50d EB |
2356 | { |
2357 | attrs.expr = NULL_TREE; | |
2358 | attrs.alias = 0; | |
2359 | } | |
754c3d5d | 2360 | attrs.size_known_p = true; |
5f2cbd0d | 2361 | attrs.size = size; |
754c3d5d RS |
2362 | } |
2363 | else if (attrs.size_known_p) | |
5ef0b50d | 2364 | { |
5f2cbd0d | 2365 | gcc_assert (!adjust_object); |
5ef0b50d | 2366 | attrs.size -= offset; |
5f2cbd0d RS |
2367 | /* ??? The store_by_pieces machinery generates negative sizes, |
2368 | so don't assert for that here. */ | |
5ef0b50d | 2369 | } |
10b76d73 | 2370 | |
f12144dd | 2371 | set_mem_attrs (new_rtx, &attrs); |
738cc472 | 2372 | |
60564289 | 2373 | return new_rtx; |
f1ec5147 RK |
2374 | } |
2375 | ||
630036c6 JJ |
2376 | /* Return a memory reference like MEMREF, but with its mode changed |
2377 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2378 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2379 | nonzero, the memory address is forced to be valid. */ |
2380 | ||
2381 | rtx | |
ef4bddc2 | 2382 | adjust_automodify_address_1 (rtx memref, machine_mode mode, rtx addr, |
502b8322 | 2383 | HOST_WIDE_INT offset, int validate) |
630036c6 | 2384 | { |
23b33725 | 2385 | memref = change_address_1 (memref, VOIDmode, addr, validate, false); |
5f2cbd0d | 2386 | return adjust_address_1 (memref, mode, offset, validate, 0, 0, 0); |
630036c6 JJ |
2387 | } |
2388 | ||
8ac61af7 RK |
2389 | /* Return a memory reference like MEMREF, but whose address is changed by |
2390 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2391 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2392 | |
2393 | rtx | |
502b8322 | 2394 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2395 | { |
60564289 | 2396 | rtx new_rtx, addr = XEXP (memref, 0); |
ef4bddc2 | 2397 | machine_mode address_mode; |
754c3d5d | 2398 | struct mem_attrs attrs, *defattrs; |
e3c8ea67 | 2399 | |
f12144dd | 2400 | attrs = *get_mem_attrs (memref); |
372d6395 | 2401 | address_mode = get_address_mode (memref); |
d4ebfa65 | 2402 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 | 2403 | |
68252e27 | 2404 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2405 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2406 | |
2407 | However, if we did go and rearrange things, we can wind up not | |
2408 | being able to recognize the magic around pic_offset_table_rtx. | |
2409 | This stuff is fragile, and is yet another example of why it is | |
2410 | bad to expose PIC machinery too early. */ | |
f12144dd RS |
2411 | if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, |
2412 | attrs.addrspace) | |
e3c8ea67 RH |
2413 | && GET_CODE (addr) == PLUS |
2414 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2415 | { | |
2416 | addr = force_reg (GET_MODE (addr), addr); | |
d4ebfa65 | 2417 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 RH |
2418 | } |
2419 | ||
60564289 | 2420 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
23b33725 | 2421 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1, false); |
0d4903b8 | 2422 | |
fdb1c7b3 | 2423 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2424 | if (new_rtx == memref) |
2425 | return new_rtx; | |
fdb1c7b3 | 2426 | |
0d4903b8 RK |
2427 | /* Update the alignment to reflect the offset. Reset the offset, which |
2428 | we don't know. */ | |
754c3d5d RS |
2429 | defattrs = mode_mem_attrs[(int) GET_MODE (new_rtx)]; |
2430 | attrs.offset_known_p = false; | |
2431 | attrs.size_known_p = defattrs->size_known_p; | |
2432 | attrs.size = defattrs->size; | |
f12144dd RS |
2433 | attrs.align = MIN (attrs.align, pow2 * BITS_PER_UNIT); |
2434 | set_mem_attrs (new_rtx, &attrs); | |
60564289 | 2435 | return new_rtx; |
0d4903b8 | 2436 | } |
68252e27 | 2437 | |
792760b9 RK |
2438 | /* Return a memory reference like MEMREF, but with its address changed to |
2439 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2440 | to is the same, just the form of the address is being changed, such as | |
23b33725 RS |
2441 | by putting something into a register. INPLACE is true if any changes |
2442 | can be made directly to MEMREF or false if MEMREF must be treated as | |
2443 | immutable. */ | |
792760b9 RK |
2444 | |
2445 | rtx | |
23b33725 | 2446 | replace_equiv_address (rtx memref, rtx addr, bool inplace) |
792760b9 | 2447 | { |
738cc472 RK |
2448 | /* change_address_1 copies the memory attribute structure without change |
2449 | and that's exactly what we want here. */ | |
40c0668b | 2450 | update_temp_slot_address (XEXP (memref, 0), addr); |
23b33725 | 2451 | return change_address_1 (memref, VOIDmode, addr, 1, inplace); |
792760b9 | 2452 | } |
738cc472 | 2453 | |
f1ec5147 RK |
2454 | /* Likewise, but the reference is not required to be valid. */ |
2455 | ||
2456 | rtx | |
23b33725 | 2457 | replace_equiv_address_nv (rtx memref, rtx addr, bool inplace) |
f1ec5147 | 2458 | { |
23b33725 | 2459 | return change_address_1 (memref, VOIDmode, addr, 0, inplace); |
f1ec5147 | 2460 | } |
e7dfe4bb RH |
2461 | |
2462 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2463 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2464 | cannot issue QImode memory operations and have to use SImode memory | |
2465 | operations plus masking logic. */ | |
2466 | ||
2467 | rtx | |
ef4bddc2 | 2468 | widen_memory_access (rtx memref, machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb | 2469 | { |
5f2cbd0d | 2470 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1, 0, 0); |
f12144dd | 2471 | struct mem_attrs attrs; |
e7dfe4bb RH |
2472 | unsigned int size = GET_MODE_SIZE (mode); |
2473 | ||
fdb1c7b3 | 2474 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2475 | if (new_rtx == memref) |
2476 | return new_rtx; | |
fdb1c7b3 | 2477 | |
f12144dd RS |
2478 | attrs = *get_mem_attrs (new_rtx); |
2479 | ||
e7dfe4bb RH |
2480 | /* If we don't know what offset we were at within the expression, then |
2481 | we can't know if we've overstepped the bounds. */ | |
754c3d5d | 2482 | if (! attrs.offset_known_p) |
f12144dd | 2483 | attrs.expr = NULL_TREE; |
e7dfe4bb | 2484 | |
f12144dd | 2485 | while (attrs.expr) |
e7dfe4bb | 2486 | { |
f12144dd | 2487 | if (TREE_CODE (attrs.expr) == COMPONENT_REF) |
e7dfe4bb | 2488 | { |
f12144dd RS |
2489 | tree field = TREE_OPERAND (attrs.expr, 1); |
2490 | tree offset = component_ref_field_offset (attrs.expr); | |
e7dfe4bb RH |
2491 | |
2492 | if (! DECL_SIZE_UNIT (field)) | |
2493 | { | |
f12144dd | 2494 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2495 | break; |
2496 | } | |
2497 | ||
2498 | /* Is the field at least as large as the access? If so, ok, | |
2499 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2500 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2501 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
754c3d5d | 2502 | && attrs.offset >= 0) |
e7dfe4bb RH |
2503 | break; |
2504 | ||
cc269bb6 | 2505 | if (! tree_fits_uhwi_p (offset)) |
e7dfe4bb | 2506 | { |
f12144dd | 2507 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2508 | break; |
2509 | } | |
2510 | ||
f12144dd | 2511 | attrs.expr = TREE_OPERAND (attrs.expr, 0); |
ae7e9ddd RS |
2512 | attrs.offset += tree_to_uhwi (offset); |
2513 | attrs.offset += (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field)) | |
754c3d5d | 2514 | / BITS_PER_UNIT); |
e7dfe4bb RH |
2515 | } |
2516 | /* Similarly for the decl. */ | |
f12144dd RS |
2517 | else if (DECL_P (attrs.expr) |
2518 | && DECL_SIZE_UNIT (attrs.expr) | |
2519 | && TREE_CODE (DECL_SIZE_UNIT (attrs.expr)) == INTEGER_CST | |
2520 | && compare_tree_int (DECL_SIZE_UNIT (attrs.expr), size) >= 0 | |
754c3d5d | 2521 | && (! attrs.offset_known_p || attrs.offset >= 0)) |
e7dfe4bb RH |
2522 | break; |
2523 | else | |
2524 | { | |
2525 | /* The widened memory access overflows the expression, which means | |
2526 | that it could alias another expression. Zap it. */ | |
f12144dd | 2527 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2528 | break; |
2529 | } | |
2530 | } | |
2531 | ||
f12144dd | 2532 | if (! attrs.expr) |
754c3d5d | 2533 | attrs.offset_known_p = false; |
e7dfe4bb RH |
2534 | |
2535 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2536 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
f12144dd | 2537 | attrs.alias = 0; |
754c3d5d RS |
2538 | attrs.size_known_p = true; |
2539 | attrs.size = size; | |
f12144dd | 2540 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2541 | return new_rtx; |
e7dfe4bb | 2542 | } |
23b2ce53 | 2543 | \f |
f6129d66 RH |
2544 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2545 | static GTY(()) tree spill_slot_decl; | |
2546 | ||
3d7e23f6 RH |
2547 | tree |
2548 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2549 | { |
2550 | tree d = spill_slot_decl; | |
2551 | rtx rd; | |
f12144dd | 2552 | struct mem_attrs attrs; |
f6129d66 | 2553 | |
3d7e23f6 | 2554 | if (d || !force_build_p) |
f6129d66 RH |
2555 | return d; |
2556 | ||
c2255bc4 AH |
2557 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2558 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2559 | DECL_ARTIFICIAL (d) = 1; |
2560 | DECL_IGNORED_P (d) = 1; | |
2561 | TREE_USED (d) = 1; | |
f6129d66 RH |
2562 | spill_slot_decl = d; |
2563 | ||
2564 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2565 | MEM_NOTRAP_P (rd) = 1; | |
f12144dd RS |
2566 | attrs = *mode_mem_attrs[(int) BLKmode]; |
2567 | attrs.alias = new_alias_set (); | |
2568 | attrs.expr = d; | |
2569 | set_mem_attrs (rd, &attrs); | |
f6129d66 RH |
2570 | SET_DECL_RTL (d, rd); |
2571 | ||
2572 | return d; | |
2573 | } | |
2574 | ||
2575 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2576 | attributes as appropriate for a register allocator spill slot. | |
2577 | These slots are not aliasable by other memory. We arrange for | |
2578 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2579 | work properly in the case of shared spill slots. */ | |
2580 | ||
2581 | void | |
2582 | set_mem_attrs_for_spill (rtx mem) | |
2583 | { | |
f12144dd RS |
2584 | struct mem_attrs attrs; |
2585 | rtx addr; | |
f6129d66 | 2586 | |
f12144dd RS |
2587 | attrs = *get_mem_attrs (mem); |
2588 | attrs.expr = get_spill_slot_decl (true); | |
2589 | attrs.alias = MEM_ALIAS_SET (DECL_RTL (attrs.expr)); | |
2590 | attrs.addrspace = ADDR_SPACE_GENERIC; | |
f6129d66 RH |
2591 | |
2592 | /* We expect the incoming memory to be of the form: | |
2593 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2594 | with perhaps the plus missing for offset = 0. */ | |
2595 | addr = XEXP (mem, 0); | |
754c3d5d RS |
2596 | attrs.offset_known_p = true; |
2597 | attrs.offset = 0; | |
f6129d66 | 2598 | if (GET_CODE (addr) == PLUS |
481683e1 | 2599 | && CONST_INT_P (XEXP (addr, 1))) |
754c3d5d | 2600 | attrs.offset = INTVAL (XEXP (addr, 1)); |
f6129d66 | 2601 | |
f12144dd | 2602 | set_mem_attrs (mem, &attrs); |
f6129d66 RH |
2603 | MEM_NOTRAP_P (mem) = 1; |
2604 | } | |
2605 | \f | |
23b2ce53 RS |
2606 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2607 | ||
7dcc3ab5 | 2608 | rtx_code_label * |
502b8322 | 2609 | gen_label_rtx (void) |
23b2ce53 | 2610 | { |
7dcc3ab5 DM |
2611 | return as_a <rtx_code_label *> ( |
2612 | gen_rtx_CODE_LABEL (VOIDmode, NULL_RTX, NULL_RTX, | |
2613 | NULL, label_num++, NULL)); | |
23b2ce53 RS |
2614 | } |
2615 | \f | |
2616 | /* For procedure integration. */ | |
2617 | ||
23b2ce53 | 2618 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2619 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2620 | Used for an inline-procedure after copying the insn chain. */ |
2621 | ||
2622 | void | |
fee3e72c | 2623 | set_new_first_and_last_insn (rtx_insn *first, rtx_insn *last) |
23b2ce53 | 2624 | { |
fee3e72c | 2625 | rtx_insn *insn; |
86fe05e0 | 2626 | |
5936d944 JH |
2627 | set_first_insn (first); |
2628 | set_last_insn (last); | |
86fe05e0 RK |
2629 | cur_insn_uid = 0; |
2630 | ||
b5b8b0ac AO |
2631 | if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS) |
2632 | { | |
2633 | int debug_count = 0; | |
2634 | ||
2635 | cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1; | |
2636 | cur_debug_insn_uid = 0; | |
2637 | ||
2638 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2639 | if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID) | |
2640 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); | |
2641 | else | |
2642 | { | |
2643 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2644 | if (DEBUG_INSN_P (insn)) | |
2645 | debug_count++; | |
2646 | } | |
2647 | ||
2648 | if (debug_count) | |
2649 | cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count; | |
2650 | else | |
2651 | cur_debug_insn_uid++; | |
2652 | } | |
2653 | else | |
2654 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2655 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2656 | |
2657 | cur_insn_uid++; | |
23b2ce53 | 2658 | } |
23b2ce53 | 2659 | \f |
750c9258 | 2660 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2661 | structure. This routine should only be called once. */ |
23b2ce53 | 2662 | |
fd743bc1 | 2663 | static void |
6bb9bf63 | 2664 | unshare_all_rtl_1 (rtx_insn *insn) |
23b2ce53 | 2665 | { |
d1b81779 | 2666 | /* Unshare just about everything else. */ |
2c07f13b | 2667 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2668 | |
23b2ce53 RS |
2669 | /* Make sure the addresses of stack slots found outside the insn chain |
2670 | (such as, in DECL_RTL of a variable) are not shared | |
2671 | with the insn chain. | |
2672 | ||
2673 | This special care is necessary when the stack slot MEM does not | |
2674 | actually appear in the insn chain. If it does appear, its address | |
2675 | is unshared from all else at that point. */ | |
8c39f8ae TS |
2676 | unsigned int i; |
2677 | rtx temp; | |
2678 | FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp) | |
2679 | (*stack_slot_list)[i] = copy_rtx_if_shared (temp); | |
23b2ce53 RS |
2680 | } |
2681 | ||
750c9258 | 2682 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2683 | structure, again. This is a fairly expensive thing to do so it |
2684 | should be done sparingly. */ | |
2685 | ||
2686 | void | |
6bb9bf63 | 2687 | unshare_all_rtl_again (rtx_insn *insn) |
d1b81779 | 2688 | { |
6bb9bf63 | 2689 | rtx_insn *p; |
624c87aa RE |
2690 | tree decl; |
2691 | ||
d1b81779 | 2692 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2693 | if (INSN_P (p)) |
d1b81779 GK |
2694 | { |
2695 | reset_used_flags (PATTERN (p)); | |
2696 | reset_used_flags (REG_NOTES (p)); | |
776bebcd JJ |
2697 | if (CALL_P (p)) |
2698 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (p)); | |
d1b81779 | 2699 | } |
624c87aa | 2700 | |
2d4aecb3 | 2701 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2702 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2703 | |
624c87aa | 2704 | /* Make sure that virtual parameters are not shared. */ |
910ad8de | 2705 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) |
5eb2a9f2 | 2706 | set_used_flags (DECL_RTL (decl)); |
624c87aa | 2707 | |
8c39f8ae TS |
2708 | rtx temp; |
2709 | unsigned int i; | |
2710 | FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp) | |
2711 | reset_used_flags (temp); | |
624c87aa | 2712 | |
b4aaa77b | 2713 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2714 | } |
2715 | ||
c2924966 | 2716 | unsigned int |
fd743bc1 PB |
2717 | unshare_all_rtl (void) |
2718 | { | |
b4aaa77b | 2719 | unshare_all_rtl_1 (get_insns ()); |
60ebe8ce JJ |
2720 | |
2721 | for (tree decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) | |
2722 | { | |
2723 | if (DECL_RTL_SET_P (decl)) | |
2724 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); | |
2725 | DECL_INCOMING_RTL (decl) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl)); | |
2726 | } | |
2727 | ||
c2924966 | 2728 | return 0; |
d1b81779 GK |
2729 | } |
2730 | ||
ef330312 | 2731 | |
2c07f13b JH |
2732 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2733 | Recursively does the same for subexpressions. */ | |
2734 | ||
2735 | static void | |
2736 | verify_rtx_sharing (rtx orig, rtx insn) | |
2737 | { | |
2738 | rtx x = orig; | |
2739 | int i; | |
2740 | enum rtx_code code; | |
2741 | const char *format_ptr; | |
2742 | ||
2743 | if (x == 0) | |
2744 | return; | |
2745 | ||
2746 | code = GET_CODE (x); | |
2747 | ||
2748 | /* These types may be freely shared. */ | |
2749 | ||
2750 | switch (code) | |
2751 | { | |
2752 | case REG: | |
0ca5af51 AO |
2753 | case DEBUG_EXPR: |
2754 | case VALUE: | |
d8116890 | 2755 | CASE_CONST_ANY: |
2c07f13b JH |
2756 | case SYMBOL_REF: |
2757 | case LABEL_REF: | |
2758 | case CODE_LABEL: | |
2759 | case PC: | |
2760 | case CC0: | |
3810076b | 2761 | case RETURN: |
26898771 | 2762 | case SIMPLE_RETURN: |
2c07f13b | 2763 | case SCRATCH: |
3e89ed8d | 2764 | /* SCRATCH must be shared because they represent distinct values. */ |
c5c5ba89 | 2765 | return; |
3e89ed8d | 2766 | case CLOBBER: |
c5c5ba89 JH |
2767 | /* Share clobbers of hard registers (like cc0), but do not share pseudo reg |
2768 | clobbers or clobbers of hard registers that originated as pseudos. | |
2769 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
2770 | if (REG_P (XEXP (x, 0)) |
2771 | && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0))) | |
2772 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0)))) | |
3e89ed8d JH |
2773 | return; |
2774 | break; | |
2c07f13b JH |
2775 | |
2776 | case CONST: | |
6fb5fa3c | 2777 | if (shared_const_p (orig)) |
2c07f13b JH |
2778 | return; |
2779 | break; | |
2780 | ||
2781 | case MEM: | |
2782 | /* A MEM is allowed to be shared if its address is constant. */ | |
2783 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2784 | || reload_completed || reload_in_progress) | |
2785 | return; | |
2786 | ||
2787 | break; | |
2788 | ||
2789 | default: | |
2790 | break; | |
2791 | } | |
2792 | ||
2793 | /* This rtx may not be shared. If it has already been seen, | |
2794 | replace it with a copy of itself. */ | |
b2b29377 | 2795 | if (flag_checking && RTX_FLAG (x, used)) |
2c07f13b | 2796 | { |
ab532386 | 2797 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2798 | debug_rtx (insn); |
ab532386 | 2799 | error ("shared rtx"); |
2c07f13b | 2800 | debug_rtx (x); |
ab532386 | 2801 | internal_error ("internal consistency failure"); |
2c07f13b | 2802 | } |
1a2caa7a | 2803 | gcc_assert (!RTX_FLAG (x, used)); |
b8698a0f | 2804 | |
2c07f13b JH |
2805 | RTX_FLAG (x, used) = 1; |
2806 | ||
6614fd40 | 2807 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2808 | |
2809 | format_ptr = GET_RTX_FORMAT (code); | |
2810 | ||
2811 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2812 | { | |
2813 | switch (*format_ptr++) | |
2814 | { | |
2815 | case 'e': | |
2816 | verify_rtx_sharing (XEXP (x, i), insn); | |
2817 | break; | |
2818 | ||
2819 | case 'E': | |
2820 | if (XVEC (x, i) != NULL) | |
2821 | { | |
2822 | int j; | |
2823 | int len = XVECLEN (x, i); | |
2824 | ||
2825 | for (j = 0; j < len; j++) | |
2826 | { | |
1a2caa7a NS |
2827 | /* We allow sharing of ASM_OPERANDS inside single |
2828 | instruction. */ | |
2c07f13b | 2829 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2830 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2831 | == ASM_OPERANDS)) | |
2c07f13b JH |
2832 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2833 | else | |
2834 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2835 | } | |
2836 | } | |
2837 | break; | |
2838 | } | |
2839 | } | |
2840 | return; | |
2841 | } | |
2842 | ||
0e0f87d4 SB |
2843 | /* Reset used-flags for INSN. */ |
2844 | ||
2845 | static void | |
2846 | reset_insn_used_flags (rtx insn) | |
2847 | { | |
2848 | gcc_assert (INSN_P (insn)); | |
2849 | reset_used_flags (PATTERN (insn)); | |
2850 | reset_used_flags (REG_NOTES (insn)); | |
2851 | if (CALL_P (insn)) | |
2852 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn)); | |
2853 | } | |
2854 | ||
a24243a0 | 2855 | /* Go through all the RTL insn bodies and clear all the USED bits. */ |
2c07f13b | 2856 | |
a24243a0 AK |
2857 | static void |
2858 | reset_all_used_flags (void) | |
2c07f13b | 2859 | { |
dc01c3d1 | 2860 | rtx_insn *p; |
2c07f13b JH |
2861 | |
2862 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2863 | if (INSN_P (p)) | |
2864 | { | |
0e0f87d4 SB |
2865 | rtx pat = PATTERN (p); |
2866 | if (GET_CODE (pat) != SEQUENCE) | |
2867 | reset_insn_used_flags (p); | |
2868 | else | |
2954a813 | 2869 | { |
0e0f87d4 SB |
2870 | gcc_assert (REG_NOTES (p) == NULL); |
2871 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
2872 | { |
2873 | rtx insn = XVECEXP (pat, 0, i); | |
2874 | if (INSN_P (insn)) | |
2875 | reset_insn_used_flags (insn); | |
2876 | } | |
2954a813 | 2877 | } |
2c07f13b | 2878 | } |
a24243a0 AK |
2879 | } |
2880 | ||
0e0f87d4 SB |
2881 | /* Verify sharing in INSN. */ |
2882 | ||
2883 | static void | |
2884 | verify_insn_sharing (rtx insn) | |
2885 | { | |
2886 | gcc_assert (INSN_P (insn)); | |
4b498f72 JJ |
2887 | verify_rtx_sharing (PATTERN (insn), insn); |
2888 | verify_rtx_sharing (REG_NOTES (insn), insn); | |
0e0f87d4 | 2889 | if (CALL_P (insn)) |
4b498f72 | 2890 | verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn), insn); |
0e0f87d4 SB |
2891 | } |
2892 | ||
a24243a0 AK |
2893 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2894 | sharing in between the subexpressions. */ | |
2895 | ||
2896 | DEBUG_FUNCTION void | |
2897 | verify_rtl_sharing (void) | |
2898 | { | |
dc01c3d1 | 2899 | rtx_insn *p; |
a24243a0 AK |
2900 | |
2901 | timevar_push (TV_VERIFY_RTL_SHARING); | |
2902 | ||
2903 | reset_all_used_flags (); | |
2c07f13b JH |
2904 | |
2905 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2906 | if (INSN_P (p)) | |
2907 | { | |
0e0f87d4 SB |
2908 | rtx pat = PATTERN (p); |
2909 | if (GET_CODE (pat) != SEQUENCE) | |
2910 | verify_insn_sharing (p); | |
2911 | else | |
2912 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
2913 | { |
2914 | rtx insn = XVECEXP (pat, 0, i); | |
2915 | if (INSN_P (insn)) | |
2916 | verify_insn_sharing (insn); | |
2917 | } | |
2c07f13b | 2918 | } |
a222c01a | 2919 | |
a24243a0 AK |
2920 | reset_all_used_flags (); |
2921 | ||
a222c01a | 2922 | timevar_pop (TV_VERIFY_RTL_SHARING); |
2c07f13b JH |
2923 | } |
2924 | ||
d1b81779 GK |
2925 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2926 | Assumes the mark bits are cleared at entry. */ | |
2927 | ||
2c07f13b | 2928 | void |
dc01c3d1 | 2929 | unshare_all_rtl_in_chain (rtx_insn *insn) |
d1b81779 GK |
2930 | { |
2931 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2932 | if (INSN_P (insn)) |
d1b81779 GK |
2933 | { |
2934 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2935 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
776bebcd JJ |
2936 | if (CALL_P (insn)) |
2937 | CALL_INSN_FUNCTION_USAGE (insn) | |
2938 | = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn)); | |
d1b81779 GK |
2939 | } |
2940 | } | |
2941 | ||
2d4aecb3 | 2942 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2943 | shared. We never replace the DECL_RTLs themselves with a copy, |
2944 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2945 | expressions in the instruction stream. | |
2946 | ||
2947 | Note that reload may convert pseudo registers into memories in-place. | |
2948 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2949 | reset the used flags on MEMs in the instruction stream, we must set | |
2950 | them again on MEMs that appear in DECL_RTLs. */ | |
2951 | ||
2d4aecb3 | 2952 | static void |
5eb2a9f2 | 2953 | set_used_decls (tree blk) |
2d4aecb3 AO |
2954 | { |
2955 | tree t; | |
2956 | ||
2957 | /* Mark decls. */ | |
910ad8de | 2958 | for (t = BLOCK_VARS (blk); t; t = DECL_CHAIN (t)) |
19e7881c | 2959 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2960 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2961 | |
2962 | /* Now process sub-blocks. */ | |
87caf699 | 2963 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 2964 | set_used_decls (t); |
2d4aecb3 AO |
2965 | } |
2966 | ||
23b2ce53 | 2967 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2968 | Recursively does the same for subexpressions. Uses |
2969 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2970 | |
2971 | rtx | |
502b8322 | 2972 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2973 | { |
32b32b16 AP |
2974 | copy_rtx_if_shared_1 (&orig); |
2975 | return orig; | |
2976 | } | |
2977 | ||
ff954f39 AP |
2978 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2979 | use. Recursively does the same for subexpressions. */ | |
2980 | ||
32b32b16 AP |
2981 | static void |
2982 | copy_rtx_if_shared_1 (rtx *orig1) | |
2983 | { | |
2984 | rtx x; | |
b3694847 SS |
2985 | int i; |
2986 | enum rtx_code code; | |
32b32b16 | 2987 | rtx *last_ptr; |
b3694847 | 2988 | const char *format_ptr; |
23b2ce53 | 2989 | int copied = 0; |
32b32b16 AP |
2990 | int length; |
2991 | ||
2992 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2993 | repeat: | |
2994 | x = *orig1; | |
23b2ce53 RS |
2995 | |
2996 | if (x == 0) | |
32b32b16 | 2997 | return; |
23b2ce53 RS |
2998 | |
2999 | code = GET_CODE (x); | |
3000 | ||
3001 | /* These types may be freely shared. */ | |
3002 | ||
3003 | switch (code) | |
3004 | { | |
3005 | case REG: | |
0ca5af51 AO |
3006 | case DEBUG_EXPR: |
3007 | case VALUE: | |
d8116890 | 3008 | CASE_CONST_ANY: |
23b2ce53 | 3009 | case SYMBOL_REF: |
2c07f13b | 3010 | case LABEL_REF: |
23b2ce53 RS |
3011 | case CODE_LABEL: |
3012 | case PC: | |
3013 | case CC0: | |
276e0224 | 3014 | case RETURN: |
26898771 | 3015 | case SIMPLE_RETURN: |
23b2ce53 | 3016 | case SCRATCH: |
0f41302f | 3017 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 3018 | return; |
3e89ed8d | 3019 | case CLOBBER: |
c5c5ba89 JH |
3020 | /* Share clobbers of hard registers (like cc0), but do not share pseudo reg |
3021 | clobbers or clobbers of hard registers that originated as pseudos. | |
3022 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
3023 | if (REG_P (XEXP (x, 0)) |
3024 | && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0))) | |
3025 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0)))) | |
3e89ed8d JH |
3026 | return; |
3027 | break; | |
23b2ce53 | 3028 | |
b851ea09 | 3029 | case CONST: |
6fb5fa3c | 3030 | if (shared_const_p (x)) |
32b32b16 | 3031 | return; |
b851ea09 RK |
3032 | break; |
3033 | ||
b5b8b0ac | 3034 | case DEBUG_INSN: |
23b2ce53 RS |
3035 | case INSN: |
3036 | case JUMP_INSN: | |
3037 | case CALL_INSN: | |
3038 | case NOTE: | |
23b2ce53 RS |
3039 | case BARRIER: |
3040 | /* The chain of insns is not being copied. */ | |
32b32b16 | 3041 | return; |
23b2ce53 | 3042 | |
e9a25f70 JL |
3043 | default: |
3044 | break; | |
23b2ce53 RS |
3045 | } |
3046 | ||
3047 | /* This rtx may not be shared. If it has already been seen, | |
3048 | replace it with a copy of itself. */ | |
3049 | ||
2adc7f12 | 3050 | if (RTX_FLAG (x, used)) |
23b2ce53 | 3051 | { |
aacd3885 | 3052 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
3053 | copied = 1; |
3054 | } | |
2adc7f12 | 3055 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
3056 | |
3057 | /* Now scan the subexpressions recursively. | |
3058 | We can store any replaced subexpressions directly into X | |
3059 | since we know X is not shared! Any vectors in X | |
3060 | must be copied if X was copied. */ | |
3061 | ||
3062 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
3063 | length = GET_RTX_LENGTH (code); |
3064 | last_ptr = NULL; | |
b8698a0f | 3065 | |
32b32b16 | 3066 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3067 | { |
3068 | switch (*format_ptr++) | |
3069 | { | |
3070 | case 'e': | |
32b32b16 AP |
3071 | if (last_ptr) |
3072 | copy_rtx_if_shared_1 (last_ptr); | |
3073 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
3074 | break; |
3075 | ||
3076 | case 'E': | |
3077 | if (XVEC (x, i) != NULL) | |
3078 | { | |
b3694847 | 3079 | int j; |
f0722107 | 3080 | int len = XVECLEN (x, i); |
b8698a0f | 3081 | |
6614fd40 KH |
3082 | /* Copy the vector iff I copied the rtx and the length |
3083 | is nonzero. */ | |
f0722107 | 3084 | if (copied && len > 0) |
8f985ec4 | 3085 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
b8698a0f | 3086 | |
5d3cc252 | 3087 | /* Call recursively on all inside the vector. */ |
f0722107 | 3088 | for (j = 0; j < len; j++) |
32b32b16 AP |
3089 | { |
3090 | if (last_ptr) | |
3091 | copy_rtx_if_shared_1 (last_ptr); | |
3092 | last_ptr = &XVECEXP (x, i, j); | |
3093 | } | |
23b2ce53 RS |
3094 | } |
3095 | break; | |
3096 | } | |
3097 | } | |
32b32b16 AP |
3098 | *orig1 = x; |
3099 | if (last_ptr) | |
3100 | { | |
3101 | orig1 = last_ptr; | |
3102 | goto repeat; | |
3103 | } | |
3104 | return; | |
23b2ce53 RS |
3105 | } |
3106 | ||
76369a82 | 3107 | /* Set the USED bit in X and its non-shareable subparts to FLAG. */ |
23b2ce53 | 3108 | |
76369a82 NF |
3109 | static void |
3110 | mark_used_flags (rtx x, int flag) | |
23b2ce53 | 3111 | { |
b3694847 SS |
3112 | int i, j; |
3113 | enum rtx_code code; | |
3114 | const char *format_ptr; | |
32b32b16 | 3115 | int length; |
23b2ce53 | 3116 | |
32b32b16 AP |
3117 | /* Repeat is used to turn tail-recursion into iteration. */ |
3118 | repeat: | |
23b2ce53 RS |
3119 | if (x == 0) |
3120 | return; | |
3121 | ||
3122 | code = GET_CODE (x); | |
3123 | ||
9faa82d8 | 3124 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
3125 | for them. */ |
3126 | ||
3127 | switch (code) | |
3128 | { | |
3129 | case REG: | |
0ca5af51 AO |
3130 | case DEBUG_EXPR: |
3131 | case VALUE: | |
d8116890 | 3132 | CASE_CONST_ANY: |
23b2ce53 RS |
3133 | case SYMBOL_REF: |
3134 | case CODE_LABEL: | |
3135 | case PC: | |
3136 | case CC0: | |
276e0224 | 3137 | case RETURN: |
26898771 | 3138 | case SIMPLE_RETURN: |
23b2ce53 RS |
3139 | return; |
3140 | ||
b5b8b0ac | 3141 | case DEBUG_INSN: |
23b2ce53 RS |
3142 | case INSN: |
3143 | case JUMP_INSN: | |
3144 | case CALL_INSN: | |
3145 | case NOTE: | |
3146 | case LABEL_REF: | |
3147 | case BARRIER: | |
3148 | /* The chain of insns is not being copied. */ | |
3149 | return; | |
750c9258 | 3150 | |
e9a25f70 JL |
3151 | default: |
3152 | break; | |
23b2ce53 RS |
3153 | } |
3154 | ||
76369a82 | 3155 | RTX_FLAG (x, used) = flag; |
23b2ce53 RS |
3156 | |
3157 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 | 3158 | length = GET_RTX_LENGTH (code); |
b8698a0f | 3159 | |
32b32b16 | 3160 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3161 | { |
3162 | switch (*format_ptr++) | |
3163 | { | |
3164 | case 'e': | |
32b32b16 AP |
3165 | if (i == length-1) |
3166 | { | |
3167 | x = XEXP (x, i); | |
3168 | goto repeat; | |
3169 | } | |
76369a82 | 3170 | mark_used_flags (XEXP (x, i), flag); |
23b2ce53 RS |
3171 | break; |
3172 | ||
3173 | case 'E': | |
3174 | for (j = 0; j < XVECLEN (x, i); j++) | |
76369a82 | 3175 | mark_used_flags (XVECEXP (x, i, j), flag); |
23b2ce53 RS |
3176 | break; |
3177 | } | |
3178 | } | |
3179 | } | |
2c07f13b | 3180 | |
76369a82 | 3181 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used |
2c07f13b JH |
3182 | to look for shared sub-parts. */ |
3183 | ||
3184 | void | |
76369a82 | 3185 | reset_used_flags (rtx x) |
2c07f13b | 3186 | { |
76369a82 NF |
3187 | mark_used_flags (x, 0); |
3188 | } | |
2c07f13b | 3189 | |
76369a82 NF |
3190 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used |
3191 | to look for shared sub-parts. */ | |
2c07f13b | 3192 | |
76369a82 NF |
3193 | void |
3194 | set_used_flags (rtx x) | |
3195 | { | |
3196 | mark_used_flags (x, 1); | |
2c07f13b | 3197 | } |
23b2ce53 RS |
3198 | \f |
3199 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
3200 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
3201 | OTHER must be valid as a SET_DEST. */ | |
3202 | ||
3203 | rtx | |
502b8322 | 3204 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
3205 | { |
3206 | while (1) | |
3207 | switch (GET_CODE (other)) | |
3208 | { | |
3209 | case SUBREG: | |
3210 | other = SUBREG_REG (other); | |
3211 | break; | |
3212 | case STRICT_LOW_PART: | |
3213 | case SIGN_EXTEND: | |
3214 | case ZERO_EXTEND: | |
3215 | other = XEXP (other, 0); | |
3216 | break; | |
3217 | default: | |
3218 | goto done; | |
3219 | } | |
3220 | done: | |
3c0cb5de | 3221 | if ((MEM_P (other) |
23b2ce53 | 3222 | && ! CONSTANT_P (x) |
f8cfc6aa | 3223 | && !REG_P (x) |
23b2ce53 | 3224 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 3225 | || (REG_P (other) |
23b2ce53 RS |
3226 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
3227 | || reg_mentioned_p (other, x)))) | |
3228 | { | |
3229 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
3230 | emit_move_insn (temp, x); | |
3231 | return temp; | |
3232 | } | |
3233 | return x; | |
3234 | } | |
3235 | \f | |
3236 | /* Emission of insns (adding them to the doubly-linked list). */ | |
3237 | ||
23b2ce53 RS |
3238 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ |
3239 | ||
db76cf1e | 3240 | rtx_insn * |
502b8322 | 3241 | get_last_insn_anywhere (void) |
23b2ce53 | 3242 | { |
614d5bd8 AM |
3243 | struct sequence_stack *seq; |
3244 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
3245 | if (seq->last != 0) | |
3246 | return seq->last; | |
23b2ce53 RS |
3247 | return 0; |
3248 | } | |
3249 | ||
2a496e8b JDA |
3250 | /* Return the first nonnote insn emitted in current sequence or current |
3251 | function. This routine looks inside SEQUENCEs. */ | |
3252 | ||
e4685bc8 | 3253 | rtx_insn * |
502b8322 | 3254 | get_first_nonnote_insn (void) |
2a496e8b | 3255 | { |
dc01c3d1 | 3256 | rtx_insn *insn = get_insns (); |
91373fe8 JDA |
3257 | |
3258 | if (insn) | |
3259 | { | |
3260 | if (NOTE_P (insn)) | |
3261 | for (insn = next_insn (insn); | |
3262 | insn && NOTE_P (insn); | |
3263 | insn = next_insn (insn)) | |
3264 | continue; | |
3265 | else | |
3266 | { | |
2ca202e7 | 3267 | if (NONJUMP_INSN_P (insn) |
91373fe8 | 3268 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
dc01c3d1 | 3269 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
91373fe8 JDA |
3270 | } |
3271 | } | |
2a496e8b JDA |
3272 | |
3273 | return insn; | |
3274 | } | |
3275 | ||
3276 | /* Return the last nonnote insn emitted in current sequence or current | |
3277 | function. This routine looks inside SEQUENCEs. */ | |
3278 | ||
e4685bc8 | 3279 | rtx_insn * |
502b8322 | 3280 | get_last_nonnote_insn (void) |
2a496e8b | 3281 | { |
dc01c3d1 | 3282 | rtx_insn *insn = get_last_insn (); |
91373fe8 JDA |
3283 | |
3284 | if (insn) | |
3285 | { | |
3286 | if (NOTE_P (insn)) | |
3287 | for (insn = previous_insn (insn); | |
3288 | insn && NOTE_P (insn); | |
3289 | insn = previous_insn (insn)) | |
3290 | continue; | |
3291 | else | |
3292 | { | |
dc01c3d1 DM |
3293 | if (NONJUMP_INSN_P (insn)) |
3294 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3295 | insn = seq->insn (seq->len () - 1); | |
91373fe8 JDA |
3296 | } |
3297 | } | |
2a496e8b JDA |
3298 | |
3299 | return insn; | |
3300 | } | |
3301 | ||
b5b8b0ac AO |
3302 | /* Return the number of actual (non-debug) insns emitted in this |
3303 | function. */ | |
3304 | ||
3305 | int | |
3306 | get_max_insn_count (void) | |
3307 | { | |
3308 | int n = cur_insn_uid; | |
3309 | ||
3310 | /* The table size must be stable across -g, to avoid codegen | |
3311 | differences due to debug insns, and not be affected by | |
3312 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
3313 | debugging of -fcompare-debug failures. */ | |
3314 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3315 | n -= cur_debug_insn_uid; | |
3316 | else | |
3317 | n -= MIN_NONDEBUG_INSN_UID; | |
3318 | ||
3319 | return n; | |
3320 | } | |
3321 | ||
23b2ce53 RS |
3322 | \f |
3323 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
3324 | of the sequence. */ | |
3325 | ||
eb51c837 | 3326 | rtx_insn * |
4ce524a1 | 3327 | next_insn (rtx_insn *insn) |
23b2ce53 | 3328 | { |
75547801 KG |
3329 | if (insn) |
3330 | { | |
3331 | insn = NEXT_INSN (insn); | |
3332 | if (insn && NONJUMP_INSN_P (insn) | |
3333 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
dc01c3d1 | 3334 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
75547801 | 3335 | } |
23b2ce53 | 3336 | |
dc01c3d1 | 3337 | return insn; |
23b2ce53 RS |
3338 | } |
3339 | ||
3340 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3341 | of the sequence. */ | |
3342 | ||
eb51c837 | 3343 | rtx_insn * |
4ce524a1 | 3344 | previous_insn (rtx_insn *insn) |
23b2ce53 | 3345 | { |
75547801 KG |
3346 | if (insn) |
3347 | { | |
3348 | insn = PREV_INSN (insn); | |
dc01c3d1 DM |
3349 | if (insn && NONJUMP_INSN_P (insn)) |
3350 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3351 | insn = seq->insn (seq->len () - 1); | |
75547801 | 3352 | } |
23b2ce53 | 3353 | |
dc01c3d1 | 3354 | return insn; |
23b2ce53 RS |
3355 | } |
3356 | ||
3357 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3358 | look inside SEQUENCEs. */ | |
3359 | ||
eb51c837 | 3360 | rtx_insn * |
c9b0a227 | 3361 | next_nonnote_insn (rtx_insn *insn) |
23b2ce53 | 3362 | { |
75547801 KG |
3363 | while (insn) |
3364 | { | |
3365 | insn = NEXT_INSN (insn); | |
3366 | if (insn == 0 || !NOTE_P (insn)) | |
3367 | break; | |
3368 | } | |
23b2ce53 | 3369 | |
dc01c3d1 | 3370 | return insn; |
23b2ce53 RS |
3371 | } |
3372 | ||
1e211590 DD |
3373 | /* Return the next insn after INSN that is not a NOTE, but stop the |
3374 | search before we enter another basic block. This routine does not | |
3375 | look inside SEQUENCEs. */ | |
3376 | ||
eb51c837 | 3377 | rtx_insn * |
e4685bc8 | 3378 | next_nonnote_insn_bb (rtx_insn *insn) |
1e211590 DD |
3379 | { |
3380 | while (insn) | |
3381 | { | |
3382 | insn = NEXT_INSN (insn); | |
3383 | if (insn == 0 || !NOTE_P (insn)) | |
3384 | break; | |
3385 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
eb51c837 | 3386 | return NULL; |
1e211590 DD |
3387 | } |
3388 | ||
dc01c3d1 | 3389 | return insn; |
1e211590 DD |
3390 | } |
3391 | ||
23b2ce53 RS |
3392 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3393 | not look inside SEQUENCEs. */ | |
3394 | ||
eb51c837 | 3395 | rtx_insn * |
c9b0a227 | 3396 | prev_nonnote_insn (rtx_insn *insn) |
23b2ce53 | 3397 | { |
75547801 KG |
3398 | while (insn) |
3399 | { | |
3400 | insn = PREV_INSN (insn); | |
3401 | if (insn == 0 || !NOTE_P (insn)) | |
3402 | break; | |
3403 | } | |
23b2ce53 | 3404 | |
dc01c3d1 | 3405 | return insn; |
23b2ce53 RS |
3406 | } |
3407 | ||
896aa4ea DD |
3408 | /* Return the previous insn before INSN that is not a NOTE, but stop |
3409 | the search before we enter another basic block. This routine does | |
3410 | not look inside SEQUENCEs. */ | |
3411 | ||
eb51c837 | 3412 | rtx_insn * |
9815687d | 3413 | prev_nonnote_insn_bb (rtx_insn *insn) |
896aa4ea | 3414 | { |
dc01c3d1 | 3415 | |
896aa4ea DD |
3416 | while (insn) |
3417 | { | |
3418 | insn = PREV_INSN (insn); | |
3419 | if (insn == 0 || !NOTE_P (insn)) | |
3420 | break; | |
3421 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
eb51c837 | 3422 | return NULL; |
896aa4ea DD |
3423 | } |
3424 | ||
dc01c3d1 | 3425 | return insn; |
896aa4ea DD |
3426 | } |
3427 | ||
b5b8b0ac AO |
3428 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3429 | routine does not look inside SEQUENCEs. */ | |
3430 | ||
eb51c837 | 3431 | rtx_insn * |
30d2ef86 | 3432 | next_nondebug_insn (rtx_insn *insn) |
b5b8b0ac AO |
3433 | { |
3434 | while (insn) | |
3435 | { | |
3436 | insn = NEXT_INSN (insn); | |
3437 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3438 | break; | |
3439 | } | |
3440 | ||
dc01c3d1 | 3441 | return insn; |
b5b8b0ac AO |
3442 | } |
3443 | ||
3444 | /* Return the previous insn before INSN that is not a DEBUG_INSN. | |
3445 | This routine does not look inside SEQUENCEs. */ | |
3446 | ||
eb51c837 | 3447 | rtx_insn * |
30d2ef86 | 3448 | prev_nondebug_insn (rtx_insn *insn) |
b5b8b0ac AO |
3449 | { |
3450 | while (insn) | |
3451 | { | |
3452 | insn = PREV_INSN (insn); | |
3453 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3454 | break; | |
3455 | } | |
3456 | ||
dc01c3d1 | 3457 | return insn; |
b5b8b0ac AO |
3458 | } |
3459 | ||
f0fc0803 JJ |
3460 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN. |
3461 | This routine does not look inside SEQUENCEs. */ | |
3462 | ||
eb51c837 | 3463 | rtx_insn * |
1f00691e | 3464 | next_nonnote_nondebug_insn (rtx_insn *insn) |
f0fc0803 JJ |
3465 | { |
3466 | while (insn) | |
3467 | { | |
3468 | insn = NEXT_INSN (insn); | |
3469 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) | |
3470 | break; | |
3471 | } | |
3472 | ||
dc01c3d1 | 3473 | return insn; |
f0fc0803 JJ |
3474 | } |
3475 | ||
3476 | /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN. | |
3477 | This routine does not look inside SEQUENCEs. */ | |
3478 | ||
eb51c837 | 3479 | rtx_insn * |
1f00691e | 3480 | prev_nonnote_nondebug_insn (rtx_insn *insn) |
f0fc0803 JJ |
3481 | { |
3482 | while (insn) | |
3483 | { | |
3484 | insn = PREV_INSN (insn); | |
3485 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) | |
3486 | break; | |
3487 | } | |
3488 | ||
dc01c3d1 | 3489 | return insn; |
f0fc0803 JJ |
3490 | } |
3491 | ||
23b2ce53 RS |
3492 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3493 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3494 | SEQUENCEs. */ |
23b2ce53 | 3495 | |
eb51c837 | 3496 | rtx_insn * |
dc01c3d1 | 3497 | next_real_insn (rtx uncast_insn) |
23b2ce53 | 3498 | { |
dc01c3d1 DM |
3499 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); |
3500 | ||
75547801 KG |
3501 | while (insn) |
3502 | { | |
3503 | insn = NEXT_INSN (insn); | |
3504 | if (insn == 0 || INSN_P (insn)) | |
3505 | break; | |
3506 | } | |
23b2ce53 | 3507 | |
dc01c3d1 | 3508 | return insn; |
23b2ce53 RS |
3509 | } |
3510 | ||
3511 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3512 | or 0, if there is none. This routine does not look inside | |
3513 | SEQUENCEs. */ | |
3514 | ||
eb51c837 | 3515 | rtx_insn * |
d8fd56b2 | 3516 | prev_real_insn (rtx_insn *insn) |
23b2ce53 | 3517 | { |
75547801 KG |
3518 | while (insn) |
3519 | { | |
3520 | insn = PREV_INSN (insn); | |
3521 | if (insn == 0 || INSN_P (insn)) | |
3522 | break; | |
3523 | } | |
23b2ce53 | 3524 | |
dc01c3d1 | 3525 | return insn; |
23b2ce53 RS |
3526 | } |
3527 | ||
ee960939 OH |
3528 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3529 | This routine does not look inside SEQUENCEs. */ | |
3530 | ||
049cfc4a | 3531 | rtx_call_insn * |
502b8322 | 3532 | last_call_insn (void) |
ee960939 | 3533 | { |
049cfc4a | 3534 | rtx_insn *insn; |
ee960939 OH |
3535 | |
3536 | for (insn = get_last_insn (); | |
4b4bf941 | 3537 | insn && !CALL_P (insn); |
ee960939 OH |
3538 | insn = PREV_INSN (insn)) |
3539 | ; | |
3540 | ||
049cfc4a | 3541 | return safe_as_a <rtx_call_insn *> (insn); |
ee960939 OH |
3542 | } |
3543 | ||
23b2ce53 | 3544 | /* Find the next insn after INSN that really does something. This routine |
9c517bf3 AK |
3545 | does not look inside SEQUENCEs. After reload this also skips over |
3546 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3547 | |
69732dcb | 3548 | int |
7c9796ed | 3549 | active_insn_p (const rtx_insn *insn) |
69732dcb | 3550 | { |
4b4bf941 | 3551 | return (CALL_P (insn) || JUMP_P (insn) |
39718607 | 3552 | || JUMP_TABLE_DATA_P (insn) /* FIXME */ |
4b4bf941 | 3553 | || (NONJUMP_INSN_P (insn) |
23b8ba81 RH |
3554 | && (! reload_completed |
3555 | || (GET_CODE (PATTERN (insn)) != USE | |
3556 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3557 | } |
3558 | ||
eb51c837 | 3559 | rtx_insn * |
7c9796ed | 3560 | next_active_insn (rtx_insn *insn) |
23b2ce53 | 3561 | { |
75547801 KG |
3562 | while (insn) |
3563 | { | |
3564 | insn = NEXT_INSN (insn); | |
3565 | if (insn == 0 || active_insn_p (insn)) | |
3566 | break; | |
3567 | } | |
23b2ce53 | 3568 | |
dc01c3d1 | 3569 | return insn; |
23b2ce53 RS |
3570 | } |
3571 | ||
3572 | /* Find the last insn before INSN that really does something. This routine | |
9c517bf3 AK |
3573 | does not look inside SEQUENCEs. After reload this also skips over |
3574 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3575 | |
eb51c837 | 3576 | rtx_insn * |
7c9796ed | 3577 | prev_active_insn (rtx_insn *insn) |
23b2ce53 | 3578 | { |
75547801 KG |
3579 | while (insn) |
3580 | { | |
3581 | insn = PREV_INSN (insn); | |
3582 | if (insn == 0 || active_insn_p (insn)) | |
3583 | break; | |
3584 | } | |
23b2ce53 | 3585 | |
dc01c3d1 | 3586 | return insn; |
23b2ce53 | 3587 | } |
23b2ce53 | 3588 | \f |
23b2ce53 RS |
3589 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3590 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3591 | applied to the result of this function should yield INSN). | |
3592 | ||
3593 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3594 | is present, it contains the insn that uses CC0. | |
3595 | ||
3596 | Return 0 if we can't find the insn. */ | |
3597 | ||
75b46023 | 3598 | rtx_insn * |
475edec0 | 3599 | next_cc0_user (rtx_insn *insn) |
23b2ce53 | 3600 | { |
906c4e36 | 3601 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3602 | |
3603 | if (note) | |
75b46023 | 3604 | return safe_as_a <rtx_insn *> (XEXP (note, 0)); |
23b2ce53 RS |
3605 | |
3606 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3607 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
dc01c3d1 | 3608 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
23b2ce53 | 3609 | |
2c3c49de | 3610 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
dc01c3d1 | 3611 | return insn; |
23b2ce53 RS |
3612 | |
3613 | return 0; | |
3614 | } | |
3615 | ||
3616 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3617 | note, it is the previous insn. */ | |
3618 | ||
75b46023 | 3619 | rtx_insn * |
5c8db5b4 | 3620 | prev_cc0_setter (rtx_insn *insn) |
23b2ce53 | 3621 | { |
906c4e36 | 3622 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3623 | |
3624 | if (note) | |
75b46023 | 3625 | return safe_as_a <rtx_insn *> (XEXP (note, 0)); |
23b2ce53 RS |
3626 | |
3627 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3628 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 | 3629 | |
dc01c3d1 | 3630 | return insn; |
23b2ce53 | 3631 | } |
e5bef2e4 | 3632 | |
594f8779 RZ |
3633 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ |
3634 | ||
3635 | static int | |
9021b8ec | 3636 | find_auto_inc (const_rtx x, const_rtx reg) |
594f8779 | 3637 | { |
9021b8ec RS |
3638 | subrtx_iterator::array_type array; |
3639 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
594f8779 | 3640 | { |
9021b8ec RS |
3641 | const_rtx x = *iter; |
3642 | if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC | |
3643 | && rtx_equal_p (reg, XEXP (x, 0))) | |
3644 | return true; | |
594f8779 | 3645 | } |
9021b8ec | 3646 | return false; |
594f8779 | 3647 | } |
594f8779 | 3648 | |
e5bef2e4 HB |
3649 | /* Increment the label uses for all labels present in rtx. */ |
3650 | ||
3651 | static void | |
502b8322 | 3652 | mark_label_nuses (rtx x) |
e5bef2e4 | 3653 | { |
b3694847 SS |
3654 | enum rtx_code code; |
3655 | int i, j; | |
3656 | const char *fmt; | |
e5bef2e4 HB |
3657 | |
3658 | code = GET_CODE (x); | |
04a121a7 TS |
3659 | if (code == LABEL_REF && LABEL_P (label_ref_label (x))) |
3660 | LABEL_NUSES (label_ref_label (x))++; | |
e5bef2e4 HB |
3661 | |
3662 | fmt = GET_RTX_FORMAT (code); | |
3663 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3664 | { | |
3665 | if (fmt[i] == 'e') | |
0fb7aeda | 3666 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3667 | else if (fmt[i] == 'E') |
0fb7aeda | 3668 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3669 | mark_label_nuses (XVECEXP (x, i, j)); |
3670 | } | |
3671 | } | |
3672 | ||
23b2ce53 RS |
3673 | \f |
3674 | /* Try splitting insns that can be split for better scheduling. | |
3675 | PAT is the pattern which might split. | |
3676 | TRIAL is the insn providing PAT. | |
cc2902df | 3677 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3678 | |
3679 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3680 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3681 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3682 | ||
53f04688 | 3683 | rtx_insn * |
bb5c4956 | 3684 | try_split (rtx pat, rtx_insn *trial, int last) |
23b2ce53 | 3685 | { |
d4eff95b | 3686 | rtx_insn *before, *after; |
dc01c3d1 DM |
3687 | rtx note; |
3688 | rtx_insn *seq, *tem; | |
5fa396ad | 3689 | profile_probability probability; |
dc01c3d1 | 3690 | rtx_insn *insn_last, *insn; |
599aedd9 | 3691 | int njumps = 0; |
e67d1102 | 3692 | rtx_insn *call_insn = NULL; |
6b24c259 | 3693 | |
cd9c1ca8 RH |
3694 | /* We're not good at redistributing frame information. */ |
3695 | if (RTX_FRAME_RELATED_P (trial)) | |
dc01c3d1 | 3696 | return trial; |
cd9c1ca8 | 3697 | |
6b24c259 JH |
3698 | if (any_condjump_p (trial) |
3699 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
5fa396ad JH |
3700 | split_branch_probability |
3701 | = profile_probability::from_reg_br_prob_note (XINT (note, 0)); | |
3702 | else | |
3703 | split_branch_probability = profile_probability::uninitialized (); | |
3704 | ||
6b24c259 JH |
3705 | probability = split_branch_probability; |
3706 | ||
bb5c4956 | 3707 | seq = split_insns (pat, trial); |
6b24c259 | 3708 | |
5fa396ad | 3709 | split_branch_probability = profile_probability::uninitialized (); |
23b2ce53 | 3710 | |
599aedd9 | 3711 | if (!seq) |
dc01c3d1 | 3712 | return trial; |
599aedd9 RH |
3713 | |
3714 | /* Avoid infinite loop if any insn of the result matches | |
3715 | the original pattern. */ | |
3716 | insn_last = seq; | |
3717 | while (1) | |
23b2ce53 | 3718 | { |
599aedd9 RH |
3719 | if (INSN_P (insn_last) |
3720 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
dc01c3d1 | 3721 | return trial; |
599aedd9 RH |
3722 | if (!NEXT_INSN (insn_last)) |
3723 | break; | |
3724 | insn_last = NEXT_INSN (insn_last); | |
3725 | } | |
750c9258 | 3726 | |
6fb5fa3c DB |
3727 | /* We will be adding the new sequence to the function. The splitters |
3728 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3729 | unshare_all_rtl_in_chain (seq); | |
3730 | ||
339ba33b | 3731 | /* Mark labels and copy flags. */ |
599aedd9 RH |
3732 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) |
3733 | { | |
4b4bf941 | 3734 | if (JUMP_P (insn)) |
599aedd9 | 3735 | { |
339ba33b RS |
3736 | if (JUMP_P (trial)) |
3737 | CROSSING_JUMP_P (insn) = CROSSING_JUMP_P (trial); | |
599aedd9 RH |
3738 | mark_jump_label (PATTERN (insn), insn, 0); |
3739 | njumps++; | |
5fa396ad | 3740 | if (probability.initialized_p () |
599aedd9 RH |
3741 | && any_condjump_p (insn) |
3742 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3743 | { |
599aedd9 RH |
3744 | /* We can preserve the REG_BR_PROB notes only if exactly |
3745 | one jump is created, otherwise the machine description | |
3746 | is responsible for this step using | |
3747 | split_branch_probability variable. */ | |
5b0264cb | 3748 | gcc_assert (njumps == 1); |
5fa396ad | 3749 | add_reg_br_prob_note (insn, probability); |
2f937369 | 3750 | } |
599aedd9 RH |
3751 | } |
3752 | } | |
3753 | ||
3754 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
65712d5c | 3755 | in SEQ and copy any additional information across. */ |
4b4bf941 | 3756 | if (CALL_P (trial)) |
599aedd9 RH |
3757 | { |
3758 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3759 | if (CALL_P (insn)) |
599aedd9 | 3760 | { |
dc01c3d1 DM |
3761 | rtx_insn *next; |
3762 | rtx *p; | |
65712d5c | 3763 | |
4f660b15 RO |
3764 | gcc_assert (call_insn == NULL_RTX); |
3765 | call_insn = insn; | |
3766 | ||
65712d5c RS |
3767 | /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the |
3768 | target may have explicitly specified. */ | |
3769 | p = &CALL_INSN_FUNCTION_USAGE (insn); | |
f6a1f3f6 RH |
3770 | while (*p) |
3771 | p = &XEXP (*p, 1); | |
3772 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
65712d5c RS |
3773 | |
3774 | /* If the old call was a sibling call, the new one must | |
3775 | be too. */ | |
599aedd9 | 3776 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
65712d5c RS |
3777 | |
3778 | /* If the new call is the last instruction in the sequence, | |
3779 | it will effectively replace the old call in-situ. Otherwise | |
3780 | we must move any following NOTE_INSN_CALL_ARG_LOCATION note | |
3781 | so that it comes immediately after the new call. */ | |
3782 | if (NEXT_INSN (insn)) | |
65f3dedb RS |
3783 | for (next = NEXT_INSN (trial); |
3784 | next && NOTE_P (next); | |
3785 | next = NEXT_INSN (next)) | |
3786 | if (NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) | |
65712d5c RS |
3787 | { |
3788 | remove_insn (next); | |
3789 | add_insn_after (next, insn, NULL); | |
65f3dedb | 3790 | break; |
65712d5c | 3791 | } |
599aedd9 RH |
3792 | } |
3793 | } | |
4b5e8abe | 3794 | |
599aedd9 RH |
3795 | /* Copy notes, particularly those related to the CFG. */ |
3796 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3797 | { | |
3798 | switch (REG_NOTE_KIND (note)) | |
3799 | { | |
3800 | case REG_EH_REGION: | |
1d65f45c | 3801 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3802 | break; |
216183ce | 3803 | |
599aedd9 RH |
3804 | case REG_NORETURN: |
3805 | case REG_SETJMP: | |
0a35513e | 3806 | case REG_TM: |
5c5f0b65 | 3807 | case REG_CALL_NOCF_CHECK: |
594f8779 | 3808 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3809 | { |
4b4bf941 | 3810 | if (CALL_P (insn)) |
65c5f2a6 | 3811 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3812 | } |
599aedd9 | 3813 | break; |
d6e95df8 | 3814 | |
599aedd9 | 3815 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3816 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3817 | { |
4b4bf941 | 3818 | if (JUMP_P (insn)) |
65c5f2a6 | 3819 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3820 | } |
599aedd9 | 3821 | break; |
e5bef2e4 | 3822 | |
594f8779 | 3823 | case REG_INC: |
760edf20 TS |
3824 | if (!AUTO_INC_DEC) |
3825 | break; | |
3826 | ||
594f8779 RZ |
3827 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
3828 | { | |
3829 | rtx reg = XEXP (note, 0); | |
3830 | if (!FIND_REG_INC_NOTE (insn, reg) | |
9021b8ec | 3831 | && find_auto_inc (PATTERN (insn), reg)) |
65c5f2a6 | 3832 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3833 | } |
3834 | break; | |
594f8779 | 3835 | |
9a08d230 | 3836 | case REG_ARGS_SIZE: |
e5b51ca0 | 3837 | fixup_args_size_notes (NULL, insn_last, INTVAL (XEXP (note, 0))); |
9a08d230 RH |
3838 | break; |
3839 | ||
4f660b15 RO |
3840 | case REG_CALL_DECL: |
3841 | gcc_assert (call_insn != NULL_RTX); | |
3842 | add_reg_note (call_insn, REG_NOTE_KIND (note), XEXP (note, 0)); | |
3843 | break; | |
3844 | ||
599aedd9 RH |
3845 | default: |
3846 | break; | |
23b2ce53 | 3847 | } |
599aedd9 RH |
3848 | } |
3849 | ||
3850 | /* If there are LABELS inside the split insns increment the | |
3851 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3852 | if (INSN_P (trial)) |
599aedd9 RH |
3853 | { |
3854 | insn = insn_last; | |
3855 | while (insn != NULL_RTX) | |
23b2ce53 | 3856 | { |
cf7c4aa6 | 3857 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3858 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3859 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3860 | |
599aedd9 RH |
3861 | insn = PREV_INSN (insn); |
3862 | } | |
23b2ce53 RS |
3863 | } |
3864 | ||
d4eff95b JC |
3865 | before = PREV_INSN (trial); |
3866 | after = NEXT_INSN (trial); | |
3867 | ||
5368224f | 3868 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATION (trial)); |
599aedd9 RH |
3869 | |
3870 | delete_insn (trial); | |
599aedd9 RH |
3871 | |
3872 | /* Recursively call try_split for each new insn created; by the | |
3873 | time control returns here that insn will be fully split, so | |
3874 | set LAST and continue from the insn after the one returned. | |
3875 | We can't use next_active_insn here since AFTER may be a note. | |
3876 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3877 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
4654c0cf | 3878 | if (! tem->deleted () && INSN_P (tem)) |
599aedd9 RH |
3879 | tem = try_split (PATTERN (tem), tem, 1); |
3880 | ||
3881 | /* Return either the first or the last insn, depending on which was | |
3882 | requested. */ | |
3883 | return last | |
5936d944 | 3884 | ? (after ? PREV_INSN (after) : get_last_insn ()) |
599aedd9 | 3885 | : NEXT_INSN (before); |
23b2ce53 RS |
3886 | } |
3887 | \f | |
3888 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3889 | Store PATTERN in the pattern slots. */ |
23b2ce53 | 3890 | |
167b9fae | 3891 | rtx_insn * |
502b8322 | 3892 | make_insn_raw (rtx pattern) |
23b2ce53 | 3893 | { |
167b9fae | 3894 | rtx_insn *insn; |
23b2ce53 | 3895 | |
167b9fae | 3896 | insn = as_a <rtx_insn *> (rtx_alloc (INSN)); |
23b2ce53 | 3897 | |
43127294 | 3898 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3899 | PATTERN (insn) = pattern; |
3900 | INSN_CODE (insn) = -1; | |
1632afca | 3901 | REG_NOTES (insn) = NULL; |
5368224f | 3902 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3903 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3904 | |
47984720 NC |
3905 | #ifdef ENABLE_RTL_CHECKING |
3906 | if (insn | |
2c3c49de | 3907 | && INSN_P (insn) |
47984720 NC |
3908 | && (returnjump_p (insn) |
3909 | || (GET_CODE (insn) == SET | |
3910 | && SET_DEST (insn) == pc_rtx))) | |
3911 | { | |
d4ee4d25 | 3912 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3913 | debug_rtx (insn); |
3914 | } | |
3915 | #endif | |
750c9258 | 3916 | |
23b2ce53 RS |
3917 | return insn; |
3918 | } | |
3919 | ||
b5b8b0ac AO |
3920 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
3921 | ||
167b9fae | 3922 | static rtx_insn * |
b5b8b0ac AO |
3923 | make_debug_insn_raw (rtx pattern) |
3924 | { | |
167b9fae | 3925 | rtx_debug_insn *insn; |
b5b8b0ac | 3926 | |
167b9fae | 3927 | insn = as_a <rtx_debug_insn *> (rtx_alloc (DEBUG_INSN)); |
b5b8b0ac AO |
3928 | INSN_UID (insn) = cur_debug_insn_uid++; |
3929 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3930 | INSN_UID (insn) = cur_insn_uid++; | |
3931 | ||
3932 | PATTERN (insn) = pattern; | |
3933 | INSN_CODE (insn) = -1; | |
3934 | REG_NOTES (insn) = NULL; | |
5368224f | 3935 | INSN_LOCATION (insn) = curr_insn_location (); |
b5b8b0ac AO |
3936 | BLOCK_FOR_INSN (insn) = NULL; |
3937 | ||
3938 | return insn; | |
3939 | } | |
3940 | ||
2f937369 | 3941 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3942 | |
167b9fae | 3943 | static rtx_insn * |
502b8322 | 3944 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3945 | { |
167b9fae | 3946 | rtx_jump_insn *insn; |
23b2ce53 | 3947 | |
167b9fae | 3948 | insn = as_a <rtx_jump_insn *> (rtx_alloc (JUMP_INSN)); |
1632afca | 3949 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3950 | |
3951 | PATTERN (insn) = pattern; | |
3952 | INSN_CODE (insn) = -1; | |
1632afca RS |
3953 | REG_NOTES (insn) = NULL; |
3954 | JUMP_LABEL (insn) = NULL; | |
5368224f | 3955 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3956 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3957 | |
3958 | return insn; | |
3959 | } | |
aff507f4 | 3960 | |
2f937369 | 3961 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 | 3962 | |
167b9fae | 3963 | static rtx_insn * |
502b8322 | 3964 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3965 | { |
167b9fae | 3966 | rtx_call_insn *insn; |
aff507f4 | 3967 | |
167b9fae | 3968 | insn = as_a <rtx_call_insn *> (rtx_alloc (CALL_INSN)); |
aff507f4 RK |
3969 | INSN_UID (insn) = cur_insn_uid++; |
3970 | ||
3971 | PATTERN (insn) = pattern; | |
3972 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3973 | REG_NOTES (insn) = NULL; |
3974 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
5368224f | 3975 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3976 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3977 | |
3978 | return insn; | |
3979 | } | |
96fba521 SB |
3980 | |
3981 | /* Like `make_insn_raw' but make a NOTE instead of an insn. */ | |
3982 | ||
66e8df53 | 3983 | static rtx_note * |
96fba521 SB |
3984 | make_note_raw (enum insn_note subtype) |
3985 | { | |
3986 | /* Some notes are never created this way at all. These notes are | |
3987 | only created by patching out insns. */ | |
3988 | gcc_assert (subtype != NOTE_INSN_DELETED_LABEL | |
3989 | && subtype != NOTE_INSN_DELETED_DEBUG_LABEL); | |
3990 | ||
66e8df53 | 3991 | rtx_note *note = as_a <rtx_note *> (rtx_alloc (NOTE)); |
96fba521 SB |
3992 | INSN_UID (note) = cur_insn_uid++; |
3993 | NOTE_KIND (note) = subtype; | |
3994 | BLOCK_FOR_INSN (note) = NULL; | |
3995 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); | |
3996 | return note; | |
3997 | } | |
23b2ce53 | 3998 | \f |
96fba521 SB |
3999 | /* Add INSN to the end of the doubly-linked list, between PREV and NEXT. |
4000 | INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects, | |
4001 | but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */ | |
4002 | ||
4003 | static inline void | |
9152e0aa | 4004 | link_insn_into_chain (rtx_insn *insn, rtx_insn *prev, rtx_insn *next) |
96fba521 | 4005 | { |
0f82e5c9 DM |
4006 | SET_PREV_INSN (insn) = prev; |
4007 | SET_NEXT_INSN (insn) = next; | |
96fba521 SB |
4008 | if (prev != NULL) |
4009 | { | |
0f82e5c9 | 4010 | SET_NEXT_INSN (prev) = insn; |
96fba521 SB |
4011 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
4012 | { | |
e6eda746 DM |
4013 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4014 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = insn; | |
96fba521 SB |
4015 | } |
4016 | } | |
4017 | if (next != NULL) | |
4018 | { | |
0f82e5c9 | 4019 | SET_PREV_INSN (next) = insn; |
96fba521 | 4020 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4021 | { |
4022 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4023 | SET_PREV_INSN (sequence->insn (0)) = insn; | |
4024 | } | |
96fba521 | 4025 | } |
3ccb989e SB |
4026 | |
4027 | if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4028 | { | |
e6eda746 DM |
4029 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (insn)); |
4030 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4031 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
3ccb989e | 4032 | } |
96fba521 SB |
4033 | } |
4034 | ||
23b2ce53 RS |
4035 | /* Add INSN to the end of the doubly-linked list. |
4036 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
4037 | ||
4038 | void | |
9152e0aa | 4039 | add_insn (rtx_insn *insn) |
23b2ce53 | 4040 | { |
9152e0aa | 4041 | rtx_insn *prev = get_last_insn (); |
96fba521 | 4042 | link_insn_into_chain (insn, prev, NULL); |
5936d944 JH |
4043 | if (NULL == get_insns ()) |
4044 | set_first_insn (insn); | |
5936d944 | 4045 | set_last_insn (insn); |
23b2ce53 RS |
4046 | } |
4047 | ||
96fba521 | 4048 | /* Add INSN into the doubly-linked list after insn AFTER. */ |
23b2ce53 | 4049 | |
96fba521 | 4050 | static void |
9152e0aa | 4051 | add_insn_after_nobb (rtx_insn *insn, rtx_insn *after) |
23b2ce53 | 4052 | { |
9152e0aa | 4053 | rtx_insn *next = NEXT_INSN (after); |
23b2ce53 | 4054 | |
4654c0cf | 4055 | gcc_assert (!optimize || !after->deleted ()); |
ba213285 | 4056 | |
96fba521 | 4057 | link_insn_into_chain (insn, after, next); |
23b2ce53 | 4058 | |
96fba521 | 4059 | if (next == NULL) |
23b2ce53 | 4060 | { |
614d5bd8 AM |
4061 | struct sequence_stack *seq; |
4062 | ||
4063 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4064 | if (after == seq->last) | |
4065 | { | |
4066 | seq->last = insn; | |
4067 | break; | |
4068 | } | |
23b2ce53 | 4069 | } |
96fba521 SB |
4070 | } |
4071 | ||
4072 | /* Add INSN into the doubly-linked list before insn BEFORE. */ | |
4073 | ||
4074 | static void | |
9152e0aa | 4075 | add_insn_before_nobb (rtx_insn *insn, rtx_insn *before) |
96fba521 | 4076 | { |
9152e0aa | 4077 | rtx_insn *prev = PREV_INSN (before); |
96fba521 | 4078 | |
4654c0cf | 4079 | gcc_assert (!optimize || !before->deleted ()); |
96fba521 SB |
4080 | |
4081 | link_insn_into_chain (insn, prev, before); | |
4082 | ||
4083 | if (prev == NULL) | |
23b2ce53 | 4084 | { |
614d5bd8 | 4085 | struct sequence_stack *seq; |
a0ae8e8d | 4086 | |
614d5bd8 AM |
4087 | for (seq = get_current_sequence (); seq; seq = seq->next) |
4088 | if (before == seq->first) | |
4089 | { | |
4090 | seq->first = insn; | |
4091 | break; | |
4092 | } | |
4093 | ||
4094 | gcc_assert (seq); | |
23b2ce53 | 4095 | } |
96fba521 SB |
4096 | } |
4097 | ||
4098 | /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN. | |
4099 | If BB is NULL, an attempt is made to infer the bb from before. | |
4100 | ||
4101 | This and the next function should be the only functions called | |
4102 | to insert an insn once delay slots have been filled since only | |
4103 | they know how to update a SEQUENCE. */ | |
23b2ce53 | 4104 | |
96fba521 | 4105 | void |
9152e0aa | 4106 | add_insn_after (rtx uncast_insn, rtx uncast_after, basic_block bb) |
96fba521 | 4107 | { |
1130d5e3 | 4108 | rtx_insn *insn = as_a <rtx_insn *> (uncast_insn); |
9152e0aa | 4109 | rtx_insn *after = as_a <rtx_insn *> (uncast_after); |
96fba521 | 4110 | add_insn_after_nobb (insn, after); |
4b4bf941 JQ |
4111 | if (!BARRIER_P (after) |
4112 | && !BARRIER_P (insn) | |
3c030e88 JH |
4113 | && (bb = BLOCK_FOR_INSN (after))) |
4114 | { | |
4115 | set_block_for_insn (insn, bb); | |
38c1593d | 4116 | if (INSN_P (insn)) |
6fb5fa3c | 4117 | df_insn_rescan (insn); |
3c030e88 | 4118 | /* Should not happen as first in the BB is always |
a1f300c0 | 4119 | either NOTE or LABEL. */ |
a813c111 | 4120 | if (BB_END (bb) == after |
3c030e88 | 4121 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 4122 | && !BARRIER_P (insn) |
a38e7aa5 | 4123 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
1130d5e3 | 4124 | BB_END (bb) = insn; |
3c030e88 | 4125 | } |
23b2ce53 RS |
4126 | } |
4127 | ||
96fba521 SB |
4128 | /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN. |
4129 | If BB is NULL, an attempt is made to infer the bb from before. | |
4130 | ||
4131 | This and the previous function should be the only functions called | |
4132 | to insert an insn once delay slots have been filled since only | |
4133 | they know how to update a SEQUENCE. */ | |
a0ae8e8d RK |
4134 | |
4135 | void | |
9152e0aa | 4136 | add_insn_before (rtx uncast_insn, rtx uncast_before, basic_block bb) |
a0ae8e8d | 4137 | { |
9152e0aa DM |
4138 | rtx_insn *insn = as_a <rtx_insn *> (uncast_insn); |
4139 | rtx_insn *before = as_a <rtx_insn *> (uncast_before); | |
96fba521 | 4140 | add_insn_before_nobb (insn, before); |
a0ae8e8d | 4141 | |
b8698a0f | 4142 | if (!bb |
6fb5fa3c DB |
4143 | && !BARRIER_P (before) |
4144 | && !BARRIER_P (insn)) | |
4145 | bb = BLOCK_FOR_INSN (before); | |
4146 | ||
4147 | if (bb) | |
3c030e88 JH |
4148 | { |
4149 | set_block_for_insn (insn, bb); | |
38c1593d | 4150 | if (INSN_P (insn)) |
6fb5fa3c | 4151 | df_insn_rescan (insn); |
5b0264cb | 4152 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 4153 | LABEL. */ |
5b0264cb NS |
4154 | gcc_assert (BB_HEAD (bb) != insn |
4155 | /* Avoid clobbering of structure when creating new BB. */ | |
4156 | || BARRIER_P (insn) | |
a38e7aa5 | 4157 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 | 4158 | } |
a0ae8e8d RK |
4159 | } |
4160 | ||
6fb5fa3c DB |
4161 | /* Replace insn with an deleted instruction note. */ |
4162 | ||
0ce2b299 EB |
4163 | void |
4164 | set_insn_deleted (rtx insn) | |
6fb5fa3c | 4165 | { |
39718607 | 4166 | if (INSN_P (insn)) |
b2908ba6 | 4167 | df_insn_delete (as_a <rtx_insn *> (insn)); |
6fb5fa3c DB |
4168 | PUT_CODE (insn, NOTE); |
4169 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
4170 | } | |
4171 | ||
4172 | ||
1f397f45 SB |
4173 | /* Unlink INSN from the insn chain. |
4174 | ||
4175 | This function knows how to handle sequences. | |
4176 | ||
4177 | This function does not invalidate data flow information associated with | |
4178 | INSN (i.e. does not call df_insn_delete). That makes this function | |
4179 | usable for only disconnecting an insn from the chain, and re-emit it | |
4180 | elsewhere later. | |
4181 | ||
4182 | To later insert INSN elsewhere in the insn chain via add_insn and | |
4183 | similar functions, PREV_INSN and NEXT_INSN must be nullified by | |
4184 | the caller. Nullifying them here breaks many insn chain walks. | |
4185 | ||
4186 | To really delete an insn and related DF information, use delete_insn. */ | |
4187 | ||
89e99eea | 4188 | void |
dc01c3d1 | 4189 | remove_insn (rtx uncast_insn) |
89e99eea | 4190 | { |
dc01c3d1 | 4191 | rtx_insn *insn = as_a <rtx_insn *> (uncast_insn); |
1130d5e3 DM |
4192 | rtx_insn *next = NEXT_INSN (insn); |
4193 | rtx_insn *prev = PREV_INSN (insn); | |
53c17031 JH |
4194 | basic_block bb; |
4195 | ||
89e99eea DB |
4196 | if (prev) |
4197 | { | |
0f82e5c9 | 4198 | SET_NEXT_INSN (prev) = next; |
4b4bf941 | 4199 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea | 4200 | { |
e6eda746 DM |
4201 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4202 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
89e99eea DB |
4203 | } |
4204 | } | |
89e99eea DB |
4205 | else |
4206 | { | |
614d5bd8 AM |
4207 | struct sequence_stack *seq; |
4208 | ||
4209 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4210 | if (insn == seq->first) | |
89e99eea | 4211 | { |
614d5bd8 | 4212 | seq->first = next; |
89e99eea DB |
4213 | break; |
4214 | } | |
4215 | ||
614d5bd8 | 4216 | gcc_assert (seq); |
89e99eea DB |
4217 | } |
4218 | ||
4219 | if (next) | |
4220 | { | |
0f82e5c9 | 4221 | SET_PREV_INSN (next) = prev; |
4b4bf941 | 4222 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4223 | { |
4224 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4225 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4226 | } | |
89e99eea | 4227 | } |
89e99eea DB |
4228 | else |
4229 | { | |
614d5bd8 AM |
4230 | struct sequence_stack *seq; |
4231 | ||
4232 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4233 | if (insn == seq->last) | |
89e99eea | 4234 | { |
614d5bd8 | 4235 | seq->last = prev; |
89e99eea DB |
4236 | break; |
4237 | } | |
4238 | ||
614d5bd8 | 4239 | gcc_assert (seq); |
89e99eea | 4240 | } |
80eb8028 | 4241 | |
80eb8028 | 4242 | /* Fix up basic block boundaries, if necessary. */ |
4b4bf941 | 4243 | if (!BARRIER_P (insn) |
53c17031 JH |
4244 | && (bb = BLOCK_FOR_INSN (insn))) |
4245 | { | |
a813c111 | 4246 | if (BB_HEAD (bb) == insn) |
53c17031 | 4247 | { |
3bf1e984 RK |
4248 | /* Never ever delete the basic block note without deleting whole |
4249 | basic block. */ | |
5b0264cb | 4250 | gcc_assert (!NOTE_P (insn)); |
1130d5e3 | 4251 | BB_HEAD (bb) = next; |
53c17031 | 4252 | } |
a813c111 | 4253 | if (BB_END (bb) == insn) |
1130d5e3 | 4254 | BB_END (bb) = prev; |
53c17031 | 4255 | } |
89e99eea DB |
4256 | } |
4257 | ||
ee960939 OH |
4258 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
4259 | ||
4260 | void | |
502b8322 | 4261 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 4262 | { |
5b0264cb | 4263 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
4264 | |
4265 | /* Put the register usage information on the CALL. If there is already | |
4266 | some usage information, put ours at the end. */ | |
4267 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
4268 | { | |
4269 | rtx link; | |
4270 | ||
4271 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
4272 | link = XEXP (link, 1)) | |
4273 | ; | |
4274 | ||
4275 | XEXP (link, 1) = call_fusage; | |
4276 | } | |
4277 | else | |
4278 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
4279 | } | |
4280 | ||
23b2ce53 RS |
4281 | /* Delete all insns made since FROM. |
4282 | FROM becomes the new last instruction. */ | |
4283 | ||
4284 | void | |
fee3e72c | 4285 | delete_insns_since (rtx_insn *from) |
23b2ce53 RS |
4286 | { |
4287 | if (from == 0) | |
5936d944 | 4288 | set_first_insn (0); |
23b2ce53 | 4289 | else |
0f82e5c9 | 4290 | SET_NEXT_INSN (from) = 0; |
5936d944 | 4291 | set_last_insn (from); |
23b2ce53 RS |
4292 | } |
4293 | ||
5dab5552 MS |
4294 | /* This function is deprecated, please use sequences instead. |
4295 | ||
4296 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
4297 | The insns to be moved are those between FROM and TO. |
4298 | They are moved to a new position after the insn AFTER. | |
4299 | AFTER must not be FROM or TO or any insn in between. | |
4300 | ||
4301 | This function does not know about SEQUENCEs and hence should not be | |
4302 | called after delay-slot filling has been done. */ | |
4303 | ||
4304 | void | |
fee3e72c | 4305 | reorder_insns_nobb (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
23b2ce53 | 4306 | { |
b2b29377 MM |
4307 | if (flag_checking) |
4308 | { | |
4309 | for (rtx_insn *x = from; x != to; x = NEXT_INSN (x)) | |
4310 | gcc_assert (after != x); | |
4311 | gcc_assert (after != to); | |
4312 | } | |
4f8344eb | 4313 | |
23b2ce53 RS |
4314 | /* Splice this bunch out of where it is now. */ |
4315 | if (PREV_INSN (from)) | |
0f82e5c9 | 4316 | SET_NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); |
23b2ce53 | 4317 | if (NEXT_INSN (to)) |
0f82e5c9 | 4318 | SET_PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); |
5936d944 JH |
4319 | if (get_last_insn () == to) |
4320 | set_last_insn (PREV_INSN (from)); | |
4321 | if (get_insns () == from) | |
4322 | set_first_insn (NEXT_INSN (to)); | |
23b2ce53 RS |
4323 | |
4324 | /* Make the new neighbors point to it and it to them. */ | |
4325 | if (NEXT_INSN (after)) | |
0f82e5c9 | 4326 | SET_PREV_INSN (NEXT_INSN (after)) = to; |
23b2ce53 | 4327 | |
0f82e5c9 DM |
4328 | SET_NEXT_INSN (to) = NEXT_INSN (after); |
4329 | SET_PREV_INSN (from) = after; | |
4330 | SET_NEXT_INSN (after) = from; | |
c3284718 | 4331 | if (after == get_last_insn ()) |
5936d944 | 4332 | set_last_insn (to); |
23b2ce53 RS |
4333 | } |
4334 | ||
3c030e88 JH |
4335 | /* Same as function above, but take care to update BB boundaries. */ |
4336 | void | |
ac9d2d2c | 4337 | reorder_insns (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
3c030e88 | 4338 | { |
ac9d2d2c | 4339 | rtx_insn *prev = PREV_INSN (from); |
3c030e88 JH |
4340 | basic_block bb, bb2; |
4341 | ||
4342 | reorder_insns_nobb (from, to, after); | |
4343 | ||
4b4bf941 | 4344 | if (!BARRIER_P (after) |
3c030e88 JH |
4345 | && (bb = BLOCK_FOR_INSN (after))) |
4346 | { | |
b2908ba6 | 4347 | rtx_insn *x; |
6fb5fa3c | 4348 | df_set_bb_dirty (bb); |
68252e27 | 4349 | |
4b4bf941 | 4350 | if (!BARRIER_P (from) |
3c030e88 JH |
4351 | && (bb2 = BLOCK_FOR_INSN (from))) |
4352 | { | |
a813c111 | 4353 | if (BB_END (bb2) == to) |
1130d5e3 | 4354 | BB_END (bb2) = prev; |
6fb5fa3c | 4355 | df_set_bb_dirty (bb2); |
3c030e88 JH |
4356 | } |
4357 | ||
a813c111 | 4358 | if (BB_END (bb) == after) |
1130d5e3 | 4359 | BB_END (bb) = to; |
3c030e88 JH |
4360 | |
4361 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 4362 | if (!BARRIER_P (x)) |
63642d5a | 4363 | df_insn_change_bb (x, bb); |
3c030e88 JH |
4364 | } |
4365 | } | |
4366 | ||
23b2ce53 | 4367 | \f |
2f937369 DM |
4368 | /* Emit insn(s) of given code and pattern |
4369 | at a specified place within the doubly-linked list. | |
23b2ce53 | 4370 | |
2f937369 DM |
4371 | All of the emit_foo global entry points accept an object |
4372 | X which is either an insn list or a PATTERN of a single | |
4373 | instruction. | |
23b2ce53 | 4374 | |
2f937369 DM |
4375 | There are thus a few canonical ways to generate code and |
4376 | emit it at a specific place in the instruction stream. For | |
4377 | example, consider the instruction named SPOT and the fact that | |
4378 | we would like to emit some instructions before SPOT. We might | |
4379 | do it like this: | |
23b2ce53 | 4380 | |
2f937369 DM |
4381 | start_sequence (); |
4382 | ... emit the new instructions ... | |
4383 | insns_head = get_insns (); | |
4384 | end_sequence (); | |
23b2ce53 | 4385 | |
2f937369 | 4386 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4387 | |
2f937369 DM |
4388 | It used to be common to generate SEQUENCE rtl instead, but that |
4389 | is a relic of the past which no longer occurs. The reason is that | |
4390 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4391 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4392 | |
cd459bf8 | 4393 | static rtx_insn * |
5f02387d | 4394 | emit_pattern_before_noloc (rtx x, rtx before, rtx last, basic_block bb, |
167b9fae | 4395 | rtx_insn *(*make_raw) (rtx)) |
23b2ce53 | 4396 | { |
167b9fae | 4397 | rtx_insn *insn; |
23b2ce53 | 4398 | |
5b0264cb | 4399 | gcc_assert (before); |
2f937369 DM |
4400 | |
4401 | if (x == NULL_RTX) | |
cd459bf8 | 4402 | return safe_as_a <rtx_insn *> (last); |
2f937369 DM |
4403 | |
4404 | switch (GET_CODE (x)) | |
23b2ce53 | 4405 | { |
b5b8b0ac | 4406 | case DEBUG_INSN: |
2f937369 DM |
4407 | case INSN: |
4408 | case JUMP_INSN: | |
4409 | case CALL_INSN: | |
4410 | case CODE_LABEL: | |
4411 | case BARRIER: | |
4412 | case NOTE: | |
167b9fae | 4413 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
4414 | while (insn) |
4415 | { | |
167b9fae | 4416 | rtx_insn *next = NEXT_INSN (insn); |
6fb5fa3c | 4417 | add_insn_before (insn, before, bb); |
2f937369 DM |
4418 | last = insn; |
4419 | insn = next; | |
4420 | } | |
4421 | break; | |
4422 | ||
4423 | #ifdef ENABLE_RTL_CHECKING | |
4424 | case SEQUENCE: | |
5b0264cb | 4425 | gcc_unreachable (); |
2f937369 DM |
4426 | break; |
4427 | #endif | |
4428 | ||
4429 | default: | |
5f02387d | 4430 | last = (*make_raw) (x); |
6fb5fa3c | 4431 | add_insn_before (last, before, bb); |
2f937369 | 4432 | break; |
23b2ce53 RS |
4433 | } |
4434 | ||
cd459bf8 | 4435 | return safe_as_a <rtx_insn *> (last); |
23b2ce53 RS |
4436 | } |
4437 | ||
5f02387d NF |
4438 | /* Make X be output before the instruction BEFORE. */ |
4439 | ||
cd459bf8 | 4440 | rtx_insn * |
596f2b17 | 4441 | emit_insn_before_noloc (rtx x, rtx_insn *before, basic_block bb) |
5f02387d NF |
4442 | { |
4443 | return emit_pattern_before_noloc (x, before, before, bb, make_insn_raw); | |
4444 | } | |
4445 | ||
2f937369 | 4446 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4447 | and output it before the instruction BEFORE. */ |
4448 | ||
1476d1bd | 4449 | rtx_jump_insn * |
596f2b17 | 4450 | emit_jump_insn_before_noloc (rtx x, rtx_insn *before) |
23b2ce53 | 4451 | { |
1476d1bd MM |
4452 | return as_a <rtx_jump_insn *> ( |
4453 | emit_pattern_before_noloc (x, before, NULL_RTX, NULL, | |
4454 | make_jump_insn_raw)); | |
23b2ce53 RS |
4455 | } |
4456 | ||
2f937369 | 4457 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4458 | and output it before the instruction BEFORE. */ |
4459 | ||
cd459bf8 | 4460 | rtx_insn * |
596f2b17 | 4461 | emit_call_insn_before_noloc (rtx x, rtx_insn *before) |
969d70ca | 4462 | { |
5f02387d NF |
4463 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4464 | make_call_insn_raw); | |
969d70ca JH |
4465 | } |
4466 | ||
b5b8b0ac AO |
4467 | /* Make an instruction with body X and code DEBUG_INSN |
4468 | and output it before the instruction BEFORE. */ | |
4469 | ||
cd459bf8 | 4470 | rtx_insn * |
b5b8b0ac AO |
4471 | emit_debug_insn_before_noloc (rtx x, rtx before) |
4472 | { | |
5f02387d NF |
4473 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4474 | make_debug_insn_raw); | |
b5b8b0ac AO |
4475 | } |
4476 | ||
23b2ce53 | 4477 | /* Make an insn of code BARRIER |
e881bb1b | 4478 | and output it before the insn BEFORE. */ |
23b2ce53 | 4479 | |
cd459bf8 | 4480 | rtx_barrier * |
502b8322 | 4481 | emit_barrier_before (rtx before) |
23b2ce53 | 4482 | { |
cd459bf8 | 4483 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4484 | |
4485 | INSN_UID (insn) = cur_insn_uid++; | |
4486 | ||
6fb5fa3c | 4487 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4488 | return insn; |
4489 | } | |
4490 | ||
e881bb1b RH |
4491 | /* Emit the label LABEL before the insn BEFORE. */ |
4492 | ||
1476d1bd | 4493 | rtx_code_label * |
596f2b17 | 4494 | emit_label_before (rtx label, rtx_insn *before) |
e881bb1b | 4495 | { |
468660d3 SB |
4496 | gcc_checking_assert (INSN_UID (label) == 0); |
4497 | INSN_UID (label) = cur_insn_uid++; | |
4498 | add_insn_before (label, before, NULL); | |
1476d1bd | 4499 | return as_a <rtx_code_label *> (label); |
e881bb1b | 4500 | } |
23b2ce53 | 4501 | \f |
2f937369 DM |
4502 | /* Helper for emit_insn_after, handles lists of instructions |
4503 | efficiently. */ | |
23b2ce53 | 4504 | |
e6eda746 DM |
4505 | static rtx_insn * |
4506 | emit_insn_after_1 (rtx_insn *first, rtx uncast_after, basic_block bb) | |
23b2ce53 | 4507 | { |
e6eda746 | 4508 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
1130d5e3 DM |
4509 | rtx_insn *last; |
4510 | rtx_insn *after_after; | |
6fb5fa3c DB |
4511 | if (!bb && !BARRIER_P (after)) |
4512 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4513 | |
6fb5fa3c | 4514 | if (bb) |
23b2ce53 | 4515 | { |
6fb5fa3c | 4516 | df_set_bb_dirty (bb); |
2f937369 | 4517 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4518 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4519 | { |
4520 | set_block_for_insn (last, bb); | |
4521 | df_insn_rescan (last); | |
4522 | } | |
4b4bf941 | 4523 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4524 | { |
4525 | set_block_for_insn (last, bb); | |
4526 | df_insn_rescan (last); | |
4527 | } | |
a813c111 | 4528 | if (BB_END (bb) == after) |
1130d5e3 | 4529 | BB_END (bb) = last; |
23b2ce53 RS |
4530 | } |
4531 | else | |
2f937369 DM |
4532 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4533 | continue; | |
4534 | ||
4535 | after_after = NEXT_INSN (after); | |
4536 | ||
0f82e5c9 DM |
4537 | SET_NEXT_INSN (after) = first; |
4538 | SET_PREV_INSN (first) = after; | |
4539 | SET_NEXT_INSN (last) = after_after; | |
2f937369 | 4540 | if (after_after) |
0f82e5c9 | 4541 | SET_PREV_INSN (after_after) = last; |
2f937369 | 4542 | |
c3284718 | 4543 | if (after == get_last_insn ()) |
5936d944 | 4544 | set_last_insn (last); |
e855c69d | 4545 | |
2f937369 DM |
4546 | return last; |
4547 | } | |
4548 | ||
cd459bf8 | 4549 | static rtx_insn * |
e6eda746 | 4550 | emit_pattern_after_noloc (rtx x, rtx uncast_after, basic_block bb, |
167b9fae | 4551 | rtx_insn *(*make_raw)(rtx)) |
2f937369 | 4552 | { |
e6eda746 DM |
4553 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
4554 | rtx_insn *last = after; | |
2f937369 | 4555 | |
5b0264cb | 4556 | gcc_assert (after); |
2f937369 DM |
4557 | |
4558 | if (x == NULL_RTX) | |
e6eda746 | 4559 | return last; |
2f937369 DM |
4560 | |
4561 | switch (GET_CODE (x)) | |
23b2ce53 | 4562 | { |
b5b8b0ac | 4563 | case DEBUG_INSN: |
2f937369 DM |
4564 | case INSN: |
4565 | case JUMP_INSN: | |
4566 | case CALL_INSN: | |
4567 | case CODE_LABEL: | |
4568 | case BARRIER: | |
4569 | case NOTE: | |
1130d5e3 | 4570 | last = emit_insn_after_1 (as_a <rtx_insn *> (x), after, bb); |
2f937369 DM |
4571 | break; |
4572 | ||
4573 | #ifdef ENABLE_RTL_CHECKING | |
4574 | case SEQUENCE: | |
5b0264cb | 4575 | gcc_unreachable (); |
2f937369 DM |
4576 | break; |
4577 | #endif | |
4578 | ||
4579 | default: | |
5f02387d | 4580 | last = (*make_raw) (x); |
6fb5fa3c | 4581 | add_insn_after (last, after, bb); |
2f937369 | 4582 | break; |
23b2ce53 RS |
4583 | } |
4584 | ||
e6eda746 | 4585 | return last; |
23b2ce53 RS |
4586 | } |
4587 | ||
5f02387d NF |
4588 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4589 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
4590 | ||
cd459bf8 | 4591 | rtx_insn * |
5f02387d NF |
4592 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
4593 | { | |
4594 | return emit_pattern_after_noloc (x, after, bb, make_insn_raw); | |
4595 | } | |
4596 | ||
255680cf | 4597 | |
2f937369 | 4598 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4599 | and output it after the insn AFTER. */ |
4600 | ||
1476d1bd | 4601 | rtx_jump_insn * |
a7102479 | 4602 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4603 | { |
1476d1bd MM |
4604 | return as_a <rtx_jump_insn *> ( |
4605 | emit_pattern_after_noloc (x, after, NULL, make_jump_insn_raw)); | |
2f937369 DM |
4606 | } |
4607 | ||
4608 | /* Make an instruction with body X and code CALL_INSN | |
4609 | and output it after the instruction AFTER. */ | |
4610 | ||
cd459bf8 | 4611 | rtx_insn * |
a7102479 | 4612 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 | 4613 | { |
5f02387d | 4614 | return emit_pattern_after_noloc (x, after, NULL, make_call_insn_raw); |
23b2ce53 RS |
4615 | } |
4616 | ||
b5b8b0ac AO |
4617 | /* Make an instruction with body X and code CALL_INSN |
4618 | and output it after the instruction AFTER. */ | |
4619 | ||
cd459bf8 | 4620 | rtx_insn * |
b5b8b0ac AO |
4621 | emit_debug_insn_after_noloc (rtx x, rtx after) |
4622 | { | |
5f02387d | 4623 | return emit_pattern_after_noloc (x, after, NULL, make_debug_insn_raw); |
b5b8b0ac AO |
4624 | } |
4625 | ||
23b2ce53 RS |
4626 | /* Make an insn of code BARRIER |
4627 | and output it after the insn AFTER. */ | |
4628 | ||
cd459bf8 | 4629 | rtx_barrier * |
502b8322 | 4630 | emit_barrier_after (rtx after) |
23b2ce53 | 4631 | { |
cd459bf8 | 4632 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4633 | |
4634 | INSN_UID (insn) = cur_insn_uid++; | |
4635 | ||
6fb5fa3c | 4636 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4637 | return insn; |
4638 | } | |
4639 | ||
4640 | /* Emit the label LABEL after the insn AFTER. */ | |
4641 | ||
cd459bf8 | 4642 | rtx_insn * |
596f2b17 | 4643 | emit_label_after (rtx label, rtx_insn *after) |
23b2ce53 | 4644 | { |
468660d3 SB |
4645 | gcc_checking_assert (INSN_UID (label) == 0); |
4646 | INSN_UID (label) = cur_insn_uid++; | |
4647 | add_insn_after (label, after, NULL); | |
cd459bf8 | 4648 | return as_a <rtx_insn *> (label); |
23b2ce53 | 4649 | } |
96fba521 SB |
4650 | \f |
4651 | /* Notes require a bit of special handling: Some notes need to have their | |
4652 | BLOCK_FOR_INSN set, others should never have it set, and some should | |
4653 | have it set or clear depending on the context. */ | |
4654 | ||
4655 | /* Return true iff a note of kind SUBTYPE should be emitted with routines | |
4656 | that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the | |
4657 | caller is asked to emit a note before BB_HEAD, or after BB_END. */ | |
4658 | ||
4659 | static bool | |
4660 | note_outside_basic_block_p (enum insn_note subtype, bool on_bb_boundary_p) | |
4661 | { | |
4662 | switch (subtype) | |
4663 | { | |
4664 | /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */ | |
4665 | case NOTE_INSN_SWITCH_TEXT_SECTIONS: | |
4666 | return true; | |
4667 | ||
4668 | /* Notes for var tracking and EH region markers can appear between or | |
4669 | inside basic blocks. If the caller is emitting on the basic block | |
4670 | boundary, do not set BLOCK_FOR_INSN on the new note. */ | |
4671 | case NOTE_INSN_VAR_LOCATION: | |
4672 | case NOTE_INSN_CALL_ARG_LOCATION: | |
4673 | case NOTE_INSN_EH_REGION_BEG: | |
4674 | case NOTE_INSN_EH_REGION_END: | |
4675 | return on_bb_boundary_p; | |
4676 | ||
4677 | /* Otherwise, BLOCK_FOR_INSN must be set. */ | |
4678 | default: | |
4679 | return false; | |
4680 | } | |
4681 | } | |
23b2ce53 RS |
4682 | |
4683 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4684 | ||
66e8df53 | 4685 | rtx_note * |
589e43f9 | 4686 | emit_note_after (enum insn_note subtype, rtx_insn *after) |
23b2ce53 | 4687 | { |
66e8df53 | 4688 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4689 | basic_block bb = BARRIER_P (after) ? NULL : BLOCK_FOR_INSN (after); |
4690 | bool on_bb_boundary_p = (bb != NULL && BB_END (bb) == after); | |
4691 | ||
4692 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4693 | add_insn_after_nobb (note, after); | |
4694 | else | |
4695 | add_insn_after (note, after, bb); | |
4696 | return note; | |
4697 | } | |
4698 | ||
4699 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ | |
4700 | ||
66e8df53 | 4701 | rtx_note * |
89b6250d | 4702 | emit_note_before (enum insn_note subtype, rtx_insn *before) |
96fba521 | 4703 | { |
66e8df53 | 4704 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4705 | basic_block bb = BARRIER_P (before) ? NULL : BLOCK_FOR_INSN (before); |
4706 | bool on_bb_boundary_p = (bb != NULL && BB_HEAD (bb) == before); | |
4707 | ||
4708 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4709 | add_insn_before_nobb (note, before); | |
4710 | else | |
4711 | add_insn_before (note, before, bb); | |
23b2ce53 RS |
4712 | return note; |
4713 | } | |
23b2ce53 | 4714 | \f |
e8110d6f NF |
4715 | /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC. |
4716 | MAKE_RAW indicates how to turn PATTERN into a real insn. */ | |
4717 | ||
cd459bf8 | 4718 | static rtx_insn * |
dc01c3d1 | 4719 | emit_pattern_after_setloc (rtx pattern, rtx uncast_after, int loc, |
167b9fae | 4720 | rtx_insn *(*make_raw) (rtx)) |
0d682900 | 4721 | { |
dc01c3d1 | 4722 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
e67d1102 | 4723 | rtx_insn *last = emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
0d682900 | 4724 | |
a7102479 | 4725 | if (pattern == NULL_RTX || !loc) |
e67d1102 | 4726 | return last; |
dd3adcf8 | 4727 | |
2f937369 DM |
4728 | after = NEXT_INSN (after); |
4729 | while (1) | |
4730 | { | |
20d4397a EB |
4731 | if (active_insn_p (after) |
4732 | && !JUMP_TABLE_DATA_P (after) /* FIXME */ | |
4733 | && !INSN_LOCATION (after)) | |
5368224f | 4734 | INSN_LOCATION (after) = loc; |
2f937369 DM |
4735 | if (after == last) |
4736 | break; | |
4737 | after = NEXT_INSN (after); | |
4738 | } | |
e67d1102 | 4739 | return last; |
0d682900 JH |
4740 | } |
4741 | ||
e8110d6f NF |
4742 | /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN |
4743 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after | |
4744 | any DEBUG_INSNs. */ | |
4745 | ||
cd459bf8 | 4746 | static rtx_insn * |
dc01c3d1 | 4747 | emit_pattern_after (rtx pattern, rtx uncast_after, bool skip_debug_insns, |
167b9fae | 4748 | rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4749 | { |
dc01c3d1 DM |
4750 | rtx_insn *after = safe_as_a <rtx_insn *> (uncast_after); |
4751 | rtx_insn *prev = after; | |
b5b8b0ac | 4752 | |
e8110d6f NF |
4753 | if (skip_debug_insns) |
4754 | while (DEBUG_INSN_P (prev)) | |
4755 | prev = PREV_INSN (prev); | |
b5b8b0ac AO |
4756 | |
4757 | if (INSN_P (prev)) | |
5368224f | 4758 | return emit_pattern_after_setloc (pattern, after, INSN_LOCATION (prev), |
e8110d6f | 4759 | make_raw); |
a7102479 | 4760 | else |
e8110d6f | 4761 | return emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
a7102479 JH |
4762 | } |
4763 | ||
5368224f | 4764 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4765 | rtx_insn * |
e8110d6f | 4766 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4767 | { |
e8110d6f NF |
4768 | return emit_pattern_after_setloc (pattern, after, loc, make_insn_raw); |
4769 | } | |
2f937369 | 4770 | |
5368224f | 4771 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4772 | rtx_insn * |
e8110d6f NF |
4773 | emit_insn_after (rtx pattern, rtx after) |
4774 | { | |
4775 | return emit_pattern_after (pattern, after, true, make_insn_raw); | |
4776 | } | |
dd3adcf8 | 4777 | |
5368224f | 4778 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4779 | rtx_jump_insn * |
e8110d6f NF |
4780 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
4781 | { | |
1476d1bd MM |
4782 | return as_a <rtx_jump_insn *> ( |
4783 | emit_pattern_after_setloc (pattern, after, loc, make_jump_insn_raw)); | |
0d682900 JH |
4784 | } |
4785 | ||
5368224f | 4786 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
1476d1bd | 4787 | rtx_jump_insn * |
a7102479 JH |
4788 | emit_jump_insn_after (rtx pattern, rtx after) |
4789 | { | |
1476d1bd MM |
4790 | return as_a <rtx_jump_insn *> ( |
4791 | emit_pattern_after (pattern, after, true, make_jump_insn_raw)); | |
a7102479 JH |
4792 | } |
4793 | ||
5368224f | 4794 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4795 | rtx_insn * |
502b8322 | 4796 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4797 | { |
e8110d6f | 4798 | return emit_pattern_after_setloc (pattern, after, loc, make_call_insn_raw); |
0d682900 JH |
4799 | } |
4800 | ||
5368224f | 4801 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4802 | rtx_insn * |
a7102479 JH |
4803 | emit_call_insn_after (rtx pattern, rtx after) |
4804 | { | |
e8110d6f | 4805 | return emit_pattern_after (pattern, after, true, make_call_insn_raw); |
a7102479 JH |
4806 | } |
4807 | ||
5368224f | 4808 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4809 | rtx_insn * |
b5b8b0ac AO |
4810 | emit_debug_insn_after_setloc (rtx pattern, rtx after, int loc) |
4811 | { | |
e8110d6f | 4812 | return emit_pattern_after_setloc (pattern, after, loc, make_debug_insn_raw); |
b5b8b0ac AO |
4813 | } |
4814 | ||
5368224f | 4815 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4816 | rtx_insn * |
b5b8b0ac AO |
4817 | emit_debug_insn_after (rtx pattern, rtx after) |
4818 | { | |
e8110d6f | 4819 | return emit_pattern_after (pattern, after, false, make_debug_insn_raw); |
b5b8b0ac AO |
4820 | } |
4821 | ||
e8110d6f NF |
4822 | /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC. |
4823 | MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP | |
4824 | indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN, | |
4825 | CALL_INSN, etc. */ | |
4826 | ||
cd459bf8 | 4827 | static rtx_insn * |
dc01c3d1 | 4828 | emit_pattern_before_setloc (rtx pattern, rtx uncast_before, int loc, bool insnp, |
167b9fae | 4829 | rtx_insn *(*make_raw) (rtx)) |
0d682900 | 4830 | { |
dc01c3d1 DM |
4831 | rtx_insn *before = as_a <rtx_insn *> (uncast_before); |
4832 | rtx_insn *first = PREV_INSN (before); | |
4833 | rtx_insn *last = emit_pattern_before_noloc (pattern, before, | |
4834 | insnp ? before : NULL_RTX, | |
4835 | NULL, make_raw); | |
a7102479 JH |
4836 | |
4837 | if (pattern == NULL_RTX || !loc) | |
dc01c3d1 | 4838 | return last; |
a7102479 | 4839 | |
26cb3993 JH |
4840 | if (!first) |
4841 | first = get_insns (); | |
4842 | else | |
4843 | first = NEXT_INSN (first); | |
a7102479 JH |
4844 | while (1) |
4845 | { | |
20d4397a EB |
4846 | if (active_insn_p (first) |
4847 | && !JUMP_TABLE_DATA_P (first) /* FIXME */ | |
4848 | && !INSN_LOCATION (first)) | |
5368224f | 4849 | INSN_LOCATION (first) = loc; |
a7102479 JH |
4850 | if (first == last) |
4851 | break; | |
4852 | first = NEXT_INSN (first); | |
4853 | } | |
dc01c3d1 | 4854 | return last; |
a7102479 JH |
4855 | } |
4856 | ||
e8110d6f NF |
4857 | /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN |
4858 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert | |
4859 | before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an | |
4860 | INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */ | |
4861 | ||
cd459bf8 | 4862 | static rtx_insn * |
dc01c3d1 | 4863 | emit_pattern_before (rtx pattern, rtx uncast_before, bool skip_debug_insns, |
167b9fae | 4864 | bool insnp, rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4865 | { |
dc01c3d1 DM |
4866 | rtx_insn *before = safe_as_a <rtx_insn *> (uncast_before); |
4867 | rtx_insn *next = before; | |
b5b8b0ac | 4868 | |
e8110d6f NF |
4869 | if (skip_debug_insns) |
4870 | while (DEBUG_INSN_P (next)) | |
4871 | next = PREV_INSN (next); | |
b5b8b0ac AO |
4872 | |
4873 | if (INSN_P (next)) | |
5368224f | 4874 | return emit_pattern_before_setloc (pattern, before, INSN_LOCATION (next), |
e8110d6f | 4875 | insnp, make_raw); |
a7102479 | 4876 | else |
e8110d6f | 4877 | return emit_pattern_before_noloc (pattern, before, |
9b2ea071 | 4878 | insnp ? before : NULL_RTX, |
e8110d6f | 4879 | NULL, make_raw); |
a7102479 JH |
4880 | } |
4881 | ||
5368224f | 4882 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4883 | rtx_insn * |
596f2b17 | 4884 | emit_insn_before_setloc (rtx pattern, rtx_insn *before, int loc) |
a7102479 | 4885 | { |
e8110d6f NF |
4886 | return emit_pattern_before_setloc (pattern, before, loc, true, |
4887 | make_insn_raw); | |
4888 | } | |
a7102479 | 4889 | |
5368224f | 4890 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
cd459bf8 | 4891 | rtx_insn * |
e8110d6f NF |
4892 | emit_insn_before (rtx pattern, rtx before) |
4893 | { | |
4894 | return emit_pattern_before (pattern, before, true, true, make_insn_raw); | |
4895 | } | |
a7102479 | 4896 | |
5368224f | 4897 | /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4898 | rtx_jump_insn * |
596f2b17 | 4899 | emit_jump_insn_before_setloc (rtx pattern, rtx_insn *before, int loc) |
e8110d6f | 4900 | { |
1476d1bd MM |
4901 | return as_a <rtx_jump_insn *> ( |
4902 | emit_pattern_before_setloc (pattern, before, loc, false, | |
4903 | make_jump_insn_raw)); | |
a7102479 JH |
4904 | } |
4905 | ||
5368224f | 4906 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
1476d1bd | 4907 | rtx_jump_insn * |
a7102479 JH |
4908 | emit_jump_insn_before (rtx pattern, rtx before) |
4909 | { | |
1476d1bd MM |
4910 | return as_a <rtx_jump_insn *> ( |
4911 | emit_pattern_before (pattern, before, true, false, | |
4912 | make_jump_insn_raw)); | |
a7102479 JH |
4913 | } |
4914 | ||
5368224f | 4915 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4916 | rtx_insn * |
596f2b17 | 4917 | emit_call_insn_before_setloc (rtx pattern, rtx_insn *before, int loc) |
a7102479 | 4918 | { |
e8110d6f NF |
4919 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4920 | make_call_insn_raw); | |
0d682900 | 4921 | } |
a7102479 | 4922 | |
e8110d6f | 4923 | /* Like emit_call_insn_before_noloc, |
5368224f | 4924 | but set insn_location according to BEFORE. */ |
cd459bf8 | 4925 | rtx_insn * |
596f2b17 | 4926 | emit_call_insn_before (rtx pattern, rtx_insn *before) |
a7102479 | 4927 | { |
e8110d6f NF |
4928 | return emit_pattern_before (pattern, before, true, false, |
4929 | make_call_insn_raw); | |
a7102479 | 4930 | } |
b5b8b0ac | 4931 | |
5368224f | 4932 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4933 | rtx_insn * |
b5b8b0ac AO |
4934 | emit_debug_insn_before_setloc (rtx pattern, rtx before, int loc) |
4935 | { | |
e8110d6f NF |
4936 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4937 | make_debug_insn_raw); | |
b5b8b0ac AO |
4938 | } |
4939 | ||
e8110d6f | 4940 | /* Like emit_debug_insn_before_noloc, |
5368224f | 4941 | but set insn_location according to BEFORE. */ |
cd459bf8 | 4942 | rtx_insn * |
3a6216b0 | 4943 | emit_debug_insn_before (rtx pattern, rtx_insn *before) |
b5b8b0ac | 4944 | { |
e8110d6f NF |
4945 | return emit_pattern_before (pattern, before, false, false, |
4946 | make_debug_insn_raw); | |
b5b8b0ac | 4947 | } |
0d682900 | 4948 | \f |
2f937369 DM |
4949 | /* Take X and emit it at the end of the doubly-linked |
4950 | INSN list. | |
23b2ce53 RS |
4951 | |
4952 | Returns the last insn emitted. */ | |
4953 | ||
cd459bf8 | 4954 | rtx_insn * |
502b8322 | 4955 | emit_insn (rtx x) |
23b2ce53 | 4956 | { |
cd459bf8 DM |
4957 | rtx_insn *last = get_last_insn (); |
4958 | rtx_insn *insn; | |
23b2ce53 | 4959 | |
2f937369 DM |
4960 | if (x == NULL_RTX) |
4961 | return last; | |
23b2ce53 | 4962 | |
2f937369 DM |
4963 | switch (GET_CODE (x)) |
4964 | { | |
b5b8b0ac | 4965 | case DEBUG_INSN: |
2f937369 DM |
4966 | case INSN: |
4967 | case JUMP_INSN: | |
4968 | case CALL_INSN: | |
4969 | case CODE_LABEL: | |
4970 | case BARRIER: | |
4971 | case NOTE: | |
cd459bf8 | 4972 | insn = as_a <rtx_insn *> (x); |
2f937369 | 4973 | while (insn) |
23b2ce53 | 4974 | { |
cd459bf8 | 4975 | rtx_insn *next = NEXT_INSN (insn); |
23b2ce53 | 4976 | add_insn (insn); |
2f937369 DM |
4977 | last = insn; |
4978 | insn = next; | |
23b2ce53 | 4979 | } |
2f937369 | 4980 | break; |
23b2ce53 | 4981 | |
2f937369 | 4982 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 4983 | case JUMP_TABLE_DATA: |
2f937369 | 4984 | case SEQUENCE: |
5b0264cb | 4985 | gcc_unreachable (); |
2f937369 DM |
4986 | break; |
4987 | #endif | |
23b2ce53 | 4988 | |
2f937369 DM |
4989 | default: |
4990 | last = make_insn_raw (x); | |
4991 | add_insn (last); | |
4992 | break; | |
23b2ce53 RS |
4993 | } |
4994 | ||
4995 | return last; | |
4996 | } | |
4997 | ||
b5b8b0ac AO |
4998 | /* Make an insn of code DEBUG_INSN with pattern X |
4999 | and add it to the end of the doubly-linked list. */ | |
5000 | ||
cd459bf8 | 5001 | rtx_insn * |
b5b8b0ac AO |
5002 | emit_debug_insn (rtx x) |
5003 | { | |
cd459bf8 DM |
5004 | rtx_insn *last = get_last_insn (); |
5005 | rtx_insn *insn; | |
b5b8b0ac AO |
5006 | |
5007 | if (x == NULL_RTX) | |
5008 | return last; | |
5009 | ||
5010 | switch (GET_CODE (x)) | |
5011 | { | |
5012 | case DEBUG_INSN: | |
5013 | case INSN: | |
5014 | case JUMP_INSN: | |
5015 | case CALL_INSN: | |
5016 | case CODE_LABEL: | |
5017 | case BARRIER: | |
5018 | case NOTE: | |
cd459bf8 | 5019 | insn = as_a <rtx_insn *> (x); |
b5b8b0ac AO |
5020 | while (insn) |
5021 | { | |
cd459bf8 | 5022 | rtx_insn *next = NEXT_INSN (insn); |
b5b8b0ac AO |
5023 | add_insn (insn); |
5024 | last = insn; | |
5025 | insn = next; | |
5026 | } | |
5027 | break; | |
5028 | ||
5029 | #ifdef ENABLE_RTL_CHECKING | |
39718607 | 5030 | case JUMP_TABLE_DATA: |
b5b8b0ac AO |
5031 | case SEQUENCE: |
5032 | gcc_unreachable (); | |
5033 | break; | |
5034 | #endif | |
5035 | ||
5036 | default: | |
5037 | last = make_debug_insn_raw (x); | |
5038 | add_insn (last); | |
5039 | break; | |
5040 | } | |
5041 | ||
5042 | return last; | |
5043 | } | |
5044 | ||
2f937369 DM |
5045 | /* Make an insn of code JUMP_INSN with pattern X |
5046 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5047 | |
cd459bf8 | 5048 | rtx_insn * |
502b8322 | 5049 | emit_jump_insn (rtx x) |
23b2ce53 | 5050 | { |
cd459bf8 DM |
5051 | rtx_insn *last = NULL; |
5052 | rtx_insn *insn; | |
23b2ce53 | 5053 | |
2f937369 | 5054 | switch (GET_CODE (x)) |
23b2ce53 | 5055 | { |
b5b8b0ac | 5056 | case DEBUG_INSN: |
2f937369 DM |
5057 | case INSN: |
5058 | case JUMP_INSN: | |
5059 | case CALL_INSN: | |
5060 | case CODE_LABEL: | |
5061 | case BARRIER: | |
5062 | case NOTE: | |
cd459bf8 | 5063 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
5064 | while (insn) |
5065 | { | |
cd459bf8 | 5066 | rtx_insn *next = NEXT_INSN (insn); |
2f937369 DM |
5067 | add_insn (insn); |
5068 | last = insn; | |
5069 | insn = next; | |
5070 | } | |
5071 | break; | |
e0a5c5eb | 5072 | |
2f937369 | 5073 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 5074 | case JUMP_TABLE_DATA: |
2f937369 | 5075 | case SEQUENCE: |
5b0264cb | 5076 | gcc_unreachable (); |
2f937369 DM |
5077 | break; |
5078 | #endif | |
e0a5c5eb | 5079 | |
2f937369 DM |
5080 | default: |
5081 | last = make_jump_insn_raw (x); | |
5082 | add_insn (last); | |
5083 | break; | |
3c030e88 | 5084 | } |
e0a5c5eb RS |
5085 | |
5086 | return last; | |
5087 | } | |
5088 | ||
2f937369 | 5089 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
5090 | and add it to the end of the doubly-linked list. */ |
5091 | ||
cd459bf8 | 5092 | rtx_insn * |
502b8322 | 5093 | emit_call_insn (rtx x) |
23b2ce53 | 5094 | { |
cd459bf8 | 5095 | rtx_insn *insn; |
2f937369 DM |
5096 | |
5097 | switch (GET_CODE (x)) | |
23b2ce53 | 5098 | { |
b5b8b0ac | 5099 | case DEBUG_INSN: |
2f937369 DM |
5100 | case INSN: |
5101 | case JUMP_INSN: | |
5102 | case CALL_INSN: | |
5103 | case CODE_LABEL: | |
5104 | case BARRIER: | |
5105 | case NOTE: | |
5106 | insn = emit_insn (x); | |
5107 | break; | |
23b2ce53 | 5108 | |
2f937369 DM |
5109 | #ifdef ENABLE_RTL_CHECKING |
5110 | case SEQUENCE: | |
39718607 | 5111 | case JUMP_TABLE_DATA: |
5b0264cb | 5112 | gcc_unreachable (); |
2f937369 DM |
5113 | break; |
5114 | #endif | |
23b2ce53 | 5115 | |
2f937369 DM |
5116 | default: |
5117 | insn = make_call_insn_raw (x); | |
23b2ce53 | 5118 | add_insn (insn); |
2f937369 | 5119 | break; |
23b2ce53 | 5120 | } |
2f937369 DM |
5121 | |
5122 | return insn; | |
23b2ce53 RS |
5123 | } |
5124 | ||
5125 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
5126 | ||
1476d1bd MM |
5127 | rtx_code_label * |
5128 | emit_label (rtx uncast_label) | |
23b2ce53 | 5129 | { |
1476d1bd MM |
5130 | rtx_code_label *label = as_a <rtx_code_label *> (uncast_label); |
5131 | ||
468660d3 SB |
5132 | gcc_checking_assert (INSN_UID (label) == 0); |
5133 | INSN_UID (label) = cur_insn_uid++; | |
1476d1bd MM |
5134 | add_insn (label); |
5135 | return label; | |
23b2ce53 RS |
5136 | } |
5137 | ||
39718607 SB |
5138 | /* Make an insn of code JUMP_TABLE_DATA |
5139 | and add it to the end of the doubly-linked list. */ | |
5140 | ||
4598afdd | 5141 | rtx_jump_table_data * |
39718607 SB |
5142 | emit_jump_table_data (rtx table) |
5143 | { | |
4598afdd DM |
5144 | rtx_jump_table_data *jump_table_data = |
5145 | as_a <rtx_jump_table_data *> (rtx_alloc (JUMP_TABLE_DATA)); | |
39718607 SB |
5146 | INSN_UID (jump_table_data) = cur_insn_uid++; |
5147 | PATTERN (jump_table_data) = table; | |
5148 | BLOCK_FOR_INSN (jump_table_data) = NULL; | |
5149 | add_insn (jump_table_data); | |
5150 | return jump_table_data; | |
5151 | } | |
5152 | ||
23b2ce53 RS |
5153 | /* Make an insn of code BARRIER |
5154 | and add it to the end of the doubly-linked list. */ | |
5155 | ||
cd459bf8 | 5156 | rtx_barrier * |
502b8322 | 5157 | emit_barrier (void) |
23b2ce53 | 5158 | { |
cd459bf8 | 5159 | rtx_barrier *barrier = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
5160 | INSN_UID (barrier) = cur_insn_uid++; |
5161 | add_insn (barrier); | |
5162 | return barrier; | |
5163 | } | |
5164 | ||
5f2fc772 | 5165 | /* Emit a copy of note ORIG. */ |
502b8322 | 5166 | |
66e8df53 DM |
5167 | rtx_note * |
5168 | emit_note_copy (rtx_note *orig) | |
5f2fc772 | 5169 | { |
96fba521 | 5170 | enum insn_note kind = (enum insn_note) NOTE_KIND (orig); |
66e8df53 | 5171 | rtx_note *note = make_note_raw (kind); |
5f2fc772 | 5172 | NOTE_DATA (note) = NOTE_DATA (orig); |
5f2fc772 | 5173 | add_insn (note); |
2e040219 | 5174 | return note; |
23b2ce53 RS |
5175 | } |
5176 | ||
2e040219 NS |
5177 | /* Make an insn of code NOTE or type NOTE_NO |
5178 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5179 | |
66e8df53 | 5180 | rtx_note * |
a38e7aa5 | 5181 | emit_note (enum insn_note kind) |
23b2ce53 | 5182 | { |
66e8df53 | 5183 | rtx_note *note = make_note_raw (kind); |
23b2ce53 RS |
5184 | add_insn (note); |
5185 | return note; | |
5186 | } | |
5187 | ||
c41c1387 RS |
5188 | /* Emit a clobber of lvalue X. */ |
5189 | ||
cd459bf8 | 5190 | rtx_insn * |
c41c1387 RS |
5191 | emit_clobber (rtx x) |
5192 | { | |
5193 | /* CONCATs should not appear in the insn stream. */ | |
5194 | if (GET_CODE (x) == CONCAT) | |
5195 | { | |
5196 | emit_clobber (XEXP (x, 0)); | |
5197 | return emit_clobber (XEXP (x, 1)); | |
5198 | } | |
5199 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
5200 | } | |
5201 | ||
5202 | /* Return a sequence of insns to clobber lvalue X. */ | |
5203 | ||
cd459bf8 | 5204 | rtx_insn * |
c41c1387 RS |
5205 | gen_clobber (rtx x) |
5206 | { | |
cd459bf8 | 5207 | rtx_insn *seq; |
c41c1387 RS |
5208 | |
5209 | start_sequence (); | |
5210 | emit_clobber (x); | |
5211 | seq = get_insns (); | |
5212 | end_sequence (); | |
5213 | return seq; | |
5214 | } | |
5215 | ||
5216 | /* Emit a use of rvalue X. */ | |
5217 | ||
cd459bf8 | 5218 | rtx_insn * |
c41c1387 RS |
5219 | emit_use (rtx x) |
5220 | { | |
5221 | /* CONCATs should not appear in the insn stream. */ | |
5222 | if (GET_CODE (x) == CONCAT) | |
5223 | { | |
5224 | emit_use (XEXP (x, 0)); | |
5225 | return emit_use (XEXP (x, 1)); | |
5226 | } | |
5227 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
5228 | } | |
5229 | ||
5230 | /* Return a sequence of insns to use rvalue X. */ | |
5231 | ||
cd459bf8 | 5232 | rtx_insn * |
c41c1387 RS |
5233 | gen_use (rtx x) |
5234 | { | |
cd459bf8 | 5235 | rtx_insn *seq; |
c41c1387 RS |
5236 | |
5237 | start_sequence (); | |
5238 | emit_use (x); | |
5239 | seq = get_insns (); | |
5240 | end_sequence (); | |
5241 | return seq; | |
5242 | } | |
5243 | ||
c8912e53 RS |
5244 | /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction. |
5245 | Return the set in INSN that such notes describe, or NULL if the notes | |
5246 | have no meaning for INSN. */ | |
5247 | ||
5248 | rtx | |
5249 | set_for_reg_notes (rtx insn) | |
5250 | { | |
5251 | rtx pat, reg; | |
5252 | ||
5253 | if (!INSN_P (insn)) | |
5254 | return NULL_RTX; | |
5255 | ||
5256 | pat = PATTERN (insn); | |
5257 | if (GET_CODE (pat) == PARALLEL) | |
5258 | { | |
5259 | /* We do not use single_set because that ignores SETs of unused | |
5260 | registers. REG_EQUAL and REG_EQUIV notes really do require the | |
5261 | PARALLEL to have a single SET. */ | |
5262 | if (multiple_sets (insn)) | |
5263 | return NULL_RTX; | |
5264 | pat = XVECEXP (pat, 0, 0); | |
5265 | } | |
5266 | ||
5267 | if (GET_CODE (pat) != SET) | |
5268 | return NULL_RTX; | |
5269 | ||
5270 | reg = SET_DEST (pat); | |
5271 | ||
5272 | /* Notes apply to the contents of a STRICT_LOW_PART. */ | |
7f7379f6 KV |
5273 | if (GET_CODE (reg) == STRICT_LOW_PART |
5274 | || GET_CODE (reg) == ZERO_EXTRACT) | |
c8912e53 RS |
5275 | reg = XEXP (reg, 0); |
5276 | ||
5277 | /* Check that we have a register. */ | |
5278 | if (!(REG_P (reg) || GET_CODE (reg) == SUBREG)) | |
5279 | return NULL_RTX; | |
5280 | ||
5281 | return pat; | |
5282 | } | |
5283 | ||
87b47c85 | 5284 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a |
30f7a378 | 5285 | note of this type already exists, remove it first. */ |
87b47c85 | 5286 | |
3d238248 | 5287 | rtx |
502b8322 | 5288 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
5289 | { |
5290 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
5291 | ||
52488da1 JW |
5292 | switch (kind) |
5293 | { | |
5294 | case REG_EQUAL: | |
5295 | case REG_EQUIV: | |
8073cbd4 EB |
5296 | /* We need to support the REG_EQUAL on USE trick of find_reloads. */ |
5297 | if (!set_for_reg_notes (insn) && GET_CODE (PATTERN (insn)) != USE) | |
c8912e53 | 5298 | return NULL_RTX; |
52488da1 JW |
5299 | |
5300 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
5301 | It serves no useful purpose and breaks eliminate_regs. */ | |
5302 | if (GET_CODE (datum) == ASM_OPERANDS) | |
5303 | return NULL_RTX; | |
109374e2 RS |
5304 | |
5305 | /* Notes with side effects are dangerous. Even if the side-effect | |
5306 | initially mirrors one in PATTERN (INSN), later optimizations | |
5307 | might alter the way that the final register value is calculated | |
5308 | and so move or alter the side-effect in some way. The note would | |
5309 | then no longer be a valid substitution for SET_SRC. */ | |
5310 | if (side_effects_p (datum)) | |
5311 | return NULL_RTX; | |
52488da1 JW |
5312 | break; |
5313 | ||
5314 | default: | |
5315 | break; | |
5316 | } | |
3d238248 | 5317 | |
c8912e53 RS |
5318 | if (note) |
5319 | XEXP (note, 0) = datum; | |
5320 | else | |
5321 | { | |
5322 | add_reg_note (insn, kind, datum); | |
5323 | note = REG_NOTES (insn); | |
5324 | } | |
6fb5fa3c DB |
5325 | |
5326 | switch (kind) | |
3d238248 | 5327 | { |
6fb5fa3c DB |
5328 | case REG_EQUAL: |
5329 | case REG_EQUIV: | |
b2908ba6 | 5330 | df_notes_rescan (as_a <rtx_insn *> (insn)); |
6fb5fa3c DB |
5331 | break; |
5332 | default: | |
5333 | break; | |
3d238248 | 5334 | } |
87b47c85 | 5335 | |
c8912e53 | 5336 | return note; |
87b47c85 | 5337 | } |
7543f918 JR |
5338 | |
5339 | /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */ | |
5340 | rtx | |
5341 | set_dst_reg_note (rtx insn, enum reg_note kind, rtx datum, rtx dst) | |
5342 | { | |
c8912e53 | 5343 | rtx set = set_for_reg_notes (insn); |
7543f918 JR |
5344 | |
5345 | if (set && SET_DEST (set) == dst) | |
5346 | return set_unique_reg_note (insn, kind, datum); | |
5347 | return NULL_RTX; | |
5348 | } | |
23b2ce53 | 5349 | \f |
9d8895c9 RS |
5350 | /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a |
5351 | following barrier if the instruction needs one and if ALLOW_BARRIER_P | |
5352 | is true. | |
5353 | ||
23b2ce53 RS |
5354 | If X is a label, it is simply added into the insn chain. */ |
5355 | ||
cd459bf8 | 5356 | rtx_insn * |
9d8895c9 | 5357 | emit (rtx x, bool allow_barrier_p) |
23b2ce53 RS |
5358 | { |
5359 | enum rtx_code code = classify_insn (x); | |
5360 | ||
5b0264cb | 5361 | switch (code) |
23b2ce53 | 5362 | { |
5b0264cb NS |
5363 | case CODE_LABEL: |
5364 | return emit_label (x); | |
5365 | case INSN: | |
5366 | return emit_insn (x); | |
5367 | case JUMP_INSN: | |
5368 | { | |
cd459bf8 | 5369 | rtx_insn *insn = emit_jump_insn (x); |
9d8895c9 RS |
5370 | if (allow_barrier_p |
5371 | && (any_uncondjump_p (insn) || GET_CODE (x) == RETURN)) | |
5b0264cb NS |
5372 | return emit_barrier (); |
5373 | return insn; | |
5374 | } | |
5375 | case CALL_INSN: | |
5376 | return emit_call_insn (x); | |
b5b8b0ac AO |
5377 | case DEBUG_INSN: |
5378 | return emit_debug_insn (x); | |
5b0264cb NS |
5379 | default: |
5380 | gcc_unreachable (); | |
23b2ce53 | 5381 | } |
23b2ce53 RS |
5382 | } |
5383 | \f | |
e2500fed | 5384 | /* Space for free sequence stack entries. */ |
1431042e | 5385 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 5386 | |
4dfa0342 RH |
5387 | /* Begin emitting insns to a sequence. If this sequence will contain |
5388 | something that might cause the compiler to pop arguments to function | |
5389 | calls (because those pops have previously been deferred; see | |
5390 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
5391 | before calling this function. That will ensure that the deferred | |
5392 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
5393 | |
5394 | void | |
502b8322 | 5395 | start_sequence (void) |
23b2ce53 RS |
5396 | { |
5397 | struct sequence_stack *tem; | |
5398 | ||
e2500fed GK |
5399 | if (free_sequence_stack != NULL) |
5400 | { | |
5401 | tem = free_sequence_stack; | |
5402 | free_sequence_stack = tem->next; | |
5403 | } | |
5404 | else | |
766090c2 | 5405 | tem = ggc_alloc<sequence_stack> (); |
23b2ce53 | 5406 | |
614d5bd8 | 5407 | tem->next = get_current_sequence ()->next; |
5936d944 JH |
5408 | tem->first = get_insns (); |
5409 | tem->last = get_last_insn (); | |
614d5bd8 | 5410 | get_current_sequence ()->next = tem; |
23b2ce53 | 5411 | |
5936d944 JH |
5412 | set_first_insn (0); |
5413 | set_last_insn (0); | |
23b2ce53 RS |
5414 | } |
5415 | ||
5c7a310f MM |
5416 | /* Set up the insn chain starting with FIRST as the current sequence, |
5417 | saving the previously current one. See the documentation for | |
5418 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5419 | |
5420 | void | |
fee3e72c | 5421 | push_to_sequence (rtx_insn *first) |
23b2ce53 | 5422 | { |
fee3e72c | 5423 | rtx_insn *last; |
23b2ce53 RS |
5424 | |
5425 | start_sequence (); | |
5426 | ||
e84a58ff EB |
5427 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)) |
5428 | ; | |
23b2ce53 | 5429 | |
5936d944 JH |
5430 | set_first_insn (first); |
5431 | set_last_insn (last); | |
23b2ce53 RS |
5432 | } |
5433 | ||
bb27eeda SE |
5434 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5435 | looping through the list. */ | |
5436 | ||
5437 | void | |
fee3e72c | 5438 | push_to_sequence2 (rtx_insn *first, rtx_insn *last) |
bb27eeda SE |
5439 | { |
5440 | start_sequence (); | |
5441 | ||
5936d944 JH |
5442 | set_first_insn (first); |
5443 | set_last_insn (last); | |
bb27eeda SE |
5444 | } |
5445 | ||
f15ae3a1 TW |
5446 | /* Set up the outer-level insn chain |
5447 | as the current sequence, saving the previously current one. */ | |
5448 | ||
5449 | void | |
502b8322 | 5450 | push_topmost_sequence (void) |
f15ae3a1 | 5451 | { |
614d5bd8 | 5452 | struct sequence_stack *top; |
f15ae3a1 TW |
5453 | |
5454 | start_sequence (); | |
5455 | ||
614d5bd8 | 5456 | top = get_topmost_sequence (); |
5936d944 JH |
5457 | set_first_insn (top->first); |
5458 | set_last_insn (top->last); | |
f15ae3a1 TW |
5459 | } |
5460 | ||
5461 | /* After emitting to the outer-level insn chain, update the outer-level | |
5462 | insn chain, and restore the previous saved state. */ | |
5463 | ||
5464 | void | |
502b8322 | 5465 | pop_topmost_sequence (void) |
f15ae3a1 | 5466 | { |
614d5bd8 | 5467 | struct sequence_stack *top; |
f15ae3a1 | 5468 | |
614d5bd8 | 5469 | top = get_topmost_sequence (); |
5936d944 JH |
5470 | top->first = get_insns (); |
5471 | top->last = get_last_insn (); | |
f15ae3a1 TW |
5472 | |
5473 | end_sequence (); | |
5474 | } | |
5475 | ||
23b2ce53 RS |
5476 | /* After emitting to a sequence, restore previous saved state. |
5477 | ||
5c7a310f | 5478 | To get the contents of the sequence just made, you must call |
2f937369 | 5479 | `get_insns' *before* calling here. |
5c7a310f MM |
5480 | |
5481 | If the compiler might have deferred popping arguments while | |
5482 | generating this sequence, and this sequence will not be immediately | |
5483 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5484 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5485 | pops are inserted into this sequence, and not into some random |
5486 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5487 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5488 | |
5489 | void | |
502b8322 | 5490 | end_sequence (void) |
23b2ce53 | 5491 | { |
614d5bd8 | 5492 | struct sequence_stack *tem = get_current_sequence ()->next; |
23b2ce53 | 5493 | |
5936d944 JH |
5494 | set_first_insn (tem->first); |
5495 | set_last_insn (tem->last); | |
614d5bd8 | 5496 | get_current_sequence ()->next = tem->next; |
23b2ce53 | 5497 | |
e2500fed GK |
5498 | memset (tem, 0, sizeof (*tem)); |
5499 | tem->next = free_sequence_stack; | |
5500 | free_sequence_stack = tem; | |
23b2ce53 RS |
5501 | } |
5502 | ||
5503 | /* Return 1 if currently emitting into a sequence. */ | |
5504 | ||
5505 | int | |
502b8322 | 5506 | in_sequence_p (void) |
23b2ce53 | 5507 | { |
614d5bd8 | 5508 | return get_current_sequence ()->next != 0; |
23b2ce53 | 5509 | } |
23b2ce53 | 5510 | \f |
59ec66dc MM |
5511 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5512 | ||
2bbdec73 | 5513 | static void |
bd60bab2 | 5514 | init_virtual_regs (void) |
59ec66dc | 5515 | { |
bd60bab2 JH |
5516 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5517 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5518 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5519 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5520 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
32990d5b JJ |
5521 | regno_reg_rtx[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM] |
5522 | = virtual_preferred_stack_boundary_rtx; | |
49ad7cfa BS |
5523 | } |
5524 | ||
da43a810 BS |
5525 | \f |
5526 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5527 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5528 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5529 | static int copy_insn_n_scratches; | |
5530 | ||
5531 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5532 | copied an ASM_OPERANDS. | |
5533 | In that case, it is the original input-operand vector. */ | |
5534 | static rtvec orig_asm_operands_vector; | |
5535 | ||
5536 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5537 | copied an ASM_OPERANDS. | |
5538 | In that case, it is the copied input-operand vector. */ | |
5539 | static rtvec copy_asm_operands_vector; | |
5540 | ||
5541 | /* Likewise for the constraints vector. */ | |
5542 | static rtvec orig_asm_constraints_vector; | |
5543 | static rtvec copy_asm_constraints_vector; | |
5544 | ||
5545 | /* Recursively create a new copy of an rtx for copy_insn. | |
5546 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5547 | ASM_OPERANDs properly. | |
5548 | Normally, this function is not used directly; use copy_insn as front end. | |
5549 | However, you could first copy an insn pattern with copy_insn and then use | |
5550 | this function afterwards to properly copy any REG_NOTEs containing | |
5551 | SCRATCHes. */ | |
5552 | ||
5553 | rtx | |
502b8322 | 5554 | copy_insn_1 (rtx orig) |
da43a810 | 5555 | { |
b3694847 SS |
5556 | rtx copy; |
5557 | int i, j; | |
5558 | RTX_CODE code; | |
5559 | const char *format_ptr; | |
da43a810 | 5560 | |
cd9c1ca8 RH |
5561 | if (orig == NULL) |
5562 | return NULL; | |
5563 | ||
da43a810 BS |
5564 | code = GET_CODE (orig); |
5565 | ||
5566 | switch (code) | |
5567 | { | |
5568 | case REG: | |
a52a87c3 | 5569 | case DEBUG_EXPR: |
d8116890 | 5570 | CASE_CONST_ANY: |
da43a810 BS |
5571 | case SYMBOL_REF: |
5572 | case CODE_LABEL: | |
5573 | case PC: | |
5574 | case CC0: | |
276e0224 | 5575 | case RETURN: |
26898771 | 5576 | case SIMPLE_RETURN: |
da43a810 | 5577 | return orig; |
3e89ed8d | 5578 | case CLOBBER: |
c5c5ba89 JH |
5579 | /* Share clobbers of hard registers (like cc0), but do not share pseudo reg |
5580 | clobbers or clobbers of hard registers that originated as pseudos. | |
5581 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
5582 | if (REG_P (XEXP (orig, 0)) |
5583 | && HARD_REGISTER_NUM_P (REGNO (XEXP (orig, 0))) | |
5584 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig, 0)))) | |
3e89ed8d JH |
5585 | return orig; |
5586 | break; | |
da43a810 BS |
5587 | |
5588 | case SCRATCH: | |
5589 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5590 | if (copy_insn_scratch_in[i] == orig) | |
5591 | return copy_insn_scratch_out[i]; | |
5592 | break; | |
5593 | ||
5594 | case CONST: | |
6fb5fa3c | 5595 | if (shared_const_p (orig)) |
da43a810 BS |
5596 | return orig; |
5597 | break; | |
750c9258 | 5598 | |
da43a810 BS |
5599 | /* A MEM with a constant address is not sharable. The problem is that |
5600 | the constant address may need to be reloaded. If the mem is shared, | |
5601 | then reloading one copy of this mem will cause all copies to appear | |
5602 | to have been reloaded. */ | |
5603 | ||
5604 | default: | |
5605 | break; | |
5606 | } | |
5607 | ||
aacd3885 RS |
5608 | /* Copy the various flags, fields, and other information. We assume |
5609 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5610 | not be copied. That is the sensible default behavior, and forces |
5611 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5612 | copy = shallow_copy_rtx (orig); |
da43a810 | 5613 | |
da43a810 | 5614 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ |
ec8e098d | 5615 | if (INSN_P (orig)) |
da43a810 | 5616 | { |
2adc7f12 JJ |
5617 | RTX_FLAG (copy, jump) = 0; |
5618 | RTX_FLAG (copy, call) = 0; | |
5619 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5620 | } |
750c9258 | 5621 | |
da43a810 BS |
5622 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5623 | ||
5624 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5625 | switch (*format_ptr++) |
5626 | { | |
5627 | case 'e': | |
5628 | if (XEXP (orig, i) != NULL) | |
5629 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5630 | break; | |
da43a810 | 5631 | |
aacd3885 RS |
5632 | case 'E': |
5633 | case 'V': | |
5634 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5635 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5636 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5637 | XVEC (copy, i) = copy_asm_operands_vector; | |
5638 | else if (XVEC (orig, i) != NULL) | |
5639 | { | |
5640 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5641 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5642 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5643 | } | |
5644 | break; | |
da43a810 | 5645 | |
aacd3885 RS |
5646 | case 't': |
5647 | case 'w': | |
5648 | case 'i': | |
5649 | case 's': | |
5650 | case 'S': | |
5651 | case 'u': | |
5652 | case '0': | |
5653 | /* These are left unchanged. */ | |
5654 | break; | |
da43a810 | 5655 | |
aacd3885 RS |
5656 | default: |
5657 | gcc_unreachable (); | |
5658 | } | |
da43a810 BS |
5659 | |
5660 | if (code == SCRATCH) | |
5661 | { | |
5662 | i = copy_insn_n_scratches++; | |
5b0264cb | 5663 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5664 | copy_insn_scratch_in[i] = orig; |
5665 | copy_insn_scratch_out[i] = copy; | |
5666 | } | |
5667 | else if (code == ASM_OPERANDS) | |
5668 | { | |
6462bb43 AO |
5669 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5670 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5671 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5672 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5673 | } |
5674 | ||
5675 | return copy; | |
5676 | } | |
5677 | ||
5678 | /* Create a new copy of an rtx. | |
5679 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5680 | ASM_OPERANDs properly. | |
5681 | INSN doesn't really have to be a full INSN; it could be just the | |
5682 | pattern. */ | |
5683 | rtx | |
502b8322 | 5684 | copy_insn (rtx insn) |
da43a810 BS |
5685 | { |
5686 | copy_insn_n_scratches = 0; | |
5687 | orig_asm_operands_vector = 0; | |
5688 | orig_asm_constraints_vector = 0; | |
5689 | copy_asm_operands_vector = 0; | |
5690 | copy_asm_constraints_vector = 0; | |
5691 | return copy_insn_1 (insn); | |
5692 | } | |
59ec66dc | 5693 | |
8e383849 JR |
5694 | /* Return a copy of INSN that can be used in a SEQUENCE delay slot, |
5695 | on that assumption that INSN itself remains in its original place. */ | |
5696 | ||
f8f0516e DM |
5697 | rtx_insn * |
5698 | copy_delay_slot_insn (rtx_insn *insn) | |
8e383849 JR |
5699 | { |
5700 | /* Copy INSN with its rtx_code, all its notes, location etc. */ | |
f8f0516e | 5701 | insn = as_a <rtx_insn *> (copy_rtx (insn)); |
8e383849 JR |
5702 | INSN_UID (insn) = cur_insn_uid++; |
5703 | return insn; | |
5704 | } | |
5705 | ||
23b2ce53 RS |
5706 | /* Initialize data structures and variables in this file |
5707 | before generating rtl for each function. */ | |
5708 | ||
5709 | void | |
502b8322 | 5710 | init_emit (void) |
23b2ce53 | 5711 | { |
5936d944 JH |
5712 | set_first_insn (NULL); |
5713 | set_last_insn (NULL); | |
b5b8b0ac AO |
5714 | if (MIN_NONDEBUG_INSN_UID) |
5715 | cur_insn_uid = MIN_NONDEBUG_INSN_UID; | |
5716 | else | |
5717 | cur_insn_uid = 1; | |
5718 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5719 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
23b2ce53 | 5720 | first_label_num = label_num; |
614d5bd8 | 5721 | get_current_sequence ()->next = NULL; |
23b2ce53 | 5722 | |
23b2ce53 RS |
5723 | /* Init the tables that describe all the pseudo regs. */ |
5724 | ||
3e029763 | 5725 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5726 | |
3e029763 | 5727 | crtl->emit.regno_pointer_align |
1b4572a8 | 5728 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5729 | |
f44986d7 DM |
5730 | regno_reg_rtx |
5731 | = ggc_cleared_vec_alloc<rtx> (crtl->emit.regno_pointer_align_length); | |
0d4903b8 | 5732 | |
e50126e8 | 5733 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 | 5734 | memcpy (regno_reg_rtx, |
5fb0e246 | 5735 | initial_regno_reg_rtx, |
6cde4876 | 5736 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
e50126e8 | 5737 | |
23b2ce53 | 5738 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5739 | init_virtual_regs (); |
740ab4a2 RK |
5740 | |
5741 | /* Indicate that the virtual registers and stack locations are | |
5742 | all pointers. */ | |
3502dc9c JDA |
5743 | REG_POINTER (stack_pointer_rtx) = 1; |
5744 | REG_POINTER (frame_pointer_rtx) = 1; | |
5745 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5746 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5747 | |
3502dc9c JDA |
5748 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5749 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5750 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5751 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5752 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5753 | |
86fe05e0 | 5754 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5755 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5756 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5757 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5758 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5759 | ||
da75ca93 EB |
5760 | /* ??? These are problematic (for example, 3 out of 4 are wrong on |
5761 | 32-bit SPARC and cannot be all fixed because of the ABI). */ | |
bdb429a5 RK |
5762 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; |
5763 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5764 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5765 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
da75ca93 | 5766 | |
bdb429a5 | 5767 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; |
86fe05e0 RK |
5768 | #endif |
5769 | ||
5e82e7bd JVA |
5770 | #ifdef INIT_EXPANDERS |
5771 | INIT_EXPANDERS; | |
5772 | #endif | |
23b2ce53 RS |
5773 | } |
5774 | ||
9b4473b6 RS |
5775 | /* Return true if X is a valid element for a duplicated vector constant |
5776 | of the given mode. */ | |
5777 | ||
5778 | bool | |
5779 | valid_for_const_vec_duplicate_p (machine_mode, rtx x) | |
5780 | { | |
5781 | return (CONST_SCALAR_INT_P (x) | |
5782 | || CONST_DOUBLE_AS_FLOAT_P (x) | |
5783 | || CONST_FIXED_P (x)); | |
5784 | } | |
5785 | ||
59d06c05 | 5786 | /* Like gen_const_vec_duplicate, but ignore const_tiny_rtx. */ |
69ef87e2 AH |
5787 | |
5788 | static rtx | |
59d06c05 | 5789 | gen_const_vec_duplicate_1 (machine_mode mode, rtx el) |
69ef87e2 | 5790 | { |
59d06c05 RS |
5791 | int nunits = GET_MODE_NUNITS (mode); |
5792 | rtvec v = rtvec_alloc (nunits); | |
5793 | for (int i = 0; i < nunits; ++i) | |
5794 | RTVEC_ELT (v, i) = el; | |
5795 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
5796 | } | |
69ef87e2 | 5797 | |
59d06c05 RS |
5798 | /* Generate a vector constant of mode MODE in which every element has |
5799 | value ELT. */ | |
69ef87e2 | 5800 | |
59d06c05 RS |
5801 | rtx |
5802 | gen_const_vec_duplicate (machine_mode mode, rtx elt) | |
5803 | { | |
5804 | scalar_mode inner_mode = GET_MODE_INNER (mode); | |
5805 | if (elt == CONST0_RTX (inner_mode)) | |
5806 | return CONST0_RTX (mode); | |
5807 | else if (elt == CONST1_RTX (inner_mode)) | |
5808 | return CONST1_RTX (mode); | |
5809 | else if (elt == CONSTM1_RTX (inner_mode)) | |
5810 | return CONSTM1_RTX (mode); | |
5811 | ||
5812 | return gen_const_vec_duplicate_1 (mode, elt); | |
5813 | } | |
5814 | ||
5815 | /* Return a vector rtx of mode MODE in which every element has value X. | |
5816 | The result will be a constant if X is constant. */ | |
5817 | ||
5818 | rtx | |
5819 | gen_vec_duplicate (machine_mode mode, rtx x) | |
5820 | { | |
9b4473b6 | 5821 | if (valid_for_const_vec_duplicate_p (mode, x)) |
59d06c05 RS |
5822 | return gen_const_vec_duplicate (mode, x); |
5823 | return gen_rtx_VEC_DUPLICATE (mode, x); | |
5824 | } | |
15ed7b52 | 5825 | |
ef339d6e RS |
5826 | /* A subroutine of const_vec_series_p that handles the case in which |
5827 | X is known to be an integer CONST_VECTOR. */ | |
5828 | ||
5829 | bool | |
5830 | const_vec_series_p_1 (const_rtx x, rtx *base_out, rtx *step_out) | |
5831 | { | |
5832 | unsigned int nelts = CONST_VECTOR_NUNITS (x); | |
5833 | if (nelts < 2) | |
5834 | return false; | |
5835 | ||
5836 | scalar_mode inner = GET_MODE_INNER (GET_MODE (x)); | |
5837 | rtx base = CONST_VECTOR_ELT (x, 0); | |
5838 | rtx step = simplify_binary_operation (MINUS, inner, | |
5839 | CONST_VECTOR_ELT (x, 1), base); | |
5840 | if (rtx_equal_p (step, CONST0_RTX (inner))) | |
5841 | return false; | |
5842 | ||
5843 | for (unsigned int i = 2; i < nelts; ++i) | |
5844 | { | |
5845 | rtx diff = simplify_binary_operation (MINUS, inner, | |
5846 | CONST_VECTOR_ELT (x, i), | |
5847 | CONST_VECTOR_ELT (x, i - 1)); | |
5848 | if (!rtx_equal_p (step, diff)) | |
5849 | return false; | |
5850 | } | |
5851 | ||
5852 | *base_out = base; | |
5853 | *step_out = step; | |
5854 | return true; | |
5855 | } | |
5856 | ||
5857 | /* Generate a vector constant of mode MODE in which element I has | |
5858 | the value BASE + I * STEP. */ | |
5859 | ||
5860 | rtx | |
5861 | gen_const_vec_series (machine_mode mode, rtx base, rtx step) | |
5862 | { | |
5863 | gcc_assert (CONSTANT_P (base) && CONSTANT_P (step)); | |
5864 | ||
5865 | int nunits = GET_MODE_NUNITS (mode); | |
5866 | rtvec v = rtvec_alloc (nunits); | |
5867 | scalar_mode inner_mode = GET_MODE_INNER (mode); | |
5868 | RTVEC_ELT (v, 0) = base; | |
5869 | for (int i = 1; i < nunits; ++i) | |
5870 | RTVEC_ELT (v, i) = simplify_gen_binary (PLUS, inner_mode, | |
5871 | RTVEC_ELT (v, i - 1), step); | |
5872 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
5873 | } | |
5874 | ||
5875 | /* Generate a vector of mode MODE in which element I has the value | |
5876 | BASE + I * STEP. The result will be a constant if BASE and STEP | |
5877 | are both constants. */ | |
5878 | ||
5879 | rtx | |
5880 | gen_vec_series (machine_mode mode, rtx base, rtx step) | |
5881 | { | |
5882 | if (step == const0_rtx) | |
5883 | return gen_vec_duplicate (mode, base); | |
5884 | if (CONSTANT_P (base) && CONSTANT_P (step)) | |
5885 | return gen_const_vec_series (mode, base, step); | |
5886 | return gen_rtx_VEC_SERIES (mode, base, step); | |
5887 | } | |
5888 | ||
59d06c05 RS |
5889 | /* Generate a new vector constant for mode MODE and constant value |
5890 | CONSTANT. */ | |
69ef87e2 | 5891 | |
59d06c05 RS |
5892 | static rtx |
5893 | gen_const_vector (machine_mode mode, int constant) | |
5894 | { | |
5895 | machine_mode inner = GET_MODE_INNER (mode); | |
69ef87e2 | 5896 | |
59d06c05 RS |
5897 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5898 | ||
5899 | rtx el = const_tiny_rtx[constant][(int) inner]; | |
5900 | gcc_assert (el); | |
69ef87e2 | 5901 | |
59d06c05 | 5902 | return gen_const_vec_duplicate_1 (mode, el); |
69ef87e2 AH |
5903 | } |
5904 | ||
a06e3c40 | 5905 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5906 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5907 | rtx |
ef4bddc2 | 5908 | gen_rtx_CONST_VECTOR (machine_mode mode, rtvec v) |
a06e3c40 | 5909 | { |
59d06c05 | 5910 | gcc_assert (GET_MODE_NUNITS (mode) == GET_NUM_ELEM (v)); |
a73b091d JW |
5911 | |
5912 | /* If the values are all the same, check to see if we can use one of the | |
5913 | standard constant vectors. */ | |
59d06c05 RS |
5914 | if (rtvec_all_equal_p (v)) |
5915 | return gen_const_vec_duplicate (mode, RTVEC_ELT (v, 0)); | |
a73b091d JW |
5916 | |
5917 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5918 | } |
5919 | ||
b5deb7b6 SL |
5920 | /* Initialise global register information required by all functions. */ |
5921 | ||
5922 | void | |
5923 | init_emit_regs (void) | |
5924 | { | |
5925 | int i; | |
ef4bddc2 | 5926 | machine_mode mode; |
1c3f523e | 5927 | mem_attrs *attrs; |
b5deb7b6 SL |
5928 | |
5929 | /* Reset register attributes */ | |
aebf76a2 | 5930 | reg_attrs_htab->empty (); |
b5deb7b6 SL |
5931 | |
5932 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5933 | init_reg_modes_target (); | |
5934 | ||
5935 | /* Assign register numbers to the globally defined register rtx. */ | |
b5deb7b6 SL |
5936 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
5937 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5938 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5939 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5940 | virtual_incoming_args_rtx = | |
5941 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5942 | virtual_stack_vars_rtx = | |
5943 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5944 | virtual_stack_dynamic_rtx = | |
5945 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5946 | virtual_outgoing_args_rtx = | |
5947 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5948 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
32990d5b JJ |
5949 | virtual_preferred_stack_boundary_rtx = |
5950 | gen_raw_REG (Pmode, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM); | |
b5deb7b6 SL |
5951 | |
5952 | /* Initialize RTL for commonly used hard registers. These are | |
5953 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5954 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5fb0e246 | 5955 | initial_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); |
b5deb7b6 SL |
5956 | |
5957 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5958 | return_address_pointer_rtx | |
5959 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5960 | #endif | |
5961 | ||
ca72dad5 | 5962 | pic_offset_table_rtx = NULL_RTX; |
b5deb7b6 SL |
5963 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
5964 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
1c3f523e RS |
5965 | |
5966 | for (i = 0; i < (int) MAX_MACHINE_MODE; i++) | |
5967 | { | |
ef4bddc2 | 5968 | mode = (machine_mode) i; |
766090c2 | 5969 | attrs = ggc_cleared_alloc<mem_attrs> (); |
1c3f523e RS |
5970 | attrs->align = BITS_PER_UNIT; |
5971 | attrs->addrspace = ADDR_SPACE_GENERIC; | |
5972 | if (mode != BLKmode) | |
5973 | { | |
754c3d5d RS |
5974 | attrs->size_known_p = true; |
5975 | attrs->size = GET_MODE_SIZE (mode); | |
1c3f523e RS |
5976 | if (STRICT_ALIGNMENT) |
5977 | attrs->align = GET_MODE_ALIGNMENT (mode); | |
5978 | } | |
5979 | mode_mem_attrs[i] = attrs; | |
5980 | } | |
af364399 ML |
5981 | |
5982 | split_branch_probability = profile_probability::uninitialized (); | |
b5deb7b6 SL |
5983 | } |
5984 | ||
aa3a12d6 RS |
5985 | /* Initialize global machine_mode variables. */ |
5986 | ||
5987 | void | |
5988 | init_derived_machine_modes (void) | |
5989 | { | |
501623d4 RS |
5990 | opt_scalar_int_mode mode_iter, opt_byte_mode, opt_word_mode; |
5991 | FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT) | |
aa3a12d6 | 5992 | { |
501623d4 RS |
5993 | scalar_int_mode mode = mode_iter.require (); |
5994 | ||
aa3a12d6 | 5995 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT |
501623d4 RS |
5996 | && !opt_byte_mode.exists ()) |
5997 | opt_byte_mode = mode; | |
aa3a12d6 RS |
5998 | |
5999 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
501623d4 RS |
6000 | && !opt_word_mode.exists ()) |
6001 | opt_word_mode = mode; | |
aa3a12d6 RS |
6002 | } |
6003 | ||
501623d4 RS |
6004 | byte_mode = opt_byte_mode.require (); |
6005 | word_mode = opt_word_mode.require (); | |
f95c5b8e RS |
6006 | ptr_mode = as_a <scalar_int_mode> |
6007 | (mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0).require ()); | |
aa3a12d6 RS |
6008 | } |
6009 | ||
2d888286 | 6010 | /* Create some permanent unique rtl objects shared between all functions. */ |
23b2ce53 RS |
6011 | |
6012 | void | |
2d888286 | 6013 | init_emit_once (void) |
23b2ce53 RS |
6014 | { |
6015 | int i; | |
ef4bddc2 | 6016 | machine_mode mode; |
857c7b46 | 6017 | scalar_float_mode double_mode; |
16d22000 | 6018 | opt_scalar_mode smode_iter; |
23b2ce53 | 6019 | |
807e902e KZ |
6020 | /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE, |
6021 | CONST_FIXED, and memory attribute hash tables. */ | |
aebf76a2 | 6022 | const_int_htab = hash_table<const_int_hasher>::create_ggc (37); |
173b24b9 | 6023 | |
807e902e | 6024 | #if TARGET_SUPPORTS_WIDE_INT |
aebf76a2 | 6025 | const_wide_int_htab = hash_table<const_wide_int_hasher>::create_ggc (37); |
807e902e | 6026 | #endif |
aebf76a2 | 6027 | const_double_htab = hash_table<const_double_hasher>::create_ggc (37); |
5692c7bc | 6028 | |
aebf76a2 | 6029 | const_fixed_htab = hash_table<const_fixed_hasher>::create_ggc (37); |
091a3ac7 | 6030 | |
aebf76a2 | 6031 | reg_attrs_htab = hash_table<reg_attr_hasher>::create_ggc (37); |
67673f5c | 6032 | |
5da077de | 6033 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
6034 | /* This is to initialize {init|mark|free}_machine_status before the first |
6035 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 6036 | end which calls push_function_context_to before the first call to |
5da077de AS |
6037 | init_function_start. */ |
6038 | INIT_EXPANDERS; | |
6039 | #endif | |
6040 | ||
23b2ce53 RS |
6041 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
6042 | ||
ecf835e9 KN |
6043 | /* Process stack-limiting command-line options. */ |
6044 | if (opt_fstack_limit_symbol_arg != NULL) | |
6045 | stack_limit_rtx | |
6046 | = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (opt_fstack_limit_symbol_arg)); | |
6047 | if (opt_fstack_limit_register_no >= 0) | |
6048 | stack_limit_rtx = gen_rtx_REG (Pmode, opt_fstack_limit_register_no); | |
6049 | ||
a2a8cc44 | 6050 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 6051 | tries to use these variables. */ |
23b2ce53 | 6052 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 6053 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 6054 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 6055 | |
68d75312 JC |
6056 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
6057 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 6058 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 6059 | else |
3b80f6ca | 6060 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 6061 | |
857c7b46 | 6062 | double_mode = float_mode_for_size (DOUBLE_TYPE_SIZE).require (); |
aa3a12d6 | 6063 | |
807e902e KZ |
6064 | real_from_integer (&dconst0, double_mode, 0, SIGNED); |
6065 | real_from_integer (&dconst1, double_mode, 1, SIGNED); | |
6066 | real_from_integer (&dconst2, double_mode, 2, SIGNED); | |
aefa9d43 KG |
6067 | |
6068 | dconstm1 = dconst1; | |
6069 | dconstm1.sign = 1; | |
03f2ea93 RS |
6070 | |
6071 | dconsthalf = dconst1; | |
1e92bbb9 | 6072 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 6073 | |
e7c82a99 | 6074 | for (i = 0; i < 3; i++) |
23b2ce53 | 6075 | { |
aefa9d43 | 6076 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
6077 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
6078 | ||
c94843d2 | 6079 | FOR_EACH_MODE_IN_CLASS (mode, MODE_FLOAT) |
15ed7b52 | 6080 | const_tiny_rtx[i][(int) mode] = |
555affd7 | 6081 | const_double_from_real_value (*r, mode); |
15ed7b52 | 6082 | |
c94843d2 | 6083 | FOR_EACH_MODE_IN_CLASS (mode, MODE_DECIMAL_FLOAT) |
5692c7bc | 6084 | const_tiny_rtx[i][(int) mode] = |
555affd7 | 6085 | const_double_from_real_value (*r, mode); |
23b2ce53 | 6086 | |
906c4e36 | 6087 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 6088 | |
c94843d2 | 6089 | FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
906c4e36 | 6090 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 | 6091 | |
ede6c734 MS |
6092 | for (mode = MIN_MODE_PARTIAL_INT; |
6093 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 6094 | mode = (machine_mode)((int)(mode) + 1)) |
33d3e559 | 6095 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
23b2ce53 RS |
6096 | } |
6097 | ||
e7c82a99 JJ |
6098 | const_tiny_rtx[3][(int) VOIDmode] = constm1_rtx; |
6099 | ||
c94843d2 | 6100 | FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
e7c82a99 JJ |
6101 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
6102 | ||
ede6c734 MS |
6103 | for (mode = MIN_MODE_PARTIAL_INT; |
6104 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 6105 | mode = (machine_mode)((int)(mode) + 1)) |
c8a89d2a | 6106 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
c94843d2 RS |
6107 | |
6108 | FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_INT) | |
e90721b1 AP |
6109 | { |
6110 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
6111 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
6112 | } | |
6113 | ||
c94843d2 | 6114 | FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_FLOAT) |
e90721b1 AP |
6115 | { |
6116 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
6117 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
6118 | } | |
6119 | ||
c94843d2 | 6120 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) |
a73b091d JW |
6121 | { |
6122 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6123 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
e7c82a99 | 6124 | const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3); |
a73b091d | 6125 | } |
69ef87e2 | 6126 | |
c94843d2 | 6127 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT) |
a73b091d JW |
6128 | { |
6129 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6130 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6131 | } | |
69ef87e2 | 6132 | |
16d22000 | 6133 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_FRACT) |
325217ed | 6134 | { |
16d22000 RS |
6135 | scalar_mode smode = smode_iter.require (); |
6136 | FCONST0 (smode).data.high = 0; | |
6137 | FCONST0 (smode).data.low = 0; | |
6138 | FCONST0 (smode).mode = smode; | |
6139 | const_tiny_rtx[0][(int) smode] | |
6140 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6141 | } |
6142 | ||
16d22000 | 6143 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UFRACT) |
325217ed | 6144 | { |
16d22000 RS |
6145 | scalar_mode smode = smode_iter.require (); |
6146 | FCONST0 (smode).data.high = 0; | |
6147 | FCONST0 (smode).data.low = 0; | |
6148 | FCONST0 (smode).mode = smode; | |
6149 | const_tiny_rtx[0][(int) smode] | |
6150 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6151 | } |
6152 | ||
16d22000 | 6153 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_ACCUM) |
325217ed | 6154 | { |
16d22000 RS |
6155 | scalar_mode smode = smode_iter.require (); |
6156 | FCONST0 (smode).data.high = 0; | |
6157 | FCONST0 (smode).data.low = 0; | |
6158 | FCONST0 (smode).mode = smode; | |
6159 | const_tiny_rtx[0][(int) smode] | |
6160 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6161 | |
6162 | /* We store the value 1. */ | |
16d22000 RS |
6163 | FCONST1 (smode).data.high = 0; |
6164 | FCONST1 (smode).data.low = 0; | |
6165 | FCONST1 (smode).mode = smode; | |
6166 | FCONST1 (smode).data | |
6167 | = double_int_one.lshift (GET_MODE_FBIT (smode), | |
9be0ac8c | 6168 | HOST_BITS_PER_DOUBLE_INT, |
16d22000 RS |
6169 | SIGNED_FIXED_POINT_MODE_P (smode)); |
6170 | const_tiny_rtx[1][(int) smode] | |
6171 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode); | |
325217ed CF |
6172 | } |
6173 | ||
16d22000 | 6174 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UACCUM) |
325217ed | 6175 | { |
16d22000 RS |
6176 | scalar_mode smode = smode_iter.require (); |
6177 | FCONST0 (smode).data.high = 0; | |
6178 | FCONST0 (smode).data.low = 0; | |
6179 | FCONST0 (smode).mode = smode; | |
6180 | const_tiny_rtx[0][(int) smode] | |
6181 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6182 | |
6183 | /* We store the value 1. */ | |
16d22000 RS |
6184 | FCONST1 (smode).data.high = 0; |
6185 | FCONST1 (smode).data.low = 0; | |
6186 | FCONST1 (smode).mode = smode; | |
6187 | FCONST1 (smode).data | |
6188 | = double_int_one.lshift (GET_MODE_FBIT (smode), | |
9be0ac8c | 6189 | HOST_BITS_PER_DOUBLE_INT, |
16d22000 RS |
6190 | SIGNED_FIXED_POINT_MODE_P (smode)); |
6191 | const_tiny_rtx[1][(int) smode] | |
6192 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode); | |
091a3ac7 CF |
6193 | } |
6194 | ||
c94843d2 | 6195 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FRACT) |
091a3ac7 CF |
6196 | { |
6197 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6198 | } | |
6199 | ||
c94843d2 | 6200 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UFRACT) |
091a3ac7 CF |
6201 | { |
6202 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6203 | } | |
6204 | ||
c94843d2 | 6205 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_ACCUM) |
091a3ac7 CF |
6206 | { |
6207 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6208 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6209 | } | |
6210 | ||
c94843d2 | 6211 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UACCUM) |
091a3ac7 CF |
6212 | { |
6213 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6214 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
6215 | } |
6216 | ||
dbbbbf3b | 6217 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
ef4bddc2 | 6218 | if (GET_MODE_CLASS ((machine_mode) i) == MODE_CC) |
dbbbbf3b | 6219 | const_tiny_rtx[0][i] = const0_rtx; |
23b2ce53 | 6220 | |
f0417c82 RH |
6221 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
6222 | if (STORE_FLAG_VALUE == 1) | |
6223 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
ca4adc91 | 6224 | |
16d22000 | 6225 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_POINTER_BOUNDS) |
d5e254e1 | 6226 | { |
16d22000 RS |
6227 | scalar_mode smode = smode_iter.require (); |
6228 | wide_int wi_zero = wi::zero (GET_MODE_PRECISION (smode)); | |
6229 | const_tiny_rtx[0][smode] = immed_wide_int_const (wi_zero, smode); | |
d5e254e1 IE |
6230 | } |
6231 | ||
ca4adc91 RS |
6232 | pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); |
6233 | ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | |
6234 | simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); | |
6235 | cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode); | |
1476d1bd MM |
6236 | invalid_insn_rtx = gen_rtx_INSN (VOIDmode, |
6237 | /*prev_insn=*/NULL, | |
6238 | /*next_insn=*/NULL, | |
6239 | /*bb=*/NULL, | |
6240 | /*pattern=*/NULL_RTX, | |
6241 | /*location=*/-1, | |
6242 | CODE_FOR_nothing, | |
6243 | /*reg_notes=*/NULL_RTX); | |
23b2ce53 | 6244 | } |
a11759a3 | 6245 | \f |
969d70ca JH |
6246 | /* Produce exact duplicate of insn INSN after AFTER. |
6247 | Care updating of libcall regions if present. */ | |
6248 | ||
cd459bf8 | 6249 | rtx_insn * |
a1950df3 | 6250 | emit_copy_of_insn_after (rtx_insn *insn, rtx_insn *after) |
969d70ca | 6251 | { |
cd459bf8 DM |
6252 | rtx_insn *new_rtx; |
6253 | rtx link; | |
969d70ca JH |
6254 | |
6255 | switch (GET_CODE (insn)) | |
6256 | { | |
6257 | case INSN: | |
60564289 | 6258 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
6259 | break; |
6260 | ||
6261 | case JUMP_INSN: | |
60564289 | 6262 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
ec27069c | 6263 | CROSSING_JUMP_P (new_rtx) = CROSSING_JUMP_P (insn); |
969d70ca JH |
6264 | break; |
6265 | ||
b5b8b0ac AO |
6266 | case DEBUG_INSN: |
6267 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
6268 | break; | |
6269 | ||
969d70ca | 6270 | case CALL_INSN: |
60564289 | 6271 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 6272 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 6273 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 6274 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
6275 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
6276 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
6277 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
b8698a0f | 6278 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) |
becfd6e5 | 6279 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
6280 | break; |
6281 | ||
6282 | default: | |
5b0264cb | 6283 | gcc_unreachable (); |
969d70ca JH |
6284 | } |
6285 | ||
6286 | /* Update LABEL_NUSES. */ | |
60564289 | 6287 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 6288 | |
5368224f | 6289 | INSN_LOCATION (new_rtx) = INSN_LOCATION (insn); |
ba4f7968 | 6290 | |
0a3d71f5 JW |
6291 | /* If the old insn is frame related, then so is the new one. This is |
6292 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
6293 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 6294 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 6295 | |
1581a12c BS |
6296 | /* Locate the end of existing REG_NOTES in NEW_RTX. */ |
6297 | rtx *ptail = ®_NOTES (new_rtx); | |
6298 | while (*ptail != NULL_RTX) | |
6299 | ptail = &XEXP (*ptail, 1); | |
6300 | ||
cf7c4aa6 HPN |
6301 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
6302 | will make them. REG_LABEL_TARGETs are created there too, but are | |
6303 | supposed to be sticky, so we copy them. */ | |
969d70ca | 6304 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 6305 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca | 6306 | { |
1581a12c BS |
6307 | *ptail = duplicate_reg_note (link); |
6308 | ptail = &XEXP (*ptail, 1); | |
969d70ca JH |
6309 | } |
6310 | ||
60564289 KG |
6311 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
6312 | return new_rtx; | |
969d70ca | 6313 | } |
e2500fed | 6314 | |
1431042e | 6315 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d | 6316 | rtx |
ef4bddc2 | 6317 | gen_hard_reg_clobber (machine_mode mode, unsigned int regno) |
3e89ed8d JH |
6318 | { |
6319 | if (hard_reg_clobbers[mode][regno]) | |
6320 | return hard_reg_clobbers[mode][regno]; | |
6321 | else | |
6322 | return (hard_reg_clobbers[mode][regno] = | |
6323 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
6324 | } | |
6325 | ||
5368224f DC |
6326 | location_t prologue_location; |
6327 | location_t epilogue_location; | |
78bde837 SB |
6328 | |
6329 | /* Hold current location information and last location information, so the | |
6330 | datastructures are built lazily only when some instructions in given | |
6331 | place are needed. */ | |
3a50da34 | 6332 | static location_t curr_location; |
78bde837 | 6333 | |
5368224f | 6334 | /* Allocate insn location datastructure. */ |
78bde837 | 6335 | void |
5368224f | 6336 | insn_locations_init (void) |
78bde837 | 6337 | { |
5368224f | 6338 | prologue_location = epilogue_location = 0; |
78bde837 | 6339 | curr_location = UNKNOWN_LOCATION; |
78bde837 SB |
6340 | } |
6341 | ||
6342 | /* At the end of emit stage, clear current location. */ | |
6343 | void | |
5368224f | 6344 | insn_locations_finalize (void) |
78bde837 | 6345 | { |
5368224f DC |
6346 | epilogue_location = curr_location; |
6347 | curr_location = UNKNOWN_LOCATION; | |
78bde837 SB |
6348 | } |
6349 | ||
6350 | /* Set current location. */ | |
6351 | void | |
5368224f | 6352 | set_curr_insn_location (location_t location) |
78bde837 | 6353 | { |
78bde837 SB |
6354 | curr_location = location; |
6355 | } | |
6356 | ||
6357 | /* Get current location. */ | |
6358 | location_t | |
5368224f | 6359 | curr_insn_location (void) |
78bde837 SB |
6360 | { |
6361 | return curr_location; | |
6362 | } | |
6363 | ||
78bde837 SB |
6364 | /* Return lexical scope block insn belongs to. */ |
6365 | tree | |
a1950df3 | 6366 | insn_scope (const rtx_insn *insn) |
78bde837 | 6367 | { |
5368224f | 6368 | return LOCATION_BLOCK (INSN_LOCATION (insn)); |
78bde837 SB |
6369 | } |
6370 | ||
6371 | /* Return line number of the statement that produced this insn. */ | |
6372 | int | |
a1950df3 | 6373 | insn_line (const rtx_insn *insn) |
78bde837 | 6374 | { |
5368224f | 6375 | return LOCATION_LINE (INSN_LOCATION (insn)); |
78bde837 SB |
6376 | } |
6377 | ||
6378 | /* Return source file of the statement that produced this insn. */ | |
6379 | const char * | |
a1950df3 | 6380 | insn_file (const rtx_insn *insn) |
78bde837 | 6381 | { |
5368224f | 6382 | return LOCATION_FILE (INSN_LOCATION (insn)); |
78bde837 | 6383 | } |
8930883e | 6384 | |
ffa4602f EB |
6385 | /* Return expanded location of the statement that produced this insn. */ |
6386 | expanded_location | |
a1950df3 | 6387 | insn_location (const rtx_insn *insn) |
ffa4602f EB |
6388 | { |
6389 | return expand_location (INSN_LOCATION (insn)); | |
6390 | } | |
6391 | ||
8930883e MK |
6392 | /* Return true if memory model MODEL requires a pre-operation (release-style) |
6393 | barrier or a post-operation (acquire-style) barrier. While not universal, | |
6394 | this function matches behavior of several targets. */ | |
6395 | ||
6396 | bool | |
6397 | need_atomic_barrier_p (enum memmodel model, bool pre) | |
6398 | { | |
40ad260d | 6399 | switch (model & MEMMODEL_BASE_MASK) |
8930883e MK |
6400 | { |
6401 | case MEMMODEL_RELAXED: | |
6402 | case MEMMODEL_CONSUME: | |
6403 | return false; | |
6404 | case MEMMODEL_RELEASE: | |
6405 | return pre; | |
6406 | case MEMMODEL_ACQUIRE: | |
6407 | return !pre; | |
6408 | case MEMMODEL_ACQ_REL: | |
6409 | case MEMMODEL_SEQ_CST: | |
6410 | return true; | |
6411 | default: | |
6412 | gcc_unreachable (); | |
6413 | } | |
6414 | } | |
8194c537 DM |
6415 | |
6416 | /* Initialize fields of rtl_data related to stack alignment. */ | |
6417 | ||
6418 | void | |
6419 | rtl_data::init_stack_alignment () | |
6420 | { | |
6421 | stack_alignment_needed = STACK_BOUNDARY; | |
6422 | max_used_stack_slot_alignment = STACK_BOUNDARY; | |
6423 | stack_alignment_estimated = 0; | |
6424 | preferred_stack_boundary = STACK_BOUNDARY; | |
6425 | } | |
6426 | ||
8930883e | 6427 | \f |
e2500fed | 6428 | #include "gt-emit-rtl.h" |