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Commit | Line | Data |
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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
09efeca1 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
b6f65e3c | 4 | Free Software Foundation, Inc. |
23b2ce53 | 5 | |
1322177d | 6 | This file is part of GCC. |
23b2ce53 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
23b2ce53 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
23b2ce53 RS |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
f822fcf7 KH |
25 | This file contains support functions for creating rtl expressions |
26 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
27 | |
28 | The patterns of the insns are created by machine-dependent | |
29 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
30 | the machine description. These routines make the individual rtx's |
31 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
32 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
33 | dependent is the kind of rtx's they make and what arguments they |
34 | use. */ | |
23b2ce53 RS |
35 | |
36 | #include "config.h" | |
670ee920 | 37 | #include "system.h" |
4977bab6 ZW |
38 | #include "coretypes.h" |
39 | #include "tm.h" | |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
325217ed | 53 | #include "fixed-value.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
e1772ac0 | 57 | #include "debug.h" |
d23c55c2 | 58 | #include "langhooks.h" |
ef330312 | 59 | #include "tree-pass.h" |
6fb5fa3c | 60 | #include "df.h" |
b5b8b0ac | 61 | #include "params.h" |
d4ebfa65 | 62 | #include "target.h" |
ca695ac9 | 63 | |
1d445e9e ILT |
64 | /* Commonly used modes. */ |
65 | ||
0f41302f MS |
66 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
67 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 68 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 69 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 70 | |
bd60bab2 JH |
71 | /* Datastructures maintained for currently processed function in RTL form. */ |
72 | ||
3e029763 | 73 | struct rtl_data x_rtl; |
bd60bab2 JH |
74 | |
75 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
76 | Allocated in parallel with regno_pointer_align. | |
77 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal | |
78 | with length attribute nested in top level structures. */ | |
79 | ||
80 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
81 | |
82 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
83 | in the entire compilation a unique label number. */ | |
84 | ||
044b4de3 | 85 | static GTY(()) int label_num = 1; |
23b2ce53 | 86 | |
23b2ce53 RS |
87 | /* Nonzero means do not generate NOTEs for source line numbers. */ |
88 | ||
89 | static int no_line_numbers; | |
90 | ||
91 | /* Commonly used rtx's, so that we only need space for one copy. | |
92 | These are initialized once for the entire compilation. | |
5692c7bc ZW |
93 | All of these are unique; no other rtx-object will be equal to any |
94 | of these. */ | |
23b2ce53 | 95 | |
5da077de | 96 | rtx global_rtl[GR_MAX]; |
23b2ce53 | 97 | |
6cde4876 JL |
98 | /* Commonly used RTL for hard registers. These objects are not necessarily |
99 | unique, so we allocate them separately from global_rtl. They are | |
100 | initialized once per compilation unit, then copied into regno_reg_rtx | |
101 | at the beginning of each function. */ | |
102 | static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
103 | ||
23b2ce53 RS |
104 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
105 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
106 | record a copy of const[012]_rtx. */ | |
107 | ||
108 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
109 | ||
68d75312 JC |
110 | rtx const_true_rtx; |
111 | ||
23b2ce53 RS |
112 | REAL_VALUE_TYPE dconst0; |
113 | REAL_VALUE_TYPE dconst1; | |
114 | REAL_VALUE_TYPE dconst2; | |
115 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 116 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 117 | |
325217ed CF |
118 | /* Record fixed-point constant 0 and 1. */ |
119 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
120 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
121 | ||
23b2ce53 RS |
122 | /* All references to the following fixed hard registers go through |
123 | these unique rtl objects. On machines where the frame-pointer and | |
124 | arg-pointer are the same register, they use the same unique object. | |
125 | ||
126 | After register allocation, other rtl objects which used to be pseudo-regs | |
127 | may be clobbered to refer to the frame-pointer register. | |
128 | But references that were originally to the frame-pointer can be | |
129 | distinguished from the others because they contain frame_pointer_rtx. | |
130 | ||
ac6f08b0 DE |
131 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
132 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
750c9258 | 133 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
ac6f08b0 DE |
134 | register elimination hard_frame_pointer_rtx should always be used. |
135 | On machines where the two registers are same (most) then these are the | |
136 | same. | |
137 | ||
23b2ce53 RS |
138 | In an inline procedure, the stack and frame pointer rtxs may not be |
139 | used for anything else. */ | |
23b2ce53 RS |
140 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ |
141 | ||
a4417a86 JW |
142 | /* This is used to implement __builtin_return_address for some machines. |
143 | See for instance the MIPS port. */ | |
144 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
145 | ||
23b2ce53 RS |
146 | /* We make one copy of (const_int C) where C is in |
147 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
148 | to save space during the compilation and simplify comparisons of | |
149 | integers. */ | |
150 | ||
5da077de | 151 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 152 | |
c13e8210 MM |
153 | /* A hash table storing CONST_INTs whose absolute value is greater |
154 | than MAX_SAVED_CONST_INT. */ | |
155 | ||
e2500fed GK |
156 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
157 | htab_t const_int_htab; | |
c13e8210 | 158 | |
173b24b9 | 159 | /* A hash table storing memory attribute structures. */ |
e2500fed GK |
160 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
161 | htab_t mem_attrs_htab; | |
173b24b9 | 162 | |
a560d4d4 JH |
163 | /* A hash table storing register attribute structures. */ |
164 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
165 | htab_t reg_attrs_htab; | |
166 | ||
5692c7bc | 167 | /* A hash table storing all CONST_DOUBLEs. */ |
e2500fed GK |
168 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
169 | htab_t const_double_htab; | |
5692c7bc | 170 | |
091a3ac7 CF |
171 | /* A hash table storing all CONST_FIXEDs. */ |
172 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) | |
173 | htab_t const_fixed_htab; | |
174 | ||
3e029763 JH |
175 | #define first_insn (crtl->emit.x_first_insn) |
176 | #define last_insn (crtl->emit.x_last_insn) | |
177 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) | |
b5b8b0ac | 178 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 JH |
179 | #define last_location (crtl->emit.x_last_location) |
180 | #define first_label_num (crtl->emit.x_first_label_num) | |
23b2ce53 | 181 | |
502b8322 | 182 | static rtx make_call_insn_raw (rtx); |
502b8322 | 183 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); |
5eb2a9f2 | 184 | static void set_used_decls (tree); |
502b8322 AJ |
185 | static void mark_label_nuses (rtx); |
186 | static hashval_t const_int_htab_hash (const void *); | |
187 | static int const_int_htab_eq (const void *, const void *); | |
188 | static hashval_t const_double_htab_hash (const void *); | |
189 | static int const_double_htab_eq (const void *, const void *); | |
190 | static rtx lookup_const_double (rtx); | |
091a3ac7 CF |
191 | static hashval_t const_fixed_htab_hash (const void *); |
192 | static int const_fixed_htab_eq (const void *, const void *); | |
193 | static rtx lookup_const_fixed (rtx); | |
502b8322 AJ |
194 | static hashval_t mem_attrs_htab_hash (const void *); |
195 | static int mem_attrs_htab_eq (const void *, const void *); | |
4862826d | 196 | static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int, |
09e881c9 | 197 | addr_space_t, enum machine_mode); |
502b8322 AJ |
198 | static hashval_t reg_attrs_htab_hash (const void *); |
199 | static int reg_attrs_htab_eq (const void *, const void *); | |
200 | static reg_attrs *get_reg_attrs (tree, int); | |
a73b091d | 201 | static rtx gen_const_vector (enum machine_mode, int); |
32b32b16 | 202 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 203 | |
6b24c259 JH |
204 | /* Probability of the conditional branch currently proceeded by try_split. |
205 | Set to -1 otherwise. */ | |
206 | int split_branch_probability = -1; | |
ca695ac9 | 207 | \f |
c13e8210 MM |
208 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
209 | ||
210 | static hashval_t | |
502b8322 | 211 | const_int_htab_hash (const void *x) |
c13e8210 | 212 | { |
f7d504c2 | 213 | return (hashval_t) INTVAL ((const_rtx) x); |
c13e8210 MM |
214 | } |
215 | ||
cc2902df | 216 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
217 | CONST_INT) is the same as that given by Y (which is really a |
218 | HOST_WIDE_INT *). */ | |
219 | ||
220 | static int | |
502b8322 | 221 | const_int_htab_eq (const void *x, const void *y) |
c13e8210 | 222 | { |
f7d504c2 | 223 | return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y)); |
5692c7bc ZW |
224 | } |
225 | ||
226 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
227 | static hashval_t | |
502b8322 | 228 | const_double_htab_hash (const void *x) |
5692c7bc | 229 | { |
f7d504c2 | 230 | const_rtx const value = (const_rtx) x; |
46b33600 | 231 | hashval_t h; |
5692c7bc | 232 | |
46b33600 RH |
233 | if (GET_MODE (value) == VOIDmode) |
234 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
235 | else | |
fe352c29 | 236 | { |
15c812e3 | 237 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
238 | /* MODE is used in the comparison, so it should be in the hash. */ |
239 | h ^= GET_MODE (value); | |
240 | } | |
5692c7bc ZW |
241 | return h; |
242 | } | |
243 | ||
cc2902df | 244 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc ZW |
245 | is the same as that represented by Y (really a ...) */ |
246 | static int | |
502b8322 | 247 | const_double_htab_eq (const void *x, const void *y) |
5692c7bc | 248 | { |
f7d504c2 | 249 | const_rtx const a = (const_rtx)x, b = (const_rtx)y; |
5692c7bc ZW |
250 | |
251 | if (GET_MODE (a) != GET_MODE (b)) | |
252 | return 0; | |
8580f7a0 RH |
253 | if (GET_MODE (a) == VOIDmode) |
254 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
255 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
256 | else | |
257 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
258 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
259 | } |
260 | ||
091a3ac7 CF |
261 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
262 | ||
263 | static hashval_t | |
264 | const_fixed_htab_hash (const void *x) | |
265 | { | |
3101faab | 266 | const_rtx const value = (const_rtx) x; |
091a3ac7 CF |
267 | hashval_t h; |
268 | ||
269 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
270 | /* MODE is used in the comparison, so it should be in the hash. */ | |
271 | h ^= GET_MODE (value); | |
272 | return h; | |
273 | } | |
274 | ||
275 | /* Returns nonzero if the value represented by X (really a ...) | |
276 | is the same as that represented by Y (really a ...). */ | |
277 | ||
278 | static int | |
279 | const_fixed_htab_eq (const void *x, const void *y) | |
280 | { | |
3101faab | 281 | const_rtx const a = (const_rtx) x, b = (const_rtx) y; |
091a3ac7 CF |
282 | |
283 | if (GET_MODE (a) != GET_MODE (b)) | |
284 | return 0; | |
285 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
286 | } | |
287 | ||
173b24b9 RK |
288 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
289 | ||
290 | static hashval_t | |
502b8322 | 291 | mem_attrs_htab_hash (const void *x) |
173b24b9 | 292 | { |
f7d504c2 | 293 | const mem_attrs *const p = (const mem_attrs *) x; |
173b24b9 RK |
294 | |
295 | return (p->alias ^ (p->align * 1000) | |
09e881c9 | 296 | ^ (p->addrspace * 4000) |
173b24b9 RK |
297 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) |
298 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
78b76d08 | 299 | ^ (size_t) iterative_hash_expr (p->expr, 0)); |
173b24b9 RK |
300 | } |
301 | ||
cc2902df | 302 | /* Returns nonzero if the value represented by X (which is really a |
173b24b9 RK |
303 | mem_attrs *) is the same as that given by Y (which is also really a |
304 | mem_attrs *). */ | |
c13e8210 MM |
305 | |
306 | static int | |
502b8322 | 307 | mem_attrs_htab_eq (const void *x, const void *y) |
c13e8210 | 308 | { |
741ac903 KG |
309 | const mem_attrs *const p = (const mem_attrs *) x; |
310 | const mem_attrs *const q = (const mem_attrs *) y; | |
173b24b9 | 311 | |
78b76d08 SB |
312 | return (p->alias == q->alias && p->offset == q->offset |
313 | && p->size == q->size && p->align == q->align | |
09e881c9 | 314 | && p->addrspace == q->addrspace |
78b76d08 SB |
315 | && (p->expr == q->expr |
316 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
317 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
318 | } |
319 | ||
173b24b9 | 320 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
10b76d73 RK |
321 | one identical to it is not already in the table. We are doing this for |
322 | MEM of mode MODE. */ | |
173b24b9 RK |
323 | |
324 | static mem_attrs * | |
4862826d | 325 | get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size, |
09e881c9 | 326 | unsigned int align, addr_space_t addrspace, enum machine_mode mode) |
173b24b9 RK |
327 | { |
328 | mem_attrs attrs; | |
329 | void **slot; | |
330 | ||
bb056a77 OH |
331 | /* If everything is the default, we can just return zero. |
332 | This must match what the corresponding MEM_* macros return when the | |
333 | field is not present. */ | |
09e881c9 | 334 | if (alias == 0 && expr == 0 && offset == 0 && addrspace == 0 |
10b76d73 RK |
335 | && (size == 0 |
336 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
bb056a77 OH |
337 | && (STRICT_ALIGNMENT && mode != BLKmode |
338 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
10b76d73 RK |
339 | return 0; |
340 | ||
173b24b9 | 341 | attrs.alias = alias; |
998d7deb | 342 | attrs.expr = expr; |
173b24b9 RK |
343 | attrs.offset = offset; |
344 | attrs.size = size; | |
345 | attrs.align = align; | |
09e881c9 | 346 | attrs.addrspace = addrspace; |
173b24b9 RK |
347 | |
348 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
349 | if (*slot == 0) | |
350 | { | |
351 | *slot = ggc_alloc (sizeof (mem_attrs)); | |
352 | memcpy (*slot, &attrs, sizeof (mem_attrs)); | |
353 | } | |
354 | ||
1b4572a8 | 355 | return (mem_attrs *) *slot; |
c13e8210 MM |
356 | } |
357 | ||
a560d4d4 JH |
358 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
359 | ||
360 | static hashval_t | |
502b8322 | 361 | reg_attrs_htab_hash (const void *x) |
a560d4d4 | 362 | { |
741ac903 | 363 | const reg_attrs *const p = (const reg_attrs *) x; |
a560d4d4 JH |
364 | |
365 | return ((p->offset * 1000) ^ (long) p->decl); | |
366 | } | |
367 | ||
6356f892 | 368 | /* Returns nonzero if the value represented by X (which is really a |
a560d4d4 JH |
369 | reg_attrs *) is the same as that given by Y (which is also really a |
370 | reg_attrs *). */ | |
371 | ||
372 | static int | |
502b8322 | 373 | reg_attrs_htab_eq (const void *x, const void *y) |
a560d4d4 | 374 | { |
741ac903 KG |
375 | const reg_attrs *const p = (const reg_attrs *) x; |
376 | const reg_attrs *const q = (const reg_attrs *) y; | |
a560d4d4 JH |
377 | |
378 | return (p->decl == q->decl && p->offset == q->offset); | |
379 | } | |
380 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
381 | one identical to it is not already in the table. We are doing this for | |
382 | MEM of mode MODE. */ | |
383 | ||
384 | static reg_attrs * | |
502b8322 | 385 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
386 | { |
387 | reg_attrs attrs; | |
388 | void **slot; | |
389 | ||
390 | /* If everything is the default, we can just return zero. */ | |
391 | if (decl == 0 && offset == 0) | |
392 | return 0; | |
393 | ||
394 | attrs.decl = decl; | |
395 | attrs.offset = offset; | |
396 | ||
397 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
398 | if (*slot == 0) | |
399 | { | |
400 | *slot = ggc_alloc (sizeof (reg_attrs)); | |
401 | memcpy (*slot, &attrs, sizeof (reg_attrs)); | |
402 | } | |
403 | ||
1b4572a8 | 404 | return (reg_attrs *) *slot; |
a560d4d4 JH |
405 | } |
406 | ||
6fb5fa3c DB |
407 | |
408 | #if !HAVE_blockage | |
409 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule | |
410 | across this insn. */ | |
411 | ||
412 | rtx | |
413 | gen_blockage (void) | |
414 | { | |
415 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
416 | MEM_VOLATILE_P (x) = true; | |
417 | return x; | |
418 | } | |
419 | #endif | |
420 | ||
421 | ||
08394eef BS |
422 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
423 | don't attempt to share with the various global pieces of rtl (such as | |
424 | frame_pointer_rtx). */ | |
425 | ||
426 | rtx | |
502b8322 | 427 | gen_raw_REG (enum machine_mode mode, int regno) |
08394eef BS |
428 | { |
429 | rtx x = gen_rtx_raw_REG (mode, regno); | |
430 | ORIGINAL_REGNO (x) = regno; | |
431 | return x; | |
432 | } | |
433 | ||
c5c76735 JL |
434 | /* There are some RTL codes that require special attention; the generation |
435 | functions do the raw handling. If you add to this list, modify | |
436 | special_rtx in gengenrtl.c as well. */ | |
437 | ||
3b80f6ca | 438 | rtx |
502b8322 | 439 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca | 440 | { |
c13e8210 MM |
441 | void **slot; |
442 | ||
3b80f6ca | 443 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 444 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
445 | |
446 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
447 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
448 | return const_true_rtx; | |
449 | #endif | |
450 | ||
c13e8210 | 451 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
452 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
453 | (hashval_t) arg, INSERT); | |
29105cea | 454 | if (*slot == 0) |
1f8f4a0b | 455 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
456 | |
457 | return (rtx) *slot; | |
3b80f6ca RH |
458 | } |
459 | ||
2496c7bd | 460 | rtx |
502b8322 | 461 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2496c7bd LB |
462 | { |
463 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
464 | } | |
465 | ||
5692c7bc ZW |
466 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
467 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
468 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
469 | ||
470 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
471 | hash table. If so, return its counterpart; otherwise add it | |
472 | to the hash table and return it. */ | |
473 | static rtx | |
502b8322 | 474 | lookup_const_double (rtx real) |
5692c7bc ZW |
475 | { |
476 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
477 | if (*slot == 0) | |
478 | *slot = real; | |
479 | ||
480 | return (rtx) *slot; | |
481 | } | |
29105cea | 482 | |
5692c7bc ZW |
483 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
484 | VALUE in mode MODE. */ | |
0133b7d9 | 485 | rtx |
502b8322 | 486 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
0133b7d9 | 487 | { |
5692c7bc ZW |
488 | rtx real = rtx_alloc (CONST_DOUBLE); |
489 | PUT_MODE (real, mode); | |
490 | ||
9e254451 | 491 | real->u.rv = value; |
5692c7bc ZW |
492 | |
493 | return lookup_const_double (real); | |
494 | } | |
495 | ||
091a3ac7 CF |
496 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
497 | hash table. If so, return its counterpart; otherwise add it | |
498 | to the hash table and return it. */ | |
499 | ||
500 | static rtx | |
501 | lookup_const_fixed (rtx fixed) | |
502 | { | |
503 | void **slot = htab_find_slot (const_fixed_htab, fixed, INSERT); | |
504 | if (*slot == 0) | |
505 | *slot = fixed; | |
506 | ||
507 | return (rtx) *slot; | |
508 | } | |
509 | ||
510 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
511 | VALUE in mode MODE. */ | |
512 | ||
513 | rtx | |
514 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, enum machine_mode mode) | |
515 | { | |
516 | rtx fixed = rtx_alloc (CONST_FIXED); | |
517 | PUT_MODE (fixed, mode); | |
518 | ||
519 | fixed->u.fv = value; | |
520 | ||
521 | return lookup_const_fixed (fixed); | |
522 | } | |
523 | ||
5692c7bc ZW |
524 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
525 | of ints: I0 is the low-order word and I1 is the high-order word. | |
526 | Do not use this routine for non-integer modes; convert to | |
527 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
528 | ||
529 | rtx | |
502b8322 | 530 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
5692c7bc ZW |
531 | { |
532 | rtx value; | |
533 | unsigned int i; | |
534 | ||
65acccdd ZD |
535 | /* There are the following cases (note that there are no modes with |
536 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT): | |
537 | ||
538 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
539 | gen_int_mode. | |
540 | 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of | |
541 | the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only | |
542 | from copies of the sign bit, and sign of i0 and i1 are the same), then | |
543 | we return a CONST_INT for i0. | |
544 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ | |
5692c7bc ZW |
545 | if (mode != VOIDmode) |
546 | { | |
5b0264cb NS |
547 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
548 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
549 | /* We can get a 0 for an error mark. */ | |
550 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
551 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT); | |
5692c7bc | 552 | |
65acccdd ZD |
553 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
554 | return gen_int_mode (i0, mode); | |
555 | ||
556 | gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT); | |
5692c7bc ZW |
557 | } |
558 | ||
559 | /* If this integer fits in one word, return a CONST_INT. */ | |
560 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
561 | return GEN_INT (i0); | |
562 | ||
563 | /* We use VOIDmode for integers. */ | |
564 | value = rtx_alloc (CONST_DOUBLE); | |
565 | PUT_MODE (value, VOIDmode); | |
566 | ||
567 | CONST_DOUBLE_LOW (value) = i0; | |
568 | CONST_DOUBLE_HIGH (value) = i1; | |
569 | ||
570 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
571 | XWINT (value, i) = 0; | |
572 | ||
573 | return lookup_const_double (value); | |
0133b7d9 RH |
574 | } |
575 | ||
3b80f6ca | 576 | rtx |
502b8322 | 577 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3b80f6ca RH |
578 | { |
579 | /* In case the MD file explicitly references the frame pointer, have | |
580 | all such references point to the same frame pointer. This is | |
581 | used during frame pointer elimination to distinguish the explicit | |
582 | references to these registers from pseudos that happened to be | |
583 | assigned to them. | |
584 | ||
585 | If we have eliminated the frame pointer or arg pointer, we will | |
586 | be using it as a normal register, for example as a spill | |
587 | register. In such cases, we might be accessing it in a mode that | |
588 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
589 | ||
590 | Also don't do this when we are making new REGs in reload, since | |
591 | we don't want to get confused with the real pointers. */ | |
592 | ||
593 | if (mode == Pmode && !reload_in_progress) | |
594 | { | |
e10c79fe LB |
595 | if (regno == FRAME_POINTER_REGNUM |
596 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
597 | return frame_pointer_rtx; |
598 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e10c79fe LB |
599 | if (regno == HARD_FRAME_POINTER_REGNUM |
600 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
601 | return hard_frame_pointer_rtx; |
602 | #endif | |
603 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 604 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
605 | return arg_pointer_rtx; |
606 | #endif | |
607 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 608 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
609 | return return_address_pointer_rtx; |
610 | #endif | |
fc555370 | 611 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
2d67bd7b | 612 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 613 | return pic_offset_table_rtx; |
bcb33994 | 614 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
615 | return stack_pointer_rtx; |
616 | } | |
617 | ||
006a94b0 | 618 | #if 0 |
6cde4876 | 619 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
620 | an existing entry in that table to avoid useless generation of RTL. |
621 | ||
622 | This code is disabled for now until we can fix the various backends | |
623 | which depend on having non-shared hard registers in some cases. Long | |
624 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
625 | on the amount of useless RTL that gets generated. |
626 | ||
627 | We'll also need to fix some code that runs after reload that wants to | |
628 | set ORIGINAL_REGNO. */ | |
629 | ||
6cde4876 JL |
630 | if (cfun |
631 | && cfun->emit | |
632 | && regno_reg_rtx | |
633 | && regno < FIRST_PSEUDO_REGISTER | |
634 | && reg_raw_mode[regno] == mode) | |
635 | return regno_reg_rtx[regno]; | |
006a94b0 | 636 | #endif |
6cde4876 | 637 | |
08394eef | 638 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
639 | } |
640 | ||
41472af8 | 641 | rtx |
502b8322 | 642 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
41472af8 MM |
643 | { |
644 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
645 | ||
646 | /* This field is not cleared by the mere allocation of the rtx, so | |
647 | we clear it here. */ | |
173b24b9 | 648 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
649 | |
650 | return rt; | |
651 | } | |
ddef6bc7 | 652 | |
542a8afa RH |
653 | /* Generate a memory referring to non-trapping constant memory. */ |
654 | ||
655 | rtx | |
656 | gen_const_mem (enum machine_mode mode, rtx addr) | |
657 | { | |
658 | rtx mem = gen_rtx_MEM (mode, addr); | |
659 | MEM_READONLY_P (mem) = 1; | |
660 | MEM_NOTRAP_P (mem) = 1; | |
661 | return mem; | |
662 | } | |
663 | ||
bf877a76 R |
664 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
665 | save areas. */ | |
666 | ||
667 | rtx | |
668 | gen_frame_mem (enum machine_mode mode, rtx addr) | |
669 | { | |
670 | rtx mem = gen_rtx_MEM (mode, addr); | |
671 | MEM_NOTRAP_P (mem) = 1; | |
672 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
673 | return mem; | |
674 | } | |
675 | ||
676 | /* Generate a MEM referring to a temporary use of the stack, not part | |
677 | of the fixed stack frame. For example, something which is pushed | |
678 | by a target splitter. */ | |
679 | rtx | |
680 | gen_tmp_stack_mem (enum machine_mode mode, rtx addr) | |
681 | { | |
682 | rtx mem = gen_rtx_MEM (mode, addr); | |
683 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 684 | if (!cfun->calls_alloca) |
bf877a76 R |
685 | set_mem_alias_set (mem, get_frame_alias_set ()); |
686 | return mem; | |
687 | } | |
688 | ||
beb72684 RH |
689 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
690 | this construct would be valid, and false otherwise. */ | |
691 | ||
692 | bool | |
693 | validate_subreg (enum machine_mode omode, enum machine_mode imode, | |
ed7a4b4b | 694 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 695 | { |
beb72684 RH |
696 | unsigned int isize = GET_MODE_SIZE (imode); |
697 | unsigned int osize = GET_MODE_SIZE (omode); | |
698 | ||
699 | /* All subregs must be aligned. */ | |
700 | if (offset % osize != 0) | |
701 | return false; | |
702 | ||
703 | /* The subreg offset cannot be outside the inner object. */ | |
704 | if (offset >= isize) | |
705 | return false; | |
706 | ||
707 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
708 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
709 | Generally, backends are doing something sketchy but it'll take time to | |
710 | fix them all. */ | |
711 | if (omode == word_mode) | |
712 | ; | |
713 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
714 | is the culprit here, and not the backends. */ | |
715 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
716 | ; | |
717 | /* Allow component subregs of complex and vector. Though given the below | |
718 | extraction rules, it's not always clear what that means. */ | |
719 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
720 | && GET_MODE_INNER (imode) == omode) | |
721 | ; | |
722 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
723 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
724 | represent this. It's questionable if this ought to be represented at | |
725 | all -- why can't this all be hidden in post-reload splitters that make | |
726 | arbitrarily mode changes to the registers themselves. */ | |
727 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
728 | ; | |
729 | /* Subregs involving floating point modes are not allowed to | |
730 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
731 | (subreg:SI (reg:DF) 0) isn't. */ | |
732 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
733 | { | |
734 | if (isize != osize) | |
735 | return false; | |
736 | } | |
ddef6bc7 | 737 | |
beb72684 RH |
738 | /* Paradoxical subregs must have offset zero. */ |
739 | if (osize > isize) | |
740 | return offset == 0; | |
741 | ||
742 | /* This is a normal subreg. Verify that the offset is representable. */ | |
743 | ||
744 | /* For hard registers, we already have most of these rules collected in | |
745 | subreg_offset_representable_p. */ | |
746 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
747 | { | |
748 | unsigned int regno = REGNO (reg); | |
749 | ||
750 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
751 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
752 | && GET_MODE_INNER (imode) == omode) | |
753 | ; | |
754 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
755 | return false; | |
ddef6bc7 | 756 | #endif |
beb72684 RH |
757 | |
758 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
759 | } | |
760 | ||
761 | /* For pseudo registers, we want most of the same checks. Namely: | |
762 | If the register no larger than a word, the subreg must be lowpart. | |
763 | If the register is larger than a word, the subreg must be the lowpart | |
764 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
765 | Given that we've already checked mode/offset alignment, we only have | |
766 | to check subword subregs here. */ | |
767 | if (osize < UNITS_PER_WORD) | |
768 | { | |
769 | enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; | |
770 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); | |
771 | if (offset % UNITS_PER_WORD != low_off) | |
772 | return false; | |
773 | } | |
774 | return true; | |
775 | } | |
776 | ||
777 | rtx | |
778 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) | |
779 | { | |
780 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 781 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
782 | } |
783 | ||
173b24b9 RK |
784 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
785 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
786 | ||
ddef6bc7 | 787 | rtx |
502b8322 | 788 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
ddef6bc7 JJ |
789 | { |
790 | enum machine_mode inmode; | |
ddef6bc7 JJ |
791 | |
792 | inmode = GET_MODE (reg); | |
793 | if (inmode == VOIDmode) | |
794 | inmode = mode; | |
e0e08ac2 JH |
795 | return gen_rtx_SUBREG (mode, reg, |
796 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 797 | } |
c5c76735 | 798 | \f |
23b2ce53 | 799 | |
80379f51 PB |
800 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
801 | ||
23b2ce53 | 802 | rtvec |
e34d07f2 | 803 | gen_rtvec (int n, ...) |
23b2ce53 | 804 | { |
80379f51 PB |
805 | int i; |
806 | rtvec rt_val; | |
e34d07f2 | 807 | va_list p; |
23b2ce53 | 808 | |
e34d07f2 | 809 | va_start (p, n); |
23b2ce53 | 810 | |
80379f51 | 811 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 812 | if (n == 0) |
80379f51 | 813 | return NULL_RTVEC; |
23b2ce53 | 814 | |
80379f51 | 815 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 816 | |
23b2ce53 | 817 | for (i = 0; i < n; i++) |
80379f51 | 818 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 819 | |
e34d07f2 | 820 | va_end (p); |
80379f51 | 821 | return rt_val; |
23b2ce53 RS |
822 | } |
823 | ||
824 | rtvec | |
502b8322 | 825 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 826 | { |
b3694847 SS |
827 | int i; |
828 | rtvec rt_val; | |
23b2ce53 | 829 | |
80379f51 | 830 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 831 | if (n == 0) |
80379f51 | 832 | return NULL_RTVEC; |
23b2ce53 | 833 | |
80379f51 | 834 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
835 | |
836 | for (i = 0; i < n; i++) | |
8f985ec4 | 837 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
838 | |
839 | return rt_val; | |
840 | } | |
841 | \f | |
38ae7651 RS |
842 | /* Return the number of bytes between the start of an OUTER_MODE |
843 | in-memory value and the start of an INNER_MODE in-memory value, | |
844 | given that the former is a lowpart of the latter. It may be a | |
845 | paradoxical lowpart, in which case the offset will be negative | |
846 | on big-endian targets. */ | |
847 | ||
848 | int | |
849 | byte_lowpart_offset (enum machine_mode outer_mode, | |
850 | enum machine_mode inner_mode) | |
851 | { | |
852 | if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)) | |
853 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
854 | else | |
855 | return -subreg_lowpart_offset (inner_mode, outer_mode); | |
856 | } | |
857 | \f | |
23b2ce53 RS |
858 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
859 | This pseudo is assigned the next sequential register number. */ | |
860 | ||
861 | rtx | |
502b8322 | 862 | gen_reg_rtx (enum machine_mode mode) |
23b2ce53 | 863 | { |
b3694847 | 864 | rtx val; |
2e3f842f | 865 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 866 | |
f8335a4f | 867 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 868 | |
2e3f842f L |
869 | /* If a virtual register with bigger mode alignment is generated, |
870 | increase stack alignment estimation because it might be spilled | |
871 | to stack later. */ | |
872 | if (SUPPORTS_STACK_ALIGNMENT | |
873 | && crtl->stack_alignment_estimated < align | |
874 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
875 | { |
876 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
877 | if (crtl->stack_alignment_estimated < min_align) | |
878 | crtl->stack_alignment_estimated = min_align; | |
879 | } | |
2e3f842f | 880 | |
1b3d8f8a GK |
881 | if (generating_concat_p |
882 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
883 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
884 | { |
885 | /* For complex modes, don't make a single pseudo. | |
886 | Instead, make a CONCAT of two pseudos. | |
887 | This allows noncontiguous allocation of the real and imaginary parts, | |
888 | which makes much better code. Besides, allocating DCmode | |
889 | pseudos overstrains reload on some machines like the 386. */ | |
890 | rtx realpart, imagpart; | |
27e58a70 | 891 | enum machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
892 | |
893 | realpart = gen_reg_rtx (partmode); | |
894 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 895 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
896 | } |
897 | ||
a560d4d4 | 898 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 899 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 900 | |
3e029763 | 901 | if (reg_rtx_no == crtl->emit.regno_pointer_align_length) |
23b2ce53 | 902 | { |
3e029763 | 903 | int old_size = crtl->emit.regno_pointer_align_length; |
60564289 | 904 | char *tmp; |
0d4903b8 | 905 | rtx *new1; |
0d4903b8 | 906 | |
60564289 KG |
907 | tmp = XRESIZEVEC (char, crtl->emit.regno_pointer_align, old_size * 2); |
908 | memset (tmp + old_size, 0, old_size); | |
909 | crtl->emit.regno_pointer_align = (unsigned char *) tmp; | |
49ad7cfa | 910 | |
1b4572a8 | 911 | new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, old_size * 2); |
49ad7cfa | 912 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
913 | regno_reg_rtx = new1; |
914 | ||
3e029763 | 915 | crtl->emit.regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
916 | } |
917 | ||
08394eef | 918 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
919 | regno_reg_rtx[reg_rtx_no++] = val; |
920 | return val; | |
921 | } | |
922 | ||
38ae7651 RS |
923 | /* Update NEW with the same attributes as REG, but with OFFSET added |
924 | to the REG_OFFSET. */ | |
a560d4d4 | 925 | |
e53a16e7 | 926 | static void |
60564289 | 927 | update_reg_offset (rtx new_rtx, rtx reg, int offset) |
a560d4d4 | 928 | { |
60564289 | 929 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 930 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
931 | } |
932 | ||
38ae7651 RS |
933 | /* Generate a register with same attributes as REG, but with OFFSET |
934 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
935 | |
936 | rtx | |
937 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, | |
938 | int offset) | |
939 | { | |
60564289 | 940 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 941 | |
60564289 KG |
942 | update_reg_offset (new_rtx, reg, offset); |
943 | return new_rtx; | |
e53a16e7 ILT |
944 | } |
945 | ||
946 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 947 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
948 | |
949 | rtx | |
950 | gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset) | |
951 | { | |
60564289 | 952 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 953 | |
60564289 KG |
954 | update_reg_offset (new_rtx, reg, offset); |
955 | return new_rtx; | |
a560d4d4 JH |
956 | } |
957 | ||
38ae7651 RS |
958 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
959 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
960 | |
961 | void | |
38ae7651 | 962 | adjust_reg_mode (rtx reg, enum machine_mode mode) |
a560d4d4 | 963 | { |
38ae7651 RS |
964 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
965 | PUT_MODE (reg, mode); | |
966 | } | |
967 | ||
968 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
969 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
970 | ||
971 | void | |
972 | set_reg_attrs_from_value (rtx reg, rtx x) | |
973 | { | |
974 | int offset; | |
975 | ||
923ba36f JJ |
976 | /* Hard registers can be reused for multiple purposes within the same |
977 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
978 | on them is wrong. */ | |
979 | if (HARD_REGISTER_P (reg)) | |
980 | return; | |
981 | ||
38ae7651 | 982 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
983 | if (MEM_P (x)) |
984 | { | |
481683e1 | 985 | if (MEM_OFFSET (x) && CONST_INT_P (MEM_OFFSET (x))) |
46b71b03 PB |
986 | REG_ATTRS (reg) |
987 | = get_reg_attrs (MEM_EXPR (x), INTVAL (MEM_OFFSET (x)) + offset); | |
988 | if (MEM_POINTER (x)) | |
0a317111 | 989 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
990 | } |
991 | else if (REG_P (x)) | |
992 | { | |
993 | if (REG_ATTRS (x)) | |
994 | update_reg_offset (reg, x, offset); | |
995 | if (REG_POINTER (x)) | |
996 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); | |
997 | } | |
998 | } | |
999 | ||
1000 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
1001 | and attributes from X. */ | |
1002 | ||
1003 | rtx | |
1004 | gen_reg_rtx_and_attrs (rtx x) | |
1005 | { | |
1006 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1007 | set_reg_attrs_from_value (reg, x); | |
1008 | return reg; | |
a560d4d4 JH |
1009 | } |
1010 | ||
9d18e06b JZ |
1011 | /* Set the register attributes for registers contained in PARM_RTX. |
1012 | Use needed values from memory attributes of MEM. */ | |
1013 | ||
1014 | void | |
502b8322 | 1015 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1016 | { |
f8cfc6aa | 1017 | if (REG_P (parm_rtx)) |
38ae7651 | 1018 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1019 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1020 | { | |
1021 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1022 | parameter goes both on the stack and in registers. */ | |
1023 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1024 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1025 | { | |
1026 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1027 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1028 | REG_ATTRS (XEXP (x, 0)) |
1029 | = get_reg_attrs (MEM_EXPR (mem), | |
1030 | INTVAL (XEXP (x, 1))); | |
1031 | } | |
1032 | } | |
1033 | } | |
1034 | ||
38ae7651 RS |
1035 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1036 | decl T. */ | |
a560d4d4 | 1037 | |
4e3825db | 1038 | void |
38ae7651 RS |
1039 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1040 | { | |
1041 | if (GET_CODE (x) == SUBREG) | |
fbe6ec81 | 1042 | { |
38ae7651 RS |
1043 | gcc_assert (subreg_lowpart_p (x)); |
1044 | x = SUBREG_REG (x); | |
fbe6ec81 | 1045 | } |
f8cfc6aa | 1046 | if (REG_P (x)) |
38ae7651 RS |
1047 | REG_ATTRS (x) |
1048 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
726612d2 | 1049 | DECL_MODE (t))); |
a560d4d4 JH |
1050 | if (GET_CODE (x) == CONCAT) |
1051 | { | |
1052 | if (REG_P (XEXP (x, 0))) | |
1053 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1054 | if (REG_P (XEXP (x, 1))) | |
1055 | REG_ATTRS (XEXP (x, 1)) | |
1056 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1057 | } | |
1058 | if (GET_CODE (x) == PARALLEL) | |
1059 | { | |
d4afac5b JZ |
1060 | int i, start; |
1061 | ||
1062 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1063 | both on the stack and in registers. */ | |
1064 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1065 | start = 0; | |
1066 | else | |
1067 | start = 1; | |
1068 | ||
1069 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1070 | { |
1071 | rtx y = XVECEXP (x, 0, i); | |
1072 | if (REG_P (XEXP (y, 0))) | |
1073 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1074 | } | |
1075 | } | |
1076 | } | |
1077 | ||
38ae7651 RS |
1078 | /* Assign the RTX X to declaration T. */ |
1079 | ||
1080 | void | |
1081 | set_decl_rtl (tree t, rtx x) | |
1082 | { | |
1083 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1084 | if (x) | |
1085 | set_reg_attrs_for_decl_rtl (t, x); | |
1086 | } | |
1087 | ||
5141868d RS |
1088 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1089 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1090 | |
1091 | void | |
5141868d | 1092 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1093 | { |
1094 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1095 | if (x && !by_reference_p) |
38ae7651 RS |
1096 | set_reg_attrs_for_decl_rtl (t, x); |
1097 | } | |
1098 | ||
754fdcca RK |
1099 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1100 | ||
1101 | void | |
502b8322 | 1102 | mark_user_reg (rtx reg) |
754fdcca RK |
1103 | { |
1104 | if (GET_CODE (reg) == CONCAT) | |
1105 | { | |
1106 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1107 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1108 | } | |
754fdcca | 1109 | else |
5b0264cb NS |
1110 | { |
1111 | gcc_assert (REG_P (reg)); | |
1112 | REG_USERVAR_P (reg) = 1; | |
1113 | } | |
754fdcca RK |
1114 | } |
1115 | ||
86fe05e0 RK |
1116 | /* Identify REG as a probable pointer register and show its alignment |
1117 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1118 | |
1119 | void | |
502b8322 | 1120 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1121 | { |
3502dc9c | 1122 | if (! REG_POINTER (reg)) |
00995e78 | 1123 | { |
3502dc9c | 1124 | REG_POINTER (reg) = 1; |
86fe05e0 | 1125 | |
00995e78 RE |
1126 | if (align) |
1127 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1128 | } | |
1129 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1130 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1131 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1132 | } |
1133 | ||
1134 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1135 | ||
1136 | int | |
502b8322 | 1137 | max_reg_num (void) |
23b2ce53 RS |
1138 | { |
1139 | return reg_rtx_no; | |
1140 | } | |
1141 | ||
1142 | /* Return 1 + the largest label number used so far in the current function. */ | |
1143 | ||
1144 | int | |
502b8322 | 1145 | max_label_num (void) |
23b2ce53 | 1146 | { |
23b2ce53 RS |
1147 | return label_num; |
1148 | } | |
1149 | ||
1150 | /* Return first label number used in this function (if any were used). */ | |
1151 | ||
1152 | int | |
502b8322 | 1153 | get_first_label_num (void) |
23b2ce53 RS |
1154 | { |
1155 | return first_label_num; | |
1156 | } | |
6de9cd9a DN |
1157 | |
1158 | /* If the rtx for label was created during the expansion of a nested | |
1159 | function, then first_label_num won't include this label number. | |
fa10beec | 1160 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1161 | |
1162 | void | |
1163 | maybe_set_first_label_num (rtx x) | |
1164 | { | |
1165 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1166 | first_label_num = CODE_LABEL_NUMBER (x); | |
1167 | } | |
23b2ce53 RS |
1168 | \f |
1169 | /* Return a value representing some low-order bits of X, where the number | |
1170 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1171 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1172 | representation is returned. |
1173 | ||
1174 | This function handles the cases in common between gen_lowpart, below, | |
1175 | and two variants in cse.c and combine.c. These are the cases that can | |
1176 | be safely handled at all points in the compilation. | |
1177 | ||
1178 | If this is not a case we can handle, return 0. */ | |
1179 | ||
1180 | rtx | |
502b8322 | 1181 | gen_lowpart_common (enum machine_mode mode, rtx x) |
23b2ce53 | 1182 | { |
ddef6bc7 | 1183 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1184 | int xsize; |
ddef6bc7 | 1185 | int offset = 0; |
550d1387 GK |
1186 | enum machine_mode innermode; |
1187 | ||
1188 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1189 | so we have to make one up. Yuk. */ | |
1190 | innermode = GET_MODE (x); | |
481683e1 | 1191 | if (CONST_INT_P (x) |
db487452 | 1192 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) |
550d1387 GK |
1193 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1194 | else if (innermode == VOIDmode) | |
1195 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0); | |
1196 | ||
1197 | xsize = GET_MODE_SIZE (innermode); | |
1198 | ||
5b0264cb | 1199 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1200 | |
550d1387 | 1201 | if (innermode == mode) |
23b2ce53 RS |
1202 | return x; |
1203 | ||
1204 | /* MODE must occupy no more words than the mode of X. */ | |
550d1387 GK |
1205 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1206 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
23b2ce53 RS |
1207 | return 0; |
1208 | ||
53501a19 | 1209 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
3d8bf70f | 1210 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
53501a19 BS |
1211 | return 0; |
1212 | ||
550d1387 | 1213 | offset = subreg_lowpart_offset (mode, innermode); |
23b2ce53 RS |
1214 | |
1215 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1216 | && (GET_MODE_CLASS (mode) == MODE_INT |
1217 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1218 | { |
1219 | /* If we are getting the low-order part of something that has been | |
1220 | sign- or zero-extended, we can either just use the object being | |
1221 | extended or make a narrower extension. If we want an even smaller | |
1222 | piece than the size of the object being extended, call ourselves | |
1223 | recursively. | |
1224 | ||
1225 | This case is used mostly by combine and cse. */ | |
1226 | ||
1227 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1228 | return XEXP (x, 0); | |
550d1387 | 1229 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
23b2ce53 | 1230 | return gen_lowpart_common (mode, XEXP (x, 0)); |
550d1387 | 1231 | else if (msize < xsize) |
3b80f6ca | 1232 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1233 | } |
f8cfc6aa | 1234 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
550d1387 | 1235 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
481683e1 | 1236 | || GET_CODE (x) == CONST_DOUBLE || CONST_INT_P (x)) |
550d1387 | 1237 | return simplify_gen_subreg (mode, x, innermode, offset); |
8aada4ad | 1238 | |
23b2ce53 RS |
1239 | /* Otherwise, we can't do this. */ |
1240 | return 0; | |
1241 | } | |
1242 | \f | |
ccba022b | 1243 | rtx |
502b8322 | 1244 | gen_highpart (enum machine_mode mode, rtx x) |
ccba022b | 1245 | { |
ddef6bc7 | 1246 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1247 | rtx result; |
ddef6bc7 | 1248 | |
ccba022b RS |
1249 | /* This case loses if X is a subreg. To catch bugs early, |
1250 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1251 | gcc_assert (msize <= UNITS_PER_WORD |
1252 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1253 | |
e0e08ac2 JH |
1254 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1255 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb NS |
1256 | gcc_assert (result); |
1257 | ||
09482e0d JW |
1258 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1259 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1260 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1261 | if (MEM_P (result)) |
1262 | { | |
1263 | result = validize_mem (result); | |
1264 | gcc_assert (result); | |
1265 | } | |
1266 | ||
e0e08ac2 JH |
1267 | return result; |
1268 | } | |
5222e470 | 1269 | |
26d249eb | 1270 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1271 | be VOIDmode constant. */ |
1272 | rtx | |
502b8322 | 1273 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
5222e470 JH |
1274 | { |
1275 | if (GET_MODE (exp) != VOIDmode) | |
1276 | { | |
5b0264cb | 1277 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1278 | return gen_highpart (outermode, exp); |
1279 | } | |
1280 | return simplify_gen_subreg (outermode, exp, innermode, | |
1281 | subreg_highpart_offset (outermode, innermode)); | |
1282 | } | |
68252e27 | 1283 | |
38ae7651 | 1284 | /* Return the SUBREG_BYTE for an OUTERMODE lowpart of an INNERMODE value. */ |
8698cce3 | 1285 | |
e0e08ac2 | 1286 | unsigned int |
502b8322 | 1287 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
e0e08ac2 JH |
1288 | { |
1289 | unsigned int offset = 0; | |
1290 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1291 | |
e0e08ac2 | 1292 | if (difference > 0) |
ccba022b | 1293 | { |
e0e08ac2 JH |
1294 | if (WORDS_BIG_ENDIAN) |
1295 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1296 | if (BYTES_BIG_ENDIAN) | |
1297 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1298 | } |
ddef6bc7 | 1299 | |
e0e08ac2 | 1300 | return offset; |
ccba022b | 1301 | } |
eea50aa0 | 1302 | |
e0e08ac2 JH |
1303 | /* Return offset in bytes to get OUTERMODE high part |
1304 | of the value in mode INNERMODE stored in memory in target format. */ | |
1305 | unsigned int | |
502b8322 | 1306 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
eea50aa0 JH |
1307 | { |
1308 | unsigned int offset = 0; | |
1309 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1310 | ||
5b0264cb | 1311 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
e0e08ac2 | 1312 | |
eea50aa0 JH |
1313 | if (difference > 0) |
1314 | { | |
e0e08ac2 | 1315 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1316 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1317 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1318 | offset += difference % UNITS_PER_WORD; |
1319 | } | |
1320 | ||
e0e08ac2 | 1321 | return offset; |
eea50aa0 | 1322 | } |
ccba022b | 1323 | |
23b2ce53 RS |
1324 | /* Return 1 iff X, assumed to be a SUBREG, |
1325 | refers to the least significant part of its containing reg. | |
1326 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1327 | ||
1328 | int | |
fa233e34 | 1329 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1330 | { |
1331 | if (GET_CODE (x) != SUBREG) | |
1332 | return 1; | |
a3a03040 RK |
1333 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1334 | return 0; | |
23b2ce53 | 1335 | |
e0e08ac2 JH |
1336 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1337 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1338 | } |
1339 | \f | |
ddef6bc7 JJ |
1340 | /* Return subword OFFSET of operand OP. |
1341 | The word number, OFFSET, is interpreted as the word number starting | |
1342 | at the low-order address. OFFSET 0 is the low-order word if not | |
1343 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1344 | ||
1345 | If we cannot extract the required word, we return zero. Otherwise, | |
1346 | an rtx corresponding to the requested word will be returned. | |
1347 | ||
1348 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1349 | reload has completed, a valid address will always be returned. After | |
1350 | reload, if a valid address cannot be returned, we return zero. | |
1351 | ||
1352 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1353 | it is the responsibility of the caller. | |
1354 | ||
1355 | MODE is the mode of OP in case it is a CONST_INT. | |
1356 | ||
1357 | ??? This is still rather broken for some cases. The problem for the | |
1358 | moment is that all callers of this thing provide no 'goal mode' to | |
1359 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1360 | in a word based SUBREG world. |
1361 | Now use of this function can be deprecated by simplify_subreg in most | |
1362 | cases. | |
1363 | */ | |
ddef6bc7 JJ |
1364 | |
1365 | rtx | |
502b8322 | 1366 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
ddef6bc7 JJ |
1367 | { |
1368 | if (mode == VOIDmode) | |
1369 | mode = GET_MODE (op); | |
1370 | ||
5b0264cb | 1371 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1372 | |
30f7a378 | 1373 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1374 | if (mode != BLKmode |
1375 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1376 | return 0; | |
1377 | ||
30f7a378 | 1378 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1379 | if (mode != BLKmode |
1380 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1381 | return const0_rtx; | |
1382 | ||
ddef6bc7 | 1383 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1384 | if (MEM_P (op)) |
ddef6bc7 | 1385 | { |
60564289 | 1386 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1387 | |
f1ec5147 | 1388 | if (! validate_address) |
60564289 | 1389 | return new_rtx; |
f1ec5147 RK |
1390 | |
1391 | else if (reload_completed) | |
ddef6bc7 | 1392 | { |
09e881c9 BE |
1393 | if (! strict_memory_address_addr_space_p (word_mode, |
1394 | XEXP (new_rtx, 0), | |
1395 | MEM_ADDR_SPACE (op))) | |
f1ec5147 | 1396 | return 0; |
ddef6bc7 | 1397 | } |
f1ec5147 | 1398 | else |
60564289 | 1399 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1400 | } |
1401 | ||
0631e0bf JH |
1402 | /* Rest can be handled by simplify_subreg. */ |
1403 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1404 | } |
1405 | ||
535a42b1 NS |
1406 | /* Similar to `operand_subword', but never return 0. If we can't |
1407 | extract the required subword, put OP into a register and try again. | |
1408 | The second attempt must succeed. We always validate the address in | |
1409 | this case. | |
23b2ce53 RS |
1410 | |
1411 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1412 | ||
1413 | rtx | |
502b8322 | 1414 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
23b2ce53 | 1415 | { |
ddef6bc7 | 1416 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1417 | |
1418 | if (result) | |
1419 | return result; | |
1420 | ||
1421 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1422 | { |
1423 | /* If this is a register which can not be accessed by words, copy it | |
1424 | to a pseudo register. */ | |
f8cfc6aa | 1425 | if (REG_P (op)) |
77e6b0eb JC |
1426 | op = copy_to_reg (op); |
1427 | else | |
1428 | op = force_reg (mode, op); | |
1429 | } | |
23b2ce53 | 1430 | |
ddef6bc7 | 1431 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1432 | gcc_assert (result); |
23b2ce53 RS |
1433 | |
1434 | return result; | |
1435 | } | |
1436 | \f | |
2b3493c8 AK |
1437 | /* Returns 1 if both MEM_EXPR can be considered equal |
1438 | and 0 otherwise. */ | |
1439 | ||
1440 | int | |
4f588890 | 1441 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1442 | { |
1443 | if (expr1 == expr2) | |
1444 | return 1; | |
1445 | ||
1446 | if (! expr1 || ! expr2) | |
1447 | return 0; | |
1448 | ||
1449 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1450 | return 0; | |
1451 | ||
55b34b5f | 1452 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1453 | } |
1454 | ||
805903b5 JJ |
1455 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1456 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1457 | -1 if not known. */ | |
1458 | ||
1459 | int | |
d9223014 | 1460 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1461 | { |
1462 | tree expr; | |
1463 | unsigned HOST_WIDE_INT offset; | |
1464 | ||
1465 | /* This function can't use | |
1466 | if (!MEM_EXPR (mem) || !MEM_OFFSET (mem) | |
1467 | || !CONST_INT_P (MEM_OFFSET (mem)) | |
1468 | || (get_object_alignment (MEM_EXPR (mem), MEM_ALIGN (mem), align) | |
1469 | < align)) | |
1470 | return -1; | |
1471 | else | |
1472 | return (- INTVAL (MEM_OFFSET (mem))) & (align / BITS_PER_UNIT - 1); | |
1473 | for two reasons: | |
1474 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1475 | for <variable>. get_inner_reference doesn't handle it and | |
1476 | even if it did, the alignment in that case needs to be determined | |
1477 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1478 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1479 | isn't sufficiently aligned, the object it is in might be. */ | |
1480 | gcc_assert (MEM_P (mem)); | |
1481 | expr = MEM_EXPR (mem); | |
1482 | if (expr == NULL_TREE | |
1483 | || MEM_OFFSET (mem) == NULL_RTX | |
1484 | || !CONST_INT_P (MEM_OFFSET (mem))) | |
1485 | return -1; | |
1486 | ||
1487 | offset = INTVAL (MEM_OFFSET (mem)); | |
1488 | if (DECL_P (expr)) | |
1489 | { | |
1490 | if (DECL_ALIGN (expr) < align) | |
1491 | return -1; | |
1492 | } | |
1493 | else if (INDIRECT_REF_P (expr)) | |
1494 | { | |
1495 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1496 | return -1; | |
1497 | } | |
1498 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1499 | { | |
1500 | while (1) | |
1501 | { | |
1502 | tree inner = TREE_OPERAND (expr, 0); | |
1503 | tree field = TREE_OPERAND (expr, 1); | |
1504 | tree byte_offset = component_ref_field_offset (expr); | |
1505 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1506 | ||
1507 | if (!byte_offset | |
1508 | || !host_integerp (byte_offset, 1) | |
1509 | || !host_integerp (bit_offset, 1)) | |
1510 | return -1; | |
1511 | ||
1512 | offset += tree_low_cst (byte_offset, 1); | |
1513 | offset += tree_low_cst (bit_offset, 1) / BITS_PER_UNIT; | |
1514 | ||
1515 | if (inner == NULL_TREE) | |
1516 | { | |
1517 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1518 | < (unsigned int) align) | |
1519 | return -1; | |
1520 | break; | |
1521 | } | |
1522 | else if (DECL_P (inner)) | |
1523 | { | |
1524 | if (DECL_ALIGN (inner) < align) | |
1525 | return -1; | |
1526 | break; | |
1527 | } | |
1528 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1529 | return -1; | |
1530 | expr = inner; | |
1531 | } | |
1532 | } | |
1533 | else | |
1534 | return -1; | |
1535 | ||
1536 | return offset & ((align / BITS_PER_UNIT) - 1); | |
1537 | } | |
1538 | ||
6926c713 | 1539 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1540 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1541 | if we are making a new object of this type. BITPOS is nonzero if |
1542 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1543 | |
1544 | void | |
502b8322 AJ |
1545 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1546 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1547 | { |
4862826d | 1548 | alias_set_type alias = MEM_ALIAS_SET (ref); |
998d7deb | 1549 | tree expr = MEM_EXPR (ref); |
8ac61af7 RK |
1550 | rtx offset = MEM_OFFSET (ref); |
1551 | rtx size = MEM_SIZE (ref); | |
1552 | unsigned int align = MEM_ALIGN (ref); | |
6f1087be | 1553 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 RK |
1554 | tree type; |
1555 | ||
1556 | /* It can happen that type_for_mode was given a mode for which there | |
1557 | is no language-level type. In which case it returns NULL, which | |
1558 | we can see here. */ | |
1559 | if (t == NULL_TREE) | |
1560 | return; | |
1561 | ||
1562 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1563 | if (type == error_mark_node) |
1564 | return; | |
173b24b9 | 1565 | |
173b24b9 RK |
1566 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1567 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1568 | info. Callers should not set DECL_RTL until after the call to | |
1569 | set_mem_attributes. */ | |
5b0264cb | 1570 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1571 | |
738cc472 | 1572 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 RK |
1573 | front-end routine) and use it. */ |
1574 | alias = get_alias_set (t); | |
173b24b9 | 1575 | |
a5e9c810 | 1576 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
07cb6e8c JM |
1577 | MEM_IN_STRUCT_P (ref) |
1578 | = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE; | |
f8ad8d7c | 1579 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1580 | |
8ac61af7 RK |
1581 | /* If we are making an object of this type, or if this is a DECL, we know |
1582 | that it is a scalar if the type is not an aggregate. */ | |
07cb6e8c JM |
1583 | if ((objectp || DECL_P (t)) |
1584 | && ! AGGREGATE_TYPE_P (type) | |
1585 | && TREE_CODE (type) != COMPLEX_TYPE) | |
173b24b9 RK |
1586 | MEM_SCALAR_P (ref) = 1; |
1587 | ||
c3d32120 RK |
1588 | /* We can set the alignment from the type if we are making an object, |
1589 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
7ccf35ed DN |
1590 | if (objectp || TREE_CODE (t) == INDIRECT_REF |
1591 | || TREE_CODE (t) == ALIGN_INDIRECT_REF | |
1592 | || TYPE_ALIGN_OK (type)) | |
c3d32120 | 1593 | align = MAX (align, TYPE_ALIGN (type)); |
7ccf35ed DN |
1594 | else |
1595 | if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF) | |
1596 | { | |
1597 | if (integer_zerop (TREE_OPERAND (t, 1))) | |
1598 | /* We don't know anything about the alignment. */ | |
1599 | align = BITS_PER_UNIT; | |
1600 | else | |
1601 | align = tree_low_cst (TREE_OPERAND (t, 1), 1); | |
1602 | } | |
40c0668b | 1603 | |
738cc472 RK |
1604 | /* If the size is known, we can set that. */ |
1605 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
8ac61af7 | 1606 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
738cc472 | 1607 | |
80965c18 RK |
1608 | /* If T is not a type, we may be able to deduce some more information about |
1609 | the expression. */ | |
1610 | if (! TYPE_P (t)) | |
8ac61af7 | 1611 | { |
8476af98 | 1612 | tree base; |
df96b059 | 1613 | bool align_computed = false; |
389fdba0 | 1614 | |
8ac61af7 RK |
1615 | if (TREE_THIS_VOLATILE (t)) |
1616 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1617 | |
c56e3582 RK |
1618 | /* Now remove any conversions: they don't change what the underlying |
1619 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 1620 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
1621 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
1622 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1623 | t = TREE_OPERAND (t, 0); |
1624 | ||
8476af98 RH |
1625 | /* We may look through structure-like accesses for the purposes of |
1626 | examining TREE_THIS_NOTRAP, but not array-like accesses. */ | |
1627 | base = t; | |
1628 | while (TREE_CODE (base) == COMPONENT_REF | |
1629 | || TREE_CODE (base) == REALPART_EXPR | |
1630 | || TREE_CODE (base) == IMAGPART_EXPR | |
1631 | || TREE_CODE (base) == BIT_FIELD_REF) | |
1632 | base = TREE_OPERAND (base, 0); | |
1633 | ||
1634 | if (DECL_P (base)) | |
1635 | { | |
1636 | if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS)) | |
1637 | MEM_NOTRAP_P (ref) = !DECL_WEAK (base); | |
1638 | else | |
1639 | MEM_NOTRAP_P (ref) = 1; | |
1640 | } | |
1641 | else | |
1642 | MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base); | |
1643 | ||
1644 | base = get_base_address (base); | |
1645 | if (base && DECL_P (base) | |
1646 | && TREE_READONLY (base) | |
1647 | && (TREE_STATIC (base) || DECL_EXTERNAL (base))) | |
1648 | { | |
1649 | tree base_type = TREE_TYPE (base); | |
1650 | gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type)) | |
1651 | || DECL_ARTIFICIAL (base)); | |
1652 | MEM_READONLY_P (ref) = 1; | |
1653 | } | |
1654 | ||
2039d7aa RH |
1655 | /* If this expression uses it's parent's alias set, mark it such |
1656 | that we won't change it. */ | |
1657 | if (component_uses_parent_alias_set (t)) | |
10b76d73 RK |
1658 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1659 | ||
8ac61af7 RK |
1660 | /* If this is a decl, set the attributes of the MEM from it. */ |
1661 | if (DECL_P (t)) | |
1662 | { | |
998d7deb RH |
1663 | expr = t; |
1664 | offset = const0_rtx; | |
6f1087be | 1665 | apply_bitpos = bitpos; |
8ac61af7 RK |
1666 | size = (DECL_SIZE_UNIT (t) |
1667 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1668 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
68252e27 | 1669 | align = DECL_ALIGN (t); |
df96b059 | 1670 | align_computed = true; |
8ac61af7 RK |
1671 | } |
1672 | ||
40c0668b | 1673 | /* If this is a constant, we know the alignment. */ |
6615c446 | 1674 | else if (CONSTANT_CLASS_P (t)) |
9ddfb1a7 RK |
1675 | { |
1676 | align = TYPE_ALIGN (type); | |
1677 | #ifdef CONSTANT_ALIGNMENT | |
1678 | align = CONSTANT_ALIGNMENT (t, align); | |
1679 | #endif | |
df96b059 | 1680 | align_computed = true; |
9ddfb1a7 | 1681 | } |
998d7deb RH |
1682 | |
1683 | /* If this is a field reference and not a bit-field, record it. */ | |
fa10beec | 1684 | /* ??? There is some information that can be gleaned from bit-fields, |
998d7deb RH |
1685 | such as the word offset in the structure that might be modified. |
1686 | But skip it for now. */ | |
1687 | else if (TREE_CODE (t) == COMPONENT_REF | |
1688 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1689 | { | |
55b34b5f | 1690 | expr = t; |
998d7deb | 1691 | offset = const0_rtx; |
6f1087be | 1692 | apply_bitpos = bitpos; |
998d7deb RH |
1693 | /* ??? Any reason the field size would be different than |
1694 | the size we got from the type? */ | |
1695 | } | |
1696 | ||
1697 | /* If this is an array reference, look for an outer field reference. */ | |
1698 | else if (TREE_CODE (t) == ARRAY_REF) | |
1699 | { | |
1700 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1701 | /* We can't modify t, because we use it at the end of the |
1702 | function. */ | |
1703 | tree t2 = t; | |
998d7deb RH |
1704 | |
1705 | do | |
1706 | { | |
1b1838b6 | 1707 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1708 | tree low_bound = array_ref_low_bound (t2); |
1709 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1710 | |
1711 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1712 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1713 | index, then convert to sizetype and multiply by the size of |
1714 | the array element. */ | |
1715 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1716 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1717 | index, low_bound); | |
2567406a | 1718 | |
44de5aeb | 1719 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1720 | size_binop (MULT_EXPR, |
1721 | fold_convert (sizetype, | |
1722 | index), | |
44de5aeb RK |
1723 | unit_size), |
1724 | off_tree); | |
1b1838b6 | 1725 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1726 | } |
1b1838b6 | 1727 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1728 | |
1b1838b6 | 1729 | if (DECL_P (t2)) |
c67a1cf6 | 1730 | { |
1b1838b6 | 1731 | expr = t2; |
40cb04f1 | 1732 | offset = NULL; |
c67a1cf6 | 1733 | if (host_integerp (off_tree, 1)) |
40cb04f1 RH |
1734 | { |
1735 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1736 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1b1838b6 | 1737 | align = DECL_ALIGN (t2); |
fc555370 | 1738 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
40cb04f1 | 1739 | align = aoff; |
df96b059 | 1740 | align_computed = true; |
40cb04f1 | 1741 | offset = GEN_INT (ioff); |
6f1087be | 1742 | apply_bitpos = bitpos; |
40cb04f1 | 1743 | } |
c67a1cf6 | 1744 | } |
1b1838b6 | 1745 | else if (TREE_CODE (t2) == COMPONENT_REF) |
998d7deb | 1746 | { |
55b34b5f RG |
1747 | expr = t2; |
1748 | offset = NULL; | |
998d7deb | 1749 | if (host_integerp (off_tree, 1)) |
6f1087be RH |
1750 | { |
1751 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1752 | apply_bitpos = bitpos; | |
1753 | } | |
998d7deb RH |
1754 | /* ??? Any reason the field size would be different than |
1755 | the size we got from the type? */ | |
1756 | } | |
c67a1cf6 | 1757 | else if (flag_argument_noalias > 1 |
1b096a0a | 1758 | && (INDIRECT_REF_P (t2)) |
1b1838b6 | 1759 | && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL) |
c67a1cf6 | 1760 | { |
1b1838b6 | 1761 | expr = t2; |
c67a1cf6 RH |
1762 | offset = NULL; |
1763 | } | |
1764 | } | |
1765 | ||
1766 | /* If this is a Fortran indirect argument reference, record the | |
1767 | parameter decl. */ | |
1768 | else if (flag_argument_noalias > 1 | |
1b096a0a | 1769 | && (INDIRECT_REF_P (t)) |
c67a1cf6 RH |
1770 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) |
1771 | { | |
1772 | expr = t; | |
1773 | offset = NULL; | |
998d7deb | 1774 | } |
df96b059 JJ |
1775 | |
1776 | if (!align_computed && !INDIRECT_REF_P (t)) | |
1777 | { | |
1778 | unsigned int obj_align | |
1779 | = get_object_alignment (t, align, BIGGEST_ALIGNMENT); | |
1780 | align = MAX (align, obj_align); | |
1781 | } | |
8ac61af7 RK |
1782 | } |
1783 | ||
15c812e3 | 1784 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
1785 | bit position offset. Similarly, increase the size of the accessed |
1786 | object to contain the negative offset. */ | |
6f1087be | 1787 | if (apply_bitpos) |
8c317c5f RH |
1788 | { |
1789 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
1790 | if (size) | |
1791 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
1792 | } | |
6f1087be | 1793 | |
7ccf35ed DN |
1794 | if (TREE_CODE (t) == ALIGN_INDIRECT_REF) |
1795 | { | |
fa10beec | 1796 | /* Force EXPR and OFFSET to NULL, since we don't know exactly what |
7ccf35ed DN |
1797 | we're overlapping. */ |
1798 | offset = NULL; | |
1799 | expr = NULL; | |
1800 | } | |
1801 | ||
8ac61af7 | 1802 | /* Now set the attributes we computed above. */ |
10b76d73 | 1803 | MEM_ATTRS (ref) |
09e881c9 BE |
1804 | = get_mem_attrs (alias, expr, offset, size, align, |
1805 | TYPE_ADDR_SPACE (type), GET_MODE (ref)); | |
8ac61af7 RK |
1806 | |
1807 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
1808 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
738cc472 RK |
1809 | return; |
1810 | ||
8ac61af7 RK |
1811 | /* If it is a reference into an aggregate, this is part of an aggregate. |
1812 | Otherwise we don't know. */ | |
173b24b9 RK |
1813 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
1814 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
1815 | || TREE_CODE (t) == BIT_FIELD_REF) | |
1816 | MEM_IN_STRUCT_P (ref) = 1; | |
1817 | } | |
1818 | ||
6f1087be | 1819 | void |
502b8322 | 1820 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
1821 | { |
1822 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
1823 | } | |
1824 | ||
173b24b9 RK |
1825 | /* Set the alias set of MEM to SET. */ |
1826 | ||
1827 | void | |
4862826d | 1828 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 1829 | { |
68252e27 | 1830 | #ifdef ENABLE_CHECKING |
173b24b9 | 1831 | /* If the new and old alias sets don't conflict, something is wrong. */ |
5b0264cb | 1832 | gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
173b24b9 RK |
1833 | #endif |
1834 | ||
998d7deb | 1835 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
10b76d73 | 1836 | MEM_SIZE (mem), MEM_ALIGN (mem), |
09e881c9 BE |
1837 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
1838 | } | |
1839 | ||
1840 | /* Set the address space of MEM to ADDRSPACE (target-defined). */ | |
1841 | ||
1842 | void | |
1843 | set_mem_addr_space (rtx mem, addr_space_t addrspace) | |
1844 | { | |
1845 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1846 | MEM_OFFSET (mem), MEM_SIZE (mem), | |
1847 | MEM_ALIGN (mem), addrspace, GET_MODE (mem)); | |
173b24b9 | 1848 | } |
738cc472 | 1849 | |
d022d93e | 1850 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
1851 | |
1852 | void | |
502b8322 | 1853 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 1854 | { |
998d7deb | 1855 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
10b76d73 | 1856 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
09e881c9 | 1857 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
738cc472 | 1858 | } |
1285011e | 1859 | |
998d7deb | 1860 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
1861 | |
1862 | void | |
502b8322 | 1863 | set_mem_expr (rtx mem, tree expr) |
1285011e RK |
1864 | { |
1865 | MEM_ATTRS (mem) | |
998d7deb | 1866 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
09e881c9 BE |
1867 | MEM_SIZE (mem), MEM_ALIGN (mem), |
1868 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); | |
1285011e | 1869 | } |
998d7deb RH |
1870 | |
1871 | /* Set the offset of MEM to OFFSET. */ | |
1872 | ||
1873 | void | |
502b8322 | 1874 | set_mem_offset (rtx mem, rtx offset) |
998d7deb RH |
1875 | { |
1876 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1877 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
09e881c9 | 1878 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
35aff10b AM |
1879 | } |
1880 | ||
1881 | /* Set the size of MEM to SIZE. */ | |
1882 | ||
1883 | void | |
502b8322 | 1884 | set_mem_size (rtx mem, rtx size) |
35aff10b AM |
1885 | { |
1886 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1887 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
09e881c9 | 1888 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
998d7deb | 1889 | } |
173b24b9 | 1890 | \f |
738cc472 RK |
1891 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
1892 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
1893 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
1894 | returned memory location is required to be valid. The memory | |
1895 | attributes are not changed. */ | |
23b2ce53 | 1896 | |
738cc472 | 1897 | static rtx |
502b8322 | 1898 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
23b2ce53 | 1899 | { |
09e881c9 | 1900 | addr_space_t as; |
60564289 | 1901 | rtx new_rtx; |
23b2ce53 | 1902 | |
5b0264cb | 1903 | gcc_assert (MEM_P (memref)); |
09e881c9 | 1904 | as = MEM_ADDR_SPACE (memref); |
23b2ce53 RS |
1905 | if (mode == VOIDmode) |
1906 | mode = GET_MODE (memref); | |
1907 | if (addr == 0) | |
1908 | addr = XEXP (memref, 0); | |
a74ff877 | 1909 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
09e881c9 | 1910 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
a74ff877 | 1911 | return memref; |
23b2ce53 | 1912 | |
f1ec5147 | 1913 | if (validate) |
23b2ce53 | 1914 | { |
f1ec5147 | 1915 | if (reload_in_progress || reload_completed) |
09e881c9 | 1916 | gcc_assert (memory_address_addr_space_p (mode, addr, as)); |
f1ec5147 | 1917 | else |
09e881c9 | 1918 | addr = memory_address_addr_space (mode, addr, as); |
23b2ce53 | 1919 | } |
750c9258 | 1920 | |
9b04c6a8 RK |
1921 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1922 | return memref; | |
1923 | ||
60564289 KG |
1924 | new_rtx = gen_rtx_MEM (mode, addr); |
1925 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
1926 | return new_rtx; | |
23b2ce53 | 1927 | } |
792760b9 | 1928 | |
738cc472 RK |
1929 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
1930 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
1931 | |
1932 | rtx | |
502b8322 | 1933 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
f4ef873c | 1934 | { |
60564289 KG |
1935 | rtx new_rtx = change_address_1 (memref, mode, addr, 1), size; |
1936 | enum machine_mode mmode = GET_MODE (new_rtx); | |
4e44c1ef JJ |
1937 | unsigned int align; |
1938 | ||
1939 | size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)); | |
1940 | align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode); | |
c2f7bcc3 | 1941 | |
fdb1c7b3 | 1942 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 1943 | if (new_rtx == memref) |
4e44c1ef JJ |
1944 | { |
1945 | if (MEM_ATTRS (memref) == 0 | |
1946 | || (MEM_EXPR (memref) == NULL | |
1947 | && MEM_OFFSET (memref) == NULL | |
1948 | && MEM_SIZE (memref) == size | |
1949 | && MEM_ALIGN (memref) == align)) | |
60564289 | 1950 | return new_rtx; |
4e44c1ef | 1951 | |
60564289 KG |
1952 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
1953 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 1954 | } |
fdb1c7b3 | 1955 | |
60564289 | 1956 | MEM_ATTRS (new_rtx) |
09e881c9 BE |
1957 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, |
1958 | MEM_ADDR_SPACE (memref), mmode); | |
823e3574 | 1959 | |
60564289 | 1960 | return new_rtx; |
f4ef873c | 1961 | } |
792760b9 | 1962 | |
738cc472 RK |
1963 | /* Return a memory reference like MEMREF, but with its mode changed |
1964 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 JJ |
1965 | nonzero, the memory address is forced to be valid. |
1966 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
1967 | and caller is responsible for adjusting MEMREF base register. */ | |
f1ec5147 RK |
1968 | |
1969 | rtx | |
502b8322 AJ |
1970 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
1971 | int validate, int adjust) | |
f1ec5147 | 1972 | { |
823e3574 | 1973 | rtx addr = XEXP (memref, 0); |
60564289 | 1974 | rtx new_rtx; |
738cc472 | 1975 | rtx memoffset = MEM_OFFSET (memref); |
10b76d73 | 1976 | rtx size = 0; |
738cc472 | 1977 | unsigned int memalign = MEM_ALIGN (memref); |
09e881c9 | 1978 | addr_space_t as = MEM_ADDR_SPACE (memref); |
d4ebfa65 | 1979 | enum machine_mode address_mode = targetm.addr_space.address_mode (as); |
a6fe9ed4 | 1980 | int pbits; |
823e3574 | 1981 | |
fdb1c7b3 JH |
1982 | /* If there are no changes, just return the original memory reference. */ |
1983 | if (mode == GET_MODE (memref) && !offset | |
09e881c9 | 1984 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
fdb1c7b3 JH |
1985 | return memref; |
1986 | ||
d14419e4 | 1987 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 1988 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
1989 | (plus (plus reg reg) const_int) -- so do this always. */ |
1990 | addr = copy_rtx (addr); | |
1991 | ||
a6fe9ed4 JM |
1992 | /* Convert a possibly large offset to a signed value within the |
1993 | range of the target address space. */ | |
d4ebfa65 | 1994 | pbits = GET_MODE_BITSIZE (address_mode); |
a6fe9ed4 JM |
1995 | if (HOST_BITS_PER_WIDE_INT > pbits) |
1996 | { | |
1997 | int shift = HOST_BITS_PER_WIDE_INT - pbits; | |
1998 | offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift)) | |
1999 | >> shift); | |
2000 | } | |
2001 | ||
4a78c787 RH |
2002 | if (adjust) |
2003 | { | |
2004 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2005 | object, we can merge it into the LO_SUM. */ | |
2006 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
2007 | && offset >= 0 | |
2008 | && (unsigned HOST_WIDE_INT) offset | |
2009 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
d4ebfa65 | 2010 | addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0), |
4a78c787 RH |
2011 | plus_constant (XEXP (addr, 1), offset)); |
2012 | else | |
2013 | addr = plus_constant (addr, offset); | |
2014 | } | |
823e3574 | 2015 | |
60564289 | 2016 | new_rtx = change_address_1 (memref, mode, addr, validate); |
738cc472 | 2017 | |
09efeca1 PB |
2018 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2019 | but this would destroy memref's MEM_ATTRS. */ | |
2020 | if (new_rtx == memref && offset != 0) | |
2021 | new_rtx = copy_rtx (new_rtx); | |
2022 | ||
738cc472 RK |
2023 | /* Compute the new values of the memory attributes due to this adjustment. |
2024 | We add the offsets and update the alignment. */ | |
2025 | if (memoffset) | |
2026 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
2027 | ||
03bf2c23 RK |
2028 | /* Compute the new alignment by taking the MIN of the alignment and the |
2029 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2030 | if zero. */ | |
2031 | if (offset != 0) | |
3bf1e984 RK |
2032 | memalign |
2033 | = MIN (memalign, | |
2034 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
738cc472 | 2035 | |
10b76d73 | 2036 | /* We can compute the size in a number of ways. */ |
60564289 KG |
2037 | if (GET_MODE (new_rtx) != BLKmode) |
2038 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new_rtx))); | |
10b76d73 RK |
2039 | else if (MEM_SIZE (memref)) |
2040 | size = plus_constant (MEM_SIZE (memref), -offset); | |
2041 | ||
60564289 | 2042 | MEM_ATTRS (new_rtx) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
09e881c9 BE |
2043 | memoffset, size, memalign, as, |
2044 | GET_MODE (new_rtx)); | |
738cc472 RK |
2045 | |
2046 | /* At some point, we should validate that this offset is within the object, | |
2047 | if all the appropriate values are known. */ | |
60564289 | 2048 | return new_rtx; |
f1ec5147 RK |
2049 | } |
2050 | ||
630036c6 JJ |
2051 | /* Return a memory reference like MEMREF, but with its mode changed |
2052 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2053 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2054 | nonzero, the memory address is forced to be valid. */ |
2055 | ||
2056 | rtx | |
502b8322 AJ |
2057 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
2058 | HOST_WIDE_INT offset, int validate) | |
630036c6 JJ |
2059 | { |
2060 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
2061 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
2062 | } | |
2063 | ||
8ac61af7 RK |
2064 | /* Return a memory reference like MEMREF, but whose address is changed by |
2065 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2066 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2067 | |
2068 | rtx | |
502b8322 | 2069 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2070 | { |
60564289 | 2071 | rtx new_rtx, addr = XEXP (memref, 0); |
09e881c9 | 2072 | addr_space_t as = MEM_ADDR_SPACE (memref); |
d4ebfa65 | 2073 | enum machine_mode address_mode = targetm.addr_space.address_mode (as); |
e3c8ea67 | 2074 | |
d4ebfa65 | 2075 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 | 2076 | |
68252e27 | 2077 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2078 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2079 | |
2080 | However, if we did go and rearrange things, we can wind up not | |
2081 | being able to recognize the magic around pic_offset_table_rtx. | |
2082 | This stuff is fragile, and is yet another example of why it is | |
2083 | bad to expose PIC machinery too early. */ | |
09e881c9 | 2084 | if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, as) |
e3c8ea67 RH |
2085 | && GET_CODE (addr) == PLUS |
2086 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2087 | { | |
2088 | addr = force_reg (GET_MODE (addr), addr); | |
d4ebfa65 | 2089 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 RH |
2090 | } |
2091 | ||
60564289 KG |
2092 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
2093 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1); | |
0d4903b8 | 2094 | |
fdb1c7b3 | 2095 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2096 | if (new_rtx == memref) |
2097 | return new_rtx; | |
fdb1c7b3 | 2098 | |
0d4903b8 RK |
2099 | /* Update the alignment to reflect the offset. Reset the offset, which |
2100 | we don't know. */ | |
60564289 | 2101 | MEM_ATTRS (new_rtx) |
2cc2d4bb | 2102 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, |
9ceca302 | 2103 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
09e881c9 | 2104 | as, GET_MODE (new_rtx)); |
60564289 | 2105 | return new_rtx; |
0d4903b8 | 2106 | } |
68252e27 | 2107 | |
792760b9 RK |
2108 | /* Return a memory reference like MEMREF, but with its address changed to |
2109 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2110 | to is the same, just the form of the address is being changed, such as | |
2111 | by putting something into a register. */ | |
2112 | ||
2113 | rtx | |
502b8322 | 2114 | replace_equiv_address (rtx memref, rtx addr) |
792760b9 | 2115 | { |
738cc472 RK |
2116 | /* change_address_1 copies the memory attribute structure without change |
2117 | and that's exactly what we want here. */ | |
40c0668b | 2118 | update_temp_slot_address (XEXP (memref, 0), addr); |
738cc472 | 2119 | return change_address_1 (memref, VOIDmode, addr, 1); |
792760b9 | 2120 | } |
738cc472 | 2121 | |
f1ec5147 RK |
2122 | /* Likewise, but the reference is not required to be valid. */ |
2123 | ||
2124 | rtx | |
502b8322 | 2125 | replace_equiv_address_nv (rtx memref, rtx addr) |
f1ec5147 | 2126 | { |
f1ec5147 RK |
2127 | return change_address_1 (memref, VOIDmode, addr, 0); |
2128 | } | |
e7dfe4bb RH |
2129 | |
2130 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2131 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2132 | cannot issue QImode memory operations and have to use SImode memory | |
2133 | operations plus masking logic. */ | |
2134 | ||
2135 | rtx | |
502b8322 | 2136 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb | 2137 | { |
60564289 KG |
2138 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1); |
2139 | tree expr = MEM_EXPR (new_rtx); | |
2140 | rtx memoffset = MEM_OFFSET (new_rtx); | |
e7dfe4bb RH |
2141 | unsigned int size = GET_MODE_SIZE (mode); |
2142 | ||
fdb1c7b3 | 2143 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2144 | if (new_rtx == memref) |
2145 | return new_rtx; | |
fdb1c7b3 | 2146 | |
e7dfe4bb RH |
2147 | /* If we don't know what offset we were at within the expression, then |
2148 | we can't know if we've overstepped the bounds. */ | |
fa1591cb | 2149 | if (! memoffset) |
e7dfe4bb RH |
2150 | expr = NULL_TREE; |
2151 | ||
2152 | while (expr) | |
2153 | { | |
2154 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2155 | { | |
2156 | tree field = TREE_OPERAND (expr, 1); | |
44de5aeb | 2157 | tree offset = component_ref_field_offset (expr); |
e7dfe4bb RH |
2158 | |
2159 | if (! DECL_SIZE_UNIT (field)) | |
2160 | { | |
2161 | expr = NULL_TREE; | |
2162 | break; | |
2163 | } | |
2164 | ||
2165 | /* Is the field at least as large as the access? If so, ok, | |
2166 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2167 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2168 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
e7dfe4bb RH |
2169 | && INTVAL (memoffset) >= 0) |
2170 | break; | |
2171 | ||
44de5aeb | 2172 | if (! host_integerp (offset, 1)) |
e7dfe4bb RH |
2173 | { |
2174 | expr = NULL_TREE; | |
2175 | break; | |
2176 | } | |
2177 | ||
2178 | expr = TREE_OPERAND (expr, 0); | |
44de5aeb RK |
2179 | memoffset |
2180 | = (GEN_INT (INTVAL (memoffset) | |
2181 | + tree_low_cst (offset, 1) | |
2182 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2183 | / BITS_PER_UNIT))); | |
e7dfe4bb RH |
2184 | } |
2185 | /* Similarly for the decl. */ | |
2186 | else if (DECL_P (expr) | |
2187 | && DECL_SIZE_UNIT (expr) | |
45f79783 | 2188 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
e7dfe4bb RH |
2189 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2190 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2191 | break; | |
2192 | else | |
2193 | { | |
2194 | /* The widened memory access overflows the expression, which means | |
2195 | that it could alias another expression. Zap it. */ | |
2196 | expr = NULL_TREE; | |
2197 | break; | |
2198 | } | |
2199 | } | |
2200 | ||
2201 | if (! expr) | |
2202 | memoffset = NULL_RTX; | |
2203 | ||
2204 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2205 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2206 | ||
60564289 | 2207 | MEM_ATTRS (new_rtx) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), |
09e881c9 BE |
2208 | MEM_ALIGN (new_rtx), |
2209 | MEM_ADDR_SPACE (new_rtx), mode); | |
e7dfe4bb | 2210 | |
60564289 | 2211 | return new_rtx; |
e7dfe4bb | 2212 | } |
23b2ce53 | 2213 | \f |
f6129d66 RH |
2214 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2215 | static GTY(()) tree spill_slot_decl; | |
2216 | ||
3d7e23f6 RH |
2217 | tree |
2218 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2219 | { |
2220 | tree d = spill_slot_decl; | |
2221 | rtx rd; | |
2222 | ||
3d7e23f6 | 2223 | if (d || !force_build_p) |
f6129d66 RH |
2224 | return d; |
2225 | ||
c2255bc4 AH |
2226 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2227 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2228 | DECL_ARTIFICIAL (d) = 1; |
2229 | DECL_IGNORED_P (d) = 1; | |
2230 | TREE_USED (d) = 1; | |
2231 | TREE_THIS_NOTRAP (d) = 1; | |
2232 | spill_slot_decl = d; | |
2233 | ||
2234 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2235 | MEM_NOTRAP_P (rd) = 1; | |
2236 | MEM_ATTRS (rd) = get_mem_attrs (new_alias_set (), d, const0_rtx, | |
09e881c9 | 2237 | NULL_RTX, 0, ADDR_SPACE_GENERIC, BLKmode); |
f6129d66 RH |
2238 | SET_DECL_RTL (d, rd); |
2239 | ||
2240 | return d; | |
2241 | } | |
2242 | ||
2243 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2244 | attributes as appropriate for a register allocator spill slot. | |
2245 | These slots are not aliasable by other memory. We arrange for | |
2246 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2247 | work properly in the case of shared spill slots. */ | |
2248 | ||
2249 | void | |
2250 | set_mem_attrs_for_spill (rtx mem) | |
2251 | { | |
2252 | alias_set_type alias; | |
2253 | rtx addr, offset; | |
2254 | tree expr; | |
2255 | ||
3d7e23f6 | 2256 | expr = get_spill_slot_decl (true); |
f6129d66 RH |
2257 | alias = MEM_ALIAS_SET (DECL_RTL (expr)); |
2258 | ||
2259 | /* We expect the incoming memory to be of the form: | |
2260 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2261 | with perhaps the plus missing for offset = 0. */ | |
2262 | addr = XEXP (mem, 0); | |
2263 | offset = const0_rtx; | |
2264 | if (GET_CODE (addr) == PLUS | |
481683e1 | 2265 | && CONST_INT_P (XEXP (addr, 1))) |
f6129d66 RH |
2266 | offset = XEXP (addr, 1); |
2267 | ||
2268 | MEM_ATTRS (mem) = get_mem_attrs (alias, expr, offset, | |
2269 | MEM_SIZE (mem), MEM_ALIGN (mem), | |
09e881c9 | 2270 | ADDR_SPACE_GENERIC, GET_MODE (mem)); |
f6129d66 RH |
2271 | MEM_NOTRAP_P (mem) = 1; |
2272 | } | |
2273 | \f | |
23b2ce53 RS |
2274 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2275 | ||
2276 | rtx | |
502b8322 | 2277 | gen_label_rtx (void) |
23b2ce53 | 2278 | { |
0dc36574 | 2279 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
502b8322 | 2280 | NULL, label_num++, NULL); |
23b2ce53 RS |
2281 | } |
2282 | \f | |
2283 | /* For procedure integration. */ | |
2284 | ||
23b2ce53 | 2285 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2286 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2287 | Used for an inline-procedure after copying the insn chain. */ |
2288 | ||
2289 | void | |
502b8322 | 2290 | set_new_first_and_last_insn (rtx first, rtx last) |
23b2ce53 | 2291 | { |
86fe05e0 RK |
2292 | rtx insn; |
2293 | ||
23b2ce53 RS |
2294 | first_insn = first; |
2295 | last_insn = last; | |
86fe05e0 RK |
2296 | cur_insn_uid = 0; |
2297 | ||
b5b8b0ac AO |
2298 | if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS) |
2299 | { | |
2300 | int debug_count = 0; | |
2301 | ||
2302 | cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1; | |
2303 | cur_debug_insn_uid = 0; | |
2304 | ||
2305 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2306 | if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID) | |
2307 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); | |
2308 | else | |
2309 | { | |
2310 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2311 | if (DEBUG_INSN_P (insn)) | |
2312 | debug_count++; | |
2313 | } | |
2314 | ||
2315 | if (debug_count) | |
2316 | cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count; | |
2317 | else | |
2318 | cur_debug_insn_uid++; | |
2319 | } | |
2320 | else | |
2321 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2322 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2323 | |
2324 | cur_insn_uid++; | |
23b2ce53 | 2325 | } |
23b2ce53 | 2326 | \f |
750c9258 | 2327 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2328 | structure. This routine should only be called once. */ |
23b2ce53 | 2329 | |
fd743bc1 | 2330 | static void |
b4aaa77b | 2331 | unshare_all_rtl_1 (rtx insn) |
23b2ce53 | 2332 | { |
d1b81779 | 2333 | /* Unshare just about everything else. */ |
2c07f13b | 2334 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2335 | |
23b2ce53 RS |
2336 | /* Make sure the addresses of stack slots found outside the insn chain |
2337 | (such as, in DECL_RTL of a variable) are not shared | |
2338 | with the insn chain. | |
2339 | ||
2340 | This special care is necessary when the stack slot MEM does not | |
2341 | actually appear in the insn chain. If it does appear, its address | |
2342 | is unshared from all else at that point. */ | |
242b0ce6 | 2343 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
2344 | } |
2345 | ||
750c9258 | 2346 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2347 | structure, again. This is a fairly expensive thing to do so it |
2348 | should be done sparingly. */ | |
2349 | ||
2350 | void | |
502b8322 | 2351 | unshare_all_rtl_again (rtx insn) |
d1b81779 GK |
2352 | { |
2353 | rtx p; | |
624c87aa RE |
2354 | tree decl; |
2355 | ||
d1b81779 | 2356 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2357 | if (INSN_P (p)) |
d1b81779 GK |
2358 | { |
2359 | reset_used_flags (PATTERN (p)); | |
2360 | reset_used_flags (REG_NOTES (p)); | |
d1b81779 | 2361 | } |
624c87aa | 2362 | |
2d4aecb3 | 2363 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2364 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2365 | |
624c87aa RE |
2366 | /* Make sure that virtual parameters are not shared. */ |
2367 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
5eb2a9f2 | 2368 | set_used_flags (DECL_RTL (decl)); |
624c87aa RE |
2369 | |
2370 | reset_used_flags (stack_slot_list); | |
2371 | ||
b4aaa77b | 2372 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2373 | } |
2374 | ||
c2924966 | 2375 | unsigned int |
fd743bc1 PB |
2376 | unshare_all_rtl (void) |
2377 | { | |
b4aaa77b | 2378 | unshare_all_rtl_1 (get_insns ()); |
c2924966 | 2379 | return 0; |
d1b81779 GK |
2380 | } |
2381 | ||
8ddbbcae | 2382 | struct rtl_opt_pass pass_unshare_all_rtl = |
ef330312 | 2383 | { |
8ddbbcae JH |
2384 | { |
2385 | RTL_PASS, | |
defb77dc | 2386 | "unshare", /* name */ |
ef330312 PB |
2387 | NULL, /* gate */ |
2388 | unshare_all_rtl, /* execute */ | |
2389 | NULL, /* sub */ | |
2390 | NULL, /* next */ | |
2391 | 0, /* static_pass_number */ | |
7072a650 | 2392 | TV_NONE, /* tv_id */ |
ef330312 PB |
2393 | 0, /* properties_required */ |
2394 | 0, /* properties_provided */ | |
2395 | 0, /* properties_destroyed */ | |
2396 | 0, /* todo_flags_start */ | |
8ddbbcae JH |
2397 | TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */ |
2398 | } | |
ef330312 PB |
2399 | }; |
2400 | ||
2401 | ||
2c07f13b JH |
2402 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2403 | Recursively does the same for subexpressions. */ | |
2404 | ||
2405 | static void | |
2406 | verify_rtx_sharing (rtx orig, rtx insn) | |
2407 | { | |
2408 | rtx x = orig; | |
2409 | int i; | |
2410 | enum rtx_code code; | |
2411 | const char *format_ptr; | |
2412 | ||
2413 | if (x == 0) | |
2414 | return; | |
2415 | ||
2416 | code = GET_CODE (x); | |
2417 | ||
2418 | /* These types may be freely shared. */ | |
2419 | ||
2420 | switch (code) | |
2421 | { | |
2422 | case REG: | |
0ca5af51 AO |
2423 | case DEBUG_EXPR: |
2424 | case VALUE: | |
2c07f13b JH |
2425 | case CONST_INT: |
2426 | case CONST_DOUBLE: | |
091a3ac7 | 2427 | case CONST_FIXED: |
2c07f13b JH |
2428 | case CONST_VECTOR: |
2429 | case SYMBOL_REF: | |
2430 | case LABEL_REF: | |
2431 | case CODE_LABEL: | |
2432 | case PC: | |
2433 | case CC0: | |
2434 | case SCRATCH: | |
2c07f13b | 2435 | return; |
3e89ed8d JH |
2436 | /* SCRATCH must be shared because they represent distinct values. */ |
2437 | case CLOBBER: | |
2438 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2439 | return; | |
2440 | break; | |
2c07f13b JH |
2441 | |
2442 | case CONST: | |
6fb5fa3c | 2443 | if (shared_const_p (orig)) |
2c07f13b JH |
2444 | return; |
2445 | break; | |
2446 | ||
2447 | case MEM: | |
2448 | /* A MEM is allowed to be shared if its address is constant. */ | |
2449 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2450 | || reload_completed || reload_in_progress) | |
2451 | return; | |
2452 | ||
2453 | break; | |
2454 | ||
2455 | default: | |
2456 | break; | |
2457 | } | |
2458 | ||
2459 | /* This rtx may not be shared. If it has already been seen, | |
2460 | replace it with a copy of itself. */ | |
1a2caa7a | 2461 | #ifdef ENABLE_CHECKING |
2c07f13b JH |
2462 | if (RTX_FLAG (x, used)) |
2463 | { | |
ab532386 | 2464 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2465 | debug_rtx (insn); |
ab532386 | 2466 | error ("shared rtx"); |
2c07f13b | 2467 | debug_rtx (x); |
ab532386 | 2468 | internal_error ("internal consistency failure"); |
2c07f13b | 2469 | } |
1a2caa7a NS |
2470 | #endif |
2471 | gcc_assert (!RTX_FLAG (x, used)); | |
2472 | ||
2c07f13b JH |
2473 | RTX_FLAG (x, used) = 1; |
2474 | ||
6614fd40 | 2475 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2476 | |
2477 | format_ptr = GET_RTX_FORMAT (code); | |
2478 | ||
2479 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2480 | { | |
2481 | switch (*format_ptr++) | |
2482 | { | |
2483 | case 'e': | |
2484 | verify_rtx_sharing (XEXP (x, i), insn); | |
2485 | break; | |
2486 | ||
2487 | case 'E': | |
2488 | if (XVEC (x, i) != NULL) | |
2489 | { | |
2490 | int j; | |
2491 | int len = XVECLEN (x, i); | |
2492 | ||
2493 | for (j = 0; j < len; j++) | |
2494 | { | |
1a2caa7a NS |
2495 | /* We allow sharing of ASM_OPERANDS inside single |
2496 | instruction. */ | |
2c07f13b | 2497 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2498 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2499 | == ASM_OPERANDS)) | |
2c07f13b JH |
2500 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2501 | else | |
2502 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2503 | } | |
2504 | } | |
2505 | break; | |
2506 | } | |
2507 | } | |
2508 | return; | |
2509 | } | |
2510 | ||
ba228239 | 2511 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2c07f13b JH |
2512 | sharing in between the subexpressions. */ |
2513 | ||
2514 | void | |
2515 | verify_rtl_sharing (void) | |
2516 | { | |
2517 | rtx p; | |
2518 | ||
2519 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2520 | if (INSN_P (p)) | |
2521 | { | |
2522 | reset_used_flags (PATTERN (p)); | |
2523 | reset_used_flags (REG_NOTES (p)); | |
2954a813 KK |
2524 | if (GET_CODE (PATTERN (p)) == SEQUENCE) |
2525 | { | |
2526 | int i; | |
2527 | rtx q, sequence = PATTERN (p); | |
2528 | ||
2529 | for (i = 0; i < XVECLEN (sequence, 0); i++) | |
2530 | { | |
2531 | q = XVECEXP (sequence, 0, i); | |
2532 | gcc_assert (INSN_P (q)); | |
2533 | reset_used_flags (PATTERN (q)); | |
2534 | reset_used_flags (REG_NOTES (q)); | |
2954a813 KK |
2535 | } |
2536 | } | |
2c07f13b JH |
2537 | } |
2538 | ||
2539 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2540 | if (INSN_P (p)) | |
2541 | { | |
2542 | verify_rtx_sharing (PATTERN (p), p); | |
2543 | verify_rtx_sharing (REG_NOTES (p), p); | |
2c07f13b JH |
2544 | } |
2545 | } | |
2546 | ||
d1b81779 GK |
2547 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2548 | Assumes the mark bits are cleared at entry. */ | |
2549 | ||
2c07f13b JH |
2550 | void |
2551 | unshare_all_rtl_in_chain (rtx insn) | |
d1b81779 GK |
2552 | { |
2553 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2554 | if (INSN_P (insn)) |
d1b81779 GK |
2555 | { |
2556 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2557 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
d1b81779 GK |
2558 | } |
2559 | } | |
2560 | ||
2d4aecb3 | 2561 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2562 | shared. We never replace the DECL_RTLs themselves with a copy, |
2563 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2564 | expressions in the instruction stream. | |
2565 | ||
2566 | Note that reload may convert pseudo registers into memories in-place. | |
2567 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2568 | reset the used flags on MEMs in the instruction stream, we must set | |
2569 | them again on MEMs that appear in DECL_RTLs. */ | |
2570 | ||
2d4aecb3 | 2571 | static void |
5eb2a9f2 | 2572 | set_used_decls (tree blk) |
2d4aecb3 AO |
2573 | { |
2574 | tree t; | |
2575 | ||
2576 | /* Mark decls. */ | |
2577 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c | 2578 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2579 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2580 | |
2581 | /* Now process sub-blocks. */ | |
87caf699 | 2582 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 2583 | set_used_decls (t); |
2d4aecb3 AO |
2584 | } |
2585 | ||
23b2ce53 | 2586 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2587 | Recursively does the same for subexpressions. Uses |
2588 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2589 | |
2590 | rtx | |
502b8322 | 2591 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2592 | { |
32b32b16 AP |
2593 | copy_rtx_if_shared_1 (&orig); |
2594 | return orig; | |
2595 | } | |
2596 | ||
ff954f39 AP |
2597 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2598 | use. Recursively does the same for subexpressions. */ | |
2599 | ||
32b32b16 AP |
2600 | static void |
2601 | copy_rtx_if_shared_1 (rtx *orig1) | |
2602 | { | |
2603 | rtx x; | |
b3694847 SS |
2604 | int i; |
2605 | enum rtx_code code; | |
32b32b16 | 2606 | rtx *last_ptr; |
b3694847 | 2607 | const char *format_ptr; |
23b2ce53 | 2608 | int copied = 0; |
32b32b16 AP |
2609 | int length; |
2610 | ||
2611 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2612 | repeat: | |
2613 | x = *orig1; | |
23b2ce53 RS |
2614 | |
2615 | if (x == 0) | |
32b32b16 | 2616 | return; |
23b2ce53 RS |
2617 | |
2618 | code = GET_CODE (x); | |
2619 | ||
2620 | /* These types may be freely shared. */ | |
2621 | ||
2622 | switch (code) | |
2623 | { | |
2624 | case REG: | |
0ca5af51 AO |
2625 | case DEBUG_EXPR: |
2626 | case VALUE: | |
23b2ce53 RS |
2627 | case CONST_INT: |
2628 | case CONST_DOUBLE: | |
091a3ac7 | 2629 | case CONST_FIXED: |
69ef87e2 | 2630 | case CONST_VECTOR: |
23b2ce53 | 2631 | case SYMBOL_REF: |
2c07f13b | 2632 | case LABEL_REF: |
23b2ce53 RS |
2633 | case CODE_LABEL: |
2634 | case PC: | |
2635 | case CC0: | |
2636 | case SCRATCH: | |
0f41302f | 2637 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 2638 | return; |
3e89ed8d JH |
2639 | case CLOBBER: |
2640 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2641 | return; | |
2642 | break; | |
23b2ce53 | 2643 | |
b851ea09 | 2644 | case CONST: |
6fb5fa3c | 2645 | if (shared_const_p (x)) |
32b32b16 | 2646 | return; |
b851ea09 RK |
2647 | break; |
2648 | ||
b5b8b0ac | 2649 | case DEBUG_INSN: |
23b2ce53 RS |
2650 | case INSN: |
2651 | case JUMP_INSN: | |
2652 | case CALL_INSN: | |
2653 | case NOTE: | |
23b2ce53 RS |
2654 | case BARRIER: |
2655 | /* The chain of insns is not being copied. */ | |
32b32b16 | 2656 | return; |
23b2ce53 | 2657 | |
e9a25f70 JL |
2658 | default: |
2659 | break; | |
23b2ce53 RS |
2660 | } |
2661 | ||
2662 | /* This rtx may not be shared. If it has already been seen, | |
2663 | replace it with a copy of itself. */ | |
2664 | ||
2adc7f12 | 2665 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2666 | { |
aacd3885 | 2667 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
2668 | copied = 1; |
2669 | } | |
2adc7f12 | 2670 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
2671 | |
2672 | /* Now scan the subexpressions recursively. | |
2673 | We can store any replaced subexpressions directly into X | |
2674 | since we know X is not shared! Any vectors in X | |
2675 | must be copied if X was copied. */ | |
2676 | ||
2677 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2678 | length = GET_RTX_LENGTH (code); |
2679 | last_ptr = NULL; | |
2680 | ||
2681 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2682 | { |
2683 | switch (*format_ptr++) | |
2684 | { | |
2685 | case 'e': | |
32b32b16 AP |
2686 | if (last_ptr) |
2687 | copy_rtx_if_shared_1 (last_ptr); | |
2688 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
2689 | break; |
2690 | ||
2691 | case 'E': | |
2692 | if (XVEC (x, i) != NULL) | |
2693 | { | |
b3694847 | 2694 | int j; |
f0722107 | 2695 | int len = XVECLEN (x, i); |
32b32b16 | 2696 | |
6614fd40 KH |
2697 | /* Copy the vector iff I copied the rtx and the length |
2698 | is nonzero. */ | |
f0722107 | 2699 | if (copied && len > 0) |
8f985ec4 | 2700 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
32b32b16 | 2701 | |
5d3cc252 | 2702 | /* Call recursively on all inside the vector. */ |
f0722107 | 2703 | for (j = 0; j < len; j++) |
32b32b16 AP |
2704 | { |
2705 | if (last_ptr) | |
2706 | copy_rtx_if_shared_1 (last_ptr); | |
2707 | last_ptr = &XVECEXP (x, i, j); | |
2708 | } | |
23b2ce53 RS |
2709 | } |
2710 | break; | |
2711 | } | |
2712 | } | |
32b32b16 AP |
2713 | *orig1 = x; |
2714 | if (last_ptr) | |
2715 | { | |
2716 | orig1 = last_ptr; | |
2717 | goto repeat; | |
2718 | } | |
2719 | return; | |
23b2ce53 RS |
2720 | } |
2721 | ||
2722 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2723 | to look for shared sub-parts. */ | |
2724 | ||
2725 | void | |
502b8322 | 2726 | reset_used_flags (rtx x) |
23b2ce53 | 2727 | { |
b3694847 SS |
2728 | int i, j; |
2729 | enum rtx_code code; | |
2730 | const char *format_ptr; | |
32b32b16 | 2731 | int length; |
23b2ce53 | 2732 | |
32b32b16 AP |
2733 | /* Repeat is used to turn tail-recursion into iteration. */ |
2734 | repeat: | |
23b2ce53 RS |
2735 | if (x == 0) |
2736 | return; | |
2737 | ||
2738 | code = GET_CODE (x); | |
2739 | ||
9faa82d8 | 2740 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2741 | for them. */ |
2742 | ||
2743 | switch (code) | |
2744 | { | |
2745 | case REG: | |
0ca5af51 AO |
2746 | case DEBUG_EXPR: |
2747 | case VALUE: | |
23b2ce53 RS |
2748 | case CONST_INT: |
2749 | case CONST_DOUBLE: | |
091a3ac7 | 2750 | case CONST_FIXED: |
69ef87e2 | 2751 | case CONST_VECTOR: |
23b2ce53 RS |
2752 | case SYMBOL_REF: |
2753 | case CODE_LABEL: | |
2754 | case PC: | |
2755 | case CC0: | |
2756 | return; | |
2757 | ||
b5b8b0ac | 2758 | case DEBUG_INSN: |
23b2ce53 RS |
2759 | case INSN: |
2760 | case JUMP_INSN: | |
2761 | case CALL_INSN: | |
2762 | case NOTE: | |
2763 | case LABEL_REF: | |
2764 | case BARRIER: | |
2765 | /* The chain of insns is not being copied. */ | |
2766 | return; | |
750c9258 | 2767 | |
e9a25f70 JL |
2768 | default: |
2769 | break; | |
23b2ce53 RS |
2770 | } |
2771 | ||
2adc7f12 | 2772 | RTX_FLAG (x, used) = 0; |
23b2ce53 RS |
2773 | |
2774 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2775 | length = GET_RTX_LENGTH (code); |
2776 | ||
2777 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2778 | { |
2779 | switch (*format_ptr++) | |
2780 | { | |
2781 | case 'e': | |
32b32b16 AP |
2782 | if (i == length-1) |
2783 | { | |
2784 | x = XEXP (x, i); | |
2785 | goto repeat; | |
2786 | } | |
23b2ce53 RS |
2787 | reset_used_flags (XEXP (x, i)); |
2788 | break; | |
2789 | ||
2790 | case 'E': | |
2791 | for (j = 0; j < XVECLEN (x, i); j++) | |
2792 | reset_used_flags (XVECEXP (x, i, j)); | |
2793 | break; | |
2794 | } | |
2795 | } | |
2796 | } | |
2c07f13b JH |
2797 | |
2798 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used | |
2799 | to look for shared sub-parts. */ | |
2800 | ||
2801 | void | |
2802 | set_used_flags (rtx x) | |
2803 | { | |
2804 | int i, j; | |
2805 | enum rtx_code code; | |
2806 | const char *format_ptr; | |
2807 | ||
2808 | if (x == 0) | |
2809 | return; | |
2810 | ||
2811 | code = GET_CODE (x); | |
2812 | ||
2813 | /* These types may be freely shared so we needn't do any resetting | |
2814 | for them. */ | |
2815 | ||
2816 | switch (code) | |
2817 | { | |
2818 | case REG: | |
0ca5af51 AO |
2819 | case DEBUG_EXPR: |
2820 | case VALUE: | |
2c07f13b JH |
2821 | case CONST_INT: |
2822 | case CONST_DOUBLE: | |
091a3ac7 | 2823 | case CONST_FIXED: |
2c07f13b JH |
2824 | case CONST_VECTOR: |
2825 | case SYMBOL_REF: | |
2826 | case CODE_LABEL: | |
2827 | case PC: | |
2828 | case CC0: | |
2829 | return; | |
2830 | ||
b5b8b0ac | 2831 | case DEBUG_INSN: |
2c07f13b JH |
2832 | case INSN: |
2833 | case JUMP_INSN: | |
2834 | case CALL_INSN: | |
2835 | case NOTE: | |
2836 | case LABEL_REF: | |
2837 | case BARRIER: | |
2838 | /* The chain of insns is not being copied. */ | |
2839 | return; | |
2840 | ||
2841 | default: | |
2842 | break; | |
2843 | } | |
2844 | ||
2845 | RTX_FLAG (x, used) = 1; | |
2846 | ||
2847 | format_ptr = GET_RTX_FORMAT (code); | |
2848 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2849 | { | |
2850 | switch (*format_ptr++) | |
2851 | { | |
2852 | case 'e': | |
2853 | set_used_flags (XEXP (x, i)); | |
2854 | break; | |
2855 | ||
2856 | case 'E': | |
2857 | for (j = 0; j < XVECLEN (x, i); j++) | |
2858 | set_used_flags (XVECEXP (x, i, j)); | |
2859 | break; | |
2860 | } | |
2861 | } | |
2862 | } | |
23b2ce53 RS |
2863 | \f |
2864 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2865 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2866 | OTHER must be valid as a SET_DEST. */ | |
2867 | ||
2868 | rtx | |
502b8322 | 2869 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
2870 | { |
2871 | while (1) | |
2872 | switch (GET_CODE (other)) | |
2873 | { | |
2874 | case SUBREG: | |
2875 | other = SUBREG_REG (other); | |
2876 | break; | |
2877 | case STRICT_LOW_PART: | |
2878 | case SIGN_EXTEND: | |
2879 | case ZERO_EXTEND: | |
2880 | other = XEXP (other, 0); | |
2881 | break; | |
2882 | default: | |
2883 | goto done; | |
2884 | } | |
2885 | done: | |
3c0cb5de | 2886 | if ((MEM_P (other) |
23b2ce53 | 2887 | && ! CONSTANT_P (x) |
f8cfc6aa | 2888 | && !REG_P (x) |
23b2ce53 | 2889 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 2890 | || (REG_P (other) |
23b2ce53 RS |
2891 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
2892 | || reg_mentioned_p (other, x)))) | |
2893 | { | |
2894 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2895 | emit_move_insn (temp, x); | |
2896 | return temp; | |
2897 | } | |
2898 | return x; | |
2899 | } | |
2900 | \f | |
2901 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2902 | ||
2903 | /* Return the first insn of the current sequence or current function. */ | |
2904 | ||
2905 | rtx | |
502b8322 | 2906 | get_insns (void) |
23b2ce53 RS |
2907 | { |
2908 | return first_insn; | |
2909 | } | |
2910 | ||
3dec4024 JH |
2911 | /* Specify a new insn as the first in the chain. */ |
2912 | ||
2913 | void | |
502b8322 | 2914 | set_first_insn (rtx insn) |
3dec4024 | 2915 | { |
5b0264cb | 2916 | gcc_assert (!PREV_INSN (insn)); |
3dec4024 JH |
2917 | first_insn = insn; |
2918 | } | |
2919 | ||
23b2ce53 RS |
2920 | /* Return the last insn emitted in current sequence or current function. */ |
2921 | ||
2922 | rtx | |
502b8322 | 2923 | get_last_insn (void) |
23b2ce53 RS |
2924 | { |
2925 | return last_insn; | |
2926 | } | |
2927 | ||
2928 | /* Specify a new insn as the last in the chain. */ | |
2929 | ||
2930 | void | |
502b8322 | 2931 | set_last_insn (rtx insn) |
23b2ce53 | 2932 | { |
5b0264cb | 2933 | gcc_assert (!NEXT_INSN (insn)); |
23b2ce53 RS |
2934 | last_insn = insn; |
2935 | } | |
2936 | ||
2937 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2938 | ||
2939 | rtx | |
502b8322 | 2940 | get_last_insn_anywhere (void) |
23b2ce53 RS |
2941 | { |
2942 | struct sequence_stack *stack; | |
2943 | if (last_insn) | |
2944 | return last_insn; | |
49ad7cfa | 2945 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2946 | if (stack->last != 0) |
2947 | return stack->last; | |
2948 | return 0; | |
2949 | } | |
2950 | ||
2a496e8b JDA |
2951 | /* Return the first nonnote insn emitted in current sequence or current |
2952 | function. This routine looks inside SEQUENCEs. */ | |
2953 | ||
2954 | rtx | |
502b8322 | 2955 | get_first_nonnote_insn (void) |
2a496e8b | 2956 | { |
91373fe8 JDA |
2957 | rtx insn = first_insn; |
2958 | ||
2959 | if (insn) | |
2960 | { | |
2961 | if (NOTE_P (insn)) | |
2962 | for (insn = next_insn (insn); | |
2963 | insn && NOTE_P (insn); | |
2964 | insn = next_insn (insn)) | |
2965 | continue; | |
2966 | else | |
2967 | { | |
2ca202e7 | 2968 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2969 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2970 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2971 | } | |
2972 | } | |
2a496e8b JDA |
2973 | |
2974 | return insn; | |
2975 | } | |
2976 | ||
2977 | /* Return the last nonnote insn emitted in current sequence or current | |
2978 | function. This routine looks inside SEQUENCEs. */ | |
2979 | ||
2980 | rtx | |
502b8322 | 2981 | get_last_nonnote_insn (void) |
2a496e8b | 2982 | { |
91373fe8 JDA |
2983 | rtx insn = last_insn; |
2984 | ||
2985 | if (insn) | |
2986 | { | |
2987 | if (NOTE_P (insn)) | |
2988 | for (insn = previous_insn (insn); | |
2989 | insn && NOTE_P (insn); | |
2990 | insn = previous_insn (insn)) | |
2991 | continue; | |
2992 | else | |
2993 | { | |
2ca202e7 | 2994 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2995 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2996 | insn = XVECEXP (PATTERN (insn), 0, | |
2997 | XVECLEN (PATTERN (insn), 0) - 1); | |
2998 | } | |
2999 | } | |
2a496e8b JDA |
3000 | |
3001 | return insn; | |
3002 | } | |
3003 | ||
23b2ce53 RS |
3004 | /* Return a number larger than any instruction's uid in this function. */ |
3005 | ||
3006 | int | |
502b8322 | 3007 | get_max_uid (void) |
23b2ce53 RS |
3008 | { |
3009 | return cur_insn_uid; | |
3010 | } | |
b5b8b0ac AO |
3011 | |
3012 | /* Return the number of actual (non-debug) insns emitted in this | |
3013 | function. */ | |
3014 | ||
3015 | int | |
3016 | get_max_insn_count (void) | |
3017 | { | |
3018 | int n = cur_insn_uid; | |
3019 | ||
3020 | /* The table size must be stable across -g, to avoid codegen | |
3021 | differences due to debug insns, and not be affected by | |
3022 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
3023 | debugging of -fcompare-debug failures. */ | |
3024 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3025 | n -= cur_debug_insn_uid; | |
3026 | else | |
3027 | n -= MIN_NONDEBUG_INSN_UID; | |
3028 | ||
3029 | return n; | |
3030 | } | |
3031 | ||
23b2ce53 RS |
3032 | \f |
3033 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
3034 | of the sequence. */ | |
3035 | ||
3036 | rtx | |
502b8322 | 3037 | next_insn (rtx insn) |
23b2ce53 | 3038 | { |
75547801 KG |
3039 | if (insn) |
3040 | { | |
3041 | insn = NEXT_INSN (insn); | |
3042 | if (insn && NONJUMP_INSN_P (insn) | |
3043 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3044 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3045 | } | |
23b2ce53 | 3046 | |
75547801 | 3047 | return insn; |
23b2ce53 RS |
3048 | } |
3049 | ||
3050 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3051 | of the sequence. */ | |
3052 | ||
3053 | rtx | |
502b8322 | 3054 | previous_insn (rtx insn) |
23b2ce53 | 3055 | { |
75547801 KG |
3056 | if (insn) |
3057 | { | |
3058 | insn = PREV_INSN (insn); | |
3059 | if (insn && NONJUMP_INSN_P (insn) | |
3060 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3061 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
3062 | } | |
23b2ce53 | 3063 | |
75547801 | 3064 | return insn; |
23b2ce53 RS |
3065 | } |
3066 | ||
3067 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3068 | look inside SEQUENCEs. */ | |
3069 | ||
3070 | rtx | |
502b8322 | 3071 | next_nonnote_insn (rtx insn) |
23b2ce53 | 3072 | { |
75547801 KG |
3073 | while (insn) |
3074 | { | |
3075 | insn = NEXT_INSN (insn); | |
3076 | if (insn == 0 || !NOTE_P (insn)) | |
3077 | break; | |
3078 | } | |
23b2ce53 | 3079 | |
75547801 | 3080 | return insn; |
23b2ce53 RS |
3081 | } |
3082 | ||
1e211590 DD |
3083 | /* Return the next insn after INSN that is not a NOTE, but stop the |
3084 | search before we enter another basic block. This routine does not | |
3085 | look inside SEQUENCEs. */ | |
3086 | ||
3087 | rtx | |
3088 | next_nonnote_insn_bb (rtx insn) | |
3089 | { | |
3090 | while (insn) | |
3091 | { | |
3092 | insn = NEXT_INSN (insn); | |
3093 | if (insn == 0 || !NOTE_P (insn)) | |
3094 | break; | |
3095 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3096 | return NULL_RTX; | |
3097 | } | |
3098 | ||
3099 | return insn; | |
3100 | } | |
3101 | ||
23b2ce53 RS |
3102 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3103 | not look inside SEQUENCEs. */ | |
3104 | ||
3105 | rtx | |
502b8322 | 3106 | prev_nonnote_insn (rtx insn) |
23b2ce53 | 3107 | { |
75547801 KG |
3108 | while (insn) |
3109 | { | |
3110 | insn = PREV_INSN (insn); | |
3111 | if (insn == 0 || !NOTE_P (insn)) | |
3112 | break; | |
3113 | } | |
23b2ce53 | 3114 | |
75547801 | 3115 | return insn; |
23b2ce53 RS |
3116 | } |
3117 | ||
896aa4ea DD |
3118 | /* Return the previous insn before INSN that is not a NOTE, but stop |
3119 | the search before we enter another basic block. This routine does | |
3120 | not look inside SEQUENCEs. */ | |
3121 | ||
3122 | rtx | |
3123 | prev_nonnote_insn_bb (rtx insn) | |
3124 | { | |
3125 | while (insn) | |
3126 | { | |
3127 | insn = PREV_INSN (insn); | |
3128 | if (insn == 0 || !NOTE_P (insn)) | |
3129 | break; | |
3130 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3131 | return NULL_RTX; | |
3132 | } | |
3133 | ||
3134 | return insn; | |
3135 | } | |
3136 | ||
b5b8b0ac AO |
3137 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3138 | routine does not look inside SEQUENCEs. */ | |
3139 | ||
3140 | rtx | |
3141 | next_nondebug_insn (rtx insn) | |
3142 | { | |
3143 | while (insn) | |
3144 | { | |
3145 | insn = NEXT_INSN (insn); | |
3146 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3147 | break; | |
3148 | } | |
3149 | ||
3150 | return insn; | |
3151 | } | |
3152 | ||
3153 | /* Return the previous insn before INSN that is not a DEBUG_INSN. | |
3154 | This routine does not look inside SEQUENCEs. */ | |
3155 | ||
3156 | rtx | |
3157 | prev_nondebug_insn (rtx insn) | |
3158 | { | |
3159 | while (insn) | |
3160 | { | |
3161 | insn = PREV_INSN (insn); | |
3162 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3163 | break; | |
3164 | } | |
3165 | ||
3166 | return insn; | |
3167 | } | |
3168 | ||
23b2ce53 RS |
3169 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3170 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3171 | SEQUENCEs. */ |
23b2ce53 RS |
3172 | |
3173 | rtx | |
502b8322 | 3174 | next_real_insn (rtx insn) |
23b2ce53 | 3175 | { |
75547801 KG |
3176 | while (insn) |
3177 | { | |
3178 | insn = NEXT_INSN (insn); | |
3179 | if (insn == 0 || INSN_P (insn)) | |
3180 | break; | |
3181 | } | |
23b2ce53 | 3182 | |
75547801 | 3183 | return insn; |
23b2ce53 RS |
3184 | } |
3185 | ||
3186 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3187 | or 0, if there is none. This routine does not look inside | |
3188 | SEQUENCEs. */ | |
3189 | ||
3190 | rtx | |
502b8322 | 3191 | prev_real_insn (rtx insn) |
23b2ce53 | 3192 | { |
75547801 KG |
3193 | while (insn) |
3194 | { | |
3195 | insn = PREV_INSN (insn); | |
3196 | if (insn == 0 || INSN_P (insn)) | |
3197 | break; | |
3198 | } | |
23b2ce53 | 3199 | |
75547801 | 3200 | return insn; |
23b2ce53 RS |
3201 | } |
3202 | ||
ee960939 OH |
3203 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3204 | This routine does not look inside SEQUENCEs. */ | |
3205 | ||
3206 | rtx | |
502b8322 | 3207 | last_call_insn (void) |
ee960939 OH |
3208 | { |
3209 | rtx insn; | |
3210 | ||
3211 | for (insn = get_last_insn (); | |
4b4bf941 | 3212 | insn && !CALL_P (insn); |
ee960939 OH |
3213 | insn = PREV_INSN (insn)) |
3214 | ; | |
3215 | ||
3216 | return insn; | |
3217 | } | |
3218 | ||
23b2ce53 RS |
3219 | /* Find the next insn after INSN that really does something. This routine |
3220 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3221 | same as next_real_insn. */ | |
3222 | ||
69732dcb | 3223 | int |
4f588890 | 3224 | active_insn_p (const_rtx insn) |
69732dcb | 3225 | { |
4b4bf941 JQ |
3226 | return (CALL_P (insn) || JUMP_P (insn) |
3227 | || (NONJUMP_INSN_P (insn) | |
23b8ba81 RH |
3228 | && (! reload_completed |
3229 | || (GET_CODE (PATTERN (insn)) != USE | |
3230 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3231 | } |
3232 | ||
23b2ce53 | 3233 | rtx |
502b8322 | 3234 | next_active_insn (rtx insn) |
23b2ce53 | 3235 | { |
75547801 KG |
3236 | while (insn) |
3237 | { | |
3238 | insn = NEXT_INSN (insn); | |
3239 | if (insn == 0 || active_insn_p (insn)) | |
3240 | break; | |
3241 | } | |
23b2ce53 | 3242 | |
75547801 | 3243 | return insn; |
23b2ce53 RS |
3244 | } |
3245 | ||
3246 | /* Find the last insn before INSN that really does something. This routine | |
3247 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3248 | same as prev_real_insn. */ | |
3249 | ||
3250 | rtx | |
502b8322 | 3251 | prev_active_insn (rtx insn) |
23b2ce53 | 3252 | { |
75547801 KG |
3253 | while (insn) |
3254 | { | |
3255 | insn = PREV_INSN (insn); | |
3256 | if (insn == 0 || active_insn_p (insn)) | |
3257 | break; | |
3258 | } | |
23b2ce53 | 3259 | |
75547801 | 3260 | return insn; |
23b2ce53 RS |
3261 | } |
3262 | ||
3263 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
3264 | ||
3265 | rtx | |
502b8322 | 3266 | next_label (rtx insn) |
23b2ce53 | 3267 | { |
75547801 KG |
3268 | while (insn) |
3269 | { | |
3270 | insn = NEXT_INSN (insn); | |
3271 | if (insn == 0 || LABEL_P (insn)) | |
3272 | break; | |
3273 | } | |
23b2ce53 | 3274 | |
75547801 | 3275 | return insn; |
23b2ce53 RS |
3276 | } |
3277 | ||
3278 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
3279 | ||
3280 | rtx | |
502b8322 | 3281 | prev_label (rtx insn) |
23b2ce53 | 3282 | { |
75547801 KG |
3283 | while (insn) |
3284 | { | |
3285 | insn = PREV_INSN (insn); | |
3286 | if (insn == 0 || LABEL_P (insn)) | |
3287 | break; | |
3288 | } | |
23b2ce53 | 3289 | |
75547801 | 3290 | return insn; |
23b2ce53 | 3291 | } |
6c2511d3 RS |
3292 | |
3293 | /* Return the last label to mark the same position as LABEL. Return null | |
3294 | if LABEL itself is null. */ | |
3295 | ||
3296 | rtx | |
3297 | skip_consecutive_labels (rtx label) | |
3298 | { | |
3299 | rtx insn; | |
3300 | ||
3301 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | |
3302 | if (LABEL_P (insn)) | |
3303 | label = insn; | |
3304 | ||
3305 | return label; | |
3306 | } | |
23b2ce53 RS |
3307 | \f |
3308 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
3309 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3310 | and REG_CC_USER notes so we can find it. */ | |
3311 | ||
3312 | void | |
502b8322 | 3313 | link_cc0_insns (rtx insn) |
c572e5ba JVA |
3314 | { |
3315 | rtx user = next_nonnote_insn (insn); | |
3316 | ||
4b4bf941 | 3317 | if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE) |
c572e5ba JVA |
3318 | user = XVECEXP (PATTERN (user), 0, 0); |
3319 | ||
65c5f2a6 ILT |
3320 | add_reg_note (user, REG_CC_SETTER, insn); |
3321 | add_reg_note (insn, REG_CC_USER, user); | |
c572e5ba JVA |
3322 | } |
3323 | ||
23b2ce53 RS |
3324 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3325 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3326 | applied to the result of this function should yield INSN). | |
3327 | ||
3328 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3329 | is present, it contains the insn that uses CC0. | |
3330 | ||
3331 | Return 0 if we can't find the insn. */ | |
3332 | ||
3333 | rtx | |
502b8322 | 3334 | next_cc0_user (rtx insn) |
23b2ce53 | 3335 | { |
906c4e36 | 3336 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3337 | |
3338 | if (note) | |
3339 | return XEXP (note, 0); | |
3340 | ||
3341 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3342 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
23b2ce53 RS |
3343 | insn = XVECEXP (PATTERN (insn), 0, 0); |
3344 | ||
2c3c49de | 3345 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
3346 | return insn; |
3347 | ||
3348 | return 0; | |
3349 | } | |
3350 | ||
3351 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3352 | note, it is the previous insn. */ | |
3353 | ||
3354 | rtx | |
502b8322 | 3355 | prev_cc0_setter (rtx insn) |
23b2ce53 | 3356 | { |
906c4e36 | 3357 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3358 | |
3359 | if (note) | |
3360 | return XEXP (note, 0); | |
3361 | ||
3362 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3363 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 RS |
3364 | |
3365 | return insn; | |
3366 | } | |
3367 | #endif | |
e5bef2e4 | 3368 | |
594f8779 RZ |
3369 | #ifdef AUTO_INC_DEC |
3370 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3371 | ||
3372 | static int | |
3373 | find_auto_inc (rtx *xp, void *data) | |
3374 | { | |
3375 | rtx x = *xp; | |
5ead67f6 | 3376 | rtx reg = (rtx) data; |
594f8779 RZ |
3377 | |
3378 | if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC) | |
3379 | return 0; | |
3380 | ||
3381 | switch (GET_CODE (x)) | |
3382 | { | |
3383 | case PRE_DEC: | |
3384 | case PRE_INC: | |
3385 | case POST_DEC: | |
3386 | case POST_INC: | |
3387 | case PRE_MODIFY: | |
3388 | case POST_MODIFY: | |
3389 | if (rtx_equal_p (reg, XEXP (x, 0))) | |
3390 | return 1; | |
3391 | break; | |
3392 | ||
3393 | default: | |
3394 | gcc_unreachable (); | |
3395 | } | |
3396 | return -1; | |
3397 | } | |
3398 | #endif | |
3399 | ||
e5bef2e4 HB |
3400 | /* Increment the label uses for all labels present in rtx. */ |
3401 | ||
3402 | static void | |
502b8322 | 3403 | mark_label_nuses (rtx x) |
e5bef2e4 | 3404 | { |
b3694847 SS |
3405 | enum rtx_code code; |
3406 | int i, j; | |
3407 | const char *fmt; | |
e5bef2e4 HB |
3408 | |
3409 | code = GET_CODE (x); | |
7537fc90 | 3410 | if (code == LABEL_REF && LABEL_P (XEXP (x, 0))) |
e5bef2e4 HB |
3411 | LABEL_NUSES (XEXP (x, 0))++; |
3412 | ||
3413 | fmt = GET_RTX_FORMAT (code); | |
3414 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3415 | { | |
3416 | if (fmt[i] == 'e') | |
0fb7aeda | 3417 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3418 | else if (fmt[i] == 'E') |
0fb7aeda | 3419 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3420 | mark_label_nuses (XVECEXP (x, i, j)); |
3421 | } | |
3422 | } | |
3423 | ||
23b2ce53 RS |
3424 | \f |
3425 | /* Try splitting insns that can be split for better scheduling. | |
3426 | PAT is the pattern which might split. | |
3427 | TRIAL is the insn providing PAT. | |
cc2902df | 3428 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3429 | |
3430 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3431 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3432 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3433 | ||
3434 | rtx | |
502b8322 | 3435 | try_split (rtx pat, rtx trial, int last) |
23b2ce53 RS |
3436 | { |
3437 | rtx before = PREV_INSN (trial); | |
3438 | rtx after = NEXT_INSN (trial); | |
23b2ce53 | 3439 | int has_barrier = 0; |
4a8cae83 | 3440 | rtx note, seq, tem; |
6b24c259 | 3441 | int probability; |
599aedd9 RH |
3442 | rtx insn_last, insn; |
3443 | int njumps = 0; | |
6b24c259 | 3444 | |
cd9c1ca8 RH |
3445 | /* We're not good at redistributing frame information. */ |
3446 | if (RTX_FRAME_RELATED_P (trial)) | |
3447 | return trial; | |
3448 | ||
6b24c259 JH |
3449 | if (any_condjump_p (trial) |
3450 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3451 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3452 | probability = split_branch_probability; | |
3453 | ||
3454 | seq = split_insns (pat, trial); | |
3455 | ||
3456 | split_branch_probability = -1; | |
23b2ce53 RS |
3457 | |
3458 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3459 | We may need to handle this specially. */ | |
4b4bf941 | 3460 | if (after && BARRIER_P (after)) |
23b2ce53 RS |
3461 | { |
3462 | has_barrier = 1; | |
3463 | after = NEXT_INSN (after); | |
3464 | } | |
3465 | ||
599aedd9 RH |
3466 | if (!seq) |
3467 | return trial; | |
3468 | ||
3469 | /* Avoid infinite loop if any insn of the result matches | |
3470 | the original pattern. */ | |
3471 | insn_last = seq; | |
3472 | while (1) | |
23b2ce53 | 3473 | { |
599aedd9 RH |
3474 | if (INSN_P (insn_last) |
3475 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3476 | return trial; | |
3477 | if (!NEXT_INSN (insn_last)) | |
3478 | break; | |
3479 | insn_last = NEXT_INSN (insn_last); | |
3480 | } | |
750c9258 | 3481 | |
6fb5fa3c DB |
3482 | /* We will be adding the new sequence to the function. The splitters |
3483 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3484 | unshare_all_rtl_in_chain (seq); | |
3485 | ||
599aedd9 RH |
3486 | /* Mark labels. */ |
3487 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3488 | { | |
4b4bf941 | 3489 | if (JUMP_P (insn)) |
599aedd9 RH |
3490 | { |
3491 | mark_jump_label (PATTERN (insn), insn, 0); | |
3492 | njumps++; | |
3493 | if (probability != -1 | |
3494 | && any_condjump_p (insn) | |
3495 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3496 | { |
599aedd9 RH |
3497 | /* We can preserve the REG_BR_PROB notes only if exactly |
3498 | one jump is created, otherwise the machine description | |
3499 | is responsible for this step using | |
3500 | split_branch_probability variable. */ | |
5b0264cb | 3501 | gcc_assert (njumps == 1); |
65c5f2a6 | 3502 | add_reg_note (insn, REG_BR_PROB, GEN_INT (probability)); |
2f937369 | 3503 | } |
599aedd9 RH |
3504 | } |
3505 | } | |
3506 | ||
3507 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3508 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
4b4bf941 | 3509 | if (CALL_P (trial)) |
599aedd9 RH |
3510 | { |
3511 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3512 | if (CALL_P (insn)) |
599aedd9 | 3513 | { |
f6a1f3f6 RH |
3514 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3515 | while (*p) | |
3516 | p = &XEXP (*p, 1); | |
3517 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
599aedd9 | 3518 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
d0539838 CC |
3519 | |
3520 | /* Update the debug information for the CALL_INSN. */ | |
3521 | if (flag_enable_icf_debug) | |
3522 | (*debug_hooks->copy_call_info) (trial, insn); | |
599aedd9 RH |
3523 | } |
3524 | } | |
4b5e8abe | 3525 | |
599aedd9 RH |
3526 | /* Copy notes, particularly those related to the CFG. */ |
3527 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3528 | { | |
3529 | switch (REG_NOTE_KIND (note)) | |
3530 | { | |
3531 | case REG_EH_REGION: | |
1d65f45c | 3532 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3533 | break; |
216183ce | 3534 | |
599aedd9 RH |
3535 | case REG_NORETURN: |
3536 | case REG_SETJMP: | |
594f8779 | 3537 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3538 | { |
4b4bf941 | 3539 | if (CALL_P (insn)) |
65c5f2a6 | 3540 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3541 | } |
599aedd9 | 3542 | break; |
d6e95df8 | 3543 | |
599aedd9 | 3544 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3545 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3546 | { |
4b4bf941 | 3547 | if (JUMP_P (insn)) |
65c5f2a6 | 3548 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3549 | } |
599aedd9 | 3550 | break; |
e5bef2e4 | 3551 | |
594f8779 RZ |
3552 | #ifdef AUTO_INC_DEC |
3553 | case REG_INC: | |
3554 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3555 | { | |
3556 | rtx reg = XEXP (note, 0); | |
3557 | if (!FIND_REG_INC_NOTE (insn, reg) | |
3558 | && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0) | |
65c5f2a6 | 3559 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3560 | } |
3561 | break; | |
3562 | #endif | |
3563 | ||
599aedd9 RH |
3564 | default: |
3565 | break; | |
23b2ce53 | 3566 | } |
599aedd9 RH |
3567 | } |
3568 | ||
3569 | /* If there are LABELS inside the split insns increment the | |
3570 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3571 | if (INSN_P (trial)) |
599aedd9 RH |
3572 | { |
3573 | insn = insn_last; | |
3574 | while (insn != NULL_RTX) | |
23b2ce53 | 3575 | { |
cf7c4aa6 | 3576 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3577 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3578 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3579 | |
599aedd9 RH |
3580 | insn = PREV_INSN (insn); |
3581 | } | |
23b2ce53 RS |
3582 | } |
3583 | ||
0435312e | 3584 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
599aedd9 RH |
3585 | |
3586 | delete_insn (trial); | |
3587 | if (has_barrier) | |
3588 | emit_barrier_after (tem); | |
3589 | ||
3590 | /* Recursively call try_split for each new insn created; by the | |
3591 | time control returns here that insn will be fully split, so | |
3592 | set LAST and continue from the insn after the one returned. | |
3593 | We can't use next_active_insn here since AFTER may be a note. | |
3594 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3595 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3596 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3597 | tem = try_split (PATTERN (tem), tem, 1); | |
3598 | ||
3599 | /* Return either the first or the last insn, depending on which was | |
3600 | requested. */ | |
3601 | return last | |
3602 | ? (after ? PREV_INSN (after) : last_insn) | |
3603 | : NEXT_INSN (before); | |
23b2ce53 RS |
3604 | } |
3605 | \f | |
3606 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3607 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
3608 | |
3609 | rtx | |
502b8322 | 3610 | make_insn_raw (rtx pattern) |
23b2ce53 | 3611 | { |
b3694847 | 3612 | rtx insn; |
23b2ce53 | 3613 | |
1f8f4a0b | 3614 | insn = rtx_alloc (INSN); |
23b2ce53 | 3615 | |
43127294 | 3616 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3617 | PATTERN (insn) = pattern; |
3618 | INSN_CODE (insn) = -1; | |
1632afca | 3619 | REG_NOTES (insn) = NULL; |
55e092c4 | 3620 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3621 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3622 | |
47984720 NC |
3623 | #ifdef ENABLE_RTL_CHECKING |
3624 | if (insn | |
2c3c49de | 3625 | && INSN_P (insn) |
47984720 NC |
3626 | && (returnjump_p (insn) |
3627 | || (GET_CODE (insn) == SET | |
3628 | && SET_DEST (insn) == pc_rtx))) | |
3629 | { | |
d4ee4d25 | 3630 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3631 | debug_rtx (insn); |
3632 | } | |
3633 | #endif | |
750c9258 | 3634 | |
23b2ce53 RS |
3635 | return insn; |
3636 | } | |
3637 | ||
b5b8b0ac AO |
3638 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
3639 | ||
3640 | rtx | |
3641 | make_debug_insn_raw (rtx pattern) | |
3642 | { | |
3643 | rtx insn; | |
3644 | ||
3645 | insn = rtx_alloc (DEBUG_INSN); | |
3646 | INSN_UID (insn) = cur_debug_insn_uid++; | |
3647 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3648 | INSN_UID (insn) = cur_insn_uid++; | |
3649 | ||
3650 | PATTERN (insn) = pattern; | |
3651 | INSN_CODE (insn) = -1; | |
3652 | REG_NOTES (insn) = NULL; | |
3653 | INSN_LOCATOR (insn) = curr_insn_locator (); | |
3654 | BLOCK_FOR_INSN (insn) = NULL; | |
3655 | ||
3656 | return insn; | |
3657 | } | |
3658 | ||
2f937369 | 3659 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3660 | |
38109dab | 3661 | rtx |
502b8322 | 3662 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3663 | { |
b3694847 | 3664 | rtx insn; |
23b2ce53 | 3665 | |
4b1f5e8c | 3666 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 3667 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3668 | |
3669 | PATTERN (insn) = pattern; | |
3670 | INSN_CODE (insn) = -1; | |
1632afca RS |
3671 | REG_NOTES (insn) = NULL; |
3672 | JUMP_LABEL (insn) = NULL; | |
55e092c4 | 3673 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3674 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3675 | |
3676 | return insn; | |
3677 | } | |
aff507f4 | 3678 | |
2f937369 | 3679 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 RK |
3680 | |
3681 | static rtx | |
502b8322 | 3682 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3683 | { |
b3694847 | 3684 | rtx insn; |
aff507f4 RK |
3685 | |
3686 | insn = rtx_alloc (CALL_INSN); | |
3687 | INSN_UID (insn) = cur_insn_uid++; | |
3688 | ||
3689 | PATTERN (insn) = pattern; | |
3690 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3691 | REG_NOTES (insn) = NULL; |
3692 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
55e092c4 | 3693 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3694 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3695 | |
3696 | return insn; | |
3697 | } | |
23b2ce53 RS |
3698 | \f |
3699 | /* Add INSN to the end of the doubly-linked list. | |
3700 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3701 | ||
3702 | void | |
502b8322 | 3703 | add_insn (rtx insn) |
23b2ce53 RS |
3704 | { |
3705 | PREV_INSN (insn) = last_insn; | |
3706 | NEXT_INSN (insn) = 0; | |
3707 | ||
3708 | if (NULL != last_insn) | |
3709 | NEXT_INSN (last_insn) = insn; | |
3710 | ||
3711 | if (NULL == first_insn) | |
3712 | first_insn = insn; | |
3713 | ||
3714 | last_insn = insn; | |
3715 | } | |
3716 | ||
a0ae8e8d RK |
3717 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3718 | the next should be the only functions called to insert an insn once | |
ba213285 | 3719 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 3720 | SEQUENCE. */ |
23b2ce53 RS |
3721 | |
3722 | void | |
6fb5fa3c | 3723 | add_insn_after (rtx insn, rtx after, basic_block bb) |
23b2ce53 RS |
3724 | { |
3725 | rtx next = NEXT_INSN (after); | |
3726 | ||
5b0264cb | 3727 | gcc_assert (!optimize || !INSN_DELETED_P (after)); |
ba213285 | 3728 | |
23b2ce53 RS |
3729 | NEXT_INSN (insn) = next; |
3730 | PREV_INSN (insn) = after; | |
3731 | ||
3732 | if (next) | |
3733 | { | |
3734 | PREV_INSN (next) = insn; | |
4b4bf941 | 3735 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
23b2ce53 RS |
3736 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; |
3737 | } | |
3738 | else if (last_insn == after) | |
3739 | last_insn = insn; | |
3740 | else | |
3741 | { | |
49ad7cfa | 3742 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
3743 | /* Scan all pending sequences too. */ |
3744 | for (; stack; stack = stack->next) | |
3745 | if (after == stack->last) | |
fef0509b RK |
3746 | { |
3747 | stack->last = insn; | |
3748 | break; | |
3749 | } | |
a0ae8e8d | 3750 | |
5b0264cb | 3751 | gcc_assert (stack); |
23b2ce53 RS |
3752 | } |
3753 | ||
4b4bf941 JQ |
3754 | if (!BARRIER_P (after) |
3755 | && !BARRIER_P (insn) | |
3c030e88 JH |
3756 | && (bb = BLOCK_FOR_INSN (after))) |
3757 | { | |
3758 | set_block_for_insn (insn, bb); | |
38c1593d | 3759 | if (INSN_P (insn)) |
6fb5fa3c | 3760 | df_insn_rescan (insn); |
3c030e88 | 3761 | /* Should not happen as first in the BB is always |
a1f300c0 | 3762 | either NOTE or LABEL. */ |
a813c111 | 3763 | if (BB_END (bb) == after |
3c030e88 | 3764 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 3765 | && !BARRIER_P (insn) |
a38e7aa5 | 3766 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
a813c111 | 3767 | BB_END (bb) = insn; |
3c030e88 JH |
3768 | } |
3769 | ||
23b2ce53 | 3770 | NEXT_INSN (after) = insn; |
4b4bf941 | 3771 | if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE) |
23b2ce53 RS |
3772 | { |
3773 | rtx sequence = PATTERN (after); | |
3774 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3775 | } | |
3776 | } | |
3777 | ||
a0ae8e8d | 3778 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
6fb5fa3c DB |
3779 | the previous should be the only functions called to insert an insn |
3780 | once delay slots have been filled since only they know how to | |
3781 | update a SEQUENCE. If BB is NULL, an attempt is made to infer the | |
3782 | bb from before. */ | |
a0ae8e8d RK |
3783 | |
3784 | void | |
6fb5fa3c | 3785 | add_insn_before (rtx insn, rtx before, basic_block bb) |
a0ae8e8d RK |
3786 | { |
3787 | rtx prev = PREV_INSN (before); | |
3788 | ||
5b0264cb | 3789 | gcc_assert (!optimize || !INSN_DELETED_P (before)); |
ba213285 | 3790 | |
a0ae8e8d RK |
3791 | PREV_INSN (insn) = prev; |
3792 | NEXT_INSN (insn) = before; | |
3793 | ||
3794 | if (prev) | |
3795 | { | |
3796 | NEXT_INSN (prev) = insn; | |
4b4bf941 | 3797 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
a0ae8e8d RK |
3798 | { |
3799 | rtx sequence = PATTERN (prev); | |
3800 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3801 | } | |
3802 | } | |
3803 | else if (first_insn == before) | |
3804 | first_insn = insn; | |
3805 | else | |
3806 | { | |
49ad7cfa | 3807 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
3808 | /* Scan all pending sequences too. */ |
3809 | for (; stack; stack = stack->next) | |
3810 | if (before == stack->first) | |
fef0509b RK |
3811 | { |
3812 | stack->first = insn; | |
3813 | break; | |
3814 | } | |
a0ae8e8d | 3815 | |
5b0264cb | 3816 | gcc_assert (stack); |
a0ae8e8d RK |
3817 | } |
3818 | ||
6fb5fa3c DB |
3819 | if (!bb |
3820 | && !BARRIER_P (before) | |
3821 | && !BARRIER_P (insn)) | |
3822 | bb = BLOCK_FOR_INSN (before); | |
3823 | ||
3824 | if (bb) | |
3c030e88 JH |
3825 | { |
3826 | set_block_for_insn (insn, bb); | |
38c1593d | 3827 | if (INSN_P (insn)) |
6fb5fa3c | 3828 | df_insn_rescan (insn); |
5b0264cb | 3829 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 3830 | LABEL. */ |
5b0264cb NS |
3831 | gcc_assert (BB_HEAD (bb) != insn |
3832 | /* Avoid clobbering of structure when creating new BB. */ | |
3833 | || BARRIER_P (insn) | |
a38e7aa5 | 3834 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 JH |
3835 | } |
3836 | ||
a0ae8e8d | 3837 | PREV_INSN (before) = insn; |
4b4bf941 | 3838 | if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE) |
a0ae8e8d RK |
3839 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; |
3840 | } | |
3841 | ||
6fb5fa3c DB |
3842 | |
3843 | /* Replace insn with an deleted instruction note. */ | |
3844 | ||
0ce2b299 EB |
3845 | void |
3846 | set_insn_deleted (rtx insn) | |
6fb5fa3c DB |
3847 | { |
3848 | df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn)); | |
3849 | PUT_CODE (insn, NOTE); | |
3850 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
3851 | } | |
3852 | ||
3853 | ||
89e99eea DB |
3854 | /* Remove an insn from its doubly-linked list. This function knows how |
3855 | to handle sequences. */ | |
3856 | void | |
502b8322 | 3857 | remove_insn (rtx insn) |
89e99eea DB |
3858 | { |
3859 | rtx next = NEXT_INSN (insn); | |
3860 | rtx prev = PREV_INSN (insn); | |
53c17031 JH |
3861 | basic_block bb; |
3862 | ||
6fb5fa3c DB |
3863 | /* Later in the code, the block will be marked dirty. */ |
3864 | df_insn_delete (NULL, INSN_UID (insn)); | |
3865 | ||
89e99eea DB |
3866 | if (prev) |
3867 | { | |
3868 | NEXT_INSN (prev) = next; | |
4b4bf941 | 3869 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea DB |
3870 | { |
3871 | rtx sequence = PATTERN (prev); | |
3872 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3873 | } | |
3874 | } | |
3875 | else if (first_insn == insn) | |
3876 | first_insn = next; | |
3877 | else | |
3878 | { | |
49ad7cfa | 3879 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3880 | /* Scan all pending sequences too. */ |
3881 | for (; stack; stack = stack->next) | |
3882 | if (insn == stack->first) | |
3883 | { | |
3884 | stack->first = next; | |
3885 | break; | |
3886 | } | |
3887 | ||
5b0264cb | 3888 | gcc_assert (stack); |
89e99eea DB |
3889 | } |
3890 | ||
3891 | if (next) | |
3892 | { | |
3893 | PREV_INSN (next) = prev; | |
4b4bf941 | 3894 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
89e99eea DB |
3895 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; |
3896 | } | |
3897 | else if (last_insn == insn) | |
3898 | last_insn = prev; | |
3899 | else | |
3900 | { | |
49ad7cfa | 3901 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3902 | /* Scan all pending sequences too. */ |
3903 | for (; stack; stack = stack->next) | |
3904 | if (insn == stack->last) | |
3905 | { | |
3906 | stack->last = prev; | |
3907 | break; | |
3908 | } | |
3909 | ||
5b0264cb | 3910 | gcc_assert (stack); |
89e99eea | 3911 | } |
4b4bf941 | 3912 | if (!BARRIER_P (insn) |
53c17031 JH |
3913 | && (bb = BLOCK_FOR_INSN (insn))) |
3914 | { | |
38c1593d | 3915 | if (INSN_P (insn)) |
6fb5fa3c | 3916 | df_set_bb_dirty (bb); |
a813c111 | 3917 | if (BB_HEAD (bb) == insn) |
53c17031 | 3918 | { |
3bf1e984 RK |
3919 | /* Never ever delete the basic block note without deleting whole |
3920 | basic block. */ | |
5b0264cb | 3921 | gcc_assert (!NOTE_P (insn)); |
a813c111 | 3922 | BB_HEAD (bb) = next; |
53c17031 | 3923 | } |
a813c111 SB |
3924 | if (BB_END (bb) == insn) |
3925 | BB_END (bb) = prev; | |
53c17031 | 3926 | } |
89e99eea DB |
3927 | } |
3928 | ||
ee960939 OH |
3929 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3930 | ||
3931 | void | |
502b8322 | 3932 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 3933 | { |
5b0264cb | 3934 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
3935 | |
3936 | /* Put the register usage information on the CALL. If there is already | |
3937 | some usage information, put ours at the end. */ | |
3938 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3939 | { | |
3940 | rtx link; | |
3941 | ||
3942 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3943 | link = XEXP (link, 1)) | |
3944 | ; | |
3945 | ||
3946 | XEXP (link, 1) = call_fusage; | |
3947 | } | |
3948 | else | |
3949 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3950 | } | |
3951 | ||
23b2ce53 RS |
3952 | /* Delete all insns made since FROM. |
3953 | FROM becomes the new last instruction. */ | |
3954 | ||
3955 | void | |
502b8322 | 3956 | delete_insns_since (rtx from) |
23b2ce53 RS |
3957 | { |
3958 | if (from == 0) | |
3959 | first_insn = 0; | |
3960 | else | |
3961 | NEXT_INSN (from) = 0; | |
3962 | last_insn = from; | |
3963 | } | |
3964 | ||
5dab5552 MS |
3965 | /* This function is deprecated, please use sequences instead. |
3966 | ||
3967 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
3968 | The insns to be moved are those between FROM and TO. |
3969 | They are moved to a new position after the insn AFTER. | |
3970 | AFTER must not be FROM or TO or any insn in between. | |
3971 | ||
3972 | This function does not know about SEQUENCEs and hence should not be | |
3973 | called after delay-slot filling has been done. */ | |
3974 | ||
3975 | void | |
502b8322 | 3976 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
23b2ce53 RS |
3977 | { |
3978 | /* Splice this bunch out of where it is now. */ | |
3979 | if (PREV_INSN (from)) | |
3980 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3981 | if (NEXT_INSN (to)) | |
3982 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
3983 | if (last_insn == to) | |
3984 | last_insn = PREV_INSN (from); | |
3985 | if (first_insn == from) | |
3986 | first_insn = NEXT_INSN (to); | |
3987 | ||
3988 | /* Make the new neighbors point to it and it to them. */ | |
3989 | if (NEXT_INSN (after)) | |
3990 | PREV_INSN (NEXT_INSN (after)) = to; | |
3991 | ||
3992 | NEXT_INSN (to) = NEXT_INSN (after); | |
3993 | PREV_INSN (from) = after; | |
3994 | NEXT_INSN (after) = from; | |
3995 | if (after == last_insn) | |
3996 | last_insn = to; | |
3997 | } | |
3998 | ||
3c030e88 JH |
3999 | /* Same as function above, but take care to update BB boundaries. */ |
4000 | void | |
502b8322 | 4001 | reorder_insns (rtx from, rtx to, rtx after) |
3c030e88 JH |
4002 | { |
4003 | rtx prev = PREV_INSN (from); | |
4004 | basic_block bb, bb2; | |
4005 | ||
4006 | reorder_insns_nobb (from, to, after); | |
4007 | ||
4b4bf941 | 4008 | if (!BARRIER_P (after) |
3c030e88 JH |
4009 | && (bb = BLOCK_FOR_INSN (after))) |
4010 | { | |
4011 | rtx x; | |
6fb5fa3c | 4012 | df_set_bb_dirty (bb); |
68252e27 | 4013 | |
4b4bf941 | 4014 | if (!BARRIER_P (from) |
3c030e88 JH |
4015 | && (bb2 = BLOCK_FOR_INSN (from))) |
4016 | { | |
a813c111 SB |
4017 | if (BB_END (bb2) == to) |
4018 | BB_END (bb2) = prev; | |
6fb5fa3c | 4019 | df_set_bb_dirty (bb2); |
3c030e88 JH |
4020 | } |
4021 | ||
a813c111 SB |
4022 | if (BB_END (bb) == after) |
4023 | BB_END (bb) = to; | |
3c030e88 JH |
4024 | |
4025 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 4026 | if (!BARRIER_P (x)) |
63642d5a | 4027 | df_insn_change_bb (x, bb); |
3c030e88 JH |
4028 | } |
4029 | } | |
4030 | ||
23b2ce53 | 4031 | \f |
2f937369 DM |
4032 | /* Emit insn(s) of given code and pattern |
4033 | at a specified place within the doubly-linked list. | |
23b2ce53 | 4034 | |
2f937369 DM |
4035 | All of the emit_foo global entry points accept an object |
4036 | X which is either an insn list or a PATTERN of a single | |
4037 | instruction. | |
23b2ce53 | 4038 | |
2f937369 DM |
4039 | There are thus a few canonical ways to generate code and |
4040 | emit it at a specific place in the instruction stream. For | |
4041 | example, consider the instruction named SPOT and the fact that | |
4042 | we would like to emit some instructions before SPOT. We might | |
4043 | do it like this: | |
23b2ce53 | 4044 | |
2f937369 DM |
4045 | start_sequence (); |
4046 | ... emit the new instructions ... | |
4047 | insns_head = get_insns (); | |
4048 | end_sequence (); | |
23b2ce53 | 4049 | |
2f937369 | 4050 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4051 | |
2f937369 DM |
4052 | It used to be common to generate SEQUENCE rtl instead, but that |
4053 | is a relic of the past which no longer occurs. The reason is that | |
4054 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4055 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4056 | |
2f937369 | 4057 | /* Make X be output before the instruction BEFORE. */ |
23b2ce53 RS |
4058 | |
4059 | rtx | |
6fb5fa3c | 4060 | emit_insn_before_noloc (rtx x, rtx before, basic_block bb) |
23b2ce53 | 4061 | { |
2f937369 | 4062 | rtx last = before; |
b3694847 | 4063 | rtx insn; |
23b2ce53 | 4064 | |
5b0264cb | 4065 | gcc_assert (before); |
2f937369 DM |
4066 | |
4067 | if (x == NULL_RTX) | |
4068 | return last; | |
4069 | ||
4070 | switch (GET_CODE (x)) | |
23b2ce53 | 4071 | { |
b5b8b0ac | 4072 | case DEBUG_INSN: |
2f937369 DM |
4073 | case INSN: |
4074 | case JUMP_INSN: | |
4075 | case CALL_INSN: | |
4076 | case CODE_LABEL: | |
4077 | case BARRIER: | |
4078 | case NOTE: | |
4079 | insn = x; | |
4080 | while (insn) | |
4081 | { | |
4082 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4083 | add_insn_before (insn, before, bb); |
2f937369 DM |
4084 | last = insn; |
4085 | insn = next; | |
4086 | } | |
4087 | break; | |
4088 | ||
4089 | #ifdef ENABLE_RTL_CHECKING | |
4090 | case SEQUENCE: | |
5b0264cb | 4091 | gcc_unreachable (); |
2f937369 DM |
4092 | break; |
4093 | #endif | |
4094 | ||
4095 | default: | |
4096 | last = make_insn_raw (x); | |
6fb5fa3c | 4097 | add_insn_before (last, before, bb); |
2f937369 | 4098 | break; |
23b2ce53 RS |
4099 | } |
4100 | ||
2f937369 | 4101 | return last; |
23b2ce53 RS |
4102 | } |
4103 | ||
2f937369 | 4104 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4105 | and output it before the instruction BEFORE. */ |
4106 | ||
4107 | rtx | |
a7102479 | 4108 | emit_jump_insn_before_noloc (rtx x, rtx before) |
23b2ce53 | 4109 | { |
d950dee3 | 4110 | rtx insn, last = NULL_RTX; |
aff507f4 | 4111 | |
5b0264cb | 4112 | gcc_assert (before); |
2f937369 DM |
4113 | |
4114 | switch (GET_CODE (x)) | |
aff507f4 | 4115 | { |
b5b8b0ac | 4116 | case DEBUG_INSN: |
2f937369 DM |
4117 | case INSN: |
4118 | case JUMP_INSN: | |
4119 | case CALL_INSN: | |
4120 | case CODE_LABEL: | |
4121 | case BARRIER: | |
4122 | case NOTE: | |
4123 | insn = x; | |
4124 | while (insn) | |
4125 | { | |
4126 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4127 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4128 | last = insn; |
4129 | insn = next; | |
4130 | } | |
4131 | break; | |
4132 | ||
4133 | #ifdef ENABLE_RTL_CHECKING | |
4134 | case SEQUENCE: | |
5b0264cb | 4135 | gcc_unreachable (); |
2f937369 DM |
4136 | break; |
4137 | #endif | |
4138 | ||
4139 | default: | |
4140 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4141 | add_insn_before (last, before, NULL); |
2f937369 | 4142 | break; |
aff507f4 RK |
4143 | } |
4144 | ||
2f937369 | 4145 | return last; |
23b2ce53 RS |
4146 | } |
4147 | ||
2f937369 | 4148 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4149 | and output it before the instruction BEFORE. */ |
4150 | ||
4151 | rtx | |
a7102479 | 4152 | emit_call_insn_before_noloc (rtx x, rtx before) |
969d70ca | 4153 | { |
d950dee3 | 4154 | rtx last = NULL_RTX, insn; |
969d70ca | 4155 | |
5b0264cb | 4156 | gcc_assert (before); |
2f937369 DM |
4157 | |
4158 | switch (GET_CODE (x)) | |
969d70ca | 4159 | { |
b5b8b0ac | 4160 | case DEBUG_INSN: |
2f937369 DM |
4161 | case INSN: |
4162 | case JUMP_INSN: | |
4163 | case CALL_INSN: | |
4164 | case CODE_LABEL: | |
4165 | case BARRIER: | |
4166 | case NOTE: | |
4167 | insn = x; | |
4168 | while (insn) | |
4169 | { | |
4170 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4171 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4172 | last = insn; |
4173 | insn = next; | |
4174 | } | |
4175 | break; | |
4176 | ||
4177 | #ifdef ENABLE_RTL_CHECKING | |
4178 | case SEQUENCE: | |
5b0264cb | 4179 | gcc_unreachable (); |
2f937369 DM |
4180 | break; |
4181 | #endif | |
4182 | ||
4183 | default: | |
4184 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4185 | add_insn_before (last, before, NULL); |
2f937369 | 4186 | break; |
969d70ca JH |
4187 | } |
4188 | ||
2f937369 | 4189 | return last; |
969d70ca JH |
4190 | } |
4191 | ||
b5b8b0ac AO |
4192 | /* Make an instruction with body X and code DEBUG_INSN |
4193 | and output it before the instruction BEFORE. */ | |
4194 | ||
4195 | rtx | |
4196 | emit_debug_insn_before_noloc (rtx x, rtx before) | |
4197 | { | |
4198 | rtx last = NULL_RTX, insn; | |
4199 | ||
4200 | gcc_assert (before); | |
4201 | ||
4202 | switch (GET_CODE (x)) | |
4203 | { | |
4204 | case DEBUG_INSN: | |
4205 | case INSN: | |
4206 | case JUMP_INSN: | |
4207 | case CALL_INSN: | |
4208 | case CODE_LABEL: | |
4209 | case BARRIER: | |
4210 | case NOTE: | |
4211 | insn = x; | |
4212 | while (insn) | |
4213 | { | |
4214 | rtx next = NEXT_INSN (insn); | |
4215 | add_insn_before (insn, before, NULL); | |
4216 | last = insn; | |
4217 | insn = next; | |
4218 | } | |
4219 | break; | |
4220 | ||
4221 | #ifdef ENABLE_RTL_CHECKING | |
4222 | case SEQUENCE: | |
4223 | gcc_unreachable (); | |
4224 | break; | |
4225 | #endif | |
4226 | ||
4227 | default: | |
4228 | last = make_debug_insn_raw (x); | |
4229 | add_insn_before (last, before, NULL); | |
4230 | break; | |
4231 | } | |
4232 | ||
4233 | return last; | |
4234 | } | |
4235 | ||
23b2ce53 | 4236 | /* Make an insn of code BARRIER |
e881bb1b | 4237 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
4238 | |
4239 | rtx | |
502b8322 | 4240 | emit_barrier_before (rtx before) |
23b2ce53 | 4241 | { |
b3694847 | 4242 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4243 | |
4244 | INSN_UID (insn) = cur_insn_uid++; | |
4245 | ||
6fb5fa3c | 4246 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4247 | return insn; |
4248 | } | |
4249 | ||
e881bb1b RH |
4250 | /* Emit the label LABEL before the insn BEFORE. */ |
4251 | ||
4252 | rtx | |
502b8322 | 4253 | emit_label_before (rtx label, rtx before) |
e881bb1b RH |
4254 | { |
4255 | /* This can be called twice for the same label as a result of the | |
4256 | confusion that follows a syntax error! So make it harmless. */ | |
4257 | if (INSN_UID (label) == 0) | |
4258 | { | |
4259 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4260 | add_insn_before (label, before, NULL); |
e881bb1b RH |
4261 | } |
4262 | ||
4263 | return label; | |
4264 | } | |
4265 | ||
23b2ce53 RS |
4266 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
4267 | ||
4268 | rtx | |
a38e7aa5 | 4269 | emit_note_before (enum insn_note subtype, rtx before) |
23b2ce53 | 4270 | { |
b3694847 | 4271 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4272 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4273 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4274 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4275 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
23b2ce53 | 4276 | |
6fb5fa3c | 4277 | add_insn_before (note, before, NULL); |
23b2ce53 RS |
4278 | return note; |
4279 | } | |
4280 | \f | |
2f937369 DM |
4281 | /* Helper for emit_insn_after, handles lists of instructions |
4282 | efficiently. */ | |
23b2ce53 | 4283 | |
2f937369 | 4284 | static rtx |
6fb5fa3c | 4285 | emit_insn_after_1 (rtx first, rtx after, basic_block bb) |
23b2ce53 | 4286 | { |
2f937369 DM |
4287 | rtx last; |
4288 | rtx after_after; | |
6fb5fa3c DB |
4289 | if (!bb && !BARRIER_P (after)) |
4290 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4291 | |
6fb5fa3c | 4292 | if (bb) |
23b2ce53 | 4293 | { |
6fb5fa3c | 4294 | df_set_bb_dirty (bb); |
2f937369 | 4295 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4296 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4297 | { |
4298 | set_block_for_insn (last, bb); | |
4299 | df_insn_rescan (last); | |
4300 | } | |
4b4bf941 | 4301 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4302 | { |
4303 | set_block_for_insn (last, bb); | |
4304 | df_insn_rescan (last); | |
4305 | } | |
a813c111 SB |
4306 | if (BB_END (bb) == after) |
4307 | BB_END (bb) = last; | |
23b2ce53 RS |
4308 | } |
4309 | else | |
2f937369 DM |
4310 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4311 | continue; | |
4312 | ||
4313 | after_after = NEXT_INSN (after); | |
4314 | ||
4315 | NEXT_INSN (after) = first; | |
4316 | PREV_INSN (first) = after; | |
4317 | NEXT_INSN (last) = after_after; | |
4318 | if (after_after) | |
4319 | PREV_INSN (after_after) = last; | |
4320 | ||
4321 | if (after == last_insn) | |
4322 | last_insn = last; | |
e855c69d | 4323 | |
2f937369 DM |
4324 | return last; |
4325 | } | |
4326 | ||
6fb5fa3c DB |
4327 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4328 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
2f937369 DM |
4329 | |
4330 | rtx | |
6fb5fa3c | 4331 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
2f937369 DM |
4332 | { |
4333 | rtx last = after; | |
4334 | ||
5b0264cb | 4335 | gcc_assert (after); |
2f937369 DM |
4336 | |
4337 | if (x == NULL_RTX) | |
4338 | return last; | |
4339 | ||
4340 | switch (GET_CODE (x)) | |
23b2ce53 | 4341 | { |
b5b8b0ac | 4342 | case DEBUG_INSN: |
2f937369 DM |
4343 | case INSN: |
4344 | case JUMP_INSN: | |
4345 | case CALL_INSN: | |
4346 | case CODE_LABEL: | |
4347 | case BARRIER: | |
4348 | case NOTE: | |
6fb5fa3c | 4349 | last = emit_insn_after_1 (x, after, bb); |
2f937369 DM |
4350 | break; |
4351 | ||
4352 | #ifdef ENABLE_RTL_CHECKING | |
4353 | case SEQUENCE: | |
5b0264cb | 4354 | gcc_unreachable (); |
2f937369 DM |
4355 | break; |
4356 | #endif | |
4357 | ||
4358 | default: | |
4359 | last = make_insn_raw (x); | |
6fb5fa3c | 4360 | add_insn_after (last, after, bb); |
2f937369 | 4361 | break; |
23b2ce53 RS |
4362 | } |
4363 | ||
2f937369 | 4364 | return last; |
23b2ce53 RS |
4365 | } |
4366 | ||
255680cf | 4367 | |
2f937369 | 4368 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4369 | and output it after the insn AFTER. */ |
4370 | ||
4371 | rtx | |
a7102479 | 4372 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4373 | { |
2f937369 | 4374 | rtx last; |
23b2ce53 | 4375 | |
5b0264cb | 4376 | gcc_assert (after); |
2f937369 DM |
4377 | |
4378 | switch (GET_CODE (x)) | |
23b2ce53 | 4379 | { |
b5b8b0ac | 4380 | case DEBUG_INSN: |
2f937369 DM |
4381 | case INSN: |
4382 | case JUMP_INSN: | |
4383 | case CALL_INSN: | |
4384 | case CODE_LABEL: | |
4385 | case BARRIER: | |
4386 | case NOTE: | |
6fb5fa3c | 4387 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4388 | break; |
4389 | ||
4390 | #ifdef ENABLE_RTL_CHECKING | |
4391 | case SEQUENCE: | |
5b0264cb | 4392 | gcc_unreachable (); |
2f937369 DM |
4393 | break; |
4394 | #endif | |
4395 | ||
4396 | default: | |
4397 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4398 | add_insn_after (last, after, NULL); |
2f937369 | 4399 | break; |
23b2ce53 RS |
4400 | } |
4401 | ||
2f937369 DM |
4402 | return last; |
4403 | } | |
4404 | ||
4405 | /* Make an instruction with body X and code CALL_INSN | |
4406 | and output it after the instruction AFTER. */ | |
4407 | ||
4408 | rtx | |
a7102479 | 4409 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 DM |
4410 | { |
4411 | rtx last; | |
4412 | ||
5b0264cb | 4413 | gcc_assert (after); |
2f937369 DM |
4414 | |
4415 | switch (GET_CODE (x)) | |
4416 | { | |
b5b8b0ac | 4417 | case DEBUG_INSN: |
2f937369 DM |
4418 | case INSN: |
4419 | case JUMP_INSN: | |
4420 | case CALL_INSN: | |
4421 | case CODE_LABEL: | |
4422 | case BARRIER: | |
4423 | case NOTE: | |
6fb5fa3c | 4424 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4425 | break; |
4426 | ||
4427 | #ifdef ENABLE_RTL_CHECKING | |
4428 | case SEQUENCE: | |
5b0264cb | 4429 | gcc_unreachable (); |
2f937369 DM |
4430 | break; |
4431 | #endif | |
4432 | ||
4433 | default: | |
4434 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4435 | add_insn_after (last, after, NULL); |
2f937369 DM |
4436 | break; |
4437 | } | |
4438 | ||
4439 | return last; | |
23b2ce53 RS |
4440 | } |
4441 | ||
b5b8b0ac AO |
4442 | /* Make an instruction with body X and code CALL_INSN |
4443 | and output it after the instruction AFTER. */ | |
4444 | ||
4445 | rtx | |
4446 | emit_debug_insn_after_noloc (rtx x, rtx after) | |
4447 | { | |
4448 | rtx last; | |
4449 | ||
4450 | gcc_assert (after); | |
4451 | ||
4452 | switch (GET_CODE (x)) | |
4453 | { | |
4454 | case DEBUG_INSN: | |
4455 | case INSN: | |
4456 | case JUMP_INSN: | |
4457 | case CALL_INSN: | |
4458 | case CODE_LABEL: | |
4459 | case BARRIER: | |
4460 | case NOTE: | |
4461 | last = emit_insn_after_1 (x, after, NULL); | |
4462 | break; | |
4463 | ||
4464 | #ifdef ENABLE_RTL_CHECKING | |
4465 | case SEQUENCE: | |
4466 | gcc_unreachable (); | |
4467 | break; | |
4468 | #endif | |
4469 | ||
4470 | default: | |
4471 | last = make_debug_insn_raw (x); | |
4472 | add_insn_after (last, after, NULL); | |
4473 | break; | |
4474 | } | |
4475 | ||
4476 | return last; | |
4477 | } | |
4478 | ||
23b2ce53 RS |
4479 | /* Make an insn of code BARRIER |
4480 | and output it after the insn AFTER. */ | |
4481 | ||
4482 | rtx | |
502b8322 | 4483 | emit_barrier_after (rtx after) |
23b2ce53 | 4484 | { |
b3694847 | 4485 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4486 | |
4487 | INSN_UID (insn) = cur_insn_uid++; | |
4488 | ||
6fb5fa3c | 4489 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4490 | return insn; |
4491 | } | |
4492 | ||
4493 | /* Emit the label LABEL after the insn AFTER. */ | |
4494 | ||
4495 | rtx | |
502b8322 | 4496 | emit_label_after (rtx label, rtx after) |
23b2ce53 RS |
4497 | { |
4498 | /* This can be called twice for the same label | |
4499 | as a result of the confusion that follows a syntax error! | |
4500 | So make it harmless. */ | |
4501 | if (INSN_UID (label) == 0) | |
4502 | { | |
4503 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4504 | add_insn_after (label, after, NULL); |
23b2ce53 RS |
4505 | } |
4506 | ||
4507 | return label; | |
4508 | } | |
4509 | ||
4510 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4511 | ||
4512 | rtx | |
a38e7aa5 | 4513 | emit_note_after (enum insn_note subtype, rtx after) |
23b2ce53 | 4514 | { |
b3694847 | 4515 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4516 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4517 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4518 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4519 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
6fb5fa3c | 4520 | add_insn_after (note, after, NULL); |
23b2ce53 RS |
4521 | return note; |
4522 | } | |
23b2ce53 | 4523 | \f |
a7102479 | 4524 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4525 | rtx |
502b8322 | 4526 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4527 | { |
6fb5fa3c | 4528 | rtx last = emit_insn_after_noloc (pattern, after, NULL); |
0d682900 | 4529 | |
a7102479 | 4530 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4531 | return last; |
4532 | ||
2f937369 DM |
4533 | after = NEXT_INSN (after); |
4534 | while (1) | |
4535 | { | |
a7102479 | 4536 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4537 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4538 | if (after == last) |
4539 | break; | |
4540 | after = NEXT_INSN (after); | |
4541 | } | |
0d682900 JH |
4542 | return last; |
4543 | } | |
4544 | ||
a7102479 JH |
4545 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4546 | rtx | |
4547 | emit_insn_after (rtx pattern, rtx after) | |
4548 | { | |
b5b8b0ac AO |
4549 | rtx prev = after; |
4550 | ||
4551 | while (DEBUG_INSN_P (prev)) | |
4552 | prev = PREV_INSN (prev); | |
4553 | ||
4554 | if (INSN_P (prev)) | |
4555 | return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (prev)); | |
a7102479 | 4556 | else |
6fb5fa3c | 4557 | return emit_insn_after_noloc (pattern, after, NULL); |
a7102479 JH |
4558 | } |
4559 | ||
4560 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4561 | rtx |
502b8322 | 4562 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4563 | { |
a7102479 | 4564 | rtx last = emit_jump_insn_after_noloc (pattern, after); |
2f937369 | 4565 | |
a7102479 | 4566 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4567 | return last; |
4568 | ||
2f937369 DM |
4569 | after = NEXT_INSN (after); |
4570 | while (1) | |
4571 | { | |
a7102479 | 4572 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4573 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4574 | if (after == last) |
4575 | break; | |
4576 | after = NEXT_INSN (after); | |
4577 | } | |
0d682900 JH |
4578 | return last; |
4579 | } | |
4580 | ||
a7102479 JH |
4581 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4582 | rtx | |
4583 | emit_jump_insn_after (rtx pattern, rtx after) | |
4584 | { | |
b5b8b0ac AO |
4585 | rtx prev = after; |
4586 | ||
4587 | while (DEBUG_INSN_P (prev)) | |
4588 | prev = PREV_INSN (prev); | |
4589 | ||
4590 | if (INSN_P (prev)) | |
4591 | return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (prev)); | |
a7102479 JH |
4592 | else |
4593 | return emit_jump_insn_after_noloc (pattern, after); | |
4594 | } | |
4595 | ||
4596 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4597 | rtx |
502b8322 | 4598 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4599 | { |
a7102479 | 4600 | rtx last = emit_call_insn_after_noloc (pattern, after); |
2f937369 | 4601 | |
a7102479 | 4602 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4603 | return last; |
4604 | ||
2f937369 DM |
4605 | after = NEXT_INSN (after); |
4606 | while (1) | |
4607 | { | |
a7102479 | 4608 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4609 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4610 | if (after == last) |
4611 | break; | |
4612 | after = NEXT_INSN (after); | |
4613 | } | |
0d682900 JH |
4614 | return last; |
4615 | } | |
4616 | ||
a7102479 JH |
4617 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4618 | rtx | |
4619 | emit_call_insn_after (rtx pattern, rtx after) | |
4620 | { | |
b5b8b0ac AO |
4621 | rtx prev = after; |
4622 | ||
4623 | while (DEBUG_INSN_P (prev)) | |
4624 | prev = PREV_INSN (prev); | |
4625 | ||
4626 | if (INSN_P (prev)) | |
4627 | return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (prev)); | |
a7102479 JH |
4628 | else |
4629 | return emit_call_insn_after_noloc (pattern, after); | |
4630 | } | |
4631 | ||
b5b8b0ac AO |
4632 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
4633 | rtx | |
4634 | emit_debug_insn_after_setloc (rtx pattern, rtx after, int loc) | |
4635 | { | |
4636 | rtx last = emit_debug_insn_after_noloc (pattern, after); | |
4637 | ||
4638 | if (pattern == NULL_RTX || !loc) | |
4639 | return last; | |
4640 | ||
4641 | after = NEXT_INSN (after); | |
4642 | while (1) | |
4643 | { | |
4644 | if (active_insn_p (after) && !INSN_LOCATOR (after)) | |
4645 | INSN_LOCATOR (after) = loc; | |
4646 | if (after == last) | |
4647 | break; | |
4648 | after = NEXT_INSN (after); | |
4649 | } | |
4650 | return last; | |
4651 | } | |
4652 | ||
4653 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ | |
4654 | rtx | |
4655 | emit_debug_insn_after (rtx pattern, rtx after) | |
4656 | { | |
4657 | if (INSN_P (after)) | |
4658 | return emit_debug_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4659 | else | |
4660 | return emit_debug_insn_after_noloc (pattern, after); | |
4661 | } | |
4662 | ||
a7102479 | 4663 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4664 | rtx |
502b8322 | 4665 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
0d682900 JH |
4666 | { |
4667 | rtx first = PREV_INSN (before); | |
6fb5fa3c | 4668 | rtx last = emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4669 | |
4670 | if (pattern == NULL_RTX || !loc) | |
4671 | return last; | |
4672 | ||
26cb3993 JH |
4673 | if (!first) |
4674 | first = get_insns (); | |
4675 | else | |
4676 | first = NEXT_INSN (first); | |
a7102479 JH |
4677 | while (1) |
4678 | { | |
4679 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4680 | INSN_LOCATOR (first) = loc; | |
4681 | if (first == last) | |
4682 | break; | |
4683 | first = NEXT_INSN (first); | |
4684 | } | |
4685 | return last; | |
4686 | } | |
4687 | ||
4688 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4689 | rtx | |
4690 | emit_insn_before (rtx pattern, rtx before) | |
4691 | { | |
b5b8b0ac AO |
4692 | rtx next = before; |
4693 | ||
4694 | while (DEBUG_INSN_P (next)) | |
4695 | next = PREV_INSN (next); | |
4696 | ||
4697 | if (INSN_P (next)) | |
4698 | return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (next)); | |
a7102479 | 4699 | else |
6fb5fa3c | 4700 | return emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4701 | } |
4702 | ||
4703 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4704 | rtx | |
4705 | emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4706 | { | |
4707 | rtx first = PREV_INSN (before); | |
4708 | rtx last = emit_jump_insn_before_noloc (pattern, before); | |
4709 | ||
4710 | if (pattern == NULL_RTX) | |
4711 | return last; | |
4712 | ||
4713 | first = NEXT_INSN (first); | |
4714 | while (1) | |
4715 | { | |
4716 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4717 | INSN_LOCATOR (first) = loc; | |
4718 | if (first == last) | |
4719 | break; | |
4720 | first = NEXT_INSN (first); | |
4721 | } | |
4722 | return last; | |
4723 | } | |
4724 | ||
4725 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4726 | rtx | |
4727 | emit_jump_insn_before (rtx pattern, rtx before) | |
4728 | { | |
b5b8b0ac AO |
4729 | rtx next = before; |
4730 | ||
4731 | while (DEBUG_INSN_P (next)) | |
4732 | next = PREV_INSN (next); | |
4733 | ||
4734 | if (INSN_P (next)) | |
4735 | return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (next)); | |
a7102479 JH |
4736 | else |
4737 | return emit_jump_insn_before_noloc (pattern, before); | |
4738 | } | |
4739 | ||
4740 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4741 | rtx | |
4742 | emit_call_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4743 | { | |
4744 | rtx first = PREV_INSN (before); | |
4745 | rtx last = emit_call_insn_before_noloc (pattern, before); | |
0d682900 | 4746 | |
dd3adcf8 DJ |
4747 | if (pattern == NULL_RTX) |
4748 | return last; | |
4749 | ||
2f937369 DM |
4750 | first = NEXT_INSN (first); |
4751 | while (1) | |
4752 | { | |
a7102479 | 4753 | if (active_insn_p (first) && !INSN_LOCATOR (first)) |
0435312e | 4754 | INSN_LOCATOR (first) = loc; |
2f937369 DM |
4755 | if (first == last) |
4756 | break; | |
4757 | first = NEXT_INSN (first); | |
4758 | } | |
0d682900 JH |
4759 | return last; |
4760 | } | |
a7102479 JH |
4761 | |
4762 | /* like emit_call_insn_before_noloc, | |
4763 | but set insn_locator according to before. */ | |
4764 | rtx | |
4765 | emit_call_insn_before (rtx pattern, rtx before) | |
4766 | { | |
b5b8b0ac AO |
4767 | rtx next = before; |
4768 | ||
4769 | while (DEBUG_INSN_P (next)) | |
4770 | next = PREV_INSN (next); | |
4771 | ||
4772 | if (INSN_P (next)) | |
4773 | return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (next)); | |
a7102479 JH |
4774 | else |
4775 | return emit_call_insn_before_noloc (pattern, before); | |
4776 | } | |
b5b8b0ac AO |
4777 | |
4778 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4779 | rtx | |
4780 | emit_debug_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4781 | { | |
4782 | rtx first = PREV_INSN (before); | |
4783 | rtx last = emit_debug_insn_before_noloc (pattern, before); | |
4784 | ||
4785 | if (pattern == NULL_RTX) | |
4786 | return last; | |
4787 | ||
4788 | first = NEXT_INSN (first); | |
4789 | while (1) | |
4790 | { | |
4791 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4792 | INSN_LOCATOR (first) = loc; | |
4793 | if (first == last) | |
4794 | break; | |
4795 | first = NEXT_INSN (first); | |
4796 | } | |
4797 | return last; | |
4798 | } | |
4799 | ||
4800 | /* like emit_debug_insn_before_noloc, | |
4801 | but set insn_locator according to before. */ | |
4802 | rtx | |
4803 | emit_debug_insn_before (rtx pattern, rtx before) | |
4804 | { | |
4805 | if (INSN_P (before)) | |
4806 | return emit_debug_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4807 | else | |
4808 | return emit_debug_insn_before_noloc (pattern, before); | |
4809 | } | |
0d682900 | 4810 | \f |
2f937369 DM |
4811 | /* Take X and emit it at the end of the doubly-linked |
4812 | INSN list. | |
23b2ce53 RS |
4813 | |
4814 | Returns the last insn emitted. */ | |
4815 | ||
4816 | rtx | |
502b8322 | 4817 | emit_insn (rtx x) |
23b2ce53 | 4818 | { |
2f937369 DM |
4819 | rtx last = last_insn; |
4820 | rtx insn; | |
23b2ce53 | 4821 | |
2f937369 DM |
4822 | if (x == NULL_RTX) |
4823 | return last; | |
23b2ce53 | 4824 | |
2f937369 DM |
4825 | switch (GET_CODE (x)) |
4826 | { | |
b5b8b0ac | 4827 | case DEBUG_INSN: |
2f937369 DM |
4828 | case INSN: |
4829 | case JUMP_INSN: | |
4830 | case CALL_INSN: | |
4831 | case CODE_LABEL: | |
4832 | case BARRIER: | |
4833 | case NOTE: | |
4834 | insn = x; | |
4835 | while (insn) | |
23b2ce53 | 4836 | { |
2f937369 | 4837 | rtx next = NEXT_INSN (insn); |
23b2ce53 | 4838 | add_insn (insn); |
2f937369 DM |
4839 | last = insn; |
4840 | insn = next; | |
23b2ce53 | 4841 | } |
2f937369 | 4842 | break; |
23b2ce53 | 4843 | |
2f937369 DM |
4844 | #ifdef ENABLE_RTL_CHECKING |
4845 | case SEQUENCE: | |
5b0264cb | 4846 | gcc_unreachable (); |
2f937369 DM |
4847 | break; |
4848 | #endif | |
23b2ce53 | 4849 | |
2f937369 DM |
4850 | default: |
4851 | last = make_insn_raw (x); | |
4852 | add_insn (last); | |
4853 | break; | |
23b2ce53 RS |
4854 | } |
4855 | ||
4856 | return last; | |
4857 | } | |
4858 | ||
b5b8b0ac AO |
4859 | /* Make an insn of code DEBUG_INSN with pattern X |
4860 | and add it to the end of the doubly-linked list. */ | |
4861 | ||
4862 | rtx | |
4863 | emit_debug_insn (rtx x) | |
4864 | { | |
4865 | rtx last = last_insn; | |
4866 | rtx insn; | |
4867 | ||
4868 | if (x == NULL_RTX) | |
4869 | return last; | |
4870 | ||
4871 | switch (GET_CODE (x)) | |
4872 | { | |
4873 | case DEBUG_INSN: | |
4874 | case INSN: | |
4875 | case JUMP_INSN: | |
4876 | case CALL_INSN: | |
4877 | case CODE_LABEL: | |
4878 | case BARRIER: | |
4879 | case NOTE: | |
4880 | insn = x; | |
4881 | while (insn) | |
4882 | { | |
4883 | rtx next = NEXT_INSN (insn); | |
4884 | add_insn (insn); | |
4885 | last = insn; | |
4886 | insn = next; | |
4887 | } | |
4888 | break; | |
4889 | ||
4890 | #ifdef ENABLE_RTL_CHECKING | |
4891 | case SEQUENCE: | |
4892 | gcc_unreachable (); | |
4893 | break; | |
4894 | #endif | |
4895 | ||
4896 | default: | |
4897 | last = make_debug_insn_raw (x); | |
4898 | add_insn (last); | |
4899 | break; | |
4900 | } | |
4901 | ||
4902 | return last; | |
4903 | } | |
4904 | ||
2f937369 DM |
4905 | /* Make an insn of code JUMP_INSN with pattern X |
4906 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4907 | |
4908 | rtx | |
502b8322 | 4909 | emit_jump_insn (rtx x) |
23b2ce53 | 4910 | { |
d950dee3 | 4911 | rtx last = NULL_RTX, insn; |
23b2ce53 | 4912 | |
2f937369 | 4913 | switch (GET_CODE (x)) |
23b2ce53 | 4914 | { |
b5b8b0ac | 4915 | case DEBUG_INSN: |
2f937369 DM |
4916 | case INSN: |
4917 | case JUMP_INSN: | |
4918 | case CALL_INSN: | |
4919 | case CODE_LABEL: | |
4920 | case BARRIER: | |
4921 | case NOTE: | |
4922 | insn = x; | |
4923 | while (insn) | |
4924 | { | |
4925 | rtx next = NEXT_INSN (insn); | |
4926 | add_insn (insn); | |
4927 | last = insn; | |
4928 | insn = next; | |
4929 | } | |
4930 | break; | |
e0a5c5eb | 4931 | |
2f937369 DM |
4932 | #ifdef ENABLE_RTL_CHECKING |
4933 | case SEQUENCE: | |
5b0264cb | 4934 | gcc_unreachable (); |
2f937369 DM |
4935 | break; |
4936 | #endif | |
e0a5c5eb | 4937 | |
2f937369 DM |
4938 | default: |
4939 | last = make_jump_insn_raw (x); | |
4940 | add_insn (last); | |
4941 | break; | |
3c030e88 | 4942 | } |
e0a5c5eb RS |
4943 | |
4944 | return last; | |
4945 | } | |
4946 | ||
2f937369 | 4947 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
4948 | and add it to the end of the doubly-linked list. */ |
4949 | ||
4950 | rtx | |
502b8322 | 4951 | emit_call_insn (rtx x) |
23b2ce53 | 4952 | { |
2f937369 DM |
4953 | rtx insn; |
4954 | ||
4955 | switch (GET_CODE (x)) | |
23b2ce53 | 4956 | { |
b5b8b0ac | 4957 | case DEBUG_INSN: |
2f937369 DM |
4958 | case INSN: |
4959 | case JUMP_INSN: | |
4960 | case CALL_INSN: | |
4961 | case CODE_LABEL: | |
4962 | case BARRIER: | |
4963 | case NOTE: | |
4964 | insn = emit_insn (x); | |
4965 | break; | |
23b2ce53 | 4966 | |
2f937369 DM |
4967 | #ifdef ENABLE_RTL_CHECKING |
4968 | case SEQUENCE: | |
5b0264cb | 4969 | gcc_unreachable (); |
2f937369 DM |
4970 | break; |
4971 | #endif | |
23b2ce53 | 4972 | |
2f937369 DM |
4973 | default: |
4974 | insn = make_call_insn_raw (x); | |
23b2ce53 | 4975 | add_insn (insn); |
2f937369 | 4976 | break; |
23b2ce53 | 4977 | } |
2f937369 DM |
4978 | |
4979 | return insn; | |
23b2ce53 RS |
4980 | } |
4981 | ||
4982 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4983 | ||
4984 | rtx | |
502b8322 | 4985 | emit_label (rtx label) |
23b2ce53 RS |
4986 | { |
4987 | /* This can be called twice for the same label | |
4988 | as a result of the confusion that follows a syntax error! | |
4989 | So make it harmless. */ | |
4990 | if (INSN_UID (label) == 0) | |
4991 | { | |
4992 | INSN_UID (label) = cur_insn_uid++; | |
4993 | add_insn (label); | |
4994 | } | |
4995 | return label; | |
4996 | } | |
4997 | ||
4998 | /* Make an insn of code BARRIER | |
4999 | and add it to the end of the doubly-linked list. */ | |
5000 | ||
5001 | rtx | |
502b8322 | 5002 | emit_barrier (void) |
23b2ce53 | 5003 | { |
b3694847 | 5004 | rtx barrier = rtx_alloc (BARRIER); |
23b2ce53 RS |
5005 | INSN_UID (barrier) = cur_insn_uid++; |
5006 | add_insn (barrier); | |
5007 | return barrier; | |
5008 | } | |
5009 | ||
5f2fc772 | 5010 | /* Emit a copy of note ORIG. */ |
502b8322 | 5011 | |
5f2fc772 NS |
5012 | rtx |
5013 | emit_note_copy (rtx orig) | |
5014 | { | |
5015 | rtx note; | |
5016 | ||
5f2fc772 NS |
5017 | note = rtx_alloc (NOTE); |
5018 | ||
5019 | INSN_UID (note) = cur_insn_uid++; | |
5020 | NOTE_DATA (note) = NOTE_DATA (orig); | |
a38e7aa5 | 5021 | NOTE_KIND (note) = NOTE_KIND (orig); |
5f2fc772 NS |
5022 | BLOCK_FOR_INSN (note) = NULL; |
5023 | add_insn (note); | |
5024 | ||
2e040219 | 5025 | return note; |
23b2ce53 RS |
5026 | } |
5027 | ||
2e040219 NS |
5028 | /* Make an insn of code NOTE or type NOTE_NO |
5029 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
5030 | |
5031 | rtx | |
a38e7aa5 | 5032 | emit_note (enum insn_note kind) |
23b2ce53 | 5033 | { |
b3694847 | 5034 | rtx note; |
23b2ce53 | 5035 | |
23b2ce53 RS |
5036 | note = rtx_alloc (NOTE); |
5037 | INSN_UID (note) = cur_insn_uid++; | |
a38e7aa5 | 5038 | NOTE_KIND (note) = kind; |
dd107e66 | 5039 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ba4f7968 | 5040 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
5041 | add_insn (note); |
5042 | return note; | |
5043 | } | |
5044 | ||
c41c1387 RS |
5045 | /* Emit a clobber of lvalue X. */ |
5046 | ||
5047 | rtx | |
5048 | emit_clobber (rtx x) | |
5049 | { | |
5050 | /* CONCATs should not appear in the insn stream. */ | |
5051 | if (GET_CODE (x) == CONCAT) | |
5052 | { | |
5053 | emit_clobber (XEXP (x, 0)); | |
5054 | return emit_clobber (XEXP (x, 1)); | |
5055 | } | |
5056 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
5057 | } | |
5058 | ||
5059 | /* Return a sequence of insns to clobber lvalue X. */ | |
5060 | ||
5061 | rtx | |
5062 | gen_clobber (rtx x) | |
5063 | { | |
5064 | rtx seq; | |
5065 | ||
5066 | start_sequence (); | |
5067 | emit_clobber (x); | |
5068 | seq = get_insns (); | |
5069 | end_sequence (); | |
5070 | return seq; | |
5071 | } | |
5072 | ||
5073 | /* Emit a use of rvalue X. */ | |
5074 | ||
5075 | rtx | |
5076 | emit_use (rtx x) | |
5077 | { | |
5078 | /* CONCATs should not appear in the insn stream. */ | |
5079 | if (GET_CODE (x) == CONCAT) | |
5080 | { | |
5081 | emit_use (XEXP (x, 0)); | |
5082 | return emit_use (XEXP (x, 1)); | |
5083 | } | |
5084 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
5085 | } | |
5086 | ||
5087 | /* Return a sequence of insns to use rvalue X. */ | |
5088 | ||
5089 | rtx | |
5090 | gen_use (rtx x) | |
5091 | { | |
5092 | rtx seq; | |
5093 | ||
5094 | start_sequence (); | |
5095 | emit_use (x); | |
5096 | seq = get_insns (); | |
5097 | end_sequence (); | |
5098 | return seq; | |
5099 | } | |
5100 | ||
23b2ce53 | 5101 | /* Cause next statement to emit a line note even if the line number |
0cea056b | 5102 | has not changed. */ |
23b2ce53 RS |
5103 | |
5104 | void | |
502b8322 | 5105 | force_next_line_note (void) |
23b2ce53 | 5106 | { |
6773e15f | 5107 | last_location = -1; |
23b2ce53 | 5108 | } |
87b47c85 AM |
5109 | |
5110 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
30f7a378 | 5111 | note of this type already exists, remove it first. */ |
87b47c85 | 5112 | |
3d238248 | 5113 | rtx |
502b8322 | 5114 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
5115 | { |
5116 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
5117 | ||
52488da1 JW |
5118 | switch (kind) |
5119 | { | |
5120 | case REG_EQUAL: | |
5121 | case REG_EQUIV: | |
5122 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
5123 | has multiple sets (some callers assume single_set | |
5124 | means the insn only has one set, when in fact it | |
5125 | means the insn only has one * useful * set). */ | |
5126 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
5127 | { | |
5b0264cb | 5128 | gcc_assert (!note); |
52488da1 JW |
5129 | return NULL_RTX; |
5130 | } | |
5131 | ||
5132 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
5133 | It serves no useful purpose and breaks eliminate_regs. */ | |
5134 | if (GET_CODE (datum) == ASM_OPERANDS) | |
5135 | return NULL_RTX; | |
6fb5fa3c DB |
5136 | |
5137 | if (note) | |
5138 | { | |
5139 | XEXP (note, 0) = datum; | |
5140 | df_notes_rescan (insn); | |
5141 | return note; | |
5142 | } | |
52488da1 JW |
5143 | break; |
5144 | ||
5145 | default: | |
6fb5fa3c DB |
5146 | if (note) |
5147 | { | |
5148 | XEXP (note, 0) = datum; | |
5149 | return note; | |
5150 | } | |
52488da1 JW |
5151 | break; |
5152 | } | |
3d238248 | 5153 | |
65c5f2a6 | 5154 | add_reg_note (insn, kind, datum); |
6fb5fa3c DB |
5155 | |
5156 | switch (kind) | |
3d238248 | 5157 | { |
6fb5fa3c DB |
5158 | case REG_EQUAL: |
5159 | case REG_EQUIV: | |
5160 | df_notes_rescan (insn); | |
5161 | break; | |
5162 | default: | |
5163 | break; | |
3d238248 | 5164 | } |
87b47c85 | 5165 | |
3d238248 | 5166 | return REG_NOTES (insn); |
87b47c85 | 5167 | } |
23b2ce53 RS |
5168 | \f |
5169 | /* Return an indication of which type of insn should have X as a body. | |
5170 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
5171 | ||
d78db459 | 5172 | static enum rtx_code |
502b8322 | 5173 | classify_insn (rtx x) |
23b2ce53 | 5174 | { |
4b4bf941 | 5175 | if (LABEL_P (x)) |
23b2ce53 RS |
5176 | return CODE_LABEL; |
5177 | if (GET_CODE (x) == CALL) | |
5178 | return CALL_INSN; | |
5179 | if (GET_CODE (x) == RETURN) | |
5180 | return JUMP_INSN; | |
5181 | if (GET_CODE (x) == SET) | |
5182 | { | |
5183 | if (SET_DEST (x) == pc_rtx) | |
5184 | return JUMP_INSN; | |
5185 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
5186 | return CALL_INSN; | |
5187 | else | |
5188 | return INSN; | |
5189 | } | |
5190 | if (GET_CODE (x) == PARALLEL) | |
5191 | { | |
b3694847 | 5192 | int j; |
23b2ce53 RS |
5193 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
5194 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
5195 | return CALL_INSN; | |
5196 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
5197 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
5198 | return JUMP_INSN; | |
5199 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
5200 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
5201 | return CALL_INSN; | |
5202 | } | |
5203 | return INSN; | |
5204 | } | |
5205 | ||
5206 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
5207 | If X is a label, it is simply added into the insn chain. */ | |
5208 | ||
5209 | rtx | |
502b8322 | 5210 | emit (rtx x) |
23b2ce53 RS |
5211 | { |
5212 | enum rtx_code code = classify_insn (x); | |
5213 | ||
5b0264cb | 5214 | switch (code) |
23b2ce53 | 5215 | { |
5b0264cb NS |
5216 | case CODE_LABEL: |
5217 | return emit_label (x); | |
5218 | case INSN: | |
5219 | return emit_insn (x); | |
5220 | case JUMP_INSN: | |
5221 | { | |
5222 | rtx insn = emit_jump_insn (x); | |
5223 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) | |
5224 | return emit_barrier (); | |
5225 | return insn; | |
5226 | } | |
5227 | case CALL_INSN: | |
5228 | return emit_call_insn (x); | |
b5b8b0ac AO |
5229 | case DEBUG_INSN: |
5230 | return emit_debug_insn (x); | |
5b0264cb NS |
5231 | default: |
5232 | gcc_unreachable (); | |
23b2ce53 | 5233 | } |
23b2ce53 RS |
5234 | } |
5235 | \f | |
e2500fed | 5236 | /* Space for free sequence stack entries. */ |
1431042e | 5237 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 5238 | |
4dfa0342 RH |
5239 | /* Begin emitting insns to a sequence. If this sequence will contain |
5240 | something that might cause the compiler to pop arguments to function | |
5241 | calls (because those pops have previously been deferred; see | |
5242 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
5243 | before calling this function. That will ensure that the deferred | |
5244 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
5245 | |
5246 | void | |
502b8322 | 5247 | start_sequence (void) |
23b2ce53 RS |
5248 | { |
5249 | struct sequence_stack *tem; | |
5250 | ||
e2500fed GK |
5251 | if (free_sequence_stack != NULL) |
5252 | { | |
5253 | tem = free_sequence_stack; | |
5254 | free_sequence_stack = tem->next; | |
5255 | } | |
5256 | else | |
1b4572a8 | 5257 | tem = GGC_NEW (struct sequence_stack); |
23b2ce53 | 5258 | |
49ad7cfa | 5259 | tem->next = seq_stack; |
23b2ce53 RS |
5260 | tem->first = first_insn; |
5261 | tem->last = last_insn; | |
5262 | ||
49ad7cfa | 5263 | seq_stack = tem; |
23b2ce53 RS |
5264 | |
5265 | first_insn = 0; | |
5266 | last_insn = 0; | |
5267 | } | |
5268 | ||
5c7a310f MM |
5269 | /* Set up the insn chain starting with FIRST as the current sequence, |
5270 | saving the previously current one. See the documentation for | |
5271 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5272 | |
5273 | void | |
502b8322 | 5274 | push_to_sequence (rtx first) |
23b2ce53 RS |
5275 | { |
5276 | rtx last; | |
5277 | ||
5278 | start_sequence (); | |
5279 | ||
5280 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
5281 | ||
5282 | first_insn = first; | |
5283 | last_insn = last; | |
5284 | } | |
5285 | ||
bb27eeda SE |
5286 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5287 | looping through the list. */ | |
5288 | ||
5289 | void | |
5290 | push_to_sequence2 (rtx first, rtx last) | |
5291 | { | |
5292 | start_sequence (); | |
5293 | ||
5294 | first_insn = first; | |
5295 | last_insn = last; | |
5296 | } | |
5297 | ||
f15ae3a1 TW |
5298 | /* Set up the outer-level insn chain |
5299 | as the current sequence, saving the previously current one. */ | |
5300 | ||
5301 | void | |
502b8322 | 5302 | push_topmost_sequence (void) |
f15ae3a1 | 5303 | { |
aefdd5ab | 5304 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
5305 | |
5306 | start_sequence (); | |
5307 | ||
49ad7cfa | 5308 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
5309 | top = stack; |
5310 | ||
5311 | first_insn = top->first; | |
5312 | last_insn = top->last; | |
5313 | } | |
5314 | ||
5315 | /* After emitting to the outer-level insn chain, update the outer-level | |
5316 | insn chain, and restore the previous saved state. */ | |
5317 | ||
5318 | void | |
502b8322 | 5319 | pop_topmost_sequence (void) |
f15ae3a1 | 5320 | { |
aefdd5ab | 5321 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 5322 | |
49ad7cfa | 5323 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
5324 | top = stack; |
5325 | ||
5326 | top->first = first_insn; | |
5327 | top->last = last_insn; | |
5328 | ||
5329 | end_sequence (); | |
5330 | } | |
5331 | ||
23b2ce53 RS |
5332 | /* After emitting to a sequence, restore previous saved state. |
5333 | ||
5c7a310f | 5334 | To get the contents of the sequence just made, you must call |
2f937369 | 5335 | `get_insns' *before* calling here. |
5c7a310f MM |
5336 | |
5337 | If the compiler might have deferred popping arguments while | |
5338 | generating this sequence, and this sequence will not be immediately | |
5339 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5340 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5341 | pops are inserted into this sequence, and not into some random |
5342 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5343 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5344 | |
5345 | void | |
502b8322 | 5346 | end_sequence (void) |
23b2ce53 | 5347 | { |
49ad7cfa | 5348 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
5349 | |
5350 | first_insn = tem->first; | |
5351 | last_insn = tem->last; | |
49ad7cfa | 5352 | seq_stack = tem->next; |
23b2ce53 | 5353 | |
e2500fed GK |
5354 | memset (tem, 0, sizeof (*tem)); |
5355 | tem->next = free_sequence_stack; | |
5356 | free_sequence_stack = tem; | |
23b2ce53 RS |
5357 | } |
5358 | ||
5359 | /* Return 1 if currently emitting into a sequence. */ | |
5360 | ||
5361 | int | |
502b8322 | 5362 | in_sequence_p (void) |
23b2ce53 | 5363 | { |
49ad7cfa | 5364 | return seq_stack != 0; |
23b2ce53 | 5365 | } |
23b2ce53 | 5366 | \f |
59ec66dc MM |
5367 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5368 | ||
2bbdec73 | 5369 | static void |
bd60bab2 | 5370 | init_virtual_regs (void) |
59ec66dc | 5371 | { |
bd60bab2 JH |
5372 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5373 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5374 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5375 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5376 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
49ad7cfa BS |
5377 | } |
5378 | ||
da43a810 BS |
5379 | \f |
5380 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5381 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5382 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5383 | static int copy_insn_n_scratches; | |
5384 | ||
5385 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5386 | copied an ASM_OPERANDS. | |
5387 | In that case, it is the original input-operand vector. */ | |
5388 | static rtvec orig_asm_operands_vector; | |
5389 | ||
5390 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5391 | copied an ASM_OPERANDS. | |
5392 | In that case, it is the copied input-operand vector. */ | |
5393 | static rtvec copy_asm_operands_vector; | |
5394 | ||
5395 | /* Likewise for the constraints vector. */ | |
5396 | static rtvec orig_asm_constraints_vector; | |
5397 | static rtvec copy_asm_constraints_vector; | |
5398 | ||
5399 | /* Recursively create a new copy of an rtx for copy_insn. | |
5400 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5401 | ASM_OPERANDs properly. | |
5402 | Normally, this function is not used directly; use copy_insn as front end. | |
5403 | However, you could first copy an insn pattern with copy_insn and then use | |
5404 | this function afterwards to properly copy any REG_NOTEs containing | |
5405 | SCRATCHes. */ | |
5406 | ||
5407 | rtx | |
502b8322 | 5408 | copy_insn_1 (rtx orig) |
da43a810 | 5409 | { |
b3694847 SS |
5410 | rtx copy; |
5411 | int i, j; | |
5412 | RTX_CODE code; | |
5413 | const char *format_ptr; | |
da43a810 | 5414 | |
cd9c1ca8 RH |
5415 | if (orig == NULL) |
5416 | return NULL; | |
5417 | ||
da43a810 BS |
5418 | code = GET_CODE (orig); |
5419 | ||
5420 | switch (code) | |
5421 | { | |
5422 | case REG: | |
da43a810 BS |
5423 | case CONST_INT: |
5424 | case CONST_DOUBLE: | |
091a3ac7 | 5425 | case CONST_FIXED: |
69ef87e2 | 5426 | case CONST_VECTOR: |
da43a810 BS |
5427 | case SYMBOL_REF: |
5428 | case CODE_LABEL: | |
5429 | case PC: | |
5430 | case CC0: | |
da43a810 | 5431 | return orig; |
3e89ed8d JH |
5432 | case CLOBBER: |
5433 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER) | |
5434 | return orig; | |
5435 | break; | |
da43a810 BS |
5436 | |
5437 | case SCRATCH: | |
5438 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5439 | if (copy_insn_scratch_in[i] == orig) | |
5440 | return copy_insn_scratch_out[i]; | |
5441 | break; | |
5442 | ||
5443 | case CONST: | |
6fb5fa3c | 5444 | if (shared_const_p (orig)) |
da43a810 BS |
5445 | return orig; |
5446 | break; | |
750c9258 | 5447 | |
da43a810 BS |
5448 | /* A MEM with a constant address is not sharable. The problem is that |
5449 | the constant address may need to be reloaded. If the mem is shared, | |
5450 | then reloading one copy of this mem will cause all copies to appear | |
5451 | to have been reloaded. */ | |
5452 | ||
5453 | default: | |
5454 | break; | |
5455 | } | |
5456 | ||
aacd3885 RS |
5457 | /* Copy the various flags, fields, and other information. We assume |
5458 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5459 | not be copied. That is the sensible default behavior, and forces |
5460 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5461 | copy = shallow_copy_rtx (orig); |
da43a810 BS |
5462 | |
5463 | /* We do not copy the USED flag, which is used as a mark bit during | |
5464 | walks over the RTL. */ | |
2adc7f12 | 5465 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5466 | |
5467 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
ec8e098d | 5468 | if (INSN_P (orig)) |
da43a810 | 5469 | { |
2adc7f12 JJ |
5470 | RTX_FLAG (copy, jump) = 0; |
5471 | RTX_FLAG (copy, call) = 0; | |
5472 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5473 | } |
750c9258 | 5474 | |
da43a810 BS |
5475 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5476 | ||
5477 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5478 | switch (*format_ptr++) |
5479 | { | |
5480 | case 'e': | |
5481 | if (XEXP (orig, i) != NULL) | |
5482 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5483 | break; | |
da43a810 | 5484 | |
aacd3885 RS |
5485 | case 'E': |
5486 | case 'V': | |
5487 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5488 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5489 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5490 | XVEC (copy, i) = copy_asm_operands_vector; | |
5491 | else if (XVEC (orig, i) != NULL) | |
5492 | { | |
5493 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5494 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5495 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5496 | } | |
5497 | break; | |
da43a810 | 5498 | |
aacd3885 RS |
5499 | case 't': |
5500 | case 'w': | |
5501 | case 'i': | |
5502 | case 's': | |
5503 | case 'S': | |
5504 | case 'u': | |
5505 | case '0': | |
5506 | /* These are left unchanged. */ | |
5507 | break; | |
da43a810 | 5508 | |
aacd3885 RS |
5509 | default: |
5510 | gcc_unreachable (); | |
5511 | } | |
da43a810 BS |
5512 | |
5513 | if (code == SCRATCH) | |
5514 | { | |
5515 | i = copy_insn_n_scratches++; | |
5b0264cb | 5516 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5517 | copy_insn_scratch_in[i] = orig; |
5518 | copy_insn_scratch_out[i] = copy; | |
5519 | } | |
5520 | else if (code == ASM_OPERANDS) | |
5521 | { | |
6462bb43 AO |
5522 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5523 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5524 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5525 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5526 | } |
5527 | ||
5528 | return copy; | |
5529 | } | |
5530 | ||
5531 | /* Create a new copy of an rtx. | |
5532 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5533 | ASM_OPERANDs properly. | |
5534 | INSN doesn't really have to be a full INSN; it could be just the | |
5535 | pattern. */ | |
5536 | rtx | |
502b8322 | 5537 | copy_insn (rtx insn) |
da43a810 BS |
5538 | { |
5539 | copy_insn_n_scratches = 0; | |
5540 | orig_asm_operands_vector = 0; | |
5541 | orig_asm_constraints_vector = 0; | |
5542 | copy_asm_operands_vector = 0; | |
5543 | copy_asm_constraints_vector = 0; | |
5544 | return copy_insn_1 (insn); | |
5545 | } | |
59ec66dc | 5546 | |
23b2ce53 RS |
5547 | /* Initialize data structures and variables in this file |
5548 | before generating rtl for each function. */ | |
5549 | ||
5550 | void | |
502b8322 | 5551 | init_emit (void) |
23b2ce53 | 5552 | { |
23b2ce53 RS |
5553 | first_insn = NULL; |
5554 | last_insn = NULL; | |
b5b8b0ac AO |
5555 | if (MIN_NONDEBUG_INSN_UID) |
5556 | cur_insn_uid = MIN_NONDEBUG_INSN_UID; | |
5557 | else | |
5558 | cur_insn_uid = 1; | |
5559 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5560 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
6773e15f | 5561 | last_location = UNKNOWN_LOCATION; |
23b2ce53 | 5562 | first_label_num = label_num; |
49ad7cfa | 5563 | seq_stack = NULL; |
23b2ce53 | 5564 | |
23b2ce53 RS |
5565 | /* Init the tables that describe all the pseudo regs. */ |
5566 | ||
3e029763 | 5567 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5568 | |
3e029763 | 5569 | crtl->emit.regno_pointer_align |
1b4572a8 | 5570 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5571 | |
750c9258 | 5572 | regno_reg_rtx |
1b4572a8 | 5573 | = GGC_NEWVEC (rtx, crtl->emit.regno_pointer_align_length); |
0d4903b8 | 5574 | |
e50126e8 | 5575 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 JL |
5576 | memcpy (regno_reg_rtx, |
5577 | static_regno_reg_rtx, | |
5578 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); | |
e50126e8 | 5579 | |
23b2ce53 | 5580 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5581 | init_virtual_regs (); |
740ab4a2 RK |
5582 | |
5583 | /* Indicate that the virtual registers and stack locations are | |
5584 | all pointers. */ | |
3502dc9c JDA |
5585 | REG_POINTER (stack_pointer_rtx) = 1; |
5586 | REG_POINTER (frame_pointer_rtx) = 1; | |
5587 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5588 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5589 | |
3502dc9c JDA |
5590 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5591 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5592 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5593 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5594 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5595 | |
86fe05e0 | 5596 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5597 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5598 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5599 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5600 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5601 | ||
5602 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5603 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5604 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5605 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5606 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5607 | #endif |
5608 | ||
5e82e7bd JVA |
5609 | #ifdef INIT_EXPANDERS |
5610 | INIT_EXPANDERS; | |
5611 | #endif | |
23b2ce53 RS |
5612 | } |
5613 | ||
a73b091d | 5614 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
69ef87e2 AH |
5615 | |
5616 | static rtx | |
a73b091d | 5617 | gen_const_vector (enum machine_mode mode, int constant) |
69ef87e2 AH |
5618 | { |
5619 | rtx tem; | |
5620 | rtvec v; | |
5621 | int units, i; | |
5622 | enum machine_mode inner; | |
5623 | ||
5624 | units = GET_MODE_NUNITS (mode); | |
5625 | inner = GET_MODE_INNER (mode); | |
5626 | ||
15ed7b52 JG |
5627 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5628 | ||
69ef87e2 AH |
5629 | v = rtvec_alloc (units); |
5630 | ||
a73b091d JW |
5631 | /* We need to call this function after we set the scalar const_tiny_rtx |
5632 | entries. */ | |
5633 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
69ef87e2 AH |
5634 | |
5635 | for (i = 0; i < units; ++i) | |
a73b091d | 5636 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
69ef87e2 | 5637 | |
a06e3c40 | 5638 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5639 | return tem; |
5640 | } | |
5641 | ||
a06e3c40 | 5642 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5643 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5644 | rtx |
502b8322 | 5645 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
a06e3c40 | 5646 | { |
a73b091d JW |
5647 | enum machine_mode inner = GET_MODE_INNER (mode); |
5648 | int nunits = GET_MODE_NUNITS (mode); | |
5649 | rtx x; | |
a06e3c40 R |
5650 | int i; |
5651 | ||
a73b091d JW |
5652 | /* Check to see if all of the elements have the same value. */ |
5653 | x = RTVEC_ELT (v, nunits - 1); | |
5654 | for (i = nunits - 2; i >= 0; i--) | |
5655 | if (RTVEC_ELT (v, i) != x) | |
5656 | break; | |
5657 | ||
5658 | /* If the values are all the same, check to see if we can use one of the | |
5659 | standard constant vectors. */ | |
5660 | if (i == -1) | |
5661 | { | |
5662 | if (x == CONST0_RTX (inner)) | |
5663 | return CONST0_RTX (mode); | |
5664 | else if (x == CONST1_RTX (inner)) | |
5665 | return CONST1_RTX (mode); | |
5666 | } | |
5667 | ||
5668 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5669 | } |
5670 | ||
b5deb7b6 SL |
5671 | /* Initialise global register information required by all functions. */ |
5672 | ||
5673 | void | |
5674 | init_emit_regs (void) | |
5675 | { | |
5676 | int i; | |
5677 | ||
5678 | /* Reset register attributes */ | |
5679 | htab_empty (reg_attrs_htab); | |
5680 | ||
5681 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5682 | init_reg_modes_target (); | |
5683 | ||
5684 | /* Assign register numbers to the globally defined register rtx. */ | |
5685 | pc_rtx = gen_rtx_PC (VOIDmode); | |
5686 | cc0_rtx = gen_rtx_CC0 (VOIDmode); | |
5687 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
5688 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5689 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5690 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5691 | virtual_incoming_args_rtx = | |
5692 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5693 | virtual_stack_vars_rtx = | |
5694 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5695 | virtual_stack_dynamic_rtx = | |
5696 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5697 | virtual_outgoing_args_rtx = | |
5698 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5699 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
5700 | ||
5701 | /* Initialize RTL for commonly used hard registers. These are | |
5702 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5703 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5704 | static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); | |
5705 | ||
5706 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5707 | return_address_pointer_rtx | |
5708 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5709 | #endif | |
5710 | ||
b5deb7b6 SL |
5711 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
5712 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
5713 | else | |
5714 | pic_offset_table_rtx = NULL_RTX; | |
5715 | } | |
5716 | ||
23b2ce53 RS |
5717 | /* Create some permanent unique rtl objects shared between all functions. |
5718 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
5719 | ||
5720 | void | |
502b8322 | 5721 | init_emit_once (int line_numbers) |
23b2ce53 RS |
5722 | { |
5723 | int i; | |
5724 | enum machine_mode mode; | |
9ec36da5 | 5725 | enum machine_mode double_mode; |
23b2ce53 | 5726 | |
091a3ac7 CF |
5727 | /* Initialize the CONST_INT, CONST_DOUBLE, CONST_FIXED, and memory attribute |
5728 | hash tables. */ | |
17211ab5 GK |
5729 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5730 | const_int_htab_eq, NULL); | |
173b24b9 | 5731 | |
17211ab5 GK |
5732 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5733 | const_double_htab_eq, NULL); | |
5692c7bc | 5734 | |
091a3ac7 CF |
5735 | const_fixed_htab = htab_create_ggc (37, const_fixed_htab_hash, |
5736 | const_fixed_htab_eq, NULL); | |
5737 | ||
17211ab5 GK |
5738 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5739 | mem_attrs_htab_eq, NULL); | |
a560d4d4 JH |
5740 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5741 | reg_attrs_htab_eq, NULL); | |
67673f5c | 5742 | |
23b2ce53 RS |
5743 | no_line_numbers = ! line_numbers; |
5744 | ||
43fa6302 AS |
5745 | /* Compute the word and byte modes. */ |
5746 | ||
5747 | byte_mode = VOIDmode; | |
5748 | word_mode = VOIDmode; | |
5749 | double_mode = VOIDmode; | |
5750 | ||
15ed7b52 JG |
5751 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5752 | mode != VOIDmode; | |
43fa6302 AS |
5753 | mode = GET_MODE_WIDER_MODE (mode)) |
5754 | { | |
5755 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5756 | && byte_mode == VOIDmode) | |
5757 | byte_mode = mode; | |
5758 | ||
5759 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5760 | && word_mode == VOIDmode) | |
5761 | word_mode = mode; | |
5762 | } | |
5763 | ||
15ed7b52 JG |
5764 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5765 | mode != VOIDmode; | |
43fa6302 AS |
5766 | mode = GET_MODE_WIDER_MODE (mode)) |
5767 | { | |
5768 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5769 | && double_mode == VOIDmode) | |
5770 | double_mode = mode; | |
5771 | } | |
5772 | ||
5773 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5774 | ||
5da077de | 5775 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5776 | /* This is to initialize {init|mark|free}_machine_status before the first |
5777 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5778 | end which calls push_function_context_to before the first call to |
5da077de AS |
5779 | init_function_start. */ |
5780 | INIT_EXPANDERS; | |
5781 | #endif | |
5782 | ||
23b2ce53 RS |
5783 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5784 | ||
a2a8cc44 | 5785 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 5786 | tries to use these variables. */ |
23b2ce53 | 5787 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5788 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5789 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5790 | |
68d75312 JC |
5791 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5792 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5793 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5794 | else |
3b80f6ca | 5795 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5796 | |
5692c7bc ZW |
5797 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5798 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5799 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
aefa9d43 KG |
5800 | |
5801 | dconstm1 = dconst1; | |
5802 | dconstm1.sign = 1; | |
03f2ea93 RS |
5803 | |
5804 | dconsthalf = dconst1; | |
1e92bbb9 | 5805 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 5806 | |
f7657db9 | 5807 | for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++) |
23b2ce53 | 5808 | { |
aefa9d43 | 5809 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
5810 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
5811 | ||
15ed7b52 JG |
5812 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5813 | mode != VOIDmode; | |
5814 | mode = GET_MODE_WIDER_MODE (mode)) | |
5815 | const_tiny_rtx[i][(int) mode] = | |
5816 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5817 | ||
5818 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5819 | mode != VOIDmode; | |
23b2ce53 | 5820 | mode = GET_MODE_WIDER_MODE (mode)) |
5692c7bc ZW |
5821 | const_tiny_rtx[i][(int) mode] = |
5822 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5823 | |
906c4e36 | 5824 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 5825 | |
15ed7b52 JG |
5826 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5827 | mode != VOIDmode; | |
23b2ce53 | 5828 | mode = GET_MODE_WIDER_MODE (mode)) |
906c4e36 | 5829 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
5830 | |
5831 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5832 | mode != VOIDmode; | |
5833 | mode = GET_MODE_WIDER_MODE (mode)) | |
5834 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
5835 | } |
5836 | ||
e90721b1 AP |
5837 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5838 | mode != VOIDmode; | |
5839 | mode = GET_MODE_WIDER_MODE (mode)) | |
5840 | { | |
5841 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5842 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5843 | } | |
5844 | ||
5845 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5846 | mode != VOIDmode; | |
5847 | mode = GET_MODE_WIDER_MODE (mode)) | |
5848 | { | |
5849 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5850 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5851 | } | |
5852 | ||
69ef87e2 AH |
5853 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5854 | mode != VOIDmode; | |
5855 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5856 | { |
5857 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5858 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5859 | } | |
69ef87e2 AH |
5860 | |
5861 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5862 | mode != VOIDmode; | |
5863 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5864 | { |
5865 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5866 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5867 | } | |
69ef87e2 | 5868 | |
325217ed CF |
5869 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
5870 | mode != VOIDmode; | |
5871 | mode = GET_MODE_WIDER_MODE (mode)) | |
5872 | { | |
5873 | FCONST0(mode).data.high = 0; | |
5874 | FCONST0(mode).data.low = 0; | |
5875 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5876 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5877 | FCONST0 (mode), mode); | |
325217ed CF |
5878 | } |
5879 | ||
5880 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
5881 | mode != VOIDmode; | |
5882 | mode = GET_MODE_WIDER_MODE (mode)) | |
5883 | { | |
5884 | FCONST0(mode).data.high = 0; | |
5885 | FCONST0(mode).data.low = 0; | |
5886 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5887 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5888 | FCONST0 (mode), mode); | |
325217ed CF |
5889 | } |
5890 | ||
5891 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
5892 | mode != VOIDmode; | |
5893 | mode = GET_MODE_WIDER_MODE (mode)) | |
5894 | { | |
5895 | FCONST0(mode).data.high = 0; | |
5896 | FCONST0(mode).data.low = 0; | |
5897 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5898 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5899 | FCONST0 (mode), mode); | |
325217ed CF |
5900 | |
5901 | /* We store the value 1. */ | |
5902 | FCONST1(mode).data.high = 0; | |
5903 | FCONST1(mode).data.low = 0; | |
5904 | FCONST1(mode).mode = mode; | |
5905 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5906 | 2 * HOST_BITS_PER_WIDE_INT, | |
5907 | &FCONST1(mode).data.low, | |
5908 | &FCONST1(mode).data.high, | |
5909 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5910 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5911 | FCONST1 (mode), mode); | |
325217ed CF |
5912 | } |
5913 | ||
5914 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
5915 | mode != VOIDmode; | |
5916 | mode = GET_MODE_WIDER_MODE (mode)) | |
5917 | { | |
5918 | FCONST0(mode).data.high = 0; | |
5919 | FCONST0(mode).data.low = 0; | |
5920 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5921 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5922 | FCONST0 (mode), mode); | |
325217ed CF |
5923 | |
5924 | /* We store the value 1. */ | |
5925 | FCONST1(mode).data.high = 0; | |
5926 | FCONST1(mode).data.low = 0; | |
5927 | FCONST1(mode).mode = mode; | |
5928 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5929 | 2 * HOST_BITS_PER_WIDE_INT, | |
5930 | &FCONST1(mode).data.low, | |
5931 | &FCONST1(mode).data.high, | |
5932 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5933 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5934 | FCONST1 (mode), mode); | |
5935 | } | |
5936 | ||
5937 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT); | |
5938 | mode != VOIDmode; | |
5939 | mode = GET_MODE_WIDER_MODE (mode)) | |
5940 | { | |
5941 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5942 | } | |
5943 | ||
5944 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT); | |
5945 | mode != VOIDmode; | |
5946 | mode = GET_MODE_WIDER_MODE (mode)) | |
5947 | { | |
5948 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5949 | } | |
5950 | ||
5951 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM); | |
5952 | mode != VOIDmode; | |
5953 | mode = GET_MODE_WIDER_MODE (mode)) | |
5954 | { | |
5955 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5956 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5957 | } | |
5958 | ||
5959 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM); | |
5960 | mode != VOIDmode; | |
5961 | mode = GET_MODE_WIDER_MODE (mode)) | |
5962 | { | |
5963 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5964 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
5965 | } |
5966 | ||
dbbbbf3b JDA |
5967 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5968 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5969 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 5970 | |
f0417c82 RH |
5971 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5972 | if (STORE_FLAG_VALUE == 1) | |
5973 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
23b2ce53 | 5974 | } |
a11759a3 | 5975 | \f |
969d70ca JH |
5976 | /* Produce exact duplicate of insn INSN after AFTER. |
5977 | Care updating of libcall regions if present. */ | |
5978 | ||
5979 | rtx | |
502b8322 | 5980 | emit_copy_of_insn_after (rtx insn, rtx after) |
969d70ca | 5981 | { |
60564289 | 5982 | rtx new_rtx, link; |
969d70ca JH |
5983 | |
5984 | switch (GET_CODE (insn)) | |
5985 | { | |
5986 | case INSN: | |
60564289 | 5987 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5988 | break; |
5989 | ||
5990 | case JUMP_INSN: | |
60564289 | 5991 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5992 | break; |
5993 | ||
b5b8b0ac AO |
5994 | case DEBUG_INSN: |
5995 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
5996 | break; | |
5997 | ||
969d70ca | 5998 | case CALL_INSN: |
60564289 | 5999 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 6000 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 6001 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 6002 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
6003 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
6004 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
6005 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
6006 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) | |
becfd6e5 | 6007 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
6008 | break; |
6009 | ||
6010 | default: | |
5b0264cb | 6011 | gcc_unreachable (); |
969d70ca JH |
6012 | } |
6013 | ||
6014 | /* Update LABEL_NUSES. */ | |
60564289 | 6015 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 6016 | |
60564289 | 6017 | INSN_LOCATOR (new_rtx) = INSN_LOCATOR (insn); |
ba4f7968 | 6018 | |
0a3d71f5 JW |
6019 | /* If the old insn is frame related, then so is the new one. This is |
6020 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
6021 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 6022 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 6023 | |
cf7c4aa6 HPN |
6024 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
6025 | will make them. REG_LABEL_TARGETs are created there too, but are | |
6026 | supposed to be sticky, so we copy them. */ | |
969d70ca | 6027 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 6028 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca JH |
6029 | { |
6030 | if (GET_CODE (link) == EXPR_LIST) | |
60564289 | 6031 | add_reg_note (new_rtx, REG_NOTE_KIND (link), |
65c5f2a6 | 6032 | copy_insn_1 (XEXP (link, 0))); |
969d70ca | 6033 | else |
60564289 | 6034 | add_reg_note (new_rtx, REG_NOTE_KIND (link), XEXP (link, 0)); |
969d70ca JH |
6035 | } |
6036 | ||
60564289 KG |
6037 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
6038 | return new_rtx; | |
969d70ca | 6039 | } |
e2500fed | 6040 | |
1431042e | 6041 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d JH |
6042 | rtx |
6043 | gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno) | |
6044 | { | |
6045 | if (hard_reg_clobbers[mode][regno]) | |
6046 | return hard_reg_clobbers[mode][regno]; | |
6047 | else | |
6048 | return (hard_reg_clobbers[mode][regno] = | |
6049 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
6050 | } | |
6051 | ||
e2500fed | 6052 | #include "gt-emit-rtl.h" |