]>
Commit | Line | Data |
---|---|---|
23b2ce53 | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ef58a523 JL |
2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
23b2ce53 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
670ee920 | 39 | #include "system.h" |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
ca695ac9 | 53 | #include "obstack.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
ca695ac9 | 57 | |
1d445e9e ILT |
58 | /* Commonly used modes. */ |
59 | ||
0f41302f MS |
60 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
61 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 62 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 63 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 64 | |
23b2ce53 RS |
65 | |
66 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
67 | in the entire compilation a unique label number. */ | |
68 | ||
69 | static int label_num = 1; | |
70 | ||
23b2ce53 RS |
71 | /* Highest label number in current function. |
72 | Zero means use the value of label_num instead. | |
73 | This is nonzero only when belatedly compiling an inline function. */ | |
74 | ||
75 | static int last_label_num; | |
76 | ||
77 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
78 | If label_num has not changed since then, last_label_num is valid. */ | |
79 | ||
80 | static int base_label_num; | |
81 | ||
82 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
83 | ||
84 | static int no_line_numbers; | |
85 | ||
86 | /* Commonly used rtx's, so that we only need space for one copy. | |
87 | These are initialized once for the entire compilation. | |
88 | All of these except perhaps the floating-point CONST_DOUBLEs | |
89 | are unique; no other rtx-object will be equal to any of these. */ | |
90 | ||
5da077de | 91 | rtx global_rtl[GR_MAX]; |
23b2ce53 RS |
92 | |
93 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
94 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
95 | record a copy of const[012]_rtx. */ | |
96 | ||
97 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
98 | ||
68d75312 JC |
99 | rtx const_true_rtx; |
100 | ||
23b2ce53 RS |
101 | REAL_VALUE_TYPE dconst0; |
102 | REAL_VALUE_TYPE dconst1; | |
103 | REAL_VALUE_TYPE dconst2; | |
104 | REAL_VALUE_TYPE dconstm1; | |
105 | ||
106 | /* All references to the following fixed hard registers go through | |
107 | these unique rtl objects. On machines where the frame-pointer and | |
108 | arg-pointer are the same register, they use the same unique object. | |
109 | ||
110 | After register allocation, other rtl objects which used to be pseudo-regs | |
111 | may be clobbered to refer to the frame-pointer register. | |
112 | But references that were originally to the frame-pointer can be | |
113 | distinguished from the others because they contain frame_pointer_rtx. | |
114 | ||
ac6f08b0 DE |
115 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
116 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
117 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
118 | register elimination hard_frame_pointer_rtx should always be used. | |
119 | On machines where the two registers are same (most) then these are the | |
120 | same. | |
121 | ||
23b2ce53 RS |
122 | In an inline procedure, the stack and frame pointer rtxs may not be |
123 | used for anything else. */ | |
23b2ce53 RS |
124 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
125 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
126 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
127 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
128 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
129 | ||
a4417a86 JW |
130 | /* This is used to implement __builtin_return_address for some machines. |
131 | See for instance the MIPS port. */ | |
132 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
133 | ||
23b2ce53 RS |
134 | /* We make one copy of (const_int C) where C is in |
135 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
136 | to save space during the compilation and simplify comparisons of | |
137 | integers. */ | |
138 | ||
5da077de | 139 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 140 | |
c13e8210 MM |
141 | /* A hash table storing CONST_INTs whose absolute value is greater |
142 | than MAX_SAVED_CONST_INT. */ | |
143 | ||
144 | static htab_t const_int_htab; | |
145 | ||
23b2ce53 RS |
146 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
147 | shortly thrown away. We use two mechanisms to prevent this waste: | |
148 | ||
a3770a81 RH |
149 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
150 | rtvec for use by gen_sequence. One entry for each size is | |
151 | sufficient because most cases are calls to gen_sequence followed by | |
152 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
153 | sequence is destructive on the insn in it anyway and hence can't be | |
154 | redone. | |
23b2ce53 RS |
155 | |
156 | We do not bother to save this cached data over nested function calls. | |
157 | Instead, we just reinitialize them. */ | |
158 | ||
159 | #define SEQUENCE_RESULT_SIZE 5 | |
160 | ||
23b2ce53 RS |
161 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
162 | ||
0f41302f | 163 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
43127294 RK |
164 | static rtx free_insn; |
165 | ||
01d939e8 BS |
166 | #define first_insn (cfun->emit->x_first_insn) |
167 | #define last_insn (cfun->emit->x_last_insn) | |
168 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
169 | #define last_linenum (cfun->emit->x_last_linenum) | |
170 | #define last_filename (cfun->emit->x_last_filename) | |
171 | #define first_label_num (cfun->emit->x_first_label_num) | |
23b2ce53 | 172 | |
da43a810 BS |
173 | /* This is where the pointer to the obstack being used for RTL is stored. */ |
174 | extern struct obstack *rtl_obstack; | |
175 | ||
711d877c KG |
176 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
177 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
178 | static rtx find_line_note PARAMS ((rtx)); | |
179 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
d1b81779 | 180 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
5c6df058 | 181 | static void unshare_all_decls PARAMS ((tree)); |
c13e8210 MM |
182 | static hashval_t const_int_htab_hash PARAMS ((const void *)); |
183 | static int const_int_htab_eq PARAMS ((const void *, | |
184 | const void *)); | |
185 | static int rtx_htab_mark_1 PARAMS ((void **, void *)); | |
186 | static void rtx_htab_mark PARAMS ((void *)); | |
187 | ||
ca695ac9 | 188 | \f |
c13e8210 MM |
189 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
190 | ||
191 | static hashval_t | |
192 | const_int_htab_hash (x) | |
193 | const void *x; | |
194 | { | |
e77d72cb | 195 | return (hashval_t) INTVAL ((const struct rtx_def *) x); |
c13e8210 MM |
196 | } |
197 | ||
198 | /* Returns non-zero if the value represented by X (which is really a | |
199 | CONST_INT) is the same as that given by Y (which is really a | |
200 | HOST_WIDE_INT *). */ | |
201 | ||
202 | static int | |
203 | const_int_htab_eq (x, y) | |
204 | const void *x; | |
205 | const void *y; | |
206 | { | |
e77d72cb | 207 | return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y)); |
c13e8210 MM |
208 | } |
209 | ||
210 | /* Mark the hash-table element X (which is really a pointer to an | |
211 | rtx). */ | |
212 | ||
213 | static int | |
214 | rtx_htab_mark_1 (x, data) | |
215 | void **x; | |
216 | void *data ATTRIBUTE_UNUSED; | |
217 | { | |
218 | ggc_mark_rtx (*x); | |
219 | return 1; | |
220 | } | |
221 | ||
222 | /* Mark all the elements of HTAB (which is really an htab_t full of | |
223 | rtxs). */ | |
224 | ||
225 | static void | |
226 | rtx_htab_mark (htab) | |
227 | void *htab; | |
228 | { | |
229 | htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL); | |
230 | } | |
231 | ||
c5c76735 JL |
232 | /* There are some RTL codes that require special attention; the generation |
233 | functions do the raw handling. If you add to this list, modify | |
234 | special_rtx in gengenrtl.c as well. */ | |
235 | ||
3b80f6ca RH |
236 | rtx |
237 | gen_rtx_CONST_INT (mode, arg) | |
c13e8210 | 238 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3b80f6ca RH |
239 | HOST_WIDE_INT arg; |
240 | { | |
c13e8210 MM |
241 | void **slot; |
242 | ||
3b80f6ca | 243 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 244 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
245 | |
246 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
247 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
248 | return const_true_rtx; | |
249 | #endif | |
250 | ||
c13e8210 | 251 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
252 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
253 | (hashval_t) arg, INSERT); | |
29105cea | 254 | if (*slot == 0) |
8dd2076d MM |
255 | { |
256 | if (!ggc_p) | |
257 | { | |
258 | push_obstacks_nochange (); | |
259 | end_temporary_allocation (); | |
29105cea RK |
260 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
261 | pop_obstacks (); | |
8dd2076d | 262 | } |
29105cea RK |
263 | else |
264 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); | |
8dd2076d | 265 | } |
c13e8210 MM |
266 | |
267 | return (rtx) *slot; | |
3b80f6ca RH |
268 | } |
269 | ||
29105cea | 270 | /* CONST_DOUBLEs needs special handling because their length is known |
0133b7d9 | 271 | only at run-time. */ |
29105cea | 272 | |
0133b7d9 RH |
273 | rtx |
274 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
275 | enum machine_mode mode; | |
276 | rtx arg0; | |
277 | HOST_WIDE_INT arg1, arg2; | |
278 | { | |
279 | rtx r = rtx_alloc (CONST_DOUBLE); | |
2454beaf RH |
280 | int i; |
281 | ||
0133b7d9 RH |
282 | PUT_MODE (r, mode); |
283 | XEXP (r, 0) = arg0; | |
ef178af3 | 284 | X0EXP (r, 1) = NULL_RTX; |
2454beaf RH |
285 | XWINT (r, 2) = arg1; |
286 | XWINT (r, 3) = arg2; | |
287 | ||
288 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
289 | XWINT (r, i) = 0; | |
290 | ||
0133b7d9 RH |
291 | return r; |
292 | } | |
293 | ||
3b80f6ca RH |
294 | rtx |
295 | gen_rtx_REG (mode, regno) | |
296 | enum machine_mode mode; | |
297 | int regno; | |
298 | { | |
299 | /* In case the MD file explicitly references the frame pointer, have | |
300 | all such references point to the same frame pointer. This is | |
301 | used during frame pointer elimination to distinguish the explicit | |
302 | references to these registers from pseudos that happened to be | |
303 | assigned to them. | |
304 | ||
305 | If we have eliminated the frame pointer or arg pointer, we will | |
306 | be using it as a normal register, for example as a spill | |
307 | register. In such cases, we might be accessing it in a mode that | |
308 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
309 | ||
310 | Also don't do this when we are making new REGs in reload, since | |
311 | we don't want to get confused with the real pointers. */ | |
312 | ||
313 | if (mode == Pmode && !reload_in_progress) | |
314 | { | |
bcb33994 | 315 | if (regno == FRAME_POINTER_REGNUM) |
3b80f6ca RH |
316 | return frame_pointer_rtx; |
317 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
bcb33994 | 318 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3b80f6ca RH |
319 | return hard_frame_pointer_rtx; |
320 | #endif | |
321 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 322 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
323 | return arg_pointer_rtx; |
324 | #endif | |
325 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 326 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
327 | return return_address_pointer_rtx; |
328 | #endif | |
bcb33994 | 329 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
330 | return stack_pointer_rtx; |
331 | } | |
332 | ||
333 | return gen_rtx_raw_REG (mode, regno); | |
334 | } | |
335 | ||
41472af8 MM |
336 | rtx |
337 | gen_rtx_MEM (mode, addr) | |
338 | enum machine_mode mode; | |
339 | rtx addr; | |
340 | { | |
341 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
342 | ||
343 | /* This field is not cleared by the mere allocation of the rtx, so | |
344 | we clear it here. */ | |
345 | MEM_ALIAS_SET (rt) = 0; | |
346 | ||
347 | return rt; | |
348 | } | |
c5c76735 | 349 | \f |
23b2ce53 RS |
350 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
351 | ** | |
352 | ** This routine generates an RTX of the size specified by | |
353 | ** <code>, which is an RTX code. The RTX structure is initialized | |
354 | ** from the arguments <element1> through <elementn>, which are | |
355 | ** interpreted according to the specific RTX type's format. The | |
356 | ** special machine mode associated with the rtx (if any) is specified | |
357 | ** in <mode>. | |
358 | ** | |
1632afca | 359 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
360 | ** rtx it will generate. For example, the following rtx structure: |
361 | ** | |
362 | ** (plus:QI (mem:QI (reg:SI 1)) | |
363 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
364 | ** | |
365 | ** ...would be generated by the following C code: | |
366 | ** | |
367 | ** gen_rtx (PLUS, QImode, | |
368 | ** gen_rtx (MEM, QImode, | |
369 | ** gen_rtx (REG, SImode, 1)), | |
370 | ** gen_rtx (MEM, QImode, | |
371 | ** gen_rtx (PLUS, SImode, | |
372 | ** gen_rtx (REG, SImode, 2), | |
373 | ** gen_rtx (REG, SImode, 3)))), | |
374 | */ | |
375 | ||
376 | /*VARARGS2*/ | |
377 | rtx | |
711d877c | 378 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
23b2ce53 | 379 | { |
5148a72b | 380 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
381 | enum rtx_code code; |
382 | enum machine_mode mode; | |
4f90e4a0 RK |
383 | #endif |
384 | va_list p; | |
23b2ce53 | 385 | register int i; /* Array indices... */ |
6f7d635c | 386 | register const char *fmt; /* Current rtx's format... */ |
23b2ce53 RS |
387 | register rtx rt_val; /* RTX to return to caller... */ |
388 | ||
4f90e4a0 RK |
389 | VA_START (p, mode); |
390 | ||
5148a72b | 391 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
392 | code = va_arg (p, enum rtx_code); |
393 | mode = va_arg (p, enum machine_mode); | |
4f90e4a0 | 394 | #endif |
23b2ce53 | 395 | |
0133b7d9 | 396 | switch (code) |
23b2ce53 | 397 | { |
0133b7d9 RH |
398 | case CONST_INT: |
399 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
400 | break; | |
401 | ||
402 | case CONST_DOUBLE: | |
403 | { | |
404 | rtx arg0 = va_arg (p, rtx); | |
405 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
406 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
407 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
408 | } | |
409 | break; | |
410 | ||
411 | case REG: | |
412 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
413 | break; | |
414 | ||
415 | case MEM: | |
416 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
417 | break; | |
418 | ||
419 | default: | |
23b2ce53 RS |
420 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
421 | rt_val->mode = mode; /* Store the machine mode... */ | |
422 | ||
423 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
424 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
425 | { | |
426 | switch (*fmt++) | |
427 | { | |
428 | case '0': /* Unused field. */ | |
429 | break; | |
430 | ||
431 | case 'i': /* An integer? */ | |
432 | XINT (rt_val, i) = va_arg (p, int); | |
433 | break; | |
434 | ||
906c4e36 RK |
435 | case 'w': /* A wide integer? */ |
436 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
437 | break; | |
438 | ||
23b2ce53 RS |
439 | case 's': /* A string? */ |
440 | XSTR (rt_val, i) = va_arg (p, char *); | |
441 | break; | |
442 | ||
443 | case 'e': /* An expression? */ | |
444 | case 'u': /* An insn? Same except when printing. */ | |
445 | XEXP (rt_val, i) = va_arg (p, rtx); | |
446 | break; | |
447 | ||
448 | case 'E': /* An RTX vector? */ | |
449 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
450 | break; | |
451 | ||
0dfa1860 MM |
452 | case 'b': /* A bitmap? */ |
453 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
454 | break; | |
455 | ||
456 | case 't': /* A tree? */ | |
457 | XTREE (rt_val, i) = va_arg (p, tree); | |
458 | break; | |
459 | ||
23b2ce53 | 460 | default: |
1632afca | 461 | abort (); |
23b2ce53 RS |
462 | } |
463 | } | |
0133b7d9 | 464 | break; |
23b2ce53 | 465 | } |
0133b7d9 | 466 | |
23b2ce53 | 467 | va_end (p); |
0133b7d9 | 468 | return rt_val; |
23b2ce53 RS |
469 | } |
470 | ||
471 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
472 | ** | |
473 | ** This routine creates an rtvec and stores within it the | |
474 | ** pointers to rtx's which are its arguments. | |
475 | */ | |
476 | ||
477 | /*VARARGS1*/ | |
478 | rtvec | |
711d877c | 479 | gen_rtvec VPARAMS ((int n, ...)) |
23b2ce53 | 480 | { |
5148a72b | 481 | #ifndef ANSI_PROTOTYPES |
4f90e4a0 RK |
482 | int n; |
483 | #endif | |
484 | int i; | |
23b2ce53 RS |
485 | va_list p; |
486 | rtx *vector; | |
487 | ||
4f90e4a0 RK |
488 | VA_START (p, n); |
489 | ||
5148a72b | 490 | #ifndef ANSI_PROTOTYPES |
23b2ce53 | 491 | n = va_arg (p, int); |
4f90e4a0 | 492 | #endif |
23b2ce53 RS |
493 | |
494 | if (n == 0) | |
495 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
496 | ||
497 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 498 | |
23b2ce53 RS |
499 | for (i = 0; i < n; i++) |
500 | vector[i] = va_arg (p, rtx); | |
501 | va_end (p); | |
502 | ||
503 | return gen_rtvec_v (n, vector); | |
504 | } | |
505 | ||
506 | rtvec | |
507 | gen_rtvec_v (n, argp) | |
508 | int n; | |
509 | rtx *argp; | |
510 | { | |
511 | register int i; | |
512 | register rtvec rt_val; | |
513 | ||
514 | if (n == 0) | |
515 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
516 | ||
517 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
518 | ||
519 | for (i = 0; i < n; i++) | |
8f985ec4 | 520 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
521 | |
522 | return rt_val; | |
523 | } | |
ba444f92 | 524 | |
23b2ce53 RS |
525 | \f |
526 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
527 | This pseudo is assigned the next sequential register number. */ | |
528 | ||
529 | rtx | |
530 | gen_reg_rtx (mode) | |
531 | enum machine_mode mode; | |
532 | { | |
01d939e8 | 533 | struct function *f = cfun; |
23b2ce53 RS |
534 | register rtx val; |
535 | ||
f1db3576 JL |
536 | /* Don't let anything called after initial flow analysis create new |
537 | registers. */ | |
538 | if (no_new_pseudos) | |
23b2ce53 RS |
539 | abort (); |
540 | ||
fc84e8a8 RS |
541 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
542 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
543 | { | |
544 | /* For complex modes, don't make a single pseudo. | |
545 | Instead, make a CONCAT of two pseudos. | |
546 | This allows noncontiguous allocation of the real and imaginary parts, | |
547 | which makes much better code. Besides, allocating DCmode | |
548 | pseudos overstrains reload on some machines like the 386. */ | |
549 | rtx realpart, imagpart; | |
550 | int size = GET_MODE_UNIT_SIZE (mode); | |
551 | enum machine_mode partmode | |
552 | = mode_for_size (size * BITS_PER_UNIT, | |
553 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
554 | ? MODE_FLOAT : MODE_INT), | |
555 | 0); | |
556 | ||
557 | realpart = gen_reg_rtx (partmode); | |
558 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 559 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
560 | } |
561 | ||
23b2ce53 RS |
562 | /* Make sure regno_pointer_flag and regno_reg_rtx are large |
563 | enough to have an element for this pseudo reg number. */ | |
564 | ||
49ad7cfa | 565 | if (reg_rtx_no == f->emit->regno_pointer_flag_length) |
23b2ce53 | 566 | { |
49ad7cfa | 567 | int old_size = f->emit->regno_pointer_flag_length; |
23b2ce53 | 568 | rtx *new1; |
e2ecd91c BS |
569 | char *new; |
570 | new = xrealloc (f->emit->regno_pointer_flag, old_size * 2); | |
49ad7cfa BS |
571 | memset (new + old_size, 0, old_size); |
572 | f->emit->regno_pointer_flag = new; | |
573 | ||
e2ecd91c | 574 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa | 575 | memset (new + old_size, 0, old_size); |
f9e158c3 | 576 | f->emit->regno_pointer_align = (unsigned char *) new; |
49ad7cfa | 577 | |
e2ecd91c BS |
578 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
579 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 580 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
581 | regno_reg_rtx = new1; |
582 | ||
49ad7cfa | 583 | f->emit->regno_pointer_flag_length = old_size * 2; |
23b2ce53 RS |
584 | } |
585 | ||
3b80f6ca | 586 | val = gen_rtx_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
587 | regno_reg_rtx[reg_rtx_no++] = val; |
588 | return val; | |
589 | } | |
590 | ||
754fdcca RK |
591 | /* Identify REG (which may be a CONCAT) as a user register. */ |
592 | ||
593 | void | |
594 | mark_user_reg (reg) | |
595 | rtx reg; | |
596 | { | |
597 | if (GET_CODE (reg) == CONCAT) | |
598 | { | |
599 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
600 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
601 | } | |
602 | else if (GET_CODE (reg) == REG) | |
603 | REG_USERVAR_P (reg) = 1; | |
604 | else | |
605 | abort (); | |
606 | } | |
607 | ||
86fe05e0 RK |
608 | /* Identify REG as a probable pointer register and show its alignment |
609 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
610 | |
611 | void | |
86fe05e0 | 612 | mark_reg_pointer (reg, align) |
23b2ce53 | 613 | rtx reg; |
86fe05e0 | 614 | int align; |
23b2ce53 | 615 | { |
00995e78 RE |
616 | if (! REGNO_POINTER_FLAG (REGNO (reg))) |
617 | { | |
618 | REGNO_POINTER_FLAG (REGNO (reg)) = 1; | |
86fe05e0 | 619 | |
00995e78 RE |
620 | if (align) |
621 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
622 | } | |
623 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
624 | /* We can no-longer be sure just how aligned this pointer is */ | |
86fe05e0 | 625 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
626 | } |
627 | ||
628 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
629 | ||
630 | int | |
631 | max_reg_num () | |
632 | { | |
633 | return reg_rtx_no; | |
634 | } | |
635 | ||
636 | /* Return 1 + the largest label number used so far in the current function. */ | |
637 | ||
638 | int | |
639 | max_label_num () | |
640 | { | |
641 | if (last_label_num && label_num == base_label_num) | |
642 | return last_label_num; | |
643 | return label_num; | |
644 | } | |
645 | ||
646 | /* Return first label number used in this function (if any were used). */ | |
647 | ||
648 | int | |
649 | get_first_label_num () | |
650 | { | |
651 | return first_label_num; | |
652 | } | |
653 | \f | |
654 | /* Return a value representing some low-order bits of X, where the number | |
655 | of low-order bits is given by MODE. Note that no conversion is done | |
656 | between floating-point and fixed-point values, rather, the bit | |
657 | representation is returned. | |
658 | ||
659 | This function handles the cases in common between gen_lowpart, below, | |
660 | and two variants in cse.c and combine.c. These are the cases that can | |
661 | be safely handled at all points in the compilation. | |
662 | ||
663 | If this is not a case we can handle, return 0. */ | |
664 | ||
665 | rtx | |
666 | gen_lowpart_common (mode, x) | |
667 | enum machine_mode mode; | |
668 | register rtx x; | |
669 | { | |
670 | int word = 0; | |
671 | ||
672 | if (GET_MODE (x) == mode) | |
673 | return x; | |
674 | ||
675 | /* MODE must occupy no more words than the mode of X. */ | |
676 | if (GET_MODE (x) != VOIDmode | |
677 | && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD | |
678 | > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1)) | |
679 | / UNITS_PER_WORD))) | |
680 | return 0; | |
681 | ||
682 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
683 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
684 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
685 | / UNITS_PER_WORD); | |
686 | ||
687 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
688 | && (GET_MODE_CLASS (mode) == MODE_INT |
689 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
690 | { |
691 | /* If we are getting the low-order part of something that has been | |
692 | sign- or zero-extended, we can either just use the object being | |
693 | extended or make a narrower extension. If we want an even smaller | |
694 | piece than the size of the object being extended, call ourselves | |
695 | recursively. | |
696 | ||
697 | This case is used mostly by combine and cse. */ | |
698 | ||
699 | if (GET_MODE (XEXP (x, 0)) == mode) | |
700 | return XEXP (x, 0); | |
701 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
702 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
703 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3b80f6ca | 704 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 RS |
705 | } |
706 | else if (GET_CODE (x) == SUBREG | |
707 | && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
708 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) | |
709 | return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0 | |
710 | ? SUBREG_REG (x) | |
3b80f6ca | 711 | : gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + word)); |
23b2ce53 RS |
712 | else if (GET_CODE (x) == REG) |
713 | { | |
4901a643 RH |
714 | /* Let the backend decide how many registers to skip. This is needed |
715 | in particular for Sparc64 where fp regs are smaller than a word. */ | |
716 | /* ??? Note that subregs are now ambiguous, in that those against | |
717 | pseudos are sized by the Word Size, while those against hard | |
718 | regs are sized by the underlying register size. Better would be | |
719 | to always interpret the subreg offset parameter as bytes or bits. */ | |
720 | ||
721 | if (WORDS_BIG_ENDIAN && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
722 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) | |
723 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
724 | ||
23b2ce53 | 725 | /* If the register is not valid for MODE, return 0. If we don't |
674d5d8b RK |
726 | do this, there is no way to fix up the resulting REG later. |
727 | But we do do this if the current REG is not valid for its | |
728 | mode. This latter is a kludge, but is required due to the | |
729 | way that parameters are passed on some machines, most | |
730 | notably Sparc. */ | |
23b2ce53 | 731 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
674d5d8b RK |
732 | && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode) |
733 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
23b2ce53 RS |
734 | return 0; |
735 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
736 | /* integrate.c can't handle parts of a return value register. */ | |
737 | && (! REG_FUNCTION_VALUE_P (x) | |
cb00f51a | 738 | || ! rtx_equal_function_value_matters) |
aff48bca JL |
739 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
740 | && ! (GET_MODE_SIZE (mode) != GET_MODE_SIZE (GET_MODE (x)) | |
741 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT | |
742 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT | |
743 | && (TEST_HARD_REG_BIT | |
744 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
745 | REGNO (x)))) | |
746 | #endif | |
cb00f51a RK |
747 | /* We want to keep the stack, frame, and arg pointers |
748 | special. */ | |
65e8fe02 | 749 | && x != frame_pointer_rtx |
cb00f51a | 750 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 751 | && x != arg_pointer_rtx |
cb00f51a | 752 | #endif |
65e8fe02 | 753 | && x != stack_pointer_rtx) |
3b80f6ca | 754 | return gen_rtx_REG (mode, REGNO (x) + word); |
23b2ce53 | 755 | else |
3b80f6ca | 756 | return gen_rtx_SUBREG (mode, x, word); |
23b2ce53 | 757 | } |
23b2ce53 RS |
758 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
759 | from the low-order part of the constant. */ | |
83e9c679 RK |
760 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
761 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
762 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 763 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
764 | { |
765 | /* If MODE is twice the host word size, X is already the desired | |
766 | representation. Otherwise, if MODE is wider than a word, we can't | |
767 | do this. If MODE is exactly a word, return just one CONST_INT. | |
768 | If MODE is smaller than a word, clear the bits that don't belong | |
769 | in our mode, unless they and our sign bit are all one. So we get | |
770 | either a reasonable negative value or a reasonable unsigned value | |
771 | for this mode. */ | |
772 | ||
a8dd0e73 | 773 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 774 | return x; |
906c4e36 | 775 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 776 | return 0; |
906c4e36 | 777 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 778 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 779 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
780 | else |
781 | { | |
27eef9ce | 782 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
1a5b457d | 783 | int width = GET_MODE_BITSIZE (mode); |
906c4e36 RK |
784 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
785 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 786 | |
27eef9ce JC |
787 | /* Sign extend to HOST_WIDE_INT. */ |
788 | val = val << (HOST_BITS_PER_WIDE_INT - width) >> (HOST_BITS_PER_WIDE_INT - width); | |
1a5b457d RK |
789 | |
790 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 791 | : GEN_INT (val)); |
1a5b457d RK |
792 | } |
793 | } | |
23b2ce53 | 794 | |
8aada4ad RK |
795 | /* If X is an integral constant but we want it in floating-point, it |
796 | must be the case that we have a union of an integer and a floating-point | |
797 | value. If the machine-parameters allow it, simulate that union here | |
d6020413 RK |
798 | and return the result. The two-word and single-word cases are |
799 | different. */ | |
8aada4ad | 800 | |
b3bf132d | 801 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 802 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 803 | || flag_pretend_float) |
8aada4ad | 804 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
d6020413 RK |
805 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
806 | && GET_CODE (x) == CONST_INT | |
906c4e36 | 807 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
b6a524cb RS |
808 | #ifdef REAL_ARITHMETIC |
809 | { | |
810 | REAL_VALUE_TYPE r; | |
811 | HOST_WIDE_INT i; | |
812 | ||
813 | i = INTVAL (x); | |
814 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
53596fba | 815 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
816 | } |
817 | #else | |
d6020413 | 818 | { |
906c4e36 | 819 | union {HOST_WIDE_INT i; float d; } u; |
d6020413 RK |
820 | |
821 | u.i = INTVAL (x); | |
53596fba | 822 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
d6020413 | 823 | } |
b6a524cb | 824 | #endif |
d6020413 | 825 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 826 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
d6020413 RK |
827 | || flag_pretend_float) |
828 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
829 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
8aada4ad RK |
830 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
831 | && GET_MODE (x) == VOIDmode | |
906c4e36 RK |
832 | && (sizeof (double) * HOST_BITS_PER_CHAR |
833 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
b6a524cb RS |
834 | #ifdef REAL_ARITHMETIC |
835 | { | |
836 | REAL_VALUE_TYPE r; | |
837 | HOST_WIDE_INT i[2]; | |
838 | HOST_WIDE_INT low, high; | |
839 | ||
840 | if (GET_CODE (x) == CONST_INT) | |
841 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); | |
842 | else | |
843 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
844 | ||
8698cce3 | 845 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the |
0f41302f | 846 | target machine. */ |
8698cce3 RK |
847 | if (WORDS_BIG_ENDIAN) |
848 | i[0] = high, i[1] = low; | |
849 | else | |
850 | i[0] = low, i[1] = high; | |
b6a524cb RS |
851 | |
852 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
53596fba | 853 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
854 | } |
855 | #else | |
8aada4ad | 856 | { |
906c4e36 RK |
857 | union {HOST_WIDE_INT i[2]; double d; } u; |
858 | HOST_WIDE_INT low, high; | |
8aada4ad RK |
859 | |
860 | if (GET_CODE (x) == CONST_INT) | |
906c4e36 | 861 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
8aada4ad RK |
862 | else |
863 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
864 | ||
865 | #ifdef HOST_WORDS_BIG_ENDIAN | |
866 | u.i[0] = high, u.i[1] = low; | |
867 | #else | |
868 | u.i[0] = low, u.i[1] = high; | |
869 | #endif | |
870 | ||
53596fba | 871 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
8aada4ad | 872 | } |
b6a524cb | 873 | #endif |
a6a503ed JW |
874 | |
875 | /* We need an extra case for machines where HOST_BITS_PER_WIDE_INT is the | |
4926b75a JL |
876 | same as sizeof (double) or when sizeof (float) is larger than the |
877 | size of a word on the target machine. */ | |
a6a503ed | 878 | #ifdef REAL_ARITHMETIC |
4926b75a | 879 | else if (mode == SFmode && GET_CODE (x) == CONST_INT) |
a6a503ed JW |
880 | { |
881 | REAL_VALUE_TYPE r; | |
882 | HOST_WIDE_INT i; | |
883 | ||
884 | i = INTVAL (x); | |
885 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
886 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
887 | } | |
8fc4af0f JJ |
888 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
889 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
890 | || flag_pretend_float) | |
891 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
892 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
893 | && GET_CODE (x) == CONST_INT | |
894 | && (sizeof (double) * HOST_BITS_PER_CHAR | |
895 | == HOST_BITS_PER_WIDE_INT)) | |
896 | { | |
897 | REAL_VALUE_TYPE r; | |
898 | HOST_WIDE_INT i; | |
899 | ||
900 | i = INTVAL (x); | |
901 | r = REAL_VALUE_FROM_TARGET_DOUBLE (&i); | |
902 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
903 | } | |
a6a503ed JW |
904 | #endif |
905 | ||
b3bf132d RK |
906 | /* Similarly, if this is converting a floating-point value into a |
907 | single-word integer. Only do this is the host and target parameters are | |
908 | compatible. */ | |
909 | ||
910 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
906c4e36 | 911 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 912 | || flag_pretend_float) |
83e9c679 RK |
913 | && (GET_MODE_CLASS (mode) == MODE_INT |
914 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
b3bf132d RK |
915 | && GET_CODE (x) == CONST_DOUBLE |
916 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
917 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
a80586cc | 918 | return operand_subword (x, word, 0, GET_MODE (x)); |
b3bf132d | 919 | |
8aada4ad RK |
920 | /* Similarly, if this is converting a floating-point value into a |
921 | two-word integer, we can do this one word at a time and make an | |
922 | integer. Only do this is the host and target parameters are | |
923 | compatible. */ | |
924 | ||
b3bf132d | 925 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 926 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 927 | || flag_pretend_float) |
83e9c679 | 928 | && (GET_MODE_CLASS (mode) == MODE_INT |
f5a2fb25 | 929 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
8aada4ad RK |
930 | && GET_CODE (x) == CONST_DOUBLE |
931 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
932 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
933 | { | |
a80586cc RK |
934 | rtx lowpart |
935 | = operand_subword (x, word + WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
936 | rtx highpart | |
937 | = operand_subword (x, word + ! WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
8aada4ad RK |
938 | |
939 | if (lowpart && GET_CODE (lowpart) == CONST_INT | |
940 | && highpart && GET_CODE (highpart) == CONST_INT) | |
941 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
942 | } | |
943 | ||
23b2ce53 RS |
944 | /* Otherwise, we can't do this. */ |
945 | return 0; | |
946 | } | |
947 | \f | |
280194b0 RS |
948 | /* Return the real part (which has mode MODE) of a complex value X. |
949 | This always comes at the low address in memory. */ | |
950 | ||
951 | rtx | |
952 | gen_realpart (mode, x) | |
953 | enum machine_mode mode; | |
954 | register rtx x; | |
955 | { | |
dc139c90 RK |
956 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
957 | return XEXP (x, 0); | |
40c0c3cf JL |
958 | else if (WORDS_BIG_ENDIAN |
959 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
960 | && REG_P (x) | |
961 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
962 | fatal ("Unable to access real part of complex value in a hard register on this target"); | |
dc139c90 | 963 | else if (WORDS_BIG_ENDIAN) |
280194b0 RS |
964 | return gen_highpart (mode, x); |
965 | else | |
966 | return gen_lowpart (mode, x); | |
967 | } | |
968 | ||
969 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
970 | This always comes at the high address in memory. */ | |
971 | ||
972 | rtx | |
973 | gen_imagpart (mode, x) | |
974 | enum machine_mode mode; | |
975 | register rtx x; | |
976 | { | |
dc139c90 RK |
977 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
978 | return XEXP (x, 1); | |
979 | else if (WORDS_BIG_ENDIAN) | |
280194b0 | 980 | return gen_lowpart (mode, x); |
40c0c3cf JL |
981 | else if (!WORDS_BIG_ENDIAN |
982 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
983 | && REG_P (x) | |
984 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
985 | fatal ("Unable to access imaginary part of complex value in a hard register on this target"); | |
280194b0 RS |
986 | else |
987 | return gen_highpart (mode, x); | |
988 | } | |
81284a6a JW |
989 | |
990 | /* Return 1 iff X, assumed to be a SUBREG, | |
991 | refers to the real part of the complex value in its containing reg. | |
992 | Complex values are always stored with the real part in the first word, | |
993 | regardless of WORDS_BIG_ENDIAN. */ | |
994 | ||
995 | int | |
996 | subreg_realpart_p (x) | |
997 | rtx x; | |
998 | { | |
999 | if (GET_CODE (x) != SUBREG) | |
1000 | abort (); | |
1001 | ||
770ae6cc RK |
1002 | return ((unsigned int) SUBREG_WORD (x) * UNITS_PER_WORD |
1003 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); | |
81284a6a | 1004 | } |
280194b0 | 1005 | \f |
23b2ce53 RS |
1006 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1007 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1008 | least-significant part of X. | |
1009 | MODE specifies how big a part of X to return; | |
1010 | it usually should not be larger than a word. | |
1011 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1012 | ||
1013 | rtx | |
1014 | gen_lowpart (mode, x) | |
1015 | enum machine_mode mode; | |
1016 | register rtx x; | |
1017 | { | |
1018 | rtx result = gen_lowpart_common (mode, x); | |
1019 | ||
1020 | if (result) | |
1021 | return result; | |
ea8262b0 RK |
1022 | else if (GET_CODE (x) == REG) |
1023 | { | |
1024 | /* Must be a hard reg that's not valid in MODE. */ | |
1025 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1026 | if (result == 0) | |
1027 | abort (); | |
72c3833b | 1028 | return result; |
ea8262b0 | 1029 | } |
23b2ce53 RS |
1030 | else if (GET_CODE (x) == MEM) |
1031 | { | |
1032 | /* The only additional case we can do is MEM. */ | |
1033 | register int offset = 0; | |
1034 | if (WORDS_BIG_ENDIAN) | |
1035 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1036 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1037 | ||
1038 | if (BYTES_BIG_ENDIAN) | |
1039 | /* Adjust the address so that the address-after-the-data | |
1040 | is unchanged. */ | |
1041 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1042 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1043 | ||
1044 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
1045 | } | |
e9a25f70 JL |
1046 | else if (GET_CODE (x) == ADDRESSOF) |
1047 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
23b2ce53 RS |
1048 | else |
1049 | abort (); | |
1050 | } | |
1051 | ||
ccba022b RS |
1052 | /* Like `gen_lowpart', but refer to the most significant part. |
1053 | This is used to access the imaginary part of a complex number. */ | |
1054 | ||
1055 | rtx | |
1056 | gen_highpart (mode, x) | |
1057 | enum machine_mode mode; | |
1058 | register rtx x; | |
1059 | { | |
1060 | /* This case loses if X is a subreg. To catch bugs early, | |
1061 | complain if an invalid MODE is used even in other cases. */ | |
1062 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
1063 | && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
1064 | abort (); | |
1065 | if (GET_CODE (x) == CONST_DOUBLE | |
1632afca | 1066 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
ccba022b RS |
1067 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
1068 | #endif | |
1069 | ) | |
3b80f6ca | 1070 | return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); |
ccba022b | 1071 | else if (GET_CODE (x) == CONST_INT) |
27eef9ce JC |
1072 | { |
1073 | if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD) | |
1074 | return const0_rtx; | |
1075 | return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD)); | |
1076 | } | |
ccba022b RS |
1077 | else if (GET_CODE (x) == MEM) |
1078 | { | |
1079 | register int offset = 0; | |
8698cce3 RK |
1080 | if (! WORDS_BIG_ENDIAN) |
1081 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1082 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1083 | ||
1084 | if (! BYTES_BIG_ENDIAN | |
1085 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
ccba022b RS |
1086 | offset -= (GET_MODE_SIZE (mode) |
1087 | - MIN (UNITS_PER_WORD, | |
1088 | GET_MODE_SIZE (GET_MODE (x)))); | |
8698cce3 | 1089 | |
ccba022b RS |
1090 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
1091 | } | |
1092 | else if (GET_CODE (x) == SUBREG) | |
1093 | { | |
1094 | /* The only time this should occur is when we are looking at a | |
1095 | multi-word item with a SUBREG whose mode is the same as that of the | |
1096 | item. It isn't clear what we would do if it wasn't. */ | |
1097 | if (SUBREG_WORD (x) != 0) | |
1098 | abort (); | |
1099 | return gen_highpart (mode, SUBREG_REG (x)); | |
1100 | } | |
1101 | else if (GET_CODE (x) == REG) | |
1102 | { | |
6cca74ab | 1103 | int word; |
ccba022b | 1104 | |
4901a643 RH |
1105 | /* Let the backend decide how many registers to skip. This is needed |
1106 | in particular for sparc64 where fp regs are smaller than a word. */ | |
1107 | /* ??? Note that subregs are now ambiguous, in that those against | |
6cca74ab | 1108 | pseudos are sized by the word size, while those against hard |
4901a643 RH |
1109 | regs are sized by the underlying register size. Better would be |
1110 | to always interpret the subreg offset parameter as bytes or bits. */ | |
1111 | ||
6cca74ab GM |
1112 | if (WORDS_BIG_ENDIAN) |
1113 | word = 0; | |
1114 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
4901a643 RH |
1115 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) |
1116 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
6cca74ab GM |
1117 | else |
1118 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
1119 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
1120 | / UNITS_PER_WORD); | |
3e4a14ef | 1121 | |
cb00f51a | 1122 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
0f41302f | 1123 | /* integrate.c can't handle parts of a return value register. */ |
4badc528 RS |
1124 | && (! REG_FUNCTION_VALUE_P (x) |
1125 | || ! rtx_equal_function_value_matters) | |
cb00f51a | 1126 | /* We want to keep the stack, frame, and arg pointers special. */ |
65e8fe02 | 1127 | && x != frame_pointer_rtx |
cb00f51a | 1128 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1129 | && x != arg_pointer_rtx |
cb00f51a | 1130 | #endif |
65e8fe02 | 1131 | && x != stack_pointer_rtx) |
3b80f6ca | 1132 | return gen_rtx_REG (mode, REGNO (x) + word); |
ccba022b | 1133 | else |
3b80f6ca | 1134 | return gen_rtx_SUBREG (mode, x, word); |
ccba022b RS |
1135 | } |
1136 | else | |
1137 | abort (); | |
1138 | } | |
1139 | ||
23b2ce53 RS |
1140 | /* Return 1 iff X, assumed to be a SUBREG, |
1141 | refers to the least significant part of its containing reg. | |
1142 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1143 | ||
1144 | int | |
1145 | subreg_lowpart_p (x) | |
1146 | rtx x; | |
1147 | { | |
1148 | if (GET_CODE (x) != SUBREG) | |
1149 | return 1; | |
a3a03040 RK |
1150 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1151 | return 0; | |
23b2ce53 RS |
1152 | |
1153 | if (WORDS_BIG_ENDIAN | |
1154 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD) | |
1155 | return (SUBREG_WORD (x) | |
1156 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1157 | - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)) | |
1158 | / UNITS_PER_WORD)); | |
1159 | ||
1160 | return SUBREG_WORD (x) == 0; | |
1161 | } | |
1162 | \f | |
1163 | /* Return subword I of operand OP. | |
1164 | The word number, I, is interpreted as the word number starting at the | |
1165 | low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN, | |
1166 | otherwise it is the high-order word. | |
1167 | ||
1168 | If we cannot extract the required word, we return zero. Otherwise, an | |
1169 | rtx corresponding to the requested word will be returned. | |
1170 | ||
1171 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1172 | reload has completed, a valid address will always be returned. After | |
1173 | reload, if a valid address cannot be returned, we return zero. | |
1174 | ||
1175 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1176 | it is the responsibility of the caller. | |
1177 | ||
1178 | MODE is the mode of OP in case it is a CONST_INT. */ | |
1179 | ||
1180 | rtx | |
1181 | operand_subword (op, i, validate_address, mode) | |
1182 | rtx op; | |
770ae6cc | 1183 | unsigned int i; |
23b2ce53 RS |
1184 | int validate_address; |
1185 | enum machine_mode mode; | |
1186 | { | |
906c4e36 RK |
1187 | HOST_WIDE_INT val; |
1188 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; | |
23b2ce53 RS |
1189 | |
1190 | if (mode == VOIDmode) | |
1191 | mode = GET_MODE (op); | |
1192 | ||
1193 | if (mode == VOIDmode) | |
1194 | abort (); | |
1195 | ||
0003feb2 | 1196 | /* If OP is narrower than a word, fail. */ |
23b2ce53 | 1197 | if (mode != BLKmode |
0003feb2 | 1198 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) |
23b2ce53 | 1199 | return 0; |
0003feb2 VM |
1200 | |
1201 | /* If we want a word outside OP, return zero. */ | |
1202 | if (mode != BLKmode | |
1203 | && (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1204 | return const0_rtx; | |
23b2ce53 RS |
1205 | |
1206 | /* If OP is already an integer word, return it. */ | |
1207 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1208 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1209 | return op; | |
1210 | ||
1211 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1212 | if (GET_CODE (op) == REG) | |
1213 | { | |
227d6ce0 JL |
1214 | /* ??? There is a potential problem with this code. It does not |
1215 | properly handle extractions of a subword from a hard register | |
1216 | that is larger than word_mode. Presumably the check for | |
1217 | HARD_REGNO_MODE_OK catches these most of these cases. */ | |
1218 | ||
1219 | /* If OP is a hard register, but OP + I is not a hard register, | |
1220 | then extracting a subword is impossible. | |
1221 | ||
1222 | For example, consider if OP is the last hard register and it is | |
1223 | larger than word_mode. If we wanted word N (for N > 0) because a | |
1224 | part of that hard register was known to contain a useful value, | |
1225 | then OP + I would refer to a pseudo, not the hard register we | |
1226 | actually wanted. */ | |
1227 | if (REGNO (op) < FIRST_PSEUDO_REGISTER | |
1228 | && REGNO (op) + i >= FIRST_PSEUDO_REGISTER) | |
1229 | return 0; | |
1230 | ||
1231 | /* If the register is not valid for MODE, return 0. Note we | |
1232 | have to check both OP and OP + I since they may refer to | |
1233 | different parts of the register file. | |
1234 | ||
1235 | Consider if OP refers to the last 96bit FP register and we want | |
1236 | subword 3 because that subword is known to contain a value we | |
1237 | needed. */ | |
23b2ce53 | 1238 | if (REGNO (op) < FIRST_PSEUDO_REGISTER |
227d6ce0 JL |
1239 | && (! HARD_REGNO_MODE_OK (REGNO (op), word_mode) |
1240 | || ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode))) | |
23b2ce53 RS |
1241 | return 0; |
1242 | else if (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1243 | || (REG_FUNCTION_VALUE_P (op) | |
cb00f51a RK |
1244 | && rtx_equal_function_value_matters) |
1245 | /* We want to keep the stack, frame, and arg pointers | |
1246 | special. */ | |
65e8fe02 | 1247 | || op == frame_pointer_rtx |
cb00f51a | 1248 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1249 | || op == arg_pointer_rtx |
cb00f51a | 1250 | #endif |
65e8fe02 | 1251 | || op == stack_pointer_rtx) |
3b80f6ca | 1252 | return gen_rtx_SUBREG (word_mode, op, i); |
23b2ce53 | 1253 | else |
3b80f6ca | 1254 | return gen_rtx_REG (word_mode, REGNO (op) + i); |
23b2ce53 RS |
1255 | } |
1256 | else if (GET_CODE (op) == SUBREG) | |
3b80f6ca | 1257 | return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), i + SUBREG_WORD (op)); |
fc84e8a8 RS |
1258 | else if (GET_CODE (op) == CONCAT) |
1259 | { | |
770ae6cc RK |
1260 | unsigned int partwords |
1261 | = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1262 | ||
fc84e8a8 RS |
1263 | if (i < partwords) |
1264 | return operand_subword (XEXP (op, 0), i, validate_address, mode); | |
1265 | return operand_subword (XEXP (op, 1), i - partwords, | |
1266 | validate_address, mode); | |
1267 | } | |
23b2ce53 RS |
1268 | |
1269 | /* Form a new MEM at the requested address. */ | |
1270 | if (GET_CODE (op) == MEM) | |
1271 | { | |
1272 | rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD); | |
1273 | rtx new; | |
1274 | ||
1275 | if (validate_address) | |
1276 | { | |
1277 | if (reload_completed) | |
1278 | { | |
1279 | if (! strict_memory_address_p (word_mode, addr)) | |
1280 | return 0; | |
1281 | } | |
1282 | else | |
1283 | addr = memory_address (word_mode, addr); | |
1284 | } | |
1285 | ||
3b80f6ca | 1286 | new = gen_rtx_MEM (word_mode, addr); |
c6df88cb | 1287 | MEM_COPY_ATTRIBUTES (new, op); |
23b2ce53 RS |
1288 | return new; |
1289 | } | |
1290 | ||
1291 | /* The only remaining cases are when OP is a constant. If the host and | |
1292 | target floating formats are the same, handling two-word floating | |
7677ffa4 | 1293 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} |
9847c2f6 RK |
1294 | are defined as returning one or two 32 bit values, respectively, |
1295 | and not values of BITS_PER_WORD bits. */ | |
1632afca | 1296 | #ifdef REAL_ARITHMETIC |
5495cc55 RH |
1297 | /* The output is some bits, the width of the target machine's word. |
1298 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1299 | host can't. */ | |
9847c2f6 | 1300 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1632afca | 1301 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1302 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1303 | && GET_CODE (op) == CONST_DOUBLE) |
1304 | { | |
9847c2f6 | 1305 | long k[2]; |
1632afca RS |
1306 | REAL_VALUE_TYPE rv; |
1307 | ||
1308 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1309 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1310 | |
9847c2f6 | 1311 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 | 1312 | which the words are written depends on the word endianness. |
7677ffa4 | 1313 | ??? This is a potential portability problem and should |
7cae975e RH |
1314 | be fixed at some point. |
1315 | ||
1316 | We must excercise caution with the sign bit. By definition there | |
1317 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1318 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1319 | So we explicitly mask and sign-extend as necessary. */ | |
9847c2f6 | 1320 | if (BITS_PER_WORD == 32) |
7cae975e RH |
1321 | { |
1322 | val = k[i]; | |
1323 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1324 | return GEN_INT (val); | |
1325 | } | |
1326 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
9847c2f6 | 1327 | else if (BITS_PER_WORD >= 64 && i == 0) |
7cae975e RH |
1328 | { |
1329 | val = k[! WORDS_BIG_ENDIAN]; | |
1330 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1331 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1332 | return GEN_INT (val); | |
1333 | } | |
9847c2f6 | 1334 | #endif |
47b34d40 JW |
1335 | else if (BITS_PER_WORD == 16) |
1336 | { | |
7cae975e RH |
1337 | val = k[i >> 1]; |
1338 | if ((i & 1) == !WORDS_BIG_ENDIAN) | |
1339 | val >>= 16; | |
1340 | val &= 0xffff; | |
1341 | return GEN_INT (val); | |
47b34d40 | 1342 | } |
7677ffa4 RK |
1343 | else |
1344 | abort (); | |
1632afca | 1345 | } |
a5559dbc RE |
1346 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1347 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1348 | && GET_MODE_BITSIZE (mode) > 64 | |
1349 | && GET_CODE (op) == CONST_DOUBLE) | |
5495cc55 RH |
1350 | { |
1351 | long k[4]; | |
1352 | REAL_VALUE_TYPE rv; | |
a5559dbc | 1353 | |
5495cc55 RH |
1354 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1355 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
a5559dbc | 1356 | |
5495cc55 RH |
1357 | if (BITS_PER_WORD == 32) |
1358 | { | |
1359 | val = k[i]; | |
1360 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1361 | return GEN_INT (val); | |
1362 | } | |
1363 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1364 | else if (BITS_PER_WORD >= 64 && i <= 1) | |
1365 | { | |
1366 | val = k[i*2 + ! WORDS_BIG_ENDIAN]; | |
1367 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1368 | val |= (HOST_WIDE_INT) k[i*2 + WORDS_BIG_ENDIAN] & 0xffffffff; | |
1369 | return GEN_INT (val); | |
1370 | } | |
1371 | #endif | |
1372 | else | |
1373 | abort (); | |
1374 | } | |
1632afca | 1375 | #else /* no REAL_ARITHMETIC */ |
23b2ce53 | 1376 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1377 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1378 | || flag_pretend_float) |
1379 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1380 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1381 | && GET_CODE (op) == CONST_DOUBLE) | |
7529ac93 CH |
1382 | { |
1383 | /* The constant is stored in the host's word-ordering, | |
1384 | but we want to access it in the target's word-ordering. Some | |
1385 | compilers don't like a conditional inside macro args, so we have two | |
1386 | copies of the return. */ | |
2fe02d7e | 1387 | #ifdef HOST_WORDS_BIG_ENDIAN |
7529ac93 CH |
1388 | return GEN_INT (i == WORDS_BIG_ENDIAN |
1389 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1390 | #else |
7529ac93 CH |
1391 | return GEN_INT (i != WORDS_BIG_ENDIAN |
1392 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1393 | #endif |
7529ac93 | 1394 | } |
1632afca | 1395 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1396 | |
1397 | /* Single word float is a little harder, since single- and double-word | |
1398 | values often do not have the same high-order bits. We have already | |
1399 | verified that we want the only defined word of the single-word value. */ | |
1632afca | 1400 | #ifdef REAL_ARITHMETIC |
9847c2f6 | 1401 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1402 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1403 | && GET_CODE (op) == CONST_DOUBLE) |
1404 | { | |
9847c2f6 | 1405 | long l; |
1632afca RS |
1406 | REAL_VALUE_TYPE rv; |
1407 | ||
1408 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1409 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
aa2ae679 | 1410 | |
7cae975e RH |
1411 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1412 | val = l; | |
1413 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
b5a3eb84 | 1414 | |
aa2ae679 JL |
1415 | if (BITS_PER_WORD == 16) |
1416 | { | |
7cae975e RH |
1417 | if ((i & 1) == !WORDS_BIG_ENDIAN) |
1418 | val >>= 16; | |
1419 | val &= 0xffff; | |
aa2ae679 | 1420 | } |
7cae975e RH |
1421 | |
1422 | return GEN_INT (val); | |
1632afca RS |
1423 | } |
1424 | #else | |
23b2ce53 | 1425 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1426 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 | 1427 | || flag_pretend_float) |
e01a2cec | 1428 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
23b2ce53 RS |
1429 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1430 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1431 | && GET_CODE (op) == CONST_DOUBLE) | |
1432 | { | |
1433 | double d; | |
906c4e36 | 1434 | union {float f; HOST_WIDE_INT i; } u; |
23b2ce53 RS |
1435 | |
1436 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1437 | ||
1438 | u.f = d; | |
906c4e36 | 1439 | return GEN_INT (u.i); |
23b2ce53 | 1440 | } |
e01a2cec RK |
1441 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1442 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1443 | || flag_pretend_float) | |
1444 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1445 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1446 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1447 | && GET_CODE (op) == CONST_DOUBLE) | |
1448 | { | |
1449 | double d; | |
1450 | union {double d; HOST_WIDE_INT i; } u; | |
1451 | ||
1452 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1453 | ||
1454 | u.d = d; | |
1455 | return GEN_INT (u.i); | |
1456 | } | |
1632afca | 1457 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1458 | |
1459 | /* The only remaining cases that we can handle are integers. | |
1460 | Convert to proper endianness now since these cases need it. | |
1461 | At this point, i == 0 means the low-order word. | |
1462 | ||
2d4f57f8 RK |
1463 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1464 | in general. However, if OP is (const_int 0), we can just return | |
1465 | it for any word. */ | |
1466 | ||
1467 | if (op == const0_rtx) | |
1468 | return op; | |
23b2ce53 RS |
1469 | |
1470 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1471 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1472 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1473 | return 0; |
1474 | ||
1475 | if (WORDS_BIG_ENDIAN) | |
1476 | i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i; | |
1477 | ||
1478 | /* Find out which word on the host machine this value is in and get | |
1479 | it from the constant. */ | |
1480 | val = (i / size_ratio == 0 | |
1481 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) | |
1482 | : (GET_CODE (op) == CONST_INT | |
1483 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1484 | ||
3f518020 | 1485 | /* Get the value we want into the low bits of val. */ |
906c4e36 | 1486 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
3f518020 JL |
1487 | val = ((val >> ((i % size_ratio) * BITS_PER_WORD))); |
1488 | ||
7e4ce834 | 1489 | val = trunc_int_for_mode (val, word_mode); |
23b2ce53 | 1490 | |
906c4e36 | 1491 | return GEN_INT (val); |
23b2ce53 RS |
1492 | } |
1493 | ||
1494 | /* Similar to `operand_subword', but never return 0. If we can't extract | |
1495 | the required subword, put OP into a register and try again. If that fails, | |
1496 | abort. We always validate the address in this case. It is not valid | |
1497 | to call this function after reload; it is mostly meant for RTL | |
1498 | generation. | |
1499 | ||
1500 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1501 | ||
1502 | rtx | |
1503 | operand_subword_force (op, i, mode) | |
1504 | rtx op; | |
770ae6cc | 1505 | unsigned int i; |
23b2ce53 RS |
1506 | enum machine_mode mode; |
1507 | { | |
1508 | rtx result = operand_subword (op, i, 1, mode); | |
1509 | ||
1510 | if (result) | |
1511 | return result; | |
1512 | ||
1513 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1514 | { |
1515 | /* If this is a register which can not be accessed by words, copy it | |
1516 | to a pseudo register. */ | |
1517 | if (GET_CODE (op) == REG) | |
1518 | op = copy_to_reg (op); | |
1519 | else | |
1520 | op = force_reg (mode, op); | |
1521 | } | |
23b2ce53 RS |
1522 | |
1523 | result = operand_subword (op, i, 1, mode); | |
1524 | if (result == 0) | |
1525 | abort (); | |
1526 | ||
1527 | return result; | |
1528 | } | |
1529 | \f | |
1530 | /* Given a compare instruction, swap the operands. | |
1531 | A test instruction is changed into a compare of 0 against the operand. */ | |
1532 | ||
1533 | void | |
1534 | reverse_comparison (insn) | |
1535 | rtx insn; | |
1536 | { | |
1537 | rtx body = PATTERN (insn); | |
1538 | rtx comp; | |
1539 | ||
1540 | if (GET_CODE (body) == SET) | |
1541 | comp = SET_SRC (body); | |
1542 | else | |
1543 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1544 | ||
1545 | if (GET_CODE (comp) == COMPARE) | |
1546 | { | |
1547 | rtx op0 = XEXP (comp, 0); | |
1548 | rtx op1 = XEXP (comp, 1); | |
1549 | XEXP (comp, 0) = op1; | |
1550 | XEXP (comp, 1) = op0; | |
1551 | } | |
1552 | else | |
1553 | { | |
c5c76735 JL |
1554 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1555 | CONST0_RTX (GET_MODE (comp)), comp); | |
23b2ce53 RS |
1556 | if (GET_CODE (body) == SET) |
1557 | SET_SRC (body) = new; | |
1558 | else | |
1559 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1560 | } | |
1561 | } | |
1562 | \f | |
1563 | /* Return a memory reference like MEMREF, but with its mode changed | |
1564 | to MODE and its address changed to ADDR. | |
1565 | (VOIDmode means don't change the mode. | |
1566 | NULL for ADDR means don't change the address.) */ | |
1567 | ||
1568 | rtx | |
1569 | change_address (memref, mode, addr) | |
1570 | rtx memref; | |
1571 | enum machine_mode mode; | |
1572 | rtx addr; | |
1573 | { | |
1574 | rtx new; | |
1575 | ||
1576 | if (GET_CODE (memref) != MEM) | |
1577 | abort (); | |
1578 | if (mode == VOIDmode) | |
1579 | mode = GET_MODE (memref); | |
1580 | if (addr == 0) | |
1581 | addr = XEXP (memref, 0); | |
1582 | ||
1583 | /* If reload is in progress or has completed, ADDR must be valid. | |
1584 | Otherwise, we can call memory_address to make it valid. */ | |
1585 | if (reload_completed || reload_in_progress) | |
1586 | { | |
1587 | if (! memory_address_p (mode, addr)) | |
1588 | abort (); | |
1589 | } | |
1590 | else | |
1591 | addr = memory_address (mode, addr); | |
1592 | ||
9b04c6a8 RK |
1593 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1594 | return memref; | |
1595 | ||
3b80f6ca | 1596 | new = gen_rtx_MEM (mode, addr); |
c6df88cb | 1597 | MEM_COPY_ATTRIBUTES (new, memref); |
23b2ce53 RS |
1598 | return new; |
1599 | } | |
1600 | \f | |
1601 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1602 | ||
1603 | rtx | |
1604 | gen_label_rtx () | |
1605 | { | |
ca695ac9 JB |
1606 | register rtx label; |
1607 | ||
b93a436e | 1608 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
8cd0faaf | 1609 | NULL_RTX, label_num++, NULL_PTR, NULL_PTR); |
ca695ac9 | 1610 | |
23b2ce53 | 1611 | LABEL_NUSES (label) = 0; |
8cd0faaf | 1612 | LABEL_ALTERNATE_NAME (label) = NULL; |
23b2ce53 RS |
1613 | return label; |
1614 | } | |
1615 | \f | |
1616 | /* For procedure integration. */ | |
1617 | ||
23b2ce53 | 1618 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 1619 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
1620 | Used for an inline-procedure after copying the insn chain. */ |
1621 | ||
1622 | void | |
1623 | set_new_first_and_last_insn (first, last) | |
1624 | rtx first, last; | |
1625 | { | |
86fe05e0 RK |
1626 | rtx insn; |
1627 | ||
23b2ce53 RS |
1628 | first_insn = first; |
1629 | last_insn = last; | |
86fe05e0 RK |
1630 | cur_insn_uid = 0; |
1631 | ||
1632 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1633 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1634 | ||
1635 | cur_insn_uid++; | |
23b2ce53 RS |
1636 | } |
1637 | ||
1638 | /* Set the range of label numbers found in the current function. | |
1639 | This is used when belatedly compiling an inline function. */ | |
1640 | ||
1641 | void | |
1642 | set_new_first_and_last_label_num (first, last) | |
1643 | int first, last; | |
1644 | { | |
1645 | base_label_num = label_num; | |
1646 | first_label_num = first; | |
1647 | last_label_num = last; | |
1648 | } | |
49ad7cfa BS |
1649 | |
1650 | /* Set the last label number found in the current function. | |
1651 | This is used when belatedly compiling an inline function. */ | |
23b2ce53 RS |
1652 | |
1653 | void | |
49ad7cfa BS |
1654 | set_new_last_label_num (last) |
1655 | int last; | |
23b2ce53 | 1656 | { |
49ad7cfa BS |
1657 | base_label_num = label_num; |
1658 | last_label_num = last; | |
23b2ce53 | 1659 | } |
49ad7cfa | 1660 | \f |
23b2ce53 RS |
1661 | /* Restore all variables describing the current status from the structure *P. |
1662 | This is used after a nested function. */ | |
1663 | ||
1664 | void | |
1665 | restore_emit_status (p) | |
272df862 | 1666 | struct function *p ATTRIBUTE_UNUSED; |
23b2ce53 | 1667 | { |
457a2d9c | 1668 | last_label_num = 0; |
49ad7cfa | 1669 | clear_emit_caches (); |
23b2ce53 | 1670 | } |
e2ecd91c | 1671 | |
21cd906e | 1672 | /* Clear out all parts of the state in F that can safely be discarded |
e2ecd91c | 1673 | after the function has been compiled, to let garbage collection |
0a8a198c | 1674 | reclaim the memory. */ |
21cd906e | 1675 | |
e2ecd91c | 1676 | void |
0a8a198c | 1677 | free_emit_status (f) |
e2ecd91c BS |
1678 | struct function *f; |
1679 | { | |
1680 | free (f->emit->x_regno_reg_rtx); | |
1681 | free (f->emit->regno_pointer_flag); | |
1682 | free (f->emit->regno_pointer_align); | |
fa51b01b RH |
1683 | free (f->emit); |
1684 | f->emit = NULL; | |
e2ecd91c | 1685 | } |
23b2ce53 | 1686 | \f |
d1b81779 GK |
1687 | /* Go through all the RTL insn bodies and copy any invalid shared |
1688 | structure. This routine should only be called once. */ | |
23b2ce53 RS |
1689 | |
1690 | void | |
d1b81779 GK |
1691 | unshare_all_rtl (fndecl, insn) |
1692 | tree fndecl; | |
1693 | rtx insn; | |
23b2ce53 | 1694 | { |
d1b81779 | 1695 | tree decl; |
23b2ce53 | 1696 | |
d1b81779 GK |
1697 | /* Make sure that virtual parameters are not shared. */ |
1698 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
242b0ce6 | 1699 | DECL_RTL (decl) = copy_rtx_if_shared (DECL_RTL (decl)); |
d1b81779 | 1700 | |
5c6df058 AO |
1701 | /* Make sure that virtual stack slots are not shared. */ |
1702 | unshare_all_decls (DECL_INITIAL (fndecl)); | |
1703 | ||
d1b81779 GK |
1704 | /* Unshare just about everything else. */ |
1705 | unshare_all_rtl_1 (insn); | |
1706 | ||
23b2ce53 RS |
1707 | /* Make sure the addresses of stack slots found outside the insn chain |
1708 | (such as, in DECL_RTL of a variable) are not shared | |
1709 | with the insn chain. | |
1710 | ||
1711 | This special care is necessary when the stack slot MEM does not | |
1712 | actually appear in the insn chain. If it does appear, its address | |
1713 | is unshared from all else at that point. */ | |
242b0ce6 | 1714 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
1715 | } |
1716 | ||
d1b81779 GK |
1717 | /* Go through all the RTL insn bodies and copy any invalid shared |
1718 | structure, again. This is a fairly expensive thing to do so it | |
1719 | should be done sparingly. */ | |
1720 | ||
1721 | void | |
1722 | unshare_all_rtl_again (insn) | |
1723 | rtx insn; | |
1724 | { | |
1725 | rtx p; | |
624c87aa RE |
1726 | tree decl; |
1727 | ||
d1b81779 GK |
1728 | for (p = insn; p; p = NEXT_INSN (p)) |
1729 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
1730 | { | |
1731 | reset_used_flags (PATTERN (p)); | |
1732 | reset_used_flags (REG_NOTES (p)); | |
1733 | reset_used_flags (LOG_LINKS (p)); | |
1734 | } | |
624c87aa RE |
1735 | |
1736 | /* Make sure that virtual parameters are not shared. */ | |
1737 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
1738 | reset_used_flags (DECL_RTL (decl)); | |
1739 | ||
1740 | reset_used_flags (stack_slot_list); | |
1741 | ||
1742 | unshare_all_rtl (cfun->decl, insn); | |
d1b81779 GK |
1743 | } |
1744 | ||
1745 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1746 | Assumes the mark bits are cleared at entry. */ | |
1747 | ||
1748 | static void | |
1749 | unshare_all_rtl_1 (insn) | |
1750 | rtx insn; | |
1751 | { | |
1752 | for (; insn; insn = NEXT_INSN (insn)) | |
1753 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1754 | { | |
1755 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1756 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1757 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1758 | } | |
1759 | } | |
1760 | ||
5c6df058 AO |
1761 | /* Go through all virtual stack slots of a function and copy any |
1762 | shared structure. */ | |
1763 | static void | |
1764 | unshare_all_decls (blk) | |
1765 | tree blk; | |
1766 | { | |
1767 | tree t; | |
1768 | ||
1769 | /* Copy shared decls. */ | |
1770 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
1771 | DECL_RTL (t) = copy_rtx_if_shared (DECL_RTL (t)); | |
1772 | ||
1773 | /* Now process sub-blocks. */ | |
1774 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1775 | unshare_all_decls (t); | |
1776 | } | |
1777 | ||
23b2ce53 RS |
1778 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1779 | Recursively does the same for subexpressions. */ | |
1780 | ||
1781 | rtx | |
1782 | copy_rtx_if_shared (orig) | |
1783 | rtx orig; | |
1784 | { | |
1785 | register rtx x = orig; | |
1786 | register int i; | |
1787 | register enum rtx_code code; | |
6f7d635c | 1788 | register const char *format_ptr; |
23b2ce53 RS |
1789 | int copied = 0; |
1790 | ||
1791 | if (x == 0) | |
1792 | return 0; | |
1793 | ||
1794 | code = GET_CODE (x); | |
1795 | ||
1796 | /* These types may be freely shared. */ | |
1797 | ||
1798 | switch (code) | |
1799 | { | |
1800 | case REG: | |
1801 | case QUEUED: | |
1802 | case CONST_INT: | |
1803 | case CONST_DOUBLE: | |
1804 | case SYMBOL_REF: | |
1805 | case CODE_LABEL: | |
1806 | case PC: | |
1807 | case CC0: | |
1808 | case SCRATCH: | |
0f41302f | 1809 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
1810 | return x; |
1811 | ||
b851ea09 RK |
1812 | case CONST: |
1813 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
1814 | a LABEL_REF, it isn't sharable. */ | |
1815 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1816 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1817 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1818 | return x; | |
1819 | break; | |
1820 | ||
23b2ce53 RS |
1821 | case INSN: |
1822 | case JUMP_INSN: | |
1823 | case CALL_INSN: | |
1824 | case NOTE: | |
23b2ce53 RS |
1825 | case BARRIER: |
1826 | /* The chain of insns is not being copied. */ | |
1827 | return x; | |
1828 | ||
1829 | case MEM: | |
83512665 JL |
1830 | /* A MEM is allowed to be shared if its address is constant. |
1831 | ||
1832 | We used to allow sharing of MEMs which referenced | |
1833 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but | |
1834 | that can lose. instantiate_virtual_regs will not unshare | |
1835 | the MEMs, and combine may change the structure of the address | |
1836 | because it looks safe and profitable in one context, but | |
1837 | in some other context it creates unrecognizable RTL. */ | |
1838 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
23b2ce53 RS |
1839 | return x; |
1840 | ||
e9a25f70 JL |
1841 | break; |
1842 | ||
1843 | default: | |
1844 | break; | |
23b2ce53 RS |
1845 | } |
1846 | ||
1847 | /* This rtx may not be shared. If it has already been seen, | |
1848 | replace it with a copy of itself. */ | |
1849 | ||
1850 | if (x->used) | |
1851 | { | |
1852 | register rtx copy; | |
1853 | ||
1854 | copy = rtx_alloc (code); | |
4c9a05bc RK |
1855 | bcopy ((char *) x, (char *) copy, |
1856 | (sizeof (*copy) - sizeof (copy->fld) | |
1857 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
1858 | x = copy; |
1859 | copied = 1; | |
1860 | } | |
1861 | x->used = 1; | |
1862 | ||
1863 | /* Now scan the subexpressions recursively. | |
1864 | We can store any replaced subexpressions directly into X | |
1865 | since we know X is not shared! Any vectors in X | |
1866 | must be copied if X was copied. */ | |
1867 | ||
1868 | format_ptr = GET_RTX_FORMAT (code); | |
1869 | ||
1870 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1871 | { | |
1872 | switch (*format_ptr++) | |
1873 | { | |
1874 | case 'e': | |
1875 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
1876 | break; | |
1877 | ||
1878 | case 'E': | |
1879 | if (XVEC (x, i) != NULL) | |
1880 | { | |
1881 | register int j; | |
f0722107 | 1882 | int len = XVECLEN (x, i); |
23b2ce53 | 1883 | |
f0722107 | 1884 | if (copied && len > 0) |
8f985ec4 | 1885 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
f0722107 RS |
1886 | for (j = 0; j < len; j++) |
1887 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
1888 | } |
1889 | break; | |
1890 | } | |
1891 | } | |
1892 | return x; | |
1893 | } | |
1894 | ||
1895 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
1896 | to look for shared sub-parts. */ | |
1897 | ||
1898 | void | |
1899 | reset_used_flags (x) | |
1900 | rtx x; | |
1901 | { | |
1902 | register int i, j; | |
1903 | register enum rtx_code code; | |
6f7d635c | 1904 | register const char *format_ptr; |
23b2ce53 RS |
1905 | |
1906 | if (x == 0) | |
1907 | return; | |
1908 | ||
1909 | code = GET_CODE (x); | |
1910 | ||
9faa82d8 | 1911 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
1912 | for them. */ |
1913 | ||
1914 | switch (code) | |
1915 | { | |
1916 | case REG: | |
1917 | case QUEUED: | |
1918 | case CONST_INT: | |
1919 | case CONST_DOUBLE: | |
1920 | case SYMBOL_REF: | |
1921 | case CODE_LABEL: | |
1922 | case PC: | |
1923 | case CC0: | |
1924 | return; | |
1925 | ||
1926 | case INSN: | |
1927 | case JUMP_INSN: | |
1928 | case CALL_INSN: | |
1929 | case NOTE: | |
1930 | case LABEL_REF: | |
1931 | case BARRIER: | |
1932 | /* The chain of insns is not being copied. */ | |
1933 | return; | |
e9a25f70 JL |
1934 | |
1935 | default: | |
1936 | break; | |
23b2ce53 RS |
1937 | } |
1938 | ||
1939 | x->used = 0; | |
1940 | ||
1941 | format_ptr = GET_RTX_FORMAT (code); | |
1942 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1943 | { | |
1944 | switch (*format_ptr++) | |
1945 | { | |
1946 | case 'e': | |
1947 | reset_used_flags (XEXP (x, i)); | |
1948 | break; | |
1949 | ||
1950 | case 'E': | |
1951 | for (j = 0; j < XVECLEN (x, i); j++) | |
1952 | reset_used_flags (XVECEXP (x, i, j)); | |
1953 | break; | |
1954 | } | |
1955 | } | |
1956 | } | |
1957 | \f | |
1958 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
1959 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
1960 | OTHER must be valid as a SET_DEST. */ | |
1961 | ||
1962 | rtx | |
1963 | make_safe_from (x, other) | |
1964 | rtx x, other; | |
1965 | { | |
1966 | while (1) | |
1967 | switch (GET_CODE (other)) | |
1968 | { | |
1969 | case SUBREG: | |
1970 | other = SUBREG_REG (other); | |
1971 | break; | |
1972 | case STRICT_LOW_PART: | |
1973 | case SIGN_EXTEND: | |
1974 | case ZERO_EXTEND: | |
1975 | other = XEXP (other, 0); | |
1976 | break; | |
1977 | default: | |
1978 | goto done; | |
1979 | } | |
1980 | done: | |
1981 | if ((GET_CODE (other) == MEM | |
1982 | && ! CONSTANT_P (x) | |
1983 | && GET_CODE (x) != REG | |
1984 | && GET_CODE (x) != SUBREG) | |
1985 | || (GET_CODE (other) == REG | |
1986 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
1987 | || reg_mentioned_p (other, x)))) | |
1988 | { | |
1989 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
1990 | emit_move_insn (temp, x); | |
1991 | return temp; | |
1992 | } | |
1993 | return x; | |
1994 | } | |
1995 | \f | |
1996 | /* Emission of insns (adding them to the doubly-linked list). */ | |
1997 | ||
1998 | /* Return the first insn of the current sequence or current function. */ | |
1999 | ||
2000 | rtx | |
2001 | get_insns () | |
2002 | { | |
2003 | return first_insn; | |
2004 | } | |
2005 | ||
2006 | /* Return the last insn emitted in current sequence or current function. */ | |
2007 | ||
2008 | rtx | |
2009 | get_last_insn () | |
2010 | { | |
2011 | return last_insn; | |
2012 | } | |
2013 | ||
2014 | /* Specify a new insn as the last in the chain. */ | |
2015 | ||
2016 | void | |
2017 | set_last_insn (insn) | |
2018 | rtx insn; | |
2019 | { | |
2020 | if (NEXT_INSN (insn) != 0) | |
2021 | abort (); | |
2022 | last_insn = insn; | |
2023 | } | |
2024 | ||
2025 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2026 | ||
2027 | rtx | |
2028 | get_last_insn_anywhere () | |
2029 | { | |
2030 | struct sequence_stack *stack; | |
2031 | if (last_insn) | |
2032 | return last_insn; | |
49ad7cfa | 2033 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2034 | if (stack->last != 0) |
2035 | return stack->last; | |
2036 | return 0; | |
2037 | } | |
2038 | ||
2039 | /* Return a number larger than any instruction's uid in this function. */ | |
2040 | ||
2041 | int | |
2042 | get_max_uid () | |
2043 | { | |
2044 | return cur_insn_uid; | |
2045 | } | |
aeeeda03 | 2046 | |
673b5311 MM |
2047 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2048 | ||
aeeeda03 | 2049 | void |
673b5311 MM |
2050 | renumber_insns (stream) |
2051 | FILE *stream; | |
aeeeda03 MM |
2052 | { |
2053 | rtx insn; | |
aeeeda03 | 2054 | |
673b5311 MM |
2055 | /* If we're not supposed to renumber instructions, don't. */ |
2056 | if (!flag_renumber_insns) | |
2057 | return; | |
2058 | ||
aeeeda03 MM |
2059 | /* If there aren't that many instructions, then it's not really |
2060 | worth renumbering them. */ | |
673b5311 | 2061 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
aeeeda03 MM |
2062 | return; |
2063 | ||
2064 | cur_insn_uid = 1; | |
2065 | ||
2066 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
673b5311 MM |
2067 | { |
2068 | if (stream) | |
2069 | fprintf (stream, "Renumbering insn %d to %d\n", | |
2070 | INSN_UID (insn), cur_insn_uid); | |
2071 | INSN_UID (insn) = cur_insn_uid++; | |
2072 | } | |
aeeeda03 | 2073 | } |
23b2ce53 RS |
2074 | \f |
2075 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2076 | of the sequence. */ | |
2077 | ||
2078 | rtx | |
2079 | next_insn (insn) | |
2080 | rtx insn; | |
2081 | { | |
2082 | if (insn) | |
2083 | { | |
2084 | insn = NEXT_INSN (insn); | |
2085 | if (insn && GET_CODE (insn) == INSN | |
2086 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2087 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2088 | } | |
2089 | ||
2090 | return insn; | |
2091 | } | |
2092 | ||
2093 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2094 | of the sequence. */ | |
2095 | ||
2096 | rtx | |
2097 | previous_insn (insn) | |
2098 | rtx insn; | |
2099 | { | |
2100 | if (insn) | |
2101 | { | |
2102 | insn = PREV_INSN (insn); | |
2103 | if (insn && GET_CODE (insn) == INSN | |
2104 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2105 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2106 | } | |
2107 | ||
2108 | return insn; | |
2109 | } | |
2110 | ||
2111 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2112 | look inside SEQUENCEs. */ | |
2113 | ||
2114 | rtx | |
2115 | next_nonnote_insn (insn) | |
2116 | rtx insn; | |
2117 | { | |
2118 | while (insn) | |
2119 | { | |
2120 | insn = NEXT_INSN (insn); | |
2121 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | return insn; | |
2126 | } | |
2127 | ||
2128 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2129 | not look inside SEQUENCEs. */ | |
2130 | ||
2131 | rtx | |
2132 | prev_nonnote_insn (insn) | |
2133 | rtx insn; | |
2134 | { | |
2135 | while (insn) | |
2136 | { | |
2137 | insn = PREV_INSN (insn); | |
2138 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2139 | break; | |
2140 | } | |
2141 | ||
2142 | return insn; | |
2143 | } | |
2144 | ||
2145 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2146 | or 0, if there is none. This routine does not look inside | |
0f41302f | 2147 | SEQUENCEs. */ |
23b2ce53 RS |
2148 | |
2149 | rtx | |
2150 | next_real_insn (insn) | |
2151 | rtx insn; | |
2152 | { | |
2153 | while (insn) | |
2154 | { | |
2155 | insn = NEXT_INSN (insn); | |
2156 | if (insn == 0 || GET_CODE (insn) == INSN | |
2157 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2158 | break; | |
2159 | } | |
2160 | ||
2161 | return insn; | |
2162 | } | |
2163 | ||
2164 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2165 | or 0, if there is none. This routine does not look inside | |
2166 | SEQUENCEs. */ | |
2167 | ||
2168 | rtx | |
2169 | prev_real_insn (insn) | |
2170 | rtx insn; | |
2171 | { | |
2172 | while (insn) | |
2173 | { | |
2174 | insn = PREV_INSN (insn); | |
2175 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2176 | || GET_CODE (insn) == JUMP_INSN) | |
2177 | break; | |
2178 | } | |
2179 | ||
2180 | return insn; | |
2181 | } | |
2182 | ||
2183 | /* Find the next insn after INSN that really does something. This routine | |
2184 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2185 | same as next_real_insn. */ | |
2186 | ||
69732dcb RH |
2187 | int |
2188 | active_insn_p (insn) | |
2189 | rtx insn; | |
2190 | { | |
2191 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2192 | || (GET_CODE (insn) == INSN | |
2193 | && (! reload_completed | |
2194 | || (GET_CODE (PATTERN (insn)) != USE | |
2195 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2196 | } | |
2197 | ||
23b2ce53 RS |
2198 | rtx |
2199 | next_active_insn (insn) | |
2200 | rtx insn; | |
2201 | { | |
2202 | while (insn) | |
2203 | { | |
2204 | insn = NEXT_INSN (insn); | |
69732dcb | 2205 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2206 | break; |
2207 | } | |
2208 | ||
2209 | return insn; | |
2210 | } | |
2211 | ||
2212 | /* Find the last insn before INSN that really does something. This routine | |
2213 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2214 | same as prev_real_insn. */ | |
2215 | ||
2216 | rtx | |
2217 | prev_active_insn (insn) | |
2218 | rtx insn; | |
2219 | { | |
2220 | while (insn) | |
2221 | { | |
2222 | insn = PREV_INSN (insn); | |
69732dcb | 2223 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2224 | break; |
2225 | } | |
2226 | ||
2227 | return insn; | |
2228 | } | |
2229 | ||
2230 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2231 | ||
2232 | rtx | |
2233 | next_label (insn) | |
2234 | rtx insn; | |
2235 | { | |
2236 | while (insn) | |
2237 | { | |
2238 | insn = NEXT_INSN (insn); | |
2239 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2240 | break; | |
2241 | } | |
2242 | ||
2243 | return insn; | |
2244 | } | |
2245 | ||
2246 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2247 | ||
2248 | rtx | |
2249 | prev_label (insn) | |
2250 | rtx insn; | |
2251 | { | |
2252 | while (insn) | |
2253 | { | |
2254 | insn = PREV_INSN (insn); | |
2255 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2256 | break; | |
2257 | } | |
2258 | ||
2259 | return insn; | |
2260 | } | |
2261 | \f | |
2262 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
2263 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2264 | and REG_CC_USER notes so we can find it. */ | |
2265 | ||
2266 | void | |
2267 | link_cc0_insns (insn) | |
2268 | rtx insn; | |
2269 | { | |
2270 | rtx user = next_nonnote_insn (insn); | |
2271 | ||
2272 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2273 | user = XVECEXP (PATTERN (user), 0, 0); | |
2274 | ||
c5c76735 JL |
2275 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2276 | REG_NOTES (user)); | |
3b80f6ca | 2277 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
2278 | } |
2279 | ||
23b2ce53 RS |
2280 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2281 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2282 | applied to the result of this function should yield INSN). | |
2283 | ||
2284 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2285 | is present, it contains the insn that uses CC0. | |
2286 | ||
2287 | Return 0 if we can't find the insn. */ | |
2288 | ||
2289 | rtx | |
2290 | next_cc0_user (insn) | |
2291 | rtx insn; | |
2292 | { | |
906c4e36 | 2293 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
2294 | |
2295 | if (note) | |
2296 | return XEXP (note, 0); | |
2297 | ||
2298 | insn = next_nonnote_insn (insn); | |
2299 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2300 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2301 | ||
2302 | if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2303 | && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
2304 | return insn; | |
2305 | ||
2306 | return 0; | |
2307 | } | |
2308 | ||
2309 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2310 | note, it is the previous insn. */ | |
2311 | ||
2312 | rtx | |
2313 | prev_cc0_setter (insn) | |
2314 | rtx insn; | |
2315 | { | |
906c4e36 | 2316 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
2317 | |
2318 | if (note) | |
2319 | return XEXP (note, 0); | |
2320 | ||
2321 | insn = prev_nonnote_insn (insn); | |
2322 | if (! sets_cc0_p (PATTERN (insn))) | |
2323 | abort (); | |
2324 | ||
2325 | return insn; | |
2326 | } | |
2327 | #endif | |
2328 | \f | |
2329 | /* Try splitting insns that can be split for better scheduling. | |
2330 | PAT is the pattern which might split. | |
2331 | TRIAL is the insn providing PAT. | |
11147ebe | 2332 | LAST is non-zero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
2333 | |
2334 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 2335 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
2336 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2337 | ||
2338 | rtx | |
11147ebe | 2339 | try_split (pat, trial, last) |
23b2ce53 | 2340 | rtx pat, trial; |
11147ebe | 2341 | int last; |
23b2ce53 RS |
2342 | { |
2343 | rtx before = PREV_INSN (trial); | |
2344 | rtx after = NEXT_INSN (trial); | |
2345 | rtx seq = split_insns (pat, trial); | |
2346 | int has_barrier = 0; | |
2347 | rtx tem; | |
2348 | ||
2349 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2350 | We may need to handle this specially. */ | |
2351 | if (after && GET_CODE (after) == BARRIER) | |
2352 | { | |
2353 | has_barrier = 1; | |
2354 | after = NEXT_INSN (after); | |
2355 | } | |
2356 | ||
2357 | if (seq) | |
2358 | { | |
2359 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2360 | The latter case will normally arise only when being done so that | |
2361 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2362 | if (GET_CODE (seq) == SEQUENCE) | |
2363 | { | |
4b5e8abe CP |
2364 | int i; |
2365 | ||
2366 | /* Avoid infinite loop if any insn of the result matches | |
2367 | the original pattern. */ | |
2368 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2369 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN | |
2370 | && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat)) | |
2371 | return trial; | |
2372 | ||
23b2ce53 RS |
2373 | /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in |
2374 | SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero, | |
2375 | increment the usage count so we don't delete the label. */ | |
23b2ce53 RS |
2376 | |
2377 | if (GET_CODE (trial) == JUMP_INSN) | |
2378 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2379 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2380 | { | |
2381 | JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial); | |
2382 | ||
2383 | if (JUMP_LABEL (trial)) | |
2384 | LABEL_NUSES (JUMP_LABEL (trial))++; | |
2385 | } | |
2386 | ||
2387 | tem = emit_insn_after (seq, before); | |
2388 | ||
2389 | delete_insn (trial); | |
2390 | if (has_barrier) | |
2391 | emit_barrier_after (tem); | |
11147ebe RK |
2392 | |
2393 | /* Recursively call try_split for each new insn created; by the | |
2394 | time control returns here that insn will be fully split, so | |
2395 | set LAST and continue from the insn after the one returned. | |
f4a3cd05 | 2396 | We can't use next_active_insn here since AFTER may be a note. |
23886015 | 2397 | Ignore deleted insns, which can be occur if not optimizing. */ |
11147ebe RK |
2398 | for (tem = NEXT_INSN (before); tem != after; |
2399 | tem = NEXT_INSN (tem)) | |
23886015 RH |
2400 | if (! INSN_DELETED_P (tem) |
2401 | && GET_RTX_CLASS (GET_CODE (tem)) == 'i') | |
f4a3cd05 | 2402 | tem = try_split (PATTERN (tem), tem, 1); |
23b2ce53 RS |
2403 | } |
2404 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2405 | else if (rtx_equal_p (seq, pat)) | |
2406 | return trial; | |
2407 | else | |
2408 | { | |
2409 | PATTERN (trial) = seq; | |
2410 | INSN_CODE (trial) = -1; | |
11147ebe | 2411 | try_split (seq, trial, last); |
23b2ce53 RS |
2412 | } |
2413 | ||
11147ebe RK |
2414 | /* Return either the first or the last insn, depending on which was |
2415 | requested. */ | |
ba52f355 CP |
2416 | return last |
2417 | ? (after ? prev_active_insn (after) : last_insn) | |
2418 | : next_active_insn (before); | |
23b2ce53 RS |
2419 | } |
2420 | ||
2421 | return trial; | |
2422 | } | |
2423 | \f | |
2424 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 2425 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
2426 | |
2427 | rtx | |
4b1f5e8c | 2428 | make_insn_raw (pattern) |
23b2ce53 | 2429 | rtx pattern; |
23b2ce53 RS |
2430 | { |
2431 | register rtx insn; | |
2432 | ||
43127294 | 2433 | /* If in RTL generation phase, see if FREE_INSN can be used. */ |
a3770a81 | 2434 | if (!ggc_p && free_insn != 0 && rtx_equal_function_value_matters) |
43127294 RK |
2435 | { |
2436 | insn = free_insn; | |
2437 | free_insn = NEXT_INSN (free_insn); | |
2438 | PUT_CODE (insn, INSN); | |
2439 | } | |
2440 | else | |
2441 | insn = rtx_alloc (INSN); | |
23b2ce53 | 2442 | |
43127294 | 2443 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2444 | PATTERN (insn) = pattern; |
2445 | INSN_CODE (insn) = -1; | |
1632afca RS |
2446 | LOG_LINKS (insn) = NULL; |
2447 | REG_NOTES (insn) = NULL; | |
23b2ce53 | 2448 | |
47984720 NC |
2449 | #ifdef ENABLE_RTL_CHECKING |
2450 | if (insn | |
2451 | && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2452 | && (returnjump_p (insn) | |
2453 | || (GET_CODE (insn) == SET | |
2454 | && SET_DEST (insn) == pc_rtx))) | |
2455 | { | |
2456 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2457 | debug_rtx (insn); | |
2458 | } | |
2459 | #endif | |
2460 | ||
23b2ce53 RS |
2461 | return insn; |
2462 | } | |
2463 | ||
2464 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2465 | ||
2466 | static rtx | |
4b1f5e8c | 2467 | make_jump_insn_raw (pattern) |
23b2ce53 | 2468 | rtx pattern; |
23b2ce53 RS |
2469 | { |
2470 | register rtx insn; | |
2471 | ||
4b1f5e8c | 2472 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 2473 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2474 | |
2475 | PATTERN (insn) = pattern; | |
2476 | INSN_CODE (insn) = -1; | |
1632afca RS |
2477 | LOG_LINKS (insn) = NULL; |
2478 | REG_NOTES (insn) = NULL; | |
2479 | JUMP_LABEL (insn) = NULL; | |
23b2ce53 RS |
2480 | |
2481 | return insn; | |
2482 | } | |
aff507f4 RK |
2483 | |
2484 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2485 | ||
2486 | static rtx | |
2487 | make_call_insn_raw (pattern) | |
2488 | rtx pattern; | |
2489 | { | |
2490 | register rtx insn; | |
2491 | ||
2492 | insn = rtx_alloc (CALL_INSN); | |
2493 | INSN_UID (insn) = cur_insn_uid++; | |
2494 | ||
2495 | PATTERN (insn) = pattern; | |
2496 | INSN_CODE (insn) = -1; | |
2497 | LOG_LINKS (insn) = NULL; | |
2498 | REG_NOTES (insn) = NULL; | |
2499 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2500 | ||
2501 | return insn; | |
2502 | } | |
23b2ce53 RS |
2503 | \f |
2504 | /* Add INSN to the end of the doubly-linked list. | |
2505 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2506 | ||
2507 | void | |
2508 | add_insn (insn) | |
2509 | register rtx insn; | |
2510 | { | |
2511 | PREV_INSN (insn) = last_insn; | |
2512 | NEXT_INSN (insn) = 0; | |
2513 | ||
2514 | if (NULL != last_insn) | |
2515 | NEXT_INSN (last_insn) = insn; | |
2516 | ||
2517 | if (NULL == first_insn) | |
2518 | first_insn = insn; | |
2519 | ||
2520 | last_insn = insn; | |
2521 | } | |
2522 | ||
a0ae8e8d RK |
2523 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2524 | the next should be the only functions called to insert an insn once | |
ba213285 | 2525 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 2526 | SEQUENCE. */ |
23b2ce53 RS |
2527 | |
2528 | void | |
2529 | add_insn_after (insn, after) | |
2530 | rtx insn, after; | |
2531 | { | |
2532 | rtx next = NEXT_INSN (after); | |
2533 | ||
6782074d | 2534 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
2535 | abort (); |
2536 | ||
23b2ce53 RS |
2537 | NEXT_INSN (insn) = next; |
2538 | PREV_INSN (insn) = after; | |
2539 | ||
2540 | if (next) | |
2541 | { | |
2542 | PREV_INSN (next) = insn; | |
2543 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2544 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2545 | } | |
2546 | else if (last_insn == after) | |
2547 | last_insn = insn; | |
2548 | else | |
2549 | { | |
49ad7cfa | 2550 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
2551 | /* Scan all pending sequences too. */ |
2552 | for (; stack; stack = stack->next) | |
2553 | if (after == stack->last) | |
fef0509b RK |
2554 | { |
2555 | stack->last = insn; | |
2556 | break; | |
2557 | } | |
a0ae8e8d RK |
2558 | |
2559 | if (stack == 0) | |
2560 | abort (); | |
23b2ce53 RS |
2561 | } |
2562 | ||
2563 | NEXT_INSN (after) = insn; | |
2564 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2565 | { | |
2566 | rtx sequence = PATTERN (after); | |
2567 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2568 | } | |
2569 | } | |
2570 | ||
a0ae8e8d RK |
2571 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2572 | the previous should be the only functions called to insert an insn once | |
ba213285 | 2573 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
2574 | SEQUENCE. */ |
2575 | ||
2576 | void | |
2577 | add_insn_before (insn, before) | |
2578 | rtx insn, before; | |
2579 | { | |
2580 | rtx prev = PREV_INSN (before); | |
2581 | ||
6782074d | 2582 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
2583 | abort (); |
2584 | ||
a0ae8e8d RK |
2585 | PREV_INSN (insn) = prev; |
2586 | NEXT_INSN (insn) = before; | |
2587 | ||
2588 | if (prev) | |
2589 | { | |
2590 | NEXT_INSN (prev) = insn; | |
2591 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2592 | { | |
2593 | rtx sequence = PATTERN (prev); | |
2594 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2595 | } | |
2596 | } | |
2597 | else if (first_insn == before) | |
2598 | first_insn = insn; | |
2599 | else | |
2600 | { | |
49ad7cfa | 2601 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
2602 | /* Scan all pending sequences too. */ |
2603 | for (; stack; stack = stack->next) | |
2604 | if (before == stack->first) | |
fef0509b RK |
2605 | { |
2606 | stack->first = insn; | |
2607 | break; | |
2608 | } | |
a0ae8e8d RK |
2609 | |
2610 | if (stack == 0) | |
2611 | abort (); | |
2612 | } | |
2613 | ||
2614 | PREV_INSN (before) = insn; | |
2615 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2616 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2617 | } | |
2618 | ||
89e99eea DB |
2619 | /* Remove an insn from its doubly-linked list. This function knows how |
2620 | to handle sequences. */ | |
2621 | void | |
2622 | remove_insn (insn) | |
2623 | rtx insn; | |
2624 | { | |
2625 | rtx next = NEXT_INSN (insn); | |
2626 | rtx prev = PREV_INSN (insn); | |
2627 | if (prev) | |
2628 | { | |
2629 | NEXT_INSN (prev) = next; | |
2630 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2631 | { | |
2632 | rtx sequence = PATTERN (prev); | |
2633 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2634 | } | |
2635 | } | |
2636 | else if (first_insn == insn) | |
2637 | first_insn = next; | |
2638 | else | |
2639 | { | |
49ad7cfa | 2640 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2641 | /* Scan all pending sequences too. */ |
2642 | for (; stack; stack = stack->next) | |
2643 | if (insn == stack->first) | |
2644 | { | |
2645 | stack->first = next; | |
2646 | break; | |
2647 | } | |
2648 | ||
2649 | if (stack == 0) | |
2650 | abort (); | |
2651 | } | |
2652 | ||
2653 | if (next) | |
2654 | { | |
2655 | PREV_INSN (next) = prev; | |
2656 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2657 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2658 | } | |
2659 | else if (last_insn == insn) | |
2660 | last_insn = prev; | |
2661 | else | |
2662 | { | |
49ad7cfa | 2663 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2664 | /* Scan all pending sequences too. */ |
2665 | for (; stack; stack = stack->next) | |
2666 | if (insn == stack->last) | |
2667 | { | |
2668 | stack->last = prev; | |
2669 | break; | |
2670 | } | |
2671 | ||
2672 | if (stack == 0) | |
2673 | abort (); | |
2674 | } | |
2675 | } | |
2676 | ||
23b2ce53 RS |
2677 | /* Delete all insns made since FROM. |
2678 | FROM becomes the new last instruction. */ | |
2679 | ||
2680 | void | |
2681 | delete_insns_since (from) | |
2682 | rtx from; | |
2683 | { | |
2684 | if (from == 0) | |
2685 | first_insn = 0; | |
2686 | else | |
2687 | NEXT_INSN (from) = 0; | |
2688 | last_insn = from; | |
2689 | } | |
2690 | ||
5dab5552 MS |
2691 | /* This function is deprecated, please use sequences instead. |
2692 | ||
2693 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
2694 | The insns to be moved are those between FROM and TO. |
2695 | They are moved to a new position after the insn AFTER. | |
2696 | AFTER must not be FROM or TO or any insn in between. | |
2697 | ||
2698 | This function does not know about SEQUENCEs and hence should not be | |
2699 | called after delay-slot filling has been done. */ | |
2700 | ||
2701 | void | |
2702 | reorder_insns (from, to, after) | |
2703 | rtx from, to, after; | |
2704 | { | |
2705 | /* Splice this bunch out of where it is now. */ | |
2706 | if (PREV_INSN (from)) | |
2707 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2708 | if (NEXT_INSN (to)) | |
2709 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2710 | if (last_insn == to) | |
2711 | last_insn = PREV_INSN (from); | |
2712 | if (first_insn == from) | |
2713 | first_insn = NEXT_INSN (to); | |
2714 | ||
2715 | /* Make the new neighbors point to it and it to them. */ | |
2716 | if (NEXT_INSN (after)) | |
2717 | PREV_INSN (NEXT_INSN (after)) = to; | |
2718 | ||
2719 | NEXT_INSN (to) = NEXT_INSN (after); | |
2720 | PREV_INSN (from) = after; | |
2721 | NEXT_INSN (after) = from; | |
2722 | if (after == last_insn) | |
2723 | last_insn = to; | |
2724 | } | |
2725 | ||
2726 | /* Return the line note insn preceding INSN. */ | |
2727 | ||
2728 | static rtx | |
2729 | find_line_note (insn) | |
2730 | rtx insn; | |
2731 | { | |
2732 | if (no_line_numbers) | |
2733 | return 0; | |
2734 | ||
2735 | for (; insn; insn = PREV_INSN (insn)) | |
2736 | if (GET_CODE (insn) == NOTE | |
2737 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2738 | break; | |
2739 | ||
2740 | return insn; | |
2741 | } | |
2742 | ||
2743 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2744 | of the moved insns when debugging. This may insert a note between AFTER | |
2745 | and FROM, and another one after TO. */ | |
2746 | ||
2747 | void | |
2748 | reorder_insns_with_line_notes (from, to, after) | |
2749 | rtx from, to, after; | |
2750 | { | |
2751 | rtx from_line = find_line_note (from); | |
2752 | rtx after_line = find_line_note (after); | |
2753 | ||
2754 | reorder_insns (from, to, after); | |
2755 | ||
2756 | if (from_line == after_line) | |
2757 | return; | |
2758 | ||
2759 | if (from_line) | |
2760 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2761 | NOTE_LINE_NUMBER (from_line), | |
2762 | after); | |
2763 | if (after_line) | |
2764 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2765 | NOTE_LINE_NUMBER (after_line), | |
2766 | to); | |
2767 | } | |
aeeeda03 | 2768 | |
64b59a80 | 2769 | /* Remove unnecessary notes from the instruction stream. */ |
aeeeda03 MM |
2770 | |
2771 | void | |
64b59a80 | 2772 | remove_unnecessary_notes () |
aeeeda03 MM |
2773 | { |
2774 | rtx insn; | |
2775 | rtx next; | |
aeeeda03 | 2776 | |
116eebd6 MM |
2777 | /* We must not remove the first instruction in the function because |
2778 | the compiler depends on the first instruction being a note. */ | |
aeeeda03 MM |
2779 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
2780 | { | |
2781 | /* Remember what's next. */ | |
2782 | next = NEXT_INSN (insn); | |
2783 | ||
2784 | /* We're only interested in notes. */ | |
2785 | if (GET_CODE (insn) != NOTE) | |
2786 | continue; | |
2787 | ||
116eebd6 MM |
2788 | /* By now, all notes indicating lexical blocks should have |
2789 | NOTE_BLOCK filled in. */ | |
2790 | if ((NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG | |
2791 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) | |
2792 | && NOTE_BLOCK (insn) == NULL_TREE) | |
2793 | abort (); | |
2794 | ||
2795 | /* Remove NOTE_INSN_DELETED notes. */ | |
aeeeda03 MM |
2796 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) |
2797 | remove_insn (insn); | |
18c038b9 MM |
2798 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) |
2799 | { | |
2800 | /* Scan back to see if there are any non-note instructions | |
2801 | between INSN and the beginning of this block. If not, | |
2802 | then there is no PC range in the generated code that will | |
2803 | actually be in this block, so there's no point in | |
2804 | remembering the existence of the block. */ | |
2805 | rtx prev; | |
2806 | ||
2807 | for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev)) | |
2808 | { | |
2809 | /* This block contains a real instruction. Note that we | |
2810 | don't include labels; if the only thing in the block | |
2811 | is a label, then there are still no PC values that | |
2812 | lie within the block. */ | |
2813 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i') | |
2814 | break; | |
2815 | ||
2816 | /* We're only interested in NOTEs. */ | |
2817 | if (GET_CODE (prev) != NOTE) | |
2818 | continue; | |
2819 | ||
2820 | if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_BEG) | |
2821 | { | |
2822 | /* If the BLOCKs referred to by these notes don't | |
2823 | match, then something is wrong with our BLOCK | |
2824 | nesting structure. */ | |
2825 | if (NOTE_BLOCK (prev) != NOTE_BLOCK (insn)) | |
2826 | abort (); | |
fcd7f76b | 2827 | |
64b59a80 | 2828 | if (debug_ignore_block (NOTE_BLOCK (insn))) |
deb5e280 | 2829 | { |
deb5e280 JM |
2830 | remove_insn (prev); |
2831 | remove_insn (insn); | |
2832 | } | |
18c038b9 MM |
2833 | break; |
2834 | } | |
2835 | else if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_END) | |
2836 | /* There's a nested block. We need to leave the | |
2837 | current block in place since otherwise the debugger | |
2838 | wouldn't be able to show symbols from our block in | |
2839 | the nested block. */ | |
2840 | break; | |
2841 | } | |
2842 | } | |
aeeeda03 MM |
2843 | } |
2844 | } | |
2845 | ||
23b2ce53 RS |
2846 | \f |
2847 | /* Emit an insn of given code and pattern | |
2848 | at a specified place within the doubly-linked list. */ | |
2849 | ||
2850 | /* Make an instruction with body PATTERN | |
2851 | and output it before the instruction BEFORE. */ | |
2852 | ||
2853 | rtx | |
2854 | emit_insn_before (pattern, before) | |
2855 | register rtx pattern, before; | |
2856 | { | |
2857 | register rtx insn = before; | |
2858 | ||
2859 | if (GET_CODE (pattern) == SEQUENCE) | |
2860 | { | |
2861 | register int i; | |
2862 | ||
2863 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2864 | { | |
2865 | insn = XVECEXP (pattern, 0, i); | |
a0ae8e8d | 2866 | add_insn_before (insn, before); |
23b2ce53 | 2867 | } |
a3770a81 | 2868 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
2869 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
2870 | } | |
2871 | else | |
2872 | { | |
4b1f5e8c | 2873 | insn = make_insn_raw (pattern); |
a0ae8e8d | 2874 | add_insn_before (insn, before); |
23b2ce53 RS |
2875 | } |
2876 | ||
2877 | return insn; | |
2878 | } | |
2879 | ||
a05924f9 JH |
2880 | /* Similar to emit_insn_before, but update basic block boundaries as well. */ |
2881 | ||
2882 | rtx | |
2883 | emit_block_insn_before (pattern, before, block) | |
2884 | rtx pattern, before; | |
2885 | basic_block block; | |
2886 | { | |
2887 | rtx prev = PREV_INSN (before); | |
2888 | rtx r = emit_insn_before (pattern, before); | |
2889 | if (block && block->head == before) | |
2890 | block->head = NEXT_INSN (prev); | |
2891 | return r; | |
2892 | } | |
2893 | ||
23b2ce53 RS |
2894 | /* Make an instruction with body PATTERN and code JUMP_INSN |
2895 | and output it before the instruction BEFORE. */ | |
2896 | ||
2897 | rtx | |
2898 | emit_jump_insn_before (pattern, before) | |
2899 | register rtx pattern, before; | |
2900 | { | |
2901 | register rtx insn; | |
2902 | ||
2903 | if (GET_CODE (pattern) == SEQUENCE) | |
2904 | insn = emit_insn_before (pattern, before); | |
2905 | else | |
2906 | { | |
85cf32bc | 2907 | insn = make_jump_insn_raw (pattern); |
a0ae8e8d | 2908 | add_insn_before (insn, before); |
23b2ce53 RS |
2909 | } |
2910 | ||
2911 | return insn; | |
2912 | } | |
2913 | ||
2914 | /* Make an instruction with body PATTERN and code CALL_INSN | |
2915 | and output it before the instruction BEFORE. */ | |
2916 | ||
2917 | rtx | |
2918 | emit_call_insn_before (pattern, before) | |
2919 | register rtx pattern, before; | |
2920 | { | |
aff507f4 RK |
2921 | register rtx insn; |
2922 | ||
2923 | if (GET_CODE (pattern) == SEQUENCE) | |
2924 | insn = emit_insn_before (pattern, before); | |
2925 | else | |
2926 | { | |
2927 | insn = make_call_insn_raw (pattern); | |
a0ae8e8d | 2928 | add_insn_before (insn, before); |
aff507f4 RK |
2929 | PUT_CODE (insn, CALL_INSN); |
2930 | } | |
2931 | ||
23b2ce53 RS |
2932 | return insn; |
2933 | } | |
2934 | ||
2935 | /* Make an insn of code BARRIER | |
e881bb1b | 2936 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
2937 | |
2938 | rtx | |
2939 | emit_barrier_before (before) | |
2940 | register rtx before; | |
2941 | { | |
2942 | register rtx insn = rtx_alloc (BARRIER); | |
2943 | ||
2944 | INSN_UID (insn) = cur_insn_uid++; | |
2945 | ||
a0ae8e8d | 2946 | add_insn_before (insn, before); |
23b2ce53 RS |
2947 | return insn; |
2948 | } | |
2949 | ||
e881bb1b RH |
2950 | /* Emit the label LABEL before the insn BEFORE. */ |
2951 | ||
2952 | rtx | |
2953 | emit_label_before (label, before) | |
2954 | rtx label, before; | |
2955 | { | |
2956 | /* This can be called twice for the same label as a result of the | |
2957 | confusion that follows a syntax error! So make it harmless. */ | |
2958 | if (INSN_UID (label) == 0) | |
2959 | { | |
2960 | INSN_UID (label) = cur_insn_uid++; | |
2961 | add_insn_before (label, before); | |
2962 | } | |
2963 | ||
2964 | return label; | |
2965 | } | |
2966 | ||
23b2ce53 RS |
2967 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
2968 | ||
2969 | rtx | |
2970 | emit_note_before (subtype, before) | |
2971 | int subtype; | |
2972 | rtx before; | |
2973 | { | |
2974 | register rtx note = rtx_alloc (NOTE); | |
2975 | INSN_UID (note) = cur_insn_uid++; | |
2976 | NOTE_SOURCE_FILE (note) = 0; | |
2977 | NOTE_LINE_NUMBER (note) = subtype; | |
2978 | ||
a0ae8e8d | 2979 | add_insn_before (note, before); |
23b2ce53 RS |
2980 | return note; |
2981 | } | |
2982 | \f | |
2983 | /* Make an insn of code INSN with body PATTERN | |
2984 | and output it after the insn AFTER. */ | |
2985 | ||
2986 | rtx | |
2987 | emit_insn_after (pattern, after) | |
2988 | register rtx pattern, after; | |
2989 | { | |
2990 | register rtx insn = after; | |
2991 | ||
2992 | if (GET_CODE (pattern) == SEQUENCE) | |
2993 | { | |
2994 | register int i; | |
2995 | ||
2996 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2997 | { | |
2998 | insn = XVECEXP (pattern, 0, i); | |
2999 | add_insn_after (insn, after); | |
3000 | after = insn; | |
3001 | } | |
a3770a81 | 3002 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
3003 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
3004 | } | |
3005 | else | |
3006 | { | |
4b1f5e8c | 3007 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3008 | add_insn_after (insn, after); |
3009 | } | |
3010 | ||
3011 | return insn; | |
3012 | } | |
3013 | ||
255680cf RK |
3014 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
3015 | as to act as if this insn were at FROM. */ | |
3016 | ||
3017 | void | |
3018 | emit_insn_after_with_line_notes (pattern, after, from) | |
3019 | rtx pattern, after, from; | |
3020 | { | |
3021 | rtx from_line = find_line_note (from); | |
3022 | rtx after_line = find_line_note (after); | |
3023 | rtx insn = emit_insn_after (pattern, after); | |
3024 | ||
3025 | if (from_line) | |
3026 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3027 | NOTE_LINE_NUMBER (from_line), | |
3028 | after); | |
3029 | ||
3030 | if (after_line) | |
3031 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3032 | NOTE_LINE_NUMBER (after_line), | |
3033 | insn); | |
3034 | } | |
3035 | ||
a05924f9 JH |
3036 | /* Similar to emit_insn_after, but update basic block boundaries as well. */ |
3037 | ||
3038 | rtx | |
3039 | emit_block_insn_after (pattern, after, block) | |
3040 | rtx pattern, after; | |
3041 | basic_block block; | |
3042 | { | |
3043 | rtx r = emit_insn_after (pattern, after); | |
3044 | if (block && block->end == after) | |
3045 | block->end = r; | |
3046 | return r; | |
3047 | } | |
3048 | ||
23b2ce53 RS |
3049 | /* Make an insn of code JUMP_INSN with body PATTERN |
3050 | and output it after the insn AFTER. */ | |
3051 | ||
3052 | rtx | |
3053 | emit_jump_insn_after (pattern, after) | |
3054 | register rtx pattern, after; | |
3055 | { | |
3056 | register rtx insn; | |
3057 | ||
3058 | if (GET_CODE (pattern) == SEQUENCE) | |
3059 | insn = emit_insn_after (pattern, after); | |
3060 | else | |
3061 | { | |
85cf32bc | 3062 | insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3063 | add_insn_after (insn, after); |
3064 | } | |
3065 | ||
3066 | return insn; | |
3067 | } | |
3068 | ||
3069 | /* Make an insn of code BARRIER | |
3070 | and output it after the insn AFTER. */ | |
3071 | ||
3072 | rtx | |
3073 | emit_barrier_after (after) | |
3074 | register rtx after; | |
3075 | { | |
3076 | register rtx insn = rtx_alloc (BARRIER); | |
3077 | ||
3078 | INSN_UID (insn) = cur_insn_uid++; | |
3079 | ||
3080 | add_insn_after (insn, after); | |
3081 | return insn; | |
3082 | } | |
3083 | ||
3084 | /* Emit the label LABEL after the insn AFTER. */ | |
3085 | ||
3086 | rtx | |
3087 | emit_label_after (label, after) | |
3088 | rtx label, after; | |
3089 | { | |
3090 | /* This can be called twice for the same label | |
3091 | as a result of the confusion that follows a syntax error! | |
3092 | So make it harmless. */ | |
3093 | if (INSN_UID (label) == 0) | |
3094 | { | |
3095 | INSN_UID (label) = cur_insn_uid++; | |
3096 | add_insn_after (label, after); | |
3097 | } | |
3098 | ||
3099 | return label; | |
3100 | } | |
3101 | ||
3102 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3103 | ||
3104 | rtx | |
3105 | emit_note_after (subtype, after) | |
3106 | int subtype; | |
3107 | rtx after; | |
3108 | { | |
3109 | register rtx note = rtx_alloc (NOTE); | |
3110 | INSN_UID (note) = cur_insn_uid++; | |
3111 | NOTE_SOURCE_FILE (note) = 0; | |
3112 | NOTE_LINE_NUMBER (note) = subtype; | |
3113 | add_insn_after (note, after); | |
3114 | return note; | |
3115 | } | |
3116 | ||
3117 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3118 | ||
3119 | rtx | |
3120 | emit_line_note_after (file, line, after) | |
3cce094d | 3121 | const char *file; |
23b2ce53 RS |
3122 | int line; |
3123 | rtx after; | |
3124 | { | |
3125 | register rtx note; | |
3126 | ||
3127 | if (no_line_numbers && line > 0) | |
3128 | { | |
3129 | cur_insn_uid++; | |
3130 | return 0; | |
3131 | } | |
3132 | ||
3133 | note = rtx_alloc (NOTE); | |
3134 | INSN_UID (note) = cur_insn_uid++; | |
3135 | NOTE_SOURCE_FILE (note) = file; | |
3136 | NOTE_LINE_NUMBER (note) = line; | |
3137 | add_insn_after (note, after); | |
3138 | return note; | |
3139 | } | |
3140 | \f | |
3141 | /* Make an insn of code INSN with pattern PATTERN | |
3142 | and add it to the end of the doubly-linked list. | |
3143 | If PATTERN is a SEQUENCE, take the elements of it | |
3144 | and emit an insn for each element. | |
3145 | ||
3146 | Returns the last insn emitted. */ | |
3147 | ||
3148 | rtx | |
3149 | emit_insn (pattern) | |
3150 | rtx pattern; | |
3151 | { | |
3152 | rtx insn = last_insn; | |
3153 | ||
3154 | if (GET_CODE (pattern) == SEQUENCE) | |
3155 | { | |
3156 | register int i; | |
3157 | ||
3158 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3159 | { | |
3160 | insn = XVECEXP (pattern, 0, i); | |
3161 | add_insn (insn); | |
3162 | } | |
a3770a81 | 3163 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
3164 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
3165 | } | |
3166 | else | |
3167 | { | |
4b1f5e8c | 3168 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3169 | add_insn (insn); |
3170 | } | |
3171 | ||
3172 | return insn; | |
3173 | } | |
3174 | ||
3175 | /* Emit the insns in a chain starting with INSN. | |
3176 | Return the last insn emitted. */ | |
3177 | ||
3178 | rtx | |
3179 | emit_insns (insn) | |
3180 | rtx insn; | |
3181 | { | |
3182 | rtx last = 0; | |
3183 | ||
3184 | while (insn) | |
3185 | { | |
3186 | rtx next = NEXT_INSN (insn); | |
3187 | add_insn (insn); | |
3188 | last = insn; | |
3189 | insn = next; | |
3190 | } | |
3191 | ||
3192 | return last; | |
3193 | } | |
3194 | ||
3195 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3196 | the insn BEFORE. Return the last insn emitted. */ | |
3197 | ||
3198 | rtx | |
3199 | emit_insns_before (insn, before) | |
3200 | rtx insn; | |
3201 | rtx before; | |
3202 | { | |
3203 | rtx last = 0; | |
3204 | ||
3205 | while (insn) | |
3206 | { | |
3207 | rtx next = NEXT_INSN (insn); | |
a0ae8e8d | 3208 | add_insn_before (insn, before); |
23b2ce53 RS |
3209 | last = insn; |
3210 | insn = next; | |
3211 | } | |
3212 | ||
3213 | return last; | |
3214 | } | |
3215 | ||
e0a5c5eb RS |
3216 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3217 | the insn AFTER. Return the last insn emitted. */ | |
3218 | ||
3219 | rtx | |
3220 | emit_insns_after (first, after) | |
3221 | register rtx first; | |
3222 | register rtx after; | |
3223 | { | |
3224 | register rtx last; | |
3225 | register rtx after_after; | |
3226 | ||
3227 | if (!after) | |
3228 | abort (); | |
3229 | ||
3230 | if (!first) | |
3231 | return first; | |
3232 | ||
3233 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3234 | continue; | |
3235 | ||
3236 | after_after = NEXT_INSN (after); | |
3237 | ||
3238 | NEXT_INSN (after) = first; | |
3239 | PREV_INSN (first) = after; | |
3240 | NEXT_INSN (last) = after_after; | |
3241 | if (after_after) | |
3242 | PREV_INSN (after_after) = last; | |
3243 | ||
c4d990db RS |
3244 | if (after == last_insn) |
3245 | last_insn = last; | |
e0a5c5eb RS |
3246 | return last; |
3247 | } | |
3248 | ||
23b2ce53 RS |
3249 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3250 | and add it to the end of the doubly-linked list. */ | |
3251 | ||
3252 | rtx | |
3253 | emit_jump_insn (pattern) | |
3254 | rtx pattern; | |
3255 | { | |
3256 | if (GET_CODE (pattern) == SEQUENCE) | |
3257 | return emit_insn (pattern); | |
3258 | else | |
3259 | { | |
85cf32bc | 3260 | register rtx insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3261 | add_insn (insn); |
3262 | return insn; | |
3263 | } | |
3264 | } | |
3265 | ||
3266 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3267 | and add it to the end of the doubly-linked list. */ | |
3268 | ||
3269 | rtx | |
3270 | emit_call_insn (pattern) | |
3271 | rtx pattern; | |
3272 | { | |
3273 | if (GET_CODE (pattern) == SEQUENCE) | |
3274 | return emit_insn (pattern); | |
3275 | else | |
3276 | { | |
aff507f4 | 3277 | register rtx insn = make_call_insn_raw (pattern); |
23b2ce53 RS |
3278 | add_insn (insn); |
3279 | PUT_CODE (insn, CALL_INSN); | |
3280 | return insn; | |
3281 | } | |
3282 | } | |
3283 | ||
3284 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3285 | ||
3286 | rtx | |
3287 | emit_label (label) | |
3288 | rtx label; | |
3289 | { | |
3290 | /* This can be called twice for the same label | |
3291 | as a result of the confusion that follows a syntax error! | |
3292 | So make it harmless. */ | |
3293 | if (INSN_UID (label) == 0) | |
3294 | { | |
3295 | INSN_UID (label) = cur_insn_uid++; | |
3296 | add_insn (label); | |
3297 | } | |
3298 | return label; | |
3299 | } | |
3300 | ||
3301 | /* Make an insn of code BARRIER | |
3302 | and add it to the end of the doubly-linked list. */ | |
3303 | ||
3304 | rtx | |
3305 | emit_barrier () | |
3306 | { | |
3307 | register rtx barrier = rtx_alloc (BARRIER); | |
3308 | INSN_UID (barrier) = cur_insn_uid++; | |
3309 | add_insn (barrier); | |
3310 | return barrier; | |
3311 | } | |
3312 | ||
3313 | /* Make an insn of code NOTE | |
3314 | with data-fields specified by FILE and LINE | |
3315 | and add it to the end of the doubly-linked list, | |
3316 | but only if line-numbers are desired for debugging info. */ | |
3317 | ||
3318 | rtx | |
3319 | emit_line_note (file, line) | |
3cce094d | 3320 | const char *file; |
23b2ce53 RS |
3321 | int line; |
3322 | { | |
3f1d071b | 3323 | set_file_and_line_for_stmt (file, line); |
23b2ce53 RS |
3324 | |
3325 | #if 0 | |
3326 | if (no_line_numbers) | |
3327 | return 0; | |
3328 | #endif | |
3329 | ||
3330 | return emit_note (file, line); | |
3331 | } | |
3332 | ||
3333 | /* Make an insn of code NOTE | |
3334 | with data-fields specified by FILE and LINE | |
3335 | and add it to the end of the doubly-linked list. | |
3336 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3337 | ||
3338 | rtx | |
3339 | emit_note (file, line) | |
3cce094d | 3340 | const char *file; |
23b2ce53 RS |
3341 | int line; |
3342 | { | |
3343 | register rtx note; | |
3344 | ||
3345 | if (line > 0) | |
3346 | { | |
3347 | if (file && last_filename && !strcmp (file, last_filename) | |
3348 | && line == last_linenum) | |
3349 | return 0; | |
3350 | last_filename = file; | |
3351 | last_linenum = line; | |
3352 | } | |
3353 | ||
3354 | if (no_line_numbers && line > 0) | |
3355 | { | |
3356 | cur_insn_uid++; | |
3357 | return 0; | |
3358 | } | |
3359 | ||
3360 | note = rtx_alloc (NOTE); | |
3361 | INSN_UID (note) = cur_insn_uid++; | |
3362 | NOTE_SOURCE_FILE (note) = file; | |
3363 | NOTE_LINE_NUMBER (note) = line; | |
3364 | add_insn (note); | |
3365 | return note; | |
3366 | } | |
3367 | ||
fe77a034 | 3368 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
23b2ce53 RS |
3369 | |
3370 | rtx | |
3371 | emit_line_note_force (file, line) | |
3cce094d | 3372 | const char *file; |
23b2ce53 RS |
3373 | int line; |
3374 | { | |
3375 | last_linenum = -1; | |
3376 | return emit_line_note (file, line); | |
3377 | } | |
3378 | ||
3379 | /* Cause next statement to emit a line note even if the line number | |
3380 | has not changed. This is used at the beginning of a function. */ | |
3381 | ||
3382 | void | |
3383 | force_next_line_note () | |
3384 | { | |
3385 | last_linenum = -1; | |
3386 | } | |
87b47c85 AM |
3387 | |
3388 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
3389 | note of this type already exists, remove it first. */ | |
3390 | ||
3391 | void | |
3392 | set_unique_reg_note (insn, kind, datum) | |
3393 | rtx insn; | |
3394 | enum reg_note kind; | |
3395 | rtx datum; | |
3396 | { | |
3397 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3398 | ||
3399 | /* First remove the note if there already is one. */ | |
3400 | if (note) | |
3401 | remove_note (insn, note); | |
3402 | ||
3403 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3404 | } | |
23b2ce53 RS |
3405 | \f |
3406 | /* Return an indication of which type of insn should have X as a body. | |
3407 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3408 | ||
3409 | enum rtx_code | |
3410 | classify_insn (x) | |
3411 | rtx x; | |
3412 | { | |
3413 | if (GET_CODE (x) == CODE_LABEL) | |
3414 | return CODE_LABEL; | |
3415 | if (GET_CODE (x) == CALL) | |
3416 | return CALL_INSN; | |
3417 | if (GET_CODE (x) == RETURN) | |
3418 | return JUMP_INSN; | |
3419 | if (GET_CODE (x) == SET) | |
3420 | { | |
3421 | if (SET_DEST (x) == pc_rtx) | |
3422 | return JUMP_INSN; | |
3423 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3424 | return CALL_INSN; | |
3425 | else | |
3426 | return INSN; | |
3427 | } | |
3428 | if (GET_CODE (x) == PARALLEL) | |
3429 | { | |
3430 | register int j; | |
3431 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3432 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3433 | return CALL_INSN; | |
3434 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3435 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3436 | return JUMP_INSN; | |
3437 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3438 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3439 | return CALL_INSN; | |
3440 | } | |
3441 | return INSN; | |
3442 | } | |
3443 | ||
3444 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3445 | If X is a label, it is simply added into the insn chain. */ | |
3446 | ||
3447 | rtx | |
3448 | emit (x) | |
3449 | rtx x; | |
3450 | { | |
3451 | enum rtx_code code = classify_insn (x); | |
3452 | ||
3453 | if (code == CODE_LABEL) | |
3454 | return emit_label (x); | |
3455 | else if (code == INSN) | |
3456 | return emit_insn (x); | |
3457 | else if (code == JUMP_INSN) | |
3458 | { | |
3459 | register rtx insn = emit_jump_insn (x); | |
7f1c097d | 3460 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
23b2ce53 RS |
3461 | return emit_barrier (); |
3462 | return insn; | |
3463 | } | |
3464 | else if (code == CALL_INSN) | |
3465 | return emit_call_insn (x); | |
3466 | else | |
3467 | abort (); | |
3468 | } | |
3469 | \f | |
5c7a310f MM |
3470 | /* Begin emitting insns to a sequence which can be packaged in an |
3471 | RTL_EXPR. If this sequence will contain something that might cause | |
3472 | the compiler to pop arguments to function calls (because those | |
3473 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3474 | details), use do_pending_stack_adjust before calling this function. | |
3475 | That will ensure that the deferred pops are not accidentally | |
3476 | emitted in the middel of this sequence. */ | |
23b2ce53 RS |
3477 | |
3478 | void | |
3479 | start_sequence () | |
3480 | { | |
3481 | struct sequence_stack *tem; | |
3482 | ||
a3770a81 | 3483 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
23b2ce53 | 3484 | |
49ad7cfa | 3485 | tem->next = seq_stack; |
23b2ce53 RS |
3486 | tem->first = first_insn; |
3487 | tem->last = last_insn; | |
591ccf92 | 3488 | tem->sequence_rtl_expr = seq_rtl_expr; |
23b2ce53 | 3489 | |
49ad7cfa | 3490 | seq_stack = tem; |
23b2ce53 RS |
3491 | |
3492 | first_insn = 0; | |
3493 | last_insn = 0; | |
3494 | } | |
3495 | ||
591ccf92 MM |
3496 | /* Similarly, but indicate that this sequence will be placed in T, an |
3497 | RTL_EXPR. See the documentation for start_sequence for more | |
3498 | information about how to use this function. */ | |
3499 | ||
3500 | void | |
3501 | start_sequence_for_rtl_expr (t) | |
3502 | tree t; | |
3503 | { | |
3504 | start_sequence (); | |
3505 | ||
3506 | seq_rtl_expr = t; | |
3507 | } | |
3508 | ||
5c7a310f MM |
3509 | /* Set up the insn chain starting with FIRST as the current sequence, |
3510 | saving the previously current one. See the documentation for | |
3511 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
3512 | |
3513 | void | |
3514 | push_to_sequence (first) | |
3515 | rtx first; | |
3516 | { | |
3517 | rtx last; | |
3518 | ||
3519 | start_sequence (); | |
3520 | ||
3521 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3522 | ||
3523 | first_insn = first; | |
3524 | last_insn = last; | |
3525 | } | |
3526 | ||
c14f7160 ML |
3527 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3528 | ||
3529 | void | |
3530 | push_to_full_sequence (first, last) | |
3531 | rtx first, last; | |
3532 | { | |
3533 | start_sequence (); | |
3534 | first_insn = first; | |
3535 | last_insn = last; | |
3536 | /* We really should have the end of the insn chain here. */ | |
3537 | if (last && NEXT_INSN (last)) | |
3538 | abort (); | |
3539 | } | |
3540 | ||
f15ae3a1 TW |
3541 | /* Set up the outer-level insn chain |
3542 | as the current sequence, saving the previously current one. */ | |
3543 | ||
3544 | void | |
3545 | push_topmost_sequence () | |
3546 | { | |
aefdd5ab | 3547 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
3548 | |
3549 | start_sequence (); | |
3550 | ||
49ad7cfa | 3551 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3552 | top = stack; |
3553 | ||
3554 | first_insn = top->first; | |
3555 | last_insn = top->last; | |
591ccf92 | 3556 | seq_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
3557 | } |
3558 | ||
3559 | /* After emitting to the outer-level insn chain, update the outer-level | |
3560 | insn chain, and restore the previous saved state. */ | |
3561 | ||
3562 | void | |
3563 | pop_topmost_sequence () | |
3564 | { | |
aefdd5ab | 3565 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 3566 | |
49ad7cfa | 3567 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3568 | top = stack; |
3569 | ||
3570 | top->first = first_insn; | |
3571 | top->last = last_insn; | |
591ccf92 | 3572 | /* ??? Why don't we save seq_rtl_expr here? */ |
f15ae3a1 TW |
3573 | |
3574 | end_sequence (); | |
3575 | } | |
3576 | ||
23b2ce53 RS |
3577 | /* After emitting to a sequence, restore previous saved state. |
3578 | ||
5c7a310f MM |
3579 | To get the contents of the sequence just made, you must call |
3580 | `gen_sequence' *before* calling here. | |
3581 | ||
3582 | If the compiler might have deferred popping arguments while | |
3583 | generating this sequence, and this sequence will not be immediately | |
3584 | inserted into the instruction stream, use do_pending_stack_adjust | |
3585 | before calling gen_sequence. That will ensure that the deferred | |
3586 | pops are inserted into this sequence, and not into some random | |
3587 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3588 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
3589 | |
3590 | void | |
3591 | end_sequence () | |
3592 | { | |
49ad7cfa | 3593 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
3594 | |
3595 | first_insn = tem->first; | |
3596 | last_insn = tem->last; | |
591ccf92 | 3597 | seq_rtl_expr = tem->sequence_rtl_expr; |
49ad7cfa | 3598 | seq_stack = tem->next; |
23b2ce53 | 3599 | |
a3770a81 | 3600 | free (tem); |
23b2ce53 RS |
3601 | } |
3602 | ||
c14f7160 ML |
3603 | /* This works like end_sequence, but records the old sequence in FIRST |
3604 | and LAST. */ | |
3605 | ||
3606 | void | |
3607 | end_full_sequence (first, last) | |
3608 | rtx *first, *last; | |
3609 | { | |
3610 | *first = first_insn; | |
3611 | *last = last_insn; | |
3612 | end_sequence(); | |
3613 | } | |
3614 | ||
23b2ce53 RS |
3615 | /* Return 1 if currently emitting into a sequence. */ |
3616 | ||
3617 | int | |
3618 | in_sequence_p () | |
3619 | { | |
49ad7cfa | 3620 | return seq_stack != 0; |
23b2ce53 RS |
3621 | } |
3622 | ||
3623 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3624 | to the current sequence. | |
3625 | ||
3626 | This is how the gen_... function from a DEFINE_EXPAND | |
3627 | constructs the SEQUENCE that it returns. */ | |
3628 | ||
3629 | rtx | |
3630 | gen_sequence () | |
3631 | { | |
3632 | rtx result; | |
3633 | rtx tem; | |
23b2ce53 RS |
3634 | int i; |
3635 | int len; | |
3636 | ||
3637 | /* Count the insns in the chain. */ | |
3638 | len = 0; | |
3639 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3640 | len++; | |
3641 | ||
ee265800 | 3642 | /* If only one insn, return it rather than a SEQUENCE. |
23b2ce53 | 3643 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
ee265800 AH |
3644 | the case of an empty list.) |
3645 | We only return the pattern of an insn if its code is INSN and it | |
3646 | has no notes. This ensures that no information gets lost. */ | |
23b2ce53 | 3647 | if (len == 1 |
ca55abae | 3648 | && ! RTX_FRAME_RELATED_P (first_insn) |
ee265800 AH |
3649 | && GET_CODE (first_insn) == INSN |
3650 | /* Don't throw away any reg notes. */ | |
3651 | && REG_NOTES (first_insn) == 0) | |
43127294 | 3652 | { |
a3770a81 RH |
3653 | if (!ggc_p) |
3654 | { | |
3655 | NEXT_INSN (first_insn) = free_insn; | |
3656 | free_insn = first_insn; | |
3657 | } | |
43127294 RK |
3658 | return PATTERN (first_insn); |
3659 | } | |
23b2ce53 RS |
3660 | |
3661 | /* Put them in a vector. See if we already have a SEQUENCE of the | |
3662 | appropriate length around. */ | |
a3770a81 RH |
3663 | if (!ggc_p && len < SEQUENCE_RESULT_SIZE |
3664 | && (result = sequence_result[len]) != 0) | |
23b2ce53 RS |
3665 | sequence_result[len] = 0; |
3666 | else | |
3667 | { | |
9faa82d8 RK |
3668 | /* Ensure that this rtl goes in saveable_obstack, since we may |
3669 | cache it. */ | |
d508ebba JW |
3670 | push_obstacks_nochange (); |
3671 | rtl_in_saveable_obstack (); | |
3b80f6ca | 3672 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
d508ebba | 3673 | pop_obstacks (); |
23b2ce53 RS |
3674 | } |
3675 | ||
3676 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3677 | XVECEXP (result, 0, i) = tem; | |
3678 | ||
3679 | return result; | |
3680 | } | |
3681 | \f | |
59ec66dc MM |
3682 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3683 | ||
3684 | void | |
49ad7cfa BS |
3685 | init_virtual_regs (es) |
3686 | struct emit_status *es; | |
59ec66dc | 3687 | { |
49ad7cfa BS |
3688 | rtx *ptr = es->x_regno_reg_rtx; |
3689 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3690 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3691 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3692 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3693 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3694 | } | |
3695 | ||
3696 | void | |
3697 | clear_emit_caches () | |
3698 | { | |
3699 | int i; | |
3700 | ||
3701 | /* Clear the start_sequence/gen_sequence cache. */ | |
49ad7cfa BS |
3702 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3703 | sequence_result[i] = 0; | |
3704 | free_insn = 0; | |
59ec66dc | 3705 | } |
da43a810 BS |
3706 | \f |
3707 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3708 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3709 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3710 | static int copy_insn_n_scratches; | |
3711 | ||
3712 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3713 | copied an ASM_OPERANDS. | |
3714 | In that case, it is the original input-operand vector. */ | |
3715 | static rtvec orig_asm_operands_vector; | |
3716 | ||
3717 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3718 | copied an ASM_OPERANDS. | |
3719 | In that case, it is the copied input-operand vector. */ | |
3720 | static rtvec copy_asm_operands_vector; | |
3721 | ||
3722 | /* Likewise for the constraints vector. */ | |
3723 | static rtvec orig_asm_constraints_vector; | |
3724 | static rtvec copy_asm_constraints_vector; | |
3725 | ||
3726 | /* Recursively create a new copy of an rtx for copy_insn. | |
3727 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3728 | ASM_OPERANDs properly. | |
3729 | Normally, this function is not used directly; use copy_insn as front end. | |
3730 | However, you could first copy an insn pattern with copy_insn and then use | |
3731 | this function afterwards to properly copy any REG_NOTEs containing | |
3732 | SCRATCHes. */ | |
3733 | ||
3734 | rtx | |
3735 | copy_insn_1 (orig) | |
3736 | register rtx orig; | |
3737 | { | |
3738 | register rtx copy; | |
3739 | register int i, j; | |
3740 | register RTX_CODE code; | |
4724334a | 3741 | register const char *format_ptr; |
da43a810 BS |
3742 | |
3743 | code = GET_CODE (orig); | |
3744 | ||
3745 | switch (code) | |
3746 | { | |
3747 | case REG: | |
3748 | case QUEUED: | |
3749 | case CONST_INT: | |
3750 | case CONST_DOUBLE: | |
3751 | case SYMBOL_REF: | |
3752 | case CODE_LABEL: | |
3753 | case PC: | |
3754 | case CC0: | |
3755 | case ADDRESSOF: | |
3756 | return orig; | |
3757 | ||
3758 | case SCRATCH: | |
3759 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3760 | if (copy_insn_scratch_in[i] == orig) | |
3761 | return copy_insn_scratch_out[i]; | |
3762 | break; | |
3763 | ||
3764 | case CONST: | |
3765 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
3766 | a LABEL_REF, it isn't sharable. */ | |
3767 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3768 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
3769 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
3770 | return orig; | |
3771 | break; | |
3772 | ||
3773 | /* A MEM with a constant address is not sharable. The problem is that | |
3774 | the constant address may need to be reloaded. If the mem is shared, | |
3775 | then reloading one copy of this mem will cause all copies to appear | |
3776 | to have been reloaded. */ | |
3777 | ||
3778 | default: | |
3779 | break; | |
3780 | } | |
3781 | ||
3782 | copy = rtx_alloc (code); | |
3783 | ||
3784 | /* Copy the various flags, and other information. We assume that | |
3785 | all fields need copying, and then clear the fields that should | |
3786 | not be copied. That is the sensible default behavior, and forces | |
3787 | us to explicitly document why we are *not* copying a flag. */ | |
3788 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
3789 | ||
3790 | /* We do not copy the USED flag, which is used as a mark bit during | |
3791 | walks over the RTL. */ | |
3792 | copy->used = 0; | |
3793 | ||
3794 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
3795 | if (GET_RTX_CLASS (code) == 'i') | |
3796 | { | |
3797 | copy->jump = 0; | |
3798 | copy->call = 0; | |
3799 | copy->frame_related = 0; | |
3800 | } | |
3801 | ||
3802 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
3803 | ||
3804 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
3805 | { | |
e63db8f6 | 3806 | copy->fld[i] = orig->fld[i]; |
da43a810 BS |
3807 | switch (*format_ptr++) |
3808 | { | |
3809 | case 'e': | |
da43a810 BS |
3810 | if (XEXP (orig, i) != NULL) |
3811 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
3812 | break; | |
3813 | ||
da43a810 BS |
3814 | case 'E': |
3815 | case 'V': | |
da43a810 BS |
3816 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
3817 | XVEC (copy, i) = copy_asm_constraints_vector; | |
3818 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
3819 | XVEC (copy, i) = copy_asm_operands_vector; | |
3820 | else if (XVEC (orig, i) != NULL) | |
3821 | { | |
3822 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
3823 | for (j = 0; j < XVECLEN (copy, i); j++) | |
3824 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
3825 | } | |
3826 | break; | |
3827 | ||
3828 | case 'b': | |
3829 | { | |
3830 | bitmap new_bits = BITMAP_OBSTACK_ALLOC (rtl_obstack); | |
3831 | bitmap_copy (new_bits, XBITMAP (orig, i)); | |
3832 | XBITMAP (copy, i) = new_bits; | |
3833 | break; | |
3834 | } | |
3835 | ||
3836 | case 't': | |
da43a810 | 3837 | case 'w': |
da43a810 | 3838 | case 'i': |
da43a810 BS |
3839 | case 's': |
3840 | case 'S': | |
e63db8f6 BS |
3841 | case 'u': |
3842 | case '0': | |
3843 | /* These are left unchanged. */ | |
da43a810 BS |
3844 | break; |
3845 | ||
3846 | default: | |
3847 | abort (); | |
3848 | } | |
3849 | } | |
3850 | ||
3851 | if (code == SCRATCH) | |
3852 | { | |
3853 | i = copy_insn_n_scratches++; | |
3854 | if (i >= MAX_RECOG_OPERANDS) | |
3855 | abort (); | |
3856 | copy_insn_scratch_in[i] = orig; | |
3857 | copy_insn_scratch_out[i] = copy; | |
3858 | } | |
3859 | else if (code == ASM_OPERANDS) | |
3860 | { | |
3861 | orig_asm_operands_vector = XVEC (orig, 3); | |
3862 | copy_asm_operands_vector = XVEC (copy, 3); | |
3863 | orig_asm_constraints_vector = XVEC (orig, 4); | |
3864 | copy_asm_constraints_vector = XVEC (copy, 4); | |
3865 | } | |
3866 | ||
3867 | return copy; | |
3868 | } | |
3869 | ||
3870 | /* Create a new copy of an rtx. | |
3871 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3872 | ASM_OPERANDs properly. | |
3873 | INSN doesn't really have to be a full INSN; it could be just the | |
3874 | pattern. */ | |
3875 | rtx | |
3876 | copy_insn (insn) | |
3877 | rtx insn; | |
3878 | { | |
3879 | copy_insn_n_scratches = 0; | |
3880 | orig_asm_operands_vector = 0; | |
3881 | orig_asm_constraints_vector = 0; | |
3882 | copy_asm_operands_vector = 0; | |
3883 | copy_asm_constraints_vector = 0; | |
3884 | return copy_insn_1 (insn); | |
3885 | } | |
59ec66dc | 3886 | |
23b2ce53 RS |
3887 | /* Initialize data structures and variables in this file |
3888 | before generating rtl for each function. */ | |
3889 | ||
3890 | void | |
3891 | init_emit () | |
3892 | { | |
01d939e8 | 3893 | struct function *f = cfun; |
23b2ce53 | 3894 | |
49ad7cfa | 3895 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
23b2ce53 RS |
3896 | first_insn = NULL; |
3897 | last_insn = NULL; | |
591ccf92 | 3898 | seq_rtl_expr = NULL; |
23b2ce53 RS |
3899 | cur_insn_uid = 1; |
3900 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
3901 | last_linenum = 0; | |
3902 | last_filename = 0; | |
3903 | first_label_num = label_num; | |
3904 | last_label_num = 0; | |
49ad7cfa | 3905 | seq_stack = NULL; |
23b2ce53 | 3906 | |
49ad7cfa | 3907 | clear_emit_caches (); |
23b2ce53 RS |
3908 | |
3909 | /* Init the tables that describe all the pseudo regs. */ | |
3910 | ||
49ad7cfa | 3911 | f->emit->regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 3912 | |
49ad7cfa | 3913 | f->emit->regno_pointer_flag |
a3770a81 | 3914 | = (char *) xcalloc (f->emit->regno_pointer_flag_length, sizeof (char)); |
23b2ce53 | 3915 | |
49ad7cfa | 3916 | f->emit->regno_pointer_align |
f9e158c3 JM |
3917 | = (unsigned char *) xcalloc (f->emit->regno_pointer_flag_length, |
3918 | sizeof (unsigned char)); | |
86fe05e0 | 3919 | |
23b2ce53 | 3920 | regno_reg_rtx |
a3770a81 RH |
3921 | = (rtx *) xcalloc (f->emit->regno_pointer_flag_length * sizeof (rtx), |
3922 | sizeof (rtx)); | |
23b2ce53 RS |
3923 | |
3924 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
49ad7cfa | 3925 | init_virtual_regs (f->emit); |
740ab4a2 RK |
3926 | |
3927 | /* Indicate that the virtual registers and stack locations are | |
3928 | all pointers. */ | |
3929 | REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1; | |
3930 | REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1; | |
15c9248c | 3931 | REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1; |
740ab4a2 RK |
3932 | REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1; |
3933 | ||
3934 | REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1; | |
3935 | REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1; | |
3936 | REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1; | |
3937 | REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1; | |
71038426 | 3938 | REGNO_POINTER_FLAG (VIRTUAL_CFA_REGNUM) = 1; |
5e82e7bd | 3939 | |
86fe05e0 | 3940 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
3941 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
3942 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
3943 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
3944 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
3945 | ||
3946 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
3947 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
3948 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
3949 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
3950 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
3951 | #endif |
3952 | ||
5e82e7bd JVA |
3953 | #ifdef INIT_EXPANDERS |
3954 | INIT_EXPANDERS; | |
3955 | #endif | |
23b2ce53 RS |
3956 | } |
3957 | ||
87ff9c8e RH |
3958 | /* Mark SS for GC. */ |
3959 | ||
3960 | static void | |
3961 | mark_sequence_stack (ss) | |
3962 | struct sequence_stack *ss; | |
3963 | { | |
3964 | while (ss) | |
3965 | { | |
3966 | ggc_mark_rtx (ss->first); | |
591ccf92 | 3967 | ggc_mark_tree (ss->sequence_rtl_expr); |
87ff9c8e RH |
3968 | ss = ss->next; |
3969 | } | |
3970 | } | |
3971 | ||
3972 | /* Mark ES for GC. */ | |
3973 | ||
3974 | void | |
fa51b01b | 3975 | mark_emit_status (es) |
87ff9c8e RH |
3976 | struct emit_status *es; |
3977 | { | |
3978 | rtx *r; | |
3979 | int i; | |
3980 | ||
3981 | if (es == 0) | |
3982 | return; | |
3983 | ||
3984 | for (i = es->regno_pointer_flag_length, r = es->x_regno_reg_rtx; | |
3985 | i > 0; --i, ++r) | |
3986 | ggc_mark_rtx (*r); | |
3987 | ||
3988 | mark_sequence_stack (es->sequence_stack); | |
591ccf92 | 3989 | ggc_mark_tree (es->sequence_rtl_expr); |
87ff9c8e RH |
3990 | ggc_mark_rtx (es->x_first_insn); |
3991 | } | |
3992 | ||
23b2ce53 RS |
3993 | /* Create some permanent unique rtl objects shared between all functions. |
3994 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
3995 | ||
3996 | void | |
3997 | init_emit_once (line_numbers) | |
3998 | int line_numbers; | |
3999 | { | |
4000 | int i; | |
4001 | enum machine_mode mode; | |
9ec36da5 | 4002 | enum machine_mode double_mode; |
23b2ce53 RS |
4003 | |
4004 | no_line_numbers = ! line_numbers; | |
4005 | ||
43fa6302 AS |
4006 | /* Compute the word and byte modes. */ |
4007 | ||
4008 | byte_mode = VOIDmode; | |
4009 | word_mode = VOIDmode; | |
4010 | double_mode = VOIDmode; | |
4011 | ||
4012 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4013 | mode = GET_MODE_WIDER_MODE (mode)) | |
4014 | { | |
4015 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
4016 | && byte_mode == VOIDmode) | |
4017 | byte_mode = mode; | |
4018 | ||
4019 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
4020 | && word_mode == VOIDmode) | |
4021 | word_mode = mode; | |
4022 | } | |
4023 | ||
4024 | #ifndef DOUBLE_TYPE_SIZE | |
4025 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
4026 | #endif | |
4027 | ||
4028 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4029 | mode = GET_MODE_WIDER_MODE (mode)) | |
4030 | { | |
4031 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
4032 | && double_mode == VOIDmode) | |
4033 | double_mode = mode; | |
4034 | } | |
4035 | ||
4036 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
4037 | ||
5da077de AS |
4038 | /* Assign register numbers to the globally defined register rtx. |
4039 | This must be done at runtime because the register number field | |
4040 | is in a union and some compilers can't initialize unions. */ | |
4041 | ||
4042 | pc_rtx = gen_rtx (PC, VOIDmode); | |
4043 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
4044 | stack_pointer_rtx = gen_rtx_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
4045 | frame_pointer_rtx = gen_rtx_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
4046 | if (hard_frame_pointer_rtx == 0) | |
4047 | hard_frame_pointer_rtx = gen_rtx_raw_REG (Pmode, | |
4048 | HARD_FRAME_POINTER_REGNUM); | |
4049 | if (arg_pointer_rtx == 0) | |
4050 | arg_pointer_rtx = gen_rtx_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
4051 | virtual_incoming_args_rtx = | |
4052 | gen_rtx_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
4053 | virtual_stack_vars_rtx = | |
4054 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
4055 | virtual_stack_dynamic_rtx = | |
4056 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
4057 | virtual_outgoing_args_rtx = | |
4058 | gen_rtx_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
4059 | virtual_cfa_rtx = gen_rtx_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
4060 | ||
4061 | /* These rtx must be roots if GC is enabled. */ | |
4062 | if (ggc_p) | |
4063 | ggc_add_rtx_root (global_rtl, GR_MAX); | |
4064 | ||
5da077de AS |
4065 | #ifdef INIT_EXPANDERS |
4066 | /* This is to initialize save_machine_status and restore_machine_status before | |
4067 | the first call to push_function_context_to. This is needed by the Chill | |
4068 | front end which calls push_function_context_to before the first cal to | |
4069 | init_function_start. */ | |
4070 | INIT_EXPANDERS; | |
4071 | #endif | |
4072 | ||
23b2ce53 RS |
4073 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
4074 | ||
c5c76735 JL |
4075 | /* Don't use gen_rtx here since gen_rtx in this case |
4076 | tries to use these variables. */ | |
23b2ce53 | 4077 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
5da077de AS |
4078 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
4079 | gen_rtx_raw_CONST_INT (VOIDmode, i); | |
4080 | if (ggc_p) | |
4081 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); | |
23b2ce53 | 4082 | |
68d75312 JC |
4083 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
4084 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 4085 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 4086 | else |
3b80f6ca | 4087 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 4088 | |
9ec36da5 JL |
4089 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
4090 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
4091 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
4092 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
23b2ce53 RS |
4093 | |
4094 | for (i = 0; i <= 2; i++) | |
4095 | { | |
4096 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4097 | mode = GET_MODE_WIDER_MODE (mode)) | |
4098 | { | |
4099 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4100 | union real_extract u; | |
4101 | ||
4c9a05bc | 4102 | bzero ((char *) &u, sizeof u); /* Zero any holes in a structure. */ |
23b2ce53 RS |
4103 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4104 | ||
4c9a05bc | 4105 | bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u); |
23b2ce53 RS |
4106 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
4107 | PUT_MODE (tem, mode); | |
4108 | ||
4109 | const_tiny_rtx[i][(int) mode] = tem; | |
4110 | } | |
4111 | ||
906c4e36 | 4112 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
4113 | |
4114 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4115 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 4116 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
4117 | |
4118 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4119 | mode != VOIDmode; | |
4120 | mode = GET_MODE_WIDER_MODE (mode)) | |
4121 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
4122 | } |
4123 | ||
aea87e88 RH |
4124 | for (mode = CCmode; mode < MAX_MACHINE_MODE; ++mode) |
4125 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
4126 | const_tiny_rtx[0][(int) mode] = const0_rtx; | |
23b2ce53 | 4127 | |
d7db6646 | 4128 | ggc_add_rtx_root (&const_tiny_rtx[0][0], sizeof(const_tiny_rtx)/sizeof(rtx)); |
21cd906e | 4129 | ggc_add_rtx_root (&const_true_rtx, 1); |
a7e1e2ac AO |
4130 | |
4131 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4132 | return_address_pointer_rtx | |
4133 | = gen_rtx_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
4134 | #endif | |
4135 | ||
4136 | #ifdef STRUCT_VALUE | |
4137 | struct_value_rtx = STRUCT_VALUE; | |
4138 | #else | |
4139 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4140 | #endif | |
4141 | ||
4142 | #ifdef STRUCT_VALUE_INCOMING | |
4143 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4144 | #else | |
4145 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4146 | struct_value_incoming_rtx | |
4147 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4148 | #else | |
4149 | struct_value_incoming_rtx = struct_value_rtx; | |
4150 | #endif | |
4151 | #endif | |
4152 | ||
4153 | #ifdef STATIC_CHAIN_REGNUM | |
4154 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4155 | ||
4156 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4157 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4158 | static_chain_incoming_rtx | |
4159 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4160 | else | |
4161 | #endif | |
4162 | static_chain_incoming_rtx = static_chain_rtx; | |
4163 | #endif | |
4164 | ||
4165 | #ifdef STATIC_CHAIN | |
4166 | static_chain_rtx = STATIC_CHAIN; | |
4167 | ||
4168 | #ifdef STATIC_CHAIN_INCOMING | |
4169 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4170 | #else | |
4171 | static_chain_incoming_rtx = static_chain_rtx; | |
4172 | #endif | |
4173 | #endif | |
4174 | ||
4175 | #ifdef PIC_OFFSET_TABLE_REGNUM | |
4176 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
4177 | #endif | |
4178 | ||
d7db6646 RH |
4179 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4180 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4181 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4182 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4183 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4184 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
c13e8210 MM |
4185 | |
4186 | /* Initialize the CONST_INT hash table. */ | |
29105cea RK |
4187 | const_int_htab = htab_create (37, const_int_htab_hash, |
4188 | const_int_htab_eq, NULL); | |
c13e8210 MM |
4189 | ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab), |
4190 | rtx_htab_mark); | |
23b2ce53 | 4191 | } |
a11759a3 JR |
4192 | \f |
4193 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4194 | switch / case handling in stmt.c to give proper line numbers in | |
4195 | warnings about unreachable code. */ | |
4196 | ||
4197 | int | |
4198 | force_line_numbers () | |
4199 | { | |
4200 | int old = no_line_numbers; | |
4201 | ||
4202 | no_line_numbers = 0; | |
4203 | if (old) | |
4204 | force_next_line_note (); | |
4205 | return old; | |
4206 | } | |
4207 | ||
4208 | void | |
4209 | restore_line_number_status (old_value) | |
4210 | int old_value; | |
4211 | { | |
4212 | no_line_numbers = old_value; | |
4213 | } |