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23b2ce53 | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
90a74703 | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
23b2ce53 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
670ee920 | 39 | #include "system.h" |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
ca695ac9 | 53 | #include "obstack.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
ca695ac9 | 57 | |
1d445e9e ILT |
58 | /* Commonly used modes. */ |
59 | ||
0f41302f MS |
60 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
61 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 62 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 63 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 64 | |
23b2ce53 RS |
65 | |
66 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
67 | in the entire compilation a unique label number. */ | |
68 | ||
69 | static int label_num = 1; | |
70 | ||
23b2ce53 RS |
71 | /* Highest label number in current function. |
72 | Zero means use the value of label_num instead. | |
73 | This is nonzero only when belatedly compiling an inline function. */ | |
74 | ||
75 | static int last_label_num; | |
76 | ||
77 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
78 | If label_num has not changed since then, last_label_num is valid. */ | |
79 | ||
80 | static int base_label_num; | |
81 | ||
82 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
83 | ||
84 | static int no_line_numbers; | |
85 | ||
86 | /* Commonly used rtx's, so that we only need space for one copy. | |
87 | These are initialized once for the entire compilation. | |
88 | All of these except perhaps the floating-point CONST_DOUBLEs | |
89 | are unique; no other rtx-object will be equal to any of these. */ | |
90 | ||
5da077de | 91 | rtx global_rtl[GR_MAX]; |
23b2ce53 RS |
92 | |
93 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
94 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
95 | record a copy of const[012]_rtx. */ | |
96 | ||
97 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
98 | ||
68d75312 JC |
99 | rtx const_true_rtx; |
100 | ||
23b2ce53 RS |
101 | REAL_VALUE_TYPE dconst0; |
102 | REAL_VALUE_TYPE dconst1; | |
103 | REAL_VALUE_TYPE dconst2; | |
104 | REAL_VALUE_TYPE dconstm1; | |
105 | ||
106 | /* All references to the following fixed hard registers go through | |
107 | these unique rtl objects. On machines where the frame-pointer and | |
108 | arg-pointer are the same register, they use the same unique object. | |
109 | ||
110 | After register allocation, other rtl objects which used to be pseudo-regs | |
111 | may be clobbered to refer to the frame-pointer register. | |
112 | But references that were originally to the frame-pointer can be | |
113 | distinguished from the others because they contain frame_pointer_rtx. | |
114 | ||
ac6f08b0 DE |
115 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
116 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
117 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
118 | register elimination hard_frame_pointer_rtx should always be used. | |
119 | On machines where the two registers are same (most) then these are the | |
120 | same. | |
121 | ||
23b2ce53 RS |
122 | In an inline procedure, the stack and frame pointer rtxs may not be |
123 | used for anything else. */ | |
23b2ce53 RS |
124 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
125 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
126 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
127 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
128 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
129 | ||
a4417a86 JW |
130 | /* This is used to implement __builtin_return_address for some machines. |
131 | See for instance the MIPS port. */ | |
132 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
133 | ||
23b2ce53 RS |
134 | /* We make one copy of (const_int C) where C is in |
135 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
136 | to save space during the compilation and simplify comparisons of | |
137 | integers. */ | |
138 | ||
5da077de | 139 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 140 | |
c13e8210 MM |
141 | /* A hash table storing CONST_INTs whose absolute value is greater |
142 | than MAX_SAVED_CONST_INT. */ | |
143 | ||
144 | static htab_t const_int_htab; | |
145 | ||
23b2ce53 RS |
146 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
147 | shortly thrown away. We use two mechanisms to prevent this waste: | |
148 | ||
a3770a81 RH |
149 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
150 | rtvec for use by gen_sequence. One entry for each size is | |
151 | sufficient because most cases are calls to gen_sequence followed by | |
152 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
153 | sequence is destructive on the insn in it anyway and hence can't be | |
154 | redone. | |
23b2ce53 RS |
155 | |
156 | We do not bother to save this cached data over nested function calls. | |
157 | Instead, we just reinitialize them. */ | |
158 | ||
159 | #define SEQUENCE_RESULT_SIZE 5 | |
160 | ||
23b2ce53 RS |
161 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
162 | ||
0f41302f | 163 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
43127294 RK |
164 | static rtx free_insn; |
165 | ||
01d939e8 BS |
166 | #define first_insn (cfun->emit->x_first_insn) |
167 | #define last_insn (cfun->emit->x_last_insn) | |
168 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
169 | #define last_linenum (cfun->emit->x_last_linenum) | |
170 | #define last_filename (cfun->emit->x_last_filename) | |
171 | #define first_label_num (cfun->emit->x_first_label_num) | |
23b2ce53 | 172 | |
711d877c KG |
173 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
174 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
175 | static rtx find_line_note PARAMS ((rtx)); | |
176 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
d1b81779 | 177 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
5c6df058 | 178 | static void unshare_all_decls PARAMS ((tree)); |
2d4aecb3 | 179 | static void reset_used_decls PARAMS ((tree)); |
e5bef2e4 | 180 | static void mark_label_nuses PARAMS ((rtx)); |
c13e8210 MM |
181 | static hashval_t const_int_htab_hash PARAMS ((const void *)); |
182 | static int const_int_htab_eq PARAMS ((const void *, | |
183 | const void *)); | |
184 | static int rtx_htab_mark_1 PARAMS ((void **, void *)); | |
185 | static void rtx_htab_mark PARAMS ((void *)); | |
186 | ||
ca695ac9 | 187 | \f |
c13e8210 MM |
188 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
189 | ||
190 | static hashval_t | |
191 | const_int_htab_hash (x) | |
192 | const void *x; | |
193 | { | |
e77d72cb | 194 | return (hashval_t) INTVAL ((const struct rtx_def *) x); |
c13e8210 MM |
195 | } |
196 | ||
197 | /* Returns non-zero if the value represented by X (which is really a | |
198 | CONST_INT) is the same as that given by Y (which is really a | |
199 | HOST_WIDE_INT *). */ | |
200 | ||
201 | static int | |
202 | const_int_htab_eq (x, y) | |
203 | const void *x; | |
204 | const void *y; | |
205 | { | |
e77d72cb | 206 | return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y)); |
c13e8210 MM |
207 | } |
208 | ||
209 | /* Mark the hash-table element X (which is really a pointer to an | |
210 | rtx). */ | |
211 | ||
212 | static int | |
213 | rtx_htab_mark_1 (x, data) | |
214 | void **x; | |
215 | void *data ATTRIBUTE_UNUSED; | |
216 | { | |
217 | ggc_mark_rtx (*x); | |
218 | return 1; | |
219 | } | |
220 | ||
221 | /* Mark all the elements of HTAB (which is really an htab_t full of | |
222 | rtxs). */ | |
223 | ||
224 | static void | |
225 | rtx_htab_mark (htab) | |
226 | void *htab; | |
227 | { | |
228 | htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL); | |
229 | } | |
230 | ||
08394eef BS |
231 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
232 | don't attempt to share with the various global pieces of rtl (such as | |
233 | frame_pointer_rtx). */ | |
234 | ||
235 | rtx | |
236 | gen_raw_REG (mode, regno) | |
237 | enum machine_mode mode; | |
238 | int regno; | |
239 | { | |
240 | rtx x = gen_rtx_raw_REG (mode, regno); | |
241 | ORIGINAL_REGNO (x) = regno; | |
242 | return x; | |
243 | } | |
244 | ||
c5c76735 JL |
245 | /* There are some RTL codes that require special attention; the generation |
246 | functions do the raw handling. If you add to this list, modify | |
247 | special_rtx in gengenrtl.c as well. */ | |
248 | ||
3b80f6ca RH |
249 | rtx |
250 | gen_rtx_CONST_INT (mode, arg) | |
c13e8210 | 251 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3b80f6ca RH |
252 | HOST_WIDE_INT arg; |
253 | { | |
c13e8210 MM |
254 | void **slot; |
255 | ||
3b80f6ca | 256 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 257 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
258 | |
259 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
260 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
261 | return const_true_rtx; | |
262 | #endif | |
263 | ||
c13e8210 | 264 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
265 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
266 | (hashval_t) arg, INSERT); | |
29105cea | 267 | if (*slot == 0) |
1f8f4a0b | 268 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
269 | |
270 | return (rtx) *slot; | |
3b80f6ca RH |
271 | } |
272 | ||
29105cea | 273 | /* CONST_DOUBLEs needs special handling because their length is known |
0133b7d9 | 274 | only at run-time. */ |
29105cea | 275 | |
0133b7d9 RH |
276 | rtx |
277 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
278 | enum machine_mode mode; | |
279 | rtx arg0; | |
280 | HOST_WIDE_INT arg1, arg2; | |
281 | { | |
282 | rtx r = rtx_alloc (CONST_DOUBLE); | |
2454beaf RH |
283 | int i; |
284 | ||
0133b7d9 RH |
285 | PUT_MODE (r, mode); |
286 | XEXP (r, 0) = arg0; | |
ef178af3 | 287 | X0EXP (r, 1) = NULL_RTX; |
2454beaf RH |
288 | XWINT (r, 2) = arg1; |
289 | XWINT (r, 3) = arg2; | |
290 | ||
291 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
292 | XWINT (r, i) = 0; | |
293 | ||
0133b7d9 RH |
294 | return r; |
295 | } | |
296 | ||
3b80f6ca RH |
297 | rtx |
298 | gen_rtx_REG (mode, regno) | |
299 | enum machine_mode mode; | |
300 | int regno; | |
301 | { | |
302 | /* In case the MD file explicitly references the frame pointer, have | |
303 | all such references point to the same frame pointer. This is | |
304 | used during frame pointer elimination to distinguish the explicit | |
305 | references to these registers from pseudos that happened to be | |
306 | assigned to them. | |
307 | ||
308 | If we have eliminated the frame pointer or arg pointer, we will | |
309 | be using it as a normal register, for example as a spill | |
310 | register. In such cases, we might be accessing it in a mode that | |
311 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
312 | ||
313 | Also don't do this when we are making new REGs in reload, since | |
314 | we don't want to get confused with the real pointers. */ | |
315 | ||
316 | if (mode == Pmode && !reload_in_progress) | |
317 | { | |
bcb33994 | 318 | if (regno == FRAME_POINTER_REGNUM) |
3b80f6ca RH |
319 | return frame_pointer_rtx; |
320 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
bcb33994 | 321 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3b80f6ca RH |
322 | return hard_frame_pointer_rtx; |
323 | #endif | |
324 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 325 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
326 | return arg_pointer_rtx; |
327 | #endif | |
328 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 329 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
330 | return return_address_pointer_rtx; |
331 | #endif | |
bcb33994 | 332 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
333 | return stack_pointer_rtx; |
334 | } | |
335 | ||
08394eef | 336 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
337 | } |
338 | ||
41472af8 MM |
339 | rtx |
340 | gen_rtx_MEM (mode, addr) | |
341 | enum machine_mode mode; | |
342 | rtx addr; | |
343 | { | |
344 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
345 | ||
346 | /* This field is not cleared by the mere allocation of the rtx, so | |
347 | we clear it here. */ | |
348 | MEM_ALIAS_SET (rt) = 0; | |
349 | ||
350 | return rt; | |
351 | } | |
ddef6bc7 JJ |
352 | |
353 | rtx | |
354 | gen_rtx_SUBREG (mode, reg, offset) | |
355 | enum machine_mode mode; | |
356 | rtx reg; | |
357 | int offset; | |
358 | { | |
359 | /* This is the most common failure type. | |
360 | Catch it early so we can see who does it. */ | |
361 | if ((offset % GET_MODE_SIZE (mode)) != 0) | |
362 | abort (); | |
363 | ||
364 | /* This check isn't usable right now because combine will | |
365 | throw arbitrary crap like a CALL into a SUBREG in | |
366 | gen_lowpart_for_combine so we must just eat it. */ | |
367 | #if 0 | |
368 | /* Check for this too. */ | |
369 | if (offset >= GET_MODE_SIZE (GET_MODE (reg))) | |
370 | abort (); | |
371 | #endif | |
372 | return gen_rtx_fmt_ei (SUBREG, mode, reg, offset); | |
373 | } | |
374 | ||
375 | /* Generate a SUBREG representing the least-significant part | |
376 | * of REG if MODE is smaller than mode of REG, otherwise | |
377 | * paradoxical SUBREG. */ | |
378 | rtx | |
379 | gen_lowpart_SUBREG (mode, reg) | |
380 | enum machine_mode mode; | |
381 | rtx reg; | |
382 | { | |
383 | enum machine_mode inmode; | |
384 | int offset; | |
385 | ||
386 | inmode = GET_MODE (reg); | |
387 | if (inmode == VOIDmode) | |
388 | inmode = mode; | |
389 | offset = 0; | |
390 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (inmode) | |
391 | && (WORDS_BIG_ENDIAN || BYTES_BIG_ENDIAN)) | |
392 | { | |
393 | offset = GET_MODE_SIZE (inmode) - GET_MODE_SIZE (mode); | |
394 | if (! BYTES_BIG_ENDIAN) | |
395 | offset = (offset / UNITS_PER_WORD) * UNITS_PER_WORD; | |
396 | else if (! WORDS_BIG_ENDIAN) | |
397 | offset %= UNITS_PER_WORD; | |
398 | } | |
399 | return gen_rtx_SUBREG (mode, reg, offset); | |
400 | } | |
c5c76735 | 401 | \f |
23b2ce53 RS |
402 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
403 | ** | |
404 | ** This routine generates an RTX of the size specified by | |
405 | ** <code>, which is an RTX code. The RTX structure is initialized | |
406 | ** from the arguments <element1> through <elementn>, which are | |
407 | ** interpreted according to the specific RTX type's format. The | |
408 | ** special machine mode associated with the rtx (if any) is specified | |
409 | ** in <mode>. | |
410 | ** | |
1632afca | 411 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
412 | ** rtx it will generate. For example, the following rtx structure: |
413 | ** | |
414 | ** (plus:QI (mem:QI (reg:SI 1)) | |
415 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
416 | ** | |
417 | ** ...would be generated by the following C code: | |
418 | ** | |
419 | ** gen_rtx (PLUS, QImode, | |
420 | ** gen_rtx (MEM, QImode, | |
421 | ** gen_rtx (REG, SImode, 1)), | |
422 | ** gen_rtx (MEM, QImode, | |
423 | ** gen_rtx (PLUS, SImode, | |
424 | ** gen_rtx (REG, SImode, 2), | |
425 | ** gen_rtx (REG, SImode, 3)))), | |
426 | */ | |
427 | ||
428 | /*VARARGS2*/ | |
429 | rtx | |
711d877c | 430 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
23b2ce53 | 431 | { |
5148a72b | 432 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
433 | enum rtx_code code; |
434 | enum machine_mode mode; | |
4f90e4a0 RK |
435 | #endif |
436 | va_list p; | |
23b2ce53 | 437 | register int i; /* Array indices... */ |
6f7d635c | 438 | register const char *fmt; /* Current rtx's format... */ |
23b2ce53 RS |
439 | register rtx rt_val; /* RTX to return to caller... */ |
440 | ||
4f90e4a0 RK |
441 | VA_START (p, mode); |
442 | ||
5148a72b | 443 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
444 | code = va_arg (p, enum rtx_code); |
445 | mode = va_arg (p, enum machine_mode); | |
4f90e4a0 | 446 | #endif |
23b2ce53 | 447 | |
0133b7d9 | 448 | switch (code) |
23b2ce53 | 449 | { |
0133b7d9 RH |
450 | case CONST_INT: |
451 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
452 | break; | |
453 | ||
454 | case CONST_DOUBLE: | |
455 | { | |
456 | rtx arg0 = va_arg (p, rtx); | |
457 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
458 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
459 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
460 | } | |
461 | break; | |
462 | ||
463 | case REG: | |
464 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
465 | break; | |
466 | ||
467 | case MEM: | |
468 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
469 | break; | |
470 | ||
471 | default: | |
23b2ce53 RS |
472 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
473 | rt_val->mode = mode; /* Store the machine mode... */ | |
474 | ||
475 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
476 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
477 | { | |
478 | switch (*fmt++) | |
479 | { | |
480 | case '0': /* Unused field. */ | |
481 | break; | |
482 | ||
483 | case 'i': /* An integer? */ | |
484 | XINT (rt_val, i) = va_arg (p, int); | |
485 | break; | |
486 | ||
906c4e36 RK |
487 | case 'w': /* A wide integer? */ |
488 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
489 | break; | |
490 | ||
23b2ce53 RS |
491 | case 's': /* A string? */ |
492 | XSTR (rt_val, i) = va_arg (p, char *); | |
493 | break; | |
494 | ||
495 | case 'e': /* An expression? */ | |
496 | case 'u': /* An insn? Same except when printing. */ | |
497 | XEXP (rt_val, i) = va_arg (p, rtx); | |
498 | break; | |
499 | ||
500 | case 'E': /* An RTX vector? */ | |
501 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
502 | break; | |
503 | ||
0dfa1860 MM |
504 | case 'b': /* A bitmap? */ |
505 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
506 | break; | |
507 | ||
508 | case 't': /* A tree? */ | |
509 | XTREE (rt_val, i) = va_arg (p, tree); | |
510 | break; | |
511 | ||
23b2ce53 | 512 | default: |
1632afca | 513 | abort (); |
23b2ce53 RS |
514 | } |
515 | } | |
0133b7d9 | 516 | break; |
23b2ce53 | 517 | } |
0133b7d9 | 518 | |
23b2ce53 | 519 | va_end (p); |
0133b7d9 | 520 | return rt_val; |
23b2ce53 RS |
521 | } |
522 | ||
523 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
524 | ** | |
525 | ** This routine creates an rtvec and stores within it the | |
526 | ** pointers to rtx's which are its arguments. | |
527 | */ | |
528 | ||
529 | /*VARARGS1*/ | |
530 | rtvec | |
711d877c | 531 | gen_rtvec VPARAMS ((int n, ...)) |
23b2ce53 | 532 | { |
5148a72b | 533 | #ifndef ANSI_PROTOTYPES |
4f90e4a0 RK |
534 | int n; |
535 | #endif | |
536 | int i; | |
23b2ce53 RS |
537 | va_list p; |
538 | rtx *vector; | |
539 | ||
4f90e4a0 RK |
540 | VA_START (p, n); |
541 | ||
5148a72b | 542 | #ifndef ANSI_PROTOTYPES |
23b2ce53 | 543 | n = va_arg (p, int); |
4f90e4a0 | 544 | #endif |
23b2ce53 RS |
545 | |
546 | if (n == 0) | |
547 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
548 | ||
549 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 550 | |
23b2ce53 RS |
551 | for (i = 0; i < n; i++) |
552 | vector[i] = va_arg (p, rtx); | |
553 | va_end (p); | |
554 | ||
555 | return gen_rtvec_v (n, vector); | |
556 | } | |
557 | ||
558 | rtvec | |
559 | gen_rtvec_v (n, argp) | |
560 | int n; | |
561 | rtx *argp; | |
562 | { | |
563 | register int i; | |
564 | register rtvec rt_val; | |
565 | ||
566 | if (n == 0) | |
567 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
568 | ||
569 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
570 | ||
571 | for (i = 0; i < n; i++) | |
8f985ec4 | 572 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
573 | |
574 | return rt_val; | |
575 | } | |
ba444f92 | 576 | |
23b2ce53 RS |
577 | \f |
578 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
579 | This pseudo is assigned the next sequential register number. */ | |
580 | ||
581 | rtx | |
582 | gen_reg_rtx (mode) | |
583 | enum machine_mode mode; | |
584 | { | |
01d939e8 | 585 | struct function *f = cfun; |
23b2ce53 RS |
586 | register rtx val; |
587 | ||
f1db3576 JL |
588 | /* Don't let anything called after initial flow analysis create new |
589 | registers. */ | |
590 | if (no_new_pseudos) | |
23b2ce53 RS |
591 | abort (); |
592 | ||
1b3d8f8a GK |
593 | if (generating_concat_p |
594 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
595 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
596 | { |
597 | /* For complex modes, don't make a single pseudo. | |
598 | Instead, make a CONCAT of two pseudos. | |
599 | This allows noncontiguous allocation of the real and imaginary parts, | |
600 | which makes much better code. Besides, allocating DCmode | |
601 | pseudos overstrains reload on some machines like the 386. */ | |
602 | rtx realpart, imagpart; | |
603 | int size = GET_MODE_UNIT_SIZE (mode); | |
604 | enum machine_mode partmode | |
605 | = mode_for_size (size * BITS_PER_UNIT, | |
606 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
607 | ? MODE_FLOAT : MODE_INT), | |
608 | 0); | |
609 | ||
610 | realpart = gen_reg_rtx (partmode); | |
611 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 612 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
613 | } |
614 | ||
3502dc9c JDA |
615 | /* Make sure regno_pointer_align and regno_reg_rtx are large enough |
616 | to have an element for this pseudo reg number. */ | |
23b2ce53 | 617 | |
3502dc9c | 618 | if (reg_rtx_no == f->emit->regno_pointer_align_length) |
23b2ce53 | 619 | { |
3502dc9c | 620 | int old_size = f->emit->regno_pointer_align_length; |
23b2ce53 | 621 | rtx *new1; |
e2ecd91c | 622 | char *new; |
e2ecd91c | 623 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa | 624 | memset (new + old_size, 0, old_size); |
f9e158c3 | 625 | f->emit->regno_pointer_align = (unsigned char *) new; |
49ad7cfa | 626 | |
e2ecd91c BS |
627 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
628 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 629 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
630 | regno_reg_rtx = new1; |
631 | ||
3502dc9c | 632 | f->emit->regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
633 | } |
634 | ||
08394eef | 635 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
636 | regno_reg_rtx[reg_rtx_no++] = val; |
637 | return val; | |
638 | } | |
639 | ||
754fdcca RK |
640 | /* Identify REG (which may be a CONCAT) as a user register. */ |
641 | ||
642 | void | |
643 | mark_user_reg (reg) | |
644 | rtx reg; | |
645 | { | |
646 | if (GET_CODE (reg) == CONCAT) | |
647 | { | |
648 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
649 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
650 | } | |
651 | else if (GET_CODE (reg) == REG) | |
652 | REG_USERVAR_P (reg) = 1; | |
653 | else | |
654 | abort (); | |
655 | } | |
656 | ||
86fe05e0 RK |
657 | /* Identify REG as a probable pointer register and show its alignment |
658 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
659 | |
660 | void | |
86fe05e0 | 661 | mark_reg_pointer (reg, align) |
23b2ce53 | 662 | rtx reg; |
86fe05e0 | 663 | int align; |
23b2ce53 | 664 | { |
3502dc9c | 665 | if (! REG_POINTER (reg)) |
00995e78 | 666 | { |
3502dc9c | 667 | REG_POINTER (reg) = 1; |
86fe05e0 | 668 | |
00995e78 RE |
669 | if (align) |
670 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
671 | } | |
672 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
673 | /* We can no-longer be sure just how aligned this pointer is */ | |
86fe05e0 | 674 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
675 | } |
676 | ||
677 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
678 | ||
679 | int | |
680 | max_reg_num () | |
681 | { | |
682 | return reg_rtx_no; | |
683 | } | |
684 | ||
685 | /* Return 1 + the largest label number used so far in the current function. */ | |
686 | ||
687 | int | |
688 | max_label_num () | |
689 | { | |
690 | if (last_label_num && label_num == base_label_num) | |
691 | return last_label_num; | |
692 | return label_num; | |
693 | } | |
694 | ||
695 | /* Return first label number used in this function (if any were used). */ | |
696 | ||
697 | int | |
698 | get_first_label_num () | |
699 | { | |
700 | return first_label_num; | |
701 | } | |
702 | \f | |
ddef6bc7 JJ |
703 | /* Return the final regno of X, which is a SUBREG of a hard |
704 | register. */ | |
705 | int | |
706 | subreg_hard_regno (x, check_mode) | |
707 | register rtx x; | |
708 | int check_mode; | |
709 | { | |
710 | enum machine_mode mode = GET_MODE (x); | |
711 | unsigned int byte_offset, base_regno, final_regno; | |
712 | rtx reg = SUBREG_REG (x); | |
713 | ||
714 | /* This is where we attempt to catch illegal subregs | |
715 | created by the compiler. */ | |
716 | if (GET_CODE (x) != SUBREG | |
717 | || GET_CODE (reg) != REG) | |
718 | abort (); | |
719 | base_regno = REGNO (reg); | |
720 | if (base_regno >= FIRST_PSEUDO_REGISTER) | |
721 | abort (); | |
0607953c | 722 | if (check_mode && ! HARD_REGNO_MODE_OK (base_regno, GET_MODE (reg))) |
ddef6bc7 JJ |
723 | abort (); |
724 | ||
725 | /* Catch non-congruent offsets too. */ | |
726 | byte_offset = SUBREG_BYTE (x); | |
727 | if ((byte_offset % GET_MODE_SIZE (mode)) != 0) | |
728 | abort (); | |
729 | ||
730 | final_regno = subreg_regno (x); | |
731 | ||
732 | return final_regno; | |
733 | } | |
734 | ||
23b2ce53 RS |
735 | /* Return a value representing some low-order bits of X, where the number |
736 | of low-order bits is given by MODE. Note that no conversion is done | |
737 | between floating-point and fixed-point values, rather, the bit | |
738 | representation is returned. | |
739 | ||
740 | This function handles the cases in common between gen_lowpart, below, | |
741 | and two variants in cse.c and combine.c. These are the cases that can | |
742 | be safely handled at all points in the compilation. | |
743 | ||
744 | If this is not a case we can handle, return 0. */ | |
745 | ||
746 | rtx | |
747 | gen_lowpart_common (mode, x) | |
748 | enum machine_mode mode; | |
749 | register rtx x; | |
750 | { | |
ddef6bc7 JJ |
751 | int msize = GET_MODE_SIZE (mode); |
752 | int xsize = GET_MODE_SIZE (GET_MODE (x)); | |
753 | int offset = 0; | |
23b2ce53 RS |
754 | |
755 | if (GET_MODE (x) == mode) | |
756 | return x; | |
757 | ||
758 | /* MODE must occupy no more words than the mode of X. */ | |
759 | if (GET_MODE (x) != VOIDmode | |
ddef6bc7 JJ |
760 | && ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
761 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
23b2ce53 RS |
762 | return 0; |
763 | ||
ddef6bc7 JJ |
764 | if ((WORDS_BIG_ENDIAN || BYTES_BIG_ENDIAN) |
765 | && xsize > msize) | |
766 | { | |
767 | int difference = xsize - msize; | |
768 | ||
769 | if (WORDS_BIG_ENDIAN) | |
770 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
771 | if (BYTES_BIG_ENDIAN) | |
772 | offset += difference % UNITS_PER_WORD; | |
773 | } | |
23b2ce53 RS |
774 | |
775 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
776 | && (GET_MODE_CLASS (mode) == MODE_INT |
777 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
778 | { |
779 | /* If we are getting the low-order part of something that has been | |
780 | sign- or zero-extended, we can either just use the object being | |
781 | extended or make a narrower extension. If we want an even smaller | |
782 | piece than the size of the object being extended, call ourselves | |
783 | recursively. | |
784 | ||
785 | This case is used mostly by combine and cse. */ | |
786 | ||
787 | if (GET_MODE (XEXP (x, 0)) == mode) | |
788 | return XEXP (x, 0); | |
789 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
790 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
791 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3b80f6ca | 792 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 RS |
793 | } |
794 | else if (GET_CODE (x) == SUBREG | |
ddef6bc7 | 795 | && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD |
23b2ce53 | 796 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) |
ddef6bc7 JJ |
797 | { |
798 | int final_offset; | |
799 | ||
800 | if (GET_MODE (SUBREG_REG (x)) == mode && subreg_lowpart_p (x)) | |
801 | return SUBREG_REG (x); | |
802 | ||
803 | /* When working with SUBREGs the rule is that the byte | |
804 | offset must be a multiple of the SUBREG's mode. */ | |
805 | final_offset = SUBREG_BYTE (x) + offset; | |
806 | final_offset = (final_offset / GET_MODE_SIZE (mode)); | |
807 | final_offset = (final_offset * GET_MODE_SIZE (mode)); | |
808 | return gen_rtx_SUBREG (mode, SUBREG_REG (x), final_offset); | |
809 | } | |
23b2ce53 RS |
810 | else if (GET_CODE (x) == REG) |
811 | { | |
ddef6bc7 JJ |
812 | /* Hard registers are done specially in certain cases. */ |
813 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
814 | { | |
815 | int final_regno = REGNO (x) + | |
816 | subreg_regno_offset (REGNO (x), GET_MODE (x), | |
817 | offset, mode); | |
818 | ||
819 | /* If the final regno is not valid for MODE, punt. */ | |
820 | /* ??? We do allow it if the current REG is not valid for | |
821 | ??? it's mode. It is a kludge to work around how float/complex | |
822 | ??? arguments are passed on 32-bit Sparc and should be fixed. */ | |
823 | if (! HARD_REGNO_MODE_OK (final_regno, mode) | |
824 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
825 | return 0; | |
826 | ||
23b2ce53 | 827 | /* integrate.c can't handle parts of a return value register. */ |
ddef6bc7 | 828 | if ((! REG_FUNCTION_VALUE_P (x) |
cb00f51a | 829 | || ! rtx_equal_function_value_matters) |
02188693 RH |
830 | #ifdef CLASS_CANNOT_CHANGE_MODE |
831 | && ! (CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (x)) | |
aff48bca JL |
832 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT |
833 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT | |
834 | && (TEST_HARD_REG_BIT | |
02188693 | 835 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], |
aff48bca JL |
836 | REGNO (x)))) |
837 | #endif | |
cb00f51a RK |
838 | /* We want to keep the stack, frame, and arg pointers |
839 | special. */ | |
65e8fe02 | 840 | && x != frame_pointer_rtx |
cb00f51a | 841 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 842 | && x != arg_pointer_rtx |
cb00f51a | 843 | #endif |
65e8fe02 | 844 | && x != stack_pointer_rtx) |
ddef6bc7 JJ |
845 | return gen_rtx_REG (mode, final_regno); |
846 | } | |
847 | return gen_rtx_SUBREG (mode, x, offset); | |
23b2ce53 | 848 | } |
23b2ce53 RS |
849 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
850 | from the low-order part of the constant. */ | |
83e9c679 RK |
851 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
852 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
853 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 854 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
855 | { |
856 | /* If MODE is twice the host word size, X is already the desired | |
857 | representation. Otherwise, if MODE is wider than a word, we can't | |
e1389cac | 858 | do this. If MODE is exactly a word, return just one CONST_INT. */ |
1a5b457d | 859 | |
a8dd0e73 | 860 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 861 | return x; |
906c4e36 | 862 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 863 | return 0; |
906c4e36 | 864 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 865 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 866 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
867 | else |
868 | { | |
27eef9ce | 869 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
906c4e36 RK |
870 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
871 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 872 | |
27eef9ce | 873 | /* Sign extend to HOST_WIDE_INT. */ |
e1389cac | 874 | val = trunc_int_for_mode (val, mode); |
1a5b457d RK |
875 | |
876 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 877 | : GEN_INT (val)); |
1a5b457d RK |
878 | } |
879 | } | |
23b2ce53 | 880 | |
a2061c0d | 881 | #ifndef REAL_ARITHMETIC |
8aada4ad RK |
882 | /* If X is an integral constant but we want it in floating-point, it |
883 | must be the case that we have a union of an integer and a floating-point | |
884 | value. If the machine-parameters allow it, simulate that union here | |
d6020413 RK |
885 | and return the result. The two-word and single-word cases are |
886 | different. */ | |
8aada4ad | 887 | |
b3bf132d | 888 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 889 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 890 | || flag_pretend_float) |
8aada4ad | 891 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
d6020413 RK |
892 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
893 | && GET_CODE (x) == CONST_INT | |
906c4e36 | 894 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
d6020413 | 895 | { |
906c4e36 | 896 | union {HOST_WIDE_INT i; float d; } u; |
d6020413 RK |
897 | |
898 | u.i = INTVAL (x); | |
53596fba | 899 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
d6020413 | 900 | } |
d6020413 | 901 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 902 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
d6020413 RK |
903 | || flag_pretend_float) |
904 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
905 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
8aada4ad RK |
906 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
907 | && GET_MODE (x) == VOIDmode | |
906c4e36 RK |
908 | && (sizeof (double) * HOST_BITS_PER_CHAR |
909 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
8aada4ad | 910 | { |
906c4e36 RK |
911 | union {HOST_WIDE_INT i[2]; double d; } u; |
912 | HOST_WIDE_INT low, high; | |
8aada4ad RK |
913 | |
914 | if (GET_CODE (x) == CONST_INT) | |
906c4e36 | 915 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
8aada4ad RK |
916 | else |
917 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
918 | ||
919 | #ifdef HOST_WORDS_BIG_ENDIAN | |
920 | u.i[0] = high, u.i[1] = low; | |
921 | #else | |
922 | u.i[0] = low, u.i[1] = high; | |
923 | #endif | |
924 | ||
53596fba | 925 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
8aada4ad | 926 | } |
a6a503ed | 927 | |
b3bf132d RK |
928 | /* Similarly, if this is converting a floating-point value into a |
929 | single-word integer. Only do this is the host and target parameters are | |
930 | compatible. */ | |
931 | ||
932 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
906c4e36 | 933 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 934 | || flag_pretend_float) |
83e9c679 RK |
935 | && (GET_MODE_CLASS (mode) == MODE_INT |
936 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
b3bf132d RK |
937 | && GET_CODE (x) == CONST_DOUBLE |
938 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
939 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
ddef6bc7 | 940 | return constant_subword (x, (offset / UNITS_PER_WORD), GET_MODE (x)); |
b3bf132d | 941 | |
8aada4ad RK |
942 | /* Similarly, if this is converting a floating-point value into a |
943 | two-word integer, we can do this one word at a time and make an | |
944 | integer. Only do this is the host and target parameters are | |
945 | compatible. */ | |
946 | ||
b3bf132d | 947 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 948 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 949 | || flag_pretend_float) |
83e9c679 | 950 | && (GET_MODE_CLASS (mode) == MODE_INT |
f5a2fb25 | 951 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
8aada4ad RK |
952 | && GET_CODE (x) == CONST_DOUBLE |
953 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
954 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
955 | { | |
ddef6bc7 JJ |
956 | rtx lowpart, highpart; |
957 | ||
958 | lowpart = constant_subword (x, | |
959 | (offset / UNITS_PER_WORD) + WORDS_BIG_ENDIAN, | |
960 | GET_MODE (x)); | |
961 | highpart = constant_subword (x, | |
962 | (offset / UNITS_PER_WORD) + (! WORDS_BIG_ENDIAN), | |
963 | GET_MODE (x)); | |
8aada4ad RK |
964 | if (lowpart && GET_CODE (lowpart) == CONST_INT |
965 | && highpart && GET_CODE (highpart) == CONST_INT) | |
966 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
967 | } | |
a2061c0d GK |
968 | #else /* ifndef REAL_ARITHMETIC */ |
969 | ||
970 | /* When we have a FP emulator, we can handle all conversions between | |
971 | FP and integer operands. This simplifies reload because it | |
972 | doesn't have to deal with constructs like (subreg:DI | |
973 | (const_double:SF ...)) or (subreg:DF (const_int ...)). */ | |
974 | ||
975 | else if (mode == SFmode | |
976 | && GET_CODE (x) == CONST_INT) | |
977 | { | |
978 | REAL_VALUE_TYPE r; | |
979 | HOST_WIDE_INT i; | |
980 | ||
981 | i = INTVAL (x); | |
982 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
983 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
984 | } | |
985 | else if (mode == DFmode | |
986 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
987 | && GET_MODE (x) == VOIDmode) | |
988 | { | |
989 | REAL_VALUE_TYPE r; | |
990 | HOST_WIDE_INT i[2]; | |
991 | HOST_WIDE_INT low, high; | |
992 | ||
993 | if (GET_CODE (x) == CONST_INT) | |
994 | { | |
995 | low = INTVAL (x); | |
996 | high = low >> (HOST_BITS_PER_WIDE_INT - 1); | |
997 | } | |
998 | else | |
999 | { | |
1000 | low = CONST_DOUBLE_LOW (x); | |
1001 | high = CONST_DOUBLE_HIGH (x); | |
1002 | } | |
1003 | ||
1004 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the | |
1005 | target machine. */ | |
1006 | if (WORDS_BIG_ENDIAN) | |
1007 | i[0] = high, i[1] = low; | |
1008 | else | |
1009 | i[0] = low, i[1] = high; | |
1010 | ||
1011 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
1012 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
1013 | } | |
1014 | else if ((GET_MODE_CLASS (mode) == MODE_INT | |
1015 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
1016 | && GET_CODE (x) == CONST_DOUBLE | |
1017 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1018 | { | |
1019 | REAL_VALUE_TYPE r; | |
1020 | long i[4]; /* Only the low 32 bits of each 'long' are used. */ | |
1021 | int endian = WORDS_BIG_ENDIAN ? 1 : 0; | |
1022 | ||
1023 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
1024 | switch (GET_MODE (x)) | |
1025 | { | |
1026 | case SFmode: | |
1027 | REAL_VALUE_TO_TARGET_SINGLE (r, i[endian]); | |
1156b23c | 1028 | i[1 - endian] = 0; |
a2061c0d GK |
1029 | break; |
1030 | case DFmode: | |
1031 | REAL_VALUE_TO_TARGET_DOUBLE (r, i); | |
1032 | break; | |
1033 | #if LONG_DOUBLE_TYPE_SIZE == 96 | |
1034 | case XFmode: | |
e389897b JJ |
1035 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i + endian); |
1036 | i[3-3*endian] = 0; | |
a2061c0d GK |
1037 | #else |
1038 | case TFmode: | |
a2061c0d | 1039 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i); |
e389897b | 1040 | #endif |
a2061c0d GK |
1041 | break; |
1042 | default: | |
1156b23c | 1043 | abort (); |
a2061c0d GK |
1044 | } |
1045 | ||
1046 | /* Now, pack the 32-bit elements of the array into a CONST_DOUBLE | |
1047 | and return it. */ | |
1048 | #if HOST_BITS_PER_WIDE_INT == 32 | |
1156b23c | 1049 | return immed_double_const (i[endian], i[1 - endian], mode); |
a2061c0d | 1050 | #else |
50e60bc3 ZW |
1051 | { |
1052 | int c; | |
1053 | ||
1054 | if (HOST_BITS_PER_WIDE_INT != 64) | |
1156b23c RK |
1055 | abort (); |
1056 | ||
50e60bc3 | 1057 | for (c = 0; c < 4; c++) |
1156b23c | 1058 | i[c] &= ~ (0L); |
e389897b JJ |
1059 | |
1060 | switch (GET_MODE (x)) | |
1061 | { | |
1062 | case SFmode: | |
1063 | case DFmode: | |
1064 | return immed_double_const (((unsigned long) i[endian]) | | |
1065 | (((HOST_WIDE_INT) i[1-endian]) << 32), | |
1066 | 0, mode); | |
1067 | default: | |
1068 | return immed_double_const (((unsigned long) i[endian*3]) | | |
1069 | (((HOST_WIDE_INT) i[1+endian]) << 32), | |
1070 | ((unsigned long) i[2-endian]) | | |
1071 | (((HOST_WIDE_INT) i[3-endian*3]) << 32), | |
1072 | mode); | |
1073 | } | |
50e60bc3 | 1074 | } |
a2061c0d GK |
1075 | #endif |
1076 | } | |
1077 | #endif /* ifndef REAL_ARITHMETIC */ | |
8aada4ad | 1078 | |
23b2ce53 RS |
1079 | /* Otherwise, we can't do this. */ |
1080 | return 0; | |
1081 | } | |
1082 | \f | |
280194b0 RS |
1083 | /* Return the real part (which has mode MODE) of a complex value X. |
1084 | This always comes at the low address in memory. */ | |
1085 | ||
1086 | rtx | |
1087 | gen_realpart (mode, x) | |
1088 | enum machine_mode mode; | |
1089 | register rtx x; | |
1090 | { | |
dc139c90 RK |
1091 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
1092 | return XEXP (x, 0); | |
40c0c3cf JL |
1093 | else if (WORDS_BIG_ENDIAN |
1094 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
1095 | && REG_P (x) | |
1096 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
400500c4 RK |
1097 | internal_error |
1098 | ("Can't access real part of complex value in hard register"); | |
dc139c90 | 1099 | else if (WORDS_BIG_ENDIAN) |
280194b0 RS |
1100 | return gen_highpart (mode, x); |
1101 | else | |
1102 | return gen_lowpart (mode, x); | |
1103 | } | |
1104 | ||
1105 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
1106 | This always comes at the high address in memory. */ | |
1107 | ||
1108 | rtx | |
1109 | gen_imagpart (mode, x) | |
1110 | enum machine_mode mode; | |
1111 | register rtx x; | |
1112 | { | |
dc139c90 RK |
1113 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
1114 | return XEXP (x, 1); | |
1115 | else if (WORDS_BIG_ENDIAN) | |
280194b0 | 1116 | return gen_lowpart (mode, x); |
ddef6bc7 | 1117 | else if (! WORDS_BIG_ENDIAN |
40c0c3cf JL |
1118 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD |
1119 | && REG_P (x) | |
1120 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
400500c4 RK |
1121 | internal_error |
1122 | ("can't access imaginary part of complex value in hard register"); | |
280194b0 RS |
1123 | else |
1124 | return gen_highpart (mode, x); | |
1125 | } | |
81284a6a JW |
1126 | |
1127 | /* Return 1 iff X, assumed to be a SUBREG, | |
1128 | refers to the real part of the complex value in its containing reg. | |
1129 | Complex values are always stored with the real part in the first word, | |
1130 | regardless of WORDS_BIG_ENDIAN. */ | |
1131 | ||
1132 | int | |
1133 | subreg_realpart_p (x) | |
1134 | rtx x; | |
1135 | { | |
1136 | if (GET_CODE (x) != SUBREG) | |
1137 | abort (); | |
1138 | ||
ddef6bc7 | 1139 | return ((unsigned int) SUBREG_BYTE (x) |
770ae6cc | 1140 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); |
81284a6a | 1141 | } |
280194b0 | 1142 | \f |
23b2ce53 RS |
1143 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1144 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1145 | least-significant part of X. | |
1146 | MODE specifies how big a part of X to return; | |
1147 | it usually should not be larger than a word. | |
1148 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1149 | ||
1150 | rtx | |
1151 | gen_lowpart (mode, x) | |
1152 | enum machine_mode mode; | |
1153 | register rtx x; | |
1154 | { | |
1155 | rtx result = gen_lowpart_common (mode, x); | |
1156 | ||
1157 | if (result) | |
1158 | return result; | |
ea8262b0 RK |
1159 | else if (GET_CODE (x) == REG) |
1160 | { | |
1161 | /* Must be a hard reg that's not valid in MODE. */ | |
1162 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1163 | if (result == 0) | |
1164 | abort (); | |
72c3833b | 1165 | return result; |
ea8262b0 | 1166 | } |
23b2ce53 RS |
1167 | else if (GET_CODE (x) == MEM) |
1168 | { | |
1169 | /* The only additional case we can do is MEM. */ | |
1170 | register int offset = 0; | |
1171 | if (WORDS_BIG_ENDIAN) | |
1172 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1173 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1174 | ||
1175 | if (BYTES_BIG_ENDIAN) | |
1176 | /* Adjust the address so that the address-after-the-data | |
1177 | is unchanged. */ | |
1178 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1179 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1180 | ||
1181 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
1182 | } | |
e9a25f70 JL |
1183 | else if (GET_CODE (x) == ADDRESSOF) |
1184 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
23b2ce53 RS |
1185 | else |
1186 | abort (); | |
1187 | } | |
1188 | ||
ccba022b RS |
1189 | /* Like `gen_lowpart', but refer to the most significant part. |
1190 | This is used to access the imaginary part of a complex number. */ | |
1191 | ||
1192 | rtx | |
1193 | gen_highpart (mode, x) | |
1194 | enum machine_mode mode; | |
1195 | register rtx x; | |
1196 | { | |
ddef6bc7 JJ |
1197 | unsigned int msize = GET_MODE_SIZE (mode); |
1198 | unsigned int xsize = GET_MODE_SIZE (GET_MODE (x)); | |
1199 | ||
ccba022b RS |
1200 | /* This case loses if X is a subreg. To catch bugs early, |
1201 | complain if an invalid MODE is used even in other cases. */ | |
ddef6bc7 JJ |
1202 | if (msize > UNITS_PER_WORD |
1203 | && msize != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
ccba022b RS |
1204 | abort (); |
1205 | if (GET_CODE (x) == CONST_DOUBLE | |
1632afca | 1206 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
ccba022b RS |
1207 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
1208 | #endif | |
1209 | ) | |
3b80f6ca | 1210 | return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); |
ccba022b | 1211 | else if (GET_CODE (x) == CONST_INT) |
27eef9ce JC |
1212 | { |
1213 | if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD) | |
1214 | return const0_rtx; | |
1215 | return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD)); | |
1216 | } | |
ccba022b RS |
1217 | else if (GET_CODE (x) == MEM) |
1218 | { | |
1219 | register int offset = 0; | |
ddef6bc7 | 1220 | |
8698cce3 | 1221 | if (! WORDS_BIG_ENDIAN) |
ddef6bc7 JJ |
1222 | offset = (MAX (xsize, UNITS_PER_WORD) |
1223 | - MAX (msize, UNITS_PER_WORD)); | |
8698cce3 RK |
1224 | |
1225 | if (! BYTES_BIG_ENDIAN | |
ddef6bc7 JJ |
1226 | && msize < UNITS_PER_WORD) |
1227 | offset -= (msize - MIN (UNITS_PER_WORD, xsize)); | |
8698cce3 | 1228 | |
ccba022b RS |
1229 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
1230 | } | |
1231 | else if (GET_CODE (x) == SUBREG) | |
1232 | { | |
1233 | /* The only time this should occur is when we are looking at a | |
1234 | multi-word item with a SUBREG whose mode is the same as that of the | |
1235 | item. It isn't clear what we would do if it wasn't. */ | |
ddef6bc7 | 1236 | if (SUBREG_BYTE (x) != 0) |
ccba022b RS |
1237 | abort (); |
1238 | return gen_highpart (mode, SUBREG_REG (x)); | |
1239 | } | |
1240 | else if (GET_CODE (x) == REG) | |
1241 | { | |
ddef6bc7 | 1242 | int offset = 0; |
4901a643 | 1243 | |
69295d6d AO |
1244 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) |
1245 | abort (); | |
ddef6bc7 JJ |
1246 | |
1247 | if ((! WORDS_BIG_ENDIAN || ! BYTES_BIG_ENDIAN) | |
1248 | && xsize > msize) | |
1249 | { | |
1250 | int difference = xsize - msize; | |
1251 | ||
1252 | if (! WORDS_BIG_ENDIAN) | |
1253 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1254 | if (! BYTES_BIG_ENDIAN) | |
1255 | offset += difference % UNITS_PER_WORD; | |
1256 | } | |
1257 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1258 | { | |
1259 | int final_regno = REGNO (x) + | |
1260 | subreg_regno_offset (REGNO (x), GET_MODE (x), offset, mode); | |
1261 | ||
1262 | /* integrate.c can't handle parts of a return value register. | |
1263 | ??? Then integrate.c should be fixed! | |
1264 | ??? What about CLASS_CANNOT_CHANGE_SIZE? */ | |
1265 | if ((! REG_FUNCTION_VALUE_P (x) | |
1266 | || ! rtx_equal_function_value_matters) | |
cb00f51a | 1267 | /* We want to keep the stack, frame, and arg pointers special. */ |
ddef6bc7 JJ |
1268 | && x != frame_pointer_rtx |
1269 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
1270 | && x != arg_pointer_rtx | |
cb00f51a | 1271 | #endif |
ddef6bc7 JJ |
1272 | && x != stack_pointer_rtx) |
1273 | return gen_rtx_REG (mode, final_regno); | |
1274 | } | |
1275 | /* Just generate a normal SUBREG. */ | |
1276 | return gen_rtx_SUBREG (mode, x, offset); | |
ccba022b RS |
1277 | } |
1278 | else | |
1279 | abort (); | |
1280 | } | |
1281 | ||
23b2ce53 RS |
1282 | /* Return 1 iff X, assumed to be a SUBREG, |
1283 | refers to the least significant part of its containing reg. | |
1284 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1285 | ||
1286 | int | |
1287 | subreg_lowpart_p (x) | |
1288 | rtx x; | |
1289 | { | |
ddef6bc7 JJ |
1290 | unsigned int offset = 0; |
1291 | int difference = (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1292 | - GET_MODE_SIZE (GET_MODE (x))); | |
1293 | ||
23b2ce53 RS |
1294 | if (GET_CODE (x) != SUBREG) |
1295 | return 1; | |
a3a03040 RK |
1296 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1297 | return 0; | |
23b2ce53 | 1298 | |
ddef6bc7 JJ |
1299 | if (difference > 0) |
1300 | { | |
1301 | if (WORDS_BIG_ENDIAN) | |
1302 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1303 | if (BYTES_BIG_ENDIAN) | |
1304 | offset += difference % UNITS_PER_WORD; | |
1305 | } | |
23b2ce53 | 1306 | |
ddef6bc7 | 1307 | return SUBREG_BYTE (x) == offset; |
23b2ce53 RS |
1308 | } |
1309 | \f | |
23b2ce53 | 1310 | |
ddef6bc7 JJ |
1311 | /* Helper routine for all the constant cases of operand_subword. |
1312 | Some places invoke this directly. */ | |
23b2ce53 RS |
1313 | |
1314 | rtx | |
ddef6bc7 | 1315 | constant_subword (op, offset, mode) |
23b2ce53 | 1316 | rtx op; |
ddef6bc7 | 1317 | int offset; |
23b2ce53 RS |
1318 | enum machine_mode mode; |
1319 | { | |
906c4e36 | 1320 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; |
ddef6bc7 | 1321 | HOST_WIDE_INT val; |
23b2ce53 RS |
1322 | |
1323 | /* If OP is already an integer word, return it. */ | |
1324 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1325 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1326 | return op; | |
1327 | ||
1632afca | 1328 | #ifdef REAL_ARITHMETIC |
5495cc55 RH |
1329 | /* The output is some bits, the width of the target machine's word. |
1330 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1331 | host can't. */ | |
9847c2f6 | 1332 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1632afca | 1333 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1334 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1335 | && GET_CODE (op) == CONST_DOUBLE) |
1336 | { | |
9847c2f6 | 1337 | long k[2]; |
1632afca RS |
1338 | REAL_VALUE_TYPE rv; |
1339 | ||
1340 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1341 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1342 | |
9847c2f6 | 1343 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 | 1344 | which the words are written depends on the word endianness. |
7677ffa4 | 1345 | ??? This is a potential portability problem and should |
7cae975e RH |
1346 | be fixed at some point. |
1347 | ||
1348 | We must excercise caution with the sign bit. By definition there | |
1349 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1350 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1351 | So we explicitly mask and sign-extend as necessary. */ | |
9847c2f6 | 1352 | if (BITS_PER_WORD == 32) |
7cae975e | 1353 | { |
ddef6bc7 | 1354 | val = k[offset]; |
7cae975e RH |
1355 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1356 | return GEN_INT (val); | |
1357 | } | |
1358 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
ddef6bc7 | 1359 | else if (BITS_PER_WORD >= 64 && offset == 0) |
7cae975e RH |
1360 | { |
1361 | val = k[! WORDS_BIG_ENDIAN]; | |
1362 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1363 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1364 | return GEN_INT (val); | |
1365 | } | |
9847c2f6 | 1366 | #endif |
47b34d40 JW |
1367 | else if (BITS_PER_WORD == 16) |
1368 | { | |
ddef6bc7 JJ |
1369 | val = k[offset >> 1]; |
1370 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) | |
7cae975e | 1371 | val >>= 16; |
73de376f | 1372 | val = ((val & 0xffff) ^ 0x8000) - 0x8000; |
7cae975e | 1373 | return GEN_INT (val); |
47b34d40 | 1374 | } |
7677ffa4 RK |
1375 | else |
1376 | abort (); | |
1632afca | 1377 | } |
a5559dbc RE |
1378 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1379 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1380 | && GET_MODE_BITSIZE (mode) > 64 | |
1381 | && GET_CODE (op) == CONST_DOUBLE) | |
5495cc55 RH |
1382 | { |
1383 | long k[4]; | |
1384 | REAL_VALUE_TYPE rv; | |
a5559dbc | 1385 | |
5495cc55 RH |
1386 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1387 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
a5559dbc | 1388 | |
5495cc55 RH |
1389 | if (BITS_PER_WORD == 32) |
1390 | { | |
ddef6bc7 | 1391 | val = k[offset]; |
5495cc55 RH |
1392 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1393 | return GEN_INT (val); | |
1394 | } | |
1395 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
ddef6bc7 | 1396 | else if (BITS_PER_WORD >= 64 && offset <= 1) |
5495cc55 | 1397 | { |
ddef6bc7 | 1398 | val = k[offset * 2 + ! WORDS_BIG_ENDIAN]; |
5495cc55 | 1399 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; |
ddef6bc7 | 1400 | val |= (HOST_WIDE_INT) k[offset * 2 + WORDS_BIG_ENDIAN] & 0xffffffff; |
5495cc55 RH |
1401 | return GEN_INT (val); |
1402 | } | |
1403 | #endif | |
1404 | else | |
1405 | abort (); | |
1406 | } | |
1632afca | 1407 | #else /* no REAL_ARITHMETIC */ |
23b2ce53 | 1408 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1409 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1410 | || flag_pretend_float) |
1411 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1412 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1413 | && GET_CODE (op) == CONST_DOUBLE) | |
7529ac93 CH |
1414 | { |
1415 | /* The constant is stored in the host's word-ordering, | |
1416 | but we want to access it in the target's word-ordering. Some | |
1417 | compilers don't like a conditional inside macro args, so we have two | |
1418 | copies of the return. */ | |
2fe02d7e | 1419 | #ifdef HOST_WORDS_BIG_ENDIAN |
ddef6bc7 | 1420 | return GEN_INT (offset == WORDS_BIG_ENDIAN |
7529ac93 | 1421 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); |
2fe02d7e | 1422 | #else |
ddef6bc7 | 1423 | return GEN_INT (offset != WORDS_BIG_ENDIAN |
7529ac93 | 1424 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); |
2fe02d7e | 1425 | #endif |
7529ac93 | 1426 | } |
1632afca | 1427 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1428 | |
1429 | /* Single word float is a little harder, since single- and double-word | |
1430 | values often do not have the same high-order bits. We have already | |
1431 | verified that we want the only defined word of the single-word value. */ | |
1632afca | 1432 | #ifdef REAL_ARITHMETIC |
9847c2f6 | 1433 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1434 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1435 | && GET_CODE (op) == CONST_DOUBLE) |
1436 | { | |
9847c2f6 | 1437 | long l; |
1632afca RS |
1438 | REAL_VALUE_TYPE rv; |
1439 | ||
1440 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1441 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
aa2ae679 | 1442 | |
7cae975e RH |
1443 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1444 | val = l; | |
1445 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
b5a3eb84 | 1446 | |
aa2ae679 JL |
1447 | if (BITS_PER_WORD == 16) |
1448 | { | |
ddef6bc7 | 1449 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) |
7cae975e | 1450 | val >>= 16; |
73de376f | 1451 | val = ((val & 0xffff) ^ 0x8000) - 0x8000; |
aa2ae679 | 1452 | } |
7cae975e RH |
1453 | |
1454 | return GEN_INT (val); | |
1632afca RS |
1455 | } |
1456 | #else | |
23b2ce53 | 1457 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1458 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 | 1459 | || flag_pretend_float) |
e01a2cec | 1460 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
23b2ce53 RS |
1461 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1462 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1463 | && GET_CODE (op) == CONST_DOUBLE) | |
1464 | { | |
1465 | double d; | |
906c4e36 | 1466 | union {float f; HOST_WIDE_INT i; } u; |
23b2ce53 RS |
1467 | |
1468 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1469 | ||
1470 | u.f = d; | |
906c4e36 | 1471 | return GEN_INT (u.i); |
23b2ce53 | 1472 | } |
e01a2cec RK |
1473 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1474 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1475 | || flag_pretend_float) | |
1476 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1477 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1478 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1479 | && GET_CODE (op) == CONST_DOUBLE) | |
1480 | { | |
1481 | double d; | |
1482 | union {double d; HOST_WIDE_INT i; } u; | |
1483 | ||
1484 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1485 | ||
1486 | u.d = d; | |
1487 | return GEN_INT (u.i); | |
1488 | } | |
1632afca | 1489 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1490 | |
1491 | /* The only remaining cases that we can handle are integers. | |
1492 | Convert to proper endianness now since these cases need it. | |
ddef6bc7 | 1493 | At this point, offset == 0 means the low-order word. |
23b2ce53 | 1494 | |
2d4f57f8 RK |
1495 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1496 | in general. However, if OP is (const_int 0), we can just return | |
1497 | it for any word. */ | |
1498 | ||
1499 | if (op == const0_rtx) | |
1500 | return op; | |
23b2ce53 RS |
1501 | |
1502 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1503 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1504 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1505 | return 0; |
1506 | ||
1507 | if (WORDS_BIG_ENDIAN) | |
ddef6bc7 | 1508 | offset = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - offset; |
23b2ce53 RS |
1509 | |
1510 | /* Find out which word on the host machine this value is in and get | |
1511 | it from the constant. */ | |
ddef6bc7 | 1512 | val = (offset / size_ratio == 0 |
23b2ce53 RS |
1513 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) |
1514 | : (GET_CODE (op) == CONST_INT | |
1515 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1516 | ||
3f518020 | 1517 | /* Get the value we want into the low bits of val. */ |
906c4e36 | 1518 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
ddef6bc7 | 1519 | val = ((val >> ((offset % size_ratio) * BITS_PER_WORD))); |
3f518020 | 1520 | |
7e4ce834 | 1521 | val = trunc_int_for_mode (val, word_mode); |
23b2ce53 | 1522 | |
906c4e36 | 1523 | return GEN_INT (val); |
23b2ce53 RS |
1524 | } |
1525 | ||
ddef6bc7 JJ |
1526 | /* Return subword OFFSET of operand OP. |
1527 | The word number, OFFSET, is interpreted as the word number starting | |
1528 | at the low-order address. OFFSET 0 is the low-order word if not | |
1529 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1530 | ||
1531 | If we cannot extract the required word, we return zero. Otherwise, | |
1532 | an rtx corresponding to the requested word will be returned. | |
1533 | ||
1534 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1535 | reload has completed, a valid address will always be returned. After | |
1536 | reload, if a valid address cannot be returned, we return zero. | |
1537 | ||
1538 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1539 | it is the responsibility of the caller. | |
1540 | ||
1541 | MODE is the mode of OP in case it is a CONST_INT. | |
1542 | ||
1543 | ??? This is still rather broken for some cases. The problem for the | |
1544 | moment is that all callers of this thing provide no 'goal mode' to | |
1545 | tell us to work with. This exists because all callers were written | |
1546 | in a word based SUBREG world. */ | |
1547 | ||
1548 | rtx | |
1549 | operand_subword (op, offset, validate_address, mode) | |
1550 | rtx op; | |
1551 | unsigned int offset; | |
1552 | int validate_address; | |
1553 | enum machine_mode mode; | |
1554 | { | |
1555 | if (mode == VOIDmode) | |
1556 | mode = GET_MODE (op); | |
1557 | ||
1558 | if (mode == VOIDmode) | |
1559 | abort (); | |
1560 | ||
1561 | /* If OP is narrower than a word, fail. */ | |
1562 | if (mode != BLKmode | |
1563 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1564 | return 0; | |
1565 | ||
1566 | /* If we want a word outside OP, return zero. */ | |
1567 | if (mode != BLKmode | |
1568 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1569 | return const0_rtx; | |
1570 | ||
1571 | switch (GET_CODE (op)) | |
1572 | { | |
1573 | case REG: | |
1574 | case SUBREG: | |
1575 | case CONCAT: | |
1576 | case MEM: | |
1577 | break; | |
1578 | ||
1579 | default: | |
1580 | /* The only remaining cases are when OP is a constant. If the host and | |
1581 | target floating formats are the same, handling two-word floating | |
1582 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} | |
1583 | are defined as returning one or two 32 bit values, respectively, | |
1584 | and not values of BITS_PER_WORD bits. */ | |
1585 | return constant_subword (op, offset, mode); | |
1586 | } | |
1587 | ||
1588 | /* If OP is already an integer word, return it. */ | |
1589 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1590 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1591 | return op; | |
1592 | ||
1593 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1594 | if (GET_CODE (op) == REG) | |
1595 | { | |
1596 | if (REGNO (op) < FIRST_PSEUDO_REGISTER) | |
1597 | { | |
1598 | int final_regno = REGNO (op) + | |
1599 | subreg_regno_offset (REGNO (op), GET_MODE (op), | |
1600 | offset * UNITS_PER_WORD, | |
1601 | word_mode); | |
1602 | ||
1603 | /* If the register is not valid for MODE, return 0. If we don't | |
1604 | do this, there is no way to fix up the resulting REG later. */ | |
1605 | if (! HARD_REGNO_MODE_OK (final_regno, word_mode)) | |
1606 | return 0; | |
1607 | ||
1608 | /* integrate.c can't handle parts of a return value register. | |
1609 | ??? Then integrate.c should be fixed! | |
1610 | ??? What about CLASS_CANNOT_CHANGE_SIZE? */ | |
1611 | if ((! REG_FUNCTION_VALUE_P (op) | |
1612 | || ! rtx_equal_function_value_matters) | |
1613 | /* ??? What about CLASS_CANNOT_CHANGE_SIZE? */ | |
1614 | /* We want to keep the stack, frame, and arg pointers | |
1615 | special. */ | |
1616 | && op != frame_pointer_rtx | |
1617 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
1618 | && op != arg_pointer_rtx | |
1619 | #endif | |
1620 | && op != stack_pointer_rtx) | |
1621 | return gen_rtx_REG (word_mode, final_regno); | |
1622 | } | |
1623 | ||
1624 | /* Just return a normal SUBREG. */ | |
1625 | return gen_rtx_SUBREG (word_mode, op, | |
1626 | (offset * UNITS_PER_WORD)); | |
1627 | } | |
1628 | else if (GET_CODE (op) == SUBREG) | |
1629 | { | |
1630 | int final_offset = ((offset * UNITS_PER_WORD) + SUBREG_BYTE (op)); | |
1631 | ||
1632 | /* When working with SUBREGs the rule is that the byte | |
1633 | offset must be a multiple of the SUBREG's mode. */ | |
1634 | final_offset = (final_offset / GET_MODE_SIZE (word_mode)); | |
1635 | final_offset = (final_offset * GET_MODE_SIZE (word_mode)); | |
1636 | return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), final_offset); | |
1637 | } | |
1638 | else if (GET_CODE (op) == CONCAT) | |
1639 | { | |
1640 | unsigned int partwords = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1641 | if (offset < partwords) | |
1642 | return operand_subword (XEXP (op, 0), offset, validate_address, mode); | |
1643 | return operand_subword (XEXP (op, 1), offset - partwords, | |
1644 | validate_address, mode); | |
1645 | } | |
1646 | ||
1647 | /* Form a new MEM at the requested address. */ | |
1648 | if (GET_CODE (op) == MEM) | |
1649 | { | |
1650 | rtx addr = plus_constant (XEXP (op, 0), (offset * UNITS_PER_WORD)); | |
1651 | rtx new; | |
1652 | ||
1653 | if (validate_address) | |
1654 | { | |
1655 | if (reload_completed) | |
1656 | { | |
1657 | if (! strict_memory_address_p (word_mode, addr)) | |
1658 | return 0; | |
1659 | } | |
1660 | else | |
1661 | addr = memory_address (word_mode, addr); | |
1662 | } | |
1663 | ||
1664 | new = gen_rtx_MEM (word_mode, addr); | |
1665 | MEM_COPY_ATTRIBUTES (new, op); | |
1666 | return new; | |
1667 | } | |
1668 | ||
1669 | /* Unreachable... (famous last words) */ | |
1670 | abort (); | |
1671 | } | |
1672 | ||
23b2ce53 RS |
1673 | /* Similar to `operand_subword', but never return 0. If we can't extract |
1674 | the required subword, put OP into a register and try again. If that fails, | |
ddef6bc7 | 1675 | abort. We always validate the address in this case. |
23b2ce53 RS |
1676 | |
1677 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1678 | ||
1679 | rtx | |
ddef6bc7 | 1680 | operand_subword_force (op, offset, mode) |
23b2ce53 | 1681 | rtx op; |
ddef6bc7 | 1682 | unsigned int offset; |
23b2ce53 RS |
1683 | enum machine_mode mode; |
1684 | { | |
ddef6bc7 | 1685 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1686 | |
1687 | if (result) | |
1688 | return result; | |
1689 | ||
1690 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1691 | { |
1692 | /* If this is a register which can not be accessed by words, copy it | |
1693 | to a pseudo register. */ | |
1694 | if (GET_CODE (op) == REG) | |
1695 | op = copy_to_reg (op); | |
1696 | else | |
1697 | op = force_reg (mode, op); | |
1698 | } | |
23b2ce53 | 1699 | |
ddef6bc7 | 1700 | result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1701 | if (result == 0) |
1702 | abort (); | |
1703 | ||
1704 | return result; | |
1705 | } | |
1706 | \f | |
1707 | /* Given a compare instruction, swap the operands. | |
1708 | A test instruction is changed into a compare of 0 against the operand. */ | |
1709 | ||
1710 | void | |
1711 | reverse_comparison (insn) | |
1712 | rtx insn; | |
1713 | { | |
1714 | rtx body = PATTERN (insn); | |
1715 | rtx comp; | |
1716 | ||
1717 | if (GET_CODE (body) == SET) | |
1718 | comp = SET_SRC (body); | |
1719 | else | |
1720 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1721 | ||
1722 | if (GET_CODE (comp) == COMPARE) | |
1723 | { | |
1724 | rtx op0 = XEXP (comp, 0); | |
1725 | rtx op1 = XEXP (comp, 1); | |
1726 | XEXP (comp, 0) = op1; | |
1727 | XEXP (comp, 1) = op0; | |
1728 | } | |
1729 | else | |
1730 | { | |
c5c76735 JL |
1731 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1732 | CONST0_RTX (GET_MODE (comp)), comp); | |
23b2ce53 RS |
1733 | if (GET_CODE (body) == SET) |
1734 | SET_SRC (body) = new; | |
1735 | else | |
1736 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1737 | } | |
1738 | } | |
1739 | \f | |
1740 | /* Return a memory reference like MEMREF, but with its mode changed | |
1741 | to MODE and its address changed to ADDR. | |
1742 | (VOIDmode means don't change the mode. | |
1743 | NULL for ADDR means don't change the address.) */ | |
1744 | ||
1745 | rtx | |
1746 | change_address (memref, mode, addr) | |
1747 | rtx memref; | |
1748 | enum machine_mode mode; | |
1749 | rtx addr; | |
1750 | { | |
1751 | rtx new; | |
1752 | ||
1753 | if (GET_CODE (memref) != MEM) | |
1754 | abort (); | |
1755 | if (mode == VOIDmode) | |
1756 | mode = GET_MODE (memref); | |
1757 | if (addr == 0) | |
1758 | addr = XEXP (memref, 0); | |
1759 | ||
1760 | /* If reload is in progress or has completed, ADDR must be valid. | |
1761 | Otherwise, we can call memory_address to make it valid. */ | |
1762 | if (reload_completed || reload_in_progress) | |
1763 | { | |
1764 | if (! memory_address_p (mode, addr)) | |
1765 | abort (); | |
1766 | } | |
1767 | else | |
1768 | addr = memory_address (mode, addr); | |
1769 | ||
9b04c6a8 RK |
1770 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1771 | return memref; | |
1772 | ||
3b80f6ca | 1773 | new = gen_rtx_MEM (mode, addr); |
c6df88cb | 1774 | MEM_COPY_ATTRIBUTES (new, memref); |
23b2ce53 RS |
1775 | return new; |
1776 | } | |
1777 | \f | |
1778 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1779 | ||
1780 | rtx | |
1781 | gen_label_rtx () | |
1782 | { | |
ca695ac9 JB |
1783 | register rtx label; |
1784 | ||
b93a436e | 1785 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
9714cf43 | 1786 | NULL_RTX, label_num++, NULL, NULL); |
ca695ac9 | 1787 | |
23b2ce53 | 1788 | LABEL_NUSES (label) = 0; |
8cd0faaf | 1789 | LABEL_ALTERNATE_NAME (label) = NULL; |
23b2ce53 RS |
1790 | return label; |
1791 | } | |
1792 | \f | |
1793 | /* For procedure integration. */ | |
1794 | ||
23b2ce53 | 1795 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 1796 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
1797 | Used for an inline-procedure after copying the insn chain. */ |
1798 | ||
1799 | void | |
1800 | set_new_first_and_last_insn (first, last) | |
1801 | rtx first, last; | |
1802 | { | |
86fe05e0 RK |
1803 | rtx insn; |
1804 | ||
23b2ce53 RS |
1805 | first_insn = first; |
1806 | last_insn = last; | |
86fe05e0 RK |
1807 | cur_insn_uid = 0; |
1808 | ||
1809 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1810 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1811 | ||
1812 | cur_insn_uid++; | |
23b2ce53 RS |
1813 | } |
1814 | ||
1815 | /* Set the range of label numbers found in the current function. | |
1816 | This is used when belatedly compiling an inline function. */ | |
1817 | ||
1818 | void | |
1819 | set_new_first_and_last_label_num (first, last) | |
1820 | int first, last; | |
1821 | { | |
1822 | base_label_num = label_num; | |
1823 | first_label_num = first; | |
1824 | last_label_num = last; | |
1825 | } | |
49ad7cfa BS |
1826 | |
1827 | /* Set the last label number found in the current function. | |
1828 | This is used when belatedly compiling an inline function. */ | |
23b2ce53 RS |
1829 | |
1830 | void | |
49ad7cfa BS |
1831 | set_new_last_label_num (last) |
1832 | int last; | |
23b2ce53 | 1833 | { |
49ad7cfa BS |
1834 | base_label_num = label_num; |
1835 | last_label_num = last; | |
23b2ce53 | 1836 | } |
49ad7cfa | 1837 | \f |
23b2ce53 RS |
1838 | /* Restore all variables describing the current status from the structure *P. |
1839 | This is used after a nested function. */ | |
1840 | ||
1841 | void | |
1842 | restore_emit_status (p) | |
272df862 | 1843 | struct function *p ATTRIBUTE_UNUSED; |
23b2ce53 | 1844 | { |
457a2d9c | 1845 | last_label_num = 0; |
49ad7cfa | 1846 | clear_emit_caches (); |
23b2ce53 | 1847 | } |
e2ecd91c | 1848 | |
21cd906e | 1849 | /* Clear out all parts of the state in F that can safely be discarded |
e2ecd91c | 1850 | after the function has been compiled, to let garbage collection |
0a8a198c | 1851 | reclaim the memory. */ |
21cd906e | 1852 | |
e2ecd91c | 1853 | void |
0a8a198c | 1854 | free_emit_status (f) |
e2ecd91c BS |
1855 | struct function *f; |
1856 | { | |
1857 | free (f->emit->x_regno_reg_rtx); | |
e2ecd91c | 1858 | free (f->emit->regno_pointer_align); |
fa51b01b RH |
1859 | free (f->emit); |
1860 | f->emit = NULL; | |
e2ecd91c | 1861 | } |
23b2ce53 | 1862 | \f |
d1b81779 GK |
1863 | /* Go through all the RTL insn bodies and copy any invalid shared |
1864 | structure. This routine should only be called once. */ | |
23b2ce53 RS |
1865 | |
1866 | void | |
d1b81779 GK |
1867 | unshare_all_rtl (fndecl, insn) |
1868 | tree fndecl; | |
1869 | rtx insn; | |
23b2ce53 | 1870 | { |
d1b81779 | 1871 | tree decl; |
23b2ce53 | 1872 | |
d1b81779 GK |
1873 | /* Make sure that virtual parameters are not shared. */ |
1874 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
19e7881c | 1875 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); |
d1b81779 | 1876 | |
5c6df058 AO |
1877 | /* Make sure that virtual stack slots are not shared. */ |
1878 | unshare_all_decls (DECL_INITIAL (fndecl)); | |
1879 | ||
d1b81779 GK |
1880 | /* Unshare just about everything else. */ |
1881 | unshare_all_rtl_1 (insn); | |
1882 | ||
23b2ce53 RS |
1883 | /* Make sure the addresses of stack slots found outside the insn chain |
1884 | (such as, in DECL_RTL of a variable) are not shared | |
1885 | with the insn chain. | |
1886 | ||
1887 | This special care is necessary when the stack slot MEM does not | |
1888 | actually appear in the insn chain. If it does appear, its address | |
1889 | is unshared from all else at that point. */ | |
242b0ce6 | 1890 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
1891 | } |
1892 | ||
d1b81779 GK |
1893 | /* Go through all the RTL insn bodies and copy any invalid shared |
1894 | structure, again. This is a fairly expensive thing to do so it | |
1895 | should be done sparingly. */ | |
1896 | ||
1897 | void | |
1898 | unshare_all_rtl_again (insn) | |
1899 | rtx insn; | |
1900 | { | |
1901 | rtx p; | |
624c87aa RE |
1902 | tree decl; |
1903 | ||
d1b81779 | 1904 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 1905 | if (INSN_P (p)) |
d1b81779 GK |
1906 | { |
1907 | reset_used_flags (PATTERN (p)); | |
1908 | reset_used_flags (REG_NOTES (p)); | |
1909 | reset_used_flags (LOG_LINKS (p)); | |
1910 | } | |
624c87aa | 1911 | |
2d4aecb3 AO |
1912 | /* Make sure that virtual stack slots are not shared. */ |
1913 | reset_used_decls (DECL_INITIAL (cfun->decl)); | |
1914 | ||
624c87aa RE |
1915 | /* Make sure that virtual parameters are not shared. */ |
1916 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
1917 | reset_used_flags (DECL_RTL (decl)); | |
1918 | ||
1919 | reset_used_flags (stack_slot_list); | |
1920 | ||
1921 | unshare_all_rtl (cfun->decl, insn); | |
d1b81779 GK |
1922 | } |
1923 | ||
1924 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1925 | Assumes the mark bits are cleared at entry. */ | |
1926 | ||
1927 | static void | |
1928 | unshare_all_rtl_1 (insn) | |
1929 | rtx insn; | |
1930 | { | |
1931 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1932 | if (INSN_P (insn)) |
d1b81779 GK |
1933 | { |
1934 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1935 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1936 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1937 | } | |
1938 | } | |
1939 | ||
5c6df058 AO |
1940 | /* Go through all virtual stack slots of a function and copy any |
1941 | shared structure. */ | |
1942 | static void | |
1943 | unshare_all_decls (blk) | |
1944 | tree blk; | |
1945 | { | |
1946 | tree t; | |
1947 | ||
1948 | /* Copy shared decls. */ | |
1949 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c MM |
1950 | if (DECL_RTL_SET_P (t)) |
1951 | SET_DECL_RTL (t, copy_rtx_if_shared (DECL_RTL (t))); | |
5c6df058 AO |
1952 | |
1953 | /* Now process sub-blocks. */ | |
1954 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1955 | unshare_all_decls (t); | |
1956 | } | |
1957 | ||
2d4aecb3 AO |
1958 | /* Go through all virtual stack slots of a function and mark them as |
1959 | not shared. */ | |
1960 | static void | |
1961 | reset_used_decls (blk) | |
1962 | tree blk; | |
1963 | { | |
1964 | tree t; | |
1965 | ||
1966 | /* Mark decls. */ | |
1967 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c MM |
1968 | if (DECL_RTL_SET_P (t)) |
1969 | reset_used_flags (DECL_RTL (t)); | |
2d4aecb3 AO |
1970 | |
1971 | /* Now process sub-blocks. */ | |
1972 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
1973 | reset_used_decls (t); | |
1974 | } | |
1975 | ||
23b2ce53 RS |
1976 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1977 | Recursively does the same for subexpressions. */ | |
1978 | ||
1979 | rtx | |
1980 | copy_rtx_if_shared (orig) | |
1981 | rtx orig; | |
1982 | { | |
1983 | register rtx x = orig; | |
1984 | register int i; | |
1985 | register enum rtx_code code; | |
6f7d635c | 1986 | register const char *format_ptr; |
23b2ce53 RS |
1987 | int copied = 0; |
1988 | ||
1989 | if (x == 0) | |
1990 | return 0; | |
1991 | ||
1992 | code = GET_CODE (x); | |
1993 | ||
1994 | /* These types may be freely shared. */ | |
1995 | ||
1996 | switch (code) | |
1997 | { | |
1998 | case REG: | |
1999 | case QUEUED: | |
2000 | case CONST_INT: | |
2001 | case CONST_DOUBLE: | |
2002 | case SYMBOL_REF: | |
2003 | case CODE_LABEL: | |
2004 | case PC: | |
2005 | case CC0: | |
2006 | case SCRATCH: | |
0f41302f | 2007 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
2008 | return x; |
2009 | ||
b851ea09 RK |
2010 | case CONST: |
2011 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
2012 | a LABEL_REF, it isn't sharable. */ | |
2013 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2014 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2015 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
2016 | return x; | |
2017 | break; | |
2018 | ||
23b2ce53 RS |
2019 | case INSN: |
2020 | case JUMP_INSN: | |
2021 | case CALL_INSN: | |
2022 | case NOTE: | |
23b2ce53 RS |
2023 | case BARRIER: |
2024 | /* The chain of insns is not being copied. */ | |
2025 | return x; | |
2026 | ||
2027 | case MEM: | |
83512665 JL |
2028 | /* A MEM is allowed to be shared if its address is constant. |
2029 | ||
2030 | We used to allow sharing of MEMs which referenced | |
2031 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but | |
2032 | that can lose. instantiate_virtual_regs will not unshare | |
2033 | the MEMs, and combine may change the structure of the address | |
2034 | because it looks safe and profitable in one context, but | |
2035 | in some other context it creates unrecognizable RTL. */ | |
2036 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
23b2ce53 RS |
2037 | return x; |
2038 | ||
e9a25f70 JL |
2039 | break; |
2040 | ||
2041 | default: | |
2042 | break; | |
23b2ce53 RS |
2043 | } |
2044 | ||
2045 | /* This rtx may not be shared. If it has already been seen, | |
2046 | replace it with a copy of itself. */ | |
2047 | ||
2048 | if (x->used) | |
2049 | { | |
2050 | register rtx copy; | |
2051 | ||
2052 | copy = rtx_alloc (code); | |
4e135bdd | 2053 | memcpy (copy, x, |
4c9a05bc RK |
2054 | (sizeof (*copy) - sizeof (copy->fld) |
2055 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
2056 | x = copy; |
2057 | copied = 1; | |
2058 | } | |
2059 | x->used = 1; | |
2060 | ||
2061 | /* Now scan the subexpressions recursively. | |
2062 | We can store any replaced subexpressions directly into X | |
2063 | since we know X is not shared! Any vectors in X | |
2064 | must be copied if X was copied. */ | |
2065 | ||
2066 | format_ptr = GET_RTX_FORMAT (code); | |
2067 | ||
2068 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2069 | { | |
2070 | switch (*format_ptr++) | |
2071 | { | |
2072 | case 'e': | |
2073 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
2074 | break; | |
2075 | ||
2076 | case 'E': | |
2077 | if (XVEC (x, i) != NULL) | |
2078 | { | |
2079 | register int j; | |
f0722107 | 2080 | int len = XVECLEN (x, i); |
23b2ce53 | 2081 | |
f0722107 | 2082 | if (copied && len > 0) |
8f985ec4 | 2083 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
f0722107 RS |
2084 | for (j = 0; j < len; j++) |
2085 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
2086 | } |
2087 | break; | |
2088 | } | |
2089 | } | |
2090 | return x; | |
2091 | } | |
2092 | ||
2093 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2094 | to look for shared sub-parts. */ | |
2095 | ||
2096 | void | |
2097 | reset_used_flags (x) | |
2098 | rtx x; | |
2099 | { | |
2100 | register int i, j; | |
2101 | register enum rtx_code code; | |
6f7d635c | 2102 | register const char *format_ptr; |
23b2ce53 RS |
2103 | |
2104 | if (x == 0) | |
2105 | return; | |
2106 | ||
2107 | code = GET_CODE (x); | |
2108 | ||
9faa82d8 | 2109 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2110 | for them. */ |
2111 | ||
2112 | switch (code) | |
2113 | { | |
2114 | case REG: | |
2115 | case QUEUED: | |
2116 | case CONST_INT: | |
2117 | case CONST_DOUBLE: | |
2118 | case SYMBOL_REF: | |
2119 | case CODE_LABEL: | |
2120 | case PC: | |
2121 | case CC0: | |
2122 | return; | |
2123 | ||
2124 | case INSN: | |
2125 | case JUMP_INSN: | |
2126 | case CALL_INSN: | |
2127 | case NOTE: | |
2128 | case LABEL_REF: | |
2129 | case BARRIER: | |
2130 | /* The chain of insns is not being copied. */ | |
2131 | return; | |
e9a25f70 JL |
2132 | |
2133 | default: | |
2134 | break; | |
23b2ce53 RS |
2135 | } |
2136 | ||
2137 | x->used = 0; | |
2138 | ||
2139 | format_ptr = GET_RTX_FORMAT (code); | |
2140 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2141 | { | |
2142 | switch (*format_ptr++) | |
2143 | { | |
2144 | case 'e': | |
2145 | reset_used_flags (XEXP (x, i)); | |
2146 | break; | |
2147 | ||
2148 | case 'E': | |
2149 | for (j = 0; j < XVECLEN (x, i); j++) | |
2150 | reset_used_flags (XVECEXP (x, i, j)); | |
2151 | break; | |
2152 | } | |
2153 | } | |
2154 | } | |
2155 | \f | |
2156 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2157 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2158 | OTHER must be valid as a SET_DEST. */ | |
2159 | ||
2160 | rtx | |
2161 | make_safe_from (x, other) | |
2162 | rtx x, other; | |
2163 | { | |
2164 | while (1) | |
2165 | switch (GET_CODE (other)) | |
2166 | { | |
2167 | case SUBREG: | |
2168 | other = SUBREG_REG (other); | |
2169 | break; | |
2170 | case STRICT_LOW_PART: | |
2171 | case SIGN_EXTEND: | |
2172 | case ZERO_EXTEND: | |
2173 | other = XEXP (other, 0); | |
2174 | break; | |
2175 | default: | |
2176 | goto done; | |
2177 | } | |
2178 | done: | |
2179 | if ((GET_CODE (other) == MEM | |
2180 | && ! CONSTANT_P (x) | |
2181 | && GET_CODE (x) != REG | |
2182 | && GET_CODE (x) != SUBREG) | |
2183 | || (GET_CODE (other) == REG | |
2184 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
2185 | || reg_mentioned_p (other, x)))) | |
2186 | { | |
2187 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2188 | emit_move_insn (temp, x); | |
2189 | return temp; | |
2190 | } | |
2191 | return x; | |
2192 | } | |
2193 | \f | |
2194 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2195 | ||
2196 | /* Return the first insn of the current sequence or current function. */ | |
2197 | ||
2198 | rtx | |
2199 | get_insns () | |
2200 | { | |
2201 | return first_insn; | |
2202 | } | |
2203 | ||
2204 | /* Return the last insn emitted in current sequence or current function. */ | |
2205 | ||
2206 | rtx | |
2207 | get_last_insn () | |
2208 | { | |
2209 | return last_insn; | |
2210 | } | |
2211 | ||
2212 | /* Specify a new insn as the last in the chain. */ | |
2213 | ||
2214 | void | |
2215 | set_last_insn (insn) | |
2216 | rtx insn; | |
2217 | { | |
2218 | if (NEXT_INSN (insn) != 0) | |
2219 | abort (); | |
2220 | last_insn = insn; | |
2221 | } | |
2222 | ||
2223 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2224 | ||
2225 | rtx | |
2226 | get_last_insn_anywhere () | |
2227 | { | |
2228 | struct sequence_stack *stack; | |
2229 | if (last_insn) | |
2230 | return last_insn; | |
49ad7cfa | 2231 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2232 | if (stack->last != 0) |
2233 | return stack->last; | |
2234 | return 0; | |
2235 | } | |
2236 | ||
2237 | /* Return a number larger than any instruction's uid in this function. */ | |
2238 | ||
2239 | int | |
2240 | get_max_uid () | |
2241 | { | |
2242 | return cur_insn_uid; | |
2243 | } | |
aeeeda03 | 2244 | |
673b5311 MM |
2245 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2246 | ||
aeeeda03 | 2247 | void |
673b5311 MM |
2248 | renumber_insns (stream) |
2249 | FILE *stream; | |
aeeeda03 MM |
2250 | { |
2251 | rtx insn; | |
aeeeda03 | 2252 | |
673b5311 MM |
2253 | /* If we're not supposed to renumber instructions, don't. */ |
2254 | if (!flag_renumber_insns) | |
2255 | return; | |
2256 | ||
aeeeda03 MM |
2257 | /* If there aren't that many instructions, then it's not really |
2258 | worth renumbering them. */ | |
673b5311 | 2259 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
aeeeda03 MM |
2260 | return; |
2261 | ||
2262 | cur_insn_uid = 1; | |
2263 | ||
2264 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
673b5311 MM |
2265 | { |
2266 | if (stream) | |
2267 | fprintf (stream, "Renumbering insn %d to %d\n", | |
2268 | INSN_UID (insn), cur_insn_uid); | |
2269 | INSN_UID (insn) = cur_insn_uid++; | |
2270 | } | |
aeeeda03 | 2271 | } |
23b2ce53 RS |
2272 | \f |
2273 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2274 | of the sequence. */ | |
2275 | ||
2276 | rtx | |
2277 | next_insn (insn) | |
2278 | rtx insn; | |
2279 | { | |
2280 | if (insn) | |
2281 | { | |
2282 | insn = NEXT_INSN (insn); | |
2283 | if (insn && GET_CODE (insn) == INSN | |
2284 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2285 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2286 | } | |
2287 | ||
2288 | return insn; | |
2289 | } | |
2290 | ||
2291 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2292 | of the sequence. */ | |
2293 | ||
2294 | rtx | |
2295 | previous_insn (insn) | |
2296 | rtx insn; | |
2297 | { | |
2298 | if (insn) | |
2299 | { | |
2300 | insn = PREV_INSN (insn); | |
2301 | if (insn && GET_CODE (insn) == INSN | |
2302 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2303 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2304 | } | |
2305 | ||
2306 | return insn; | |
2307 | } | |
2308 | ||
2309 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2310 | look inside SEQUENCEs. */ | |
2311 | ||
2312 | rtx | |
2313 | next_nonnote_insn (insn) | |
2314 | rtx insn; | |
2315 | { | |
2316 | while (insn) | |
2317 | { | |
2318 | insn = NEXT_INSN (insn); | |
2319 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2320 | break; | |
2321 | } | |
2322 | ||
2323 | return insn; | |
2324 | } | |
2325 | ||
2326 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2327 | not look inside SEQUENCEs. */ | |
2328 | ||
2329 | rtx | |
2330 | prev_nonnote_insn (insn) | |
2331 | rtx insn; | |
2332 | { | |
2333 | while (insn) | |
2334 | { | |
2335 | insn = PREV_INSN (insn); | |
2336 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2337 | break; | |
2338 | } | |
2339 | ||
2340 | return insn; | |
2341 | } | |
2342 | ||
2343 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2344 | or 0, if there is none. This routine does not look inside | |
0f41302f | 2345 | SEQUENCEs. */ |
23b2ce53 RS |
2346 | |
2347 | rtx | |
2348 | next_real_insn (insn) | |
2349 | rtx insn; | |
2350 | { | |
2351 | while (insn) | |
2352 | { | |
2353 | insn = NEXT_INSN (insn); | |
2354 | if (insn == 0 || GET_CODE (insn) == INSN | |
2355 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2356 | break; | |
2357 | } | |
2358 | ||
2359 | return insn; | |
2360 | } | |
2361 | ||
2362 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2363 | or 0, if there is none. This routine does not look inside | |
2364 | SEQUENCEs. */ | |
2365 | ||
2366 | rtx | |
2367 | prev_real_insn (insn) | |
2368 | rtx insn; | |
2369 | { | |
2370 | while (insn) | |
2371 | { | |
2372 | insn = PREV_INSN (insn); | |
2373 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2374 | || GET_CODE (insn) == JUMP_INSN) | |
2375 | break; | |
2376 | } | |
2377 | ||
2378 | return insn; | |
2379 | } | |
2380 | ||
2381 | /* Find the next insn after INSN that really does something. This routine | |
2382 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2383 | same as next_real_insn. */ | |
2384 | ||
69732dcb RH |
2385 | int |
2386 | active_insn_p (insn) | |
2387 | rtx insn; | |
2388 | { | |
2389 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2390 | || (GET_CODE (insn) == INSN | |
2391 | && (! reload_completed | |
2392 | || (GET_CODE (PATTERN (insn)) != USE | |
2393 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2394 | } | |
2395 | ||
23b2ce53 RS |
2396 | rtx |
2397 | next_active_insn (insn) | |
2398 | rtx insn; | |
2399 | { | |
2400 | while (insn) | |
2401 | { | |
2402 | insn = NEXT_INSN (insn); | |
69732dcb | 2403 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2404 | break; |
2405 | } | |
2406 | ||
2407 | return insn; | |
2408 | } | |
2409 | ||
2410 | /* Find the last insn before INSN that really does something. This routine | |
2411 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2412 | same as prev_real_insn. */ | |
2413 | ||
2414 | rtx | |
2415 | prev_active_insn (insn) | |
2416 | rtx insn; | |
2417 | { | |
2418 | while (insn) | |
2419 | { | |
2420 | insn = PREV_INSN (insn); | |
69732dcb | 2421 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2422 | break; |
2423 | } | |
2424 | ||
2425 | return insn; | |
2426 | } | |
2427 | ||
2428 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2429 | ||
2430 | rtx | |
2431 | next_label (insn) | |
2432 | rtx insn; | |
2433 | { | |
2434 | while (insn) | |
2435 | { | |
2436 | insn = NEXT_INSN (insn); | |
2437 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2438 | break; | |
2439 | } | |
2440 | ||
2441 | return insn; | |
2442 | } | |
2443 | ||
2444 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2445 | ||
2446 | rtx | |
2447 | prev_label (insn) | |
2448 | rtx insn; | |
2449 | { | |
2450 | while (insn) | |
2451 | { | |
2452 | insn = PREV_INSN (insn); | |
2453 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2454 | break; | |
2455 | } | |
2456 | ||
2457 | return insn; | |
2458 | } | |
2459 | \f | |
2460 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
2461 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2462 | and REG_CC_USER notes so we can find it. */ | |
2463 | ||
2464 | void | |
2465 | link_cc0_insns (insn) | |
2466 | rtx insn; | |
2467 | { | |
2468 | rtx user = next_nonnote_insn (insn); | |
2469 | ||
2470 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2471 | user = XVECEXP (PATTERN (user), 0, 0); | |
2472 | ||
c5c76735 JL |
2473 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2474 | REG_NOTES (user)); | |
3b80f6ca | 2475 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
2476 | } |
2477 | ||
23b2ce53 RS |
2478 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2479 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2480 | applied to the result of this function should yield INSN). | |
2481 | ||
2482 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2483 | is present, it contains the insn that uses CC0. | |
2484 | ||
2485 | Return 0 if we can't find the insn. */ | |
2486 | ||
2487 | rtx | |
2488 | next_cc0_user (insn) | |
2489 | rtx insn; | |
2490 | { | |
906c4e36 | 2491 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
2492 | |
2493 | if (note) | |
2494 | return XEXP (note, 0); | |
2495 | ||
2496 | insn = next_nonnote_insn (insn); | |
2497 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2498 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2499 | ||
2c3c49de | 2500 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
2501 | return insn; |
2502 | ||
2503 | return 0; | |
2504 | } | |
2505 | ||
2506 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2507 | note, it is the previous insn. */ | |
2508 | ||
2509 | rtx | |
2510 | prev_cc0_setter (insn) | |
2511 | rtx insn; | |
2512 | { | |
906c4e36 | 2513 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
2514 | |
2515 | if (note) | |
2516 | return XEXP (note, 0); | |
2517 | ||
2518 | insn = prev_nonnote_insn (insn); | |
2519 | if (! sets_cc0_p (PATTERN (insn))) | |
2520 | abort (); | |
2521 | ||
2522 | return insn; | |
2523 | } | |
2524 | #endif | |
e5bef2e4 HB |
2525 | |
2526 | /* Increment the label uses for all labels present in rtx. */ | |
2527 | ||
2528 | static void | |
2529 | mark_label_nuses(x) | |
2530 | rtx x; | |
2531 | { | |
2532 | register enum rtx_code code; | |
2533 | register int i, j; | |
2534 | register const char *fmt; | |
2535 | ||
2536 | code = GET_CODE (x); | |
2537 | if (code == LABEL_REF) | |
2538 | LABEL_NUSES (XEXP (x, 0))++; | |
2539 | ||
2540 | fmt = GET_RTX_FORMAT (code); | |
2541 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2542 | { | |
2543 | if (fmt[i] == 'e') | |
2544 | mark_label_nuses (XEXP (x, i)); | |
2545 | else if (fmt[i] == 'E') | |
2546 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2547 | mark_label_nuses (XVECEXP (x, i, j)); | |
2548 | } | |
2549 | } | |
2550 | ||
23b2ce53 RS |
2551 | \f |
2552 | /* Try splitting insns that can be split for better scheduling. | |
2553 | PAT is the pattern which might split. | |
2554 | TRIAL is the insn providing PAT. | |
11147ebe | 2555 | LAST is non-zero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
2556 | |
2557 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 2558 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
2559 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2560 | ||
2561 | rtx | |
11147ebe | 2562 | try_split (pat, trial, last) |
23b2ce53 | 2563 | rtx pat, trial; |
11147ebe | 2564 | int last; |
23b2ce53 RS |
2565 | { |
2566 | rtx before = PREV_INSN (trial); | |
2567 | rtx after = NEXT_INSN (trial); | |
2568 | rtx seq = split_insns (pat, trial); | |
2569 | int has_barrier = 0; | |
2570 | rtx tem; | |
2571 | ||
2572 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2573 | We may need to handle this specially. */ | |
2574 | if (after && GET_CODE (after) == BARRIER) | |
2575 | { | |
2576 | has_barrier = 1; | |
2577 | after = NEXT_INSN (after); | |
2578 | } | |
2579 | ||
2580 | if (seq) | |
2581 | { | |
2582 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2583 | The latter case will normally arise only when being done so that | |
2584 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2585 | if (GET_CODE (seq) == SEQUENCE) | |
2586 | { | |
4b5e8abe | 2587 | int i; |
d6e95df8 AH |
2588 | rtx eh_note; |
2589 | ||
4b5e8abe CP |
2590 | /* Avoid infinite loop if any insn of the result matches |
2591 | the original pattern. */ | |
2592 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2593 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN | |
2594 | && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat)) | |
2595 | return trial; | |
2596 | ||
90a74703 JH |
2597 | /* Mark labels. */ |
2598 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2599 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2600 | mark_jump_label (PATTERN (XVECEXP (seq, 0, i)), | |
2601 | XVECEXP (seq, 0, i), 0, 0); | |
23b2ce53 | 2602 | |
2d01e445 AO |
2603 | /* If we are splitting a CALL_INSN, look for the CALL_INSN |
2604 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
2605 | if (GET_CODE (trial) == CALL_INSN) | |
2606 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2607 | if (GET_CODE (XVECEXP (seq, 0, i)) == CALL_INSN) | |
2608 | CALL_INSN_FUNCTION_USAGE (XVECEXP (seq, 0, i)) | |
2609 | = CALL_INSN_FUNCTION_USAGE (trial); | |
2610 | ||
d6e95df8 AH |
2611 | /* Copy EH notes. */ |
2612 | if ((eh_note = find_reg_note (trial, REG_EH_REGION, NULL_RTX))) | |
2613 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2614 | { | |
2615 | rtx insn = XVECEXP (seq, 0, i); | |
2616 | if (GET_CODE (insn) == CALL_INSN | |
2617 | || (flag_non_call_exceptions | |
2618 | && may_trap_p (PATTERN (insn)))) | |
2619 | REG_NOTES (insn) | |
2620 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), | |
2621 | REG_NOTES (insn)); | |
2622 | } | |
2623 | ||
e5bef2e4 HB |
2624 | /* If there are LABELS inside the split insns increment the |
2625 | usage count so we don't delete the label. */ | |
2626 | if (GET_CODE (trial) == INSN) | |
2627 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2628 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN) | |
2629 | mark_label_nuses (PATTERN (XVECEXP (seq, 0, i))); | |
2630 | ||
23b2ce53 RS |
2631 | tem = emit_insn_after (seq, before); |
2632 | ||
2633 | delete_insn (trial); | |
2634 | if (has_barrier) | |
2635 | emit_barrier_after (tem); | |
11147ebe RK |
2636 | |
2637 | /* Recursively call try_split for each new insn created; by the | |
2638 | time control returns here that insn will be fully split, so | |
2639 | set LAST and continue from the insn after the one returned. | |
f4a3cd05 | 2640 | We can't use next_active_insn here since AFTER may be a note. |
23886015 | 2641 | Ignore deleted insns, which can be occur if not optimizing. */ |
2c3c49de RB |
2642 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) |
2643 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
f4a3cd05 | 2644 | tem = try_split (PATTERN (tem), tem, 1); |
23b2ce53 RS |
2645 | } |
2646 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2647 | else if (rtx_equal_p (seq, pat)) | |
2648 | return trial; | |
2649 | else | |
2650 | { | |
2651 | PATTERN (trial) = seq; | |
2652 | INSN_CODE (trial) = -1; | |
11147ebe | 2653 | try_split (seq, trial, last); |
23b2ce53 RS |
2654 | } |
2655 | ||
11147ebe RK |
2656 | /* Return either the first or the last insn, depending on which was |
2657 | requested. */ | |
ba52f355 CP |
2658 | return last |
2659 | ? (after ? prev_active_insn (after) : last_insn) | |
2660 | : next_active_insn (before); | |
23b2ce53 RS |
2661 | } |
2662 | ||
2663 | return trial; | |
2664 | } | |
2665 | \f | |
2666 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 2667 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
2668 | |
2669 | rtx | |
4b1f5e8c | 2670 | make_insn_raw (pattern) |
23b2ce53 | 2671 | rtx pattern; |
23b2ce53 RS |
2672 | { |
2673 | register rtx insn; | |
2674 | ||
1f8f4a0b | 2675 | insn = rtx_alloc (INSN); |
23b2ce53 | 2676 | |
43127294 | 2677 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2678 | PATTERN (insn) = pattern; |
2679 | INSN_CODE (insn) = -1; | |
1632afca RS |
2680 | LOG_LINKS (insn) = NULL; |
2681 | REG_NOTES (insn) = NULL; | |
23b2ce53 | 2682 | |
47984720 NC |
2683 | #ifdef ENABLE_RTL_CHECKING |
2684 | if (insn | |
2c3c49de | 2685 | && INSN_P (insn) |
47984720 NC |
2686 | && (returnjump_p (insn) |
2687 | || (GET_CODE (insn) == SET | |
2688 | && SET_DEST (insn) == pc_rtx))) | |
2689 | { | |
2690 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2691 | debug_rtx (insn); | |
2692 | } | |
2693 | #endif | |
2694 | ||
23b2ce53 RS |
2695 | return insn; |
2696 | } | |
2697 | ||
2698 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2699 | ||
2700 | static rtx | |
4b1f5e8c | 2701 | make_jump_insn_raw (pattern) |
23b2ce53 | 2702 | rtx pattern; |
23b2ce53 RS |
2703 | { |
2704 | register rtx insn; | |
2705 | ||
4b1f5e8c | 2706 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 2707 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2708 | |
2709 | PATTERN (insn) = pattern; | |
2710 | INSN_CODE (insn) = -1; | |
1632afca RS |
2711 | LOG_LINKS (insn) = NULL; |
2712 | REG_NOTES (insn) = NULL; | |
2713 | JUMP_LABEL (insn) = NULL; | |
23b2ce53 RS |
2714 | |
2715 | return insn; | |
2716 | } | |
aff507f4 RK |
2717 | |
2718 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2719 | ||
2720 | static rtx | |
2721 | make_call_insn_raw (pattern) | |
2722 | rtx pattern; | |
2723 | { | |
2724 | register rtx insn; | |
2725 | ||
2726 | insn = rtx_alloc (CALL_INSN); | |
2727 | INSN_UID (insn) = cur_insn_uid++; | |
2728 | ||
2729 | PATTERN (insn) = pattern; | |
2730 | INSN_CODE (insn) = -1; | |
2731 | LOG_LINKS (insn) = NULL; | |
2732 | REG_NOTES (insn) = NULL; | |
2733 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2734 | ||
2735 | return insn; | |
2736 | } | |
23b2ce53 RS |
2737 | \f |
2738 | /* Add INSN to the end of the doubly-linked list. | |
2739 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2740 | ||
2741 | void | |
2742 | add_insn (insn) | |
2743 | register rtx insn; | |
2744 | { | |
2745 | PREV_INSN (insn) = last_insn; | |
2746 | NEXT_INSN (insn) = 0; | |
2747 | ||
2748 | if (NULL != last_insn) | |
2749 | NEXT_INSN (last_insn) = insn; | |
2750 | ||
2751 | if (NULL == first_insn) | |
2752 | first_insn = insn; | |
2753 | ||
2754 | last_insn = insn; | |
2755 | } | |
2756 | ||
a0ae8e8d RK |
2757 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2758 | the next should be the only functions called to insert an insn once | |
ba213285 | 2759 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 2760 | SEQUENCE. */ |
23b2ce53 RS |
2761 | |
2762 | void | |
2763 | add_insn_after (insn, after) | |
2764 | rtx insn, after; | |
2765 | { | |
2766 | rtx next = NEXT_INSN (after); | |
2767 | ||
6782074d | 2768 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
2769 | abort (); |
2770 | ||
23b2ce53 RS |
2771 | NEXT_INSN (insn) = next; |
2772 | PREV_INSN (insn) = after; | |
2773 | ||
2774 | if (next) | |
2775 | { | |
2776 | PREV_INSN (next) = insn; | |
2777 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2778 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2779 | } | |
2780 | else if (last_insn == after) | |
2781 | last_insn = insn; | |
2782 | else | |
2783 | { | |
49ad7cfa | 2784 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
2785 | /* Scan all pending sequences too. */ |
2786 | for (; stack; stack = stack->next) | |
2787 | if (after == stack->last) | |
fef0509b RK |
2788 | { |
2789 | stack->last = insn; | |
2790 | break; | |
2791 | } | |
a0ae8e8d RK |
2792 | |
2793 | if (stack == 0) | |
2794 | abort (); | |
23b2ce53 RS |
2795 | } |
2796 | ||
2797 | NEXT_INSN (after) = insn; | |
2798 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2799 | { | |
2800 | rtx sequence = PATTERN (after); | |
2801 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2802 | } | |
2803 | } | |
2804 | ||
a0ae8e8d RK |
2805 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2806 | the previous should be the only functions called to insert an insn once | |
ba213285 | 2807 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
2808 | SEQUENCE. */ |
2809 | ||
2810 | void | |
2811 | add_insn_before (insn, before) | |
2812 | rtx insn, before; | |
2813 | { | |
2814 | rtx prev = PREV_INSN (before); | |
2815 | ||
6782074d | 2816 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
2817 | abort (); |
2818 | ||
a0ae8e8d RK |
2819 | PREV_INSN (insn) = prev; |
2820 | NEXT_INSN (insn) = before; | |
2821 | ||
2822 | if (prev) | |
2823 | { | |
2824 | NEXT_INSN (prev) = insn; | |
2825 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2826 | { | |
2827 | rtx sequence = PATTERN (prev); | |
2828 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2829 | } | |
2830 | } | |
2831 | else if (first_insn == before) | |
2832 | first_insn = insn; | |
2833 | else | |
2834 | { | |
49ad7cfa | 2835 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
2836 | /* Scan all pending sequences too. */ |
2837 | for (; stack; stack = stack->next) | |
2838 | if (before == stack->first) | |
fef0509b RK |
2839 | { |
2840 | stack->first = insn; | |
2841 | break; | |
2842 | } | |
a0ae8e8d RK |
2843 | |
2844 | if (stack == 0) | |
2845 | abort (); | |
2846 | } | |
2847 | ||
2848 | PREV_INSN (before) = insn; | |
2849 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2850 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2851 | } | |
2852 | ||
89e99eea DB |
2853 | /* Remove an insn from its doubly-linked list. This function knows how |
2854 | to handle sequences. */ | |
2855 | void | |
2856 | remove_insn (insn) | |
2857 | rtx insn; | |
2858 | { | |
2859 | rtx next = NEXT_INSN (insn); | |
2860 | rtx prev = PREV_INSN (insn); | |
2861 | if (prev) | |
2862 | { | |
2863 | NEXT_INSN (prev) = next; | |
2864 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2865 | { | |
2866 | rtx sequence = PATTERN (prev); | |
2867 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2868 | } | |
2869 | } | |
2870 | else if (first_insn == insn) | |
2871 | first_insn = next; | |
2872 | else | |
2873 | { | |
49ad7cfa | 2874 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2875 | /* Scan all pending sequences too. */ |
2876 | for (; stack; stack = stack->next) | |
2877 | if (insn == stack->first) | |
2878 | { | |
2879 | stack->first = next; | |
2880 | break; | |
2881 | } | |
2882 | ||
2883 | if (stack == 0) | |
2884 | abort (); | |
2885 | } | |
2886 | ||
2887 | if (next) | |
2888 | { | |
2889 | PREV_INSN (next) = prev; | |
2890 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2891 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2892 | } | |
2893 | else if (last_insn == insn) | |
2894 | last_insn = prev; | |
2895 | else | |
2896 | { | |
49ad7cfa | 2897 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2898 | /* Scan all pending sequences too. */ |
2899 | for (; stack; stack = stack->next) | |
2900 | if (insn == stack->last) | |
2901 | { | |
2902 | stack->last = prev; | |
2903 | break; | |
2904 | } | |
2905 | ||
2906 | if (stack == 0) | |
2907 | abort (); | |
2908 | } | |
2909 | } | |
2910 | ||
23b2ce53 RS |
2911 | /* Delete all insns made since FROM. |
2912 | FROM becomes the new last instruction. */ | |
2913 | ||
2914 | void | |
2915 | delete_insns_since (from) | |
2916 | rtx from; | |
2917 | { | |
2918 | if (from == 0) | |
2919 | first_insn = 0; | |
2920 | else | |
2921 | NEXT_INSN (from) = 0; | |
2922 | last_insn = from; | |
2923 | } | |
2924 | ||
5dab5552 MS |
2925 | /* This function is deprecated, please use sequences instead. |
2926 | ||
2927 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
2928 | The insns to be moved are those between FROM and TO. |
2929 | They are moved to a new position after the insn AFTER. | |
2930 | AFTER must not be FROM or TO or any insn in between. | |
2931 | ||
2932 | This function does not know about SEQUENCEs and hence should not be | |
2933 | called after delay-slot filling has been done. */ | |
2934 | ||
2935 | void | |
2936 | reorder_insns (from, to, after) | |
2937 | rtx from, to, after; | |
2938 | { | |
2939 | /* Splice this bunch out of where it is now. */ | |
2940 | if (PREV_INSN (from)) | |
2941 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2942 | if (NEXT_INSN (to)) | |
2943 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2944 | if (last_insn == to) | |
2945 | last_insn = PREV_INSN (from); | |
2946 | if (first_insn == from) | |
2947 | first_insn = NEXT_INSN (to); | |
2948 | ||
2949 | /* Make the new neighbors point to it and it to them. */ | |
2950 | if (NEXT_INSN (after)) | |
2951 | PREV_INSN (NEXT_INSN (after)) = to; | |
2952 | ||
2953 | NEXT_INSN (to) = NEXT_INSN (after); | |
2954 | PREV_INSN (from) = after; | |
2955 | NEXT_INSN (after) = from; | |
2956 | if (after == last_insn) | |
2957 | last_insn = to; | |
2958 | } | |
2959 | ||
2960 | /* Return the line note insn preceding INSN. */ | |
2961 | ||
2962 | static rtx | |
2963 | find_line_note (insn) | |
2964 | rtx insn; | |
2965 | { | |
2966 | if (no_line_numbers) | |
2967 | return 0; | |
2968 | ||
2969 | for (; insn; insn = PREV_INSN (insn)) | |
2970 | if (GET_CODE (insn) == NOTE | |
2971 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2972 | break; | |
2973 | ||
2974 | return insn; | |
2975 | } | |
2976 | ||
2977 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2978 | of the moved insns when debugging. This may insert a note between AFTER | |
2979 | and FROM, and another one after TO. */ | |
2980 | ||
2981 | void | |
2982 | reorder_insns_with_line_notes (from, to, after) | |
2983 | rtx from, to, after; | |
2984 | { | |
2985 | rtx from_line = find_line_note (from); | |
2986 | rtx after_line = find_line_note (after); | |
2987 | ||
2988 | reorder_insns (from, to, after); | |
2989 | ||
2990 | if (from_line == after_line) | |
2991 | return; | |
2992 | ||
2993 | if (from_line) | |
2994 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2995 | NOTE_LINE_NUMBER (from_line), | |
2996 | after); | |
2997 | if (after_line) | |
2998 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2999 | NOTE_LINE_NUMBER (after_line), | |
3000 | to); | |
3001 | } | |
aeeeda03 | 3002 | |
64b59a80 | 3003 | /* Remove unnecessary notes from the instruction stream. */ |
aeeeda03 MM |
3004 | |
3005 | void | |
64b59a80 | 3006 | remove_unnecessary_notes () |
aeeeda03 | 3007 | { |
542d73ae RH |
3008 | rtx block_stack = NULL_RTX; |
3009 | rtx eh_stack = NULL_RTX; | |
aeeeda03 MM |
3010 | rtx insn; |
3011 | rtx next; | |
542d73ae | 3012 | rtx tmp; |
aeeeda03 | 3013 | |
116eebd6 MM |
3014 | /* We must not remove the first instruction in the function because |
3015 | the compiler depends on the first instruction being a note. */ | |
aeeeda03 MM |
3016 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
3017 | { | |
3018 | /* Remember what's next. */ | |
3019 | next = NEXT_INSN (insn); | |
3020 | ||
3021 | /* We're only interested in notes. */ | |
3022 | if (GET_CODE (insn) != NOTE) | |
3023 | continue; | |
3024 | ||
542d73ae | 3025 | switch (NOTE_LINE_NUMBER (insn)) |
18c038b9 | 3026 | { |
542d73ae RH |
3027 | case NOTE_INSN_DELETED: |
3028 | remove_insn (insn); | |
3029 | break; | |
3030 | ||
3031 | case NOTE_INSN_EH_REGION_BEG: | |
3032 | eh_stack = alloc_INSN_LIST (insn, eh_stack); | |
3033 | break; | |
3034 | ||
3035 | case NOTE_INSN_EH_REGION_END: | |
3036 | /* Too many end notes. */ | |
3037 | if (eh_stack == NULL_RTX) | |
3038 | abort (); | |
3039 | /* Mismatched nesting. */ | |
3040 | if (NOTE_EH_HANDLER (XEXP (eh_stack, 0)) != NOTE_EH_HANDLER (insn)) | |
3041 | abort (); | |
3042 | tmp = eh_stack; | |
3043 | eh_stack = XEXP (eh_stack, 1); | |
3044 | free_INSN_LIST_node (tmp); | |
3045 | break; | |
3046 | ||
3047 | case NOTE_INSN_BLOCK_BEG: | |
3048 | /* By now, all notes indicating lexical blocks should have | |
3049 | NOTE_BLOCK filled in. */ | |
3050 | if (NOTE_BLOCK (insn) == NULL_TREE) | |
3051 | abort (); | |
3052 | block_stack = alloc_INSN_LIST (insn, block_stack); | |
3053 | break; | |
3054 | ||
3055 | case NOTE_INSN_BLOCK_END: | |
3056 | /* Too many end notes. */ | |
3057 | if (block_stack == NULL_RTX) | |
3058 | abort (); | |
3059 | /* Mismatched nesting. */ | |
3060 | if (NOTE_BLOCK (XEXP (block_stack, 0)) != NOTE_BLOCK (insn)) | |
3061 | abort (); | |
3062 | tmp = block_stack; | |
3063 | block_stack = XEXP (block_stack, 1); | |
3064 | free_INSN_LIST_node (tmp); | |
3065 | ||
18c038b9 MM |
3066 | /* Scan back to see if there are any non-note instructions |
3067 | between INSN and the beginning of this block. If not, | |
3068 | then there is no PC range in the generated code that will | |
3069 | actually be in this block, so there's no point in | |
3070 | remembering the existence of the block. */ | |
542d73ae | 3071 | for (tmp = PREV_INSN (insn); tmp ; tmp = PREV_INSN (tmp)) |
18c038b9 MM |
3072 | { |
3073 | /* This block contains a real instruction. Note that we | |
3074 | don't include labels; if the only thing in the block | |
3075 | is a label, then there are still no PC values that | |
3076 | lie within the block. */ | |
542d73ae | 3077 | if (INSN_P (tmp)) |
18c038b9 MM |
3078 | break; |
3079 | ||
3080 | /* We're only interested in NOTEs. */ | |
542d73ae | 3081 | if (GET_CODE (tmp) != NOTE) |
18c038b9 MM |
3082 | continue; |
3083 | ||
542d73ae | 3084 | if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_BEG) |
18c038b9 | 3085 | { |
542d73ae RH |
3086 | /* We just verified that this BLOCK matches us |
3087 | with the block_stack check above. */ | |
64b59a80 | 3088 | if (debug_ignore_block (NOTE_BLOCK (insn))) |
deb5e280 | 3089 | { |
542d73ae | 3090 | remove_insn (tmp); |
deb5e280 JM |
3091 | remove_insn (insn); |
3092 | } | |
18c038b9 MM |
3093 | break; |
3094 | } | |
542d73ae | 3095 | else if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_END) |
18c038b9 MM |
3096 | /* There's a nested block. We need to leave the |
3097 | current block in place since otherwise the debugger | |
3098 | wouldn't be able to show symbols from our block in | |
3099 | the nested block. */ | |
3100 | break; | |
3101 | } | |
3102 | } | |
aeeeda03 | 3103 | } |
542d73ae RH |
3104 | |
3105 | /* Too many begin notes. */ | |
3106 | if (block_stack || eh_stack) | |
3107 | abort (); | |
aeeeda03 MM |
3108 | } |
3109 | ||
23b2ce53 RS |
3110 | \f |
3111 | /* Emit an insn of given code and pattern | |
3112 | at a specified place within the doubly-linked list. */ | |
3113 | ||
3114 | /* Make an instruction with body PATTERN | |
3115 | and output it before the instruction BEFORE. */ | |
3116 | ||
3117 | rtx | |
3118 | emit_insn_before (pattern, before) | |
3119 | register rtx pattern, before; | |
3120 | { | |
3121 | register rtx insn = before; | |
3122 | ||
3123 | if (GET_CODE (pattern) == SEQUENCE) | |
3124 | { | |
3125 | register int i; | |
3126 | ||
3127 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3128 | { | |
3129 | insn = XVECEXP (pattern, 0, i); | |
a0ae8e8d | 3130 | add_insn_before (insn, before); |
23b2ce53 | 3131 | } |
23b2ce53 RS |
3132 | } |
3133 | else | |
3134 | { | |
4b1f5e8c | 3135 | insn = make_insn_raw (pattern); |
a0ae8e8d | 3136 | add_insn_before (insn, before); |
23b2ce53 RS |
3137 | } |
3138 | ||
3139 | return insn; | |
3140 | } | |
3141 | ||
a05924f9 JH |
3142 | /* Similar to emit_insn_before, but update basic block boundaries as well. */ |
3143 | ||
3144 | rtx | |
3145 | emit_block_insn_before (pattern, before, block) | |
3146 | rtx pattern, before; | |
3147 | basic_block block; | |
3148 | { | |
3149 | rtx prev = PREV_INSN (before); | |
3150 | rtx r = emit_insn_before (pattern, before); | |
3151 | if (block && block->head == before) | |
3152 | block->head = NEXT_INSN (prev); | |
3153 | return r; | |
3154 | } | |
3155 | ||
23b2ce53 RS |
3156 | /* Make an instruction with body PATTERN and code JUMP_INSN |
3157 | and output it before the instruction BEFORE. */ | |
3158 | ||
3159 | rtx | |
3160 | emit_jump_insn_before (pattern, before) | |
3161 | register rtx pattern, before; | |
3162 | { | |
3163 | register rtx insn; | |
3164 | ||
3165 | if (GET_CODE (pattern) == SEQUENCE) | |
3166 | insn = emit_insn_before (pattern, before); | |
3167 | else | |
3168 | { | |
85cf32bc | 3169 | insn = make_jump_insn_raw (pattern); |
a0ae8e8d | 3170 | add_insn_before (insn, before); |
23b2ce53 RS |
3171 | } |
3172 | ||
3173 | return insn; | |
3174 | } | |
3175 | ||
3176 | /* Make an instruction with body PATTERN and code CALL_INSN | |
3177 | and output it before the instruction BEFORE. */ | |
3178 | ||
3179 | rtx | |
3180 | emit_call_insn_before (pattern, before) | |
3181 | register rtx pattern, before; | |
3182 | { | |
aff507f4 RK |
3183 | register rtx insn; |
3184 | ||
3185 | if (GET_CODE (pattern) == SEQUENCE) | |
3186 | insn = emit_insn_before (pattern, before); | |
3187 | else | |
3188 | { | |
3189 | insn = make_call_insn_raw (pattern); | |
a0ae8e8d | 3190 | add_insn_before (insn, before); |
aff507f4 RK |
3191 | PUT_CODE (insn, CALL_INSN); |
3192 | } | |
3193 | ||
23b2ce53 RS |
3194 | return insn; |
3195 | } | |
3196 | ||
3197 | /* Make an insn of code BARRIER | |
e881bb1b | 3198 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
3199 | |
3200 | rtx | |
3201 | emit_barrier_before (before) | |
3202 | register rtx before; | |
3203 | { | |
3204 | register rtx insn = rtx_alloc (BARRIER); | |
3205 | ||
3206 | INSN_UID (insn) = cur_insn_uid++; | |
3207 | ||
a0ae8e8d | 3208 | add_insn_before (insn, before); |
23b2ce53 RS |
3209 | return insn; |
3210 | } | |
3211 | ||
e881bb1b RH |
3212 | /* Emit the label LABEL before the insn BEFORE. */ |
3213 | ||
3214 | rtx | |
3215 | emit_label_before (label, before) | |
3216 | rtx label, before; | |
3217 | { | |
3218 | /* This can be called twice for the same label as a result of the | |
3219 | confusion that follows a syntax error! So make it harmless. */ | |
3220 | if (INSN_UID (label) == 0) | |
3221 | { | |
3222 | INSN_UID (label) = cur_insn_uid++; | |
3223 | add_insn_before (label, before); | |
3224 | } | |
3225 | ||
3226 | return label; | |
3227 | } | |
3228 | ||
23b2ce53 RS |
3229 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
3230 | ||
3231 | rtx | |
3232 | emit_note_before (subtype, before) | |
3233 | int subtype; | |
3234 | rtx before; | |
3235 | { | |
3236 | register rtx note = rtx_alloc (NOTE); | |
3237 | INSN_UID (note) = cur_insn_uid++; | |
3238 | NOTE_SOURCE_FILE (note) = 0; | |
3239 | NOTE_LINE_NUMBER (note) = subtype; | |
3240 | ||
a0ae8e8d | 3241 | add_insn_before (note, before); |
23b2ce53 RS |
3242 | return note; |
3243 | } | |
3244 | \f | |
3245 | /* Make an insn of code INSN with body PATTERN | |
3246 | and output it after the insn AFTER. */ | |
3247 | ||
3248 | rtx | |
3249 | emit_insn_after (pattern, after) | |
3250 | register rtx pattern, after; | |
3251 | { | |
3252 | register rtx insn = after; | |
3253 | ||
3254 | if (GET_CODE (pattern) == SEQUENCE) | |
3255 | { | |
3256 | register int i; | |
3257 | ||
3258 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3259 | { | |
3260 | insn = XVECEXP (pattern, 0, i); | |
3261 | add_insn_after (insn, after); | |
3262 | after = insn; | |
3263 | } | |
23b2ce53 RS |
3264 | } |
3265 | else | |
3266 | { | |
4b1f5e8c | 3267 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3268 | add_insn_after (insn, after); |
3269 | } | |
3270 | ||
3271 | return insn; | |
3272 | } | |
3273 | ||
255680cf RK |
3274 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
3275 | as to act as if this insn were at FROM. */ | |
3276 | ||
3277 | void | |
3278 | emit_insn_after_with_line_notes (pattern, after, from) | |
3279 | rtx pattern, after, from; | |
3280 | { | |
3281 | rtx from_line = find_line_note (from); | |
3282 | rtx after_line = find_line_note (after); | |
3283 | rtx insn = emit_insn_after (pattern, after); | |
3284 | ||
3285 | if (from_line) | |
3286 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3287 | NOTE_LINE_NUMBER (from_line), | |
3288 | after); | |
3289 | ||
3290 | if (after_line) | |
3291 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3292 | NOTE_LINE_NUMBER (after_line), | |
3293 | insn); | |
3294 | } | |
3295 | ||
a05924f9 JH |
3296 | /* Similar to emit_insn_after, but update basic block boundaries as well. */ |
3297 | ||
3298 | rtx | |
3299 | emit_block_insn_after (pattern, after, block) | |
3300 | rtx pattern, after; | |
3301 | basic_block block; | |
3302 | { | |
3303 | rtx r = emit_insn_after (pattern, after); | |
3304 | if (block && block->end == after) | |
3305 | block->end = r; | |
3306 | return r; | |
3307 | } | |
3308 | ||
23b2ce53 RS |
3309 | /* Make an insn of code JUMP_INSN with body PATTERN |
3310 | and output it after the insn AFTER. */ | |
3311 | ||
3312 | rtx | |
3313 | emit_jump_insn_after (pattern, after) | |
3314 | register rtx pattern, after; | |
3315 | { | |
3316 | register rtx insn; | |
3317 | ||
3318 | if (GET_CODE (pattern) == SEQUENCE) | |
3319 | insn = emit_insn_after (pattern, after); | |
3320 | else | |
3321 | { | |
85cf32bc | 3322 | insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3323 | add_insn_after (insn, after); |
3324 | } | |
3325 | ||
3326 | return insn; | |
3327 | } | |
3328 | ||
3329 | /* Make an insn of code BARRIER | |
3330 | and output it after the insn AFTER. */ | |
3331 | ||
3332 | rtx | |
3333 | emit_barrier_after (after) | |
3334 | register rtx after; | |
3335 | { | |
3336 | register rtx insn = rtx_alloc (BARRIER); | |
3337 | ||
3338 | INSN_UID (insn) = cur_insn_uid++; | |
3339 | ||
3340 | add_insn_after (insn, after); | |
3341 | return insn; | |
3342 | } | |
3343 | ||
3344 | /* Emit the label LABEL after the insn AFTER. */ | |
3345 | ||
3346 | rtx | |
3347 | emit_label_after (label, after) | |
3348 | rtx label, after; | |
3349 | { | |
3350 | /* This can be called twice for the same label | |
3351 | as a result of the confusion that follows a syntax error! | |
3352 | So make it harmless. */ | |
3353 | if (INSN_UID (label) == 0) | |
3354 | { | |
3355 | INSN_UID (label) = cur_insn_uid++; | |
3356 | add_insn_after (label, after); | |
3357 | } | |
3358 | ||
3359 | return label; | |
3360 | } | |
3361 | ||
3362 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3363 | ||
3364 | rtx | |
3365 | emit_note_after (subtype, after) | |
3366 | int subtype; | |
3367 | rtx after; | |
3368 | { | |
3369 | register rtx note = rtx_alloc (NOTE); | |
3370 | INSN_UID (note) = cur_insn_uid++; | |
3371 | NOTE_SOURCE_FILE (note) = 0; | |
3372 | NOTE_LINE_NUMBER (note) = subtype; | |
3373 | add_insn_after (note, after); | |
3374 | return note; | |
3375 | } | |
3376 | ||
3377 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3378 | ||
3379 | rtx | |
3380 | emit_line_note_after (file, line, after) | |
3cce094d | 3381 | const char *file; |
23b2ce53 RS |
3382 | int line; |
3383 | rtx after; | |
3384 | { | |
3385 | register rtx note; | |
3386 | ||
3387 | if (no_line_numbers && line > 0) | |
3388 | { | |
3389 | cur_insn_uid++; | |
3390 | return 0; | |
3391 | } | |
3392 | ||
3393 | note = rtx_alloc (NOTE); | |
3394 | INSN_UID (note) = cur_insn_uid++; | |
3395 | NOTE_SOURCE_FILE (note) = file; | |
3396 | NOTE_LINE_NUMBER (note) = line; | |
3397 | add_insn_after (note, after); | |
3398 | return note; | |
3399 | } | |
3400 | \f | |
3401 | /* Make an insn of code INSN with pattern PATTERN | |
3402 | and add it to the end of the doubly-linked list. | |
3403 | If PATTERN is a SEQUENCE, take the elements of it | |
3404 | and emit an insn for each element. | |
3405 | ||
3406 | Returns the last insn emitted. */ | |
3407 | ||
3408 | rtx | |
3409 | emit_insn (pattern) | |
3410 | rtx pattern; | |
3411 | { | |
3412 | rtx insn = last_insn; | |
3413 | ||
3414 | if (GET_CODE (pattern) == SEQUENCE) | |
3415 | { | |
3416 | register int i; | |
3417 | ||
3418 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3419 | { | |
3420 | insn = XVECEXP (pattern, 0, i); | |
3421 | add_insn (insn); | |
3422 | } | |
23b2ce53 RS |
3423 | } |
3424 | else | |
3425 | { | |
4b1f5e8c | 3426 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3427 | add_insn (insn); |
3428 | } | |
3429 | ||
3430 | return insn; | |
3431 | } | |
3432 | ||
3433 | /* Emit the insns in a chain starting with INSN. | |
3434 | Return the last insn emitted. */ | |
3435 | ||
3436 | rtx | |
3437 | emit_insns (insn) | |
3438 | rtx insn; | |
3439 | { | |
3440 | rtx last = 0; | |
3441 | ||
3442 | while (insn) | |
3443 | { | |
3444 | rtx next = NEXT_INSN (insn); | |
3445 | add_insn (insn); | |
3446 | last = insn; | |
3447 | insn = next; | |
3448 | } | |
3449 | ||
3450 | return last; | |
3451 | } | |
3452 | ||
3453 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3454 | the insn BEFORE. Return the last insn emitted. */ | |
3455 | ||
3456 | rtx | |
3457 | emit_insns_before (insn, before) | |
3458 | rtx insn; | |
3459 | rtx before; | |
3460 | { | |
3461 | rtx last = 0; | |
3462 | ||
3463 | while (insn) | |
3464 | { | |
3465 | rtx next = NEXT_INSN (insn); | |
a0ae8e8d | 3466 | add_insn_before (insn, before); |
23b2ce53 RS |
3467 | last = insn; |
3468 | insn = next; | |
3469 | } | |
3470 | ||
3471 | return last; | |
3472 | } | |
3473 | ||
e0a5c5eb RS |
3474 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3475 | the insn AFTER. Return the last insn emitted. */ | |
3476 | ||
3477 | rtx | |
3478 | emit_insns_after (first, after) | |
3479 | register rtx first; | |
3480 | register rtx after; | |
3481 | { | |
3482 | register rtx last; | |
3483 | register rtx after_after; | |
3484 | ||
3485 | if (!after) | |
3486 | abort (); | |
3487 | ||
3488 | if (!first) | |
3489 | return first; | |
3490 | ||
3491 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3492 | continue; | |
3493 | ||
3494 | after_after = NEXT_INSN (after); | |
3495 | ||
3496 | NEXT_INSN (after) = first; | |
3497 | PREV_INSN (first) = after; | |
3498 | NEXT_INSN (last) = after_after; | |
3499 | if (after_after) | |
3500 | PREV_INSN (after_after) = last; | |
3501 | ||
c4d990db RS |
3502 | if (after == last_insn) |
3503 | last_insn = last; | |
e0a5c5eb RS |
3504 | return last; |
3505 | } | |
3506 | ||
23b2ce53 RS |
3507 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3508 | and add it to the end of the doubly-linked list. */ | |
3509 | ||
3510 | rtx | |
3511 | emit_jump_insn (pattern) | |
3512 | rtx pattern; | |
3513 | { | |
3514 | if (GET_CODE (pattern) == SEQUENCE) | |
3515 | return emit_insn (pattern); | |
3516 | else | |
3517 | { | |
85cf32bc | 3518 | register rtx insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3519 | add_insn (insn); |
3520 | return insn; | |
3521 | } | |
3522 | } | |
3523 | ||
3524 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3525 | and add it to the end of the doubly-linked list. */ | |
3526 | ||
3527 | rtx | |
3528 | emit_call_insn (pattern) | |
3529 | rtx pattern; | |
3530 | { | |
3531 | if (GET_CODE (pattern) == SEQUENCE) | |
3532 | return emit_insn (pattern); | |
3533 | else | |
3534 | { | |
aff507f4 | 3535 | register rtx insn = make_call_insn_raw (pattern); |
23b2ce53 RS |
3536 | add_insn (insn); |
3537 | PUT_CODE (insn, CALL_INSN); | |
3538 | return insn; | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3543 | ||
3544 | rtx | |
3545 | emit_label (label) | |
3546 | rtx label; | |
3547 | { | |
3548 | /* This can be called twice for the same label | |
3549 | as a result of the confusion that follows a syntax error! | |
3550 | So make it harmless. */ | |
3551 | if (INSN_UID (label) == 0) | |
3552 | { | |
3553 | INSN_UID (label) = cur_insn_uid++; | |
3554 | add_insn (label); | |
3555 | } | |
3556 | return label; | |
3557 | } | |
3558 | ||
3559 | /* Make an insn of code BARRIER | |
3560 | and add it to the end of the doubly-linked list. */ | |
3561 | ||
3562 | rtx | |
3563 | emit_barrier () | |
3564 | { | |
3565 | register rtx barrier = rtx_alloc (BARRIER); | |
3566 | INSN_UID (barrier) = cur_insn_uid++; | |
3567 | add_insn (barrier); | |
3568 | return barrier; | |
3569 | } | |
3570 | ||
3571 | /* Make an insn of code NOTE | |
3572 | with data-fields specified by FILE and LINE | |
3573 | and add it to the end of the doubly-linked list, | |
3574 | but only if line-numbers are desired for debugging info. */ | |
3575 | ||
3576 | rtx | |
3577 | emit_line_note (file, line) | |
3cce094d | 3578 | const char *file; |
23b2ce53 RS |
3579 | int line; |
3580 | { | |
3f1d071b | 3581 | set_file_and_line_for_stmt (file, line); |
23b2ce53 RS |
3582 | |
3583 | #if 0 | |
3584 | if (no_line_numbers) | |
3585 | return 0; | |
3586 | #endif | |
3587 | ||
3588 | return emit_note (file, line); | |
3589 | } | |
3590 | ||
3591 | /* Make an insn of code NOTE | |
3592 | with data-fields specified by FILE and LINE | |
3593 | and add it to the end of the doubly-linked list. | |
3594 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3595 | ||
3596 | rtx | |
3597 | emit_note (file, line) | |
3cce094d | 3598 | const char *file; |
23b2ce53 RS |
3599 | int line; |
3600 | { | |
3601 | register rtx note; | |
3602 | ||
3603 | if (line > 0) | |
3604 | { | |
3605 | if (file && last_filename && !strcmp (file, last_filename) | |
3606 | && line == last_linenum) | |
3607 | return 0; | |
3608 | last_filename = file; | |
3609 | last_linenum = line; | |
3610 | } | |
3611 | ||
3612 | if (no_line_numbers && line > 0) | |
3613 | { | |
3614 | cur_insn_uid++; | |
3615 | return 0; | |
3616 | } | |
3617 | ||
3618 | note = rtx_alloc (NOTE); | |
3619 | INSN_UID (note) = cur_insn_uid++; | |
3620 | NOTE_SOURCE_FILE (note) = file; | |
3621 | NOTE_LINE_NUMBER (note) = line; | |
3622 | add_insn (note); | |
3623 | return note; | |
3624 | } | |
3625 | ||
fe77a034 | 3626 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
23b2ce53 RS |
3627 | |
3628 | rtx | |
3629 | emit_line_note_force (file, line) | |
3cce094d | 3630 | const char *file; |
23b2ce53 RS |
3631 | int line; |
3632 | { | |
3633 | last_linenum = -1; | |
3634 | return emit_line_note (file, line); | |
3635 | } | |
3636 | ||
3637 | /* Cause next statement to emit a line note even if the line number | |
3638 | has not changed. This is used at the beginning of a function. */ | |
3639 | ||
3640 | void | |
3641 | force_next_line_note () | |
3642 | { | |
3643 | last_linenum = -1; | |
3644 | } | |
87b47c85 AM |
3645 | |
3646 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
3647 | note of this type already exists, remove it first. */ | |
3648 | ||
3649 | void | |
3650 | set_unique_reg_note (insn, kind, datum) | |
3651 | rtx insn; | |
3652 | enum reg_note kind; | |
3653 | rtx datum; | |
3654 | { | |
3655 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3656 | ||
3657 | /* First remove the note if there already is one. */ | |
3658 | if (note) | |
3659 | remove_note (insn, note); | |
3660 | ||
3661 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3662 | } | |
23b2ce53 RS |
3663 | \f |
3664 | /* Return an indication of which type of insn should have X as a body. | |
3665 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3666 | ||
3667 | enum rtx_code | |
3668 | classify_insn (x) | |
3669 | rtx x; | |
3670 | { | |
3671 | if (GET_CODE (x) == CODE_LABEL) | |
3672 | return CODE_LABEL; | |
3673 | if (GET_CODE (x) == CALL) | |
3674 | return CALL_INSN; | |
3675 | if (GET_CODE (x) == RETURN) | |
3676 | return JUMP_INSN; | |
3677 | if (GET_CODE (x) == SET) | |
3678 | { | |
3679 | if (SET_DEST (x) == pc_rtx) | |
3680 | return JUMP_INSN; | |
3681 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3682 | return CALL_INSN; | |
3683 | else | |
3684 | return INSN; | |
3685 | } | |
3686 | if (GET_CODE (x) == PARALLEL) | |
3687 | { | |
3688 | register int j; | |
3689 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3690 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3691 | return CALL_INSN; | |
3692 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3693 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3694 | return JUMP_INSN; | |
3695 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3696 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3697 | return CALL_INSN; | |
3698 | } | |
3699 | return INSN; | |
3700 | } | |
3701 | ||
3702 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3703 | If X is a label, it is simply added into the insn chain. */ | |
3704 | ||
3705 | rtx | |
3706 | emit (x) | |
3707 | rtx x; | |
3708 | { | |
3709 | enum rtx_code code = classify_insn (x); | |
3710 | ||
3711 | if (code == CODE_LABEL) | |
3712 | return emit_label (x); | |
3713 | else if (code == INSN) | |
3714 | return emit_insn (x); | |
3715 | else if (code == JUMP_INSN) | |
3716 | { | |
3717 | register rtx insn = emit_jump_insn (x); | |
7f1c097d | 3718 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
23b2ce53 RS |
3719 | return emit_barrier (); |
3720 | return insn; | |
3721 | } | |
3722 | else if (code == CALL_INSN) | |
3723 | return emit_call_insn (x); | |
3724 | else | |
3725 | abort (); | |
3726 | } | |
3727 | \f | |
5c7a310f MM |
3728 | /* Begin emitting insns to a sequence which can be packaged in an |
3729 | RTL_EXPR. If this sequence will contain something that might cause | |
3730 | the compiler to pop arguments to function calls (because those | |
3731 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3732 | details), use do_pending_stack_adjust before calling this function. | |
3733 | That will ensure that the deferred pops are not accidentally | |
4eb00163 | 3734 | emitted in the middle of this sequence. */ |
23b2ce53 RS |
3735 | |
3736 | void | |
3737 | start_sequence () | |
3738 | { | |
3739 | struct sequence_stack *tem; | |
3740 | ||
a3770a81 | 3741 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
23b2ce53 | 3742 | |
49ad7cfa | 3743 | tem->next = seq_stack; |
23b2ce53 RS |
3744 | tem->first = first_insn; |
3745 | tem->last = last_insn; | |
591ccf92 | 3746 | tem->sequence_rtl_expr = seq_rtl_expr; |
23b2ce53 | 3747 | |
49ad7cfa | 3748 | seq_stack = tem; |
23b2ce53 RS |
3749 | |
3750 | first_insn = 0; | |
3751 | last_insn = 0; | |
3752 | } | |
3753 | ||
591ccf92 MM |
3754 | /* Similarly, but indicate that this sequence will be placed in T, an |
3755 | RTL_EXPR. See the documentation for start_sequence for more | |
3756 | information about how to use this function. */ | |
3757 | ||
3758 | void | |
3759 | start_sequence_for_rtl_expr (t) | |
3760 | tree t; | |
3761 | { | |
3762 | start_sequence (); | |
3763 | ||
3764 | seq_rtl_expr = t; | |
3765 | } | |
3766 | ||
5c7a310f MM |
3767 | /* Set up the insn chain starting with FIRST as the current sequence, |
3768 | saving the previously current one. See the documentation for | |
3769 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
3770 | |
3771 | void | |
3772 | push_to_sequence (first) | |
3773 | rtx first; | |
3774 | { | |
3775 | rtx last; | |
3776 | ||
3777 | start_sequence (); | |
3778 | ||
3779 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3780 | ||
3781 | first_insn = first; | |
3782 | last_insn = last; | |
3783 | } | |
3784 | ||
c14f7160 ML |
3785 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3786 | ||
3787 | void | |
3788 | push_to_full_sequence (first, last) | |
3789 | rtx first, last; | |
3790 | { | |
3791 | start_sequence (); | |
3792 | first_insn = first; | |
3793 | last_insn = last; | |
3794 | /* We really should have the end of the insn chain here. */ | |
3795 | if (last && NEXT_INSN (last)) | |
3796 | abort (); | |
3797 | } | |
3798 | ||
f15ae3a1 TW |
3799 | /* Set up the outer-level insn chain |
3800 | as the current sequence, saving the previously current one. */ | |
3801 | ||
3802 | void | |
3803 | push_topmost_sequence () | |
3804 | { | |
aefdd5ab | 3805 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
3806 | |
3807 | start_sequence (); | |
3808 | ||
49ad7cfa | 3809 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3810 | top = stack; |
3811 | ||
3812 | first_insn = top->first; | |
3813 | last_insn = top->last; | |
591ccf92 | 3814 | seq_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
3815 | } |
3816 | ||
3817 | /* After emitting to the outer-level insn chain, update the outer-level | |
3818 | insn chain, and restore the previous saved state. */ | |
3819 | ||
3820 | void | |
3821 | pop_topmost_sequence () | |
3822 | { | |
aefdd5ab | 3823 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 3824 | |
49ad7cfa | 3825 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3826 | top = stack; |
3827 | ||
3828 | top->first = first_insn; | |
3829 | top->last = last_insn; | |
591ccf92 | 3830 | /* ??? Why don't we save seq_rtl_expr here? */ |
f15ae3a1 TW |
3831 | |
3832 | end_sequence (); | |
3833 | } | |
3834 | ||
23b2ce53 RS |
3835 | /* After emitting to a sequence, restore previous saved state. |
3836 | ||
5c7a310f MM |
3837 | To get the contents of the sequence just made, you must call |
3838 | `gen_sequence' *before* calling here. | |
3839 | ||
3840 | If the compiler might have deferred popping arguments while | |
3841 | generating this sequence, and this sequence will not be immediately | |
3842 | inserted into the instruction stream, use do_pending_stack_adjust | |
3843 | before calling gen_sequence. That will ensure that the deferred | |
3844 | pops are inserted into this sequence, and not into some random | |
3845 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3846 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
3847 | |
3848 | void | |
3849 | end_sequence () | |
3850 | { | |
49ad7cfa | 3851 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
3852 | |
3853 | first_insn = tem->first; | |
3854 | last_insn = tem->last; | |
591ccf92 | 3855 | seq_rtl_expr = tem->sequence_rtl_expr; |
49ad7cfa | 3856 | seq_stack = tem->next; |
23b2ce53 | 3857 | |
a3770a81 | 3858 | free (tem); |
23b2ce53 RS |
3859 | } |
3860 | ||
c14f7160 ML |
3861 | /* This works like end_sequence, but records the old sequence in FIRST |
3862 | and LAST. */ | |
3863 | ||
3864 | void | |
3865 | end_full_sequence (first, last) | |
3866 | rtx *first, *last; | |
3867 | { | |
3868 | *first = first_insn; | |
3869 | *last = last_insn; | |
3870 | end_sequence(); | |
3871 | } | |
3872 | ||
23b2ce53 RS |
3873 | /* Return 1 if currently emitting into a sequence. */ |
3874 | ||
3875 | int | |
3876 | in_sequence_p () | |
3877 | { | |
49ad7cfa | 3878 | return seq_stack != 0; |
23b2ce53 RS |
3879 | } |
3880 | ||
3881 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3882 | to the current sequence. | |
3883 | ||
3884 | This is how the gen_... function from a DEFINE_EXPAND | |
3885 | constructs the SEQUENCE that it returns. */ | |
3886 | ||
3887 | rtx | |
3888 | gen_sequence () | |
3889 | { | |
3890 | rtx result; | |
3891 | rtx tem; | |
23b2ce53 RS |
3892 | int i; |
3893 | int len; | |
3894 | ||
3895 | /* Count the insns in the chain. */ | |
3896 | len = 0; | |
3897 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3898 | len++; | |
3899 | ||
ee265800 | 3900 | /* If only one insn, return it rather than a SEQUENCE. |
23b2ce53 | 3901 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
ee265800 AH |
3902 | the case of an empty list.) |
3903 | We only return the pattern of an insn if its code is INSN and it | |
3904 | has no notes. This ensures that no information gets lost. */ | |
23b2ce53 | 3905 | if (len == 1 |
ca55abae | 3906 | && ! RTX_FRAME_RELATED_P (first_insn) |
ee265800 AH |
3907 | && GET_CODE (first_insn) == INSN |
3908 | /* Don't throw away any reg notes. */ | |
3909 | && REG_NOTES (first_insn) == 0) | |
1f8f4a0b | 3910 | return PATTERN (first_insn); |
23b2ce53 | 3911 | |
1f8f4a0b | 3912 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
23b2ce53 RS |
3913 | |
3914 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3915 | XVECEXP (result, 0, i) = tem; | |
3916 | ||
3917 | return result; | |
3918 | } | |
3919 | \f | |
59ec66dc MM |
3920 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3921 | ||
3922 | void | |
49ad7cfa BS |
3923 | init_virtual_regs (es) |
3924 | struct emit_status *es; | |
59ec66dc | 3925 | { |
49ad7cfa BS |
3926 | rtx *ptr = es->x_regno_reg_rtx; |
3927 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3928 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3929 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3930 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3931 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3932 | } | |
3933 | ||
3934 | void | |
3935 | clear_emit_caches () | |
3936 | { | |
3937 | int i; | |
3938 | ||
3939 | /* Clear the start_sequence/gen_sequence cache. */ | |
49ad7cfa BS |
3940 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3941 | sequence_result[i] = 0; | |
3942 | free_insn = 0; | |
59ec66dc | 3943 | } |
da43a810 BS |
3944 | \f |
3945 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3946 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3947 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3948 | static int copy_insn_n_scratches; | |
3949 | ||
3950 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3951 | copied an ASM_OPERANDS. | |
3952 | In that case, it is the original input-operand vector. */ | |
3953 | static rtvec orig_asm_operands_vector; | |
3954 | ||
3955 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3956 | copied an ASM_OPERANDS. | |
3957 | In that case, it is the copied input-operand vector. */ | |
3958 | static rtvec copy_asm_operands_vector; | |
3959 | ||
3960 | /* Likewise for the constraints vector. */ | |
3961 | static rtvec orig_asm_constraints_vector; | |
3962 | static rtvec copy_asm_constraints_vector; | |
3963 | ||
3964 | /* Recursively create a new copy of an rtx for copy_insn. | |
3965 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3966 | ASM_OPERANDs properly. | |
3967 | Normally, this function is not used directly; use copy_insn as front end. | |
3968 | However, you could first copy an insn pattern with copy_insn and then use | |
3969 | this function afterwards to properly copy any REG_NOTEs containing | |
3970 | SCRATCHes. */ | |
3971 | ||
3972 | rtx | |
3973 | copy_insn_1 (orig) | |
3974 | register rtx orig; | |
3975 | { | |
3976 | register rtx copy; | |
3977 | register int i, j; | |
3978 | register RTX_CODE code; | |
4724334a | 3979 | register const char *format_ptr; |
da43a810 BS |
3980 | |
3981 | code = GET_CODE (orig); | |
3982 | ||
3983 | switch (code) | |
3984 | { | |
3985 | case REG: | |
3986 | case QUEUED: | |
3987 | case CONST_INT: | |
3988 | case CONST_DOUBLE: | |
3989 | case SYMBOL_REF: | |
3990 | case CODE_LABEL: | |
3991 | case PC: | |
3992 | case CC0: | |
3993 | case ADDRESSOF: | |
3994 | return orig; | |
3995 | ||
3996 | case SCRATCH: | |
3997 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3998 | if (copy_insn_scratch_in[i] == orig) | |
3999 | return copy_insn_scratch_out[i]; | |
4000 | break; | |
4001 | ||
4002 | case CONST: | |
4003 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
4004 | a LABEL_REF, it isn't sharable. */ | |
4005 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
4006 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
4007 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
4008 | return orig; | |
4009 | break; | |
4010 | ||
4011 | /* A MEM with a constant address is not sharable. The problem is that | |
4012 | the constant address may need to be reloaded. If the mem is shared, | |
4013 | then reloading one copy of this mem will cause all copies to appear | |
4014 | to have been reloaded. */ | |
4015 | ||
4016 | default: | |
4017 | break; | |
4018 | } | |
4019 | ||
4020 | copy = rtx_alloc (code); | |
4021 | ||
4022 | /* Copy the various flags, and other information. We assume that | |
4023 | all fields need copying, and then clear the fields that should | |
4024 | not be copied. That is the sensible default behavior, and forces | |
4025 | us to explicitly document why we are *not* copying a flag. */ | |
4026 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
4027 | ||
4028 | /* We do not copy the USED flag, which is used as a mark bit during | |
4029 | walks over the RTL. */ | |
4030 | copy->used = 0; | |
4031 | ||
4032 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
4033 | if (GET_RTX_CLASS (code) == 'i') | |
4034 | { | |
4035 | copy->jump = 0; | |
4036 | copy->call = 0; | |
4037 | copy->frame_related = 0; | |
4038 | } | |
4039 | ||
4040 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
4041 | ||
4042 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
4043 | { | |
e63db8f6 | 4044 | copy->fld[i] = orig->fld[i]; |
da43a810 BS |
4045 | switch (*format_ptr++) |
4046 | { | |
4047 | case 'e': | |
da43a810 BS |
4048 | if (XEXP (orig, i) != NULL) |
4049 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
4050 | break; | |
4051 | ||
da43a810 BS |
4052 | case 'E': |
4053 | case 'V': | |
da43a810 BS |
4054 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
4055 | XVEC (copy, i) = copy_asm_constraints_vector; | |
4056 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
4057 | XVEC (copy, i) = copy_asm_operands_vector; | |
4058 | else if (XVEC (orig, i) != NULL) | |
4059 | { | |
4060 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
4061 | for (j = 0; j < XVECLEN (copy, i); j++) | |
4062 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
4063 | } | |
4064 | break; | |
4065 | ||
da43a810 | 4066 | case 't': |
da43a810 | 4067 | case 'w': |
da43a810 | 4068 | case 'i': |
da43a810 BS |
4069 | case 's': |
4070 | case 'S': | |
e63db8f6 BS |
4071 | case 'u': |
4072 | case '0': | |
4073 | /* These are left unchanged. */ | |
da43a810 BS |
4074 | break; |
4075 | ||
4076 | default: | |
4077 | abort (); | |
4078 | } | |
4079 | } | |
4080 | ||
4081 | if (code == SCRATCH) | |
4082 | { | |
4083 | i = copy_insn_n_scratches++; | |
4084 | if (i >= MAX_RECOG_OPERANDS) | |
4085 | abort (); | |
4086 | copy_insn_scratch_in[i] = orig; | |
4087 | copy_insn_scratch_out[i] = copy; | |
4088 | } | |
4089 | else if (code == ASM_OPERANDS) | |
4090 | { | |
6462bb43 AO |
4091 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
4092 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
4093 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
4094 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
4095 | } |
4096 | ||
4097 | return copy; | |
4098 | } | |
4099 | ||
4100 | /* Create a new copy of an rtx. | |
4101 | This function differs from copy_rtx in that it handles SCRATCHes and | |
4102 | ASM_OPERANDs properly. | |
4103 | INSN doesn't really have to be a full INSN; it could be just the | |
4104 | pattern. */ | |
4105 | rtx | |
4106 | copy_insn (insn) | |
4107 | rtx insn; | |
4108 | { | |
4109 | copy_insn_n_scratches = 0; | |
4110 | orig_asm_operands_vector = 0; | |
4111 | orig_asm_constraints_vector = 0; | |
4112 | copy_asm_operands_vector = 0; | |
4113 | copy_asm_constraints_vector = 0; | |
4114 | return copy_insn_1 (insn); | |
4115 | } | |
59ec66dc | 4116 | |
23b2ce53 RS |
4117 | /* Initialize data structures and variables in this file |
4118 | before generating rtl for each function. */ | |
4119 | ||
4120 | void | |
4121 | init_emit () | |
4122 | { | |
01d939e8 | 4123 | struct function *f = cfun; |
23b2ce53 | 4124 | |
49ad7cfa | 4125 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
23b2ce53 RS |
4126 | first_insn = NULL; |
4127 | last_insn = NULL; | |
591ccf92 | 4128 | seq_rtl_expr = NULL; |
23b2ce53 RS |
4129 | cur_insn_uid = 1; |
4130 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
4131 | last_linenum = 0; | |
4132 | last_filename = 0; | |
4133 | first_label_num = label_num; | |
4134 | last_label_num = 0; | |
49ad7cfa | 4135 | seq_stack = NULL; |
23b2ce53 | 4136 | |
49ad7cfa | 4137 | clear_emit_caches (); |
23b2ce53 RS |
4138 | |
4139 | /* Init the tables that describe all the pseudo regs. */ | |
4140 | ||
3502dc9c | 4141 | f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 4142 | |
49ad7cfa | 4143 | f->emit->regno_pointer_align |
3502dc9c | 4144 | = (unsigned char *) xcalloc (f->emit->regno_pointer_align_length, |
f9e158c3 | 4145 | sizeof (unsigned char)); |
86fe05e0 | 4146 | |
23b2ce53 | 4147 | regno_reg_rtx |
3502dc9c | 4148 | = (rtx *) xcalloc (f->emit->regno_pointer_align_length * sizeof (rtx), |
a3770a81 | 4149 | sizeof (rtx)); |
23b2ce53 RS |
4150 | |
4151 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
49ad7cfa | 4152 | init_virtual_regs (f->emit); |
740ab4a2 RK |
4153 | |
4154 | /* Indicate that the virtual registers and stack locations are | |
4155 | all pointers. */ | |
3502dc9c JDA |
4156 | REG_POINTER (stack_pointer_rtx) = 1; |
4157 | REG_POINTER (frame_pointer_rtx) = 1; | |
4158 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
4159 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 4160 | |
3502dc9c JDA |
4161 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
4162 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
4163 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
4164 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
4165 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 4166 | |
86fe05e0 | 4167 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
4168 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
4169 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
4170 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
4171 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
4172 | ||
4173 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
4174 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
4175 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
4176 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
4177 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
4178 | #endif |
4179 | ||
5e82e7bd JVA |
4180 | #ifdef INIT_EXPANDERS |
4181 | INIT_EXPANDERS; | |
4182 | #endif | |
23b2ce53 RS |
4183 | } |
4184 | ||
87ff9c8e RH |
4185 | /* Mark SS for GC. */ |
4186 | ||
4187 | static void | |
4188 | mark_sequence_stack (ss) | |
4189 | struct sequence_stack *ss; | |
4190 | { | |
4191 | while (ss) | |
4192 | { | |
4193 | ggc_mark_rtx (ss->first); | |
591ccf92 | 4194 | ggc_mark_tree (ss->sequence_rtl_expr); |
87ff9c8e RH |
4195 | ss = ss->next; |
4196 | } | |
4197 | } | |
4198 | ||
4199 | /* Mark ES for GC. */ | |
4200 | ||
4201 | void | |
fa51b01b | 4202 | mark_emit_status (es) |
87ff9c8e RH |
4203 | struct emit_status *es; |
4204 | { | |
4205 | rtx *r; | |
4206 | int i; | |
4207 | ||
4208 | if (es == 0) | |
4209 | return; | |
4210 | ||
3502dc9c | 4211 | for (i = es->regno_pointer_align_length, r = es->x_regno_reg_rtx; |
87ff9c8e RH |
4212 | i > 0; --i, ++r) |
4213 | ggc_mark_rtx (*r); | |
4214 | ||
4215 | mark_sequence_stack (es->sequence_stack); | |
591ccf92 | 4216 | ggc_mark_tree (es->sequence_rtl_expr); |
87ff9c8e RH |
4217 | ggc_mark_rtx (es->x_first_insn); |
4218 | } | |
4219 | ||
23b2ce53 RS |
4220 | /* Create some permanent unique rtl objects shared between all functions. |
4221 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
4222 | ||
4223 | void | |
4224 | init_emit_once (line_numbers) | |
4225 | int line_numbers; | |
4226 | { | |
4227 | int i; | |
4228 | enum machine_mode mode; | |
9ec36da5 | 4229 | enum machine_mode double_mode; |
23b2ce53 | 4230 | |
67673f5c MM |
4231 | /* Initialize the CONST_INT hash table. */ |
4232 | const_int_htab = htab_create (37, const_int_htab_hash, | |
4233 | const_int_htab_eq, NULL); | |
4234 | ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab), | |
4235 | rtx_htab_mark); | |
4236 | ||
23b2ce53 RS |
4237 | no_line_numbers = ! line_numbers; |
4238 | ||
43fa6302 AS |
4239 | /* Compute the word and byte modes. */ |
4240 | ||
4241 | byte_mode = VOIDmode; | |
4242 | word_mode = VOIDmode; | |
4243 | double_mode = VOIDmode; | |
4244 | ||
4245 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4246 | mode = GET_MODE_WIDER_MODE (mode)) | |
4247 | { | |
4248 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
4249 | && byte_mode == VOIDmode) | |
4250 | byte_mode = mode; | |
4251 | ||
4252 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
4253 | && word_mode == VOIDmode) | |
4254 | word_mode = mode; | |
4255 | } | |
4256 | ||
43fa6302 AS |
4257 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; |
4258 | mode = GET_MODE_WIDER_MODE (mode)) | |
4259 | { | |
4260 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
4261 | && double_mode == VOIDmode) | |
4262 | double_mode = mode; | |
4263 | } | |
4264 | ||
4265 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
4266 | ||
5da077de AS |
4267 | /* Assign register numbers to the globally defined register rtx. |
4268 | This must be done at runtime because the register number field | |
4269 | is in a union and some compilers can't initialize unions. */ | |
4270 | ||
4271 | pc_rtx = gen_rtx (PC, VOIDmode); | |
4272 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
08394eef BS |
4273 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
4274 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5da077de | 4275 | if (hard_frame_pointer_rtx == 0) |
08394eef BS |
4276 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, |
4277 | HARD_FRAME_POINTER_REGNUM); | |
5da077de | 4278 | if (arg_pointer_rtx == 0) |
08394eef | 4279 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); |
5da077de | 4280 | virtual_incoming_args_rtx = |
08394eef | 4281 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); |
5da077de | 4282 | virtual_stack_vars_rtx = |
08394eef | 4283 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); |
5da077de | 4284 | virtual_stack_dynamic_rtx = |
08394eef | 4285 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); |
5da077de | 4286 | virtual_outgoing_args_rtx = |
08394eef BS |
4287 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); |
4288 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
5da077de AS |
4289 | |
4290 | /* These rtx must be roots if GC is enabled. */ | |
1f8f4a0b | 4291 | ggc_add_rtx_root (global_rtl, GR_MAX); |
5da077de | 4292 | |
5da077de | 4293 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
4294 | /* This is to initialize {init|mark|free}_machine_status before the first |
4295 | call to push_function_context_to. This is needed by the Chill front | |
4296 | end which calls push_function_context_to before the first cal to | |
5da077de AS |
4297 | init_function_start. */ |
4298 | INIT_EXPANDERS; | |
4299 | #endif | |
4300 | ||
23b2ce53 RS |
4301 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
4302 | ||
c5c76735 JL |
4303 | /* Don't use gen_rtx here since gen_rtx in this case |
4304 | tries to use these variables. */ | |
23b2ce53 | 4305 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
5da077de AS |
4306 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
4307 | gen_rtx_raw_CONST_INT (VOIDmode, i); | |
1f8f4a0b | 4308 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); |
23b2ce53 | 4309 | |
68d75312 JC |
4310 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
4311 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 4312 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 4313 | else |
3b80f6ca | 4314 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 4315 | |
9ec36da5 JL |
4316 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
4317 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
4318 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
4319 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
23b2ce53 RS |
4320 | |
4321 | for (i = 0; i <= 2; i++) | |
4322 | { | |
4323 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4324 | mode = GET_MODE_WIDER_MODE (mode)) | |
4325 | { | |
4326 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4327 | union real_extract u; | |
4328 | ||
961192e1 | 4329 | memset ((char *) &u, 0, sizeof u); /* Zero any holes in a structure. */ |
23b2ce53 RS |
4330 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4331 | ||
4e135bdd | 4332 | memcpy (&CONST_DOUBLE_LOW (tem), &u, sizeof u); |
23b2ce53 | 4333 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
f8a83ee3 | 4334 | CONST_DOUBLE_CHAIN (tem) = NULL_RTX; |
23b2ce53 RS |
4335 | PUT_MODE (tem, mode); |
4336 | ||
4337 | const_tiny_rtx[i][(int) mode] = tem; | |
4338 | } | |
4339 | ||
906c4e36 | 4340 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
4341 | |
4342 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4343 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 4344 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
4345 | |
4346 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4347 | mode != VOIDmode; | |
4348 | mode = GET_MODE_WIDER_MODE (mode)) | |
4349 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
4350 | } |
4351 | ||
dbbbbf3b JDA |
4352 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
4353 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
4354 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 4355 | |
f0417c82 RH |
4356 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
4357 | if (STORE_FLAG_VALUE == 1) | |
4358 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
4359 | ||
b6a1cbae GM |
4360 | /* For bounded pointers, `&const_tiny_rtx[0][0]' is not the same as |
4361 | `(rtx *) const_tiny_rtx'. The former has bounds that only cover | |
4362 | `const_tiny_rtx[0]', whereas the latter has bounds that cover all. */ | |
4363 | ggc_add_rtx_root ((rtx *) const_tiny_rtx, sizeof const_tiny_rtx / sizeof (rtx)); | |
21cd906e | 4364 | ggc_add_rtx_root (&const_true_rtx, 1); |
a7e1e2ac AO |
4365 | |
4366 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4367 | return_address_pointer_rtx | |
08394eef | 4368 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); |
a7e1e2ac AO |
4369 | #endif |
4370 | ||
4371 | #ifdef STRUCT_VALUE | |
4372 | struct_value_rtx = STRUCT_VALUE; | |
4373 | #else | |
4374 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4375 | #endif | |
4376 | ||
4377 | #ifdef STRUCT_VALUE_INCOMING | |
4378 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4379 | #else | |
4380 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4381 | struct_value_incoming_rtx | |
4382 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4383 | #else | |
4384 | struct_value_incoming_rtx = struct_value_rtx; | |
4385 | #endif | |
4386 | #endif | |
4387 | ||
4388 | #ifdef STATIC_CHAIN_REGNUM | |
4389 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4390 | ||
4391 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4392 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4393 | static_chain_incoming_rtx | |
4394 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4395 | else | |
4396 | #endif | |
4397 | static_chain_incoming_rtx = static_chain_rtx; | |
4398 | #endif | |
4399 | ||
4400 | #ifdef STATIC_CHAIN | |
4401 | static_chain_rtx = STATIC_CHAIN; | |
4402 | ||
4403 | #ifdef STATIC_CHAIN_INCOMING | |
4404 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4405 | #else | |
4406 | static_chain_incoming_rtx = static_chain_rtx; | |
4407 | #endif | |
4408 | #endif | |
4409 | ||
848e0190 JH |
4410 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
4411 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
a7e1e2ac | 4412 | |
d7db6646 RH |
4413 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4414 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4415 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4416 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4417 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4418 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
23b2ce53 | 4419 | } |
a11759a3 JR |
4420 | \f |
4421 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4422 | switch / case handling in stmt.c to give proper line numbers in | |
4423 | warnings about unreachable code. */ | |
4424 | ||
4425 | int | |
4426 | force_line_numbers () | |
4427 | { | |
4428 | int old = no_line_numbers; | |
4429 | ||
4430 | no_line_numbers = 0; | |
4431 | if (old) | |
4432 | force_next_line_note (); | |
4433 | return old; | |
4434 | } | |
4435 | ||
4436 | void | |
4437 | restore_line_number_status (old_value) | |
4438 | int old_value; | |
4439 | { | |
4440 | no_line_numbers = old_value; | |
4441 | } |