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Commit | Line | Data |
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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
54fb1ae0 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
c2969d8e | 4 | 2010, 2011 |
b6f65e3c | 5 | Free Software Foundation, Inc. |
23b2ce53 | 6 | |
1322177d | 7 | This file is part of GCC. |
23b2ce53 | 8 | |
1322177d LB |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 11 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 12 | version. |
23b2ce53 | 13 | |
1322177d LB |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
23b2ce53 RS |
18 | |
19 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
22 | |
23 | ||
24 | /* Middle-to-low level generation of rtx code and insns. | |
25 | ||
f822fcf7 KH |
26 | This file contains support functions for creating rtl expressions |
27 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
28 | |
29 | The patterns of the insns are created by machine-dependent | |
30 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
31 | the machine description. These routines make the individual rtx's |
32 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
33 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
34 | dependent is the kind of rtx's they make and what arguments they |
35 | use. */ | |
23b2ce53 RS |
36 | |
37 | #include "config.h" | |
670ee920 | 38 | #include "system.h" |
4977bab6 ZW |
39 | #include "coretypes.h" |
40 | #include "tm.h" | |
718f9c0f | 41 | #include "diagnostic-core.h" |
23b2ce53 | 42 | #include "rtl.h" |
a25c7971 | 43 | #include "tree.h" |
6baf1cc8 | 44 | #include "tm_p.h" |
23b2ce53 RS |
45 | #include "flags.h" |
46 | #include "function.h" | |
47 | #include "expr.h" | |
48 | #include "regs.h" | |
aff48bca | 49 | #include "hard-reg-set.h" |
c13e8210 | 50 | #include "hashtab.h" |
23b2ce53 | 51 | #include "insn-config.h" |
e9a25f70 | 52 | #include "recog.h" |
0dfa1860 | 53 | #include "bitmap.h" |
a05924f9 | 54 | #include "basic-block.h" |
87ff9c8e | 55 | #include "ggc.h" |
e1772ac0 | 56 | #include "debug.h" |
d23c55c2 | 57 | #include "langhooks.h" |
ef330312 | 58 | #include "tree-pass.h" |
6fb5fa3c | 59 | #include "df.h" |
b5b8b0ac | 60 | #include "params.h" |
d4ebfa65 | 61 | #include "target.h" |
4994da65 | 62 | #include "tree-flow.h" |
ca695ac9 | 63 | |
5fb0e246 RS |
64 | struct target_rtl default_target_rtl; |
65 | #if SWITCHABLE_TARGET | |
66 | struct target_rtl *this_target_rtl = &default_target_rtl; | |
67 | #endif | |
68 | ||
69 | #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx) | |
70 | ||
1d445e9e ILT |
71 | /* Commonly used modes. */ |
72 | ||
0f41302f MS |
73 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
74 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 75 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 76 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 77 | |
bd60bab2 JH |
78 | /* Datastructures maintained for currently processed function in RTL form. */ |
79 | ||
3e029763 | 80 | struct rtl_data x_rtl; |
bd60bab2 JH |
81 | |
82 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
b8698a0f | 83 | Allocated in parallel with regno_pointer_align. |
bd60bab2 JH |
84 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal |
85 | with length attribute nested in top level structures. */ | |
86 | ||
87 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
88 | |
89 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
90 | in the entire compilation a unique label number. */ | |
91 | ||
044b4de3 | 92 | static GTY(()) int label_num = 1; |
23b2ce53 | 93 | |
23b2ce53 RS |
94 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
95 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
96 | record a copy of const[012]_rtx. */ | |
97 | ||
98 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
99 | ||
68d75312 JC |
100 | rtx const_true_rtx; |
101 | ||
23b2ce53 RS |
102 | REAL_VALUE_TYPE dconst0; |
103 | REAL_VALUE_TYPE dconst1; | |
104 | REAL_VALUE_TYPE dconst2; | |
105 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 106 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 107 | |
325217ed CF |
108 | /* Record fixed-point constant 0 and 1. */ |
109 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
110 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
111 | ||
23b2ce53 RS |
112 | /* We make one copy of (const_int C) where C is in |
113 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
114 | to save space during the compilation and simplify comparisons of | |
115 | integers. */ | |
116 | ||
5da077de | 117 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 118 | |
c13e8210 MM |
119 | /* A hash table storing CONST_INTs whose absolute value is greater |
120 | than MAX_SAVED_CONST_INT. */ | |
121 | ||
e2500fed GK |
122 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
123 | htab_t const_int_htab; | |
c13e8210 | 124 | |
173b24b9 | 125 | /* A hash table storing memory attribute structures. */ |
e2500fed GK |
126 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
127 | htab_t mem_attrs_htab; | |
173b24b9 | 128 | |
a560d4d4 JH |
129 | /* A hash table storing register attribute structures. */ |
130 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
131 | htab_t reg_attrs_htab; | |
132 | ||
5692c7bc | 133 | /* A hash table storing all CONST_DOUBLEs. */ |
e2500fed GK |
134 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
135 | htab_t const_double_htab; | |
5692c7bc | 136 | |
091a3ac7 CF |
137 | /* A hash table storing all CONST_FIXEDs. */ |
138 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) | |
139 | htab_t const_fixed_htab; | |
140 | ||
3e029763 | 141 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) |
b5b8b0ac | 142 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 JH |
143 | #define last_location (crtl->emit.x_last_location) |
144 | #define first_label_num (crtl->emit.x_first_label_num) | |
23b2ce53 | 145 | |
502b8322 | 146 | static rtx make_call_insn_raw (rtx); |
502b8322 | 147 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); |
5eb2a9f2 | 148 | static void set_used_decls (tree); |
502b8322 AJ |
149 | static void mark_label_nuses (rtx); |
150 | static hashval_t const_int_htab_hash (const void *); | |
151 | static int const_int_htab_eq (const void *, const void *); | |
152 | static hashval_t const_double_htab_hash (const void *); | |
153 | static int const_double_htab_eq (const void *, const void *); | |
154 | static rtx lookup_const_double (rtx); | |
091a3ac7 CF |
155 | static hashval_t const_fixed_htab_hash (const void *); |
156 | static int const_fixed_htab_eq (const void *, const void *); | |
157 | static rtx lookup_const_fixed (rtx); | |
502b8322 AJ |
158 | static hashval_t mem_attrs_htab_hash (const void *); |
159 | static int mem_attrs_htab_eq (const void *, const void *); | |
4862826d | 160 | static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int, |
09e881c9 | 161 | addr_space_t, enum machine_mode); |
502b8322 AJ |
162 | static hashval_t reg_attrs_htab_hash (const void *); |
163 | static int reg_attrs_htab_eq (const void *, const void *); | |
164 | static reg_attrs *get_reg_attrs (tree, int); | |
a73b091d | 165 | static rtx gen_const_vector (enum machine_mode, int); |
32b32b16 | 166 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 167 | |
6b24c259 JH |
168 | /* Probability of the conditional branch currently proceeded by try_split. |
169 | Set to -1 otherwise. */ | |
170 | int split_branch_probability = -1; | |
ca695ac9 | 171 | \f |
c13e8210 MM |
172 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
173 | ||
174 | static hashval_t | |
502b8322 | 175 | const_int_htab_hash (const void *x) |
c13e8210 | 176 | { |
f7d504c2 | 177 | return (hashval_t) INTVAL ((const_rtx) x); |
c13e8210 MM |
178 | } |
179 | ||
cc2902df | 180 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
181 | CONST_INT) is the same as that given by Y (which is really a |
182 | HOST_WIDE_INT *). */ | |
183 | ||
184 | static int | |
502b8322 | 185 | const_int_htab_eq (const void *x, const void *y) |
c13e8210 | 186 | { |
f7d504c2 | 187 | return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y)); |
5692c7bc ZW |
188 | } |
189 | ||
190 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
191 | static hashval_t | |
502b8322 | 192 | const_double_htab_hash (const void *x) |
5692c7bc | 193 | { |
f7d504c2 | 194 | const_rtx const value = (const_rtx) x; |
46b33600 | 195 | hashval_t h; |
5692c7bc | 196 | |
46b33600 RH |
197 | if (GET_MODE (value) == VOIDmode) |
198 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
199 | else | |
fe352c29 | 200 | { |
15c812e3 | 201 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
202 | /* MODE is used in the comparison, so it should be in the hash. */ |
203 | h ^= GET_MODE (value); | |
204 | } | |
5692c7bc ZW |
205 | return h; |
206 | } | |
207 | ||
cc2902df | 208 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc ZW |
209 | is the same as that represented by Y (really a ...) */ |
210 | static int | |
502b8322 | 211 | const_double_htab_eq (const void *x, const void *y) |
5692c7bc | 212 | { |
f7d504c2 | 213 | const_rtx const a = (const_rtx)x, b = (const_rtx)y; |
5692c7bc ZW |
214 | |
215 | if (GET_MODE (a) != GET_MODE (b)) | |
216 | return 0; | |
8580f7a0 RH |
217 | if (GET_MODE (a) == VOIDmode) |
218 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
219 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
220 | else | |
221 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
222 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
223 | } |
224 | ||
091a3ac7 CF |
225 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
226 | ||
227 | static hashval_t | |
228 | const_fixed_htab_hash (const void *x) | |
229 | { | |
3101faab | 230 | const_rtx const value = (const_rtx) x; |
091a3ac7 CF |
231 | hashval_t h; |
232 | ||
233 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
234 | /* MODE is used in the comparison, so it should be in the hash. */ | |
235 | h ^= GET_MODE (value); | |
236 | return h; | |
237 | } | |
238 | ||
239 | /* Returns nonzero if the value represented by X (really a ...) | |
240 | is the same as that represented by Y (really a ...). */ | |
241 | ||
242 | static int | |
243 | const_fixed_htab_eq (const void *x, const void *y) | |
244 | { | |
3101faab | 245 | const_rtx const a = (const_rtx) x, b = (const_rtx) y; |
091a3ac7 CF |
246 | |
247 | if (GET_MODE (a) != GET_MODE (b)) | |
248 | return 0; | |
249 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
250 | } | |
251 | ||
173b24b9 RK |
252 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
253 | ||
254 | static hashval_t | |
502b8322 | 255 | mem_attrs_htab_hash (const void *x) |
173b24b9 | 256 | { |
f7d504c2 | 257 | const mem_attrs *const p = (const mem_attrs *) x; |
173b24b9 RK |
258 | |
259 | return (p->alias ^ (p->align * 1000) | |
09e881c9 | 260 | ^ (p->addrspace * 4000) |
173b24b9 RK |
261 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) |
262 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
78b76d08 | 263 | ^ (size_t) iterative_hash_expr (p->expr, 0)); |
173b24b9 RK |
264 | } |
265 | ||
cc2902df | 266 | /* Returns nonzero if the value represented by X (which is really a |
173b24b9 RK |
267 | mem_attrs *) is the same as that given by Y (which is also really a |
268 | mem_attrs *). */ | |
c13e8210 MM |
269 | |
270 | static int | |
502b8322 | 271 | mem_attrs_htab_eq (const void *x, const void *y) |
c13e8210 | 272 | { |
741ac903 KG |
273 | const mem_attrs *const p = (const mem_attrs *) x; |
274 | const mem_attrs *const q = (const mem_attrs *) y; | |
173b24b9 | 275 | |
78b76d08 SB |
276 | return (p->alias == q->alias && p->offset == q->offset |
277 | && p->size == q->size && p->align == q->align | |
09e881c9 | 278 | && p->addrspace == q->addrspace |
78b76d08 SB |
279 | && (p->expr == q->expr |
280 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
281 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
282 | } |
283 | ||
173b24b9 | 284 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
10b76d73 RK |
285 | one identical to it is not already in the table. We are doing this for |
286 | MEM of mode MODE. */ | |
173b24b9 RK |
287 | |
288 | static mem_attrs * | |
4862826d | 289 | get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size, |
09e881c9 | 290 | unsigned int align, addr_space_t addrspace, enum machine_mode mode) |
173b24b9 RK |
291 | { |
292 | mem_attrs attrs; | |
293 | void **slot; | |
294 | ||
bb056a77 OH |
295 | /* If everything is the default, we can just return zero. |
296 | This must match what the corresponding MEM_* macros return when the | |
297 | field is not present. */ | |
09e881c9 | 298 | if (alias == 0 && expr == 0 && offset == 0 && addrspace == 0 |
10b76d73 RK |
299 | && (size == 0 |
300 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
bb056a77 OH |
301 | && (STRICT_ALIGNMENT && mode != BLKmode |
302 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
10b76d73 RK |
303 | return 0; |
304 | ||
173b24b9 | 305 | attrs.alias = alias; |
998d7deb | 306 | attrs.expr = expr; |
173b24b9 RK |
307 | attrs.offset = offset; |
308 | attrs.size = size; | |
309 | attrs.align = align; | |
09e881c9 | 310 | attrs.addrspace = addrspace; |
173b24b9 RK |
311 | |
312 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
313 | if (*slot == 0) | |
314 | { | |
a9429e29 | 315 | *slot = ggc_alloc_mem_attrs (); |
173b24b9 RK |
316 | memcpy (*slot, &attrs, sizeof (mem_attrs)); |
317 | } | |
318 | ||
1b4572a8 | 319 | return (mem_attrs *) *slot; |
c13e8210 MM |
320 | } |
321 | ||
a560d4d4 JH |
322 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
323 | ||
324 | static hashval_t | |
502b8322 | 325 | reg_attrs_htab_hash (const void *x) |
a560d4d4 | 326 | { |
741ac903 | 327 | const reg_attrs *const p = (const reg_attrs *) x; |
a560d4d4 | 328 | |
9841210f | 329 | return ((p->offset * 1000) ^ (intptr_t) p->decl); |
a560d4d4 JH |
330 | } |
331 | ||
6356f892 | 332 | /* Returns nonzero if the value represented by X (which is really a |
a560d4d4 JH |
333 | reg_attrs *) is the same as that given by Y (which is also really a |
334 | reg_attrs *). */ | |
335 | ||
336 | static int | |
502b8322 | 337 | reg_attrs_htab_eq (const void *x, const void *y) |
a560d4d4 | 338 | { |
741ac903 KG |
339 | const reg_attrs *const p = (const reg_attrs *) x; |
340 | const reg_attrs *const q = (const reg_attrs *) y; | |
a560d4d4 JH |
341 | |
342 | return (p->decl == q->decl && p->offset == q->offset); | |
343 | } | |
344 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
345 | one identical to it is not already in the table. We are doing this for | |
346 | MEM of mode MODE. */ | |
347 | ||
348 | static reg_attrs * | |
502b8322 | 349 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
350 | { |
351 | reg_attrs attrs; | |
352 | void **slot; | |
353 | ||
354 | /* If everything is the default, we can just return zero. */ | |
355 | if (decl == 0 && offset == 0) | |
356 | return 0; | |
357 | ||
358 | attrs.decl = decl; | |
359 | attrs.offset = offset; | |
360 | ||
361 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
362 | if (*slot == 0) | |
363 | { | |
a9429e29 | 364 | *slot = ggc_alloc_reg_attrs (); |
a560d4d4 JH |
365 | memcpy (*slot, &attrs, sizeof (reg_attrs)); |
366 | } | |
367 | ||
1b4572a8 | 368 | return (reg_attrs *) *slot; |
a560d4d4 JH |
369 | } |
370 | ||
6fb5fa3c DB |
371 | |
372 | #if !HAVE_blockage | |
373 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule | |
374 | across this insn. */ | |
375 | ||
376 | rtx | |
377 | gen_blockage (void) | |
378 | { | |
379 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
380 | MEM_VOLATILE_P (x) = true; | |
381 | return x; | |
382 | } | |
383 | #endif | |
384 | ||
385 | ||
08394eef BS |
386 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
387 | don't attempt to share with the various global pieces of rtl (such as | |
388 | frame_pointer_rtx). */ | |
389 | ||
390 | rtx | |
502b8322 | 391 | gen_raw_REG (enum machine_mode mode, int regno) |
08394eef BS |
392 | { |
393 | rtx x = gen_rtx_raw_REG (mode, regno); | |
394 | ORIGINAL_REGNO (x) = regno; | |
395 | return x; | |
396 | } | |
397 | ||
c5c76735 JL |
398 | /* There are some RTL codes that require special attention; the generation |
399 | functions do the raw handling. If you add to this list, modify | |
400 | special_rtx in gengenrtl.c as well. */ | |
401 | ||
3b80f6ca | 402 | rtx |
502b8322 | 403 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca | 404 | { |
c13e8210 MM |
405 | void **slot; |
406 | ||
3b80f6ca | 407 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 408 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
409 | |
410 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
411 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
412 | return const_true_rtx; | |
413 | #endif | |
414 | ||
c13e8210 | 415 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
416 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
417 | (hashval_t) arg, INSERT); | |
29105cea | 418 | if (*slot == 0) |
1f8f4a0b | 419 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
420 | |
421 | return (rtx) *slot; | |
3b80f6ca RH |
422 | } |
423 | ||
2496c7bd | 424 | rtx |
502b8322 | 425 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2496c7bd LB |
426 | { |
427 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
428 | } | |
429 | ||
5692c7bc ZW |
430 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
431 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
432 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
433 | ||
434 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
435 | hash table. If so, return its counterpart; otherwise add it | |
436 | to the hash table and return it. */ | |
437 | static rtx | |
502b8322 | 438 | lookup_const_double (rtx real) |
5692c7bc ZW |
439 | { |
440 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
441 | if (*slot == 0) | |
442 | *slot = real; | |
443 | ||
444 | return (rtx) *slot; | |
445 | } | |
29105cea | 446 | |
5692c7bc ZW |
447 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
448 | VALUE in mode MODE. */ | |
0133b7d9 | 449 | rtx |
502b8322 | 450 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
0133b7d9 | 451 | { |
5692c7bc ZW |
452 | rtx real = rtx_alloc (CONST_DOUBLE); |
453 | PUT_MODE (real, mode); | |
454 | ||
9e254451 | 455 | real->u.rv = value; |
5692c7bc ZW |
456 | |
457 | return lookup_const_double (real); | |
458 | } | |
459 | ||
091a3ac7 CF |
460 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
461 | hash table. If so, return its counterpart; otherwise add it | |
462 | to the hash table and return it. */ | |
463 | ||
464 | static rtx | |
465 | lookup_const_fixed (rtx fixed) | |
466 | { | |
467 | void **slot = htab_find_slot (const_fixed_htab, fixed, INSERT); | |
468 | if (*slot == 0) | |
469 | *slot = fixed; | |
470 | ||
471 | return (rtx) *slot; | |
472 | } | |
473 | ||
474 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
475 | VALUE in mode MODE. */ | |
476 | ||
477 | rtx | |
478 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, enum machine_mode mode) | |
479 | { | |
480 | rtx fixed = rtx_alloc (CONST_FIXED); | |
481 | PUT_MODE (fixed, mode); | |
482 | ||
483 | fixed->u.fv = value; | |
484 | ||
485 | return lookup_const_fixed (fixed); | |
486 | } | |
487 | ||
3e93ff81 AS |
488 | /* Constructs double_int from rtx CST. */ |
489 | ||
490 | double_int | |
491 | rtx_to_double_int (const_rtx cst) | |
492 | { | |
493 | double_int r; | |
494 | ||
495 | if (CONST_INT_P (cst)) | |
496 | r = shwi_to_double_int (INTVAL (cst)); | |
497 | else if (CONST_DOUBLE_P (cst) && GET_MODE (cst) == VOIDmode) | |
498 | { | |
499 | r.low = CONST_DOUBLE_LOW (cst); | |
500 | r.high = CONST_DOUBLE_HIGH (cst); | |
501 | } | |
502 | else | |
503 | gcc_unreachable (); | |
504 | ||
505 | return r; | |
506 | } | |
507 | ||
508 | ||
54fb1ae0 AS |
509 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as |
510 | a double_int. */ | |
511 | ||
512 | rtx | |
513 | immed_double_int_const (double_int i, enum machine_mode mode) | |
514 | { | |
515 | return immed_double_const (i.low, i.high, mode); | |
516 | } | |
517 | ||
5692c7bc ZW |
518 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
519 | of ints: I0 is the low-order word and I1 is the high-order word. | |
520 | Do not use this routine for non-integer modes; convert to | |
521 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
522 | ||
523 | rtx | |
502b8322 | 524 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
5692c7bc ZW |
525 | { |
526 | rtx value; | |
527 | unsigned int i; | |
528 | ||
65acccdd ZD |
529 | /* There are the following cases (note that there are no modes with |
530 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT): | |
531 | ||
532 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
533 | gen_int_mode. | |
534 | 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of | |
535 | the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only | |
b8698a0f | 536 | from copies of the sign bit, and sign of i0 and i1 are the same), then |
65acccdd ZD |
537 | we return a CONST_INT for i0. |
538 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ | |
5692c7bc ZW |
539 | if (mode != VOIDmode) |
540 | { | |
5b0264cb NS |
541 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
542 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
543 | /* We can get a 0 for an error mark. */ | |
544 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
545 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT); | |
5692c7bc | 546 | |
65acccdd ZD |
547 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
548 | return gen_int_mode (i0, mode); | |
549 | ||
550 | gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT); | |
5692c7bc ZW |
551 | } |
552 | ||
553 | /* If this integer fits in one word, return a CONST_INT. */ | |
554 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
555 | return GEN_INT (i0); | |
556 | ||
557 | /* We use VOIDmode for integers. */ | |
558 | value = rtx_alloc (CONST_DOUBLE); | |
559 | PUT_MODE (value, VOIDmode); | |
560 | ||
561 | CONST_DOUBLE_LOW (value) = i0; | |
562 | CONST_DOUBLE_HIGH (value) = i1; | |
563 | ||
564 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
565 | XWINT (value, i) = 0; | |
566 | ||
567 | return lookup_const_double (value); | |
0133b7d9 RH |
568 | } |
569 | ||
3b80f6ca | 570 | rtx |
502b8322 | 571 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3b80f6ca RH |
572 | { |
573 | /* In case the MD file explicitly references the frame pointer, have | |
574 | all such references point to the same frame pointer. This is | |
575 | used during frame pointer elimination to distinguish the explicit | |
576 | references to these registers from pseudos that happened to be | |
577 | assigned to them. | |
578 | ||
579 | If we have eliminated the frame pointer or arg pointer, we will | |
580 | be using it as a normal register, for example as a spill | |
581 | register. In such cases, we might be accessing it in a mode that | |
582 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
583 | ||
584 | Also don't do this when we are making new REGs in reload, since | |
585 | we don't want to get confused with the real pointers. */ | |
586 | ||
587 | if (mode == Pmode && !reload_in_progress) | |
588 | { | |
e10c79fe LB |
589 | if (regno == FRAME_POINTER_REGNUM |
590 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca | 591 | return frame_pointer_rtx; |
e3339d0f | 592 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
e10c79fe LB |
593 | if (regno == HARD_FRAME_POINTER_REGNUM |
594 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
595 | return hard_frame_pointer_rtx; |
596 | #endif | |
e3339d0f | 597 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && !HARD_FRAME_POINTER_IS_ARG_POINTER |
bcb33994 | 598 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
599 | return arg_pointer_rtx; |
600 | #endif | |
601 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 602 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
603 | return return_address_pointer_rtx; |
604 | #endif | |
fc555370 | 605 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
bf9412cd | 606 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM |
2d67bd7b | 607 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 608 | return pic_offset_table_rtx; |
bcb33994 | 609 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
610 | return stack_pointer_rtx; |
611 | } | |
612 | ||
006a94b0 | 613 | #if 0 |
6cde4876 | 614 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
615 | an existing entry in that table to avoid useless generation of RTL. |
616 | ||
617 | This code is disabled for now until we can fix the various backends | |
618 | which depend on having non-shared hard registers in some cases. Long | |
619 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
620 | on the amount of useless RTL that gets generated. |
621 | ||
622 | We'll also need to fix some code that runs after reload that wants to | |
623 | set ORIGINAL_REGNO. */ | |
624 | ||
6cde4876 JL |
625 | if (cfun |
626 | && cfun->emit | |
627 | && regno_reg_rtx | |
628 | && regno < FIRST_PSEUDO_REGISTER | |
629 | && reg_raw_mode[regno] == mode) | |
630 | return regno_reg_rtx[regno]; | |
006a94b0 | 631 | #endif |
6cde4876 | 632 | |
08394eef | 633 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
634 | } |
635 | ||
41472af8 | 636 | rtx |
502b8322 | 637 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
41472af8 MM |
638 | { |
639 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
640 | ||
641 | /* This field is not cleared by the mere allocation of the rtx, so | |
642 | we clear it here. */ | |
173b24b9 | 643 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
644 | |
645 | return rt; | |
646 | } | |
ddef6bc7 | 647 | |
542a8afa RH |
648 | /* Generate a memory referring to non-trapping constant memory. */ |
649 | ||
650 | rtx | |
651 | gen_const_mem (enum machine_mode mode, rtx addr) | |
652 | { | |
653 | rtx mem = gen_rtx_MEM (mode, addr); | |
654 | MEM_READONLY_P (mem) = 1; | |
655 | MEM_NOTRAP_P (mem) = 1; | |
656 | return mem; | |
657 | } | |
658 | ||
bf877a76 R |
659 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
660 | save areas. */ | |
661 | ||
662 | rtx | |
663 | gen_frame_mem (enum machine_mode mode, rtx addr) | |
664 | { | |
665 | rtx mem = gen_rtx_MEM (mode, addr); | |
666 | MEM_NOTRAP_P (mem) = 1; | |
667 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
668 | return mem; | |
669 | } | |
670 | ||
671 | /* Generate a MEM referring to a temporary use of the stack, not part | |
672 | of the fixed stack frame. For example, something which is pushed | |
673 | by a target splitter. */ | |
674 | rtx | |
675 | gen_tmp_stack_mem (enum machine_mode mode, rtx addr) | |
676 | { | |
677 | rtx mem = gen_rtx_MEM (mode, addr); | |
678 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 679 | if (!cfun->calls_alloca) |
bf877a76 R |
680 | set_mem_alias_set (mem, get_frame_alias_set ()); |
681 | return mem; | |
682 | } | |
683 | ||
beb72684 RH |
684 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
685 | this construct would be valid, and false otherwise. */ | |
686 | ||
687 | bool | |
688 | validate_subreg (enum machine_mode omode, enum machine_mode imode, | |
ed7a4b4b | 689 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 690 | { |
beb72684 RH |
691 | unsigned int isize = GET_MODE_SIZE (imode); |
692 | unsigned int osize = GET_MODE_SIZE (omode); | |
693 | ||
694 | /* All subregs must be aligned. */ | |
695 | if (offset % osize != 0) | |
696 | return false; | |
697 | ||
698 | /* The subreg offset cannot be outside the inner object. */ | |
699 | if (offset >= isize) | |
700 | return false; | |
701 | ||
702 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
703 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
704 | Generally, backends are doing something sketchy but it'll take time to | |
705 | fix them all. */ | |
706 | if (omode == word_mode) | |
707 | ; | |
708 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
709 | is the culprit here, and not the backends. */ | |
710 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
711 | ; | |
712 | /* Allow component subregs of complex and vector. Though given the below | |
713 | extraction rules, it's not always clear what that means. */ | |
714 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
715 | && GET_MODE_INNER (imode) == omode) | |
716 | ; | |
717 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
718 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
719 | represent this. It's questionable if this ought to be represented at | |
720 | all -- why can't this all be hidden in post-reload splitters that make | |
721 | arbitrarily mode changes to the registers themselves. */ | |
722 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
723 | ; | |
724 | /* Subregs involving floating point modes are not allowed to | |
725 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
726 | (subreg:SI (reg:DF) 0) isn't. */ | |
727 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
728 | { | |
729 | if (isize != osize) | |
730 | return false; | |
731 | } | |
ddef6bc7 | 732 | |
beb72684 RH |
733 | /* Paradoxical subregs must have offset zero. */ |
734 | if (osize > isize) | |
735 | return offset == 0; | |
736 | ||
737 | /* This is a normal subreg. Verify that the offset is representable. */ | |
738 | ||
739 | /* For hard registers, we already have most of these rules collected in | |
740 | subreg_offset_representable_p. */ | |
741 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
742 | { | |
743 | unsigned int regno = REGNO (reg); | |
744 | ||
745 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
746 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
747 | && GET_MODE_INNER (imode) == omode) | |
748 | ; | |
749 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
750 | return false; | |
ddef6bc7 | 751 | #endif |
beb72684 RH |
752 | |
753 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
754 | } | |
755 | ||
756 | /* For pseudo registers, we want most of the same checks. Namely: | |
757 | If the register no larger than a word, the subreg must be lowpart. | |
758 | If the register is larger than a word, the subreg must be the lowpart | |
759 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
760 | Given that we've already checked mode/offset alignment, we only have | |
761 | to check subword subregs here. */ | |
762 | if (osize < UNITS_PER_WORD) | |
763 | { | |
764 | enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; | |
765 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); | |
766 | if (offset % UNITS_PER_WORD != low_off) | |
767 | return false; | |
768 | } | |
769 | return true; | |
770 | } | |
771 | ||
772 | rtx | |
773 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) | |
774 | { | |
775 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 776 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
777 | } |
778 | ||
173b24b9 RK |
779 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
780 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
781 | ||
ddef6bc7 | 782 | rtx |
502b8322 | 783 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
ddef6bc7 JJ |
784 | { |
785 | enum machine_mode inmode; | |
ddef6bc7 JJ |
786 | |
787 | inmode = GET_MODE (reg); | |
788 | if (inmode == VOIDmode) | |
789 | inmode = mode; | |
e0e08ac2 JH |
790 | return gen_rtx_SUBREG (mode, reg, |
791 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 792 | } |
c5c76735 | 793 | \f |
23b2ce53 | 794 | |
80379f51 PB |
795 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
796 | ||
23b2ce53 | 797 | rtvec |
e34d07f2 | 798 | gen_rtvec (int n, ...) |
23b2ce53 | 799 | { |
80379f51 PB |
800 | int i; |
801 | rtvec rt_val; | |
e34d07f2 | 802 | va_list p; |
23b2ce53 | 803 | |
e34d07f2 | 804 | va_start (p, n); |
23b2ce53 | 805 | |
80379f51 | 806 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 807 | if (n == 0) |
0edf1bb2 JL |
808 | { |
809 | va_end (p); | |
810 | return NULL_RTVEC; | |
811 | } | |
23b2ce53 | 812 | |
80379f51 | 813 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 814 | |
23b2ce53 | 815 | for (i = 0; i < n; i++) |
80379f51 | 816 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 817 | |
e34d07f2 | 818 | va_end (p); |
80379f51 | 819 | return rt_val; |
23b2ce53 RS |
820 | } |
821 | ||
822 | rtvec | |
502b8322 | 823 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 824 | { |
b3694847 SS |
825 | int i; |
826 | rtvec rt_val; | |
23b2ce53 | 827 | |
80379f51 | 828 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 829 | if (n == 0) |
80379f51 | 830 | return NULL_RTVEC; |
23b2ce53 | 831 | |
80379f51 | 832 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
833 | |
834 | for (i = 0; i < n; i++) | |
8f985ec4 | 835 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
836 | |
837 | return rt_val; | |
838 | } | |
839 | \f | |
38ae7651 RS |
840 | /* Return the number of bytes between the start of an OUTER_MODE |
841 | in-memory value and the start of an INNER_MODE in-memory value, | |
842 | given that the former is a lowpart of the latter. It may be a | |
843 | paradoxical lowpart, in which case the offset will be negative | |
844 | on big-endian targets. */ | |
845 | ||
846 | int | |
847 | byte_lowpart_offset (enum machine_mode outer_mode, | |
848 | enum machine_mode inner_mode) | |
849 | { | |
850 | if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)) | |
851 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
852 | else | |
853 | return -subreg_lowpart_offset (inner_mode, outer_mode); | |
854 | } | |
855 | \f | |
23b2ce53 RS |
856 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
857 | This pseudo is assigned the next sequential register number. */ | |
858 | ||
859 | rtx | |
502b8322 | 860 | gen_reg_rtx (enum machine_mode mode) |
23b2ce53 | 861 | { |
b3694847 | 862 | rtx val; |
2e3f842f | 863 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 864 | |
f8335a4f | 865 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 866 | |
2e3f842f L |
867 | /* If a virtual register with bigger mode alignment is generated, |
868 | increase stack alignment estimation because it might be spilled | |
869 | to stack later. */ | |
b8698a0f | 870 | if (SUPPORTS_STACK_ALIGNMENT |
2e3f842f L |
871 | && crtl->stack_alignment_estimated < align |
872 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
873 | { |
874 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
875 | if (crtl->stack_alignment_estimated < min_align) | |
876 | crtl->stack_alignment_estimated = min_align; | |
877 | } | |
2e3f842f | 878 | |
1b3d8f8a GK |
879 | if (generating_concat_p |
880 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
881 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
882 | { |
883 | /* For complex modes, don't make a single pseudo. | |
884 | Instead, make a CONCAT of two pseudos. | |
885 | This allows noncontiguous allocation of the real and imaginary parts, | |
886 | which makes much better code. Besides, allocating DCmode | |
887 | pseudos overstrains reload on some machines like the 386. */ | |
888 | rtx realpart, imagpart; | |
27e58a70 | 889 | enum machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
890 | |
891 | realpart = gen_reg_rtx (partmode); | |
892 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 893 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
894 | } |
895 | ||
a560d4d4 | 896 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 897 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 898 | |
3e029763 | 899 | if (reg_rtx_no == crtl->emit.regno_pointer_align_length) |
23b2ce53 | 900 | { |
3e029763 | 901 | int old_size = crtl->emit.regno_pointer_align_length; |
60564289 | 902 | char *tmp; |
0d4903b8 | 903 | rtx *new1; |
0d4903b8 | 904 | |
60564289 KG |
905 | tmp = XRESIZEVEC (char, crtl->emit.regno_pointer_align, old_size * 2); |
906 | memset (tmp + old_size, 0, old_size); | |
907 | crtl->emit.regno_pointer_align = (unsigned char *) tmp; | |
49ad7cfa | 908 | |
1b4572a8 | 909 | new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, old_size * 2); |
49ad7cfa | 910 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
911 | regno_reg_rtx = new1; |
912 | ||
3e029763 | 913 | crtl->emit.regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
914 | } |
915 | ||
08394eef | 916 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
917 | regno_reg_rtx[reg_rtx_no++] = val; |
918 | return val; | |
919 | } | |
920 | ||
38ae7651 RS |
921 | /* Update NEW with the same attributes as REG, but with OFFSET added |
922 | to the REG_OFFSET. */ | |
a560d4d4 | 923 | |
e53a16e7 | 924 | static void |
60564289 | 925 | update_reg_offset (rtx new_rtx, rtx reg, int offset) |
a560d4d4 | 926 | { |
60564289 | 927 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 928 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
929 | } |
930 | ||
38ae7651 RS |
931 | /* Generate a register with same attributes as REG, but with OFFSET |
932 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
933 | |
934 | rtx | |
935 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, | |
936 | int offset) | |
937 | { | |
60564289 | 938 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 939 | |
60564289 KG |
940 | update_reg_offset (new_rtx, reg, offset); |
941 | return new_rtx; | |
e53a16e7 ILT |
942 | } |
943 | ||
944 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 945 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
946 | |
947 | rtx | |
948 | gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset) | |
949 | { | |
60564289 | 950 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 951 | |
60564289 KG |
952 | update_reg_offset (new_rtx, reg, offset); |
953 | return new_rtx; | |
a560d4d4 JH |
954 | } |
955 | ||
38ae7651 RS |
956 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
957 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
958 | |
959 | void | |
38ae7651 | 960 | adjust_reg_mode (rtx reg, enum machine_mode mode) |
a560d4d4 | 961 | { |
38ae7651 RS |
962 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
963 | PUT_MODE (reg, mode); | |
964 | } | |
965 | ||
966 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
967 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
968 | ||
969 | void | |
970 | set_reg_attrs_from_value (rtx reg, rtx x) | |
971 | { | |
972 | int offset; | |
973 | ||
923ba36f JJ |
974 | /* Hard registers can be reused for multiple purposes within the same |
975 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
976 | on them is wrong. */ | |
977 | if (HARD_REGISTER_P (reg)) | |
978 | return; | |
979 | ||
38ae7651 | 980 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
981 | if (MEM_P (x)) |
982 | { | |
481683e1 | 983 | if (MEM_OFFSET (x) && CONST_INT_P (MEM_OFFSET (x))) |
46b71b03 PB |
984 | REG_ATTRS (reg) |
985 | = get_reg_attrs (MEM_EXPR (x), INTVAL (MEM_OFFSET (x)) + offset); | |
986 | if (MEM_POINTER (x)) | |
0a317111 | 987 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
988 | } |
989 | else if (REG_P (x)) | |
990 | { | |
991 | if (REG_ATTRS (x)) | |
992 | update_reg_offset (reg, x, offset); | |
993 | if (REG_POINTER (x)) | |
994 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); | |
995 | } | |
996 | } | |
997 | ||
998 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
999 | and attributes from X. */ | |
1000 | ||
1001 | rtx | |
1002 | gen_reg_rtx_and_attrs (rtx x) | |
1003 | { | |
1004 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1005 | set_reg_attrs_from_value (reg, x); | |
1006 | return reg; | |
a560d4d4 JH |
1007 | } |
1008 | ||
9d18e06b JZ |
1009 | /* Set the register attributes for registers contained in PARM_RTX. |
1010 | Use needed values from memory attributes of MEM. */ | |
1011 | ||
1012 | void | |
502b8322 | 1013 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1014 | { |
f8cfc6aa | 1015 | if (REG_P (parm_rtx)) |
38ae7651 | 1016 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1017 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1018 | { | |
1019 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1020 | parameter goes both on the stack and in registers. */ | |
1021 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1022 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1023 | { | |
1024 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1025 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1026 | REG_ATTRS (XEXP (x, 0)) |
1027 | = get_reg_attrs (MEM_EXPR (mem), | |
1028 | INTVAL (XEXP (x, 1))); | |
1029 | } | |
1030 | } | |
1031 | } | |
1032 | ||
38ae7651 RS |
1033 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1034 | decl T. */ | |
a560d4d4 | 1035 | |
4e3825db | 1036 | void |
38ae7651 RS |
1037 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1038 | { | |
1039 | if (GET_CODE (x) == SUBREG) | |
fbe6ec81 | 1040 | { |
38ae7651 RS |
1041 | gcc_assert (subreg_lowpart_p (x)); |
1042 | x = SUBREG_REG (x); | |
fbe6ec81 | 1043 | } |
f8cfc6aa | 1044 | if (REG_P (x)) |
38ae7651 RS |
1045 | REG_ATTRS (x) |
1046 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
726612d2 | 1047 | DECL_MODE (t))); |
a560d4d4 JH |
1048 | if (GET_CODE (x) == CONCAT) |
1049 | { | |
1050 | if (REG_P (XEXP (x, 0))) | |
1051 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1052 | if (REG_P (XEXP (x, 1))) | |
1053 | REG_ATTRS (XEXP (x, 1)) | |
1054 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1055 | } | |
1056 | if (GET_CODE (x) == PARALLEL) | |
1057 | { | |
d4afac5b JZ |
1058 | int i, start; |
1059 | ||
1060 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1061 | both on the stack and in registers. */ | |
1062 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1063 | start = 0; | |
1064 | else | |
1065 | start = 1; | |
1066 | ||
1067 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1068 | { |
1069 | rtx y = XVECEXP (x, 0, i); | |
1070 | if (REG_P (XEXP (y, 0))) | |
1071 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1072 | } | |
1073 | } | |
1074 | } | |
1075 | ||
38ae7651 RS |
1076 | /* Assign the RTX X to declaration T. */ |
1077 | ||
1078 | void | |
1079 | set_decl_rtl (tree t, rtx x) | |
1080 | { | |
1081 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1082 | if (x) | |
1083 | set_reg_attrs_for_decl_rtl (t, x); | |
1084 | } | |
1085 | ||
5141868d RS |
1086 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1087 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1088 | |
1089 | void | |
5141868d | 1090 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1091 | { |
1092 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1093 | if (x && !by_reference_p) |
38ae7651 RS |
1094 | set_reg_attrs_for_decl_rtl (t, x); |
1095 | } | |
1096 | ||
754fdcca RK |
1097 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1098 | ||
1099 | void | |
502b8322 | 1100 | mark_user_reg (rtx reg) |
754fdcca RK |
1101 | { |
1102 | if (GET_CODE (reg) == CONCAT) | |
1103 | { | |
1104 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1105 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1106 | } | |
754fdcca | 1107 | else |
5b0264cb NS |
1108 | { |
1109 | gcc_assert (REG_P (reg)); | |
1110 | REG_USERVAR_P (reg) = 1; | |
1111 | } | |
754fdcca RK |
1112 | } |
1113 | ||
86fe05e0 RK |
1114 | /* Identify REG as a probable pointer register and show its alignment |
1115 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1116 | |
1117 | void | |
502b8322 | 1118 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1119 | { |
3502dc9c | 1120 | if (! REG_POINTER (reg)) |
00995e78 | 1121 | { |
3502dc9c | 1122 | REG_POINTER (reg) = 1; |
86fe05e0 | 1123 | |
00995e78 RE |
1124 | if (align) |
1125 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1126 | } | |
1127 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1128 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1129 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1130 | } |
1131 | ||
1132 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1133 | ||
1134 | int | |
502b8322 | 1135 | max_reg_num (void) |
23b2ce53 RS |
1136 | { |
1137 | return reg_rtx_no; | |
1138 | } | |
1139 | ||
1140 | /* Return 1 + the largest label number used so far in the current function. */ | |
1141 | ||
1142 | int | |
502b8322 | 1143 | max_label_num (void) |
23b2ce53 | 1144 | { |
23b2ce53 RS |
1145 | return label_num; |
1146 | } | |
1147 | ||
1148 | /* Return first label number used in this function (if any were used). */ | |
1149 | ||
1150 | int | |
502b8322 | 1151 | get_first_label_num (void) |
23b2ce53 RS |
1152 | { |
1153 | return first_label_num; | |
1154 | } | |
6de9cd9a DN |
1155 | |
1156 | /* If the rtx for label was created during the expansion of a nested | |
1157 | function, then first_label_num won't include this label number. | |
fa10beec | 1158 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1159 | |
1160 | void | |
1161 | maybe_set_first_label_num (rtx x) | |
1162 | { | |
1163 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1164 | first_label_num = CODE_LABEL_NUMBER (x); | |
1165 | } | |
23b2ce53 RS |
1166 | \f |
1167 | /* Return a value representing some low-order bits of X, where the number | |
1168 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1169 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1170 | representation is returned. |
1171 | ||
1172 | This function handles the cases in common between gen_lowpart, below, | |
1173 | and two variants in cse.c and combine.c. These are the cases that can | |
1174 | be safely handled at all points in the compilation. | |
1175 | ||
1176 | If this is not a case we can handle, return 0. */ | |
1177 | ||
1178 | rtx | |
502b8322 | 1179 | gen_lowpart_common (enum machine_mode mode, rtx x) |
23b2ce53 | 1180 | { |
ddef6bc7 | 1181 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1182 | int xsize; |
ddef6bc7 | 1183 | int offset = 0; |
550d1387 GK |
1184 | enum machine_mode innermode; |
1185 | ||
1186 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1187 | so we have to make one up. Yuk. */ | |
1188 | innermode = GET_MODE (x); | |
481683e1 | 1189 | if (CONST_INT_P (x) |
db487452 | 1190 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) |
550d1387 GK |
1191 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1192 | else if (innermode == VOIDmode) | |
1193 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0); | |
b8698a0f | 1194 | |
550d1387 GK |
1195 | xsize = GET_MODE_SIZE (innermode); |
1196 | ||
5b0264cb | 1197 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1198 | |
550d1387 | 1199 | if (innermode == mode) |
23b2ce53 RS |
1200 | return x; |
1201 | ||
1202 | /* MODE must occupy no more words than the mode of X. */ | |
550d1387 GK |
1203 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1204 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
23b2ce53 RS |
1205 | return 0; |
1206 | ||
53501a19 | 1207 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
3d8bf70f | 1208 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
53501a19 BS |
1209 | return 0; |
1210 | ||
550d1387 | 1211 | offset = subreg_lowpart_offset (mode, innermode); |
23b2ce53 RS |
1212 | |
1213 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1214 | && (GET_MODE_CLASS (mode) == MODE_INT |
1215 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1216 | { |
1217 | /* If we are getting the low-order part of something that has been | |
1218 | sign- or zero-extended, we can either just use the object being | |
1219 | extended or make a narrower extension. If we want an even smaller | |
1220 | piece than the size of the object being extended, call ourselves | |
1221 | recursively. | |
1222 | ||
1223 | This case is used mostly by combine and cse. */ | |
1224 | ||
1225 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1226 | return XEXP (x, 0); | |
550d1387 | 1227 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
23b2ce53 | 1228 | return gen_lowpart_common (mode, XEXP (x, 0)); |
550d1387 | 1229 | else if (msize < xsize) |
3b80f6ca | 1230 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1231 | } |
f8cfc6aa | 1232 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
550d1387 | 1233 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
481683e1 | 1234 | || GET_CODE (x) == CONST_DOUBLE || CONST_INT_P (x)) |
550d1387 | 1235 | return simplify_gen_subreg (mode, x, innermode, offset); |
8aada4ad | 1236 | |
23b2ce53 RS |
1237 | /* Otherwise, we can't do this. */ |
1238 | return 0; | |
1239 | } | |
1240 | \f | |
ccba022b | 1241 | rtx |
502b8322 | 1242 | gen_highpart (enum machine_mode mode, rtx x) |
ccba022b | 1243 | { |
ddef6bc7 | 1244 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1245 | rtx result; |
ddef6bc7 | 1246 | |
ccba022b RS |
1247 | /* This case loses if X is a subreg. To catch bugs early, |
1248 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1249 | gcc_assert (msize <= UNITS_PER_WORD |
1250 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1251 | |
e0e08ac2 JH |
1252 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1253 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb | 1254 | gcc_assert (result); |
b8698a0f | 1255 | |
09482e0d JW |
1256 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1257 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1258 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1259 | if (MEM_P (result)) |
1260 | { | |
1261 | result = validize_mem (result); | |
1262 | gcc_assert (result); | |
1263 | } | |
b8698a0f | 1264 | |
e0e08ac2 JH |
1265 | return result; |
1266 | } | |
5222e470 | 1267 | |
26d249eb | 1268 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1269 | be VOIDmode constant. */ |
1270 | rtx | |
502b8322 | 1271 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
5222e470 JH |
1272 | { |
1273 | if (GET_MODE (exp) != VOIDmode) | |
1274 | { | |
5b0264cb | 1275 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1276 | return gen_highpart (outermode, exp); |
1277 | } | |
1278 | return simplify_gen_subreg (outermode, exp, innermode, | |
1279 | subreg_highpart_offset (outermode, innermode)); | |
1280 | } | |
68252e27 | 1281 | |
38ae7651 | 1282 | /* Return the SUBREG_BYTE for an OUTERMODE lowpart of an INNERMODE value. */ |
8698cce3 | 1283 | |
e0e08ac2 | 1284 | unsigned int |
502b8322 | 1285 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
e0e08ac2 JH |
1286 | { |
1287 | unsigned int offset = 0; | |
1288 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1289 | |
e0e08ac2 | 1290 | if (difference > 0) |
ccba022b | 1291 | { |
e0e08ac2 JH |
1292 | if (WORDS_BIG_ENDIAN) |
1293 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1294 | if (BYTES_BIG_ENDIAN) | |
1295 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1296 | } |
ddef6bc7 | 1297 | |
e0e08ac2 | 1298 | return offset; |
ccba022b | 1299 | } |
eea50aa0 | 1300 | |
e0e08ac2 JH |
1301 | /* Return offset in bytes to get OUTERMODE high part |
1302 | of the value in mode INNERMODE stored in memory in target format. */ | |
1303 | unsigned int | |
502b8322 | 1304 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
eea50aa0 JH |
1305 | { |
1306 | unsigned int offset = 0; | |
1307 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1308 | ||
5b0264cb | 1309 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
e0e08ac2 | 1310 | |
eea50aa0 JH |
1311 | if (difference > 0) |
1312 | { | |
e0e08ac2 | 1313 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1314 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1315 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1316 | offset += difference % UNITS_PER_WORD; |
1317 | } | |
1318 | ||
e0e08ac2 | 1319 | return offset; |
eea50aa0 | 1320 | } |
ccba022b | 1321 | |
23b2ce53 RS |
1322 | /* Return 1 iff X, assumed to be a SUBREG, |
1323 | refers to the least significant part of its containing reg. | |
1324 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1325 | ||
1326 | int | |
fa233e34 | 1327 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1328 | { |
1329 | if (GET_CODE (x) != SUBREG) | |
1330 | return 1; | |
a3a03040 RK |
1331 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1332 | return 0; | |
23b2ce53 | 1333 | |
e0e08ac2 JH |
1334 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1335 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1336 | } |
1337 | \f | |
ddef6bc7 JJ |
1338 | /* Return subword OFFSET of operand OP. |
1339 | The word number, OFFSET, is interpreted as the word number starting | |
1340 | at the low-order address. OFFSET 0 is the low-order word if not | |
1341 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1342 | ||
1343 | If we cannot extract the required word, we return zero. Otherwise, | |
1344 | an rtx corresponding to the requested word will be returned. | |
1345 | ||
1346 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1347 | reload has completed, a valid address will always be returned. After | |
1348 | reload, if a valid address cannot be returned, we return zero. | |
1349 | ||
1350 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1351 | it is the responsibility of the caller. | |
1352 | ||
1353 | MODE is the mode of OP in case it is a CONST_INT. | |
1354 | ||
1355 | ??? This is still rather broken for some cases. The problem for the | |
1356 | moment is that all callers of this thing provide no 'goal mode' to | |
1357 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1358 | in a word based SUBREG world. |
1359 | Now use of this function can be deprecated by simplify_subreg in most | |
1360 | cases. | |
1361 | */ | |
ddef6bc7 JJ |
1362 | |
1363 | rtx | |
502b8322 | 1364 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
ddef6bc7 JJ |
1365 | { |
1366 | if (mode == VOIDmode) | |
1367 | mode = GET_MODE (op); | |
1368 | ||
5b0264cb | 1369 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1370 | |
30f7a378 | 1371 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1372 | if (mode != BLKmode |
1373 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1374 | return 0; | |
1375 | ||
30f7a378 | 1376 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1377 | if (mode != BLKmode |
1378 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1379 | return const0_rtx; | |
1380 | ||
ddef6bc7 | 1381 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1382 | if (MEM_P (op)) |
ddef6bc7 | 1383 | { |
60564289 | 1384 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1385 | |
f1ec5147 | 1386 | if (! validate_address) |
60564289 | 1387 | return new_rtx; |
f1ec5147 RK |
1388 | |
1389 | else if (reload_completed) | |
ddef6bc7 | 1390 | { |
09e881c9 BE |
1391 | if (! strict_memory_address_addr_space_p (word_mode, |
1392 | XEXP (new_rtx, 0), | |
1393 | MEM_ADDR_SPACE (op))) | |
f1ec5147 | 1394 | return 0; |
ddef6bc7 | 1395 | } |
f1ec5147 | 1396 | else |
60564289 | 1397 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1398 | } |
1399 | ||
0631e0bf JH |
1400 | /* Rest can be handled by simplify_subreg. */ |
1401 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1402 | } |
1403 | ||
535a42b1 NS |
1404 | /* Similar to `operand_subword', but never return 0. If we can't |
1405 | extract the required subword, put OP into a register and try again. | |
1406 | The second attempt must succeed. We always validate the address in | |
1407 | this case. | |
23b2ce53 RS |
1408 | |
1409 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1410 | ||
1411 | rtx | |
502b8322 | 1412 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
23b2ce53 | 1413 | { |
ddef6bc7 | 1414 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1415 | |
1416 | if (result) | |
1417 | return result; | |
1418 | ||
1419 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1420 | { |
1421 | /* If this is a register which can not be accessed by words, copy it | |
1422 | to a pseudo register. */ | |
f8cfc6aa | 1423 | if (REG_P (op)) |
77e6b0eb JC |
1424 | op = copy_to_reg (op); |
1425 | else | |
1426 | op = force_reg (mode, op); | |
1427 | } | |
23b2ce53 | 1428 | |
ddef6bc7 | 1429 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1430 | gcc_assert (result); |
23b2ce53 RS |
1431 | |
1432 | return result; | |
1433 | } | |
1434 | \f | |
2b3493c8 AK |
1435 | /* Returns 1 if both MEM_EXPR can be considered equal |
1436 | and 0 otherwise. */ | |
1437 | ||
1438 | int | |
4f588890 | 1439 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1440 | { |
1441 | if (expr1 == expr2) | |
1442 | return 1; | |
1443 | ||
1444 | if (! expr1 || ! expr2) | |
1445 | return 0; | |
1446 | ||
1447 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1448 | return 0; | |
1449 | ||
55b34b5f | 1450 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1451 | } |
1452 | ||
805903b5 JJ |
1453 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1454 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1455 | -1 if not known. */ | |
1456 | ||
1457 | int | |
d9223014 | 1458 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1459 | { |
1460 | tree expr; | |
1461 | unsigned HOST_WIDE_INT offset; | |
1462 | ||
1463 | /* This function can't use | |
1464 | if (!MEM_EXPR (mem) || !MEM_OFFSET (mem) | |
1465 | || !CONST_INT_P (MEM_OFFSET (mem)) | |
e80c2726 RG |
1466 | || (MAX (MEM_ALIGN (mem), |
1467 | get_object_alignment (MEM_EXPR (mem), align)) | |
805903b5 JJ |
1468 | < align)) |
1469 | return -1; | |
1470 | else | |
1471 | return (- INTVAL (MEM_OFFSET (mem))) & (align / BITS_PER_UNIT - 1); | |
1472 | for two reasons: | |
1473 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1474 | for <variable>. get_inner_reference doesn't handle it and | |
1475 | even if it did, the alignment in that case needs to be determined | |
1476 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1477 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1478 | isn't sufficiently aligned, the object it is in might be. */ | |
1479 | gcc_assert (MEM_P (mem)); | |
1480 | expr = MEM_EXPR (mem); | |
1481 | if (expr == NULL_TREE | |
1482 | || MEM_OFFSET (mem) == NULL_RTX | |
1483 | || !CONST_INT_P (MEM_OFFSET (mem))) | |
1484 | return -1; | |
1485 | ||
1486 | offset = INTVAL (MEM_OFFSET (mem)); | |
1487 | if (DECL_P (expr)) | |
1488 | { | |
1489 | if (DECL_ALIGN (expr) < align) | |
1490 | return -1; | |
1491 | } | |
1492 | else if (INDIRECT_REF_P (expr)) | |
1493 | { | |
1494 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1495 | return -1; | |
1496 | } | |
1497 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1498 | { | |
1499 | while (1) | |
1500 | { | |
1501 | tree inner = TREE_OPERAND (expr, 0); | |
1502 | tree field = TREE_OPERAND (expr, 1); | |
1503 | tree byte_offset = component_ref_field_offset (expr); | |
1504 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1505 | ||
1506 | if (!byte_offset | |
1507 | || !host_integerp (byte_offset, 1) | |
1508 | || !host_integerp (bit_offset, 1)) | |
1509 | return -1; | |
1510 | ||
1511 | offset += tree_low_cst (byte_offset, 1); | |
1512 | offset += tree_low_cst (bit_offset, 1) / BITS_PER_UNIT; | |
1513 | ||
1514 | if (inner == NULL_TREE) | |
1515 | { | |
1516 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1517 | < (unsigned int) align) | |
1518 | return -1; | |
1519 | break; | |
1520 | } | |
1521 | else if (DECL_P (inner)) | |
1522 | { | |
1523 | if (DECL_ALIGN (inner) < align) | |
1524 | return -1; | |
1525 | break; | |
1526 | } | |
1527 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1528 | return -1; | |
1529 | expr = inner; | |
1530 | } | |
1531 | } | |
1532 | else | |
1533 | return -1; | |
1534 | ||
1535 | return offset & ((align / BITS_PER_UNIT) - 1); | |
1536 | } | |
1537 | ||
6926c713 | 1538 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1539 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1540 | if we are making a new object of this type. BITPOS is nonzero if |
1541 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1542 | |
1543 | void | |
502b8322 AJ |
1544 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1545 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1546 | { |
268f7033 UW |
1547 | alias_set_type alias; |
1548 | tree expr = NULL; | |
1549 | rtx offset = NULL_RTX; | |
1550 | rtx size = NULL_RTX; | |
1551 | unsigned int align = BITS_PER_UNIT; | |
6f1087be | 1552 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 RK |
1553 | tree type; |
1554 | ||
1555 | /* It can happen that type_for_mode was given a mode for which there | |
1556 | is no language-level type. In which case it returns NULL, which | |
1557 | we can see here. */ | |
1558 | if (t == NULL_TREE) | |
1559 | return; | |
1560 | ||
1561 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1562 | if (type == error_mark_node) |
1563 | return; | |
173b24b9 | 1564 | |
173b24b9 RK |
1565 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1566 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1567 | info. Callers should not set DECL_RTL until after the call to | |
1568 | set_mem_attributes. */ | |
5b0264cb | 1569 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1570 | |
738cc472 | 1571 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 RK |
1572 | front-end routine) and use it. */ |
1573 | alias = get_alias_set (t); | |
173b24b9 | 1574 | |
a5e9c810 | 1575 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
07cb6e8c JM |
1576 | MEM_IN_STRUCT_P (ref) |
1577 | = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE; | |
f8ad8d7c | 1578 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1579 | |
8ac61af7 RK |
1580 | /* If we are making an object of this type, or if this is a DECL, we know |
1581 | that it is a scalar if the type is not an aggregate. */ | |
07cb6e8c JM |
1582 | if ((objectp || DECL_P (t)) |
1583 | && ! AGGREGATE_TYPE_P (type) | |
1584 | && TREE_CODE (type) != COMPLEX_TYPE) | |
173b24b9 RK |
1585 | MEM_SCALAR_P (ref) = 1; |
1586 | ||
268f7033 UW |
1587 | /* Default values from pre-existing memory attributes if present. */ |
1588 | if (MEM_ATTRS (ref)) | |
1589 | { | |
1590 | /* ??? Can this ever happen? Calling this routine on a MEM that | |
1591 | already carries memory attributes should probably be invalid. */ | |
1592 | expr = MEM_EXPR (ref); | |
1593 | offset = MEM_OFFSET (ref); | |
1594 | size = MEM_SIZE (ref); | |
1595 | align = MEM_ALIGN (ref); | |
1596 | } | |
1597 | ||
1598 | /* Otherwise, default values from the mode of the MEM reference. */ | |
1599 | else if (GET_MODE (ref) != BLKmode) | |
1600 | { | |
1601 | /* Respect mode size. */ | |
1602 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (ref))); | |
1603 | /* ??? Is this really necessary? We probably should always get | |
1604 | the size from the type below. */ | |
1605 | ||
1606 | /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type; | |
1607 | if T is an object, always compute the object alignment below. */ | |
1608 | if (STRICT_ALIGNMENT && TYPE_P (t)) | |
1609 | align = GET_MODE_ALIGNMENT (GET_MODE (ref)); | |
1610 | /* ??? If T is a type, respecting mode alignment may *also* be wrong | |
1611 | e.g. if the type carries an alignment attribute. Should we be | |
1612 | able to simply always use TYPE_ALIGN? */ | |
1613 | } | |
1614 | ||
c3d32120 RK |
1615 | /* We can set the alignment from the type if we are making an object, |
1616 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
a80903ff | 1617 | if (objectp || TREE_CODE (t) == INDIRECT_REF || TYPE_ALIGN_OK (type)) |
c3d32120 | 1618 | align = MAX (align, TYPE_ALIGN (type)); |
a80903ff | 1619 | |
70f34814 RG |
1620 | else if (TREE_CODE (t) == MEM_REF) |
1621 | { | |
a80903ff | 1622 | tree op0 = TREE_OPERAND (t, 0); |
3e32c761 RG |
1623 | if (TREE_CODE (op0) == ADDR_EXPR |
1624 | && (DECL_P (TREE_OPERAND (op0, 0)) | |
1625 | || CONSTANT_CLASS_P (TREE_OPERAND (op0, 0)))) | |
70f34814 | 1626 | { |
3e32c761 RG |
1627 | if (DECL_P (TREE_OPERAND (op0, 0))) |
1628 | align = DECL_ALIGN (TREE_OPERAND (op0, 0)); | |
1629 | else if (CONSTANT_CLASS_P (TREE_OPERAND (op0, 0))) | |
1630 | { | |
1631 | align = TYPE_ALIGN (TREE_TYPE (TREE_OPERAND (op0, 0))); | |
70f34814 | 1632 | #ifdef CONSTANT_ALIGNMENT |
3e32c761 | 1633 | align = CONSTANT_ALIGNMENT (TREE_OPERAND (op0, 0), align); |
70f34814 | 1634 | #endif |
3e32c761 RG |
1635 | } |
1636 | if (TREE_INT_CST_LOW (TREE_OPERAND (t, 1)) != 0) | |
1637 | { | |
1638 | unsigned HOST_WIDE_INT ioff | |
1639 | = TREE_INT_CST_LOW (TREE_OPERAND (t, 1)); | |
1640 | unsigned HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1641 | align = MIN (aoff, align); | |
1642 | } | |
70f34814 RG |
1643 | } |
1644 | else | |
5951297a EB |
1645 | /* ??? This isn't fully correct, we can't set the alignment from the |
1646 | type in all cases. */ | |
1647 | align = MAX (align, TYPE_ALIGN (type)); | |
70f34814 | 1648 | } |
a80903ff | 1649 | |
9407f6bc RG |
1650 | else if (TREE_CODE (t) == TARGET_MEM_REF) |
1651 | /* ??? This isn't fully correct, we can't set the alignment from the | |
1652 | type in all cases. */ | |
1653 | align = MAX (align, TYPE_ALIGN (type)); | |
1654 | ||
738cc472 RK |
1655 | /* If the size is known, we can set that. */ |
1656 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
8ac61af7 | 1657 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
738cc472 | 1658 | |
80965c18 RK |
1659 | /* If T is not a type, we may be able to deduce some more information about |
1660 | the expression. */ | |
1661 | if (! TYPE_P (t)) | |
8ac61af7 | 1662 | { |
8476af98 | 1663 | tree base; |
df96b059 | 1664 | bool align_computed = false; |
389fdba0 | 1665 | |
8ac61af7 RK |
1666 | if (TREE_THIS_VOLATILE (t)) |
1667 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1668 | |
c56e3582 RK |
1669 | /* Now remove any conversions: they don't change what the underlying |
1670 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 1671 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
1672 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
1673 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1674 | t = TREE_OPERAND (t, 0); |
1675 | ||
4994da65 RG |
1676 | /* Note whether this expression can trap. */ |
1677 | MEM_NOTRAP_P (ref) = !tree_could_trap_p (t); | |
1678 | ||
1679 | base = get_base_address (t); | |
8476af98 RH |
1680 | if (base && DECL_P (base) |
1681 | && TREE_READONLY (base) | |
b1923f0a RG |
1682 | && (TREE_STATIC (base) || DECL_EXTERNAL (base)) |
1683 | && !TREE_THIS_VOLATILE (base)) | |
21d9971a | 1684 | MEM_READONLY_P (ref) = 1; |
8476af98 | 1685 | |
2039d7aa RH |
1686 | /* If this expression uses it's parent's alias set, mark it such |
1687 | that we won't change it. */ | |
1688 | if (component_uses_parent_alias_set (t)) | |
10b76d73 RK |
1689 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1690 | ||
8ac61af7 RK |
1691 | /* If this is a decl, set the attributes of the MEM from it. */ |
1692 | if (DECL_P (t)) | |
1693 | { | |
998d7deb RH |
1694 | expr = t; |
1695 | offset = const0_rtx; | |
6f1087be | 1696 | apply_bitpos = bitpos; |
8ac61af7 RK |
1697 | size = (DECL_SIZE_UNIT (t) |
1698 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1699 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
68252e27 | 1700 | align = DECL_ALIGN (t); |
df96b059 | 1701 | align_computed = true; |
8ac61af7 RK |
1702 | } |
1703 | ||
40c0668b | 1704 | /* If this is a constant, we know the alignment. */ |
6615c446 | 1705 | else if (CONSTANT_CLASS_P (t)) |
9ddfb1a7 RK |
1706 | { |
1707 | align = TYPE_ALIGN (type); | |
1708 | #ifdef CONSTANT_ALIGNMENT | |
1709 | align = CONSTANT_ALIGNMENT (t, align); | |
1710 | #endif | |
df96b059 | 1711 | align_computed = true; |
9ddfb1a7 | 1712 | } |
998d7deb RH |
1713 | |
1714 | /* If this is a field reference and not a bit-field, record it. */ | |
fa10beec | 1715 | /* ??? There is some information that can be gleaned from bit-fields, |
998d7deb RH |
1716 | such as the word offset in the structure that might be modified. |
1717 | But skip it for now. */ | |
1718 | else if (TREE_CODE (t) == COMPONENT_REF | |
1719 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1720 | { | |
55b34b5f | 1721 | expr = t; |
998d7deb | 1722 | offset = const0_rtx; |
6f1087be | 1723 | apply_bitpos = bitpos; |
998d7deb RH |
1724 | /* ??? Any reason the field size would be different than |
1725 | the size we got from the type? */ | |
1726 | } | |
1727 | ||
1728 | /* If this is an array reference, look for an outer field reference. */ | |
1729 | else if (TREE_CODE (t) == ARRAY_REF) | |
1730 | { | |
1731 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1732 | /* We can't modify t, because we use it at the end of the |
1733 | function. */ | |
1734 | tree t2 = t; | |
998d7deb RH |
1735 | |
1736 | do | |
1737 | { | |
1b1838b6 | 1738 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1739 | tree low_bound = array_ref_low_bound (t2); |
1740 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1741 | |
1742 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1743 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1744 | index, then convert to sizetype and multiply by the size of |
1745 | the array element. */ | |
1746 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1747 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1748 | index, low_bound); | |
2567406a | 1749 | |
44de5aeb | 1750 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1751 | size_binop (MULT_EXPR, |
1752 | fold_convert (sizetype, | |
1753 | index), | |
44de5aeb RK |
1754 | unit_size), |
1755 | off_tree); | |
1b1838b6 | 1756 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1757 | } |
1b1838b6 | 1758 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1759 | |
1b1838b6 | 1760 | if (DECL_P (t2)) |
c67a1cf6 | 1761 | { |
1b1838b6 | 1762 | expr = t2; |
40cb04f1 | 1763 | offset = NULL; |
c67a1cf6 | 1764 | if (host_integerp (off_tree, 1)) |
40cb04f1 RH |
1765 | { |
1766 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1767 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1b1838b6 | 1768 | align = DECL_ALIGN (t2); |
fc555370 | 1769 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
40cb04f1 | 1770 | align = aoff; |
df96b059 | 1771 | align_computed = true; |
40cb04f1 | 1772 | offset = GEN_INT (ioff); |
6f1087be | 1773 | apply_bitpos = bitpos; |
40cb04f1 | 1774 | } |
c67a1cf6 | 1775 | } |
1b1838b6 | 1776 | else if (TREE_CODE (t2) == COMPONENT_REF) |
998d7deb | 1777 | { |
55b34b5f RG |
1778 | expr = t2; |
1779 | offset = NULL; | |
998d7deb | 1780 | if (host_integerp (off_tree, 1)) |
6f1087be RH |
1781 | { |
1782 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1783 | apply_bitpos = bitpos; | |
1784 | } | |
998d7deb RH |
1785 | /* ??? Any reason the field size would be different than |
1786 | the size we got from the type? */ | |
1787 | } | |
56c47f22 | 1788 | |
56c47f22 | 1789 | /* If this is an indirect reference, record it. */ |
be1ac4ec | 1790 | else if (TREE_CODE (t) == MEM_REF) |
56c47f22 RG |
1791 | { |
1792 | expr = t; | |
1793 | offset = const0_rtx; | |
1794 | apply_bitpos = bitpos; | |
1795 | } | |
c67a1cf6 RH |
1796 | } |
1797 | ||
56c47f22 | 1798 | /* If this is an indirect reference, record it. */ |
70f34814 | 1799 | else if (TREE_CODE (t) == MEM_REF |
be1ac4ec | 1800 | || TREE_CODE (t) == TARGET_MEM_REF) |
56c47f22 RG |
1801 | { |
1802 | expr = t; | |
1803 | offset = const0_rtx; | |
1804 | apply_bitpos = bitpos; | |
1805 | } | |
1806 | ||
df96b059 JJ |
1807 | if (!align_computed && !INDIRECT_REF_P (t)) |
1808 | { | |
e80c2726 | 1809 | unsigned int obj_align = get_object_alignment (t, BIGGEST_ALIGNMENT); |
df96b059 JJ |
1810 | align = MAX (align, obj_align); |
1811 | } | |
8ac61af7 RK |
1812 | } |
1813 | ||
15c812e3 | 1814 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
1815 | bit position offset. Similarly, increase the size of the accessed |
1816 | object to contain the negative offset. */ | |
6f1087be | 1817 | if (apply_bitpos) |
8c317c5f RH |
1818 | { |
1819 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
1820 | if (size) | |
1821 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
1822 | } | |
6f1087be | 1823 | |
8ac61af7 | 1824 | /* Now set the attributes we computed above. */ |
10b76d73 | 1825 | MEM_ATTRS (ref) |
09e881c9 BE |
1826 | = get_mem_attrs (alias, expr, offset, size, align, |
1827 | TYPE_ADDR_SPACE (type), GET_MODE (ref)); | |
8ac61af7 RK |
1828 | |
1829 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
1830 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
738cc472 RK |
1831 | return; |
1832 | ||
8ac61af7 RK |
1833 | /* If it is a reference into an aggregate, this is part of an aggregate. |
1834 | Otherwise we don't know. */ | |
173b24b9 RK |
1835 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
1836 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
1837 | || TREE_CODE (t) == BIT_FIELD_REF) | |
1838 | MEM_IN_STRUCT_P (ref) = 1; | |
1839 | } | |
1840 | ||
6f1087be | 1841 | void |
502b8322 | 1842 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
1843 | { |
1844 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
1845 | } | |
1846 | ||
173b24b9 RK |
1847 | /* Set the alias set of MEM to SET. */ |
1848 | ||
1849 | void | |
4862826d | 1850 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 1851 | { |
173b24b9 | 1852 | /* If the new and old alias sets don't conflict, something is wrong. */ |
77a74ed7 | 1853 | gcc_checking_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
173b24b9 | 1854 | |
998d7deb | 1855 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
10b76d73 | 1856 | MEM_SIZE (mem), MEM_ALIGN (mem), |
09e881c9 BE |
1857 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
1858 | } | |
1859 | ||
1860 | /* Set the address space of MEM to ADDRSPACE (target-defined). */ | |
1861 | ||
1862 | void | |
1863 | set_mem_addr_space (rtx mem, addr_space_t addrspace) | |
1864 | { | |
1865 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1866 | MEM_OFFSET (mem), MEM_SIZE (mem), | |
1867 | MEM_ALIGN (mem), addrspace, GET_MODE (mem)); | |
173b24b9 | 1868 | } |
738cc472 | 1869 | |
d022d93e | 1870 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
1871 | |
1872 | void | |
502b8322 | 1873 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 1874 | { |
998d7deb | 1875 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
10b76d73 | 1876 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
09e881c9 | 1877 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
738cc472 | 1878 | } |
1285011e | 1879 | |
998d7deb | 1880 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
1881 | |
1882 | void | |
502b8322 | 1883 | set_mem_expr (rtx mem, tree expr) |
1285011e RK |
1884 | { |
1885 | MEM_ATTRS (mem) | |
998d7deb | 1886 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
09e881c9 BE |
1887 | MEM_SIZE (mem), MEM_ALIGN (mem), |
1888 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); | |
1285011e | 1889 | } |
998d7deb RH |
1890 | |
1891 | /* Set the offset of MEM to OFFSET. */ | |
1892 | ||
1893 | void | |
502b8322 | 1894 | set_mem_offset (rtx mem, rtx offset) |
998d7deb RH |
1895 | { |
1896 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1897 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
09e881c9 | 1898 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
35aff10b AM |
1899 | } |
1900 | ||
1901 | /* Set the size of MEM to SIZE. */ | |
1902 | ||
1903 | void | |
502b8322 | 1904 | set_mem_size (rtx mem, rtx size) |
35aff10b AM |
1905 | { |
1906 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1907 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
09e881c9 | 1908 | MEM_ADDR_SPACE (mem), GET_MODE (mem)); |
998d7deb | 1909 | } |
173b24b9 | 1910 | \f |
738cc472 RK |
1911 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
1912 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
1913 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
1914 | returned memory location is required to be valid. The memory | |
1915 | attributes are not changed. */ | |
23b2ce53 | 1916 | |
738cc472 | 1917 | static rtx |
502b8322 | 1918 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
23b2ce53 | 1919 | { |
09e881c9 | 1920 | addr_space_t as; |
60564289 | 1921 | rtx new_rtx; |
23b2ce53 | 1922 | |
5b0264cb | 1923 | gcc_assert (MEM_P (memref)); |
09e881c9 | 1924 | as = MEM_ADDR_SPACE (memref); |
23b2ce53 RS |
1925 | if (mode == VOIDmode) |
1926 | mode = GET_MODE (memref); | |
1927 | if (addr == 0) | |
1928 | addr = XEXP (memref, 0); | |
a74ff877 | 1929 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
09e881c9 | 1930 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
a74ff877 | 1931 | return memref; |
23b2ce53 | 1932 | |
f1ec5147 | 1933 | if (validate) |
23b2ce53 | 1934 | { |
f1ec5147 | 1935 | if (reload_in_progress || reload_completed) |
09e881c9 | 1936 | gcc_assert (memory_address_addr_space_p (mode, addr, as)); |
f1ec5147 | 1937 | else |
09e881c9 | 1938 | addr = memory_address_addr_space (mode, addr, as); |
23b2ce53 | 1939 | } |
750c9258 | 1940 | |
9b04c6a8 RK |
1941 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1942 | return memref; | |
1943 | ||
60564289 KG |
1944 | new_rtx = gen_rtx_MEM (mode, addr); |
1945 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
1946 | return new_rtx; | |
23b2ce53 | 1947 | } |
792760b9 | 1948 | |
738cc472 RK |
1949 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
1950 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
1951 | |
1952 | rtx | |
502b8322 | 1953 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
f4ef873c | 1954 | { |
60564289 KG |
1955 | rtx new_rtx = change_address_1 (memref, mode, addr, 1), size; |
1956 | enum machine_mode mmode = GET_MODE (new_rtx); | |
4e44c1ef JJ |
1957 | unsigned int align; |
1958 | ||
1959 | size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)); | |
1960 | align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode); | |
c2f7bcc3 | 1961 | |
fdb1c7b3 | 1962 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 1963 | if (new_rtx == memref) |
4e44c1ef JJ |
1964 | { |
1965 | if (MEM_ATTRS (memref) == 0 | |
1966 | || (MEM_EXPR (memref) == NULL | |
1967 | && MEM_OFFSET (memref) == NULL | |
1968 | && MEM_SIZE (memref) == size | |
1969 | && MEM_ALIGN (memref) == align)) | |
60564289 | 1970 | return new_rtx; |
4e44c1ef | 1971 | |
60564289 KG |
1972 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
1973 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 1974 | } |
fdb1c7b3 | 1975 | |
60564289 | 1976 | MEM_ATTRS (new_rtx) |
09e881c9 BE |
1977 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, |
1978 | MEM_ADDR_SPACE (memref), mmode); | |
823e3574 | 1979 | |
60564289 | 1980 | return new_rtx; |
f4ef873c | 1981 | } |
792760b9 | 1982 | |
738cc472 RK |
1983 | /* Return a memory reference like MEMREF, but with its mode changed |
1984 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 JJ |
1985 | nonzero, the memory address is forced to be valid. |
1986 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
1987 | and caller is responsible for adjusting MEMREF base register. */ | |
f1ec5147 RK |
1988 | |
1989 | rtx | |
502b8322 AJ |
1990 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
1991 | int validate, int adjust) | |
f1ec5147 | 1992 | { |
823e3574 | 1993 | rtx addr = XEXP (memref, 0); |
60564289 | 1994 | rtx new_rtx; |
738cc472 | 1995 | rtx memoffset = MEM_OFFSET (memref); |
10b76d73 | 1996 | rtx size = 0; |
738cc472 | 1997 | unsigned int memalign = MEM_ALIGN (memref); |
09e881c9 | 1998 | addr_space_t as = MEM_ADDR_SPACE (memref); |
d4ebfa65 | 1999 | enum machine_mode address_mode = targetm.addr_space.address_mode (as); |
a6fe9ed4 | 2000 | int pbits; |
823e3574 | 2001 | |
fdb1c7b3 JH |
2002 | /* If there are no changes, just return the original memory reference. */ |
2003 | if (mode == GET_MODE (memref) && !offset | |
09e881c9 | 2004 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
fdb1c7b3 JH |
2005 | return memref; |
2006 | ||
d14419e4 | 2007 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2008 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2009 | (plus (plus reg reg) const_int) -- so do this always. */ |
2010 | addr = copy_rtx (addr); | |
2011 | ||
a6fe9ed4 JM |
2012 | /* Convert a possibly large offset to a signed value within the |
2013 | range of the target address space. */ | |
d4ebfa65 | 2014 | pbits = GET_MODE_BITSIZE (address_mode); |
a6fe9ed4 JM |
2015 | if (HOST_BITS_PER_WIDE_INT > pbits) |
2016 | { | |
2017 | int shift = HOST_BITS_PER_WIDE_INT - pbits; | |
2018 | offset = (((HOST_WIDE_INT) ((unsigned HOST_WIDE_INT) offset << shift)) | |
2019 | >> shift); | |
2020 | } | |
2021 | ||
4a78c787 RH |
2022 | if (adjust) |
2023 | { | |
2024 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2025 | object, we can merge it into the LO_SUM. */ | |
2026 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
2027 | && offset >= 0 | |
2028 | && (unsigned HOST_WIDE_INT) offset | |
2029 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
d4ebfa65 | 2030 | addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0), |
4a78c787 RH |
2031 | plus_constant (XEXP (addr, 1), offset)); |
2032 | else | |
2033 | addr = plus_constant (addr, offset); | |
2034 | } | |
823e3574 | 2035 | |
60564289 | 2036 | new_rtx = change_address_1 (memref, mode, addr, validate); |
738cc472 | 2037 | |
09efeca1 PB |
2038 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2039 | but this would destroy memref's MEM_ATTRS. */ | |
2040 | if (new_rtx == memref && offset != 0) | |
2041 | new_rtx = copy_rtx (new_rtx); | |
2042 | ||
738cc472 RK |
2043 | /* Compute the new values of the memory attributes due to this adjustment. |
2044 | We add the offsets and update the alignment. */ | |
2045 | if (memoffset) | |
2046 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
2047 | ||
03bf2c23 RK |
2048 | /* Compute the new alignment by taking the MIN of the alignment and the |
2049 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2050 | if zero. */ | |
2051 | if (offset != 0) | |
3bf1e984 RK |
2052 | memalign |
2053 | = MIN (memalign, | |
2054 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
738cc472 | 2055 | |
10b76d73 | 2056 | /* We can compute the size in a number of ways. */ |
60564289 KG |
2057 | if (GET_MODE (new_rtx) != BLKmode) |
2058 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new_rtx))); | |
10b76d73 RK |
2059 | else if (MEM_SIZE (memref)) |
2060 | size = plus_constant (MEM_SIZE (memref), -offset); | |
2061 | ||
60564289 | 2062 | MEM_ATTRS (new_rtx) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
09e881c9 BE |
2063 | memoffset, size, memalign, as, |
2064 | GET_MODE (new_rtx)); | |
738cc472 RK |
2065 | |
2066 | /* At some point, we should validate that this offset is within the object, | |
2067 | if all the appropriate values are known. */ | |
60564289 | 2068 | return new_rtx; |
f1ec5147 RK |
2069 | } |
2070 | ||
630036c6 JJ |
2071 | /* Return a memory reference like MEMREF, but with its mode changed |
2072 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2073 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2074 | nonzero, the memory address is forced to be valid. */ |
2075 | ||
2076 | rtx | |
502b8322 AJ |
2077 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
2078 | HOST_WIDE_INT offset, int validate) | |
630036c6 JJ |
2079 | { |
2080 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
2081 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
2082 | } | |
2083 | ||
8ac61af7 RK |
2084 | /* Return a memory reference like MEMREF, but whose address is changed by |
2085 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2086 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2087 | |
2088 | rtx | |
502b8322 | 2089 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2090 | { |
60564289 | 2091 | rtx new_rtx, addr = XEXP (memref, 0); |
09e881c9 | 2092 | addr_space_t as = MEM_ADDR_SPACE (memref); |
d4ebfa65 | 2093 | enum machine_mode address_mode = targetm.addr_space.address_mode (as); |
e3c8ea67 | 2094 | |
d4ebfa65 | 2095 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 | 2096 | |
68252e27 | 2097 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2098 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2099 | |
2100 | However, if we did go and rearrange things, we can wind up not | |
2101 | being able to recognize the magic around pic_offset_table_rtx. | |
2102 | This stuff is fragile, and is yet another example of why it is | |
2103 | bad to expose PIC machinery too early. */ | |
09e881c9 | 2104 | if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, as) |
e3c8ea67 RH |
2105 | && GET_CODE (addr) == PLUS |
2106 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2107 | { | |
2108 | addr = force_reg (GET_MODE (addr), addr); | |
d4ebfa65 | 2109 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 RH |
2110 | } |
2111 | ||
60564289 KG |
2112 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
2113 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1); | |
0d4903b8 | 2114 | |
fdb1c7b3 | 2115 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2116 | if (new_rtx == memref) |
2117 | return new_rtx; | |
fdb1c7b3 | 2118 | |
0d4903b8 RK |
2119 | /* Update the alignment to reflect the offset. Reset the offset, which |
2120 | we don't know. */ | |
60564289 | 2121 | MEM_ATTRS (new_rtx) |
2cc2d4bb | 2122 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, |
9ceca302 | 2123 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
09e881c9 | 2124 | as, GET_MODE (new_rtx)); |
60564289 | 2125 | return new_rtx; |
0d4903b8 | 2126 | } |
68252e27 | 2127 | |
792760b9 RK |
2128 | /* Return a memory reference like MEMREF, but with its address changed to |
2129 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2130 | to is the same, just the form of the address is being changed, such as | |
2131 | by putting something into a register. */ | |
2132 | ||
2133 | rtx | |
502b8322 | 2134 | replace_equiv_address (rtx memref, rtx addr) |
792760b9 | 2135 | { |
738cc472 RK |
2136 | /* change_address_1 copies the memory attribute structure without change |
2137 | and that's exactly what we want here. */ | |
40c0668b | 2138 | update_temp_slot_address (XEXP (memref, 0), addr); |
738cc472 | 2139 | return change_address_1 (memref, VOIDmode, addr, 1); |
792760b9 | 2140 | } |
738cc472 | 2141 | |
f1ec5147 RK |
2142 | /* Likewise, but the reference is not required to be valid. */ |
2143 | ||
2144 | rtx | |
502b8322 | 2145 | replace_equiv_address_nv (rtx memref, rtx addr) |
f1ec5147 | 2146 | { |
f1ec5147 RK |
2147 | return change_address_1 (memref, VOIDmode, addr, 0); |
2148 | } | |
e7dfe4bb RH |
2149 | |
2150 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2151 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2152 | cannot issue QImode memory operations and have to use SImode memory | |
2153 | operations plus masking logic. */ | |
2154 | ||
2155 | rtx | |
502b8322 | 2156 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb | 2157 | { |
60564289 KG |
2158 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1); |
2159 | tree expr = MEM_EXPR (new_rtx); | |
2160 | rtx memoffset = MEM_OFFSET (new_rtx); | |
e7dfe4bb RH |
2161 | unsigned int size = GET_MODE_SIZE (mode); |
2162 | ||
fdb1c7b3 | 2163 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2164 | if (new_rtx == memref) |
2165 | return new_rtx; | |
fdb1c7b3 | 2166 | |
e7dfe4bb RH |
2167 | /* If we don't know what offset we were at within the expression, then |
2168 | we can't know if we've overstepped the bounds. */ | |
fa1591cb | 2169 | if (! memoffset) |
e7dfe4bb RH |
2170 | expr = NULL_TREE; |
2171 | ||
2172 | while (expr) | |
2173 | { | |
2174 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2175 | { | |
2176 | tree field = TREE_OPERAND (expr, 1); | |
44de5aeb | 2177 | tree offset = component_ref_field_offset (expr); |
e7dfe4bb RH |
2178 | |
2179 | if (! DECL_SIZE_UNIT (field)) | |
2180 | { | |
2181 | expr = NULL_TREE; | |
2182 | break; | |
2183 | } | |
2184 | ||
2185 | /* Is the field at least as large as the access? If so, ok, | |
2186 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2187 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2188 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
e7dfe4bb RH |
2189 | && INTVAL (memoffset) >= 0) |
2190 | break; | |
2191 | ||
44de5aeb | 2192 | if (! host_integerp (offset, 1)) |
e7dfe4bb RH |
2193 | { |
2194 | expr = NULL_TREE; | |
2195 | break; | |
2196 | } | |
2197 | ||
2198 | expr = TREE_OPERAND (expr, 0); | |
44de5aeb RK |
2199 | memoffset |
2200 | = (GEN_INT (INTVAL (memoffset) | |
2201 | + tree_low_cst (offset, 1) | |
2202 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2203 | / BITS_PER_UNIT))); | |
e7dfe4bb RH |
2204 | } |
2205 | /* Similarly for the decl. */ | |
2206 | else if (DECL_P (expr) | |
2207 | && DECL_SIZE_UNIT (expr) | |
45f79783 | 2208 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
e7dfe4bb RH |
2209 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2210 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2211 | break; | |
2212 | else | |
2213 | { | |
2214 | /* The widened memory access overflows the expression, which means | |
2215 | that it could alias another expression. Zap it. */ | |
2216 | expr = NULL_TREE; | |
2217 | break; | |
2218 | } | |
2219 | } | |
2220 | ||
2221 | if (! expr) | |
2222 | memoffset = NULL_RTX; | |
2223 | ||
2224 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2225 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2226 | ||
60564289 | 2227 | MEM_ATTRS (new_rtx) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), |
09e881c9 BE |
2228 | MEM_ALIGN (new_rtx), |
2229 | MEM_ADDR_SPACE (new_rtx), mode); | |
e7dfe4bb | 2230 | |
60564289 | 2231 | return new_rtx; |
e7dfe4bb | 2232 | } |
23b2ce53 | 2233 | \f |
f6129d66 RH |
2234 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2235 | static GTY(()) tree spill_slot_decl; | |
2236 | ||
3d7e23f6 RH |
2237 | tree |
2238 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2239 | { |
2240 | tree d = spill_slot_decl; | |
2241 | rtx rd; | |
2242 | ||
3d7e23f6 | 2243 | if (d || !force_build_p) |
f6129d66 RH |
2244 | return d; |
2245 | ||
c2255bc4 AH |
2246 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2247 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2248 | DECL_ARTIFICIAL (d) = 1; |
2249 | DECL_IGNORED_P (d) = 1; | |
2250 | TREE_USED (d) = 1; | |
f6129d66 RH |
2251 | spill_slot_decl = d; |
2252 | ||
2253 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2254 | MEM_NOTRAP_P (rd) = 1; | |
2255 | MEM_ATTRS (rd) = get_mem_attrs (new_alias_set (), d, const0_rtx, | |
09e881c9 | 2256 | NULL_RTX, 0, ADDR_SPACE_GENERIC, BLKmode); |
f6129d66 RH |
2257 | SET_DECL_RTL (d, rd); |
2258 | ||
2259 | return d; | |
2260 | } | |
2261 | ||
2262 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2263 | attributes as appropriate for a register allocator spill slot. | |
2264 | These slots are not aliasable by other memory. We arrange for | |
2265 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2266 | work properly in the case of shared spill slots. */ | |
2267 | ||
2268 | void | |
2269 | set_mem_attrs_for_spill (rtx mem) | |
2270 | { | |
2271 | alias_set_type alias; | |
2272 | rtx addr, offset; | |
2273 | tree expr; | |
2274 | ||
3d7e23f6 | 2275 | expr = get_spill_slot_decl (true); |
f6129d66 RH |
2276 | alias = MEM_ALIAS_SET (DECL_RTL (expr)); |
2277 | ||
2278 | /* We expect the incoming memory to be of the form: | |
2279 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2280 | with perhaps the plus missing for offset = 0. */ | |
2281 | addr = XEXP (mem, 0); | |
2282 | offset = const0_rtx; | |
2283 | if (GET_CODE (addr) == PLUS | |
481683e1 | 2284 | && CONST_INT_P (XEXP (addr, 1))) |
f6129d66 RH |
2285 | offset = XEXP (addr, 1); |
2286 | ||
2287 | MEM_ATTRS (mem) = get_mem_attrs (alias, expr, offset, | |
2288 | MEM_SIZE (mem), MEM_ALIGN (mem), | |
09e881c9 | 2289 | ADDR_SPACE_GENERIC, GET_MODE (mem)); |
f6129d66 RH |
2290 | MEM_NOTRAP_P (mem) = 1; |
2291 | } | |
2292 | \f | |
23b2ce53 RS |
2293 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2294 | ||
2295 | rtx | |
502b8322 | 2296 | gen_label_rtx (void) |
23b2ce53 | 2297 | { |
0dc36574 | 2298 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
502b8322 | 2299 | NULL, label_num++, NULL); |
23b2ce53 RS |
2300 | } |
2301 | \f | |
2302 | /* For procedure integration. */ | |
2303 | ||
23b2ce53 | 2304 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2305 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2306 | Used for an inline-procedure after copying the insn chain. */ |
2307 | ||
2308 | void | |
502b8322 | 2309 | set_new_first_and_last_insn (rtx first, rtx last) |
23b2ce53 | 2310 | { |
86fe05e0 RK |
2311 | rtx insn; |
2312 | ||
5936d944 JH |
2313 | set_first_insn (first); |
2314 | set_last_insn (last); | |
86fe05e0 RK |
2315 | cur_insn_uid = 0; |
2316 | ||
b5b8b0ac AO |
2317 | if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS) |
2318 | { | |
2319 | int debug_count = 0; | |
2320 | ||
2321 | cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1; | |
2322 | cur_debug_insn_uid = 0; | |
2323 | ||
2324 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2325 | if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID) | |
2326 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); | |
2327 | else | |
2328 | { | |
2329 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2330 | if (DEBUG_INSN_P (insn)) | |
2331 | debug_count++; | |
2332 | } | |
2333 | ||
2334 | if (debug_count) | |
2335 | cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count; | |
2336 | else | |
2337 | cur_debug_insn_uid++; | |
2338 | } | |
2339 | else | |
2340 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2341 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2342 | |
2343 | cur_insn_uid++; | |
23b2ce53 | 2344 | } |
23b2ce53 | 2345 | \f |
750c9258 | 2346 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2347 | structure. This routine should only be called once. */ |
23b2ce53 | 2348 | |
fd743bc1 | 2349 | static void |
b4aaa77b | 2350 | unshare_all_rtl_1 (rtx insn) |
23b2ce53 | 2351 | { |
d1b81779 | 2352 | /* Unshare just about everything else. */ |
2c07f13b | 2353 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2354 | |
23b2ce53 RS |
2355 | /* Make sure the addresses of stack slots found outside the insn chain |
2356 | (such as, in DECL_RTL of a variable) are not shared | |
2357 | with the insn chain. | |
2358 | ||
2359 | This special care is necessary when the stack slot MEM does not | |
2360 | actually appear in the insn chain. If it does appear, its address | |
2361 | is unshared from all else at that point. */ | |
242b0ce6 | 2362 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
2363 | } |
2364 | ||
750c9258 | 2365 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2366 | structure, again. This is a fairly expensive thing to do so it |
2367 | should be done sparingly. */ | |
2368 | ||
2369 | void | |
502b8322 | 2370 | unshare_all_rtl_again (rtx insn) |
d1b81779 GK |
2371 | { |
2372 | rtx p; | |
624c87aa RE |
2373 | tree decl; |
2374 | ||
d1b81779 | 2375 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2376 | if (INSN_P (p)) |
d1b81779 GK |
2377 | { |
2378 | reset_used_flags (PATTERN (p)); | |
2379 | reset_used_flags (REG_NOTES (p)); | |
d1b81779 | 2380 | } |
624c87aa | 2381 | |
2d4aecb3 | 2382 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2383 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2384 | |
624c87aa | 2385 | /* Make sure that virtual parameters are not shared. */ |
910ad8de | 2386 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) |
5eb2a9f2 | 2387 | set_used_flags (DECL_RTL (decl)); |
624c87aa RE |
2388 | |
2389 | reset_used_flags (stack_slot_list); | |
2390 | ||
b4aaa77b | 2391 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2392 | } |
2393 | ||
c2924966 | 2394 | unsigned int |
fd743bc1 PB |
2395 | unshare_all_rtl (void) |
2396 | { | |
b4aaa77b | 2397 | unshare_all_rtl_1 (get_insns ()); |
c2924966 | 2398 | return 0; |
d1b81779 GK |
2399 | } |
2400 | ||
8ddbbcae | 2401 | struct rtl_opt_pass pass_unshare_all_rtl = |
ef330312 | 2402 | { |
8ddbbcae JH |
2403 | { |
2404 | RTL_PASS, | |
defb77dc | 2405 | "unshare", /* name */ |
ef330312 PB |
2406 | NULL, /* gate */ |
2407 | unshare_all_rtl, /* execute */ | |
2408 | NULL, /* sub */ | |
2409 | NULL, /* next */ | |
2410 | 0, /* static_pass_number */ | |
7072a650 | 2411 | TV_NONE, /* tv_id */ |
ef330312 PB |
2412 | 0, /* properties_required */ |
2413 | 0, /* properties_provided */ | |
2414 | 0, /* properties_destroyed */ | |
2415 | 0, /* todo_flags_start */ | |
8ddbbcae JH |
2416 | TODO_dump_func | TODO_verify_rtl_sharing /* todo_flags_finish */ |
2417 | } | |
ef330312 PB |
2418 | }; |
2419 | ||
2420 | ||
2c07f13b JH |
2421 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2422 | Recursively does the same for subexpressions. */ | |
2423 | ||
2424 | static void | |
2425 | verify_rtx_sharing (rtx orig, rtx insn) | |
2426 | { | |
2427 | rtx x = orig; | |
2428 | int i; | |
2429 | enum rtx_code code; | |
2430 | const char *format_ptr; | |
2431 | ||
2432 | if (x == 0) | |
2433 | return; | |
2434 | ||
2435 | code = GET_CODE (x); | |
2436 | ||
2437 | /* These types may be freely shared. */ | |
2438 | ||
2439 | switch (code) | |
2440 | { | |
2441 | case REG: | |
0ca5af51 AO |
2442 | case DEBUG_EXPR: |
2443 | case VALUE: | |
2c07f13b JH |
2444 | case CONST_INT: |
2445 | case CONST_DOUBLE: | |
091a3ac7 | 2446 | case CONST_FIXED: |
2c07f13b JH |
2447 | case CONST_VECTOR: |
2448 | case SYMBOL_REF: | |
2449 | case LABEL_REF: | |
2450 | case CODE_LABEL: | |
2451 | case PC: | |
2452 | case CC0: | |
3810076b | 2453 | case RETURN: |
2c07f13b | 2454 | case SCRATCH: |
2c07f13b | 2455 | return; |
3e89ed8d JH |
2456 | /* SCRATCH must be shared because they represent distinct values. */ |
2457 | case CLOBBER: | |
2458 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2459 | return; | |
2460 | break; | |
2c07f13b JH |
2461 | |
2462 | case CONST: | |
6fb5fa3c | 2463 | if (shared_const_p (orig)) |
2c07f13b JH |
2464 | return; |
2465 | break; | |
2466 | ||
2467 | case MEM: | |
2468 | /* A MEM is allowed to be shared if its address is constant. */ | |
2469 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2470 | || reload_completed || reload_in_progress) | |
2471 | return; | |
2472 | ||
2473 | break; | |
2474 | ||
2475 | default: | |
2476 | break; | |
2477 | } | |
2478 | ||
2479 | /* This rtx may not be shared. If it has already been seen, | |
2480 | replace it with a copy of itself. */ | |
1a2caa7a | 2481 | #ifdef ENABLE_CHECKING |
2c07f13b JH |
2482 | if (RTX_FLAG (x, used)) |
2483 | { | |
ab532386 | 2484 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2485 | debug_rtx (insn); |
ab532386 | 2486 | error ("shared rtx"); |
2c07f13b | 2487 | debug_rtx (x); |
ab532386 | 2488 | internal_error ("internal consistency failure"); |
2c07f13b | 2489 | } |
1a2caa7a NS |
2490 | #endif |
2491 | gcc_assert (!RTX_FLAG (x, used)); | |
b8698a0f | 2492 | |
2c07f13b JH |
2493 | RTX_FLAG (x, used) = 1; |
2494 | ||
6614fd40 | 2495 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2496 | |
2497 | format_ptr = GET_RTX_FORMAT (code); | |
2498 | ||
2499 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2500 | { | |
2501 | switch (*format_ptr++) | |
2502 | { | |
2503 | case 'e': | |
2504 | verify_rtx_sharing (XEXP (x, i), insn); | |
2505 | break; | |
2506 | ||
2507 | case 'E': | |
2508 | if (XVEC (x, i) != NULL) | |
2509 | { | |
2510 | int j; | |
2511 | int len = XVECLEN (x, i); | |
2512 | ||
2513 | for (j = 0; j < len; j++) | |
2514 | { | |
1a2caa7a NS |
2515 | /* We allow sharing of ASM_OPERANDS inside single |
2516 | instruction. */ | |
2c07f13b | 2517 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2518 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2519 | == ASM_OPERANDS)) | |
2c07f13b JH |
2520 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2521 | else | |
2522 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2523 | } | |
2524 | } | |
2525 | break; | |
2526 | } | |
2527 | } | |
2528 | return; | |
2529 | } | |
2530 | ||
ba228239 | 2531 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2c07f13b JH |
2532 | sharing in between the subexpressions. */ |
2533 | ||
24e47c76 | 2534 | DEBUG_FUNCTION void |
2c07f13b JH |
2535 | verify_rtl_sharing (void) |
2536 | { | |
2537 | rtx p; | |
2538 | ||
a222c01a MM |
2539 | timevar_push (TV_VERIFY_RTL_SHARING); |
2540 | ||
2c07f13b JH |
2541 | for (p = get_insns (); p; p = NEXT_INSN (p)) |
2542 | if (INSN_P (p)) | |
2543 | { | |
2544 | reset_used_flags (PATTERN (p)); | |
2545 | reset_used_flags (REG_NOTES (p)); | |
2954a813 KK |
2546 | if (GET_CODE (PATTERN (p)) == SEQUENCE) |
2547 | { | |
2548 | int i; | |
2549 | rtx q, sequence = PATTERN (p); | |
2550 | ||
2551 | for (i = 0; i < XVECLEN (sequence, 0); i++) | |
2552 | { | |
2553 | q = XVECEXP (sequence, 0, i); | |
2554 | gcc_assert (INSN_P (q)); | |
2555 | reset_used_flags (PATTERN (q)); | |
2556 | reset_used_flags (REG_NOTES (q)); | |
2954a813 KK |
2557 | } |
2558 | } | |
2c07f13b JH |
2559 | } |
2560 | ||
2561 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2562 | if (INSN_P (p)) | |
2563 | { | |
2564 | verify_rtx_sharing (PATTERN (p), p); | |
2565 | verify_rtx_sharing (REG_NOTES (p), p); | |
2c07f13b | 2566 | } |
a222c01a MM |
2567 | |
2568 | timevar_pop (TV_VERIFY_RTL_SHARING); | |
2c07f13b JH |
2569 | } |
2570 | ||
d1b81779 GK |
2571 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2572 | Assumes the mark bits are cleared at entry. */ | |
2573 | ||
2c07f13b JH |
2574 | void |
2575 | unshare_all_rtl_in_chain (rtx insn) | |
d1b81779 GK |
2576 | { |
2577 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2578 | if (INSN_P (insn)) |
d1b81779 GK |
2579 | { |
2580 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2581 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
d1b81779 GK |
2582 | } |
2583 | } | |
2584 | ||
2d4aecb3 | 2585 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2586 | shared. We never replace the DECL_RTLs themselves with a copy, |
2587 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2588 | expressions in the instruction stream. | |
2589 | ||
2590 | Note that reload may convert pseudo registers into memories in-place. | |
2591 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2592 | reset the used flags on MEMs in the instruction stream, we must set | |
2593 | them again on MEMs that appear in DECL_RTLs. */ | |
2594 | ||
2d4aecb3 | 2595 | static void |
5eb2a9f2 | 2596 | set_used_decls (tree blk) |
2d4aecb3 AO |
2597 | { |
2598 | tree t; | |
2599 | ||
2600 | /* Mark decls. */ | |
910ad8de | 2601 | for (t = BLOCK_VARS (blk); t; t = DECL_CHAIN (t)) |
19e7881c | 2602 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2603 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2604 | |
2605 | /* Now process sub-blocks. */ | |
87caf699 | 2606 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 2607 | set_used_decls (t); |
2d4aecb3 AO |
2608 | } |
2609 | ||
23b2ce53 | 2610 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2611 | Recursively does the same for subexpressions. Uses |
2612 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2613 | |
2614 | rtx | |
502b8322 | 2615 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2616 | { |
32b32b16 AP |
2617 | copy_rtx_if_shared_1 (&orig); |
2618 | return orig; | |
2619 | } | |
2620 | ||
ff954f39 AP |
2621 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2622 | use. Recursively does the same for subexpressions. */ | |
2623 | ||
32b32b16 AP |
2624 | static void |
2625 | copy_rtx_if_shared_1 (rtx *orig1) | |
2626 | { | |
2627 | rtx x; | |
b3694847 SS |
2628 | int i; |
2629 | enum rtx_code code; | |
32b32b16 | 2630 | rtx *last_ptr; |
b3694847 | 2631 | const char *format_ptr; |
23b2ce53 | 2632 | int copied = 0; |
32b32b16 AP |
2633 | int length; |
2634 | ||
2635 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2636 | repeat: | |
2637 | x = *orig1; | |
23b2ce53 RS |
2638 | |
2639 | if (x == 0) | |
32b32b16 | 2640 | return; |
23b2ce53 RS |
2641 | |
2642 | code = GET_CODE (x); | |
2643 | ||
2644 | /* These types may be freely shared. */ | |
2645 | ||
2646 | switch (code) | |
2647 | { | |
2648 | case REG: | |
0ca5af51 AO |
2649 | case DEBUG_EXPR: |
2650 | case VALUE: | |
23b2ce53 RS |
2651 | case CONST_INT: |
2652 | case CONST_DOUBLE: | |
091a3ac7 | 2653 | case CONST_FIXED: |
69ef87e2 | 2654 | case CONST_VECTOR: |
23b2ce53 | 2655 | case SYMBOL_REF: |
2c07f13b | 2656 | case LABEL_REF: |
23b2ce53 RS |
2657 | case CODE_LABEL: |
2658 | case PC: | |
2659 | case CC0: | |
2660 | case SCRATCH: | |
0f41302f | 2661 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 2662 | return; |
3e89ed8d JH |
2663 | case CLOBBER: |
2664 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2665 | return; | |
2666 | break; | |
23b2ce53 | 2667 | |
b851ea09 | 2668 | case CONST: |
6fb5fa3c | 2669 | if (shared_const_p (x)) |
32b32b16 | 2670 | return; |
b851ea09 RK |
2671 | break; |
2672 | ||
b5b8b0ac | 2673 | case DEBUG_INSN: |
23b2ce53 RS |
2674 | case INSN: |
2675 | case JUMP_INSN: | |
2676 | case CALL_INSN: | |
2677 | case NOTE: | |
23b2ce53 RS |
2678 | case BARRIER: |
2679 | /* The chain of insns is not being copied. */ | |
32b32b16 | 2680 | return; |
23b2ce53 | 2681 | |
e9a25f70 JL |
2682 | default: |
2683 | break; | |
23b2ce53 RS |
2684 | } |
2685 | ||
2686 | /* This rtx may not be shared. If it has already been seen, | |
2687 | replace it with a copy of itself. */ | |
2688 | ||
2adc7f12 | 2689 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2690 | { |
aacd3885 | 2691 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
2692 | copied = 1; |
2693 | } | |
2adc7f12 | 2694 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
2695 | |
2696 | /* Now scan the subexpressions recursively. | |
2697 | We can store any replaced subexpressions directly into X | |
2698 | since we know X is not shared! Any vectors in X | |
2699 | must be copied if X was copied. */ | |
2700 | ||
2701 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2702 | length = GET_RTX_LENGTH (code); |
2703 | last_ptr = NULL; | |
b8698a0f | 2704 | |
32b32b16 | 2705 | for (i = 0; i < length; i++) |
23b2ce53 RS |
2706 | { |
2707 | switch (*format_ptr++) | |
2708 | { | |
2709 | case 'e': | |
32b32b16 AP |
2710 | if (last_ptr) |
2711 | copy_rtx_if_shared_1 (last_ptr); | |
2712 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
2713 | break; |
2714 | ||
2715 | case 'E': | |
2716 | if (XVEC (x, i) != NULL) | |
2717 | { | |
b3694847 | 2718 | int j; |
f0722107 | 2719 | int len = XVECLEN (x, i); |
b8698a0f | 2720 | |
6614fd40 KH |
2721 | /* Copy the vector iff I copied the rtx and the length |
2722 | is nonzero. */ | |
f0722107 | 2723 | if (copied && len > 0) |
8f985ec4 | 2724 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
b8698a0f | 2725 | |
5d3cc252 | 2726 | /* Call recursively on all inside the vector. */ |
f0722107 | 2727 | for (j = 0; j < len; j++) |
32b32b16 AP |
2728 | { |
2729 | if (last_ptr) | |
2730 | copy_rtx_if_shared_1 (last_ptr); | |
2731 | last_ptr = &XVECEXP (x, i, j); | |
2732 | } | |
23b2ce53 RS |
2733 | } |
2734 | break; | |
2735 | } | |
2736 | } | |
32b32b16 AP |
2737 | *orig1 = x; |
2738 | if (last_ptr) | |
2739 | { | |
2740 | orig1 = last_ptr; | |
2741 | goto repeat; | |
2742 | } | |
2743 | return; | |
23b2ce53 RS |
2744 | } |
2745 | ||
76369a82 | 2746 | /* Set the USED bit in X and its non-shareable subparts to FLAG. */ |
23b2ce53 | 2747 | |
76369a82 NF |
2748 | static void |
2749 | mark_used_flags (rtx x, int flag) | |
23b2ce53 | 2750 | { |
b3694847 SS |
2751 | int i, j; |
2752 | enum rtx_code code; | |
2753 | const char *format_ptr; | |
32b32b16 | 2754 | int length; |
23b2ce53 | 2755 | |
32b32b16 AP |
2756 | /* Repeat is used to turn tail-recursion into iteration. */ |
2757 | repeat: | |
23b2ce53 RS |
2758 | if (x == 0) |
2759 | return; | |
2760 | ||
2761 | code = GET_CODE (x); | |
2762 | ||
9faa82d8 | 2763 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2764 | for them. */ |
2765 | ||
2766 | switch (code) | |
2767 | { | |
2768 | case REG: | |
0ca5af51 AO |
2769 | case DEBUG_EXPR: |
2770 | case VALUE: | |
23b2ce53 RS |
2771 | case CONST_INT: |
2772 | case CONST_DOUBLE: | |
091a3ac7 | 2773 | case CONST_FIXED: |
69ef87e2 | 2774 | case CONST_VECTOR: |
23b2ce53 RS |
2775 | case SYMBOL_REF: |
2776 | case CODE_LABEL: | |
2777 | case PC: | |
2778 | case CC0: | |
2779 | return; | |
2780 | ||
b5b8b0ac | 2781 | case DEBUG_INSN: |
23b2ce53 RS |
2782 | case INSN: |
2783 | case JUMP_INSN: | |
2784 | case CALL_INSN: | |
2785 | case NOTE: | |
2786 | case LABEL_REF: | |
2787 | case BARRIER: | |
2788 | /* The chain of insns is not being copied. */ | |
2789 | return; | |
750c9258 | 2790 | |
e9a25f70 JL |
2791 | default: |
2792 | break; | |
23b2ce53 RS |
2793 | } |
2794 | ||
76369a82 | 2795 | RTX_FLAG (x, used) = flag; |
23b2ce53 RS |
2796 | |
2797 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 | 2798 | length = GET_RTX_LENGTH (code); |
b8698a0f | 2799 | |
32b32b16 | 2800 | for (i = 0; i < length; i++) |
23b2ce53 RS |
2801 | { |
2802 | switch (*format_ptr++) | |
2803 | { | |
2804 | case 'e': | |
32b32b16 AP |
2805 | if (i == length-1) |
2806 | { | |
2807 | x = XEXP (x, i); | |
2808 | goto repeat; | |
2809 | } | |
76369a82 | 2810 | mark_used_flags (XEXP (x, i), flag); |
23b2ce53 RS |
2811 | break; |
2812 | ||
2813 | case 'E': | |
2814 | for (j = 0; j < XVECLEN (x, i); j++) | |
76369a82 | 2815 | mark_used_flags (XVECEXP (x, i, j), flag); |
23b2ce53 RS |
2816 | break; |
2817 | } | |
2818 | } | |
2819 | } | |
2c07f13b | 2820 | |
76369a82 | 2821 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used |
2c07f13b JH |
2822 | to look for shared sub-parts. */ |
2823 | ||
2824 | void | |
76369a82 | 2825 | reset_used_flags (rtx x) |
2c07f13b | 2826 | { |
76369a82 NF |
2827 | mark_used_flags (x, 0); |
2828 | } | |
2c07f13b | 2829 | |
76369a82 NF |
2830 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used |
2831 | to look for shared sub-parts. */ | |
2c07f13b | 2832 | |
76369a82 NF |
2833 | void |
2834 | set_used_flags (rtx x) | |
2835 | { | |
2836 | mark_used_flags (x, 1); | |
2c07f13b | 2837 | } |
23b2ce53 RS |
2838 | \f |
2839 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2840 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2841 | OTHER must be valid as a SET_DEST. */ | |
2842 | ||
2843 | rtx | |
502b8322 | 2844 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
2845 | { |
2846 | while (1) | |
2847 | switch (GET_CODE (other)) | |
2848 | { | |
2849 | case SUBREG: | |
2850 | other = SUBREG_REG (other); | |
2851 | break; | |
2852 | case STRICT_LOW_PART: | |
2853 | case SIGN_EXTEND: | |
2854 | case ZERO_EXTEND: | |
2855 | other = XEXP (other, 0); | |
2856 | break; | |
2857 | default: | |
2858 | goto done; | |
2859 | } | |
2860 | done: | |
3c0cb5de | 2861 | if ((MEM_P (other) |
23b2ce53 | 2862 | && ! CONSTANT_P (x) |
f8cfc6aa | 2863 | && !REG_P (x) |
23b2ce53 | 2864 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 2865 | || (REG_P (other) |
23b2ce53 RS |
2866 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
2867 | || reg_mentioned_p (other, x)))) | |
2868 | { | |
2869 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2870 | emit_move_insn (temp, x); | |
2871 | return temp; | |
2872 | } | |
2873 | return x; | |
2874 | } | |
2875 | \f | |
2876 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2877 | ||
23b2ce53 RS |
2878 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ |
2879 | ||
2880 | rtx | |
502b8322 | 2881 | get_last_insn_anywhere (void) |
23b2ce53 RS |
2882 | { |
2883 | struct sequence_stack *stack; | |
5936d944 JH |
2884 | if (get_last_insn ()) |
2885 | return get_last_insn (); | |
49ad7cfa | 2886 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2887 | if (stack->last != 0) |
2888 | return stack->last; | |
2889 | return 0; | |
2890 | } | |
2891 | ||
2a496e8b JDA |
2892 | /* Return the first nonnote insn emitted in current sequence or current |
2893 | function. This routine looks inside SEQUENCEs. */ | |
2894 | ||
2895 | rtx | |
502b8322 | 2896 | get_first_nonnote_insn (void) |
2a496e8b | 2897 | { |
5936d944 | 2898 | rtx insn = get_insns (); |
91373fe8 JDA |
2899 | |
2900 | if (insn) | |
2901 | { | |
2902 | if (NOTE_P (insn)) | |
2903 | for (insn = next_insn (insn); | |
2904 | insn && NOTE_P (insn); | |
2905 | insn = next_insn (insn)) | |
2906 | continue; | |
2907 | else | |
2908 | { | |
2ca202e7 | 2909 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2910 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2911 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2912 | } | |
2913 | } | |
2a496e8b JDA |
2914 | |
2915 | return insn; | |
2916 | } | |
2917 | ||
2918 | /* Return the last nonnote insn emitted in current sequence or current | |
2919 | function. This routine looks inside SEQUENCEs. */ | |
2920 | ||
2921 | rtx | |
502b8322 | 2922 | get_last_nonnote_insn (void) |
2a496e8b | 2923 | { |
5936d944 | 2924 | rtx insn = get_last_insn (); |
91373fe8 JDA |
2925 | |
2926 | if (insn) | |
2927 | { | |
2928 | if (NOTE_P (insn)) | |
2929 | for (insn = previous_insn (insn); | |
2930 | insn && NOTE_P (insn); | |
2931 | insn = previous_insn (insn)) | |
2932 | continue; | |
2933 | else | |
2934 | { | |
2ca202e7 | 2935 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2936 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2937 | insn = XVECEXP (PATTERN (insn), 0, | |
2938 | XVECLEN (PATTERN (insn), 0) - 1); | |
2939 | } | |
2940 | } | |
2a496e8b JDA |
2941 | |
2942 | return insn; | |
2943 | } | |
2944 | ||
b5b8b0ac AO |
2945 | /* Return the number of actual (non-debug) insns emitted in this |
2946 | function. */ | |
2947 | ||
2948 | int | |
2949 | get_max_insn_count (void) | |
2950 | { | |
2951 | int n = cur_insn_uid; | |
2952 | ||
2953 | /* The table size must be stable across -g, to avoid codegen | |
2954 | differences due to debug insns, and not be affected by | |
2955 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
2956 | debugging of -fcompare-debug failures. */ | |
2957 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
2958 | n -= cur_debug_insn_uid; | |
2959 | else | |
2960 | n -= MIN_NONDEBUG_INSN_UID; | |
2961 | ||
2962 | return n; | |
2963 | } | |
2964 | ||
23b2ce53 RS |
2965 | \f |
2966 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2967 | of the sequence. */ | |
2968 | ||
2969 | rtx | |
502b8322 | 2970 | next_insn (rtx insn) |
23b2ce53 | 2971 | { |
75547801 KG |
2972 | if (insn) |
2973 | { | |
2974 | insn = NEXT_INSN (insn); | |
2975 | if (insn && NONJUMP_INSN_P (insn) | |
2976 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2977 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2978 | } | |
23b2ce53 | 2979 | |
75547801 | 2980 | return insn; |
23b2ce53 RS |
2981 | } |
2982 | ||
2983 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2984 | of the sequence. */ | |
2985 | ||
2986 | rtx | |
502b8322 | 2987 | previous_insn (rtx insn) |
23b2ce53 | 2988 | { |
75547801 KG |
2989 | if (insn) |
2990 | { | |
2991 | insn = PREV_INSN (insn); | |
2992 | if (insn && NONJUMP_INSN_P (insn) | |
2993 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2994 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2995 | } | |
23b2ce53 | 2996 | |
75547801 | 2997 | return insn; |
23b2ce53 RS |
2998 | } |
2999 | ||
3000 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3001 | look inside SEQUENCEs. */ | |
3002 | ||
3003 | rtx | |
502b8322 | 3004 | next_nonnote_insn (rtx insn) |
23b2ce53 | 3005 | { |
75547801 KG |
3006 | while (insn) |
3007 | { | |
3008 | insn = NEXT_INSN (insn); | |
3009 | if (insn == 0 || !NOTE_P (insn)) | |
3010 | break; | |
3011 | } | |
23b2ce53 | 3012 | |
75547801 | 3013 | return insn; |
23b2ce53 RS |
3014 | } |
3015 | ||
1e211590 DD |
3016 | /* Return the next insn after INSN that is not a NOTE, but stop the |
3017 | search before we enter another basic block. This routine does not | |
3018 | look inside SEQUENCEs. */ | |
3019 | ||
3020 | rtx | |
3021 | next_nonnote_insn_bb (rtx insn) | |
3022 | { | |
3023 | while (insn) | |
3024 | { | |
3025 | insn = NEXT_INSN (insn); | |
3026 | if (insn == 0 || !NOTE_P (insn)) | |
3027 | break; | |
3028 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3029 | return NULL_RTX; | |
3030 | } | |
3031 | ||
3032 | return insn; | |
3033 | } | |
3034 | ||
23b2ce53 RS |
3035 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3036 | not look inside SEQUENCEs. */ | |
3037 | ||
3038 | rtx | |
502b8322 | 3039 | prev_nonnote_insn (rtx insn) |
23b2ce53 | 3040 | { |
75547801 KG |
3041 | while (insn) |
3042 | { | |
3043 | insn = PREV_INSN (insn); | |
3044 | if (insn == 0 || !NOTE_P (insn)) | |
3045 | break; | |
3046 | } | |
23b2ce53 | 3047 | |
75547801 | 3048 | return insn; |
23b2ce53 RS |
3049 | } |
3050 | ||
896aa4ea DD |
3051 | /* Return the previous insn before INSN that is not a NOTE, but stop |
3052 | the search before we enter another basic block. This routine does | |
3053 | not look inside SEQUENCEs. */ | |
3054 | ||
3055 | rtx | |
3056 | prev_nonnote_insn_bb (rtx insn) | |
3057 | { | |
3058 | while (insn) | |
3059 | { | |
3060 | insn = PREV_INSN (insn); | |
3061 | if (insn == 0 || !NOTE_P (insn)) | |
3062 | break; | |
3063 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3064 | return NULL_RTX; | |
3065 | } | |
3066 | ||
3067 | return insn; | |
3068 | } | |
3069 | ||
b5b8b0ac AO |
3070 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3071 | routine does not look inside SEQUENCEs. */ | |
3072 | ||
3073 | rtx | |
3074 | next_nondebug_insn (rtx insn) | |
3075 | { | |
3076 | while (insn) | |
3077 | { | |
3078 | insn = NEXT_INSN (insn); | |
3079 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3080 | break; | |
3081 | } | |
3082 | ||
3083 | return insn; | |
3084 | } | |
3085 | ||
3086 | /* Return the previous insn before INSN that is not a DEBUG_INSN. | |
3087 | This routine does not look inside SEQUENCEs. */ | |
3088 | ||
3089 | rtx | |
3090 | prev_nondebug_insn (rtx insn) | |
3091 | { | |
3092 | while (insn) | |
3093 | { | |
3094 | insn = PREV_INSN (insn); | |
3095 | if (insn == 0 || !DEBUG_INSN_P (insn)) | |
3096 | break; | |
3097 | } | |
3098 | ||
3099 | return insn; | |
3100 | } | |
3101 | ||
f0fc0803 JJ |
3102 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN. |
3103 | This routine does not look inside SEQUENCEs. */ | |
3104 | ||
3105 | rtx | |
3106 | next_nonnote_nondebug_insn (rtx insn) | |
3107 | { | |
3108 | while (insn) | |
3109 | { | |
3110 | insn = NEXT_INSN (insn); | |
3111 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) | |
3112 | break; | |
3113 | } | |
3114 | ||
3115 | return insn; | |
3116 | } | |
3117 | ||
3118 | /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN. | |
3119 | This routine does not look inside SEQUENCEs. */ | |
3120 | ||
3121 | rtx | |
3122 | prev_nonnote_nondebug_insn (rtx insn) | |
3123 | { | |
3124 | while (insn) | |
3125 | { | |
3126 | insn = PREV_INSN (insn); | |
3127 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) | |
3128 | break; | |
3129 | } | |
3130 | ||
3131 | return insn; | |
3132 | } | |
3133 | ||
23b2ce53 RS |
3134 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3135 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3136 | SEQUENCEs. */ |
23b2ce53 RS |
3137 | |
3138 | rtx | |
502b8322 | 3139 | next_real_insn (rtx insn) |
23b2ce53 | 3140 | { |
75547801 KG |
3141 | while (insn) |
3142 | { | |
3143 | insn = NEXT_INSN (insn); | |
3144 | if (insn == 0 || INSN_P (insn)) | |
3145 | break; | |
3146 | } | |
23b2ce53 | 3147 | |
75547801 | 3148 | return insn; |
23b2ce53 RS |
3149 | } |
3150 | ||
3151 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3152 | or 0, if there is none. This routine does not look inside | |
3153 | SEQUENCEs. */ | |
3154 | ||
3155 | rtx | |
502b8322 | 3156 | prev_real_insn (rtx insn) |
23b2ce53 | 3157 | { |
75547801 KG |
3158 | while (insn) |
3159 | { | |
3160 | insn = PREV_INSN (insn); | |
3161 | if (insn == 0 || INSN_P (insn)) | |
3162 | break; | |
3163 | } | |
23b2ce53 | 3164 | |
75547801 | 3165 | return insn; |
23b2ce53 RS |
3166 | } |
3167 | ||
ee960939 OH |
3168 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3169 | This routine does not look inside SEQUENCEs. */ | |
3170 | ||
3171 | rtx | |
502b8322 | 3172 | last_call_insn (void) |
ee960939 OH |
3173 | { |
3174 | rtx insn; | |
3175 | ||
3176 | for (insn = get_last_insn (); | |
4b4bf941 | 3177 | insn && !CALL_P (insn); |
ee960939 OH |
3178 | insn = PREV_INSN (insn)) |
3179 | ; | |
3180 | ||
3181 | return insn; | |
3182 | } | |
3183 | ||
23b2ce53 | 3184 | /* Find the next insn after INSN that really does something. This routine |
9c517bf3 AK |
3185 | does not look inside SEQUENCEs. After reload this also skips over |
3186 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3187 | |
69732dcb | 3188 | int |
4f588890 | 3189 | active_insn_p (const_rtx insn) |
69732dcb | 3190 | { |
4b4bf941 JQ |
3191 | return (CALL_P (insn) || JUMP_P (insn) |
3192 | || (NONJUMP_INSN_P (insn) | |
23b8ba81 RH |
3193 | && (! reload_completed |
3194 | || (GET_CODE (PATTERN (insn)) != USE | |
3195 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3196 | } |
3197 | ||
23b2ce53 | 3198 | rtx |
502b8322 | 3199 | next_active_insn (rtx insn) |
23b2ce53 | 3200 | { |
75547801 KG |
3201 | while (insn) |
3202 | { | |
3203 | insn = NEXT_INSN (insn); | |
3204 | if (insn == 0 || active_insn_p (insn)) | |
3205 | break; | |
3206 | } | |
23b2ce53 | 3207 | |
75547801 | 3208 | return insn; |
23b2ce53 RS |
3209 | } |
3210 | ||
3211 | /* Find the last insn before INSN that really does something. This routine | |
9c517bf3 AK |
3212 | does not look inside SEQUENCEs. After reload this also skips over |
3213 | standalone USE and CLOBBER insn. */ | |
23b2ce53 RS |
3214 | |
3215 | rtx | |
502b8322 | 3216 | prev_active_insn (rtx insn) |
23b2ce53 | 3217 | { |
75547801 KG |
3218 | while (insn) |
3219 | { | |
3220 | insn = PREV_INSN (insn); | |
3221 | if (insn == 0 || active_insn_p (insn)) | |
3222 | break; | |
3223 | } | |
23b2ce53 | 3224 | |
75547801 | 3225 | return insn; |
23b2ce53 RS |
3226 | } |
3227 | ||
3228 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
3229 | ||
3230 | rtx | |
502b8322 | 3231 | next_label (rtx insn) |
23b2ce53 | 3232 | { |
75547801 KG |
3233 | while (insn) |
3234 | { | |
3235 | insn = NEXT_INSN (insn); | |
3236 | if (insn == 0 || LABEL_P (insn)) | |
3237 | break; | |
3238 | } | |
23b2ce53 | 3239 | |
75547801 | 3240 | return insn; |
23b2ce53 RS |
3241 | } |
3242 | ||
3243 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
3244 | ||
3245 | rtx | |
502b8322 | 3246 | prev_label (rtx insn) |
23b2ce53 | 3247 | { |
75547801 KG |
3248 | while (insn) |
3249 | { | |
3250 | insn = PREV_INSN (insn); | |
3251 | if (insn == 0 || LABEL_P (insn)) | |
3252 | break; | |
3253 | } | |
23b2ce53 | 3254 | |
75547801 | 3255 | return insn; |
23b2ce53 | 3256 | } |
6c2511d3 RS |
3257 | |
3258 | /* Return the last label to mark the same position as LABEL. Return null | |
3259 | if LABEL itself is null. */ | |
3260 | ||
3261 | rtx | |
3262 | skip_consecutive_labels (rtx label) | |
3263 | { | |
3264 | rtx insn; | |
3265 | ||
3266 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | |
3267 | if (LABEL_P (insn)) | |
3268 | label = insn; | |
3269 | ||
3270 | return label; | |
3271 | } | |
23b2ce53 RS |
3272 | \f |
3273 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
3274 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3275 | and REG_CC_USER notes so we can find it. */ | |
3276 | ||
3277 | void | |
502b8322 | 3278 | link_cc0_insns (rtx insn) |
c572e5ba JVA |
3279 | { |
3280 | rtx user = next_nonnote_insn (insn); | |
3281 | ||
4b4bf941 | 3282 | if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE) |
c572e5ba JVA |
3283 | user = XVECEXP (PATTERN (user), 0, 0); |
3284 | ||
65c5f2a6 ILT |
3285 | add_reg_note (user, REG_CC_SETTER, insn); |
3286 | add_reg_note (insn, REG_CC_USER, user); | |
c572e5ba JVA |
3287 | } |
3288 | ||
23b2ce53 RS |
3289 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3290 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3291 | applied to the result of this function should yield INSN). | |
3292 | ||
3293 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3294 | is present, it contains the insn that uses CC0. | |
3295 | ||
3296 | Return 0 if we can't find the insn. */ | |
3297 | ||
3298 | rtx | |
502b8322 | 3299 | next_cc0_user (rtx insn) |
23b2ce53 | 3300 | { |
906c4e36 | 3301 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3302 | |
3303 | if (note) | |
3304 | return XEXP (note, 0); | |
3305 | ||
3306 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3307 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
23b2ce53 RS |
3308 | insn = XVECEXP (PATTERN (insn), 0, 0); |
3309 | ||
2c3c49de | 3310 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
3311 | return insn; |
3312 | ||
3313 | return 0; | |
3314 | } | |
3315 | ||
3316 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3317 | note, it is the previous insn. */ | |
3318 | ||
3319 | rtx | |
502b8322 | 3320 | prev_cc0_setter (rtx insn) |
23b2ce53 | 3321 | { |
906c4e36 | 3322 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3323 | |
3324 | if (note) | |
3325 | return XEXP (note, 0); | |
3326 | ||
3327 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3328 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 RS |
3329 | |
3330 | return insn; | |
3331 | } | |
3332 | #endif | |
e5bef2e4 | 3333 | |
594f8779 RZ |
3334 | #ifdef AUTO_INC_DEC |
3335 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3336 | ||
3337 | static int | |
3338 | find_auto_inc (rtx *xp, void *data) | |
3339 | { | |
3340 | rtx x = *xp; | |
5ead67f6 | 3341 | rtx reg = (rtx) data; |
594f8779 RZ |
3342 | |
3343 | if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC) | |
3344 | return 0; | |
3345 | ||
3346 | switch (GET_CODE (x)) | |
3347 | { | |
3348 | case PRE_DEC: | |
3349 | case PRE_INC: | |
3350 | case POST_DEC: | |
3351 | case POST_INC: | |
3352 | case PRE_MODIFY: | |
3353 | case POST_MODIFY: | |
3354 | if (rtx_equal_p (reg, XEXP (x, 0))) | |
3355 | return 1; | |
3356 | break; | |
3357 | ||
3358 | default: | |
3359 | gcc_unreachable (); | |
3360 | } | |
3361 | return -1; | |
3362 | } | |
3363 | #endif | |
3364 | ||
e5bef2e4 HB |
3365 | /* Increment the label uses for all labels present in rtx. */ |
3366 | ||
3367 | static void | |
502b8322 | 3368 | mark_label_nuses (rtx x) |
e5bef2e4 | 3369 | { |
b3694847 SS |
3370 | enum rtx_code code; |
3371 | int i, j; | |
3372 | const char *fmt; | |
e5bef2e4 HB |
3373 | |
3374 | code = GET_CODE (x); | |
7537fc90 | 3375 | if (code == LABEL_REF && LABEL_P (XEXP (x, 0))) |
e5bef2e4 HB |
3376 | LABEL_NUSES (XEXP (x, 0))++; |
3377 | ||
3378 | fmt = GET_RTX_FORMAT (code); | |
3379 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3380 | { | |
3381 | if (fmt[i] == 'e') | |
0fb7aeda | 3382 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3383 | else if (fmt[i] == 'E') |
0fb7aeda | 3384 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3385 | mark_label_nuses (XVECEXP (x, i, j)); |
3386 | } | |
3387 | } | |
3388 | ||
23b2ce53 RS |
3389 | \f |
3390 | /* Try splitting insns that can be split for better scheduling. | |
3391 | PAT is the pattern which might split. | |
3392 | TRIAL is the insn providing PAT. | |
cc2902df | 3393 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3394 | |
3395 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3396 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3397 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3398 | ||
3399 | rtx | |
502b8322 | 3400 | try_split (rtx pat, rtx trial, int last) |
23b2ce53 RS |
3401 | { |
3402 | rtx before = PREV_INSN (trial); | |
3403 | rtx after = NEXT_INSN (trial); | |
23b2ce53 | 3404 | int has_barrier = 0; |
4a8cae83 | 3405 | rtx note, seq, tem; |
6b24c259 | 3406 | int probability; |
599aedd9 RH |
3407 | rtx insn_last, insn; |
3408 | int njumps = 0; | |
6b24c259 | 3409 | |
cd9c1ca8 RH |
3410 | /* We're not good at redistributing frame information. */ |
3411 | if (RTX_FRAME_RELATED_P (trial)) | |
3412 | return trial; | |
3413 | ||
6b24c259 JH |
3414 | if (any_condjump_p (trial) |
3415 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3416 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3417 | probability = split_branch_probability; | |
3418 | ||
3419 | seq = split_insns (pat, trial); | |
3420 | ||
3421 | split_branch_probability = -1; | |
23b2ce53 RS |
3422 | |
3423 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3424 | We may need to handle this specially. */ | |
4b4bf941 | 3425 | if (after && BARRIER_P (after)) |
23b2ce53 RS |
3426 | { |
3427 | has_barrier = 1; | |
3428 | after = NEXT_INSN (after); | |
3429 | } | |
3430 | ||
599aedd9 RH |
3431 | if (!seq) |
3432 | return trial; | |
3433 | ||
3434 | /* Avoid infinite loop if any insn of the result matches | |
3435 | the original pattern. */ | |
3436 | insn_last = seq; | |
3437 | while (1) | |
23b2ce53 | 3438 | { |
599aedd9 RH |
3439 | if (INSN_P (insn_last) |
3440 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3441 | return trial; | |
3442 | if (!NEXT_INSN (insn_last)) | |
3443 | break; | |
3444 | insn_last = NEXT_INSN (insn_last); | |
3445 | } | |
750c9258 | 3446 | |
6fb5fa3c DB |
3447 | /* We will be adding the new sequence to the function. The splitters |
3448 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3449 | unshare_all_rtl_in_chain (seq); | |
3450 | ||
599aedd9 RH |
3451 | /* Mark labels. */ |
3452 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3453 | { | |
4b4bf941 | 3454 | if (JUMP_P (insn)) |
599aedd9 RH |
3455 | { |
3456 | mark_jump_label (PATTERN (insn), insn, 0); | |
3457 | njumps++; | |
3458 | if (probability != -1 | |
3459 | && any_condjump_p (insn) | |
3460 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3461 | { |
599aedd9 RH |
3462 | /* We can preserve the REG_BR_PROB notes only if exactly |
3463 | one jump is created, otherwise the machine description | |
3464 | is responsible for this step using | |
3465 | split_branch_probability variable. */ | |
5b0264cb | 3466 | gcc_assert (njumps == 1); |
65c5f2a6 | 3467 | add_reg_note (insn, REG_BR_PROB, GEN_INT (probability)); |
2f937369 | 3468 | } |
599aedd9 RH |
3469 | } |
3470 | } | |
3471 | ||
3472 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3473 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
4b4bf941 | 3474 | if (CALL_P (trial)) |
599aedd9 RH |
3475 | { |
3476 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3477 | if (CALL_P (insn)) |
599aedd9 | 3478 | { |
f6a1f3f6 RH |
3479 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3480 | while (*p) | |
3481 | p = &XEXP (*p, 1); | |
3482 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
599aedd9 RH |
3483 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3484 | } | |
3485 | } | |
4b5e8abe | 3486 | |
599aedd9 RH |
3487 | /* Copy notes, particularly those related to the CFG. */ |
3488 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3489 | { | |
3490 | switch (REG_NOTE_KIND (note)) | |
3491 | { | |
3492 | case REG_EH_REGION: | |
1d65f45c | 3493 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3494 | break; |
216183ce | 3495 | |
599aedd9 RH |
3496 | case REG_NORETURN: |
3497 | case REG_SETJMP: | |
594f8779 | 3498 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3499 | { |
4b4bf941 | 3500 | if (CALL_P (insn)) |
65c5f2a6 | 3501 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3502 | } |
599aedd9 | 3503 | break; |
d6e95df8 | 3504 | |
599aedd9 | 3505 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3506 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3507 | { |
4b4bf941 | 3508 | if (JUMP_P (insn)) |
65c5f2a6 | 3509 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3510 | } |
599aedd9 | 3511 | break; |
e5bef2e4 | 3512 | |
594f8779 RZ |
3513 | #ifdef AUTO_INC_DEC |
3514 | case REG_INC: | |
3515 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3516 | { | |
3517 | rtx reg = XEXP (note, 0); | |
3518 | if (!FIND_REG_INC_NOTE (insn, reg) | |
3519 | && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0) | |
65c5f2a6 | 3520 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3521 | } |
3522 | break; | |
3523 | #endif | |
3524 | ||
599aedd9 RH |
3525 | default: |
3526 | break; | |
23b2ce53 | 3527 | } |
599aedd9 RH |
3528 | } |
3529 | ||
3530 | /* If there are LABELS inside the split insns increment the | |
3531 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3532 | if (INSN_P (trial)) |
599aedd9 RH |
3533 | { |
3534 | insn = insn_last; | |
3535 | while (insn != NULL_RTX) | |
23b2ce53 | 3536 | { |
cf7c4aa6 | 3537 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3538 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3539 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3540 | |
599aedd9 RH |
3541 | insn = PREV_INSN (insn); |
3542 | } | |
23b2ce53 RS |
3543 | } |
3544 | ||
0435312e | 3545 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
599aedd9 RH |
3546 | |
3547 | delete_insn (trial); | |
3548 | if (has_barrier) | |
3549 | emit_barrier_after (tem); | |
3550 | ||
3551 | /* Recursively call try_split for each new insn created; by the | |
3552 | time control returns here that insn will be fully split, so | |
3553 | set LAST and continue from the insn after the one returned. | |
3554 | We can't use next_active_insn here since AFTER may be a note. | |
3555 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3556 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3557 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3558 | tem = try_split (PATTERN (tem), tem, 1); | |
3559 | ||
3560 | /* Return either the first or the last insn, depending on which was | |
3561 | requested. */ | |
3562 | return last | |
5936d944 | 3563 | ? (after ? PREV_INSN (after) : get_last_insn ()) |
599aedd9 | 3564 | : NEXT_INSN (before); |
23b2ce53 RS |
3565 | } |
3566 | \f | |
3567 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3568 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
3569 | |
3570 | rtx | |
502b8322 | 3571 | make_insn_raw (rtx pattern) |
23b2ce53 | 3572 | { |
b3694847 | 3573 | rtx insn; |
23b2ce53 | 3574 | |
1f8f4a0b | 3575 | insn = rtx_alloc (INSN); |
23b2ce53 | 3576 | |
43127294 | 3577 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3578 | PATTERN (insn) = pattern; |
3579 | INSN_CODE (insn) = -1; | |
1632afca | 3580 | REG_NOTES (insn) = NULL; |
55e092c4 | 3581 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3582 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3583 | |
47984720 NC |
3584 | #ifdef ENABLE_RTL_CHECKING |
3585 | if (insn | |
2c3c49de | 3586 | && INSN_P (insn) |
47984720 NC |
3587 | && (returnjump_p (insn) |
3588 | || (GET_CODE (insn) == SET | |
3589 | && SET_DEST (insn) == pc_rtx))) | |
3590 | { | |
d4ee4d25 | 3591 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3592 | debug_rtx (insn); |
3593 | } | |
3594 | #endif | |
750c9258 | 3595 | |
23b2ce53 RS |
3596 | return insn; |
3597 | } | |
3598 | ||
b5b8b0ac AO |
3599 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
3600 | ||
3601 | rtx | |
3602 | make_debug_insn_raw (rtx pattern) | |
3603 | { | |
3604 | rtx insn; | |
3605 | ||
3606 | insn = rtx_alloc (DEBUG_INSN); | |
3607 | INSN_UID (insn) = cur_debug_insn_uid++; | |
3608 | if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID) | |
3609 | INSN_UID (insn) = cur_insn_uid++; | |
3610 | ||
3611 | PATTERN (insn) = pattern; | |
3612 | INSN_CODE (insn) = -1; | |
3613 | REG_NOTES (insn) = NULL; | |
3614 | INSN_LOCATOR (insn) = curr_insn_locator (); | |
3615 | BLOCK_FOR_INSN (insn) = NULL; | |
3616 | ||
3617 | return insn; | |
3618 | } | |
3619 | ||
2f937369 | 3620 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3621 | |
38109dab | 3622 | rtx |
502b8322 | 3623 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3624 | { |
b3694847 | 3625 | rtx insn; |
23b2ce53 | 3626 | |
4b1f5e8c | 3627 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 3628 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3629 | |
3630 | PATTERN (insn) = pattern; | |
3631 | INSN_CODE (insn) = -1; | |
1632afca RS |
3632 | REG_NOTES (insn) = NULL; |
3633 | JUMP_LABEL (insn) = NULL; | |
55e092c4 | 3634 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3635 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3636 | |
3637 | return insn; | |
3638 | } | |
aff507f4 | 3639 | |
2f937369 | 3640 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 RK |
3641 | |
3642 | static rtx | |
502b8322 | 3643 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3644 | { |
b3694847 | 3645 | rtx insn; |
aff507f4 RK |
3646 | |
3647 | insn = rtx_alloc (CALL_INSN); | |
3648 | INSN_UID (insn) = cur_insn_uid++; | |
3649 | ||
3650 | PATTERN (insn) = pattern; | |
3651 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3652 | REG_NOTES (insn) = NULL; |
3653 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
55e092c4 | 3654 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3655 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3656 | |
3657 | return insn; | |
3658 | } | |
23b2ce53 RS |
3659 | \f |
3660 | /* Add INSN to the end of the doubly-linked list. | |
3661 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3662 | ||
3663 | void | |
502b8322 | 3664 | add_insn (rtx insn) |
23b2ce53 | 3665 | { |
5936d944 | 3666 | PREV_INSN (insn) = get_last_insn(); |
23b2ce53 RS |
3667 | NEXT_INSN (insn) = 0; |
3668 | ||
5936d944 JH |
3669 | if (NULL != get_last_insn()) |
3670 | NEXT_INSN (get_last_insn ()) = insn; | |
23b2ce53 | 3671 | |
5936d944 JH |
3672 | if (NULL == get_insns ()) |
3673 | set_first_insn (insn); | |
23b2ce53 | 3674 | |
5936d944 | 3675 | set_last_insn (insn); |
23b2ce53 RS |
3676 | } |
3677 | ||
a0ae8e8d RK |
3678 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3679 | the next should be the only functions called to insert an insn once | |
ba213285 | 3680 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 3681 | SEQUENCE. */ |
23b2ce53 RS |
3682 | |
3683 | void | |
6fb5fa3c | 3684 | add_insn_after (rtx insn, rtx after, basic_block bb) |
23b2ce53 RS |
3685 | { |
3686 | rtx next = NEXT_INSN (after); | |
3687 | ||
5b0264cb | 3688 | gcc_assert (!optimize || !INSN_DELETED_P (after)); |
ba213285 | 3689 | |
23b2ce53 RS |
3690 | NEXT_INSN (insn) = next; |
3691 | PREV_INSN (insn) = after; | |
3692 | ||
3693 | if (next) | |
3694 | { | |
3695 | PREV_INSN (next) = insn; | |
4b4bf941 | 3696 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
23b2ce53 RS |
3697 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; |
3698 | } | |
5936d944 JH |
3699 | else if (get_last_insn () == after) |
3700 | set_last_insn (insn); | |
23b2ce53 RS |
3701 | else |
3702 | { | |
49ad7cfa | 3703 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
3704 | /* Scan all pending sequences too. */ |
3705 | for (; stack; stack = stack->next) | |
3706 | if (after == stack->last) | |
fef0509b RK |
3707 | { |
3708 | stack->last = insn; | |
3709 | break; | |
3710 | } | |
a0ae8e8d | 3711 | |
5b0264cb | 3712 | gcc_assert (stack); |
23b2ce53 RS |
3713 | } |
3714 | ||
4b4bf941 JQ |
3715 | if (!BARRIER_P (after) |
3716 | && !BARRIER_P (insn) | |
3c030e88 JH |
3717 | && (bb = BLOCK_FOR_INSN (after))) |
3718 | { | |
3719 | set_block_for_insn (insn, bb); | |
38c1593d | 3720 | if (INSN_P (insn)) |
6fb5fa3c | 3721 | df_insn_rescan (insn); |
3c030e88 | 3722 | /* Should not happen as first in the BB is always |
a1f300c0 | 3723 | either NOTE or LABEL. */ |
a813c111 | 3724 | if (BB_END (bb) == after |
3c030e88 | 3725 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 3726 | && !BARRIER_P (insn) |
a38e7aa5 | 3727 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
a813c111 | 3728 | BB_END (bb) = insn; |
3c030e88 JH |
3729 | } |
3730 | ||
23b2ce53 | 3731 | NEXT_INSN (after) = insn; |
4b4bf941 | 3732 | if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE) |
23b2ce53 RS |
3733 | { |
3734 | rtx sequence = PATTERN (after); | |
3735 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3736 | } | |
3737 | } | |
3738 | ||
a0ae8e8d | 3739 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
6fb5fa3c DB |
3740 | the previous should be the only functions called to insert an insn |
3741 | once delay slots have been filled since only they know how to | |
3742 | update a SEQUENCE. If BB is NULL, an attempt is made to infer the | |
3743 | bb from before. */ | |
a0ae8e8d RK |
3744 | |
3745 | void | |
6fb5fa3c | 3746 | add_insn_before (rtx insn, rtx before, basic_block bb) |
a0ae8e8d RK |
3747 | { |
3748 | rtx prev = PREV_INSN (before); | |
3749 | ||
5b0264cb | 3750 | gcc_assert (!optimize || !INSN_DELETED_P (before)); |
ba213285 | 3751 | |
a0ae8e8d RK |
3752 | PREV_INSN (insn) = prev; |
3753 | NEXT_INSN (insn) = before; | |
3754 | ||
3755 | if (prev) | |
3756 | { | |
3757 | NEXT_INSN (prev) = insn; | |
4b4bf941 | 3758 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
a0ae8e8d RK |
3759 | { |
3760 | rtx sequence = PATTERN (prev); | |
3761 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3762 | } | |
3763 | } | |
5936d944 JH |
3764 | else if (get_insns () == before) |
3765 | set_first_insn (insn); | |
a0ae8e8d RK |
3766 | else |
3767 | { | |
49ad7cfa | 3768 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
3769 | /* Scan all pending sequences too. */ |
3770 | for (; stack; stack = stack->next) | |
3771 | if (before == stack->first) | |
fef0509b RK |
3772 | { |
3773 | stack->first = insn; | |
3774 | break; | |
3775 | } | |
a0ae8e8d | 3776 | |
5b0264cb | 3777 | gcc_assert (stack); |
a0ae8e8d RK |
3778 | } |
3779 | ||
b8698a0f | 3780 | if (!bb |
6fb5fa3c DB |
3781 | && !BARRIER_P (before) |
3782 | && !BARRIER_P (insn)) | |
3783 | bb = BLOCK_FOR_INSN (before); | |
3784 | ||
3785 | if (bb) | |
3c030e88 JH |
3786 | { |
3787 | set_block_for_insn (insn, bb); | |
38c1593d | 3788 | if (INSN_P (insn)) |
6fb5fa3c | 3789 | df_insn_rescan (insn); |
5b0264cb | 3790 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 3791 | LABEL. */ |
5b0264cb NS |
3792 | gcc_assert (BB_HEAD (bb) != insn |
3793 | /* Avoid clobbering of structure when creating new BB. */ | |
3794 | || BARRIER_P (insn) | |
a38e7aa5 | 3795 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 JH |
3796 | } |
3797 | ||
a0ae8e8d | 3798 | PREV_INSN (before) = insn; |
4b4bf941 | 3799 | if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE) |
a0ae8e8d RK |
3800 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; |
3801 | } | |
3802 | ||
6fb5fa3c DB |
3803 | |
3804 | /* Replace insn with an deleted instruction note. */ | |
3805 | ||
0ce2b299 EB |
3806 | void |
3807 | set_insn_deleted (rtx insn) | |
6fb5fa3c DB |
3808 | { |
3809 | df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn)); | |
3810 | PUT_CODE (insn, NOTE); | |
3811 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
3812 | } | |
3813 | ||
3814 | ||
89e99eea DB |
3815 | /* Remove an insn from its doubly-linked list. This function knows how |
3816 | to handle sequences. */ | |
3817 | void | |
502b8322 | 3818 | remove_insn (rtx insn) |
89e99eea DB |
3819 | { |
3820 | rtx next = NEXT_INSN (insn); | |
3821 | rtx prev = PREV_INSN (insn); | |
53c17031 JH |
3822 | basic_block bb; |
3823 | ||
6fb5fa3c DB |
3824 | /* Later in the code, the block will be marked dirty. */ |
3825 | df_insn_delete (NULL, INSN_UID (insn)); | |
3826 | ||
89e99eea DB |
3827 | if (prev) |
3828 | { | |
3829 | NEXT_INSN (prev) = next; | |
4b4bf941 | 3830 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea DB |
3831 | { |
3832 | rtx sequence = PATTERN (prev); | |
3833 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3834 | } | |
3835 | } | |
5936d944 JH |
3836 | else if (get_insns () == insn) |
3837 | { | |
fb9ef4c1 JH |
3838 | if (next) |
3839 | PREV_INSN (next) = NULL; | |
5936d944 JH |
3840 | set_first_insn (next); |
3841 | } | |
89e99eea DB |
3842 | else |
3843 | { | |
49ad7cfa | 3844 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3845 | /* Scan all pending sequences too. */ |
3846 | for (; stack; stack = stack->next) | |
3847 | if (insn == stack->first) | |
3848 | { | |
3849 | stack->first = next; | |
3850 | break; | |
3851 | } | |
3852 | ||
5b0264cb | 3853 | gcc_assert (stack); |
89e99eea DB |
3854 | } |
3855 | ||
3856 | if (next) | |
3857 | { | |
3858 | PREV_INSN (next) = prev; | |
4b4bf941 | 3859 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
89e99eea DB |
3860 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; |
3861 | } | |
5936d944 JH |
3862 | else if (get_last_insn () == insn) |
3863 | set_last_insn (prev); | |
89e99eea DB |
3864 | else |
3865 | { | |
49ad7cfa | 3866 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3867 | /* Scan all pending sequences too. */ |
3868 | for (; stack; stack = stack->next) | |
3869 | if (insn == stack->last) | |
3870 | { | |
3871 | stack->last = prev; | |
3872 | break; | |
3873 | } | |
3874 | ||
5b0264cb | 3875 | gcc_assert (stack); |
89e99eea | 3876 | } |
4b4bf941 | 3877 | if (!BARRIER_P (insn) |
53c17031 JH |
3878 | && (bb = BLOCK_FOR_INSN (insn))) |
3879 | { | |
4e0084e4 | 3880 | if (NONDEBUG_INSN_P (insn)) |
6fb5fa3c | 3881 | df_set_bb_dirty (bb); |
a813c111 | 3882 | if (BB_HEAD (bb) == insn) |
53c17031 | 3883 | { |
3bf1e984 RK |
3884 | /* Never ever delete the basic block note without deleting whole |
3885 | basic block. */ | |
5b0264cb | 3886 | gcc_assert (!NOTE_P (insn)); |
a813c111 | 3887 | BB_HEAD (bb) = next; |
53c17031 | 3888 | } |
a813c111 SB |
3889 | if (BB_END (bb) == insn) |
3890 | BB_END (bb) = prev; | |
53c17031 | 3891 | } |
89e99eea DB |
3892 | } |
3893 | ||
ee960939 OH |
3894 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3895 | ||
3896 | void | |
502b8322 | 3897 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 3898 | { |
5b0264cb | 3899 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
3900 | |
3901 | /* Put the register usage information on the CALL. If there is already | |
3902 | some usage information, put ours at the end. */ | |
3903 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3904 | { | |
3905 | rtx link; | |
3906 | ||
3907 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3908 | link = XEXP (link, 1)) | |
3909 | ; | |
3910 | ||
3911 | XEXP (link, 1) = call_fusage; | |
3912 | } | |
3913 | else | |
3914 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3915 | } | |
3916 | ||
23b2ce53 RS |
3917 | /* Delete all insns made since FROM. |
3918 | FROM becomes the new last instruction. */ | |
3919 | ||
3920 | void | |
502b8322 | 3921 | delete_insns_since (rtx from) |
23b2ce53 RS |
3922 | { |
3923 | if (from == 0) | |
5936d944 | 3924 | set_first_insn (0); |
23b2ce53 RS |
3925 | else |
3926 | NEXT_INSN (from) = 0; | |
5936d944 | 3927 | set_last_insn (from); |
23b2ce53 RS |
3928 | } |
3929 | ||
5dab5552 MS |
3930 | /* This function is deprecated, please use sequences instead. |
3931 | ||
3932 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
3933 | The insns to be moved are those between FROM and TO. |
3934 | They are moved to a new position after the insn AFTER. | |
3935 | AFTER must not be FROM or TO or any insn in between. | |
3936 | ||
3937 | This function does not know about SEQUENCEs and hence should not be | |
3938 | called after delay-slot filling has been done. */ | |
3939 | ||
3940 | void | |
502b8322 | 3941 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
23b2ce53 | 3942 | { |
4f8344eb HPN |
3943 | #ifdef ENABLE_CHECKING |
3944 | rtx x; | |
3945 | for (x = from; x != to; x = NEXT_INSN (x)) | |
3946 | gcc_assert (after != x); | |
3947 | gcc_assert (after != to); | |
3948 | #endif | |
3949 | ||
23b2ce53 RS |
3950 | /* Splice this bunch out of where it is now. */ |
3951 | if (PREV_INSN (from)) | |
3952 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3953 | if (NEXT_INSN (to)) | |
3954 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
5936d944 JH |
3955 | if (get_last_insn () == to) |
3956 | set_last_insn (PREV_INSN (from)); | |
3957 | if (get_insns () == from) | |
3958 | set_first_insn (NEXT_INSN (to)); | |
23b2ce53 RS |
3959 | |
3960 | /* Make the new neighbors point to it and it to them. */ | |
3961 | if (NEXT_INSN (after)) | |
3962 | PREV_INSN (NEXT_INSN (after)) = to; | |
3963 | ||
3964 | NEXT_INSN (to) = NEXT_INSN (after); | |
3965 | PREV_INSN (from) = after; | |
3966 | NEXT_INSN (after) = from; | |
5936d944 JH |
3967 | if (after == get_last_insn()) |
3968 | set_last_insn (to); | |
23b2ce53 RS |
3969 | } |
3970 | ||
3c030e88 JH |
3971 | /* Same as function above, but take care to update BB boundaries. */ |
3972 | void | |
502b8322 | 3973 | reorder_insns (rtx from, rtx to, rtx after) |
3c030e88 JH |
3974 | { |
3975 | rtx prev = PREV_INSN (from); | |
3976 | basic_block bb, bb2; | |
3977 | ||
3978 | reorder_insns_nobb (from, to, after); | |
3979 | ||
4b4bf941 | 3980 | if (!BARRIER_P (after) |
3c030e88 JH |
3981 | && (bb = BLOCK_FOR_INSN (after))) |
3982 | { | |
3983 | rtx x; | |
6fb5fa3c | 3984 | df_set_bb_dirty (bb); |
68252e27 | 3985 | |
4b4bf941 | 3986 | if (!BARRIER_P (from) |
3c030e88 JH |
3987 | && (bb2 = BLOCK_FOR_INSN (from))) |
3988 | { | |
a813c111 SB |
3989 | if (BB_END (bb2) == to) |
3990 | BB_END (bb2) = prev; | |
6fb5fa3c | 3991 | df_set_bb_dirty (bb2); |
3c030e88 JH |
3992 | } |
3993 | ||
a813c111 SB |
3994 | if (BB_END (bb) == after) |
3995 | BB_END (bb) = to; | |
3c030e88 JH |
3996 | |
3997 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 3998 | if (!BARRIER_P (x)) |
63642d5a | 3999 | df_insn_change_bb (x, bb); |
3c030e88 JH |
4000 | } |
4001 | } | |
4002 | ||
23b2ce53 | 4003 | \f |
2f937369 DM |
4004 | /* Emit insn(s) of given code and pattern |
4005 | at a specified place within the doubly-linked list. | |
23b2ce53 | 4006 | |
2f937369 DM |
4007 | All of the emit_foo global entry points accept an object |
4008 | X which is either an insn list or a PATTERN of a single | |
4009 | instruction. | |
23b2ce53 | 4010 | |
2f937369 DM |
4011 | There are thus a few canonical ways to generate code and |
4012 | emit it at a specific place in the instruction stream. For | |
4013 | example, consider the instruction named SPOT and the fact that | |
4014 | we would like to emit some instructions before SPOT. We might | |
4015 | do it like this: | |
23b2ce53 | 4016 | |
2f937369 DM |
4017 | start_sequence (); |
4018 | ... emit the new instructions ... | |
4019 | insns_head = get_insns (); | |
4020 | end_sequence (); | |
23b2ce53 | 4021 | |
2f937369 | 4022 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4023 | |
2f937369 DM |
4024 | It used to be common to generate SEQUENCE rtl instead, but that |
4025 | is a relic of the past which no longer occurs. The reason is that | |
4026 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4027 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4028 | |
5f02387d NF |
4029 | static rtx |
4030 | emit_pattern_before_noloc (rtx x, rtx before, rtx last, basic_block bb, | |
4031 | rtx (*make_raw) (rtx)) | |
23b2ce53 | 4032 | { |
b3694847 | 4033 | rtx insn; |
23b2ce53 | 4034 | |
5b0264cb | 4035 | gcc_assert (before); |
2f937369 DM |
4036 | |
4037 | if (x == NULL_RTX) | |
4038 | return last; | |
4039 | ||
4040 | switch (GET_CODE (x)) | |
23b2ce53 | 4041 | { |
b5b8b0ac | 4042 | case DEBUG_INSN: |
2f937369 DM |
4043 | case INSN: |
4044 | case JUMP_INSN: | |
4045 | case CALL_INSN: | |
4046 | case CODE_LABEL: | |
4047 | case BARRIER: | |
4048 | case NOTE: | |
4049 | insn = x; | |
4050 | while (insn) | |
4051 | { | |
4052 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4053 | add_insn_before (insn, before, bb); |
2f937369 DM |
4054 | last = insn; |
4055 | insn = next; | |
4056 | } | |
4057 | break; | |
4058 | ||
4059 | #ifdef ENABLE_RTL_CHECKING | |
4060 | case SEQUENCE: | |
5b0264cb | 4061 | gcc_unreachable (); |
2f937369 DM |
4062 | break; |
4063 | #endif | |
4064 | ||
4065 | default: | |
5f02387d | 4066 | last = (*make_raw) (x); |
6fb5fa3c | 4067 | add_insn_before (last, before, bb); |
2f937369 | 4068 | break; |
23b2ce53 RS |
4069 | } |
4070 | ||
2f937369 | 4071 | return last; |
23b2ce53 RS |
4072 | } |
4073 | ||
5f02387d NF |
4074 | /* Make X be output before the instruction BEFORE. */ |
4075 | ||
4076 | rtx | |
4077 | emit_insn_before_noloc (rtx x, rtx before, basic_block bb) | |
4078 | { | |
4079 | return emit_pattern_before_noloc (x, before, before, bb, make_insn_raw); | |
4080 | } | |
4081 | ||
2f937369 | 4082 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4083 | and output it before the instruction BEFORE. */ |
4084 | ||
4085 | rtx | |
a7102479 | 4086 | emit_jump_insn_before_noloc (rtx x, rtx before) |
23b2ce53 | 4087 | { |
5f02387d NF |
4088 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4089 | make_jump_insn_raw); | |
23b2ce53 RS |
4090 | } |
4091 | ||
2f937369 | 4092 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4093 | and output it before the instruction BEFORE. */ |
4094 | ||
4095 | rtx | |
a7102479 | 4096 | emit_call_insn_before_noloc (rtx x, rtx before) |
969d70ca | 4097 | { |
5f02387d NF |
4098 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4099 | make_call_insn_raw); | |
969d70ca JH |
4100 | } |
4101 | ||
b5b8b0ac AO |
4102 | /* Make an instruction with body X and code DEBUG_INSN |
4103 | and output it before the instruction BEFORE. */ | |
4104 | ||
4105 | rtx | |
4106 | emit_debug_insn_before_noloc (rtx x, rtx before) | |
4107 | { | |
5f02387d NF |
4108 | return emit_pattern_before_noloc (x, before, NULL_RTX, NULL, |
4109 | make_debug_insn_raw); | |
b5b8b0ac AO |
4110 | } |
4111 | ||
23b2ce53 | 4112 | /* Make an insn of code BARRIER |
e881bb1b | 4113 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
4114 | |
4115 | rtx | |
502b8322 | 4116 | emit_barrier_before (rtx before) |
23b2ce53 | 4117 | { |
b3694847 | 4118 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4119 | |
4120 | INSN_UID (insn) = cur_insn_uid++; | |
4121 | ||
6fb5fa3c | 4122 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4123 | return insn; |
4124 | } | |
4125 | ||
e881bb1b RH |
4126 | /* Emit the label LABEL before the insn BEFORE. */ |
4127 | ||
4128 | rtx | |
502b8322 | 4129 | emit_label_before (rtx label, rtx before) |
e881bb1b RH |
4130 | { |
4131 | /* This can be called twice for the same label as a result of the | |
4132 | confusion that follows a syntax error! So make it harmless. */ | |
4133 | if (INSN_UID (label) == 0) | |
4134 | { | |
4135 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4136 | add_insn_before (label, before, NULL); |
e881bb1b RH |
4137 | } |
4138 | ||
4139 | return label; | |
4140 | } | |
4141 | ||
23b2ce53 RS |
4142 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
4143 | ||
4144 | rtx | |
a38e7aa5 | 4145 | emit_note_before (enum insn_note subtype, rtx before) |
23b2ce53 | 4146 | { |
b3694847 | 4147 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4148 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4149 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4150 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4151 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
23b2ce53 | 4152 | |
6fb5fa3c | 4153 | add_insn_before (note, before, NULL); |
23b2ce53 RS |
4154 | return note; |
4155 | } | |
4156 | \f | |
2f937369 DM |
4157 | /* Helper for emit_insn_after, handles lists of instructions |
4158 | efficiently. */ | |
23b2ce53 | 4159 | |
2f937369 | 4160 | static rtx |
6fb5fa3c | 4161 | emit_insn_after_1 (rtx first, rtx after, basic_block bb) |
23b2ce53 | 4162 | { |
2f937369 DM |
4163 | rtx last; |
4164 | rtx after_after; | |
6fb5fa3c DB |
4165 | if (!bb && !BARRIER_P (after)) |
4166 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4167 | |
6fb5fa3c | 4168 | if (bb) |
23b2ce53 | 4169 | { |
6fb5fa3c | 4170 | df_set_bb_dirty (bb); |
2f937369 | 4171 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4172 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4173 | { |
4174 | set_block_for_insn (last, bb); | |
4175 | df_insn_rescan (last); | |
4176 | } | |
4b4bf941 | 4177 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4178 | { |
4179 | set_block_for_insn (last, bb); | |
4180 | df_insn_rescan (last); | |
4181 | } | |
a813c111 SB |
4182 | if (BB_END (bb) == after) |
4183 | BB_END (bb) = last; | |
23b2ce53 RS |
4184 | } |
4185 | else | |
2f937369 DM |
4186 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4187 | continue; | |
4188 | ||
4189 | after_after = NEXT_INSN (after); | |
4190 | ||
4191 | NEXT_INSN (after) = first; | |
4192 | PREV_INSN (first) = after; | |
4193 | NEXT_INSN (last) = after_after; | |
4194 | if (after_after) | |
4195 | PREV_INSN (after_after) = last; | |
4196 | ||
5936d944 JH |
4197 | if (after == get_last_insn()) |
4198 | set_last_insn (last); | |
e855c69d | 4199 | |
2f937369 DM |
4200 | return last; |
4201 | } | |
4202 | ||
5f02387d NF |
4203 | static rtx |
4204 | emit_pattern_after_noloc (rtx x, rtx after, basic_block bb, | |
4205 | rtx (*make_raw)(rtx)) | |
2f937369 DM |
4206 | { |
4207 | rtx last = after; | |
4208 | ||
5b0264cb | 4209 | gcc_assert (after); |
2f937369 DM |
4210 | |
4211 | if (x == NULL_RTX) | |
4212 | return last; | |
4213 | ||
4214 | switch (GET_CODE (x)) | |
23b2ce53 | 4215 | { |
b5b8b0ac | 4216 | case DEBUG_INSN: |
2f937369 DM |
4217 | case INSN: |
4218 | case JUMP_INSN: | |
4219 | case CALL_INSN: | |
4220 | case CODE_LABEL: | |
4221 | case BARRIER: | |
4222 | case NOTE: | |
6fb5fa3c | 4223 | last = emit_insn_after_1 (x, after, bb); |
2f937369 DM |
4224 | break; |
4225 | ||
4226 | #ifdef ENABLE_RTL_CHECKING | |
4227 | case SEQUENCE: | |
5b0264cb | 4228 | gcc_unreachable (); |
2f937369 DM |
4229 | break; |
4230 | #endif | |
4231 | ||
4232 | default: | |
5f02387d | 4233 | last = (*make_raw) (x); |
6fb5fa3c | 4234 | add_insn_after (last, after, bb); |
2f937369 | 4235 | break; |
23b2ce53 RS |
4236 | } |
4237 | ||
2f937369 | 4238 | return last; |
23b2ce53 RS |
4239 | } |
4240 | ||
5f02387d NF |
4241 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4242 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
4243 | ||
4244 | rtx | |
4245 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) | |
4246 | { | |
4247 | return emit_pattern_after_noloc (x, after, bb, make_insn_raw); | |
4248 | } | |
4249 | ||
255680cf | 4250 | |
2f937369 | 4251 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4252 | and output it after the insn AFTER. */ |
4253 | ||
4254 | rtx | |
a7102479 | 4255 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4256 | { |
5f02387d | 4257 | return emit_pattern_after_noloc (x, after, NULL, make_jump_insn_raw); |
2f937369 DM |
4258 | } |
4259 | ||
4260 | /* Make an instruction with body X and code CALL_INSN | |
4261 | and output it after the instruction AFTER. */ | |
4262 | ||
4263 | rtx | |
a7102479 | 4264 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 | 4265 | { |
5f02387d | 4266 | return emit_pattern_after_noloc (x, after, NULL, make_call_insn_raw); |
23b2ce53 RS |
4267 | } |
4268 | ||
b5b8b0ac AO |
4269 | /* Make an instruction with body X and code CALL_INSN |
4270 | and output it after the instruction AFTER. */ | |
4271 | ||
4272 | rtx | |
4273 | emit_debug_insn_after_noloc (rtx x, rtx after) | |
4274 | { | |
5f02387d | 4275 | return emit_pattern_after_noloc (x, after, NULL, make_debug_insn_raw); |
b5b8b0ac AO |
4276 | } |
4277 | ||
23b2ce53 RS |
4278 | /* Make an insn of code BARRIER |
4279 | and output it after the insn AFTER. */ | |
4280 | ||
4281 | rtx | |
502b8322 | 4282 | emit_barrier_after (rtx after) |
23b2ce53 | 4283 | { |
b3694847 | 4284 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4285 | |
4286 | INSN_UID (insn) = cur_insn_uid++; | |
4287 | ||
6fb5fa3c | 4288 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4289 | return insn; |
4290 | } | |
4291 | ||
4292 | /* Emit the label LABEL after the insn AFTER. */ | |
4293 | ||
4294 | rtx | |
502b8322 | 4295 | emit_label_after (rtx label, rtx after) |
23b2ce53 RS |
4296 | { |
4297 | /* This can be called twice for the same label | |
4298 | as a result of the confusion that follows a syntax error! | |
4299 | So make it harmless. */ | |
4300 | if (INSN_UID (label) == 0) | |
4301 | { | |
4302 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4303 | add_insn_after (label, after, NULL); |
23b2ce53 RS |
4304 | } |
4305 | ||
4306 | return label; | |
4307 | } | |
4308 | ||
4309 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4310 | ||
4311 | rtx | |
a38e7aa5 | 4312 | emit_note_after (enum insn_note subtype, rtx after) |
23b2ce53 | 4313 | { |
b3694847 | 4314 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4315 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4316 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4317 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4318 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
6fb5fa3c | 4319 | add_insn_after (note, after, NULL); |
23b2ce53 RS |
4320 | return note; |
4321 | } | |
23b2ce53 | 4322 | \f |
e8110d6f NF |
4323 | /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC. |
4324 | MAKE_RAW indicates how to turn PATTERN into a real insn. */ | |
4325 | ||
4326 | static rtx | |
4327 | emit_pattern_after_setloc (rtx pattern, rtx after, int loc, | |
4328 | rtx (*make_raw) (rtx)) | |
0d682900 | 4329 | { |
e8110d6f | 4330 | rtx last = emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
0d682900 | 4331 | |
a7102479 | 4332 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4333 | return last; |
4334 | ||
2f937369 DM |
4335 | after = NEXT_INSN (after); |
4336 | while (1) | |
4337 | { | |
a7102479 | 4338 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4339 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4340 | if (after == last) |
4341 | break; | |
4342 | after = NEXT_INSN (after); | |
4343 | } | |
0d682900 JH |
4344 | return last; |
4345 | } | |
4346 | ||
e8110d6f NF |
4347 | /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN |
4348 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after | |
4349 | any DEBUG_INSNs. */ | |
4350 | ||
4351 | static rtx | |
4352 | emit_pattern_after (rtx pattern, rtx after, bool skip_debug_insns, | |
4353 | rtx (*make_raw) (rtx)) | |
a7102479 | 4354 | { |
b5b8b0ac AO |
4355 | rtx prev = after; |
4356 | ||
e8110d6f NF |
4357 | if (skip_debug_insns) |
4358 | while (DEBUG_INSN_P (prev)) | |
4359 | prev = PREV_INSN (prev); | |
b5b8b0ac AO |
4360 | |
4361 | if (INSN_P (prev)) | |
e8110d6f NF |
4362 | return emit_pattern_after_setloc (pattern, after, INSN_LOCATOR (prev), |
4363 | make_raw); | |
a7102479 | 4364 | else |
e8110d6f | 4365 | return emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
a7102479 JH |
4366 | } |
4367 | ||
e8110d6f | 4368 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to LOC. */ |
0d682900 | 4369 | rtx |
e8110d6f | 4370 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4371 | { |
e8110d6f NF |
4372 | return emit_pattern_after_setloc (pattern, after, loc, make_insn_raw); |
4373 | } | |
2f937369 | 4374 | |
e8110d6f NF |
4375 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4376 | rtx | |
4377 | emit_insn_after (rtx pattern, rtx after) | |
4378 | { | |
4379 | return emit_pattern_after (pattern, after, true, make_insn_raw); | |
4380 | } | |
dd3adcf8 | 4381 | |
e8110d6f NF |
4382 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to LOC. */ |
4383 | rtx | |
4384 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) | |
4385 | { | |
4386 | return emit_pattern_after_setloc (pattern, after, loc, make_jump_insn_raw); | |
0d682900 JH |
4387 | } |
4388 | ||
a7102479 JH |
4389 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4390 | rtx | |
4391 | emit_jump_insn_after (rtx pattern, rtx after) | |
4392 | { | |
e8110d6f | 4393 | return emit_pattern_after (pattern, after, true, make_jump_insn_raw); |
a7102479 JH |
4394 | } |
4395 | ||
e8110d6f | 4396 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to LOC. */ |
0d682900 | 4397 | rtx |
502b8322 | 4398 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4399 | { |
e8110d6f | 4400 | return emit_pattern_after_setloc (pattern, after, loc, make_call_insn_raw); |
0d682900 JH |
4401 | } |
4402 | ||
a7102479 JH |
4403 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4404 | rtx | |
4405 | emit_call_insn_after (rtx pattern, rtx after) | |
4406 | { | |
e8110d6f | 4407 | return emit_pattern_after (pattern, after, true, make_call_insn_raw); |
a7102479 JH |
4408 | } |
4409 | ||
e8110d6f | 4410 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to LOC. */ |
b5b8b0ac AO |
4411 | rtx |
4412 | emit_debug_insn_after_setloc (rtx pattern, rtx after, int loc) | |
4413 | { | |
e8110d6f | 4414 | return emit_pattern_after_setloc (pattern, after, loc, make_debug_insn_raw); |
b5b8b0ac AO |
4415 | } |
4416 | ||
4417 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ | |
4418 | rtx | |
4419 | emit_debug_insn_after (rtx pattern, rtx after) | |
4420 | { | |
e8110d6f | 4421 | return emit_pattern_after (pattern, after, false, make_debug_insn_raw); |
b5b8b0ac AO |
4422 | } |
4423 | ||
e8110d6f NF |
4424 | /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC. |
4425 | MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP | |
4426 | indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN, | |
4427 | CALL_INSN, etc. */ | |
4428 | ||
4429 | static rtx | |
4430 | emit_pattern_before_setloc (rtx pattern, rtx before, int loc, bool insnp, | |
4431 | rtx (*make_raw) (rtx)) | |
0d682900 JH |
4432 | { |
4433 | rtx first = PREV_INSN (before); | |
e8110d6f NF |
4434 | rtx last = emit_pattern_before_noloc (pattern, before, |
4435 | insnp ? before : NULL_RTX, | |
4436 | NULL, make_raw); | |
a7102479 JH |
4437 | |
4438 | if (pattern == NULL_RTX || !loc) | |
4439 | return last; | |
4440 | ||
26cb3993 JH |
4441 | if (!first) |
4442 | first = get_insns (); | |
4443 | else | |
4444 | first = NEXT_INSN (first); | |
a7102479 JH |
4445 | while (1) |
4446 | { | |
4447 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4448 | INSN_LOCATOR (first) = loc; | |
4449 | if (first == last) | |
4450 | break; | |
4451 | first = NEXT_INSN (first); | |
4452 | } | |
4453 | return last; | |
4454 | } | |
4455 | ||
e8110d6f NF |
4456 | /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN |
4457 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert | |
4458 | before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an | |
4459 | INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */ | |
4460 | ||
4461 | static rtx | |
4462 | emit_pattern_before (rtx pattern, rtx before, bool skip_debug_insns, | |
4463 | bool insnp, rtx (*make_raw) (rtx)) | |
a7102479 | 4464 | { |
b5b8b0ac AO |
4465 | rtx next = before; |
4466 | ||
e8110d6f NF |
4467 | if (skip_debug_insns) |
4468 | while (DEBUG_INSN_P (next)) | |
4469 | next = PREV_INSN (next); | |
b5b8b0ac AO |
4470 | |
4471 | if (INSN_P (next)) | |
e8110d6f NF |
4472 | return emit_pattern_before_setloc (pattern, before, INSN_LOCATOR (next), |
4473 | insnp, make_raw); | |
a7102479 | 4474 | else |
e8110d6f NF |
4475 | return emit_pattern_before_noloc (pattern, before, |
4476 | insnp ? before : NULL_RTX, | |
4477 | NULL, make_raw); | |
a7102479 JH |
4478 | } |
4479 | ||
e8110d6f | 4480 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to LOC. */ |
a7102479 | 4481 | rtx |
e8110d6f | 4482 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
a7102479 | 4483 | { |
e8110d6f NF |
4484 | return emit_pattern_before_setloc (pattern, before, loc, true, |
4485 | make_insn_raw); | |
4486 | } | |
a7102479 | 4487 | |
e8110d6f NF |
4488 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ |
4489 | rtx | |
4490 | emit_insn_before (rtx pattern, rtx before) | |
4491 | { | |
4492 | return emit_pattern_before (pattern, before, true, true, make_insn_raw); | |
4493 | } | |
a7102479 | 4494 | |
e8110d6f NF |
4495 | /* like emit_insn_before_noloc, but set INSN_LOCATOR according to LOC. */ |
4496 | rtx | |
4497 | emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4498 | { | |
4499 | return emit_pattern_before_setloc (pattern, before, loc, false, | |
4500 | make_jump_insn_raw); | |
a7102479 JH |
4501 | } |
4502 | ||
4503 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4504 | rtx | |
4505 | emit_jump_insn_before (rtx pattern, rtx before) | |
4506 | { | |
e8110d6f NF |
4507 | return emit_pattern_before (pattern, before, true, false, |
4508 | make_jump_insn_raw); | |
a7102479 JH |
4509 | } |
4510 | ||
e8110d6f | 4511 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to LOC. */ |
a7102479 JH |
4512 | rtx |
4513 | emit_call_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4514 | { | |
e8110d6f NF |
4515 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4516 | make_call_insn_raw); | |
0d682900 | 4517 | } |
a7102479 | 4518 | |
e8110d6f NF |
4519 | /* Like emit_call_insn_before_noloc, |
4520 | but set insn_locator according to BEFORE. */ | |
a7102479 JH |
4521 | rtx |
4522 | emit_call_insn_before (rtx pattern, rtx before) | |
4523 | { | |
e8110d6f NF |
4524 | return emit_pattern_before (pattern, before, true, false, |
4525 | make_call_insn_raw); | |
a7102479 | 4526 | } |
b5b8b0ac | 4527 | |
e8110d6f | 4528 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to LOC. */ |
b5b8b0ac AO |
4529 | rtx |
4530 | emit_debug_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4531 | { | |
e8110d6f NF |
4532 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4533 | make_debug_insn_raw); | |
b5b8b0ac AO |
4534 | } |
4535 | ||
e8110d6f NF |
4536 | /* Like emit_debug_insn_before_noloc, |
4537 | but set insn_locator according to BEFORE. */ | |
b5b8b0ac AO |
4538 | rtx |
4539 | emit_debug_insn_before (rtx pattern, rtx before) | |
4540 | { | |
e8110d6f NF |
4541 | return emit_pattern_before (pattern, before, false, false, |
4542 | make_debug_insn_raw); | |
b5b8b0ac | 4543 | } |
0d682900 | 4544 | \f |
2f937369 DM |
4545 | /* Take X and emit it at the end of the doubly-linked |
4546 | INSN list. | |
23b2ce53 RS |
4547 | |
4548 | Returns the last insn emitted. */ | |
4549 | ||
4550 | rtx | |
502b8322 | 4551 | emit_insn (rtx x) |
23b2ce53 | 4552 | { |
5936d944 | 4553 | rtx last = get_last_insn(); |
2f937369 | 4554 | rtx insn; |
23b2ce53 | 4555 | |
2f937369 DM |
4556 | if (x == NULL_RTX) |
4557 | return last; | |
23b2ce53 | 4558 | |
2f937369 DM |
4559 | switch (GET_CODE (x)) |
4560 | { | |
b5b8b0ac | 4561 | case DEBUG_INSN: |
2f937369 DM |
4562 | case INSN: |
4563 | case JUMP_INSN: | |
4564 | case CALL_INSN: | |
4565 | case CODE_LABEL: | |
4566 | case BARRIER: | |
4567 | case NOTE: | |
4568 | insn = x; | |
4569 | while (insn) | |
23b2ce53 | 4570 | { |
2f937369 | 4571 | rtx next = NEXT_INSN (insn); |
23b2ce53 | 4572 | add_insn (insn); |
2f937369 DM |
4573 | last = insn; |
4574 | insn = next; | |
23b2ce53 | 4575 | } |
2f937369 | 4576 | break; |
23b2ce53 | 4577 | |
2f937369 DM |
4578 | #ifdef ENABLE_RTL_CHECKING |
4579 | case SEQUENCE: | |
5b0264cb | 4580 | gcc_unreachable (); |
2f937369 DM |
4581 | break; |
4582 | #endif | |
23b2ce53 | 4583 | |
2f937369 DM |
4584 | default: |
4585 | last = make_insn_raw (x); | |
4586 | add_insn (last); | |
4587 | break; | |
23b2ce53 RS |
4588 | } |
4589 | ||
4590 | return last; | |
4591 | } | |
4592 | ||
b5b8b0ac AO |
4593 | /* Make an insn of code DEBUG_INSN with pattern X |
4594 | and add it to the end of the doubly-linked list. */ | |
4595 | ||
4596 | rtx | |
4597 | emit_debug_insn (rtx x) | |
4598 | { | |
5936d944 | 4599 | rtx last = get_last_insn(); |
b5b8b0ac AO |
4600 | rtx insn; |
4601 | ||
4602 | if (x == NULL_RTX) | |
4603 | return last; | |
4604 | ||
4605 | switch (GET_CODE (x)) | |
4606 | { | |
4607 | case DEBUG_INSN: | |
4608 | case INSN: | |
4609 | case JUMP_INSN: | |
4610 | case CALL_INSN: | |
4611 | case CODE_LABEL: | |
4612 | case BARRIER: | |
4613 | case NOTE: | |
4614 | insn = x; | |
4615 | while (insn) | |
4616 | { | |
4617 | rtx next = NEXT_INSN (insn); | |
4618 | add_insn (insn); | |
4619 | last = insn; | |
4620 | insn = next; | |
4621 | } | |
4622 | break; | |
4623 | ||
4624 | #ifdef ENABLE_RTL_CHECKING | |
4625 | case SEQUENCE: | |
4626 | gcc_unreachable (); | |
4627 | break; | |
4628 | #endif | |
4629 | ||
4630 | default: | |
4631 | last = make_debug_insn_raw (x); | |
4632 | add_insn (last); | |
4633 | break; | |
4634 | } | |
4635 | ||
4636 | return last; | |
4637 | } | |
4638 | ||
2f937369 DM |
4639 | /* Make an insn of code JUMP_INSN with pattern X |
4640 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4641 | |
4642 | rtx | |
502b8322 | 4643 | emit_jump_insn (rtx x) |
23b2ce53 | 4644 | { |
d950dee3 | 4645 | rtx last = NULL_RTX, insn; |
23b2ce53 | 4646 | |
2f937369 | 4647 | switch (GET_CODE (x)) |
23b2ce53 | 4648 | { |
b5b8b0ac | 4649 | case DEBUG_INSN: |
2f937369 DM |
4650 | case INSN: |
4651 | case JUMP_INSN: | |
4652 | case CALL_INSN: | |
4653 | case CODE_LABEL: | |
4654 | case BARRIER: | |
4655 | case NOTE: | |
4656 | insn = x; | |
4657 | while (insn) | |
4658 | { | |
4659 | rtx next = NEXT_INSN (insn); | |
4660 | add_insn (insn); | |
4661 | last = insn; | |
4662 | insn = next; | |
4663 | } | |
4664 | break; | |
e0a5c5eb | 4665 | |
2f937369 DM |
4666 | #ifdef ENABLE_RTL_CHECKING |
4667 | case SEQUENCE: | |
5b0264cb | 4668 | gcc_unreachable (); |
2f937369 DM |
4669 | break; |
4670 | #endif | |
e0a5c5eb | 4671 | |
2f937369 DM |
4672 | default: |
4673 | last = make_jump_insn_raw (x); | |
4674 | add_insn (last); | |
4675 | break; | |
3c030e88 | 4676 | } |
e0a5c5eb RS |
4677 | |
4678 | return last; | |
4679 | } | |
4680 | ||
2f937369 | 4681 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
4682 | and add it to the end of the doubly-linked list. */ |
4683 | ||
4684 | rtx | |
502b8322 | 4685 | emit_call_insn (rtx x) |
23b2ce53 | 4686 | { |
2f937369 DM |
4687 | rtx insn; |
4688 | ||
4689 | switch (GET_CODE (x)) | |
23b2ce53 | 4690 | { |
b5b8b0ac | 4691 | case DEBUG_INSN: |
2f937369 DM |
4692 | case INSN: |
4693 | case JUMP_INSN: | |
4694 | case CALL_INSN: | |
4695 | case CODE_LABEL: | |
4696 | case BARRIER: | |
4697 | case NOTE: | |
4698 | insn = emit_insn (x); | |
4699 | break; | |
23b2ce53 | 4700 | |
2f937369 DM |
4701 | #ifdef ENABLE_RTL_CHECKING |
4702 | case SEQUENCE: | |
5b0264cb | 4703 | gcc_unreachable (); |
2f937369 DM |
4704 | break; |
4705 | #endif | |
23b2ce53 | 4706 | |
2f937369 DM |
4707 | default: |
4708 | insn = make_call_insn_raw (x); | |
23b2ce53 | 4709 | add_insn (insn); |
2f937369 | 4710 | break; |
23b2ce53 | 4711 | } |
2f937369 DM |
4712 | |
4713 | return insn; | |
23b2ce53 RS |
4714 | } |
4715 | ||
4716 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4717 | ||
4718 | rtx | |
502b8322 | 4719 | emit_label (rtx label) |
23b2ce53 RS |
4720 | { |
4721 | /* This can be called twice for the same label | |
4722 | as a result of the confusion that follows a syntax error! | |
4723 | So make it harmless. */ | |
4724 | if (INSN_UID (label) == 0) | |
4725 | { | |
4726 | INSN_UID (label) = cur_insn_uid++; | |
4727 | add_insn (label); | |
4728 | } | |
4729 | return label; | |
4730 | } | |
4731 | ||
4732 | /* Make an insn of code BARRIER | |
4733 | and add it to the end of the doubly-linked list. */ | |
4734 | ||
4735 | rtx | |
502b8322 | 4736 | emit_barrier (void) |
23b2ce53 | 4737 | { |
b3694847 | 4738 | rtx barrier = rtx_alloc (BARRIER); |
23b2ce53 RS |
4739 | INSN_UID (barrier) = cur_insn_uid++; |
4740 | add_insn (barrier); | |
4741 | return barrier; | |
4742 | } | |
4743 | ||
5f2fc772 | 4744 | /* Emit a copy of note ORIG. */ |
502b8322 | 4745 | |
5f2fc772 NS |
4746 | rtx |
4747 | emit_note_copy (rtx orig) | |
4748 | { | |
4749 | rtx note; | |
b8698a0f | 4750 | |
5f2fc772 | 4751 | note = rtx_alloc (NOTE); |
b8698a0f | 4752 | |
5f2fc772 NS |
4753 | INSN_UID (note) = cur_insn_uid++; |
4754 | NOTE_DATA (note) = NOTE_DATA (orig); | |
a38e7aa5 | 4755 | NOTE_KIND (note) = NOTE_KIND (orig); |
5f2fc772 NS |
4756 | BLOCK_FOR_INSN (note) = NULL; |
4757 | add_insn (note); | |
b8698a0f | 4758 | |
2e040219 | 4759 | return note; |
23b2ce53 RS |
4760 | } |
4761 | ||
2e040219 NS |
4762 | /* Make an insn of code NOTE or type NOTE_NO |
4763 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4764 | |
4765 | rtx | |
a38e7aa5 | 4766 | emit_note (enum insn_note kind) |
23b2ce53 | 4767 | { |
b3694847 | 4768 | rtx note; |
23b2ce53 | 4769 | |
23b2ce53 RS |
4770 | note = rtx_alloc (NOTE); |
4771 | INSN_UID (note) = cur_insn_uid++; | |
a38e7aa5 | 4772 | NOTE_KIND (note) = kind; |
dd107e66 | 4773 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ba4f7968 | 4774 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
4775 | add_insn (note); |
4776 | return note; | |
4777 | } | |
4778 | ||
c41c1387 RS |
4779 | /* Emit a clobber of lvalue X. */ |
4780 | ||
4781 | rtx | |
4782 | emit_clobber (rtx x) | |
4783 | { | |
4784 | /* CONCATs should not appear in the insn stream. */ | |
4785 | if (GET_CODE (x) == CONCAT) | |
4786 | { | |
4787 | emit_clobber (XEXP (x, 0)); | |
4788 | return emit_clobber (XEXP (x, 1)); | |
4789 | } | |
4790 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
4791 | } | |
4792 | ||
4793 | /* Return a sequence of insns to clobber lvalue X. */ | |
4794 | ||
4795 | rtx | |
4796 | gen_clobber (rtx x) | |
4797 | { | |
4798 | rtx seq; | |
4799 | ||
4800 | start_sequence (); | |
4801 | emit_clobber (x); | |
4802 | seq = get_insns (); | |
4803 | end_sequence (); | |
4804 | return seq; | |
4805 | } | |
4806 | ||
4807 | /* Emit a use of rvalue X. */ | |
4808 | ||
4809 | rtx | |
4810 | emit_use (rtx x) | |
4811 | { | |
4812 | /* CONCATs should not appear in the insn stream. */ | |
4813 | if (GET_CODE (x) == CONCAT) | |
4814 | { | |
4815 | emit_use (XEXP (x, 0)); | |
4816 | return emit_use (XEXP (x, 1)); | |
4817 | } | |
4818 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
4819 | } | |
4820 | ||
4821 | /* Return a sequence of insns to use rvalue X. */ | |
4822 | ||
4823 | rtx | |
4824 | gen_use (rtx x) | |
4825 | { | |
4826 | rtx seq; | |
4827 | ||
4828 | start_sequence (); | |
4829 | emit_use (x); | |
4830 | seq = get_insns (); | |
4831 | end_sequence (); | |
4832 | return seq; | |
4833 | } | |
4834 | ||
23b2ce53 | 4835 | /* Cause next statement to emit a line note even if the line number |
0cea056b | 4836 | has not changed. */ |
23b2ce53 RS |
4837 | |
4838 | void | |
502b8322 | 4839 | force_next_line_note (void) |
23b2ce53 | 4840 | { |
6773e15f | 4841 | last_location = -1; |
23b2ce53 | 4842 | } |
87b47c85 AM |
4843 | |
4844 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
30f7a378 | 4845 | note of this type already exists, remove it first. */ |
87b47c85 | 4846 | |
3d238248 | 4847 | rtx |
502b8322 | 4848 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
4849 | { |
4850 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
4851 | ||
52488da1 JW |
4852 | switch (kind) |
4853 | { | |
4854 | case REG_EQUAL: | |
4855 | case REG_EQUIV: | |
4856 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
4857 | has multiple sets (some callers assume single_set | |
4858 | means the insn only has one set, when in fact it | |
4859 | means the insn only has one * useful * set). */ | |
4860 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
4861 | { | |
5b0264cb | 4862 | gcc_assert (!note); |
52488da1 JW |
4863 | return NULL_RTX; |
4864 | } | |
4865 | ||
4866 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
4867 | It serves no useful purpose and breaks eliminate_regs. */ | |
4868 | if (GET_CODE (datum) == ASM_OPERANDS) | |
4869 | return NULL_RTX; | |
6fb5fa3c DB |
4870 | |
4871 | if (note) | |
4872 | { | |
4873 | XEXP (note, 0) = datum; | |
4874 | df_notes_rescan (insn); | |
4875 | return note; | |
4876 | } | |
52488da1 JW |
4877 | break; |
4878 | ||
4879 | default: | |
6fb5fa3c DB |
4880 | if (note) |
4881 | { | |
4882 | XEXP (note, 0) = datum; | |
4883 | return note; | |
4884 | } | |
52488da1 JW |
4885 | break; |
4886 | } | |
3d238248 | 4887 | |
65c5f2a6 | 4888 | add_reg_note (insn, kind, datum); |
6fb5fa3c DB |
4889 | |
4890 | switch (kind) | |
3d238248 | 4891 | { |
6fb5fa3c DB |
4892 | case REG_EQUAL: |
4893 | case REG_EQUIV: | |
4894 | df_notes_rescan (insn); | |
4895 | break; | |
4896 | default: | |
4897 | break; | |
3d238248 | 4898 | } |
87b47c85 | 4899 | |
3d238248 | 4900 | return REG_NOTES (insn); |
87b47c85 | 4901 | } |
23b2ce53 RS |
4902 | \f |
4903 | /* Return an indication of which type of insn should have X as a body. | |
4904 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
4905 | ||
d78db459 | 4906 | static enum rtx_code |
502b8322 | 4907 | classify_insn (rtx x) |
23b2ce53 | 4908 | { |
4b4bf941 | 4909 | if (LABEL_P (x)) |
23b2ce53 RS |
4910 | return CODE_LABEL; |
4911 | if (GET_CODE (x) == CALL) | |
4912 | return CALL_INSN; | |
4913 | if (GET_CODE (x) == RETURN) | |
4914 | return JUMP_INSN; | |
4915 | if (GET_CODE (x) == SET) | |
4916 | { | |
4917 | if (SET_DEST (x) == pc_rtx) | |
4918 | return JUMP_INSN; | |
4919 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
4920 | return CALL_INSN; | |
4921 | else | |
4922 | return INSN; | |
4923 | } | |
4924 | if (GET_CODE (x) == PARALLEL) | |
4925 | { | |
b3694847 | 4926 | int j; |
23b2ce53 RS |
4927 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
4928 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
4929 | return CALL_INSN; | |
4930 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4931 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
4932 | return JUMP_INSN; | |
4933 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4934 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
4935 | return CALL_INSN; | |
4936 | } | |
4937 | return INSN; | |
4938 | } | |
4939 | ||
4940 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
4941 | If X is a label, it is simply added into the insn chain. */ | |
4942 | ||
4943 | rtx | |
502b8322 | 4944 | emit (rtx x) |
23b2ce53 RS |
4945 | { |
4946 | enum rtx_code code = classify_insn (x); | |
4947 | ||
5b0264cb | 4948 | switch (code) |
23b2ce53 | 4949 | { |
5b0264cb NS |
4950 | case CODE_LABEL: |
4951 | return emit_label (x); | |
4952 | case INSN: | |
4953 | return emit_insn (x); | |
4954 | case JUMP_INSN: | |
4955 | { | |
4956 | rtx insn = emit_jump_insn (x); | |
4957 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) | |
4958 | return emit_barrier (); | |
4959 | return insn; | |
4960 | } | |
4961 | case CALL_INSN: | |
4962 | return emit_call_insn (x); | |
b5b8b0ac AO |
4963 | case DEBUG_INSN: |
4964 | return emit_debug_insn (x); | |
5b0264cb NS |
4965 | default: |
4966 | gcc_unreachable (); | |
23b2ce53 | 4967 | } |
23b2ce53 RS |
4968 | } |
4969 | \f | |
e2500fed | 4970 | /* Space for free sequence stack entries. */ |
1431042e | 4971 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 4972 | |
4dfa0342 RH |
4973 | /* Begin emitting insns to a sequence. If this sequence will contain |
4974 | something that might cause the compiler to pop arguments to function | |
4975 | calls (because those pops have previously been deferred; see | |
4976 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
4977 | before calling this function. That will ensure that the deferred | |
4978 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
4979 | |
4980 | void | |
502b8322 | 4981 | start_sequence (void) |
23b2ce53 RS |
4982 | { |
4983 | struct sequence_stack *tem; | |
4984 | ||
e2500fed GK |
4985 | if (free_sequence_stack != NULL) |
4986 | { | |
4987 | tem = free_sequence_stack; | |
4988 | free_sequence_stack = tem->next; | |
4989 | } | |
4990 | else | |
a9429e29 | 4991 | tem = ggc_alloc_sequence_stack (); |
23b2ce53 | 4992 | |
49ad7cfa | 4993 | tem->next = seq_stack; |
5936d944 JH |
4994 | tem->first = get_insns (); |
4995 | tem->last = get_last_insn (); | |
23b2ce53 | 4996 | |
49ad7cfa | 4997 | seq_stack = tem; |
23b2ce53 | 4998 | |
5936d944 JH |
4999 | set_first_insn (0); |
5000 | set_last_insn (0); | |
23b2ce53 RS |
5001 | } |
5002 | ||
5c7a310f MM |
5003 | /* Set up the insn chain starting with FIRST as the current sequence, |
5004 | saving the previously current one. See the documentation for | |
5005 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5006 | |
5007 | void | |
502b8322 | 5008 | push_to_sequence (rtx first) |
23b2ce53 RS |
5009 | { |
5010 | rtx last; | |
5011 | ||
5012 | start_sequence (); | |
5013 | ||
5014 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
5015 | ||
5936d944 JH |
5016 | set_first_insn (first); |
5017 | set_last_insn (last); | |
23b2ce53 RS |
5018 | } |
5019 | ||
bb27eeda SE |
5020 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5021 | looping through the list. */ | |
5022 | ||
5023 | void | |
5024 | push_to_sequence2 (rtx first, rtx last) | |
5025 | { | |
5026 | start_sequence (); | |
5027 | ||
5936d944 JH |
5028 | set_first_insn (first); |
5029 | set_last_insn (last); | |
bb27eeda SE |
5030 | } |
5031 | ||
f15ae3a1 TW |
5032 | /* Set up the outer-level insn chain |
5033 | as the current sequence, saving the previously current one. */ | |
5034 | ||
5035 | void | |
502b8322 | 5036 | push_topmost_sequence (void) |
f15ae3a1 | 5037 | { |
aefdd5ab | 5038 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
5039 | |
5040 | start_sequence (); | |
5041 | ||
49ad7cfa | 5042 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
5043 | top = stack; |
5044 | ||
5936d944 JH |
5045 | set_first_insn (top->first); |
5046 | set_last_insn (top->last); | |
f15ae3a1 TW |
5047 | } |
5048 | ||
5049 | /* After emitting to the outer-level insn chain, update the outer-level | |
5050 | insn chain, and restore the previous saved state. */ | |
5051 | ||
5052 | void | |
502b8322 | 5053 | pop_topmost_sequence (void) |
f15ae3a1 | 5054 | { |
aefdd5ab | 5055 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 5056 | |
49ad7cfa | 5057 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
5058 | top = stack; |
5059 | ||
5936d944 JH |
5060 | top->first = get_insns (); |
5061 | top->last = get_last_insn (); | |
f15ae3a1 TW |
5062 | |
5063 | end_sequence (); | |
5064 | } | |
5065 | ||
23b2ce53 RS |
5066 | /* After emitting to a sequence, restore previous saved state. |
5067 | ||
5c7a310f | 5068 | To get the contents of the sequence just made, you must call |
2f937369 | 5069 | `get_insns' *before* calling here. |
5c7a310f MM |
5070 | |
5071 | If the compiler might have deferred popping arguments while | |
5072 | generating this sequence, and this sequence will not be immediately | |
5073 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5074 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5075 | pops are inserted into this sequence, and not into some random |
5076 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5077 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5078 | |
5079 | void | |
502b8322 | 5080 | end_sequence (void) |
23b2ce53 | 5081 | { |
49ad7cfa | 5082 | struct sequence_stack *tem = seq_stack; |
23b2ce53 | 5083 | |
5936d944 JH |
5084 | set_first_insn (tem->first); |
5085 | set_last_insn (tem->last); | |
49ad7cfa | 5086 | seq_stack = tem->next; |
23b2ce53 | 5087 | |
e2500fed GK |
5088 | memset (tem, 0, sizeof (*tem)); |
5089 | tem->next = free_sequence_stack; | |
5090 | free_sequence_stack = tem; | |
23b2ce53 RS |
5091 | } |
5092 | ||
5093 | /* Return 1 if currently emitting into a sequence. */ | |
5094 | ||
5095 | int | |
502b8322 | 5096 | in_sequence_p (void) |
23b2ce53 | 5097 | { |
49ad7cfa | 5098 | return seq_stack != 0; |
23b2ce53 | 5099 | } |
23b2ce53 | 5100 | \f |
59ec66dc MM |
5101 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5102 | ||
2bbdec73 | 5103 | static void |
bd60bab2 | 5104 | init_virtual_regs (void) |
59ec66dc | 5105 | { |
bd60bab2 JH |
5106 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5107 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5108 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5109 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5110 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
32990d5b JJ |
5111 | regno_reg_rtx[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM] |
5112 | = virtual_preferred_stack_boundary_rtx; | |
49ad7cfa BS |
5113 | } |
5114 | ||
da43a810 BS |
5115 | \f |
5116 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5117 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5118 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5119 | static int copy_insn_n_scratches; | |
5120 | ||
5121 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5122 | copied an ASM_OPERANDS. | |
5123 | In that case, it is the original input-operand vector. */ | |
5124 | static rtvec orig_asm_operands_vector; | |
5125 | ||
5126 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5127 | copied an ASM_OPERANDS. | |
5128 | In that case, it is the copied input-operand vector. */ | |
5129 | static rtvec copy_asm_operands_vector; | |
5130 | ||
5131 | /* Likewise for the constraints vector. */ | |
5132 | static rtvec orig_asm_constraints_vector; | |
5133 | static rtvec copy_asm_constraints_vector; | |
5134 | ||
5135 | /* Recursively create a new copy of an rtx for copy_insn. | |
5136 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5137 | ASM_OPERANDs properly. | |
5138 | Normally, this function is not used directly; use copy_insn as front end. | |
5139 | However, you could first copy an insn pattern with copy_insn and then use | |
5140 | this function afterwards to properly copy any REG_NOTEs containing | |
5141 | SCRATCHes. */ | |
5142 | ||
5143 | rtx | |
502b8322 | 5144 | copy_insn_1 (rtx orig) |
da43a810 | 5145 | { |
b3694847 SS |
5146 | rtx copy; |
5147 | int i, j; | |
5148 | RTX_CODE code; | |
5149 | const char *format_ptr; | |
da43a810 | 5150 | |
cd9c1ca8 RH |
5151 | if (orig == NULL) |
5152 | return NULL; | |
5153 | ||
da43a810 BS |
5154 | code = GET_CODE (orig); |
5155 | ||
5156 | switch (code) | |
5157 | { | |
5158 | case REG: | |
da43a810 BS |
5159 | case CONST_INT: |
5160 | case CONST_DOUBLE: | |
091a3ac7 | 5161 | case CONST_FIXED: |
69ef87e2 | 5162 | case CONST_VECTOR: |
da43a810 BS |
5163 | case SYMBOL_REF: |
5164 | case CODE_LABEL: | |
5165 | case PC: | |
5166 | case CC0: | |
da43a810 | 5167 | return orig; |
3e89ed8d JH |
5168 | case CLOBBER: |
5169 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER) | |
5170 | return orig; | |
5171 | break; | |
da43a810 BS |
5172 | |
5173 | case SCRATCH: | |
5174 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5175 | if (copy_insn_scratch_in[i] == orig) | |
5176 | return copy_insn_scratch_out[i]; | |
5177 | break; | |
5178 | ||
5179 | case CONST: | |
6fb5fa3c | 5180 | if (shared_const_p (orig)) |
da43a810 BS |
5181 | return orig; |
5182 | break; | |
750c9258 | 5183 | |
da43a810 BS |
5184 | /* A MEM with a constant address is not sharable. The problem is that |
5185 | the constant address may need to be reloaded. If the mem is shared, | |
5186 | then reloading one copy of this mem will cause all copies to appear | |
5187 | to have been reloaded. */ | |
5188 | ||
5189 | default: | |
5190 | break; | |
5191 | } | |
5192 | ||
aacd3885 RS |
5193 | /* Copy the various flags, fields, and other information. We assume |
5194 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5195 | not be copied. That is the sensible default behavior, and forces |
5196 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5197 | copy = shallow_copy_rtx (orig); |
da43a810 BS |
5198 | |
5199 | /* We do not copy the USED flag, which is used as a mark bit during | |
5200 | walks over the RTL. */ | |
2adc7f12 | 5201 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5202 | |
5203 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
ec8e098d | 5204 | if (INSN_P (orig)) |
da43a810 | 5205 | { |
2adc7f12 JJ |
5206 | RTX_FLAG (copy, jump) = 0; |
5207 | RTX_FLAG (copy, call) = 0; | |
5208 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5209 | } |
750c9258 | 5210 | |
da43a810 BS |
5211 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5212 | ||
5213 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5214 | switch (*format_ptr++) |
5215 | { | |
5216 | case 'e': | |
5217 | if (XEXP (orig, i) != NULL) | |
5218 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5219 | break; | |
da43a810 | 5220 | |
aacd3885 RS |
5221 | case 'E': |
5222 | case 'V': | |
5223 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5224 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5225 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5226 | XVEC (copy, i) = copy_asm_operands_vector; | |
5227 | else if (XVEC (orig, i) != NULL) | |
5228 | { | |
5229 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5230 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5231 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5232 | } | |
5233 | break; | |
da43a810 | 5234 | |
aacd3885 RS |
5235 | case 't': |
5236 | case 'w': | |
5237 | case 'i': | |
5238 | case 's': | |
5239 | case 'S': | |
5240 | case 'u': | |
5241 | case '0': | |
5242 | /* These are left unchanged. */ | |
5243 | break; | |
da43a810 | 5244 | |
aacd3885 RS |
5245 | default: |
5246 | gcc_unreachable (); | |
5247 | } | |
da43a810 BS |
5248 | |
5249 | if (code == SCRATCH) | |
5250 | { | |
5251 | i = copy_insn_n_scratches++; | |
5b0264cb | 5252 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5253 | copy_insn_scratch_in[i] = orig; |
5254 | copy_insn_scratch_out[i] = copy; | |
5255 | } | |
5256 | else if (code == ASM_OPERANDS) | |
5257 | { | |
6462bb43 AO |
5258 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5259 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5260 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5261 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5262 | } |
5263 | ||
5264 | return copy; | |
5265 | } | |
5266 | ||
5267 | /* Create a new copy of an rtx. | |
5268 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5269 | ASM_OPERANDs properly. | |
5270 | INSN doesn't really have to be a full INSN; it could be just the | |
5271 | pattern. */ | |
5272 | rtx | |
502b8322 | 5273 | copy_insn (rtx insn) |
da43a810 BS |
5274 | { |
5275 | copy_insn_n_scratches = 0; | |
5276 | orig_asm_operands_vector = 0; | |
5277 | orig_asm_constraints_vector = 0; | |
5278 | copy_asm_operands_vector = 0; | |
5279 | copy_asm_constraints_vector = 0; | |
5280 | return copy_insn_1 (insn); | |
5281 | } | |
59ec66dc | 5282 | |
23b2ce53 RS |
5283 | /* Initialize data structures and variables in this file |
5284 | before generating rtl for each function. */ | |
5285 | ||
5286 | void | |
502b8322 | 5287 | init_emit (void) |
23b2ce53 | 5288 | { |
5936d944 JH |
5289 | set_first_insn (NULL); |
5290 | set_last_insn (NULL); | |
b5b8b0ac AO |
5291 | if (MIN_NONDEBUG_INSN_UID) |
5292 | cur_insn_uid = MIN_NONDEBUG_INSN_UID; | |
5293 | else | |
5294 | cur_insn_uid = 1; | |
5295 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5296 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
6773e15f | 5297 | last_location = UNKNOWN_LOCATION; |
23b2ce53 | 5298 | first_label_num = label_num; |
49ad7cfa | 5299 | seq_stack = NULL; |
23b2ce53 | 5300 | |
23b2ce53 RS |
5301 | /* Init the tables that describe all the pseudo regs. */ |
5302 | ||
3e029763 | 5303 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5304 | |
3e029763 | 5305 | crtl->emit.regno_pointer_align |
1b4572a8 | 5306 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5307 | |
a9429e29 | 5308 | regno_reg_rtx = ggc_alloc_vec_rtx (crtl->emit.regno_pointer_align_length); |
0d4903b8 | 5309 | |
e50126e8 | 5310 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 | 5311 | memcpy (regno_reg_rtx, |
5fb0e246 | 5312 | initial_regno_reg_rtx, |
6cde4876 | 5313 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
e50126e8 | 5314 | |
23b2ce53 | 5315 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5316 | init_virtual_regs (); |
740ab4a2 RK |
5317 | |
5318 | /* Indicate that the virtual registers and stack locations are | |
5319 | all pointers. */ | |
3502dc9c JDA |
5320 | REG_POINTER (stack_pointer_rtx) = 1; |
5321 | REG_POINTER (frame_pointer_rtx) = 1; | |
5322 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5323 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5324 | |
3502dc9c JDA |
5325 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5326 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5327 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5328 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5329 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5330 | |
86fe05e0 | 5331 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5332 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5333 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5334 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5335 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5336 | ||
5337 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5338 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5339 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5340 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5341 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5342 | #endif |
5343 | ||
5e82e7bd JVA |
5344 | #ifdef INIT_EXPANDERS |
5345 | INIT_EXPANDERS; | |
5346 | #endif | |
23b2ce53 RS |
5347 | } |
5348 | ||
a73b091d | 5349 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
69ef87e2 AH |
5350 | |
5351 | static rtx | |
a73b091d | 5352 | gen_const_vector (enum machine_mode mode, int constant) |
69ef87e2 AH |
5353 | { |
5354 | rtx tem; | |
5355 | rtvec v; | |
5356 | int units, i; | |
5357 | enum machine_mode inner; | |
5358 | ||
5359 | units = GET_MODE_NUNITS (mode); | |
5360 | inner = GET_MODE_INNER (mode); | |
5361 | ||
15ed7b52 JG |
5362 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5363 | ||
69ef87e2 AH |
5364 | v = rtvec_alloc (units); |
5365 | ||
a73b091d JW |
5366 | /* We need to call this function after we set the scalar const_tiny_rtx |
5367 | entries. */ | |
5368 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
69ef87e2 AH |
5369 | |
5370 | for (i = 0; i < units; ++i) | |
a73b091d | 5371 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
69ef87e2 | 5372 | |
a06e3c40 | 5373 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5374 | return tem; |
5375 | } | |
5376 | ||
a06e3c40 | 5377 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5378 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5379 | rtx |
502b8322 | 5380 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
a06e3c40 | 5381 | { |
a73b091d JW |
5382 | enum machine_mode inner = GET_MODE_INNER (mode); |
5383 | int nunits = GET_MODE_NUNITS (mode); | |
5384 | rtx x; | |
a06e3c40 R |
5385 | int i; |
5386 | ||
a73b091d JW |
5387 | /* Check to see if all of the elements have the same value. */ |
5388 | x = RTVEC_ELT (v, nunits - 1); | |
5389 | for (i = nunits - 2; i >= 0; i--) | |
5390 | if (RTVEC_ELT (v, i) != x) | |
5391 | break; | |
5392 | ||
5393 | /* If the values are all the same, check to see if we can use one of the | |
5394 | standard constant vectors. */ | |
5395 | if (i == -1) | |
5396 | { | |
5397 | if (x == CONST0_RTX (inner)) | |
5398 | return CONST0_RTX (mode); | |
5399 | else if (x == CONST1_RTX (inner)) | |
5400 | return CONST1_RTX (mode); | |
5401 | } | |
5402 | ||
5403 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5404 | } |
5405 | ||
b5deb7b6 SL |
5406 | /* Initialise global register information required by all functions. */ |
5407 | ||
5408 | void | |
5409 | init_emit_regs (void) | |
5410 | { | |
5411 | int i; | |
5412 | ||
5413 | /* Reset register attributes */ | |
5414 | htab_empty (reg_attrs_htab); | |
5415 | ||
5416 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5417 | init_reg_modes_target (); | |
5418 | ||
5419 | /* Assign register numbers to the globally defined register rtx. */ | |
3810076b BS |
5420 | pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); |
5421 | ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | |
5422 | cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode); | |
b5deb7b6 SL |
5423 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
5424 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5425 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5426 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5427 | virtual_incoming_args_rtx = | |
5428 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5429 | virtual_stack_vars_rtx = | |
5430 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5431 | virtual_stack_dynamic_rtx = | |
5432 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5433 | virtual_outgoing_args_rtx = | |
5434 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5435 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
32990d5b JJ |
5436 | virtual_preferred_stack_boundary_rtx = |
5437 | gen_raw_REG (Pmode, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM); | |
b5deb7b6 SL |
5438 | |
5439 | /* Initialize RTL for commonly used hard registers. These are | |
5440 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5441 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5fb0e246 | 5442 | initial_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); |
b5deb7b6 SL |
5443 | |
5444 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5445 | return_address_pointer_rtx | |
5446 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5447 | #endif | |
5448 | ||
b5deb7b6 SL |
5449 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
5450 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
5451 | else | |
5452 | pic_offset_table_rtx = NULL_RTX; | |
5453 | } | |
5454 | ||
2d888286 | 5455 | /* Create some permanent unique rtl objects shared between all functions. */ |
23b2ce53 RS |
5456 | |
5457 | void | |
2d888286 | 5458 | init_emit_once (void) |
23b2ce53 RS |
5459 | { |
5460 | int i; | |
5461 | enum machine_mode mode; | |
9ec36da5 | 5462 | enum machine_mode double_mode; |
23b2ce53 | 5463 | |
091a3ac7 CF |
5464 | /* Initialize the CONST_INT, CONST_DOUBLE, CONST_FIXED, and memory attribute |
5465 | hash tables. */ | |
17211ab5 GK |
5466 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5467 | const_int_htab_eq, NULL); | |
173b24b9 | 5468 | |
17211ab5 GK |
5469 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5470 | const_double_htab_eq, NULL); | |
5692c7bc | 5471 | |
091a3ac7 CF |
5472 | const_fixed_htab = htab_create_ggc (37, const_fixed_htab_hash, |
5473 | const_fixed_htab_eq, NULL); | |
5474 | ||
17211ab5 GK |
5475 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5476 | mem_attrs_htab_eq, NULL); | |
a560d4d4 JH |
5477 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5478 | reg_attrs_htab_eq, NULL); | |
67673f5c | 5479 | |
43fa6302 AS |
5480 | /* Compute the word and byte modes. */ |
5481 | ||
5482 | byte_mode = VOIDmode; | |
5483 | word_mode = VOIDmode; | |
5484 | double_mode = VOIDmode; | |
5485 | ||
15ed7b52 JG |
5486 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5487 | mode != VOIDmode; | |
43fa6302 AS |
5488 | mode = GET_MODE_WIDER_MODE (mode)) |
5489 | { | |
5490 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5491 | && byte_mode == VOIDmode) | |
5492 | byte_mode = mode; | |
5493 | ||
5494 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5495 | && word_mode == VOIDmode) | |
5496 | word_mode = mode; | |
5497 | } | |
5498 | ||
15ed7b52 JG |
5499 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5500 | mode != VOIDmode; | |
43fa6302 AS |
5501 | mode = GET_MODE_WIDER_MODE (mode)) |
5502 | { | |
5503 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5504 | && double_mode == VOIDmode) | |
5505 | double_mode = mode; | |
5506 | } | |
5507 | ||
5508 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5509 | ||
5da077de | 5510 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5511 | /* This is to initialize {init|mark|free}_machine_status before the first |
5512 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5513 | end which calls push_function_context_to before the first call to |
5da077de AS |
5514 | init_function_start. */ |
5515 | INIT_EXPANDERS; | |
5516 | #endif | |
5517 | ||
23b2ce53 RS |
5518 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5519 | ||
a2a8cc44 | 5520 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 5521 | tries to use these variables. */ |
23b2ce53 | 5522 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5523 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5524 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5525 | |
68d75312 JC |
5526 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5527 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5528 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5529 | else |
3b80f6ca | 5530 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5531 | |
5692c7bc ZW |
5532 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5533 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5534 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
aefa9d43 KG |
5535 | |
5536 | dconstm1 = dconst1; | |
5537 | dconstm1.sign = 1; | |
03f2ea93 RS |
5538 | |
5539 | dconsthalf = dconst1; | |
1e92bbb9 | 5540 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 5541 | |
f7657db9 | 5542 | for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++) |
23b2ce53 | 5543 | { |
aefa9d43 | 5544 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
5545 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
5546 | ||
15ed7b52 JG |
5547 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5548 | mode != VOIDmode; | |
5549 | mode = GET_MODE_WIDER_MODE (mode)) | |
5550 | const_tiny_rtx[i][(int) mode] = | |
5551 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5552 | ||
5553 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5554 | mode != VOIDmode; | |
23b2ce53 | 5555 | mode = GET_MODE_WIDER_MODE (mode)) |
5692c7bc ZW |
5556 | const_tiny_rtx[i][(int) mode] = |
5557 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5558 | |
906c4e36 | 5559 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 5560 | |
15ed7b52 JG |
5561 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5562 | mode != VOIDmode; | |
23b2ce53 | 5563 | mode = GET_MODE_WIDER_MODE (mode)) |
906c4e36 | 5564 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
5565 | |
5566 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5567 | mode != VOIDmode; | |
5568 | mode = GET_MODE_WIDER_MODE (mode)) | |
5569 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
5570 | } |
5571 | ||
e90721b1 AP |
5572 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5573 | mode != VOIDmode; | |
5574 | mode = GET_MODE_WIDER_MODE (mode)) | |
5575 | { | |
5576 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5577 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5578 | } | |
5579 | ||
5580 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5581 | mode != VOIDmode; | |
5582 | mode = GET_MODE_WIDER_MODE (mode)) | |
5583 | { | |
5584 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5585 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5586 | } | |
5587 | ||
69ef87e2 AH |
5588 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5589 | mode != VOIDmode; | |
5590 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5591 | { |
5592 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5593 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5594 | } | |
69ef87e2 AH |
5595 | |
5596 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5597 | mode != VOIDmode; | |
5598 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5599 | { |
5600 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5601 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5602 | } | |
69ef87e2 | 5603 | |
325217ed CF |
5604 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
5605 | mode != VOIDmode; | |
5606 | mode = GET_MODE_WIDER_MODE (mode)) | |
5607 | { | |
5608 | FCONST0(mode).data.high = 0; | |
5609 | FCONST0(mode).data.low = 0; | |
5610 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5611 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5612 | FCONST0 (mode), mode); | |
325217ed CF |
5613 | } |
5614 | ||
5615 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
5616 | mode != VOIDmode; | |
5617 | mode = GET_MODE_WIDER_MODE (mode)) | |
5618 | { | |
5619 | FCONST0(mode).data.high = 0; | |
5620 | FCONST0(mode).data.low = 0; | |
5621 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5622 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5623 | FCONST0 (mode), mode); | |
325217ed CF |
5624 | } |
5625 | ||
5626 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
5627 | mode != VOIDmode; | |
5628 | mode = GET_MODE_WIDER_MODE (mode)) | |
5629 | { | |
5630 | FCONST0(mode).data.high = 0; | |
5631 | FCONST0(mode).data.low = 0; | |
5632 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5633 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5634 | FCONST0 (mode), mode); | |
325217ed CF |
5635 | |
5636 | /* We store the value 1. */ | |
5637 | FCONST1(mode).data.high = 0; | |
5638 | FCONST1(mode).data.low = 0; | |
5639 | FCONST1(mode).mode = mode; | |
5640 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5641 | 2 * HOST_BITS_PER_WIDE_INT, | |
5642 | &FCONST1(mode).data.low, | |
5643 | &FCONST1(mode).data.high, | |
5644 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5645 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5646 | FCONST1 (mode), mode); | |
325217ed CF |
5647 | } |
5648 | ||
5649 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
5650 | mode != VOIDmode; | |
5651 | mode = GET_MODE_WIDER_MODE (mode)) | |
5652 | { | |
5653 | FCONST0(mode).data.high = 0; | |
5654 | FCONST0(mode).data.low = 0; | |
5655 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5656 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5657 | FCONST0 (mode), mode); | |
325217ed CF |
5658 | |
5659 | /* We store the value 1. */ | |
5660 | FCONST1(mode).data.high = 0; | |
5661 | FCONST1(mode).data.low = 0; | |
5662 | FCONST1(mode).mode = mode; | |
5663 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5664 | 2 * HOST_BITS_PER_WIDE_INT, | |
5665 | &FCONST1(mode).data.low, | |
5666 | &FCONST1(mode).data.high, | |
5667 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5668 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5669 | FCONST1 (mode), mode); | |
5670 | } | |
5671 | ||
5672 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT); | |
5673 | mode != VOIDmode; | |
5674 | mode = GET_MODE_WIDER_MODE (mode)) | |
5675 | { | |
5676 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5677 | } | |
5678 | ||
5679 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT); | |
5680 | mode != VOIDmode; | |
5681 | mode = GET_MODE_WIDER_MODE (mode)) | |
5682 | { | |
5683 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5684 | } | |
5685 | ||
5686 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM); | |
5687 | mode != VOIDmode; | |
5688 | mode = GET_MODE_WIDER_MODE (mode)) | |
5689 | { | |
5690 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5691 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5692 | } | |
5693 | ||
5694 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM); | |
5695 | mode != VOIDmode; | |
5696 | mode = GET_MODE_WIDER_MODE (mode)) | |
5697 | { | |
5698 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5699 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
5700 | } |
5701 | ||
dbbbbf3b JDA |
5702 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5703 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5704 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 5705 | |
f0417c82 RH |
5706 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5707 | if (STORE_FLAG_VALUE == 1) | |
5708 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
23b2ce53 | 5709 | } |
a11759a3 | 5710 | \f |
969d70ca JH |
5711 | /* Produce exact duplicate of insn INSN after AFTER. |
5712 | Care updating of libcall regions if present. */ | |
5713 | ||
5714 | rtx | |
502b8322 | 5715 | emit_copy_of_insn_after (rtx insn, rtx after) |
969d70ca | 5716 | { |
60564289 | 5717 | rtx new_rtx, link; |
969d70ca JH |
5718 | |
5719 | switch (GET_CODE (insn)) | |
5720 | { | |
5721 | case INSN: | |
60564289 | 5722 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5723 | break; |
5724 | ||
5725 | case JUMP_INSN: | |
60564289 | 5726 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
5727 | break; |
5728 | ||
b5b8b0ac AO |
5729 | case DEBUG_INSN: |
5730 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
5731 | break; | |
5732 | ||
969d70ca | 5733 | case CALL_INSN: |
60564289 | 5734 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 5735 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 5736 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 5737 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
5738 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
5739 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
5740 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
b8698a0f | 5741 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) |
becfd6e5 | 5742 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
5743 | break; |
5744 | ||
5745 | default: | |
5b0264cb | 5746 | gcc_unreachable (); |
969d70ca JH |
5747 | } |
5748 | ||
5749 | /* Update LABEL_NUSES. */ | |
60564289 | 5750 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 5751 | |
60564289 | 5752 | INSN_LOCATOR (new_rtx) = INSN_LOCATOR (insn); |
ba4f7968 | 5753 | |
0a3d71f5 JW |
5754 | /* If the old insn is frame related, then so is the new one. This is |
5755 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
5756 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 5757 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 5758 | |
cf7c4aa6 HPN |
5759 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
5760 | will make them. REG_LABEL_TARGETs are created there too, but are | |
5761 | supposed to be sticky, so we copy them. */ | |
969d70ca | 5762 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 5763 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca JH |
5764 | { |
5765 | if (GET_CODE (link) == EXPR_LIST) | |
60564289 | 5766 | add_reg_note (new_rtx, REG_NOTE_KIND (link), |
65c5f2a6 | 5767 | copy_insn_1 (XEXP (link, 0))); |
969d70ca | 5768 | else |
60564289 | 5769 | add_reg_note (new_rtx, REG_NOTE_KIND (link), XEXP (link, 0)); |
969d70ca JH |
5770 | } |
5771 | ||
60564289 KG |
5772 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
5773 | return new_rtx; | |
969d70ca | 5774 | } |
e2500fed | 5775 | |
1431042e | 5776 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d JH |
5777 | rtx |
5778 | gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno) | |
5779 | { | |
5780 | if (hard_reg_clobbers[mode][regno]) | |
5781 | return hard_reg_clobbers[mode][regno]; | |
5782 | else | |
5783 | return (hard_reg_clobbers[mode][regno] = | |
5784 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
5785 | } | |
5786 | ||
e2500fed | 5787 | #include "gt-emit-rtl.h" |