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Commit | Line | Data |
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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
e53a16e7 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
b6f65e3c | 4 | Free Software Foundation, Inc. |
23b2ce53 | 5 | |
1322177d | 6 | This file is part of GCC. |
23b2ce53 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
23b2ce53 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
23b2ce53 RS |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
f822fcf7 KH |
25 | This file contains support functions for creating rtl expressions |
26 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
27 | |
28 | The patterns of the insns are created by machine-dependent | |
29 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
30 | the machine description. These routines make the individual rtx's |
31 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
32 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
33 | dependent is the kind of rtx's they make and what arguments they |
34 | use. */ | |
23b2ce53 RS |
35 | |
36 | #include "config.h" | |
670ee920 | 37 | #include "system.h" |
4977bab6 ZW |
38 | #include "coretypes.h" |
39 | #include "tm.h" | |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
325217ed | 53 | #include "fixed-value.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
e1772ac0 | 57 | #include "debug.h" |
d23c55c2 | 58 | #include "langhooks.h" |
ef330312 | 59 | #include "tree-pass.h" |
6fb5fa3c | 60 | #include "df.h" |
ca695ac9 | 61 | |
1d445e9e ILT |
62 | /* Commonly used modes. */ |
63 | ||
0f41302f MS |
64 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
65 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 66 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 67 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 68 | |
23b2ce53 RS |
69 | |
70 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
71 | in the entire compilation a unique label number. */ | |
72 | ||
044b4de3 | 73 | static GTY(()) int label_num = 1; |
23b2ce53 | 74 | |
23b2ce53 RS |
75 | /* Nonzero means do not generate NOTEs for source line numbers. */ |
76 | ||
77 | static int no_line_numbers; | |
78 | ||
79 | /* Commonly used rtx's, so that we only need space for one copy. | |
80 | These are initialized once for the entire compilation. | |
5692c7bc ZW |
81 | All of these are unique; no other rtx-object will be equal to any |
82 | of these. */ | |
23b2ce53 | 83 | |
5da077de | 84 | rtx global_rtl[GR_MAX]; |
23b2ce53 | 85 | |
6cde4876 JL |
86 | /* Commonly used RTL for hard registers. These objects are not necessarily |
87 | unique, so we allocate them separately from global_rtl. They are | |
88 | initialized once per compilation unit, then copied into regno_reg_rtx | |
89 | at the beginning of each function. */ | |
90 | static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
91 | ||
23b2ce53 RS |
92 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
93 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
94 | record a copy of const[012]_rtx. */ | |
95 | ||
96 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
97 | ||
68d75312 JC |
98 | rtx const_true_rtx; |
99 | ||
23b2ce53 RS |
100 | REAL_VALUE_TYPE dconst0; |
101 | REAL_VALUE_TYPE dconst1; | |
102 | REAL_VALUE_TYPE dconst2; | |
f7657db9 KG |
103 | REAL_VALUE_TYPE dconst3; |
104 | REAL_VALUE_TYPE dconst10; | |
23b2ce53 | 105 | REAL_VALUE_TYPE dconstm1; |
03f2ea93 RS |
106 | REAL_VALUE_TYPE dconstm2; |
107 | REAL_VALUE_TYPE dconsthalf; | |
f7657db9 | 108 | REAL_VALUE_TYPE dconstthird; |
b86a760a | 109 | REAL_VALUE_TYPE dconstsqrt2; |
ab01a87c | 110 | REAL_VALUE_TYPE dconste; |
23b2ce53 | 111 | |
325217ed CF |
112 | /* Record fixed-point constant 0 and 1. */ |
113 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
114 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
115 | ||
23b2ce53 RS |
116 | /* All references to the following fixed hard registers go through |
117 | these unique rtl objects. On machines where the frame-pointer and | |
118 | arg-pointer are the same register, they use the same unique object. | |
119 | ||
120 | After register allocation, other rtl objects which used to be pseudo-regs | |
121 | may be clobbered to refer to the frame-pointer register. | |
122 | But references that were originally to the frame-pointer can be | |
123 | distinguished from the others because they contain frame_pointer_rtx. | |
124 | ||
ac6f08b0 DE |
125 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
126 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
750c9258 | 127 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
ac6f08b0 DE |
128 | register elimination hard_frame_pointer_rtx should always be used. |
129 | On machines where the two registers are same (most) then these are the | |
130 | same. | |
131 | ||
23b2ce53 RS |
132 | In an inline procedure, the stack and frame pointer rtxs may not be |
133 | used for anything else. */ | |
23b2ce53 RS |
134 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ |
135 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
136 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
137 | ||
a4417a86 JW |
138 | /* This is used to implement __builtin_return_address for some machines. |
139 | See for instance the MIPS port. */ | |
140 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
141 | ||
23b2ce53 RS |
142 | /* We make one copy of (const_int C) where C is in |
143 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
144 | to save space during the compilation and simplify comparisons of | |
145 | integers. */ | |
146 | ||
5da077de | 147 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 148 | |
c13e8210 MM |
149 | /* A hash table storing CONST_INTs whose absolute value is greater |
150 | than MAX_SAVED_CONST_INT. */ | |
151 | ||
e2500fed GK |
152 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
153 | htab_t const_int_htab; | |
c13e8210 | 154 | |
173b24b9 | 155 | /* A hash table storing memory attribute structures. */ |
e2500fed GK |
156 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
157 | htab_t mem_attrs_htab; | |
173b24b9 | 158 | |
a560d4d4 JH |
159 | /* A hash table storing register attribute structures. */ |
160 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
161 | htab_t reg_attrs_htab; | |
162 | ||
5692c7bc | 163 | /* A hash table storing all CONST_DOUBLEs. */ |
e2500fed GK |
164 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
165 | htab_t const_double_htab; | |
5692c7bc | 166 | |
091a3ac7 CF |
167 | /* A hash table storing all CONST_FIXEDs. */ |
168 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) | |
169 | htab_t const_fixed_htab; | |
170 | ||
01d939e8 BS |
171 | #define first_insn (cfun->emit->x_first_insn) |
172 | #define last_insn (cfun->emit->x_last_insn) | |
173 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
fd3acbb3 | 174 | #define last_location (cfun->emit->x_last_location) |
01d939e8 | 175 | #define first_label_num (cfun->emit->x_first_label_num) |
23b2ce53 | 176 | |
502b8322 | 177 | static rtx make_call_insn_raw (rtx); |
502b8322 | 178 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); |
5eb2a9f2 | 179 | static void set_used_decls (tree); |
502b8322 AJ |
180 | static void mark_label_nuses (rtx); |
181 | static hashval_t const_int_htab_hash (const void *); | |
182 | static int const_int_htab_eq (const void *, const void *); | |
183 | static hashval_t const_double_htab_hash (const void *); | |
184 | static int const_double_htab_eq (const void *, const void *); | |
185 | static rtx lookup_const_double (rtx); | |
091a3ac7 CF |
186 | static hashval_t const_fixed_htab_hash (const void *); |
187 | static int const_fixed_htab_eq (const void *, const void *); | |
188 | static rtx lookup_const_fixed (rtx); | |
502b8322 AJ |
189 | static hashval_t mem_attrs_htab_hash (const void *); |
190 | static int mem_attrs_htab_eq (const void *, const void *); | |
4862826d | 191 | static mem_attrs *get_mem_attrs (alias_set_type, tree, rtx, rtx, unsigned int, |
502b8322 AJ |
192 | enum machine_mode); |
193 | static hashval_t reg_attrs_htab_hash (const void *); | |
194 | static int reg_attrs_htab_eq (const void *, const void *); | |
195 | static reg_attrs *get_reg_attrs (tree, int); | |
196 | static tree component_ref_for_mem_expr (tree); | |
a73b091d | 197 | static rtx gen_const_vector (enum machine_mode, int); |
32b32b16 | 198 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 199 | |
6b24c259 JH |
200 | /* Probability of the conditional branch currently proceeded by try_split. |
201 | Set to -1 otherwise. */ | |
202 | int split_branch_probability = -1; | |
ca695ac9 | 203 | \f |
c13e8210 MM |
204 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
205 | ||
206 | static hashval_t | |
502b8322 | 207 | const_int_htab_hash (const void *x) |
c13e8210 | 208 | { |
f7d504c2 | 209 | return (hashval_t) INTVAL ((const_rtx) x); |
c13e8210 MM |
210 | } |
211 | ||
cc2902df | 212 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
213 | CONST_INT) is the same as that given by Y (which is really a |
214 | HOST_WIDE_INT *). */ | |
215 | ||
216 | static int | |
502b8322 | 217 | const_int_htab_eq (const void *x, const void *y) |
c13e8210 | 218 | { |
f7d504c2 | 219 | return (INTVAL ((const_rtx) x) == *((const HOST_WIDE_INT *) y)); |
5692c7bc ZW |
220 | } |
221 | ||
222 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
223 | static hashval_t | |
502b8322 | 224 | const_double_htab_hash (const void *x) |
5692c7bc | 225 | { |
f7d504c2 | 226 | const_rtx const value = (const_rtx) x; |
46b33600 | 227 | hashval_t h; |
5692c7bc | 228 | |
46b33600 RH |
229 | if (GET_MODE (value) == VOIDmode) |
230 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
231 | else | |
fe352c29 | 232 | { |
15c812e3 | 233 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
234 | /* MODE is used in the comparison, so it should be in the hash. */ |
235 | h ^= GET_MODE (value); | |
236 | } | |
5692c7bc ZW |
237 | return h; |
238 | } | |
239 | ||
cc2902df | 240 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc ZW |
241 | is the same as that represented by Y (really a ...) */ |
242 | static int | |
502b8322 | 243 | const_double_htab_eq (const void *x, const void *y) |
5692c7bc | 244 | { |
f7d504c2 | 245 | const_rtx const a = (const_rtx)x, b = (const_rtx)y; |
5692c7bc ZW |
246 | |
247 | if (GET_MODE (a) != GET_MODE (b)) | |
248 | return 0; | |
8580f7a0 RH |
249 | if (GET_MODE (a) == VOIDmode) |
250 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
251 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
252 | else | |
253 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
254 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
255 | } |
256 | ||
091a3ac7 CF |
257 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
258 | ||
259 | static hashval_t | |
260 | const_fixed_htab_hash (const void *x) | |
261 | { | |
3101faab | 262 | const_rtx const value = (const_rtx) x; |
091a3ac7 CF |
263 | hashval_t h; |
264 | ||
265 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
266 | /* MODE is used in the comparison, so it should be in the hash. */ | |
267 | h ^= GET_MODE (value); | |
268 | return h; | |
269 | } | |
270 | ||
271 | /* Returns nonzero if the value represented by X (really a ...) | |
272 | is the same as that represented by Y (really a ...). */ | |
273 | ||
274 | static int | |
275 | const_fixed_htab_eq (const void *x, const void *y) | |
276 | { | |
3101faab | 277 | const_rtx const a = (const_rtx) x, b = (const_rtx) y; |
091a3ac7 CF |
278 | |
279 | if (GET_MODE (a) != GET_MODE (b)) | |
280 | return 0; | |
281 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
282 | } | |
283 | ||
173b24b9 RK |
284 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
285 | ||
286 | static hashval_t | |
502b8322 | 287 | mem_attrs_htab_hash (const void *x) |
173b24b9 | 288 | { |
f7d504c2 | 289 | const mem_attrs *const p = (const mem_attrs *) x; |
173b24b9 RK |
290 | |
291 | return (p->alias ^ (p->align * 1000) | |
292 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) | |
293 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
78b76d08 | 294 | ^ (size_t) iterative_hash_expr (p->expr, 0)); |
173b24b9 RK |
295 | } |
296 | ||
cc2902df | 297 | /* Returns nonzero if the value represented by X (which is really a |
173b24b9 RK |
298 | mem_attrs *) is the same as that given by Y (which is also really a |
299 | mem_attrs *). */ | |
c13e8210 MM |
300 | |
301 | static int | |
502b8322 | 302 | mem_attrs_htab_eq (const void *x, const void *y) |
c13e8210 | 303 | { |
741ac903 KG |
304 | const mem_attrs *const p = (const mem_attrs *) x; |
305 | const mem_attrs *const q = (const mem_attrs *) y; | |
173b24b9 | 306 | |
78b76d08 SB |
307 | return (p->alias == q->alias && p->offset == q->offset |
308 | && p->size == q->size && p->align == q->align | |
309 | && (p->expr == q->expr | |
310 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
311 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
312 | } |
313 | ||
173b24b9 | 314 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
10b76d73 RK |
315 | one identical to it is not already in the table. We are doing this for |
316 | MEM of mode MODE. */ | |
173b24b9 RK |
317 | |
318 | static mem_attrs * | |
4862826d | 319 | get_mem_attrs (alias_set_type alias, tree expr, rtx offset, rtx size, |
502b8322 | 320 | unsigned int align, enum machine_mode mode) |
173b24b9 RK |
321 | { |
322 | mem_attrs attrs; | |
323 | void **slot; | |
324 | ||
bb056a77 OH |
325 | /* If everything is the default, we can just return zero. |
326 | This must match what the corresponding MEM_* macros return when the | |
327 | field is not present. */ | |
998d7deb | 328 | if (alias == 0 && expr == 0 && offset == 0 |
10b76d73 RK |
329 | && (size == 0 |
330 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
bb056a77 OH |
331 | && (STRICT_ALIGNMENT && mode != BLKmode |
332 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
10b76d73 RK |
333 | return 0; |
334 | ||
173b24b9 | 335 | attrs.alias = alias; |
998d7deb | 336 | attrs.expr = expr; |
173b24b9 RK |
337 | attrs.offset = offset; |
338 | attrs.size = size; | |
339 | attrs.align = align; | |
340 | ||
341 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
342 | if (*slot == 0) | |
343 | { | |
344 | *slot = ggc_alloc (sizeof (mem_attrs)); | |
345 | memcpy (*slot, &attrs, sizeof (mem_attrs)); | |
346 | } | |
347 | ||
348 | return *slot; | |
c13e8210 MM |
349 | } |
350 | ||
a560d4d4 JH |
351 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
352 | ||
353 | static hashval_t | |
502b8322 | 354 | reg_attrs_htab_hash (const void *x) |
a560d4d4 | 355 | { |
741ac903 | 356 | const reg_attrs *const p = (const reg_attrs *) x; |
a560d4d4 JH |
357 | |
358 | return ((p->offset * 1000) ^ (long) p->decl); | |
359 | } | |
360 | ||
6356f892 | 361 | /* Returns nonzero if the value represented by X (which is really a |
a560d4d4 JH |
362 | reg_attrs *) is the same as that given by Y (which is also really a |
363 | reg_attrs *). */ | |
364 | ||
365 | static int | |
502b8322 | 366 | reg_attrs_htab_eq (const void *x, const void *y) |
a560d4d4 | 367 | { |
741ac903 KG |
368 | const reg_attrs *const p = (const reg_attrs *) x; |
369 | const reg_attrs *const q = (const reg_attrs *) y; | |
a560d4d4 JH |
370 | |
371 | return (p->decl == q->decl && p->offset == q->offset); | |
372 | } | |
373 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
374 | one identical to it is not already in the table. We are doing this for | |
375 | MEM of mode MODE. */ | |
376 | ||
377 | static reg_attrs * | |
502b8322 | 378 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
379 | { |
380 | reg_attrs attrs; | |
381 | void **slot; | |
382 | ||
383 | /* If everything is the default, we can just return zero. */ | |
384 | if (decl == 0 && offset == 0) | |
385 | return 0; | |
386 | ||
387 | attrs.decl = decl; | |
388 | attrs.offset = offset; | |
389 | ||
390 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
391 | if (*slot == 0) | |
392 | { | |
393 | *slot = ggc_alloc (sizeof (reg_attrs)); | |
394 | memcpy (*slot, &attrs, sizeof (reg_attrs)); | |
395 | } | |
396 | ||
397 | return *slot; | |
398 | } | |
399 | ||
6fb5fa3c DB |
400 | |
401 | #if !HAVE_blockage | |
402 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule | |
403 | across this insn. */ | |
404 | ||
405 | rtx | |
406 | gen_blockage (void) | |
407 | { | |
408 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
409 | MEM_VOLATILE_P (x) = true; | |
410 | return x; | |
411 | } | |
412 | #endif | |
413 | ||
414 | ||
08394eef BS |
415 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
416 | don't attempt to share with the various global pieces of rtl (such as | |
417 | frame_pointer_rtx). */ | |
418 | ||
419 | rtx | |
502b8322 | 420 | gen_raw_REG (enum machine_mode mode, int regno) |
08394eef BS |
421 | { |
422 | rtx x = gen_rtx_raw_REG (mode, regno); | |
423 | ORIGINAL_REGNO (x) = regno; | |
424 | return x; | |
425 | } | |
426 | ||
c5c76735 JL |
427 | /* There are some RTL codes that require special attention; the generation |
428 | functions do the raw handling. If you add to this list, modify | |
429 | special_rtx in gengenrtl.c as well. */ | |
430 | ||
3b80f6ca | 431 | rtx |
502b8322 | 432 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca | 433 | { |
c13e8210 MM |
434 | void **slot; |
435 | ||
3b80f6ca | 436 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 437 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
438 | |
439 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
440 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
441 | return const_true_rtx; | |
442 | #endif | |
443 | ||
c13e8210 | 444 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
445 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
446 | (hashval_t) arg, INSERT); | |
29105cea | 447 | if (*slot == 0) |
1f8f4a0b | 448 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
449 | |
450 | return (rtx) *slot; | |
3b80f6ca RH |
451 | } |
452 | ||
2496c7bd | 453 | rtx |
502b8322 | 454 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2496c7bd LB |
455 | { |
456 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
457 | } | |
458 | ||
5692c7bc ZW |
459 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
460 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
461 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
462 | ||
463 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
464 | hash table. If so, return its counterpart; otherwise add it | |
465 | to the hash table and return it. */ | |
466 | static rtx | |
502b8322 | 467 | lookup_const_double (rtx real) |
5692c7bc ZW |
468 | { |
469 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
470 | if (*slot == 0) | |
471 | *slot = real; | |
472 | ||
473 | return (rtx) *slot; | |
474 | } | |
29105cea | 475 | |
5692c7bc ZW |
476 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
477 | VALUE in mode MODE. */ | |
0133b7d9 | 478 | rtx |
502b8322 | 479 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
0133b7d9 | 480 | { |
5692c7bc ZW |
481 | rtx real = rtx_alloc (CONST_DOUBLE); |
482 | PUT_MODE (real, mode); | |
483 | ||
9e254451 | 484 | real->u.rv = value; |
5692c7bc ZW |
485 | |
486 | return lookup_const_double (real); | |
487 | } | |
488 | ||
091a3ac7 CF |
489 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
490 | hash table. If so, return its counterpart; otherwise add it | |
491 | to the hash table and return it. */ | |
492 | ||
493 | static rtx | |
494 | lookup_const_fixed (rtx fixed) | |
495 | { | |
496 | void **slot = htab_find_slot (const_fixed_htab, fixed, INSERT); | |
497 | if (*slot == 0) | |
498 | *slot = fixed; | |
499 | ||
500 | return (rtx) *slot; | |
501 | } | |
502 | ||
503 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
504 | VALUE in mode MODE. */ | |
505 | ||
506 | rtx | |
507 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, enum machine_mode mode) | |
508 | { | |
509 | rtx fixed = rtx_alloc (CONST_FIXED); | |
510 | PUT_MODE (fixed, mode); | |
511 | ||
512 | fixed->u.fv = value; | |
513 | ||
514 | return lookup_const_fixed (fixed); | |
515 | } | |
516 | ||
5692c7bc ZW |
517 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
518 | of ints: I0 is the low-order word and I1 is the high-order word. | |
519 | Do not use this routine for non-integer modes; convert to | |
520 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
521 | ||
522 | rtx | |
502b8322 | 523 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
5692c7bc ZW |
524 | { |
525 | rtx value; | |
526 | unsigned int i; | |
527 | ||
65acccdd ZD |
528 | /* There are the following cases (note that there are no modes with |
529 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < 2 * HOST_BITS_PER_WIDE_INT): | |
530 | ||
531 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
532 | gen_int_mode. | |
533 | 2) GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT, but the value of | |
534 | the integer fits into HOST_WIDE_INT anyway (i.e., i1 consists only | |
535 | from copies of the sign bit, and sign of i0 and i1 are the same), then | |
536 | we return a CONST_INT for i0. | |
537 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ | |
5692c7bc ZW |
538 | if (mode != VOIDmode) |
539 | { | |
5b0264cb NS |
540 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
541 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
542 | /* We can get a 0 for an error mark. */ | |
543 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
544 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT); | |
5692c7bc | 545 | |
65acccdd ZD |
546 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
547 | return gen_int_mode (i0, mode); | |
548 | ||
549 | gcc_assert (GET_MODE_BITSIZE (mode) == 2 * HOST_BITS_PER_WIDE_INT); | |
5692c7bc ZW |
550 | } |
551 | ||
552 | /* If this integer fits in one word, return a CONST_INT. */ | |
553 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
554 | return GEN_INT (i0); | |
555 | ||
556 | /* We use VOIDmode for integers. */ | |
557 | value = rtx_alloc (CONST_DOUBLE); | |
558 | PUT_MODE (value, VOIDmode); | |
559 | ||
560 | CONST_DOUBLE_LOW (value) = i0; | |
561 | CONST_DOUBLE_HIGH (value) = i1; | |
562 | ||
563 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
564 | XWINT (value, i) = 0; | |
565 | ||
566 | return lookup_const_double (value); | |
0133b7d9 RH |
567 | } |
568 | ||
3b80f6ca | 569 | rtx |
502b8322 | 570 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3b80f6ca RH |
571 | { |
572 | /* In case the MD file explicitly references the frame pointer, have | |
573 | all such references point to the same frame pointer. This is | |
574 | used during frame pointer elimination to distinguish the explicit | |
575 | references to these registers from pseudos that happened to be | |
576 | assigned to them. | |
577 | ||
578 | If we have eliminated the frame pointer or arg pointer, we will | |
579 | be using it as a normal register, for example as a spill | |
580 | register. In such cases, we might be accessing it in a mode that | |
581 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
582 | ||
583 | Also don't do this when we are making new REGs in reload, since | |
584 | we don't want to get confused with the real pointers. */ | |
585 | ||
586 | if (mode == Pmode && !reload_in_progress) | |
587 | { | |
e10c79fe LB |
588 | if (regno == FRAME_POINTER_REGNUM |
589 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
590 | return frame_pointer_rtx; |
591 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e10c79fe LB |
592 | if (regno == HARD_FRAME_POINTER_REGNUM |
593 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
594 | return hard_frame_pointer_rtx; |
595 | #endif | |
596 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 597 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
598 | return arg_pointer_rtx; |
599 | #endif | |
600 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 601 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
602 | return return_address_pointer_rtx; |
603 | #endif | |
fc555370 | 604 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
2d67bd7b | 605 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 606 | return pic_offset_table_rtx; |
bcb33994 | 607 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
608 | return stack_pointer_rtx; |
609 | } | |
610 | ||
006a94b0 | 611 | #if 0 |
6cde4876 | 612 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
613 | an existing entry in that table to avoid useless generation of RTL. |
614 | ||
615 | This code is disabled for now until we can fix the various backends | |
616 | which depend on having non-shared hard registers in some cases. Long | |
617 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
618 | on the amount of useless RTL that gets generated. |
619 | ||
620 | We'll also need to fix some code that runs after reload that wants to | |
621 | set ORIGINAL_REGNO. */ | |
622 | ||
6cde4876 JL |
623 | if (cfun |
624 | && cfun->emit | |
625 | && regno_reg_rtx | |
626 | && regno < FIRST_PSEUDO_REGISTER | |
627 | && reg_raw_mode[regno] == mode) | |
628 | return regno_reg_rtx[regno]; | |
006a94b0 | 629 | #endif |
6cde4876 | 630 | |
08394eef | 631 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
632 | } |
633 | ||
41472af8 | 634 | rtx |
502b8322 | 635 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
41472af8 MM |
636 | { |
637 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
638 | ||
639 | /* This field is not cleared by the mere allocation of the rtx, so | |
640 | we clear it here. */ | |
173b24b9 | 641 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
642 | |
643 | return rt; | |
644 | } | |
ddef6bc7 | 645 | |
542a8afa RH |
646 | /* Generate a memory referring to non-trapping constant memory. */ |
647 | ||
648 | rtx | |
649 | gen_const_mem (enum machine_mode mode, rtx addr) | |
650 | { | |
651 | rtx mem = gen_rtx_MEM (mode, addr); | |
652 | MEM_READONLY_P (mem) = 1; | |
653 | MEM_NOTRAP_P (mem) = 1; | |
654 | return mem; | |
655 | } | |
656 | ||
bf877a76 R |
657 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
658 | save areas. */ | |
659 | ||
660 | rtx | |
661 | gen_frame_mem (enum machine_mode mode, rtx addr) | |
662 | { | |
663 | rtx mem = gen_rtx_MEM (mode, addr); | |
664 | MEM_NOTRAP_P (mem) = 1; | |
665 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
666 | return mem; | |
667 | } | |
668 | ||
669 | /* Generate a MEM referring to a temporary use of the stack, not part | |
670 | of the fixed stack frame. For example, something which is pushed | |
671 | by a target splitter. */ | |
672 | rtx | |
673 | gen_tmp_stack_mem (enum machine_mode mode, rtx addr) | |
674 | { | |
675 | rtx mem = gen_rtx_MEM (mode, addr); | |
676 | MEM_NOTRAP_P (mem) = 1; | |
677 | if (!current_function_calls_alloca) | |
678 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
679 | return mem; | |
680 | } | |
681 | ||
beb72684 RH |
682 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
683 | this construct would be valid, and false otherwise. */ | |
684 | ||
685 | bool | |
686 | validate_subreg (enum machine_mode omode, enum machine_mode imode, | |
ed7a4b4b | 687 | const_rtx reg, unsigned int offset) |
ddef6bc7 | 688 | { |
beb72684 RH |
689 | unsigned int isize = GET_MODE_SIZE (imode); |
690 | unsigned int osize = GET_MODE_SIZE (omode); | |
691 | ||
692 | /* All subregs must be aligned. */ | |
693 | if (offset % osize != 0) | |
694 | return false; | |
695 | ||
696 | /* The subreg offset cannot be outside the inner object. */ | |
697 | if (offset >= isize) | |
698 | return false; | |
699 | ||
700 | /* ??? This should not be here. Temporarily continue to allow word_mode | |
701 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
702 | Generally, backends are doing something sketchy but it'll take time to | |
703 | fix them all. */ | |
704 | if (omode == word_mode) | |
705 | ; | |
706 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
707 | is the culprit here, and not the backends. */ | |
708 | else if (osize >= UNITS_PER_WORD && isize >= osize) | |
709 | ; | |
710 | /* Allow component subregs of complex and vector. Though given the below | |
711 | extraction rules, it's not always clear what that means. */ | |
712 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
713 | && GET_MODE_INNER (imode) == omode) | |
714 | ; | |
715 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
716 | i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to | |
717 | represent this. It's questionable if this ought to be represented at | |
718 | all -- why can't this all be hidden in post-reload splitters that make | |
719 | arbitrarily mode changes to the registers themselves. */ | |
720 | else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode) | |
721 | ; | |
722 | /* Subregs involving floating point modes are not allowed to | |
723 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
724 | (subreg:SI (reg:DF) 0) isn't. */ | |
725 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
726 | { | |
727 | if (isize != osize) | |
728 | return false; | |
729 | } | |
ddef6bc7 | 730 | |
beb72684 RH |
731 | /* Paradoxical subregs must have offset zero. */ |
732 | if (osize > isize) | |
733 | return offset == 0; | |
734 | ||
735 | /* This is a normal subreg. Verify that the offset is representable. */ | |
736 | ||
737 | /* For hard registers, we already have most of these rules collected in | |
738 | subreg_offset_representable_p. */ | |
739 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
740 | { | |
741 | unsigned int regno = REGNO (reg); | |
742 | ||
743 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
744 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
745 | && GET_MODE_INNER (imode) == omode) | |
746 | ; | |
747 | else if (REG_CANNOT_CHANGE_MODE_P (regno, imode, omode)) | |
748 | return false; | |
ddef6bc7 | 749 | #endif |
beb72684 RH |
750 | |
751 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
752 | } | |
753 | ||
754 | /* For pseudo registers, we want most of the same checks. Namely: | |
755 | If the register no larger than a word, the subreg must be lowpart. | |
756 | If the register is larger than a word, the subreg must be the lowpart | |
757 | of a subword. A subreg does *not* perform arbitrary bit extraction. | |
758 | Given that we've already checked mode/offset alignment, we only have | |
759 | to check subword subregs here. */ | |
760 | if (osize < UNITS_PER_WORD) | |
761 | { | |
762 | enum machine_mode wmode = isize > UNITS_PER_WORD ? word_mode : imode; | |
763 | unsigned int low_off = subreg_lowpart_offset (omode, wmode); | |
764 | if (offset % UNITS_PER_WORD != low_off) | |
765 | return false; | |
766 | } | |
767 | return true; | |
768 | } | |
769 | ||
770 | rtx | |
771 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) | |
772 | { | |
773 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 774 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
775 | } |
776 | ||
173b24b9 RK |
777 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
778 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
779 | ||
ddef6bc7 | 780 | rtx |
502b8322 | 781 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
ddef6bc7 JJ |
782 | { |
783 | enum machine_mode inmode; | |
ddef6bc7 JJ |
784 | |
785 | inmode = GET_MODE (reg); | |
786 | if (inmode == VOIDmode) | |
787 | inmode = mode; | |
e0e08ac2 JH |
788 | return gen_rtx_SUBREG (mode, reg, |
789 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 790 | } |
c5c76735 | 791 | \f |
23b2ce53 RS |
792 | /* gen_rtvec (n, [rt1, ..., rtn]) |
793 | ** | |
794 | ** This routine creates an rtvec and stores within it the | |
795 | ** pointers to rtx's which are its arguments. | |
796 | */ | |
797 | ||
798 | /*VARARGS1*/ | |
799 | rtvec | |
e34d07f2 | 800 | gen_rtvec (int n, ...) |
23b2ce53 | 801 | { |
6268b922 | 802 | int i, save_n; |
23b2ce53 | 803 | rtx *vector; |
e34d07f2 | 804 | va_list p; |
23b2ce53 | 805 | |
e34d07f2 | 806 | va_start (p, n); |
23b2ce53 RS |
807 | |
808 | if (n == 0) | |
809 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
810 | ||
703ad42b | 811 | vector = alloca (n * sizeof (rtx)); |
4f90e4a0 | 812 | |
23b2ce53 RS |
813 | for (i = 0; i < n; i++) |
814 | vector[i] = va_arg (p, rtx); | |
6268b922 KG |
815 | |
816 | /* The definition of VA_* in K&R C causes `n' to go out of scope. */ | |
817 | save_n = n; | |
e34d07f2 | 818 | va_end (p); |
23b2ce53 | 819 | |
6268b922 | 820 | return gen_rtvec_v (save_n, vector); |
23b2ce53 RS |
821 | } |
822 | ||
823 | rtvec | |
502b8322 | 824 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 825 | { |
b3694847 SS |
826 | int i; |
827 | rtvec rt_val; | |
23b2ce53 RS |
828 | |
829 | if (n == 0) | |
830 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
831 | ||
832 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
833 | ||
834 | for (i = 0; i < n; i++) | |
8f985ec4 | 835 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
836 | |
837 | return rt_val; | |
838 | } | |
839 | \f | |
840 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
841 | This pseudo is assigned the next sequential register number. */ | |
842 | ||
843 | rtx | |
502b8322 | 844 | gen_reg_rtx (enum machine_mode mode) |
23b2ce53 | 845 | { |
01d939e8 | 846 | struct function *f = cfun; |
b3694847 | 847 | rtx val; |
23b2ce53 | 848 | |
f8335a4f | 849 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 850 | |
1b3d8f8a GK |
851 | if (generating_concat_p |
852 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
853 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
854 | { |
855 | /* For complex modes, don't make a single pseudo. | |
856 | Instead, make a CONCAT of two pseudos. | |
857 | This allows noncontiguous allocation of the real and imaginary parts, | |
858 | which makes much better code. Besides, allocating DCmode | |
859 | pseudos overstrains reload on some machines like the 386. */ | |
860 | rtx realpart, imagpart; | |
27e58a70 | 861 | enum machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
862 | |
863 | realpart = gen_reg_rtx (partmode); | |
864 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 865 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
866 | } |
867 | ||
a560d4d4 | 868 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 869 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 870 | |
3502dc9c | 871 | if (reg_rtx_no == f->emit->regno_pointer_align_length) |
23b2ce53 | 872 | { |
3502dc9c | 873 | int old_size = f->emit->regno_pointer_align_length; |
e2ecd91c | 874 | char *new; |
0d4903b8 | 875 | rtx *new1; |
0d4903b8 | 876 | |
e2500fed | 877 | new = ggc_realloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa | 878 | memset (new + old_size, 0, old_size); |
f9e158c3 | 879 | f->emit->regno_pointer_align = (unsigned char *) new; |
49ad7cfa | 880 | |
703ad42b KG |
881 | new1 = ggc_realloc (f->emit->x_regno_reg_rtx, |
882 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 883 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
884 | regno_reg_rtx = new1; |
885 | ||
3502dc9c | 886 | f->emit->regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
887 | } |
888 | ||
08394eef | 889 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
890 | regno_reg_rtx[reg_rtx_no++] = val; |
891 | return val; | |
892 | } | |
893 | ||
e53a16e7 | 894 | /* Update NEW with the same attributes as REG, but offsetted by OFFSET. |
e314a036 | 895 | Do the big endian correction if needed. */ |
a560d4d4 | 896 | |
e53a16e7 ILT |
897 | static void |
898 | update_reg_offset (rtx new, rtx reg, int offset) | |
a560d4d4 | 899 | { |
e314a036 JZ |
900 | tree decl; |
901 | HOST_WIDE_INT var_size; | |
902 | ||
903 | /* PR middle-end/14084 | |
904 | The problem appears when a variable is stored in a larger register | |
905 | and later it is used in the original mode or some mode in between | |
906 | or some part of variable is accessed. | |
907 | ||
908 | On little endian machines there is no problem because | |
909 | the REG_OFFSET of the start of the variable is the same when | |
910 | accessed in any mode (it is 0). | |
911 | ||
912 | However, this is not true on big endian machines. | |
913 | The offset of the start of the variable is different when accessed | |
914 | in different modes. | |
915 | When we are taking a part of the REG we have to change the OFFSET | |
916 | from offset WRT size of mode of REG to offset WRT size of variable. | |
917 | ||
918 | If we would not do the big endian correction the resulting REG_OFFSET | |
919 | would be larger than the size of the DECL. | |
920 | ||
921 | Examples of correction, for BYTES_BIG_ENDIAN WORDS_BIG_ENDIAN machine: | |
922 | ||
923 | REG.mode MODE DECL size old offset new offset description | |
924 | DI SI 4 4 0 int32 in SImode | |
925 | DI SI 1 4 0 char in SImode | |
926 | DI QI 1 7 0 char in QImode | |
927 | DI QI 4 5 1 1st element in QImode | |
928 | of char[4] | |
929 | DI HI 4 6 2 1st element in HImode | |
930 | of int16[2] | |
931 | ||
932 | If the size of DECL is equal or greater than the size of REG | |
933 | we can't do this correction because the register holds the | |
934 | whole variable or a part of the variable and thus the REG_OFFSET | |
935 | is already correct. */ | |
936 | ||
937 | decl = REG_EXPR (reg); | |
938 | if ((BYTES_BIG_ENDIAN || WORDS_BIG_ENDIAN) | |
939 | && decl != NULL | |
940 | && offset > 0 | |
e53a16e7 | 941 | && GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (GET_MODE (new)) |
e314a036 JZ |
942 | && ((var_size = int_size_in_bytes (TREE_TYPE (decl))) > 0 |
943 | && var_size < GET_MODE_SIZE (GET_MODE (reg)))) | |
944 | { | |
945 | int offset_le; | |
946 | ||
947 | /* Convert machine endian to little endian WRT size of mode of REG. */ | |
948 | if (WORDS_BIG_ENDIAN) | |
949 | offset_le = ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset) | |
950 | / UNITS_PER_WORD) * UNITS_PER_WORD; | |
951 | else | |
952 | offset_le = (offset / UNITS_PER_WORD) * UNITS_PER_WORD; | |
953 | ||
954 | if (BYTES_BIG_ENDIAN) | |
955 | offset_le += ((GET_MODE_SIZE (GET_MODE (reg)) - 1 - offset) | |
956 | % UNITS_PER_WORD); | |
957 | else | |
958 | offset_le += offset % UNITS_PER_WORD; | |
959 | ||
960 | if (offset_le >= var_size) | |
961 | { | |
962 | /* MODE is wider than the variable so the new reg will cover | |
963 | the whole variable so the resulting OFFSET should be 0. */ | |
964 | offset = 0; | |
965 | } | |
966 | else | |
967 | { | |
968 | /* Convert little endian to machine endian WRT size of variable. */ | |
969 | if (WORDS_BIG_ENDIAN) | |
970 | offset = ((var_size - 1 - offset_le) | |
971 | / UNITS_PER_WORD) * UNITS_PER_WORD; | |
972 | else | |
973 | offset = (offset_le / UNITS_PER_WORD) * UNITS_PER_WORD; | |
974 | ||
975 | if (BYTES_BIG_ENDIAN) | |
976 | offset += ((var_size - 1 - offset_le) | |
977 | % UNITS_PER_WORD); | |
978 | else | |
979 | offset += offset_le % UNITS_PER_WORD; | |
980 | } | |
981 | } | |
982 | ||
a560d4d4 | 983 | REG_ATTRS (new) = get_reg_attrs (REG_EXPR (reg), |
502b8322 | 984 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
985 | } |
986 | ||
987 | /* Generate a register with same attributes as REG, but offsetted by | |
988 | OFFSET. */ | |
989 | ||
990 | rtx | |
991 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, | |
992 | int offset) | |
993 | { | |
994 | rtx new = gen_rtx_REG (mode, regno); | |
995 | ||
996 | update_reg_offset (new, reg, offset); | |
997 | return new; | |
998 | } | |
999 | ||
1000 | /* Generate a new pseudo-register with the same attributes as REG, but | |
1001 | offsetted by OFFSET. */ | |
1002 | ||
1003 | rtx | |
1004 | gen_reg_rtx_offset (rtx reg, enum machine_mode mode, int offset) | |
1005 | { | |
1006 | rtx new = gen_reg_rtx (mode); | |
1007 | ||
1008 | update_reg_offset (new, reg, offset); | |
a560d4d4 JH |
1009 | return new; |
1010 | } | |
1011 | ||
1012 | /* Set the decl for MEM to DECL. */ | |
1013 | ||
1014 | void | |
502b8322 | 1015 | set_reg_attrs_from_mem (rtx reg, rtx mem) |
a560d4d4 JH |
1016 | { |
1017 | if (MEM_OFFSET (mem) && GET_CODE (MEM_OFFSET (mem)) == CONST_INT) | |
1018 | REG_ATTRS (reg) | |
1019 | = get_reg_attrs (MEM_EXPR (mem), INTVAL (MEM_OFFSET (mem))); | |
1020 | } | |
1021 | ||
9d18e06b JZ |
1022 | /* Set the register attributes for registers contained in PARM_RTX. |
1023 | Use needed values from memory attributes of MEM. */ | |
1024 | ||
1025 | void | |
502b8322 | 1026 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1027 | { |
f8cfc6aa | 1028 | if (REG_P (parm_rtx)) |
9d18e06b JZ |
1029 | set_reg_attrs_from_mem (parm_rtx, mem); |
1030 | else if (GET_CODE (parm_rtx) == PARALLEL) | |
1031 | { | |
1032 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1033 | parameter goes both on the stack and in registers. */ | |
1034 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1035 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1036 | { | |
1037 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1038 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1039 | REG_ATTRS (XEXP (x, 0)) |
1040 | = get_reg_attrs (MEM_EXPR (mem), | |
1041 | INTVAL (XEXP (x, 1))); | |
1042 | } | |
1043 | } | |
1044 | } | |
1045 | ||
a560d4d4 JH |
1046 | /* Assign the RTX X to declaration T. */ |
1047 | void | |
502b8322 | 1048 | set_decl_rtl (tree t, rtx x) |
a560d4d4 | 1049 | { |
820cc88f | 1050 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; |
a560d4d4 | 1051 | |
fbe6ec81 JZ |
1052 | if (!x) |
1053 | return; | |
1054 | /* For register, we maintain the reverse information too. */ | |
f8cfc6aa | 1055 | if (REG_P (x)) |
fbe6ec81 JZ |
1056 | REG_ATTRS (x) = get_reg_attrs (t, 0); |
1057 | else if (GET_CODE (x) == SUBREG) | |
1058 | REG_ATTRS (SUBREG_REG (x)) | |
1059 | = get_reg_attrs (t, -SUBREG_BYTE (x)); | |
1060 | if (GET_CODE (x) == CONCAT) | |
1061 | { | |
1062 | if (REG_P (XEXP (x, 0))) | |
1063 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1064 | if (REG_P (XEXP (x, 1))) | |
1065 | REG_ATTRS (XEXP (x, 1)) | |
1066 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1067 | } | |
1068 | if (GET_CODE (x) == PARALLEL) | |
1069 | { | |
1070 | int i; | |
1071 | for (i = 0; i < XVECLEN (x, 0); i++) | |
1072 | { | |
1073 | rtx y = XVECEXP (x, 0, i); | |
1074 | if (REG_P (XEXP (y, 0))) | |
1075 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1076 | } | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | /* Assign the RTX X to parameter declaration T. */ | |
1081 | void | |
1082 | set_decl_incoming_rtl (tree t, rtx x) | |
1083 | { | |
1084 | DECL_INCOMING_RTL (t) = x; | |
1085 | ||
a560d4d4 JH |
1086 | if (!x) |
1087 | return; | |
4d6922ee | 1088 | /* For register, we maintain the reverse information too. */ |
f8cfc6aa | 1089 | if (REG_P (x)) |
a560d4d4 JH |
1090 | REG_ATTRS (x) = get_reg_attrs (t, 0); |
1091 | else if (GET_CODE (x) == SUBREG) | |
1092 | REG_ATTRS (SUBREG_REG (x)) | |
1093 | = get_reg_attrs (t, -SUBREG_BYTE (x)); | |
1094 | if (GET_CODE (x) == CONCAT) | |
1095 | { | |
1096 | if (REG_P (XEXP (x, 0))) | |
1097 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1098 | if (REG_P (XEXP (x, 1))) | |
1099 | REG_ATTRS (XEXP (x, 1)) | |
1100 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1101 | } | |
1102 | if (GET_CODE (x) == PARALLEL) | |
1103 | { | |
d4afac5b JZ |
1104 | int i, start; |
1105 | ||
1106 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1107 | both on the stack and in registers. */ | |
1108 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1109 | start = 0; | |
1110 | else | |
1111 | start = 1; | |
1112 | ||
1113 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1114 | { |
1115 | rtx y = XVECEXP (x, 0, i); | |
1116 | if (REG_P (XEXP (y, 0))) | |
1117 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | ||
754fdcca RK |
1122 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1123 | ||
1124 | void | |
502b8322 | 1125 | mark_user_reg (rtx reg) |
754fdcca RK |
1126 | { |
1127 | if (GET_CODE (reg) == CONCAT) | |
1128 | { | |
1129 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1130 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1131 | } | |
754fdcca | 1132 | else |
5b0264cb NS |
1133 | { |
1134 | gcc_assert (REG_P (reg)); | |
1135 | REG_USERVAR_P (reg) = 1; | |
1136 | } | |
754fdcca RK |
1137 | } |
1138 | ||
86fe05e0 RK |
1139 | /* Identify REG as a probable pointer register and show its alignment |
1140 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1141 | |
1142 | void | |
502b8322 | 1143 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1144 | { |
3502dc9c | 1145 | if (! REG_POINTER (reg)) |
00995e78 | 1146 | { |
3502dc9c | 1147 | REG_POINTER (reg) = 1; |
86fe05e0 | 1148 | |
00995e78 RE |
1149 | if (align) |
1150 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1151 | } | |
1152 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1153 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1154 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1155 | } |
1156 | ||
1157 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1158 | ||
1159 | int | |
502b8322 | 1160 | max_reg_num (void) |
23b2ce53 RS |
1161 | { |
1162 | return reg_rtx_no; | |
1163 | } | |
1164 | ||
1165 | /* Return 1 + the largest label number used so far in the current function. */ | |
1166 | ||
1167 | int | |
502b8322 | 1168 | max_label_num (void) |
23b2ce53 | 1169 | { |
23b2ce53 RS |
1170 | return label_num; |
1171 | } | |
1172 | ||
1173 | /* Return first label number used in this function (if any were used). */ | |
1174 | ||
1175 | int | |
502b8322 | 1176 | get_first_label_num (void) |
23b2ce53 RS |
1177 | { |
1178 | return first_label_num; | |
1179 | } | |
6de9cd9a DN |
1180 | |
1181 | /* If the rtx for label was created during the expansion of a nested | |
1182 | function, then first_label_num won't include this label number. | |
1183 | Fix this now so that array indicies work later. */ | |
1184 | ||
1185 | void | |
1186 | maybe_set_first_label_num (rtx x) | |
1187 | { | |
1188 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1189 | first_label_num = CODE_LABEL_NUMBER (x); | |
1190 | } | |
23b2ce53 RS |
1191 | \f |
1192 | /* Return a value representing some low-order bits of X, where the number | |
1193 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1194 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1195 | representation is returned. |
1196 | ||
1197 | This function handles the cases in common between gen_lowpart, below, | |
1198 | and two variants in cse.c and combine.c. These are the cases that can | |
1199 | be safely handled at all points in the compilation. | |
1200 | ||
1201 | If this is not a case we can handle, return 0. */ | |
1202 | ||
1203 | rtx | |
502b8322 | 1204 | gen_lowpart_common (enum machine_mode mode, rtx x) |
23b2ce53 | 1205 | { |
ddef6bc7 | 1206 | int msize = GET_MODE_SIZE (mode); |
550d1387 | 1207 | int xsize; |
ddef6bc7 | 1208 | int offset = 0; |
550d1387 GK |
1209 | enum machine_mode innermode; |
1210 | ||
1211 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1212 | so we have to make one up. Yuk. */ | |
1213 | innermode = GET_MODE (x); | |
db487452 R |
1214 | if (GET_CODE (x) == CONST_INT |
1215 | && msize * BITS_PER_UNIT <= HOST_BITS_PER_WIDE_INT) | |
550d1387 GK |
1216 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
1217 | else if (innermode == VOIDmode) | |
1218 | innermode = mode_for_size (HOST_BITS_PER_WIDE_INT * 2, MODE_INT, 0); | |
1219 | ||
1220 | xsize = GET_MODE_SIZE (innermode); | |
1221 | ||
5b0264cb | 1222 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1223 | |
550d1387 | 1224 | if (innermode == mode) |
23b2ce53 RS |
1225 | return x; |
1226 | ||
1227 | /* MODE must occupy no more words than the mode of X. */ | |
550d1387 GK |
1228 | if ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1229 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
23b2ce53 RS |
1230 | return 0; |
1231 | ||
53501a19 | 1232 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
3d8bf70f | 1233 | if (SCALAR_FLOAT_MODE_P (mode) && msize > xsize) |
53501a19 BS |
1234 | return 0; |
1235 | ||
550d1387 | 1236 | offset = subreg_lowpart_offset (mode, innermode); |
23b2ce53 RS |
1237 | |
1238 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1239 | && (GET_MODE_CLASS (mode) == MODE_INT |
1240 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1241 | { |
1242 | /* If we are getting the low-order part of something that has been | |
1243 | sign- or zero-extended, we can either just use the object being | |
1244 | extended or make a narrower extension. If we want an even smaller | |
1245 | piece than the size of the object being extended, call ourselves | |
1246 | recursively. | |
1247 | ||
1248 | This case is used mostly by combine and cse. */ | |
1249 | ||
1250 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1251 | return XEXP (x, 0); | |
550d1387 | 1252 | else if (msize < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) |
23b2ce53 | 1253 | return gen_lowpart_common (mode, XEXP (x, 0)); |
550d1387 | 1254 | else if (msize < xsize) |
3b80f6ca | 1255 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1256 | } |
f8cfc6aa | 1257 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
550d1387 GK |
1258 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
1259 | || GET_CODE (x) == CONST_DOUBLE || GET_CODE (x) == CONST_INT) | |
1260 | return simplify_gen_subreg (mode, x, innermode, offset); | |
8aada4ad | 1261 | |
23b2ce53 RS |
1262 | /* Otherwise, we can't do this. */ |
1263 | return 0; | |
1264 | } | |
1265 | \f | |
ccba022b | 1266 | rtx |
502b8322 | 1267 | gen_highpart (enum machine_mode mode, rtx x) |
ccba022b | 1268 | { |
ddef6bc7 | 1269 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1270 | rtx result; |
ddef6bc7 | 1271 | |
ccba022b RS |
1272 | /* This case loses if X is a subreg. To catch bugs early, |
1273 | complain if an invalid MODE is used even in other cases. */ | |
5b0264cb NS |
1274 | gcc_assert (msize <= UNITS_PER_WORD |
1275 | || msize == (unsigned int) GET_MODE_UNIT_SIZE (GET_MODE (x))); | |
ddef6bc7 | 1276 | |
e0e08ac2 JH |
1277 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1278 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb NS |
1279 | gcc_assert (result); |
1280 | ||
09482e0d JW |
1281 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1282 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1283 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1284 | if (MEM_P (result)) |
1285 | { | |
1286 | result = validize_mem (result); | |
1287 | gcc_assert (result); | |
1288 | } | |
1289 | ||
e0e08ac2 JH |
1290 | return result; |
1291 | } | |
5222e470 | 1292 | |
26d249eb | 1293 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1294 | be VOIDmode constant. */ |
1295 | rtx | |
502b8322 | 1296 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
5222e470 JH |
1297 | { |
1298 | if (GET_MODE (exp) != VOIDmode) | |
1299 | { | |
5b0264cb | 1300 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1301 | return gen_highpart (outermode, exp); |
1302 | } | |
1303 | return simplify_gen_subreg (outermode, exp, innermode, | |
1304 | subreg_highpart_offset (outermode, innermode)); | |
1305 | } | |
68252e27 | 1306 | |
e0e08ac2 JH |
1307 | /* Return offset in bytes to get OUTERMODE low part |
1308 | of the value in mode INNERMODE stored in memory in target format. */ | |
8698cce3 | 1309 | |
e0e08ac2 | 1310 | unsigned int |
502b8322 | 1311 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
e0e08ac2 JH |
1312 | { |
1313 | unsigned int offset = 0; | |
1314 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1315 | |
e0e08ac2 | 1316 | if (difference > 0) |
ccba022b | 1317 | { |
e0e08ac2 JH |
1318 | if (WORDS_BIG_ENDIAN) |
1319 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1320 | if (BYTES_BIG_ENDIAN) | |
1321 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1322 | } |
ddef6bc7 | 1323 | |
e0e08ac2 | 1324 | return offset; |
ccba022b | 1325 | } |
eea50aa0 | 1326 | |
e0e08ac2 JH |
1327 | /* Return offset in bytes to get OUTERMODE high part |
1328 | of the value in mode INNERMODE stored in memory in target format. */ | |
1329 | unsigned int | |
502b8322 | 1330 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
eea50aa0 JH |
1331 | { |
1332 | unsigned int offset = 0; | |
1333 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1334 | ||
5b0264cb | 1335 | gcc_assert (GET_MODE_SIZE (innermode) >= GET_MODE_SIZE (outermode)); |
e0e08ac2 | 1336 | |
eea50aa0 JH |
1337 | if (difference > 0) |
1338 | { | |
e0e08ac2 | 1339 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1340 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1341 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1342 | offset += difference % UNITS_PER_WORD; |
1343 | } | |
1344 | ||
e0e08ac2 | 1345 | return offset; |
eea50aa0 | 1346 | } |
ccba022b | 1347 | |
23b2ce53 RS |
1348 | /* Return 1 iff X, assumed to be a SUBREG, |
1349 | refers to the least significant part of its containing reg. | |
1350 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1351 | ||
1352 | int | |
fa233e34 | 1353 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1354 | { |
1355 | if (GET_CODE (x) != SUBREG) | |
1356 | return 1; | |
a3a03040 RK |
1357 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1358 | return 0; | |
23b2ce53 | 1359 | |
e0e08ac2 JH |
1360 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1361 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1362 | } |
1363 | \f | |
ddef6bc7 JJ |
1364 | /* Return subword OFFSET of operand OP. |
1365 | The word number, OFFSET, is interpreted as the word number starting | |
1366 | at the low-order address. OFFSET 0 is the low-order word if not | |
1367 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1368 | ||
1369 | If we cannot extract the required word, we return zero. Otherwise, | |
1370 | an rtx corresponding to the requested word will be returned. | |
1371 | ||
1372 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1373 | reload has completed, a valid address will always be returned. After | |
1374 | reload, if a valid address cannot be returned, we return zero. | |
1375 | ||
1376 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1377 | it is the responsibility of the caller. | |
1378 | ||
1379 | MODE is the mode of OP in case it is a CONST_INT. | |
1380 | ||
1381 | ??? This is still rather broken for some cases. The problem for the | |
1382 | moment is that all callers of this thing provide no 'goal mode' to | |
1383 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1384 | in a word based SUBREG world. |
1385 | Now use of this function can be deprecated by simplify_subreg in most | |
1386 | cases. | |
1387 | */ | |
ddef6bc7 JJ |
1388 | |
1389 | rtx | |
502b8322 | 1390 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
ddef6bc7 JJ |
1391 | { |
1392 | if (mode == VOIDmode) | |
1393 | mode = GET_MODE (op); | |
1394 | ||
5b0264cb | 1395 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1396 | |
30f7a378 | 1397 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1398 | if (mode != BLKmode |
1399 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1400 | return 0; | |
1401 | ||
30f7a378 | 1402 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1403 | if (mode != BLKmode |
1404 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1405 | return const0_rtx; | |
1406 | ||
ddef6bc7 | 1407 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1408 | if (MEM_P (op)) |
ddef6bc7 | 1409 | { |
f1ec5147 | 1410 | rtx new = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1411 | |
f1ec5147 RK |
1412 | if (! validate_address) |
1413 | return new; | |
1414 | ||
1415 | else if (reload_completed) | |
ddef6bc7 | 1416 | { |
f1ec5147 RK |
1417 | if (! strict_memory_address_p (word_mode, XEXP (new, 0))) |
1418 | return 0; | |
ddef6bc7 | 1419 | } |
f1ec5147 RK |
1420 | else |
1421 | return replace_equiv_address (new, XEXP (new, 0)); | |
ddef6bc7 JJ |
1422 | } |
1423 | ||
0631e0bf JH |
1424 | /* Rest can be handled by simplify_subreg. */ |
1425 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1426 | } |
1427 | ||
535a42b1 NS |
1428 | /* Similar to `operand_subword', but never return 0. If we can't |
1429 | extract the required subword, put OP into a register and try again. | |
1430 | The second attempt must succeed. We always validate the address in | |
1431 | this case. | |
23b2ce53 RS |
1432 | |
1433 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1434 | ||
1435 | rtx | |
502b8322 | 1436 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
23b2ce53 | 1437 | { |
ddef6bc7 | 1438 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1439 | |
1440 | if (result) | |
1441 | return result; | |
1442 | ||
1443 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1444 | { |
1445 | /* If this is a register which can not be accessed by words, copy it | |
1446 | to a pseudo register. */ | |
f8cfc6aa | 1447 | if (REG_P (op)) |
77e6b0eb JC |
1448 | op = copy_to_reg (op); |
1449 | else | |
1450 | op = force_reg (mode, op); | |
1451 | } | |
23b2ce53 | 1452 | |
ddef6bc7 | 1453 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1454 | gcc_assert (result); |
23b2ce53 RS |
1455 | |
1456 | return result; | |
1457 | } | |
1458 | \f | |
998d7deb RH |
1459 | /* Within a MEM_EXPR, we care about either (1) a component ref of a decl, |
1460 | or (2) a component ref of something variable. Represent the later with | |
1461 | a NULL expression. */ | |
1462 | ||
1463 | static tree | |
502b8322 | 1464 | component_ref_for_mem_expr (tree ref) |
998d7deb RH |
1465 | { |
1466 | tree inner = TREE_OPERAND (ref, 0); | |
1467 | ||
1468 | if (TREE_CODE (inner) == COMPONENT_REF) | |
1469 | inner = component_ref_for_mem_expr (inner); | |
c56e3582 RK |
1470 | else |
1471 | { | |
c56e3582 | 1472 | /* Now remove any conversions: they don't change what the underlying |
6fce44af | 1473 | object is. Likewise for SAVE_EXPR. */ |
c56e3582 RK |
1474 | while (TREE_CODE (inner) == NOP_EXPR || TREE_CODE (inner) == CONVERT_EXPR |
1475 | || TREE_CODE (inner) == NON_LVALUE_EXPR | |
1476 | || TREE_CODE (inner) == VIEW_CONVERT_EXPR | |
6fce44af RK |
1477 | || TREE_CODE (inner) == SAVE_EXPR) |
1478 | inner = TREE_OPERAND (inner, 0); | |
c56e3582 RK |
1479 | |
1480 | if (! DECL_P (inner)) | |
1481 | inner = NULL_TREE; | |
1482 | } | |
998d7deb RH |
1483 | |
1484 | if (inner == TREE_OPERAND (ref, 0)) | |
1485 | return ref; | |
1486 | else | |
3244e67d RS |
1487 | return build3 (COMPONENT_REF, TREE_TYPE (ref), inner, |
1488 | TREE_OPERAND (ref, 1), NULL_TREE); | |
998d7deb | 1489 | } |
173b24b9 | 1490 | |
2b3493c8 AK |
1491 | /* Returns 1 if both MEM_EXPR can be considered equal |
1492 | and 0 otherwise. */ | |
1493 | ||
1494 | int | |
4f588890 | 1495 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1496 | { |
1497 | if (expr1 == expr2) | |
1498 | return 1; | |
1499 | ||
1500 | if (! expr1 || ! expr2) | |
1501 | return 0; | |
1502 | ||
1503 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1504 | return 0; | |
1505 | ||
1506 | if (TREE_CODE (expr1) == COMPONENT_REF) | |
1507 | return | |
1508 | mem_expr_equal_p (TREE_OPERAND (expr1, 0), | |
1509 | TREE_OPERAND (expr2, 0)) | |
1510 | && mem_expr_equal_p (TREE_OPERAND (expr1, 1), /* field decl */ | |
1511 | TREE_OPERAND (expr2, 1)); | |
1512 | ||
1b096a0a | 1513 | if (INDIRECT_REF_P (expr1)) |
2b3493c8 AK |
1514 | return mem_expr_equal_p (TREE_OPERAND (expr1, 0), |
1515 | TREE_OPERAND (expr2, 0)); | |
2b3493c8 | 1516 | |
5b0264cb | 1517 | /* ARRAY_REFs, ARRAY_RANGE_REFs and BIT_FIELD_REFs should already |
2b3493c8 | 1518 | have been resolved here. */ |
5b0264cb NS |
1519 | gcc_assert (DECL_P (expr1)); |
1520 | ||
1521 | /* Decls with different pointers can't be equal. */ | |
1522 | return 0; | |
2b3493c8 AK |
1523 | } |
1524 | ||
173b24b9 RK |
1525 | /* Given REF, a MEM, and T, either the type of X or the expression |
1526 | corresponding to REF, set the memory attributes. OBJECTP is nonzero | |
6f1087be RH |
1527 | if we are making a new object of this type. BITPOS is nonzero if |
1528 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1529 | |
1530 | void | |
502b8322 AJ |
1531 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1532 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1533 | { |
4862826d | 1534 | alias_set_type alias = MEM_ALIAS_SET (ref); |
998d7deb | 1535 | tree expr = MEM_EXPR (ref); |
8ac61af7 RK |
1536 | rtx offset = MEM_OFFSET (ref); |
1537 | rtx size = MEM_SIZE (ref); | |
1538 | unsigned int align = MEM_ALIGN (ref); | |
6f1087be | 1539 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 RK |
1540 | tree type; |
1541 | ||
1542 | /* It can happen that type_for_mode was given a mode for which there | |
1543 | is no language-level type. In which case it returns NULL, which | |
1544 | we can see here. */ | |
1545 | if (t == NULL_TREE) | |
1546 | return; | |
1547 | ||
1548 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1549 | if (type == error_mark_node) |
1550 | return; | |
173b24b9 | 1551 | |
173b24b9 RK |
1552 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1553 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1554 | info. Callers should not set DECL_RTL until after the call to | |
1555 | set_mem_attributes. */ | |
5b0264cb | 1556 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1557 | |
738cc472 | 1558 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 RK |
1559 | front-end routine) and use it. */ |
1560 | alias = get_alias_set (t); | |
173b24b9 | 1561 | |
a5e9c810 | 1562 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
07cb6e8c JM |
1563 | MEM_IN_STRUCT_P (ref) |
1564 | = AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE; | |
f8ad8d7c | 1565 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1566 | |
8ac61af7 RK |
1567 | /* If we are making an object of this type, or if this is a DECL, we know |
1568 | that it is a scalar if the type is not an aggregate. */ | |
07cb6e8c JM |
1569 | if ((objectp || DECL_P (t)) |
1570 | && ! AGGREGATE_TYPE_P (type) | |
1571 | && TREE_CODE (type) != COMPLEX_TYPE) | |
173b24b9 RK |
1572 | MEM_SCALAR_P (ref) = 1; |
1573 | ||
c3d32120 RK |
1574 | /* We can set the alignment from the type if we are making an object, |
1575 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
7ccf35ed DN |
1576 | if (objectp || TREE_CODE (t) == INDIRECT_REF |
1577 | || TREE_CODE (t) == ALIGN_INDIRECT_REF | |
1578 | || TYPE_ALIGN_OK (type)) | |
c3d32120 | 1579 | align = MAX (align, TYPE_ALIGN (type)); |
7ccf35ed DN |
1580 | else |
1581 | if (TREE_CODE (t) == MISALIGNED_INDIRECT_REF) | |
1582 | { | |
1583 | if (integer_zerop (TREE_OPERAND (t, 1))) | |
1584 | /* We don't know anything about the alignment. */ | |
1585 | align = BITS_PER_UNIT; | |
1586 | else | |
1587 | align = tree_low_cst (TREE_OPERAND (t, 1), 1); | |
1588 | } | |
40c0668b | 1589 | |
738cc472 RK |
1590 | /* If the size is known, we can set that. */ |
1591 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
8ac61af7 | 1592 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
738cc472 | 1593 | |
80965c18 RK |
1594 | /* If T is not a type, we may be able to deduce some more information about |
1595 | the expression. */ | |
1596 | if (! TYPE_P (t)) | |
8ac61af7 | 1597 | { |
8476af98 | 1598 | tree base; |
389fdba0 | 1599 | |
8ac61af7 RK |
1600 | if (TREE_THIS_VOLATILE (t)) |
1601 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1602 | |
c56e3582 RK |
1603 | /* Now remove any conversions: they don't change what the underlying |
1604 | object is. Likewise for SAVE_EXPR. */ | |
8ac61af7 | 1605 | while (TREE_CODE (t) == NOP_EXPR || TREE_CODE (t) == CONVERT_EXPR |
c56e3582 RK |
1606 | || TREE_CODE (t) == NON_LVALUE_EXPR |
1607 | || TREE_CODE (t) == VIEW_CONVERT_EXPR | |
1608 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1609 | t = TREE_OPERAND (t, 0); |
1610 | ||
8476af98 RH |
1611 | /* We may look through structure-like accesses for the purposes of |
1612 | examining TREE_THIS_NOTRAP, but not array-like accesses. */ | |
1613 | base = t; | |
1614 | while (TREE_CODE (base) == COMPONENT_REF | |
1615 | || TREE_CODE (base) == REALPART_EXPR | |
1616 | || TREE_CODE (base) == IMAGPART_EXPR | |
1617 | || TREE_CODE (base) == BIT_FIELD_REF) | |
1618 | base = TREE_OPERAND (base, 0); | |
1619 | ||
1620 | if (DECL_P (base)) | |
1621 | { | |
1622 | if (CODE_CONTAINS_STRUCT (TREE_CODE (base), TS_DECL_WITH_VIS)) | |
1623 | MEM_NOTRAP_P (ref) = !DECL_WEAK (base); | |
1624 | else | |
1625 | MEM_NOTRAP_P (ref) = 1; | |
1626 | } | |
1627 | else | |
1628 | MEM_NOTRAP_P (ref) = TREE_THIS_NOTRAP (base); | |
1629 | ||
1630 | base = get_base_address (base); | |
1631 | if (base && DECL_P (base) | |
1632 | && TREE_READONLY (base) | |
1633 | && (TREE_STATIC (base) || DECL_EXTERNAL (base))) | |
1634 | { | |
1635 | tree base_type = TREE_TYPE (base); | |
1636 | gcc_assert (!(base_type && TYPE_NEEDS_CONSTRUCTING (base_type)) | |
1637 | || DECL_ARTIFICIAL (base)); | |
1638 | MEM_READONLY_P (ref) = 1; | |
1639 | } | |
1640 | ||
2039d7aa RH |
1641 | /* If this expression uses it's parent's alias set, mark it such |
1642 | that we won't change it. */ | |
1643 | if (component_uses_parent_alias_set (t)) | |
10b76d73 RK |
1644 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
1645 | ||
8ac61af7 RK |
1646 | /* If this is a decl, set the attributes of the MEM from it. */ |
1647 | if (DECL_P (t)) | |
1648 | { | |
998d7deb RH |
1649 | expr = t; |
1650 | offset = const0_rtx; | |
6f1087be | 1651 | apply_bitpos = bitpos; |
8ac61af7 RK |
1652 | size = (DECL_SIZE_UNIT (t) |
1653 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1654 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
68252e27 | 1655 | align = DECL_ALIGN (t); |
8ac61af7 RK |
1656 | } |
1657 | ||
40c0668b | 1658 | /* If this is a constant, we know the alignment. */ |
6615c446 | 1659 | else if (CONSTANT_CLASS_P (t)) |
9ddfb1a7 RK |
1660 | { |
1661 | align = TYPE_ALIGN (type); | |
1662 | #ifdef CONSTANT_ALIGNMENT | |
1663 | align = CONSTANT_ALIGNMENT (t, align); | |
1664 | #endif | |
1665 | } | |
998d7deb RH |
1666 | |
1667 | /* If this is a field reference and not a bit-field, record it. */ | |
1668 | /* ??? There is some information that can be gleened from bit-fields, | |
1669 | such as the word offset in the structure that might be modified. | |
1670 | But skip it for now. */ | |
1671 | else if (TREE_CODE (t) == COMPONENT_REF | |
1672 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1673 | { | |
1674 | expr = component_ref_for_mem_expr (t); | |
1675 | offset = const0_rtx; | |
6f1087be | 1676 | apply_bitpos = bitpos; |
998d7deb RH |
1677 | /* ??? Any reason the field size would be different than |
1678 | the size we got from the type? */ | |
1679 | } | |
1680 | ||
1681 | /* If this is an array reference, look for an outer field reference. */ | |
1682 | else if (TREE_CODE (t) == ARRAY_REF) | |
1683 | { | |
1684 | tree off_tree = size_zero_node; | |
1b1838b6 JW |
1685 | /* We can't modify t, because we use it at the end of the |
1686 | function. */ | |
1687 | tree t2 = t; | |
998d7deb RH |
1688 | |
1689 | do | |
1690 | { | |
1b1838b6 | 1691 | tree index = TREE_OPERAND (t2, 1); |
44de5aeb RK |
1692 | tree low_bound = array_ref_low_bound (t2); |
1693 | tree unit_size = array_ref_element_size (t2); | |
2567406a JH |
1694 | |
1695 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1696 | First subtract the lower bound, if any, in the type of the | |
44de5aeb RK |
1697 | index, then convert to sizetype and multiply by the size of |
1698 | the array element. */ | |
1699 | if (! integer_zerop (low_bound)) | |
4845b383 KH |
1700 | index = fold_build2 (MINUS_EXPR, TREE_TYPE (index), |
1701 | index, low_bound); | |
2567406a | 1702 | |
44de5aeb | 1703 | off_tree = size_binop (PLUS_EXPR, |
b6f65e3c RS |
1704 | size_binop (MULT_EXPR, |
1705 | fold_convert (sizetype, | |
1706 | index), | |
44de5aeb RK |
1707 | unit_size), |
1708 | off_tree); | |
1b1838b6 | 1709 | t2 = TREE_OPERAND (t2, 0); |
998d7deb | 1710 | } |
1b1838b6 | 1711 | while (TREE_CODE (t2) == ARRAY_REF); |
998d7deb | 1712 | |
1b1838b6 | 1713 | if (DECL_P (t2)) |
c67a1cf6 | 1714 | { |
1b1838b6 | 1715 | expr = t2; |
40cb04f1 | 1716 | offset = NULL; |
c67a1cf6 | 1717 | if (host_integerp (off_tree, 1)) |
40cb04f1 RH |
1718 | { |
1719 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1720 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1b1838b6 | 1721 | align = DECL_ALIGN (t2); |
fc555370 | 1722 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
40cb04f1 RH |
1723 | align = aoff; |
1724 | offset = GEN_INT (ioff); | |
6f1087be | 1725 | apply_bitpos = bitpos; |
40cb04f1 | 1726 | } |
c67a1cf6 | 1727 | } |
1b1838b6 | 1728 | else if (TREE_CODE (t2) == COMPONENT_REF) |
998d7deb | 1729 | { |
1b1838b6 | 1730 | expr = component_ref_for_mem_expr (t2); |
998d7deb | 1731 | if (host_integerp (off_tree, 1)) |
6f1087be RH |
1732 | { |
1733 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1734 | apply_bitpos = bitpos; | |
1735 | } | |
998d7deb RH |
1736 | /* ??? Any reason the field size would be different than |
1737 | the size we got from the type? */ | |
1738 | } | |
c67a1cf6 | 1739 | else if (flag_argument_noalias > 1 |
1b096a0a | 1740 | && (INDIRECT_REF_P (t2)) |
1b1838b6 | 1741 | && TREE_CODE (TREE_OPERAND (t2, 0)) == PARM_DECL) |
c67a1cf6 | 1742 | { |
1b1838b6 | 1743 | expr = t2; |
c67a1cf6 RH |
1744 | offset = NULL; |
1745 | } | |
1746 | } | |
1747 | ||
1748 | /* If this is a Fortran indirect argument reference, record the | |
1749 | parameter decl. */ | |
1750 | else if (flag_argument_noalias > 1 | |
1b096a0a | 1751 | && (INDIRECT_REF_P (t)) |
c67a1cf6 RH |
1752 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) |
1753 | { | |
1754 | expr = t; | |
1755 | offset = NULL; | |
998d7deb | 1756 | } |
8ac61af7 RK |
1757 | } |
1758 | ||
15c812e3 | 1759 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
1760 | bit position offset. Similarly, increase the size of the accessed |
1761 | object to contain the negative offset. */ | |
6f1087be | 1762 | if (apply_bitpos) |
8c317c5f RH |
1763 | { |
1764 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
1765 | if (size) | |
1766 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
1767 | } | |
6f1087be | 1768 | |
7ccf35ed DN |
1769 | if (TREE_CODE (t) == ALIGN_INDIRECT_REF) |
1770 | { | |
1771 | /* Force EXPR and OFFSE to NULL, since we don't know exactly what | |
1772 | we're overlapping. */ | |
1773 | offset = NULL; | |
1774 | expr = NULL; | |
1775 | } | |
1776 | ||
8ac61af7 | 1777 | /* Now set the attributes we computed above. */ |
10b76d73 | 1778 | MEM_ATTRS (ref) |
998d7deb | 1779 | = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref)); |
8ac61af7 RK |
1780 | |
1781 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
1782 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
738cc472 RK |
1783 | return; |
1784 | ||
8ac61af7 RK |
1785 | /* If it is a reference into an aggregate, this is part of an aggregate. |
1786 | Otherwise we don't know. */ | |
173b24b9 RK |
1787 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
1788 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
1789 | || TREE_CODE (t) == BIT_FIELD_REF) | |
1790 | MEM_IN_STRUCT_P (ref) = 1; | |
1791 | } | |
1792 | ||
6f1087be | 1793 | void |
502b8322 | 1794 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
1795 | { |
1796 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
1797 | } | |
1798 | ||
a560d4d4 JH |
1799 | /* Set the decl for MEM to DECL. */ |
1800 | ||
1801 | void | |
502b8322 | 1802 | set_mem_attrs_from_reg (rtx mem, rtx reg) |
a560d4d4 JH |
1803 | { |
1804 | MEM_ATTRS (mem) | |
1805 | = get_mem_attrs (MEM_ALIAS_SET (mem), REG_EXPR (reg), | |
1806 | GEN_INT (REG_OFFSET (reg)), | |
1807 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); | |
1808 | } | |
1809 | ||
173b24b9 RK |
1810 | /* Set the alias set of MEM to SET. */ |
1811 | ||
1812 | void | |
4862826d | 1813 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 1814 | { |
68252e27 | 1815 | #ifdef ENABLE_CHECKING |
173b24b9 | 1816 | /* If the new and old alias sets don't conflict, something is wrong. */ |
5b0264cb | 1817 | gcc_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
173b24b9 RK |
1818 | #endif |
1819 | ||
998d7deb | 1820 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
10b76d73 RK |
1821 | MEM_SIZE (mem), MEM_ALIGN (mem), |
1822 | GET_MODE (mem)); | |
173b24b9 | 1823 | } |
738cc472 | 1824 | |
d022d93e | 1825 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
1826 | |
1827 | void | |
502b8322 | 1828 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 1829 | { |
998d7deb | 1830 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
10b76d73 RK |
1831 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
1832 | GET_MODE (mem)); | |
738cc472 | 1833 | } |
1285011e | 1834 | |
998d7deb | 1835 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
1836 | |
1837 | void | |
502b8322 | 1838 | set_mem_expr (rtx mem, tree expr) |
1285011e RK |
1839 | { |
1840 | MEM_ATTRS (mem) | |
998d7deb | 1841 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
1285011e RK |
1842 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); |
1843 | } | |
998d7deb RH |
1844 | |
1845 | /* Set the offset of MEM to OFFSET. */ | |
1846 | ||
1847 | void | |
502b8322 | 1848 | set_mem_offset (rtx mem, rtx offset) |
998d7deb RH |
1849 | { |
1850 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1851 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
1852 | GET_MODE (mem)); | |
35aff10b AM |
1853 | } |
1854 | ||
1855 | /* Set the size of MEM to SIZE. */ | |
1856 | ||
1857 | void | |
502b8322 | 1858 | set_mem_size (rtx mem, rtx size) |
35aff10b AM |
1859 | { |
1860 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
1861 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
1862 | GET_MODE (mem)); | |
998d7deb | 1863 | } |
173b24b9 | 1864 | \f |
738cc472 RK |
1865 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
1866 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
1867 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
1868 | returned memory location is required to be valid. The memory | |
1869 | attributes are not changed. */ | |
23b2ce53 | 1870 | |
738cc472 | 1871 | static rtx |
502b8322 | 1872 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
23b2ce53 RS |
1873 | { |
1874 | rtx new; | |
1875 | ||
5b0264cb | 1876 | gcc_assert (MEM_P (memref)); |
23b2ce53 RS |
1877 | if (mode == VOIDmode) |
1878 | mode = GET_MODE (memref); | |
1879 | if (addr == 0) | |
1880 | addr = XEXP (memref, 0); | |
a74ff877 JH |
1881 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
1882 | && (!validate || memory_address_p (mode, addr))) | |
1883 | return memref; | |
23b2ce53 | 1884 | |
f1ec5147 | 1885 | if (validate) |
23b2ce53 | 1886 | { |
f1ec5147 | 1887 | if (reload_in_progress || reload_completed) |
5b0264cb | 1888 | gcc_assert (memory_address_p (mode, addr)); |
f1ec5147 RK |
1889 | else |
1890 | addr = memory_address (mode, addr); | |
23b2ce53 | 1891 | } |
750c9258 | 1892 | |
9b04c6a8 RK |
1893 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1894 | return memref; | |
1895 | ||
3b80f6ca | 1896 | new = gen_rtx_MEM (mode, addr); |
c6df88cb | 1897 | MEM_COPY_ATTRIBUTES (new, memref); |
23b2ce53 RS |
1898 | return new; |
1899 | } | |
792760b9 | 1900 | |
738cc472 RK |
1901 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
1902 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
1903 | |
1904 | rtx | |
502b8322 | 1905 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
f4ef873c | 1906 | { |
4e44c1ef | 1907 | rtx new = change_address_1 (memref, mode, addr, 1), size; |
738cc472 | 1908 | enum machine_mode mmode = GET_MODE (new); |
4e44c1ef JJ |
1909 | unsigned int align; |
1910 | ||
1911 | size = mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)); | |
1912 | align = mmode == BLKmode ? BITS_PER_UNIT : GET_MODE_ALIGNMENT (mmode); | |
c2f7bcc3 | 1913 | |
fdb1c7b3 JH |
1914 | /* If there are no changes, just return the original memory reference. */ |
1915 | if (new == memref) | |
4e44c1ef JJ |
1916 | { |
1917 | if (MEM_ATTRS (memref) == 0 | |
1918 | || (MEM_EXPR (memref) == NULL | |
1919 | && MEM_OFFSET (memref) == NULL | |
1920 | && MEM_SIZE (memref) == size | |
1921 | && MEM_ALIGN (memref) == align)) | |
1922 | return new; | |
1923 | ||
64fc7c00 | 1924 | new = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
4e44c1ef JJ |
1925 | MEM_COPY_ATTRIBUTES (new, memref); |
1926 | } | |
fdb1c7b3 | 1927 | |
738cc472 | 1928 | MEM_ATTRS (new) |
4e44c1ef | 1929 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, size, align, mmode); |
823e3574 | 1930 | |
738cc472 | 1931 | return new; |
f4ef873c | 1932 | } |
792760b9 | 1933 | |
738cc472 RK |
1934 | /* Return a memory reference like MEMREF, but with its mode changed |
1935 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 JJ |
1936 | nonzero, the memory address is forced to be valid. |
1937 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
1938 | and caller is responsible for adjusting MEMREF base register. */ | |
f1ec5147 RK |
1939 | |
1940 | rtx | |
502b8322 AJ |
1941 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
1942 | int validate, int adjust) | |
f1ec5147 | 1943 | { |
823e3574 | 1944 | rtx addr = XEXP (memref, 0); |
738cc472 RK |
1945 | rtx new; |
1946 | rtx memoffset = MEM_OFFSET (memref); | |
10b76d73 | 1947 | rtx size = 0; |
738cc472 | 1948 | unsigned int memalign = MEM_ALIGN (memref); |
823e3574 | 1949 | |
fdb1c7b3 JH |
1950 | /* If there are no changes, just return the original memory reference. */ |
1951 | if (mode == GET_MODE (memref) && !offset | |
1952 | && (!validate || memory_address_p (mode, addr))) | |
1953 | return memref; | |
1954 | ||
d14419e4 | 1955 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 1956 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
1957 | (plus (plus reg reg) const_int) -- so do this always. */ |
1958 | addr = copy_rtx (addr); | |
1959 | ||
4a78c787 RH |
1960 | if (adjust) |
1961 | { | |
1962 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
1963 | object, we can merge it into the LO_SUM. */ | |
1964 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
1965 | && offset >= 0 | |
1966 | && (unsigned HOST_WIDE_INT) offset | |
1967 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
1968 | addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0), | |
1969 | plus_constant (XEXP (addr, 1), offset)); | |
1970 | else | |
1971 | addr = plus_constant (addr, offset); | |
1972 | } | |
823e3574 | 1973 | |
738cc472 RK |
1974 | new = change_address_1 (memref, mode, addr, validate); |
1975 | ||
1976 | /* Compute the new values of the memory attributes due to this adjustment. | |
1977 | We add the offsets and update the alignment. */ | |
1978 | if (memoffset) | |
1979 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
1980 | ||
03bf2c23 RK |
1981 | /* Compute the new alignment by taking the MIN of the alignment and the |
1982 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
1983 | if zero. */ | |
1984 | if (offset != 0) | |
3bf1e984 RK |
1985 | memalign |
1986 | = MIN (memalign, | |
1987 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
738cc472 | 1988 | |
10b76d73 | 1989 | /* We can compute the size in a number of ways. */ |
a06ef755 RK |
1990 | if (GET_MODE (new) != BLKmode) |
1991 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new))); | |
10b76d73 RK |
1992 | else if (MEM_SIZE (memref)) |
1993 | size = plus_constant (MEM_SIZE (memref), -offset); | |
1994 | ||
998d7deb | 1995 | MEM_ATTRS (new) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
10b76d73 | 1996 | memoffset, size, memalign, GET_MODE (new)); |
738cc472 RK |
1997 | |
1998 | /* At some point, we should validate that this offset is within the object, | |
1999 | if all the appropriate values are known. */ | |
2000 | return new; | |
f1ec5147 RK |
2001 | } |
2002 | ||
630036c6 JJ |
2003 | /* Return a memory reference like MEMREF, but with its mode changed |
2004 | to MODE and its address changed to ADDR, which is assumed to be | |
2005 | MEMREF offseted by OFFSET bytes. If VALIDATE is | |
2006 | nonzero, the memory address is forced to be valid. */ | |
2007 | ||
2008 | rtx | |
502b8322 AJ |
2009 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
2010 | HOST_WIDE_INT offset, int validate) | |
630036c6 JJ |
2011 | { |
2012 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
2013 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
2014 | } | |
2015 | ||
8ac61af7 RK |
2016 | /* Return a memory reference like MEMREF, but whose address is changed by |
2017 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2018 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2019 | |
2020 | rtx | |
502b8322 | 2021 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2022 | { |
e3c8ea67 RH |
2023 | rtx new, addr = XEXP (memref, 0); |
2024 | ||
2025 | new = simplify_gen_binary (PLUS, Pmode, addr, offset); | |
2026 | ||
68252e27 | 2027 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2028 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2029 | |
2030 | However, if we did go and rearrange things, we can wind up not | |
2031 | being able to recognize the magic around pic_offset_table_rtx. | |
2032 | This stuff is fragile, and is yet another example of why it is | |
2033 | bad to expose PIC machinery too early. */ | |
2034 | if (! memory_address_p (GET_MODE (memref), new) | |
2035 | && GET_CODE (addr) == PLUS | |
2036 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2037 | { | |
2038 | addr = force_reg (GET_MODE (addr), addr); | |
2039 | new = simplify_gen_binary (PLUS, Pmode, addr, offset); | |
2040 | } | |
2041 | ||
f6041ed8 | 2042 | update_temp_slot_address (XEXP (memref, 0), new); |
e3c8ea67 | 2043 | new = change_address_1 (memref, VOIDmode, new, 1); |
0d4903b8 | 2044 | |
fdb1c7b3 JH |
2045 | /* If there are no changes, just return the original memory reference. */ |
2046 | if (new == memref) | |
2047 | return new; | |
2048 | ||
0d4903b8 RK |
2049 | /* Update the alignment to reflect the offset. Reset the offset, which |
2050 | we don't know. */ | |
2cc2d4bb RK |
2051 | MEM_ATTRS (new) |
2052 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, | |
9ceca302 | 2053 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
2cc2d4bb | 2054 | GET_MODE (new)); |
0d4903b8 RK |
2055 | return new; |
2056 | } | |
68252e27 | 2057 | |
792760b9 RK |
2058 | /* Return a memory reference like MEMREF, but with its address changed to |
2059 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2060 | to is the same, just the form of the address is being changed, such as | |
2061 | by putting something into a register. */ | |
2062 | ||
2063 | rtx | |
502b8322 | 2064 | replace_equiv_address (rtx memref, rtx addr) |
792760b9 | 2065 | { |
738cc472 RK |
2066 | /* change_address_1 copies the memory attribute structure without change |
2067 | and that's exactly what we want here. */ | |
40c0668b | 2068 | update_temp_slot_address (XEXP (memref, 0), addr); |
738cc472 | 2069 | return change_address_1 (memref, VOIDmode, addr, 1); |
792760b9 | 2070 | } |
738cc472 | 2071 | |
f1ec5147 RK |
2072 | /* Likewise, but the reference is not required to be valid. */ |
2073 | ||
2074 | rtx | |
502b8322 | 2075 | replace_equiv_address_nv (rtx memref, rtx addr) |
f1ec5147 | 2076 | { |
f1ec5147 RK |
2077 | return change_address_1 (memref, VOIDmode, addr, 0); |
2078 | } | |
e7dfe4bb RH |
2079 | |
2080 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2081 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2082 | cannot issue QImode memory operations and have to use SImode memory | |
2083 | operations plus masking logic. */ | |
2084 | ||
2085 | rtx | |
502b8322 | 2086 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb RH |
2087 | { |
2088 | rtx new = adjust_address_1 (memref, mode, offset, 1, 1); | |
2089 | tree expr = MEM_EXPR (new); | |
2090 | rtx memoffset = MEM_OFFSET (new); | |
2091 | unsigned int size = GET_MODE_SIZE (mode); | |
2092 | ||
fdb1c7b3 JH |
2093 | /* If there are no changes, just return the original memory reference. */ |
2094 | if (new == memref) | |
2095 | return new; | |
2096 | ||
e7dfe4bb RH |
2097 | /* If we don't know what offset we were at within the expression, then |
2098 | we can't know if we've overstepped the bounds. */ | |
fa1591cb | 2099 | if (! memoffset) |
e7dfe4bb RH |
2100 | expr = NULL_TREE; |
2101 | ||
2102 | while (expr) | |
2103 | { | |
2104 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2105 | { | |
2106 | tree field = TREE_OPERAND (expr, 1); | |
44de5aeb | 2107 | tree offset = component_ref_field_offset (expr); |
e7dfe4bb RH |
2108 | |
2109 | if (! DECL_SIZE_UNIT (field)) | |
2110 | { | |
2111 | expr = NULL_TREE; | |
2112 | break; | |
2113 | } | |
2114 | ||
2115 | /* Is the field at least as large as the access? If so, ok, | |
2116 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2117 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2118 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
e7dfe4bb RH |
2119 | && INTVAL (memoffset) >= 0) |
2120 | break; | |
2121 | ||
44de5aeb | 2122 | if (! host_integerp (offset, 1)) |
e7dfe4bb RH |
2123 | { |
2124 | expr = NULL_TREE; | |
2125 | break; | |
2126 | } | |
2127 | ||
2128 | expr = TREE_OPERAND (expr, 0); | |
44de5aeb RK |
2129 | memoffset |
2130 | = (GEN_INT (INTVAL (memoffset) | |
2131 | + tree_low_cst (offset, 1) | |
2132 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2133 | / BITS_PER_UNIT))); | |
e7dfe4bb RH |
2134 | } |
2135 | /* Similarly for the decl. */ | |
2136 | else if (DECL_P (expr) | |
2137 | && DECL_SIZE_UNIT (expr) | |
45f79783 | 2138 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
e7dfe4bb RH |
2139 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2140 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2141 | break; | |
2142 | else | |
2143 | { | |
2144 | /* The widened memory access overflows the expression, which means | |
2145 | that it could alias another expression. Zap it. */ | |
2146 | expr = NULL_TREE; | |
2147 | break; | |
2148 | } | |
2149 | } | |
2150 | ||
2151 | if (! expr) | |
2152 | memoffset = NULL_RTX; | |
2153 | ||
2154 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2155 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2156 | ||
2157 | MEM_ATTRS (new) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), | |
2158 | MEM_ALIGN (new), mode); | |
2159 | ||
2160 | return new; | |
2161 | } | |
23b2ce53 RS |
2162 | \f |
2163 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
2164 | ||
2165 | rtx | |
502b8322 | 2166 | gen_label_rtx (void) |
23b2ce53 | 2167 | { |
0dc36574 | 2168 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
502b8322 | 2169 | NULL, label_num++, NULL); |
23b2ce53 RS |
2170 | } |
2171 | \f | |
2172 | /* For procedure integration. */ | |
2173 | ||
23b2ce53 | 2174 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2175 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2176 | Used for an inline-procedure after copying the insn chain. */ |
2177 | ||
2178 | void | |
502b8322 | 2179 | set_new_first_and_last_insn (rtx first, rtx last) |
23b2ce53 | 2180 | { |
86fe05e0 RK |
2181 | rtx insn; |
2182 | ||
23b2ce53 RS |
2183 | first_insn = first; |
2184 | last_insn = last; | |
86fe05e0 RK |
2185 | cur_insn_uid = 0; |
2186 | ||
2187 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2188 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2189 | ||
2190 | cur_insn_uid++; | |
23b2ce53 | 2191 | } |
23b2ce53 | 2192 | \f |
750c9258 | 2193 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2194 | structure. This routine should only be called once. */ |
23b2ce53 | 2195 | |
fd743bc1 | 2196 | static void |
b4aaa77b | 2197 | unshare_all_rtl_1 (rtx insn) |
23b2ce53 | 2198 | { |
d1b81779 | 2199 | /* Unshare just about everything else. */ |
2c07f13b | 2200 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2201 | |
23b2ce53 RS |
2202 | /* Make sure the addresses of stack slots found outside the insn chain |
2203 | (such as, in DECL_RTL of a variable) are not shared | |
2204 | with the insn chain. | |
2205 | ||
2206 | This special care is necessary when the stack slot MEM does not | |
2207 | actually appear in the insn chain. If it does appear, its address | |
2208 | is unshared from all else at that point. */ | |
242b0ce6 | 2209 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
2210 | } |
2211 | ||
750c9258 | 2212 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2213 | structure, again. This is a fairly expensive thing to do so it |
2214 | should be done sparingly. */ | |
2215 | ||
2216 | void | |
502b8322 | 2217 | unshare_all_rtl_again (rtx insn) |
d1b81779 GK |
2218 | { |
2219 | rtx p; | |
624c87aa RE |
2220 | tree decl; |
2221 | ||
d1b81779 | 2222 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2223 | if (INSN_P (p)) |
d1b81779 GK |
2224 | { |
2225 | reset_used_flags (PATTERN (p)); | |
2226 | reset_used_flags (REG_NOTES (p)); | |
d1b81779 | 2227 | } |
624c87aa | 2228 | |
2d4aecb3 | 2229 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2230 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2231 | |
624c87aa RE |
2232 | /* Make sure that virtual parameters are not shared. */ |
2233 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
5eb2a9f2 | 2234 | set_used_flags (DECL_RTL (decl)); |
624c87aa RE |
2235 | |
2236 | reset_used_flags (stack_slot_list); | |
2237 | ||
b4aaa77b | 2238 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2239 | } |
2240 | ||
c2924966 | 2241 | unsigned int |
fd743bc1 PB |
2242 | unshare_all_rtl (void) |
2243 | { | |
b4aaa77b | 2244 | unshare_all_rtl_1 (get_insns ()); |
c2924966 | 2245 | return 0; |
d1b81779 GK |
2246 | } |
2247 | ||
ef330312 PB |
2248 | struct tree_opt_pass pass_unshare_all_rtl = |
2249 | { | |
defb77dc | 2250 | "unshare", /* name */ |
ef330312 PB |
2251 | NULL, /* gate */ |
2252 | unshare_all_rtl, /* execute */ | |
2253 | NULL, /* sub */ | |
2254 | NULL, /* next */ | |
2255 | 0, /* static_pass_number */ | |
2256 | 0, /* tv_id */ | |
2257 | 0, /* properties_required */ | |
2258 | 0, /* properties_provided */ | |
2259 | 0, /* properties_destroyed */ | |
2260 | 0, /* todo_flags_start */ | |
defb77dc | 2261 | TODO_dump_func, /* todo_flags_finish */ |
ef330312 PB |
2262 | 0 /* letter */ |
2263 | }; | |
2264 | ||
2265 | ||
2c07f13b JH |
2266 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2267 | Recursively does the same for subexpressions. */ | |
2268 | ||
2269 | static void | |
2270 | verify_rtx_sharing (rtx orig, rtx insn) | |
2271 | { | |
2272 | rtx x = orig; | |
2273 | int i; | |
2274 | enum rtx_code code; | |
2275 | const char *format_ptr; | |
2276 | ||
2277 | if (x == 0) | |
2278 | return; | |
2279 | ||
2280 | code = GET_CODE (x); | |
2281 | ||
2282 | /* These types may be freely shared. */ | |
2283 | ||
2284 | switch (code) | |
2285 | { | |
2286 | case REG: | |
2c07f13b JH |
2287 | case CONST_INT: |
2288 | case CONST_DOUBLE: | |
091a3ac7 | 2289 | case CONST_FIXED: |
2c07f13b JH |
2290 | case CONST_VECTOR: |
2291 | case SYMBOL_REF: | |
2292 | case LABEL_REF: | |
2293 | case CODE_LABEL: | |
2294 | case PC: | |
2295 | case CC0: | |
2296 | case SCRATCH: | |
2c07f13b | 2297 | return; |
3e89ed8d JH |
2298 | /* SCRATCH must be shared because they represent distinct values. */ |
2299 | case CLOBBER: | |
2300 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2301 | return; | |
2302 | break; | |
2c07f13b JH |
2303 | |
2304 | case CONST: | |
6fb5fa3c | 2305 | if (shared_const_p (orig)) |
2c07f13b JH |
2306 | return; |
2307 | break; | |
2308 | ||
2309 | case MEM: | |
2310 | /* A MEM is allowed to be shared if its address is constant. */ | |
2311 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2312 | || reload_completed || reload_in_progress) | |
2313 | return; | |
2314 | ||
2315 | break; | |
2316 | ||
2317 | default: | |
2318 | break; | |
2319 | } | |
2320 | ||
2321 | /* This rtx may not be shared. If it has already been seen, | |
2322 | replace it with a copy of itself. */ | |
1a2caa7a | 2323 | #ifdef ENABLE_CHECKING |
2c07f13b JH |
2324 | if (RTX_FLAG (x, used)) |
2325 | { | |
ab532386 | 2326 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2327 | debug_rtx (insn); |
ab532386 | 2328 | error ("shared rtx"); |
2c07f13b | 2329 | debug_rtx (x); |
ab532386 | 2330 | internal_error ("internal consistency failure"); |
2c07f13b | 2331 | } |
1a2caa7a NS |
2332 | #endif |
2333 | gcc_assert (!RTX_FLAG (x, used)); | |
2334 | ||
2c07f13b JH |
2335 | RTX_FLAG (x, used) = 1; |
2336 | ||
6614fd40 | 2337 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2338 | |
2339 | format_ptr = GET_RTX_FORMAT (code); | |
2340 | ||
2341 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2342 | { | |
2343 | switch (*format_ptr++) | |
2344 | { | |
2345 | case 'e': | |
2346 | verify_rtx_sharing (XEXP (x, i), insn); | |
2347 | break; | |
2348 | ||
2349 | case 'E': | |
2350 | if (XVEC (x, i) != NULL) | |
2351 | { | |
2352 | int j; | |
2353 | int len = XVECLEN (x, i); | |
2354 | ||
2355 | for (j = 0; j < len; j++) | |
2356 | { | |
1a2caa7a NS |
2357 | /* We allow sharing of ASM_OPERANDS inside single |
2358 | instruction. */ | |
2c07f13b | 2359 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2360 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2361 | == ASM_OPERANDS)) | |
2c07f13b JH |
2362 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2363 | else | |
2364 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2365 | } | |
2366 | } | |
2367 | break; | |
2368 | } | |
2369 | } | |
2370 | return; | |
2371 | } | |
2372 | ||
ba228239 | 2373 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2c07f13b JH |
2374 | sharing in between the subexpressions. */ |
2375 | ||
2376 | void | |
2377 | verify_rtl_sharing (void) | |
2378 | { | |
2379 | rtx p; | |
2380 | ||
2381 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2382 | if (INSN_P (p)) | |
2383 | { | |
2384 | reset_used_flags (PATTERN (p)); | |
2385 | reset_used_flags (REG_NOTES (p)); | |
2954a813 KK |
2386 | if (GET_CODE (PATTERN (p)) == SEQUENCE) |
2387 | { | |
2388 | int i; | |
2389 | rtx q, sequence = PATTERN (p); | |
2390 | ||
2391 | for (i = 0; i < XVECLEN (sequence, 0); i++) | |
2392 | { | |
2393 | q = XVECEXP (sequence, 0, i); | |
2394 | gcc_assert (INSN_P (q)); | |
2395 | reset_used_flags (PATTERN (q)); | |
2396 | reset_used_flags (REG_NOTES (q)); | |
2954a813 KK |
2397 | } |
2398 | } | |
2c07f13b JH |
2399 | } |
2400 | ||
2401 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2402 | if (INSN_P (p)) | |
2403 | { | |
2404 | verify_rtx_sharing (PATTERN (p), p); | |
2405 | verify_rtx_sharing (REG_NOTES (p), p); | |
2c07f13b JH |
2406 | } |
2407 | } | |
2408 | ||
d1b81779 GK |
2409 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
2410 | Assumes the mark bits are cleared at entry. */ | |
2411 | ||
2c07f13b JH |
2412 | void |
2413 | unshare_all_rtl_in_chain (rtx insn) | |
d1b81779 GK |
2414 | { |
2415 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2416 | if (INSN_P (insn)) |
d1b81779 GK |
2417 | { |
2418 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2419 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
d1b81779 GK |
2420 | } |
2421 | } | |
2422 | ||
2d4aecb3 | 2423 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
2424 | shared. We never replace the DECL_RTLs themselves with a copy, |
2425 | but expressions mentioned into a DECL_RTL cannot be shared with | |
2426 | expressions in the instruction stream. | |
2427 | ||
2428 | Note that reload may convert pseudo registers into memories in-place. | |
2429 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
2430 | reset the used flags on MEMs in the instruction stream, we must set | |
2431 | them again on MEMs that appear in DECL_RTLs. */ | |
2432 | ||
2d4aecb3 | 2433 | static void |
5eb2a9f2 | 2434 | set_used_decls (tree blk) |
2d4aecb3 AO |
2435 | { |
2436 | tree t; | |
2437 | ||
2438 | /* Mark decls. */ | |
2439 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c | 2440 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 2441 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
2442 | |
2443 | /* Now process sub-blocks. */ | |
2444 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
5eb2a9f2 | 2445 | set_used_decls (t); |
2d4aecb3 AO |
2446 | } |
2447 | ||
23b2ce53 | 2448 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
2449 | Recursively does the same for subexpressions. Uses |
2450 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
2451 | |
2452 | rtx | |
502b8322 | 2453 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2454 | { |
32b32b16 AP |
2455 | copy_rtx_if_shared_1 (&orig); |
2456 | return orig; | |
2457 | } | |
2458 | ||
ff954f39 AP |
2459 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
2460 | use. Recursively does the same for subexpressions. */ | |
2461 | ||
32b32b16 AP |
2462 | static void |
2463 | copy_rtx_if_shared_1 (rtx *orig1) | |
2464 | { | |
2465 | rtx x; | |
b3694847 SS |
2466 | int i; |
2467 | enum rtx_code code; | |
32b32b16 | 2468 | rtx *last_ptr; |
b3694847 | 2469 | const char *format_ptr; |
23b2ce53 | 2470 | int copied = 0; |
32b32b16 AP |
2471 | int length; |
2472 | ||
2473 | /* Repeat is used to turn tail-recursion into iteration. */ | |
2474 | repeat: | |
2475 | x = *orig1; | |
23b2ce53 RS |
2476 | |
2477 | if (x == 0) | |
32b32b16 | 2478 | return; |
23b2ce53 RS |
2479 | |
2480 | code = GET_CODE (x); | |
2481 | ||
2482 | /* These types may be freely shared. */ | |
2483 | ||
2484 | switch (code) | |
2485 | { | |
2486 | case REG: | |
23b2ce53 RS |
2487 | case CONST_INT: |
2488 | case CONST_DOUBLE: | |
091a3ac7 | 2489 | case CONST_FIXED: |
69ef87e2 | 2490 | case CONST_VECTOR: |
23b2ce53 | 2491 | case SYMBOL_REF: |
2c07f13b | 2492 | case LABEL_REF: |
23b2ce53 RS |
2493 | case CODE_LABEL: |
2494 | case PC: | |
2495 | case CC0: | |
2496 | case SCRATCH: | |
0f41302f | 2497 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 2498 | return; |
3e89ed8d JH |
2499 | case CLOBBER: |
2500 | if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
2501 | return; | |
2502 | break; | |
23b2ce53 | 2503 | |
b851ea09 | 2504 | case CONST: |
6fb5fa3c | 2505 | if (shared_const_p (x)) |
32b32b16 | 2506 | return; |
b851ea09 RK |
2507 | break; |
2508 | ||
23b2ce53 RS |
2509 | case INSN: |
2510 | case JUMP_INSN: | |
2511 | case CALL_INSN: | |
2512 | case NOTE: | |
23b2ce53 RS |
2513 | case BARRIER: |
2514 | /* The chain of insns is not being copied. */ | |
32b32b16 | 2515 | return; |
23b2ce53 | 2516 | |
e9a25f70 JL |
2517 | default: |
2518 | break; | |
23b2ce53 RS |
2519 | } |
2520 | ||
2521 | /* This rtx may not be shared. If it has already been seen, | |
2522 | replace it with a copy of itself. */ | |
2523 | ||
2adc7f12 | 2524 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2525 | { |
aacd3885 | 2526 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
2527 | copied = 1; |
2528 | } | |
2adc7f12 | 2529 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
2530 | |
2531 | /* Now scan the subexpressions recursively. | |
2532 | We can store any replaced subexpressions directly into X | |
2533 | since we know X is not shared! Any vectors in X | |
2534 | must be copied if X was copied. */ | |
2535 | ||
2536 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2537 | length = GET_RTX_LENGTH (code); |
2538 | last_ptr = NULL; | |
2539 | ||
2540 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2541 | { |
2542 | switch (*format_ptr++) | |
2543 | { | |
2544 | case 'e': | |
32b32b16 AP |
2545 | if (last_ptr) |
2546 | copy_rtx_if_shared_1 (last_ptr); | |
2547 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
2548 | break; |
2549 | ||
2550 | case 'E': | |
2551 | if (XVEC (x, i) != NULL) | |
2552 | { | |
b3694847 | 2553 | int j; |
f0722107 | 2554 | int len = XVECLEN (x, i); |
32b32b16 | 2555 | |
6614fd40 KH |
2556 | /* Copy the vector iff I copied the rtx and the length |
2557 | is nonzero. */ | |
f0722107 | 2558 | if (copied && len > 0) |
8f985ec4 | 2559 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
32b32b16 | 2560 | |
5d3cc252 | 2561 | /* Call recursively on all inside the vector. */ |
f0722107 | 2562 | for (j = 0; j < len; j++) |
32b32b16 AP |
2563 | { |
2564 | if (last_ptr) | |
2565 | copy_rtx_if_shared_1 (last_ptr); | |
2566 | last_ptr = &XVECEXP (x, i, j); | |
2567 | } | |
23b2ce53 RS |
2568 | } |
2569 | break; | |
2570 | } | |
2571 | } | |
32b32b16 AP |
2572 | *orig1 = x; |
2573 | if (last_ptr) | |
2574 | { | |
2575 | orig1 = last_ptr; | |
2576 | goto repeat; | |
2577 | } | |
2578 | return; | |
23b2ce53 RS |
2579 | } |
2580 | ||
2581 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2582 | to look for shared sub-parts. */ | |
2583 | ||
2584 | void | |
502b8322 | 2585 | reset_used_flags (rtx x) |
23b2ce53 | 2586 | { |
b3694847 SS |
2587 | int i, j; |
2588 | enum rtx_code code; | |
2589 | const char *format_ptr; | |
32b32b16 | 2590 | int length; |
23b2ce53 | 2591 | |
32b32b16 AP |
2592 | /* Repeat is used to turn tail-recursion into iteration. */ |
2593 | repeat: | |
23b2ce53 RS |
2594 | if (x == 0) |
2595 | return; | |
2596 | ||
2597 | code = GET_CODE (x); | |
2598 | ||
9faa82d8 | 2599 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2600 | for them. */ |
2601 | ||
2602 | switch (code) | |
2603 | { | |
2604 | case REG: | |
23b2ce53 RS |
2605 | case CONST_INT: |
2606 | case CONST_DOUBLE: | |
091a3ac7 | 2607 | case CONST_FIXED: |
69ef87e2 | 2608 | case CONST_VECTOR: |
23b2ce53 RS |
2609 | case SYMBOL_REF: |
2610 | case CODE_LABEL: | |
2611 | case PC: | |
2612 | case CC0: | |
2613 | return; | |
2614 | ||
2615 | case INSN: | |
2616 | case JUMP_INSN: | |
2617 | case CALL_INSN: | |
2618 | case NOTE: | |
2619 | case LABEL_REF: | |
2620 | case BARRIER: | |
2621 | /* The chain of insns is not being copied. */ | |
2622 | return; | |
750c9258 | 2623 | |
e9a25f70 JL |
2624 | default: |
2625 | break; | |
23b2ce53 RS |
2626 | } |
2627 | ||
2adc7f12 | 2628 | RTX_FLAG (x, used) = 0; |
23b2ce53 RS |
2629 | |
2630 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
2631 | length = GET_RTX_LENGTH (code); |
2632 | ||
2633 | for (i = 0; i < length; i++) | |
23b2ce53 RS |
2634 | { |
2635 | switch (*format_ptr++) | |
2636 | { | |
2637 | case 'e': | |
32b32b16 AP |
2638 | if (i == length-1) |
2639 | { | |
2640 | x = XEXP (x, i); | |
2641 | goto repeat; | |
2642 | } | |
23b2ce53 RS |
2643 | reset_used_flags (XEXP (x, i)); |
2644 | break; | |
2645 | ||
2646 | case 'E': | |
2647 | for (j = 0; j < XVECLEN (x, i); j++) | |
2648 | reset_used_flags (XVECEXP (x, i, j)); | |
2649 | break; | |
2650 | } | |
2651 | } | |
2652 | } | |
2c07f13b JH |
2653 | |
2654 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used | |
2655 | to look for shared sub-parts. */ | |
2656 | ||
2657 | void | |
2658 | set_used_flags (rtx x) | |
2659 | { | |
2660 | int i, j; | |
2661 | enum rtx_code code; | |
2662 | const char *format_ptr; | |
2663 | ||
2664 | if (x == 0) | |
2665 | return; | |
2666 | ||
2667 | code = GET_CODE (x); | |
2668 | ||
2669 | /* These types may be freely shared so we needn't do any resetting | |
2670 | for them. */ | |
2671 | ||
2672 | switch (code) | |
2673 | { | |
2674 | case REG: | |
2c07f13b JH |
2675 | case CONST_INT: |
2676 | case CONST_DOUBLE: | |
091a3ac7 | 2677 | case CONST_FIXED: |
2c07f13b JH |
2678 | case CONST_VECTOR: |
2679 | case SYMBOL_REF: | |
2680 | case CODE_LABEL: | |
2681 | case PC: | |
2682 | case CC0: | |
2683 | return; | |
2684 | ||
2685 | case INSN: | |
2686 | case JUMP_INSN: | |
2687 | case CALL_INSN: | |
2688 | case NOTE: | |
2689 | case LABEL_REF: | |
2690 | case BARRIER: | |
2691 | /* The chain of insns is not being copied. */ | |
2692 | return; | |
2693 | ||
2694 | default: | |
2695 | break; | |
2696 | } | |
2697 | ||
2698 | RTX_FLAG (x, used) = 1; | |
2699 | ||
2700 | format_ptr = GET_RTX_FORMAT (code); | |
2701 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2702 | { | |
2703 | switch (*format_ptr++) | |
2704 | { | |
2705 | case 'e': | |
2706 | set_used_flags (XEXP (x, i)); | |
2707 | break; | |
2708 | ||
2709 | case 'E': | |
2710 | for (j = 0; j < XVECLEN (x, i); j++) | |
2711 | set_used_flags (XVECEXP (x, i, j)); | |
2712 | break; | |
2713 | } | |
2714 | } | |
2715 | } | |
23b2ce53 RS |
2716 | \f |
2717 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2718 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2719 | OTHER must be valid as a SET_DEST. */ | |
2720 | ||
2721 | rtx | |
502b8322 | 2722 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
2723 | { |
2724 | while (1) | |
2725 | switch (GET_CODE (other)) | |
2726 | { | |
2727 | case SUBREG: | |
2728 | other = SUBREG_REG (other); | |
2729 | break; | |
2730 | case STRICT_LOW_PART: | |
2731 | case SIGN_EXTEND: | |
2732 | case ZERO_EXTEND: | |
2733 | other = XEXP (other, 0); | |
2734 | break; | |
2735 | default: | |
2736 | goto done; | |
2737 | } | |
2738 | done: | |
3c0cb5de | 2739 | if ((MEM_P (other) |
23b2ce53 | 2740 | && ! CONSTANT_P (x) |
f8cfc6aa | 2741 | && !REG_P (x) |
23b2ce53 | 2742 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 2743 | || (REG_P (other) |
23b2ce53 RS |
2744 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
2745 | || reg_mentioned_p (other, x)))) | |
2746 | { | |
2747 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2748 | emit_move_insn (temp, x); | |
2749 | return temp; | |
2750 | } | |
2751 | return x; | |
2752 | } | |
2753 | \f | |
2754 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2755 | ||
2756 | /* Return the first insn of the current sequence or current function. */ | |
2757 | ||
2758 | rtx | |
502b8322 | 2759 | get_insns (void) |
23b2ce53 RS |
2760 | { |
2761 | return first_insn; | |
2762 | } | |
2763 | ||
3dec4024 JH |
2764 | /* Specify a new insn as the first in the chain. */ |
2765 | ||
2766 | void | |
502b8322 | 2767 | set_first_insn (rtx insn) |
3dec4024 | 2768 | { |
5b0264cb | 2769 | gcc_assert (!PREV_INSN (insn)); |
3dec4024 JH |
2770 | first_insn = insn; |
2771 | } | |
2772 | ||
23b2ce53 RS |
2773 | /* Return the last insn emitted in current sequence or current function. */ |
2774 | ||
2775 | rtx | |
502b8322 | 2776 | get_last_insn (void) |
23b2ce53 RS |
2777 | { |
2778 | return last_insn; | |
2779 | } | |
2780 | ||
2781 | /* Specify a new insn as the last in the chain. */ | |
2782 | ||
2783 | void | |
502b8322 | 2784 | set_last_insn (rtx insn) |
23b2ce53 | 2785 | { |
5b0264cb | 2786 | gcc_assert (!NEXT_INSN (insn)); |
23b2ce53 RS |
2787 | last_insn = insn; |
2788 | } | |
2789 | ||
2790 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2791 | ||
2792 | rtx | |
502b8322 | 2793 | get_last_insn_anywhere (void) |
23b2ce53 RS |
2794 | { |
2795 | struct sequence_stack *stack; | |
2796 | if (last_insn) | |
2797 | return last_insn; | |
49ad7cfa | 2798 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2799 | if (stack->last != 0) |
2800 | return stack->last; | |
2801 | return 0; | |
2802 | } | |
2803 | ||
2a496e8b JDA |
2804 | /* Return the first nonnote insn emitted in current sequence or current |
2805 | function. This routine looks inside SEQUENCEs. */ | |
2806 | ||
2807 | rtx | |
502b8322 | 2808 | get_first_nonnote_insn (void) |
2a496e8b | 2809 | { |
91373fe8 JDA |
2810 | rtx insn = first_insn; |
2811 | ||
2812 | if (insn) | |
2813 | { | |
2814 | if (NOTE_P (insn)) | |
2815 | for (insn = next_insn (insn); | |
2816 | insn && NOTE_P (insn); | |
2817 | insn = next_insn (insn)) | |
2818 | continue; | |
2819 | else | |
2820 | { | |
2ca202e7 | 2821 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2822 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2823 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2824 | } | |
2825 | } | |
2a496e8b JDA |
2826 | |
2827 | return insn; | |
2828 | } | |
2829 | ||
2830 | /* Return the last nonnote insn emitted in current sequence or current | |
2831 | function. This routine looks inside SEQUENCEs. */ | |
2832 | ||
2833 | rtx | |
502b8322 | 2834 | get_last_nonnote_insn (void) |
2a496e8b | 2835 | { |
91373fe8 JDA |
2836 | rtx insn = last_insn; |
2837 | ||
2838 | if (insn) | |
2839 | { | |
2840 | if (NOTE_P (insn)) | |
2841 | for (insn = previous_insn (insn); | |
2842 | insn && NOTE_P (insn); | |
2843 | insn = previous_insn (insn)) | |
2844 | continue; | |
2845 | else | |
2846 | { | |
2ca202e7 | 2847 | if (NONJUMP_INSN_P (insn) |
91373fe8 JDA |
2848 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
2849 | insn = XVECEXP (PATTERN (insn), 0, | |
2850 | XVECLEN (PATTERN (insn), 0) - 1); | |
2851 | } | |
2852 | } | |
2a496e8b JDA |
2853 | |
2854 | return insn; | |
2855 | } | |
2856 | ||
23b2ce53 RS |
2857 | /* Return a number larger than any instruction's uid in this function. */ |
2858 | ||
2859 | int | |
502b8322 | 2860 | get_max_uid (void) |
23b2ce53 RS |
2861 | { |
2862 | return cur_insn_uid; | |
2863 | } | |
2864 | \f | |
2865 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2866 | of the sequence. */ | |
2867 | ||
9678086d KG |
2868 | #define NEXT_INSN_BODY do { \ |
2869 | if (insn) \ | |
2870 | { \ | |
2871 | insn = NEXT_INSN (insn); \ | |
2872 | if (insn && NONJUMP_INSN_P (insn) \ | |
2873 | && GET_CODE (PATTERN (insn)) == SEQUENCE) \ | |
2874 | insn = XVECEXP (PATTERN (insn), 0, 0); \ | |
2875 | } \ | |
2876 | return insn; \ | |
2877 | } while (0) | |
2878 | ||
23b2ce53 | 2879 | rtx |
502b8322 | 2880 | next_insn (rtx insn) |
23b2ce53 | 2881 | { |
9678086d KG |
2882 | NEXT_INSN_BODY; |
2883 | } | |
23b2ce53 | 2884 | |
9678086d KG |
2885 | const_rtx |
2886 | const_next_insn (const_rtx insn) | |
2887 | { | |
2888 | NEXT_INSN_BODY; | |
23b2ce53 RS |
2889 | } |
2890 | ||
9678086d KG |
2891 | #undef NEXT_INSN_BODY |
2892 | ||
23b2ce53 RS |
2893 | /* Return the previous insn. If it is a SEQUENCE, return the last insn |
2894 | of the sequence. */ | |
2895 | ||
9678086d KG |
2896 | #define PREVIOUS_INSN_BODY do { \ |
2897 | if (insn) \ | |
2898 | { \ | |
2899 | insn = PREV_INSN (insn); \ | |
2900 | if (insn && NONJUMP_INSN_P (insn) \ | |
2901 | && GET_CODE (PATTERN (insn)) == SEQUENCE) \ | |
2902 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); \ | |
2903 | } \ | |
2904 | return insn; \ | |
2905 | } while (0) | |
2906 | ||
23b2ce53 | 2907 | rtx |
502b8322 | 2908 | previous_insn (rtx insn) |
23b2ce53 | 2909 | { |
9678086d KG |
2910 | PREVIOUS_INSN_BODY; |
2911 | } | |
23b2ce53 | 2912 | |
9678086d KG |
2913 | const_rtx |
2914 | const_previous_insn (const_rtx insn) | |
2915 | { | |
2916 | PREVIOUS_INSN_BODY; | |
23b2ce53 RS |
2917 | } |
2918 | ||
9678086d KG |
2919 | #undef PREVIOUS_INSN_BODY |
2920 | ||
23b2ce53 RS |
2921 | /* Return the next insn after INSN that is not a NOTE. This routine does not |
2922 | look inside SEQUENCEs. */ | |
2923 | ||
9678086d KG |
2924 | #define NEXT_NONNOTE_INSN_BODY do { \ |
2925 | while (insn) \ | |
2926 | { \ | |
2927 | insn = NEXT_INSN (insn); \ | |
2928 | if (insn == 0 || !NOTE_P (insn)) \ | |
2929 | break; \ | |
2930 | } \ | |
2931 | return insn; \ | |
2932 | } while (0) | |
2933 | ||
23b2ce53 | 2934 | rtx |
502b8322 | 2935 | next_nonnote_insn (rtx insn) |
23b2ce53 | 2936 | { |
9678086d KG |
2937 | NEXT_NONNOTE_INSN_BODY; |
2938 | } | |
23b2ce53 | 2939 | |
9678086d KG |
2940 | const_rtx |
2941 | const_next_nonnote_insn (const_rtx insn) | |
2942 | { | |
2943 | NEXT_NONNOTE_INSN_BODY; | |
23b2ce53 RS |
2944 | } |
2945 | ||
9678086d KG |
2946 | #undef NEXT_NONNOTE_INSN_BODY |
2947 | ||
23b2ce53 RS |
2948 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
2949 | not look inside SEQUENCEs. */ | |
2950 | ||
9678086d KG |
2951 | #define PREV_NONNOTE_INSN_BODY do { \ |
2952 | while (insn) \ | |
2953 | { \ | |
2954 | insn = PREV_INSN (insn); \ | |
2955 | if (insn == 0 || !NOTE_P (insn)) \ | |
2956 | break; \ | |
2957 | } \ | |
2958 | return insn; \ | |
2959 | } while (0) | |
2960 | ||
23b2ce53 | 2961 | rtx |
502b8322 | 2962 | prev_nonnote_insn (rtx insn) |
23b2ce53 | 2963 | { |
9678086d KG |
2964 | PREV_NONNOTE_INSN_BODY; |
2965 | } | |
23b2ce53 | 2966 | |
9678086d KG |
2967 | const_rtx |
2968 | const_prev_nonnote_insn (const_rtx insn) | |
2969 | { | |
2970 | PREV_NONNOTE_INSN_BODY; | |
23b2ce53 RS |
2971 | } |
2972 | ||
9678086d KG |
2973 | #undef PREV_NONNOTE_INSN_BODY |
2974 | ||
23b2ce53 RS |
2975 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
2976 | or 0, if there is none. This routine does not look inside | |
0f41302f | 2977 | SEQUENCEs. */ |
23b2ce53 | 2978 | |
9678086d KG |
2979 | #define NEXT_REAL_INSN_BODY do { \ |
2980 | while (insn) \ | |
2981 | { \ | |
2982 | insn = NEXT_INSN (insn); \ | |
2983 | if (insn == 0 || INSN_P (insn)) \ | |
2984 | break; \ | |
2985 | } \ | |
2986 | return insn; \ | |
2987 | } while (0) | |
2988 | ||
23b2ce53 | 2989 | rtx |
502b8322 | 2990 | next_real_insn (rtx insn) |
23b2ce53 | 2991 | { |
9678086d KG |
2992 | NEXT_REAL_INSN_BODY; |
2993 | } | |
23b2ce53 | 2994 | |
9678086d KG |
2995 | const_rtx |
2996 | const_next_real_insn (const_rtx insn) | |
2997 | { | |
2998 | NEXT_REAL_INSN_BODY; | |
23b2ce53 RS |
2999 | } |
3000 | ||
9678086d KG |
3001 | #undef NEXT_REAL_INSN_BODY |
3002 | ||
23b2ce53 RS |
3003 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; |
3004 | or 0, if there is none. This routine does not look inside | |
3005 | SEQUENCEs. */ | |
3006 | ||
9678086d KG |
3007 | #define PREV_REAL_INSN_BODY do { \ |
3008 | while (insn) \ | |
3009 | { \ | |
3010 | insn = PREV_INSN (insn); \ | |
3011 | if (insn == 0 || INSN_P (insn)) \ | |
3012 | break; \ | |
3013 | } \ | |
3014 | return insn; \ | |
3015 | } while (0) | |
3016 | ||
23b2ce53 | 3017 | rtx |
502b8322 | 3018 | prev_real_insn (rtx insn) |
23b2ce53 | 3019 | { |
9678086d KG |
3020 | PREV_REAL_INSN_BODY; |
3021 | } | |
23b2ce53 | 3022 | |
9678086d KG |
3023 | const_rtx |
3024 | const_prev_real_insn (const_rtx insn) | |
3025 | { | |
3026 | PREV_REAL_INSN_BODY; | |
23b2ce53 RS |
3027 | } |
3028 | ||
9678086d KG |
3029 | #undef PREV_REAL_INSN_BODY |
3030 | ||
ee960939 OH |
3031 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3032 | This routine does not look inside SEQUENCEs. */ | |
3033 | ||
3034 | rtx | |
502b8322 | 3035 | last_call_insn (void) |
ee960939 OH |
3036 | { |
3037 | rtx insn; | |
3038 | ||
3039 | for (insn = get_last_insn (); | |
4b4bf941 | 3040 | insn && !CALL_P (insn); |
ee960939 OH |
3041 | insn = PREV_INSN (insn)) |
3042 | ; | |
3043 | ||
3044 | return insn; | |
3045 | } | |
3046 | ||
23b2ce53 RS |
3047 | /* Find the next insn after INSN that really does something. This routine |
3048 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3049 | same as next_real_insn. */ | |
3050 | ||
69732dcb | 3051 | int |
4f588890 | 3052 | active_insn_p (const_rtx insn) |
69732dcb | 3053 | { |
4b4bf941 JQ |
3054 | return (CALL_P (insn) || JUMP_P (insn) |
3055 | || (NONJUMP_INSN_P (insn) | |
23b8ba81 RH |
3056 | && (! reload_completed |
3057 | || (GET_CODE (PATTERN (insn)) != USE | |
3058 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3059 | } |
3060 | ||
9678086d KG |
3061 | #define NEXT_ACTIVE_INSN_BODY do { \ |
3062 | while (insn) \ | |
3063 | { \ | |
3064 | insn = NEXT_INSN (insn); \ | |
3065 | if (insn == 0 || active_insn_p (insn)) \ | |
3066 | break; \ | |
3067 | } \ | |
3068 | return insn;\ | |
3069 | } while (0) | |
3070 | ||
23b2ce53 | 3071 | rtx |
502b8322 | 3072 | next_active_insn (rtx insn) |
23b2ce53 | 3073 | { |
9678086d KG |
3074 | NEXT_ACTIVE_INSN_BODY; |
3075 | } | |
23b2ce53 | 3076 | |
9678086d KG |
3077 | const_rtx |
3078 | const_next_active_insn (const_rtx insn) | |
3079 | { | |
3080 | NEXT_ACTIVE_INSN_BODY; | |
23b2ce53 RS |
3081 | } |
3082 | ||
9678086d KG |
3083 | #undef NEXT_ACTIVE_INSN_BODY |
3084 | ||
23b2ce53 RS |
3085 | /* Find the last insn before INSN that really does something. This routine |
3086 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3087 | same as prev_real_insn. */ | |
3088 | ||
9678086d KG |
3089 | #define PREV_ACTIVE_INSN_BODY do { \ |
3090 | while (insn) \ | |
3091 | { \ | |
3092 | insn = PREV_INSN (insn);\ | |
3093 | if (insn == 0 || active_insn_p (insn)) \ | |
3094 | break; \ | |
3095 | } \ | |
3096 | return insn; \ | |
3097 | } while (0) | |
3098 | ||
23b2ce53 | 3099 | rtx |
502b8322 | 3100 | prev_active_insn (rtx insn) |
23b2ce53 | 3101 | { |
9678086d KG |
3102 | PREV_ACTIVE_INSN_BODY; |
3103 | } | |
23b2ce53 | 3104 | |
9678086d KG |
3105 | const_rtx |
3106 | const_prev_active_insn (const_rtx insn) | |
3107 | { | |
3108 | PREV_ACTIVE_INSN_BODY; | |
23b2ce53 RS |
3109 | } |
3110 | ||
9678086d KG |
3111 | #undef PREV_ACTIVE_INSN_BODY |
3112 | ||
23b2ce53 RS |
3113 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ |
3114 | ||
9678086d KG |
3115 | #define NEXT_LABEL_BODY do { \ |
3116 | while (insn) \ | |
3117 | { \ | |
3118 | insn = NEXT_INSN (insn); \ | |
3119 | if (insn == 0 || LABEL_P (insn)) \ | |
3120 | break; \ | |
3121 | } \ | |
3122 | return insn; \ | |
3123 | } while (0) | |
3124 | ||
23b2ce53 | 3125 | rtx |
502b8322 | 3126 | next_label (rtx insn) |
23b2ce53 | 3127 | { |
9678086d KG |
3128 | NEXT_LABEL_BODY; |
3129 | } | |
23b2ce53 | 3130 | |
9678086d KG |
3131 | const_rtx |
3132 | const_next_label (const_rtx insn) | |
3133 | { | |
3134 | NEXT_LABEL_BODY; | |
23b2ce53 RS |
3135 | } |
3136 | ||
9678086d KG |
3137 | #undef NEXT_LABEL_BODY |
3138 | ||
23b2ce53 RS |
3139 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ |
3140 | ||
9678086d KG |
3141 | #define PREV_LABEL_BODY do { \ |
3142 | while (insn) \ | |
3143 | { \ | |
3144 | insn = PREV_INSN (insn); \ | |
3145 | if (insn == 0 || LABEL_P (insn)) \ | |
3146 | break; \ | |
3147 | } \ | |
3148 | return insn; \ | |
3149 | } while (0) | |
3150 | ||
23b2ce53 | 3151 | rtx |
502b8322 | 3152 | prev_label (rtx insn) |
23b2ce53 | 3153 | { |
9678086d KG |
3154 | PREV_LABEL_BODY; |
3155 | } | |
23b2ce53 | 3156 | |
9678086d KG |
3157 | const_rtx |
3158 | const_prev_label (const_rtx insn) | |
3159 | { | |
3160 | PREV_LABEL_BODY; | |
23b2ce53 | 3161 | } |
6c2511d3 | 3162 | |
9678086d KG |
3163 | #undef PREV_LABEL_BODY |
3164 | ||
6c2511d3 RS |
3165 | /* Return the last label to mark the same position as LABEL. Return null |
3166 | if LABEL itself is null. */ | |
3167 | ||
3168 | rtx | |
3169 | skip_consecutive_labels (rtx label) | |
3170 | { | |
3171 | rtx insn; | |
3172 | ||
3173 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | |
3174 | if (LABEL_P (insn)) | |
3175 | label = insn; | |
3176 | ||
3177 | return label; | |
3178 | } | |
23b2ce53 RS |
3179 | \f |
3180 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
3181 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3182 | and REG_CC_USER notes so we can find it. */ | |
3183 | ||
3184 | void | |
502b8322 | 3185 | link_cc0_insns (rtx insn) |
c572e5ba JVA |
3186 | { |
3187 | rtx user = next_nonnote_insn (insn); | |
3188 | ||
4b4bf941 | 3189 | if (NONJUMP_INSN_P (user) && GET_CODE (PATTERN (user)) == SEQUENCE) |
c572e5ba JVA |
3190 | user = XVECEXP (PATTERN (user), 0, 0); |
3191 | ||
c5c76735 JL |
3192 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
3193 | REG_NOTES (user)); | |
3b80f6ca | 3194 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
3195 | } |
3196 | ||
23b2ce53 RS |
3197 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3198 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3199 | applied to the result of this function should yield INSN). | |
3200 | ||
3201 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3202 | is present, it contains the insn that uses CC0. | |
3203 | ||
3204 | Return 0 if we can't find the insn. */ | |
3205 | ||
3206 | rtx | |
502b8322 | 3207 | next_cc0_user (rtx insn) |
23b2ce53 | 3208 | { |
906c4e36 | 3209 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3210 | |
3211 | if (note) | |
3212 | return XEXP (note, 0); | |
3213 | ||
3214 | insn = next_nonnote_insn (insn); | |
4b4bf941 | 3215 | if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) |
23b2ce53 RS |
3216 | insn = XVECEXP (PATTERN (insn), 0, 0); |
3217 | ||
2c3c49de | 3218 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
3219 | return insn; |
3220 | ||
3221 | return 0; | |
3222 | } | |
3223 | ||
3224 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3225 | note, it is the previous insn. */ | |
3226 | ||
3227 | rtx | |
502b8322 | 3228 | prev_cc0_setter (rtx insn) |
23b2ce53 | 3229 | { |
906c4e36 | 3230 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3231 | |
3232 | if (note) | |
3233 | return XEXP (note, 0); | |
3234 | ||
3235 | insn = prev_nonnote_insn (insn); | |
5b0264cb | 3236 | gcc_assert (sets_cc0_p (PATTERN (insn))); |
23b2ce53 RS |
3237 | |
3238 | return insn; | |
3239 | } | |
3240 | #endif | |
e5bef2e4 | 3241 | |
594f8779 RZ |
3242 | #ifdef AUTO_INC_DEC |
3243 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ | |
3244 | ||
3245 | static int | |
3246 | find_auto_inc (rtx *xp, void *data) | |
3247 | { | |
3248 | rtx x = *xp; | |
3249 | rtx reg = data; | |
3250 | ||
3251 | if (GET_RTX_CLASS (GET_CODE (x)) != RTX_AUTOINC) | |
3252 | return 0; | |
3253 | ||
3254 | switch (GET_CODE (x)) | |
3255 | { | |
3256 | case PRE_DEC: | |
3257 | case PRE_INC: | |
3258 | case POST_DEC: | |
3259 | case POST_INC: | |
3260 | case PRE_MODIFY: | |
3261 | case POST_MODIFY: | |
3262 | if (rtx_equal_p (reg, XEXP (x, 0))) | |
3263 | return 1; | |
3264 | break; | |
3265 | ||
3266 | default: | |
3267 | gcc_unreachable (); | |
3268 | } | |
3269 | return -1; | |
3270 | } | |
3271 | #endif | |
3272 | ||
e5bef2e4 HB |
3273 | /* Increment the label uses for all labels present in rtx. */ |
3274 | ||
3275 | static void | |
502b8322 | 3276 | mark_label_nuses (rtx x) |
e5bef2e4 | 3277 | { |
b3694847 SS |
3278 | enum rtx_code code; |
3279 | int i, j; | |
3280 | const char *fmt; | |
e5bef2e4 HB |
3281 | |
3282 | code = GET_CODE (x); | |
7537fc90 | 3283 | if (code == LABEL_REF && LABEL_P (XEXP (x, 0))) |
e5bef2e4 HB |
3284 | LABEL_NUSES (XEXP (x, 0))++; |
3285 | ||
3286 | fmt = GET_RTX_FORMAT (code); | |
3287 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3288 | { | |
3289 | if (fmt[i] == 'e') | |
0fb7aeda | 3290 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3291 | else if (fmt[i] == 'E') |
0fb7aeda | 3292 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3293 | mark_label_nuses (XVECEXP (x, i, j)); |
3294 | } | |
3295 | } | |
3296 | ||
23b2ce53 RS |
3297 | \f |
3298 | /* Try splitting insns that can be split for better scheduling. | |
3299 | PAT is the pattern which might split. | |
3300 | TRIAL is the insn providing PAT. | |
cc2902df | 3301 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3302 | |
3303 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3304 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3305 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3306 | ||
3307 | rtx | |
502b8322 | 3308 | try_split (rtx pat, rtx trial, int last) |
23b2ce53 RS |
3309 | { |
3310 | rtx before = PREV_INSN (trial); | |
3311 | rtx after = NEXT_INSN (trial); | |
23b2ce53 | 3312 | int has_barrier = 0; |
1c7f7c66 | 3313 | rtx tem, note_retval; |
6b24c259 JH |
3314 | rtx note, seq; |
3315 | int probability; | |
599aedd9 RH |
3316 | rtx insn_last, insn; |
3317 | int njumps = 0; | |
6b24c259 JH |
3318 | |
3319 | if (any_condjump_p (trial) | |
3320 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3321 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3322 | probability = split_branch_probability; | |
3323 | ||
3324 | seq = split_insns (pat, trial); | |
3325 | ||
3326 | split_branch_probability = -1; | |
23b2ce53 RS |
3327 | |
3328 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3329 | We may need to handle this specially. */ | |
4b4bf941 | 3330 | if (after && BARRIER_P (after)) |
23b2ce53 RS |
3331 | { |
3332 | has_barrier = 1; | |
3333 | after = NEXT_INSN (after); | |
3334 | } | |
3335 | ||
599aedd9 RH |
3336 | if (!seq) |
3337 | return trial; | |
3338 | ||
3339 | /* Avoid infinite loop if any insn of the result matches | |
3340 | the original pattern. */ | |
3341 | insn_last = seq; | |
3342 | while (1) | |
23b2ce53 | 3343 | { |
599aedd9 RH |
3344 | if (INSN_P (insn_last) |
3345 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3346 | return trial; | |
3347 | if (!NEXT_INSN (insn_last)) | |
3348 | break; | |
3349 | insn_last = NEXT_INSN (insn_last); | |
3350 | } | |
750c9258 | 3351 | |
6fb5fa3c DB |
3352 | /* We will be adding the new sequence to the function. The splitters |
3353 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3354 | unshare_all_rtl_in_chain (seq); | |
3355 | ||
599aedd9 RH |
3356 | /* Mark labels. */ |
3357 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3358 | { | |
4b4bf941 | 3359 | if (JUMP_P (insn)) |
599aedd9 RH |
3360 | { |
3361 | mark_jump_label (PATTERN (insn), insn, 0); | |
3362 | njumps++; | |
3363 | if (probability != -1 | |
3364 | && any_condjump_p (insn) | |
3365 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3366 | { |
599aedd9 RH |
3367 | /* We can preserve the REG_BR_PROB notes only if exactly |
3368 | one jump is created, otherwise the machine description | |
3369 | is responsible for this step using | |
3370 | split_branch_probability variable. */ | |
5b0264cb | 3371 | gcc_assert (njumps == 1); |
599aedd9 RH |
3372 | REG_NOTES (insn) |
3373 | = gen_rtx_EXPR_LIST (REG_BR_PROB, | |
3374 | GEN_INT (probability), | |
3375 | REG_NOTES (insn)); | |
2f937369 | 3376 | } |
599aedd9 RH |
3377 | } |
3378 | } | |
3379 | ||
3380 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3381 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
4b4bf941 | 3382 | if (CALL_P (trial)) |
599aedd9 RH |
3383 | { |
3384 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3385 | if (CALL_P (insn)) |
599aedd9 | 3386 | { |
f6a1f3f6 RH |
3387 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3388 | while (*p) | |
3389 | p = &XEXP (*p, 1); | |
3390 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
599aedd9 RH |
3391 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3392 | } | |
3393 | } | |
4b5e8abe | 3394 | |
599aedd9 RH |
3395 | /* Copy notes, particularly those related to the CFG. */ |
3396 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3397 | { | |
3398 | switch (REG_NOTE_KIND (note)) | |
3399 | { | |
3400 | case REG_EH_REGION: | |
594f8779 | 3401 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3402 | { |
4b4bf941 | 3403 | if (CALL_P (insn) |
d3a583b1 | 3404 | || (flag_non_call_exceptions && INSN_P (insn) |
599aedd9 RH |
3405 | && may_trap_p (PATTERN (insn)))) |
3406 | REG_NOTES (insn) | |
3407 | = gen_rtx_EXPR_LIST (REG_EH_REGION, | |
3408 | XEXP (note, 0), | |
3409 | REG_NOTES (insn)); | |
2f937369 | 3410 | } |
599aedd9 | 3411 | break; |
216183ce | 3412 | |
599aedd9 RH |
3413 | case REG_NORETURN: |
3414 | case REG_SETJMP: | |
594f8779 | 3415 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3416 | { |
4b4bf941 | 3417 | if (CALL_P (insn)) |
599aedd9 RH |
3418 | REG_NOTES (insn) |
3419 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3420 | XEXP (note, 0), | |
3421 | REG_NOTES (insn)); | |
216183ce | 3422 | } |
599aedd9 | 3423 | break; |
d6e95df8 | 3424 | |
599aedd9 | 3425 | case REG_NON_LOCAL_GOTO: |
594f8779 | 3426 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3427 | { |
4b4bf941 | 3428 | if (JUMP_P (insn)) |
599aedd9 RH |
3429 | REG_NOTES (insn) |
3430 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3431 | XEXP (note, 0), | |
3432 | REG_NOTES (insn)); | |
2f937369 | 3433 | } |
599aedd9 | 3434 | break; |
e5bef2e4 | 3435 | |
594f8779 RZ |
3436 | #ifdef AUTO_INC_DEC |
3437 | case REG_INC: | |
3438 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) | |
3439 | { | |
3440 | rtx reg = XEXP (note, 0); | |
3441 | if (!FIND_REG_INC_NOTE (insn, reg) | |
3442 | && for_each_rtx (&PATTERN (insn), find_auto_inc, reg) > 0) | |
3443 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, reg, | |
3444 | REG_NOTES (insn)); | |
3445 | } | |
3446 | break; | |
3447 | #endif | |
3448 | ||
1c7f7c66 SL |
3449 | case REG_LIBCALL: |
3450 | /* Relink the insns with REG_LIBCALL note and with REG_RETVAL note | |
3451 | after split. */ | |
3452 | REG_NOTES (insn_last) | |
49317655 | 3453 | = gen_rtx_INSN_LIST (REG_LIBCALL, |
1c7f7c66 SL |
3454 | XEXP (note, 0), |
3455 | REG_NOTES (insn_last)); | |
3456 | ||
3457 | note_retval = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL); | |
3458 | XEXP (note_retval, 0) = insn_last; | |
3459 | break; | |
3460 | ||
599aedd9 RH |
3461 | default: |
3462 | break; | |
23b2ce53 | 3463 | } |
599aedd9 RH |
3464 | } |
3465 | ||
3466 | /* If there are LABELS inside the split insns increment the | |
3467 | usage count so we don't delete the label. */ | |
4b4bf941 | 3468 | if (NONJUMP_INSN_P (trial)) |
599aedd9 RH |
3469 | { |
3470 | insn = insn_last; | |
3471 | while (insn != NULL_RTX) | |
23b2ce53 | 3472 | { |
4b4bf941 | 3473 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3474 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3475 | |
599aedd9 RH |
3476 | insn = PREV_INSN (insn); |
3477 | } | |
23b2ce53 RS |
3478 | } |
3479 | ||
0435312e | 3480 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
599aedd9 RH |
3481 | |
3482 | delete_insn (trial); | |
3483 | if (has_barrier) | |
3484 | emit_barrier_after (tem); | |
3485 | ||
3486 | /* Recursively call try_split for each new insn created; by the | |
3487 | time control returns here that insn will be fully split, so | |
3488 | set LAST and continue from the insn after the one returned. | |
3489 | We can't use next_active_insn here since AFTER may be a note. | |
3490 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3491 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3492 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3493 | tem = try_split (PATTERN (tem), tem, 1); | |
3494 | ||
3495 | /* Return either the first or the last insn, depending on which was | |
3496 | requested. */ | |
3497 | return last | |
3498 | ? (after ? PREV_INSN (after) : last_insn) | |
3499 | : NEXT_INSN (before); | |
23b2ce53 RS |
3500 | } |
3501 | \f | |
3502 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3503 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
3504 | |
3505 | rtx | |
502b8322 | 3506 | make_insn_raw (rtx pattern) |
23b2ce53 | 3507 | { |
b3694847 | 3508 | rtx insn; |
23b2ce53 | 3509 | |
1f8f4a0b | 3510 | insn = rtx_alloc (INSN); |
23b2ce53 | 3511 | |
43127294 | 3512 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3513 | PATTERN (insn) = pattern; |
3514 | INSN_CODE (insn) = -1; | |
1632afca | 3515 | REG_NOTES (insn) = NULL; |
55e092c4 | 3516 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3517 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3518 | |
47984720 NC |
3519 | #ifdef ENABLE_RTL_CHECKING |
3520 | if (insn | |
2c3c49de | 3521 | && INSN_P (insn) |
47984720 NC |
3522 | && (returnjump_p (insn) |
3523 | || (GET_CODE (insn) == SET | |
3524 | && SET_DEST (insn) == pc_rtx))) | |
3525 | { | |
d4ee4d25 | 3526 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3527 | debug_rtx (insn); |
3528 | } | |
3529 | #endif | |
750c9258 | 3530 | |
23b2ce53 RS |
3531 | return insn; |
3532 | } | |
3533 | ||
2f937369 | 3534 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 3535 | |
38109dab | 3536 | rtx |
502b8322 | 3537 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3538 | { |
b3694847 | 3539 | rtx insn; |
23b2ce53 | 3540 | |
4b1f5e8c | 3541 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 3542 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3543 | |
3544 | PATTERN (insn) = pattern; | |
3545 | INSN_CODE (insn) = -1; | |
1632afca RS |
3546 | REG_NOTES (insn) = NULL; |
3547 | JUMP_LABEL (insn) = NULL; | |
55e092c4 | 3548 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3549 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3550 | |
3551 | return insn; | |
3552 | } | |
aff507f4 | 3553 | |
2f937369 | 3554 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 RK |
3555 | |
3556 | static rtx | |
502b8322 | 3557 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3558 | { |
b3694847 | 3559 | rtx insn; |
aff507f4 RK |
3560 | |
3561 | insn = rtx_alloc (CALL_INSN); | |
3562 | INSN_UID (insn) = cur_insn_uid++; | |
3563 | ||
3564 | PATTERN (insn) = pattern; | |
3565 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
3566 | REG_NOTES (insn) = NULL; |
3567 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
55e092c4 | 3568 | INSN_LOCATOR (insn) = curr_insn_locator (); |
ba4f7968 | 3569 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3570 | |
3571 | return insn; | |
3572 | } | |
23b2ce53 RS |
3573 | \f |
3574 | /* Add INSN to the end of the doubly-linked list. | |
3575 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3576 | ||
3577 | void | |
502b8322 | 3578 | add_insn (rtx insn) |
23b2ce53 RS |
3579 | { |
3580 | PREV_INSN (insn) = last_insn; | |
3581 | NEXT_INSN (insn) = 0; | |
3582 | ||
3583 | if (NULL != last_insn) | |
3584 | NEXT_INSN (last_insn) = insn; | |
3585 | ||
3586 | if (NULL == first_insn) | |
3587 | first_insn = insn; | |
3588 | ||
3589 | last_insn = insn; | |
3590 | } | |
3591 | ||
a0ae8e8d RK |
3592 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3593 | the next should be the only functions called to insert an insn once | |
ba213285 | 3594 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 3595 | SEQUENCE. */ |
23b2ce53 RS |
3596 | |
3597 | void | |
6fb5fa3c | 3598 | add_insn_after (rtx insn, rtx after, basic_block bb) |
23b2ce53 RS |
3599 | { |
3600 | rtx next = NEXT_INSN (after); | |
3601 | ||
5b0264cb | 3602 | gcc_assert (!optimize || !INSN_DELETED_P (after)); |
ba213285 | 3603 | |
23b2ce53 RS |
3604 | NEXT_INSN (insn) = next; |
3605 | PREV_INSN (insn) = after; | |
3606 | ||
3607 | if (next) | |
3608 | { | |
3609 | PREV_INSN (next) = insn; | |
4b4bf941 | 3610 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
23b2ce53 RS |
3611 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; |
3612 | } | |
3613 | else if (last_insn == after) | |
3614 | last_insn = insn; | |
3615 | else | |
3616 | { | |
49ad7cfa | 3617 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
3618 | /* Scan all pending sequences too. */ |
3619 | for (; stack; stack = stack->next) | |
3620 | if (after == stack->last) | |
fef0509b RK |
3621 | { |
3622 | stack->last = insn; | |
3623 | break; | |
3624 | } | |
a0ae8e8d | 3625 | |
5b0264cb | 3626 | gcc_assert (stack); |
23b2ce53 RS |
3627 | } |
3628 | ||
4b4bf941 JQ |
3629 | if (!BARRIER_P (after) |
3630 | && !BARRIER_P (insn) | |
3c030e88 JH |
3631 | && (bb = BLOCK_FOR_INSN (after))) |
3632 | { | |
3633 | set_block_for_insn (insn, bb); | |
38c1593d | 3634 | if (INSN_P (insn)) |
6fb5fa3c | 3635 | df_insn_rescan (insn); |
3c030e88 | 3636 | /* Should not happen as first in the BB is always |
a1f300c0 | 3637 | either NOTE or LABEL. */ |
a813c111 | 3638 | if (BB_END (bb) == after |
3c030e88 | 3639 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 3640 | && !BARRIER_P (insn) |
a38e7aa5 | 3641 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
a813c111 | 3642 | BB_END (bb) = insn; |
3c030e88 JH |
3643 | } |
3644 | ||
23b2ce53 | 3645 | NEXT_INSN (after) = insn; |
4b4bf941 | 3646 | if (NONJUMP_INSN_P (after) && GET_CODE (PATTERN (after)) == SEQUENCE) |
23b2ce53 RS |
3647 | { |
3648 | rtx sequence = PATTERN (after); | |
3649 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3650 | } | |
3651 | } | |
3652 | ||
a0ae8e8d | 3653 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
6fb5fa3c DB |
3654 | the previous should be the only functions called to insert an insn |
3655 | once delay slots have been filled since only they know how to | |
3656 | update a SEQUENCE. If BB is NULL, an attempt is made to infer the | |
3657 | bb from before. */ | |
a0ae8e8d RK |
3658 | |
3659 | void | |
6fb5fa3c | 3660 | add_insn_before (rtx insn, rtx before, basic_block bb) |
a0ae8e8d RK |
3661 | { |
3662 | rtx prev = PREV_INSN (before); | |
3663 | ||
5b0264cb | 3664 | gcc_assert (!optimize || !INSN_DELETED_P (before)); |
ba213285 | 3665 | |
a0ae8e8d RK |
3666 | PREV_INSN (insn) = prev; |
3667 | NEXT_INSN (insn) = before; | |
3668 | ||
3669 | if (prev) | |
3670 | { | |
3671 | NEXT_INSN (prev) = insn; | |
4b4bf941 | 3672 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
a0ae8e8d RK |
3673 | { |
3674 | rtx sequence = PATTERN (prev); | |
3675 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3676 | } | |
3677 | } | |
3678 | else if (first_insn == before) | |
3679 | first_insn = insn; | |
3680 | else | |
3681 | { | |
49ad7cfa | 3682 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
3683 | /* Scan all pending sequences too. */ |
3684 | for (; stack; stack = stack->next) | |
3685 | if (before == stack->first) | |
fef0509b RK |
3686 | { |
3687 | stack->first = insn; | |
3688 | break; | |
3689 | } | |
a0ae8e8d | 3690 | |
5b0264cb | 3691 | gcc_assert (stack); |
a0ae8e8d RK |
3692 | } |
3693 | ||
6fb5fa3c DB |
3694 | if (!bb |
3695 | && !BARRIER_P (before) | |
3696 | && !BARRIER_P (insn)) | |
3697 | bb = BLOCK_FOR_INSN (before); | |
3698 | ||
3699 | if (bb) | |
3c030e88 JH |
3700 | { |
3701 | set_block_for_insn (insn, bb); | |
38c1593d | 3702 | if (INSN_P (insn)) |
6fb5fa3c | 3703 | df_insn_rescan (insn); |
5b0264cb | 3704 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 3705 | LABEL. */ |
5b0264cb NS |
3706 | gcc_assert (BB_HEAD (bb) != insn |
3707 | /* Avoid clobbering of structure when creating new BB. */ | |
3708 | || BARRIER_P (insn) | |
a38e7aa5 | 3709 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 JH |
3710 | } |
3711 | ||
a0ae8e8d | 3712 | PREV_INSN (before) = insn; |
4b4bf941 | 3713 | if (NONJUMP_INSN_P (before) && GET_CODE (PATTERN (before)) == SEQUENCE) |
a0ae8e8d RK |
3714 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; |
3715 | } | |
3716 | ||
6fb5fa3c DB |
3717 | |
3718 | /* Replace insn with an deleted instruction note. */ | |
3719 | ||
3720 | void set_insn_deleted (rtx insn) | |
3721 | { | |
3722 | df_insn_delete (BLOCK_FOR_INSN (insn), INSN_UID (insn)); | |
3723 | PUT_CODE (insn, NOTE); | |
3724 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
3725 | } | |
3726 | ||
3727 | ||
89e99eea DB |
3728 | /* Remove an insn from its doubly-linked list. This function knows how |
3729 | to handle sequences. */ | |
3730 | void | |
502b8322 | 3731 | remove_insn (rtx insn) |
89e99eea DB |
3732 | { |
3733 | rtx next = NEXT_INSN (insn); | |
3734 | rtx prev = PREV_INSN (insn); | |
53c17031 JH |
3735 | basic_block bb; |
3736 | ||
6fb5fa3c DB |
3737 | /* Later in the code, the block will be marked dirty. */ |
3738 | df_insn_delete (NULL, INSN_UID (insn)); | |
3739 | ||
89e99eea DB |
3740 | if (prev) |
3741 | { | |
3742 | NEXT_INSN (prev) = next; | |
4b4bf941 | 3743 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea DB |
3744 | { |
3745 | rtx sequence = PATTERN (prev); | |
3746 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3747 | } | |
3748 | } | |
3749 | else if (first_insn == insn) | |
3750 | first_insn = next; | |
3751 | else | |
3752 | { | |
49ad7cfa | 3753 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3754 | /* Scan all pending sequences too. */ |
3755 | for (; stack; stack = stack->next) | |
3756 | if (insn == stack->first) | |
3757 | { | |
3758 | stack->first = next; | |
3759 | break; | |
3760 | } | |
3761 | ||
5b0264cb | 3762 | gcc_assert (stack); |
89e99eea DB |
3763 | } |
3764 | ||
3765 | if (next) | |
3766 | { | |
3767 | PREV_INSN (next) = prev; | |
4b4bf941 | 3768 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
89e99eea DB |
3769 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; |
3770 | } | |
3771 | else if (last_insn == insn) | |
3772 | last_insn = prev; | |
3773 | else | |
3774 | { | |
49ad7cfa | 3775 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3776 | /* Scan all pending sequences too. */ |
3777 | for (; stack; stack = stack->next) | |
3778 | if (insn == stack->last) | |
3779 | { | |
3780 | stack->last = prev; | |
3781 | break; | |
3782 | } | |
3783 | ||
5b0264cb | 3784 | gcc_assert (stack); |
89e99eea | 3785 | } |
4b4bf941 | 3786 | if (!BARRIER_P (insn) |
53c17031 JH |
3787 | && (bb = BLOCK_FOR_INSN (insn))) |
3788 | { | |
38c1593d | 3789 | if (INSN_P (insn)) |
6fb5fa3c | 3790 | df_set_bb_dirty (bb); |
a813c111 | 3791 | if (BB_HEAD (bb) == insn) |
53c17031 | 3792 | { |
3bf1e984 RK |
3793 | /* Never ever delete the basic block note without deleting whole |
3794 | basic block. */ | |
5b0264cb | 3795 | gcc_assert (!NOTE_P (insn)); |
a813c111 | 3796 | BB_HEAD (bb) = next; |
53c17031 | 3797 | } |
a813c111 SB |
3798 | if (BB_END (bb) == insn) |
3799 | BB_END (bb) = prev; | |
53c17031 | 3800 | } |
89e99eea DB |
3801 | } |
3802 | ||
ee960939 OH |
3803 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3804 | ||
3805 | void | |
502b8322 | 3806 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 3807 | { |
5b0264cb | 3808 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
3809 | |
3810 | /* Put the register usage information on the CALL. If there is already | |
3811 | some usage information, put ours at the end. */ | |
3812 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3813 | { | |
3814 | rtx link; | |
3815 | ||
3816 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3817 | link = XEXP (link, 1)) | |
3818 | ; | |
3819 | ||
3820 | XEXP (link, 1) = call_fusage; | |
3821 | } | |
3822 | else | |
3823 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3824 | } | |
3825 | ||
23b2ce53 RS |
3826 | /* Delete all insns made since FROM. |
3827 | FROM becomes the new last instruction. */ | |
3828 | ||
3829 | void | |
502b8322 | 3830 | delete_insns_since (rtx from) |
23b2ce53 RS |
3831 | { |
3832 | if (from == 0) | |
3833 | first_insn = 0; | |
3834 | else | |
3835 | NEXT_INSN (from) = 0; | |
3836 | last_insn = from; | |
3837 | } | |
3838 | ||
5dab5552 MS |
3839 | /* This function is deprecated, please use sequences instead. |
3840 | ||
3841 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
3842 | The insns to be moved are those between FROM and TO. |
3843 | They are moved to a new position after the insn AFTER. | |
3844 | AFTER must not be FROM or TO or any insn in between. | |
3845 | ||
3846 | This function does not know about SEQUENCEs and hence should not be | |
3847 | called after delay-slot filling has been done. */ | |
3848 | ||
3849 | void | |
502b8322 | 3850 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
23b2ce53 RS |
3851 | { |
3852 | /* Splice this bunch out of where it is now. */ | |
3853 | if (PREV_INSN (from)) | |
3854 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3855 | if (NEXT_INSN (to)) | |
3856 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
3857 | if (last_insn == to) | |
3858 | last_insn = PREV_INSN (from); | |
3859 | if (first_insn == from) | |
3860 | first_insn = NEXT_INSN (to); | |
3861 | ||
3862 | /* Make the new neighbors point to it and it to them. */ | |
3863 | if (NEXT_INSN (after)) | |
3864 | PREV_INSN (NEXT_INSN (after)) = to; | |
3865 | ||
3866 | NEXT_INSN (to) = NEXT_INSN (after); | |
3867 | PREV_INSN (from) = after; | |
3868 | NEXT_INSN (after) = from; | |
3869 | if (after == last_insn) | |
3870 | last_insn = to; | |
3871 | } | |
3872 | ||
3c030e88 JH |
3873 | /* Same as function above, but take care to update BB boundaries. */ |
3874 | void | |
502b8322 | 3875 | reorder_insns (rtx from, rtx to, rtx after) |
3c030e88 JH |
3876 | { |
3877 | rtx prev = PREV_INSN (from); | |
3878 | basic_block bb, bb2; | |
3879 | ||
3880 | reorder_insns_nobb (from, to, after); | |
3881 | ||
4b4bf941 | 3882 | if (!BARRIER_P (after) |
3c030e88 JH |
3883 | && (bb = BLOCK_FOR_INSN (after))) |
3884 | { | |
3885 | rtx x; | |
6fb5fa3c | 3886 | df_set_bb_dirty (bb); |
68252e27 | 3887 | |
4b4bf941 | 3888 | if (!BARRIER_P (from) |
3c030e88 JH |
3889 | && (bb2 = BLOCK_FOR_INSN (from))) |
3890 | { | |
a813c111 SB |
3891 | if (BB_END (bb2) == to) |
3892 | BB_END (bb2) = prev; | |
6fb5fa3c | 3893 | df_set_bb_dirty (bb2); |
3c030e88 JH |
3894 | } |
3895 | ||
a813c111 SB |
3896 | if (BB_END (bb) == after) |
3897 | BB_END (bb) = to; | |
3c030e88 JH |
3898 | |
3899 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 3900 | if (!BARRIER_P (x)) |
6fb5fa3c DB |
3901 | { |
3902 | set_block_for_insn (x, bb); | |
3903 | df_insn_change_bb (x); | |
3904 | } | |
3c030e88 JH |
3905 | } |
3906 | } | |
3907 | ||
23b2ce53 | 3908 | \f |
2f937369 DM |
3909 | /* Emit insn(s) of given code and pattern |
3910 | at a specified place within the doubly-linked list. | |
23b2ce53 | 3911 | |
2f937369 DM |
3912 | All of the emit_foo global entry points accept an object |
3913 | X which is either an insn list or a PATTERN of a single | |
3914 | instruction. | |
23b2ce53 | 3915 | |
2f937369 DM |
3916 | There are thus a few canonical ways to generate code and |
3917 | emit it at a specific place in the instruction stream. For | |
3918 | example, consider the instruction named SPOT and the fact that | |
3919 | we would like to emit some instructions before SPOT. We might | |
3920 | do it like this: | |
23b2ce53 | 3921 | |
2f937369 DM |
3922 | start_sequence (); |
3923 | ... emit the new instructions ... | |
3924 | insns_head = get_insns (); | |
3925 | end_sequence (); | |
23b2ce53 | 3926 | |
2f937369 | 3927 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 3928 | |
2f937369 DM |
3929 | It used to be common to generate SEQUENCE rtl instead, but that |
3930 | is a relic of the past which no longer occurs. The reason is that | |
3931 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
3932 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 3933 | |
2f937369 | 3934 | /* Make X be output before the instruction BEFORE. */ |
23b2ce53 RS |
3935 | |
3936 | rtx | |
6fb5fa3c | 3937 | emit_insn_before_noloc (rtx x, rtx before, basic_block bb) |
23b2ce53 | 3938 | { |
2f937369 | 3939 | rtx last = before; |
b3694847 | 3940 | rtx insn; |
23b2ce53 | 3941 | |
5b0264cb | 3942 | gcc_assert (before); |
2f937369 DM |
3943 | |
3944 | if (x == NULL_RTX) | |
3945 | return last; | |
3946 | ||
3947 | switch (GET_CODE (x)) | |
23b2ce53 | 3948 | { |
2f937369 DM |
3949 | case INSN: |
3950 | case JUMP_INSN: | |
3951 | case CALL_INSN: | |
3952 | case CODE_LABEL: | |
3953 | case BARRIER: | |
3954 | case NOTE: | |
3955 | insn = x; | |
3956 | while (insn) | |
3957 | { | |
3958 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 3959 | add_insn_before (insn, before, bb); |
2f937369 DM |
3960 | last = insn; |
3961 | insn = next; | |
3962 | } | |
3963 | break; | |
3964 | ||
3965 | #ifdef ENABLE_RTL_CHECKING | |
3966 | case SEQUENCE: | |
5b0264cb | 3967 | gcc_unreachable (); |
2f937369 DM |
3968 | break; |
3969 | #endif | |
3970 | ||
3971 | default: | |
3972 | last = make_insn_raw (x); | |
6fb5fa3c | 3973 | add_insn_before (last, before, bb); |
2f937369 | 3974 | break; |
23b2ce53 RS |
3975 | } |
3976 | ||
2f937369 | 3977 | return last; |
23b2ce53 RS |
3978 | } |
3979 | ||
2f937369 | 3980 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
3981 | and output it before the instruction BEFORE. */ |
3982 | ||
3983 | rtx | |
a7102479 | 3984 | emit_jump_insn_before_noloc (rtx x, rtx before) |
23b2ce53 | 3985 | { |
d950dee3 | 3986 | rtx insn, last = NULL_RTX; |
aff507f4 | 3987 | |
5b0264cb | 3988 | gcc_assert (before); |
2f937369 DM |
3989 | |
3990 | switch (GET_CODE (x)) | |
aff507f4 | 3991 | { |
2f937369 DM |
3992 | case INSN: |
3993 | case JUMP_INSN: | |
3994 | case CALL_INSN: | |
3995 | case CODE_LABEL: | |
3996 | case BARRIER: | |
3997 | case NOTE: | |
3998 | insn = x; | |
3999 | while (insn) | |
4000 | { | |
4001 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4002 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4003 | last = insn; |
4004 | insn = next; | |
4005 | } | |
4006 | break; | |
4007 | ||
4008 | #ifdef ENABLE_RTL_CHECKING | |
4009 | case SEQUENCE: | |
5b0264cb | 4010 | gcc_unreachable (); |
2f937369 DM |
4011 | break; |
4012 | #endif | |
4013 | ||
4014 | default: | |
4015 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4016 | add_insn_before (last, before, NULL); |
2f937369 | 4017 | break; |
aff507f4 RK |
4018 | } |
4019 | ||
2f937369 | 4020 | return last; |
23b2ce53 RS |
4021 | } |
4022 | ||
2f937369 | 4023 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4024 | and output it before the instruction BEFORE. */ |
4025 | ||
4026 | rtx | |
a7102479 | 4027 | emit_call_insn_before_noloc (rtx x, rtx before) |
969d70ca | 4028 | { |
d950dee3 | 4029 | rtx last = NULL_RTX, insn; |
969d70ca | 4030 | |
5b0264cb | 4031 | gcc_assert (before); |
2f937369 DM |
4032 | |
4033 | switch (GET_CODE (x)) | |
969d70ca | 4034 | { |
2f937369 DM |
4035 | case INSN: |
4036 | case JUMP_INSN: | |
4037 | case CALL_INSN: | |
4038 | case CODE_LABEL: | |
4039 | case BARRIER: | |
4040 | case NOTE: | |
4041 | insn = x; | |
4042 | while (insn) | |
4043 | { | |
4044 | rtx next = NEXT_INSN (insn); | |
6fb5fa3c | 4045 | add_insn_before (insn, before, NULL); |
2f937369 DM |
4046 | last = insn; |
4047 | insn = next; | |
4048 | } | |
4049 | break; | |
4050 | ||
4051 | #ifdef ENABLE_RTL_CHECKING | |
4052 | case SEQUENCE: | |
5b0264cb | 4053 | gcc_unreachable (); |
2f937369 DM |
4054 | break; |
4055 | #endif | |
4056 | ||
4057 | default: | |
4058 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4059 | add_insn_before (last, before, NULL); |
2f937369 | 4060 | break; |
969d70ca JH |
4061 | } |
4062 | ||
2f937369 | 4063 | return last; |
969d70ca JH |
4064 | } |
4065 | ||
23b2ce53 | 4066 | /* Make an insn of code BARRIER |
e881bb1b | 4067 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
4068 | |
4069 | rtx | |
502b8322 | 4070 | emit_barrier_before (rtx before) |
23b2ce53 | 4071 | { |
b3694847 | 4072 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4073 | |
4074 | INSN_UID (insn) = cur_insn_uid++; | |
4075 | ||
6fb5fa3c | 4076 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4077 | return insn; |
4078 | } | |
4079 | ||
e881bb1b RH |
4080 | /* Emit the label LABEL before the insn BEFORE. */ |
4081 | ||
4082 | rtx | |
502b8322 | 4083 | emit_label_before (rtx label, rtx before) |
e881bb1b RH |
4084 | { |
4085 | /* This can be called twice for the same label as a result of the | |
4086 | confusion that follows a syntax error! So make it harmless. */ | |
4087 | if (INSN_UID (label) == 0) | |
4088 | { | |
4089 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4090 | add_insn_before (label, before, NULL); |
e881bb1b RH |
4091 | } |
4092 | ||
4093 | return label; | |
4094 | } | |
4095 | ||
23b2ce53 RS |
4096 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
4097 | ||
4098 | rtx | |
a38e7aa5 | 4099 | emit_note_before (enum insn_note subtype, rtx before) |
23b2ce53 | 4100 | { |
b3694847 | 4101 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4102 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4103 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4104 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4105 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
23b2ce53 | 4106 | |
6fb5fa3c | 4107 | add_insn_before (note, before, NULL); |
23b2ce53 RS |
4108 | return note; |
4109 | } | |
4110 | \f | |
2f937369 DM |
4111 | /* Helper for emit_insn_after, handles lists of instructions |
4112 | efficiently. */ | |
23b2ce53 | 4113 | |
2f937369 | 4114 | static rtx |
6fb5fa3c | 4115 | emit_insn_after_1 (rtx first, rtx after, basic_block bb) |
23b2ce53 | 4116 | { |
2f937369 DM |
4117 | rtx last; |
4118 | rtx after_after; | |
6fb5fa3c DB |
4119 | if (!bb && !BARRIER_P (after)) |
4120 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4121 | |
6fb5fa3c | 4122 | if (bb) |
23b2ce53 | 4123 | { |
6fb5fa3c | 4124 | df_set_bb_dirty (bb); |
2f937369 | 4125 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4126 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4127 | { |
4128 | set_block_for_insn (last, bb); | |
4129 | df_insn_rescan (last); | |
4130 | } | |
4b4bf941 | 4131 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4132 | { |
4133 | set_block_for_insn (last, bb); | |
4134 | df_insn_rescan (last); | |
4135 | } | |
a813c111 SB |
4136 | if (BB_END (bb) == after) |
4137 | BB_END (bb) = last; | |
23b2ce53 RS |
4138 | } |
4139 | else | |
2f937369 DM |
4140 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4141 | continue; | |
4142 | ||
4143 | after_after = NEXT_INSN (after); | |
4144 | ||
4145 | NEXT_INSN (after) = first; | |
4146 | PREV_INSN (first) = after; | |
4147 | NEXT_INSN (last) = after_after; | |
4148 | if (after_after) | |
4149 | PREV_INSN (after_after) = last; | |
4150 | ||
4151 | if (after == last_insn) | |
4152 | last_insn = last; | |
4153 | return last; | |
4154 | } | |
4155 | ||
6fb5fa3c DB |
4156 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4157 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
2f937369 DM |
4158 | |
4159 | rtx | |
6fb5fa3c | 4160 | emit_insn_after_noloc (rtx x, rtx after, basic_block bb) |
2f937369 DM |
4161 | { |
4162 | rtx last = after; | |
4163 | ||
5b0264cb | 4164 | gcc_assert (after); |
2f937369 DM |
4165 | |
4166 | if (x == NULL_RTX) | |
4167 | return last; | |
4168 | ||
4169 | switch (GET_CODE (x)) | |
23b2ce53 | 4170 | { |
2f937369 DM |
4171 | case INSN: |
4172 | case JUMP_INSN: | |
4173 | case CALL_INSN: | |
4174 | case CODE_LABEL: | |
4175 | case BARRIER: | |
4176 | case NOTE: | |
6fb5fa3c | 4177 | last = emit_insn_after_1 (x, after, bb); |
2f937369 DM |
4178 | break; |
4179 | ||
4180 | #ifdef ENABLE_RTL_CHECKING | |
4181 | case SEQUENCE: | |
5b0264cb | 4182 | gcc_unreachable (); |
2f937369 DM |
4183 | break; |
4184 | #endif | |
4185 | ||
4186 | default: | |
4187 | last = make_insn_raw (x); | |
6fb5fa3c | 4188 | add_insn_after (last, after, bb); |
2f937369 | 4189 | break; |
23b2ce53 RS |
4190 | } |
4191 | ||
2f937369 | 4192 | return last; |
23b2ce53 RS |
4193 | } |
4194 | ||
255680cf | 4195 | |
2f937369 | 4196 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4197 | and output it after the insn AFTER. */ |
4198 | ||
4199 | rtx | |
a7102479 | 4200 | emit_jump_insn_after_noloc (rtx x, rtx after) |
23b2ce53 | 4201 | { |
2f937369 | 4202 | rtx last; |
23b2ce53 | 4203 | |
5b0264cb | 4204 | gcc_assert (after); |
2f937369 DM |
4205 | |
4206 | switch (GET_CODE (x)) | |
23b2ce53 | 4207 | { |
2f937369 DM |
4208 | case INSN: |
4209 | case JUMP_INSN: | |
4210 | case CALL_INSN: | |
4211 | case CODE_LABEL: | |
4212 | case BARRIER: | |
4213 | case NOTE: | |
6fb5fa3c | 4214 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4215 | break; |
4216 | ||
4217 | #ifdef ENABLE_RTL_CHECKING | |
4218 | case SEQUENCE: | |
5b0264cb | 4219 | gcc_unreachable (); |
2f937369 DM |
4220 | break; |
4221 | #endif | |
4222 | ||
4223 | default: | |
4224 | last = make_jump_insn_raw (x); | |
6fb5fa3c | 4225 | add_insn_after (last, after, NULL); |
2f937369 | 4226 | break; |
23b2ce53 RS |
4227 | } |
4228 | ||
2f937369 DM |
4229 | return last; |
4230 | } | |
4231 | ||
4232 | /* Make an instruction with body X and code CALL_INSN | |
4233 | and output it after the instruction AFTER. */ | |
4234 | ||
4235 | rtx | |
a7102479 | 4236 | emit_call_insn_after_noloc (rtx x, rtx after) |
2f937369 DM |
4237 | { |
4238 | rtx last; | |
4239 | ||
5b0264cb | 4240 | gcc_assert (after); |
2f937369 DM |
4241 | |
4242 | switch (GET_CODE (x)) | |
4243 | { | |
4244 | case INSN: | |
4245 | case JUMP_INSN: | |
4246 | case CALL_INSN: | |
4247 | case CODE_LABEL: | |
4248 | case BARRIER: | |
4249 | case NOTE: | |
6fb5fa3c | 4250 | last = emit_insn_after_1 (x, after, NULL); |
2f937369 DM |
4251 | break; |
4252 | ||
4253 | #ifdef ENABLE_RTL_CHECKING | |
4254 | case SEQUENCE: | |
5b0264cb | 4255 | gcc_unreachable (); |
2f937369 DM |
4256 | break; |
4257 | #endif | |
4258 | ||
4259 | default: | |
4260 | last = make_call_insn_raw (x); | |
6fb5fa3c | 4261 | add_insn_after (last, after, NULL); |
2f937369 DM |
4262 | break; |
4263 | } | |
4264 | ||
4265 | return last; | |
23b2ce53 RS |
4266 | } |
4267 | ||
4268 | /* Make an insn of code BARRIER | |
4269 | and output it after the insn AFTER. */ | |
4270 | ||
4271 | rtx | |
502b8322 | 4272 | emit_barrier_after (rtx after) |
23b2ce53 | 4273 | { |
b3694847 | 4274 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4275 | |
4276 | INSN_UID (insn) = cur_insn_uid++; | |
4277 | ||
6fb5fa3c | 4278 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4279 | return insn; |
4280 | } | |
4281 | ||
4282 | /* Emit the label LABEL after the insn AFTER. */ | |
4283 | ||
4284 | rtx | |
502b8322 | 4285 | emit_label_after (rtx label, rtx after) |
23b2ce53 RS |
4286 | { |
4287 | /* This can be called twice for the same label | |
4288 | as a result of the confusion that follows a syntax error! | |
4289 | So make it harmless. */ | |
4290 | if (INSN_UID (label) == 0) | |
4291 | { | |
4292 | INSN_UID (label) = cur_insn_uid++; | |
6fb5fa3c | 4293 | add_insn_after (label, after, NULL); |
23b2ce53 RS |
4294 | } |
4295 | ||
4296 | return label; | |
4297 | } | |
4298 | ||
4299 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4300 | ||
4301 | rtx | |
a38e7aa5 | 4302 | emit_note_after (enum insn_note subtype, rtx after) |
23b2ce53 | 4303 | { |
b3694847 | 4304 | rtx note = rtx_alloc (NOTE); |
23b2ce53 | 4305 | INSN_UID (note) = cur_insn_uid++; |
a38e7aa5 | 4306 | NOTE_KIND (note) = subtype; |
ba4f7968 | 4307 | BLOCK_FOR_INSN (note) = NULL; |
9dbe7947 | 4308 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
6fb5fa3c | 4309 | add_insn_after (note, after, NULL); |
23b2ce53 RS |
4310 | return note; |
4311 | } | |
23b2ce53 | 4312 | \f |
a7102479 | 4313 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4314 | rtx |
502b8322 | 4315 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4316 | { |
6fb5fa3c | 4317 | rtx last = emit_insn_after_noloc (pattern, after, NULL); |
0d682900 | 4318 | |
a7102479 | 4319 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4320 | return last; |
4321 | ||
2f937369 DM |
4322 | after = NEXT_INSN (after); |
4323 | while (1) | |
4324 | { | |
a7102479 | 4325 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4326 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4327 | if (after == last) |
4328 | break; | |
4329 | after = NEXT_INSN (after); | |
4330 | } | |
0d682900 JH |
4331 | return last; |
4332 | } | |
4333 | ||
a7102479 JH |
4334 | /* Like emit_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4335 | rtx | |
4336 | emit_insn_after (rtx pattern, rtx after) | |
4337 | { | |
4338 | if (INSN_P (after)) | |
4339 | return emit_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4340 | else | |
6fb5fa3c | 4341 | return emit_insn_after_noloc (pattern, after, NULL); |
a7102479 JH |
4342 | } |
4343 | ||
4344 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4345 | rtx |
502b8322 | 4346 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4347 | { |
a7102479 | 4348 | rtx last = emit_jump_insn_after_noloc (pattern, after); |
2f937369 | 4349 | |
a7102479 | 4350 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4351 | return last; |
4352 | ||
2f937369 DM |
4353 | after = NEXT_INSN (after); |
4354 | while (1) | |
4355 | { | |
a7102479 | 4356 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4357 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4358 | if (after == last) |
4359 | break; | |
4360 | after = NEXT_INSN (after); | |
4361 | } | |
0d682900 JH |
4362 | return last; |
4363 | } | |
4364 | ||
a7102479 JH |
4365 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4366 | rtx | |
4367 | emit_jump_insn_after (rtx pattern, rtx after) | |
4368 | { | |
4369 | if (INSN_P (after)) | |
4370 | return emit_jump_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4371 | else | |
4372 | return emit_jump_insn_after_noloc (pattern, after); | |
4373 | } | |
4374 | ||
4375 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4376 | rtx |
502b8322 | 4377 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 | 4378 | { |
a7102479 | 4379 | rtx last = emit_call_insn_after_noloc (pattern, after); |
2f937369 | 4380 | |
a7102479 | 4381 | if (pattern == NULL_RTX || !loc) |
dd3adcf8 DJ |
4382 | return last; |
4383 | ||
2f937369 DM |
4384 | after = NEXT_INSN (after); |
4385 | while (1) | |
4386 | { | |
a7102479 | 4387 | if (active_insn_p (after) && !INSN_LOCATOR (after)) |
0435312e | 4388 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4389 | if (after == last) |
4390 | break; | |
4391 | after = NEXT_INSN (after); | |
4392 | } | |
0d682900 JH |
4393 | return last; |
4394 | } | |
4395 | ||
a7102479 JH |
4396 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATOR according to AFTER. */ |
4397 | rtx | |
4398 | emit_call_insn_after (rtx pattern, rtx after) | |
4399 | { | |
4400 | if (INSN_P (after)) | |
4401 | return emit_call_insn_after_setloc (pattern, after, INSN_LOCATOR (after)); | |
4402 | else | |
4403 | return emit_call_insn_after_noloc (pattern, after); | |
4404 | } | |
4405 | ||
4406 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to SCOPE. */ | |
0d682900 | 4407 | rtx |
502b8322 | 4408 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
0d682900 JH |
4409 | { |
4410 | rtx first = PREV_INSN (before); | |
6fb5fa3c | 4411 | rtx last = emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4412 | |
4413 | if (pattern == NULL_RTX || !loc) | |
4414 | return last; | |
4415 | ||
26cb3993 JH |
4416 | if (!first) |
4417 | first = get_insns (); | |
4418 | else | |
4419 | first = NEXT_INSN (first); | |
a7102479 JH |
4420 | while (1) |
4421 | { | |
4422 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4423 | INSN_LOCATOR (first) = loc; | |
4424 | if (first == last) | |
4425 | break; | |
4426 | first = NEXT_INSN (first); | |
4427 | } | |
4428 | return last; | |
4429 | } | |
4430 | ||
4431 | /* Like emit_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4432 | rtx | |
4433 | emit_insn_before (rtx pattern, rtx before) | |
4434 | { | |
4435 | if (INSN_P (before)) | |
4436 | return emit_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4437 | else | |
6fb5fa3c | 4438 | return emit_insn_before_noloc (pattern, before, NULL); |
a7102479 JH |
4439 | } |
4440 | ||
4441 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4442 | rtx | |
4443 | emit_jump_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4444 | { | |
4445 | rtx first = PREV_INSN (before); | |
4446 | rtx last = emit_jump_insn_before_noloc (pattern, before); | |
4447 | ||
4448 | if (pattern == NULL_RTX) | |
4449 | return last; | |
4450 | ||
4451 | first = NEXT_INSN (first); | |
4452 | while (1) | |
4453 | { | |
4454 | if (active_insn_p (first) && !INSN_LOCATOR (first)) | |
4455 | INSN_LOCATOR (first) = loc; | |
4456 | if (first == last) | |
4457 | break; | |
4458 | first = NEXT_INSN (first); | |
4459 | } | |
4460 | return last; | |
4461 | } | |
4462 | ||
4463 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATOR according to BEFORE. */ | |
4464 | rtx | |
4465 | emit_jump_insn_before (rtx pattern, rtx before) | |
4466 | { | |
4467 | if (INSN_P (before)) | |
4468 | return emit_jump_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4469 | else | |
4470 | return emit_jump_insn_before_noloc (pattern, before); | |
4471 | } | |
4472 | ||
4473 | /* like emit_insn_before_noloc, but set insn_locator according to scope. */ | |
4474 | rtx | |
4475 | emit_call_insn_before_setloc (rtx pattern, rtx before, int loc) | |
4476 | { | |
4477 | rtx first = PREV_INSN (before); | |
4478 | rtx last = emit_call_insn_before_noloc (pattern, before); | |
0d682900 | 4479 | |
dd3adcf8 DJ |
4480 | if (pattern == NULL_RTX) |
4481 | return last; | |
4482 | ||
2f937369 DM |
4483 | first = NEXT_INSN (first); |
4484 | while (1) | |
4485 | { | |
a7102479 | 4486 | if (active_insn_p (first) && !INSN_LOCATOR (first)) |
0435312e | 4487 | INSN_LOCATOR (first) = loc; |
2f937369 DM |
4488 | if (first == last) |
4489 | break; | |
4490 | first = NEXT_INSN (first); | |
4491 | } | |
0d682900 JH |
4492 | return last; |
4493 | } | |
a7102479 JH |
4494 | |
4495 | /* like emit_call_insn_before_noloc, | |
4496 | but set insn_locator according to before. */ | |
4497 | rtx | |
4498 | emit_call_insn_before (rtx pattern, rtx before) | |
4499 | { | |
4500 | if (INSN_P (before)) | |
4501 | return emit_call_insn_before_setloc (pattern, before, INSN_LOCATOR (before)); | |
4502 | else | |
4503 | return emit_call_insn_before_noloc (pattern, before); | |
4504 | } | |
0d682900 | 4505 | \f |
2f937369 DM |
4506 | /* Take X and emit it at the end of the doubly-linked |
4507 | INSN list. | |
23b2ce53 RS |
4508 | |
4509 | Returns the last insn emitted. */ | |
4510 | ||
4511 | rtx | |
502b8322 | 4512 | emit_insn (rtx x) |
23b2ce53 | 4513 | { |
2f937369 DM |
4514 | rtx last = last_insn; |
4515 | rtx insn; | |
23b2ce53 | 4516 | |
2f937369 DM |
4517 | if (x == NULL_RTX) |
4518 | return last; | |
23b2ce53 | 4519 | |
2f937369 DM |
4520 | switch (GET_CODE (x)) |
4521 | { | |
4522 | case INSN: | |
4523 | case JUMP_INSN: | |
4524 | case CALL_INSN: | |
4525 | case CODE_LABEL: | |
4526 | case BARRIER: | |
4527 | case NOTE: | |
4528 | insn = x; | |
4529 | while (insn) | |
23b2ce53 | 4530 | { |
2f937369 | 4531 | rtx next = NEXT_INSN (insn); |
23b2ce53 | 4532 | add_insn (insn); |
2f937369 DM |
4533 | last = insn; |
4534 | insn = next; | |
23b2ce53 | 4535 | } |
2f937369 | 4536 | break; |
23b2ce53 | 4537 | |
2f937369 DM |
4538 | #ifdef ENABLE_RTL_CHECKING |
4539 | case SEQUENCE: | |
5b0264cb | 4540 | gcc_unreachable (); |
2f937369 DM |
4541 | break; |
4542 | #endif | |
23b2ce53 | 4543 | |
2f937369 DM |
4544 | default: |
4545 | last = make_insn_raw (x); | |
4546 | add_insn (last); | |
4547 | break; | |
23b2ce53 RS |
4548 | } |
4549 | ||
4550 | return last; | |
4551 | } | |
4552 | ||
2f937369 DM |
4553 | /* Make an insn of code JUMP_INSN with pattern X |
4554 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4555 | |
4556 | rtx | |
502b8322 | 4557 | emit_jump_insn (rtx x) |
23b2ce53 | 4558 | { |
d950dee3 | 4559 | rtx last = NULL_RTX, insn; |
23b2ce53 | 4560 | |
2f937369 | 4561 | switch (GET_CODE (x)) |
23b2ce53 | 4562 | { |
2f937369 DM |
4563 | case INSN: |
4564 | case JUMP_INSN: | |
4565 | case CALL_INSN: | |
4566 | case CODE_LABEL: | |
4567 | case BARRIER: | |
4568 | case NOTE: | |
4569 | insn = x; | |
4570 | while (insn) | |
4571 | { | |
4572 | rtx next = NEXT_INSN (insn); | |
4573 | add_insn (insn); | |
4574 | last = insn; | |
4575 | insn = next; | |
4576 | } | |
4577 | break; | |
e0a5c5eb | 4578 | |
2f937369 DM |
4579 | #ifdef ENABLE_RTL_CHECKING |
4580 | case SEQUENCE: | |
5b0264cb | 4581 | gcc_unreachable (); |
2f937369 DM |
4582 | break; |
4583 | #endif | |
e0a5c5eb | 4584 | |
2f937369 DM |
4585 | default: |
4586 | last = make_jump_insn_raw (x); | |
4587 | add_insn (last); | |
4588 | break; | |
3c030e88 | 4589 | } |
e0a5c5eb RS |
4590 | |
4591 | return last; | |
4592 | } | |
4593 | ||
2f937369 | 4594 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
4595 | and add it to the end of the doubly-linked list. */ |
4596 | ||
4597 | rtx | |
502b8322 | 4598 | emit_call_insn (rtx x) |
23b2ce53 | 4599 | { |
2f937369 DM |
4600 | rtx insn; |
4601 | ||
4602 | switch (GET_CODE (x)) | |
23b2ce53 | 4603 | { |
2f937369 DM |
4604 | case INSN: |
4605 | case JUMP_INSN: | |
4606 | case CALL_INSN: | |
4607 | case CODE_LABEL: | |
4608 | case BARRIER: | |
4609 | case NOTE: | |
4610 | insn = emit_insn (x); | |
4611 | break; | |
23b2ce53 | 4612 | |
2f937369 DM |
4613 | #ifdef ENABLE_RTL_CHECKING |
4614 | case SEQUENCE: | |
5b0264cb | 4615 | gcc_unreachable (); |
2f937369 DM |
4616 | break; |
4617 | #endif | |
23b2ce53 | 4618 | |
2f937369 DM |
4619 | default: |
4620 | insn = make_call_insn_raw (x); | |
23b2ce53 | 4621 | add_insn (insn); |
2f937369 | 4622 | break; |
23b2ce53 | 4623 | } |
2f937369 DM |
4624 | |
4625 | return insn; | |
23b2ce53 RS |
4626 | } |
4627 | ||
4628 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4629 | ||
4630 | rtx | |
502b8322 | 4631 | emit_label (rtx label) |
23b2ce53 RS |
4632 | { |
4633 | /* This can be called twice for the same label | |
4634 | as a result of the confusion that follows a syntax error! | |
4635 | So make it harmless. */ | |
4636 | if (INSN_UID (label) == 0) | |
4637 | { | |
4638 | INSN_UID (label) = cur_insn_uid++; | |
4639 | add_insn (label); | |
4640 | } | |
4641 | return label; | |
4642 | } | |
4643 | ||
4644 | /* Make an insn of code BARRIER | |
4645 | and add it to the end of the doubly-linked list. */ | |
4646 | ||
4647 | rtx | |
502b8322 | 4648 | emit_barrier (void) |
23b2ce53 | 4649 | { |
b3694847 | 4650 | rtx barrier = rtx_alloc (BARRIER); |
23b2ce53 RS |
4651 | INSN_UID (barrier) = cur_insn_uid++; |
4652 | add_insn (barrier); | |
4653 | return barrier; | |
4654 | } | |
4655 | ||
5f2fc772 | 4656 | /* Emit a copy of note ORIG. */ |
502b8322 | 4657 | |
5f2fc772 NS |
4658 | rtx |
4659 | emit_note_copy (rtx orig) | |
4660 | { | |
4661 | rtx note; | |
4662 | ||
5f2fc772 NS |
4663 | note = rtx_alloc (NOTE); |
4664 | ||
4665 | INSN_UID (note) = cur_insn_uid++; | |
4666 | NOTE_DATA (note) = NOTE_DATA (orig); | |
a38e7aa5 | 4667 | NOTE_KIND (note) = NOTE_KIND (orig); |
5f2fc772 NS |
4668 | BLOCK_FOR_INSN (note) = NULL; |
4669 | add_insn (note); | |
4670 | ||
2e040219 | 4671 | return note; |
23b2ce53 RS |
4672 | } |
4673 | ||
2e040219 NS |
4674 | /* Make an insn of code NOTE or type NOTE_NO |
4675 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4676 | |
4677 | rtx | |
a38e7aa5 | 4678 | emit_note (enum insn_note kind) |
23b2ce53 | 4679 | { |
b3694847 | 4680 | rtx note; |
23b2ce53 | 4681 | |
23b2ce53 RS |
4682 | note = rtx_alloc (NOTE); |
4683 | INSN_UID (note) = cur_insn_uid++; | |
a38e7aa5 | 4684 | NOTE_KIND (note) = kind; |
dd107e66 | 4685 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ba4f7968 | 4686 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
4687 | add_insn (note); |
4688 | return note; | |
4689 | } | |
4690 | ||
23b2ce53 | 4691 | /* Cause next statement to emit a line note even if the line number |
0cea056b | 4692 | has not changed. */ |
23b2ce53 RS |
4693 | |
4694 | void | |
502b8322 | 4695 | force_next_line_note (void) |
23b2ce53 | 4696 | { |
6773e15f PB |
4697 | #ifdef USE_MAPPED_LOCATION |
4698 | last_location = -1; | |
4699 | #else | |
fd3acbb3 | 4700 | last_location.line = -1; |
6773e15f | 4701 | #endif |
23b2ce53 | 4702 | } |
87b47c85 AM |
4703 | |
4704 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
30f7a378 | 4705 | note of this type already exists, remove it first. */ |
87b47c85 | 4706 | |
3d238248 | 4707 | rtx |
502b8322 | 4708 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
4709 | { |
4710 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
6fb5fa3c | 4711 | rtx new_note = NULL; |
87b47c85 | 4712 | |
52488da1 JW |
4713 | switch (kind) |
4714 | { | |
4715 | case REG_EQUAL: | |
4716 | case REG_EQUIV: | |
4717 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
4718 | has multiple sets (some callers assume single_set | |
4719 | means the insn only has one set, when in fact it | |
4720 | means the insn only has one * useful * set). */ | |
4721 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
4722 | { | |
5b0264cb | 4723 | gcc_assert (!note); |
52488da1 JW |
4724 | return NULL_RTX; |
4725 | } | |
4726 | ||
4727 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
4728 | It serves no useful purpose and breaks eliminate_regs. */ | |
4729 | if (GET_CODE (datum) == ASM_OPERANDS) | |
4730 | return NULL_RTX; | |
6fb5fa3c DB |
4731 | |
4732 | if (note) | |
4733 | { | |
4734 | XEXP (note, 0) = datum; | |
4735 | df_notes_rescan (insn); | |
4736 | return note; | |
4737 | } | |
52488da1 JW |
4738 | break; |
4739 | ||
4740 | default: | |
6fb5fa3c DB |
4741 | if (note) |
4742 | { | |
4743 | XEXP (note, 0) = datum; | |
4744 | return note; | |
4745 | } | |
52488da1 JW |
4746 | break; |
4747 | } | |
3d238248 | 4748 | |
6fb5fa3c DB |
4749 | new_note = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); |
4750 | REG_NOTES (insn) = new_note; | |
4751 | ||
4752 | switch (kind) | |
3d238248 | 4753 | { |
6fb5fa3c DB |
4754 | case REG_EQUAL: |
4755 | case REG_EQUIV: | |
4756 | df_notes_rescan (insn); | |
4757 | break; | |
4758 | default: | |
4759 | break; | |
3d238248 | 4760 | } |
87b47c85 | 4761 | |
3d238248 | 4762 | return REG_NOTES (insn); |
87b47c85 | 4763 | } |
23b2ce53 RS |
4764 | \f |
4765 | /* Return an indication of which type of insn should have X as a body. | |
4766 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
4767 | ||
d78db459 | 4768 | static enum rtx_code |
502b8322 | 4769 | classify_insn (rtx x) |
23b2ce53 | 4770 | { |
4b4bf941 | 4771 | if (LABEL_P (x)) |
23b2ce53 RS |
4772 | return CODE_LABEL; |
4773 | if (GET_CODE (x) == CALL) | |
4774 | return CALL_INSN; | |
4775 | if (GET_CODE (x) == RETURN) | |
4776 | return JUMP_INSN; | |
4777 | if (GET_CODE (x) == SET) | |
4778 | { | |
4779 | if (SET_DEST (x) == pc_rtx) | |
4780 | return JUMP_INSN; | |
4781 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
4782 | return CALL_INSN; | |
4783 | else | |
4784 | return INSN; | |
4785 | } | |
4786 | if (GET_CODE (x) == PARALLEL) | |
4787 | { | |
b3694847 | 4788 | int j; |
23b2ce53 RS |
4789 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
4790 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
4791 | return CALL_INSN; | |
4792 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4793 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
4794 | return JUMP_INSN; | |
4795 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4796 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
4797 | return CALL_INSN; | |
4798 | } | |
4799 | return INSN; | |
4800 | } | |
4801 | ||
4802 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
4803 | If X is a label, it is simply added into the insn chain. */ | |
4804 | ||
4805 | rtx | |
502b8322 | 4806 | emit (rtx x) |
23b2ce53 RS |
4807 | { |
4808 | enum rtx_code code = classify_insn (x); | |
4809 | ||
5b0264cb | 4810 | switch (code) |
23b2ce53 | 4811 | { |
5b0264cb NS |
4812 | case CODE_LABEL: |
4813 | return emit_label (x); | |
4814 | case INSN: | |
4815 | return emit_insn (x); | |
4816 | case JUMP_INSN: | |
4817 | { | |
4818 | rtx insn = emit_jump_insn (x); | |
4819 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) | |
4820 | return emit_barrier (); | |
4821 | return insn; | |
4822 | } | |
4823 | case CALL_INSN: | |
4824 | return emit_call_insn (x); | |
4825 | default: | |
4826 | gcc_unreachable (); | |
23b2ce53 | 4827 | } |
23b2ce53 RS |
4828 | } |
4829 | \f | |
e2500fed | 4830 | /* Space for free sequence stack entries. */ |
1431042e | 4831 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 4832 | |
4dfa0342 RH |
4833 | /* Begin emitting insns to a sequence. If this sequence will contain |
4834 | something that might cause the compiler to pop arguments to function | |
4835 | calls (because those pops have previously been deferred; see | |
4836 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
4837 | before calling this function. That will ensure that the deferred | |
4838 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
4839 | |
4840 | void | |
502b8322 | 4841 | start_sequence (void) |
23b2ce53 RS |
4842 | { |
4843 | struct sequence_stack *tem; | |
4844 | ||
e2500fed GK |
4845 | if (free_sequence_stack != NULL) |
4846 | { | |
4847 | tem = free_sequence_stack; | |
4848 | free_sequence_stack = tem->next; | |
4849 | } | |
4850 | else | |
703ad42b | 4851 | tem = ggc_alloc (sizeof (struct sequence_stack)); |
23b2ce53 | 4852 | |
49ad7cfa | 4853 | tem->next = seq_stack; |
23b2ce53 RS |
4854 | tem->first = first_insn; |
4855 | tem->last = last_insn; | |
4856 | ||
49ad7cfa | 4857 | seq_stack = tem; |
23b2ce53 RS |
4858 | |
4859 | first_insn = 0; | |
4860 | last_insn = 0; | |
4861 | } | |
4862 | ||
5c7a310f MM |
4863 | /* Set up the insn chain starting with FIRST as the current sequence, |
4864 | saving the previously current one. See the documentation for | |
4865 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
4866 | |
4867 | void | |
502b8322 | 4868 | push_to_sequence (rtx first) |
23b2ce53 RS |
4869 | { |
4870 | rtx last; | |
4871 | ||
4872 | start_sequence (); | |
4873 | ||
4874 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
4875 | ||
4876 | first_insn = first; | |
4877 | last_insn = last; | |
4878 | } | |
4879 | ||
bb27eeda SE |
4880 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
4881 | looping through the list. */ | |
4882 | ||
4883 | void | |
4884 | push_to_sequence2 (rtx first, rtx last) | |
4885 | { | |
4886 | start_sequence (); | |
4887 | ||
4888 | first_insn = first; | |
4889 | last_insn = last; | |
4890 | } | |
4891 | ||
f15ae3a1 TW |
4892 | /* Set up the outer-level insn chain |
4893 | as the current sequence, saving the previously current one. */ | |
4894 | ||
4895 | void | |
502b8322 | 4896 | push_topmost_sequence (void) |
f15ae3a1 | 4897 | { |
aefdd5ab | 4898 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
4899 | |
4900 | start_sequence (); | |
4901 | ||
49ad7cfa | 4902 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
4903 | top = stack; |
4904 | ||
4905 | first_insn = top->first; | |
4906 | last_insn = top->last; | |
4907 | } | |
4908 | ||
4909 | /* After emitting to the outer-level insn chain, update the outer-level | |
4910 | insn chain, and restore the previous saved state. */ | |
4911 | ||
4912 | void | |
502b8322 | 4913 | pop_topmost_sequence (void) |
f15ae3a1 | 4914 | { |
aefdd5ab | 4915 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 4916 | |
49ad7cfa | 4917 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
4918 | top = stack; |
4919 | ||
4920 | top->first = first_insn; | |
4921 | top->last = last_insn; | |
4922 | ||
4923 | end_sequence (); | |
4924 | } | |
4925 | ||
23b2ce53 RS |
4926 | /* After emitting to a sequence, restore previous saved state. |
4927 | ||
5c7a310f | 4928 | To get the contents of the sequence just made, you must call |
2f937369 | 4929 | `get_insns' *before* calling here. |
5c7a310f MM |
4930 | |
4931 | If the compiler might have deferred popping arguments while | |
4932 | generating this sequence, and this sequence will not be immediately | |
4933 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 4934 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
4935 | pops are inserted into this sequence, and not into some random |
4936 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
4937 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
4938 | |
4939 | void | |
502b8322 | 4940 | end_sequence (void) |
23b2ce53 | 4941 | { |
49ad7cfa | 4942 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
4943 | |
4944 | first_insn = tem->first; | |
4945 | last_insn = tem->last; | |
49ad7cfa | 4946 | seq_stack = tem->next; |
23b2ce53 | 4947 | |
e2500fed GK |
4948 | memset (tem, 0, sizeof (*tem)); |
4949 | tem->next = free_sequence_stack; | |
4950 | free_sequence_stack = tem; | |
23b2ce53 RS |
4951 | } |
4952 | ||
4953 | /* Return 1 if currently emitting into a sequence. */ | |
4954 | ||
4955 | int | |
502b8322 | 4956 | in_sequence_p (void) |
23b2ce53 | 4957 | { |
49ad7cfa | 4958 | return seq_stack != 0; |
23b2ce53 | 4959 | } |
23b2ce53 | 4960 | \f |
59ec66dc MM |
4961 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
4962 | ||
2bbdec73 | 4963 | static void |
502b8322 | 4964 | init_virtual_regs (struct emit_status *es) |
59ec66dc | 4965 | { |
49ad7cfa BS |
4966 | rtx *ptr = es->x_regno_reg_rtx; |
4967 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
4968 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
4969 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
4970 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
4971 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
4972 | } | |
4973 | ||
da43a810 BS |
4974 | \f |
4975 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
4976 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
4977 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
4978 | static int copy_insn_n_scratches; | |
4979 | ||
4980 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
4981 | copied an ASM_OPERANDS. | |
4982 | In that case, it is the original input-operand vector. */ | |
4983 | static rtvec orig_asm_operands_vector; | |
4984 | ||
4985 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
4986 | copied an ASM_OPERANDS. | |
4987 | In that case, it is the copied input-operand vector. */ | |
4988 | static rtvec copy_asm_operands_vector; | |
4989 | ||
4990 | /* Likewise for the constraints vector. */ | |
4991 | static rtvec orig_asm_constraints_vector; | |
4992 | static rtvec copy_asm_constraints_vector; | |
4993 | ||
4994 | /* Recursively create a new copy of an rtx for copy_insn. | |
4995 | This function differs from copy_rtx in that it handles SCRATCHes and | |
4996 | ASM_OPERANDs properly. | |
4997 | Normally, this function is not used directly; use copy_insn as front end. | |
4998 | However, you could first copy an insn pattern with copy_insn and then use | |
4999 | this function afterwards to properly copy any REG_NOTEs containing | |
5000 | SCRATCHes. */ | |
5001 | ||
5002 | rtx | |
502b8322 | 5003 | copy_insn_1 (rtx orig) |
da43a810 | 5004 | { |
b3694847 SS |
5005 | rtx copy; |
5006 | int i, j; | |
5007 | RTX_CODE code; | |
5008 | const char *format_ptr; | |
da43a810 BS |
5009 | |
5010 | code = GET_CODE (orig); | |
5011 | ||
5012 | switch (code) | |
5013 | { | |
5014 | case REG: | |
da43a810 BS |
5015 | case CONST_INT: |
5016 | case CONST_DOUBLE: | |
091a3ac7 | 5017 | case CONST_FIXED: |
69ef87e2 | 5018 | case CONST_VECTOR: |
da43a810 BS |
5019 | case SYMBOL_REF: |
5020 | case CODE_LABEL: | |
5021 | case PC: | |
5022 | case CC0: | |
da43a810 | 5023 | return orig; |
3e89ed8d JH |
5024 | case CLOBBER: |
5025 | if (REG_P (XEXP (orig, 0)) && REGNO (XEXP (orig, 0)) < FIRST_PSEUDO_REGISTER) | |
5026 | return orig; | |
5027 | break; | |
da43a810 BS |
5028 | |
5029 | case SCRATCH: | |
5030 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5031 | if (copy_insn_scratch_in[i] == orig) | |
5032 | return copy_insn_scratch_out[i]; | |
5033 | break; | |
5034 | ||
5035 | case CONST: | |
6fb5fa3c | 5036 | if (shared_const_p (orig)) |
da43a810 BS |
5037 | return orig; |
5038 | break; | |
750c9258 | 5039 | |
da43a810 BS |
5040 | /* A MEM with a constant address is not sharable. The problem is that |
5041 | the constant address may need to be reloaded. If the mem is shared, | |
5042 | then reloading one copy of this mem will cause all copies to appear | |
5043 | to have been reloaded. */ | |
5044 | ||
5045 | default: | |
5046 | break; | |
5047 | } | |
5048 | ||
aacd3885 RS |
5049 | /* Copy the various flags, fields, and other information. We assume |
5050 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5051 | not be copied. That is the sensible default behavior, and forces |
5052 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5053 | copy = shallow_copy_rtx (orig); |
da43a810 BS |
5054 | |
5055 | /* We do not copy the USED flag, which is used as a mark bit during | |
5056 | walks over the RTL. */ | |
2adc7f12 | 5057 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5058 | |
5059 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
ec8e098d | 5060 | if (INSN_P (orig)) |
da43a810 | 5061 | { |
2adc7f12 JJ |
5062 | RTX_FLAG (copy, jump) = 0; |
5063 | RTX_FLAG (copy, call) = 0; | |
5064 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5065 | } |
750c9258 | 5066 | |
da43a810 BS |
5067 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5068 | ||
5069 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5070 | switch (*format_ptr++) |
5071 | { | |
5072 | case 'e': | |
5073 | if (XEXP (orig, i) != NULL) | |
5074 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5075 | break; | |
da43a810 | 5076 | |
aacd3885 RS |
5077 | case 'E': |
5078 | case 'V': | |
5079 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5080 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5081 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5082 | XVEC (copy, i) = copy_asm_operands_vector; | |
5083 | else if (XVEC (orig, i) != NULL) | |
5084 | { | |
5085 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5086 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5087 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5088 | } | |
5089 | break; | |
da43a810 | 5090 | |
aacd3885 RS |
5091 | case 't': |
5092 | case 'w': | |
5093 | case 'i': | |
5094 | case 's': | |
5095 | case 'S': | |
5096 | case 'u': | |
5097 | case '0': | |
5098 | /* These are left unchanged. */ | |
5099 | break; | |
da43a810 | 5100 | |
aacd3885 RS |
5101 | default: |
5102 | gcc_unreachable (); | |
5103 | } | |
da43a810 BS |
5104 | |
5105 | if (code == SCRATCH) | |
5106 | { | |
5107 | i = copy_insn_n_scratches++; | |
5b0264cb | 5108 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5109 | copy_insn_scratch_in[i] = orig; |
5110 | copy_insn_scratch_out[i] = copy; | |
5111 | } | |
5112 | else if (code == ASM_OPERANDS) | |
5113 | { | |
6462bb43 AO |
5114 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5115 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5116 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5117 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5118 | } |
5119 | ||
5120 | return copy; | |
5121 | } | |
5122 | ||
5123 | /* Create a new copy of an rtx. | |
5124 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5125 | ASM_OPERANDs properly. | |
5126 | INSN doesn't really have to be a full INSN; it could be just the | |
5127 | pattern. */ | |
5128 | rtx | |
502b8322 | 5129 | copy_insn (rtx insn) |
da43a810 BS |
5130 | { |
5131 | copy_insn_n_scratches = 0; | |
5132 | orig_asm_operands_vector = 0; | |
5133 | orig_asm_constraints_vector = 0; | |
5134 | copy_asm_operands_vector = 0; | |
5135 | copy_asm_constraints_vector = 0; | |
5136 | return copy_insn_1 (insn); | |
5137 | } | |
59ec66dc | 5138 | |
23b2ce53 RS |
5139 | /* Initialize data structures and variables in this file |
5140 | before generating rtl for each function. */ | |
5141 | ||
5142 | void | |
502b8322 | 5143 | init_emit (void) |
23b2ce53 | 5144 | { |
01d939e8 | 5145 | struct function *f = cfun; |
23b2ce53 | 5146 | |
703ad42b | 5147 | f->emit = ggc_alloc (sizeof (struct emit_status)); |
23b2ce53 RS |
5148 | first_insn = NULL; |
5149 | last_insn = NULL; | |
5150 | cur_insn_uid = 1; | |
5151 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
6773e15f | 5152 | last_location = UNKNOWN_LOCATION; |
23b2ce53 | 5153 | first_label_num = label_num; |
49ad7cfa | 5154 | seq_stack = NULL; |
23b2ce53 | 5155 | |
23b2ce53 RS |
5156 | /* Init the tables that describe all the pseudo regs. */ |
5157 | ||
3502dc9c | 5158 | f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5159 | |
49ad7cfa | 5160 | f->emit->regno_pointer_align |
703ad42b KG |
5161 | = ggc_alloc_cleared (f->emit->regno_pointer_align_length |
5162 | * sizeof (unsigned char)); | |
86fe05e0 | 5163 | |
750c9258 | 5164 | regno_reg_rtx |
703ad42b | 5165 | = ggc_alloc (f->emit->regno_pointer_align_length * sizeof (rtx)); |
0d4903b8 | 5166 | |
e50126e8 | 5167 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 JL |
5168 | memcpy (regno_reg_rtx, |
5169 | static_regno_reg_rtx, | |
5170 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); | |
e50126e8 | 5171 | |
23b2ce53 | 5172 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
49ad7cfa | 5173 | init_virtual_regs (f->emit); |
740ab4a2 RK |
5174 | |
5175 | /* Indicate that the virtual registers and stack locations are | |
5176 | all pointers. */ | |
3502dc9c JDA |
5177 | REG_POINTER (stack_pointer_rtx) = 1; |
5178 | REG_POINTER (frame_pointer_rtx) = 1; | |
5179 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5180 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5181 | |
3502dc9c JDA |
5182 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5183 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5184 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5185 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5186 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5187 | |
86fe05e0 | 5188 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5189 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5190 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5191 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5192 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5193 | ||
5194 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5195 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5196 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5197 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5198 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5199 | #endif |
5200 | ||
5e82e7bd JVA |
5201 | #ifdef INIT_EXPANDERS |
5202 | INIT_EXPANDERS; | |
5203 | #endif | |
23b2ce53 RS |
5204 | } |
5205 | ||
a73b091d | 5206 | /* Generate a vector constant for mode MODE and constant value CONSTANT. */ |
69ef87e2 AH |
5207 | |
5208 | static rtx | |
a73b091d | 5209 | gen_const_vector (enum machine_mode mode, int constant) |
69ef87e2 AH |
5210 | { |
5211 | rtx tem; | |
5212 | rtvec v; | |
5213 | int units, i; | |
5214 | enum machine_mode inner; | |
5215 | ||
5216 | units = GET_MODE_NUNITS (mode); | |
5217 | inner = GET_MODE_INNER (mode); | |
5218 | ||
15ed7b52 JG |
5219 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
5220 | ||
69ef87e2 AH |
5221 | v = rtvec_alloc (units); |
5222 | ||
a73b091d JW |
5223 | /* We need to call this function after we set the scalar const_tiny_rtx |
5224 | entries. */ | |
5225 | gcc_assert (const_tiny_rtx[constant][(int) inner]); | |
69ef87e2 AH |
5226 | |
5227 | for (i = 0; i < units; ++i) | |
a73b091d | 5228 | RTVEC_ELT (v, i) = const_tiny_rtx[constant][(int) inner]; |
69ef87e2 | 5229 | |
a06e3c40 | 5230 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5231 | return tem; |
5232 | } | |
5233 | ||
a06e3c40 | 5234 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 5235 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 5236 | rtx |
502b8322 | 5237 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
a06e3c40 | 5238 | { |
a73b091d JW |
5239 | enum machine_mode inner = GET_MODE_INNER (mode); |
5240 | int nunits = GET_MODE_NUNITS (mode); | |
5241 | rtx x; | |
a06e3c40 R |
5242 | int i; |
5243 | ||
a73b091d JW |
5244 | /* Check to see if all of the elements have the same value. */ |
5245 | x = RTVEC_ELT (v, nunits - 1); | |
5246 | for (i = nunits - 2; i >= 0; i--) | |
5247 | if (RTVEC_ELT (v, i) != x) | |
5248 | break; | |
5249 | ||
5250 | /* If the values are all the same, check to see if we can use one of the | |
5251 | standard constant vectors. */ | |
5252 | if (i == -1) | |
5253 | { | |
5254 | if (x == CONST0_RTX (inner)) | |
5255 | return CONST0_RTX (mode); | |
5256 | else if (x == CONST1_RTX (inner)) | |
5257 | return CONST1_RTX (mode); | |
5258 | } | |
5259 | ||
5260 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
a06e3c40 R |
5261 | } |
5262 | ||
b5deb7b6 SL |
5263 | /* Initialise global register information required by all functions. */ |
5264 | ||
5265 | void | |
5266 | init_emit_regs (void) | |
5267 | { | |
5268 | int i; | |
5269 | ||
5270 | /* Reset register attributes */ | |
5271 | htab_empty (reg_attrs_htab); | |
5272 | ||
5273 | /* We need reg_raw_mode, so initialize the modes now. */ | |
5274 | init_reg_modes_target (); | |
5275 | ||
5276 | /* Assign register numbers to the globally defined register rtx. */ | |
5277 | pc_rtx = gen_rtx_PC (VOIDmode); | |
5278 | cc0_rtx = gen_rtx_CC0 (VOIDmode); | |
5279 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
5280 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5281 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
5282 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
5283 | virtual_incoming_args_rtx = | |
5284 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
5285 | virtual_stack_vars_rtx = | |
5286 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
5287 | virtual_stack_dynamic_rtx = | |
5288 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
5289 | virtual_outgoing_args_rtx = | |
5290 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
5291 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
5292 | ||
5293 | /* Initialize RTL for commonly used hard registers. These are | |
5294 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5295 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5296 | static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); | |
5297 | ||
5298 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
5299 | return_address_pointer_rtx | |
5300 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
5301 | #endif | |
5302 | ||
5303 | #ifdef STATIC_CHAIN_REGNUM | |
5304 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
5305 | ||
5306 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
5307 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
5308 | static_chain_incoming_rtx | |
5309 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
5310 | else | |
5311 | #endif | |
5312 | static_chain_incoming_rtx = static_chain_rtx; | |
5313 | #endif | |
5314 | ||
5315 | #ifdef STATIC_CHAIN | |
5316 | static_chain_rtx = STATIC_CHAIN; | |
5317 | ||
5318 | #ifdef STATIC_CHAIN_INCOMING | |
5319 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
5320 | #else | |
5321 | static_chain_incoming_rtx = static_chain_rtx; | |
5322 | #endif | |
5323 | #endif | |
5324 | ||
5325 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
5326 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
5327 | else | |
5328 | pic_offset_table_rtx = NULL_RTX; | |
5329 | } | |
5330 | ||
23b2ce53 RS |
5331 | /* Create some permanent unique rtl objects shared between all functions. |
5332 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
5333 | ||
5334 | void | |
502b8322 | 5335 | init_emit_once (int line_numbers) |
23b2ce53 RS |
5336 | { |
5337 | int i; | |
5338 | enum machine_mode mode; | |
9ec36da5 | 5339 | enum machine_mode double_mode; |
23b2ce53 | 5340 | |
091a3ac7 CF |
5341 | /* Initialize the CONST_INT, CONST_DOUBLE, CONST_FIXED, and memory attribute |
5342 | hash tables. */ | |
17211ab5 GK |
5343 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5344 | const_int_htab_eq, NULL); | |
173b24b9 | 5345 | |
17211ab5 GK |
5346 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5347 | const_double_htab_eq, NULL); | |
5692c7bc | 5348 | |
091a3ac7 CF |
5349 | const_fixed_htab = htab_create_ggc (37, const_fixed_htab_hash, |
5350 | const_fixed_htab_eq, NULL); | |
5351 | ||
17211ab5 GK |
5352 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5353 | mem_attrs_htab_eq, NULL); | |
a560d4d4 JH |
5354 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5355 | reg_attrs_htab_eq, NULL); | |
67673f5c | 5356 | |
23b2ce53 RS |
5357 | no_line_numbers = ! line_numbers; |
5358 | ||
43fa6302 AS |
5359 | /* Compute the word and byte modes. */ |
5360 | ||
5361 | byte_mode = VOIDmode; | |
5362 | word_mode = VOIDmode; | |
5363 | double_mode = VOIDmode; | |
5364 | ||
15ed7b52 JG |
5365 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5366 | mode != VOIDmode; | |
43fa6302 AS |
5367 | mode = GET_MODE_WIDER_MODE (mode)) |
5368 | { | |
5369 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5370 | && byte_mode == VOIDmode) | |
5371 | byte_mode = mode; | |
5372 | ||
5373 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5374 | && word_mode == VOIDmode) | |
5375 | word_mode = mode; | |
5376 | } | |
5377 | ||
15ed7b52 JG |
5378 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5379 | mode != VOIDmode; | |
43fa6302 AS |
5380 | mode = GET_MODE_WIDER_MODE (mode)) |
5381 | { | |
5382 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5383 | && double_mode == VOIDmode) | |
5384 | double_mode = mode; | |
5385 | } | |
5386 | ||
5387 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5388 | ||
5da077de | 5389 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5390 | /* This is to initialize {init|mark|free}_machine_status before the first |
5391 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5392 | end which calls push_function_context_to before the first call to |
5da077de AS |
5393 | init_function_start. */ |
5394 | INIT_EXPANDERS; | |
5395 | #endif | |
5396 | ||
23b2ce53 RS |
5397 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5398 | ||
a2a8cc44 | 5399 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 5400 | tries to use these variables. */ |
23b2ce53 | 5401 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5402 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5403 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5404 | |
68d75312 JC |
5405 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5406 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5407 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5408 | else |
3b80f6ca | 5409 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5410 | |
5692c7bc ZW |
5411 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5412 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5413 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
f7657db9 KG |
5414 | REAL_VALUE_FROM_INT (dconst3, 3, 0, double_mode); |
5415 | REAL_VALUE_FROM_INT (dconst10, 10, 0, double_mode); | |
5692c7bc | 5416 | REAL_VALUE_FROM_INT (dconstm1, -1, -1, double_mode); |
03f2ea93 RS |
5417 | REAL_VALUE_FROM_INT (dconstm2, -2, -1, double_mode); |
5418 | ||
5419 | dconsthalf = dconst1; | |
1e92bbb9 | 5420 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 5421 | |
f7657db9 KG |
5422 | real_arithmetic (&dconstthird, RDIV_EXPR, &dconst1, &dconst3); |
5423 | ||
ab01a87c KG |
5424 | /* Initialize mathematical constants for constant folding builtins. |
5425 | These constants need to be given to at least 160 bits precision. */ | |
b86a760a KG |
5426 | real_from_string (&dconstsqrt2, |
5427 | "1.4142135623730950488016887242096980785696718753769480731766797379907"); | |
ab01a87c KG |
5428 | real_from_string (&dconste, |
5429 | "2.7182818284590452353602874713526624977572470936999595749669676277241"); | |
5430 | ||
f7657db9 | 5431 | for (i = 0; i < (int) ARRAY_SIZE (const_tiny_rtx); i++) |
23b2ce53 | 5432 | { |
b216cd4a ZW |
5433 | REAL_VALUE_TYPE *r = |
5434 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); | |
5435 | ||
15ed7b52 JG |
5436 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); |
5437 | mode != VOIDmode; | |
5438 | mode = GET_MODE_WIDER_MODE (mode)) | |
5439 | const_tiny_rtx[i][(int) mode] = | |
5440 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
5441 | ||
5442 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_DECIMAL_FLOAT); | |
5443 | mode != VOIDmode; | |
23b2ce53 | 5444 | mode = GET_MODE_WIDER_MODE (mode)) |
5692c7bc ZW |
5445 | const_tiny_rtx[i][(int) mode] = |
5446 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5447 | |
906c4e36 | 5448 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 5449 | |
15ed7b52 JG |
5450 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
5451 | mode != VOIDmode; | |
23b2ce53 | 5452 | mode = GET_MODE_WIDER_MODE (mode)) |
906c4e36 | 5453 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
5454 | |
5455 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5456 | mode != VOIDmode; | |
5457 | mode = GET_MODE_WIDER_MODE (mode)) | |
5458 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
5459 | } |
5460 | ||
e90721b1 AP |
5461 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_INT); |
5462 | mode != VOIDmode; | |
5463 | mode = GET_MODE_WIDER_MODE (mode)) | |
5464 | { | |
5465 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5466 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5467 | } | |
5468 | ||
5469 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_COMPLEX_FLOAT); | |
5470 | mode != VOIDmode; | |
5471 | mode = GET_MODE_WIDER_MODE (mode)) | |
5472 | { | |
5473 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
5474 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
5475 | } | |
5476 | ||
69ef87e2 AH |
5477 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5478 | mode != VOIDmode; | |
5479 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5480 | { |
5481 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5482 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5483 | } | |
69ef87e2 AH |
5484 | |
5485 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5486 | mode != VOIDmode; | |
5487 | mode = GET_MODE_WIDER_MODE (mode)) | |
a73b091d JW |
5488 | { |
5489 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5490 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5491 | } | |
69ef87e2 | 5492 | |
325217ed CF |
5493 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FRACT); |
5494 | mode != VOIDmode; | |
5495 | mode = GET_MODE_WIDER_MODE (mode)) | |
5496 | { | |
5497 | FCONST0(mode).data.high = 0; | |
5498 | FCONST0(mode).data.low = 0; | |
5499 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5500 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5501 | FCONST0 (mode), mode); | |
325217ed CF |
5502 | } |
5503 | ||
5504 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UFRACT); | |
5505 | mode != VOIDmode; | |
5506 | mode = GET_MODE_WIDER_MODE (mode)) | |
5507 | { | |
5508 | FCONST0(mode).data.high = 0; | |
5509 | FCONST0(mode).data.low = 0; | |
5510 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5511 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5512 | FCONST0 (mode), mode); | |
325217ed CF |
5513 | } |
5514 | ||
5515 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_ACCUM); | |
5516 | mode != VOIDmode; | |
5517 | mode = GET_MODE_WIDER_MODE (mode)) | |
5518 | { | |
5519 | FCONST0(mode).data.high = 0; | |
5520 | FCONST0(mode).data.low = 0; | |
5521 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5522 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5523 | FCONST0 (mode), mode); | |
325217ed CF |
5524 | |
5525 | /* We store the value 1. */ | |
5526 | FCONST1(mode).data.high = 0; | |
5527 | FCONST1(mode).data.low = 0; | |
5528 | FCONST1(mode).mode = mode; | |
5529 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5530 | 2 * HOST_BITS_PER_WIDE_INT, | |
5531 | &FCONST1(mode).data.low, | |
5532 | &FCONST1(mode).data.high, | |
5533 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5534 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5535 | FCONST1 (mode), mode); | |
325217ed CF |
5536 | } |
5537 | ||
5538 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_UACCUM); | |
5539 | mode != VOIDmode; | |
5540 | mode = GET_MODE_WIDER_MODE (mode)) | |
5541 | { | |
5542 | FCONST0(mode).data.high = 0; | |
5543 | FCONST0(mode).data.low = 0; | |
5544 | FCONST0(mode).mode = mode; | |
091a3ac7 CF |
5545 | const_tiny_rtx[0][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5546 | FCONST0 (mode), mode); | |
325217ed CF |
5547 | |
5548 | /* We store the value 1. */ | |
5549 | FCONST1(mode).data.high = 0; | |
5550 | FCONST1(mode).data.low = 0; | |
5551 | FCONST1(mode).mode = mode; | |
5552 | lshift_double (1, 0, GET_MODE_FBIT (mode), | |
5553 | 2 * HOST_BITS_PER_WIDE_INT, | |
5554 | &FCONST1(mode).data.low, | |
5555 | &FCONST1(mode).data.high, | |
5556 | SIGNED_FIXED_POINT_MODE_P (mode)); | |
091a3ac7 CF |
5557 | const_tiny_rtx[1][(int) mode] = CONST_FIXED_FROM_FIXED_VALUE ( |
5558 | FCONST1 (mode), mode); | |
5559 | } | |
5560 | ||
5561 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FRACT); | |
5562 | mode != VOIDmode; | |
5563 | mode = GET_MODE_WIDER_MODE (mode)) | |
5564 | { | |
5565 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5566 | } | |
5567 | ||
5568 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UFRACT); | |
5569 | mode != VOIDmode; | |
5570 | mode = GET_MODE_WIDER_MODE (mode)) | |
5571 | { | |
5572 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5573 | } | |
5574 | ||
5575 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_ACCUM); | |
5576 | mode != VOIDmode; | |
5577 | mode = GET_MODE_WIDER_MODE (mode)) | |
5578 | { | |
5579 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5580 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
5581 | } | |
5582 | ||
5583 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_UACCUM); | |
5584 | mode != VOIDmode; | |
5585 | mode = GET_MODE_WIDER_MODE (mode)) | |
5586 | { | |
5587 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
5588 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
5589 | } |
5590 | ||
dbbbbf3b JDA |
5591 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5592 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5593 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 5594 | |
f0417c82 RH |
5595 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5596 | if (STORE_FLAG_VALUE == 1) | |
5597 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
23b2ce53 | 5598 | } |
a11759a3 | 5599 | \f |
969d70ca JH |
5600 | /* Produce exact duplicate of insn INSN after AFTER. |
5601 | Care updating of libcall regions if present. */ | |
5602 | ||
5603 | rtx | |
502b8322 | 5604 | emit_copy_of_insn_after (rtx insn, rtx after) |
969d70ca JH |
5605 | { |
5606 | rtx new; | |
5607 | rtx note1, note2, link; | |
5608 | ||
5609 | switch (GET_CODE (insn)) | |
5610 | { | |
5611 | case INSN: | |
5612 | new = emit_insn_after (copy_insn (PATTERN (insn)), after); | |
5613 | break; | |
5614 | ||
5615 | case JUMP_INSN: | |
5616 | new = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); | |
5617 | break; | |
5618 | ||
5619 | case CALL_INSN: | |
5620 | new = emit_call_insn_after (copy_insn (PATTERN (insn)), after); | |
5621 | if (CALL_INSN_FUNCTION_USAGE (insn)) | |
5622 | CALL_INSN_FUNCTION_USAGE (new) | |
5623 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); | |
5624 | SIBLING_CALL_P (new) = SIBLING_CALL_P (insn); | |
5625 | CONST_OR_PURE_CALL_P (new) = CONST_OR_PURE_CALL_P (insn); | |
5626 | break; | |
5627 | ||
5628 | default: | |
5b0264cb | 5629 | gcc_unreachable (); |
969d70ca JH |
5630 | } |
5631 | ||
5632 | /* Update LABEL_NUSES. */ | |
5633 | mark_jump_label (PATTERN (new), new, 0); | |
5634 | ||
0435312e | 5635 | INSN_LOCATOR (new) = INSN_LOCATOR (insn); |
ba4f7968 | 5636 | |
0a3d71f5 JW |
5637 | /* If the old insn is frame related, then so is the new one. This is |
5638 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
5639 | which may be duplicated by the basic block reordering code. */ | |
5640 | RTX_FRAME_RELATED_P (new) = RTX_FRAME_RELATED_P (insn); | |
5641 | ||
969d70ca JH |
5642 | /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will |
5643 | make them. */ | |
5644 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
5645 | if (REG_NOTE_KIND (link) != REG_LABEL) | |
5646 | { | |
5647 | if (GET_CODE (link) == EXPR_LIST) | |
5648 | REG_NOTES (new) | |
4b73962b JH |
5649 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link), |
5650 | copy_insn_1 (XEXP (link, 0)), REG_NOTES (new)); | |
969d70ca JH |
5651 | else |
5652 | REG_NOTES (new) | |
4b73962b | 5653 | = gen_rtx_INSN_LIST (REG_NOTE_KIND (link), |
95e2a53b | 5654 | XEXP (link, 0), REG_NOTES (new)); |
969d70ca JH |
5655 | } |
5656 | ||
5657 | /* Fix the libcall sequences. */ | |
5658 | if ((note1 = find_reg_note (new, REG_RETVAL, NULL_RTX)) != NULL) | |
5659 | { | |
5660 | rtx p = new; | |
5661 | while ((note2 = find_reg_note (p, REG_LIBCALL, NULL_RTX)) == NULL) | |
5662 | p = PREV_INSN (p); | |
5663 | XEXP (note1, 0) = p; | |
5664 | XEXP (note2, 0) = new; | |
5665 | } | |
6f0d3566 | 5666 | INSN_CODE (new) = INSN_CODE (insn); |
969d70ca JH |
5667 | return new; |
5668 | } | |
e2500fed | 5669 | |
1431042e | 5670 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d JH |
5671 | rtx |
5672 | gen_hard_reg_clobber (enum machine_mode mode, unsigned int regno) | |
5673 | { | |
5674 | if (hard_reg_clobbers[mode][regno]) | |
5675 | return hard_reg_clobbers[mode][regno]; | |
5676 | else | |
5677 | return (hard_reg_clobbers[mode][regno] = | |
5678 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
5679 | } | |
5680 | ||
e2500fed | 5681 | #include "gt-emit-rtl.h" |