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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
99dee823 | 2 | Copyright (C) 1987-2021 Free Software Foundation, Inc. |
23b2ce53 | 3 | |
1322177d | 4 | This file is part of GCC. |
23b2ce53 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
23b2ce53 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
23b2ce53 RS |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
23b2ce53 RS |
19 | |
20 | ||
21 | /* Middle-to-low level generation of rtx code and insns. | |
22 | ||
f822fcf7 KH |
23 | This file contains support functions for creating rtl expressions |
24 | and manipulating them in the doubly-linked chain of insns. | |
23b2ce53 RS |
25 | |
26 | The patterns of the insns are created by machine-dependent | |
27 | routines in insn-emit.c, which is generated automatically from | |
f822fcf7 KH |
28 | the machine description. These routines make the individual rtx's |
29 | of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch], | |
30 | which are automatically generated from rtl.def; what is machine | |
a2a8cc44 KH |
31 | dependent is the kind of rtx's they make and what arguments they |
32 | use. */ | |
23b2ce53 RS |
33 | |
34 | #include "config.h" | |
670ee920 | 35 | #include "system.h" |
4977bab6 | 36 | #include "coretypes.h" |
4d0cdd0c | 37 | #include "memmodel.h" |
c7131fb2 | 38 | #include "backend.h" |
957060b5 | 39 | #include "target.h" |
23b2ce53 | 40 | #include "rtl.h" |
957060b5 | 41 | #include "tree.h" |
c7131fb2 | 42 | #include "df.h" |
957060b5 AM |
43 | #include "tm_p.h" |
44 | #include "stringpool.h" | |
957060b5 AM |
45 | #include "insn-config.h" |
46 | #include "regs.h" | |
47 | #include "emit-rtl.h" | |
48 | #include "recog.h" | |
c7131fb2 | 49 | #include "diagnostic-core.h" |
40e23961 | 50 | #include "alias.h" |
40e23961 | 51 | #include "fold-const.h" |
d8a2d370 | 52 | #include "varasm.h" |
60393bbc | 53 | #include "cfgrtl.h" |
60393bbc | 54 | #include "tree-eh.h" |
36566b39 | 55 | #include "explow.h" |
23b2ce53 | 56 | #include "expr.h" |
9b2b7279 | 57 | #include "builtins.h" |
9021b8ec | 58 | #include "rtl-iter.h" |
1f9ceff1 | 59 | #include "stor-layout.h" |
ecf835e9 | 60 | #include "opts.h" |
5fa396ad | 61 | #include "predict.h" |
3877c560 | 62 | #include "rtx-vector-builder.h" |
fa70c221 RB |
63 | #include "gimple.h" |
64 | #include "gimple-ssa.h" | |
65 | #include "gimplify.h" | |
ca695ac9 | 66 | |
5fb0e246 RS |
67 | struct target_rtl default_target_rtl; |
68 | #if SWITCHABLE_TARGET | |
69 | struct target_rtl *this_target_rtl = &default_target_rtl; | |
70 | #endif | |
71 | ||
72 | #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx) | |
73 | ||
1d445e9e ILT |
74 | /* Commonly used modes. */ |
75 | ||
501623d4 RS |
76 | scalar_int_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
77 | scalar_int_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
78 | scalar_int_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ | |
1d445e9e | 79 | |
bd60bab2 JH |
80 | /* Datastructures maintained for currently processed function in RTL form. */ |
81 | ||
3e029763 | 82 | struct rtl_data x_rtl; |
bd60bab2 JH |
83 | |
84 | /* Indexed by pseudo register number, gives the rtx for that pseudo. | |
b8698a0f | 85 | Allocated in parallel with regno_pointer_align. |
bd60bab2 JH |
86 | FIXME: We could put it into emit_status struct, but gengtype is not able to deal |
87 | with length attribute nested in top level structures. */ | |
88 | ||
89 | rtx * regno_reg_rtx; | |
23b2ce53 RS |
90 | |
91 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
92 | in the entire compilation a unique label number. */ | |
93 | ||
044b4de3 | 94 | static GTY(()) int label_num = 1; |
23b2ce53 | 95 | |
23b2ce53 RS |
96 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
97 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
e7c82a99 JJ |
98 | record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX |
99 | is set only for MODE_INT and MODE_VECTOR_INT modes. */ | |
23b2ce53 | 100 | |
e7c82a99 | 101 | rtx const_tiny_rtx[4][(int) MAX_MACHINE_MODE]; |
23b2ce53 | 102 | |
68d75312 JC |
103 | rtx const_true_rtx; |
104 | ||
23b2ce53 RS |
105 | REAL_VALUE_TYPE dconst0; |
106 | REAL_VALUE_TYPE dconst1; | |
107 | REAL_VALUE_TYPE dconst2; | |
108 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 | 109 | REAL_VALUE_TYPE dconsthalf; |
23b2ce53 | 110 | |
325217ed CF |
111 | /* Record fixed-point constant 0 and 1. */ |
112 | FIXED_VALUE_TYPE fconst0[MAX_FCONST0]; | |
113 | FIXED_VALUE_TYPE fconst1[MAX_FCONST1]; | |
114 | ||
23b2ce53 RS |
115 | /* We make one copy of (const_int C) where C is in |
116 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
117 | to save space during the compilation and simplify comparisons of | |
118 | integers. */ | |
119 | ||
5da077de | 120 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 121 | |
ca4adc91 RS |
122 | /* Standard pieces of rtx, to be substituted directly into things. */ |
123 | rtx pc_rtx; | |
124 | rtx ret_rtx; | |
125 | rtx simple_return_rtx; | |
ca4adc91 | 126 | |
1476d1bd MM |
127 | /* Marker used for denoting an INSN, which should never be accessed (i.e., |
128 | this pointer should normally never be dereferenced), but is required to be | |
129 | distinct from NULL_RTX. Currently used by peephole2 pass. */ | |
130 | rtx_insn *invalid_insn_rtx; | |
131 | ||
c13e8210 MM |
132 | /* A hash table storing CONST_INTs whose absolute value is greater |
133 | than MAX_SAVED_CONST_INT. */ | |
134 | ||
6c907cff | 135 | struct const_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
136 | { |
137 | typedef HOST_WIDE_INT compare_type; | |
138 | ||
139 | static hashval_t hash (rtx i); | |
140 | static bool equal (rtx i, HOST_WIDE_INT h); | |
141 | }; | |
c13e8210 | 142 | |
aebf76a2 TS |
143 | static GTY ((cache)) hash_table<const_int_hasher> *const_int_htab; |
144 | ||
6c907cff | 145 | struct const_wide_int_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
146 | { |
147 | static hashval_t hash (rtx x); | |
148 | static bool equal (rtx x, rtx y); | |
149 | }; | |
150 | ||
151 | static GTY ((cache)) hash_table<const_wide_int_hasher> *const_wide_int_htab; | |
807e902e | 152 | |
0c12fc9b RS |
153 | struct const_poly_int_hasher : ggc_cache_ptr_hash<rtx_def> |
154 | { | |
155 | typedef std::pair<machine_mode, poly_wide_int_ref> compare_type; | |
156 | ||
157 | static hashval_t hash (rtx x); | |
158 | static bool equal (rtx x, const compare_type &y); | |
159 | }; | |
160 | ||
161 | static GTY ((cache)) hash_table<const_poly_int_hasher> *const_poly_int_htab; | |
162 | ||
a560d4d4 | 163 | /* A hash table storing register attribute structures. */ |
6c907cff | 164 | struct reg_attr_hasher : ggc_cache_ptr_hash<reg_attrs> |
aebf76a2 TS |
165 | { |
166 | static hashval_t hash (reg_attrs *x); | |
167 | static bool equal (reg_attrs *a, reg_attrs *b); | |
168 | }; | |
169 | ||
170 | static GTY ((cache)) hash_table<reg_attr_hasher> *reg_attrs_htab; | |
a560d4d4 | 171 | |
5692c7bc | 172 | /* A hash table storing all CONST_DOUBLEs. */ |
6c907cff | 173 | struct const_double_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
174 | { |
175 | static hashval_t hash (rtx x); | |
176 | static bool equal (rtx x, rtx y); | |
177 | }; | |
178 | ||
179 | static GTY ((cache)) hash_table<const_double_hasher> *const_double_htab; | |
5692c7bc | 180 | |
091a3ac7 | 181 | /* A hash table storing all CONST_FIXEDs. */ |
6c907cff | 182 | struct const_fixed_hasher : ggc_cache_ptr_hash<rtx_def> |
aebf76a2 TS |
183 | { |
184 | static hashval_t hash (rtx x); | |
185 | static bool equal (rtx x, rtx y); | |
186 | }; | |
187 | ||
188 | static GTY ((cache)) hash_table<const_fixed_hasher> *const_fixed_htab; | |
091a3ac7 | 189 | |
3e029763 | 190 | #define cur_insn_uid (crtl->emit.x_cur_insn_uid) |
b5b8b0ac | 191 | #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid) |
3e029763 | 192 | #define first_label_num (crtl->emit.x_first_label_num) |
23b2ce53 | 193 | |
5eb2a9f2 | 194 | static void set_used_decls (tree); |
502b8322 | 195 | static void mark_label_nuses (rtx); |
807e902e | 196 | #if TARGET_SUPPORTS_WIDE_INT |
807e902e KZ |
197 | static rtx lookup_const_wide_int (rtx); |
198 | #endif | |
502b8322 | 199 | static rtx lookup_const_double (rtx); |
091a3ac7 | 200 | static rtx lookup_const_fixed (rtx); |
ef4bddc2 | 201 | static rtx gen_const_vector (machine_mode, int); |
32b32b16 | 202 | static void copy_rtx_if_shared_1 (rtx *orig); |
c13e8210 | 203 | |
5fa396ad JH |
204 | /* Probability of the conditional branch currently proceeded by try_split. */ |
205 | profile_probability split_branch_probability; | |
ca695ac9 | 206 | \f |
c13e8210 MM |
207 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
208 | ||
aebf76a2 TS |
209 | hashval_t |
210 | const_int_hasher::hash (rtx x) | |
c13e8210 | 211 | { |
aebf76a2 | 212 | return (hashval_t) INTVAL (x); |
c13e8210 MM |
213 | } |
214 | ||
cc2902df | 215 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
216 | CONST_INT) is the same as that given by Y (which is really a |
217 | HOST_WIDE_INT *). */ | |
218 | ||
aebf76a2 TS |
219 | bool |
220 | const_int_hasher::equal (rtx x, HOST_WIDE_INT y) | |
c13e8210 | 221 | { |
aebf76a2 | 222 | return (INTVAL (x) == y); |
5692c7bc ZW |
223 | } |
224 | ||
807e902e KZ |
225 | #if TARGET_SUPPORTS_WIDE_INT |
226 | /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */ | |
227 | ||
aebf76a2 TS |
228 | hashval_t |
229 | const_wide_int_hasher::hash (rtx x) | |
807e902e KZ |
230 | { |
231 | int i; | |
d7ca26e4 | 232 | unsigned HOST_WIDE_INT hash = 0; |
aebf76a2 | 233 | const_rtx xr = x; |
807e902e KZ |
234 | |
235 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
236 | hash += CONST_WIDE_INT_ELT (xr, i); | |
237 | ||
238 | return (hashval_t) hash; | |
239 | } | |
240 | ||
241 | /* Returns nonzero if the value represented by X (which is really a | |
242 | CONST_WIDE_INT) is the same as that given by Y (which is really a | |
243 | CONST_WIDE_INT). */ | |
244 | ||
aebf76a2 TS |
245 | bool |
246 | const_wide_int_hasher::equal (rtx x, rtx y) | |
807e902e KZ |
247 | { |
248 | int i; | |
aebf76a2 TS |
249 | const_rtx xr = x; |
250 | const_rtx yr = y; | |
807e902e | 251 | if (CONST_WIDE_INT_NUNITS (xr) != CONST_WIDE_INT_NUNITS (yr)) |
aebf76a2 | 252 | return false; |
807e902e KZ |
253 | |
254 | for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++) | |
255 | if (CONST_WIDE_INT_ELT (xr, i) != CONST_WIDE_INT_ELT (yr, i)) | |
aebf76a2 | 256 | return false; |
807e902e | 257 | |
aebf76a2 | 258 | return true; |
807e902e KZ |
259 | } |
260 | #endif | |
261 | ||
0c12fc9b RS |
262 | /* Returns a hash code for CONST_POLY_INT X. */ |
263 | ||
264 | hashval_t | |
265 | const_poly_int_hasher::hash (rtx x) | |
266 | { | |
267 | inchash::hash h; | |
268 | h.add_int (GET_MODE (x)); | |
269 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
270 | h.add_wide_int (CONST_POLY_INT_COEFFS (x)[i]); | |
271 | return h.end (); | |
272 | } | |
273 | ||
274 | /* Returns nonzero if CONST_POLY_INT X is an rtx representation of Y. */ | |
275 | ||
276 | bool | |
277 | const_poly_int_hasher::equal (rtx x, const compare_type &y) | |
278 | { | |
279 | if (GET_MODE (x) != y.first) | |
280 | return false; | |
281 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
282 | if (CONST_POLY_INT_COEFFS (x)[i] != y.second.coeffs[i]) | |
283 | return false; | |
284 | return true; | |
285 | } | |
286 | ||
5692c7bc | 287 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ |
aebf76a2 TS |
288 | hashval_t |
289 | const_double_hasher::hash (rtx x) | |
5692c7bc | 290 | { |
aebf76a2 | 291 | const_rtx const value = x; |
46b33600 | 292 | hashval_t h; |
5692c7bc | 293 | |
807e902e | 294 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (value) == VOIDmode) |
46b33600 RH |
295 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); |
296 | else | |
fe352c29 | 297 | { |
15c812e3 | 298 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
299 | /* MODE is used in the comparison, so it should be in the hash. */ |
300 | h ^= GET_MODE (value); | |
301 | } | |
5692c7bc ZW |
302 | return h; |
303 | } | |
304 | ||
cc2902df | 305 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc | 306 | is the same as that represented by Y (really a ...) */ |
aebf76a2 TS |
307 | bool |
308 | const_double_hasher::equal (rtx x, rtx y) | |
5692c7bc | 309 | { |
aebf76a2 | 310 | const_rtx const a = x, b = y; |
5692c7bc ZW |
311 | |
312 | if (GET_MODE (a) != GET_MODE (b)) | |
313 | return 0; | |
807e902e | 314 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (a) == VOIDmode) |
8580f7a0 RH |
315 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) |
316 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
317 | else | |
318 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
319 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
320 | } |
321 | ||
091a3ac7 CF |
322 | /* Returns a hash code for X (which is really a CONST_FIXED). */ |
323 | ||
aebf76a2 TS |
324 | hashval_t |
325 | const_fixed_hasher::hash (rtx x) | |
091a3ac7 | 326 | { |
aebf76a2 | 327 | const_rtx const value = x; |
091a3ac7 CF |
328 | hashval_t h; |
329 | ||
330 | h = fixed_hash (CONST_FIXED_VALUE (value)); | |
331 | /* MODE is used in the comparison, so it should be in the hash. */ | |
332 | h ^= GET_MODE (value); | |
333 | return h; | |
334 | } | |
335 | ||
aebf76a2 TS |
336 | /* Returns nonzero if the value represented by X is the same as that |
337 | represented by Y. */ | |
091a3ac7 | 338 | |
aebf76a2 TS |
339 | bool |
340 | const_fixed_hasher::equal (rtx x, rtx y) | |
091a3ac7 | 341 | { |
aebf76a2 | 342 | const_rtx const a = x, b = y; |
091a3ac7 CF |
343 | |
344 | if (GET_MODE (a) != GET_MODE (b)) | |
345 | return 0; | |
346 | return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b)); | |
347 | } | |
348 | ||
f12144dd | 349 | /* Return true if the given memory attributes are equal. */ |
c13e8210 | 350 | |
96b3c03f | 351 | bool |
99b1c316 | 352 | mem_attrs_eq_p (const class mem_attrs *p, const class mem_attrs *q) |
c13e8210 | 353 | { |
96b3c03f RB |
354 | if (p == q) |
355 | return true; | |
356 | if (!p || !q) | |
357 | return false; | |
754c3d5d RS |
358 | return (p->alias == q->alias |
359 | && p->offset_known_p == q->offset_known_p | |
d05d7551 | 360 | && (!p->offset_known_p || known_eq (p->offset, q->offset)) |
754c3d5d | 361 | && p->size_known_p == q->size_known_p |
d05d7551 | 362 | && (!p->size_known_p || known_eq (p->size, q->size)) |
754c3d5d | 363 | && p->align == q->align |
09e881c9 | 364 | && p->addrspace == q->addrspace |
78b76d08 SB |
365 | && (p->expr == q->expr |
366 | || (p->expr != NULL_TREE && q->expr != NULL_TREE | |
367 | && operand_equal_p (p->expr, q->expr, 0)))); | |
c13e8210 MM |
368 | } |
369 | ||
f12144dd | 370 | /* Set MEM's memory attributes so that they are the same as ATTRS. */ |
10b76d73 | 371 | |
f12144dd RS |
372 | static void |
373 | set_mem_attrs (rtx mem, mem_attrs *attrs) | |
374 | { | |
f12144dd RS |
375 | /* If everything is the default, we can just clear the attributes. */ |
376 | if (mem_attrs_eq_p (attrs, mode_mem_attrs[(int) GET_MODE (mem)])) | |
377 | { | |
378 | MEM_ATTRS (mem) = 0; | |
379 | return; | |
380 | } | |
173b24b9 | 381 | |
84053e02 RB |
382 | if (!MEM_ATTRS (mem) |
383 | || !mem_attrs_eq_p (attrs, MEM_ATTRS (mem))) | |
173b24b9 | 384 | { |
766090c2 | 385 | MEM_ATTRS (mem) = ggc_alloc<mem_attrs> (); |
84053e02 | 386 | memcpy (MEM_ATTRS (mem), attrs, sizeof (mem_attrs)); |
173b24b9 | 387 | } |
c13e8210 MM |
388 | } |
389 | ||
a560d4d4 JH |
390 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
391 | ||
aebf76a2 TS |
392 | hashval_t |
393 | reg_attr_hasher::hash (reg_attrs *x) | |
a560d4d4 | 394 | { |
aebf76a2 | 395 | const reg_attrs *const p = x; |
a560d4d4 | 396 | |
84bc717b RS |
397 | inchash::hash h; |
398 | h.add_ptr (p->decl); | |
399 | h.add_poly_hwi (p->offset); | |
400 | return h.end (); | |
a560d4d4 JH |
401 | } |
402 | ||
aebf76a2 TS |
403 | /* Returns nonzero if the value represented by X is the same as that given by |
404 | Y. */ | |
a560d4d4 | 405 | |
aebf76a2 TS |
406 | bool |
407 | reg_attr_hasher::equal (reg_attrs *x, reg_attrs *y) | |
a560d4d4 | 408 | { |
aebf76a2 TS |
409 | const reg_attrs *const p = x; |
410 | const reg_attrs *const q = y; | |
a560d4d4 | 411 | |
84bc717b | 412 | return (p->decl == q->decl && known_eq (p->offset, q->offset)); |
a560d4d4 JH |
413 | } |
414 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
415 | one identical to it is not already in the table. We are doing this for | |
416 | MEM of mode MODE. */ | |
417 | ||
418 | static reg_attrs * | |
84bc717b | 419 | get_reg_attrs (tree decl, poly_int64 offset) |
a560d4d4 JH |
420 | { |
421 | reg_attrs attrs; | |
a560d4d4 JH |
422 | |
423 | /* If everything is the default, we can just return zero. */ | |
84bc717b | 424 | if (decl == 0 && known_eq (offset, 0)) |
a560d4d4 JH |
425 | return 0; |
426 | ||
427 | attrs.decl = decl; | |
428 | attrs.offset = offset; | |
429 | ||
aebf76a2 | 430 | reg_attrs **slot = reg_attrs_htab->find_slot (&attrs, INSERT); |
a560d4d4 JH |
431 | if (*slot == 0) |
432 | { | |
766090c2 | 433 | *slot = ggc_alloc<reg_attrs> (); |
a560d4d4 JH |
434 | memcpy (*slot, &attrs, sizeof (reg_attrs)); |
435 | } | |
436 | ||
aebf76a2 | 437 | return *slot; |
a560d4d4 JH |
438 | } |
439 | ||
6fb5fa3c DB |
440 | |
441 | #if !HAVE_blockage | |
adddc347 HPN |
442 | /* Generate an empty ASM_INPUT, which is used to block attempts to schedule, |
443 | and to block register equivalences to be seen across this insn. */ | |
6fb5fa3c DB |
444 | |
445 | rtx | |
446 | gen_blockage (void) | |
447 | { | |
448 | rtx x = gen_rtx_ASM_INPUT (VOIDmode, ""); | |
449 | MEM_VOLATILE_P (x) = true; | |
450 | return x; | |
451 | } | |
452 | #endif | |
453 | ||
454 | ||
8deccbb7 RS |
455 | /* Set the mode and register number of X to MODE and REGNO. */ |
456 | ||
457 | void | |
458 | set_mode_and_regno (rtx x, machine_mode mode, unsigned int regno) | |
459 | { | |
9188b286 | 460 | unsigned int nregs = (HARD_REGISTER_NUM_P (regno) |
ad474626 | 461 | ? hard_regno_nregs (regno, mode) |
9188b286 | 462 | : 1); |
8deccbb7 | 463 | PUT_MODE_RAW (x, mode); |
9188b286 | 464 | set_regno_raw (x, regno, nregs); |
8deccbb7 RS |
465 | } |
466 | ||
20fa157e IL |
467 | /* Initialize a fresh REG rtx with mode MODE and register REGNO. */ |
468 | ||
469 | rtx | |
470 | init_raw_REG (rtx x, machine_mode mode, unsigned int regno) | |
471 | { | |
472 | set_mode_and_regno (x, mode, regno); | |
473 | REG_ATTRS (x) = NULL; | |
474 | ORIGINAL_REGNO (x) = regno; | |
475 | return x; | |
476 | } | |
477 | ||
08394eef BS |
478 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
479 | don't attempt to share with the various global pieces of rtl (such as | |
480 | frame_pointer_rtx). */ | |
481 | ||
482 | rtx | |
8deccbb7 | 483 | gen_raw_REG (machine_mode mode, unsigned int regno) |
08394eef | 484 | { |
84c2ad23 | 485 | rtx x = rtx_alloc (REG MEM_STAT_INFO); |
20fa157e | 486 | init_raw_REG (x, mode, regno); |
08394eef BS |
487 | return x; |
488 | } | |
489 | ||
c5c76735 JL |
490 | /* There are some RTL codes that require special attention; the generation |
491 | functions do the raw handling. If you add to this list, modify | |
492 | special_rtx in gengenrtl.c as well. */ | |
493 | ||
38e60c55 | 494 | rtx_expr_list * |
ef4bddc2 | 495 | gen_rtx_EXPR_LIST (machine_mode mode, rtx expr, rtx expr_list) |
38e60c55 DM |
496 | { |
497 | return as_a <rtx_expr_list *> (gen_rtx_fmt_ee (EXPR_LIST, mode, expr, | |
498 | expr_list)); | |
499 | } | |
500 | ||
a756c6be | 501 | rtx_insn_list * |
ef4bddc2 | 502 | gen_rtx_INSN_LIST (machine_mode mode, rtx insn, rtx insn_list) |
a756c6be DM |
503 | { |
504 | return as_a <rtx_insn_list *> (gen_rtx_fmt_ue (INSN_LIST, mode, insn, | |
505 | insn_list)); | |
506 | } | |
507 | ||
d6e1e8b8 | 508 | rtx_insn * |
ef4bddc2 | 509 | gen_rtx_INSN (machine_mode mode, rtx_insn *prev_insn, rtx_insn *next_insn, |
d6e1e8b8 DM |
510 | basic_block bb, rtx pattern, int location, int code, |
511 | rtx reg_notes) | |
512 | { | |
513 | return as_a <rtx_insn *> (gen_rtx_fmt_uuBeiie (INSN, mode, | |
514 | prev_insn, next_insn, | |
515 | bb, pattern, location, code, | |
516 | reg_notes)); | |
517 | } | |
518 | ||
3b80f6ca | 519 | rtx |
ef4bddc2 | 520 | gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca RH |
521 | { |
522 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) | |
5da077de | 523 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
524 | |
525 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
526 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
527 | return const_true_rtx; | |
528 | #endif | |
529 | ||
c13e8210 | 530 | /* Look up the CONST_INT in the hash table. */ |
aebf76a2 TS |
531 | rtx *slot = const_int_htab->find_slot_with_hash (arg, (hashval_t) arg, |
532 | INSERT); | |
29105cea | 533 | if (*slot == 0) |
1f8f4a0b | 534 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 | 535 | |
aebf76a2 | 536 | return *slot; |
3b80f6ca RH |
537 | } |
538 | ||
2496c7bd | 539 | rtx |
0c12fc9b | 540 | gen_int_mode (poly_int64 c, machine_mode mode) |
2496c7bd | 541 | { |
0c12fc9b RS |
542 | c = trunc_int_for_mode (c, mode); |
543 | if (c.is_constant ()) | |
544 | return GEN_INT (c.coeffs[0]); | |
545 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
546 | return immed_wide_int_const (poly_wide_int::from (c, prec, SIGNED), mode); | |
2496c7bd LB |
547 | } |
548 | ||
5692c7bc ZW |
549 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
550 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
551 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
552 | ||
553 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
554 | hash table. If so, return its counterpart; otherwise add it | |
555 | to the hash table and return it. */ | |
556 | static rtx | |
502b8322 | 557 | lookup_const_double (rtx real) |
5692c7bc | 558 | { |
aebf76a2 | 559 | rtx *slot = const_double_htab->find_slot (real, INSERT); |
5692c7bc ZW |
560 | if (*slot == 0) |
561 | *slot = real; | |
562 | ||
aebf76a2 | 563 | return *slot; |
5692c7bc | 564 | } |
29105cea | 565 | |
5692c7bc ZW |
566 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
567 | VALUE in mode MODE. */ | |
0133b7d9 | 568 | rtx |
ef4bddc2 | 569 | const_double_from_real_value (REAL_VALUE_TYPE value, machine_mode mode) |
0133b7d9 | 570 | { |
5692c7bc ZW |
571 | rtx real = rtx_alloc (CONST_DOUBLE); |
572 | PUT_MODE (real, mode); | |
573 | ||
9e254451 | 574 | real->u.rv = value; |
5692c7bc ZW |
575 | |
576 | return lookup_const_double (real); | |
577 | } | |
578 | ||
091a3ac7 CF |
579 | /* Determine whether FIXED, a CONST_FIXED, already exists in the |
580 | hash table. If so, return its counterpart; otherwise add it | |
581 | to the hash table and return it. */ | |
582 | ||
583 | static rtx | |
584 | lookup_const_fixed (rtx fixed) | |
585 | { | |
aebf76a2 | 586 | rtx *slot = const_fixed_htab->find_slot (fixed, INSERT); |
091a3ac7 CF |
587 | if (*slot == 0) |
588 | *slot = fixed; | |
589 | ||
aebf76a2 | 590 | return *slot; |
091a3ac7 CF |
591 | } |
592 | ||
593 | /* Return a CONST_FIXED rtx for a fixed-point value specified by | |
594 | VALUE in mode MODE. */ | |
595 | ||
596 | rtx | |
ef4bddc2 | 597 | const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, machine_mode mode) |
091a3ac7 CF |
598 | { |
599 | rtx fixed = rtx_alloc (CONST_FIXED); | |
600 | PUT_MODE (fixed, mode); | |
601 | ||
602 | fixed->u.fv = value; | |
603 | ||
604 | return lookup_const_fixed (fixed); | |
605 | } | |
606 | ||
807e902e | 607 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
3e93ff81 AS |
608 | /* Constructs double_int from rtx CST. */ |
609 | ||
610 | double_int | |
611 | rtx_to_double_int (const_rtx cst) | |
612 | { | |
613 | double_int r; | |
614 | ||
615 | if (CONST_INT_P (cst)) | |
27bcd47c | 616 | r = double_int::from_shwi (INTVAL (cst)); |
48175537 | 617 | else if (CONST_DOUBLE_AS_INT_P (cst)) |
3e93ff81 AS |
618 | { |
619 | r.low = CONST_DOUBLE_LOW (cst); | |
620 | r.high = CONST_DOUBLE_HIGH (cst); | |
621 | } | |
622 | else | |
623 | gcc_unreachable (); | |
624 | ||
625 | return r; | |
626 | } | |
807e902e | 627 | #endif |
3e93ff81 | 628 | |
807e902e KZ |
629 | #if TARGET_SUPPORTS_WIDE_INT |
630 | /* Determine whether CONST_WIDE_INT WINT already exists in the hash table. | |
631 | If so, return its counterpart; otherwise add it to the hash table and | |
632 | return it. */ | |
3e93ff81 | 633 | |
807e902e KZ |
634 | static rtx |
635 | lookup_const_wide_int (rtx wint) | |
636 | { | |
aebf76a2 | 637 | rtx *slot = const_wide_int_htab->find_slot (wint, INSERT); |
807e902e KZ |
638 | if (*slot == 0) |
639 | *slot = wint; | |
640 | ||
aebf76a2 | 641 | return *slot; |
807e902e KZ |
642 | } |
643 | #endif | |
644 | ||
645 | /* Return an rtx constant for V, given that the constant has mode MODE. | |
646 | The returned rtx will be a CONST_INT if V fits, otherwise it will be | |
647 | a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT | |
648 | (if TARGET_SUPPORTS_WIDE_INT). */ | |
54fb1ae0 | 649 | |
0c12fc9b RS |
650 | static rtx |
651 | immed_wide_int_const_1 (const wide_int_ref &v, machine_mode mode) | |
54fb1ae0 | 652 | { |
807e902e | 653 | unsigned int len = v.get_len (); |
db61b7f9 RS |
654 | /* Not scalar_int_mode because we also allow pointer bound modes. */ |
655 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
807e902e KZ |
656 | |
657 | /* Allow truncation but not extension since we do not know if the | |
658 | number is signed or unsigned. */ | |
659 | gcc_assert (prec <= v.get_precision ()); | |
660 | ||
661 | if (len < 2 || prec <= HOST_BITS_PER_WIDE_INT) | |
662 | return gen_int_mode (v.elt (0), mode); | |
663 | ||
664 | #if TARGET_SUPPORTS_WIDE_INT | |
665 | { | |
666 | unsigned int i; | |
667 | rtx value; | |
668 | unsigned int blocks_needed | |
669 | = (prec + HOST_BITS_PER_WIDE_INT - 1) / HOST_BITS_PER_WIDE_INT; | |
670 | ||
671 | if (len > blocks_needed) | |
672 | len = blocks_needed; | |
673 | ||
674 | value = const_wide_int_alloc (len); | |
675 | ||
676 | /* It is so tempting to just put the mode in here. Must control | |
677 | myself ... */ | |
678 | PUT_MODE (value, VOIDmode); | |
679 | CWI_PUT_NUM_ELEM (value, len); | |
680 | ||
681 | for (i = 0; i < len; i++) | |
682 | CONST_WIDE_INT_ELT (value, i) = v.elt (i); | |
683 | ||
684 | return lookup_const_wide_int (value); | |
685 | } | |
686 | #else | |
687 | return immed_double_const (v.elt (0), v.elt (1), mode); | |
688 | #endif | |
54fb1ae0 AS |
689 | } |
690 | ||
807e902e | 691 | #if TARGET_SUPPORTS_WIDE_INT == 0 |
5692c7bc ZW |
692 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair |
693 | of ints: I0 is the low-order word and I1 is the high-order word. | |
49ab6098 | 694 | For values that are larger than HOST_BITS_PER_DOUBLE_INT, the |
929e10f4 MS |
695 | implied upper bits are copies of the high bit of i1. The value |
696 | itself is neither signed nor unsigned. Do not use this routine for | |
697 | non-integer modes; convert to REAL_VALUE_TYPE and use | |
555affd7 | 698 | const_double_from_real_value. */ |
5692c7bc ZW |
699 | |
700 | rtx | |
ef4bddc2 | 701 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, machine_mode mode) |
5692c7bc ZW |
702 | { |
703 | rtx value; | |
704 | unsigned int i; | |
705 | ||
65acccdd | 706 | /* There are the following cases (note that there are no modes with |
49ab6098 | 707 | HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT): |
65acccdd ZD |
708 | |
709 | 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use | |
710 | gen_int_mode. | |
929e10f4 MS |
711 | 2) If the value of the integer fits into HOST_WIDE_INT anyway |
712 | (i.e., i1 consists only from copies of the sign bit, and sign | |
713 | of i0 and i1 are the same), then we return a CONST_INT for i0. | |
65acccdd | 714 | 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */ |
db61b7f9 RS |
715 | scalar_mode smode; |
716 | if (is_a <scalar_mode> (mode, &smode) | |
717 | && GET_MODE_BITSIZE (smode) <= HOST_BITS_PER_WIDE_INT) | |
718 | return gen_int_mode (i0, mode); | |
5692c7bc ZW |
719 | |
720 | /* If this integer fits in one word, return a CONST_INT. */ | |
721 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
722 | return GEN_INT (i0); | |
723 | ||
724 | /* We use VOIDmode for integers. */ | |
725 | value = rtx_alloc (CONST_DOUBLE); | |
726 | PUT_MODE (value, VOIDmode); | |
727 | ||
728 | CONST_DOUBLE_LOW (value) = i0; | |
729 | CONST_DOUBLE_HIGH (value) = i1; | |
730 | ||
731 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
732 | XWINT (value, i) = 0; | |
733 | ||
734 | return lookup_const_double (value); | |
0133b7d9 | 735 | } |
807e902e | 736 | #endif |
0133b7d9 | 737 | |
0c12fc9b RS |
738 | /* Return an rtx representation of C in mode MODE. */ |
739 | ||
740 | rtx | |
741 | immed_wide_int_const (const poly_wide_int_ref &c, machine_mode mode) | |
742 | { | |
743 | if (c.is_constant ()) | |
744 | return immed_wide_int_const_1 (c.coeffs[0], mode); | |
745 | ||
746 | /* Not scalar_int_mode because we also allow pointer bound modes. */ | |
747 | unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode)); | |
748 | ||
749 | /* Allow truncation but not extension since we do not know if the | |
750 | number is signed or unsigned. */ | |
751 | gcc_assert (prec <= c.coeffs[0].get_precision ()); | |
752 | poly_wide_int newc = poly_wide_int::from (c, prec, SIGNED); | |
753 | ||
754 | /* See whether we already have an rtx for this constant. */ | |
755 | inchash::hash h; | |
756 | h.add_int (mode); | |
757 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
758 | h.add_wide_int (newc.coeffs[i]); | |
759 | const_poly_int_hasher::compare_type typed_value (mode, newc); | |
760 | rtx *slot = const_poly_int_htab->find_slot_with_hash (typed_value, | |
761 | h.end (), INSERT); | |
762 | rtx x = *slot; | |
763 | if (x) | |
764 | return x; | |
765 | ||
766 | /* Create a new rtx. There's a choice to be made here between installing | |
767 | the actual mode of the rtx or leaving it as VOIDmode (for consistency | |
768 | with CONST_INT). In practice the handling of the codes is different | |
769 | enough that we get no benefit from using VOIDmode, and various places | |
770 | assume that VOIDmode implies CONST_INT. Using the real mode seems like | |
771 | the right long-term direction anyway. */ | |
772 | typedef trailing_wide_ints<NUM_POLY_INT_COEFFS> twi; | |
773 | size_t extra_size = twi::extra_size (prec); | |
774 | x = rtx_alloc_v (CONST_POLY_INT, | |
775 | sizeof (struct const_poly_int_def) + extra_size); | |
776 | PUT_MODE (x, mode); | |
777 | CONST_POLY_INT_COEFFS (x).set_precision (prec); | |
778 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
779 | CONST_POLY_INT_COEFFS (x)[i] = newc.coeffs[i]; | |
780 | ||
781 | *slot = x; | |
782 | return x; | |
783 | } | |
784 | ||
3b80f6ca | 785 | rtx |
ef4bddc2 | 786 | gen_rtx_REG (machine_mode mode, unsigned int regno) |
3b80f6ca RH |
787 | { |
788 | /* In case the MD file explicitly references the frame pointer, have | |
789 | all such references point to the same frame pointer. This is | |
790 | used during frame pointer elimination to distinguish the explicit | |
791 | references to these registers from pseudos that happened to be | |
792 | assigned to them. | |
793 | ||
794 | If we have eliminated the frame pointer or arg pointer, we will | |
795 | be using it as a normal register, for example as a spill | |
796 | register. In such cases, we might be accessing it in a mode that | |
797 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
798 | ||
799 | Also don't do this when we are making new REGs in reload, since | |
800 | we don't want to get confused with the real pointers. */ | |
801 | ||
55a2c322 | 802 | if (mode == Pmode && !reload_in_progress && !lra_in_progress) |
3b80f6ca | 803 | { |
e10c79fe LB |
804 | if (regno == FRAME_POINTER_REGNUM |
805 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca | 806 | return frame_pointer_rtx; |
c3e08036 TS |
807 | |
808 | if (!HARD_FRAME_POINTER_IS_FRAME_POINTER | |
809 | && regno == HARD_FRAME_POINTER_REGNUM | |
e10c79fe | 810 | && (!reload_completed || frame_pointer_needed)) |
3b80f6ca | 811 | return hard_frame_pointer_rtx; |
3f393fc6 TS |
812 | #if !HARD_FRAME_POINTER_IS_ARG_POINTER |
813 | if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
814 | && regno == ARG_POINTER_REGNUM) | |
3b80f6ca RH |
815 | return arg_pointer_rtx; |
816 | #endif | |
817 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 818 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
819 | return return_address_pointer_rtx; |
820 | #endif | |
fc555370 | 821 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
bf9412cd | 822 | && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM |
2d67bd7b | 823 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 824 | return pic_offset_table_rtx; |
bcb33994 | 825 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
826 | return stack_pointer_rtx; |
827 | } | |
828 | ||
006a94b0 | 829 | #if 0 |
6cde4876 | 830 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
831 | an existing entry in that table to avoid useless generation of RTL. |
832 | ||
833 | This code is disabled for now until we can fix the various backends | |
834 | which depend on having non-shared hard registers in some cases. Long | |
835 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
836 | on the amount of useless RTL that gets generated. |
837 | ||
838 | We'll also need to fix some code that runs after reload that wants to | |
839 | set ORIGINAL_REGNO. */ | |
840 | ||
6cde4876 JL |
841 | if (cfun |
842 | && cfun->emit | |
843 | && regno_reg_rtx | |
844 | && regno < FIRST_PSEUDO_REGISTER | |
845 | && reg_raw_mode[regno] == mode) | |
846 | return regno_reg_rtx[regno]; | |
006a94b0 | 847 | #endif |
6cde4876 | 848 | |
08394eef | 849 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
850 | } |
851 | ||
41472af8 | 852 | rtx |
ef4bddc2 | 853 | gen_rtx_MEM (machine_mode mode, rtx addr) |
41472af8 MM |
854 | { |
855 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
856 | ||
857 | /* This field is not cleared by the mere allocation of the rtx, so | |
858 | we clear it here. */ | |
173b24b9 | 859 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
860 | |
861 | return rt; | |
862 | } | |
ddef6bc7 | 863 | |
542a8afa RH |
864 | /* Generate a memory referring to non-trapping constant memory. */ |
865 | ||
866 | rtx | |
ef4bddc2 | 867 | gen_const_mem (machine_mode mode, rtx addr) |
542a8afa RH |
868 | { |
869 | rtx mem = gen_rtx_MEM (mode, addr); | |
870 | MEM_READONLY_P (mem) = 1; | |
871 | MEM_NOTRAP_P (mem) = 1; | |
872 | return mem; | |
873 | } | |
874 | ||
bf877a76 R |
875 | /* Generate a MEM referring to fixed portions of the frame, e.g., register |
876 | save areas. */ | |
877 | ||
878 | rtx | |
ef4bddc2 | 879 | gen_frame_mem (machine_mode mode, rtx addr) |
bf877a76 R |
880 | { |
881 | rtx mem = gen_rtx_MEM (mode, addr); | |
882 | MEM_NOTRAP_P (mem) = 1; | |
883 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
884 | return mem; | |
885 | } | |
886 | ||
887 | /* Generate a MEM referring to a temporary use of the stack, not part | |
888 | of the fixed stack frame. For example, something which is pushed | |
889 | by a target splitter. */ | |
890 | rtx | |
ef4bddc2 | 891 | gen_tmp_stack_mem (machine_mode mode, rtx addr) |
bf877a76 R |
892 | { |
893 | rtx mem = gen_rtx_MEM (mode, addr); | |
894 | MEM_NOTRAP_P (mem) = 1; | |
e3b5732b | 895 | if (!cfun->calls_alloca) |
bf877a76 R |
896 | set_mem_alias_set (mem, get_frame_alias_set ()); |
897 | return mem; | |
898 | } | |
899 | ||
beb72684 RH |
900 | /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if |
901 | this construct would be valid, and false otherwise. */ | |
902 | ||
903 | bool | |
ef4bddc2 | 904 | validate_subreg (machine_mode omode, machine_mode imode, |
91914e56 | 905 | const_rtx reg, poly_uint64 offset) |
ddef6bc7 | 906 | { |
fad2288b RS |
907 | poly_uint64 isize = GET_MODE_SIZE (imode); |
908 | poly_uint64 osize = GET_MODE_SIZE (omode); | |
909 | ||
910 | /* The sizes must be ordered, so that we know whether the subreg | |
911 | is partial, paradoxical or complete. */ | |
912 | if (!ordered_p (isize, osize)) | |
913 | return false; | |
beb72684 RH |
914 | |
915 | /* All subregs must be aligned. */ | |
91914e56 | 916 | if (!multiple_p (offset, osize)) |
beb72684 RH |
917 | return false; |
918 | ||
919 | /* The subreg offset cannot be outside the inner object. */ | |
91914e56 | 920 | if (maybe_ge (offset, isize)) |
beb72684 RH |
921 | return false; |
922 | ||
fad2288b | 923 | poly_uint64 regsize = REGMODE_NATURAL_SIZE (imode); |
1eae67f8 | 924 | |
beb72684 RH |
925 | /* ??? This should not be here. Temporarily continue to allow word_mode |
926 | subregs of anything. The most common offender is (subreg:SI (reg:DF)). | |
927 | Generally, backends are doing something sketchy but it'll take time to | |
928 | fix them all. */ | |
929 | if (omode == word_mode) | |
930 | ; | |
931 | /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field | |
932 | is the culprit here, and not the backends. */ | |
fad2288b | 933 | else if (known_ge (osize, regsize) && known_ge (isize, osize)) |
beb72684 RH |
934 | ; |
935 | /* Allow component subregs of complex and vector. Though given the below | |
936 | extraction rules, it's not always clear what that means. */ | |
937 | else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) | |
938 | && GET_MODE_INNER (imode) == omode) | |
939 | ; | |
940 | /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs, | |
9d0dc47d | 941 | i.e. (subreg:V4SF (reg:SF) 0) or (subreg:V4SF (reg:V2SF) 0). This |
942 | surely isn't the cleanest way to represent this. It's questionable | |
943 | if this ought to be represented at all -- why can't this all be hidden | |
944 | in post-reload splitters that make arbitrarily mode changes to the | |
945 | registers themselves. */ | |
946 | else if (VECTOR_MODE_P (omode) | |
947 | && GET_MODE_INNER (omode) == GET_MODE_INNER (imode)) | |
beb72684 RH |
948 | ; |
949 | /* Subregs involving floating point modes are not allowed to | |
950 | change size. Therefore (subreg:DI (reg:DF) 0) is fine, but | |
951 | (subreg:SI (reg:DF) 0) isn't. */ | |
952 | else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)) | |
953 | { | |
fad2288b | 954 | if (! (known_eq (isize, osize) |
55a2c322 VM |
955 | /* LRA can use subreg to store a floating point value in |
956 | an integer mode. Although the floating point and the | |
957 | integer modes need the same number of hard registers, | |
958 | the size of floating point mode can be less than the | |
959 | integer mode. LRA also uses subregs for a register | |
960 | should be used in different mode in on insn. */ | |
961 | || lra_in_progress)) | |
beb72684 RH |
962 | return false; |
963 | } | |
ddef6bc7 | 964 | |
beb72684 | 965 | /* Paradoxical subregs must have offset zero. */ |
fad2288b | 966 | if (maybe_gt (osize, isize)) |
91914e56 | 967 | return known_eq (offset, 0U); |
beb72684 RH |
968 | |
969 | /* This is a normal subreg. Verify that the offset is representable. */ | |
970 | ||
971 | /* For hard registers, we already have most of these rules collected in | |
972 | subreg_offset_representable_p. */ | |
973 | if (reg && REG_P (reg) && HARD_REGISTER_P (reg)) | |
974 | { | |
975 | unsigned int regno = REGNO (reg); | |
976 | ||
beb72684 RH |
977 | if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode)) |
978 | && GET_MODE_INNER (imode) == omode) | |
979 | ; | |
0d803030 | 980 | else if (!REG_CAN_CHANGE_MODE_P (regno, imode, omode)) |
beb72684 | 981 | return false; |
beb72684 RH |
982 | |
983 | return subreg_offset_representable_p (regno, imode, offset, omode); | |
984 | } | |
985 | ||
fad2288b RS |
986 | /* The outer size must be ordered wrt the register size, otherwise |
987 | we wouldn't know at compile time how many registers the outer | |
988 | mode occupies. */ | |
989 | if (!ordered_p (osize, regsize)) | |
990 | return false; | |
991 | ||
beb72684 | 992 | /* For pseudo registers, we want most of the same checks. Namely: |
1eae67f8 RS |
993 | |
994 | Assume that the pseudo register will be allocated to hard registers | |
995 | that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE, | |
996 | the remainder must correspond to the lowpart of the containing hard | |
997 | register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset, | |
998 | otherwise it is at the lowest offset. | |
999 | ||
1000 | Given that we've already checked the mode and offset alignment, | |
1001 | we only have to check subblock subregs here. */ | |
fad2288b | 1002 | if (maybe_lt (osize, regsize) |
55a2c322 | 1003 | && ! (lra_in_progress && (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode)))) |
beb72684 | 1004 | { |
fad2288b RS |
1005 | /* It is invalid for the target to pick a register size for a mode |
1006 | that isn't ordered wrt to the size of that mode. */ | |
1007 | poly_uint64 block_size = ordered_min (isize, regsize); | |
91914e56 RS |
1008 | unsigned int start_reg; |
1009 | poly_uint64 offset_within_reg; | |
1010 | if (!can_div_trunc_p (offset, block_size, &start_reg, &offset_within_reg) | |
1011 | || (BYTES_BIG_ENDIAN | |
1012 | ? maybe_ne (offset_within_reg, block_size - osize) | |
1013 | : maybe_ne (offset_within_reg, 0U))) | |
beb72684 RH |
1014 | return false; |
1015 | } | |
1016 | return true; | |
1017 | } | |
1018 | ||
1019 | rtx | |
91914e56 | 1020 | gen_rtx_SUBREG (machine_mode mode, rtx reg, poly_uint64 offset) |
beb72684 RH |
1021 | { |
1022 | gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset)); | |
5692c7bc | 1023 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
1024 | } |
1025 | ||
173b24b9 RK |
1026 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
1027 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
1028 | ||
ddef6bc7 | 1029 | rtx |
ef4bddc2 | 1030 | gen_lowpart_SUBREG (machine_mode mode, rtx reg) |
ddef6bc7 | 1031 | { |
ef4bddc2 | 1032 | machine_mode inmode; |
ddef6bc7 JJ |
1033 | |
1034 | inmode = GET_MODE (reg); | |
1035 | if (inmode == VOIDmode) | |
1036 | inmode = mode; | |
e0e08ac2 JH |
1037 | return gen_rtx_SUBREG (mode, reg, |
1038 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 1039 | } |
fcc74520 RS |
1040 | |
1041 | rtx | |
ef4bddc2 | 1042 | gen_rtx_VAR_LOCATION (machine_mode mode, tree decl, rtx loc, |
fcc74520 RS |
1043 | enum var_init_status status) |
1044 | { | |
1045 | rtx x = gen_rtx_fmt_te (VAR_LOCATION, mode, decl, loc); | |
1046 | PAT_VAR_LOCATION_STATUS (x) = status; | |
1047 | return x; | |
1048 | } | |
c5c76735 | 1049 | \f |
23b2ce53 | 1050 | |
80379f51 PB |
1051 | /* Create an rtvec and stores within it the RTXen passed in the arguments. */ |
1052 | ||
23b2ce53 | 1053 | rtvec |
e34d07f2 | 1054 | gen_rtvec (int n, ...) |
23b2ce53 | 1055 | { |
80379f51 PB |
1056 | int i; |
1057 | rtvec rt_val; | |
e34d07f2 | 1058 | va_list p; |
23b2ce53 | 1059 | |
e34d07f2 | 1060 | va_start (p, n); |
23b2ce53 | 1061 | |
80379f51 | 1062 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 1063 | if (n == 0) |
0edf1bb2 JL |
1064 | { |
1065 | va_end (p); | |
1066 | return NULL_RTVEC; | |
1067 | } | |
23b2ce53 | 1068 | |
80379f51 | 1069 | rt_val = rtvec_alloc (n); |
4f90e4a0 | 1070 | |
23b2ce53 | 1071 | for (i = 0; i < n; i++) |
80379f51 | 1072 | rt_val->elem[i] = va_arg (p, rtx); |
6268b922 | 1073 | |
e34d07f2 | 1074 | va_end (p); |
80379f51 | 1075 | return rt_val; |
23b2ce53 RS |
1076 | } |
1077 | ||
1078 | rtvec | |
502b8322 | 1079 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 1080 | { |
b3694847 SS |
1081 | int i; |
1082 | rtvec rt_val; | |
23b2ce53 | 1083 | |
80379f51 | 1084 | /* Don't allocate an empty rtvec... */ |
23b2ce53 | 1085 | if (n == 0) |
80379f51 | 1086 | return NULL_RTVEC; |
23b2ce53 | 1087 | |
80379f51 | 1088 | rt_val = rtvec_alloc (n); |
23b2ce53 RS |
1089 | |
1090 | for (i = 0; i < n; i++) | |
8f985ec4 | 1091 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
1092 | |
1093 | return rt_val; | |
1094 | } | |
e6eda746 DM |
1095 | |
1096 | rtvec | |
1097 | gen_rtvec_v (int n, rtx_insn **argp) | |
1098 | { | |
1099 | int i; | |
1100 | rtvec rt_val; | |
1101 | ||
1102 | /* Don't allocate an empty rtvec... */ | |
1103 | if (n == 0) | |
1104 | return NULL_RTVEC; | |
1105 | ||
1106 | rt_val = rtvec_alloc (n); | |
1107 | ||
1108 | for (i = 0; i < n; i++) | |
1109 | rt_val->elem[i] = *argp++; | |
1110 | ||
1111 | return rt_val; | |
1112 | } | |
1113 | ||
23b2ce53 | 1114 | \f |
38ae7651 RS |
1115 | /* Return the number of bytes between the start of an OUTER_MODE |
1116 | in-memory value and the start of an INNER_MODE in-memory value, | |
1117 | given that the former is a lowpart of the latter. It may be a | |
1118 | paradoxical lowpart, in which case the offset will be negative | |
1119 | on big-endian targets. */ | |
1120 | ||
91914e56 | 1121 | poly_int64 |
ef4bddc2 RS |
1122 | byte_lowpart_offset (machine_mode outer_mode, |
1123 | machine_mode inner_mode) | |
38ae7651 | 1124 | { |
03a95621 | 1125 | if (paradoxical_subreg_p (outer_mode, inner_mode)) |
38ae7651 | 1126 | return -subreg_lowpart_offset (inner_mode, outer_mode); |
03a95621 RS |
1127 | else |
1128 | return subreg_lowpart_offset (outer_mode, inner_mode); | |
38ae7651 | 1129 | } |
3d09ba95 RS |
1130 | |
1131 | /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET) | |
1132 | from address X. For paradoxical big-endian subregs this is a | |
1133 | negative value, otherwise it's the same as OFFSET. */ | |
1134 | ||
91914e56 | 1135 | poly_int64 |
3d09ba95 | 1136 | subreg_memory_offset (machine_mode outer_mode, machine_mode inner_mode, |
91914e56 | 1137 | poly_uint64 offset) |
3d09ba95 RS |
1138 | { |
1139 | if (paradoxical_subreg_p (outer_mode, inner_mode)) | |
1140 | { | |
91914e56 | 1141 | gcc_assert (known_eq (offset, 0U)); |
3d09ba95 RS |
1142 | return -subreg_lowpart_offset (inner_mode, outer_mode); |
1143 | } | |
1144 | return offset; | |
1145 | } | |
1146 | ||
1147 | /* As above, but return the offset that existing subreg X would have | |
1148 | if SUBREG_REG (X) were stored in memory. The only significant thing | |
1149 | about the current SUBREG_REG is its mode. */ | |
1150 | ||
91914e56 | 1151 | poly_int64 |
3d09ba95 RS |
1152 | subreg_memory_offset (const_rtx x) |
1153 | { | |
1154 | return subreg_memory_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)), | |
1155 | SUBREG_BYTE (x)); | |
1156 | } | |
38ae7651 | 1157 | \f |
23b2ce53 RS |
1158 | /* Generate a REG rtx for a new pseudo register of mode MODE. |
1159 | This pseudo is assigned the next sequential register number. */ | |
1160 | ||
1161 | rtx | |
ef4bddc2 | 1162 | gen_reg_rtx (machine_mode mode) |
23b2ce53 | 1163 | { |
b3694847 | 1164 | rtx val; |
2e3f842f | 1165 | unsigned int align = GET_MODE_ALIGNMENT (mode); |
23b2ce53 | 1166 | |
f8335a4f | 1167 | gcc_assert (can_create_pseudo_p ()); |
23b2ce53 | 1168 | |
2e3f842f L |
1169 | /* If a virtual register with bigger mode alignment is generated, |
1170 | increase stack alignment estimation because it might be spilled | |
1171 | to stack later. */ | |
b8698a0f | 1172 | if (SUPPORTS_STACK_ALIGNMENT |
2e3f842f L |
1173 | && crtl->stack_alignment_estimated < align |
1174 | && !crtl->stack_realign_processed) | |
ae58e548 JJ |
1175 | { |
1176 | unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align); | |
1177 | if (crtl->stack_alignment_estimated < min_align) | |
1178 | crtl->stack_alignment_estimated = min_align; | |
1179 | } | |
2e3f842f | 1180 | |
1b3d8f8a GK |
1181 | if (generating_concat_p |
1182 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
1183 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
1184 | { |
1185 | /* For complex modes, don't make a single pseudo. | |
1186 | Instead, make a CONCAT of two pseudos. | |
1187 | This allows noncontiguous allocation of the real and imaginary parts, | |
1188 | which makes much better code. Besides, allocating DCmode | |
1189 | pseudos overstrains reload on some machines like the 386. */ | |
1190 | rtx realpart, imagpart; | |
ef4bddc2 | 1191 | machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
1192 | |
1193 | realpart = gen_reg_rtx (partmode); | |
1194 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 1195 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
1196 | } |
1197 | ||
004a7e45 UB |
1198 | /* Do not call gen_reg_rtx with uninitialized crtl. */ |
1199 | gcc_assert (crtl->emit.regno_pointer_align_length); | |
1200 | ||
f44986d7 DM |
1201 | crtl->emit.ensure_regno_capacity (); |
1202 | gcc_assert (reg_rtx_no < crtl->emit.regno_pointer_align_length); | |
23b2ce53 | 1203 | |
f44986d7 DM |
1204 | val = gen_raw_REG (mode, reg_rtx_no); |
1205 | regno_reg_rtx[reg_rtx_no++] = val; | |
1206 | return val; | |
1207 | } | |
0d4903b8 | 1208 | |
f44986d7 DM |
1209 | /* Make sure m_regno_pointer_align, and regno_reg_rtx are large |
1210 | enough to have elements in the range 0 <= idx <= reg_rtx_no. */ | |
49ad7cfa | 1211 | |
f44986d7 DM |
1212 | void |
1213 | emit_status::ensure_regno_capacity () | |
1214 | { | |
1215 | int old_size = regno_pointer_align_length; | |
23b2ce53 | 1216 | |
f44986d7 DM |
1217 | if (reg_rtx_no < old_size) |
1218 | return; | |
23b2ce53 | 1219 | |
f44986d7 DM |
1220 | int new_size = old_size * 2; |
1221 | while (reg_rtx_no >= new_size) | |
1222 | new_size *= 2; | |
1223 | ||
1224 | char *tmp = XRESIZEVEC (char, regno_pointer_align, new_size); | |
1225 | memset (tmp + old_size, 0, new_size - old_size); | |
1226 | regno_pointer_align = (unsigned char *) tmp; | |
1227 | ||
1228 | rtx *new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, new_size); | |
1229 | memset (new1 + old_size, 0, (new_size - old_size) * sizeof (rtx)); | |
1230 | regno_reg_rtx = new1; | |
1231 | ||
1232 | crtl->emit.regno_pointer_align_length = new_size; | |
23b2ce53 RS |
1233 | } |
1234 | ||
a698cc03 JL |
1235 | /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */ |
1236 | ||
1237 | bool | |
1238 | reg_is_parm_p (rtx reg) | |
1239 | { | |
1240 | tree decl; | |
1241 | ||
1242 | gcc_assert (REG_P (reg)); | |
1243 | decl = REG_EXPR (reg); | |
1244 | return (decl && TREE_CODE (decl) == PARM_DECL); | |
1245 | } | |
1246 | ||
38ae7651 RS |
1247 | /* Update NEW with the same attributes as REG, but with OFFSET added |
1248 | to the REG_OFFSET. */ | |
a560d4d4 | 1249 | |
e53a16e7 | 1250 | static void |
84bc717b | 1251 | update_reg_offset (rtx new_rtx, rtx reg, poly_int64 offset) |
a560d4d4 | 1252 | { |
60564289 | 1253 | REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg), |
84bc717b | 1254 | REG_OFFSET (reg) + offset); |
e53a16e7 ILT |
1255 | } |
1256 | ||
38ae7651 RS |
1257 | /* Generate a register with same attributes as REG, but with OFFSET |
1258 | added to the REG_OFFSET. */ | |
e53a16e7 ILT |
1259 | |
1260 | rtx | |
ef4bddc2 | 1261 | gen_rtx_REG_offset (rtx reg, machine_mode mode, unsigned int regno, |
84bc717b | 1262 | poly_int64 offset) |
e53a16e7 | 1263 | { |
60564289 | 1264 | rtx new_rtx = gen_rtx_REG (mode, regno); |
e53a16e7 | 1265 | |
60564289 KG |
1266 | update_reg_offset (new_rtx, reg, offset); |
1267 | return new_rtx; | |
e53a16e7 ILT |
1268 | } |
1269 | ||
1270 | /* Generate a new pseudo-register with the same attributes as REG, but | |
38ae7651 | 1271 | with OFFSET added to the REG_OFFSET. */ |
e53a16e7 ILT |
1272 | |
1273 | rtx | |
ef4bddc2 | 1274 | gen_reg_rtx_offset (rtx reg, machine_mode mode, int offset) |
e53a16e7 | 1275 | { |
60564289 | 1276 | rtx new_rtx = gen_reg_rtx (mode); |
e53a16e7 | 1277 | |
60564289 KG |
1278 | update_reg_offset (new_rtx, reg, offset); |
1279 | return new_rtx; | |
a560d4d4 JH |
1280 | } |
1281 | ||
38ae7651 RS |
1282 | /* Adjust REG in-place so that it has mode MODE. It is assumed that the |
1283 | new register is a (possibly paradoxical) lowpart of the old one. */ | |
a560d4d4 JH |
1284 | |
1285 | void | |
ef4bddc2 | 1286 | adjust_reg_mode (rtx reg, machine_mode mode) |
a560d4d4 | 1287 | { |
38ae7651 RS |
1288 | update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg))); |
1289 | PUT_MODE (reg, mode); | |
1290 | } | |
1291 | ||
1292 | /* Copy REG's attributes from X, if X has any attributes. If REG and X | |
1293 | have different modes, REG is a (possibly paradoxical) lowpart of X. */ | |
1294 | ||
1295 | void | |
1296 | set_reg_attrs_from_value (rtx reg, rtx x) | |
1297 | { | |
84bc717b | 1298 | poly_int64 offset; |
de6f3f7a L |
1299 | bool can_be_reg_pointer = true; |
1300 | ||
1301 | /* Don't call mark_reg_pointer for incompatible pointer sign | |
1302 | extension. */ | |
1303 | while (GET_CODE (x) == SIGN_EXTEND | |
1304 | || GET_CODE (x) == ZERO_EXTEND | |
1305 | || GET_CODE (x) == TRUNCATE | |
1306 | || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x))) | |
1307 | { | |
2a870875 RS |
1308 | #if defined(POINTERS_EXTEND_UNSIGNED) |
1309 | if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED) | |
8d8e740c BE |
1310 | || (GET_CODE (x) == ZERO_EXTEND && ! POINTERS_EXTEND_UNSIGNED) |
1311 | || (paradoxical_subreg_p (x) | |
1312 | && ! (SUBREG_PROMOTED_VAR_P (x) | |
1313 | && SUBREG_CHECK_PROMOTED_SIGN (x, | |
1314 | POINTERS_EXTEND_UNSIGNED)))) | |
2a870875 | 1315 | && !targetm.have_ptr_extend ()) |
de6f3f7a L |
1316 | can_be_reg_pointer = false; |
1317 | #endif | |
1318 | x = XEXP (x, 0); | |
1319 | } | |
38ae7651 | 1320 | |
923ba36f JJ |
1321 | /* Hard registers can be reused for multiple purposes within the same |
1322 | function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN | |
1323 | on them is wrong. */ | |
1324 | if (HARD_REGISTER_P (reg)) | |
1325 | return; | |
1326 | ||
38ae7651 | 1327 | offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x)); |
46b71b03 PB |
1328 | if (MEM_P (x)) |
1329 | { | |
527210c4 RS |
1330 | if (MEM_OFFSET_KNOWN_P (x)) |
1331 | REG_ATTRS (reg) = get_reg_attrs (MEM_EXPR (x), | |
1332 | MEM_OFFSET (x) + offset); | |
de6f3f7a | 1333 | if (can_be_reg_pointer && MEM_POINTER (x)) |
0a317111 | 1334 | mark_reg_pointer (reg, 0); |
46b71b03 PB |
1335 | } |
1336 | else if (REG_P (x)) | |
1337 | { | |
1338 | if (REG_ATTRS (x)) | |
1339 | update_reg_offset (reg, x, offset); | |
de6f3f7a | 1340 | if (can_be_reg_pointer && REG_POINTER (x)) |
46b71b03 PB |
1341 | mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x))); |
1342 | } | |
1343 | } | |
1344 | ||
1345 | /* Generate a REG rtx for a new pseudo register, copying the mode | |
1346 | and attributes from X. */ | |
1347 | ||
1348 | rtx | |
1349 | gen_reg_rtx_and_attrs (rtx x) | |
1350 | { | |
1351 | rtx reg = gen_reg_rtx (GET_MODE (x)); | |
1352 | set_reg_attrs_from_value (reg, x); | |
1353 | return reg; | |
a560d4d4 JH |
1354 | } |
1355 | ||
9d18e06b JZ |
1356 | /* Set the register attributes for registers contained in PARM_RTX. |
1357 | Use needed values from memory attributes of MEM. */ | |
1358 | ||
1359 | void | |
502b8322 | 1360 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b | 1361 | { |
f8cfc6aa | 1362 | if (REG_P (parm_rtx)) |
38ae7651 | 1363 | set_reg_attrs_from_value (parm_rtx, mem); |
9d18e06b JZ |
1364 | else if (GET_CODE (parm_rtx) == PARALLEL) |
1365 | { | |
1366 | /* Check for a NULL entry in the first slot, used to indicate that the | |
1367 | parameter goes both on the stack and in registers. */ | |
1368 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
1369 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
1370 | { | |
1371 | rtx x = XVECEXP (parm_rtx, 0, i); | |
f8cfc6aa | 1372 | if (REG_P (XEXP (x, 0))) |
9d18e06b JZ |
1373 | REG_ATTRS (XEXP (x, 0)) |
1374 | = get_reg_attrs (MEM_EXPR (mem), | |
1375 | INTVAL (XEXP (x, 1))); | |
1376 | } | |
1377 | } | |
1378 | } | |
1379 | ||
38ae7651 RS |
1380 | /* Set the REG_ATTRS for registers in value X, given that X represents |
1381 | decl T. */ | |
a560d4d4 | 1382 | |
4e3825db | 1383 | void |
38ae7651 RS |
1384 | set_reg_attrs_for_decl_rtl (tree t, rtx x) |
1385 | { | |
1f9ceff1 AO |
1386 | if (!t) |
1387 | return; | |
1388 | tree tdecl = t; | |
38ae7651 | 1389 | if (GET_CODE (x) == SUBREG) |
fbe6ec81 | 1390 | { |
38ae7651 RS |
1391 | gcc_assert (subreg_lowpart_p (x)); |
1392 | x = SUBREG_REG (x); | |
fbe6ec81 | 1393 | } |
f8cfc6aa | 1394 | if (REG_P (x)) |
38ae7651 RS |
1395 | REG_ATTRS (x) |
1396 | = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x), | |
1f9ceff1 AO |
1397 | DECL_P (tdecl) |
1398 | ? DECL_MODE (tdecl) | |
1399 | : TYPE_MODE (TREE_TYPE (tdecl)))); | |
a560d4d4 JH |
1400 | if (GET_CODE (x) == CONCAT) |
1401 | { | |
1402 | if (REG_P (XEXP (x, 0))) | |
1403 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
1404 | if (REG_P (XEXP (x, 1))) | |
1405 | REG_ATTRS (XEXP (x, 1)) | |
1406 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
1407 | } | |
1408 | if (GET_CODE (x) == PARALLEL) | |
1409 | { | |
d4afac5b JZ |
1410 | int i, start; |
1411 | ||
1412 | /* Check for a NULL entry, used to indicate that the parameter goes | |
1413 | both on the stack and in registers. */ | |
1414 | if (XEXP (XVECEXP (x, 0, 0), 0)) | |
1415 | start = 0; | |
1416 | else | |
1417 | start = 1; | |
1418 | ||
1419 | for (i = start; i < XVECLEN (x, 0); i++) | |
a560d4d4 JH |
1420 | { |
1421 | rtx y = XVECEXP (x, 0, i); | |
1422 | if (REG_P (XEXP (y, 0))) | |
1423 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
1424 | } | |
1425 | } | |
1426 | } | |
1427 | ||
38ae7651 RS |
1428 | /* Assign the RTX X to declaration T. */ |
1429 | ||
1430 | void | |
1431 | set_decl_rtl (tree t, rtx x) | |
1432 | { | |
1433 | DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x; | |
1434 | if (x) | |
1435 | set_reg_attrs_for_decl_rtl (t, x); | |
1436 | } | |
1437 | ||
5141868d RS |
1438 | /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true |
1439 | if the ABI requires the parameter to be passed by reference. */ | |
38ae7651 RS |
1440 | |
1441 | void | |
5141868d | 1442 | set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p) |
38ae7651 RS |
1443 | { |
1444 | DECL_INCOMING_RTL (t) = x; | |
5141868d | 1445 | if (x && !by_reference_p) |
38ae7651 RS |
1446 | set_reg_attrs_for_decl_rtl (t, x); |
1447 | } | |
1448 | ||
754fdcca RK |
1449 | /* Identify REG (which may be a CONCAT) as a user register. */ |
1450 | ||
1451 | void | |
502b8322 | 1452 | mark_user_reg (rtx reg) |
754fdcca RK |
1453 | { |
1454 | if (GET_CODE (reg) == CONCAT) | |
1455 | { | |
1456 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
1457 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
1458 | } | |
754fdcca | 1459 | else |
5b0264cb NS |
1460 | { |
1461 | gcc_assert (REG_P (reg)); | |
1462 | REG_USERVAR_P (reg) = 1; | |
1463 | } | |
754fdcca RK |
1464 | } |
1465 | ||
86fe05e0 RK |
1466 | /* Identify REG as a probable pointer register and show its alignment |
1467 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
1468 | |
1469 | void | |
502b8322 | 1470 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 1471 | { |
3502dc9c | 1472 | if (! REG_POINTER (reg)) |
00995e78 | 1473 | { |
3502dc9c | 1474 | REG_POINTER (reg) = 1; |
86fe05e0 | 1475 | |
00995e78 RE |
1476 | if (align) |
1477 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
1478 | } | |
1479 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
6614fd40 | 1480 | /* We can no-longer be sure just how aligned this pointer is. */ |
86fe05e0 | 1481 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
1482 | } |
1483 | ||
1484 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
1485 | ||
1486 | int | |
502b8322 | 1487 | max_reg_num (void) |
23b2ce53 RS |
1488 | { |
1489 | return reg_rtx_no; | |
1490 | } | |
1491 | ||
1492 | /* Return 1 + the largest label number used so far in the current function. */ | |
1493 | ||
1494 | int | |
502b8322 | 1495 | max_label_num (void) |
23b2ce53 | 1496 | { |
23b2ce53 RS |
1497 | return label_num; |
1498 | } | |
1499 | ||
1500 | /* Return first label number used in this function (if any were used). */ | |
1501 | ||
1502 | int | |
502b8322 | 1503 | get_first_label_num (void) |
23b2ce53 RS |
1504 | { |
1505 | return first_label_num; | |
1506 | } | |
6de9cd9a DN |
1507 | |
1508 | /* If the rtx for label was created during the expansion of a nested | |
1509 | function, then first_label_num won't include this label number. | |
fa10beec | 1510 | Fix this now so that array indices work later. */ |
6de9cd9a DN |
1511 | |
1512 | void | |
9aa50db7 | 1513 | maybe_set_first_label_num (rtx_code_label *x) |
6de9cd9a DN |
1514 | { |
1515 | if (CODE_LABEL_NUMBER (x) < first_label_num) | |
1516 | first_label_num = CODE_LABEL_NUMBER (x); | |
1517 | } | |
51b86113 DM |
1518 | |
1519 | /* For use by the RTL function loader, when mingling with normal | |
1520 | functions. | |
1521 | Ensure that label_num is greater than the label num of X, to avoid | |
1522 | duplicate labels in the generated assembler. */ | |
1523 | ||
1524 | void | |
1525 | maybe_set_max_label_num (rtx_code_label *x) | |
1526 | { | |
1527 | if (CODE_LABEL_NUMBER (x) >= label_num) | |
1528 | label_num = CODE_LABEL_NUMBER (x) + 1; | |
1529 | } | |
1530 | ||
23b2ce53 RS |
1531 | \f |
1532 | /* Return a value representing some low-order bits of X, where the number | |
1533 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1534 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1535 | representation is returned. |
1536 | ||
1537 | This function handles the cases in common between gen_lowpart, below, | |
1538 | and two variants in cse.c and combine.c. These are the cases that can | |
1539 | be safely handled at all points in the compilation. | |
1540 | ||
1541 | If this is not a case we can handle, return 0. */ | |
1542 | ||
1543 | rtx | |
ef4bddc2 | 1544 | gen_lowpart_common (machine_mode mode, rtx x) |
23b2ce53 | 1545 | { |
fad2288b | 1546 | poly_uint64 msize = GET_MODE_SIZE (mode); |
ef4bddc2 | 1547 | machine_mode innermode; |
550d1387 GK |
1548 | |
1549 | /* Unfortunately, this routine doesn't take a parameter for the mode of X, | |
1550 | so we have to make one up. Yuk. */ | |
1551 | innermode = GET_MODE (x); | |
481683e1 | 1552 | if (CONST_INT_P (x) |
fad2288b RS |
1553 | && known_le (msize * BITS_PER_UNIT, |
1554 | (unsigned HOST_WIDE_INT) HOST_BITS_PER_WIDE_INT)) | |
f4b31647 | 1555 | innermode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require (); |
550d1387 | 1556 | else if (innermode == VOIDmode) |
f4b31647 | 1557 | innermode = int_mode_for_size (HOST_BITS_PER_DOUBLE_INT, 0).require (); |
b8698a0f | 1558 | |
5b0264cb | 1559 | gcc_assert (innermode != VOIDmode && innermode != BLKmode); |
23b2ce53 | 1560 | |
550d1387 | 1561 | if (innermode == mode) |
23b2ce53 RS |
1562 | return x; |
1563 | ||
fad2288b RS |
1564 | /* The size of the outer and inner modes must be ordered. */ |
1565 | poly_uint64 xsize = GET_MODE_SIZE (innermode); | |
1566 | if (!ordered_p (msize, xsize)) | |
1567 | return 0; | |
1568 | ||
1eae67f8 RS |
1569 | if (SCALAR_FLOAT_MODE_P (mode)) |
1570 | { | |
1571 | /* Don't allow paradoxical FLOAT_MODE subregs. */ | |
fad2288b | 1572 | if (maybe_gt (msize, xsize)) |
1eae67f8 RS |
1573 | return 0; |
1574 | } | |
1575 | else | |
1576 | { | |
1577 | /* MODE must occupy no more of the underlying registers than X. */ | |
fad2288b RS |
1578 | poly_uint64 regsize = REGMODE_NATURAL_SIZE (innermode); |
1579 | unsigned int mregs, xregs; | |
1580 | if (!can_div_away_from_zero_p (msize, regsize, &mregs) | |
1581 | || !can_div_away_from_zero_p (xsize, regsize, &xregs) | |
1582 | || mregs > xregs) | |
1eae67f8 RS |
1583 | return 0; |
1584 | } | |
53501a19 | 1585 | |
54651377 | 1586 | scalar_int_mode int_mode, int_innermode, from_mode; |
23b2ce53 | 1587 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) |
54651377 RS |
1588 | && is_a <scalar_int_mode> (mode, &int_mode) |
1589 | && is_a <scalar_int_mode> (innermode, &int_innermode) | |
1590 | && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &from_mode)) | |
23b2ce53 RS |
1591 | { |
1592 | /* If we are getting the low-order part of something that has been | |
1593 | sign- or zero-extended, we can either just use the object being | |
1594 | extended or make a narrower extension. If we want an even smaller | |
1595 | piece than the size of the object being extended, call ourselves | |
1596 | recursively. | |
1597 | ||
1598 | This case is used mostly by combine and cse. */ | |
1599 | ||
54651377 | 1600 | if (from_mode == int_mode) |
23b2ce53 | 1601 | return XEXP (x, 0); |
54651377 RS |
1602 | else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (from_mode)) |
1603 | return gen_lowpart_common (int_mode, XEXP (x, 0)); | |
1604 | else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode)) | |
1605 | return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0)); | |
23b2ce53 | 1606 | } |
f8cfc6aa | 1607 | else if (GET_CODE (x) == SUBREG || REG_P (x) |
2072a319 | 1608 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR |
0c12fc9b RS |
1609 | || CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x) |
1610 | || CONST_POLY_INT_P (x)) | |
3403a1a9 | 1611 | return lowpart_subreg (mode, x, innermode); |
8aada4ad | 1612 | |
23b2ce53 RS |
1613 | /* Otherwise, we can't do this. */ |
1614 | return 0; | |
1615 | } | |
1616 | \f | |
ccba022b | 1617 | rtx |
ef4bddc2 | 1618 | gen_highpart (machine_mode mode, rtx x) |
ccba022b | 1619 | { |
cf098191 | 1620 | poly_uint64 msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1621 | rtx result; |
ddef6bc7 | 1622 | |
ccba022b RS |
1623 | /* This case loses if X is a subreg. To catch bugs early, |
1624 | complain if an invalid MODE is used even in other cases. */ | |
cf098191 RS |
1625 | gcc_assert (known_le (msize, (unsigned int) UNITS_PER_WORD) |
1626 | || known_eq (msize, GET_MODE_UNIT_SIZE (GET_MODE (x)))); | |
ddef6bc7 | 1627 | |
e0e08ac2 JH |
1628 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1629 | subreg_highpart_offset (mode, GET_MODE (x))); | |
5b0264cb | 1630 | gcc_assert (result); |
b8698a0f | 1631 | |
09482e0d JW |
1632 | /* simplify_gen_subreg is not guaranteed to return a valid operand for |
1633 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1634 | emitting code if necessary to do so. */ | |
5b0264cb NS |
1635 | if (MEM_P (result)) |
1636 | { | |
1637 | result = validize_mem (result); | |
1638 | gcc_assert (result); | |
1639 | } | |
b8698a0f | 1640 | |
e0e08ac2 JH |
1641 | return result; |
1642 | } | |
5222e470 | 1643 | |
26d249eb | 1644 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1645 | be VOIDmode constant. */ |
1646 | rtx | |
ef4bddc2 | 1647 | gen_highpart_mode (machine_mode outermode, machine_mode innermode, rtx exp) |
5222e470 JH |
1648 | { |
1649 | if (GET_MODE (exp) != VOIDmode) | |
1650 | { | |
5b0264cb | 1651 | gcc_assert (GET_MODE (exp) == innermode); |
5222e470 JH |
1652 | return gen_highpart (outermode, exp); |
1653 | } | |
1654 | return simplify_gen_subreg (outermode, exp, innermode, | |
1655 | subreg_highpart_offset (outermode, innermode)); | |
1656 | } | |
68252e27 | 1657 | |
33951763 RS |
1658 | /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has |
1659 | OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */ | |
8698cce3 | 1660 | |
91914e56 RS |
1661 | poly_uint64 |
1662 | subreg_size_lowpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes) | |
e0e08ac2 | 1663 | { |
91914e56 RS |
1664 | gcc_checking_assert (ordered_p (outer_bytes, inner_bytes)); |
1665 | if (maybe_gt (outer_bytes, inner_bytes)) | |
33951763 RS |
1666 | /* Paradoxical subregs always have a SUBREG_BYTE of 0. */ |
1667 | return 0; | |
ddef6bc7 | 1668 | |
33951763 RS |
1669 | if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN) |
1670 | return inner_bytes - outer_bytes; | |
1671 | else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN) | |
1672 | return 0; | |
1673 | else | |
1674 | return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, 0); | |
ccba022b | 1675 | } |
eea50aa0 | 1676 | |
33951763 RS |
1677 | /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has |
1678 | OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */ | |
1679 | ||
91914e56 RS |
1680 | poly_uint64 |
1681 | subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes) | |
eea50aa0 | 1682 | { |
91914e56 | 1683 | gcc_assert (known_ge (inner_bytes, outer_bytes)); |
eea50aa0 | 1684 | |
33951763 RS |
1685 | if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN) |
1686 | return 0; | |
1687 | else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN) | |
1688 | return inner_bytes - outer_bytes; | |
1689 | else | |
1690 | return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, | |
1691 | (inner_bytes - outer_bytes) | |
1692 | * BITS_PER_UNIT); | |
eea50aa0 | 1693 | } |
ccba022b | 1694 | |
23b2ce53 RS |
1695 | /* Return 1 iff X, assumed to be a SUBREG, |
1696 | refers to the least significant part of its containing reg. | |
1697 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1698 | ||
1699 | int | |
fa233e34 | 1700 | subreg_lowpart_p (const_rtx x) |
23b2ce53 RS |
1701 | { |
1702 | if (GET_CODE (x) != SUBREG) | |
1703 | return 1; | |
a3a03040 RK |
1704 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1705 | return 0; | |
23b2ce53 | 1706 | |
91914e56 RS |
1707 | return known_eq (subreg_lowpart_offset (GET_MODE (x), |
1708 | GET_MODE (SUBREG_REG (x))), | |
1709 | SUBREG_BYTE (x)); | |
23b2ce53 RS |
1710 | } |
1711 | \f | |
ddef6bc7 JJ |
1712 | /* Return subword OFFSET of operand OP. |
1713 | The word number, OFFSET, is interpreted as the word number starting | |
1714 | at the low-order address. OFFSET 0 is the low-order word if not | |
1715 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1716 | ||
1717 | If we cannot extract the required word, we return zero. Otherwise, | |
1718 | an rtx corresponding to the requested word will be returned. | |
1719 | ||
1720 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1721 | reload has completed, a valid address will always be returned. After | |
1722 | reload, if a valid address cannot be returned, we return zero. | |
1723 | ||
1724 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1725 | it is the responsibility of the caller. | |
1726 | ||
1727 | MODE is the mode of OP in case it is a CONST_INT. | |
1728 | ||
1729 | ??? This is still rather broken for some cases. The problem for the | |
1730 | moment is that all callers of this thing provide no 'goal mode' to | |
1731 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1732 | in a word based SUBREG world. |
1733 | Now use of this function can be deprecated by simplify_subreg in most | |
1734 | cases. | |
1735 | */ | |
ddef6bc7 JJ |
1736 | |
1737 | rtx | |
fdbfe4e5 RS |
1738 | operand_subword (rtx op, poly_uint64 offset, int validate_address, |
1739 | machine_mode mode) | |
ddef6bc7 JJ |
1740 | { |
1741 | if (mode == VOIDmode) | |
1742 | mode = GET_MODE (op); | |
1743 | ||
5b0264cb | 1744 | gcc_assert (mode != VOIDmode); |
ddef6bc7 | 1745 | |
30f7a378 | 1746 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 | 1747 | if (mode != BLKmode |
fdbfe4e5 | 1748 | && maybe_lt (GET_MODE_SIZE (mode), UNITS_PER_WORD)) |
ddef6bc7 JJ |
1749 | return 0; |
1750 | ||
30f7a378 | 1751 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 | 1752 | if (mode != BLKmode |
fdbfe4e5 | 1753 | && maybe_gt ((offset + 1) * UNITS_PER_WORD, GET_MODE_SIZE (mode))) |
ddef6bc7 JJ |
1754 | return const0_rtx; |
1755 | ||
ddef6bc7 | 1756 | /* Form a new MEM at the requested address. */ |
3c0cb5de | 1757 | if (MEM_P (op)) |
ddef6bc7 | 1758 | { |
60564289 | 1759 | rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1760 | |
f1ec5147 | 1761 | if (! validate_address) |
60564289 | 1762 | return new_rtx; |
f1ec5147 RK |
1763 | |
1764 | else if (reload_completed) | |
ddef6bc7 | 1765 | { |
09e881c9 BE |
1766 | if (! strict_memory_address_addr_space_p (word_mode, |
1767 | XEXP (new_rtx, 0), | |
1768 | MEM_ADDR_SPACE (op))) | |
f1ec5147 | 1769 | return 0; |
ddef6bc7 | 1770 | } |
f1ec5147 | 1771 | else |
60564289 | 1772 | return replace_equiv_address (new_rtx, XEXP (new_rtx, 0)); |
ddef6bc7 JJ |
1773 | } |
1774 | ||
0631e0bf JH |
1775 | /* Rest can be handled by simplify_subreg. */ |
1776 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1777 | } |
1778 | ||
535a42b1 NS |
1779 | /* Similar to `operand_subword', but never return 0. If we can't |
1780 | extract the required subword, put OP into a register and try again. | |
1781 | The second attempt must succeed. We always validate the address in | |
1782 | this case. | |
23b2ce53 RS |
1783 | |
1784 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1785 | ||
1786 | rtx | |
fdbfe4e5 | 1787 | operand_subword_force (rtx op, poly_uint64 offset, machine_mode mode) |
23b2ce53 | 1788 | { |
ddef6bc7 | 1789 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1790 | |
1791 | if (result) | |
1792 | return result; | |
1793 | ||
1794 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb | 1795 | { |
67914693 | 1796 | /* If this is a register which cannot be accessed by words, copy it |
77e6b0eb | 1797 | to a pseudo register. */ |
f8cfc6aa | 1798 | if (REG_P (op)) |
77e6b0eb JC |
1799 | op = copy_to_reg (op); |
1800 | else | |
1801 | op = force_reg (mode, op); | |
1802 | } | |
23b2ce53 | 1803 | |
ddef6bc7 | 1804 | result = operand_subword (op, offset, 1, mode); |
5b0264cb | 1805 | gcc_assert (result); |
23b2ce53 RS |
1806 | |
1807 | return result; | |
1808 | } | |
1809 | \f | |
d05d7551 RS |
1810 | mem_attrs::mem_attrs () |
1811 | : expr (NULL_TREE), | |
1812 | offset (0), | |
1813 | size (0), | |
1814 | alias (0), | |
1815 | align (0), | |
1816 | addrspace (ADDR_SPACE_GENERIC), | |
1817 | offset_known_p (false), | |
1818 | size_known_p (false) | |
1819 | {} | |
1820 | ||
2b3493c8 AK |
1821 | /* Returns 1 if both MEM_EXPR can be considered equal |
1822 | and 0 otherwise. */ | |
1823 | ||
1824 | int | |
4f588890 | 1825 | mem_expr_equal_p (const_tree expr1, const_tree expr2) |
2b3493c8 AK |
1826 | { |
1827 | if (expr1 == expr2) | |
1828 | return 1; | |
1829 | ||
1830 | if (! expr1 || ! expr2) | |
1831 | return 0; | |
1832 | ||
1833 | if (TREE_CODE (expr1) != TREE_CODE (expr2)) | |
1834 | return 0; | |
1835 | ||
55b34b5f | 1836 | return operand_equal_p (expr1, expr2, 0); |
2b3493c8 AK |
1837 | } |
1838 | ||
805903b5 JJ |
1839 | /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN |
1840 | bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or | |
1841 | -1 if not known. */ | |
1842 | ||
1843 | int | |
d9223014 | 1844 | get_mem_align_offset (rtx mem, unsigned int align) |
805903b5 JJ |
1845 | { |
1846 | tree expr; | |
d05d7551 | 1847 | poly_uint64 offset; |
805903b5 JJ |
1848 | |
1849 | /* This function can't use | |
527210c4 | 1850 | if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem) |
e80c2726 | 1851 | || (MAX (MEM_ALIGN (mem), |
0eb77834 | 1852 | MAX (align, get_object_alignment (MEM_EXPR (mem)))) |
805903b5 JJ |
1853 | < align)) |
1854 | return -1; | |
1855 | else | |
527210c4 | 1856 | return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1); |
805903b5 JJ |
1857 | for two reasons: |
1858 | - COMPONENT_REFs in MEM_EXPR can have NULL first operand, | |
1859 | for <variable>. get_inner_reference doesn't handle it and | |
1860 | even if it did, the alignment in that case needs to be determined | |
1861 | from DECL_FIELD_CONTEXT's TYPE_ALIGN. | |
1862 | - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR | |
1863 | isn't sufficiently aligned, the object it is in might be. */ | |
1864 | gcc_assert (MEM_P (mem)); | |
1865 | expr = MEM_EXPR (mem); | |
527210c4 | 1866 | if (expr == NULL_TREE || !MEM_OFFSET_KNOWN_P (mem)) |
805903b5 JJ |
1867 | return -1; |
1868 | ||
527210c4 | 1869 | offset = MEM_OFFSET (mem); |
805903b5 JJ |
1870 | if (DECL_P (expr)) |
1871 | { | |
1872 | if (DECL_ALIGN (expr) < align) | |
1873 | return -1; | |
1874 | } | |
1875 | else if (INDIRECT_REF_P (expr)) | |
1876 | { | |
1877 | if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align) | |
1878 | return -1; | |
1879 | } | |
1880 | else if (TREE_CODE (expr) == COMPONENT_REF) | |
1881 | { | |
1882 | while (1) | |
1883 | { | |
1884 | tree inner = TREE_OPERAND (expr, 0); | |
1885 | tree field = TREE_OPERAND (expr, 1); | |
1886 | tree byte_offset = component_ref_field_offset (expr); | |
1887 | tree bit_offset = DECL_FIELD_BIT_OFFSET (field); | |
1888 | ||
d05d7551 | 1889 | poly_uint64 suboffset; |
805903b5 | 1890 | if (!byte_offset |
d05d7551 | 1891 | || !poly_int_tree_p (byte_offset, &suboffset) |
cc269bb6 | 1892 | || !tree_fits_uhwi_p (bit_offset)) |
805903b5 JJ |
1893 | return -1; |
1894 | ||
d05d7551 | 1895 | offset += suboffset; |
ae7e9ddd | 1896 | offset += tree_to_uhwi (bit_offset) / BITS_PER_UNIT; |
805903b5 JJ |
1897 | |
1898 | if (inner == NULL_TREE) | |
1899 | { | |
1900 | if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field)) | |
1901 | < (unsigned int) align) | |
1902 | return -1; | |
1903 | break; | |
1904 | } | |
1905 | else if (DECL_P (inner)) | |
1906 | { | |
1907 | if (DECL_ALIGN (inner) < align) | |
1908 | return -1; | |
1909 | break; | |
1910 | } | |
1911 | else if (TREE_CODE (inner) != COMPONENT_REF) | |
1912 | return -1; | |
1913 | expr = inner; | |
1914 | } | |
1915 | } | |
1916 | else | |
1917 | return -1; | |
1918 | ||
d05d7551 RS |
1919 | HOST_WIDE_INT misalign; |
1920 | if (!known_misalignment (offset, align / BITS_PER_UNIT, &misalign)) | |
1921 | return -1; | |
1922 | return misalign; | |
805903b5 JJ |
1923 | } |
1924 | ||
6926c713 | 1925 | /* Given REF (a MEM) and T, either the type of X or the expression |
173b24b9 | 1926 | corresponding to REF, set the memory attributes. OBJECTP is nonzero |
6f1087be RH |
1927 | if we are making a new object of this type. BITPOS is nonzero if |
1928 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1929 | |
1930 | void | |
502b8322 | 1931 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
d05d7551 | 1932 | poly_int64 bitpos) |
173b24b9 | 1933 | { |
d05d7551 | 1934 | poly_int64 apply_bitpos = 0; |
173b24b9 | 1935 | tree type; |
99b1c316 | 1936 | class mem_attrs attrs, *defattrs, *refattrs; |
f18a7b25 | 1937 | addr_space_t as; |
173b24b9 RK |
1938 | |
1939 | /* It can happen that type_for_mode was given a mode for which there | |
1940 | is no language-level type. In which case it returns NULL, which | |
1941 | we can see here. */ | |
1942 | if (t == NULL_TREE) | |
1943 | return; | |
1944 | ||
1945 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
eeb23c11 MM |
1946 | if (type == error_mark_node) |
1947 | return; | |
173b24b9 | 1948 | |
173b24b9 RK |
1949 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1950 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1951 | info. Callers should not set DECL_RTL until after the call to | |
1952 | set_mem_attributes. */ | |
5b0264cb | 1953 | gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t)); |
173b24b9 | 1954 | |
738cc472 | 1955 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 | 1956 | front-end routine) and use it. */ |
f12144dd | 1957 | attrs.alias = get_alias_set (t); |
173b24b9 | 1958 | |
a5e9c810 | 1959 | MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type); |
f8ad8d7c | 1960 | MEM_POINTER (ref) = POINTER_TYPE_P (type); |
173b24b9 | 1961 | |
268f7033 | 1962 | /* Default values from pre-existing memory attributes if present. */ |
f12144dd RS |
1963 | refattrs = MEM_ATTRS (ref); |
1964 | if (refattrs) | |
268f7033 UW |
1965 | { |
1966 | /* ??? Can this ever happen? Calling this routine on a MEM that | |
1967 | already carries memory attributes should probably be invalid. */ | |
f12144dd | 1968 | attrs.expr = refattrs->expr; |
754c3d5d | 1969 | attrs.offset_known_p = refattrs->offset_known_p; |
f12144dd | 1970 | attrs.offset = refattrs->offset; |
754c3d5d | 1971 | attrs.size_known_p = refattrs->size_known_p; |
f12144dd RS |
1972 | attrs.size = refattrs->size; |
1973 | attrs.align = refattrs->align; | |
268f7033 UW |
1974 | } |
1975 | ||
1976 | /* Otherwise, default values from the mode of the MEM reference. */ | |
f12144dd | 1977 | else |
268f7033 | 1978 | { |
f12144dd RS |
1979 | defattrs = mode_mem_attrs[(int) GET_MODE (ref)]; |
1980 | gcc_assert (!defattrs->expr); | |
754c3d5d | 1981 | gcc_assert (!defattrs->offset_known_p); |
f12144dd | 1982 | |
268f7033 | 1983 | /* Respect mode size. */ |
754c3d5d | 1984 | attrs.size_known_p = defattrs->size_known_p; |
f12144dd | 1985 | attrs.size = defattrs->size; |
268f7033 UW |
1986 | /* ??? Is this really necessary? We probably should always get |
1987 | the size from the type below. */ | |
1988 | ||
1989 | /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type; | |
1990 | if T is an object, always compute the object alignment below. */ | |
f12144dd RS |
1991 | if (TYPE_P (t)) |
1992 | attrs.align = defattrs->align; | |
1993 | else | |
1994 | attrs.align = BITS_PER_UNIT; | |
268f7033 UW |
1995 | /* ??? If T is a type, respecting mode alignment may *also* be wrong |
1996 | e.g. if the type carries an alignment attribute. Should we be | |
1997 | able to simply always use TYPE_ALIGN? */ | |
1998 | } | |
1999 | ||
25b75a48 BE |
2000 | /* We can set the alignment from the type if we are making an object or if |
2001 | this is an INDIRECT_REF. */ | |
2002 | if (objectp || TREE_CODE (t) == INDIRECT_REF) | |
f12144dd | 2003 | attrs.align = MAX (attrs.align, TYPE_ALIGN (type)); |
a80903ff | 2004 | |
738cc472 | 2005 | /* If the size is known, we can set that. */ |
a787ccc3 | 2006 | tree new_size = TYPE_SIZE_UNIT (type); |
738cc472 | 2007 | |
30b0317c RB |
2008 | /* The address-space is that of the type. */ |
2009 | as = TYPE_ADDR_SPACE (type); | |
2010 | ||
80965c18 RK |
2011 | /* If T is not a type, we may be able to deduce some more information about |
2012 | the expression. */ | |
2013 | if (! TYPE_P (t)) | |
8ac61af7 | 2014 | { |
8476af98 | 2015 | tree base; |
389fdba0 | 2016 | |
8ac61af7 RK |
2017 | if (TREE_THIS_VOLATILE (t)) |
2018 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 2019 | |
c56e3582 RK |
2020 | /* Now remove any conversions: they don't change what the underlying |
2021 | object is. Likewise for SAVE_EXPR. */ | |
1043771b | 2022 | while (CONVERT_EXPR_P (t) |
c56e3582 RK |
2023 | || TREE_CODE (t) == VIEW_CONVERT_EXPR |
2024 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
2025 | t = TREE_OPERAND (t, 0); |
2026 | ||
4994da65 RG |
2027 | /* Note whether this expression can trap. */ |
2028 | MEM_NOTRAP_P (ref) = !tree_could_trap_p (t); | |
2029 | ||
2030 | base = get_base_address (t); | |
f18a7b25 MJ |
2031 | if (base) |
2032 | { | |
2033 | if (DECL_P (base) | |
2034 | && TREE_READONLY (base) | |
2035 | && (TREE_STATIC (base) || DECL_EXTERNAL (base)) | |
2036 | && !TREE_THIS_VOLATILE (base)) | |
2037 | MEM_READONLY_P (ref) = 1; | |
2038 | ||
2039 | /* Mark static const strings readonly as well. */ | |
2040 | if (TREE_CODE (base) == STRING_CST | |
2041 | && TREE_READONLY (base) | |
2042 | && TREE_STATIC (base)) | |
2043 | MEM_READONLY_P (ref) = 1; | |
2044 | ||
30b0317c | 2045 | /* Address-space information is on the base object. */ |
f18a7b25 MJ |
2046 | if (TREE_CODE (base) == MEM_REF |
2047 | || TREE_CODE (base) == TARGET_MEM_REF) | |
2048 | as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base, | |
2049 | 0)))); | |
2050 | else | |
2051 | as = TYPE_ADDR_SPACE (TREE_TYPE (base)); | |
2052 | } | |
ba30e50d | 2053 | |
2039d7aa RH |
2054 | /* If this expression uses it's parent's alias set, mark it such |
2055 | that we won't change it. */ | |
b4ada065 | 2056 | if (component_uses_parent_alias_set_from (t) != NULL_TREE) |
10b76d73 RK |
2057 | MEM_KEEP_ALIAS_SET_P (ref) = 1; |
2058 | ||
8ac61af7 RK |
2059 | /* If this is a decl, set the attributes of the MEM from it. */ |
2060 | if (DECL_P (t)) | |
2061 | { | |
f12144dd | 2062 | attrs.expr = t; |
754c3d5d RS |
2063 | attrs.offset_known_p = true; |
2064 | attrs.offset = 0; | |
6f1087be | 2065 | apply_bitpos = bitpos; |
a787ccc3 | 2066 | new_size = DECL_SIZE_UNIT (t); |
8ac61af7 RK |
2067 | } |
2068 | ||
80d6f89e RB |
2069 | /* ??? If we end up with a constant or a descriptor do not |
2070 | record a MEM_EXPR. */ | |
2071 | else if (CONSTANT_CLASS_P (t) | |
2072 | || TREE_CODE (t) == CONSTRUCTOR) | |
30b0317c | 2073 | ; |
998d7deb | 2074 | |
a787ccc3 RS |
2075 | /* If this is a field reference, record it. */ |
2076 | else if (TREE_CODE (t) == COMPONENT_REF) | |
998d7deb | 2077 | { |
f12144dd | 2078 | attrs.expr = t; |
754c3d5d RS |
2079 | attrs.offset_known_p = true; |
2080 | attrs.offset = 0; | |
6f1087be | 2081 | apply_bitpos = bitpos; |
a787ccc3 RS |
2082 | if (DECL_BIT_FIELD (TREE_OPERAND (t, 1))) |
2083 | new_size = DECL_SIZE_UNIT (TREE_OPERAND (t, 1)); | |
998d7deb RH |
2084 | } |
2085 | ||
80d6f89e RB |
2086 | /* Else record it. */ |
2087 | else | |
56c47f22 | 2088 | { |
80d6f89e RB |
2089 | gcc_assert (handled_component_p (t) |
2090 | || TREE_CODE (t) == MEM_REF | |
2091 | || TREE_CODE (t) == TARGET_MEM_REF); | |
f12144dd | 2092 | attrs.expr = t; |
754c3d5d RS |
2093 | attrs.offset_known_p = true; |
2094 | attrs.offset = 0; | |
56c47f22 RG |
2095 | apply_bitpos = bitpos; |
2096 | } | |
2097 | ||
fa70c221 RB |
2098 | /* If this is a reference based on a partitioned decl replace the |
2099 | base with a MEM_REF of the pointer representative we created | |
2100 | during stack slot partitioning. */ | |
2101 | if (attrs.expr | |
2102 | && VAR_P (base) | |
2103 | && ! is_global_var (base) | |
2104 | && cfun->gimple_df->decls_to_pointers != NULL) | |
2105 | { | |
2106 | tree *namep = cfun->gimple_df->decls_to_pointers->get (base); | |
2107 | if (namep) | |
2108 | { | |
2109 | attrs.expr = unshare_expr (attrs.expr); | |
2110 | tree *orig_base = &attrs.expr; | |
2111 | while (handled_component_p (*orig_base)) | |
2112 | orig_base = &TREE_OPERAND (*orig_base, 0); | |
2113 | tree aptrt = reference_alias_ptr_type (*orig_base); | |
2114 | *orig_base = build2 (MEM_REF, TREE_TYPE (*orig_base), *namep, | |
2115 | build_int_cst (aptrt, 0)); | |
2116 | } | |
2117 | } | |
2118 | ||
30b0317c RB |
2119 | /* Compute the alignment. */ |
2120 | unsigned int obj_align; | |
2121 | unsigned HOST_WIDE_INT obj_bitpos; | |
2122 | get_object_alignment_1 (t, &obj_align, &obj_bitpos); | |
d05d7551 RS |
2123 | unsigned int diff_align = known_alignment (obj_bitpos - bitpos); |
2124 | if (diff_align != 0) | |
2125 | obj_align = MIN (obj_align, diff_align); | |
30b0317c | 2126 | attrs.align = MAX (attrs.align, obj_align); |
8ac61af7 RK |
2127 | } |
2128 | ||
d05d7551 RS |
2129 | poly_uint64 const_size; |
2130 | if (poly_int_tree_p (new_size, &const_size)) | |
a787ccc3 RS |
2131 | { |
2132 | attrs.size_known_p = true; | |
d05d7551 | 2133 | attrs.size = const_size; |
a787ccc3 RS |
2134 | } |
2135 | ||
15c812e3 | 2136 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
2137 | bit position offset. Similarly, increase the size of the accessed |
2138 | object to contain the negative offset. */ | |
d05d7551 | 2139 | if (maybe_ne (apply_bitpos, 0)) |
8c317c5f | 2140 | { |
754c3d5d | 2141 | gcc_assert (attrs.offset_known_p); |
d05d7551 RS |
2142 | poly_int64 bytepos = bits_to_bytes_round_down (apply_bitpos); |
2143 | attrs.offset -= bytepos; | |
754c3d5d | 2144 | if (attrs.size_known_p) |
d05d7551 | 2145 | attrs.size += bytepos; |
8c317c5f | 2146 | } |
6f1087be | 2147 | |
8ac61af7 | 2148 | /* Now set the attributes we computed above. */ |
f18a7b25 | 2149 | attrs.addrspace = as; |
f12144dd | 2150 | set_mem_attrs (ref, &attrs); |
173b24b9 RK |
2151 | } |
2152 | ||
6f1087be | 2153 | void |
502b8322 | 2154 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
2155 | { |
2156 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
2157 | } | |
2158 | ||
173b24b9 RK |
2159 | /* Set the alias set of MEM to SET. */ |
2160 | ||
2161 | void | |
4862826d | 2162 | set_mem_alias_set (rtx mem, alias_set_type set) |
173b24b9 | 2163 | { |
173b24b9 | 2164 | /* If the new and old alias sets don't conflict, something is wrong. */ |
77a74ed7 | 2165 | gcc_checking_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))); |
d05d7551 | 2166 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2167 | attrs.alias = set; |
2168 | set_mem_attrs (mem, &attrs); | |
09e881c9 BE |
2169 | } |
2170 | ||
2171 | /* Set the address space of MEM to ADDRSPACE (target-defined). */ | |
2172 | ||
2173 | void | |
2174 | set_mem_addr_space (rtx mem, addr_space_t addrspace) | |
2175 | { | |
d05d7551 | 2176 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2177 | attrs.addrspace = addrspace; |
2178 | set_mem_attrs (mem, &attrs); | |
173b24b9 | 2179 | } |
738cc472 | 2180 | |
d022d93e | 2181 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
2182 | |
2183 | void | |
502b8322 | 2184 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 2185 | { |
d05d7551 | 2186 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2187 | attrs.align = align; |
2188 | set_mem_attrs (mem, &attrs); | |
738cc472 | 2189 | } |
1285011e | 2190 | |
998d7deb | 2191 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
2192 | |
2193 | void | |
502b8322 | 2194 | set_mem_expr (rtx mem, tree expr) |
1285011e | 2195 | { |
d05d7551 | 2196 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2197 | attrs.expr = expr; |
2198 | set_mem_attrs (mem, &attrs); | |
1285011e | 2199 | } |
998d7deb RH |
2200 | |
2201 | /* Set the offset of MEM to OFFSET. */ | |
2202 | ||
2203 | void | |
d05d7551 | 2204 | set_mem_offset (rtx mem, poly_int64 offset) |
998d7deb | 2205 | { |
d05d7551 | 2206 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d RS |
2207 | attrs.offset_known_p = true; |
2208 | attrs.offset = offset; | |
527210c4 RS |
2209 | set_mem_attrs (mem, &attrs); |
2210 | } | |
2211 | ||
2212 | /* Clear the offset of MEM. */ | |
2213 | ||
2214 | void | |
2215 | clear_mem_offset (rtx mem) | |
2216 | { | |
d05d7551 | 2217 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d | 2218 | attrs.offset_known_p = false; |
f12144dd | 2219 | set_mem_attrs (mem, &attrs); |
35aff10b AM |
2220 | } |
2221 | ||
2222 | /* Set the size of MEM to SIZE. */ | |
2223 | ||
2224 | void | |
d05d7551 | 2225 | set_mem_size (rtx mem, poly_int64 size) |
35aff10b | 2226 | { |
d05d7551 | 2227 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d RS |
2228 | attrs.size_known_p = true; |
2229 | attrs.size = size; | |
f5541398 RS |
2230 | set_mem_attrs (mem, &attrs); |
2231 | } | |
2232 | ||
2233 | /* Clear the size of MEM. */ | |
2234 | ||
2235 | void | |
2236 | clear_mem_size (rtx mem) | |
2237 | { | |
d05d7551 | 2238 | mem_attrs attrs (*get_mem_attrs (mem)); |
754c3d5d | 2239 | attrs.size_known_p = false; |
f12144dd | 2240 | set_mem_attrs (mem, &attrs); |
998d7deb | 2241 | } |
173b24b9 | 2242 | \f |
738cc472 RK |
2243 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
2244 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
2245 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
23b33725 RS |
2246 | returned memory location is required to be valid. INPLACE is true if any |
2247 | changes can be made directly to MEMREF or false if MEMREF must be treated | |
2248 | as immutable. | |
2249 | ||
2250 | The memory attributes are not changed. */ | |
23b2ce53 | 2251 | |
738cc472 | 2252 | static rtx |
ef4bddc2 | 2253 | change_address_1 (rtx memref, machine_mode mode, rtx addr, int validate, |
23b33725 | 2254 | bool inplace) |
23b2ce53 | 2255 | { |
09e881c9 | 2256 | addr_space_t as; |
60564289 | 2257 | rtx new_rtx; |
23b2ce53 | 2258 | |
5b0264cb | 2259 | gcc_assert (MEM_P (memref)); |
09e881c9 | 2260 | as = MEM_ADDR_SPACE (memref); |
23b2ce53 RS |
2261 | if (mode == VOIDmode) |
2262 | mode = GET_MODE (memref); | |
2263 | if (addr == 0) | |
2264 | addr = XEXP (memref, 0); | |
a74ff877 | 2265 | if (mode == GET_MODE (memref) && addr == XEXP (memref, 0) |
09e881c9 | 2266 | && (!validate || memory_address_addr_space_p (mode, addr, as))) |
a74ff877 | 2267 | return memref; |
23b2ce53 | 2268 | |
91c5ee5b VM |
2269 | /* Don't validate address for LRA. LRA can make the address valid |
2270 | by itself in most efficient way. */ | |
2271 | if (validate && !lra_in_progress) | |
23b2ce53 | 2272 | { |
f1ec5147 | 2273 | if (reload_in_progress || reload_completed) |
09e881c9 | 2274 | gcc_assert (memory_address_addr_space_p (mode, addr, as)); |
f1ec5147 | 2275 | else |
09e881c9 | 2276 | addr = memory_address_addr_space (mode, addr, as); |
23b2ce53 | 2277 | } |
750c9258 | 2278 | |
9b04c6a8 RK |
2279 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
2280 | return memref; | |
2281 | ||
23b33725 RS |
2282 | if (inplace) |
2283 | { | |
2284 | XEXP (memref, 0) = addr; | |
2285 | return memref; | |
2286 | } | |
2287 | ||
60564289 KG |
2288 | new_rtx = gen_rtx_MEM (mode, addr); |
2289 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
2290 | return new_rtx; | |
23b2ce53 | 2291 | } |
792760b9 | 2292 | |
738cc472 RK |
2293 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
2294 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
2295 | |
2296 | rtx | |
ef4bddc2 | 2297 | change_address (rtx memref, machine_mode mode, rtx addr) |
f4ef873c | 2298 | { |
23b33725 | 2299 | rtx new_rtx = change_address_1 (memref, mode, addr, 1, false); |
ef4bddc2 | 2300 | machine_mode mmode = GET_MODE (new_rtx); |
99b1c316 | 2301 | class mem_attrs *defattrs; |
4e44c1ef | 2302 | |
d05d7551 | 2303 | mem_attrs attrs (*get_mem_attrs (memref)); |
f12144dd | 2304 | defattrs = mode_mem_attrs[(int) mmode]; |
754c3d5d RS |
2305 | attrs.expr = NULL_TREE; |
2306 | attrs.offset_known_p = false; | |
2307 | attrs.size_known_p = defattrs->size_known_p; | |
f12144dd RS |
2308 | attrs.size = defattrs->size; |
2309 | attrs.align = defattrs->align; | |
c2f7bcc3 | 2310 | |
fdb1c7b3 | 2311 | /* If there are no changes, just return the original memory reference. */ |
60564289 | 2312 | if (new_rtx == memref) |
4e44c1ef | 2313 | { |
f12144dd | 2314 | if (mem_attrs_eq_p (get_mem_attrs (memref), &attrs)) |
60564289 | 2315 | return new_rtx; |
4e44c1ef | 2316 | |
60564289 KG |
2317 | new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0)); |
2318 | MEM_COPY_ATTRIBUTES (new_rtx, memref); | |
4e44c1ef | 2319 | } |
fdb1c7b3 | 2320 | |
f12144dd | 2321 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2322 | return new_rtx; |
f4ef873c | 2323 | } |
792760b9 | 2324 | |
738cc472 RK |
2325 | /* Return a memory reference like MEMREF, but with its mode changed |
2326 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 | 2327 | nonzero, the memory address is forced to be valid. |
5ef0b50d EB |
2328 | If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS |
2329 | and the caller is responsible for adjusting MEMREF base register. | |
2330 | If ADJUST_OBJECT is zero, the underlying object associated with the | |
2331 | memory reference is left unchanged and the caller is responsible for | |
2332 | dealing with it. Otherwise, if the new memory reference is outside | |
5f2cbd0d RS |
2333 | the underlying object, even partially, then the object is dropped. |
2334 | SIZE, if nonzero, is the size of an access in cases where MODE | |
2335 | has no inherent size. */ | |
f1ec5147 RK |
2336 | |
2337 | rtx | |
d05d7551 | 2338 | adjust_address_1 (rtx memref, machine_mode mode, poly_int64 offset, |
5f2cbd0d | 2339 | int validate, int adjust_address, int adjust_object, |
d05d7551 | 2340 | poly_int64 size) |
f1ec5147 | 2341 | { |
823e3574 | 2342 | rtx addr = XEXP (memref, 0); |
60564289 | 2343 | rtx new_rtx; |
095a2d76 | 2344 | scalar_int_mode address_mode; |
99b1c316 | 2345 | class mem_attrs attrs (*get_mem_attrs (memref)), *defattrs; |
f12144dd | 2346 | unsigned HOST_WIDE_INT max_align; |
0207fa90 | 2347 | #ifdef POINTERS_EXTEND_UNSIGNED |
095a2d76 | 2348 | scalar_int_mode pointer_mode |
0207fa90 EB |
2349 | = targetm.addr_space.pointer_mode (attrs.addrspace); |
2350 | #endif | |
823e3574 | 2351 | |
ee88e690 EB |
2352 | /* VOIDmode means no mode change for change_address_1. */ |
2353 | if (mode == VOIDmode) | |
2354 | mode = GET_MODE (memref); | |
2355 | ||
5f2cbd0d RS |
2356 | /* Take the size of non-BLKmode accesses from the mode. */ |
2357 | defattrs = mode_mem_attrs[(int) mode]; | |
2358 | if (defattrs->size_known_p) | |
2359 | size = defattrs->size; | |
2360 | ||
fdb1c7b3 | 2361 | /* If there are no changes, just return the original memory reference. */ |
d05d7551 RS |
2362 | if (mode == GET_MODE (memref) |
2363 | && known_eq (offset, 0) | |
2364 | && (known_eq (size, 0) | |
2365 | || (attrs.size_known_p && known_eq (attrs.size, size))) | |
f12144dd RS |
2366 | && (!validate || memory_address_addr_space_p (mode, addr, |
2367 | attrs.addrspace))) | |
fdb1c7b3 JH |
2368 | return memref; |
2369 | ||
d14419e4 | 2370 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2371 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2372 | (plus (plus reg reg) const_int) -- so do this always. */ |
2373 | addr = copy_rtx (addr); | |
2374 | ||
a6fe9ed4 JM |
2375 | /* Convert a possibly large offset to a signed value within the |
2376 | range of the target address space. */ | |
372d6395 | 2377 | address_mode = get_address_mode (memref); |
d05d7551 | 2378 | offset = trunc_int_for_mode (offset, address_mode); |
a6fe9ed4 | 2379 | |
5ef0b50d | 2380 | if (adjust_address) |
4a78c787 RH |
2381 | { |
2382 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2383 | object, we can merge it into the LO_SUM. */ | |
d05d7551 RS |
2384 | if (GET_MODE (memref) != BLKmode |
2385 | && GET_CODE (addr) == LO_SUM | |
2386 | && known_in_range_p (offset, | |
2387 | 0, (GET_MODE_ALIGNMENT (GET_MODE (memref)) | |
2388 | / BITS_PER_UNIT))) | |
d4ebfa65 | 2389 | addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0), |
0a81f074 RS |
2390 | plus_constant (address_mode, |
2391 | XEXP (addr, 1), offset)); | |
0207fa90 EB |
2392 | #ifdef POINTERS_EXTEND_UNSIGNED |
2393 | /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid | |
2394 | in that mode, we merge it into the ZERO_EXTEND. We take advantage of | |
2395 | the fact that pointers are not allowed to overflow. */ | |
2396 | else if (POINTERS_EXTEND_UNSIGNED > 0 | |
2397 | && GET_CODE (addr) == ZERO_EXTEND | |
2398 | && GET_MODE (XEXP (addr, 0)) == pointer_mode | |
d05d7551 | 2399 | && known_eq (trunc_int_for_mode (offset, pointer_mode), offset)) |
0207fa90 EB |
2400 | addr = gen_rtx_ZERO_EXTEND (address_mode, |
2401 | plus_constant (pointer_mode, | |
2402 | XEXP (addr, 0), offset)); | |
2403 | #endif | |
4a78c787 | 2404 | else |
0a81f074 | 2405 | addr = plus_constant (address_mode, addr, offset); |
4a78c787 | 2406 | } |
823e3574 | 2407 | |
23b33725 | 2408 | new_rtx = change_address_1 (memref, mode, addr, validate, false); |
738cc472 | 2409 | |
09efeca1 PB |
2410 | /* If the address is a REG, change_address_1 rightfully returns memref, |
2411 | but this would destroy memref's MEM_ATTRS. */ | |
d05d7551 | 2412 | if (new_rtx == memref && maybe_ne (offset, 0)) |
09efeca1 PB |
2413 | new_rtx = copy_rtx (new_rtx); |
2414 | ||
5ef0b50d EB |
2415 | /* Conservatively drop the object if we don't know where we start from. */ |
2416 | if (adjust_object && (!attrs.offset_known_p || !attrs.size_known_p)) | |
2417 | { | |
2418 | attrs.expr = NULL_TREE; | |
2419 | attrs.alias = 0; | |
2420 | } | |
2421 | ||
738cc472 RK |
2422 | /* Compute the new values of the memory attributes due to this adjustment. |
2423 | We add the offsets and update the alignment. */ | |
754c3d5d | 2424 | if (attrs.offset_known_p) |
5ef0b50d EB |
2425 | { |
2426 | attrs.offset += offset; | |
2427 | ||
2428 | /* Drop the object if the new left end is not within its bounds. */ | |
d05d7551 | 2429 | if (adjust_object && maybe_lt (attrs.offset, 0)) |
5ef0b50d EB |
2430 | { |
2431 | attrs.expr = NULL_TREE; | |
2432 | attrs.alias = 0; | |
2433 | } | |
2434 | } | |
738cc472 | 2435 | |
03bf2c23 RK |
2436 | /* Compute the new alignment by taking the MIN of the alignment and the |
2437 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2438 | if zero. */ | |
d05d7551 | 2439 | if (maybe_ne (offset, 0)) |
f12144dd | 2440 | { |
d05d7551 | 2441 | max_align = known_alignment (offset) * BITS_PER_UNIT; |
f12144dd RS |
2442 | attrs.align = MIN (attrs.align, max_align); |
2443 | } | |
738cc472 | 2444 | |
d05d7551 | 2445 | if (maybe_ne (size, 0)) |
754c3d5d | 2446 | { |
5ef0b50d | 2447 | /* Drop the object if the new right end is not within its bounds. */ |
d05d7551 | 2448 | if (adjust_object && maybe_gt (offset + size, attrs.size)) |
5ef0b50d EB |
2449 | { |
2450 | attrs.expr = NULL_TREE; | |
2451 | attrs.alias = 0; | |
2452 | } | |
754c3d5d | 2453 | attrs.size_known_p = true; |
5f2cbd0d | 2454 | attrs.size = size; |
754c3d5d RS |
2455 | } |
2456 | else if (attrs.size_known_p) | |
5ef0b50d | 2457 | { |
5f2cbd0d | 2458 | gcc_assert (!adjust_object); |
5ef0b50d | 2459 | attrs.size -= offset; |
5f2cbd0d RS |
2460 | /* ??? The store_by_pieces machinery generates negative sizes, |
2461 | so don't assert for that here. */ | |
5ef0b50d | 2462 | } |
10b76d73 | 2463 | |
f12144dd | 2464 | set_mem_attrs (new_rtx, &attrs); |
738cc472 | 2465 | |
60564289 | 2466 | return new_rtx; |
f1ec5147 RK |
2467 | } |
2468 | ||
630036c6 JJ |
2469 | /* Return a memory reference like MEMREF, but with its mode changed |
2470 | to MODE and its address changed to ADDR, which is assumed to be | |
fa10beec | 2471 | MEMREF offset by OFFSET bytes. If VALIDATE is |
630036c6 JJ |
2472 | nonzero, the memory address is forced to be valid. */ |
2473 | ||
2474 | rtx | |
ef4bddc2 | 2475 | adjust_automodify_address_1 (rtx memref, machine_mode mode, rtx addr, |
d05d7551 | 2476 | poly_int64 offset, int validate) |
630036c6 | 2477 | { |
23b33725 | 2478 | memref = change_address_1 (memref, VOIDmode, addr, validate, false); |
5f2cbd0d | 2479 | return adjust_address_1 (memref, mode, offset, validate, 0, 0, 0); |
630036c6 JJ |
2480 | } |
2481 | ||
8ac61af7 RK |
2482 | /* Return a memory reference like MEMREF, but whose address is changed by |
2483 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2484 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2485 | |
2486 | rtx | |
502b8322 | 2487 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2488 | { |
60564289 | 2489 | rtx new_rtx, addr = XEXP (memref, 0); |
ef4bddc2 | 2490 | machine_mode address_mode; |
99b1c316 | 2491 | class mem_attrs *defattrs; |
e3c8ea67 | 2492 | |
d05d7551 | 2493 | mem_attrs attrs (*get_mem_attrs (memref)); |
372d6395 | 2494 | address_mode = get_address_mode (memref); |
d4ebfa65 | 2495 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 | 2496 | |
68252e27 | 2497 | /* At this point we don't know _why_ the address is invalid. It |
4d6922ee | 2498 | could have secondary memory references, multiplies or anything. |
e3c8ea67 RH |
2499 | |
2500 | However, if we did go and rearrange things, we can wind up not | |
2501 | being able to recognize the magic around pic_offset_table_rtx. | |
2502 | This stuff is fragile, and is yet another example of why it is | |
2503 | bad to expose PIC machinery too early. */ | |
f12144dd RS |
2504 | if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx, |
2505 | attrs.addrspace) | |
e3c8ea67 RH |
2506 | && GET_CODE (addr) == PLUS |
2507 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2508 | { | |
2509 | addr = force_reg (GET_MODE (addr), addr); | |
d4ebfa65 | 2510 | new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset); |
e3c8ea67 RH |
2511 | } |
2512 | ||
60564289 | 2513 | update_temp_slot_address (XEXP (memref, 0), new_rtx); |
23b33725 | 2514 | new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1, false); |
0d4903b8 | 2515 | |
fdb1c7b3 | 2516 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2517 | if (new_rtx == memref) |
2518 | return new_rtx; | |
fdb1c7b3 | 2519 | |
0d4903b8 RK |
2520 | /* Update the alignment to reflect the offset. Reset the offset, which |
2521 | we don't know. */ | |
754c3d5d RS |
2522 | defattrs = mode_mem_attrs[(int) GET_MODE (new_rtx)]; |
2523 | attrs.offset_known_p = false; | |
2524 | attrs.size_known_p = defattrs->size_known_p; | |
2525 | attrs.size = defattrs->size; | |
f12144dd RS |
2526 | attrs.align = MIN (attrs.align, pow2 * BITS_PER_UNIT); |
2527 | set_mem_attrs (new_rtx, &attrs); | |
60564289 | 2528 | return new_rtx; |
0d4903b8 | 2529 | } |
68252e27 | 2530 | |
792760b9 RK |
2531 | /* Return a memory reference like MEMREF, but with its address changed to |
2532 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2533 | to is the same, just the form of the address is being changed, such as | |
23b33725 RS |
2534 | by putting something into a register. INPLACE is true if any changes |
2535 | can be made directly to MEMREF or false if MEMREF must be treated as | |
2536 | immutable. */ | |
792760b9 RK |
2537 | |
2538 | rtx | |
23b33725 | 2539 | replace_equiv_address (rtx memref, rtx addr, bool inplace) |
792760b9 | 2540 | { |
738cc472 RK |
2541 | /* change_address_1 copies the memory attribute structure without change |
2542 | and that's exactly what we want here. */ | |
40c0668b | 2543 | update_temp_slot_address (XEXP (memref, 0), addr); |
23b33725 | 2544 | return change_address_1 (memref, VOIDmode, addr, 1, inplace); |
792760b9 | 2545 | } |
738cc472 | 2546 | |
f1ec5147 RK |
2547 | /* Likewise, but the reference is not required to be valid. */ |
2548 | ||
2549 | rtx | |
23b33725 | 2550 | replace_equiv_address_nv (rtx memref, rtx addr, bool inplace) |
f1ec5147 | 2551 | { |
23b33725 | 2552 | return change_address_1 (memref, VOIDmode, addr, 0, inplace); |
f1ec5147 | 2553 | } |
e7dfe4bb RH |
2554 | |
2555 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2556 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2557 | cannot issue QImode memory operations and have to use SImode memory | |
2558 | operations plus masking logic. */ | |
2559 | ||
2560 | rtx | |
d05d7551 | 2561 | widen_memory_access (rtx memref, machine_mode mode, poly_int64 offset) |
e7dfe4bb | 2562 | { |
5f2cbd0d | 2563 | rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1, 0, 0); |
cf098191 | 2564 | poly_uint64 size = GET_MODE_SIZE (mode); |
e7dfe4bb | 2565 | |
fdb1c7b3 | 2566 | /* If there are no changes, just return the original memory reference. */ |
60564289 KG |
2567 | if (new_rtx == memref) |
2568 | return new_rtx; | |
fdb1c7b3 | 2569 | |
d05d7551 | 2570 | mem_attrs attrs (*get_mem_attrs (new_rtx)); |
f12144dd | 2571 | |
e7dfe4bb RH |
2572 | /* If we don't know what offset we were at within the expression, then |
2573 | we can't know if we've overstepped the bounds. */ | |
754c3d5d | 2574 | if (! attrs.offset_known_p) |
f12144dd | 2575 | attrs.expr = NULL_TREE; |
e7dfe4bb | 2576 | |
f12144dd | 2577 | while (attrs.expr) |
e7dfe4bb | 2578 | { |
f12144dd | 2579 | if (TREE_CODE (attrs.expr) == COMPONENT_REF) |
e7dfe4bb | 2580 | { |
f12144dd RS |
2581 | tree field = TREE_OPERAND (attrs.expr, 1); |
2582 | tree offset = component_ref_field_offset (attrs.expr); | |
e7dfe4bb RH |
2583 | |
2584 | if (! DECL_SIZE_UNIT (field)) | |
2585 | { | |
f12144dd | 2586 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2587 | break; |
2588 | } | |
2589 | ||
2590 | /* Is the field at least as large as the access? If so, ok, | |
2591 | otherwise strip back to the containing structure. */ | |
d05d7551 RS |
2592 | if (poly_int_tree_p (DECL_SIZE_UNIT (field)) |
2593 | && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (field)), size) | |
2594 | && known_ge (attrs.offset, 0)) | |
e7dfe4bb RH |
2595 | break; |
2596 | ||
d05d7551 RS |
2597 | poly_uint64 suboffset; |
2598 | if (!poly_int_tree_p (offset, &suboffset)) | |
e7dfe4bb | 2599 | { |
f12144dd | 2600 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2601 | break; |
2602 | } | |
2603 | ||
f12144dd | 2604 | attrs.expr = TREE_OPERAND (attrs.expr, 0); |
d05d7551 | 2605 | attrs.offset += suboffset; |
ae7e9ddd | 2606 | attrs.offset += (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field)) |
754c3d5d | 2607 | / BITS_PER_UNIT); |
e7dfe4bb RH |
2608 | } |
2609 | /* Similarly for the decl. */ | |
f12144dd RS |
2610 | else if (DECL_P (attrs.expr) |
2611 | && DECL_SIZE_UNIT (attrs.expr) | |
d05d7551 RS |
2612 | && poly_int_tree_p (DECL_SIZE_UNIT (attrs.expr)) |
2613 | && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (attrs.expr)), | |
2614 | size) | |
2615 | && known_ge (attrs.offset, 0)) | |
e7dfe4bb RH |
2616 | break; |
2617 | else | |
2618 | { | |
2619 | /* The widened memory access overflows the expression, which means | |
2620 | that it could alias another expression. Zap it. */ | |
f12144dd | 2621 | attrs.expr = NULL_TREE; |
e7dfe4bb RH |
2622 | break; |
2623 | } | |
2624 | } | |
2625 | ||
f12144dd | 2626 | if (! attrs.expr) |
754c3d5d | 2627 | attrs.offset_known_p = false; |
e7dfe4bb RH |
2628 | |
2629 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2630 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
f12144dd | 2631 | attrs.alias = 0; |
754c3d5d RS |
2632 | attrs.size_known_p = true; |
2633 | attrs.size = size; | |
f12144dd | 2634 | set_mem_attrs (new_rtx, &attrs); |
60564289 | 2635 | return new_rtx; |
e7dfe4bb | 2636 | } |
23b2ce53 | 2637 | \f |
f6129d66 RH |
2638 | /* A fake decl that is used as the MEM_EXPR of spill slots. */ |
2639 | static GTY(()) tree spill_slot_decl; | |
2640 | ||
3d7e23f6 RH |
2641 | tree |
2642 | get_spill_slot_decl (bool force_build_p) | |
f6129d66 RH |
2643 | { |
2644 | tree d = spill_slot_decl; | |
2645 | rtx rd; | |
2646 | ||
3d7e23f6 | 2647 | if (d || !force_build_p) |
f6129d66 RH |
2648 | return d; |
2649 | ||
c2255bc4 AH |
2650 | d = build_decl (DECL_SOURCE_LOCATION (current_function_decl), |
2651 | VAR_DECL, get_identifier ("%sfp"), void_type_node); | |
f6129d66 RH |
2652 | DECL_ARTIFICIAL (d) = 1; |
2653 | DECL_IGNORED_P (d) = 1; | |
2654 | TREE_USED (d) = 1; | |
f6129d66 RH |
2655 | spill_slot_decl = d; |
2656 | ||
2657 | rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx); | |
2658 | MEM_NOTRAP_P (rd) = 1; | |
d05d7551 | 2659 | mem_attrs attrs (*mode_mem_attrs[(int) BLKmode]); |
f12144dd RS |
2660 | attrs.alias = new_alias_set (); |
2661 | attrs.expr = d; | |
2662 | set_mem_attrs (rd, &attrs); | |
f6129d66 RH |
2663 | SET_DECL_RTL (d, rd); |
2664 | ||
2665 | return d; | |
2666 | } | |
2667 | ||
2668 | /* Given MEM, a result from assign_stack_local, fill in the memory | |
2669 | attributes as appropriate for a register allocator spill slot. | |
2670 | These slots are not aliasable by other memory. We arrange for | |
2671 | them all to use a single MEM_EXPR, so that the aliasing code can | |
2672 | work properly in the case of shared spill slots. */ | |
2673 | ||
2674 | void | |
2675 | set_mem_attrs_for_spill (rtx mem) | |
2676 | { | |
f12144dd | 2677 | rtx addr; |
f6129d66 | 2678 | |
d05d7551 | 2679 | mem_attrs attrs (*get_mem_attrs (mem)); |
f12144dd RS |
2680 | attrs.expr = get_spill_slot_decl (true); |
2681 | attrs.alias = MEM_ALIAS_SET (DECL_RTL (attrs.expr)); | |
2682 | attrs.addrspace = ADDR_SPACE_GENERIC; | |
f6129d66 RH |
2683 | |
2684 | /* We expect the incoming memory to be of the form: | |
2685 | (mem:MODE (plus (reg sfp) (const_int offset))) | |
2686 | with perhaps the plus missing for offset = 0. */ | |
2687 | addr = XEXP (mem, 0); | |
754c3d5d | 2688 | attrs.offset_known_p = true; |
d05d7551 | 2689 | strip_offset (addr, &attrs.offset); |
f6129d66 | 2690 | |
f12144dd | 2691 | set_mem_attrs (mem, &attrs); |
f6129d66 RH |
2692 | MEM_NOTRAP_P (mem) = 1; |
2693 | } | |
2694 | \f | |
23b2ce53 RS |
2695 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ |
2696 | ||
7dcc3ab5 | 2697 | rtx_code_label * |
502b8322 | 2698 | gen_label_rtx (void) |
23b2ce53 | 2699 | { |
7dcc3ab5 DM |
2700 | return as_a <rtx_code_label *> ( |
2701 | gen_rtx_CODE_LABEL (VOIDmode, NULL_RTX, NULL_RTX, | |
2702 | NULL, label_num++, NULL)); | |
23b2ce53 RS |
2703 | } |
2704 | \f | |
2705 | /* For procedure integration. */ | |
2706 | ||
23b2ce53 | 2707 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2708 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2709 | Used for an inline-procedure after copying the insn chain. */ |
2710 | ||
2711 | void | |
fee3e72c | 2712 | set_new_first_and_last_insn (rtx_insn *first, rtx_insn *last) |
23b2ce53 | 2713 | { |
fee3e72c | 2714 | rtx_insn *insn; |
86fe05e0 | 2715 | |
5936d944 JH |
2716 | set_first_insn (first); |
2717 | set_last_insn (last); | |
86fe05e0 RK |
2718 | cur_insn_uid = 0; |
2719 | ||
028d4092 | 2720 | if (param_min_nondebug_insn_uid || MAY_HAVE_DEBUG_INSNS) |
b5b8b0ac AO |
2721 | { |
2722 | int debug_count = 0; | |
2723 | ||
028d4092 | 2724 | cur_insn_uid = param_min_nondebug_insn_uid - 1; |
b5b8b0ac AO |
2725 | cur_debug_insn_uid = 0; |
2726 | ||
2727 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
028d4092 | 2728 | if (INSN_UID (insn) < param_min_nondebug_insn_uid) |
b5b8b0ac AO |
2729 | cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn)); |
2730 | else | |
2731 | { | |
2732 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2733 | if (DEBUG_INSN_P (insn)) | |
2734 | debug_count++; | |
2735 | } | |
2736 | ||
2737 | if (debug_count) | |
028d4092 | 2738 | cur_debug_insn_uid = param_min_nondebug_insn_uid + debug_count; |
b5b8b0ac AO |
2739 | else |
2740 | cur_debug_insn_uid++; | |
2741 | } | |
2742 | else | |
2743 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2744 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
86fe05e0 RK |
2745 | |
2746 | cur_insn_uid++; | |
23b2ce53 | 2747 | } |
23b2ce53 | 2748 | \f |
750c9258 | 2749 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2750 | structure. This routine should only be called once. */ |
23b2ce53 | 2751 | |
fd743bc1 | 2752 | static void |
6bb9bf63 | 2753 | unshare_all_rtl_1 (rtx_insn *insn) |
23b2ce53 | 2754 | { |
d1b81779 | 2755 | /* Unshare just about everything else. */ |
2c07f13b | 2756 | unshare_all_rtl_in_chain (insn); |
750c9258 | 2757 | |
23b2ce53 RS |
2758 | /* Make sure the addresses of stack slots found outside the insn chain |
2759 | (such as, in DECL_RTL of a variable) are not shared | |
2760 | with the insn chain. | |
2761 | ||
2762 | This special care is necessary when the stack slot MEM does not | |
2763 | actually appear in the insn chain. If it does appear, its address | |
2764 | is unshared from all else at that point. */ | |
8c39f8ae TS |
2765 | unsigned int i; |
2766 | rtx temp; | |
2767 | FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp) | |
2768 | (*stack_slot_list)[i] = copy_rtx_if_shared (temp); | |
23b2ce53 RS |
2769 | } |
2770 | ||
750c9258 | 2771 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2772 | structure, again. This is a fairly expensive thing to do so it |
2773 | should be done sparingly. */ | |
2774 | ||
2775 | void | |
6bb9bf63 | 2776 | unshare_all_rtl_again (rtx_insn *insn) |
d1b81779 | 2777 | { |
6bb9bf63 | 2778 | rtx_insn *p; |
624c87aa RE |
2779 | tree decl; |
2780 | ||
d1b81779 | 2781 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2782 | if (INSN_P (p)) |
d1b81779 GK |
2783 | { |
2784 | reset_used_flags (PATTERN (p)); | |
2785 | reset_used_flags (REG_NOTES (p)); | |
776bebcd JJ |
2786 | if (CALL_P (p)) |
2787 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (p)); | |
d1b81779 | 2788 | } |
624c87aa | 2789 | |
2d4aecb3 | 2790 | /* Make sure that virtual stack slots are not shared. */ |
5eb2a9f2 | 2791 | set_used_decls (DECL_INITIAL (cfun->decl)); |
2d4aecb3 | 2792 | |
624c87aa | 2793 | /* Make sure that virtual parameters are not shared. */ |
910ad8de | 2794 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) |
5eb2a9f2 | 2795 | set_used_flags (DECL_RTL (decl)); |
624c87aa | 2796 | |
8c39f8ae TS |
2797 | rtx temp; |
2798 | unsigned int i; | |
2799 | FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp) | |
2800 | reset_used_flags (temp); | |
624c87aa | 2801 | |
b4aaa77b | 2802 | unshare_all_rtl_1 (insn); |
fd743bc1 PB |
2803 | } |
2804 | ||
c2924966 | 2805 | unsigned int |
fd743bc1 PB |
2806 | unshare_all_rtl (void) |
2807 | { | |
b4aaa77b | 2808 | unshare_all_rtl_1 (get_insns ()); |
60ebe8ce JJ |
2809 | |
2810 | for (tree decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl)) | |
2811 | { | |
2812 | if (DECL_RTL_SET_P (decl)) | |
2813 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); | |
2814 | DECL_INCOMING_RTL (decl) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl)); | |
2815 | } | |
2816 | ||
c2924966 | 2817 | return 0; |
d1b81779 GK |
2818 | } |
2819 | ||
ef330312 | 2820 | |
2c07f13b JH |
2821 | /* Check that ORIG is not marked when it should not be and mark ORIG as in use, |
2822 | Recursively does the same for subexpressions. */ | |
2823 | ||
2824 | static void | |
2825 | verify_rtx_sharing (rtx orig, rtx insn) | |
2826 | { | |
2827 | rtx x = orig; | |
2828 | int i; | |
2829 | enum rtx_code code; | |
2830 | const char *format_ptr; | |
2831 | ||
2832 | if (x == 0) | |
2833 | return; | |
2834 | ||
2835 | code = GET_CODE (x); | |
2836 | ||
2837 | /* These types may be freely shared. */ | |
2838 | ||
2839 | switch (code) | |
2840 | { | |
2841 | case REG: | |
0ca5af51 AO |
2842 | case DEBUG_EXPR: |
2843 | case VALUE: | |
d8116890 | 2844 | CASE_CONST_ANY: |
2c07f13b JH |
2845 | case SYMBOL_REF: |
2846 | case LABEL_REF: | |
2847 | case CODE_LABEL: | |
2848 | case PC: | |
3810076b | 2849 | case RETURN: |
26898771 | 2850 | case SIMPLE_RETURN: |
2c07f13b | 2851 | case SCRATCH: |
3e89ed8d | 2852 | /* SCRATCH must be shared because they represent distinct values. */ |
c5c5ba89 | 2853 | return; |
3e89ed8d | 2854 | case CLOBBER: |
bd1cd0d0 | 2855 | /* Share clobbers of hard registers, but do not share pseudo reg |
c5c5ba89 JH |
2856 | clobbers or clobbers of hard registers that originated as pseudos. |
2857 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
2858 | if (REG_P (XEXP (x, 0)) |
2859 | && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0))) | |
2860 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0)))) | |
3e89ed8d JH |
2861 | return; |
2862 | break; | |
2c07f13b JH |
2863 | |
2864 | case CONST: | |
6fb5fa3c | 2865 | if (shared_const_p (orig)) |
2c07f13b JH |
2866 | return; |
2867 | break; | |
2868 | ||
2869 | case MEM: | |
2870 | /* A MEM is allowed to be shared if its address is constant. */ | |
2871 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
2872 | || reload_completed || reload_in_progress) | |
2873 | return; | |
2874 | ||
2875 | break; | |
2876 | ||
2877 | default: | |
2878 | break; | |
2879 | } | |
2880 | ||
2881 | /* This rtx may not be shared. If it has already been seen, | |
2882 | replace it with a copy of itself. */ | |
b2b29377 | 2883 | if (flag_checking && RTX_FLAG (x, used)) |
2c07f13b | 2884 | { |
ab532386 | 2885 | error ("invalid rtl sharing found in the insn"); |
2c07f13b | 2886 | debug_rtx (insn); |
ab532386 | 2887 | error ("shared rtx"); |
2c07f13b | 2888 | debug_rtx (x); |
ab532386 | 2889 | internal_error ("internal consistency failure"); |
2c07f13b | 2890 | } |
1a2caa7a | 2891 | gcc_assert (!RTX_FLAG (x, used)); |
b8698a0f | 2892 | |
2c07f13b JH |
2893 | RTX_FLAG (x, used) = 1; |
2894 | ||
6614fd40 | 2895 | /* Now scan the subexpressions recursively. */ |
2c07f13b JH |
2896 | |
2897 | format_ptr = GET_RTX_FORMAT (code); | |
2898 | ||
2899 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2900 | { | |
2901 | switch (*format_ptr++) | |
2902 | { | |
2903 | case 'e': | |
2904 | verify_rtx_sharing (XEXP (x, i), insn); | |
2905 | break; | |
2906 | ||
2907 | case 'E': | |
2908 | if (XVEC (x, i) != NULL) | |
2909 | { | |
2910 | int j; | |
2911 | int len = XVECLEN (x, i); | |
2912 | ||
2913 | for (j = 0; j < len; j++) | |
2914 | { | |
1a2caa7a NS |
2915 | /* We allow sharing of ASM_OPERANDS inside single |
2916 | instruction. */ | |
2c07f13b | 2917 | if (j && GET_CODE (XVECEXP (x, i, j)) == SET |
1a2caa7a NS |
2918 | && (GET_CODE (SET_SRC (XVECEXP (x, i, j))) |
2919 | == ASM_OPERANDS)) | |
2c07f13b JH |
2920 | verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn); |
2921 | else | |
2922 | verify_rtx_sharing (XVECEXP (x, i, j), insn); | |
2923 | } | |
2924 | } | |
2925 | break; | |
2926 | } | |
2927 | } | |
2928 | return; | |
2929 | } | |
2930 | ||
0e0f87d4 SB |
2931 | /* Reset used-flags for INSN. */ |
2932 | ||
2933 | static void | |
2934 | reset_insn_used_flags (rtx insn) | |
2935 | { | |
2936 | gcc_assert (INSN_P (insn)); | |
2937 | reset_used_flags (PATTERN (insn)); | |
2938 | reset_used_flags (REG_NOTES (insn)); | |
2939 | if (CALL_P (insn)) | |
2940 | reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn)); | |
2941 | } | |
2942 | ||
a24243a0 | 2943 | /* Go through all the RTL insn bodies and clear all the USED bits. */ |
2c07f13b | 2944 | |
a24243a0 AK |
2945 | static void |
2946 | reset_all_used_flags (void) | |
2c07f13b | 2947 | { |
dc01c3d1 | 2948 | rtx_insn *p; |
2c07f13b JH |
2949 | |
2950 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2951 | if (INSN_P (p)) | |
2952 | { | |
0e0f87d4 SB |
2953 | rtx pat = PATTERN (p); |
2954 | if (GET_CODE (pat) != SEQUENCE) | |
2955 | reset_insn_used_flags (p); | |
2956 | else | |
2954a813 | 2957 | { |
0e0f87d4 SB |
2958 | gcc_assert (REG_NOTES (p) == NULL); |
2959 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
2960 | { |
2961 | rtx insn = XVECEXP (pat, 0, i); | |
2962 | if (INSN_P (insn)) | |
2963 | reset_insn_used_flags (insn); | |
2964 | } | |
2954a813 | 2965 | } |
2c07f13b | 2966 | } |
a24243a0 AK |
2967 | } |
2968 | ||
0e0f87d4 SB |
2969 | /* Verify sharing in INSN. */ |
2970 | ||
2971 | static void | |
2972 | verify_insn_sharing (rtx insn) | |
2973 | { | |
2974 | gcc_assert (INSN_P (insn)); | |
4b498f72 JJ |
2975 | verify_rtx_sharing (PATTERN (insn), insn); |
2976 | verify_rtx_sharing (REG_NOTES (insn), insn); | |
0e0f87d4 | 2977 | if (CALL_P (insn)) |
4b498f72 | 2978 | verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn), insn); |
0e0f87d4 SB |
2979 | } |
2980 | ||
a24243a0 AK |
2981 | /* Go through all the RTL insn bodies and check that there is no unexpected |
2982 | sharing in between the subexpressions. */ | |
2983 | ||
2984 | DEBUG_FUNCTION void | |
2985 | verify_rtl_sharing (void) | |
2986 | { | |
dc01c3d1 | 2987 | rtx_insn *p; |
a24243a0 AK |
2988 | |
2989 | timevar_push (TV_VERIFY_RTL_SHARING); | |
2990 | ||
2991 | reset_all_used_flags (); | |
2c07f13b JH |
2992 | |
2993 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2994 | if (INSN_P (p)) | |
2995 | { | |
0e0f87d4 SB |
2996 | rtx pat = PATTERN (p); |
2997 | if (GET_CODE (pat) != SEQUENCE) | |
2998 | verify_insn_sharing (p); | |
2999 | else | |
3000 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
748e88da JDA |
3001 | { |
3002 | rtx insn = XVECEXP (pat, 0, i); | |
3003 | if (INSN_P (insn)) | |
3004 | verify_insn_sharing (insn); | |
3005 | } | |
2c07f13b | 3006 | } |
a222c01a | 3007 | |
a24243a0 AK |
3008 | reset_all_used_flags (); |
3009 | ||
a222c01a | 3010 | timevar_pop (TV_VERIFY_RTL_SHARING); |
2c07f13b JH |
3011 | } |
3012 | ||
d1b81779 GK |
3013 | /* Go through all the RTL insn bodies and copy any invalid shared structure. |
3014 | Assumes the mark bits are cleared at entry. */ | |
3015 | ||
2c07f13b | 3016 | void |
dc01c3d1 | 3017 | unshare_all_rtl_in_chain (rtx_insn *insn) |
d1b81779 GK |
3018 | { |
3019 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 3020 | if (INSN_P (insn)) |
d1b81779 GK |
3021 | { |
3022 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
3023 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
776bebcd JJ |
3024 | if (CALL_P (insn)) |
3025 | CALL_INSN_FUNCTION_USAGE (insn) | |
3026 | = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn)); | |
d1b81779 GK |
3027 | } |
3028 | } | |
3029 | ||
2d4aecb3 | 3030 | /* Go through all virtual stack slots of a function and mark them as |
5eb2a9f2 RS |
3031 | shared. We never replace the DECL_RTLs themselves with a copy, |
3032 | but expressions mentioned into a DECL_RTL cannot be shared with | |
3033 | expressions in the instruction stream. | |
3034 | ||
3035 | Note that reload may convert pseudo registers into memories in-place. | |
3036 | Pseudo registers are always shared, but MEMs never are. Thus if we | |
3037 | reset the used flags on MEMs in the instruction stream, we must set | |
3038 | them again on MEMs that appear in DECL_RTLs. */ | |
3039 | ||
2d4aecb3 | 3040 | static void |
5eb2a9f2 | 3041 | set_used_decls (tree blk) |
2d4aecb3 AO |
3042 | { |
3043 | tree t; | |
3044 | ||
3045 | /* Mark decls. */ | |
910ad8de | 3046 | for (t = BLOCK_VARS (blk); t; t = DECL_CHAIN (t)) |
19e7881c | 3047 | if (DECL_RTL_SET_P (t)) |
5eb2a9f2 | 3048 | set_used_flags (DECL_RTL (t)); |
2d4aecb3 AO |
3049 | |
3050 | /* Now process sub-blocks. */ | |
87caf699 | 3051 | for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t)) |
5eb2a9f2 | 3052 | set_used_decls (t); |
2d4aecb3 AO |
3053 | } |
3054 | ||
23b2ce53 | 3055 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
ff954f39 AP |
3056 | Recursively does the same for subexpressions. Uses |
3057 | copy_rtx_if_shared_1 to reduce stack space. */ | |
23b2ce53 RS |
3058 | |
3059 | rtx | |
502b8322 | 3060 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 3061 | { |
32b32b16 AP |
3062 | copy_rtx_if_shared_1 (&orig); |
3063 | return orig; | |
3064 | } | |
3065 | ||
ff954f39 AP |
3066 | /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in |
3067 | use. Recursively does the same for subexpressions. */ | |
3068 | ||
32b32b16 AP |
3069 | static void |
3070 | copy_rtx_if_shared_1 (rtx *orig1) | |
3071 | { | |
3072 | rtx x; | |
b3694847 SS |
3073 | int i; |
3074 | enum rtx_code code; | |
32b32b16 | 3075 | rtx *last_ptr; |
b3694847 | 3076 | const char *format_ptr; |
23b2ce53 | 3077 | int copied = 0; |
32b32b16 AP |
3078 | int length; |
3079 | ||
3080 | /* Repeat is used to turn tail-recursion into iteration. */ | |
3081 | repeat: | |
3082 | x = *orig1; | |
23b2ce53 RS |
3083 | |
3084 | if (x == 0) | |
32b32b16 | 3085 | return; |
23b2ce53 RS |
3086 | |
3087 | code = GET_CODE (x); | |
3088 | ||
3089 | /* These types may be freely shared. */ | |
3090 | ||
3091 | switch (code) | |
3092 | { | |
3093 | case REG: | |
0ca5af51 AO |
3094 | case DEBUG_EXPR: |
3095 | case VALUE: | |
d8116890 | 3096 | CASE_CONST_ANY: |
23b2ce53 | 3097 | case SYMBOL_REF: |
2c07f13b | 3098 | case LABEL_REF: |
23b2ce53 RS |
3099 | case CODE_LABEL: |
3100 | case PC: | |
276e0224 | 3101 | case RETURN: |
26898771 | 3102 | case SIMPLE_RETURN: |
23b2ce53 | 3103 | case SCRATCH: |
0f41302f | 3104 | /* SCRATCH must be shared because they represent distinct values. */ |
32b32b16 | 3105 | return; |
3e89ed8d | 3106 | case CLOBBER: |
bd1cd0d0 | 3107 | /* Share clobbers of hard registers, but do not share pseudo reg |
c5c5ba89 JH |
3108 | clobbers or clobbers of hard registers that originated as pseudos. |
3109 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
3110 | if (REG_P (XEXP (x, 0)) |
3111 | && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0))) | |
3112 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0)))) | |
3e89ed8d JH |
3113 | return; |
3114 | break; | |
23b2ce53 | 3115 | |
b851ea09 | 3116 | case CONST: |
6fb5fa3c | 3117 | if (shared_const_p (x)) |
32b32b16 | 3118 | return; |
b851ea09 RK |
3119 | break; |
3120 | ||
b5b8b0ac | 3121 | case DEBUG_INSN: |
23b2ce53 RS |
3122 | case INSN: |
3123 | case JUMP_INSN: | |
3124 | case CALL_INSN: | |
3125 | case NOTE: | |
23b2ce53 RS |
3126 | case BARRIER: |
3127 | /* The chain of insns is not being copied. */ | |
32b32b16 | 3128 | return; |
23b2ce53 | 3129 | |
e9a25f70 JL |
3130 | default: |
3131 | break; | |
23b2ce53 RS |
3132 | } |
3133 | ||
3134 | /* This rtx may not be shared. If it has already been seen, | |
3135 | replace it with a copy of itself. */ | |
3136 | ||
2adc7f12 | 3137 | if (RTX_FLAG (x, used)) |
23b2ce53 | 3138 | { |
aacd3885 | 3139 | x = shallow_copy_rtx (x); |
23b2ce53 RS |
3140 | copied = 1; |
3141 | } | |
2adc7f12 | 3142 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
3143 | |
3144 | /* Now scan the subexpressions recursively. | |
3145 | We can store any replaced subexpressions directly into X | |
3146 | since we know X is not shared! Any vectors in X | |
3147 | must be copied if X was copied. */ | |
3148 | ||
3149 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 AP |
3150 | length = GET_RTX_LENGTH (code); |
3151 | last_ptr = NULL; | |
b8698a0f | 3152 | |
32b32b16 | 3153 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3154 | { |
3155 | switch (*format_ptr++) | |
3156 | { | |
3157 | case 'e': | |
32b32b16 AP |
3158 | if (last_ptr) |
3159 | copy_rtx_if_shared_1 (last_ptr); | |
3160 | last_ptr = &XEXP (x, i); | |
23b2ce53 RS |
3161 | break; |
3162 | ||
3163 | case 'E': | |
3164 | if (XVEC (x, i) != NULL) | |
3165 | { | |
b3694847 | 3166 | int j; |
f0722107 | 3167 | int len = XVECLEN (x, i); |
b8698a0f | 3168 | |
6614fd40 KH |
3169 | /* Copy the vector iff I copied the rtx and the length |
3170 | is nonzero. */ | |
f0722107 | 3171 | if (copied && len > 0) |
8f985ec4 | 3172 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
b8698a0f | 3173 | |
5d3cc252 | 3174 | /* Call recursively on all inside the vector. */ |
f0722107 | 3175 | for (j = 0; j < len; j++) |
32b32b16 AP |
3176 | { |
3177 | if (last_ptr) | |
3178 | copy_rtx_if_shared_1 (last_ptr); | |
3179 | last_ptr = &XVECEXP (x, i, j); | |
3180 | } | |
23b2ce53 RS |
3181 | } |
3182 | break; | |
3183 | } | |
3184 | } | |
32b32b16 AP |
3185 | *orig1 = x; |
3186 | if (last_ptr) | |
3187 | { | |
3188 | orig1 = last_ptr; | |
3189 | goto repeat; | |
3190 | } | |
3191 | return; | |
23b2ce53 RS |
3192 | } |
3193 | ||
76369a82 | 3194 | /* Set the USED bit in X and its non-shareable subparts to FLAG. */ |
23b2ce53 | 3195 | |
76369a82 NF |
3196 | static void |
3197 | mark_used_flags (rtx x, int flag) | |
23b2ce53 | 3198 | { |
b3694847 SS |
3199 | int i, j; |
3200 | enum rtx_code code; | |
3201 | const char *format_ptr; | |
32b32b16 | 3202 | int length; |
23b2ce53 | 3203 | |
32b32b16 AP |
3204 | /* Repeat is used to turn tail-recursion into iteration. */ |
3205 | repeat: | |
23b2ce53 RS |
3206 | if (x == 0) |
3207 | return; | |
3208 | ||
3209 | code = GET_CODE (x); | |
3210 | ||
9faa82d8 | 3211 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
3212 | for them. */ |
3213 | ||
3214 | switch (code) | |
3215 | { | |
3216 | case REG: | |
0ca5af51 AO |
3217 | case DEBUG_EXPR: |
3218 | case VALUE: | |
d8116890 | 3219 | CASE_CONST_ANY: |
23b2ce53 RS |
3220 | case SYMBOL_REF: |
3221 | case CODE_LABEL: | |
3222 | case PC: | |
276e0224 | 3223 | case RETURN: |
26898771 | 3224 | case SIMPLE_RETURN: |
23b2ce53 RS |
3225 | return; |
3226 | ||
b5b8b0ac | 3227 | case DEBUG_INSN: |
23b2ce53 RS |
3228 | case INSN: |
3229 | case JUMP_INSN: | |
3230 | case CALL_INSN: | |
3231 | case NOTE: | |
3232 | case LABEL_REF: | |
3233 | case BARRIER: | |
3234 | /* The chain of insns is not being copied. */ | |
3235 | return; | |
750c9258 | 3236 | |
e9a25f70 JL |
3237 | default: |
3238 | break; | |
23b2ce53 RS |
3239 | } |
3240 | ||
76369a82 | 3241 | RTX_FLAG (x, used) = flag; |
23b2ce53 RS |
3242 | |
3243 | format_ptr = GET_RTX_FORMAT (code); | |
32b32b16 | 3244 | length = GET_RTX_LENGTH (code); |
b8698a0f | 3245 | |
32b32b16 | 3246 | for (i = 0; i < length; i++) |
23b2ce53 RS |
3247 | { |
3248 | switch (*format_ptr++) | |
3249 | { | |
3250 | case 'e': | |
32b32b16 AP |
3251 | if (i == length-1) |
3252 | { | |
3253 | x = XEXP (x, i); | |
3254 | goto repeat; | |
3255 | } | |
76369a82 | 3256 | mark_used_flags (XEXP (x, i), flag); |
23b2ce53 RS |
3257 | break; |
3258 | ||
3259 | case 'E': | |
3260 | for (j = 0; j < XVECLEN (x, i); j++) | |
76369a82 | 3261 | mark_used_flags (XVECEXP (x, i, j), flag); |
23b2ce53 RS |
3262 | break; |
3263 | } | |
3264 | } | |
3265 | } | |
2c07f13b | 3266 | |
76369a82 | 3267 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used |
2c07f13b JH |
3268 | to look for shared sub-parts. */ |
3269 | ||
3270 | void | |
76369a82 | 3271 | reset_used_flags (rtx x) |
2c07f13b | 3272 | { |
76369a82 NF |
3273 | mark_used_flags (x, 0); |
3274 | } | |
2c07f13b | 3275 | |
76369a82 NF |
3276 | /* Set all the USED bits in X to allow copy_rtx_if_shared to be used |
3277 | to look for shared sub-parts. */ | |
2c07f13b | 3278 | |
76369a82 NF |
3279 | void |
3280 | set_used_flags (rtx x) | |
3281 | { | |
3282 | mark_used_flags (x, 1); | |
2c07f13b | 3283 | } |
23b2ce53 RS |
3284 | \f |
3285 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
3286 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
3287 | OTHER must be valid as a SET_DEST. */ | |
3288 | ||
3289 | rtx | |
502b8322 | 3290 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
3291 | { |
3292 | while (1) | |
3293 | switch (GET_CODE (other)) | |
3294 | { | |
3295 | case SUBREG: | |
3296 | other = SUBREG_REG (other); | |
3297 | break; | |
3298 | case STRICT_LOW_PART: | |
3299 | case SIGN_EXTEND: | |
3300 | case ZERO_EXTEND: | |
3301 | other = XEXP (other, 0); | |
3302 | break; | |
3303 | default: | |
3304 | goto done; | |
3305 | } | |
3306 | done: | |
3c0cb5de | 3307 | if ((MEM_P (other) |
23b2ce53 | 3308 | && ! CONSTANT_P (x) |
f8cfc6aa | 3309 | && !REG_P (x) |
23b2ce53 | 3310 | && GET_CODE (x) != SUBREG) |
f8cfc6aa | 3311 | || (REG_P (other) |
23b2ce53 RS |
3312 | && (REGNO (other) < FIRST_PSEUDO_REGISTER |
3313 | || reg_mentioned_p (other, x)))) | |
3314 | { | |
3315 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
3316 | emit_move_insn (temp, x); | |
3317 | return temp; | |
3318 | } | |
3319 | return x; | |
3320 | } | |
3321 | \f | |
3322 | /* Emission of insns (adding them to the doubly-linked list). */ | |
3323 | ||
23b2ce53 RS |
3324 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ |
3325 | ||
db76cf1e | 3326 | rtx_insn * |
502b8322 | 3327 | get_last_insn_anywhere (void) |
23b2ce53 | 3328 | { |
614d5bd8 AM |
3329 | struct sequence_stack *seq; |
3330 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
3331 | if (seq->last != 0) | |
3332 | return seq->last; | |
23b2ce53 RS |
3333 | return 0; |
3334 | } | |
3335 | ||
2a496e8b JDA |
3336 | /* Return the first nonnote insn emitted in current sequence or current |
3337 | function. This routine looks inside SEQUENCEs. */ | |
3338 | ||
e4685bc8 | 3339 | rtx_insn * |
502b8322 | 3340 | get_first_nonnote_insn (void) |
2a496e8b | 3341 | { |
dc01c3d1 | 3342 | rtx_insn *insn = get_insns (); |
91373fe8 JDA |
3343 | |
3344 | if (insn) | |
3345 | { | |
3346 | if (NOTE_P (insn)) | |
3347 | for (insn = next_insn (insn); | |
3348 | insn && NOTE_P (insn); | |
3349 | insn = next_insn (insn)) | |
3350 | continue; | |
3351 | else | |
3352 | { | |
2ca202e7 | 3353 | if (NONJUMP_INSN_P (insn) |
91373fe8 | 3354 | && GET_CODE (PATTERN (insn)) == SEQUENCE) |
dc01c3d1 | 3355 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
91373fe8 JDA |
3356 | } |
3357 | } | |
2a496e8b JDA |
3358 | |
3359 | return insn; | |
3360 | } | |
3361 | ||
3362 | /* Return the last nonnote insn emitted in current sequence or current | |
3363 | function. This routine looks inside SEQUENCEs. */ | |
3364 | ||
e4685bc8 | 3365 | rtx_insn * |
502b8322 | 3366 | get_last_nonnote_insn (void) |
2a496e8b | 3367 | { |
dc01c3d1 | 3368 | rtx_insn *insn = get_last_insn (); |
91373fe8 JDA |
3369 | |
3370 | if (insn) | |
3371 | { | |
3372 | if (NOTE_P (insn)) | |
3373 | for (insn = previous_insn (insn); | |
3374 | insn && NOTE_P (insn); | |
3375 | insn = previous_insn (insn)) | |
3376 | continue; | |
3377 | else | |
3378 | { | |
dc01c3d1 DM |
3379 | if (NONJUMP_INSN_P (insn)) |
3380 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3381 | insn = seq->insn (seq->len () - 1); | |
91373fe8 JDA |
3382 | } |
3383 | } | |
2a496e8b JDA |
3384 | |
3385 | return insn; | |
3386 | } | |
3387 | ||
b5b8b0ac AO |
3388 | /* Return the number of actual (non-debug) insns emitted in this |
3389 | function. */ | |
3390 | ||
3391 | int | |
3392 | get_max_insn_count (void) | |
3393 | { | |
3394 | int n = cur_insn_uid; | |
3395 | ||
3396 | /* The table size must be stable across -g, to avoid codegen | |
3397 | differences due to debug insns, and not be affected by | |
3398 | -fmin-insn-uid, to avoid excessive table size and to simplify | |
3399 | debugging of -fcompare-debug failures. */ | |
028d4092 | 3400 | if (cur_debug_insn_uid > param_min_nondebug_insn_uid) |
b5b8b0ac AO |
3401 | n -= cur_debug_insn_uid; |
3402 | else | |
028d4092 | 3403 | n -= param_min_nondebug_insn_uid; |
b5b8b0ac AO |
3404 | |
3405 | return n; | |
3406 | } | |
3407 | ||
23b2ce53 RS |
3408 | \f |
3409 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
3410 | of the sequence. */ | |
3411 | ||
eb51c837 | 3412 | rtx_insn * |
4ce524a1 | 3413 | next_insn (rtx_insn *insn) |
23b2ce53 | 3414 | { |
75547801 KG |
3415 | if (insn) |
3416 | { | |
3417 | insn = NEXT_INSN (insn); | |
3418 | if (insn && NONJUMP_INSN_P (insn) | |
3419 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
dc01c3d1 | 3420 | insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0); |
75547801 | 3421 | } |
23b2ce53 | 3422 | |
dc01c3d1 | 3423 | return insn; |
23b2ce53 RS |
3424 | } |
3425 | ||
3426 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
3427 | of the sequence. */ | |
3428 | ||
eb51c837 | 3429 | rtx_insn * |
4ce524a1 | 3430 | previous_insn (rtx_insn *insn) |
23b2ce53 | 3431 | { |
75547801 KG |
3432 | if (insn) |
3433 | { | |
3434 | insn = PREV_INSN (insn); | |
dc01c3d1 DM |
3435 | if (insn && NONJUMP_INSN_P (insn)) |
3436 | if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) | |
3437 | insn = seq->insn (seq->len () - 1); | |
75547801 | 3438 | } |
23b2ce53 | 3439 | |
dc01c3d1 | 3440 | return insn; |
23b2ce53 RS |
3441 | } |
3442 | ||
3443 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3444 | look inside SEQUENCEs. */ | |
3445 | ||
eb51c837 | 3446 | rtx_insn * |
c9b0a227 | 3447 | next_nonnote_insn (rtx_insn *insn) |
23b2ce53 | 3448 | { |
75547801 KG |
3449 | while (insn) |
3450 | { | |
3451 | insn = NEXT_INSN (insn); | |
3452 | if (insn == 0 || !NOTE_P (insn)) | |
3453 | break; | |
3454 | } | |
23b2ce53 | 3455 | |
dc01c3d1 | 3456 | return insn; |
23b2ce53 RS |
3457 | } |
3458 | ||
f40dd646 AO |
3459 | /* Return the next insn after INSN that is not a DEBUG_INSN. This |
3460 | routine does not look inside SEQUENCEs. */ | |
1e211590 | 3461 | |
eb51c837 | 3462 | rtx_insn * |
f40dd646 | 3463 | next_nondebug_insn (rtx_insn *insn) |
1e211590 DD |
3464 | { |
3465 | while (insn) | |
3466 | { | |
3467 | insn = NEXT_INSN (insn); | |
f40dd646 | 3468 | if (insn == 0 || !DEBUG_INSN_P (insn)) |
1e211590 | 3469 | break; |
1e211590 DD |
3470 | } |
3471 | ||
dc01c3d1 | 3472 | return insn; |
1e211590 DD |
3473 | } |
3474 | ||
23b2ce53 RS |
3475 | /* Return the previous insn before INSN that is not a NOTE. This routine does |
3476 | not look inside SEQUENCEs. */ | |
3477 | ||
eb51c837 | 3478 | rtx_insn * |
c9b0a227 | 3479 | prev_nonnote_insn (rtx_insn *insn) |
23b2ce53 | 3480 | { |
75547801 KG |
3481 | while (insn) |
3482 | { | |
3483 | insn = PREV_INSN (insn); | |
3484 | if (insn == 0 || !NOTE_P (insn)) | |
3485 | break; | |
3486 | } | |
23b2ce53 | 3487 | |
dc01c3d1 | 3488 | return insn; |
23b2ce53 RS |
3489 | } |
3490 | ||
f40dd646 AO |
3491 | /* Return the previous insn before INSN that is not a DEBUG_INSN. |
3492 | This routine does not look inside SEQUENCEs. */ | |
896aa4ea | 3493 | |
eb51c837 | 3494 | rtx_insn * |
f40dd646 | 3495 | prev_nondebug_insn (rtx_insn *insn) |
896aa4ea DD |
3496 | { |
3497 | while (insn) | |
3498 | { | |
3499 | insn = PREV_INSN (insn); | |
f40dd646 | 3500 | if (insn == 0 || !DEBUG_INSN_P (insn)) |
896aa4ea | 3501 | break; |
896aa4ea DD |
3502 | } |
3503 | ||
dc01c3d1 | 3504 | return insn; |
896aa4ea DD |
3505 | } |
3506 | ||
f40dd646 AO |
3507 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN. |
3508 | This routine does not look inside SEQUENCEs. */ | |
b5b8b0ac | 3509 | |
eb51c837 | 3510 | rtx_insn * |
f40dd646 | 3511 | next_nonnote_nondebug_insn (rtx_insn *insn) |
b5b8b0ac AO |
3512 | { |
3513 | while (insn) | |
3514 | { | |
3515 | insn = NEXT_INSN (insn); | |
f40dd646 | 3516 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) |
b5b8b0ac AO |
3517 | break; |
3518 | } | |
3519 | ||
dc01c3d1 | 3520 | return insn; |
b5b8b0ac AO |
3521 | } |
3522 | ||
f40dd646 AO |
3523 | /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN, |
3524 | but stop the search before we enter another basic block. This | |
3525 | routine does not look inside SEQUENCEs. */ | |
b5b8b0ac | 3526 | |
eb51c837 | 3527 | rtx_insn * |
f40dd646 | 3528 | next_nonnote_nondebug_insn_bb (rtx_insn *insn) |
b5b8b0ac AO |
3529 | { |
3530 | while (insn) | |
3531 | { | |
f40dd646 AO |
3532 | insn = NEXT_INSN (insn); |
3533 | if (insn == 0) | |
3534 | break; | |
3535 | if (DEBUG_INSN_P (insn)) | |
3536 | continue; | |
3537 | if (!NOTE_P (insn)) | |
b5b8b0ac | 3538 | break; |
f40dd646 AO |
3539 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
3540 | return NULL; | |
b5b8b0ac AO |
3541 | } |
3542 | ||
dc01c3d1 | 3543 | return insn; |
b5b8b0ac AO |
3544 | } |
3545 | ||
f40dd646 | 3546 | /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN. |
f0fc0803 JJ |
3547 | This routine does not look inside SEQUENCEs. */ |
3548 | ||
eb51c837 | 3549 | rtx_insn * |
f40dd646 | 3550 | prev_nonnote_nondebug_insn (rtx_insn *insn) |
f0fc0803 JJ |
3551 | { |
3552 | while (insn) | |
3553 | { | |
f40dd646 | 3554 | insn = PREV_INSN (insn); |
f0fc0803 JJ |
3555 | if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn))) |
3556 | break; | |
3557 | } | |
3558 | ||
dc01c3d1 | 3559 | return insn; |
f0fc0803 JJ |
3560 | } |
3561 | ||
f40dd646 AO |
3562 | /* Return the previous insn before INSN that is not a NOTE nor |
3563 | DEBUG_INSN, but stop the search before we enter another basic | |
3564 | block. This routine does not look inside SEQUENCEs. */ | |
f0fc0803 | 3565 | |
eb51c837 | 3566 | rtx_insn * |
f40dd646 | 3567 | prev_nonnote_nondebug_insn_bb (rtx_insn *insn) |
f0fc0803 JJ |
3568 | { |
3569 | while (insn) | |
3570 | { | |
3571 | insn = PREV_INSN (insn); | |
f40dd646 | 3572 | if (insn == 0) |
f0fc0803 | 3573 | break; |
f40dd646 AO |
3574 | if (DEBUG_INSN_P (insn)) |
3575 | continue; | |
3576 | if (!NOTE_P (insn)) | |
3577 | break; | |
3578 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) | |
3579 | return NULL; | |
f0fc0803 JJ |
3580 | } |
3581 | ||
dc01c3d1 | 3582 | return insn; |
f0fc0803 JJ |
3583 | } |
3584 | ||
ec2d7121 | 3585 | /* Return the next INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN after INSN; |
23b2ce53 | 3586 | or 0, if there is none. This routine does not look inside |
0f41302f | 3587 | SEQUENCEs. */ |
23b2ce53 | 3588 | |
eb51c837 | 3589 | rtx_insn * |
4dea3bff | 3590 | next_real_insn (rtx_insn *insn) |
23b2ce53 | 3591 | { |
75547801 KG |
3592 | while (insn) |
3593 | { | |
3594 | insn = NEXT_INSN (insn); | |
3595 | if (insn == 0 || INSN_P (insn)) | |
3596 | break; | |
3597 | } | |
23b2ce53 | 3598 | |
dc01c3d1 | 3599 | return insn; |
23b2ce53 RS |
3600 | } |
3601 | ||
ec2d7121 | 3602 | /* Return the last INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN before INSN; |
23b2ce53 RS |
3603 | or 0, if there is none. This routine does not look inside |
3604 | SEQUENCEs. */ | |
3605 | ||
eb51c837 | 3606 | rtx_insn * |
d8fd56b2 | 3607 | prev_real_insn (rtx_insn *insn) |
23b2ce53 | 3608 | { |
75547801 KG |
3609 | while (insn) |
3610 | { | |
3611 | insn = PREV_INSN (insn); | |
3612 | if (insn == 0 || INSN_P (insn)) | |
3613 | break; | |
3614 | } | |
23b2ce53 | 3615 | |
dc01c3d1 | 3616 | return insn; |
23b2ce53 RS |
3617 | } |
3618 | ||
ec2d7121 JJ |
3619 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; |
3620 | or 0, if there is none. This routine does not look inside | |
3621 | SEQUENCEs. */ | |
3622 | ||
3623 | rtx_insn * | |
3624 | next_real_nondebug_insn (rtx uncast_insn) | |
3625 | { | |
3626 | rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn); | |
3627 | ||
3628 | while (insn) | |
3629 | { | |
3630 | insn = NEXT_INSN (insn); | |
3631 | if (insn == 0 || NONDEBUG_INSN_P (insn)) | |
3632 | break; | |
3633 | } | |
3634 | ||
3635 | return insn; | |
3636 | } | |
3637 | ||
3638 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3639 | or 0, if there is none. This routine does not look inside | |
3640 | SEQUENCEs. */ | |
3641 | ||
3642 | rtx_insn * | |
3643 | prev_real_nondebug_insn (rtx_insn *insn) | |
3644 | { | |
3645 | while (insn) | |
3646 | { | |
3647 | insn = PREV_INSN (insn); | |
3648 | if (insn == 0 || NONDEBUG_INSN_P (insn)) | |
3649 | break; | |
3650 | } | |
3651 | ||
3652 | return insn; | |
3653 | } | |
3654 | ||
ee960939 OH |
3655 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3656 | This routine does not look inside SEQUENCEs. */ | |
3657 | ||
049cfc4a | 3658 | rtx_call_insn * |
502b8322 | 3659 | last_call_insn (void) |
ee960939 | 3660 | { |
049cfc4a | 3661 | rtx_insn *insn; |
ee960939 OH |
3662 | |
3663 | for (insn = get_last_insn (); | |
4b4bf941 | 3664 | insn && !CALL_P (insn); |
ee960939 OH |
3665 | insn = PREV_INSN (insn)) |
3666 | ; | |
3667 | ||
049cfc4a | 3668 | return safe_as_a <rtx_call_insn *> (insn); |
ee960939 OH |
3669 | } |
3670 | ||
23b2ce53 | 3671 | /* Find the next insn after INSN that really does something. This routine |
9c517bf3 AK |
3672 | does not look inside SEQUENCEs. After reload this also skips over |
3673 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3674 | |
69732dcb | 3675 | int |
7c9796ed | 3676 | active_insn_p (const rtx_insn *insn) |
69732dcb | 3677 | { |
4b4bf941 | 3678 | return (CALL_P (insn) || JUMP_P (insn) |
39718607 | 3679 | || JUMP_TABLE_DATA_P (insn) /* FIXME */ |
4b4bf941 | 3680 | || (NONJUMP_INSN_P (insn) |
23b8ba81 RH |
3681 | && (! reload_completed |
3682 | || (GET_CODE (PATTERN (insn)) != USE | |
3683 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3684 | } |
3685 | ||
eb51c837 | 3686 | rtx_insn * |
7c9796ed | 3687 | next_active_insn (rtx_insn *insn) |
23b2ce53 | 3688 | { |
75547801 KG |
3689 | while (insn) |
3690 | { | |
3691 | insn = NEXT_INSN (insn); | |
3692 | if (insn == 0 || active_insn_p (insn)) | |
3693 | break; | |
3694 | } | |
23b2ce53 | 3695 | |
dc01c3d1 | 3696 | return insn; |
23b2ce53 RS |
3697 | } |
3698 | ||
3699 | /* Find the last insn before INSN that really does something. This routine | |
9c517bf3 AK |
3700 | does not look inside SEQUENCEs. After reload this also skips over |
3701 | standalone USE and CLOBBER insn. */ | |
23b2ce53 | 3702 | |
eb51c837 | 3703 | rtx_insn * |
7c9796ed | 3704 | prev_active_insn (rtx_insn *insn) |
23b2ce53 | 3705 | { |
75547801 KG |
3706 | while (insn) |
3707 | { | |
3708 | insn = PREV_INSN (insn); | |
3709 | if (insn == 0 || active_insn_p (insn)) | |
3710 | break; | |
3711 | } | |
23b2ce53 | 3712 | |
dc01c3d1 | 3713 | return insn; |
23b2ce53 | 3714 | } |
23b2ce53 | 3715 | \f |
594f8779 RZ |
3716 | /* Find a RTX_AUTOINC class rtx which matches DATA. */ |
3717 | ||
3718 | static int | |
9021b8ec | 3719 | find_auto_inc (const_rtx x, const_rtx reg) |
594f8779 | 3720 | { |
9021b8ec RS |
3721 | subrtx_iterator::array_type array; |
3722 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
594f8779 | 3723 | { |
9021b8ec RS |
3724 | const_rtx x = *iter; |
3725 | if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC | |
3726 | && rtx_equal_p (reg, XEXP (x, 0))) | |
3727 | return true; | |
594f8779 | 3728 | } |
9021b8ec | 3729 | return false; |
594f8779 | 3730 | } |
594f8779 | 3731 | |
e5bef2e4 HB |
3732 | /* Increment the label uses for all labels present in rtx. */ |
3733 | ||
3734 | static void | |
502b8322 | 3735 | mark_label_nuses (rtx x) |
e5bef2e4 | 3736 | { |
b3694847 SS |
3737 | enum rtx_code code; |
3738 | int i, j; | |
3739 | const char *fmt; | |
e5bef2e4 HB |
3740 | |
3741 | code = GET_CODE (x); | |
04a121a7 TS |
3742 | if (code == LABEL_REF && LABEL_P (label_ref_label (x))) |
3743 | LABEL_NUSES (label_ref_label (x))++; | |
e5bef2e4 HB |
3744 | |
3745 | fmt = GET_RTX_FORMAT (code); | |
3746 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3747 | { | |
3748 | if (fmt[i] == 'e') | |
0fb7aeda | 3749 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3750 | else if (fmt[i] == 'E') |
0fb7aeda | 3751 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3752 | mark_label_nuses (XVECEXP (x, i, j)); |
3753 | } | |
3754 | } | |
3755 | ||
23b2ce53 RS |
3756 | \f |
3757 | /* Try splitting insns that can be split for better scheduling. | |
3758 | PAT is the pattern which might split. | |
3759 | TRIAL is the insn providing PAT. | |
cc2902df | 3760 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3761 | |
3762 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3763 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3764 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3765 | ||
53f04688 | 3766 | rtx_insn * |
bb5c4956 | 3767 | try_split (rtx pat, rtx_insn *trial, int last) |
23b2ce53 | 3768 | { |
d4eff95b | 3769 | rtx_insn *before, *after; |
dc01c3d1 DM |
3770 | rtx note; |
3771 | rtx_insn *seq, *tem; | |
5fa396ad | 3772 | profile_probability probability; |
dc01c3d1 | 3773 | rtx_insn *insn_last, *insn; |
599aedd9 | 3774 | int njumps = 0; |
e67d1102 | 3775 | rtx_insn *call_insn = NULL; |
6b24c259 JH |
3776 | |
3777 | if (any_condjump_p (trial) | |
3778 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
5fa396ad JH |
3779 | split_branch_probability |
3780 | = profile_probability::from_reg_br_prob_note (XINT (note, 0)); | |
3781 | else | |
3782 | split_branch_probability = profile_probability::uninitialized (); | |
3783 | ||
6b24c259 JH |
3784 | probability = split_branch_probability; |
3785 | ||
bb5c4956 | 3786 | seq = split_insns (pat, trial); |
6b24c259 | 3787 | |
5fa396ad | 3788 | split_branch_probability = profile_probability::uninitialized (); |
23b2ce53 | 3789 | |
599aedd9 | 3790 | if (!seq) |
dc01c3d1 | 3791 | return trial; |
599aedd9 | 3792 | |
e7d55c6b | 3793 | int split_insn_count = 0; |
599aedd9 RH |
3794 | /* Avoid infinite loop if any insn of the result matches |
3795 | the original pattern. */ | |
3796 | insn_last = seq; | |
3797 | while (1) | |
23b2ce53 | 3798 | { |
599aedd9 RH |
3799 | if (INSN_P (insn_last) |
3800 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
dc01c3d1 | 3801 | return trial; |
e7d55c6b | 3802 | split_insn_count++; |
599aedd9 RH |
3803 | if (!NEXT_INSN (insn_last)) |
3804 | break; | |
3805 | insn_last = NEXT_INSN (insn_last); | |
3806 | } | |
750c9258 | 3807 | |
e7d55c6b SKS |
3808 | /* We're not good at redistributing frame information if |
3809 | the split occurs before reload or if it results in more | |
3810 | than one insn. */ | |
3811 | if (RTX_FRAME_RELATED_P (trial)) | |
3812 | { | |
3813 | if (!reload_completed || split_insn_count != 1) | |
3814 | return trial; | |
3815 | ||
3816 | rtx_insn *new_insn = seq; | |
3817 | rtx_insn *old_insn = trial; | |
3818 | copy_frame_info_to_split_insn (old_insn, new_insn); | |
3819 | } | |
3820 | ||
6fb5fa3c DB |
3821 | /* We will be adding the new sequence to the function. The splitters |
3822 | may have introduced invalid RTL sharing, so unshare the sequence now. */ | |
3823 | unshare_all_rtl_in_chain (seq); | |
3824 | ||
339ba33b | 3825 | /* Mark labels and copy flags. */ |
599aedd9 RH |
3826 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) |
3827 | { | |
4b4bf941 | 3828 | if (JUMP_P (insn)) |
599aedd9 | 3829 | { |
339ba33b RS |
3830 | if (JUMP_P (trial)) |
3831 | CROSSING_JUMP_P (insn) = CROSSING_JUMP_P (trial); | |
599aedd9 RH |
3832 | mark_jump_label (PATTERN (insn), insn, 0); |
3833 | njumps++; | |
5fa396ad | 3834 | if (probability.initialized_p () |
599aedd9 RH |
3835 | && any_condjump_p (insn) |
3836 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3837 | { |
599aedd9 RH |
3838 | /* We can preserve the REG_BR_PROB notes only if exactly |
3839 | one jump is created, otherwise the machine description | |
3840 | is responsible for this step using | |
3841 | split_branch_probability variable. */ | |
5b0264cb | 3842 | gcc_assert (njumps == 1); |
5fa396ad | 3843 | add_reg_br_prob_note (insn, probability); |
2f937369 | 3844 | } |
599aedd9 RH |
3845 | } |
3846 | } | |
3847 | ||
3848 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
65712d5c | 3849 | in SEQ and copy any additional information across. */ |
4b4bf941 | 3850 | if (CALL_P (trial)) |
599aedd9 RH |
3851 | { |
3852 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
4b4bf941 | 3853 | if (CALL_P (insn)) |
599aedd9 | 3854 | { |
4f660b15 RO |
3855 | gcc_assert (call_insn == NULL_RTX); |
3856 | call_insn = insn; | |
3857 | ||
65712d5c RS |
3858 | /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the |
3859 | target may have explicitly specified. */ | |
00b94487 | 3860 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
f6a1f3f6 RH |
3861 | while (*p) |
3862 | p = &XEXP (*p, 1); | |
3863 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
65712d5c RS |
3864 | |
3865 | /* If the old call was a sibling call, the new one must | |
3866 | be too. */ | |
599aedd9 RH |
3867 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3868 | } | |
3869 | } | |
4b5e8abe | 3870 | |
599aedd9 RH |
3871 | /* Copy notes, particularly those related to the CFG. */ |
3872 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3873 | { | |
3874 | switch (REG_NOTE_KIND (note)) | |
3875 | { | |
3876 | case REG_EH_REGION: | |
1d65f45c | 3877 | copy_reg_eh_region_note_backward (note, insn_last, NULL); |
599aedd9 | 3878 | break; |
216183ce | 3879 | |
599aedd9 RH |
3880 | case REG_NORETURN: |
3881 | case REG_SETJMP: | |
0a35513e | 3882 | case REG_TM: |
5c5f0b65 | 3883 | case REG_CALL_NOCF_CHECK: |
00b94487 | 3884 | case REG_CALL_ARG_LOCATION: |
594f8779 | 3885 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
216183ce | 3886 | { |
4b4bf941 | 3887 | if (CALL_P (insn)) |
65c5f2a6 | 3888 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
216183ce | 3889 | } |
599aedd9 | 3890 | break; |
d6e95df8 | 3891 | |
599aedd9 | 3892 | case REG_NON_LOCAL_GOTO: |
73f1289e | 3893 | case REG_LABEL_TARGET: |
594f8779 | 3894 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
2f937369 | 3895 | { |
4b4bf941 | 3896 | if (JUMP_P (insn)) |
65c5f2a6 | 3897 | add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); |
2f937369 | 3898 | } |
599aedd9 | 3899 | break; |
e5bef2e4 | 3900 | |
594f8779 | 3901 | case REG_INC: |
760edf20 TS |
3902 | if (!AUTO_INC_DEC) |
3903 | break; | |
3904 | ||
594f8779 RZ |
3905 | for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn)) |
3906 | { | |
3907 | rtx reg = XEXP (note, 0); | |
3908 | if (!FIND_REG_INC_NOTE (insn, reg) | |
9021b8ec | 3909 | && find_auto_inc (PATTERN (insn), reg)) |
65c5f2a6 | 3910 | add_reg_note (insn, REG_INC, reg); |
594f8779 RZ |
3911 | } |
3912 | break; | |
594f8779 | 3913 | |
9a08d230 | 3914 | case REG_ARGS_SIZE: |
68184180 | 3915 | fixup_args_size_notes (NULL, insn_last, get_args_size (note)); |
9a08d230 RH |
3916 | break; |
3917 | ||
4f660b15 | 3918 | case REG_CALL_DECL: |
49e65199 | 3919 | case REG_UNTYPED_CALL: |
4f660b15 RO |
3920 | gcc_assert (call_insn != NULL_RTX); |
3921 | add_reg_note (call_insn, REG_NOTE_KIND (note), XEXP (note, 0)); | |
3922 | break; | |
3923 | ||
599aedd9 RH |
3924 | default: |
3925 | break; | |
23b2ce53 | 3926 | } |
599aedd9 RH |
3927 | } |
3928 | ||
3929 | /* If there are LABELS inside the split insns increment the | |
3930 | usage count so we don't delete the label. */ | |
cf7c4aa6 | 3931 | if (INSN_P (trial)) |
599aedd9 RH |
3932 | { |
3933 | insn = insn_last; | |
3934 | while (insn != NULL_RTX) | |
23b2ce53 | 3935 | { |
cf7c4aa6 | 3936 | /* JUMP_P insns have already been "marked" above. */ |
4b4bf941 | 3937 | if (NONJUMP_INSN_P (insn)) |
599aedd9 | 3938 | mark_label_nuses (PATTERN (insn)); |
23b2ce53 | 3939 | |
599aedd9 RH |
3940 | insn = PREV_INSN (insn); |
3941 | } | |
23b2ce53 RS |
3942 | } |
3943 | ||
d4eff95b JC |
3944 | before = PREV_INSN (trial); |
3945 | after = NEXT_INSN (trial); | |
3946 | ||
45309d28 | 3947 | emit_insn_after_setloc (seq, trial, INSN_LOCATION (trial)); |
599aedd9 RH |
3948 | |
3949 | delete_insn (trial); | |
599aedd9 RH |
3950 | |
3951 | /* Recursively call try_split for each new insn created; by the | |
3952 | time control returns here that insn will be fully split, so | |
3953 | set LAST and continue from the insn after the one returned. | |
3954 | We can't use next_active_insn here since AFTER may be a note. | |
3955 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3956 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
4654c0cf | 3957 | if (! tem->deleted () && INSN_P (tem)) |
599aedd9 RH |
3958 | tem = try_split (PATTERN (tem), tem, 1); |
3959 | ||
3960 | /* Return either the first or the last insn, depending on which was | |
3961 | requested. */ | |
3962 | return last | |
5936d944 | 3963 | ? (after ? PREV_INSN (after) : get_last_insn ()) |
599aedd9 | 3964 | : NEXT_INSN (before); |
23b2ce53 RS |
3965 | } |
3966 | \f | |
3967 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3968 | Store PATTERN in the pattern slots. */ |
23b2ce53 | 3969 | |
167b9fae | 3970 | rtx_insn * |
502b8322 | 3971 | make_insn_raw (rtx pattern) |
23b2ce53 | 3972 | { |
167b9fae | 3973 | rtx_insn *insn; |
23b2ce53 | 3974 | |
167b9fae | 3975 | insn = as_a <rtx_insn *> (rtx_alloc (INSN)); |
23b2ce53 | 3976 | |
43127294 | 3977 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3978 | PATTERN (insn) = pattern; |
3979 | INSN_CODE (insn) = -1; | |
1632afca | 3980 | REG_NOTES (insn) = NULL; |
5368224f | 3981 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 3982 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3983 | |
47984720 NC |
3984 | #ifdef ENABLE_RTL_CHECKING |
3985 | if (insn | |
2c3c49de | 3986 | && INSN_P (insn) |
47984720 NC |
3987 | && (returnjump_p (insn) |
3988 | || (GET_CODE (insn) == SET | |
3989 | && SET_DEST (insn) == pc_rtx))) | |
3990 | { | |
d4ee4d25 | 3991 | warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n"); |
47984720 NC |
3992 | debug_rtx (insn); |
3993 | } | |
3994 | #endif | |
750c9258 | 3995 | |
23b2ce53 RS |
3996 | return insn; |
3997 | } | |
3998 | ||
b5b8b0ac AO |
3999 | /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */ |
4000 | ||
167b9fae | 4001 | static rtx_insn * |
b5b8b0ac AO |
4002 | make_debug_insn_raw (rtx pattern) |
4003 | { | |
167b9fae | 4004 | rtx_debug_insn *insn; |
b5b8b0ac | 4005 | |
167b9fae | 4006 | insn = as_a <rtx_debug_insn *> (rtx_alloc (DEBUG_INSN)); |
b5b8b0ac | 4007 | INSN_UID (insn) = cur_debug_insn_uid++; |
028d4092 | 4008 | if (cur_debug_insn_uid > param_min_nondebug_insn_uid) |
b5b8b0ac AO |
4009 | INSN_UID (insn) = cur_insn_uid++; |
4010 | ||
4011 | PATTERN (insn) = pattern; | |
4012 | INSN_CODE (insn) = -1; | |
4013 | REG_NOTES (insn) = NULL; | |
5368224f | 4014 | INSN_LOCATION (insn) = curr_insn_location (); |
b5b8b0ac AO |
4015 | BLOCK_FOR_INSN (insn) = NULL; |
4016 | ||
4017 | return insn; | |
4018 | } | |
4019 | ||
2f937369 | 4020 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 | 4021 | |
167b9fae | 4022 | static rtx_insn * |
502b8322 | 4023 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 4024 | { |
167b9fae | 4025 | rtx_jump_insn *insn; |
23b2ce53 | 4026 | |
167b9fae | 4027 | insn = as_a <rtx_jump_insn *> (rtx_alloc (JUMP_INSN)); |
1632afca | 4028 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
4029 | |
4030 | PATTERN (insn) = pattern; | |
4031 | INSN_CODE (insn) = -1; | |
1632afca RS |
4032 | REG_NOTES (insn) = NULL; |
4033 | JUMP_LABEL (insn) = NULL; | |
5368224f | 4034 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 4035 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
4036 | |
4037 | return insn; | |
4038 | } | |
aff507f4 | 4039 | |
2f937369 | 4040 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 | 4041 | |
167b9fae | 4042 | static rtx_insn * |
502b8322 | 4043 | make_call_insn_raw (rtx pattern) |
aff507f4 | 4044 | { |
167b9fae | 4045 | rtx_call_insn *insn; |
aff507f4 | 4046 | |
167b9fae | 4047 | insn = as_a <rtx_call_insn *> (rtx_alloc (CALL_INSN)); |
aff507f4 RK |
4048 | INSN_UID (insn) = cur_insn_uid++; |
4049 | ||
4050 | PATTERN (insn) = pattern; | |
4051 | INSN_CODE (insn) = -1; | |
aff507f4 RK |
4052 | REG_NOTES (insn) = NULL; |
4053 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
5368224f | 4054 | INSN_LOCATION (insn) = curr_insn_location (); |
ba4f7968 | 4055 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
4056 | |
4057 | return insn; | |
4058 | } | |
96fba521 SB |
4059 | |
4060 | /* Like `make_insn_raw' but make a NOTE instead of an insn. */ | |
4061 | ||
66e8df53 | 4062 | static rtx_note * |
96fba521 SB |
4063 | make_note_raw (enum insn_note subtype) |
4064 | { | |
4065 | /* Some notes are never created this way at all. These notes are | |
4066 | only created by patching out insns. */ | |
4067 | gcc_assert (subtype != NOTE_INSN_DELETED_LABEL | |
4068 | && subtype != NOTE_INSN_DELETED_DEBUG_LABEL); | |
4069 | ||
66e8df53 | 4070 | rtx_note *note = as_a <rtx_note *> (rtx_alloc (NOTE)); |
96fba521 SB |
4071 | INSN_UID (note) = cur_insn_uid++; |
4072 | NOTE_KIND (note) = subtype; | |
4073 | BLOCK_FOR_INSN (note) = NULL; | |
4074 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); | |
4075 | return note; | |
4076 | } | |
23b2ce53 | 4077 | \f |
96fba521 SB |
4078 | /* Add INSN to the end of the doubly-linked list, between PREV and NEXT. |
4079 | INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects, | |
4080 | but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */ | |
4081 | ||
4082 | static inline void | |
9152e0aa | 4083 | link_insn_into_chain (rtx_insn *insn, rtx_insn *prev, rtx_insn *next) |
96fba521 | 4084 | { |
0f82e5c9 DM |
4085 | SET_PREV_INSN (insn) = prev; |
4086 | SET_NEXT_INSN (insn) = next; | |
96fba521 SB |
4087 | if (prev != NULL) |
4088 | { | |
0f82e5c9 | 4089 | SET_NEXT_INSN (prev) = insn; |
96fba521 SB |
4090 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
4091 | { | |
e6eda746 DM |
4092 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4093 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = insn; | |
96fba521 SB |
4094 | } |
4095 | } | |
4096 | if (next != NULL) | |
4097 | { | |
0f82e5c9 | 4098 | SET_PREV_INSN (next) = insn; |
96fba521 | 4099 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4100 | { |
4101 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4102 | SET_PREV_INSN (sequence->insn (0)) = insn; | |
4103 | } | |
96fba521 | 4104 | } |
3ccb989e SB |
4105 | |
4106 | if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4107 | { | |
e6eda746 DM |
4108 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (insn)); |
4109 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4110 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
3ccb989e | 4111 | } |
96fba521 SB |
4112 | } |
4113 | ||
23b2ce53 RS |
4114 | /* Add INSN to the end of the doubly-linked list. |
4115 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
4116 | ||
4117 | void | |
9152e0aa | 4118 | add_insn (rtx_insn *insn) |
23b2ce53 | 4119 | { |
9152e0aa | 4120 | rtx_insn *prev = get_last_insn (); |
96fba521 | 4121 | link_insn_into_chain (insn, prev, NULL); |
01512446 | 4122 | if (get_insns () == NULL) |
5936d944 | 4123 | set_first_insn (insn); |
5936d944 | 4124 | set_last_insn (insn); |
23b2ce53 RS |
4125 | } |
4126 | ||
96fba521 | 4127 | /* Add INSN into the doubly-linked list after insn AFTER. */ |
23b2ce53 | 4128 | |
96fba521 | 4129 | static void |
9152e0aa | 4130 | add_insn_after_nobb (rtx_insn *insn, rtx_insn *after) |
23b2ce53 | 4131 | { |
9152e0aa | 4132 | rtx_insn *next = NEXT_INSN (after); |
23b2ce53 | 4133 | |
4654c0cf | 4134 | gcc_assert (!optimize || !after->deleted ()); |
ba213285 | 4135 | |
96fba521 | 4136 | link_insn_into_chain (insn, after, next); |
23b2ce53 | 4137 | |
96fba521 | 4138 | if (next == NULL) |
23b2ce53 | 4139 | { |
614d5bd8 AM |
4140 | struct sequence_stack *seq; |
4141 | ||
4142 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4143 | if (after == seq->last) | |
4144 | { | |
4145 | seq->last = insn; | |
4146 | break; | |
4147 | } | |
23b2ce53 | 4148 | } |
96fba521 SB |
4149 | } |
4150 | ||
4151 | /* Add INSN into the doubly-linked list before insn BEFORE. */ | |
4152 | ||
4153 | static void | |
9152e0aa | 4154 | add_insn_before_nobb (rtx_insn *insn, rtx_insn *before) |
96fba521 | 4155 | { |
9152e0aa | 4156 | rtx_insn *prev = PREV_INSN (before); |
96fba521 | 4157 | |
4654c0cf | 4158 | gcc_assert (!optimize || !before->deleted ()); |
96fba521 SB |
4159 | |
4160 | link_insn_into_chain (insn, prev, before); | |
4161 | ||
4162 | if (prev == NULL) | |
23b2ce53 | 4163 | { |
614d5bd8 | 4164 | struct sequence_stack *seq; |
a0ae8e8d | 4165 | |
614d5bd8 AM |
4166 | for (seq = get_current_sequence (); seq; seq = seq->next) |
4167 | if (before == seq->first) | |
4168 | { | |
4169 | seq->first = insn; | |
4170 | break; | |
4171 | } | |
4172 | ||
4173 | gcc_assert (seq); | |
23b2ce53 | 4174 | } |
96fba521 SB |
4175 | } |
4176 | ||
4177 | /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN. | |
4178 | If BB is NULL, an attempt is made to infer the bb from before. | |
4179 | ||
4180 | This and the next function should be the only functions called | |
4181 | to insert an insn once delay slots have been filled since only | |
4182 | they know how to update a SEQUENCE. */ | |
23b2ce53 | 4183 | |
96fba521 | 4184 | void |
4dea3bff | 4185 | add_insn_after (rtx_insn *insn, rtx_insn *after, basic_block bb) |
96fba521 SB |
4186 | { |
4187 | add_insn_after_nobb (insn, after); | |
4b4bf941 JQ |
4188 | if (!BARRIER_P (after) |
4189 | && !BARRIER_P (insn) | |
3c030e88 JH |
4190 | && (bb = BLOCK_FOR_INSN (after))) |
4191 | { | |
4192 | set_block_for_insn (insn, bb); | |
38c1593d | 4193 | if (INSN_P (insn)) |
6fb5fa3c | 4194 | df_insn_rescan (insn); |
3c030e88 | 4195 | /* Should not happen as first in the BB is always |
a1f300c0 | 4196 | either NOTE or LABEL. */ |
a813c111 | 4197 | if (BB_END (bb) == after |
3c030e88 | 4198 | /* Avoid clobbering of structure when creating new BB. */ |
4b4bf941 | 4199 | && !BARRIER_P (insn) |
a38e7aa5 | 4200 | && !NOTE_INSN_BASIC_BLOCK_P (insn)) |
1130d5e3 | 4201 | BB_END (bb) = insn; |
3c030e88 | 4202 | } |
23b2ce53 RS |
4203 | } |
4204 | ||
96fba521 SB |
4205 | /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN. |
4206 | If BB is NULL, an attempt is made to infer the bb from before. | |
4207 | ||
4208 | This and the previous function should be the only functions called | |
4209 | to insert an insn once delay slots have been filled since only | |
4210 | they know how to update a SEQUENCE. */ | |
a0ae8e8d RK |
4211 | |
4212 | void | |
4dea3bff | 4213 | add_insn_before (rtx_insn *insn, rtx_insn *before, basic_block bb) |
a0ae8e8d | 4214 | { |
96fba521 | 4215 | add_insn_before_nobb (insn, before); |
a0ae8e8d | 4216 | |
b8698a0f | 4217 | if (!bb |
6fb5fa3c DB |
4218 | && !BARRIER_P (before) |
4219 | && !BARRIER_P (insn)) | |
4220 | bb = BLOCK_FOR_INSN (before); | |
4221 | ||
4222 | if (bb) | |
3c030e88 JH |
4223 | { |
4224 | set_block_for_insn (insn, bb); | |
38c1593d | 4225 | if (INSN_P (insn)) |
6fb5fa3c | 4226 | df_insn_rescan (insn); |
5b0264cb | 4227 | /* Should not happen as first in the BB is always either NOTE or |
43e05e45 | 4228 | LABEL. */ |
5b0264cb NS |
4229 | gcc_assert (BB_HEAD (bb) != insn |
4230 | /* Avoid clobbering of structure when creating new BB. */ | |
4231 | || BARRIER_P (insn) | |
a38e7aa5 | 4232 | || NOTE_INSN_BASIC_BLOCK_P (insn)); |
3c030e88 | 4233 | } |
a0ae8e8d RK |
4234 | } |
4235 | ||
6fb5fa3c DB |
4236 | /* Replace insn with an deleted instruction note. */ |
4237 | ||
0ce2b299 | 4238 | void |
df0b55f0 | 4239 | set_insn_deleted (rtx_insn *insn) |
6fb5fa3c | 4240 | { |
39718607 | 4241 | if (INSN_P (insn)) |
df0b55f0 | 4242 | df_insn_delete (insn); |
6fb5fa3c DB |
4243 | PUT_CODE (insn, NOTE); |
4244 | NOTE_KIND (insn) = NOTE_INSN_DELETED; | |
4245 | } | |
4246 | ||
4247 | ||
1f397f45 SB |
4248 | /* Unlink INSN from the insn chain. |
4249 | ||
4250 | This function knows how to handle sequences. | |
4251 | ||
4252 | This function does not invalidate data flow information associated with | |
4253 | INSN (i.e. does not call df_insn_delete). That makes this function | |
4254 | usable for only disconnecting an insn from the chain, and re-emit it | |
4255 | elsewhere later. | |
4256 | ||
4257 | To later insert INSN elsewhere in the insn chain via add_insn and | |
4258 | similar functions, PREV_INSN and NEXT_INSN must be nullified by | |
4259 | the caller. Nullifying them here breaks many insn chain walks. | |
4260 | ||
4261 | To really delete an insn and related DF information, use delete_insn. */ | |
4262 | ||
89e99eea | 4263 | void |
4dea3bff | 4264 | remove_insn (rtx_insn *insn) |
89e99eea | 4265 | { |
1130d5e3 DM |
4266 | rtx_insn *next = NEXT_INSN (insn); |
4267 | rtx_insn *prev = PREV_INSN (insn); | |
53c17031 JH |
4268 | basic_block bb; |
4269 | ||
89e99eea DB |
4270 | if (prev) |
4271 | { | |
0f82e5c9 | 4272 | SET_NEXT_INSN (prev) = next; |
4b4bf941 | 4273 | if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE) |
89e99eea | 4274 | { |
e6eda746 DM |
4275 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev)); |
4276 | SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next; | |
89e99eea DB |
4277 | } |
4278 | } | |
89e99eea DB |
4279 | else |
4280 | { | |
614d5bd8 AM |
4281 | struct sequence_stack *seq; |
4282 | ||
4283 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4284 | if (insn == seq->first) | |
89e99eea | 4285 | { |
614d5bd8 | 4286 | seq->first = next; |
89e99eea DB |
4287 | break; |
4288 | } | |
4289 | ||
614d5bd8 | 4290 | gcc_assert (seq); |
89e99eea DB |
4291 | } |
4292 | ||
4293 | if (next) | |
4294 | { | |
0f82e5c9 | 4295 | SET_PREV_INSN (next) = prev; |
4b4bf941 | 4296 | if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) |
e6eda746 DM |
4297 | { |
4298 | rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next)); | |
4299 | SET_PREV_INSN (sequence->insn (0)) = prev; | |
4300 | } | |
89e99eea | 4301 | } |
89e99eea DB |
4302 | else |
4303 | { | |
614d5bd8 AM |
4304 | struct sequence_stack *seq; |
4305 | ||
4306 | for (seq = get_current_sequence (); seq; seq = seq->next) | |
4307 | if (insn == seq->last) | |
89e99eea | 4308 | { |
614d5bd8 | 4309 | seq->last = prev; |
89e99eea DB |
4310 | break; |
4311 | } | |
4312 | ||
614d5bd8 | 4313 | gcc_assert (seq); |
89e99eea | 4314 | } |
80eb8028 | 4315 | |
80eb8028 | 4316 | /* Fix up basic block boundaries, if necessary. */ |
4b4bf941 | 4317 | if (!BARRIER_P (insn) |
53c17031 JH |
4318 | && (bb = BLOCK_FOR_INSN (insn))) |
4319 | { | |
a813c111 | 4320 | if (BB_HEAD (bb) == insn) |
53c17031 | 4321 | { |
3bf1e984 RK |
4322 | /* Never ever delete the basic block note without deleting whole |
4323 | basic block. */ | |
5b0264cb | 4324 | gcc_assert (!NOTE_P (insn)); |
1130d5e3 | 4325 | BB_HEAD (bb) = next; |
53c17031 | 4326 | } |
a813c111 | 4327 | if (BB_END (bb) == insn) |
1130d5e3 | 4328 | BB_END (bb) = prev; |
53c17031 | 4329 | } |
89e99eea DB |
4330 | } |
4331 | ||
ee960939 OH |
4332 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
4333 | ||
4334 | void | |
502b8322 | 4335 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 | 4336 | { |
5b0264cb | 4337 | gcc_assert (call_insn && CALL_P (call_insn)); |
ee960939 OH |
4338 | |
4339 | /* Put the register usage information on the CALL. If there is already | |
4340 | some usage information, put ours at the end. */ | |
4341 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
4342 | { | |
4343 | rtx link; | |
4344 | ||
4345 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
4346 | link = XEXP (link, 1)) | |
4347 | ; | |
4348 | ||
4349 | XEXP (link, 1) = call_fusage; | |
4350 | } | |
4351 | else | |
4352 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
4353 | } | |
4354 | ||
23b2ce53 RS |
4355 | /* Delete all insns made since FROM. |
4356 | FROM becomes the new last instruction. */ | |
4357 | ||
4358 | void | |
fee3e72c | 4359 | delete_insns_since (rtx_insn *from) |
23b2ce53 RS |
4360 | { |
4361 | if (from == 0) | |
5936d944 | 4362 | set_first_insn (0); |
23b2ce53 | 4363 | else |
0f82e5c9 | 4364 | SET_NEXT_INSN (from) = 0; |
5936d944 | 4365 | set_last_insn (from); |
23b2ce53 RS |
4366 | } |
4367 | ||
5dab5552 MS |
4368 | /* This function is deprecated, please use sequences instead. |
4369 | ||
4370 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
4371 | The insns to be moved are those between FROM and TO. |
4372 | They are moved to a new position after the insn AFTER. | |
4373 | AFTER must not be FROM or TO or any insn in between. | |
4374 | ||
4375 | This function does not know about SEQUENCEs and hence should not be | |
4376 | called after delay-slot filling has been done. */ | |
4377 | ||
4378 | void | |
fee3e72c | 4379 | reorder_insns_nobb (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
23b2ce53 | 4380 | { |
b2b29377 MM |
4381 | if (flag_checking) |
4382 | { | |
4383 | for (rtx_insn *x = from; x != to; x = NEXT_INSN (x)) | |
4384 | gcc_assert (after != x); | |
4385 | gcc_assert (after != to); | |
4386 | } | |
4f8344eb | 4387 | |
23b2ce53 RS |
4388 | /* Splice this bunch out of where it is now. */ |
4389 | if (PREV_INSN (from)) | |
0f82e5c9 | 4390 | SET_NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); |
23b2ce53 | 4391 | if (NEXT_INSN (to)) |
0f82e5c9 | 4392 | SET_PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); |
5936d944 JH |
4393 | if (get_last_insn () == to) |
4394 | set_last_insn (PREV_INSN (from)); | |
4395 | if (get_insns () == from) | |
4396 | set_first_insn (NEXT_INSN (to)); | |
23b2ce53 RS |
4397 | |
4398 | /* Make the new neighbors point to it and it to them. */ | |
4399 | if (NEXT_INSN (after)) | |
0f82e5c9 | 4400 | SET_PREV_INSN (NEXT_INSN (after)) = to; |
23b2ce53 | 4401 | |
0f82e5c9 DM |
4402 | SET_NEXT_INSN (to) = NEXT_INSN (after); |
4403 | SET_PREV_INSN (from) = after; | |
4404 | SET_NEXT_INSN (after) = from; | |
c3284718 | 4405 | if (after == get_last_insn ()) |
5936d944 | 4406 | set_last_insn (to); |
23b2ce53 RS |
4407 | } |
4408 | ||
3c030e88 JH |
4409 | /* Same as function above, but take care to update BB boundaries. */ |
4410 | void | |
ac9d2d2c | 4411 | reorder_insns (rtx_insn *from, rtx_insn *to, rtx_insn *after) |
3c030e88 | 4412 | { |
ac9d2d2c | 4413 | rtx_insn *prev = PREV_INSN (from); |
3c030e88 JH |
4414 | basic_block bb, bb2; |
4415 | ||
4416 | reorder_insns_nobb (from, to, after); | |
4417 | ||
4b4bf941 | 4418 | if (!BARRIER_P (after) |
3c030e88 JH |
4419 | && (bb = BLOCK_FOR_INSN (after))) |
4420 | { | |
b2908ba6 | 4421 | rtx_insn *x; |
6fb5fa3c | 4422 | df_set_bb_dirty (bb); |
68252e27 | 4423 | |
4b4bf941 | 4424 | if (!BARRIER_P (from) |
3c030e88 JH |
4425 | && (bb2 = BLOCK_FOR_INSN (from))) |
4426 | { | |
a813c111 | 4427 | if (BB_END (bb2) == to) |
1130d5e3 | 4428 | BB_END (bb2) = prev; |
6fb5fa3c | 4429 | df_set_bb_dirty (bb2); |
3c030e88 JH |
4430 | } |
4431 | ||
a813c111 | 4432 | if (BB_END (bb) == after) |
1130d5e3 | 4433 | BB_END (bb) = to; |
3c030e88 JH |
4434 | |
4435 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
7bd5ed5c | 4436 | if (!BARRIER_P (x)) |
63642d5a | 4437 | df_insn_change_bb (x, bb); |
3c030e88 JH |
4438 | } |
4439 | } | |
4440 | ||
23b2ce53 | 4441 | \f |
2f937369 DM |
4442 | /* Emit insn(s) of given code and pattern |
4443 | at a specified place within the doubly-linked list. | |
23b2ce53 | 4444 | |
2f937369 DM |
4445 | All of the emit_foo global entry points accept an object |
4446 | X which is either an insn list or a PATTERN of a single | |
4447 | instruction. | |
23b2ce53 | 4448 | |
2f937369 DM |
4449 | There are thus a few canonical ways to generate code and |
4450 | emit it at a specific place in the instruction stream. For | |
4451 | example, consider the instruction named SPOT and the fact that | |
4452 | we would like to emit some instructions before SPOT. We might | |
4453 | do it like this: | |
23b2ce53 | 4454 | |
2f937369 DM |
4455 | start_sequence (); |
4456 | ... emit the new instructions ... | |
4457 | insns_head = get_insns (); | |
4458 | end_sequence (); | |
23b2ce53 | 4459 | |
2f937369 | 4460 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4461 | |
2f937369 DM |
4462 | It used to be common to generate SEQUENCE rtl instead, but that |
4463 | is a relic of the past which no longer occurs. The reason is that | |
4464 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4465 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4466 | |
cd459bf8 | 4467 | static rtx_insn * |
4dea3bff DM |
4468 | emit_pattern_before_noloc (rtx x, rtx_insn *before, rtx_insn *last, |
4469 | basic_block bb, | |
167b9fae | 4470 | rtx_insn *(*make_raw) (rtx)) |
23b2ce53 | 4471 | { |
167b9fae | 4472 | rtx_insn *insn; |
23b2ce53 | 4473 | |
5b0264cb | 4474 | gcc_assert (before); |
2f937369 DM |
4475 | |
4476 | if (x == NULL_RTX) | |
4dea3bff | 4477 | return last; |
2f937369 DM |
4478 | |
4479 | switch (GET_CODE (x)) | |
23b2ce53 | 4480 | { |
b5b8b0ac | 4481 | case DEBUG_INSN: |
2f937369 DM |
4482 | case INSN: |
4483 | case JUMP_INSN: | |
4484 | case CALL_INSN: | |
4485 | case CODE_LABEL: | |
4486 | case BARRIER: | |
4487 | case NOTE: | |
167b9fae | 4488 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
4489 | while (insn) |
4490 | { | |
167b9fae | 4491 | rtx_insn *next = NEXT_INSN (insn); |
6fb5fa3c | 4492 | add_insn_before (insn, before, bb); |
2f937369 DM |
4493 | last = insn; |
4494 | insn = next; | |
4495 | } | |
4496 | break; | |
4497 | ||
4498 | #ifdef ENABLE_RTL_CHECKING | |
4499 | case SEQUENCE: | |
5b0264cb | 4500 | gcc_unreachable (); |
2f937369 DM |
4501 | break; |
4502 | #endif | |
4503 | ||
4504 | default: | |
5f02387d | 4505 | last = (*make_raw) (x); |
6fb5fa3c | 4506 | add_insn_before (last, before, bb); |
2f937369 | 4507 | break; |
23b2ce53 RS |
4508 | } |
4509 | ||
4dea3bff | 4510 | return last; |
23b2ce53 RS |
4511 | } |
4512 | ||
5f02387d NF |
4513 | /* Make X be output before the instruction BEFORE. */ |
4514 | ||
cd459bf8 | 4515 | rtx_insn * |
596f2b17 | 4516 | emit_insn_before_noloc (rtx x, rtx_insn *before, basic_block bb) |
5f02387d NF |
4517 | { |
4518 | return emit_pattern_before_noloc (x, before, before, bb, make_insn_raw); | |
4519 | } | |
4520 | ||
2f937369 | 4521 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4522 | and output it before the instruction BEFORE. */ |
4523 | ||
1476d1bd | 4524 | rtx_jump_insn * |
596f2b17 | 4525 | emit_jump_insn_before_noloc (rtx x, rtx_insn *before) |
23b2ce53 | 4526 | { |
1476d1bd | 4527 | return as_a <rtx_jump_insn *> ( |
4dea3bff | 4528 | emit_pattern_before_noloc (x, before, NULL, NULL, |
1476d1bd | 4529 | make_jump_insn_raw)); |
23b2ce53 RS |
4530 | } |
4531 | ||
2f937369 | 4532 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4533 | and output it before the instruction BEFORE. */ |
4534 | ||
cd459bf8 | 4535 | rtx_insn * |
596f2b17 | 4536 | emit_call_insn_before_noloc (rtx x, rtx_insn *before) |
969d70ca | 4537 | { |
4dea3bff | 4538 | return emit_pattern_before_noloc (x, before, NULL, NULL, |
5f02387d | 4539 | make_call_insn_raw); |
969d70ca JH |
4540 | } |
4541 | ||
b5b8b0ac AO |
4542 | /* Make an instruction with body X and code DEBUG_INSN |
4543 | and output it before the instruction BEFORE. */ | |
4544 | ||
cd459bf8 | 4545 | rtx_insn * |
4dea3bff | 4546 | emit_debug_insn_before_noloc (rtx x, rtx_insn *before) |
b5b8b0ac | 4547 | { |
4dea3bff | 4548 | return emit_pattern_before_noloc (x, before, NULL, NULL, |
5f02387d | 4549 | make_debug_insn_raw); |
b5b8b0ac AO |
4550 | } |
4551 | ||
23b2ce53 | 4552 | /* Make an insn of code BARRIER |
e881bb1b | 4553 | and output it before the insn BEFORE. */ |
23b2ce53 | 4554 | |
cd459bf8 | 4555 | rtx_barrier * |
4dea3bff | 4556 | emit_barrier_before (rtx_insn *before) |
23b2ce53 | 4557 | { |
cd459bf8 | 4558 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4559 | |
4560 | INSN_UID (insn) = cur_insn_uid++; | |
4561 | ||
6fb5fa3c | 4562 | add_insn_before (insn, before, NULL); |
23b2ce53 RS |
4563 | return insn; |
4564 | } | |
4565 | ||
e881bb1b RH |
4566 | /* Emit the label LABEL before the insn BEFORE. */ |
4567 | ||
1476d1bd | 4568 | rtx_code_label * |
4dea3bff | 4569 | emit_label_before (rtx_code_label *label, rtx_insn *before) |
e881bb1b | 4570 | { |
468660d3 SB |
4571 | gcc_checking_assert (INSN_UID (label) == 0); |
4572 | INSN_UID (label) = cur_insn_uid++; | |
4573 | add_insn_before (label, before, NULL); | |
4dea3bff | 4574 | return label; |
e881bb1b | 4575 | } |
23b2ce53 | 4576 | \f |
2f937369 DM |
4577 | /* Helper for emit_insn_after, handles lists of instructions |
4578 | efficiently. */ | |
23b2ce53 | 4579 | |
e6eda746 | 4580 | static rtx_insn * |
4dea3bff | 4581 | emit_insn_after_1 (rtx_insn *first, rtx_insn *after, basic_block bb) |
23b2ce53 | 4582 | { |
1130d5e3 DM |
4583 | rtx_insn *last; |
4584 | rtx_insn *after_after; | |
6fb5fa3c DB |
4585 | if (!bb && !BARRIER_P (after)) |
4586 | bb = BLOCK_FOR_INSN (after); | |
23b2ce53 | 4587 | |
6fb5fa3c | 4588 | if (bb) |
23b2ce53 | 4589 | { |
6fb5fa3c | 4590 | df_set_bb_dirty (bb); |
2f937369 | 4591 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4b4bf941 | 4592 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4593 | { |
4594 | set_block_for_insn (last, bb); | |
4595 | df_insn_rescan (last); | |
4596 | } | |
4b4bf941 | 4597 | if (!BARRIER_P (last)) |
6fb5fa3c DB |
4598 | { |
4599 | set_block_for_insn (last, bb); | |
4600 | df_insn_rescan (last); | |
4601 | } | |
a813c111 | 4602 | if (BB_END (bb) == after) |
1130d5e3 | 4603 | BB_END (bb) = last; |
23b2ce53 RS |
4604 | } |
4605 | else | |
2f937369 DM |
4606 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4607 | continue; | |
4608 | ||
4609 | after_after = NEXT_INSN (after); | |
4610 | ||
0f82e5c9 DM |
4611 | SET_NEXT_INSN (after) = first; |
4612 | SET_PREV_INSN (first) = after; | |
4613 | SET_NEXT_INSN (last) = after_after; | |
2f937369 | 4614 | if (after_after) |
0f82e5c9 | 4615 | SET_PREV_INSN (after_after) = last; |
2f937369 | 4616 | |
c3284718 | 4617 | if (after == get_last_insn ()) |
5936d944 | 4618 | set_last_insn (last); |
e855c69d | 4619 | |
2f937369 DM |
4620 | return last; |
4621 | } | |
4622 | ||
cd459bf8 | 4623 | static rtx_insn * |
4dea3bff | 4624 | emit_pattern_after_noloc (rtx x, rtx_insn *after, basic_block bb, |
167b9fae | 4625 | rtx_insn *(*make_raw)(rtx)) |
2f937369 | 4626 | { |
e6eda746 | 4627 | rtx_insn *last = after; |
2f937369 | 4628 | |
5b0264cb | 4629 | gcc_assert (after); |
2f937369 DM |
4630 | |
4631 | if (x == NULL_RTX) | |
e6eda746 | 4632 | return last; |
2f937369 DM |
4633 | |
4634 | switch (GET_CODE (x)) | |
23b2ce53 | 4635 | { |
b5b8b0ac | 4636 | case DEBUG_INSN: |
2f937369 DM |
4637 | case INSN: |
4638 | case JUMP_INSN: | |
4639 | case CALL_INSN: | |
4640 | case CODE_LABEL: | |
4641 | case BARRIER: | |
4642 | case NOTE: | |
1130d5e3 | 4643 | last = emit_insn_after_1 (as_a <rtx_insn *> (x), after, bb); |
2f937369 DM |
4644 | break; |
4645 | ||
4646 | #ifdef ENABLE_RTL_CHECKING | |
4647 | case SEQUENCE: | |
5b0264cb | 4648 | gcc_unreachable (); |
2f937369 DM |
4649 | break; |
4650 | #endif | |
4651 | ||
4652 | default: | |
5f02387d | 4653 | last = (*make_raw) (x); |
6fb5fa3c | 4654 | add_insn_after (last, after, bb); |
2f937369 | 4655 | break; |
23b2ce53 RS |
4656 | } |
4657 | ||
e6eda746 | 4658 | return last; |
23b2ce53 RS |
4659 | } |
4660 | ||
5f02387d NF |
4661 | /* Make X be output after the insn AFTER and set the BB of insn. If |
4662 | BB is NULL, an attempt is made to infer the BB from AFTER. */ | |
4663 | ||
cd459bf8 | 4664 | rtx_insn * |
4dea3bff | 4665 | emit_insn_after_noloc (rtx x, rtx_insn *after, basic_block bb) |
5f02387d NF |
4666 | { |
4667 | return emit_pattern_after_noloc (x, after, bb, make_insn_raw); | |
4668 | } | |
4669 | ||
255680cf | 4670 | |
2f937369 | 4671 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4672 | and output it after the insn AFTER. */ |
4673 | ||
1476d1bd | 4674 | rtx_jump_insn * |
4dea3bff | 4675 | emit_jump_insn_after_noloc (rtx x, rtx_insn *after) |
23b2ce53 | 4676 | { |
1476d1bd MM |
4677 | return as_a <rtx_jump_insn *> ( |
4678 | emit_pattern_after_noloc (x, after, NULL, make_jump_insn_raw)); | |
2f937369 DM |
4679 | } |
4680 | ||
4681 | /* Make an instruction with body X and code CALL_INSN | |
4682 | and output it after the instruction AFTER. */ | |
4683 | ||
cd459bf8 | 4684 | rtx_insn * |
4dea3bff | 4685 | emit_call_insn_after_noloc (rtx x, rtx_insn *after) |
2f937369 | 4686 | { |
5f02387d | 4687 | return emit_pattern_after_noloc (x, after, NULL, make_call_insn_raw); |
23b2ce53 RS |
4688 | } |
4689 | ||
b5b8b0ac AO |
4690 | /* Make an instruction with body X and code CALL_INSN |
4691 | and output it after the instruction AFTER. */ | |
4692 | ||
cd459bf8 | 4693 | rtx_insn * |
4dea3bff | 4694 | emit_debug_insn_after_noloc (rtx x, rtx_insn *after) |
b5b8b0ac | 4695 | { |
5f02387d | 4696 | return emit_pattern_after_noloc (x, after, NULL, make_debug_insn_raw); |
b5b8b0ac AO |
4697 | } |
4698 | ||
23b2ce53 RS |
4699 | /* Make an insn of code BARRIER |
4700 | and output it after the insn AFTER. */ | |
4701 | ||
cd459bf8 | 4702 | rtx_barrier * |
4dea3bff | 4703 | emit_barrier_after (rtx_insn *after) |
23b2ce53 | 4704 | { |
cd459bf8 | 4705 | rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
4706 | |
4707 | INSN_UID (insn) = cur_insn_uid++; | |
4708 | ||
6fb5fa3c | 4709 | add_insn_after (insn, after, NULL); |
23b2ce53 RS |
4710 | return insn; |
4711 | } | |
4712 | ||
4713 | /* Emit the label LABEL after the insn AFTER. */ | |
4714 | ||
cd459bf8 | 4715 | rtx_insn * |
4dea3bff | 4716 | emit_label_after (rtx_insn *label, rtx_insn *after) |
23b2ce53 | 4717 | { |
468660d3 SB |
4718 | gcc_checking_assert (INSN_UID (label) == 0); |
4719 | INSN_UID (label) = cur_insn_uid++; | |
4720 | add_insn_after (label, after, NULL); | |
4dea3bff | 4721 | return label; |
23b2ce53 | 4722 | } |
96fba521 SB |
4723 | \f |
4724 | /* Notes require a bit of special handling: Some notes need to have their | |
4725 | BLOCK_FOR_INSN set, others should never have it set, and some should | |
4726 | have it set or clear depending on the context. */ | |
4727 | ||
4728 | /* Return true iff a note of kind SUBTYPE should be emitted with routines | |
4729 | that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the | |
4730 | caller is asked to emit a note before BB_HEAD, or after BB_END. */ | |
4731 | ||
4732 | static bool | |
4733 | note_outside_basic_block_p (enum insn_note subtype, bool on_bb_boundary_p) | |
4734 | { | |
4735 | switch (subtype) | |
4736 | { | |
4737 | /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */ | |
4738 | case NOTE_INSN_SWITCH_TEXT_SECTIONS: | |
4739 | return true; | |
4740 | ||
4741 | /* Notes for var tracking and EH region markers can appear between or | |
4742 | inside basic blocks. If the caller is emitting on the basic block | |
4743 | boundary, do not set BLOCK_FOR_INSN on the new note. */ | |
4744 | case NOTE_INSN_VAR_LOCATION: | |
96fba521 SB |
4745 | case NOTE_INSN_EH_REGION_BEG: |
4746 | case NOTE_INSN_EH_REGION_END: | |
4747 | return on_bb_boundary_p; | |
4748 | ||
4749 | /* Otherwise, BLOCK_FOR_INSN must be set. */ | |
4750 | default: | |
4751 | return false; | |
4752 | } | |
4753 | } | |
23b2ce53 RS |
4754 | |
4755 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4756 | ||
66e8df53 | 4757 | rtx_note * |
589e43f9 | 4758 | emit_note_after (enum insn_note subtype, rtx_insn *after) |
23b2ce53 | 4759 | { |
66e8df53 | 4760 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4761 | basic_block bb = BARRIER_P (after) ? NULL : BLOCK_FOR_INSN (after); |
4762 | bool on_bb_boundary_p = (bb != NULL && BB_END (bb) == after); | |
4763 | ||
4764 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4765 | add_insn_after_nobb (note, after); | |
4766 | else | |
4767 | add_insn_after (note, after, bb); | |
4768 | return note; | |
4769 | } | |
4770 | ||
4771 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ | |
4772 | ||
66e8df53 | 4773 | rtx_note * |
89b6250d | 4774 | emit_note_before (enum insn_note subtype, rtx_insn *before) |
96fba521 | 4775 | { |
66e8df53 | 4776 | rtx_note *note = make_note_raw (subtype); |
96fba521 SB |
4777 | basic_block bb = BARRIER_P (before) ? NULL : BLOCK_FOR_INSN (before); |
4778 | bool on_bb_boundary_p = (bb != NULL && BB_HEAD (bb) == before); | |
4779 | ||
4780 | if (note_outside_basic_block_p (subtype, on_bb_boundary_p)) | |
4781 | add_insn_before_nobb (note, before); | |
4782 | else | |
4783 | add_insn_before (note, before, bb); | |
23b2ce53 RS |
4784 | return note; |
4785 | } | |
23b2ce53 | 4786 | \f |
e8110d6f NF |
4787 | /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC. |
4788 | MAKE_RAW indicates how to turn PATTERN into a real insn. */ | |
4789 | ||
cd459bf8 | 4790 | static rtx_insn * |
4dea3bff | 4791 | emit_pattern_after_setloc (rtx pattern, rtx_insn *after, location_t loc, |
167b9fae | 4792 | rtx_insn *(*make_raw) (rtx)) |
0d682900 | 4793 | { |
e67d1102 | 4794 | rtx_insn *last = emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
0d682900 | 4795 | |
a7102479 | 4796 | if (pattern == NULL_RTX || !loc) |
e67d1102 | 4797 | return last; |
dd3adcf8 | 4798 | |
2f937369 DM |
4799 | after = NEXT_INSN (after); |
4800 | while (1) | |
4801 | { | |
20d4397a EB |
4802 | if (active_insn_p (after) |
4803 | && !JUMP_TABLE_DATA_P (after) /* FIXME */ | |
4804 | && !INSN_LOCATION (after)) | |
5368224f | 4805 | INSN_LOCATION (after) = loc; |
2f937369 DM |
4806 | if (after == last) |
4807 | break; | |
4808 | after = NEXT_INSN (after); | |
4809 | } | |
e67d1102 | 4810 | return last; |
0d682900 JH |
4811 | } |
4812 | ||
e8110d6f NF |
4813 | /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN |
4814 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after | |
4815 | any DEBUG_INSNs. */ | |
4816 | ||
cd459bf8 | 4817 | static rtx_insn * |
df0b55f0 | 4818 | emit_pattern_after (rtx pattern, rtx_insn *after, bool skip_debug_insns, |
167b9fae | 4819 | rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4820 | { |
dc01c3d1 | 4821 | rtx_insn *prev = after; |
b5b8b0ac | 4822 | |
e8110d6f NF |
4823 | if (skip_debug_insns) |
4824 | while (DEBUG_INSN_P (prev)) | |
4825 | prev = PREV_INSN (prev); | |
b5b8b0ac AO |
4826 | |
4827 | if (INSN_P (prev)) | |
5368224f | 4828 | return emit_pattern_after_setloc (pattern, after, INSN_LOCATION (prev), |
e8110d6f | 4829 | make_raw); |
a7102479 | 4830 | else |
e8110d6f | 4831 | return emit_pattern_after_noloc (pattern, after, NULL, make_raw); |
a7102479 JH |
4832 | } |
4833 | ||
5368224f | 4834 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4835 | rtx_insn * |
4dea3bff | 4836 | emit_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
0d682900 | 4837 | { |
e8110d6f NF |
4838 | return emit_pattern_after_setloc (pattern, after, loc, make_insn_raw); |
4839 | } | |
2f937369 | 4840 | |
5368224f | 4841 | /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4842 | rtx_insn * |
df0b55f0 | 4843 | emit_insn_after (rtx pattern, rtx_insn *after) |
e8110d6f NF |
4844 | { |
4845 | return emit_pattern_after (pattern, after, true, make_insn_raw); | |
4846 | } | |
dd3adcf8 | 4847 | |
5368224f | 4848 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4849 | rtx_jump_insn * |
4dea3bff | 4850 | emit_jump_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
e8110d6f | 4851 | { |
1476d1bd MM |
4852 | return as_a <rtx_jump_insn *> ( |
4853 | emit_pattern_after_setloc (pattern, after, loc, make_jump_insn_raw)); | |
0d682900 JH |
4854 | } |
4855 | ||
5368224f | 4856 | /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
1476d1bd | 4857 | rtx_jump_insn * |
df0b55f0 | 4858 | emit_jump_insn_after (rtx pattern, rtx_insn *after) |
a7102479 | 4859 | { |
1476d1bd MM |
4860 | return as_a <rtx_jump_insn *> ( |
4861 | emit_pattern_after (pattern, after, true, make_jump_insn_raw)); | |
a7102479 JH |
4862 | } |
4863 | ||
5368224f | 4864 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4865 | rtx_insn * |
4dea3bff | 4866 | emit_call_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
0d682900 | 4867 | { |
e8110d6f | 4868 | return emit_pattern_after_setloc (pattern, after, loc, make_call_insn_raw); |
0d682900 JH |
4869 | } |
4870 | ||
5368224f | 4871 | /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4872 | rtx_insn * |
df0b55f0 | 4873 | emit_call_insn_after (rtx pattern, rtx_insn *after) |
a7102479 | 4874 | { |
e8110d6f | 4875 | return emit_pattern_after (pattern, after, true, make_call_insn_raw); |
a7102479 JH |
4876 | } |
4877 | ||
5368224f | 4878 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4879 | rtx_insn * |
4dea3bff | 4880 | emit_debug_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc) |
b5b8b0ac | 4881 | { |
e8110d6f | 4882 | return emit_pattern_after_setloc (pattern, after, loc, make_debug_insn_raw); |
b5b8b0ac AO |
4883 | } |
4884 | ||
5368224f | 4885 | /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */ |
cd459bf8 | 4886 | rtx_insn * |
df0b55f0 | 4887 | emit_debug_insn_after (rtx pattern, rtx_insn *after) |
b5b8b0ac | 4888 | { |
e8110d6f | 4889 | return emit_pattern_after (pattern, after, false, make_debug_insn_raw); |
b5b8b0ac AO |
4890 | } |
4891 | ||
e8110d6f NF |
4892 | /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC. |
4893 | MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP | |
4894 | indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN, | |
4895 | CALL_INSN, etc. */ | |
4896 | ||
cd459bf8 | 4897 | static rtx_insn * |
4dea3bff DM |
4898 | emit_pattern_before_setloc (rtx pattern, rtx_insn *before, location_t loc, |
4899 | bool insnp, rtx_insn *(*make_raw) (rtx)) | |
0d682900 | 4900 | { |
dc01c3d1 DM |
4901 | rtx_insn *first = PREV_INSN (before); |
4902 | rtx_insn *last = emit_pattern_before_noloc (pattern, before, | |
4dea3bff | 4903 | insnp ? before : NULL, |
dc01c3d1 | 4904 | NULL, make_raw); |
a7102479 JH |
4905 | |
4906 | if (pattern == NULL_RTX || !loc) | |
dc01c3d1 | 4907 | return last; |
a7102479 | 4908 | |
26cb3993 JH |
4909 | if (!first) |
4910 | first = get_insns (); | |
4911 | else | |
4912 | first = NEXT_INSN (first); | |
a7102479 JH |
4913 | while (1) |
4914 | { | |
20d4397a EB |
4915 | if (active_insn_p (first) |
4916 | && !JUMP_TABLE_DATA_P (first) /* FIXME */ | |
4917 | && !INSN_LOCATION (first)) | |
5368224f | 4918 | INSN_LOCATION (first) = loc; |
a7102479 JH |
4919 | if (first == last) |
4920 | break; | |
4921 | first = NEXT_INSN (first); | |
4922 | } | |
dc01c3d1 | 4923 | return last; |
a7102479 JH |
4924 | } |
4925 | ||
e8110d6f NF |
4926 | /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN |
4927 | into a real insn. SKIP_DEBUG_INSNS indicates whether to insert | |
4928 | before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an | |
4929 | INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */ | |
4930 | ||
cd459bf8 | 4931 | static rtx_insn * |
df0b55f0 | 4932 | emit_pattern_before (rtx pattern, rtx_insn *before, bool skip_debug_insns, |
167b9fae | 4933 | bool insnp, rtx_insn *(*make_raw) (rtx)) |
a7102479 | 4934 | { |
dc01c3d1 | 4935 | rtx_insn *next = before; |
b5b8b0ac | 4936 | |
e8110d6f NF |
4937 | if (skip_debug_insns) |
4938 | while (DEBUG_INSN_P (next)) | |
4939 | next = PREV_INSN (next); | |
b5b8b0ac AO |
4940 | |
4941 | if (INSN_P (next)) | |
5368224f | 4942 | return emit_pattern_before_setloc (pattern, before, INSN_LOCATION (next), |
e8110d6f | 4943 | insnp, make_raw); |
a7102479 | 4944 | else |
e8110d6f | 4945 | return emit_pattern_before_noloc (pattern, before, |
4dea3bff | 4946 | insnp ? before : NULL, |
e8110d6f | 4947 | NULL, make_raw); |
a7102479 JH |
4948 | } |
4949 | ||
5368224f | 4950 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4951 | rtx_insn * |
4dea3bff | 4952 | emit_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
a7102479 | 4953 | { |
e8110d6f NF |
4954 | return emit_pattern_before_setloc (pattern, before, loc, true, |
4955 | make_insn_raw); | |
4956 | } | |
a7102479 | 4957 | |
5368224f | 4958 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
cd459bf8 | 4959 | rtx_insn * |
df0b55f0 | 4960 | emit_insn_before (rtx pattern, rtx_insn *before) |
e8110d6f NF |
4961 | { |
4962 | return emit_pattern_before (pattern, before, true, true, make_insn_raw); | |
4963 | } | |
a7102479 | 4964 | |
5368224f | 4965 | /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
1476d1bd | 4966 | rtx_jump_insn * |
4dea3bff | 4967 | emit_jump_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
e8110d6f | 4968 | { |
1476d1bd MM |
4969 | return as_a <rtx_jump_insn *> ( |
4970 | emit_pattern_before_setloc (pattern, before, loc, false, | |
4971 | make_jump_insn_raw)); | |
a7102479 JH |
4972 | } |
4973 | ||
5368224f | 4974 | /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */ |
1476d1bd | 4975 | rtx_jump_insn * |
df0b55f0 | 4976 | emit_jump_insn_before (rtx pattern, rtx_insn *before) |
a7102479 | 4977 | { |
1476d1bd MM |
4978 | return as_a <rtx_jump_insn *> ( |
4979 | emit_pattern_before (pattern, before, true, false, | |
4980 | make_jump_insn_raw)); | |
a7102479 JH |
4981 | } |
4982 | ||
5368224f | 4983 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 4984 | rtx_insn * |
4dea3bff | 4985 | emit_call_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
a7102479 | 4986 | { |
e8110d6f NF |
4987 | return emit_pattern_before_setloc (pattern, before, loc, false, |
4988 | make_call_insn_raw); | |
0d682900 | 4989 | } |
a7102479 | 4990 | |
e8110d6f | 4991 | /* Like emit_call_insn_before_noloc, |
5368224f | 4992 | but set insn_location according to BEFORE. */ |
cd459bf8 | 4993 | rtx_insn * |
596f2b17 | 4994 | emit_call_insn_before (rtx pattern, rtx_insn *before) |
a7102479 | 4995 | { |
e8110d6f NF |
4996 | return emit_pattern_before (pattern, before, true, false, |
4997 | make_call_insn_raw); | |
a7102479 | 4998 | } |
b5b8b0ac | 4999 | |
5368224f | 5000 | /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */ |
cd459bf8 | 5001 | rtx_insn * |
4dea3bff | 5002 | emit_debug_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc) |
b5b8b0ac | 5003 | { |
e8110d6f NF |
5004 | return emit_pattern_before_setloc (pattern, before, loc, false, |
5005 | make_debug_insn_raw); | |
b5b8b0ac AO |
5006 | } |
5007 | ||
e8110d6f | 5008 | /* Like emit_debug_insn_before_noloc, |
5368224f | 5009 | but set insn_location according to BEFORE. */ |
cd459bf8 | 5010 | rtx_insn * |
3a6216b0 | 5011 | emit_debug_insn_before (rtx pattern, rtx_insn *before) |
b5b8b0ac | 5012 | { |
e8110d6f NF |
5013 | return emit_pattern_before (pattern, before, false, false, |
5014 | make_debug_insn_raw); | |
b5b8b0ac | 5015 | } |
0d682900 | 5016 | \f |
2f937369 DM |
5017 | /* Take X and emit it at the end of the doubly-linked |
5018 | INSN list. | |
23b2ce53 RS |
5019 | |
5020 | Returns the last insn emitted. */ | |
5021 | ||
cd459bf8 | 5022 | rtx_insn * |
502b8322 | 5023 | emit_insn (rtx x) |
23b2ce53 | 5024 | { |
cd459bf8 DM |
5025 | rtx_insn *last = get_last_insn (); |
5026 | rtx_insn *insn; | |
23b2ce53 | 5027 | |
2f937369 DM |
5028 | if (x == NULL_RTX) |
5029 | return last; | |
23b2ce53 | 5030 | |
2f937369 DM |
5031 | switch (GET_CODE (x)) |
5032 | { | |
b5b8b0ac | 5033 | case DEBUG_INSN: |
2f937369 DM |
5034 | case INSN: |
5035 | case JUMP_INSN: | |
5036 | case CALL_INSN: | |
5037 | case CODE_LABEL: | |
5038 | case BARRIER: | |
5039 | case NOTE: | |
cd459bf8 | 5040 | insn = as_a <rtx_insn *> (x); |
2f937369 | 5041 | while (insn) |
23b2ce53 | 5042 | { |
cd459bf8 | 5043 | rtx_insn *next = NEXT_INSN (insn); |
23b2ce53 | 5044 | add_insn (insn); |
2f937369 DM |
5045 | last = insn; |
5046 | insn = next; | |
23b2ce53 | 5047 | } |
2f937369 | 5048 | break; |
23b2ce53 | 5049 | |
2f937369 | 5050 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 5051 | case JUMP_TABLE_DATA: |
2f937369 | 5052 | case SEQUENCE: |
5b0264cb | 5053 | gcc_unreachable (); |
2f937369 DM |
5054 | break; |
5055 | #endif | |
23b2ce53 | 5056 | |
2f937369 DM |
5057 | default: |
5058 | last = make_insn_raw (x); | |
5059 | add_insn (last); | |
5060 | break; | |
23b2ce53 RS |
5061 | } |
5062 | ||
5063 | return last; | |
5064 | } | |
5065 | ||
b5b8b0ac AO |
5066 | /* Make an insn of code DEBUG_INSN with pattern X |
5067 | and add it to the end of the doubly-linked list. */ | |
5068 | ||
cd459bf8 | 5069 | rtx_insn * |
b5b8b0ac AO |
5070 | emit_debug_insn (rtx x) |
5071 | { | |
cd459bf8 DM |
5072 | rtx_insn *last = get_last_insn (); |
5073 | rtx_insn *insn; | |
b5b8b0ac AO |
5074 | |
5075 | if (x == NULL_RTX) | |
5076 | return last; | |
5077 | ||
5078 | switch (GET_CODE (x)) | |
5079 | { | |
5080 | case DEBUG_INSN: | |
5081 | case INSN: | |
5082 | case JUMP_INSN: | |
5083 | case CALL_INSN: | |
5084 | case CODE_LABEL: | |
5085 | case BARRIER: | |
5086 | case NOTE: | |
cd459bf8 | 5087 | insn = as_a <rtx_insn *> (x); |
b5b8b0ac AO |
5088 | while (insn) |
5089 | { | |
cd459bf8 | 5090 | rtx_insn *next = NEXT_INSN (insn); |
b5b8b0ac AO |
5091 | add_insn (insn); |
5092 | last = insn; | |
5093 | insn = next; | |
5094 | } | |
5095 | break; | |
5096 | ||
5097 | #ifdef ENABLE_RTL_CHECKING | |
39718607 | 5098 | case JUMP_TABLE_DATA: |
b5b8b0ac AO |
5099 | case SEQUENCE: |
5100 | gcc_unreachable (); | |
5101 | break; | |
5102 | #endif | |
5103 | ||
5104 | default: | |
5105 | last = make_debug_insn_raw (x); | |
5106 | add_insn (last); | |
5107 | break; | |
5108 | } | |
5109 | ||
5110 | return last; | |
5111 | } | |
5112 | ||
2f937369 DM |
5113 | /* Make an insn of code JUMP_INSN with pattern X |
5114 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5115 | |
cd459bf8 | 5116 | rtx_insn * |
502b8322 | 5117 | emit_jump_insn (rtx x) |
23b2ce53 | 5118 | { |
cd459bf8 DM |
5119 | rtx_insn *last = NULL; |
5120 | rtx_insn *insn; | |
23b2ce53 | 5121 | |
2f937369 | 5122 | switch (GET_CODE (x)) |
23b2ce53 | 5123 | { |
b5b8b0ac | 5124 | case DEBUG_INSN: |
2f937369 DM |
5125 | case INSN: |
5126 | case JUMP_INSN: | |
5127 | case CALL_INSN: | |
5128 | case CODE_LABEL: | |
5129 | case BARRIER: | |
5130 | case NOTE: | |
cd459bf8 | 5131 | insn = as_a <rtx_insn *> (x); |
2f937369 DM |
5132 | while (insn) |
5133 | { | |
cd459bf8 | 5134 | rtx_insn *next = NEXT_INSN (insn); |
2f937369 DM |
5135 | add_insn (insn); |
5136 | last = insn; | |
5137 | insn = next; | |
5138 | } | |
5139 | break; | |
e0a5c5eb | 5140 | |
2f937369 | 5141 | #ifdef ENABLE_RTL_CHECKING |
39718607 | 5142 | case JUMP_TABLE_DATA: |
2f937369 | 5143 | case SEQUENCE: |
5b0264cb | 5144 | gcc_unreachable (); |
2f937369 DM |
5145 | break; |
5146 | #endif | |
e0a5c5eb | 5147 | |
2f937369 DM |
5148 | default: |
5149 | last = make_jump_insn_raw (x); | |
5150 | add_insn (last); | |
5151 | break; | |
3c030e88 | 5152 | } |
e0a5c5eb RS |
5153 | |
5154 | return last; | |
5155 | } | |
5156 | ||
2f937369 | 5157 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
5158 | and add it to the end of the doubly-linked list. */ |
5159 | ||
cd459bf8 | 5160 | rtx_insn * |
502b8322 | 5161 | emit_call_insn (rtx x) |
23b2ce53 | 5162 | { |
cd459bf8 | 5163 | rtx_insn *insn; |
2f937369 DM |
5164 | |
5165 | switch (GET_CODE (x)) | |
23b2ce53 | 5166 | { |
b5b8b0ac | 5167 | case DEBUG_INSN: |
2f937369 DM |
5168 | case INSN: |
5169 | case JUMP_INSN: | |
5170 | case CALL_INSN: | |
5171 | case CODE_LABEL: | |
5172 | case BARRIER: | |
5173 | case NOTE: | |
5174 | insn = emit_insn (x); | |
5175 | break; | |
23b2ce53 | 5176 | |
2f937369 DM |
5177 | #ifdef ENABLE_RTL_CHECKING |
5178 | case SEQUENCE: | |
39718607 | 5179 | case JUMP_TABLE_DATA: |
5b0264cb | 5180 | gcc_unreachable (); |
2f937369 DM |
5181 | break; |
5182 | #endif | |
23b2ce53 | 5183 | |
2f937369 DM |
5184 | default: |
5185 | insn = make_call_insn_raw (x); | |
23b2ce53 | 5186 | add_insn (insn); |
2f937369 | 5187 | break; |
23b2ce53 | 5188 | } |
2f937369 DM |
5189 | |
5190 | return insn; | |
23b2ce53 RS |
5191 | } |
5192 | ||
5193 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
5194 | ||
1476d1bd MM |
5195 | rtx_code_label * |
5196 | emit_label (rtx uncast_label) | |
23b2ce53 | 5197 | { |
1476d1bd MM |
5198 | rtx_code_label *label = as_a <rtx_code_label *> (uncast_label); |
5199 | ||
468660d3 SB |
5200 | gcc_checking_assert (INSN_UID (label) == 0); |
5201 | INSN_UID (label) = cur_insn_uid++; | |
1476d1bd MM |
5202 | add_insn (label); |
5203 | return label; | |
23b2ce53 RS |
5204 | } |
5205 | ||
39718607 SB |
5206 | /* Make an insn of code JUMP_TABLE_DATA |
5207 | and add it to the end of the doubly-linked list. */ | |
5208 | ||
4598afdd | 5209 | rtx_jump_table_data * |
39718607 SB |
5210 | emit_jump_table_data (rtx table) |
5211 | { | |
4598afdd DM |
5212 | rtx_jump_table_data *jump_table_data = |
5213 | as_a <rtx_jump_table_data *> (rtx_alloc (JUMP_TABLE_DATA)); | |
39718607 SB |
5214 | INSN_UID (jump_table_data) = cur_insn_uid++; |
5215 | PATTERN (jump_table_data) = table; | |
5216 | BLOCK_FOR_INSN (jump_table_data) = NULL; | |
5217 | add_insn (jump_table_data); | |
5218 | return jump_table_data; | |
5219 | } | |
5220 | ||
23b2ce53 RS |
5221 | /* Make an insn of code BARRIER |
5222 | and add it to the end of the doubly-linked list. */ | |
5223 | ||
cd459bf8 | 5224 | rtx_barrier * |
502b8322 | 5225 | emit_barrier (void) |
23b2ce53 | 5226 | { |
cd459bf8 | 5227 | rtx_barrier *barrier = as_a <rtx_barrier *> (rtx_alloc (BARRIER)); |
23b2ce53 RS |
5228 | INSN_UID (barrier) = cur_insn_uid++; |
5229 | add_insn (barrier); | |
5230 | return barrier; | |
5231 | } | |
5232 | ||
5f2fc772 | 5233 | /* Emit a copy of note ORIG. */ |
502b8322 | 5234 | |
66e8df53 DM |
5235 | rtx_note * |
5236 | emit_note_copy (rtx_note *orig) | |
5f2fc772 | 5237 | { |
96fba521 | 5238 | enum insn_note kind = (enum insn_note) NOTE_KIND (orig); |
66e8df53 | 5239 | rtx_note *note = make_note_raw (kind); |
5f2fc772 | 5240 | NOTE_DATA (note) = NOTE_DATA (orig); |
5f2fc772 | 5241 | add_insn (note); |
2e040219 | 5242 | return note; |
23b2ce53 RS |
5243 | } |
5244 | ||
2e040219 NS |
5245 | /* Make an insn of code NOTE or type NOTE_NO |
5246 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 | 5247 | |
66e8df53 | 5248 | rtx_note * |
a38e7aa5 | 5249 | emit_note (enum insn_note kind) |
23b2ce53 | 5250 | { |
66e8df53 | 5251 | rtx_note *note = make_note_raw (kind); |
23b2ce53 RS |
5252 | add_insn (note); |
5253 | return note; | |
5254 | } | |
5255 | ||
c41c1387 RS |
5256 | /* Emit a clobber of lvalue X. */ |
5257 | ||
cd459bf8 | 5258 | rtx_insn * |
c41c1387 RS |
5259 | emit_clobber (rtx x) |
5260 | { | |
5261 | /* CONCATs should not appear in the insn stream. */ | |
5262 | if (GET_CODE (x) == CONCAT) | |
5263 | { | |
5264 | emit_clobber (XEXP (x, 0)); | |
5265 | return emit_clobber (XEXP (x, 1)); | |
5266 | } | |
5267 | return emit_insn (gen_rtx_CLOBBER (VOIDmode, x)); | |
5268 | } | |
5269 | ||
5270 | /* Return a sequence of insns to clobber lvalue X. */ | |
5271 | ||
cd459bf8 | 5272 | rtx_insn * |
c41c1387 RS |
5273 | gen_clobber (rtx x) |
5274 | { | |
cd459bf8 | 5275 | rtx_insn *seq; |
c41c1387 RS |
5276 | |
5277 | start_sequence (); | |
5278 | emit_clobber (x); | |
5279 | seq = get_insns (); | |
5280 | end_sequence (); | |
5281 | return seq; | |
5282 | } | |
5283 | ||
5284 | /* Emit a use of rvalue X. */ | |
5285 | ||
cd459bf8 | 5286 | rtx_insn * |
c41c1387 RS |
5287 | emit_use (rtx x) |
5288 | { | |
5289 | /* CONCATs should not appear in the insn stream. */ | |
5290 | if (GET_CODE (x) == CONCAT) | |
5291 | { | |
5292 | emit_use (XEXP (x, 0)); | |
5293 | return emit_use (XEXP (x, 1)); | |
5294 | } | |
5295 | return emit_insn (gen_rtx_USE (VOIDmode, x)); | |
5296 | } | |
5297 | ||
5298 | /* Return a sequence of insns to use rvalue X. */ | |
5299 | ||
cd459bf8 | 5300 | rtx_insn * |
c41c1387 RS |
5301 | gen_use (rtx x) |
5302 | { | |
cd459bf8 | 5303 | rtx_insn *seq; |
c41c1387 RS |
5304 | |
5305 | start_sequence (); | |
5306 | emit_use (x); | |
5307 | seq = get_insns (); | |
5308 | end_sequence (); | |
5309 | return seq; | |
5310 | } | |
5311 | ||
c8912e53 RS |
5312 | /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction. |
5313 | Return the set in INSN that such notes describe, or NULL if the notes | |
5314 | have no meaning for INSN. */ | |
5315 | ||
5316 | rtx | |
5317 | set_for_reg_notes (rtx insn) | |
5318 | { | |
5319 | rtx pat, reg; | |
5320 | ||
5321 | if (!INSN_P (insn)) | |
5322 | return NULL_RTX; | |
5323 | ||
5324 | pat = PATTERN (insn); | |
5325 | if (GET_CODE (pat) == PARALLEL) | |
5326 | { | |
5327 | /* We do not use single_set because that ignores SETs of unused | |
5328 | registers. REG_EQUAL and REG_EQUIV notes really do require the | |
5329 | PARALLEL to have a single SET. */ | |
5330 | if (multiple_sets (insn)) | |
5331 | return NULL_RTX; | |
5332 | pat = XVECEXP (pat, 0, 0); | |
5333 | } | |
5334 | ||
5335 | if (GET_CODE (pat) != SET) | |
5336 | return NULL_RTX; | |
5337 | ||
5338 | reg = SET_DEST (pat); | |
5339 | ||
5340 | /* Notes apply to the contents of a STRICT_LOW_PART. */ | |
7f7379f6 KV |
5341 | if (GET_CODE (reg) == STRICT_LOW_PART |
5342 | || GET_CODE (reg) == ZERO_EXTRACT) | |
c8912e53 RS |
5343 | reg = XEXP (reg, 0); |
5344 | ||
5345 | /* Check that we have a register. */ | |
5346 | if (!(REG_P (reg) || GET_CODE (reg) == SUBREG)) | |
5347 | return NULL_RTX; | |
5348 | ||
5349 | return pat; | |
5350 | } | |
5351 | ||
87b47c85 | 5352 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a |
30f7a378 | 5353 | note of this type already exists, remove it first. */ |
87b47c85 | 5354 | |
3d238248 | 5355 | rtx |
502b8322 | 5356 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
5357 | { |
5358 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
5359 | ||
52488da1 JW |
5360 | switch (kind) |
5361 | { | |
5362 | case REG_EQUAL: | |
5363 | case REG_EQUIV: | |
8073cbd4 EB |
5364 | /* We need to support the REG_EQUAL on USE trick of find_reloads. */ |
5365 | if (!set_for_reg_notes (insn) && GET_CODE (PATTERN (insn)) != USE) | |
c8912e53 | 5366 | return NULL_RTX; |
52488da1 JW |
5367 | |
5368 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
5369 | It serves no useful purpose and breaks eliminate_regs. */ | |
5370 | if (GET_CODE (datum) == ASM_OPERANDS) | |
5371 | return NULL_RTX; | |
109374e2 RS |
5372 | |
5373 | /* Notes with side effects are dangerous. Even if the side-effect | |
5374 | initially mirrors one in PATTERN (INSN), later optimizations | |
5375 | might alter the way that the final register value is calculated | |
5376 | and so move or alter the side-effect in some way. The note would | |
5377 | then no longer be a valid substitution for SET_SRC. */ | |
5378 | if (side_effects_p (datum)) | |
5379 | return NULL_RTX; | |
52488da1 JW |
5380 | break; |
5381 | ||
5382 | default: | |
5383 | break; | |
5384 | } | |
3d238248 | 5385 | |
c8912e53 RS |
5386 | if (note) |
5387 | XEXP (note, 0) = datum; | |
5388 | else | |
5389 | { | |
5390 | add_reg_note (insn, kind, datum); | |
5391 | note = REG_NOTES (insn); | |
5392 | } | |
6fb5fa3c DB |
5393 | |
5394 | switch (kind) | |
3d238248 | 5395 | { |
6fb5fa3c DB |
5396 | case REG_EQUAL: |
5397 | case REG_EQUIV: | |
b2908ba6 | 5398 | df_notes_rescan (as_a <rtx_insn *> (insn)); |
6fb5fa3c DB |
5399 | break; |
5400 | default: | |
5401 | break; | |
3d238248 | 5402 | } |
87b47c85 | 5403 | |
c8912e53 | 5404 | return note; |
87b47c85 | 5405 | } |
7543f918 JR |
5406 | |
5407 | /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */ | |
5408 | rtx | |
5409 | set_dst_reg_note (rtx insn, enum reg_note kind, rtx datum, rtx dst) | |
5410 | { | |
c8912e53 | 5411 | rtx set = set_for_reg_notes (insn); |
7543f918 JR |
5412 | |
5413 | if (set && SET_DEST (set) == dst) | |
5414 | return set_unique_reg_note (insn, kind, datum); | |
5415 | return NULL_RTX; | |
5416 | } | |
23b2ce53 | 5417 | \f |
9d8895c9 RS |
5418 | /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a |
5419 | following barrier if the instruction needs one and if ALLOW_BARRIER_P | |
5420 | is true. | |
5421 | ||
23b2ce53 RS |
5422 | If X is a label, it is simply added into the insn chain. */ |
5423 | ||
cd459bf8 | 5424 | rtx_insn * |
9d8895c9 | 5425 | emit (rtx x, bool allow_barrier_p) |
23b2ce53 RS |
5426 | { |
5427 | enum rtx_code code = classify_insn (x); | |
5428 | ||
5b0264cb | 5429 | switch (code) |
23b2ce53 | 5430 | { |
5b0264cb NS |
5431 | case CODE_LABEL: |
5432 | return emit_label (x); | |
5433 | case INSN: | |
5434 | return emit_insn (x); | |
5435 | case JUMP_INSN: | |
5436 | { | |
cd459bf8 | 5437 | rtx_insn *insn = emit_jump_insn (x); |
9d8895c9 RS |
5438 | if (allow_barrier_p |
5439 | && (any_uncondjump_p (insn) || GET_CODE (x) == RETURN)) | |
5b0264cb NS |
5440 | return emit_barrier (); |
5441 | return insn; | |
5442 | } | |
5443 | case CALL_INSN: | |
5444 | return emit_call_insn (x); | |
b5b8b0ac AO |
5445 | case DEBUG_INSN: |
5446 | return emit_debug_insn (x); | |
5b0264cb NS |
5447 | default: |
5448 | gcc_unreachable (); | |
23b2ce53 | 5449 | } |
23b2ce53 RS |
5450 | } |
5451 | \f | |
e2500fed | 5452 | /* Space for free sequence stack entries. */ |
1431042e | 5453 | static GTY ((deletable)) struct sequence_stack *free_sequence_stack; |
e2500fed | 5454 | |
4dfa0342 RH |
5455 | /* Begin emitting insns to a sequence. If this sequence will contain |
5456 | something that might cause the compiler to pop arguments to function | |
5457 | calls (because those pops have previously been deferred; see | |
5458 | INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust | |
5459 | before calling this function. That will ensure that the deferred | |
5460 | pops are not accidentally emitted in the middle of this sequence. */ | |
23b2ce53 RS |
5461 | |
5462 | void | |
502b8322 | 5463 | start_sequence (void) |
23b2ce53 RS |
5464 | { |
5465 | struct sequence_stack *tem; | |
5466 | ||
e2500fed GK |
5467 | if (free_sequence_stack != NULL) |
5468 | { | |
5469 | tem = free_sequence_stack; | |
5470 | free_sequence_stack = tem->next; | |
5471 | } | |
5472 | else | |
766090c2 | 5473 | tem = ggc_alloc<sequence_stack> (); |
23b2ce53 | 5474 | |
614d5bd8 | 5475 | tem->next = get_current_sequence ()->next; |
5936d944 JH |
5476 | tem->first = get_insns (); |
5477 | tem->last = get_last_insn (); | |
614d5bd8 | 5478 | get_current_sequence ()->next = tem; |
23b2ce53 | 5479 | |
5936d944 JH |
5480 | set_first_insn (0); |
5481 | set_last_insn (0); | |
23b2ce53 RS |
5482 | } |
5483 | ||
5c7a310f MM |
5484 | /* Set up the insn chain starting with FIRST as the current sequence, |
5485 | saving the previously current one. See the documentation for | |
5486 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
5487 | |
5488 | void | |
fee3e72c | 5489 | push_to_sequence (rtx_insn *first) |
23b2ce53 | 5490 | { |
fee3e72c | 5491 | rtx_insn *last; |
23b2ce53 RS |
5492 | |
5493 | start_sequence (); | |
5494 | ||
e84a58ff EB |
5495 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)) |
5496 | ; | |
23b2ce53 | 5497 | |
5936d944 JH |
5498 | set_first_insn (first); |
5499 | set_last_insn (last); | |
23b2ce53 RS |
5500 | } |
5501 | ||
bb27eeda SE |
5502 | /* Like push_to_sequence, but take the last insn as an argument to avoid |
5503 | looping through the list. */ | |
5504 | ||
5505 | void | |
fee3e72c | 5506 | push_to_sequence2 (rtx_insn *first, rtx_insn *last) |
bb27eeda SE |
5507 | { |
5508 | start_sequence (); | |
5509 | ||
5936d944 JH |
5510 | set_first_insn (first); |
5511 | set_last_insn (last); | |
bb27eeda SE |
5512 | } |
5513 | ||
f15ae3a1 TW |
5514 | /* Set up the outer-level insn chain |
5515 | as the current sequence, saving the previously current one. */ | |
5516 | ||
5517 | void | |
502b8322 | 5518 | push_topmost_sequence (void) |
f15ae3a1 | 5519 | { |
614d5bd8 | 5520 | struct sequence_stack *top; |
f15ae3a1 TW |
5521 | |
5522 | start_sequence (); | |
5523 | ||
614d5bd8 | 5524 | top = get_topmost_sequence (); |
5936d944 JH |
5525 | set_first_insn (top->first); |
5526 | set_last_insn (top->last); | |
f15ae3a1 TW |
5527 | } |
5528 | ||
5529 | /* After emitting to the outer-level insn chain, update the outer-level | |
5530 | insn chain, and restore the previous saved state. */ | |
5531 | ||
5532 | void | |
502b8322 | 5533 | pop_topmost_sequence (void) |
f15ae3a1 | 5534 | { |
614d5bd8 | 5535 | struct sequence_stack *top; |
f15ae3a1 | 5536 | |
614d5bd8 | 5537 | top = get_topmost_sequence (); |
5936d944 JH |
5538 | top->first = get_insns (); |
5539 | top->last = get_last_insn (); | |
f15ae3a1 TW |
5540 | |
5541 | end_sequence (); | |
5542 | } | |
5543 | ||
23b2ce53 RS |
5544 | /* After emitting to a sequence, restore previous saved state. |
5545 | ||
5c7a310f | 5546 | To get the contents of the sequence just made, you must call |
2f937369 | 5547 | `get_insns' *before* calling here. |
5c7a310f MM |
5548 | |
5549 | If the compiler might have deferred popping arguments while | |
5550 | generating this sequence, and this sequence will not be immediately | |
5551 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 5552 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
5553 | pops are inserted into this sequence, and not into some random |
5554 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
5555 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
5556 | |
5557 | void | |
502b8322 | 5558 | end_sequence (void) |
23b2ce53 | 5559 | { |
614d5bd8 | 5560 | struct sequence_stack *tem = get_current_sequence ()->next; |
23b2ce53 | 5561 | |
5936d944 JH |
5562 | set_first_insn (tem->first); |
5563 | set_last_insn (tem->last); | |
614d5bd8 | 5564 | get_current_sequence ()->next = tem->next; |
23b2ce53 | 5565 | |
e2500fed GK |
5566 | memset (tem, 0, sizeof (*tem)); |
5567 | tem->next = free_sequence_stack; | |
5568 | free_sequence_stack = tem; | |
23b2ce53 RS |
5569 | } |
5570 | ||
5571 | /* Return 1 if currently emitting into a sequence. */ | |
5572 | ||
5573 | int | |
502b8322 | 5574 | in_sequence_p (void) |
23b2ce53 | 5575 | { |
614d5bd8 | 5576 | return get_current_sequence ()->next != 0; |
23b2ce53 | 5577 | } |
23b2ce53 | 5578 | \f |
59ec66dc MM |
5579 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5580 | ||
2bbdec73 | 5581 | static void |
bd60bab2 | 5582 | init_virtual_regs (void) |
59ec66dc | 5583 | { |
bd60bab2 JH |
5584 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; |
5585 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5586 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5587 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5588 | regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
32990d5b JJ |
5589 | regno_reg_rtx[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM] |
5590 | = virtual_preferred_stack_boundary_rtx; | |
49ad7cfa BS |
5591 | } |
5592 | ||
da43a810 BS |
5593 | \f |
5594 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5595 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5596 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5597 | static int copy_insn_n_scratches; | |
5598 | ||
5599 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5600 | copied an ASM_OPERANDS. | |
5601 | In that case, it is the original input-operand vector. */ | |
5602 | static rtvec orig_asm_operands_vector; | |
5603 | ||
5604 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5605 | copied an ASM_OPERANDS. | |
5606 | In that case, it is the copied input-operand vector. */ | |
5607 | static rtvec copy_asm_operands_vector; | |
5608 | ||
5609 | /* Likewise for the constraints vector. */ | |
5610 | static rtvec orig_asm_constraints_vector; | |
5611 | static rtvec copy_asm_constraints_vector; | |
5612 | ||
5613 | /* Recursively create a new copy of an rtx for copy_insn. | |
5614 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5615 | ASM_OPERANDs properly. | |
5616 | Normally, this function is not used directly; use copy_insn as front end. | |
5617 | However, you could first copy an insn pattern with copy_insn and then use | |
5618 | this function afterwards to properly copy any REG_NOTEs containing | |
5619 | SCRATCHes. */ | |
5620 | ||
5621 | rtx | |
502b8322 | 5622 | copy_insn_1 (rtx orig) |
da43a810 | 5623 | { |
b3694847 SS |
5624 | rtx copy; |
5625 | int i, j; | |
5626 | RTX_CODE code; | |
5627 | const char *format_ptr; | |
da43a810 | 5628 | |
cd9c1ca8 RH |
5629 | if (orig == NULL) |
5630 | return NULL; | |
5631 | ||
da43a810 BS |
5632 | code = GET_CODE (orig); |
5633 | ||
5634 | switch (code) | |
5635 | { | |
5636 | case REG: | |
a52a87c3 | 5637 | case DEBUG_EXPR: |
d8116890 | 5638 | CASE_CONST_ANY: |
da43a810 BS |
5639 | case SYMBOL_REF: |
5640 | case CODE_LABEL: | |
5641 | case PC: | |
276e0224 | 5642 | case RETURN: |
26898771 | 5643 | case SIMPLE_RETURN: |
da43a810 | 5644 | return orig; |
3e89ed8d | 5645 | case CLOBBER: |
bd1cd0d0 | 5646 | /* Share clobbers of hard registers, but do not share pseudo reg |
c5c5ba89 JH |
5647 | clobbers or clobbers of hard registers that originated as pseudos. |
5648 | This is needed to allow safe register renaming. */ | |
d7ae3739 EB |
5649 | if (REG_P (XEXP (orig, 0)) |
5650 | && HARD_REGISTER_NUM_P (REGNO (XEXP (orig, 0))) | |
5651 | && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig, 0)))) | |
3e89ed8d JH |
5652 | return orig; |
5653 | break; | |
da43a810 BS |
5654 | |
5655 | case SCRATCH: | |
5656 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5657 | if (copy_insn_scratch_in[i] == orig) | |
5658 | return copy_insn_scratch_out[i]; | |
5659 | break; | |
5660 | ||
5661 | case CONST: | |
6fb5fa3c | 5662 | if (shared_const_p (orig)) |
da43a810 BS |
5663 | return orig; |
5664 | break; | |
750c9258 | 5665 | |
da43a810 BS |
5666 | /* A MEM with a constant address is not sharable. The problem is that |
5667 | the constant address may need to be reloaded. If the mem is shared, | |
5668 | then reloading one copy of this mem will cause all copies to appear | |
5669 | to have been reloaded. */ | |
5670 | ||
5671 | default: | |
5672 | break; | |
5673 | } | |
5674 | ||
aacd3885 RS |
5675 | /* Copy the various flags, fields, and other information. We assume |
5676 | that all fields need copying, and then clear the fields that should | |
da43a810 BS |
5677 | not be copied. That is the sensible default behavior, and forces |
5678 | us to explicitly document why we are *not* copying a flag. */ | |
aacd3885 | 5679 | copy = shallow_copy_rtx (orig); |
da43a810 | 5680 | |
da43a810 | 5681 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ |
ec8e098d | 5682 | if (INSN_P (orig)) |
da43a810 | 5683 | { |
2adc7f12 JJ |
5684 | RTX_FLAG (copy, jump) = 0; |
5685 | RTX_FLAG (copy, call) = 0; | |
5686 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5687 | } |
750c9258 | 5688 | |
da43a810 BS |
5689 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5690 | ||
5691 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
aacd3885 RS |
5692 | switch (*format_ptr++) |
5693 | { | |
5694 | case 'e': | |
5695 | if (XEXP (orig, i) != NULL) | |
5696 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5697 | break; | |
da43a810 | 5698 | |
aacd3885 RS |
5699 | case 'E': |
5700 | case 'V': | |
5701 | if (XVEC (orig, i) == orig_asm_constraints_vector) | |
5702 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5703 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5704 | XVEC (copy, i) = copy_asm_operands_vector; | |
5705 | else if (XVEC (orig, i) != NULL) | |
5706 | { | |
5707 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5708 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5709 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5710 | } | |
5711 | break; | |
da43a810 | 5712 | |
aacd3885 RS |
5713 | case 't': |
5714 | case 'w': | |
5715 | case 'i': | |
91914e56 | 5716 | case 'p': |
aacd3885 RS |
5717 | case 's': |
5718 | case 'S': | |
5719 | case 'u': | |
5720 | case '0': | |
5721 | /* These are left unchanged. */ | |
5722 | break; | |
da43a810 | 5723 | |
aacd3885 RS |
5724 | default: |
5725 | gcc_unreachable (); | |
5726 | } | |
da43a810 BS |
5727 | |
5728 | if (code == SCRATCH) | |
5729 | { | |
5730 | i = copy_insn_n_scratches++; | |
5b0264cb | 5731 | gcc_assert (i < MAX_RECOG_OPERANDS); |
da43a810 BS |
5732 | copy_insn_scratch_in[i] = orig; |
5733 | copy_insn_scratch_out[i] = copy; | |
5734 | } | |
5735 | else if (code == ASM_OPERANDS) | |
5736 | { | |
6462bb43 AO |
5737 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5738 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5739 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5740 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5741 | } |
5742 | ||
5743 | return copy; | |
5744 | } | |
5745 | ||
5746 | /* Create a new copy of an rtx. | |
5747 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5748 | ASM_OPERANDs properly. | |
5749 | INSN doesn't really have to be a full INSN; it could be just the | |
5750 | pattern. */ | |
5751 | rtx | |
502b8322 | 5752 | copy_insn (rtx insn) |
da43a810 BS |
5753 | { |
5754 | copy_insn_n_scratches = 0; | |
5755 | orig_asm_operands_vector = 0; | |
5756 | orig_asm_constraints_vector = 0; | |
5757 | copy_asm_operands_vector = 0; | |
5758 | copy_asm_constraints_vector = 0; | |
5759 | return copy_insn_1 (insn); | |
5760 | } | |
59ec66dc | 5761 | |
8e383849 JR |
5762 | /* Return a copy of INSN that can be used in a SEQUENCE delay slot, |
5763 | on that assumption that INSN itself remains in its original place. */ | |
5764 | ||
f8f0516e DM |
5765 | rtx_insn * |
5766 | copy_delay_slot_insn (rtx_insn *insn) | |
8e383849 JR |
5767 | { |
5768 | /* Copy INSN with its rtx_code, all its notes, location etc. */ | |
f8f0516e | 5769 | insn = as_a <rtx_insn *> (copy_rtx (insn)); |
8e383849 JR |
5770 | INSN_UID (insn) = cur_insn_uid++; |
5771 | return insn; | |
5772 | } | |
5773 | ||
23b2ce53 RS |
5774 | /* Initialize data structures and variables in this file |
5775 | before generating rtl for each function. */ | |
5776 | ||
5777 | void | |
502b8322 | 5778 | init_emit (void) |
23b2ce53 | 5779 | { |
5936d944 JH |
5780 | set_first_insn (NULL); |
5781 | set_last_insn (NULL); | |
028d4092 ML |
5782 | if (param_min_nondebug_insn_uid) |
5783 | cur_insn_uid = param_min_nondebug_insn_uid; | |
b5b8b0ac AO |
5784 | else |
5785 | cur_insn_uid = 1; | |
5786 | cur_debug_insn_uid = 1; | |
23b2ce53 | 5787 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; |
23b2ce53 | 5788 | first_label_num = label_num; |
614d5bd8 | 5789 | get_current_sequence ()->next = NULL; |
23b2ce53 | 5790 | |
23b2ce53 RS |
5791 | /* Init the tables that describe all the pseudo regs. */ |
5792 | ||
3e029763 | 5793 | crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5794 | |
3e029763 | 5795 | crtl->emit.regno_pointer_align |
1b4572a8 | 5796 | = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length); |
86fe05e0 | 5797 | |
f44986d7 DM |
5798 | regno_reg_rtx |
5799 | = ggc_cleared_vec_alloc<rtx> (crtl->emit.regno_pointer_align_length); | |
0d4903b8 | 5800 | |
e50126e8 | 5801 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 | 5802 | memcpy (regno_reg_rtx, |
5fb0e246 | 5803 | initial_regno_reg_rtx, |
6cde4876 | 5804 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
e50126e8 | 5805 | |
23b2ce53 | 5806 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
bd60bab2 | 5807 | init_virtual_regs (); |
740ab4a2 RK |
5808 | |
5809 | /* Indicate that the virtual registers and stack locations are | |
5810 | all pointers. */ | |
3502dc9c JDA |
5811 | REG_POINTER (stack_pointer_rtx) = 1; |
5812 | REG_POINTER (frame_pointer_rtx) = 1; | |
5813 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5814 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5815 | |
3502dc9c JDA |
5816 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5817 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5818 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5819 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5820 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5821 | |
86fe05e0 | 5822 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5823 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5824 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5825 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5826 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5827 | ||
5828 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5829 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5830 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5831 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
da75ca93 | 5832 | |
bdb429a5 | 5833 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; |
86fe05e0 RK |
5834 | #endif |
5835 | ||
5e82e7bd JVA |
5836 | #ifdef INIT_EXPANDERS |
5837 | INIT_EXPANDERS; | |
5838 | #endif | |
23b2ce53 RS |
5839 | } |
5840 | ||
cd5ff7bc RS |
5841 | /* Return the value of element I of CONST_VECTOR X as a wide_int. */ |
5842 | ||
5843 | wide_int | |
5844 | const_vector_int_elt (const_rtx x, unsigned int i) | |
5845 | { | |
5846 | /* First handle elements that are directly encoded. */ | |
5847 | machine_mode elt_mode = GET_MODE_INNER (GET_MODE (x)); | |
5848 | if (i < (unsigned int) XVECLEN (x, 0)) | |
5849 | return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x, i), elt_mode); | |
5850 | ||
5851 | /* Identify the pattern that contains element I and work out the index of | |
5852 | the last encoded element for that pattern. */ | |
5853 | unsigned int encoded_nelts = const_vector_encoded_nelts (x); | |
5854 | unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); | |
5855 | unsigned int count = i / npatterns; | |
5856 | unsigned int pattern = i % npatterns; | |
5857 | unsigned int final_i = encoded_nelts - npatterns + pattern; | |
5858 | ||
5859 | /* If there are no steps, the final encoded value is the right one. */ | |
5860 | if (!CONST_VECTOR_STEPPED_P (x)) | |
5861 | return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x, final_i), elt_mode); | |
5862 | ||
5863 | /* Otherwise work out the value from the last two encoded elements. */ | |
5864 | rtx v1 = CONST_VECTOR_ENCODED_ELT (x, final_i - npatterns); | |
5865 | rtx v2 = CONST_VECTOR_ENCODED_ELT (x, final_i); | |
5866 | wide_int diff = wi::sub (rtx_mode_t (v2, elt_mode), | |
5867 | rtx_mode_t (v1, elt_mode)); | |
5868 | return wi::add (rtx_mode_t (v2, elt_mode), (count - 2) * diff); | |
5869 | } | |
5870 | ||
5871 | /* Return the value of element I of CONST_VECTOR X. */ | |
5872 | ||
5873 | rtx | |
5874 | const_vector_elt (const_rtx x, unsigned int i) | |
5875 | { | |
5876 | /* First handle elements that are directly encoded. */ | |
5877 | if (i < (unsigned int) XVECLEN (x, 0)) | |
5878 | return CONST_VECTOR_ENCODED_ELT (x, i); | |
5879 | ||
5880 | /* If there are no steps, the final encoded value is the right one. */ | |
5881 | if (!CONST_VECTOR_STEPPED_P (x)) | |
5882 | { | |
5883 | /* Identify the pattern that contains element I and work out the index of | |
5884 | the last encoded element for that pattern. */ | |
5885 | unsigned int encoded_nelts = const_vector_encoded_nelts (x); | |
5886 | unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); | |
5887 | unsigned int pattern = i % npatterns; | |
5888 | unsigned int final_i = encoded_nelts - npatterns + pattern; | |
5889 | return CONST_VECTOR_ENCODED_ELT (x, final_i); | |
5890 | } | |
5891 | ||
5892 | /* Otherwise work out the value from the last two encoded elements. */ | |
5893 | return immed_wide_int_const (const_vector_int_elt (x, i), | |
5894 | GET_MODE_INNER (GET_MODE (x))); | |
5895 | } | |
5896 | ||
c0cc00c4 JJ |
5897 | /* Return true if X is a valid element for a CONST_VECTOR of the given |
5898 | mode. */ | |
9b4473b6 RS |
5899 | |
5900 | bool | |
c0cc00c4 | 5901 | valid_for_const_vector_p (machine_mode, rtx x) |
9b4473b6 RS |
5902 | { |
5903 | return (CONST_SCALAR_INT_P (x) | |
1b5f74e8 | 5904 | || CONST_POLY_INT_P (x) |
9b4473b6 RS |
5905 | || CONST_DOUBLE_AS_FLOAT_P (x) |
5906 | || CONST_FIXED_P (x)); | |
5907 | } | |
5908 | ||
59d06c05 RS |
5909 | /* Generate a vector constant of mode MODE in which every element has |
5910 | value ELT. */ | |
69ef87e2 | 5911 | |
59d06c05 RS |
5912 | rtx |
5913 | gen_const_vec_duplicate (machine_mode mode, rtx elt) | |
5914 | { | |
3877c560 RS |
5915 | rtx_vector_builder builder (mode, 1, 1); |
5916 | builder.quick_push (elt); | |
5917 | return builder.build (); | |
59d06c05 RS |
5918 | } |
5919 | ||
5920 | /* Return a vector rtx of mode MODE in which every element has value X. | |
5921 | The result will be a constant if X is constant. */ | |
5922 | ||
5923 | rtx | |
5924 | gen_vec_duplicate (machine_mode mode, rtx x) | |
5925 | { | |
c0cc00c4 | 5926 | if (valid_for_const_vector_p (mode, x)) |
59d06c05 RS |
5927 | return gen_const_vec_duplicate (mode, x); |
5928 | return gen_rtx_VEC_DUPLICATE (mode, x); | |
5929 | } | |
15ed7b52 | 5930 | |
3877c560 RS |
5931 | /* A subroutine of const_vec_series_p that handles the case in which: |
5932 | ||
5933 | (GET_CODE (X) == CONST_VECTOR | |
5934 | && CONST_VECTOR_NPATTERNS (X) == 1 | |
5935 | && !CONST_VECTOR_DUPLICATE_P (X)) | |
5936 | ||
5937 | is known to hold. */ | |
ef339d6e RS |
5938 | |
5939 | bool | |
5940 | const_vec_series_p_1 (const_rtx x, rtx *base_out, rtx *step_out) | |
5941 | { | |
3877c560 RS |
5942 | /* Stepped sequences are only defined for integers, to avoid specifying |
5943 | rounding behavior. */ | |
5944 | if (GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT) | |
5945 | return false; | |
5946 | ||
5947 | /* A non-duplicated vector with two elements can always be seen as a | |
5948 | series with a nonzero step. Longer vectors must have a stepped | |
5949 | encoding. */ | |
7b777afa | 5950 | if (maybe_ne (CONST_VECTOR_NUNITS (x), 2) |
3877c560 | 5951 | && !CONST_VECTOR_STEPPED_P (x)) |
ef339d6e RS |
5952 | return false; |
5953 | ||
3877c560 | 5954 | /* Calculate the step between the first and second elements. */ |
ef339d6e RS |
5955 | scalar_mode inner = GET_MODE_INNER (GET_MODE (x)); |
5956 | rtx base = CONST_VECTOR_ELT (x, 0); | |
5957 | rtx step = simplify_binary_operation (MINUS, inner, | |
3877c560 | 5958 | CONST_VECTOR_ENCODED_ELT (x, 1), base); |
ef339d6e RS |
5959 | if (rtx_equal_p (step, CONST0_RTX (inner))) |
5960 | return false; | |
5961 | ||
3877c560 RS |
5962 | /* If we have a stepped encoding, check that the step between the |
5963 | second and third elements is the same as STEP. */ | |
5964 | if (CONST_VECTOR_STEPPED_P (x)) | |
ef339d6e RS |
5965 | { |
5966 | rtx diff = simplify_binary_operation (MINUS, inner, | |
3877c560 RS |
5967 | CONST_VECTOR_ENCODED_ELT (x, 2), |
5968 | CONST_VECTOR_ENCODED_ELT (x, 1)); | |
ef339d6e RS |
5969 | if (!rtx_equal_p (step, diff)) |
5970 | return false; | |
5971 | } | |
5972 | ||
5973 | *base_out = base; | |
5974 | *step_out = step; | |
5975 | return true; | |
5976 | } | |
5977 | ||
5978 | /* Generate a vector constant of mode MODE in which element I has | |
5979 | the value BASE + I * STEP. */ | |
5980 | ||
5981 | rtx | |
5982 | gen_const_vec_series (machine_mode mode, rtx base, rtx step) | |
5983 | { | |
af2e4475 RS |
5984 | gcc_assert (valid_for_const_vector_p (mode, base) |
5985 | && valid_for_const_vector_p (mode, step)); | |
ef339d6e | 5986 | |
3877c560 RS |
5987 | rtx_vector_builder builder (mode, 1, 3); |
5988 | builder.quick_push (base); | |
5989 | for (int i = 1; i < 3; ++i) | |
5990 | builder.quick_push (simplify_gen_binary (PLUS, GET_MODE_INNER (mode), | |
5991 | builder[i - 1], step)); | |
5992 | return builder.build (); | |
ef339d6e RS |
5993 | } |
5994 | ||
5995 | /* Generate a vector of mode MODE in which element I has the value | |
5996 | BASE + I * STEP. The result will be a constant if BASE and STEP | |
5997 | are both constants. */ | |
5998 | ||
5999 | rtx | |
6000 | gen_vec_series (machine_mode mode, rtx base, rtx step) | |
6001 | { | |
6002 | if (step == const0_rtx) | |
6003 | return gen_vec_duplicate (mode, base); | |
af2e4475 RS |
6004 | if (valid_for_const_vector_p (mode, base) |
6005 | && valid_for_const_vector_p (mode, step)) | |
ef339d6e RS |
6006 | return gen_const_vec_series (mode, base, step); |
6007 | return gen_rtx_VEC_SERIES (mode, base, step); | |
6008 | } | |
6009 | ||
59d06c05 RS |
6010 | /* Generate a new vector constant for mode MODE and constant value |
6011 | CONSTANT. */ | |
69ef87e2 | 6012 | |
59d06c05 RS |
6013 | static rtx |
6014 | gen_const_vector (machine_mode mode, int constant) | |
6015 | { | |
6016 | machine_mode inner = GET_MODE_INNER (mode); | |
69ef87e2 | 6017 | |
59d06c05 RS |
6018 | gcc_assert (!DECIMAL_FLOAT_MODE_P (inner)); |
6019 | ||
6020 | rtx el = const_tiny_rtx[constant][(int) inner]; | |
6021 | gcc_assert (el); | |
69ef87e2 | 6022 | |
3877c560 | 6023 | return gen_const_vec_duplicate (mode, el); |
69ef87e2 AH |
6024 | } |
6025 | ||
a06e3c40 | 6026 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
a73b091d | 6027 | all elements are zero, and the one vector when all elements are one. */ |
a06e3c40 | 6028 | rtx |
ef4bddc2 | 6029 | gen_rtx_CONST_VECTOR (machine_mode mode, rtvec v) |
a06e3c40 | 6030 | { |
7b777afa | 6031 | gcc_assert (known_eq (GET_MODE_NUNITS (mode), GET_NUM_ELEM (v))); |
a73b091d JW |
6032 | |
6033 | /* If the values are all the same, check to see if we can use one of the | |
6034 | standard constant vectors. */ | |
59d06c05 RS |
6035 | if (rtvec_all_equal_p (v)) |
6036 | return gen_const_vec_duplicate (mode, RTVEC_ELT (v, 0)); | |
a73b091d | 6037 | |
3877c560 RS |
6038 | unsigned int nunits = GET_NUM_ELEM (v); |
6039 | rtx_vector_builder builder (mode, nunits, 1); | |
6040 | for (unsigned int i = 0; i < nunits; ++i) | |
6041 | builder.quick_push (RTVEC_ELT (v, i)); | |
6042 | return builder.build (v); | |
a06e3c40 R |
6043 | } |
6044 | ||
b5deb7b6 SL |
6045 | /* Initialise global register information required by all functions. */ |
6046 | ||
6047 | void | |
6048 | init_emit_regs (void) | |
6049 | { | |
6050 | int i; | |
ef4bddc2 | 6051 | machine_mode mode; |
1c3f523e | 6052 | mem_attrs *attrs; |
b5deb7b6 SL |
6053 | |
6054 | /* Reset register attributes */ | |
aebf76a2 | 6055 | reg_attrs_htab->empty (); |
b5deb7b6 SL |
6056 | |
6057 | /* We need reg_raw_mode, so initialize the modes now. */ | |
6058 | init_reg_modes_target (); | |
6059 | ||
6060 | /* Assign register numbers to the globally defined register rtx. */ | |
b5deb7b6 SL |
6061 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
6062 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
6063 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
6064 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
6065 | virtual_incoming_args_rtx = | |
6066 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
6067 | virtual_stack_vars_rtx = | |
6068 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
6069 | virtual_stack_dynamic_rtx = | |
6070 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
6071 | virtual_outgoing_args_rtx = | |
6072 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
6073 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
32990d5b JJ |
6074 | virtual_preferred_stack_boundary_rtx = |
6075 | gen_raw_REG (Pmode, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM); | |
b5deb7b6 SL |
6076 | |
6077 | /* Initialize RTL for commonly used hard registers. These are | |
6078 | copied into regno_reg_rtx as we begin to compile each function. */ | |
6079 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5fb0e246 | 6080 | initial_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); |
b5deb7b6 SL |
6081 | |
6082 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
6083 | return_address_pointer_rtx | |
6084 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
6085 | #endif | |
6086 | ||
ca72dad5 | 6087 | pic_offset_table_rtx = NULL_RTX; |
b5deb7b6 SL |
6088 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
6089 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
1c3f523e RS |
6090 | |
6091 | for (i = 0; i < (int) MAX_MACHINE_MODE; i++) | |
6092 | { | |
ef4bddc2 | 6093 | mode = (machine_mode) i; |
766090c2 | 6094 | attrs = ggc_cleared_alloc<mem_attrs> (); |
1c3f523e RS |
6095 | attrs->align = BITS_PER_UNIT; |
6096 | attrs->addrspace = ADDR_SPACE_GENERIC; | |
532c7a45 | 6097 | if (mode != BLKmode && mode != VOIDmode) |
1c3f523e | 6098 | { |
754c3d5d RS |
6099 | attrs->size_known_p = true; |
6100 | attrs->size = GET_MODE_SIZE (mode); | |
1c3f523e RS |
6101 | if (STRICT_ALIGNMENT) |
6102 | attrs->align = GET_MODE_ALIGNMENT (mode); | |
6103 | } | |
6104 | mode_mem_attrs[i] = attrs; | |
6105 | } | |
af364399 ML |
6106 | |
6107 | split_branch_probability = profile_probability::uninitialized (); | |
b5deb7b6 SL |
6108 | } |
6109 | ||
aa3a12d6 RS |
6110 | /* Initialize global machine_mode variables. */ |
6111 | ||
6112 | void | |
6113 | init_derived_machine_modes (void) | |
6114 | { | |
501623d4 RS |
6115 | opt_scalar_int_mode mode_iter, opt_byte_mode, opt_word_mode; |
6116 | FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT) | |
aa3a12d6 | 6117 | { |
501623d4 RS |
6118 | scalar_int_mode mode = mode_iter.require (); |
6119 | ||
aa3a12d6 | 6120 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT |
501623d4 RS |
6121 | && !opt_byte_mode.exists ()) |
6122 | opt_byte_mode = mode; | |
aa3a12d6 RS |
6123 | |
6124 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
501623d4 RS |
6125 | && !opt_word_mode.exists ()) |
6126 | opt_word_mode = mode; | |
aa3a12d6 RS |
6127 | } |
6128 | ||
501623d4 RS |
6129 | byte_mode = opt_byte_mode.require (); |
6130 | word_mode = opt_word_mode.require (); | |
f95c5b8e RS |
6131 | ptr_mode = as_a <scalar_int_mode> |
6132 | (mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0).require ()); | |
aa3a12d6 RS |
6133 | } |
6134 | ||
2d888286 | 6135 | /* Create some permanent unique rtl objects shared between all functions. */ |
23b2ce53 RS |
6136 | |
6137 | void | |
2d888286 | 6138 | init_emit_once (void) |
23b2ce53 RS |
6139 | { |
6140 | int i; | |
ef4bddc2 | 6141 | machine_mode mode; |
857c7b46 | 6142 | scalar_float_mode double_mode; |
16d22000 | 6143 | opt_scalar_mode smode_iter; |
23b2ce53 | 6144 | |
807e902e KZ |
6145 | /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE, |
6146 | CONST_FIXED, and memory attribute hash tables. */ | |
aebf76a2 | 6147 | const_int_htab = hash_table<const_int_hasher>::create_ggc (37); |
173b24b9 | 6148 | |
807e902e | 6149 | #if TARGET_SUPPORTS_WIDE_INT |
aebf76a2 | 6150 | const_wide_int_htab = hash_table<const_wide_int_hasher>::create_ggc (37); |
807e902e | 6151 | #endif |
aebf76a2 | 6152 | const_double_htab = hash_table<const_double_hasher>::create_ggc (37); |
5692c7bc | 6153 | |
0c12fc9b RS |
6154 | if (NUM_POLY_INT_COEFFS > 1) |
6155 | const_poly_int_htab = hash_table<const_poly_int_hasher>::create_ggc (37); | |
6156 | ||
aebf76a2 | 6157 | const_fixed_htab = hash_table<const_fixed_hasher>::create_ggc (37); |
091a3ac7 | 6158 | |
aebf76a2 | 6159 | reg_attrs_htab = hash_table<reg_attr_hasher>::create_ggc (37); |
67673f5c | 6160 | |
5da077de | 6161 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
6162 | /* This is to initialize {init|mark|free}_machine_status before the first |
6163 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 6164 | end which calls push_function_context_to before the first call to |
5da077de AS |
6165 | init_function_start. */ |
6166 | INIT_EXPANDERS; | |
6167 | #endif | |
6168 | ||
23b2ce53 RS |
6169 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
6170 | ||
ecf835e9 KN |
6171 | /* Process stack-limiting command-line options. */ |
6172 | if (opt_fstack_limit_symbol_arg != NULL) | |
6173 | stack_limit_rtx | |
6174 | = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (opt_fstack_limit_symbol_arg)); | |
6175 | if (opt_fstack_limit_register_no >= 0) | |
6176 | stack_limit_rtx = gen_rtx_REG (Pmode, opt_fstack_limit_register_no); | |
6177 | ||
a2a8cc44 | 6178 | /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case |
c5c76735 | 6179 | tries to use these variables. */ |
23b2ce53 | 6180 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 6181 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 6182 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 6183 | |
68d75312 JC |
6184 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
6185 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 6186 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 6187 | else |
3b80f6ca | 6188 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 6189 | |
857c7b46 | 6190 | double_mode = float_mode_for_size (DOUBLE_TYPE_SIZE).require (); |
aa3a12d6 | 6191 | |
807e902e KZ |
6192 | real_from_integer (&dconst0, double_mode, 0, SIGNED); |
6193 | real_from_integer (&dconst1, double_mode, 1, SIGNED); | |
6194 | real_from_integer (&dconst2, double_mode, 2, SIGNED); | |
aefa9d43 KG |
6195 | |
6196 | dconstm1 = dconst1; | |
6197 | dconstm1.sign = 1; | |
03f2ea93 RS |
6198 | |
6199 | dconsthalf = dconst1; | |
1e92bbb9 | 6200 | SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1); |
23b2ce53 | 6201 | |
e7c82a99 | 6202 | for (i = 0; i < 3; i++) |
23b2ce53 | 6203 | { |
aefa9d43 | 6204 | const REAL_VALUE_TYPE *const r = |
b216cd4a ZW |
6205 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); |
6206 | ||
c94843d2 | 6207 | FOR_EACH_MODE_IN_CLASS (mode, MODE_FLOAT) |
15ed7b52 | 6208 | const_tiny_rtx[i][(int) mode] = |
555affd7 | 6209 | const_double_from_real_value (*r, mode); |
15ed7b52 | 6210 | |
c94843d2 | 6211 | FOR_EACH_MODE_IN_CLASS (mode, MODE_DECIMAL_FLOAT) |
5692c7bc | 6212 | const_tiny_rtx[i][(int) mode] = |
555affd7 | 6213 | const_double_from_real_value (*r, mode); |
23b2ce53 | 6214 | |
906c4e36 | 6215 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 | 6216 | |
c94843d2 | 6217 | FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
906c4e36 | 6218 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 | 6219 | |
ede6c734 MS |
6220 | for (mode = MIN_MODE_PARTIAL_INT; |
6221 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 6222 | mode = (machine_mode)((int)(mode) + 1)) |
33d3e559 | 6223 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
23b2ce53 RS |
6224 | } |
6225 | ||
e7c82a99 JJ |
6226 | const_tiny_rtx[3][(int) VOIDmode] = constm1_rtx; |
6227 | ||
c94843d2 | 6228 | FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
e7c82a99 JJ |
6229 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
6230 | ||
5c0caeb3 RS |
6231 | /* For BImode, 1 and -1 are unsigned and signed interpretations |
6232 | of the same value. */ | |
6233 | const_tiny_rtx[0][(int) BImode] = const0_rtx; | |
6234 | const_tiny_rtx[1][(int) BImode] = const_true_rtx; | |
6235 | const_tiny_rtx[3][(int) BImode] = const_true_rtx; | |
6236 | ||
ede6c734 MS |
6237 | for (mode = MIN_MODE_PARTIAL_INT; |
6238 | mode <= MAX_MODE_PARTIAL_INT; | |
ef4bddc2 | 6239 | mode = (machine_mode)((int)(mode) + 1)) |
c8a89d2a | 6240 | const_tiny_rtx[3][(int) mode] = constm1_rtx; |
c94843d2 RS |
6241 | |
6242 | FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_INT) | |
e90721b1 AP |
6243 | { |
6244 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
6245 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
6246 | } | |
6247 | ||
c94843d2 | 6248 | FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_FLOAT) |
e90721b1 AP |
6249 | { |
6250 | rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)]; | |
6251 | const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner); | |
6252 | } | |
6253 | ||
5c0caeb3 RS |
6254 | /* As for BImode, "all 1" and "all -1" are unsigned and signed |
6255 | interpretations of the same value. */ | |
6256 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_BOOL) | |
6257 | { | |
6258 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6259 | const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3); | |
6260 | const_tiny_rtx[1][(int) mode] = const_tiny_rtx[3][(int) mode]; | |
6261 | } | |
6262 | ||
c94843d2 | 6263 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) |
a73b091d JW |
6264 | { |
6265 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6266 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
e7c82a99 | 6267 | const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3); |
a73b091d | 6268 | } |
69ef87e2 | 6269 | |
c94843d2 | 6270 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT) |
a73b091d JW |
6271 | { |
6272 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6273 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6274 | } | |
69ef87e2 | 6275 | |
16d22000 | 6276 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_FRACT) |
325217ed | 6277 | { |
16d22000 RS |
6278 | scalar_mode smode = smode_iter.require (); |
6279 | FCONST0 (smode).data.high = 0; | |
6280 | FCONST0 (smode).data.low = 0; | |
6281 | FCONST0 (smode).mode = smode; | |
6282 | const_tiny_rtx[0][(int) smode] | |
6283 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6284 | } |
6285 | ||
16d22000 | 6286 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UFRACT) |
325217ed | 6287 | { |
16d22000 RS |
6288 | scalar_mode smode = smode_iter.require (); |
6289 | FCONST0 (smode).data.high = 0; | |
6290 | FCONST0 (smode).data.low = 0; | |
6291 | FCONST0 (smode).mode = smode; | |
6292 | const_tiny_rtx[0][(int) smode] | |
6293 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6294 | } |
6295 | ||
16d22000 | 6296 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_ACCUM) |
325217ed | 6297 | { |
16d22000 RS |
6298 | scalar_mode smode = smode_iter.require (); |
6299 | FCONST0 (smode).data.high = 0; | |
6300 | FCONST0 (smode).data.low = 0; | |
6301 | FCONST0 (smode).mode = smode; | |
6302 | const_tiny_rtx[0][(int) smode] | |
6303 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6304 | |
6305 | /* We store the value 1. */ | |
16d22000 RS |
6306 | FCONST1 (smode).data.high = 0; |
6307 | FCONST1 (smode).data.low = 0; | |
6308 | FCONST1 (smode).mode = smode; | |
6309 | FCONST1 (smode).data | |
6310 | = double_int_one.lshift (GET_MODE_FBIT (smode), | |
9be0ac8c | 6311 | HOST_BITS_PER_DOUBLE_INT, |
16d22000 RS |
6312 | SIGNED_FIXED_POINT_MODE_P (smode)); |
6313 | const_tiny_rtx[1][(int) smode] | |
6314 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode); | |
325217ed CF |
6315 | } |
6316 | ||
16d22000 | 6317 | FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UACCUM) |
325217ed | 6318 | { |
16d22000 RS |
6319 | scalar_mode smode = smode_iter.require (); |
6320 | FCONST0 (smode).data.high = 0; | |
6321 | FCONST0 (smode).data.low = 0; | |
6322 | FCONST0 (smode).mode = smode; | |
6323 | const_tiny_rtx[0][(int) smode] | |
6324 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode); | |
325217ed CF |
6325 | |
6326 | /* We store the value 1. */ | |
16d22000 RS |
6327 | FCONST1 (smode).data.high = 0; |
6328 | FCONST1 (smode).data.low = 0; | |
6329 | FCONST1 (smode).mode = smode; | |
6330 | FCONST1 (smode).data | |
6331 | = double_int_one.lshift (GET_MODE_FBIT (smode), | |
9be0ac8c | 6332 | HOST_BITS_PER_DOUBLE_INT, |
16d22000 RS |
6333 | SIGNED_FIXED_POINT_MODE_P (smode)); |
6334 | const_tiny_rtx[1][(int) smode] | |
6335 | = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode); | |
091a3ac7 CF |
6336 | } |
6337 | ||
c94843d2 | 6338 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FRACT) |
091a3ac7 CF |
6339 | { |
6340 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6341 | } | |
6342 | ||
c94843d2 | 6343 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UFRACT) |
091a3ac7 CF |
6344 | { |
6345 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6346 | } | |
6347 | ||
c94843d2 | 6348 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_ACCUM) |
091a3ac7 CF |
6349 | { |
6350 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6351 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
6352 | } | |
6353 | ||
c94843d2 | 6354 | FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UACCUM) |
091a3ac7 CF |
6355 | { |
6356 | const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0); | |
6357 | const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1); | |
325217ed CF |
6358 | } |
6359 | ||
dbbbbf3b | 6360 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
ef4bddc2 | 6361 | if (GET_MODE_CLASS ((machine_mode) i) == MODE_CC) |
dbbbbf3b | 6362 | const_tiny_rtx[0][i] = const0_rtx; |
23b2ce53 | 6363 | |
ca4adc91 RS |
6364 | pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); |
6365 | ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | |
6366 | simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); | |
1476d1bd MM |
6367 | invalid_insn_rtx = gen_rtx_INSN (VOIDmode, |
6368 | /*prev_insn=*/NULL, | |
6369 | /*next_insn=*/NULL, | |
6370 | /*bb=*/NULL, | |
6371 | /*pattern=*/NULL_RTX, | |
6372 | /*location=*/-1, | |
6373 | CODE_FOR_nothing, | |
6374 | /*reg_notes=*/NULL_RTX); | |
23b2ce53 | 6375 | } |
a11759a3 | 6376 | \f |
969d70ca JH |
6377 | /* Produce exact duplicate of insn INSN after AFTER. |
6378 | Care updating of libcall regions if present. */ | |
6379 | ||
cd459bf8 | 6380 | rtx_insn * |
a1950df3 | 6381 | emit_copy_of_insn_after (rtx_insn *insn, rtx_insn *after) |
969d70ca | 6382 | { |
cd459bf8 DM |
6383 | rtx_insn *new_rtx; |
6384 | rtx link; | |
969d70ca JH |
6385 | |
6386 | switch (GET_CODE (insn)) | |
6387 | { | |
6388 | case INSN: | |
60564289 | 6389 | new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca JH |
6390 | break; |
6391 | ||
6392 | case JUMP_INSN: | |
60564289 | 6393 | new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); |
ec27069c | 6394 | CROSSING_JUMP_P (new_rtx) = CROSSING_JUMP_P (insn); |
969d70ca JH |
6395 | break; |
6396 | ||
b5b8b0ac AO |
6397 | case DEBUG_INSN: |
6398 | new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after); | |
6399 | break; | |
6400 | ||
969d70ca | 6401 | case CALL_INSN: |
60564289 | 6402 | new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after); |
969d70ca | 6403 | if (CALL_INSN_FUNCTION_USAGE (insn)) |
60564289 | 6404 | CALL_INSN_FUNCTION_USAGE (new_rtx) |
969d70ca | 6405 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); |
60564289 KG |
6406 | SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn); |
6407 | RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn); | |
6408 | RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn); | |
b8698a0f | 6409 | RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx) |
becfd6e5 | 6410 | = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn); |
969d70ca JH |
6411 | break; |
6412 | ||
6413 | default: | |
5b0264cb | 6414 | gcc_unreachable (); |
969d70ca JH |
6415 | } |
6416 | ||
6417 | /* Update LABEL_NUSES. */ | |
60564289 | 6418 | mark_jump_label (PATTERN (new_rtx), new_rtx, 0); |
969d70ca | 6419 | |
5368224f | 6420 | INSN_LOCATION (new_rtx) = INSN_LOCATION (insn); |
ba4f7968 | 6421 | |
0a3d71f5 JW |
6422 | /* If the old insn is frame related, then so is the new one. This is |
6423 | primarily needed for IA-64 unwind info which marks epilogue insns, | |
6424 | which may be duplicated by the basic block reordering code. */ | |
60564289 | 6425 | RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn); |
0a3d71f5 | 6426 | |
1581a12c BS |
6427 | /* Locate the end of existing REG_NOTES in NEW_RTX. */ |
6428 | rtx *ptail = ®_NOTES (new_rtx); | |
6429 | while (*ptail != NULL_RTX) | |
6430 | ptail = &XEXP (*ptail, 1); | |
6431 | ||
cf7c4aa6 HPN |
6432 | /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label |
6433 | will make them. REG_LABEL_TARGETs are created there too, but are | |
6434 | supposed to be sticky, so we copy them. */ | |
969d70ca | 6435 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
cf7c4aa6 | 6436 | if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND) |
969d70ca | 6437 | { |
1581a12c BS |
6438 | *ptail = duplicate_reg_note (link); |
6439 | ptail = &XEXP (*ptail, 1); | |
969d70ca JH |
6440 | } |
6441 | ||
60564289 KG |
6442 | INSN_CODE (new_rtx) = INSN_CODE (insn); |
6443 | return new_rtx; | |
969d70ca | 6444 | } |
e2500fed | 6445 | |
1431042e | 6446 | static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; |
3e89ed8d | 6447 | rtx |
ef4bddc2 | 6448 | gen_hard_reg_clobber (machine_mode mode, unsigned int regno) |
3e89ed8d JH |
6449 | { |
6450 | if (hard_reg_clobbers[mode][regno]) | |
6451 | return hard_reg_clobbers[mode][regno]; | |
6452 | else | |
6453 | return (hard_reg_clobbers[mode][regno] = | |
6454 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); | |
6455 | } | |
6456 | ||
5368224f DC |
6457 | location_t prologue_location; |
6458 | location_t epilogue_location; | |
78bde837 SB |
6459 | |
6460 | /* Hold current location information and last location information, so the | |
6461 | datastructures are built lazily only when some instructions in given | |
6462 | place are needed. */ | |
3a50da34 | 6463 | static location_t curr_location; |
78bde837 | 6464 | |
5368224f | 6465 | /* Allocate insn location datastructure. */ |
78bde837 | 6466 | void |
5368224f | 6467 | insn_locations_init (void) |
78bde837 | 6468 | { |
5368224f | 6469 | prologue_location = epilogue_location = 0; |
78bde837 | 6470 | curr_location = UNKNOWN_LOCATION; |
78bde837 SB |
6471 | } |
6472 | ||
6473 | /* At the end of emit stage, clear current location. */ | |
6474 | void | |
5368224f | 6475 | insn_locations_finalize (void) |
78bde837 | 6476 | { |
5368224f DC |
6477 | epilogue_location = curr_location; |
6478 | curr_location = UNKNOWN_LOCATION; | |
78bde837 SB |
6479 | } |
6480 | ||
6481 | /* Set current location. */ | |
6482 | void | |
5368224f | 6483 | set_curr_insn_location (location_t location) |
78bde837 | 6484 | { |
78bde837 SB |
6485 | curr_location = location; |
6486 | } | |
6487 | ||
6488 | /* Get current location. */ | |
6489 | location_t | |
5368224f | 6490 | curr_insn_location (void) |
78bde837 SB |
6491 | { |
6492 | return curr_location; | |
6493 | } | |
6494 | ||
079e0f61 EB |
6495 | /* Set the location of the insn chain starting at INSN to LOC. */ |
6496 | void | |
6497 | set_insn_locations (rtx_insn *insn, location_t loc) | |
6498 | { | |
6499 | while (insn) | |
6500 | { | |
6501 | if (INSN_P (insn)) | |
6502 | INSN_LOCATION (insn) = loc; | |
6503 | insn = NEXT_INSN (insn); | |
6504 | } | |
6505 | } | |
6506 | ||
78bde837 SB |
6507 | /* Return lexical scope block insn belongs to. */ |
6508 | tree | |
a1950df3 | 6509 | insn_scope (const rtx_insn *insn) |
78bde837 | 6510 | { |
5368224f | 6511 | return LOCATION_BLOCK (INSN_LOCATION (insn)); |
78bde837 SB |
6512 | } |
6513 | ||
6514 | /* Return line number of the statement that produced this insn. */ | |
6515 | int | |
a1950df3 | 6516 | insn_line (const rtx_insn *insn) |
78bde837 | 6517 | { |
5368224f | 6518 | return LOCATION_LINE (INSN_LOCATION (insn)); |
78bde837 SB |
6519 | } |
6520 | ||
6521 | /* Return source file of the statement that produced this insn. */ | |
6522 | const char * | |
a1950df3 | 6523 | insn_file (const rtx_insn *insn) |
78bde837 | 6524 | { |
5368224f | 6525 | return LOCATION_FILE (INSN_LOCATION (insn)); |
78bde837 | 6526 | } |
8930883e | 6527 | |
ffa4602f EB |
6528 | /* Return expanded location of the statement that produced this insn. */ |
6529 | expanded_location | |
a1950df3 | 6530 | insn_location (const rtx_insn *insn) |
ffa4602f EB |
6531 | { |
6532 | return expand_location (INSN_LOCATION (insn)); | |
6533 | } | |
6534 | ||
8930883e MK |
6535 | /* Return true if memory model MODEL requires a pre-operation (release-style) |
6536 | barrier or a post-operation (acquire-style) barrier. While not universal, | |
6537 | this function matches behavior of several targets. */ | |
6538 | ||
6539 | bool | |
6540 | need_atomic_barrier_p (enum memmodel model, bool pre) | |
6541 | { | |
40ad260d | 6542 | switch (model & MEMMODEL_BASE_MASK) |
8930883e MK |
6543 | { |
6544 | case MEMMODEL_RELAXED: | |
6545 | case MEMMODEL_CONSUME: | |
6546 | return false; | |
6547 | case MEMMODEL_RELEASE: | |
6548 | return pre; | |
6549 | case MEMMODEL_ACQUIRE: | |
6550 | return !pre; | |
6551 | case MEMMODEL_ACQ_REL: | |
6552 | case MEMMODEL_SEQ_CST: | |
6553 | return true; | |
6554 | default: | |
6555 | gcc_unreachable (); | |
6556 | } | |
6557 | } | |
8194c537 | 6558 | |
abd3c800 RS |
6559 | /* Return a constant shift amount for shifting a value of mode MODE |
6560 | by VALUE bits. */ | |
6561 | ||
6562 | rtx | |
0c12fc9b | 6563 | gen_int_shift_amount (machine_mode, poly_int64 value) |
abd3c800 RS |
6564 | { |
6565 | /* Use a 64-bit mode, to avoid any truncation. | |
6566 | ||
6567 | ??? Perhaps this should be automatically derived from the .md files | |
6568 | instead, or perhaps have a target hook. */ | |
6569 | scalar_int_mode shift_mode = (BITS_PER_UNIT == 8 | |
6570 | ? DImode | |
6571 | : int_mode_for_size (64, 0).require ()); | |
6572 | return gen_int_mode (value, shift_mode); | |
6573 | } | |
6574 | ||
8194c537 DM |
6575 | /* Initialize fields of rtl_data related to stack alignment. */ |
6576 | ||
6577 | void | |
6578 | rtl_data::init_stack_alignment () | |
6579 | { | |
6580 | stack_alignment_needed = STACK_BOUNDARY; | |
6581 | max_used_stack_slot_alignment = STACK_BOUNDARY; | |
6582 | stack_alignment_estimated = 0; | |
6583 | preferred_stack_boundary = STACK_BOUNDARY; | |
6584 | } | |
6585 | ||
8930883e | 6586 | \f |
e2500fed | 6587 | #include "gt-emit-rtl.h" |