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Commit | Line | Data |
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5e6908ea | 1 | /* Emit RTL for the GCC expander. |
ef58a523 | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
9d18e06b | 3 | 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
23b2ce53 | 4 | |
1322177d | 5 | This file is part of GCC. |
23b2ce53 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
23b2ce53 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
23b2ce53 RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
670ee920 | 39 | #include "system.h" |
4977bab6 ZW |
40 | #include "coretypes.h" |
41 | #include "tm.h" | |
01198c2f | 42 | #include "toplev.h" |
23b2ce53 | 43 | #include "rtl.h" |
a25c7971 | 44 | #include "tree.h" |
6baf1cc8 | 45 | #include "tm_p.h" |
23b2ce53 RS |
46 | #include "flags.h" |
47 | #include "function.h" | |
48 | #include "expr.h" | |
49 | #include "regs.h" | |
aff48bca | 50 | #include "hard-reg-set.h" |
c13e8210 | 51 | #include "hashtab.h" |
23b2ce53 | 52 | #include "insn-config.h" |
e9a25f70 | 53 | #include "recog.h" |
23b2ce53 | 54 | #include "real.h" |
0dfa1860 | 55 | #include "bitmap.h" |
a05924f9 | 56 | #include "basic-block.h" |
87ff9c8e | 57 | #include "ggc.h" |
e1772ac0 | 58 | #include "debug.h" |
d23c55c2 | 59 | #include "langhooks.h" |
ca695ac9 | 60 | |
1d445e9e ILT |
61 | /* Commonly used modes. */ |
62 | ||
0f41302f MS |
63 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
64 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 65 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 66 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 67 | |
23b2ce53 RS |
68 | |
69 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
70 | in the entire compilation a unique label number. */ | |
71 | ||
044b4de3 | 72 | static GTY(()) int label_num = 1; |
23b2ce53 | 73 | |
23b2ce53 RS |
74 | /* Highest label number in current function. |
75 | Zero means use the value of label_num instead. | |
76 | This is nonzero only when belatedly compiling an inline function. */ | |
77 | ||
78 | static int last_label_num; | |
79 | ||
80 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
81 | If label_num has not changed since then, last_label_num is valid. */ | |
82 | ||
83 | static int base_label_num; | |
84 | ||
85 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
86 | ||
87 | static int no_line_numbers; | |
88 | ||
89 | /* Commonly used rtx's, so that we only need space for one copy. | |
90 | These are initialized once for the entire compilation. | |
5692c7bc ZW |
91 | All of these are unique; no other rtx-object will be equal to any |
92 | of these. */ | |
23b2ce53 | 93 | |
5da077de | 94 | rtx global_rtl[GR_MAX]; |
23b2ce53 | 95 | |
6cde4876 JL |
96 | /* Commonly used RTL for hard registers. These objects are not necessarily |
97 | unique, so we allocate them separately from global_rtl. They are | |
98 | initialized once per compilation unit, then copied into regno_reg_rtx | |
99 | at the beginning of each function. */ | |
100 | static GTY(()) rtx static_regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
101 | ||
23b2ce53 RS |
102 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for |
103 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
104 | record a copy of const[012]_rtx. */ | |
105 | ||
106 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
107 | ||
68d75312 JC |
108 | rtx const_true_rtx; |
109 | ||
23b2ce53 RS |
110 | REAL_VALUE_TYPE dconst0; |
111 | REAL_VALUE_TYPE dconst1; | |
112 | REAL_VALUE_TYPE dconst2; | |
113 | REAL_VALUE_TYPE dconstm1; | |
03f2ea93 RS |
114 | REAL_VALUE_TYPE dconstm2; |
115 | REAL_VALUE_TYPE dconsthalf; | |
23b2ce53 RS |
116 | |
117 | /* All references to the following fixed hard registers go through | |
118 | these unique rtl objects. On machines where the frame-pointer and | |
119 | arg-pointer are the same register, they use the same unique object. | |
120 | ||
121 | After register allocation, other rtl objects which used to be pseudo-regs | |
122 | may be clobbered to refer to the frame-pointer register. | |
123 | But references that were originally to the frame-pointer can be | |
124 | distinguished from the others because they contain frame_pointer_rtx. | |
125 | ||
ac6f08b0 DE |
126 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
127 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
750c9258 | 128 | should be used if it is being set, and frame_pointer_rtx otherwise. After |
ac6f08b0 DE |
129 | register elimination hard_frame_pointer_rtx should always be used. |
130 | On machines where the two registers are same (most) then these are the | |
131 | same. | |
132 | ||
23b2ce53 RS |
133 | In an inline procedure, the stack and frame pointer rtxs may not be |
134 | used for anything else. */ | |
23b2ce53 RS |
135 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
136 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
137 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
138 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
139 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
140 | ||
a4417a86 JW |
141 | /* This is used to implement __builtin_return_address for some machines. |
142 | See for instance the MIPS port. */ | |
143 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
144 | ||
23b2ce53 RS |
145 | /* We make one copy of (const_int C) where C is in |
146 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
147 | to save space during the compilation and simplify comparisons of | |
148 | integers. */ | |
149 | ||
5da077de | 150 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 151 | |
c13e8210 MM |
152 | /* A hash table storing CONST_INTs whose absolute value is greater |
153 | than MAX_SAVED_CONST_INT. */ | |
154 | ||
e2500fed GK |
155 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
156 | htab_t const_int_htab; | |
c13e8210 | 157 | |
173b24b9 | 158 | /* A hash table storing memory attribute structures. */ |
e2500fed GK |
159 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct mem_attrs))) |
160 | htab_t mem_attrs_htab; | |
173b24b9 | 161 | |
a560d4d4 JH |
162 | /* A hash table storing register attribute structures. */ |
163 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct reg_attrs))) | |
164 | htab_t reg_attrs_htab; | |
165 | ||
5692c7bc | 166 | /* A hash table storing all CONST_DOUBLEs. */ |
e2500fed GK |
167 | static GTY ((if_marked ("ggc_marked_p"), param_is (struct rtx_def))) |
168 | htab_t const_double_htab; | |
5692c7bc | 169 | |
01d939e8 BS |
170 | #define first_insn (cfun->emit->x_first_insn) |
171 | #define last_insn (cfun->emit->x_last_insn) | |
172 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
fd3acbb3 | 173 | #define last_location (cfun->emit->x_last_location) |
01d939e8 | 174 | #define first_label_num (cfun->emit->x_first_label_num) |
23b2ce53 | 175 | |
502b8322 AJ |
176 | static rtx make_jump_insn_raw (rtx); |
177 | static rtx make_call_insn_raw (rtx); | |
178 | static rtx find_line_note (rtx); | |
179 | static rtx change_address_1 (rtx, enum machine_mode, rtx, int); | |
180 | static void unshare_all_rtl_1 (rtx); | |
181 | static void unshare_all_decls (tree); | |
182 | static void reset_used_decls (tree); | |
183 | static void mark_label_nuses (rtx); | |
184 | static hashval_t const_int_htab_hash (const void *); | |
185 | static int const_int_htab_eq (const void *, const void *); | |
186 | static hashval_t const_double_htab_hash (const void *); | |
187 | static int const_double_htab_eq (const void *, const void *); | |
188 | static rtx lookup_const_double (rtx); | |
189 | static hashval_t mem_attrs_htab_hash (const void *); | |
190 | static int mem_attrs_htab_eq (const void *, const void *); | |
191 | static mem_attrs *get_mem_attrs (HOST_WIDE_INT, tree, rtx, rtx, unsigned int, | |
192 | enum machine_mode); | |
193 | static hashval_t reg_attrs_htab_hash (const void *); | |
194 | static int reg_attrs_htab_eq (const void *, const void *); | |
195 | static reg_attrs *get_reg_attrs (tree, int); | |
196 | static tree component_ref_for_mem_expr (tree); | |
197 | static rtx gen_const_vector_0 (enum machine_mode); | |
198 | static rtx gen_complex_constant_part (enum machine_mode, rtx, int); | |
c13e8210 | 199 | |
6b24c259 JH |
200 | /* Probability of the conditional branch currently proceeded by try_split. |
201 | Set to -1 otherwise. */ | |
202 | int split_branch_probability = -1; | |
ca695ac9 | 203 | \f |
c13e8210 MM |
204 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
205 | ||
206 | static hashval_t | |
502b8322 | 207 | const_int_htab_hash (const void *x) |
c13e8210 | 208 | { |
5692c7bc | 209 | return (hashval_t) INTVAL ((struct rtx_def *) x); |
c13e8210 MM |
210 | } |
211 | ||
cc2902df | 212 | /* Returns nonzero if the value represented by X (which is really a |
c13e8210 MM |
213 | CONST_INT) is the same as that given by Y (which is really a |
214 | HOST_WIDE_INT *). */ | |
215 | ||
216 | static int | |
502b8322 | 217 | const_int_htab_eq (const void *x, const void *y) |
c13e8210 | 218 | { |
5692c7bc ZW |
219 | return (INTVAL ((rtx) x) == *((const HOST_WIDE_INT *) y)); |
220 | } | |
221 | ||
222 | /* Returns a hash code for X (which is really a CONST_DOUBLE). */ | |
223 | static hashval_t | |
502b8322 | 224 | const_double_htab_hash (const void *x) |
5692c7bc | 225 | { |
5692c7bc | 226 | rtx value = (rtx) x; |
46b33600 | 227 | hashval_t h; |
5692c7bc | 228 | |
46b33600 RH |
229 | if (GET_MODE (value) == VOIDmode) |
230 | h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value); | |
231 | else | |
fe352c29 | 232 | { |
15c812e3 | 233 | h = real_hash (CONST_DOUBLE_REAL_VALUE (value)); |
fe352c29 DJ |
234 | /* MODE is used in the comparison, so it should be in the hash. */ |
235 | h ^= GET_MODE (value); | |
236 | } | |
5692c7bc ZW |
237 | return h; |
238 | } | |
239 | ||
cc2902df | 240 | /* Returns nonzero if the value represented by X (really a ...) |
5692c7bc ZW |
241 | is the same as that represented by Y (really a ...) */ |
242 | static int | |
502b8322 | 243 | const_double_htab_eq (const void *x, const void *y) |
5692c7bc ZW |
244 | { |
245 | rtx a = (rtx)x, b = (rtx)y; | |
5692c7bc ZW |
246 | |
247 | if (GET_MODE (a) != GET_MODE (b)) | |
248 | return 0; | |
8580f7a0 RH |
249 | if (GET_MODE (a) == VOIDmode) |
250 | return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b) | |
251 | && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b)); | |
252 | else | |
253 | return real_identical (CONST_DOUBLE_REAL_VALUE (a), | |
254 | CONST_DOUBLE_REAL_VALUE (b)); | |
c13e8210 MM |
255 | } |
256 | ||
173b24b9 RK |
257 | /* Returns a hash code for X (which is a really a mem_attrs *). */ |
258 | ||
259 | static hashval_t | |
502b8322 | 260 | mem_attrs_htab_hash (const void *x) |
173b24b9 RK |
261 | { |
262 | mem_attrs *p = (mem_attrs *) x; | |
263 | ||
264 | return (p->alias ^ (p->align * 1000) | |
265 | ^ ((p->offset ? INTVAL (p->offset) : 0) * 50000) | |
266 | ^ ((p->size ? INTVAL (p->size) : 0) * 2500000) | |
998d7deb | 267 | ^ (size_t) p->expr); |
173b24b9 RK |
268 | } |
269 | ||
cc2902df | 270 | /* Returns nonzero if the value represented by X (which is really a |
173b24b9 RK |
271 | mem_attrs *) is the same as that given by Y (which is also really a |
272 | mem_attrs *). */ | |
c13e8210 MM |
273 | |
274 | static int | |
502b8322 | 275 | mem_attrs_htab_eq (const void *x, const void *y) |
c13e8210 | 276 | { |
173b24b9 RK |
277 | mem_attrs *p = (mem_attrs *) x; |
278 | mem_attrs *q = (mem_attrs *) y; | |
279 | ||
998d7deb | 280 | return (p->alias == q->alias && p->expr == q->expr && p->offset == q->offset |
173b24b9 | 281 | && p->size == q->size && p->align == q->align); |
c13e8210 MM |
282 | } |
283 | ||
173b24b9 | 284 | /* Allocate a new mem_attrs structure and insert it into the hash table if |
10b76d73 RK |
285 | one identical to it is not already in the table. We are doing this for |
286 | MEM of mode MODE. */ | |
173b24b9 RK |
287 | |
288 | static mem_attrs * | |
502b8322 AJ |
289 | get_mem_attrs (HOST_WIDE_INT alias, tree expr, rtx offset, rtx size, |
290 | unsigned int align, enum machine_mode mode) | |
173b24b9 RK |
291 | { |
292 | mem_attrs attrs; | |
293 | void **slot; | |
294 | ||
bb056a77 OH |
295 | /* If everything is the default, we can just return zero. |
296 | This must match what the corresponding MEM_* macros return when the | |
297 | field is not present. */ | |
998d7deb | 298 | if (alias == 0 && expr == 0 && offset == 0 |
10b76d73 RK |
299 | && (size == 0 |
300 | || (mode != BLKmode && GET_MODE_SIZE (mode) == INTVAL (size))) | |
bb056a77 OH |
301 | && (STRICT_ALIGNMENT && mode != BLKmode |
302 | ? align == GET_MODE_ALIGNMENT (mode) : align == BITS_PER_UNIT)) | |
10b76d73 RK |
303 | return 0; |
304 | ||
173b24b9 | 305 | attrs.alias = alias; |
998d7deb | 306 | attrs.expr = expr; |
173b24b9 RK |
307 | attrs.offset = offset; |
308 | attrs.size = size; | |
309 | attrs.align = align; | |
310 | ||
311 | slot = htab_find_slot (mem_attrs_htab, &attrs, INSERT); | |
312 | if (*slot == 0) | |
313 | { | |
314 | *slot = ggc_alloc (sizeof (mem_attrs)); | |
315 | memcpy (*slot, &attrs, sizeof (mem_attrs)); | |
316 | } | |
317 | ||
318 | return *slot; | |
c13e8210 MM |
319 | } |
320 | ||
a560d4d4 JH |
321 | /* Returns a hash code for X (which is a really a reg_attrs *). */ |
322 | ||
323 | static hashval_t | |
502b8322 | 324 | reg_attrs_htab_hash (const void *x) |
a560d4d4 JH |
325 | { |
326 | reg_attrs *p = (reg_attrs *) x; | |
327 | ||
328 | return ((p->offset * 1000) ^ (long) p->decl); | |
329 | } | |
330 | ||
6356f892 | 331 | /* Returns nonzero if the value represented by X (which is really a |
a560d4d4 JH |
332 | reg_attrs *) is the same as that given by Y (which is also really a |
333 | reg_attrs *). */ | |
334 | ||
335 | static int | |
502b8322 | 336 | reg_attrs_htab_eq (const void *x, const void *y) |
a560d4d4 JH |
337 | { |
338 | reg_attrs *p = (reg_attrs *) x; | |
339 | reg_attrs *q = (reg_attrs *) y; | |
340 | ||
341 | return (p->decl == q->decl && p->offset == q->offset); | |
342 | } | |
343 | /* Allocate a new reg_attrs structure and insert it into the hash table if | |
344 | one identical to it is not already in the table. We are doing this for | |
345 | MEM of mode MODE. */ | |
346 | ||
347 | static reg_attrs * | |
502b8322 | 348 | get_reg_attrs (tree decl, int offset) |
a560d4d4 JH |
349 | { |
350 | reg_attrs attrs; | |
351 | void **slot; | |
352 | ||
353 | /* If everything is the default, we can just return zero. */ | |
354 | if (decl == 0 && offset == 0) | |
355 | return 0; | |
356 | ||
357 | attrs.decl = decl; | |
358 | attrs.offset = offset; | |
359 | ||
360 | slot = htab_find_slot (reg_attrs_htab, &attrs, INSERT); | |
361 | if (*slot == 0) | |
362 | { | |
363 | *slot = ggc_alloc (sizeof (reg_attrs)); | |
364 | memcpy (*slot, &attrs, sizeof (reg_attrs)); | |
365 | } | |
366 | ||
367 | return *slot; | |
368 | } | |
369 | ||
08394eef BS |
370 | /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and |
371 | don't attempt to share with the various global pieces of rtl (such as | |
372 | frame_pointer_rtx). */ | |
373 | ||
374 | rtx | |
502b8322 | 375 | gen_raw_REG (enum machine_mode mode, int regno) |
08394eef BS |
376 | { |
377 | rtx x = gen_rtx_raw_REG (mode, regno); | |
378 | ORIGINAL_REGNO (x) = regno; | |
379 | return x; | |
380 | } | |
381 | ||
c5c76735 JL |
382 | /* There are some RTL codes that require special attention; the generation |
383 | functions do the raw handling. If you add to this list, modify | |
384 | special_rtx in gengenrtl.c as well. */ | |
385 | ||
3b80f6ca | 386 | rtx |
502b8322 | 387 | gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg) |
3b80f6ca | 388 | { |
c13e8210 MM |
389 | void **slot; |
390 | ||
3b80f6ca | 391 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 392 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
393 | |
394 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
395 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
396 | return const_true_rtx; | |
397 | #endif | |
398 | ||
c13e8210 | 399 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
400 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
401 | (hashval_t) arg, INSERT); | |
29105cea | 402 | if (*slot == 0) |
1f8f4a0b | 403 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
c13e8210 MM |
404 | |
405 | return (rtx) *slot; | |
3b80f6ca RH |
406 | } |
407 | ||
2496c7bd | 408 | rtx |
502b8322 | 409 | gen_int_mode (HOST_WIDE_INT c, enum machine_mode mode) |
2496c7bd LB |
410 | { |
411 | return GEN_INT (trunc_int_for_mode (c, mode)); | |
412 | } | |
413 | ||
5692c7bc ZW |
414 | /* CONST_DOUBLEs might be created from pairs of integers, or from |
415 | REAL_VALUE_TYPEs. Also, their length is known only at run time, | |
416 | so we cannot use gen_rtx_raw_CONST_DOUBLE. */ | |
417 | ||
418 | /* Determine whether REAL, a CONST_DOUBLE, already exists in the | |
419 | hash table. If so, return its counterpart; otherwise add it | |
420 | to the hash table and return it. */ | |
421 | static rtx | |
502b8322 | 422 | lookup_const_double (rtx real) |
5692c7bc ZW |
423 | { |
424 | void **slot = htab_find_slot (const_double_htab, real, INSERT); | |
425 | if (*slot == 0) | |
426 | *slot = real; | |
427 | ||
428 | return (rtx) *slot; | |
429 | } | |
29105cea | 430 | |
5692c7bc ZW |
431 | /* Return a CONST_DOUBLE rtx for a floating-point value specified by |
432 | VALUE in mode MODE. */ | |
0133b7d9 | 433 | rtx |
502b8322 | 434 | const_double_from_real_value (REAL_VALUE_TYPE value, enum machine_mode mode) |
0133b7d9 | 435 | { |
5692c7bc ZW |
436 | rtx real = rtx_alloc (CONST_DOUBLE); |
437 | PUT_MODE (real, mode); | |
438 | ||
439 | memcpy (&CONST_DOUBLE_LOW (real), &value, sizeof (REAL_VALUE_TYPE)); | |
440 | ||
441 | return lookup_const_double (real); | |
442 | } | |
443 | ||
444 | /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair | |
445 | of ints: I0 is the low-order word and I1 is the high-order word. | |
446 | Do not use this routine for non-integer modes; convert to | |
447 | REAL_VALUE_TYPE and use CONST_DOUBLE_FROM_REAL_VALUE. */ | |
448 | ||
449 | rtx | |
502b8322 | 450 | immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, enum machine_mode mode) |
5692c7bc ZW |
451 | { |
452 | rtx value; | |
453 | unsigned int i; | |
454 | ||
455 | if (mode != VOIDmode) | |
456 | { | |
457 | int width; | |
458 | if (GET_MODE_CLASS (mode) != MODE_INT | |
cb2a532e AH |
459 | && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT |
460 | /* We can get a 0 for an error mark. */ | |
461 | && GET_MODE_CLASS (mode) != MODE_VECTOR_INT | |
462 | && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) | |
5692c7bc ZW |
463 | abort (); |
464 | ||
465 | /* We clear out all bits that don't belong in MODE, unless they and | |
466 | our sign bit are all one. So we get either a reasonable negative | |
467 | value or a reasonable unsigned value for this mode. */ | |
468 | width = GET_MODE_BITSIZE (mode); | |
469 | if (width < HOST_BITS_PER_WIDE_INT | |
470 | && ((i0 & ((HOST_WIDE_INT) (-1) << (width - 1))) | |
471 | != ((HOST_WIDE_INT) (-1) << (width - 1)))) | |
472 | i0 &= ((HOST_WIDE_INT) 1 << width) - 1, i1 = 0; | |
473 | else if (width == HOST_BITS_PER_WIDE_INT | |
474 | && ! (i1 == ~0 && i0 < 0)) | |
475 | i1 = 0; | |
476 | else if (width > 2 * HOST_BITS_PER_WIDE_INT) | |
477 | /* We cannot represent this value as a constant. */ | |
478 | abort (); | |
479 | ||
480 | /* If this would be an entire word for the target, but is not for | |
481 | the host, then sign-extend on the host so that the number will | |
482 | look the same way on the host that it would on the target. | |
483 | ||
484 | For example, when building a 64 bit alpha hosted 32 bit sparc | |
485 | targeted compiler, then we want the 32 bit unsigned value -1 to be | |
486 | represented as a 64 bit value -1, and not as 0x00000000ffffffff. | |
487 | The latter confuses the sparc backend. */ | |
488 | ||
489 | if (width < HOST_BITS_PER_WIDE_INT | |
490 | && (i0 & ((HOST_WIDE_INT) 1 << (width - 1)))) | |
491 | i0 |= ((HOST_WIDE_INT) (-1) << width); | |
2454beaf | 492 | |
5692c7bc ZW |
493 | /* If MODE fits within HOST_BITS_PER_WIDE_INT, always use a |
494 | CONST_INT. | |
2454beaf | 495 | |
5692c7bc ZW |
496 | ??? Strictly speaking, this is wrong if we create a CONST_INT for |
497 | a large unsigned constant with the size of MODE being | |
498 | HOST_BITS_PER_WIDE_INT and later try to interpret that constant | |
499 | in a wider mode. In that case we will mis-interpret it as a | |
500 | negative number. | |
2454beaf | 501 | |
5692c7bc ZW |
502 | Unfortunately, the only alternative is to make a CONST_DOUBLE for |
503 | any constant in any mode if it is an unsigned constant larger | |
504 | than the maximum signed integer in an int on the host. However, | |
505 | doing this will break everyone that always expects to see a | |
506 | CONST_INT for SImode and smaller. | |
507 | ||
508 | We have always been making CONST_INTs in this case, so nothing | |
509 | new is being broken. */ | |
510 | ||
511 | if (width <= HOST_BITS_PER_WIDE_INT) | |
512 | i1 = (i0 < 0) ? ~(HOST_WIDE_INT) 0 : 0; | |
513 | } | |
514 | ||
515 | /* If this integer fits in one word, return a CONST_INT. */ | |
516 | if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0)) | |
517 | return GEN_INT (i0); | |
518 | ||
519 | /* We use VOIDmode for integers. */ | |
520 | value = rtx_alloc (CONST_DOUBLE); | |
521 | PUT_MODE (value, VOIDmode); | |
522 | ||
523 | CONST_DOUBLE_LOW (value) = i0; | |
524 | CONST_DOUBLE_HIGH (value) = i1; | |
525 | ||
526 | for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++) | |
527 | XWINT (value, i) = 0; | |
528 | ||
529 | return lookup_const_double (value); | |
0133b7d9 RH |
530 | } |
531 | ||
3b80f6ca | 532 | rtx |
502b8322 | 533 | gen_rtx_REG (enum machine_mode mode, unsigned int regno) |
3b80f6ca RH |
534 | { |
535 | /* In case the MD file explicitly references the frame pointer, have | |
536 | all such references point to the same frame pointer. This is | |
537 | used during frame pointer elimination to distinguish the explicit | |
538 | references to these registers from pseudos that happened to be | |
539 | assigned to them. | |
540 | ||
541 | If we have eliminated the frame pointer or arg pointer, we will | |
542 | be using it as a normal register, for example as a spill | |
543 | register. In such cases, we might be accessing it in a mode that | |
544 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
545 | ||
546 | Also don't do this when we are making new REGs in reload, since | |
547 | we don't want to get confused with the real pointers. */ | |
548 | ||
549 | if (mode == Pmode && !reload_in_progress) | |
550 | { | |
e10c79fe LB |
551 | if (regno == FRAME_POINTER_REGNUM |
552 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
553 | return frame_pointer_rtx; |
554 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
e10c79fe LB |
555 | if (regno == HARD_FRAME_POINTER_REGNUM |
556 | && (!reload_completed || frame_pointer_needed)) | |
3b80f6ca RH |
557 | return hard_frame_pointer_rtx; |
558 | #endif | |
559 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 560 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
561 | return arg_pointer_rtx; |
562 | #endif | |
563 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 564 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
565 | return return_address_pointer_rtx; |
566 | #endif | |
fc555370 | 567 | if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM |
2d67bd7b | 568 | && fixed_regs[PIC_OFFSET_TABLE_REGNUM]) |
68252e27 | 569 | return pic_offset_table_rtx; |
bcb33994 | 570 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
571 | return stack_pointer_rtx; |
572 | } | |
573 | ||
006a94b0 | 574 | #if 0 |
6cde4876 | 575 | /* If the per-function register table has been set up, try to re-use |
006a94b0 JL |
576 | an existing entry in that table to avoid useless generation of RTL. |
577 | ||
578 | This code is disabled for now until we can fix the various backends | |
579 | which depend on having non-shared hard registers in some cases. Long | |
580 | term we want to re-enable this code as it can significantly cut down | |
e10c79fe LB |
581 | on the amount of useless RTL that gets generated. |
582 | ||
583 | We'll also need to fix some code that runs after reload that wants to | |
584 | set ORIGINAL_REGNO. */ | |
585 | ||
6cde4876 JL |
586 | if (cfun |
587 | && cfun->emit | |
588 | && regno_reg_rtx | |
589 | && regno < FIRST_PSEUDO_REGISTER | |
590 | && reg_raw_mode[regno] == mode) | |
591 | return regno_reg_rtx[regno]; | |
006a94b0 | 592 | #endif |
6cde4876 | 593 | |
08394eef | 594 | return gen_raw_REG (mode, regno); |
3b80f6ca RH |
595 | } |
596 | ||
41472af8 | 597 | rtx |
502b8322 | 598 | gen_rtx_MEM (enum machine_mode mode, rtx addr) |
41472af8 MM |
599 | { |
600 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
601 | ||
602 | /* This field is not cleared by the mere allocation of the rtx, so | |
603 | we clear it here. */ | |
173b24b9 | 604 | MEM_ATTRS (rt) = 0; |
41472af8 MM |
605 | |
606 | return rt; | |
607 | } | |
ddef6bc7 JJ |
608 | |
609 | rtx | |
502b8322 | 610 | gen_rtx_SUBREG (enum machine_mode mode, rtx reg, int offset) |
ddef6bc7 JJ |
611 | { |
612 | /* This is the most common failure type. | |
613 | Catch it early so we can see who does it. */ | |
614 | if ((offset % GET_MODE_SIZE (mode)) != 0) | |
615 | abort (); | |
616 | ||
617 | /* This check isn't usable right now because combine will | |
618 | throw arbitrary crap like a CALL into a SUBREG in | |
619 | gen_lowpart_for_combine so we must just eat it. */ | |
620 | #if 0 | |
621 | /* Check for this too. */ | |
622 | if (offset >= GET_MODE_SIZE (GET_MODE (reg))) | |
623 | abort (); | |
624 | #endif | |
5692c7bc | 625 | return gen_rtx_raw_SUBREG (mode, reg, offset); |
ddef6bc7 JJ |
626 | } |
627 | ||
173b24b9 RK |
628 | /* Generate a SUBREG representing the least-significant part of REG if MODE |
629 | is smaller than mode of REG, otherwise paradoxical SUBREG. */ | |
630 | ||
ddef6bc7 | 631 | rtx |
502b8322 | 632 | gen_lowpart_SUBREG (enum machine_mode mode, rtx reg) |
ddef6bc7 JJ |
633 | { |
634 | enum machine_mode inmode; | |
ddef6bc7 JJ |
635 | |
636 | inmode = GET_MODE (reg); | |
637 | if (inmode == VOIDmode) | |
638 | inmode = mode; | |
e0e08ac2 JH |
639 | return gen_rtx_SUBREG (mode, reg, |
640 | subreg_lowpart_offset (mode, inmode)); | |
ddef6bc7 | 641 | } |
c5c76735 | 642 | \f |
23b2ce53 RS |
643 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
644 | ** | |
645 | ** This routine generates an RTX of the size specified by | |
646 | ** <code>, which is an RTX code. The RTX structure is initialized | |
647 | ** from the arguments <element1> through <elementn>, which are | |
648 | ** interpreted according to the specific RTX type's format. The | |
649 | ** special machine mode associated with the rtx (if any) is specified | |
650 | ** in <mode>. | |
651 | ** | |
1632afca | 652 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
653 | ** rtx it will generate. For example, the following rtx structure: |
654 | ** | |
655 | ** (plus:QI (mem:QI (reg:SI 1)) | |
656 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
657 | ** | |
658 | ** ...would be generated by the following C code: | |
659 | ** | |
750c9258 | 660 | ** gen_rtx (PLUS, QImode, |
23b2ce53 RS |
661 | ** gen_rtx (MEM, QImode, |
662 | ** gen_rtx (REG, SImode, 1)), | |
663 | ** gen_rtx (MEM, QImode, | |
664 | ** gen_rtx (PLUS, SImode, | |
665 | ** gen_rtx (REG, SImode, 2), | |
666 | ** gen_rtx (REG, SImode, 3)))), | |
667 | */ | |
668 | ||
669 | /*VARARGS2*/ | |
670 | rtx | |
e34d07f2 | 671 | gen_rtx (enum rtx_code code, enum machine_mode mode, ...) |
23b2ce53 | 672 | { |
b3694847 SS |
673 | int i; /* Array indices... */ |
674 | const char *fmt; /* Current rtx's format... */ | |
675 | rtx rt_val; /* RTX to return to caller... */ | |
e34d07f2 | 676 | va_list p; |
23b2ce53 | 677 | |
e34d07f2 | 678 | va_start (p, mode); |
23b2ce53 | 679 | |
0133b7d9 | 680 | switch (code) |
23b2ce53 | 681 | { |
0133b7d9 RH |
682 | case CONST_INT: |
683 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
684 | break; | |
685 | ||
686 | case CONST_DOUBLE: | |
687 | { | |
a79e3a45 | 688 | HOST_WIDE_INT arg0 = va_arg (p, HOST_WIDE_INT); |
0133b7d9 | 689 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); |
a79e3a45 | 690 | |
0fb7aeda | 691 | rt_val = immed_double_const (arg0, arg1, mode); |
0133b7d9 RH |
692 | } |
693 | break; | |
694 | ||
695 | case REG: | |
696 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
697 | break; | |
698 | ||
699 | case MEM: | |
700 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
701 | break; | |
702 | ||
703 | default: | |
23b2ce53 RS |
704 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
705 | rt_val->mode = mode; /* Store the machine mode... */ | |
706 | ||
707 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
708 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
709 | { | |
710 | switch (*fmt++) | |
711 | { | |
a73071bc | 712 | case '0': /* Field with unknown use. Zero it. */ |
d5b9108c | 713 | X0EXP (rt_val, i) = NULL_RTX; |
23b2ce53 RS |
714 | break; |
715 | ||
716 | case 'i': /* An integer? */ | |
717 | XINT (rt_val, i) = va_arg (p, int); | |
718 | break; | |
719 | ||
906c4e36 RK |
720 | case 'w': /* A wide integer? */ |
721 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
722 | break; | |
723 | ||
23b2ce53 RS |
724 | case 's': /* A string? */ |
725 | XSTR (rt_val, i) = va_arg (p, char *); | |
726 | break; | |
727 | ||
728 | case 'e': /* An expression? */ | |
729 | case 'u': /* An insn? Same except when printing. */ | |
730 | XEXP (rt_val, i) = va_arg (p, rtx); | |
731 | break; | |
732 | ||
733 | case 'E': /* An RTX vector? */ | |
734 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
735 | break; | |
736 | ||
0dfa1860 MM |
737 | case 'b': /* A bitmap? */ |
738 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
739 | break; | |
740 | ||
741 | case 't': /* A tree? */ | |
742 | XTREE (rt_val, i) = va_arg (p, tree); | |
743 | break; | |
744 | ||
23b2ce53 | 745 | default: |
1632afca | 746 | abort (); |
23b2ce53 RS |
747 | } |
748 | } | |
0133b7d9 | 749 | break; |
23b2ce53 | 750 | } |
0133b7d9 | 751 | |
e34d07f2 | 752 | va_end (p); |
0133b7d9 | 753 | return rt_val; |
23b2ce53 RS |
754 | } |
755 | ||
756 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
757 | ** | |
758 | ** This routine creates an rtvec and stores within it the | |
759 | ** pointers to rtx's which are its arguments. | |
760 | */ | |
761 | ||
762 | /*VARARGS1*/ | |
763 | rtvec | |
e34d07f2 | 764 | gen_rtvec (int n, ...) |
23b2ce53 | 765 | { |
6268b922 | 766 | int i, save_n; |
23b2ce53 | 767 | rtx *vector; |
e34d07f2 | 768 | va_list p; |
23b2ce53 | 769 | |
e34d07f2 | 770 | va_start (p, n); |
23b2ce53 RS |
771 | |
772 | if (n == 0) | |
773 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
774 | ||
775 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 776 | |
23b2ce53 RS |
777 | for (i = 0; i < n; i++) |
778 | vector[i] = va_arg (p, rtx); | |
6268b922 KG |
779 | |
780 | /* The definition of VA_* in K&R C causes `n' to go out of scope. */ | |
781 | save_n = n; | |
e34d07f2 | 782 | va_end (p); |
23b2ce53 | 783 | |
6268b922 | 784 | return gen_rtvec_v (save_n, vector); |
23b2ce53 RS |
785 | } |
786 | ||
787 | rtvec | |
502b8322 | 788 | gen_rtvec_v (int n, rtx *argp) |
23b2ce53 | 789 | { |
b3694847 SS |
790 | int i; |
791 | rtvec rt_val; | |
23b2ce53 RS |
792 | |
793 | if (n == 0) | |
794 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
795 | ||
796 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
797 | ||
798 | for (i = 0; i < n; i++) | |
8f985ec4 | 799 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
800 | |
801 | return rt_val; | |
802 | } | |
803 | \f | |
804 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
805 | This pseudo is assigned the next sequential register number. */ | |
806 | ||
807 | rtx | |
502b8322 | 808 | gen_reg_rtx (enum machine_mode mode) |
23b2ce53 | 809 | { |
01d939e8 | 810 | struct function *f = cfun; |
b3694847 | 811 | rtx val; |
23b2ce53 | 812 | |
f1db3576 JL |
813 | /* Don't let anything called after initial flow analysis create new |
814 | registers. */ | |
815 | if (no_new_pseudos) | |
23b2ce53 RS |
816 | abort (); |
817 | ||
1b3d8f8a GK |
818 | if (generating_concat_p |
819 | && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
820 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)) | |
fc84e8a8 RS |
821 | { |
822 | /* For complex modes, don't make a single pseudo. | |
823 | Instead, make a CONCAT of two pseudos. | |
824 | This allows noncontiguous allocation of the real and imaginary parts, | |
825 | which makes much better code. Besides, allocating DCmode | |
826 | pseudos overstrains reload on some machines like the 386. */ | |
827 | rtx realpart, imagpart; | |
27e58a70 | 828 | enum machine_mode partmode = GET_MODE_INNER (mode); |
fc84e8a8 RS |
829 | |
830 | realpart = gen_reg_rtx (partmode); | |
831 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 832 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
833 | } |
834 | ||
a560d4d4 | 835 | /* Make sure regno_pointer_align, and regno_reg_rtx are large |
0d4903b8 | 836 | enough to have an element for this pseudo reg number. */ |
23b2ce53 | 837 | |
3502dc9c | 838 | if (reg_rtx_no == f->emit->regno_pointer_align_length) |
23b2ce53 | 839 | { |
3502dc9c | 840 | int old_size = f->emit->regno_pointer_align_length; |
e2ecd91c | 841 | char *new; |
0d4903b8 | 842 | rtx *new1; |
0d4903b8 | 843 | |
e2500fed | 844 | new = ggc_realloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa | 845 | memset (new + old_size, 0, old_size); |
f9e158c3 | 846 | f->emit->regno_pointer_align = (unsigned char *) new; |
49ad7cfa | 847 | |
e2500fed GK |
848 | new1 = (rtx *) ggc_realloc (f->emit->x_regno_reg_rtx, |
849 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 850 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
851 | regno_reg_rtx = new1; |
852 | ||
3502dc9c | 853 | f->emit->regno_pointer_align_length = old_size * 2; |
23b2ce53 RS |
854 | } |
855 | ||
08394eef | 856 | val = gen_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
857 | regno_reg_rtx[reg_rtx_no++] = val; |
858 | return val; | |
859 | } | |
860 | ||
a560d4d4 JH |
861 | /* Generate an register with same attributes as REG, |
862 | but offsetted by OFFSET. */ | |
863 | ||
864 | rtx | |
502b8322 | 865 | gen_rtx_REG_offset (rtx reg, enum machine_mode mode, unsigned int regno, int offset) |
a560d4d4 JH |
866 | { |
867 | rtx new = gen_rtx_REG (mode, regno); | |
868 | REG_ATTRS (new) = get_reg_attrs (REG_EXPR (reg), | |
502b8322 | 869 | REG_OFFSET (reg) + offset); |
a560d4d4 JH |
870 | return new; |
871 | } | |
872 | ||
873 | /* Set the decl for MEM to DECL. */ | |
874 | ||
875 | void | |
502b8322 | 876 | set_reg_attrs_from_mem (rtx reg, rtx mem) |
a560d4d4 JH |
877 | { |
878 | if (MEM_OFFSET (mem) && GET_CODE (MEM_OFFSET (mem)) == CONST_INT) | |
879 | REG_ATTRS (reg) | |
880 | = get_reg_attrs (MEM_EXPR (mem), INTVAL (MEM_OFFSET (mem))); | |
881 | } | |
882 | ||
9d18e06b JZ |
883 | /* Set the register attributes for registers contained in PARM_RTX. |
884 | Use needed values from memory attributes of MEM. */ | |
885 | ||
886 | void | |
502b8322 | 887 | set_reg_attrs_for_parm (rtx parm_rtx, rtx mem) |
9d18e06b JZ |
888 | { |
889 | if (GET_CODE (parm_rtx) == REG) | |
890 | set_reg_attrs_from_mem (parm_rtx, mem); | |
891 | else if (GET_CODE (parm_rtx) == PARALLEL) | |
892 | { | |
893 | /* Check for a NULL entry in the first slot, used to indicate that the | |
894 | parameter goes both on the stack and in registers. */ | |
895 | int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1; | |
896 | for (; i < XVECLEN (parm_rtx, 0); i++) | |
897 | { | |
898 | rtx x = XVECEXP (parm_rtx, 0, i); | |
899 | if (GET_CODE (XEXP (x, 0)) == REG) | |
900 | REG_ATTRS (XEXP (x, 0)) | |
901 | = get_reg_attrs (MEM_EXPR (mem), | |
902 | INTVAL (XEXP (x, 1))); | |
903 | } | |
904 | } | |
905 | } | |
906 | ||
a560d4d4 JH |
907 | /* Assign the RTX X to declaration T. */ |
908 | void | |
502b8322 | 909 | set_decl_rtl (tree t, rtx x) |
a560d4d4 JH |
910 | { |
911 | DECL_CHECK (t)->decl.rtl = x; | |
912 | ||
913 | if (!x) | |
914 | return; | |
915 | /* For register, we maitain the reverse information too. */ | |
916 | if (GET_CODE (x) == REG) | |
917 | REG_ATTRS (x) = get_reg_attrs (t, 0); | |
918 | else if (GET_CODE (x) == SUBREG) | |
919 | REG_ATTRS (SUBREG_REG (x)) | |
920 | = get_reg_attrs (t, -SUBREG_BYTE (x)); | |
921 | if (GET_CODE (x) == CONCAT) | |
922 | { | |
923 | if (REG_P (XEXP (x, 0))) | |
924 | REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0); | |
925 | if (REG_P (XEXP (x, 1))) | |
926 | REG_ATTRS (XEXP (x, 1)) | |
927 | = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0)))); | |
928 | } | |
929 | if (GET_CODE (x) == PARALLEL) | |
930 | { | |
931 | int i; | |
932 | for (i = 0; i < XVECLEN (x, 0); i++) | |
933 | { | |
934 | rtx y = XVECEXP (x, 0, i); | |
935 | if (REG_P (XEXP (y, 0))) | |
936 | REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1))); | |
937 | } | |
938 | } | |
939 | } | |
940 | ||
754fdcca RK |
941 | /* Identify REG (which may be a CONCAT) as a user register. */ |
942 | ||
943 | void | |
502b8322 | 944 | mark_user_reg (rtx reg) |
754fdcca RK |
945 | { |
946 | if (GET_CODE (reg) == CONCAT) | |
947 | { | |
948 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
949 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
950 | } | |
951 | else if (GET_CODE (reg) == REG) | |
952 | REG_USERVAR_P (reg) = 1; | |
953 | else | |
954 | abort (); | |
955 | } | |
956 | ||
86fe05e0 RK |
957 | /* Identify REG as a probable pointer register and show its alignment |
958 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
959 | |
960 | void | |
502b8322 | 961 | mark_reg_pointer (rtx reg, int align) |
23b2ce53 | 962 | { |
3502dc9c | 963 | if (! REG_POINTER (reg)) |
00995e78 | 964 | { |
3502dc9c | 965 | REG_POINTER (reg) = 1; |
86fe05e0 | 966 | |
00995e78 RE |
967 | if (align) |
968 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
969 | } | |
970 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
971 | /* We can no-longer be sure just how aligned this pointer is */ | |
86fe05e0 | 972 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
973 | } |
974 | ||
975 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
976 | ||
977 | int | |
502b8322 | 978 | max_reg_num (void) |
23b2ce53 RS |
979 | { |
980 | return reg_rtx_no; | |
981 | } | |
982 | ||
983 | /* Return 1 + the largest label number used so far in the current function. */ | |
984 | ||
985 | int | |
502b8322 | 986 | max_label_num (void) |
23b2ce53 RS |
987 | { |
988 | if (last_label_num && label_num == base_label_num) | |
989 | return last_label_num; | |
990 | return label_num; | |
991 | } | |
992 | ||
993 | /* Return first label number used in this function (if any were used). */ | |
994 | ||
995 | int | |
502b8322 | 996 | get_first_label_num (void) |
23b2ce53 RS |
997 | { |
998 | return first_label_num; | |
999 | } | |
1000 | \f | |
ddef6bc7 JJ |
1001 | /* Return the final regno of X, which is a SUBREG of a hard |
1002 | register. */ | |
1003 | int | |
502b8322 | 1004 | subreg_hard_regno (rtx x, int check_mode) |
ddef6bc7 JJ |
1005 | { |
1006 | enum machine_mode mode = GET_MODE (x); | |
1007 | unsigned int byte_offset, base_regno, final_regno; | |
1008 | rtx reg = SUBREG_REG (x); | |
1009 | ||
1010 | /* This is where we attempt to catch illegal subregs | |
1011 | created by the compiler. */ | |
1012 | if (GET_CODE (x) != SUBREG | |
1013 | || GET_CODE (reg) != REG) | |
1014 | abort (); | |
1015 | base_regno = REGNO (reg); | |
1016 | if (base_regno >= FIRST_PSEUDO_REGISTER) | |
1017 | abort (); | |
0607953c | 1018 | if (check_mode && ! HARD_REGNO_MODE_OK (base_regno, GET_MODE (reg))) |
ddef6bc7 | 1019 | abort (); |
04c5580f JH |
1020 | #ifdef ENABLE_CHECKING |
1021 | if (!subreg_offset_representable_p (REGNO (reg), GET_MODE (reg), | |
502b8322 | 1022 | SUBREG_BYTE (x), mode)) |
04c5580f JH |
1023 | abort (); |
1024 | #endif | |
ddef6bc7 JJ |
1025 | /* Catch non-congruent offsets too. */ |
1026 | byte_offset = SUBREG_BYTE (x); | |
1027 | if ((byte_offset % GET_MODE_SIZE (mode)) != 0) | |
1028 | abort (); | |
1029 | ||
1030 | final_regno = subreg_regno (x); | |
1031 | ||
1032 | return final_regno; | |
1033 | } | |
1034 | ||
23b2ce53 RS |
1035 | /* Return a value representing some low-order bits of X, where the number |
1036 | of low-order bits is given by MODE. Note that no conversion is done | |
750c9258 | 1037 | between floating-point and fixed-point values, rather, the bit |
23b2ce53 RS |
1038 | representation is returned. |
1039 | ||
1040 | This function handles the cases in common between gen_lowpart, below, | |
1041 | and two variants in cse.c and combine.c. These are the cases that can | |
1042 | be safely handled at all points in the compilation. | |
1043 | ||
1044 | If this is not a case we can handle, return 0. */ | |
1045 | ||
1046 | rtx | |
502b8322 | 1047 | gen_lowpart_common (enum machine_mode mode, rtx x) |
23b2ce53 | 1048 | { |
ddef6bc7 JJ |
1049 | int msize = GET_MODE_SIZE (mode); |
1050 | int xsize = GET_MODE_SIZE (GET_MODE (x)); | |
1051 | int offset = 0; | |
23b2ce53 RS |
1052 | |
1053 | if (GET_MODE (x) == mode) | |
1054 | return x; | |
1055 | ||
1056 | /* MODE must occupy no more words than the mode of X. */ | |
1057 | if (GET_MODE (x) != VOIDmode | |
ddef6bc7 JJ |
1058 | && ((msize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD |
1059 | > ((xsize + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
23b2ce53 RS |
1060 | return 0; |
1061 | ||
53501a19 BS |
1062 | /* Don't allow generating paradoxical FLOAT_MODE subregs. */ |
1063 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1064 | && GET_MODE (x) != VOIDmode && msize > xsize) | |
1065 | return 0; | |
1066 | ||
e0e08ac2 | 1067 | offset = subreg_lowpart_offset (mode, GET_MODE (x)); |
23b2ce53 RS |
1068 | |
1069 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
1070 | && (GET_MODE_CLASS (mode) == MODE_INT |
1071 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
1072 | { |
1073 | /* If we are getting the low-order part of something that has been | |
1074 | sign- or zero-extended, we can either just use the object being | |
1075 | extended or make a narrower extension. If we want an even smaller | |
1076 | piece than the size of the object being extended, call ourselves | |
1077 | recursively. | |
1078 | ||
1079 | This case is used mostly by combine and cse. */ | |
1080 | ||
1081 | if (GET_MODE (XEXP (x, 0)) == mode) | |
1082 | return XEXP (x, 0); | |
1083 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
1084 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
1085 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3b80f6ca | 1086 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 | 1087 | } |
76321db6 | 1088 | else if (GET_CODE (x) == SUBREG || GET_CODE (x) == REG |
34a80643 | 1089 | || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR) |
e0e08ac2 | 1090 | return simplify_gen_subreg (mode, x, GET_MODE (x), offset); |
9f629a21 | 1091 | else if (VECTOR_MODE_P (mode) && GET_MODE (x) == VOIDmode) |
0488fa7c | 1092 | return simplify_gen_subreg (mode, x, int_mode_for_mode (mode), offset); |
23b2ce53 RS |
1093 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
1094 | from the low-order part of the constant. */ | |
83e9c679 RK |
1095 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
1096 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
1097 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 1098 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
1099 | { |
1100 | /* If MODE is twice the host word size, X is already the desired | |
1101 | representation. Otherwise, if MODE is wider than a word, we can't | |
e1389cac | 1102 | do this. If MODE is exactly a word, return just one CONST_INT. */ |
1a5b457d | 1103 | |
a8dd0e73 | 1104 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 1105 | return x; |
906c4e36 | 1106 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 1107 | return 0; |
906c4e36 | 1108 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 1109 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 1110 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
1111 | else |
1112 | { | |
27eef9ce | 1113 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
906c4e36 RK |
1114 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
1115 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 1116 | |
27eef9ce | 1117 | /* Sign extend to HOST_WIDE_INT. */ |
e1389cac | 1118 | val = trunc_int_for_mode (val, mode); |
1a5b457d RK |
1119 | |
1120 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 1121 | : GEN_INT (val)); |
1a5b457d RK |
1122 | } |
1123 | } | |
23b2ce53 | 1124 | |
ba31d94e | 1125 | /* The floating-point emulator can handle all conversions between |
a2061c0d GK |
1126 | FP and integer operands. This simplifies reload because it |
1127 | doesn't have to deal with constructs like (subreg:DI | |
1128 | (const_double:SF ...)) or (subreg:DF (const_int ...)). */ | |
57dadce2 EC |
1129 | /* Single-precision floats are always 32-bits and double-precision |
1130 | floats are always 64-bits. */ | |
a2061c0d | 1131 | |
76321db6 | 1132 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT |
57dadce2 | 1133 | && GET_MODE_BITSIZE (mode) == 32 |
a2061c0d | 1134 | && GET_CODE (x) == CONST_INT) |
68252e27 | 1135 | { |
a2061c0d | 1136 | REAL_VALUE_TYPE r; |
efdc7e19 | 1137 | long i = INTVAL (x); |
a2061c0d | 1138 | |
efdc7e19 | 1139 | real_from_target (&r, &i, mode); |
a2061c0d | 1140 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
68252e27 | 1141 | } |
76321db6 | 1142 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT |
57dadce2 | 1143 | && GET_MODE_BITSIZE (mode) == 64 |
a2061c0d GK |
1144 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
1145 | && GET_MODE (x) == VOIDmode) | |
1146 | { | |
1147 | REAL_VALUE_TYPE r; | |
a2061c0d | 1148 | HOST_WIDE_INT low, high; |
efdc7e19 | 1149 | long i[2]; |
a2061c0d GK |
1150 | |
1151 | if (GET_CODE (x) == CONST_INT) | |
1152 | { | |
1153 | low = INTVAL (x); | |
1154 | high = low >> (HOST_BITS_PER_WIDE_INT - 1); | |
1155 | } | |
1156 | else | |
1157 | { | |
750c9258 | 1158 | low = CONST_DOUBLE_LOW (x); |
a2061c0d GK |
1159 | high = CONST_DOUBLE_HIGH (x); |
1160 | } | |
1161 | ||
efdc7e19 RH |
1162 | if (HOST_BITS_PER_WIDE_INT > 32) |
1163 | high = low >> 31 >> 1; | |
1164 | ||
a2061c0d GK |
1165 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the |
1166 | target machine. */ | |
1167 | if (WORDS_BIG_ENDIAN) | |
1168 | i[0] = high, i[1] = low; | |
1169 | else | |
1170 | i[0] = low, i[1] = high; | |
1171 | ||
efdc7e19 | 1172 | real_from_target (&r, i, mode); |
a2061c0d GK |
1173 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
1174 | } | |
1175 | else if ((GET_MODE_CLASS (mode) == MODE_INT | |
1176 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
1177 | && GET_CODE (x) == CONST_DOUBLE | |
1178 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1179 | { | |
1180 | REAL_VALUE_TYPE r; | |
1181 | long i[4]; /* Only the low 32 bits of each 'long' are used. */ | |
1182 | int endian = WORDS_BIG_ENDIAN ? 1 : 0; | |
1183 | ||
8125704b GK |
1184 | /* Convert 'r' into an array of four 32-bit words in target word |
1185 | order. */ | |
a2061c0d | 1186 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
57dadce2 | 1187 | switch (GET_MODE_BITSIZE (GET_MODE (x))) |
a2061c0d | 1188 | { |
57dadce2 | 1189 | case 32: |
68252e27 | 1190 | REAL_VALUE_TO_TARGET_SINGLE (r, i[3 * endian]); |
8125704b GK |
1191 | i[1] = 0; |
1192 | i[2] = 0; | |
68252e27 KH |
1193 | i[3 - 3 * endian] = 0; |
1194 | break; | |
57dadce2 | 1195 | case 64: |
68252e27 | 1196 | REAL_VALUE_TO_TARGET_DOUBLE (r, i + 2 * endian); |
8125704b GK |
1197 | i[2 - 2 * endian] = 0; |
1198 | i[3 - 2 * endian] = 0; | |
68252e27 | 1199 | break; |
57dadce2 | 1200 | case 96: |
e389897b | 1201 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i + endian); |
8125704b | 1202 | i[3 - 3 * endian] = 0; |
76321db6 | 1203 | break; |
57dadce2 | 1204 | case 128: |
a2061c0d GK |
1205 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, i); |
1206 | break; | |
1207 | default: | |
1156b23c | 1208 | abort (); |
a2061c0d | 1209 | } |
a2061c0d GK |
1210 | /* Now, pack the 32-bit elements of the array into a CONST_DOUBLE |
1211 | and return it. */ | |
1212 | #if HOST_BITS_PER_WIDE_INT == 32 | |
8125704b | 1213 | return immed_double_const (i[3 * endian], i[1 + endian], mode); |
a2061c0d | 1214 | #else |
8125704b GK |
1215 | if (HOST_BITS_PER_WIDE_INT != 64) |
1216 | abort (); | |
50e60bc3 | 1217 | |
a76033a0 GK |
1218 | return immed_double_const ((((unsigned long) i[3 * endian]) |
1219 | | ((HOST_WIDE_INT) i[1 + endian] << 32)), | |
1220 | (((unsigned long) i[2 - endian]) | |
1221 | | ((HOST_WIDE_INT) i[3 - 3 * endian] << 32)), | |
8125704b | 1222 | mode); |
a2061c0d GK |
1223 | #endif |
1224 | } | |
14ca333d RS |
1225 | /* If MODE is a condition code and X is a CONST_INT, the value of X |
1226 | must already have been "recognized" by the back-end, and we can | |
1227 | assume that it is valid for this mode. */ | |
1228 | else if (GET_MODE_CLASS (mode) == MODE_CC | |
1229 | && GET_CODE (x) == CONST_INT) | |
1230 | return x; | |
8aada4ad | 1231 | |
23b2ce53 RS |
1232 | /* Otherwise, we can't do this. */ |
1233 | return 0; | |
1234 | } | |
1235 | \f | |
b1d673be RS |
1236 | /* Return the constant real or imaginary part (which has mode MODE) |
1237 | of a complex value X. The IMAGPART_P argument determines whether | |
1238 | the real or complex component should be returned. This function | |
1239 | returns NULL_RTX if the component isn't a constant. */ | |
1240 | ||
1241 | static rtx | |
502b8322 | 1242 | gen_complex_constant_part (enum machine_mode mode, rtx x, int imagpart_p) |
b1d673be RS |
1243 | { |
1244 | tree decl, part; | |
1245 | ||
1246 | if (GET_CODE (x) == MEM | |
4c2da7f2 | 1247 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) |
b1d673be RS |
1248 | { |
1249 | decl = SYMBOL_REF_DECL (XEXP (x, 0)); | |
1250 | if (decl != NULL_TREE && TREE_CODE (decl) == COMPLEX_CST) | |
1251 | { | |
1252 | part = imagpart_p ? TREE_IMAGPART (decl) : TREE_REALPART (decl); | |
1253 | if (TREE_CODE (part) == REAL_CST | |
1254 | || TREE_CODE (part) == INTEGER_CST) | |
1255 | return expand_expr (part, NULL_RTX, mode, 0); | |
1256 | } | |
1257 | } | |
1258 | return NULL_RTX; | |
1259 | } | |
1260 | ||
280194b0 RS |
1261 | /* Return the real part (which has mode MODE) of a complex value X. |
1262 | This always comes at the low address in memory. */ | |
1263 | ||
1264 | rtx | |
502b8322 | 1265 | gen_realpart (enum machine_mode mode, rtx x) |
280194b0 | 1266 | { |
b1d673be RS |
1267 | rtx part; |
1268 | ||
1269 | /* Handle complex constants. */ | |
1270 | part = gen_complex_constant_part (mode, x, 0); | |
1271 | if (part != NULL_RTX) | |
1272 | return part; | |
1273 | ||
e0e08ac2 JH |
1274 | if (WORDS_BIG_ENDIAN |
1275 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
1276 | && REG_P (x) | |
1277 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
400500c4 | 1278 | internal_error |
c725bd79 | 1279 | ("can't access real part of complex value in hard register"); |
dc139c90 | 1280 | else if (WORDS_BIG_ENDIAN) |
280194b0 RS |
1281 | return gen_highpart (mode, x); |
1282 | else | |
1283 | return gen_lowpart (mode, x); | |
1284 | } | |
1285 | ||
1286 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
1287 | This always comes at the high address in memory. */ | |
1288 | ||
1289 | rtx | |
502b8322 | 1290 | gen_imagpart (enum machine_mode mode, rtx x) |
280194b0 | 1291 | { |
b1d673be RS |
1292 | rtx part; |
1293 | ||
1294 | /* Handle complex constants. */ | |
1295 | part = gen_complex_constant_part (mode, x, 1); | |
1296 | if (part != NULL_RTX) | |
1297 | return part; | |
1298 | ||
e0e08ac2 | 1299 | if (WORDS_BIG_ENDIAN) |
280194b0 | 1300 | return gen_lowpart (mode, x); |
ddef6bc7 | 1301 | else if (! WORDS_BIG_ENDIAN |
40c0c3cf JL |
1302 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD |
1303 | && REG_P (x) | |
1304 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
400500c4 RK |
1305 | internal_error |
1306 | ("can't access imaginary part of complex value in hard register"); | |
280194b0 RS |
1307 | else |
1308 | return gen_highpart (mode, x); | |
1309 | } | |
81284a6a JW |
1310 | |
1311 | /* Return 1 iff X, assumed to be a SUBREG, | |
1312 | refers to the real part of the complex value in its containing reg. | |
1313 | Complex values are always stored with the real part in the first word, | |
1314 | regardless of WORDS_BIG_ENDIAN. */ | |
1315 | ||
1316 | int | |
502b8322 | 1317 | subreg_realpart_p (rtx x) |
81284a6a JW |
1318 | { |
1319 | if (GET_CODE (x) != SUBREG) | |
1320 | abort (); | |
1321 | ||
ddef6bc7 | 1322 | return ((unsigned int) SUBREG_BYTE (x) |
770ae6cc | 1323 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); |
81284a6a | 1324 | } |
280194b0 | 1325 | \f |
23b2ce53 RS |
1326 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1327 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1328 | least-significant part of X. | |
1329 | MODE specifies how big a part of X to return; | |
1330 | it usually should not be larger than a word. | |
1331 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1332 | ||
1333 | rtx | |
502b8322 | 1334 | gen_lowpart (enum machine_mode mode, rtx x) |
23b2ce53 RS |
1335 | { |
1336 | rtx result = gen_lowpart_common (mode, x); | |
1337 | ||
1338 | if (result) | |
1339 | return result; | |
ea8262b0 RK |
1340 | else if (GET_CODE (x) == REG) |
1341 | { | |
1342 | /* Must be a hard reg that's not valid in MODE. */ | |
1343 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1344 | if (result == 0) | |
1345 | abort (); | |
72c3833b | 1346 | return result; |
ea8262b0 | 1347 | } |
23b2ce53 RS |
1348 | else if (GET_CODE (x) == MEM) |
1349 | { | |
1350 | /* The only additional case we can do is MEM. */ | |
b3694847 | 1351 | int offset = 0; |
37f5242b RS |
1352 | |
1353 | /* The following exposes the use of "x" to CSE. */ | |
1354 | if (GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD | |
9dd04ab5 | 1355 | && SCALAR_INT_MODE_P (GET_MODE (x)) |
37f5242b RS |
1356 | && ! no_new_pseudos) |
1357 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
1358 | ||
23b2ce53 RS |
1359 | if (WORDS_BIG_ENDIAN) |
1360 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1361 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1362 | ||
1363 | if (BYTES_BIG_ENDIAN) | |
1364 | /* Adjust the address so that the address-after-the-data | |
1365 | is unchanged. */ | |
1366 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1367 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1368 | ||
f4ef873c | 1369 | return adjust_address (x, mode, offset); |
23b2ce53 | 1370 | } |
e9a25f70 JL |
1371 | else if (GET_CODE (x) == ADDRESSOF) |
1372 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
23b2ce53 RS |
1373 | else |
1374 | abort (); | |
1375 | } | |
1376 | ||
750c9258 | 1377 | /* Like `gen_lowpart', but refer to the most significant part. |
ccba022b RS |
1378 | This is used to access the imaginary part of a complex number. */ |
1379 | ||
1380 | rtx | |
502b8322 | 1381 | gen_highpart (enum machine_mode mode, rtx x) |
ccba022b | 1382 | { |
ddef6bc7 | 1383 | unsigned int msize = GET_MODE_SIZE (mode); |
e0e08ac2 | 1384 | rtx result; |
ddef6bc7 | 1385 | |
ccba022b RS |
1386 | /* This case loses if X is a subreg. To catch bugs early, |
1387 | complain if an invalid MODE is used even in other cases. */ | |
ddef6bc7 JJ |
1388 | if (msize > UNITS_PER_WORD |
1389 | && msize != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
ccba022b | 1390 | abort (); |
ddef6bc7 | 1391 | |
e0e08ac2 JH |
1392 | result = simplify_gen_subreg (mode, x, GET_MODE (x), |
1393 | subreg_highpart_offset (mode, GET_MODE (x))); | |
09482e0d JW |
1394 | |
1395 | /* simplify_gen_subreg is not guaranteed to return a valid operand for | |
1396 | the target if we have a MEM. gen_highpart must return a valid operand, | |
1397 | emitting code if necessary to do so. */ | |
13b8c631 | 1398 | if (result != NULL_RTX && GET_CODE (result) == MEM) |
09482e0d JW |
1399 | result = validize_mem (result); |
1400 | ||
e0e08ac2 JH |
1401 | if (!result) |
1402 | abort (); | |
1403 | return result; | |
1404 | } | |
5222e470 | 1405 | |
26d249eb | 1406 | /* Like gen_highpart, but accept mode of EXP operand in case EXP can |
5222e470 JH |
1407 | be VOIDmode constant. */ |
1408 | rtx | |
502b8322 | 1409 | gen_highpart_mode (enum machine_mode outermode, enum machine_mode innermode, rtx exp) |
5222e470 JH |
1410 | { |
1411 | if (GET_MODE (exp) != VOIDmode) | |
1412 | { | |
1413 | if (GET_MODE (exp) != innermode) | |
1414 | abort (); | |
1415 | return gen_highpart (outermode, exp); | |
1416 | } | |
1417 | return simplify_gen_subreg (outermode, exp, innermode, | |
1418 | subreg_highpart_offset (outermode, innermode)); | |
1419 | } | |
68252e27 | 1420 | |
e0e08ac2 JH |
1421 | /* Return offset in bytes to get OUTERMODE low part |
1422 | of the value in mode INNERMODE stored in memory in target format. */ | |
8698cce3 | 1423 | |
e0e08ac2 | 1424 | unsigned int |
502b8322 | 1425 | subreg_lowpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
e0e08ac2 JH |
1426 | { |
1427 | unsigned int offset = 0; | |
1428 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
8698cce3 | 1429 | |
e0e08ac2 | 1430 | if (difference > 0) |
ccba022b | 1431 | { |
e0e08ac2 JH |
1432 | if (WORDS_BIG_ENDIAN) |
1433 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; | |
1434 | if (BYTES_BIG_ENDIAN) | |
1435 | offset += difference % UNITS_PER_WORD; | |
ccba022b | 1436 | } |
ddef6bc7 | 1437 | |
e0e08ac2 | 1438 | return offset; |
ccba022b | 1439 | } |
eea50aa0 | 1440 | |
e0e08ac2 JH |
1441 | /* Return offset in bytes to get OUTERMODE high part |
1442 | of the value in mode INNERMODE stored in memory in target format. */ | |
1443 | unsigned int | |
502b8322 | 1444 | subreg_highpart_offset (enum machine_mode outermode, enum machine_mode innermode) |
eea50aa0 JH |
1445 | { |
1446 | unsigned int offset = 0; | |
1447 | int difference = (GET_MODE_SIZE (innermode) - GET_MODE_SIZE (outermode)); | |
1448 | ||
e0e08ac2 | 1449 | if (GET_MODE_SIZE (innermode) < GET_MODE_SIZE (outermode)) |
68252e27 | 1450 | abort (); |
e0e08ac2 | 1451 | |
eea50aa0 JH |
1452 | if (difference > 0) |
1453 | { | |
e0e08ac2 | 1454 | if (! WORDS_BIG_ENDIAN) |
eea50aa0 | 1455 | offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD; |
e0e08ac2 | 1456 | if (! BYTES_BIG_ENDIAN) |
eea50aa0 JH |
1457 | offset += difference % UNITS_PER_WORD; |
1458 | } | |
1459 | ||
e0e08ac2 | 1460 | return offset; |
eea50aa0 | 1461 | } |
ccba022b | 1462 | |
23b2ce53 RS |
1463 | /* Return 1 iff X, assumed to be a SUBREG, |
1464 | refers to the least significant part of its containing reg. | |
1465 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1466 | ||
1467 | int | |
502b8322 | 1468 | subreg_lowpart_p (rtx x) |
23b2ce53 RS |
1469 | { |
1470 | if (GET_CODE (x) != SUBREG) | |
1471 | return 1; | |
a3a03040 RK |
1472 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1473 | return 0; | |
23b2ce53 | 1474 | |
e0e08ac2 JH |
1475 | return (subreg_lowpart_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x))) |
1476 | == SUBREG_BYTE (x)); | |
23b2ce53 RS |
1477 | } |
1478 | \f | |
23b2ce53 | 1479 | |
ddef6bc7 JJ |
1480 | /* Helper routine for all the constant cases of operand_subword. |
1481 | Some places invoke this directly. */ | |
23b2ce53 RS |
1482 | |
1483 | rtx | |
502b8322 | 1484 | constant_subword (rtx op, int offset, enum machine_mode mode) |
23b2ce53 | 1485 | { |
906c4e36 | 1486 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; |
ddef6bc7 | 1487 | HOST_WIDE_INT val; |
23b2ce53 RS |
1488 | |
1489 | /* If OP is already an integer word, return it. */ | |
1490 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1491 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1492 | return op; | |
1493 | ||
5495cc55 RH |
1494 | /* The output is some bits, the width of the target machine's word. |
1495 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1496 | host can't. */ | |
9847c2f6 | 1497 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1632afca | 1498 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1499 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1500 | && GET_CODE (op) == CONST_DOUBLE) |
1501 | { | |
9847c2f6 | 1502 | long k[2]; |
1632afca RS |
1503 | REAL_VALUE_TYPE rv; |
1504 | ||
1505 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1506 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1507 | |
9847c2f6 | 1508 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 | 1509 | which the words are written depends on the word endianness. |
7677ffa4 | 1510 | ??? This is a potential portability problem and should |
7cae975e RH |
1511 | be fixed at some point. |
1512 | ||
a1f300c0 | 1513 | We must exercise caution with the sign bit. By definition there |
7cae975e RH |
1514 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. |
1515 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1516 | So we explicitly mask and sign-extend as necessary. */ | |
9847c2f6 | 1517 | if (BITS_PER_WORD == 32) |
7cae975e | 1518 | { |
ddef6bc7 | 1519 | val = k[offset]; |
7cae975e RH |
1520 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1521 | return GEN_INT (val); | |
1522 | } | |
1523 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
ddef6bc7 | 1524 | else if (BITS_PER_WORD >= 64 && offset == 0) |
7cae975e RH |
1525 | { |
1526 | val = k[! WORDS_BIG_ENDIAN]; | |
1527 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1528 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1529 | return GEN_INT (val); | |
1530 | } | |
9847c2f6 | 1531 | #endif |
47b34d40 JW |
1532 | else if (BITS_PER_WORD == 16) |
1533 | { | |
ddef6bc7 JJ |
1534 | val = k[offset >> 1]; |
1535 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) | |
7cae975e | 1536 | val >>= 16; |
73de376f | 1537 | val = ((val & 0xffff) ^ 0x8000) - 0x8000; |
7cae975e | 1538 | return GEN_INT (val); |
47b34d40 | 1539 | } |
7677ffa4 RK |
1540 | else |
1541 | abort (); | |
1632afca | 1542 | } |
a5559dbc RE |
1543 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1544 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1545 | && GET_MODE_BITSIZE (mode) > 64 | |
1546 | && GET_CODE (op) == CONST_DOUBLE) | |
5495cc55 RH |
1547 | { |
1548 | long k[4]; | |
1549 | REAL_VALUE_TYPE rv; | |
a5559dbc | 1550 | |
5495cc55 RH |
1551 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1552 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
a5559dbc | 1553 | |
5495cc55 RH |
1554 | if (BITS_PER_WORD == 32) |
1555 | { | |
ddef6bc7 | 1556 | val = k[offset]; |
5495cc55 RH |
1557 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; |
1558 | return GEN_INT (val); | |
1559 | } | |
1560 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
ddef6bc7 | 1561 | else if (BITS_PER_WORD >= 64 && offset <= 1) |
5495cc55 | 1562 | { |
ddef6bc7 | 1563 | val = k[offset * 2 + ! WORDS_BIG_ENDIAN]; |
5495cc55 | 1564 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; |
ddef6bc7 | 1565 | val |= (HOST_WIDE_INT) k[offset * 2 + WORDS_BIG_ENDIAN] & 0xffffffff; |
5495cc55 RH |
1566 | return GEN_INT (val); |
1567 | } | |
1568 | #endif | |
1569 | else | |
1570 | abort (); | |
1571 | } | |
23b2ce53 RS |
1572 | |
1573 | /* Single word float is a little harder, since single- and double-word | |
1574 | values often do not have the same high-order bits. We have already | |
1575 | verified that we want the only defined word of the single-word value. */ | |
9847c2f6 | 1576 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1577 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1578 | && GET_CODE (op) == CONST_DOUBLE) |
1579 | { | |
9847c2f6 | 1580 | long l; |
1632afca RS |
1581 | REAL_VALUE_TYPE rv; |
1582 | ||
1583 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1584 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
aa2ae679 | 1585 | |
7cae975e RH |
1586 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1587 | val = l; | |
1588 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
b5a3eb84 | 1589 | |
aa2ae679 JL |
1590 | if (BITS_PER_WORD == 16) |
1591 | { | |
ddef6bc7 | 1592 | if ((offset & 1) == ! WORDS_BIG_ENDIAN) |
7cae975e | 1593 | val >>= 16; |
73de376f | 1594 | val = ((val & 0xffff) ^ 0x8000) - 0x8000; |
aa2ae679 | 1595 | } |
7cae975e RH |
1596 | |
1597 | return GEN_INT (val); | |
1632afca | 1598 | } |
750c9258 | 1599 | |
23b2ce53 RS |
1600 | /* The only remaining cases that we can handle are integers. |
1601 | Convert to proper endianness now since these cases need it. | |
750c9258 | 1602 | At this point, offset == 0 means the low-order word. |
23b2ce53 | 1603 | |
2d4f57f8 RK |
1604 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1605 | in general. However, if OP is (const_int 0), we can just return | |
1606 | it for any word. */ | |
1607 | ||
1608 | if (op == const0_rtx) | |
1609 | return op; | |
23b2ce53 RS |
1610 | |
1611 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1612 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1613 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1614 | return 0; |
1615 | ||
1616 | if (WORDS_BIG_ENDIAN) | |
ddef6bc7 | 1617 | offset = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - offset; |
23b2ce53 RS |
1618 | |
1619 | /* Find out which word on the host machine this value is in and get | |
1620 | it from the constant. */ | |
ddef6bc7 | 1621 | val = (offset / size_ratio == 0 |
23b2ce53 RS |
1622 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) |
1623 | : (GET_CODE (op) == CONST_INT | |
1624 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1625 | ||
3f518020 | 1626 | /* Get the value we want into the low bits of val. */ |
906c4e36 | 1627 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
ddef6bc7 | 1628 | val = ((val >> ((offset % size_ratio) * BITS_PER_WORD))); |
3f518020 | 1629 | |
7e4ce834 | 1630 | val = trunc_int_for_mode (val, word_mode); |
23b2ce53 | 1631 | |
906c4e36 | 1632 | return GEN_INT (val); |
23b2ce53 RS |
1633 | } |
1634 | ||
ddef6bc7 JJ |
1635 | /* Return subword OFFSET of operand OP. |
1636 | The word number, OFFSET, is interpreted as the word number starting | |
1637 | at the low-order address. OFFSET 0 is the low-order word if not | |
1638 | WORDS_BIG_ENDIAN, otherwise it is the high-order word. | |
1639 | ||
1640 | If we cannot extract the required word, we return zero. Otherwise, | |
1641 | an rtx corresponding to the requested word will be returned. | |
1642 | ||
1643 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1644 | reload has completed, a valid address will always be returned. After | |
1645 | reload, if a valid address cannot be returned, we return zero. | |
1646 | ||
1647 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1648 | it is the responsibility of the caller. | |
1649 | ||
1650 | MODE is the mode of OP in case it is a CONST_INT. | |
1651 | ||
1652 | ??? This is still rather broken for some cases. The problem for the | |
1653 | moment is that all callers of this thing provide no 'goal mode' to | |
1654 | tell us to work with. This exists because all callers were written | |
0631e0bf JH |
1655 | in a word based SUBREG world. |
1656 | Now use of this function can be deprecated by simplify_subreg in most | |
1657 | cases. | |
1658 | */ | |
ddef6bc7 JJ |
1659 | |
1660 | rtx | |
502b8322 | 1661 | operand_subword (rtx op, unsigned int offset, int validate_address, enum machine_mode mode) |
ddef6bc7 JJ |
1662 | { |
1663 | if (mode == VOIDmode) | |
1664 | mode = GET_MODE (op); | |
1665 | ||
1666 | if (mode == VOIDmode) | |
1667 | abort (); | |
1668 | ||
30f7a378 | 1669 | /* If OP is narrower than a word, fail. */ |
ddef6bc7 JJ |
1670 | if (mode != BLKmode |
1671 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) | |
1672 | return 0; | |
1673 | ||
30f7a378 | 1674 | /* If we want a word outside OP, return zero. */ |
ddef6bc7 JJ |
1675 | if (mode != BLKmode |
1676 | && (offset + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1677 | return const0_rtx; | |
1678 | ||
ddef6bc7 JJ |
1679 | /* Form a new MEM at the requested address. */ |
1680 | if (GET_CODE (op) == MEM) | |
1681 | { | |
f1ec5147 | 1682 | rtx new = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD); |
ddef6bc7 | 1683 | |
f1ec5147 RK |
1684 | if (! validate_address) |
1685 | return new; | |
1686 | ||
1687 | else if (reload_completed) | |
ddef6bc7 | 1688 | { |
f1ec5147 RK |
1689 | if (! strict_memory_address_p (word_mode, XEXP (new, 0))) |
1690 | return 0; | |
ddef6bc7 | 1691 | } |
f1ec5147 RK |
1692 | else |
1693 | return replace_equiv_address (new, XEXP (new, 0)); | |
ddef6bc7 JJ |
1694 | } |
1695 | ||
0631e0bf JH |
1696 | /* Rest can be handled by simplify_subreg. */ |
1697 | return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD)); | |
ddef6bc7 JJ |
1698 | } |
1699 | ||
23b2ce53 RS |
1700 | /* Similar to `operand_subword', but never return 0. If we can't extract |
1701 | the required subword, put OP into a register and try again. If that fails, | |
750c9258 | 1702 | abort. We always validate the address in this case. |
23b2ce53 RS |
1703 | |
1704 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1705 | ||
1706 | rtx | |
502b8322 | 1707 | operand_subword_force (rtx op, unsigned int offset, enum machine_mode mode) |
23b2ce53 | 1708 | { |
ddef6bc7 | 1709 | rtx result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1710 | |
1711 | if (result) | |
1712 | return result; | |
1713 | ||
1714 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1715 | { |
1716 | /* If this is a register which can not be accessed by words, copy it | |
1717 | to a pseudo register. */ | |
1718 | if (GET_CODE (op) == REG) | |
1719 | op = copy_to_reg (op); | |
1720 | else | |
1721 | op = force_reg (mode, op); | |
1722 | } | |
23b2ce53 | 1723 | |
ddef6bc7 | 1724 | result = operand_subword (op, offset, 1, mode); |
23b2ce53 RS |
1725 | if (result == 0) |
1726 | abort (); | |
1727 | ||
1728 | return result; | |
1729 | } | |
1730 | \f | |
1731 | /* Given a compare instruction, swap the operands. | |
1732 | A test instruction is changed into a compare of 0 against the operand. */ | |
1733 | ||
1734 | void | |
502b8322 | 1735 | reverse_comparison (rtx insn) |
23b2ce53 RS |
1736 | { |
1737 | rtx body = PATTERN (insn); | |
1738 | rtx comp; | |
1739 | ||
1740 | if (GET_CODE (body) == SET) | |
1741 | comp = SET_SRC (body); | |
1742 | else | |
1743 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1744 | ||
1745 | if (GET_CODE (comp) == COMPARE) | |
1746 | { | |
1747 | rtx op0 = XEXP (comp, 0); | |
1748 | rtx op1 = XEXP (comp, 1); | |
1749 | XEXP (comp, 0) = op1; | |
1750 | XEXP (comp, 1) = op0; | |
1751 | } | |
1752 | else | |
1753 | { | |
c5c76735 JL |
1754 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1755 | CONST0_RTX (GET_MODE (comp)), comp); | |
23b2ce53 RS |
1756 | if (GET_CODE (body) == SET) |
1757 | SET_SRC (body) = new; | |
1758 | else | |
1759 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1760 | } | |
1761 | } | |
1762 | \f | |
998d7deb RH |
1763 | /* Within a MEM_EXPR, we care about either (1) a component ref of a decl, |
1764 | or (2) a component ref of something variable. Represent the later with | |
1765 | a NULL expression. */ | |
1766 | ||
1767 | static tree | |
502b8322 | 1768 | component_ref_for_mem_expr (tree ref) |
998d7deb RH |
1769 | { |
1770 | tree inner = TREE_OPERAND (ref, 0); | |
1771 | ||
1772 | if (TREE_CODE (inner) == COMPONENT_REF) | |
1773 | inner = component_ref_for_mem_expr (inner); | |
c56e3582 RK |
1774 | else |
1775 | { | |
1776 | tree placeholder_ptr = 0; | |
1777 | ||
1778 | /* Now remove any conversions: they don't change what the underlying | |
1779 | object is. Likewise for SAVE_EXPR. Also handle PLACEHOLDER_EXPR. */ | |
1780 | while (TREE_CODE (inner) == NOP_EXPR || TREE_CODE (inner) == CONVERT_EXPR | |
1781 | || TREE_CODE (inner) == NON_LVALUE_EXPR | |
1782 | || TREE_CODE (inner) == VIEW_CONVERT_EXPR | |
1783 | || TREE_CODE (inner) == SAVE_EXPR | |
1784 | || TREE_CODE (inner) == PLACEHOLDER_EXPR) | |
68252e27 KH |
1785 | if (TREE_CODE (inner) == PLACEHOLDER_EXPR) |
1786 | inner = find_placeholder (inner, &placeholder_ptr); | |
1787 | else | |
1788 | inner = TREE_OPERAND (inner, 0); | |
c56e3582 RK |
1789 | |
1790 | if (! DECL_P (inner)) | |
1791 | inner = NULL_TREE; | |
1792 | } | |
998d7deb RH |
1793 | |
1794 | if (inner == TREE_OPERAND (ref, 0)) | |
1795 | return ref; | |
1796 | else | |
c56e3582 RK |
1797 | return build (COMPONENT_REF, TREE_TYPE (ref), inner, |
1798 | TREE_OPERAND (ref, 1)); | |
998d7deb | 1799 | } |
173b24b9 RK |
1800 | |
1801 | /* Given REF, a MEM, and T, either the type of X or the expression | |
1802 | corresponding to REF, set the memory attributes. OBJECTP is nonzero | |
6f1087be RH |
1803 | if we are making a new object of this type. BITPOS is nonzero if |
1804 | there is an offset outstanding on T that will be applied later. */ | |
173b24b9 RK |
1805 | |
1806 | void | |
502b8322 AJ |
1807 | set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp, |
1808 | HOST_WIDE_INT bitpos) | |
173b24b9 | 1809 | { |
8ac61af7 | 1810 | HOST_WIDE_INT alias = MEM_ALIAS_SET (ref); |
998d7deb | 1811 | tree expr = MEM_EXPR (ref); |
8ac61af7 RK |
1812 | rtx offset = MEM_OFFSET (ref); |
1813 | rtx size = MEM_SIZE (ref); | |
1814 | unsigned int align = MEM_ALIGN (ref); | |
6f1087be | 1815 | HOST_WIDE_INT apply_bitpos = 0; |
173b24b9 RK |
1816 | tree type; |
1817 | ||
1818 | /* It can happen that type_for_mode was given a mode for which there | |
1819 | is no language-level type. In which case it returns NULL, which | |
1820 | we can see here. */ | |
1821 | if (t == NULL_TREE) | |
1822 | return; | |
1823 | ||
1824 | type = TYPE_P (t) ? t : TREE_TYPE (t); | |
1825 | ||
173b24b9 RK |
1826 | /* If we have already set DECL_RTL = ref, get_alias_set will get the |
1827 | wrong answer, as it assumes that DECL_RTL already has the right alias | |
1828 | info. Callers should not set DECL_RTL until after the call to | |
1829 | set_mem_attributes. */ | |
1830 | if (DECL_P (t) && ref == DECL_RTL_IF_SET (t)) | |
1831 | abort (); | |
1832 | ||
738cc472 | 1833 | /* Get the alias set from the expression or type (perhaps using a |
8ac61af7 RK |
1834 | front-end routine) and use it. */ |
1835 | alias = get_alias_set (t); | |
173b24b9 RK |
1836 | |
1837 | MEM_VOLATILE_P (ref) = TYPE_VOLATILE (type); | |
1838 | MEM_IN_STRUCT_P (ref) = AGGREGATE_TYPE_P (type); | |
03bf2c23 | 1839 | RTX_UNCHANGING_P (ref) |
1285011e RK |
1840 | |= ((lang_hooks.honor_readonly |
1841 | && (TYPE_READONLY (type) || TREE_READONLY (t))) | |
1842 | || (! TYPE_P (t) && TREE_CONSTANT (t))); | |
173b24b9 | 1843 | |
8ac61af7 RK |
1844 | /* If we are making an object of this type, or if this is a DECL, we know |
1845 | that it is a scalar if the type is not an aggregate. */ | |
1846 | if ((objectp || DECL_P (t)) && ! AGGREGATE_TYPE_P (type)) | |
173b24b9 RK |
1847 | MEM_SCALAR_P (ref) = 1; |
1848 | ||
c3d32120 RK |
1849 | /* We can set the alignment from the type if we are making an object, |
1850 | this is an INDIRECT_REF, or if TYPE_ALIGN_OK. */ | |
1851 | if (objectp || TREE_CODE (t) == INDIRECT_REF || TYPE_ALIGN_OK (type)) | |
1852 | align = MAX (align, TYPE_ALIGN (type)); | |
40c0668b | 1853 | |
738cc472 RK |
1854 | /* If the size is known, we can set that. */ |
1855 | if (TYPE_SIZE_UNIT (type) && host_integerp (TYPE_SIZE_UNIT (type), 1)) | |
8ac61af7 | 1856 | size = GEN_INT (tree_low_cst (TYPE_SIZE_UNIT (type), 1)); |
738cc472 | 1857 | |
80965c18 RK |
1858 | /* If T is not a type, we may be able to deduce some more information about |
1859 | the expression. */ | |
1860 | if (! TYPE_P (t)) | |
8ac61af7 RK |
1861 | { |
1862 | maybe_set_unchanging (ref, t); | |
1863 | if (TREE_THIS_VOLATILE (t)) | |
1864 | MEM_VOLATILE_P (ref) = 1; | |
173b24b9 | 1865 | |
c56e3582 RK |
1866 | /* Now remove any conversions: they don't change what the underlying |
1867 | object is. Likewise for SAVE_EXPR. */ | |
8ac61af7 | 1868 | while (TREE_CODE (t) == NOP_EXPR || TREE_CODE (t) == CONVERT_EXPR |
c56e3582 RK |
1869 | || TREE_CODE (t) == NON_LVALUE_EXPR |
1870 | || TREE_CODE (t) == VIEW_CONVERT_EXPR | |
1871 | || TREE_CODE (t) == SAVE_EXPR) | |
8ac61af7 RK |
1872 | t = TREE_OPERAND (t, 0); |
1873 | ||
10b76d73 RK |
1874 | /* If this expression can't be addressed (e.g., it contains a reference |
1875 | to a non-addressable field), show we don't change its alias set. */ | |
1876 | if (! can_address_p (t)) | |
1877 | MEM_KEEP_ALIAS_SET_P (ref) = 1; | |
1878 | ||
8ac61af7 RK |
1879 | /* If this is a decl, set the attributes of the MEM from it. */ |
1880 | if (DECL_P (t)) | |
1881 | { | |
998d7deb RH |
1882 | expr = t; |
1883 | offset = const0_rtx; | |
6f1087be | 1884 | apply_bitpos = bitpos; |
8ac61af7 RK |
1885 | size = (DECL_SIZE_UNIT (t) |
1886 | && host_integerp (DECL_SIZE_UNIT (t), 1) | |
1887 | ? GEN_INT (tree_low_cst (DECL_SIZE_UNIT (t), 1)) : 0); | |
68252e27 | 1888 | align = DECL_ALIGN (t); |
8ac61af7 RK |
1889 | } |
1890 | ||
40c0668b | 1891 | /* If this is a constant, we know the alignment. */ |
9ddfb1a7 RK |
1892 | else if (TREE_CODE_CLASS (TREE_CODE (t)) == 'c') |
1893 | { | |
1894 | align = TYPE_ALIGN (type); | |
1895 | #ifdef CONSTANT_ALIGNMENT | |
1896 | align = CONSTANT_ALIGNMENT (t, align); | |
1897 | #endif | |
1898 | } | |
998d7deb RH |
1899 | |
1900 | /* If this is a field reference and not a bit-field, record it. */ | |
1901 | /* ??? There is some information that can be gleened from bit-fields, | |
1902 | such as the word offset in the structure that might be modified. | |
1903 | But skip it for now. */ | |
1904 | else if (TREE_CODE (t) == COMPONENT_REF | |
1905 | && ! DECL_BIT_FIELD (TREE_OPERAND (t, 1))) | |
1906 | { | |
1907 | expr = component_ref_for_mem_expr (t); | |
1908 | offset = const0_rtx; | |
6f1087be | 1909 | apply_bitpos = bitpos; |
998d7deb RH |
1910 | /* ??? Any reason the field size would be different than |
1911 | the size we got from the type? */ | |
1912 | } | |
1913 | ||
1914 | /* If this is an array reference, look for an outer field reference. */ | |
1915 | else if (TREE_CODE (t) == ARRAY_REF) | |
1916 | { | |
1917 | tree off_tree = size_zero_node; | |
1918 | ||
1919 | do | |
1920 | { | |
2567406a JH |
1921 | tree index = TREE_OPERAND (t, 1); |
1922 | tree array = TREE_OPERAND (t, 0); | |
1923 | tree domain = TYPE_DOMAIN (TREE_TYPE (array)); | |
1924 | tree low_bound = (domain ? TYPE_MIN_VALUE (domain) : 0); | |
1925 | tree unit_size = TYPE_SIZE_UNIT (TREE_TYPE (TREE_TYPE (array))); | |
1926 | ||
1927 | /* We assume all arrays have sizes that are a multiple of a byte. | |
1928 | First subtract the lower bound, if any, in the type of the | |
1929 | index, then convert to sizetype and multiply by the size of the | |
1930 | array element. */ | |
1931 | if (low_bound != 0 && ! integer_zerop (low_bound)) | |
1932 | index = fold (build (MINUS_EXPR, TREE_TYPE (index), | |
1933 | index, low_bound)); | |
1934 | ||
1935 | /* If the index has a self-referential type, pass it to a | |
1936 | WITH_RECORD_EXPR; if the component size is, pass our | |
1937 | component to one. */ | |
7a6cdb44 | 1938 | if (CONTAINS_PLACEHOLDER_P (index)) |
2567406a | 1939 | index = build (WITH_RECORD_EXPR, TREE_TYPE (index), index, t); |
7a6cdb44 | 1940 | if (CONTAINS_PLACEHOLDER_P (unit_size)) |
2567406a JH |
1941 | unit_size = build (WITH_RECORD_EXPR, sizetype, |
1942 | unit_size, array); | |
1943 | ||
998d7deb RH |
1944 | off_tree |
1945 | = fold (build (PLUS_EXPR, sizetype, | |
1946 | fold (build (MULT_EXPR, sizetype, | |
2567406a JH |
1947 | index, |
1948 | unit_size)), | |
998d7deb RH |
1949 | off_tree)); |
1950 | t = TREE_OPERAND (t, 0); | |
1951 | } | |
1952 | while (TREE_CODE (t) == ARRAY_REF); | |
1953 | ||
c67a1cf6 RH |
1954 | if (DECL_P (t)) |
1955 | { | |
1956 | expr = t; | |
40cb04f1 | 1957 | offset = NULL; |
c67a1cf6 | 1958 | if (host_integerp (off_tree, 1)) |
40cb04f1 RH |
1959 | { |
1960 | HOST_WIDE_INT ioff = tree_low_cst (off_tree, 1); | |
1961 | HOST_WIDE_INT aoff = (ioff & -ioff) * BITS_PER_UNIT; | |
1962 | align = DECL_ALIGN (t); | |
fc555370 | 1963 | if (aoff && (unsigned HOST_WIDE_INT) aoff < align) |
40cb04f1 RH |
1964 | align = aoff; |
1965 | offset = GEN_INT (ioff); | |
6f1087be | 1966 | apply_bitpos = bitpos; |
40cb04f1 | 1967 | } |
c67a1cf6 RH |
1968 | } |
1969 | else if (TREE_CODE (t) == COMPONENT_REF) | |
998d7deb RH |
1970 | { |
1971 | expr = component_ref_for_mem_expr (t); | |
1972 | if (host_integerp (off_tree, 1)) | |
6f1087be RH |
1973 | { |
1974 | offset = GEN_INT (tree_low_cst (off_tree, 1)); | |
1975 | apply_bitpos = bitpos; | |
1976 | } | |
998d7deb RH |
1977 | /* ??? Any reason the field size would be different than |
1978 | the size we got from the type? */ | |
1979 | } | |
c67a1cf6 RH |
1980 | else if (flag_argument_noalias > 1 |
1981 | && TREE_CODE (t) == INDIRECT_REF | |
1982 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) | |
1983 | { | |
1984 | expr = t; | |
1985 | offset = NULL; | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | /* If this is a Fortran indirect argument reference, record the | |
1990 | parameter decl. */ | |
1991 | else if (flag_argument_noalias > 1 | |
1992 | && TREE_CODE (t) == INDIRECT_REF | |
1993 | && TREE_CODE (TREE_OPERAND (t, 0)) == PARM_DECL) | |
1994 | { | |
1995 | expr = t; | |
1996 | offset = NULL; | |
998d7deb | 1997 | } |
8ac61af7 RK |
1998 | } |
1999 | ||
15c812e3 | 2000 | /* If we modified OFFSET based on T, then subtract the outstanding |
8c317c5f RH |
2001 | bit position offset. Similarly, increase the size of the accessed |
2002 | object to contain the negative offset. */ | |
6f1087be | 2003 | if (apply_bitpos) |
8c317c5f RH |
2004 | { |
2005 | offset = plus_constant (offset, -(apply_bitpos / BITS_PER_UNIT)); | |
2006 | if (size) | |
2007 | size = plus_constant (size, apply_bitpos / BITS_PER_UNIT); | |
2008 | } | |
6f1087be | 2009 | |
8ac61af7 | 2010 | /* Now set the attributes we computed above. */ |
10b76d73 | 2011 | MEM_ATTRS (ref) |
998d7deb | 2012 | = get_mem_attrs (alias, expr, offset, size, align, GET_MODE (ref)); |
8ac61af7 RK |
2013 | |
2014 | /* If this is already known to be a scalar or aggregate, we are done. */ | |
2015 | if (MEM_IN_STRUCT_P (ref) || MEM_SCALAR_P (ref)) | |
738cc472 RK |
2016 | return; |
2017 | ||
8ac61af7 RK |
2018 | /* If it is a reference into an aggregate, this is part of an aggregate. |
2019 | Otherwise we don't know. */ | |
173b24b9 RK |
2020 | else if (TREE_CODE (t) == COMPONENT_REF || TREE_CODE (t) == ARRAY_REF |
2021 | || TREE_CODE (t) == ARRAY_RANGE_REF | |
2022 | || TREE_CODE (t) == BIT_FIELD_REF) | |
2023 | MEM_IN_STRUCT_P (ref) = 1; | |
2024 | } | |
2025 | ||
6f1087be | 2026 | void |
502b8322 | 2027 | set_mem_attributes (rtx ref, tree t, int objectp) |
6f1087be RH |
2028 | { |
2029 | set_mem_attributes_minus_bitpos (ref, t, objectp, 0); | |
2030 | } | |
2031 | ||
a560d4d4 JH |
2032 | /* Set the decl for MEM to DECL. */ |
2033 | ||
2034 | void | |
502b8322 | 2035 | set_mem_attrs_from_reg (rtx mem, rtx reg) |
a560d4d4 JH |
2036 | { |
2037 | MEM_ATTRS (mem) | |
2038 | = get_mem_attrs (MEM_ALIAS_SET (mem), REG_EXPR (reg), | |
2039 | GEN_INT (REG_OFFSET (reg)), | |
2040 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); | |
2041 | } | |
2042 | ||
173b24b9 RK |
2043 | /* Set the alias set of MEM to SET. */ |
2044 | ||
2045 | void | |
502b8322 | 2046 | set_mem_alias_set (rtx mem, HOST_WIDE_INT set) |
173b24b9 | 2047 | { |
68252e27 | 2048 | #ifdef ENABLE_CHECKING |
173b24b9 RK |
2049 | /* If the new and old alias sets don't conflict, something is wrong. */ |
2050 | if (!alias_sets_conflict_p (set, MEM_ALIAS_SET (mem))) | |
2051 | abort (); | |
173b24b9 RK |
2052 | #endif |
2053 | ||
998d7deb | 2054 | MEM_ATTRS (mem) = get_mem_attrs (set, MEM_EXPR (mem), MEM_OFFSET (mem), |
10b76d73 RK |
2055 | MEM_SIZE (mem), MEM_ALIGN (mem), |
2056 | GET_MODE (mem)); | |
173b24b9 | 2057 | } |
738cc472 | 2058 | |
d022d93e | 2059 | /* Set the alignment of MEM to ALIGN bits. */ |
738cc472 RK |
2060 | |
2061 | void | |
502b8322 | 2062 | set_mem_align (rtx mem, unsigned int align) |
738cc472 | 2063 | { |
998d7deb | 2064 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), |
10b76d73 RK |
2065 | MEM_OFFSET (mem), MEM_SIZE (mem), align, |
2066 | GET_MODE (mem)); | |
738cc472 | 2067 | } |
1285011e | 2068 | |
998d7deb | 2069 | /* Set the expr for MEM to EXPR. */ |
1285011e RK |
2070 | |
2071 | void | |
502b8322 | 2072 | set_mem_expr (rtx mem, tree expr) |
1285011e RK |
2073 | { |
2074 | MEM_ATTRS (mem) | |
998d7deb | 2075 | = get_mem_attrs (MEM_ALIAS_SET (mem), expr, MEM_OFFSET (mem), |
1285011e RK |
2076 | MEM_SIZE (mem), MEM_ALIGN (mem), GET_MODE (mem)); |
2077 | } | |
998d7deb RH |
2078 | |
2079 | /* Set the offset of MEM to OFFSET. */ | |
2080 | ||
2081 | void | |
502b8322 | 2082 | set_mem_offset (rtx mem, rtx offset) |
998d7deb RH |
2083 | { |
2084 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
2085 | offset, MEM_SIZE (mem), MEM_ALIGN (mem), | |
2086 | GET_MODE (mem)); | |
35aff10b AM |
2087 | } |
2088 | ||
2089 | /* Set the size of MEM to SIZE. */ | |
2090 | ||
2091 | void | |
502b8322 | 2092 | set_mem_size (rtx mem, rtx size) |
35aff10b AM |
2093 | { |
2094 | MEM_ATTRS (mem) = get_mem_attrs (MEM_ALIAS_SET (mem), MEM_EXPR (mem), | |
2095 | MEM_OFFSET (mem), size, MEM_ALIGN (mem), | |
2096 | GET_MODE (mem)); | |
998d7deb | 2097 | } |
173b24b9 | 2098 | \f |
738cc472 RK |
2099 | /* Return a memory reference like MEMREF, but with its mode changed to MODE |
2100 | and its address changed to ADDR. (VOIDmode means don't change the mode. | |
2101 | NULL for ADDR means don't change the address.) VALIDATE is nonzero if the | |
2102 | returned memory location is required to be valid. The memory | |
2103 | attributes are not changed. */ | |
23b2ce53 | 2104 | |
738cc472 | 2105 | static rtx |
502b8322 | 2106 | change_address_1 (rtx memref, enum machine_mode mode, rtx addr, int validate) |
23b2ce53 RS |
2107 | { |
2108 | rtx new; | |
2109 | ||
2110 | if (GET_CODE (memref) != MEM) | |
2111 | abort (); | |
2112 | if (mode == VOIDmode) | |
2113 | mode = GET_MODE (memref); | |
2114 | if (addr == 0) | |
2115 | addr = XEXP (memref, 0); | |
2116 | ||
f1ec5147 | 2117 | if (validate) |
23b2ce53 | 2118 | { |
f1ec5147 RK |
2119 | if (reload_in_progress || reload_completed) |
2120 | { | |
2121 | if (! memory_address_p (mode, addr)) | |
2122 | abort (); | |
2123 | } | |
2124 | else | |
2125 | addr = memory_address (mode, addr); | |
23b2ce53 | 2126 | } |
750c9258 | 2127 | |
9b04c6a8 RK |
2128 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
2129 | return memref; | |
2130 | ||
3b80f6ca | 2131 | new = gen_rtx_MEM (mode, addr); |
c6df88cb | 2132 | MEM_COPY_ATTRIBUTES (new, memref); |
23b2ce53 RS |
2133 | return new; |
2134 | } | |
792760b9 | 2135 | |
738cc472 RK |
2136 | /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what |
2137 | way we are changing MEMREF, so we only preserve the alias set. */ | |
f4ef873c RK |
2138 | |
2139 | rtx | |
502b8322 | 2140 | change_address (rtx memref, enum machine_mode mode, rtx addr) |
f4ef873c | 2141 | { |
738cc472 RK |
2142 | rtx new = change_address_1 (memref, mode, addr, 1); |
2143 | enum machine_mode mmode = GET_MODE (new); | |
c2f7bcc3 | 2144 | |
738cc472 RK |
2145 | MEM_ATTRS (new) |
2146 | = get_mem_attrs (MEM_ALIAS_SET (memref), 0, 0, | |
2147 | mmode == BLKmode ? 0 : GEN_INT (GET_MODE_SIZE (mmode)), | |
a06ef755 RK |
2148 | (mmode == BLKmode ? BITS_PER_UNIT |
2149 | : GET_MODE_ALIGNMENT (mmode)), | |
10b76d73 | 2150 | mmode); |
823e3574 | 2151 | |
738cc472 | 2152 | return new; |
f4ef873c | 2153 | } |
792760b9 | 2154 | |
738cc472 RK |
2155 | /* Return a memory reference like MEMREF, but with its mode changed |
2156 | to MODE and its address offset by OFFSET bytes. If VALIDATE is | |
630036c6 JJ |
2157 | nonzero, the memory address is forced to be valid. |
2158 | If ADJUST is zero, OFFSET is only used to update MEM_ATTRS | |
2159 | and caller is responsible for adjusting MEMREF base register. */ | |
f1ec5147 RK |
2160 | |
2161 | rtx | |
502b8322 AJ |
2162 | adjust_address_1 (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset, |
2163 | int validate, int adjust) | |
f1ec5147 | 2164 | { |
823e3574 | 2165 | rtx addr = XEXP (memref, 0); |
738cc472 RK |
2166 | rtx new; |
2167 | rtx memoffset = MEM_OFFSET (memref); | |
10b76d73 | 2168 | rtx size = 0; |
738cc472 | 2169 | unsigned int memalign = MEM_ALIGN (memref); |
823e3574 | 2170 | |
d14419e4 | 2171 | /* ??? Prefer to create garbage instead of creating shared rtl. |
cc2902df | 2172 | This may happen even if offset is nonzero -- consider |
d14419e4 RH |
2173 | (plus (plus reg reg) const_int) -- so do this always. */ |
2174 | addr = copy_rtx (addr); | |
2175 | ||
4a78c787 RH |
2176 | if (adjust) |
2177 | { | |
2178 | /* If MEMREF is a LO_SUM and the offset is within the alignment of the | |
2179 | object, we can merge it into the LO_SUM. */ | |
2180 | if (GET_MODE (memref) != BLKmode && GET_CODE (addr) == LO_SUM | |
2181 | && offset >= 0 | |
2182 | && (unsigned HOST_WIDE_INT) offset | |
2183 | < GET_MODE_ALIGNMENT (GET_MODE (memref)) / BITS_PER_UNIT) | |
2184 | addr = gen_rtx_LO_SUM (Pmode, XEXP (addr, 0), | |
2185 | plus_constant (XEXP (addr, 1), offset)); | |
2186 | else | |
2187 | addr = plus_constant (addr, offset); | |
2188 | } | |
823e3574 | 2189 | |
738cc472 RK |
2190 | new = change_address_1 (memref, mode, addr, validate); |
2191 | ||
2192 | /* Compute the new values of the memory attributes due to this adjustment. | |
2193 | We add the offsets and update the alignment. */ | |
2194 | if (memoffset) | |
2195 | memoffset = GEN_INT (offset + INTVAL (memoffset)); | |
2196 | ||
03bf2c23 RK |
2197 | /* Compute the new alignment by taking the MIN of the alignment and the |
2198 | lowest-order set bit in OFFSET, but don't change the alignment if OFFSET | |
2199 | if zero. */ | |
2200 | if (offset != 0) | |
3bf1e984 RK |
2201 | memalign |
2202 | = MIN (memalign, | |
2203 | (unsigned HOST_WIDE_INT) (offset & -offset) * BITS_PER_UNIT); | |
738cc472 | 2204 | |
10b76d73 | 2205 | /* We can compute the size in a number of ways. */ |
a06ef755 RK |
2206 | if (GET_MODE (new) != BLKmode) |
2207 | size = GEN_INT (GET_MODE_SIZE (GET_MODE (new))); | |
10b76d73 RK |
2208 | else if (MEM_SIZE (memref)) |
2209 | size = plus_constant (MEM_SIZE (memref), -offset); | |
2210 | ||
998d7deb | 2211 | MEM_ATTRS (new) = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), |
10b76d73 | 2212 | memoffset, size, memalign, GET_MODE (new)); |
738cc472 RK |
2213 | |
2214 | /* At some point, we should validate that this offset is within the object, | |
2215 | if all the appropriate values are known. */ | |
2216 | return new; | |
f1ec5147 RK |
2217 | } |
2218 | ||
630036c6 JJ |
2219 | /* Return a memory reference like MEMREF, but with its mode changed |
2220 | to MODE and its address changed to ADDR, which is assumed to be | |
2221 | MEMREF offseted by OFFSET bytes. If VALIDATE is | |
2222 | nonzero, the memory address is forced to be valid. */ | |
2223 | ||
2224 | rtx | |
502b8322 AJ |
2225 | adjust_automodify_address_1 (rtx memref, enum machine_mode mode, rtx addr, |
2226 | HOST_WIDE_INT offset, int validate) | |
630036c6 JJ |
2227 | { |
2228 | memref = change_address_1 (memref, VOIDmode, addr, validate); | |
2229 | return adjust_address_1 (memref, mode, offset, validate, 0); | |
2230 | } | |
2231 | ||
8ac61af7 RK |
2232 | /* Return a memory reference like MEMREF, but whose address is changed by |
2233 | adding OFFSET, an RTX, to it. POW2 is the highest power of two factor | |
2234 | known to be in OFFSET (possibly 1). */ | |
0d4903b8 RK |
2235 | |
2236 | rtx | |
502b8322 | 2237 | offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2) |
0d4903b8 | 2238 | { |
e3c8ea67 RH |
2239 | rtx new, addr = XEXP (memref, 0); |
2240 | ||
2241 | new = simplify_gen_binary (PLUS, Pmode, addr, offset); | |
2242 | ||
68252e27 | 2243 | /* At this point we don't know _why_ the address is invalid. It |
e3c8ea67 RH |
2244 | could have secondary memory refereces, multiplies or anything. |
2245 | ||
2246 | However, if we did go and rearrange things, we can wind up not | |
2247 | being able to recognize the magic around pic_offset_table_rtx. | |
2248 | This stuff is fragile, and is yet another example of why it is | |
2249 | bad to expose PIC machinery too early. */ | |
2250 | if (! memory_address_p (GET_MODE (memref), new) | |
2251 | && GET_CODE (addr) == PLUS | |
2252 | && XEXP (addr, 0) == pic_offset_table_rtx) | |
2253 | { | |
2254 | addr = force_reg (GET_MODE (addr), addr); | |
2255 | new = simplify_gen_binary (PLUS, Pmode, addr, offset); | |
2256 | } | |
2257 | ||
f6041ed8 | 2258 | update_temp_slot_address (XEXP (memref, 0), new); |
e3c8ea67 | 2259 | new = change_address_1 (memref, VOIDmode, new, 1); |
0d4903b8 RK |
2260 | |
2261 | /* Update the alignment to reflect the offset. Reset the offset, which | |
2262 | we don't know. */ | |
2cc2d4bb RK |
2263 | MEM_ATTRS (new) |
2264 | = get_mem_attrs (MEM_ALIAS_SET (memref), MEM_EXPR (memref), 0, 0, | |
9ceca302 | 2265 | MIN (MEM_ALIGN (memref), pow2 * BITS_PER_UNIT), |
2cc2d4bb | 2266 | GET_MODE (new)); |
0d4903b8 RK |
2267 | return new; |
2268 | } | |
68252e27 | 2269 | |
792760b9 RK |
2270 | /* Return a memory reference like MEMREF, but with its address changed to |
2271 | ADDR. The caller is asserting that the actual piece of memory pointed | |
2272 | to is the same, just the form of the address is being changed, such as | |
2273 | by putting something into a register. */ | |
2274 | ||
2275 | rtx | |
502b8322 | 2276 | replace_equiv_address (rtx memref, rtx addr) |
792760b9 | 2277 | { |
738cc472 RK |
2278 | /* change_address_1 copies the memory attribute structure without change |
2279 | and that's exactly what we want here. */ | |
40c0668b | 2280 | update_temp_slot_address (XEXP (memref, 0), addr); |
738cc472 | 2281 | return change_address_1 (memref, VOIDmode, addr, 1); |
792760b9 | 2282 | } |
738cc472 | 2283 | |
f1ec5147 RK |
2284 | /* Likewise, but the reference is not required to be valid. */ |
2285 | ||
2286 | rtx | |
502b8322 | 2287 | replace_equiv_address_nv (rtx memref, rtx addr) |
f1ec5147 | 2288 | { |
f1ec5147 RK |
2289 | return change_address_1 (memref, VOIDmode, addr, 0); |
2290 | } | |
e7dfe4bb RH |
2291 | |
2292 | /* Return a memory reference like MEMREF, but with its mode widened to | |
2293 | MODE and offset by OFFSET. This would be used by targets that e.g. | |
2294 | cannot issue QImode memory operations and have to use SImode memory | |
2295 | operations plus masking logic. */ | |
2296 | ||
2297 | rtx | |
502b8322 | 2298 | widen_memory_access (rtx memref, enum machine_mode mode, HOST_WIDE_INT offset) |
e7dfe4bb RH |
2299 | { |
2300 | rtx new = adjust_address_1 (memref, mode, offset, 1, 1); | |
2301 | tree expr = MEM_EXPR (new); | |
2302 | rtx memoffset = MEM_OFFSET (new); | |
2303 | unsigned int size = GET_MODE_SIZE (mode); | |
2304 | ||
2305 | /* If we don't know what offset we were at within the expression, then | |
2306 | we can't know if we've overstepped the bounds. */ | |
fa1591cb | 2307 | if (! memoffset) |
e7dfe4bb RH |
2308 | expr = NULL_TREE; |
2309 | ||
2310 | while (expr) | |
2311 | { | |
2312 | if (TREE_CODE (expr) == COMPONENT_REF) | |
2313 | { | |
2314 | tree field = TREE_OPERAND (expr, 1); | |
2315 | ||
2316 | if (! DECL_SIZE_UNIT (field)) | |
2317 | { | |
2318 | expr = NULL_TREE; | |
2319 | break; | |
2320 | } | |
2321 | ||
2322 | /* Is the field at least as large as the access? If so, ok, | |
2323 | otherwise strip back to the containing structure. */ | |
03667700 RK |
2324 | if (TREE_CODE (DECL_SIZE_UNIT (field)) == INTEGER_CST |
2325 | && compare_tree_int (DECL_SIZE_UNIT (field), size) >= 0 | |
e7dfe4bb RH |
2326 | && INTVAL (memoffset) >= 0) |
2327 | break; | |
2328 | ||
2329 | if (! host_integerp (DECL_FIELD_OFFSET (field), 1)) | |
2330 | { | |
2331 | expr = NULL_TREE; | |
2332 | break; | |
2333 | } | |
2334 | ||
2335 | expr = TREE_OPERAND (expr, 0); | |
2336 | memoffset = (GEN_INT (INTVAL (memoffset) | |
2337 | + tree_low_cst (DECL_FIELD_OFFSET (field), 1) | |
2338 | + (tree_low_cst (DECL_FIELD_BIT_OFFSET (field), 1) | |
2339 | / BITS_PER_UNIT))); | |
2340 | } | |
2341 | /* Similarly for the decl. */ | |
2342 | else if (DECL_P (expr) | |
2343 | && DECL_SIZE_UNIT (expr) | |
45f79783 | 2344 | && TREE_CODE (DECL_SIZE_UNIT (expr)) == INTEGER_CST |
e7dfe4bb RH |
2345 | && compare_tree_int (DECL_SIZE_UNIT (expr), size) >= 0 |
2346 | && (! memoffset || INTVAL (memoffset) >= 0)) | |
2347 | break; | |
2348 | else | |
2349 | { | |
2350 | /* The widened memory access overflows the expression, which means | |
2351 | that it could alias another expression. Zap it. */ | |
2352 | expr = NULL_TREE; | |
2353 | break; | |
2354 | } | |
2355 | } | |
2356 | ||
2357 | if (! expr) | |
2358 | memoffset = NULL_RTX; | |
2359 | ||
2360 | /* The widened memory may alias other stuff, so zap the alias set. */ | |
2361 | /* ??? Maybe use get_alias_set on any remaining expression. */ | |
2362 | ||
2363 | MEM_ATTRS (new) = get_mem_attrs (0, expr, memoffset, GEN_INT (size), | |
2364 | MEM_ALIGN (new), mode); | |
2365 | ||
2366 | return new; | |
2367 | } | |
23b2ce53 RS |
2368 | \f |
2369 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
2370 | ||
2371 | rtx | |
502b8322 | 2372 | gen_label_rtx (void) |
23b2ce53 | 2373 | { |
0dc36574 | 2374 | return gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, NULL_RTX, |
502b8322 | 2375 | NULL, label_num++, NULL); |
23b2ce53 RS |
2376 | } |
2377 | \f | |
2378 | /* For procedure integration. */ | |
2379 | ||
23b2ce53 | 2380 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 2381 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
2382 | Used for an inline-procedure after copying the insn chain. */ |
2383 | ||
2384 | void | |
502b8322 | 2385 | set_new_first_and_last_insn (rtx first, rtx last) |
23b2ce53 | 2386 | { |
86fe05e0 RK |
2387 | rtx insn; |
2388 | ||
23b2ce53 RS |
2389 | first_insn = first; |
2390 | last_insn = last; | |
86fe05e0 RK |
2391 | cur_insn_uid = 0; |
2392 | ||
2393 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2394 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
2395 | ||
2396 | cur_insn_uid++; | |
23b2ce53 RS |
2397 | } |
2398 | ||
2399 | /* Set the range of label numbers found in the current function. | |
2400 | This is used when belatedly compiling an inline function. */ | |
2401 | ||
2402 | void | |
502b8322 | 2403 | set_new_first_and_last_label_num (int first, int last) |
23b2ce53 RS |
2404 | { |
2405 | base_label_num = label_num; | |
2406 | first_label_num = first; | |
2407 | last_label_num = last; | |
2408 | } | |
49ad7cfa BS |
2409 | |
2410 | /* Set the last label number found in the current function. | |
2411 | This is used when belatedly compiling an inline function. */ | |
23b2ce53 RS |
2412 | |
2413 | void | |
502b8322 | 2414 | set_new_last_label_num (int last) |
23b2ce53 | 2415 | { |
49ad7cfa BS |
2416 | base_label_num = label_num; |
2417 | last_label_num = last; | |
23b2ce53 | 2418 | } |
49ad7cfa | 2419 | \f |
23b2ce53 RS |
2420 | /* Restore all variables describing the current status from the structure *P. |
2421 | This is used after a nested function. */ | |
2422 | ||
2423 | void | |
502b8322 | 2424 | restore_emit_status (struct function *p ATTRIBUTE_UNUSED) |
23b2ce53 | 2425 | { |
457a2d9c | 2426 | last_label_num = 0; |
23b2ce53 RS |
2427 | } |
2428 | \f | |
750c9258 | 2429 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 | 2430 | structure. This routine should only be called once. */ |
23b2ce53 RS |
2431 | |
2432 | void | |
502b8322 | 2433 | unshare_all_rtl (tree fndecl, rtx insn) |
23b2ce53 | 2434 | { |
d1b81779 | 2435 | tree decl; |
23b2ce53 | 2436 | |
d1b81779 GK |
2437 | /* Make sure that virtual parameters are not shared. */ |
2438 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
19e7881c | 2439 | SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl))); |
d1b81779 | 2440 | |
5c6df058 AO |
2441 | /* Make sure that virtual stack slots are not shared. */ |
2442 | unshare_all_decls (DECL_INITIAL (fndecl)); | |
2443 | ||
d1b81779 GK |
2444 | /* Unshare just about everything else. */ |
2445 | unshare_all_rtl_1 (insn); | |
750c9258 | 2446 | |
23b2ce53 RS |
2447 | /* Make sure the addresses of stack slots found outside the insn chain |
2448 | (such as, in DECL_RTL of a variable) are not shared | |
2449 | with the insn chain. | |
2450 | ||
2451 | This special care is necessary when the stack slot MEM does not | |
2452 | actually appear in the insn chain. If it does appear, its address | |
2453 | is unshared from all else at that point. */ | |
242b0ce6 | 2454 | stack_slot_list = copy_rtx_if_shared (stack_slot_list); |
23b2ce53 RS |
2455 | } |
2456 | ||
750c9258 | 2457 | /* Go through all the RTL insn bodies and copy any invalid shared |
d1b81779 GK |
2458 | structure, again. This is a fairly expensive thing to do so it |
2459 | should be done sparingly. */ | |
2460 | ||
2461 | void | |
502b8322 | 2462 | unshare_all_rtl_again (rtx insn) |
d1b81779 GK |
2463 | { |
2464 | rtx p; | |
624c87aa RE |
2465 | tree decl; |
2466 | ||
d1b81779 | 2467 | for (p = insn; p; p = NEXT_INSN (p)) |
2c3c49de | 2468 | if (INSN_P (p)) |
d1b81779 GK |
2469 | { |
2470 | reset_used_flags (PATTERN (p)); | |
2471 | reset_used_flags (REG_NOTES (p)); | |
2472 | reset_used_flags (LOG_LINKS (p)); | |
2473 | } | |
624c87aa | 2474 | |
2d4aecb3 AO |
2475 | /* Make sure that virtual stack slots are not shared. */ |
2476 | reset_used_decls (DECL_INITIAL (cfun->decl)); | |
2477 | ||
624c87aa RE |
2478 | /* Make sure that virtual parameters are not shared. */ |
2479 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
2480 | reset_used_flags (DECL_RTL (decl)); | |
2481 | ||
2482 | reset_used_flags (stack_slot_list); | |
2483 | ||
2484 | unshare_all_rtl (cfun->decl, insn); | |
d1b81779 GK |
2485 | } |
2486 | ||
2487 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
2488 | Assumes the mark bits are cleared at entry. */ | |
2489 | ||
2490 | static void | |
502b8322 | 2491 | unshare_all_rtl_1 (rtx insn) |
d1b81779 GK |
2492 | { |
2493 | for (; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 2494 | if (INSN_P (insn)) |
d1b81779 GK |
2495 | { |
2496 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
2497 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
2498 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
2499 | } | |
2500 | } | |
2501 | ||
5c6df058 AO |
2502 | /* Go through all virtual stack slots of a function and copy any |
2503 | shared structure. */ | |
2504 | static void | |
502b8322 | 2505 | unshare_all_decls (tree blk) |
5c6df058 AO |
2506 | { |
2507 | tree t; | |
2508 | ||
2509 | /* Copy shared decls. */ | |
2510 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c MM |
2511 | if (DECL_RTL_SET_P (t)) |
2512 | SET_DECL_RTL (t, copy_rtx_if_shared (DECL_RTL (t))); | |
5c6df058 AO |
2513 | |
2514 | /* Now process sub-blocks. */ | |
2515 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
2516 | unshare_all_decls (t); | |
2517 | } | |
2518 | ||
2d4aecb3 | 2519 | /* Go through all virtual stack slots of a function and mark them as |
30f7a378 | 2520 | not shared. */ |
2d4aecb3 | 2521 | static void |
502b8322 | 2522 | reset_used_decls (tree blk) |
2d4aecb3 AO |
2523 | { |
2524 | tree t; | |
2525 | ||
2526 | /* Mark decls. */ | |
2527 | for (t = BLOCK_VARS (blk); t; t = TREE_CHAIN (t)) | |
19e7881c MM |
2528 | if (DECL_RTL_SET_P (t)) |
2529 | reset_used_flags (DECL_RTL (t)); | |
2d4aecb3 AO |
2530 | |
2531 | /* Now process sub-blocks. */ | |
2532 | for (t = BLOCK_SUBBLOCKS (blk); t; t = TREE_CHAIN (t)) | |
2533 | reset_used_decls (t); | |
2534 | } | |
2535 | ||
127c1ba5 | 2536 | /* Similar to `copy_rtx' except that if MAY_SHARE is present, it is |
93fe8e92 RK |
2537 | placed in the result directly, rather than being copied. MAY_SHARE is |
2538 | either a MEM of an EXPR_LIST of MEMs. */ | |
127c1ba5 RK |
2539 | |
2540 | rtx | |
502b8322 | 2541 | copy_most_rtx (rtx orig, rtx may_share) |
127c1ba5 RK |
2542 | { |
2543 | rtx copy; | |
2544 | int i, j; | |
2545 | RTX_CODE code; | |
2546 | const char *format_ptr; | |
2547 | ||
93fe8e92 RK |
2548 | if (orig == may_share |
2549 | || (GET_CODE (may_share) == EXPR_LIST | |
2550 | && in_expr_list_p (may_share, orig))) | |
127c1ba5 RK |
2551 | return orig; |
2552 | ||
2553 | code = GET_CODE (orig); | |
2554 | ||
2555 | switch (code) | |
2556 | { | |
2557 | case REG: | |
2558 | case QUEUED: | |
2559 | case CONST_INT: | |
2560 | case CONST_DOUBLE: | |
2561 | case CONST_VECTOR: | |
2562 | case SYMBOL_REF: | |
2563 | case CODE_LABEL: | |
2564 | case PC: | |
2565 | case CC0: | |
2566 | return orig; | |
2567 | default: | |
2568 | break; | |
2569 | } | |
2570 | ||
2571 | copy = rtx_alloc (code); | |
2572 | PUT_MODE (copy, GET_MODE (orig)); | |
2adc7f12 JJ |
2573 | RTX_FLAG (copy, in_struct) = RTX_FLAG (orig, in_struct); |
2574 | RTX_FLAG (copy, volatil) = RTX_FLAG (orig, volatil); | |
2575 | RTX_FLAG (copy, unchanging) = RTX_FLAG (orig, unchanging); | |
2576 | RTX_FLAG (copy, integrated) = RTX_FLAG (orig, integrated); | |
2577 | RTX_FLAG (copy, frame_related) = RTX_FLAG (orig, frame_related); | |
127c1ba5 RK |
2578 | |
2579 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
2580 | ||
2581 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
2582 | { | |
2583 | switch (*format_ptr++) | |
2584 | { | |
2585 | case 'e': | |
2586 | XEXP (copy, i) = XEXP (orig, i); | |
2587 | if (XEXP (orig, i) != NULL && XEXP (orig, i) != may_share) | |
2588 | XEXP (copy, i) = copy_most_rtx (XEXP (orig, i), may_share); | |
2589 | break; | |
2590 | ||
2591 | case 'u': | |
2592 | XEXP (copy, i) = XEXP (orig, i); | |
2593 | break; | |
2594 | ||
2595 | case 'E': | |
2596 | case 'V': | |
2597 | XVEC (copy, i) = XVEC (orig, i); | |
2598 | if (XVEC (orig, i) != NULL) | |
2599 | { | |
2600 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
2601 | for (j = 0; j < XVECLEN (copy, i); j++) | |
2602 | XVECEXP (copy, i, j) | |
2603 | = copy_most_rtx (XVECEXP (orig, i, j), may_share); | |
2604 | } | |
2605 | break; | |
2606 | ||
2607 | case 'w': | |
2608 | XWINT (copy, i) = XWINT (orig, i); | |
2609 | break; | |
2610 | ||
2611 | case 'n': | |
2612 | case 'i': | |
2613 | XINT (copy, i) = XINT (orig, i); | |
2614 | break; | |
2615 | ||
2616 | case 't': | |
2617 | XTREE (copy, i) = XTREE (orig, i); | |
2618 | break; | |
2619 | ||
2620 | case 's': | |
2621 | case 'S': | |
2622 | XSTR (copy, i) = XSTR (orig, i); | |
2623 | break; | |
2624 | ||
2625 | case '0': | |
2626 | /* Copy this through the wide int field; that's safest. */ | |
2627 | X0WINT (copy, i) = X0WINT (orig, i); | |
2628 | break; | |
2629 | ||
2630 | default: | |
2631 | abort (); | |
2632 | } | |
2633 | } | |
2634 | return copy; | |
2635 | } | |
2636 | ||
23b2ce53 RS |
2637 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
2638 | Recursively does the same for subexpressions. */ | |
2639 | ||
2640 | rtx | |
502b8322 | 2641 | copy_rtx_if_shared (rtx orig) |
23b2ce53 | 2642 | { |
b3694847 SS |
2643 | rtx x = orig; |
2644 | int i; | |
2645 | enum rtx_code code; | |
2646 | const char *format_ptr; | |
23b2ce53 RS |
2647 | int copied = 0; |
2648 | ||
2649 | if (x == 0) | |
2650 | return 0; | |
2651 | ||
2652 | code = GET_CODE (x); | |
2653 | ||
2654 | /* These types may be freely shared. */ | |
2655 | ||
2656 | switch (code) | |
2657 | { | |
2658 | case REG: | |
2659 | case QUEUED: | |
2660 | case CONST_INT: | |
2661 | case CONST_DOUBLE: | |
69ef87e2 | 2662 | case CONST_VECTOR: |
23b2ce53 RS |
2663 | case SYMBOL_REF: |
2664 | case CODE_LABEL: | |
2665 | case PC: | |
2666 | case CC0: | |
2667 | case SCRATCH: | |
0f41302f | 2668 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
2669 | return x; |
2670 | ||
b851ea09 RK |
2671 | case CONST: |
2672 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
2673 | a LABEL_REF, it isn't sharable. */ | |
2674 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2675 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2676 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
2677 | return x; | |
2678 | break; | |
2679 | ||
23b2ce53 RS |
2680 | case INSN: |
2681 | case JUMP_INSN: | |
2682 | case CALL_INSN: | |
2683 | case NOTE: | |
23b2ce53 RS |
2684 | case BARRIER: |
2685 | /* The chain of insns is not being copied. */ | |
2686 | return x; | |
2687 | ||
2688 | case MEM: | |
83512665 JL |
2689 | /* A MEM is allowed to be shared if its address is constant. |
2690 | ||
750c9258 | 2691 | We used to allow sharing of MEMs which referenced |
83512665 JL |
2692 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but |
2693 | that can lose. instantiate_virtual_regs will not unshare | |
2694 | the MEMs, and combine may change the structure of the address | |
2695 | because it looks safe and profitable in one context, but | |
2696 | in some other context it creates unrecognizable RTL. */ | |
2697 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
23b2ce53 RS |
2698 | return x; |
2699 | ||
e9a25f70 JL |
2700 | break; |
2701 | ||
2702 | default: | |
2703 | break; | |
23b2ce53 RS |
2704 | } |
2705 | ||
2706 | /* This rtx may not be shared. If it has already been seen, | |
2707 | replace it with a copy of itself. */ | |
2708 | ||
2adc7f12 | 2709 | if (RTX_FLAG (x, used)) |
23b2ce53 | 2710 | { |
b3694847 | 2711 | rtx copy; |
23b2ce53 RS |
2712 | |
2713 | copy = rtx_alloc (code); | |
4e135bdd | 2714 | memcpy (copy, x, |
4c9a05bc RK |
2715 | (sizeof (*copy) - sizeof (copy->fld) |
2716 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
2717 | x = copy; |
2718 | copied = 1; | |
2719 | } | |
2adc7f12 | 2720 | RTX_FLAG (x, used) = 1; |
23b2ce53 RS |
2721 | |
2722 | /* Now scan the subexpressions recursively. | |
2723 | We can store any replaced subexpressions directly into X | |
2724 | since we know X is not shared! Any vectors in X | |
2725 | must be copied if X was copied. */ | |
2726 | ||
2727 | format_ptr = GET_RTX_FORMAT (code); | |
2728 | ||
2729 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2730 | { | |
2731 | switch (*format_ptr++) | |
2732 | { | |
2733 | case 'e': | |
2734 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
2735 | break; | |
2736 | ||
2737 | case 'E': | |
2738 | if (XVEC (x, i) != NULL) | |
2739 | { | |
b3694847 | 2740 | int j; |
f0722107 | 2741 | int len = XVECLEN (x, i); |
23b2ce53 | 2742 | |
f0722107 | 2743 | if (copied && len > 0) |
8f985ec4 | 2744 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
f0722107 RS |
2745 | for (j = 0; j < len; j++) |
2746 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
2747 | } |
2748 | break; | |
2749 | } | |
2750 | } | |
2751 | return x; | |
2752 | } | |
2753 | ||
2754 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
2755 | to look for shared sub-parts. */ | |
2756 | ||
2757 | void | |
502b8322 | 2758 | reset_used_flags (rtx x) |
23b2ce53 | 2759 | { |
b3694847 SS |
2760 | int i, j; |
2761 | enum rtx_code code; | |
2762 | const char *format_ptr; | |
23b2ce53 RS |
2763 | |
2764 | if (x == 0) | |
2765 | return; | |
2766 | ||
2767 | code = GET_CODE (x); | |
2768 | ||
9faa82d8 | 2769 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
2770 | for them. */ |
2771 | ||
2772 | switch (code) | |
2773 | { | |
2774 | case REG: | |
2775 | case QUEUED: | |
2776 | case CONST_INT: | |
2777 | case CONST_DOUBLE: | |
69ef87e2 | 2778 | case CONST_VECTOR: |
23b2ce53 RS |
2779 | case SYMBOL_REF: |
2780 | case CODE_LABEL: | |
2781 | case PC: | |
2782 | case CC0: | |
2783 | return; | |
2784 | ||
2785 | case INSN: | |
2786 | case JUMP_INSN: | |
2787 | case CALL_INSN: | |
2788 | case NOTE: | |
2789 | case LABEL_REF: | |
2790 | case BARRIER: | |
2791 | /* The chain of insns is not being copied. */ | |
2792 | return; | |
750c9258 | 2793 | |
e9a25f70 JL |
2794 | default: |
2795 | break; | |
23b2ce53 RS |
2796 | } |
2797 | ||
2adc7f12 | 2798 | RTX_FLAG (x, used) = 0; |
23b2ce53 RS |
2799 | |
2800 | format_ptr = GET_RTX_FORMAT (code); | |
2801 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
2802 | { | |
2803 | switch (*format_ptr++) | |
2804 | { | |
2805 | case 'e': | |
2806 | reset_used_flags (XEXP (x, i)); | |
2807 | break; | |
2808 | ||
2809 | case 'E': | |
2810 | for (j = 0; j < XVECLEN (x, i); j++) | |
2811 | reset_used_flags (XVECEXP (x, i, j)); | |
2812 | break; | |
2813 | } | |
2814 | } | |
2815 | } | |
2816 | \f | |
2817 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
2818 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
2819 | OTHER must be valid as a SET_DEST. */ | |
2820 | ||
2821 | rtx | |
502b8322 | 2822 | make_safe_from (rtx x, rtx other) |
23b2ce53 RS |
2823 | { |
2824 | while (1) | |
2825 | switch (GET_CODE (other)) | |
2826 | { | |
2827 | case SUBREG: | |
2828 | other = SUBREG_REG (other); | |
2829 | break; | |
2830 | case STRICT_LOW_PART: | |
2831 | case SIGN_EXTEND: | |
2832 | case ZERO_EXTEND: | |
2833 | other = XEXP (other, 0); | |
2834 | break; | |
2835 | default: | |
2836 | goto done; | |
2837 | } | |
2838 | done: | |
2839 | if ((GET_CODE (other) == MEM | |
2840 | && ! CONSTANT_P (x) | |
2841 | && GET_CODE (x) != REG | |
2842 | && GET_CODE (x) != SUBREG) | |
2843 | || (GET_CODE (other) == REG | |
2844 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
2845 | || reg_mentioned_p (other, x)))) | |
2846 | { | |
2847 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
2848 | emit_move_insn (temp, x); | |
2849 | return temp; | |
2850 | } | |
2851 | return x; | |
2852 | } | |
2853 | \f | |
2854 | /* Emission of insns (adding them to the doubly-linked list). */ | |
2855 | ||
2856 | /* Return the first insn of the current sequence or current function. */ | |
2857 | ||
2858 | rtx | |
502b8322 | 2859 | get_insns (void) |
23b2ce53 RS |
2860 | { |
2861 | return first_insn; | |
2862 | } | |
2863 | ||
3dec4024 JH |
2864 | /* Specify a new insn as the first in the chain. */ |
2865 | ||
2866 | void | |
502b8322 | 2867 | set_first_insn (rtx insn) |
3dec4024 JH |
2868 | { |
2869 | if (PREV_INSN (insn) != 0) | |
2870 | abort (); | |
2871 | first_insn = insn; | |
2872 | } | |
2873 | ||
23b2ce53 RS |
2874 | /* Return the last insn emitted in current sequence or current function. */ |
2875 | ||
2876 | rtx | |
502b8322 | 2877 | get_last_insn (void) |
23b2ce53 RS |
2878 | { |
2879 | return last_insn; | |
2880 | } | |
2881 | ||
2882 | /* Specify a new insn as the last in the chain. */ | |
2883 | ||
2884 | void | |
502b8322 | 2885 | set_last_insn (rtx insn) |
23b2ce53 RS |
2886 | { |
2887 | if (NEXT_INSN (insn) != 0) | |
2888 | abort (); | |
2889 | last_insn = insn; | |
2890 | } | |
2891 | ||
2892 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2893 | ||
2894 | rtx | |
502b8322 | 2895 | get_last_insn_anywhere (void) |
23b2ce53 RS |
2896 | { |
2897 | struct sequence_stack *stack; | |
2898 | if (last_insn) | |
2899 | return last_insn; | |
49ad7cfa | 2900 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2901 | if (stack->last != 0) |
2902 | return stack->last; | |
2903 | return 0; | |
2904 | } | |
2905 | ||
2a496e8b JDA |
2906 | /* Return the first nonnote insn emitted in current sequence or current |
2907 | function. This routine looks inside SEQUENCEs. */ | |
2908 | ||
2909 | rtx | |
502b8322 | 2910 | get_first_nonnote_insn (void) |
2a496e8b JDA |
2911 | { |
2912 | rtx insn = first_insn; | |
2913 | ||
2914 | while (insn) | |
2915 | { | |
2916 | insn = next_insn (insn); | |
2917 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2918 | break; | |
2919 | } | |
2920 | ||
2921 | return insn; | |
2922 | } | |
2923 | ||
2924 | /* Return the last nonnote insn emitted in current sequence or current | |
2925 | function. This routine looks inside SEQUENCEs. */ | |
2926 | ||
2927 | rtx | |
502b8322 | 2928 | get_last_nonnote_insn (void) |
2a496e8b JDA |
2929 | { |
2930 | rtx insn = last_insn; | |
2931 | ||
2932 | while (insn) | |
2933 | { | |
2934 | insn = previous_insn (insn); | |
2935 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2936 | break; | |
2937 | } | |
2938 | ||
2939 | return insn; | |
2940 | } | |
2941 | ||
23b2ce53 RS |
2942 | /* Return a number larger than any instruction's uid in this function. */ |
2943 | ||
2944 | int | |
502b8322 | 2945 | get_max_uid (void) |
23b2ce53 RS |
2946 | { |
2947 | return cur_insn_uid; | |
2948 | } | |
aeeeda03 | 2949 | |
673b5311 MM |
2950 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2951 | ||
aeeeda03 | 2952 | void |
502b8322 | 2953 | renumber_insns (FILE *stream) |
aeeeda03 MM |
2954 | { |
2955 | rtx insn; | |
aeeeda03 | 2956 | |
673b5311 MM |
2957 | /* If we're not supposed to renumber instructions, don't. */ |
2958 | if (!flag_renumber_insns) | |
2959 | return; | |
2960 | ||
aeeeda03 MM |
2961 | /* If there aren't that many instructions, then it's not really |
2962 | worth renumbering them. */ | |
673b5311 | 2963 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
aeeeda03 MM |
2964 | return; |
2965 | ||
2966 | cur_insn_uid = 1; | |
2967 | ||
2968 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
673b5311 MM |
2969 | { |
2970 | if (stream) | |
750c9258 | 2971 | fprintf (stream, "Renumbering insn %d to %d\n", |
673b5311 MM |
2972 | INSN_UID (insn), cur_insn_uid); |
2973 | INSN_UID (insn) = cur_insn_uid++; | |
2974 | } | |
aeeeda03 | 2975 | } |
23b2ce53 RS |
2976 | \f |
2977 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2978 | of the sequence. */ | |
2979 | ||
2980 | rtx | |
502b8322 | 2981 | next_insn (rtx insn) |
23b2ce53 RS |
2982 | { |
2983 | if (insn) | |
2984 | { | |
2985 | insn = NEXT_INSN (insn); | |
2986 | if (insn && GET_CODE (insn) == INSN | |
2987 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2988 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2989 | } | |
2990 | ||
2991 | return insn; | |
2992 | } | |
2993 | ||
2994 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2995 | of the sequence. */ | |
2996 | ||
2997 | rtx | |
502b8322 | 2998 | previous_insn (rtx insn) |
23b2ce53 RS |
2999 | { |
3000 | if (insn) | |
3001 | { | |
3002 | insn = PREV_INSN (insn); | |
3003 | if (insn && GET_CODE (insn) == INSN | |
3004 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3005 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
3006 | } | |
3007 | ||
3008 | return insn; | |
3009 | } | |
3010 | ||
3011 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
3012 | look inside SEQUENCEs. */ | |
3013 | ||
3014 | rtx | |
502b8322 | 3015 | next_nonnote_insn (rtx insn) |
23b2ce53 RS |
3016 | { |
3017 | while (insn) | |
3018 | { | |
3019 | insn = NEXT_INSN (insn); | |
3020 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
3021 | break; | |
3022 | } | |
3023 | ||
3024 | return insn; | |
3025 | } | |
3026 | ||
3027 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
3028 | not look inside SEQUENCEs. */ | |
3029 | ||
3030 | rtx | |
502b8322 | 3031 | prev_nonnote_insn (rtx insn) |
23b2ce53 RS |
3032 | { |
3033 | while (insn) | |
3034 | { | |
3035 | insn = PREV_INSN (insn); | |
3036 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
3037 | break; | |
3038 | } | |
3039 | ||
3040 | return insn; | |
3041 | } | |
3042 | ||
3043 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
3044 | or 0, if there is none. This routine does not look inside | |
0f41302f | 3045 | SEQUENCEs. */ |
23b2ce53 RS |
3046 | |
3047 | rtx | |
502b8322 | 3048 | next_real_insn (rtx insn) |
23b2ce53 RS |
3049 | { |
3050 | while (insn) | |
3051 | { | |
3052 | insn = NEXT_INSN (insn); | |
3053 | if (insn == 0 || GET_CODE (insn) == INSN | |
3054 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
3055 | break; | |
3056 | } | |
3057 | ||
3058 | return insn; | |
3059 | } | |
3060 | ||
3061 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
3062 | or 0, if there is none. This routine does not look inside | |
3063 | SEQUENCEs. */ | |
3064 | ||
3065 | rtx | |
502b8322 | 3066 | prev_real_insn (rtx insn) |
23b2ce53 RS |
3067 | { |
3068 | while (insn) | |
3069 | { | |
3070 | insn = PREV_INSN (insn); | |
3071 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
3072 | || GET_CODE (insn) == JUMP_INSN) | |
3073 | break; | |
3074 | } | |
3075 | ||
3076 | return insn; | |
3077 | } | |
3078 | ||
ee960939 OH |
3079 | /* Return the last CALL_INSN in the current list, or 0 if there is none. |
3080 | This routine does not look inside SEQUENCEs. */ | |
3081 | ||
3082 | rtx | |
502b8322 | 3083 | last_call_insn (void) |
ee960939 OH |
3084 | { |
3085 | rtx insn; | |
3086 | ||
3087 | for (insn = get_last_insn (); | |
3088 | insn && GET_CODE (insn) != CALL_INSN; | |
3089 | insn = PREV_INSN (insn)) | |
3090 | ; | |
3091 | ||
3092 | return insn; | |
3093 | } | |
3094 | ||
23b2ce53 RS |
3095 | /* Find the next insn after INSN that really does something. This routine |
3096 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3097 | same as next_real_insn. */ | |
3098 | ||
69732dcb | 3099 | int |
502b8322 | 3100 | active_insn_p (rtx insn) |
69732dcb | 3101 | { |
23b8ba81 RH |
3102 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN |
3103 | || (GET_CODE (insn) == INSN | |
3104 | && (! reload_completed | |
3105 | || (GET_CODE (PATTERN (insn)) != USE | |
3106 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
69732dcb RH |
3107 | } |
3108 | ||
23b2ce53 | 3109 | rtx |
502b8322 | 3110 | next_active_insn (rtx insn) |
23b2ce53 RS |
3111 | { |
3112 | while (insn) | |
3113 | { | |
3114 | insn = NEXT_INSN (insn); | |
69732dcb | 3115 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
3116 | break; |
3117 | } | |
3118 | ||
3119 | return insn; | |
3120 | } | |
3121 | ||
3122 | /* Find the last insn before INSN that really does something. This routine | |
3123 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
3124 | same as prev_real_insn. */ | |
3125 | ||
3126 | rtx | |
502b8322 | 3127 | prev_active_insn (rtx insn) |
23b2ce53 RS |
3128 | { |
3129 | while (insn) | |
3130 | { | |
3131 | insn = PREV_INSN (insn); | |
69732dcb | 3132 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
3133 | break; |
3134 | } | |
3135 | ||
3136 | return insn; | |
3137 | } | |
3138 | ||
3139 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
3140 | ||
3141 | rtx | |
502b8322 | 3142 | next_label (rtx insn) |
23b2ce53 RS |
3143 | { |
3144 | while (insn) | |
3145 | { | |
3146 | insn = NEXT_INSN (insn); | |
3147 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
3148 | break; | |
3149 | } | |
3150 | ||
3151 | return insn; | |
3152 | } | |
3153 | ||
3154 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
3155 | ||
3156 | rtx | |
502b8322 | 3157 | prev_label (rtx insn) |
23b2ce53 RS |
3158 | { |
3159 | while (insn) | |
3160 | { | |
3161 | insn = PREV_INSN (insn); | |
3162 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
3163 | break; | |
3164 | } | |
3165 | ||
3166 | return insn; | |
3167 | } | |
3168 | \f | |
3169 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
3170 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
3171 | and REG_CC_USER notes so we can find it. */ | |
3172 | ||
3173 | void | |
502b8322 | 3174 | link_cc0_insns (rtx insn) |
c572e5ba JVA |
3175 | { |
3176 | rtx user = next_nonnote_insn (insn); | |
3177 | ||
3178 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
3179 | user = XVECEXP (PATTERN (user), 0, 0); | |
3180 | ||
c5c76735 JL |
3181 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
3182 | REG_NOTES (user)); | |
3b80f6ca | 3183 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
3184 | } |
3185 | ||
23b2ce53 RS |
3186 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
3187 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
3188 | applied to the result of this function should yield INSN). | |
3189 | ||
3190 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
3191 | is present, it contains the insn that uses CC0. | |
3192 | ||
3193 | Return 0 if we can't find the insn. */ | |
3194 | ||
3195 | rtx | |
502b8322 | 3196 | next_cc0_user (rtx insn) |
23b2ce53 | 3197 | { |
906c4e36 | 3198 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
3199 | |
3200 | if (note) | |
3201 | return XEXP (note, 0); | |
3202 | ||
3203 | insn = next_nonnote_insn (insn); | |
3204 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3205 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3206 | ||
2c3c49de | 3207 | if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn))) |
23b2ce53 RS |
3208 | return insn; |
3209 | ||
3210 | return 0; | |
3211 | } | |
3212 | ||
3213 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
3214 | note, it is the previous insn. */ | |
3215 | ||
3216 | rtx | |
502b8322 | 3217 | prev_cc0_setter (rtx insn) |
23b2ce53 | 3218 | { |
906c4e36 | 3219 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
3220 | |
3221 | if (note) | |
3222 | return XEXP (note, 0); | |
3223 | ||
3224 | insn = prev_nonnote_insn (insn); | |
3225 | if (! sets_cc0_p (PATTERN (insn))) | |
3226 | abort (); | |
3227 | ||
3228 | return insn; | |
3229 | } | |
3230 | #endif | |
e5bef2e4 HB |
3231 | |
3232 | /* Increment the label uses for all labels present in rtx. */ | |
3233 | ||
3234 | static void | |
502b8322 | 3235 | mark_label_nuses (rtx x) |
e5bef2e4 | 3236 | { |
b3694847 SS |
3237 | enum rtx_code code; |
3238 | int i, j; | |
3239 | const char *fmt; | |
e5bef2e4 HB |
3240 | |
3241 | code = GET_CODE (x); | |
3242 | if (code == LABEL_REF) | |
3243 | LABEL_NUSES (XEXP (x, 0))++; | |
3244 | ||
3245 | fmt = GET_RTX_FORMAT (code); | |
3246 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3247 | { | |
3248 | if (fmt[i] == 'e') | |
0fb7aeda | 3249 | mark_label_nuses (XEXP (x, i)); |
e5bef2e4 | 3250 | else if (fmt[i] == 'E') |
0fb7aeda | 3251 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
e5bef2e4 HB |
3252 | mark_label_nuses (XVECEXP (x, i, j)); |
3253 | } | |
3254 | } | |
3255 | ||
23b2ce53 RS |
3256 | \f |
3257 | /* Try splitting insns that can be split for better scheduling. | |
3258 | PAT is the pattern which might split. | |
3259 | TRIAL is the insn providing PAT. | |
cc2902df | 3260 | LAST is nonzero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
3261 | |
3262 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 3263 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
3264 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
3265 | ||
3266 | rtx | |
502b8322 | 3267 | try_split (rtx pat, rtx trial, int last) |
23b2ce53 RS |
3268 | { |
3269 | rtx before = PREV_INSN (trial); | |
3270 | rtx after = NEXT_INSN (trial); | |
23b2ce53 RS |
3271 | int has_barrier = 0; |
3272 | rtx tem; | |
6b24c259 JH |
3273 | rtx note, seq; |
3274 | int probability; | |
599aedd9 RH |
3275 | rtx insn_last, insn; |
3276 | int njumps = 0; | |
6b24c259 JH |
3277 | |
3278 | if (any_condjump_p (trial) | |
3279 | && (note = find_reg_note (trial, REG_BR_PROB, 0))) | |
3280 | split_branch_probability = INTVAL (XEXP (note, 0)); | |
3281 | probability = split_branch_probability; | |
3282 | ||
3283 | seq = split_insns (pat, trial); | |
3284 | ||
3285 | split_branch_probability = -1; | |
23b2ce53 RS |
3286 | |
3287 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
3288 | We may need to handle this specially. */ | |
3289 | if (after && GET_CODE (after) == BARRIER) | |
3290 | { | |
3291 | has_barrier = 1; | |
3292 | after = NEXT_INSN (after); | |
3293 | } | |
3294 | ||
599aedd9 RH |
3295 | if (!seq) |
3296 | return trial; | |
3297 | ||
3298 | /* Avoid infinite loop if any insn of the result matches | |
3299 | the original pattern. */ | |
3300 | insn_last = seq; | |
3301 | while (1) | |
23b2ce53 | 3302 | { |
599aedd9 RH |
3303 | if (INSN_P (insn_last) |
3304 | && rtx_equal_p (PATTERN (insn_last), pat)) | |
3305 | return trial; | |
3306 | if (!NEXT_INSN (insn_last)) | |
3307 | break; | |
3308 | insn_last = NEXT_INSN (insn_last); | |
3309 | } | |
750c9258 | 3310 | |
599aedd9 RH |
3311 | /* Mark labels. */ |
3312 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3313 | { | |
3314 | if (GET_CODE (insn) == JUMP_INSN) | |
3315 | { | |
3316 | mark_jump_label (PATTERN (insn), insn, 0); | |
3317 | njumps++; | |
3318 | if (probability != -1 | |
3319 | && any_condjump_p (insn) | |
3320 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
2f937369 | 3321 | { |
599aedd9 RH |
3322 | /* We can preserve the REG_BR_PROB notes only if exactly |
3323 | one jump is created, otherwise the machine description | |
3324 | is responsible for this step using | |
3325 | split_branch_probability variable. */ | |
3326 | if (njumps != 1) | |
3327 | abort (); | |
3328 | REG_NOTES (insn) | |
3329 | = gen_rtx_EXPR_LIST (REG_BR_PROB, | |
3330 | GEN_INT (probability), | |
3331 | REG_NOTES (insn)); | |
2f937369 | 3332 | } |
599aedd9 RH |
3333 | } |
3334 | } | |
3335 | ||
3336 | /* If we are splitting a CALL_INSN, look for the CALL_INSN | |
3337 | in SEQ and copy our CALL_INSN_FUNCTION_USAGE to it. */ | |
3338 | if (GET_CODE (trial) == CALL_INSN) | |
3339 | { | |
3340 | for (insn = insn_last; insn ; insn = PREV_INSN (insn)) | |
3341 | if (GET_CODE (insn) == CALL_INSN) | |
3342 | { | |
f6a1f3f6 RH |
3343 | rtx *p = &CALL_INSN_FUNCTION_USAGE (insn); |
3344 | while (*p) | |
3345 | p = &XEXP (*p, 1); | |
3346 | *p = CALL_INSN_FUNCTION_USAGE (trial); | |
599aedd9 RH |
3347 | SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial); |
3348 | } | |
3349 | } | |
4b5e8abe | 3350 | |
599aedd9 RH |
3351 | /* Copy notes, particularly those related to the CFG. */ |
3352 | for (note = REG_NOTES (trial); note; note = XEXP (note, 1)) | |
3353 | { | |
3354 | switch (REG_NOTE_KIND (note)) | |
3355 | { | |
3356 | case REG_EH_REGION: | |
2f937369 DM |
3357 | insn = insn_last; |
3358 | while (insn != NULL_RTX) | |
3359 | { | |
599aedd9 RH |
3360 | if (GET_CODE (insn) == CALL_INSN |
3361 | || (flag_non_call_exceptions | |
3362 | && may_trap_p (PATTERN (insn)))) | |
3363 | REG_NOTES (insn) | |
3364 | = gen_rtx_EXPR_LIST (REG_EH_REGION, | |
3365 | XEXP (note, 0), | |
3366 | REG_NOTES (insn)); | |
2f937369 DM |
3367 | insn = PREV_INSN (insn); |
3368 | } | |
599aedd9 | 3369 | break; |
216183ce | 3370 | |
599aedd9 RH |
3371 | case REG_NORETURN: |
3372 | case REG_SETJMP: | |
3373 | case REG_ALWAYS_RETURN: | |
3374 | insn = insn_last; | |
3375 | while (insn != NULL_RTX) | |
216183ce | 3376 | { |
599aedd9 RH |
3377 | if (GET_CODE (insn) == CALL_INSN) |
3378 | REG_NOTES (insn) | |
3379 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3380 | XEXP (note, 0), | |
3381 | REG_NOTES (insn)); | |
3382 | insn = PREV_INSN (insn); | |
216183ce | 3383 | } |
599aedd9 | 3384 | break; |
d6e95df8 | 3385 | |
599aedd9 RH |
3386 | case REG_NON_LOCAL_GOTO: |
3387 | insn = insn_last; | |
3388 | while (insn != NULL_RTX) | |
2f937369 | 3389 | { |
599aedd9 RH |
3390 | if (GET_CODE (insn) == JUMP_INSN) |
3391 | REG_NOTES (insn) | |
3392 | = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note), | |
3393 | XEXP (note, 0), | |
3394 | REG_NOTES (insn)); | |
3395 | insn = PREV_INSN (insn); | |
2f937369 | 3396 | } |
599aedd9 | 3397 | break; |
e5bef2e4 | 3398 | |
599aedd9 RH |
3399 | default: |
3400 | break; | |
23b2ce53 | 3401 | } |
599aedd9 RH |
3402 | } |
3403 | ||
3404 | /* If there are LABELS inside the split insns increment the | |
3405 | usage count so we don't delete the label. */ | |
3406 | if (GET_CODE (trial) == INSN) | |
3407 | { | |
3408 | insn = insn_last; | |
3409 | while (insn != NULL_RTX) | |
23b2ce53 | 3410 | { |
599aedd9 RH |
3411 | if (GET_CODE (insn) == INSN) |
3412 | mark_label_nuses (PATTERN (insn)); | |
23b2ce53 | 3413 | |
599aedd9 RH |
3414 | insn = PREV_INSN (insn); |
3415 | } | |
23b2ce53 RS |
3416 | } |
3417 | ||
0435312e | 3418 | tem = emit_insn_after_setloc (seq, trial, INSN_LOCATOR (trial)); |
599aedd9 RH |
3419 | |
3420 | delete_insn (trial); | |
3421 | if (has_barrier) | |
3422 | emit_barrier_after (tem); | |
3423 | ||
3424 | /* Recursively call try_split for each new insn created; by the | |
3425 | time control returns here that insn will be fully split, so | |
3426 | set LAST and continue from the insn after the one returned. | |
3427 | We can't use next_active_insn here since AFTER may be a note. | |
3428 | Ignore deleted insns, which can be occur if not optimizing. */ | |
3429 | for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem)) | |
3430 | if (! INSN_DELETED_P (tem) && INSN_P (tem)) | |
3431 | tem = try_split (PATTERN (tem), tem, 1); | |
3432 | ||
3433 | /* Return either the first or the last insn, depending on which was | |
3434 | requested. */ | |
3435 | return last | |
3436 | ? (after ? PREV_INSN (after) : last_insn) | |
3437 | : NEXT_INSN (before); | |
23b2ce53 RS |
3438 | } |
3439 | \f | |
3440 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 3441 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
3442 | |
3443 | rtx | |
502b8322 | 3444 | make_insn_raw (rtx pattern) |
23b2ce53 | 3445 | { |
b3694847 | 3446 | rtx insn; |
23b2ce53 | 3447 | |
1f8f4a0b | 3448 | insn = rtx_alloc (INSN); |
23b2ce53 | 3449 | |
43127294 | 3450 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3451 | PATTERN (insn) = pattern; |
3452 | INSN_CODE (insn) = -1; | |
1632afca RS |
3453 | LOG_LINKS (insn) = NULL; |
3454 | REG_NOTES (insn) = NULL; | |
0435312e | 3455 | INSN_LOCATOR (insn) = 0; |
ba4f7968 | 3456 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 | 3457 | |
47984720 NC |
3458 | #ifdef ENABLE_RTL_CHECKING |
3459 | if (insn | |
2c3c49de | 3460 | && INSN_P (insn) |
47984720 NC |
3461 | && (returnjump_p (insn) |
3462 | || (GET_CODE (insn) == SET | |
3463 | && SET_DEST (insn) == pc_rtx))) | |
3464 | { | |
3465 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
3466 | debug_rtx (insn); | |
3467 | } | |
3468 | #endif | |
750c9258 | 3469 | |
23b2ce53 RS |
3470 | return insn; |
3471 | } | |
3472 | ||
2f937369 | 3473 | /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */ |
23b2ce53 RS |
3474 | |
3475 | static rtx | |
502b8322 | 3476 | make_jump_insn_raw (rtx pattern) |
23b2ce53 | 3477 | { |
b3694847 | 3478 | rtx insn; |
23b2ce53 | 3479 | |
4b1f5e8c | 3480 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 3481 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
3482 | |
3483 | PATTERN (insn) = pattern; | |
3484 | INSN_CODE (insn) = -1; | |
1632afca RS |
3485 | LOG_LINKS (insn) = NULL; |
3486 | REG_NOTES (insn) = NULL; | |
3487 | JUMP_LABEL (insn) = NULL; | |
0435312e | 3488 | INSN_LOCATOR (insn) = 0; |
ba4f7968 | 3489 | BLOCK_FOR_INSN (insn) = NULL; |
23b2ce53 RS |
3490 | |
3491 | return insn; | |
3492 | } | |
aff507f4 | 3493 | |
2f937369 | 3494 | /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */ |
aff507f4 RK |
3495 | |
3496 | static rtx | |
502b8322 | 3497 | make_call_insn_raw (rtx pattern) |
aff507f4 | 3498 | { |
b3694847 | 3499 | rtx insn; |
aff507f4 RK |
3500 | |
3501 | insn = rtx_alloc (CALL_INSN); | |
3502 | INSN_UID (insn) = cur_insn_uid++; | |
3503 | ||
3504 | PATTERN (insn) = pattern; | |
3505 | INSN_CODE (insn) = -1; | |
3506 | LOG_LINKS (insn) = NULL; | |
3507 | REG_NOTES (insn) = NULL; | |
3508 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
0435312e | 3509 | INSN_LOCATOR (insn) = 0; |
ba4f7968 | 3510 | BLOCK_FOR_INSN (insn) = NULL; |
aff507f4 RK |
3511 | |
3512 | return insn; | |
3513 | } | |
23b2ce53 RS |
3514 | \f |
3515 | /* Add INSN to the end of the doubly-linked list. | |
3516 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
3517 | ||
3518 | void | |
502b8322 | 3519 | add_insn (rtx insn) |
23b2ce53 RS |
3520 | { |
3521 | PREV_INSN (insn) = last_insn; | |
3522 | NEXT_INSN (insn) = 0; | |
3523 | ||
3524 | if (NULL != last_insn) | |
3525 | NEXT_INSN (last_insn) = insn; | |
3526 | ||
3527 | if (NULL == first_insn) | |
3528 | first_insn = insn; | |
3529 | ||
3530 | last_insn = insn; | |
3531 | } | |
3532 | ||
a0ae8e8d RK |
3533 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
3534 | the next should be the only functions called to insert an insn once | |
ba213285 | 3535 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 3536 | SEQUENCE. */ |
23b2ce53 RS |
3537 | |
3538 | void | |
502b8322 | 3539 | add_insn_after (rtx insn, rtx after) |
23b2ce53 RS |
3540 | { |
3541 | rtx next = NEXT_INSN (after); | |
3c030e88 | 3542 | basic_block bb; |
23b2ce53 | 3543 | |
6782074d | 3544 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
3545 | abort (); |
3546 | ||
23b2ce53 RS |
3547 | NEXT_INSN (insn) = next; |
3548 | PREV_INSN (insn) = after; | |
3549 | ||
3550 | if (next) | |
3551 | { | |
3552 | PREV_INSN (next) = insn; | |
3553 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
3554 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
3555 | } | |
3556 | else if (last_insn == after) | |
3557 | last_insn = insn; | |
3558 | else | |
3559 | { | |
49ad7cfa | 3560 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
3561 | /* Scan all pending sequences too. */ |
3562 | for (; stack; stack = stack->next) | |
3563 | if (after == stack->last) | |
fef0509b RK |
3564 | { |
3565 | stack->last = insn; | |
3566 | break; | |
3567 | } | |
a0ae8e8d RK |
3568 | |
3569 | if (stack == 0) | |
3570 | abort (); | |
23b2ce53 RS |
3571 | } |
3572 | ||
ba4f7968 JH |
3573 | if (GET_CODE (after) != BARRIER |
3574 | && GET_CODE (insn) != BARRIER | |
3c030e88 JH |
3575 | && (bb = BLOCK_FOR_INSN (after))) |
3576 | { | |
3577 | set_block_for_insn (insn, bb); | |
38c1593d | 3578 | if (INSN_P (insn)) |
68252e27 | 3579 | bb->flags |= BB_DIRTY; |
3c030e88 | 3580 | /* Should not happen as first in the BB is always |
a1f300c0 | 3581 | either NOTE or LABEL. */ |
3c030e88 JH |
3582 | if (bb->end == after |
3583 | /* Avoid clobbering of structure when creating new BB. */ | |
3584 | && GET_CODE (insn) != BARRIER | |
3585 | && (GET_CODE (insn) != NOTE | |
3586 | || NOTE_LINE_NUMBER (insn) != NOTE_INSN_BASIC_BLOCK)) | |
3587 | bb->end = insn; | |
3588 | } | |
3589 | ||
23b2ce53 RS |
3590 | NEXT_INSN (after) = insn; |
3591 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
3592 | { | |
3593 | rtx sequence = PATTERN (after); | |
3594 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3595 | } | |
3596 | } | |
3597 | ||
a0ae8e8d RK |
3598 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
3599 | the previous should be the only functions called to insert an insn once | |
ba213285 | 3600 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
3601 | SEQUENCE. */ |
3602 | ||
3603 | void | |
502b8322 | 3604 | add_insn_before (rtx insn, rtx before) |
a0ae8e8d RK |
3605 | { |
3606 | rtx prev = PREV_INSN (before); | |
3c030e88 | 3607 | basic_block bb; |
a0ae8e8d | 3608 | |
6782074d | 3609 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
3610 | abort (); |
3611 | ||
a0ae8e8d RK |
3612 | PREV_INSN (insn) = prev; |
3613 | NEXT_INSN (insn) = before; | |
3614 | ||
3615 | if (prev) | |
3616 | { | |
3617 | NEXT_INSN (prev) = insn; | |
3618 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
3619 | { | |
3620 | rtx sequence = PATTERN (prev); | |
3621 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
3622 | } | |
3623 | } | |
3624 | else if (first_insn == before) | |
3625 | first_insn = insn; | |
3626 | else | |
3627 | { | |
49ad7cfa | 3628 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
3629 | /* Scan all pending sequences too. */ |
3630 | for (; stack; stack = stack->next) | |
3631 | if (before == stack->first) | |
fef0509b RK |
3632 | { |
3633 | stack->first = insn; | |
3634 | break; | |
3635 | } | |
a0ae8e8d RK |
3636 | |
3637 | if (stack == 0) | |
3638 | abort (); | |
3639 | } | |
3640 | ||
ba4f7968 JH |
3641 | if (GET_CODE (before) != BARRIER |
3642 | && GET_CODE (insn) != BARRIER | |
3c030e88 JH |
3643 | && (bb = BLOCK_FOR_INSN (before))) |
3644 | { | |
3645 | set_block_for_insn (insn, bb); | |
38c1593d | 3646 | if (INSN_P (insn)) |
68252e27 | 3647 | bb->flags |= BB_DIRTY; |
3c030e88 | 3648 | /* Should not happen as first in the BB is always |
a1f300c0 | 3649 | either NOTE or LABEl. */ |
3c030e88 JH |
3650 | if (bb->head == insn |
3651 | /* Avoid clobbering of structure when creating new BB. */ | |
3652 | && GET_CODE (insn) != BARRIER | |
3653 | && (GET_CODE (insn) != NOTE | |
3654 | || NOTE_LINE_NUMBER (insn) != NOTE_INSN_BASIC_BLOCK)) | |
3655 | abort (); | |
3656 | } | |
3657 | ||
a0ae8e8d RK |
3658 | PREV_INSN (before) = insn; |
3659 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
3660 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
3661 | } | |
3662 | ||
89e99eea DB |
3663 | /* Remove an insn from its doubly-linked list. This function knows how |
3664 | to handle sequences. */ | |
3665 | void | |
502b8322 | 3666 | remove_insn (rtx insn) |
89e99eea DB |
3667 | { |
3668 | rtx next = NEXT_INSN (insn); | |
3669 | rtx prev = PREV_INSN (insn); | |
53c17031 JH |
3670 | basic_block bb; |
3671 | ||
89e99eea DB |
3672 | if (prev) |
3673 | { | |
3674 | NEXT_INSN (prev) = next; | |
3675 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
3676 | { | |
3677 | rtx sequence = PATTERN (prev); | |
3678 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
3679 | } | |
3680 | } | |
3681 | else if (first_insn == insn) | |
3682 | first_insn = next; | |
3683 | else | |
3684 | { | |
49ad7cfa | 3685 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3686 | /* Scan all pending sequences too. */ |
3687 | for (; stack; stack = stack->next) | |
3688 | if (insn == stack->first) | |
3689 | { | |
3690 | stack->first = next; | |
3691 | break; | |
3692 | } | |
3693 | ||
3694 | if (stack == 0) | |
3695 | abort (); | |
3696 | } | |
3697 | ||
3698 | if (next) | |
3699 | { | |
3700 | PREV_INSN (next) = prev; | |
3701 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
3702 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
3703 | } | |
3704 | else if (last_insn == insn) | |
3705 | last_insn = prev; | |
3706 | else | |
3707 | { | |
49ad7cfa | 3708 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
3709 | /* Scan all pending sequences too. */ |
3710 | for (; stack; stack = stack->next) | |
3711 | if (insn == stack->last) | |
3712 | { | |
3713 | stack->last = prev; | |
3714 | break; | |
3715 | } | |
3716 | ||
3717 | if (stack == 0) | |
3718 | abort (); | |
3719 | } | |
ba4f7968 | 3720 | if (GET_CODE (insn) != BARRIER |
53c17031 JH |
3721 | && (bb = BLOCK_FOR_INSN (insn))) |
3722 | { | |
38c1593d | 3723 | if (INSN_P (insn)) |
68252e27 | 3724 | bb->flags |= BB_DIRTY; |
53c17031 JH |
3725 | if (bb->head == insn) |
3726 | { | |
3bf1e984 RK |
3727 | /* Never ever delete the basic block note without deleting whole |
3728 | basic block. */ | |
53c17031 JH |
3729 | if (GET_CODE (insn) == NOTE) |
3730 | abort (); | |
3731 | bb->head = next; | |
3732 | } | |
3733 | if (bb->end == insn) | |
3734 | bb->end = prev; | |
3735 | } | |
89e99eea DB |
3736 | } |
3737 | ||
ee960939 OH |
3738 | /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */ |
3739 | ||
3740 | void | |
502b8322 | 3741 | add_function_usage_to (rtx call_insn, rtx call_fusage) |
ee960939 OH |
3742 | { |
3743 | if (! call_insn || GET_CODE (call_insn) != CALL_INSN) | |
3744 | abort (); | |
3745 | ||
3746 | /* Put the register usage information on the CALL. If there is already | |
3747 | some usage information, put ours at the end. */ | |
3748 | if (CALL_INSN_FUNCTION_USAGE (call_insn)) | |
3749 | { | |
3750 | rtx link; | |
3751 | ||
3752 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0; | |
3753 | link = XEXP (link, 1)) | |
3754 | ; | |
3755 | ||
3756 | XEXP (link, 1) = call_fusage; | |
3757 | } | |
3758 | else | |
3759 | CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage; | |
3760 | } | |
3761 | ||
23b2ce53 RS |
3762 | /* Delete all insns made since FROM. |
3763 | FROM becomes the new last instruction. */ | |
3764 | ||
3765 | void | |
502b8322 | 3766 | delete_insns_since (rtx from) |
23b2ce53 RS |
3767 | { |
3768 | if (from == 0) | |
3769 | first_insn = 0; | |
3770 | else | |
3771 | NEXT_INSN (from) = 0; | |
3772 | last_insn = from; | |
3773 | } | |
3774 | ||
5dab5552 MS |
3775 | /* This function is deprecated, please use sequences instead. |
3776 | ||
3777 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
3778 | The insns to be moved are those between FROM and TO. |
3779 | They are moved to a new position after the insn AFTER. | |
3780 | AFTER must not be FROM or TO or any insn in between. | |
3781 | ||
3782 | This function does not know about SEQUENCEs and hence should not be | |
3783 | called after delay-slot filling has been done. */ | |
3784 | ||
3785 | void | |
502b8322 | 3786 | reorder_insns_nobb (rtx from, rtx to, rtx after) |
23b2ce53 RS |
3787 | { |
3788 | /* Splice this bunch out of where it is now. */ | |
3789 | if (PREV_INSN (from)) | |
3790 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
3791 | if (NEXT_INSN (to)) | |
3792 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
3793 | if (last_insn == to) | |
3794 | last_insn = PREV_INSN (from); | |
3795 | if (first_insn == from) | |
3796 | first_insn = NEXT_INSN (to); | |
3797 | ||
3798 | /* Make the new neighbors point to it and it to them. */ | |
3799 | if (NEXT_INSN (after)) | |
3800 | PREV_INSN (NEXT_INSN (after)) = to; | |
3801 | ||
3802 | NEXT_INSN (to) = NEXT_INSN (after); | |
3803 | PREV_INSN (from) = after; | |
3804 | NEXT_INSN (after) = from; | |
3805 | if (after == last_insn) | |
3806 | last_insn = to; | |
3807 | } | |
3808 | ||
3c030e88 JH |
3809 | /* Same as function above, but take care to update BB boundaries. */ |
3810 | void | |
502b8322 | 3811 | reorder_insns (rtx from, rtx to, rtx after) |
3c030e88 JH |
3812 | { |
3813 | rtx prev = PREV_INSN (from); | |
3814 | basic_block bb, bb2; | |
3815 | ||
3816 | reorder_insns_nobb (from, to, after); | |
3817 | ||
ba4f7968 | 3818 | if (GET_CODE (after) != BARRIER |
3c030e88 JH |
3819 | && (bb = BLOCK_FOR_INSN (after))) |
3820 | { | |
3821 | rtx x; | |
38c1593d | 3822 | bb->flags |= BB_DIRTY; |
68252e27 | 3823 | |
ba4f7968 | 3824 | if (GET_CODE (from) != BARRIER |
3c030e88 JH |
3825 | && (bb2 = BLOCK_FOR_INSN (from))) |
3826 | { | |
3827 | if (bb2->end == to) | |
3828 | bb2->end = prev; | |
38c1593d | 3829 | bb2->flags |= BB_DIRTY; |
3c030e88 JH |
3830 | } |
3831 | ||
3832 | if (bb->end == after) | |
3833 | bb->end = to; | |
3834 | ||
3835 | for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x)) | |
3836 | set_block_for_insn (x, bb); | |
3837 | } | |
3838 | } | |
3839 | ||
23b2ce53 RS |
3840 | /* Return the line note insn preceding INSN. */ |
3841 | ||
3842 | static rtx | |
502b8322 | 3843 | find_line_note (rtx insn) |
23b2ce53 RS |
3844 | { |
3845 | if (no_line_numbers) | |
3846 | return 0; | |
3847 | ||
3848 | for (; insn; insn = PREV_INSN (insn)) | |
3849 | if (GET_CODE (insn) == NOTE | |
0fb7aeda | 3850 | && NOTE_LINE_NUMBER (insn) >= 0) |
23b2ce53 RS |
3851 | break; |
3852 | ||
3853 | return insn; | |
3854 | } | |
3855 | ||
3856 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
3857 | of the moved insns when debugging. This may insert a note between AFTER | |
3858 | and FROM, and another one after TO. */ | |
3859 | ||
3860 | void | |
502b8322 | 3861 | reorder_insns_with_line_notes (rtx from, rtx to, rtx after) |
23b2ce53 RS |
3862 | { |
3863 | rtx from_line = find_line_note (from); | |
3864 | rtx after_line = find_line_note (after); | |
3865 | ||
3866 | reorder_insns (from, to, after); | |
3867 | ||
3868 | if (from_line == after_line) | |
3869 | return; | |
3870 | ||
3871 | if (from_line) | |
5f2fc772 | 3872 | emit_note_copy_after (from_line, after); |
23b2ce53 | 3873 | if (after_line) |
5f2fc772 | 3874 | emit_note_copy_after (after_line, to); |
23b2ce53 | 3875 | } |
aeeeda03 | 3876 | |
64b59a80 | 3877 | /* Remove unnecessary notes from the instruction stream. */ |
aeeeda03 MM |
3878 | |
3879 | void | |
502b8322 | 3880 | remove_unnecessary_notes (void) |
aeeeda03 | 3881 | { |
542d73ae RH |
3882 | rtx block_stack = NULL_RTX; |
3883 | rtx eh_stack = NULL_RTX; | |
aeeeda03 MM |
3884 | rtx insn; |
3885 | rtx next; | |
542d73ae | 3886 | rtx tmp; |
aeeeda03 | 3887 | |
116eebd6 MM |
3888 | /* We must not remove the first instruction in the function because |
3889 | the compiler depends on the first instruction being a note. */ | |
aeeeda03 MM |
3890 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
3891 | { | |
3892 | /* Remember what's next. */ | |
3893 | next = NEXT_INSN (insn); | |
3894 | ||
3895 | /* We're only interested in notes. */ | |
3896 | if (GET_CODE (insn) != NOTE) | |
3897 | continue; | |
3898 | ||
542d73ae | 3899 | switch (NOTE_LINE_NUMBER (insn)) |
18c038b9 | 3900 | { |
542d73ae | 3901 | case NOTE_INSN_DELETED: |
e803a64b | 3902 | case NOTE_INSN_LOOP_END_TOP_COND: |
542d73ae RH |
3903 | remove_insn (insn); |
3904 | break; | |
3905 | ||
3906 | case NOTE_INSN_EH_REGION_BEG: | |
3907 | eh_stack = alloc_INSN_LIST (insn, eh_stack); | |
3908 | break; | |
3909 | ||
3910 | case NOTE_INSN_EH_REGION_END: | |
3911 | /* Too many end notes. */ | |
3912 | if (eh_stack == NULL_RTX) | |
3913 | abort (); | |
3914 | /* Mismatched nesting. */ | |
3915 | if (NOTE_EH_HANDLER (XEXP (eh_stack, 0)) != NOTE_EH_HANDLER (insn)) | |
3916 | abort (); | |
3917 | tmp = eh_stack; | |
3918 | eh_stack = XEXP (eh_stack, 1); | |
3919 | free_INSN_LIST_node (tmp); | |
3920 | break; | |
3921 | ||
3922 | case NOTE_INSN_BLOCK_BEG: | |
3923 | /* By now, all notes indicating lexical blocks should have | |
3924 | NOTE_BLOCK filled in. */ | |
3925 | if (NOTE_BLOCK (insn) == NULL_TREE) | |
3926 | abort (); | |
3927 | block_stack = alloc_INSN_LIST (insn, block_stack); | |
3928 | break; | |
3929 | ||
3930 | case NOTE_INSN_BLOCK_END: | |
3931 | /* Too many end notes. */ | |
3932 | if (block_stack == NULL_RTX) | |
3933 | abort (); | |
3934 | /* Mismatched nesting. */ | |
3935 | if (NOTE_BLOCK (XEXP (block_stack, 0)) != NOTE_BLOCK (insn)) | |
3936 | abort (); | |
3937 | tmp = block_stack; | |
3938 | block_stack = XEXP (block_stack, 1); | |
3939 | free_INSN_LIST_node (tmp); | |
3940 | ||
18c038b9 MM |
3941 | /* Scan back to see if there are any non-note instructions |
3942 | between INSN and the beginning of this block. If not, | |
3943 | then there is no PC range in the generated code that will | |
3944 | actually be in this block, so there's no point in | |
3945 | remembering the existence of the block. */ | |
68252e27 | 3946 | for (tmp = PREV_INSN (insn); tmp; tmp = PREV_INSN (tmp)) |
18c038b9 MM |
3947 | { |
3948 | /* This block contains a real instruction. Note that we | |
3949 | don't include labels; if the only thing in the block | |
3950 | is a label, then there are still no PC values that | |
3951 | lie within the block. */ | |
542d73ae | 3952 | if (INSN_P (tmp)) |
18c038b9 MM |
3953 | break; |
3954 | ||
3955 | /* We're only interested in NOTEs. */ | |
542d73ae | 3956 | if (GET_CODE (tmp) != NOTE) |
18c038b9 MM |
3957 | continue; |
3958 | ||
542d73ae | 3959 | if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_BEG) |
18c038b9 | 3960 | { |
e1772ac0 NB |
3961 | /* We just verified that this BLOCK matches us with |
3962 | the block_stack check above. Never delete the | |
3963 | BLOCK for the outermost scope of the function; we | |
3964 | can refer to names from that scope even if the | |
3965 | block notes are messed up. */ | |
3966 | if (! is_body_block (NOTE_BLOCK (insn)) | |
3967 | && (*debug_hooks->ignore_block) (NOTE_BLOCK (insn))) | |
deb5e280 | 3968 | { |
542d73ae | 3969 | remove_insn (tmp); |
deb5e280 JM |
3970 | remove_insn (insn); |
3971 | } | |
18c038b9 MM |
3972 | break; |
3973 | } | |
542d73ae | 3974 | else if (NOTE_LINE_NUMBER (tmp) == NOTE_INSN_BLOCK_END) |
18c038b9 MM |
3975 | /* There's a nested block. We need to leave the |
3976 | current block in place since otherwise the debugger | |
3977 | wouldn't be able to show symbols from our block in | |
3978 | the nested block. */ | |
3979 | break; | |
3980 | } | |
3981 | } | |
aeeeda03 | 3982 | } |
542d73ae RH |
3983 | |
3984 | /* Too many begin notes. */ | |
3985 | if (block_stack || eh_stack) | |
3986 | abort (); | |
aeeeda03 MM |
3987 | } |
3988 | ||
23b2ce53 | 3989 | \f |
2f937369 DM |
3990 | /* Emit insn(s) of given code and pattern |
3991 | at a specified place within the doubly-linked list. | |
23b2ce53 | 3992 | |
2f937369 DM |
3993 | All of the emit_foo global entry points accept an object |
3994 | X which is either an insn list or a PATTERN of a single | |
3995 | instruction. | |
23b2ce53 | 3996 | |
2f937369 DM |
3997 | There are thus a few canonical ways to generate code and |
3998 | emit it at a specific place in the instruction stream. For | |
3999 | example, consider the instruction named SPOT and the fact that | |
4000 | we would like to emit some instructions before SPOT. We might | |
4001 | do it like this: | |
23b2ce53 | 4002 | |
2f937369 DM |
4003 | start_sequence (); |
4004 | ... emit the new instructions ... | |
4005 | insns_head = get_insns (); | |
4006 | end_sequence (); | |
23b2ce53 | 4007 | |
2f937369 | 4008 | emit_insn_before (insns_head, SPOT); |
23b2ce53 | 4009 | |
2f937369 DM |
4010 | It used to be common to generate SEQUENCE rtl instead, but that |
4011 | is a relic of the past which no longer occurs. The reason is that | |
4012 | SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE | |
4013 | generated would almost certainly die right after it was created. */ | |
23b2ce53 | 4014 | |
2f937369 | 4015 | /* Make X be output before the instruction BEFORE. */ |
23b2ce53 RS |
4016 | |
4017 | rtx | |
502b8322 | 4018 | emit_insn_before (rtx x, rtx before) |
23b2ce53 | 4019 | { |
2f937369 | 4020 | rtx last = before; |
b3694847 | 4021 | rtx insn; |
23b2ce53 | 4022 | |
2f937369 DM |
4023 | #ifdef ENABLE_RTL_CHECKING |
4024 | if (before == NULL_RTX) | |
4025 | abort (); | |
4026 | #endif | |
4027 | ||
4028 | if (x == NULL_RTX) | |
4029 | return last; | |
4030 | ||
4031 | switch (GET_CODE (x)) | |
23b2ce53 | 4032 | { |
2f937369 DM |
4033 | case INSN: |
4034 | case JUMP_INSN: | |
4035 | case CALL_INSN: | |
4036 | case CODE_LABEL: | |
4037 | case BARRIER: | |
4038 | case NOTE: | |
4039 | insn = x; | |
4040 | while (insn) | |
4041 | { | |
4042 | rtx next = NEXT_INSN (insn); | |
4043 | add_insn_before (insn, before); | |
4044 | last = insn; | |
4045 | insn = next; | |
4046 | } | |
4047 | break; | |
4048 | ||
4049 | #ifdef ENABLE_RTL_CHECKING | |
4050 | case SEQUENCE: | |
4051 | abort (); | |
4052 | break; | |
4053 | #endif | |
4054 | ||
4055 | default: | |
4056 | last = make_insn_raw (x); | |
4057 | add_insn_before (last, before); | |
4058 | break; | |
23b2ce53 RS |
4059 | } |
4060 | ||
2f937369 | 4061 | return last; |
23b2ce53 RS |
4062 | } |
4063 | ||
2f937369 | 4064 | /* Make an instruction with body X and code JUMP_INSN |
23b2ce53 RS |
4065 | and output it before the instruction BEFORE. */ |
4066 | ||
4067 | rtx | |
502b8322 | 4068 | emit_jump_insn_before (rtx x, rtx before) |
23b2ce53 | 4069 | { |
d950dee3 | 4070 | rtx insn, last = NULL_RTX; |
aff507f4 | 4071 | |
2f937369 DM |
4072 | #ifdef ENABLE_RTL_CHECKING |
4073 | if (before == NULL_RTX) | |
4074 | abort (); | |
4075 | #endif | |
4076 | ||
4077 | switch (GET_CODE (x)) | |
aff507f4 | 4078 | { |
2f937369 DM |
4079 | case INSN: |
4080 | case JUMP_INSN: | |
4081 | case CALL_INSN: | |
4082 | case CODE_LABEL: | |
4083 | case BARRIER: | |
4084 | case NOTE: | |
4085 | insn = x; | |
4086 | while (insn) | |
4087 | { | |
4088 | rtx next = NEXT_INSN (insn); | |
4089 | add_insn_before (insn, before); | |
4090 | last = insn; | |
4091 | insn = next; | |
4092 | } | |
4093 | break; | |
4094 | ||
4095 | #ifdef ENABLE_RTL_CHECKING | |
4096 | case SEQUENCE: | |
4097 | abort (); | |
4098 | break; | |
4099 | #endif | |
4100 | ||
4101 | default: | |
4102 | last = make_jump_insn_raw (x); | |
4103 | add_insn_before (last, before); | |
4104 | break; | |
aff507f4 RK |
4105 | } |
4106 | ||
2f937369 | 4107 | return last; |
23b2ce53 RS |
4108 | } |
4109 | ||
2f937369 | 4110 | /* Make an instruction with body X and code CALL_INSN |
969d70ca JH |
4111 | and output it before the instruction BEFORE. */ |
4112 | ||
4113 | rtx | |
502b8322 | 4114 | emit_call_insn_before (rtx x, rtx before) |
969d70ca | 4115 | { |
d950dee3 | 4116 | rtx last = NULL_RTX, insn; |
969d70ca | 4117 | |
2f937369 DM |
4118 | #ifdef ENABLE_RTL_CHECKING |
4119 | if (before == NULL_RTX) | |
4120 | abort (); | |
4121 | #endif | |
4122 | ||
4123 | switch (GET_CODE (x)) | |
969d70ca | 4124 | { |
2f937369 DM |
4125 | case INSN: |
4126 | case JUMP_INSN: | |
4127 | case CALL_INSN: | |
4128 | case CODE_LABEL: | |
4129 | case BARRIER: | |
4130 | case NOTE: | |
4131 | insn = x; | |
4132 | while (insn) | |
4133 | { | |
4134 | rtx next = NEXT_INSN (insn); | |
4135 | add_insn_before (insn, before); | |
4136 | last = insn; | |
4137 | insn = next; | |
4138 | } | |
4139 | break; | |
4140 | ||
4141 | #ifdef ENABLE_RTL_CHECKING | |
4142 | case SEQUENCE: | |
4143 | abort (); | |
4144 | break; | |
4145 | #endif | |
4146 | ||
4147 | default: | |
4148 | last = make_call_insn_raw (x); | |
4149 | add_insn_before (last, before); | |
4150 | break; | |
969d70ca JH |
4151 | } |
4152 | ||
2f937369 | 4153 | return last; |
969d70ca JH |
4154 | } |
4155 | ||
23b2ce53 | 4156 | /* Make an insn of code BARRIER |
e881bb1b | 4157 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
4158 | |
4159 | rtx | |
502b8322 | 4160 | emit_barrier_before (rtx before) |
23b2ce53 | 4161 | { |
b3694847 | 4162 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4163 | |
4164 | INSN_UID (insn) = cur_insn_uid++; | |
4165 | ||
a0ae8e8d | 4166 | add_insn_before (insn, before); |
23b2ce53 RS |
4167 | return insn; |
4168 | } | |
4169 | ||
e881bb1b RH |
4170 | /* Emit the label LABEL before the insn BEFORE. */ |
4171 | ||
4172 | rtx | |
502b8322 | 4173 | emit_label_before (rtx label, rtx before) |
e881bb1b RH |
4174 | { |
4175 | /* This can be called twice for the same label as a result of the | |
4176 | confusion that follows a syntax error! So make it harmless. */ | |
4177 | if (INSN_UID (label) == 0) | |
4178 | { | |
4179 | INSN_UID (label) = cur_insn_uid++; | |
4180 | add_insn_before (label, before); | |
4181 | } | |
4182 | ||
4183 | return label; | |
4184 | } | |
4185 | ||
23b2ce53 RS |
4186 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
4187 | ||
4188 | rtx | |
502b8322 | 4189 | emit_note_before (int subtype, rtx before) |
23b2ce53 | 4190 | { |
b3694847 | 4191 | rtx note = rtx_alloc (NOTE); |
23b2ce53 RS |
4192 | INSN_UID (note) = cur_insn_uid++; |
4193 | NOTE_SOURCE_FILE (note) = 0; | |
4194 | NOTE_LINE_NUMBER (note) = subtype; | |
ba4f7968 | 4195 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 | 4196 | |
a0ae8e8d | 4197 | add_insn_before (note, before); |
23b2ce53 RS |
4198 | return note; |
4199 | } | |
4200 | \f | |
2f937369 DM |
4201 | /* Helper for emit_insn_after, handles lists of instructions |
4202 | efficiently. */ | |
23b2ce53 | 4203 | |
502b8322 | 4204 | static rtx emit_insn_after_1 (rtx, rtx); |
2f937369 DM |
4205 | |
4206 | static rtx | |
502b8322 | 4207 | emit_insn_after_1 (rtx first, rtx after) |
23b2ce53 | 4208 | { |
2f937369 DM |
4209 | rtx last; |
4210 | rtx after_after; | |
4211 | basic_block bb; | |
23b2ce53 | 4212 | |
2f937369 DM |
4213 | if (GET_CODE (after) != BARRIER |
4214 | && (bb = BLOCK_FOR_INSN (after))) | |
23b2ce53 | 4215 | { |
2f937369 DM |
4216 | bb->flags |= BB_DIRTY; |
4217 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
4218 | if (GET_CODE (last) != BARRIER) | |
4219 | set_block_for_insn (last, bb); | |
4220 | if (GET_CODE (last) != BARRIER) | |
4221 | set_block_for_insn (last, bb); | |
4222 | if (bb->end == after) | |
4223 | bb->end = last; | |
23b2ce53 RS |
4224 | } |
4225 | else | |
2f937369 DM |
4226 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) |
4227 | continue; | |
4228 | ||
4229 | after_after = NEXT_INSN (after); | |
4230 | ||
4231 | NEXT_INSN (after) = first; | |
4232 | PREV_INSN (first) = after; | |
4233 | NEXT_INSN (last) = after_after; | |
4234 | if (after_after) | |
4235 | PREV_INSN (after_after) = last; | |
4236 | ||
4237 | if (after == last_insn) | |
4238 | last_insn = last; | |
4239 | return last; | |
4240 | } | |
4241 | ||
4242 | /* Make X be output after the insn AFTER. */ | |
4243 | ||
4244 | rtx | |
502b8322 | 4245 | emit_insn_after (rtx x, rtx after) |
2f937369 DM |
4246 | { |
4247 | rtx last = after; | |
4248 | ||
4249 | #ifdef ENABLE_RTL_CHECKING | |
4250 | if (after == NULL_RTX) | |
4251 | abort (); | |
4252 | #endif | |
4253 | ||
4254 | if (x == NULL_RTX) | |
4255 | return last; | |
4256 | ||
4257 | switch (GET_CODE (x)) | |
23b2ce53 | 4258 | { |
2f937369 DM |
4259 | case INSN: |
4260 | case JUMP_INSN: | |
4261 | case CALL_INSN: | |
4262 | case CODE_LABEL: | |
4263 | case BARRIER: | |
4264 | case NOTE: | |
4265 | last = emit_insn_after_1 (x, after); | |
4266 | break; | |
4267 | ||
4268 | #ifdef ENABLE_RTL_CHECKING | |
4269 | case SEQUENCE: | |
4270 | abort (); | |
4271 | break; | |
4272 | #endif | |
4273 | ||
4274 | default: | |
4275 | last = make_insn_raw (x); | |
4276 | add_insn_after (last, after); | |
4277 | break; | |
23b2ce53 RS |
4278 | } |
4279 | ||
2f937369 | 4280 | return last; |
23b2ce53 RS |
4281 | } |
4282 | ||
255680cf RK |
4283 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
4284 | as to act as if this insn were at FROM. */ | |
4285 | ||
4286 | void | |
502b8322 | 4287 | emit_insn_after_with_line_notes (rtx x, rtx after, rtx from) |
255680cf RK |
4288 | { |
4289 | rtx from_line = find_line_note (from); | |
4290 | rtx after_line = find_line_note (after); | |
2f937369 | 4291 | rtx insn = emit_insn_after (x, after); |
255680cf RK |
4292 | |
4293 | if (from_line) | |
5f2fc772 | 4294 | emit_note_copy_after (from_line, after); |
255680cf RK |
4295 | |
4296 | if (after_line) | |
5f2fc772 | 4297 | emit_note_copy_after (after_line, insn); |
255680cf RK |
4298 | } |
4299 | ||
2f937369 | 4300 | /* Make an insn of code JUMP_INSN with body X |
23b2ce53 RS |
4301 | and output it after the insn AFTER. */ |
4302 | ||
4303 | rtx | |
502b8322 | 4304 | emit_jump_insn_after (rtx x, rtx after) |
23b2ce53 | 4305 | { |
2f937369 | 4306 | rtx last; |
23b2ce53 | 4307 | |
2f937369 DM |
4308 | #ifdef ENABLE_RTL_CHECKING |
4309 | if (after == NULL_RTX) | |
4310 | abort (); | |
4311 | #endif | |
4312 | ||
4313 | switch (GET_CODE (x)) | |
23b2ce53 | 4314 | { |
2f937369 DM |
4315 | case INSN: |
4316 | case JUMP_INSN: | |
4317 | case CALL_INSN: | |
4318 | case CODE_LABEL: | |
4319 | case BARRIER: | |
4320 | case NOTE: | |
4321 | last = emit_insn_after_1 (x, after); | |
4322 | break; | |
4323 | ||
4324 | #ifdef ENABLE_RTL_CHECKING | |
4325 | case SEQUENCE: | |
4326 | abort (); | |
4327 | break; | |
4328 | #endif | |
4329 | ||
4330 | default: | |
4331 | last = make_jump_insn_raw (x); | |
4332 | add_insn_after (last, after); | |
4333 | break; | |
23b2ce53 RS |
4334 | } |
4335 | ||
2f937369 DM |
4336 | return last; |
4337 | } | |
4338 | ||
4339 | /* Make an instruction with body X and code CALL_INSN | |
4340 | and output it after the instruction AFTER. */ | |
4341 | ||
4342 | rtx | |
502b8322 | 4343 | emit_call_insn_after (rtx x, rtx after) |
2f937369 DM |
4344 | { |
4345 | rtx last; | |
4346 | ||
4347 | #ifdef ENABLE_RTL_CHECKING | |
4348 | if (after == NULL_RTX) | |
4349 | abort (); | |
4350 | #endif | |
4351 | ||
4352 | switch (GET_CODE (x)) | |
4353 | { | |
4354 | case INSN: | |
4355 | case JUMP_INSN: | |
4356 | case CALL_INSN: | |
4357 | case CODE_LABEL: | |
4358 | case BARRIER: | |
4359 | case NOTE: | |
4360 | last = emit_insn_after_1 (x, after); | |
4361 | break; | |
4362 | ||
4363 | #ifdef ENABLE_RTL_CHECKING | |
4364 | case SEQUENCE: | |
4365 | abort (); | |
4366 | break; | |
4367 | #endif | |
4368 | ||
4369 | default: | |
4370 | last = make_call_insn_raw (x); | |
4371 | add_insn_after (last, after); | |
4372 | break; | |
4373 | } | |
4374 | ||
4375 | return last; | |
23b2ce53 RS |
4376 | } |
4377 | ||
4378 | /* Make an insn of code BARRIER | |
4379 | and output it after the insn AFTER. */ | |
4380 | ||
4381 | rtx | |
502b8322 | 4382 | emit_barrier_after (rtx after) |
23b2ce53 | 4383 | { |
b3694847 | 4384 | rtx insn = rtx_alloc (BARRIER); |
23b2ce53 RS |
4385 | |
4386 | INSN_UID (insn) = cur_insn_uid++; | |
4387 | ||
4388 | add_insn_after (insn, after); | |
4389 | return insn; | |
4390 | } | |
4391 | ||
4392 | /* Emit the label LABEL after the insn AFTER. */ | |
4393 | ||
4394 | rtx | |
502b8322 | 4395 | emit_label_after (rtx label, rtx after) |
23b2ce53 RS |
4396 | { |
4397 | /* This can be called twice for the same label | |
4398 | as a result of the confusion that follows a syntax error! | |
4399 | So make it harmless. */ | |
4400 | if (INSN_UID (label) == 0) | |
4401 | { | |
4402 | INSN_UID (label) = cur_insn_uid++; | |
4403 | add_insn_after (label, after); | |
4404 | } | |
4405 | ||
4406 | return label; | |
4407 | } | |
4408 | ||
4409 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
4410 | ||
4411 | rtx | |
502b8322 | 4412 | emit_note_after (int subtype, rtx after) |
23b2ce53 | 4413 | { |
b3694847 | 4414 | rtx note = rtx_alloc (NOTE); |
23b2ce53 RS |
4415 | INSN_UID (note) = cur_insn_uid++; |
4416 | NOTE_SOURCE_FILE (note) = 0; | |
4417 | NOTE_LINE_NUMBER (note) = subtype; | |
ba4f7968 | 4418 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
4419 | add_insn_after (note, after); |
4420 | return note; | |
4421 | } | |
4422 | ||
5f2fc772 | 4423 | /* Emit a copy of note ORIG after the insn AFTER. */ |
23b2ce53 RS |
4424 | |
4425 | rtx | |
5f2fc772 | 4426 | emit_note_copy_after (rtx orig, rtx after) |
23b2ce53 | 4427 | { |
b3694847 | 4428 | rtx note; |
23b2ce53 | 4429 | |
5f2fc772 | 4430 | if (NOTE_LINE_NUMBER (orig) >= 0 && no_line_numbers) |
23b2ce53 RS |
4431 | { |
4432 | cur_insn_uid++; | |
4433 | return 0; | |
4434 | } | |
4435 | ||
68252e27 | 4436 | note = rtx_alloc (NOTE); |
23b2ce53 | 4437 | INSN_UID (note) = cur_insn_uid++; |
5f2fc772 NS |
4438 | NOTE_LINE_NUMBER (note) = NOTE_LINE_NUMBER (orig); |
4439 | NOTE_DATA (note) = NOTE_DATA (orig); | |
ba4f7968 | 4440 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
4441 | add_insn_after (note, after); |
4442 | return note; | |
4443 | } | |
4444 | \f | |
0435312e | 4445 | /* Like emit_insn_after, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4446 | rtx |
502b8322 | 4447 | emit_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 JH |
4448 | { |
4449 | rtx last = emit_insn_after (pattern, after); | |
0d682900 | 4450 | |
2f937369 DM |
4451 | after = NEXT_INSN (after); |
4452 | while (1) | |
4453 | { | |
d11cea13 | 4454 | if (active_insn_p (after)) |
0435312e | 4455 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4456 | if (after == last) |
4457 | break; | |
4458 | after = NEXT_INSN (after); | |
4459 | } | |
0d682900 JH |
4460 | return last; |
4461 | } | |
4462 | ||
0435312e | 4463 | /* Like emit_jump_insn_after, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4464 | rtx |
502b8322 | 4465 | emit_jump_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 JH |
4466 | { |
4467 | rtx last = emit_jump_insn_after (pattern, after); | |
2f937369 DM |
4468 | |
4469 | after = NEXT_INSN (after); | |
4470 | while (1) | |
4471 | { | |
d11cea13 | 4472 | if (active_insn_p (after)) |
0435312e | 4473 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4474 | if (after == last) |
4475 | break; | |
4476 | after = NEXT_INSN (after); | |
4477 | } | |
0d682900 JH |
4478 | return last; |
4479 | } | |
4480 | ||
0435312e | 4481 | /* Like emit_call_insn_after, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4482 | rtx |
502b8322 | 4483 | emit_call_insn_after_setloc (rtx pattern, rtx after, int loc) |
0d682900 JH |
4484 | { |
4485 | rtx last = emit_call_insn_after (pattern, after); | |
2f937369 DM |
4486 | |
4487 | after = NEXT_INSN (after); | |
4488 | while (1) | |
4489 | { | |
d11cea13 | 4490 | if (active_insn_p (after)) |
0435312e | 4491 | INSN_LOCATOR (after) = loc; |
2f937369 DM |
4492 | if (after == last) |
4493 | break; | |
4494 | after = NEXT_INSN (after); | |
4495 | } | |
0d682900 JH |
4496 | return last; |
4497 | } | |
4498 | ||
0435312e | 4499 | /* Like emit_insn_before, but set INSN_LOCATOR according to SCOPE. */ |
0d682900 | 4500 | rtx |
502b8322 | 4501 | emit_insn_before_setloc (rtx pattern, rtx before, int loc) |
0d682900 JH |
4502 | { |
4503 | rtx first = PREV_INSN (before); | |
4504 | rtx last = emit_insn_before (pattern, before); | |
4505 | ||
2f937369 DM |
4506 | first = NEXT_INSN (first); |
4507 | while (1) | |
4508 | { | |
d11cea13 | 4509 | if (active_insn_p (first)) |
0435312e | 4510 | INSN_LOCATOR (first) = loc; |
2f937369 DM |
4511 | if (first == last) |
4512 | break; | |
4513 | first = NEXT_INSN (first); | |
4514 | } | |
0d682900 JH |
4515 | return last; |
4516 | } | |
4517 | \f | |
2f937369 DM |
4518 | /* Take X and emit it at the end of the doubly-linked |
4519 | INSN list. | |
23b2ce53 RS |
4520 | |
4521 | Returns the last insn emitted. */ | |
4522 | ||
4523 | rtx | |
502b8322 | 4524 | emit_insn (rtx x) |
23b2ce53 | 4525 | { |
2f937369 DM |
4526 | rtx last = last_insn; |
4527 | rtx insn; | |
23b2ce53 | 4528 | |
2f937369 DM |
4529 | if (x == NULL_RTX) |
4530 | return last; | |
23b2ce53 | 4531 | |
2f937369 DM |
4532 | switch (GET_CODE (x)) |
4533 | { | |
4534 | case INSN: | |
4535 | case JUMP_INSN: | |
4536 | case CALL_INSN: | |
4537 | case CODE_LABEL: | |
4538 | case BARRIER: | |
4539 | case NOTE: | |
4540 | insn = x; | |
4541 | while (insn) | |
23b2ce53 | 4542 | { |
2f937369 | 4543 | rtx next = NEXT_INSN (insn); |
23b2ce53 | 4544 | add_insn (insn); |
2f937369 DM |
4545 | last = insn; |
4546 | insn = next; | |
23b2ce53 | 4547 | } |
2f937369 | 4548 | break; |
23b2ce53 | 4549 | |
2f937369 DM |
4550 | #ifdef ENABLE_RTL_CHECKING |
4551 | case SEQUENCE: | |
4552 | abort (); | |
4553 | break; | |
4554 | #endif | |
23b2ce53 | 4555 | |
2f937369 DM |
4556 | default: |
4557 | last = make_insn_raw (x); | |
4558 | add_insn (last); | |
4559 | break; | |
23b2ce53 RS |
4560 | } |
4561 | ||
4562 | return last; | |
4563 | } | |
4564 | ||
2f937369 DM |
4565 | /* Make an insn of code JUMP_INSN with pattern X |
4566 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4567 | |
4568 | rtx | |
502b8322 | 4569 | emit_jump_insn (rtx x) |
23b2ce53 | 4570 | { |
d950dee3 | 4571 | rtx last = NULL_RTX, insn; |
23b2ce53 | 4572 | |
2f937369 | 4573 | switch (GET_CODE (x)) |
23b2ce53 | 4574 | { |
2f937369 DM |
4575 | case INSN: |
4576 | case JUMP_INSN: | |
4577 | case CALL_INSN: | |
4578 | case CODE_LABEL: | |
4579 | case BARRIER: | |
4580 | case NOTE: | |
4581 | insn = x; | |
4582 | while (insn) | |
4583 | { | |
4584 | rtx next = NEXT_INSN (insn); | |
4585 | add_insn (insn); | |
4586 | last = insn; | |
4587 | insn = next; | |
4588 | } | |
4589 | break; | |
e0a5c5eb | 4590 | |
2f937369 DM |
4591 | #ifdef ENABLE_RTL_CHECKING |
4592 | case SEQUENCE: | |
4593 | abort (); | |
4594 | break; | |
4595 | #endif | |
e0a5c5eb | 4596 | |
2f937369 DM |
4597 | default: |
4598 | last = make_jump_insn_raw (x); | |
4599 | add_insn (last); | |
4600 | break; | |
3c030e88 | 4601 | } |
e0a5c5eb RS |
4602 | |
4603 | return last; | |
4604 | } | |
4605 | ||
2f937369 | 4606 | /* Make an insn of code CALL_INSN with pattern X |
23b2ce53 RS |
4607 | and add it to the end of the doubly-linked list. */ |
4608 | ||
4609 | rtx | |
502b8322 | 4610 | emit_call_insn (rtx x) |
23b2ce53 | 4611 | { |
2f937369 DM |
4612 | rtx insn; |
4613 | ||
4614 | switch (GET_CODE (x)) | |
23b2ce53 | 4615 | { |
2f937369 DM |
4616 | case INSN: |
4617 | case JUMP_INSN: | |
4618 | case CALL_INSN: | |
4619 | case CODE_LABEL: | |
4620 | case BARRIER: | |
4621 | case NOTE: | |
4622 | insn = emit_insn (x); | |
4623 | break; | |
23b2ce53 | 4624 | |
2f937369 DM |
4625 | #ifdef ENABLE_RTL_CHECKING |
4626 | case SEQUENCE: | |
4627 | abort (); | |
4628 | break; | |
4629 | #endif | |
23b2ce53 | 4630 | |
2f937369 DM |
4631 | default: |
4632 | insn = make_call_insn_raw (x); | |
23b2ce53 | 4633 | add_insn (insn); |
2f937369 | 4634 | break; |
23b2ce53 | 4635 | } |
2f937369 DM |
4636 | |
4637 | return insn; | |
23b2ce53 RS |
4638 | } |
4639 | ||
4640 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
4641 | ||
4642 | rtx | |
502b8322 | 4643 | emit_label (rtx label) |
23b2ce53 RS |
4644 | { |
4645 | /* This can be called twice for the same label | |
4646 | as a result of the confusion that follows a syntax error! | |
4647 | So make it harmless. */ | |
4648 | if (INSN_UID (label) == 0) | |
4649 | { | |
4650 | INSN_UID (label) = cur_insn_uid++; | |
4651 | add_insn (label); | |
4652 | } | |
4653 | return label; | |
4654 | } | |
4655 | ||
4656 | /* Make an insn of code BARRIER | |
4657 | and add it to the end of the doubly-linked list. */ | |
4658 | ||
4659 | rtx | |
502b8322 | 4660 | emit_barrier (void) |
23b2ce53 | 4661 | { |
b3694847 | 4662 | rtx barrier = rtx_alloc (BARRIER); |
23b2ce53 RS |
4663 | INSN_UID (barrier) = cur_insn_uid++; |
4664 | add_insn (barrier); | |
4665 | return barrier; | |
4666 | } | |
4667 | ||
4668 | /* Make an insn of code NOTE | |
4669 | with data-fields specified by FILE and LINE | |
4670 | and add it to the end of the doubly-linked list, | |
4671 | but only if line-numbers are desired for debugging info. */ | |
4672 | ||
4673 | rtx | |
502b8322 | 4674 | emit_line_note (const char *file, int line) |
23b2ce53 | 4675 | { |
2e040219 | 4676 | rtx note; |
502b8322 | 4677 | |
fd3acbb3 NS |
4678 | if (line < 0) |
4679 | abort (); | |
502b8322 | 4680 | |
3f1d071b | 4681 | set_file_and_line_for_stmt (file, line); |
23b2ce53 | 4682 | |
fd3acbb3 NS |
4683 | if (file && last_location.file && !strcmp (file, last_location.file) |
4684 | && line == last_location.line) | |
4685 | return NULL_RTX; | |
4686 | last_location.file = file; | |
4687 | last_location.line = line; | |
4688 | ||
23b2ce53 | 4689 | if (no_line_numbers) |
fd3acbb3 NS |
4690 | { |
4691 | cur_insn_uid++; | |
4692 | return NULL_RTX; | |
4693 | } | |
23b2ce53 | 4694 | |
2e040219 NS |
4695 | note = emit_note (line); |
4696 | NOTE_SOURCE_FILE (note) = file; | |
5f2fc772 NS |
4697 | |
4698 | return note; | |
4699 | } | |
4700 | ||
4701 | /* Emit a copy of note ORIG. */ | |
502b8322 | 4702 | |
5f2fc772 NS |
4703 | rtx |
4704 | emit_note_copy (rtx orig) | |
4705 | { | |
4706 | rtx note; | |
4707 | ||
4708 | if (NOTE_LINE_NUMBER (orig) >= 0 && no_line_numbers) | |
4709 | { | |
4710 | cur_insn_uid++; | |
4711 | return NULL_RTX; | |
4712 | } | |
4713 | ||
4714 | note = rtx_alloc (NOTE); | |
4715 | ||
4716 | INSN_UID (note) = cur_insn_uid++; | |
4717 | NOTE_DATA (note) = NOTE_DATA (orig); | |
4718 | NOTE_LINE_NUMBER (note) = NOTE_LINE_NUMBER (orig); | |
4719 | BLOCK_FOR_INSN (note) = NULL; | |
4720 | add_insn (note); | |
4721 | ||
2e040219 | 4722 | return note; |
23b2ce53 RS |
4723 | } |
4724 | ||
2e040219 NS |
4725 | /* Make an insn of code NOTE or type NOTE_NO |
4726 | and add it to the end of the doubly-linked list. */ | |
23b2ce53 RS |
4727 | |
4728 | rtx | |
502b8322 | 4729 | emit_note (int note_no) |
23b2ce53 | 4730 | { |
b3694847 | 4731 | rtx note; |
23b2ce53 | 4732 | |
23b2ce53 RS |
4733 | note = rtx_alloc (NOTE); |
4734 | INSN_UID (note) = cur_insn_uid++; | |
2e040219 | 4735 | NOTE_LINE_NUMBER (note) = note_no; |
dd107e66 | 4736 | memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note))); |
ba4f7968 | 4737 | BLOCK_FOR_INSN (note) = NULL; |
23b2ce53 RS |
4738 | add_insn (note); |
4739 | return note; | |
4740 | } | |
4741 | ||
fe77a034 | 4742 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
23b2ce53 RS |
4743 | |
4744 | rtx | |
502b8322 | 4745 | emit_line_note_force (const char *file, int line) |
23b2ce53 | 4746 | { |
fd3acbb3 | 4747 | last_location.line = -1; |
23b2ce53 RS |
4748 | return emit_line_note (file, line); |
4749 | } | |
4750 | ||
4751 | /* Cause next statement to emit a line note even if the line number | |
4752 | has not changed. This is used at the beginning of a function. */ | |
4753 | ||
4754 | void | |
502b8322 | 4755 | force_next_line_note (void) |
23b2ce53 | 4756 | { |
fd3acbb3 | 4757 | last_location.line = -1; |
23b2ce53 | 4758 | } |
87b47c85 AM |
4759 | |
4760 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
30f7a378 | 4761 | note of this type already exists, remove it first. */ |
87b47c85 | 4762 | |
3d238248 | 4763 | rtx |
502b8322 | 4764 | set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum) |
87b47c85 AM |
4765 | { |
4766 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
4767 | ||
52488da1 JW |
4768 | switch (kind) |
4769 | { | |
4770 | case REG_EQUAL: | |
4771 | case REG_EQUIV: | |
4772 | /* Don't add REG_EQUAL/REG_EQUIV notes if the insn | |
4773 | has multiple sets (some callers assume single_set | |
4774 | means the insn only has one set, when in fact it | |
4775 | means the insn only has one * useful * set). */ | |
4776 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
4777 | { | |
4778 | if (note) | |
4779 | abort (); | |
4780 | return NULL_RTX; | |
4781 | } | |
4782 | ||
4783 | /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes. | |
4784 | It serves no useful purpose and breaks eliminate_regs. */ | |
4785 | if (GET_CODE (datum) == ASM_OPERANDS) | |
4786 | return NULL_RTX; | |
4787 | break; | |
4788 | ||
4789 | default: | |
4790 | break; | |
4791 | } | |
3d238248 | 4792 | |
750c9258 | 4793 | if (note) |
3d238248 JJ |
4794 | { |
4795 | XEXP (note, 0) = datum; | |
4796 | return note; | |
4797 | } | |
87b47c85 AM |
4798 | |
4799 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3d238248 | 4800 | return REG_NOTES (insn); |
87b47c85 | 4801 | } |
23b2ce53 RS |
4802 | \f |
4803 | /* Return an indication of which type of insn should have X as a body. | |
4804 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
4805 | ||
4806 | enum rtx_code | |
502b8322 | 4807 | classify_insn (rtx x) |
23b2ce53 RS |
4808 | { |
4809 | if (GET_CODE (x) == CODE_LABEL) | |
4810 | return CODE_LABEL; | |
4811 | if (GET_CODE (x) == CALL) | |
4812 | return CALL_INSN; | |
4813 | if (GET_CODE (x) == RETURN) | |
4814 | return JUMP_INSN; | |
4815 | if (GET_CODE (x) == SET) | |
4816 | { | |
4817 | if (SET_DEST (x) == pc_rtx) | |
4818 | return JUMP_INSN; | |
4819 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
4820 | return CALL_INSN; | |
4821 | else | |
4822 | return INSN; | |
4823 | } | |
4824 | if (GET_CODE (x) == PARALLEL) | |
4825 | { | |
b3694847 | 4826 | int j; |
23b2ce53 RS |
4827 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) |
4828 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
4829 | return CALL_INSN; | |
4830 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4831 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
4832 | return JUMP_INSN; | |
4833 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
4834 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
4835 | return CALL_INSN; | |
4836 | } | |
4837 | return INSN; | |
4838 | } | |
4839 | ||
4840 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
4841 | If X is a label, it is simply added into the insn chain. */ | |
4842 | ||
4843 | rtx | |
502b8322 | 4844 | emit (rtx x) |
23b2ce53 RS |
4845 | { |
4846 | enum rtx_code code = classify_insn (x); | |
4847 | ||
4848 | if (code == CODE_LABEL) | |
4849 | return emit_label (x); | |
4850 | else if (code == INSN) | |
4851 | return emit_insn (x); | |
4852 | else if (code == JUMP_INSN) | |
4853 | { | |
b3694847 | 4854 | rtx insn = emit_jump_insn (x); |
7f1c097d | 4855 | if (any_uncondjump_p (insn) || GET_CODE (x) == RETURN) |
23b2ce53 RS |
4856 | return emit_barrier (); |
4857 | return insn; | |
4858 | } | |
4859 | else if (code == CALL_INSN) | |
4860 | return emit_call_insn (x); | |
4861 | else | |
4862 | abort (); | |
4863 | } | |
4864 | \f | |
e2500fed GK |
4865 | /* Space for free sequence stack entries. */ |
4866 | static GTY ((deletable (""))) struct sequence_stack *free_sequence_stack; | |
4867 | ||
5c7a310f MM |
4868 | /* Begin emitting insns to a sequence which can be packaged in an |
4869 | RTL_EXPR. If this sequence will contain something that might cause | |
4870 | the compiler to pop arguments to function calls (because those | |
4871 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
4872 | details), use do_pending_stack_adjust before calling this function. | |
4873 | That will ensure that the deferred pops are not accidentally | |
4eb00163 | 4874 | emitted in the middle of this sequence. */ |
23b2ce53 RS |
4875 | |
4876 | void | |
502b8322 | 4877 | start_sequence (void) |
23b2ce53 RS |
4878 | { |
4879 | struct sequence_stack *tem; | |
4880 | ||
e2500fed GK |
4881 | if (free_sequence_stack != NULL) |
4882 | { | |
4883 | tem = free_sequence_stack; | |
4884 | free_sequence_stack = tem->next; | |
4885 | } | |
4886 | else | |
4887 | tem = (struct sequence_stack *) ggc_alloc (sizeof (struct sequence_stack)); | |
23b2ce53 | 4888 | |
49ad7cfa | 4889 | tem->next = seq_stack; |
23b2ce53 RS |
4890 | tem->first = first_insn; |
4891 | tem->last = last_insn; | |
591ccf92 | 4892 | tem->sequence_rtl_expr = seq_rtl_expr; |
23b2ce53 | 4893 | |
49ad7cfa | 4894 | seq_stack = tem; |
23b2ce53 RS |
4895 | |
4896 | first_insn = 0; | |
4897 | last_insn = 0; | |
4898 | } | |
4899 | ||
591ccf92 MM |
4900 | /* Similarly, but indicate that this sequence will be placed in T, an |
4901 | RTL_EXPR. See the documentation for start_sequence for more | |
4902 | information about how to use this function. */ | |
4903 | ||
4904 | void | |
502b8322 | 4905 | start_sequence_for_rtl_expr (tree t) |
591ccf92 MM |
4906 | { |
4907 | start_sequence (); | |
4908 | ||
4909 | seq_rtl_expr = t; | |
4910 | } | |
4911 | ||
5c7a310f MM |
4912 | /* Set up the insn chain starting with FIRST as the current sequence, |
4913 | saving the previously current one. See the documentation for | |
4914 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
4915 | |
4916 | void | |
502b8322 | 4917 | push_to_sequence (rtx first) |
23b2ce53 RS |
4918 | { |
4919 | rtx last; | |
4920 | ||
4921 | start_sequence (); | |
4922 | ||
4923 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
4924 | ||
4925 | first_insn = first; | |
4926 | last_insn = last; | |
4927 | } | |
4928 | ||
c14f7160 ML |
4929 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
4930 | ||
4931 | void | |
502b8322 | 4932 | push_to_full_sequence (rtx first, rtx last) |
c14f7160 ML |
4933 | { |
4934 | start_sequence (); | |
4935 | first_insn = first; | |
4936 | last_insn = last; | |
4937 | /* We really should have the end of the insn chain here. */ | |
4938 | if (last && NEXT_INSN (last)) | |
4939 | abort (); | |
4940 | } | |
4941 | ||
f15ae3a1 TW |
4942 | /* Set up the outer-level insn chain |
4943 | as the current sequence, saving the previously current one. */ | |
4944 | ||
4945 | void | |
502b8322 | 4946 | push_topmost_sequence (void) |
f15ae3a1 | 4947 | { |
aefdd5ab | 4948 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
4949 | |
4950 | start_sequence (); | |
4951 | ||
49ad7cfa | 4952 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
4953 | top = stack; |
4954 | ||
4955 | first_insn = top->first; | |
4956 | last_insn = top->last; | |
591ccf92 | 4957 | seq_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
4958 | } |
4959 | ||
4960 | /* After emitting to the outer-level insn chain, update the outer-level | |
4961 | insn chain, and restore the previous saved state. */ | |
4962 | ||
4963 | void | |
502b8322 | 4964 | pop_topmost_sequence (void) |
f15ae3a1 | 4965 | { |
aefdd5ab | 4966 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 4967 | |
49ad7cfa | 4968 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
4969 | top = stack; |
4970 | ||
4971 | top->first = first_insn; | |
4972 | top->last = last_insn; | |
591ccf92 | 4973 | /* ??? Why don't we save seq_rtl_expr here? */ |
f15ae3a1 TW |
4974 | |
4975 | end_sequence (); | |
4976 | } | |
4977 | ||
23b2ce53 RS |
4978 | /* After emitting to a sequence, restore previous saved state. |
4979 | ||
5c7a310f | 4980 | To get the contents of the sequence just made, you must call |
2f937369 | 4981 | `get_insns' *before* calling here. |
5c7a310f MM |
4982 | |
4983 | If the compiler might have deferred popping arguments while | |
4984 | generating this sequence, and this sequence will not be immediately | |
4985 | inserted into the instruction stream, use do_pending_stack_adjust | |
2f937369 | 4986 | before calling get_insns. That will ensure that the deferred |
5c7a310f MM |
4987 | pops are inserted into this sequence, and not into some random |
4988 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
4989 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
4990 | |
4991 | void | |
502b8322 | 4992 | end_sequence (void) |
23b2ce53 | 4993 | { |
49ad7cfa | 4994 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
4995 | |
4996 | first_insn = tem->first; | |
4997 | last_insn = tem->last; | |
591ccf92 | 4998 | seq_rtl_expr = tem->sequence_rtl_expr; |
49ad7cfa | 4999 | seq_stack = tem->next; |
23b2ce53 | 5000 | |
e2500fed GK |
5001 | memset (tem, 0, sizeof (*tem)); |
5002 | tem->next = free_sequence_stack; | |
5003 | free_sequence_stack = tem; | |
23b2ce53 RS |
5004 | } |
5005 | ||
c14f7160 ML |
5006 | /* This works like end_sequence, but records the old sequence in FIRST |
5007 | and LAST. */ | |
5008 | ||
5009 | void | |
502b8322 | 5010 | end_full_sequence (rtx *first, rtx *last) |
c14f7160 ML |
5011 | { |
5012 | *first = first_insn; | |
5013 | *last = last_insn; | |
68252e27 | 5014 | end_sequence (); |
c14f7160 ML |
5015 | } |
5016 | ||
23b2ce53 RS |
5017 | /* Return 1 if currently emitting into a sequence. */ |
5018 | ||
5019 | int | |
502b8322 | 5020 | in_sequence_p (void) |
23b2ce53 | 5021 | { |
49ad7cfa | 5022 | return seq_stack != 0; |
23b2ce53 | 5023 | } |
23b2ce53 | 5024 | \f |
59ec66dc MM |
5025 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
5026 | ||
5027 | void | |
502b8322 | 5028 | init_virtual_regs (struct emit_status *es) |
59ec66dc | 5029 | { |
49ad7cfa BS |
5030 | rtx *ptr = es->x_regno_reg_rtx; |
5031 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
5032 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
5033 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
5034 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
5035 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
5036 | } | |
5037 | ||
da43a810 BS |
5038 | \f |
5039 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
5040 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
5041 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
5042 | static int copy_insn_n_scratches; | |
5043 | ||
5044 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5045 | copied an ASM_OPERANDS. | |
5046 | In that case, it is the original input-operand vector. */ | |
5047 | static rtvec orig_asm_operands_vector; | |
5048 | ||
5049 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
5050 | copied an ASM_OPERANDS. | |
5051 | In that case, it is the copied input-operand vector. */ | |
5052 | static rtvec copy_asm_operands_vector; | |
5053 | ||
5054 | /* Likewise for the constraints vector. */ | |
5055 | static rtvec orig_asm_constraints_vector; | |
5056 | static rtvec copy_asm_constraints_vector; | |
5057 | ||
5058 | /* Recursively create a new copy of an rtx for copy_insn. | |
5059 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5060 | ASM_OPERANDs properly. | |
5061 | Normally, this function is not used directly; use copy_insn as front end. | |
5062 | However, you could first copy an insn pattern with copy_insn and then use | |
5063 | this function afterwards to properly copy any REG_NOTEs containing | |
5064 | SCRATCHes. */ | |
5065 | ||
5066 | rtx | |
502b8322 | 5067 | copy_insn_1 (rtx orig) |
da43a810 | 5068 | { |
b3694847 SS |
5069 | rtx copy; |
5070 | int i, j; | |
5071 | RTX_CODE code; | |
5072 | const char *format_ptr; | |
da43a810 BS |
5073 | |
5074 | code = GET_CODE (orig); | |
5075 | ||
5076 | switch (code) | |
5077 | { | |
5078 | case REG: | |
5079 | case QUEUED: | |
5080 | case CONST_INT: | |
5081 | case CONST_DOUBLE: | |
69ef87e2 | 5082 | case CONST_VECTOR: |
da43a810 BS |
5083 | case SYMBOL_REF: |
5084 | case CODE_LABEL: | |
5085 | case PC: | |
5086 | case CC0: | |
5087 | case ADDRESSOF: | |
5088 | return orig; | |
5089 | ||
5090 | case SCRATCH: | |
5091 | for (i = 0; i < copy_insn_n_scratches; i++) | |
5092 | if (copy_insn_scratch_in[i] == orig) | |
5093 | return copy_insn_scratch_out[i]; | |
5094 | break; | |
5095 | ||
5096 | case CONST: | |
5097 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
5098 | a LABEL_REF, it isn't sharable. */ | |
5099 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
5100 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
5101 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
5102 | return orig; | |
5103 | break; | |
750c9258 | 5104 | |
da43a810 BS |
5105 | /* A MEM with a constant address is not sharable. The problem is that |
5106 | the constant address may need to be reloaded. If the mem is shared, | |
5107 | then reloading one copy of this mem will cause all copies to appear | |
5108 | to have been reloaded. */ | |
5109 | ||
5110 | default: | |
5111 | break; | |
5112 | } | |
5113 | ||
5114 | copy = rtx_alloc (code); | |
5115 | ||
5116 | /* Copy the various flags, and other information. We assume that | |
5117 | all fields need copying, and then clear the fields that should | |
5118 | not be copied. That is the sensible default behavior, and forces | |
5119 | us to explicitly document why we are *not* copying a flag. */ | |
5120 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
5121 | ||
5122 | /* We do not copy the USED flag, which is used as a mark bit during | |
5123 | walks over the RTL. */ | |
2adc7f12 | 5124 | RTX_FLAG (copy, used) = 0; |
da43a810 BS |
5125 | |
5126 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
5127 | if (GET_RTX_CLASS (code) == 'i') | |
5128 | { | |
2adc7f12 JJ |
5129 | RTX_FLAG (copy, jump) = 0; |
5130 | RTX_FLAG (copy, call) = 0; | |
5131 | RTX_FLAG (copy, frame_related) = 0; | |
da43a810 | 5132 | } |
750c9258 | 5133 | |
da43a810 BS |
5134 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); |
5135 | ||
5136 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
5137 | { | |
e63db8f6 | 5138 | copy->fld[i] = orig->fld[i]; |
da43a810 BS |
5139 | switch (*format_ptr++) |
5140 | { | |
5141 | case 'e': | |
da43a810 BS |
5142 | if (XEXP (orig, i) != NULL) |
5143 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
5144 | break; | |
5145 | ||
da43a810 BS |
5146 | case 'E': |
5147 | case 'V': | |
da43a810 BS |
5148 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
5149 | XVEC (copy, i) = copy_asm_constraints_vector; | |
5150 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
5151 | XVEC (copy, i) = copy_asm_operands_vector; | |
5152 | else if (XVEC (orig, i) != NULL) | |
5153 | { | |
5154 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
5155 | for (j = 0; j < XVECLEN (copy, i); j++) | |
5156 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
5157 | } | |
5158 | break; | |
5159 | ||
da43a810 | 5160 | case 't': |
da43a810 | 5161 | case 'w': |
da43a810 | 5162 | case 'i': |
da43a810 BS |
5163 | case 's': |
5164 | case 'S': | |
e63db8f6 BS |
5165 | case 'u': |
5166 | case '0': | |
5167 | /* These are left unchanged. */ | |
da43a810 BS |
5168 | break; |
5169 | ||
5170 | default: | |
5171 | abort (); | |
5172 | } | |
5173 | } | |
5174 | ||
5175 | if (code == SCRATCH) | |
5176 | { | |
5177 | i = copy_insn_n_scratches++; | |
5178 | if (i >= MAX_RECOG_OPERANDS) | |
5179 | abort (); | |
5180 | copy_insn_scratch_in[i] = orig; | |
5181 | copy_insn_scratch_out[i] = copy; | |
5182 | } | |
5183 | else if (code == ASM_OPERANDS) | |
5184 | { | |
6462bb43 AO |
5185 | orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig); |
5186 | copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy); | |
5187 | orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig); | |
5188 | copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy); | |
da43a810 BS |
5189 | } |
5190 | ||
5191 | return copy; | |
5192 | } | |
5193 | ||
5194 | /* Create a new copy of an rtx. | |
5195 | This function differs from copy_rtx in that it handles SCRATCHes and | |
5196 | ASM_OPERANDs properly. | |
5197 | INSN doesn't really have to be a full INSN; it could be just the | |
5198 | pattern. */ | |
5199 | rtx | |
502b8322 | 5200 | copy_insn (rtx insn) |
da43a810 BS |
5201 | { |
5202 | copy_insn_n_scratches = 0; | |
5203 | orig_asm_operands_vector = 0; | |
5204 | orig_asm_constraints_vector = 0; | |
5205 | copy_asm_operands_vector = 0; | |
5206 | copy_asm_constraints_vector = 0; | |
5207 | return copy_insn_1 (insn); | |
5208 | } | |
59ec66dc | 5209 | |
23b2ce53 RS |
5210 | /* Initialize data structures and variables in this file |
5211 | before generating rtl for each function. */ | |
5212 | ||
5213 | void | |
502b8322 | 5214 | init_emit (void) |
23b2ce53 | 5215 | { |
01d939e8 | 5216 | struct function *f = cfun; |
23b2ce53 | 5217 | |
e2500fed | 5218 | f->emit = (struct emit_status *) ggc_alloc (sizeof (struct emit_status)); |
23b2ce53 RS |
5219 | first_insn = NULL; |
5220 | last_insn = NULL; | |
591ccf92 | 5221 | seq_rtl_expr = NULL; |
23b2ce53 RS |
5222 | cur_insn_uid = 1; |
5223 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
fd3acbb3 NS |
5224 | last_location.line = 0; |
5225 | last_location.file = 0; | |
23b2ce53 RS |
5226 | first_label_num = label_num; |
5227 | last_label_num = 0; | |
49ad7cfa | 5228 | seq_stack = NULL; |
23b2ce53 | 5229 | |
23b2ce53 RS |
5230 | /* Init the tables that describe all the pseudo regs. */ |
5231 | ||
3502dc9c | 5232 | f->emit->regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 5233 | |
49ad7cfa | 5234 | f->emit->regno_pointer_align |
e2500fed GK |
5235 | = (unsigned char *) ggc_alloc_cleared (f->emit->regno_pointer_align_length |
5236 | * sizeof (unsigned char)); | |
86fe05e0 | 5237 | |
750c9258 | 5238 | regno_reg_rtx |
ddb0ae00 | 5239 | = (rtx *) ggc_alloc (f->emit->regno_pointer_align_length * sizeof (rtx)); |
0d4903b8 | 5240 | |
e50126e8 | 5241 | /* Put copies of all the hard registers into regno_reg_rtx. */ |
6cde4876 JL |
5242 | memcpy (regno_reg_rtx, |
5243 | static_regno_reg_rtx, | |
5244 | FIRST_PSEUDO_REGISTER * sizeof (rtx)); | |
e50126e8 | 5245 | |
23b2ce53 | 5246 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ |
49ad7cfa | 5247 | init_virtual_regs (f->emit); |
740ab4a2 RK |
5248 | |
5249 | /* Indicate that the virtual registers and stack locations are | |
5250 | all pointers. */ | |
3502dc9c JDA |
5251 | REG_POINTER (stack_pointer_rtx) = 1; |
5252 | REG_POINTER (frame_pointer_rtx) = 1; | |
5253 | REG_POINTER (hard_frame_pointer_rtx) = 1; | |
5254 | REG_POINTER (arg_pointer_rtx) = 1; | |
740ab4a2 | 5255 | |
3502dc9c JDA |
5256 | REG_POINTER (virtual_incoming_args_rtx) = 1; |
5257 | REG_POINTER (virtual_stack_vars_rtx) = 1; | |
5258 | REG_POINTER (virtual_stack_dynamic_rtx) = 1; | |
5259 | REG_POINTER (virtual_outgoing_args_rtx) = 1; | |
5260 | REG_POINTER (virtual_cfa_rtx) = 1; | |
5e82e7bd | 5261 | |
86fe05e0 | 5262 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
5263 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
5264 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5265 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
5266 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
5267 | ||
5268 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5269 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
5270 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
5271 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
5272 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
5273 | #endif |
5274 | ||
5e82e7bd JVA |
5275 | #ifdef INIT_EXPANDERS |
5276 | INIT_EXPANDERS; | |
5277 | #endif | |
23b2ce53 RS |
5278 | } |
5279 | ||
ff88fe10 | 5280 | /* Generate the constant 0. */ |
69ef87e2 AH |
5281 | |
5282 | static rtx | |
502b8322 | 5283 | gen_const_vector_0 (enum machine_mode mode) |
69ef87e2 AH |
5284 | { |
5285 | rtx tem; | |
5286 | rtvec v; | |
5287 | int units, i; | |
5288 | enum machine_mode inner; | |
5289 | ||
5290 | units = GET_MODE_NUNITS (mode); | |
5291 | inner = GET_MODE_INNER (mode); | |
5292 | ||
5293 | v = rtvec_alloc (units); | |
5294 | ||
5295 | /* We need to call this function after we to set CONST0_RTX first. */ | |
5296 | if (!CONST0_RTX (inner)) | |
5297 | abort (); | |
5298 | ||
5299 | for (i = 0; i < units; ++i) | |
5300 | RTVEC_ELT (v, i) = CONST0_RTX (inner); | |
5301 | ||
a06e3c40 | 5302 | tem = gen_rtx_raw_CONST_VECTOR (mode, v); |
69ef87e2 AH |
5303 | return tem; |
5304 | } | |
5305 | ||
a06e3c40 R |
5306 | /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when |
5307 | all elements are zero. */ | |
5308 | rtx | |
502b8322 | 5309 | gen_rtx_CONST_VECTOR (enum machine_mode mode, rtvec v) |
a06e3c40 R |
5310 | { |
5311 | rtx inner_zero = CONST0_RTX (GET_MODE_INNER (mode)); | |
5312 | int i; | |
5313 | ||
5314 | for (i = GET_MODE_NUNITS (mode) - 1; i >= 0; i--) | |
5315 | if (RTVEC_ELT (v, i) != inner_zero) | |
5316 | return gen_rtx_raw_CONST_VECTOR (mode, v); | |
5317 | return CONST0_RTX (mode); | |
5318 | } | |
5319 | ||
23b2ce53 RS |
5320 | /* Create some permanent unique rtl objects shared between all functions. |
5321 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
5322 | ||
5323 | void | |
502b8322 | 5324 | init_emit_once (int line_numbers) |
23b2ce53 RS |
5325 | { |
5326 | int i; | |
5327 | enum machine_mode mode; | |
9ec36da5 | 5328 | enum machine_mode double_mode; |
23b2ce53 | 5329 | |
5692c7bc ZW |
5330 | /* Initialize the CONST_INT, CONST_DOUBLE, and memory attribute hash |
5331 | tables. */ | |
17211ab5 GK |
5332 | const_int_htab = htab_create_ggc (37, const_int_htab_hash, |
5333 | const_int_htab_eq, NULL); | |
173b24b9 | 5334 | |
17211ab5 GK |
5335 | const_double_htab = htab_create_ggc (37, const_double_htab_hash, |
5336 | const_double_htab_eq, NULL); | |
5692c7bc | 5337 | |
17211ab5 GK |
5338 | mem_attrs_htab = htab_create_ggc (37, mem_attrs_htab_hash, |
5339 | mem_attrs_htab_eq, NULL); | |
a560d4d4 JH |
5340 | reg_attrs_htab = htab_create_ggc (37, reg_attrs_htab_hash, |
5341 | reg_attrs_htab_eq, NULL); | |
67673f5c | 5342 | |
23b2ce53 RS |
5343 | no_line_numbers = ! line_numbers; |
5344 | ||
43fa6302 AS |
5345 | /* Compute the word and byte modes. */ |
5346 | ||
5347 | byte_mode = VOIDmode; | |
5348 | word_mode = VOIDmode; | |
5349 | double_mode = VOIDmode; | |
5350 | ||
5351 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
5352 | mode = GET_MODE_WIDER_MODE (mode)) | |
5353 | { | |
5354 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
5355 | && byte_mode == VOIDmode) | |
5356 | byte_mode = mode; | |
5357 | ||
5358 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
5359 | && word_mode == VOIDmode) | |
5360 | word_mode = mode; | |
5361 | } | |
5362 | ||
43fa6302 AS |
5363 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; |
5364 | mode = GET_MODE_WIDER_MODE (mode)) | |
5365 | { | |
5366 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
5367 | && double_mode == VOIDmode) | |
5368 | double_mode = mode; | |
5369 | } | |
5370 | ||
5371 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
5372 | ||
5da077de AS |
5373 | /* Assign register numbers to the globally defined register rtx. |
5374 | This must be done at runtime because the register number field | |
5375 | is in a union and some compilers can't initialize unions. */ | |
5376 | ||
5377 | pc_rtx = gen_rtx (PC, VOIDmode); | |
5378 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
08394eef BS |
5379 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); |
5380 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
5da077de | 5381 | if (hard_frame_pointer_rtx == 0) |
750c9258 | 5382 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, |
08394eef | 5383 | HARD_FRAME_POINTER_REGNUM); |
5da077de | 5384 | if (arg_pointer_rtx == 0) |
08394eef | 5385 | arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM); |
750c9258 | 5386 | virtual_incoming_args_rtx = |
08394eef | 5387 | gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); |
750c9258 | 5388 | virtual_stack_vars_rtx = |
08394eef | 5389 | gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); |
750c9258 | 5390 | virtual_stack_dynamic_rtx = |
08394eef | 5391 | gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); |
750c9258 AJ |
5392 | virtual_outgoing_args_rtx = |
5393 | gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
08394eef | 5394 | virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); |
5da077de | 5395 | |
6cde4876 JL |
5396 | /* Initialize RTL for commonly used hard registers. These are |
5397 | copied into regno_reg_rtx as we begin to compile each function. */ | |
5398 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5399 | static_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i); | |
5400 | ||
5da077de | 5401 | #ifdef INIT_EXPANDERS |
414c4dc4 NC |
5402 | /* This is to initialize {init|mark|free}_machine_status before the first |
5403 | call to push_function_context_to. This is needed by the Chill front | |
a1f300c0 | 5404 | end which calls push_function_context_to before the first call to |
5da077de AS |
5405 | init_function_start. */ |
5406 | INIT_EXPANDERS; | |
5407 | #endif | |
5408 | ||
23b2ce53 RS |
5409 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
5410 | ||
c5c76735 JL |
5411 | /* Don't use gen_rtx here since gen_rtx in this case |
5412 | tries to use these variables. */ | |
23b2ce53 | 5413 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
750c9258 | 5414 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
f1b690f1 | 5415 | gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i); |
23b2ce53 | 5416 | |
68d75312 JC |
5417 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
5418 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 5419 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 5420 | else |
3b80f6ca | 5421 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 5422 | |
5692c7bc ZW |
5423 | REAL_VALUE_FROM_INT (dconst0, 0, 0, double_mode); |
5424 | REAL_VALUE_FROM_INT (dconst1, 1, 0, double_mode); | |
5425 | REAL_VALUE_FROM_INT (dconst2, 2, 0, double_mode); | |
5426 | REAL_VALUE_FROM_INT (dconstm1, -1, -1, double_mode); | |
03f2ea93 RS |
5427 | REAL_VALUE_FROM_INT (dconstm2, -2, -1, double_mode); |
5428 | ||
5429 | dconsthalf = dconst1; | |
5430 | dconsthalf.exp--; | |
23b2ce53 RS |
5431 | |
5432 | for (i = 0; i <= 2; i++) | |
5433 | { | |
b216cd4a ZW |
5434 | REAL_VALUE_TYPE *r = |
5435 | (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2); | |
5436 | ||
23b2ce53 RS |
5437 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; |
5438 | mode = GET_MODE_WIDER_MODE (mode)) | |
5692c7bc ZW |
5439 | const_tiny_rtx[i][(int) mode] = |
5440 | CONST_DOUBLE_FROM_REAL_VALUE (*r, mode); | |
23b2ce53 | 5441 | |
906c4e36 | 5442 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
5443 | |
5444 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
5445 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 5446 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
5447 | |
5448 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
5449 | mode != VOIDmode; | |
5450 | mode = GET_MODE_WIDER_MODE (mode)) | |
5451 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
5452 | } |
5453 | ||
69ef87e2 AH |
5454 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); |
5455 | mode != VOIDmode; | |
5456 | mode = GET_MODE_WIDER_MODE (mode)) | |
ff88fe10 | 5457 | const_tiny_rtx[0][(int) mode] = gen_const_vector_0 (mode); |
69ef87e2 AH |
5458 | |
5459 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); | |
5460 | mode != VOIDmode; | |
5461 | mode = GET_MODE_WIDER_MODE (mode)) | |
ff88fe10 | 5462 | const_tiny_rtx[0][(int) mode] = gen_const_vector_0 (mode); |
69ef87e2 | 5463 | |
dbbbbf3b JDA |
5464 | for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i) |
5465 | if (GET_MODE_CLASS ((enum machine_mode) i) == MODE_CC) | |
5466 | const_tiny_rtx[0][i] = const0_rtx; | |
23b2ce53 | 5467 | |
f0417c82 RH |
5468 | const_tiny_rtx[0][(int) BImode] = const0_rtx; |
5469 | if (STORE_FLAG_VALUE == 1) | |
5470 | const_tiny_rtx[1][(int) BImode] = const1_rtx; | |
5471 | ||
a7e1e2ac AO |
5472 | #ifdef RETURN_ADDRESS_POINTER_REGNUM |
5473 | return_address_pointer_rtx | |
08394eef | 5474 | = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); |
a7e1e2ac AO |
5475 | #endif |
5476 | ||
5477 | #ifdef STRUCT_VALUE | |
5478 | struct_value_rtx = STRUCT_VALUE; | |
5479 | #else | |
5480 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
5481 | #endif | |
5482 | ||
5483 | #ifdef STRUCT_VALUE_INCOMING | |
5484 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
5485 | #else | |
5486 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
5487 | struct_value_incoming_rtx | |
5488 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
5489 | #else | |
5490 | struct_value_incoming_rtx = struct_value_rtx; | |
5491 | #endif | |
5492 | #endif | |
5493 | ||
5494 | #ifdef STATIC_CHAIN_REGNUM | |
5495 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
5496 | ||
5497 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
5498 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
5499 | static_chain_incoming_rtx | |
5500 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
5501 | else | |
5502 | #endif | |
5503 | static_chain_incoming_rtx = static_chain_rtx; | |
5504 | #endif | |
5505 | ||
5506 | #ifdef STATIC_CHAIN | |
5507 | static_chain_rtx = STATIC_CHAIN; | |
5508 | ||
5509 | #ifdef STATIC_CHAIN_INCOMING | |
5510 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
5511 | #else | |
5512 | static_chain_incoming_rtx = static_chain_rtx; | |
5513 | #endif | |
5514 | #endif | |
5515 | ||
fc555370 | 5516 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) |
751551d5 | 5517 | pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); |
23b2ce53 | 5518 | } |
a11759a3 JR |
5519 | \f |
5520 | /* Query and clear/ restore no_line_numbers. This is used by the | |
5521 | switch / case handling in stmt.c to give proper line numbers in | |
5522 | warnings about unreachable code. */ | |
5523 | ||
5524 | int | |
502b8322 | 5525 | force_line_numbers (void) |
a11759a3 JR |
5526 | { |
5527 | int old = no_line_numbers; | |
5528 | ||
5529 | no_line_numbers = 0; | |
5530 | if (old) | |
5531 | force_next_line_note (); | |
5532 | return old; | |
5533 | } | |
5534 | ||
5535 | void | |
502b8322 | 5536 | restore_line_number_status (int old_value) |
a11759a3 JR |
5537 | { |
5538 | no_line_numbers = old_value; | |
5539 | } | |
969d70ca JH |
5540 | |
5541 | /* Produce exact duplicate of insn INSN after AFTER. | |
5542 | Care updating of libcall regions if present. */ | |
5543 | ||
5544 | rtx | |
502b8322 | 5545 | emit_copy_of_insn_after (rtx insn, rtx after) |
969d70ca JH |
5546 | { |
5547 | rtx new; | |
5548 | rtx note1, note2, link; | |
5549 | ||
5550 | switch (GET_CODE (insn)) | |
5551 | { | |
5552 | case INSN: | |
5553 | new = emit_insn_after (copy_insn (PATTERN (insn)), after); | |
5554 | break; | |
5555 | ||
5556 | case JUMP_INSN: | |
5557 | new = emit_jump_insn_after (copy_insn (PATTERN (insn)), after); | |
5558 | break; | |
5559 | ||
5560 | case CALL_INSN: | |
5561 | new = emit_call_insn_after (copy_insn (PATTERN (insn)), after); | |
5562 | if (CALL_INSN_FUNCTION_USAGE (insn)) | |
5563 | CALL_INSN_FUNCTION_USAGE (new) | |
5564 | = copy_insn (CALL_INSN_FUNCTION_USAGE (insn)); | |
5565 | SIBLING_CALL_P (new) = SIBLING_CALL_P (insn); | |
5566 | CONST_OR_PURE_CALL_P (new) = CONST_OR_PURE_CALL_P (insn); | |
5567 | break; | |
5568 | ||
5569 | default: | |
5570 | abort (); | |
5571 | } | |
5572 | ||
5573 | /* Update LABEL_NUSES. */ | |
5574 | mark_jump_label (PATTERN (new), new, 0); | |
5575 | ||
0435312e | 5576 | INSN_LOCATOR (new) = INSN_LOCATOR (insn); |
ba4f7968 | 5577 | |
969d70ca JH |
5578 | /* Copy all REG_NOTES except REG_LABEL since mark_jump_label will |
5579 | make them. */ | |
5580 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
5581 | if (REG_NOTE_KIND (link) != REG_LABEL) | |
5582 | { | |
5583 | if (GET_CODE (link) == EXPR_LIST) | |
5584 | REG_NOTES (new) | |
5585 | = copy_insn_1 (gen_rtx_EXPR_LIST (REG_NOTE_KIND (link), | |
5586 | XEXP (link, 0), | |
5587 | REG_NOTES (new))); | |
5588 | else | |
5589 | REG_NOTES (new) | |
5590 | = copy_insn_1 (gen_rtx_INSN_LIST (REG_NOTE_KIND (link), | |
5591 | XEXP (link, 0), | |
5592 | REG_NOTES (new))); | |
5593 | } | |
5594 | ||
5595 | /* Fix the libcall sequences. */ | |
5596 | if ((note1 = find_reg_note (new, REG_RETVAL, NULL_RTX)) != NULL) | |
5597 | { | |
5598 | rtx p = new; | |
5599 | while ((note2 = find_reg_note (p, REG_LIBCALL, NULL_RTX)) == NULL) | |
5600 | p = PREV_INSN (p); | |
5601 | XEXP (note1, 0) = p; | |
5602 | XEXP (note2, 0) = new; | |
5603 | } | |
6f0d3566 | 5604 | INSN_CODE (new) = INSN_CODE (insn); |
969d70ca JH |
5605 | return new; |
5606 | } | |
e2500fed GK |
5607 | |
5608 | #include "gt-emit-rtl.h" |