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3cf2715d 1/* Convert RTL to assembler code and output it, for GNU compiler.
3b708058 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
7072a650 3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
17ac08e2 4 Free Software Foundation, Inc.
3cf2715d 5
1322177d 6This file is part of GCC.
3cf2715d 7
1322177d
LB
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
9dcd6f09 10Software Foundation; either version 3, or (at your option) any later
1322177d 11version.
3cf2715d 12
1322177d
LB
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
3cf2715d
DE
17
18You should have received a copy of the GNU General Public License
9dcd6f09
NC
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
3cf2715d 21
3cf2715d
DE
22/* This is the final pass of the compiler.
23 It looks at the rtl code for a function and outputs assembler code.
24
25 Call `final_start_function' to output the assembler code for function entry,
26 `final' to output assembler code for some RTL code,
27 `final_end_function' to output assembler code for function exit.
28 If a function is compiled in several pieces, each piece is
29 output separately with `final'.
30
31 Some optimizations are also done at this level.
32 Move instructions that were made unnecessary by good register allocation
33 are detected and omitted from the output. (Though most of these
34 are removed by the last jump pass.)
35
36 Instructions to set the condition codes are omitted when it can be
37 seen that the condition codes already had the desired values.
38
39 In some cases it is sufficient if the inherited condition codes
40 have related values, but this may require the following insn
41 (the one that tests the condition codes) to be modified.
42
43 The code for the function prologue and epilogue are generated
08c148a8
NB
44 directly in assembler by the target functions function_prologue and
45 function_epilogue. Those instructions never exist as rtl. */
3cf2715d
DE
46
47#include "config.h"
670ee920 48#include "system.h"
4977bab6
ZW
49#include "coretypes.h"
50#include "tm.h"
3cf2715d
DE
51
52#include "tree.h"
53#include "rtl.h"
6baf1cc8 54#include "tm_p.h"
3cf2715d
DE
55#include "regs.h"
56#include "insn-config.h"
3cf2715d 57#include "insn-attr.h"
3cf2715d
DE
58#include "recog.h"
59#include "conditions.h"
60#include "flags.h"
61#include "real.h"
62#include "hard-reg-set.h"
3cf2715d 63#include "output.h"
3d195391 64#include "except.h"
49ad7cfa 65#include "function.h"
10f0ad3d 66#include "toplev.h"
d6f4ec51 67#include "reload.h"
ab87f8c8 68#include "intl.h"
be1bb652 69#include "basic-block.h"
08c148a8 70#include "target.h"
a5a42b92 71#include "debug.h"
49d801d3 72#include "expr.h"
ba4f7968 73#include "cfglayout.h"
ef330312 74#include "tree-pass.h"
55b34b5f 75#include "tree-flow.h"
ef330312
PB
76#include "timevar.h"
77#include "cgraph.h"
78#include "coverage.h"
6fb5fa3c 79#include "df.h"
294340bf 80#include "vecprim.h"
c8aea42c 81#include "ggc.h"
edbed3d3
JH
82#include "cfgloop.h"
83#include "params.h"
3cf2715d 84
440aabf8
NB
85#ifdef XCOFF_DEBUGGING_INFO
86#include "xcoffout.h" /* Needed for external data
87 declarations for e.g. AIX 4.x. */
88#endif
89
76ead72b
RL
90#if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO)
91#include "dwarf2out.h"
92#endif
93
6a08f7b3
DP
94#ifdef DBX_DEBUGGING_INFO
95#include "dbxout.h"
96#endif
97
ce82daed
DB
98#ifdef SDB_DEBUGGING_INFO
99#include "sdbout.h"
100#endif
101
3cf2715d
DE
102/* If we aren't using cc0, CC_STATUS_INIT shouldn't exist. So define a
103 null default for it to save conditionalization later. */
104#ifndef CC_STATUS_INIT
105#define CC_STATUS_INIT
106#endif
107
108/* How to start an assembler comment. */
109#ifndef ASM_COMMENT_START
110#define ASM_COMMENT_START ";#"
111#endif
112
113/* Is the given character a logical line separator for the assembler? */
114#ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
980d8882 115#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
3cf2715d
DE
116#endif
117
75197b37
BS
118#ifndef JUMP_TABLES_IN_TEXT_SECTION
119#define JUMP_TABLES_IN_TEXT_SECTION 0
120#endif
121
589fe865
DJ
122/* Bitflags used by final_scan_insn. */
123#define SEEN_BB 1
124#define SEEN_NOTE 2
125#define SEEN_EMITTED 4
126
3cf2715d 127/* Last insn processed by final_scan_insn. */
b1a9f6a0
RH
128static rtx debug_insn;
129rtx current_output_insn;
3cf2715d
DE
130
131/* Line number of last NOTE. */
132static int last_linenum;
133
6c52e687
CC
134/* Last discriminator written to assembly. */
135static int last_discriminator;
136
137/* Discriminator of current block. */
138static int discriminator;
139
eac40081
RK
140/* Highest line number in current block. */
141static int high_block_linenum;
142
143/* Likewise for function. */
144static int high_function_linenum;
145
3cf2715d 146/* Filename of last NOTE. */
3cce094d 147static const char *last_filename;
3cf2715d 148
d752cfdb
JJ
149/* Override filename and line number. */
150static const char *override_filename;
151static int override_linenum;
152
b8176fe4
EB
153/* Whether to force emission of a line note before the next insn. */
154static bool force_source_line = false;
b0efb46b 155
5f2f0edd 156extern const int length_unit_log; /* This is defined in insn-attrtab.c. */
fc470718 157
3cf2715d 158/* Nonzero while outputting an `asm' with operands.
535a42b1 159 This means that inconsistencies are the user's fault, so don't die.
3cf2715d 160 The precise value is the insn being output, to pass to error_for_asm. */
c8b94768 161rtx this_is_asm_operands;
3cf2715d
DE
162
163/* Number of operands of this insn, for an `asm' with operands. */
22bf4422 164static unsigned int insn_noperands;
3cf2715d
DE
165
166/* Compare optimization flag. */
167
168static rtx last_ignored_compare = 0;
169
3cf2715d
DE
170/* Assign a unique number to each insn that is output.
171 This can be used to generate unique local labels. */
172
173static int insn_counter = 0;
174
175#ifdef HAVE_cc0
176/* This variable contains machine-dependent flags (defined in tm.h)
177 set and examined by output routines
178 that describe how to interpret the condition codes properly. */
179
180CC_STATUS cc_status;
181
182/* During output of an insn, this contains a copy of cc_status
183 from before the insn. */
184
185CC_STATUS cc_prev_status;
186#endif
187
18c038b9 188/* Number of unmatched NOTE_INSN_BLOCK_BEG notes we have seen. */
3cf2715d
DE
189
190static int block_depth;
191
192/* Nonzero if have enabled APP processing of our assembler output. */
193
194static int app_on;
195
196/* If we are outputting an insn sequence, this contains the sequence rtx.
197 Zero otherwise. */
198
199rtx final_sequence;
200
201#ifdef ASSEMBLER_DIALECT
202
203/* Number of the assembler dialect to use, starting at 0. */
204static int dialect_number;
205#endif
206
afe48e06
RH
207#ifdef HAVE_conditional_execution
208/* Nonnull if the insn currently being emitted was a COND_EXEC pattern. */
209rtx current_insn_predicate;
210#endif
211
1d300e19 212#ifdef HAVE_ATTR_length
6cf9ac28
AJ
213static int asm_insn_count (rtx);
214#endif
215static void profile_function (FILE *);
216static void profile_after_prologue (FILE *);
ed5ef2e4 217static bool notice_source_line (rtx, bool *);
6fb5fa3c 218static rtx walk_alter_subreg (rtx *, bool *);
6cf9ac28
AJ
219static void output_asm_name (void);
220static void output_alternate_entry_point (FILE *, rtx);
221static tree get_mem_expr_from_op (rtx, int *);
222static void output_asm_operand_names (rtx *, int *, int);
223static void output_operand (rtx, int);
e9a25f70 224#ifdef LEAF_REGISTERS
6cf9ac28 225static void leaf_renumber_regs (rtx);
e9a25f70
JL
226#endif
227#ifdef HAVE_cc0
6cf9ac28 228static int alter_cond (rtx);
e9a25f70 229#endif
ca3075bd 230#ifndef ADDR_VEC_ALIGN
6cf9ac28 231static int final_addr_vec_align (rtx);
ca3075bd 232#endif
7bdb32b9 233#ifdef HAVE_ATTR_length
6cf9ac28 234static int align_fuzz (rtx, rtx, int, unsigned);
7bdb32b9 235#endif
3cf2715d
DE
236\f
237/* Initialize data in final at the beginning of a compilation. */
238
239void
6cf9ac28 240init_final (const char *filename ATTRIBUTE_UNUSED)
3cf2715d 241{
3cf2715d 242 app_on = 0;
3cf2715d
DE
243 final_sequence = 0;
244
245#ifdef ASSEMBLER_DIALECT
246 dialect_number = ASSEMBLER_DIALECT;
247#endif
248}
249
08c148a8 250/* Default target function prologue and epilogue assembler output.
b9f22704 251
08c148a8
NB
252 If not overridden for epilogue code, then the function body itself
253 contains return instructions wherever needed. */
254void
6cf9ac28
AJ
255default_function_pro_epilogue (FILE *file ATTRIBUTE_UNUSED,
256 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
08c148a8
NB
257{
258}
259
b4c25db2
NB
260/* Default target hook that outputs nothing to a stream. */
261void
6cf9ac28 262no_asm_to_stream (FILE *file ATTRIBUTE_UNUSED)
b4c25db2
NB
263{
264}
265
3cf2715d
DE
266/* Enable APP processing of subsequent output.
267 Used before the output from an `asm' statement. */
268
269void
6cf9ac28 270app_enable (void)
3cf2715d
DE
271{
272 if (! app_on)
273 {
51723711 274 fputs (ASM_APP_ON, asm_out_file);
3cf2715d
DE
275 app_on = 1;
276 }
277}
278
279/* Disable APP processing of subsequent output.
280 Called from varasm.c before most kinds of output. */
281
282void
6cf9ac28 283app_disable (void)
3cf2715d
DE
284{
285 if (app_on)
286 {
51723711 287 fputs (ASM_APP_OFF, asm_out_file);
3cf2715d
DE
288 app_on = 0;
289 }
290}
291\f
f5d927c0 292/* Return the number of slots filled in the current
3cf2715d
DE
293 delayed branch sequence (we don't count the insn needing the
294 delay slot). Zero if not in a delayed branch sequence. */
295
296#ifdef DELAY_SLOTS
297int
6cf9ac28 298dbr_sequence_length (void)
3cf2715d
DE
299{
300 if (final_sequence != 0)
301 return XVECLEN (final_sequence, 0) - 1;
302 else
303 return 0;
304}
305#endif
306\f
307/* The next two pages contain routines used to compute the length of an insn
308 and to shorten branches. */
309
310/* Arrays for insn lengths, and addresses. The latter is referenced by
311 `insn_current_length'. */
312
addd7df6 313static int *insn_lengths;
9d98a694 314
294340bf 315VEC(int,heap) *insn_addresses_;
3cf2715d 316
ea3cbda5
R
317/* Max uid for which the above arrays are valid. */
318static int insn_lengths_max_uid;
319
3cf2715d
DE
320/* Address of insn being processed. Used by `insn_current_length'. */
321int insn_current_address;
322
fc470718
R
323/* Address of insn being processed in previous iteration. */
324int insn_last_address;
325
d6a7951f 326/* known invariant alignment of insn being processed. */
fc470718
R
327int insn_current_align;
328
95707627
R
329/* After shorten_branches, for any insn, uid_align[INSN_UID (insn)]
330 gives the next following alignment insn that increases the known
331 alignment, or NULL_RTX if there is no such insn.
332 For any alignment obtained this way, we can again index uid_align with
333 its uid to obtain the next following align that in turn increases the
334 alignment, till we reach NULL_RTX; the sequence obtained this way
335 for each insn we'll call the alignment chain of this insn in the following
336 comments. */
337
f5d927c0
KH
338struct label_alignment
339{
9e423e6d
JW
340 short alignment;
341 short max_skip;
342};
343
344static rtx *uid_align;
345static int *uid_shuid;
346static struct label_alignment *label_align;
95707627 347
3cf2715d
DE
348/* Indicate that branch shortening hasn't yet been done. */
349
350void
6cf9ac28 351init_insn_lengths (void)
3cf2715d 352{
95707627
R
353 if (uid_shuid)
354 {
355 free (uid_shuid);
356 uid_shuid = 0;
357 }
358 if (insn_lengths)
359 {
360 free (insn_lengths);
361 insn_lengths = 0;
ea3cbda5 362 insn_lengths_max_uid = 0;
95707627 363 }
9d98a694
AO
364#ifdef HAVE_ATTR_length
365 INSN_ADDRESSES_FREE ();
366#endif
95707627
R
367 if (uid_align)
368 {
369 free (uid_align);
370 uid_align = 0;
371 }
3cf2715d
DE
372}
373
374/* Obtain the current length of an insn. If branch shortening has been done,
6fc0bb99 375 get its actual length. Otherwise, use FALLBACK_FN to calculate the
070a7956
R
376 length. */
377static inline int
378get_attr_length_1 (rtx insn ATTRIBUTE_UNUSED,
379 int (*fallback_fn) (rtx) ATTRIBUTE_UNUSED)
3cf2715d
DE
380{
381#ifdef HAVE_ATTR_length
382 rtx body;
383 int i;
384 int length = 0;
385
ea3cbda5 386 if (insn_lengths_max_uid > INSN_UID (insn))
3cf2715d
DE
387 return insn_lengths[INSN_UID (insn)];
388 else
389 switch (GET_CODE (insn))
390 {
391 case NOTE:
392 case BARRIER:
393 case CODE_LABEL:
b5b8b0ac 394 case DEBUG_INSN:
3cf2715d
DE
395 return 0;
396
397 case CALL_INSN:
070a7956 398 length = fallback_fn (insn);
3cf2715d
DE
399 break;
400
401 case JUMP_INSN:
402 body = PATTERN (insn);
dd3f0101 403 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
3cf2715d 404 {
fc470718
R
405 /* Alignment is machine-dependent and should be handled by
406 ADDR_VEC_ALIGN. */
3cf2715d
DE
407 }
408 else
070a7956 409 length = fallback_fn (insn);
3cf2715d
DE
410 break;
411
412 case INSN:
413 body = PATTERN (insn);
414 if (GET_CODE (body) == USE || GET_CODE (body) == CLOBBER)
415 return 0;
416
417 else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0)
070a7956 418 length = asm_insn_count (body) * fallback_fn (insn);
3cf2715d
DE
419 else if (GET_CODE (body) == SEQUENCE)
420 for (i = 0; i < XVECLEN (body, 0); i++)
47d268d0 421 length += get_attr_length_1 (XVECEXP (body, 0, i), fallback_fn);
3cf2715d 422 else
070a7956 423 length = fallback_fn (insn);
e9a25f70
JL
424 break;
425
426 default:
427 break;
3cf2715d
DE
428 }
429
430#ifdef ADJUST_INSN_LENGTH
431 ADJUST_INSN_LENGTH (insn, length);
432#endif
433 return length;
434#else /* not HAVE_ATTR_length */
435 return 0;
a9305dcb
R
436#define insn_default_length 0
437#define insn_min_length 0
3cf2715d
DE
438#endif /* not HAVE_ATTR_length */
439}
070a7956
R
440
441/* Obtain the current length of an insn. If branch shortening has been done,
442 get its actual length. Otherwise, get its maximum length. */
443int
444get_attr_length (rtx insn)
445{
446 return get_attr_length_1 (insn, insn_default_length);
447}
448
449/* Obtain the current length of an insn. If branch shortening has been done,
450 get its actual length. Otherwise, get its minimum length. */
451int
452get_attr_min_length (rtx insn)
453{
454 return get_attr_length_1 (insn, insn_min_length);
455}
3cf2715d 456\f
fc470718
R
457/* Code to handle alignment inside shorten_branches. */
458
459/* Here is an explanation how the algorithm in align_fuzz can give
460 proper results:
461
462 Call a sequence of instructions beginning with alignment point X
463 and continuing until the next alignment point `block X'. When `X'
f5d927c0 464 is used in an expression, it means the alignment value of the
fc470718 465 alignment point.
f5d927c0 466
fc470718
R
467 Call the distance between the start of the first insn of block X, and
468 the end of the last insn of block X `IX', for the `inner size of X'.
469 This is clearly the sum of the instruction lengths.
f5d927c0 470
fc470718
R
471 Likewise with the next alignment-delimited block following X, which we
472 shall call block Y.
f5d927c0 473
fc470718
R
474 Call the distance between the start of the first insn of block X, and
475 the start of the first insn of block Y `OX', for the `outer size of X'.
f5d927c0 476
fc470718 477 The estimated padding is then OX - IX.
f5d927c0 478
fc470718 479 OX can be safely estimated as
f5d927c0 480
fc470718
R
481 if (X >= Y)
482 OX = round_up(IX, Y)
483 else
484 OX = round_up(IX, X) + Y - X
f5d927c0 485
fc470718
R
486 Clearly est(IX) >= real(IX), because that only depends on the
487 instruction lengths, and those being overestimated is a given.
f5d927c0 488
fc470718
R
489 Clearly round_up(foo, Z) >= round_up(bar, Z) if foo >= bar, so
490 we needn't worry about that when thinking about OX.
f5d927c0 491
fc470718
R
492 When X >= Y, the alignment provided by Y adds no uncertainty factor
493 for branch ranges starting before X, so we can just round what we have.
494 But when X < Y, we don't know anything about the, so to speak,
495 `middle bits', so we have to assume the worst when aligning up from an
496 address mod X to one mod Y, which is Y - X. */
497
498#ifndef LABEL_ALIGN
efa3896a 499#define LABEL_ALIGN(LABEL) align_labels_log
fc470718
R
500#endif
501
9e423e6d 502#ifndef LABEL_ALIGN_MAX_SKIP
2cca7283 503#define LABEL_ALIGN_MAX_SKIP align_labels_max_skip
9e423e6d
JW
504#endif
505
fc470718 506#ifndef LOOP_ALIGN
efa3896a 507#define LOOP_ALIGN(LABEL) align_loops_log
fc470718
R
508#endif
509
9e423e6d 510#ifndef LOOP_ALIGN_MAX_SKIP
2cca7283 511#define LOOP_ALIGN_MAX_SKIP align_loops_max_skip
9e423e6d
JW
512#endif
513
fc470718 514#ifndef LABEL_ALIGN_AFTER_BARRIER
340f7e7c 515#define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0
fc470718
R
516#endif
517
9e423e6d 518#ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
247a370b
JH
519#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0
520#endif
521
522#ifndef JUMP_ALIGN
523#define JUMP_ALIGN(LABEL) align_jumps_log
524#endif
525
526#ifndef JUMP_ALIGN_MAX_SKIP
2cca7283 527#define JUMP_ALIGN_MAX_SKIP align_jumps_max_skip
9e423e6d
JW
528#endif
529
fc470718 530#ifndef ADDR_VEC_ALIGN
ca3075bd 531static int
6cf9ac28 532final_addr_vec_align (rtx addr_vec)
fc470718 533{
2a841588 534 int align = GET_MODE_SIZE (GET_MODE (PATTERN (addr_vec)));
fc470718
R
535
536 if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT)
537 align = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
2a841588 538 return exact_log2 (align);
fc470718
R
539
540}
f5d927c0 541
fc470718
R
542#define ADDR_VEC_ALIGN(ADDR_VEC) final_addr_vec_align (ADDR_VEC)
543#endif
544
545#ifndef INSN_LENGTH_ALIGNMENT
546#define INSN_LENGTH_ALIGNMENT(INSN) length_unit_log
547#endif
548
fc470718
R
549#define INSN_SHUID(INSN) (uid_shuid[INSN_UID (INSN)])
550
de7987a6 551static int min_labelno, max_labelno;
fc470718
R
552
553#define LABEL_TO_ALIGNMENT(LABEL) \
9e423e6d
JW
554 (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].alignment)
555
556#define LABEL_TO_MAX_SKIP(LABEL) \
557 (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].max_skip)
fc470718
R
558
559/* For the benefit of port specific code do this also as a function. */
f5d927c0 560
fc470718 561int
6cf9ac28 562label_to_alignment (rtx label)
fc470718 563{
40a8f07a
JJ
564 if (CODE_LABEL_NUMBER (label) <= max_labelno)
565 return LABEL_TO_ALIGNMENT (label);
566 return 0;
567}
568
569int
570label_to_max_skip (rtx label)
571{
572 if (CODE_LABEL_NUMBER (label) <= max_labelno)
573 return LABEL_TO_MAX_SKIP (label);
574 return 0;
fc470718
R
575}
576
577#ifdef HAVE_ATTR_length
578/* The differences in addresses
579 between a branch and its target might grow or shrink depending on
580 the alignment the start insn of the range (the branch for a forward
581 branch or the label for a backward branch) starts out on; if these
582 differences are used naively, they can even oscillate infinitely.
583 We therefore want to compute a 'worst case' address difference that
584 is independent of the alignment the start insn of the range end
585 up on, and that is at least as large as the actual difference.
586 The function align_fuzz calculates the amount we have to add to the
587 naively computed difference, by traversing the part of the alignment
588 chain of the start insn of the range that is in front of the end insn
589 of the range, and considering for each alignment the maximum amount
590 that it might contribute to a size increase.
591
592 For casesi tables, we also want to know worst case minimum amounts of
593 address difference, in case a machine description wants to introduce
594 some common offset that is added to all offsets in a table.
d6a7951f 595 For this purpose, align_fuzz with a growth argument of 0 computes the
fc470718
R
596 appropriate adjustment. */
597
fc470718
R
598/* Compute the maximum delta by which the difference of the addresses of
599 START and END might grow / shrink due to a different address for start
600 which changes the size of alignment insns between START and END.
601 KNOWN_ALIGN_LOG is the alignment known for START.
602 GROWTH should be ~0 if the objective is to compute potential code size
603 increase, and 0 if the objective is to compute potential shrink.
604 The return value is undefined for any other value of GROWTH. */
f5d927c0 605
ca3075bd 606static int
6cf9ac28 607align_fuzz (rtx start, rtx end, int known_align_log, unsigned int growth)
fc470718
R
608{
609 int uid = INSN_UID (start);
610 rtx align_label;
611 int known_align = 1 << known_align_log;
612 int end_shuid = INSN_SHUID (end);
613 int fuzz = 0;
614
615 for (align_label = uid_align[uid]; align_label; align_label = uid_align[uid])
616 {
617 int align_addr, new_align;
618
619 uid = INSN_UID (align_label);
9d98a694 620 align_addr = INSN_ADDRESSES (uid) - insn_lengths[uid];
fc470718
R
621 if (uid_shuid[uid] > end_shuid)
622 break;
623 known_align_log = LABEL_TO_ALIGNMENT (align_label);
624 new_align = 1 << known_align_log;
625 if (new_align < known_align)
626 continue;
627 fuzz += (-align_addr ^ growth) & (new_align - known_align);
628 known_align = new_align;
629 }
630 return fuzz;
631}
632
633/* Compute a worst-case reference address of a branch so that it
634 can be safely used in the presence of aligned labels. Since the
635 size of the branch itself is unknown, the size of the branch is
636 not included in the range. I.e. for a forward branch, the reference
637 address is the end address of the branch as known from the previous
638 branch shortening pass, minus a value to account for possible size
639 increase due to alignment. For a backward branch, it is the start
640 address of the branch as known from the current pass, plus a value
641 to account for possible size increase due to alignment.
642 NB.: Therefore, the maximum offset allowed for backward branches needs
643 to exclude the branch size. */
f5d927c0 644
fc470718 645int
6cf9ac28 646insn_current_reference_address (rtx branch)
fc470718 647{
5527bf14
RH
648 rtx dest, seq;
649 int seq_uid;
650
651 if (! INSN_ADDRESSES_SET_P ())
652 return 0;
653
654 seq = NEXT_INSN (PREV_INSN (branch));
655 seq_uid = INSN_UID (seq);
4b4bf941 656 if (!JUMP_P (branch))
fc470718
R
657 /* This can happen for example on the PA; the objective is to know the
658 offset to address something in front of the start of the function.
659 Thus, we can treat it like a backward branch.
660 We assume here that FUNCTION_BOUNDARY / BITS_PER_UNIT is larger than
661 any alignment we'd encounter, so we skip the call to align_fuzz. */
662 return insn_current_address;
663 dest = JUMP_LABEL (branch);
5527bf14 664
b9f22704 665 /* BRANCH has no proper alignment chain set, so use SEQ.
afc6898e
BS
666 BRANCH also has no INSN_SHUID. */
667 if (INSN_SHUID (seq) < INSN_SHUID (dest))
fc470718 668 {
f5d927c0 669 /* Forward branch. */
fc470718 670 return (insn_last_address + insn_lengths[seq_uid]
26024475 671 - align_fuzz (seq, dest, length_unit_log, ~0));
fc470718
R
672 }
673 else
674 {
f5d927c0 675 /* Backward branch. */
fc470718 676 return (insn_current_address
923f7cf9 677 + align_fuzz (dest, seq, length_unit_log, ~0));
fc470718
R
678 }
679}
680#endif /* HAVE_ATTR_length */
681\f
65727068
KH
682/* Compute branch alignments based on frequency information in the
683 CFG. */
684
e855c69d 685unsigned int
6cf9ac28 686compute_alignments (void)
247a370b 687{
247a370b 688 int log, max_skip, max_log;
e0082a72 689 basic_block bb;
edbed3d3
JH
690 int freq_max = 0;
691 int freq_threshold = 0;
247a370b
JH
692
693 if (label_align)
694 {
695 free (label_align);
696 label_align = 0;
697 }
698
699 max_labelno = max_label_num ();
700 min_labelno = get_first_label_num ();
5ed6ace5 701 label_align = XCNEWVEC (struct label_alignment, max_labelno - min_labelno + 1);
247a370b
JH
702
703 /* If not optimizing or optimizing for size, don't assign any alignments. */
efd8f750 704 if (! optimize || optimize_function_for_size_p (cfun))
c2924966 705 return 0;
247a370b 706
edbed3d3
JH
707 if (dump_file)
708 {
709 dump_flow_info (dump_file, TDF_DETAILS);
710 flow_loops_dump (dump_file, NULL, 1);
711 loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
712 }
713 FOR_EACH_BB (bb)
714 if (bb->frequency > freq_max)
715 freq_max = bb->frequency;
716 freq_threshold = freq_max / PARAM_VALUE (PARAM_ALIGN_THRESHOLD);
717
718 if (dump_file)
719 fprintf(dump_file, "freq_max: %i\n",freq_max);
e0082a72 720 FOR_EACH_BB (bb)
247a370b 721 {
a813c111 722 rtx label = BB_HEAD (bb);
247a370b
JH
723 int fallthru_frequency = 0, branch_frequency = 0, has_fallthru = 0;
724 edge e;
628f6a4e 725 edge_iterator ei;
247a370b 726
4b4bf941 727 if (!LABEL_P (label)
8bcf15f6 728 || optimize_bb_for_size_p (bb))
edbed3d3
JH
729 {
730 if (dump_file)
731 fprintf(dump_file, "BB %4i freq %4i loop %2i loop_depth %2i skipped.\n",
732 bb->index, bb->frequency, bb->loop_father->num, bb->loop_depth);
733 continue;
734 }
247a370b
JH
735 max_log = LABEL_ALIGN (label);
736 max_skip = LABEL_ALIGN_MAX_SKIP;
737
628f6a4e 738 FOR_EACH_EDGE (e, ei, bb->preds)
247a370b
JH
739 {
740 if (e->flags & EDGE_FALLTHRU)
741 has_fallthru = 1, fallthru_frequency += EDGE_FREQUENCY (e);
742 else
743 branch_frequency += EDGE_FREQUENCY (e);
744 }
edbed3d3
JH
745 if (dump_file)
746 {
747 fprintf(dump_file, "BB %4i freq %4i loop %2i loop_depth %2i fall %4i branch %4i",
748 bb->index, bb->frequency, bb->loop_father->num,
749 bb->loop_depth,
750 fallthru_frequency, branch_frequency);
751 if (!bb->loop_father->inner && bb->loop_father->num)
752 fprintf (dump_file, " inner_loop");
753 if (bb->loop_father->header == bb)
754 fprintf (dump_file, " loop_header");
755 fprintf (dump_file, "\n");
756 }
247a370b 757
f63d1bf7 758 /* There are two purposes to align block with no fallthru incoming edge:
247a370b 759 1) to avoid fetch stalls when branch destination is near cache boundary
d6a7951f 760 2) to improve cache efficiency in case the previous block is not executed
247a370b
JH
761 (so it does not need to be in the cache).
762
763 We to catch first case, we align frequently executed blocks.
764 To catch the second, we align blocks that are executed more frequently
eaec9b3d 765 than the predecessor and the predecessor is likely to not be executed
247a370b
JH
766 when function is called. */
767
768 if (!has_fallthru
edbed3d3 769 && (branch_frequency > freq_threshold
f6366fc7
ZD
770 || (bb->frequency > bb->prev_bb->frequency * 10
771 && (bb->prev_bb->frequency
247a370b
JH
772 <= ENTRY_BLOCK_PTR->frequency / 2))))
773 {
774 log = JUMP_ALIGN (label);
edbed3d3
JH
775 if (dump_file)
776 fprintf(dump_file, " jump alignment added.\n");
247a370b
JH
777 if (max_log < log)
778 {
779 max_log = log;
780 max_skip = JUMP_ALIGN_MAX_SKIP;
781 }
782 }
783 /* In case block is frequent and reached mostly by non-fallthru edge,
09da1532 784 align it. It is most likely a first block of loop. */
247a370b 785 if (has_fallthru
efd8f750 786 && optimize_bb_for_speed_p (bb)
edbed3d3
JH
787 && branch_frequency + fallthru_frequency > freq_threshold
788 && (branch_frequency
789 > fallthru_frequency * PARAM_VALUE (PARAM_ALIGN_LOOP_ITERATIONS)))
247a370b
JH
790 {
791 log = LOOP_ALIGN (label);
edbed3d3
JH
792 if (dump_file)
793 fprintf(dump_file, " internal loop alignment added.\n");
247a370b
JH
794 if (max_log < log)
795 {
796 max_log = log;
797 max_skip = LOOP_ALIGN_MAX_SKIP;
798 }
799 }
800 LABEL_TO_ALIGNMENT (label) = max_log;
801 LABEL_TO_MAX_SKIP (label) = max_skip;
802 }
edbed3d3
JH
803
804 if (dump_file)
e855c69d
AB
805 {
806 loop_optimizer_finalize ();
807 free_dominance_info (CDI_DOMINATORS);
808 }
c2924966 809 return 0;
247a370b 810}
ef330312 811
8ddbbcae 812struct rtl_opt_pass pass_compute_alignments =
ef330312 813{
8ddbbcae
JH
814 {
815 RTL_PASS,
edbed3d3 816 "alignments", /* name */
ef330312
PB
817 NULL, /* gate */
818 compute_alignments, /* execute */
819 NULL, /* sub */
820 NULL, /* next */
821 0, /* static_pass_number */
7072a650 822 TV_NONE, /* tv_id */
ef330312
PB
823 0, /* properties_required */
824 0, /* properties_provided */
825 0, /* properties_destroyed */
826 0, /* todo_flags_start */
edbed3d3 827 TODO_dump_func | TODO_verify_rtl_sharing
8ddbbcae
JH
828 | TODO_ggc_collect /* todo_flags_finish */
829 }
ef330312
PB
830};
831
247a370b 832\f
3cf2715d
DE
833/* Make a pass over all insns and compute their actual lengths by shortening
834 any branches of variable length if possible. */
835
fc470718
R
836/* shorten_branches might be called multiple times: for example, the SH
837 port splits out-of-range conditional branches in MACHINE_DEPENDENT_REORG.
838 In order to do this, it needs proper length information, which it obtains
839 by calling shorten_branches. This cannot be collapsed with
d6a7951f 840 shorten_branches itself into a single pass unless we also want to integrate
fc470718
R
841 reorg.c, since the branch splitting exposes new instructions with delay
842 slots. */
843
3cf2715d 844void
6cf9ac28 845shorten_branches (rtx first ATTRIBUTE_UNUSED)
3cf2715d 846{
3cf2715d 847 rtx insn;
fc470718
R
848 int max_uid;
849 int i;
fc470718 850 int max_log;
9e423e6d 851 int max_skip;
fc470718
R
852#ifdef HAVE_ATTR_length
853#define MAX_CODE_ALIGN 16
854 rtx seq;
3cf2715d 855 int something_changed = 1;
3cf2715d
DE
856 char *varying_length;
857 rtx body;
858 int uid;
fc470718 859 rtx align_tab[MAX_CODE_ALIGN];
3cf2715d 860
fc470718 861#endif
3d14e82f 862
3446405d
JH
863 /* Compute maximum UID and allocate label_align / uid_shuid. */
864 max_uid = get_max_uid ();
d9b6874b 865
471854f8 866 /* Free uid_shuid before reallocating it. */
07a1f795 867 free (uid_shuid);
b0efb46b 868
5ed6ace5 869 uid_shuid = XNEWVEC (int, max_uid);
25e22dc0 870
247a370b
JH
871 if (max_labelno != max_label_num ())
872 {
873 int old = max_labelno;
874 int n_labels;
875 int n_old_labels;
876
877 max_labelno = max_label_num ();
878
879 n_labels = max_labelno - min_labelno + 1;
880 n_old_labels = old - min_labelno + 1;
881
1b4572a8 882 label_align = XRESIZEVEC (struct label_alignment, label_align, n_labels);
247a370b 883
535a42b1 884 /* Range of labels grows monotonically in the function. Failing here
247a370b 885 means that the initialization of array got lost. */
0bccc606 886 gcc_assert (n_old_labels <= n_labels);
247a370b
JH
887
888 memset (label_align + n_old_labels, 0,
889 (n_labels - n_old_labels) * sizeof (struct label_alignment));
890 }
891
fc470718
R
892 /* Initialize label_align and set up uid_shuid to be strictly
893 monotonically rising with insn order. */
e2faec75
R
894 /* We use max_log here to keep track of the maximum alignment we want to
895 impose on the next CODE_LABEL (or the current one if we are processing
896 the CODE_LABEL itself). */
f5d927c0 897
9e423e6d
JW
898 max_log = 0;
899 max_skip = 0;
900
901 for (insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn))
fc470718
R
902 {
903 int log;
904
905 INSN_SHUID (insn) = i++;
2c3c49de 906 if (INSN_P (insn))
80838531 907 continue;
b0efb46b 908
80838531 909 if (LABEL_P (insn))
fc470718
R
910 {
911 rtx next;
0676c393 912 bool next_is_jumptable;
ff81832f 913
247a370b
JH
914 /* Merge in alignments computed by compute_alignments. */
915 log = LABEL_TO_ALIGNMENT (insn);
916 if (max_log < log)
917 {
918 max_log = log;
919 max_skip = LABEL_TO_MAX_SKIP (insn);
920 }
fc470718 921
0676c393
MM
922 next = next_nonnote_insn (insn);
923 next_is_jumptable = next && JUMP_TABLE_DATA_P (next);
924 if (!next_is_jumptable)
9e423e6d 925 {
0676c393
MM
926 log = LABEL_ALIGN (insn);
927 if (max_log < log)
928 {
929 max_log = log;
930 max_skip = LABEL_ALIGN_MAX_SKIP;
931 }
9e423e6d 932 }
75197b37
BS
933 /* ADDR_VECs only take room if read-only data goes into the text
934 section. */
0676c393
MM
935 if ((JUMP_TABLES_IN_TEXT_SECTION
936 || readonly_data_section == text_section)
937 && next_is_jumptable)
938 {
939 log = ADDR_VEC_ALIGN (next);
940 if (max_log < log)
941 {
942 max_log = log;
943 max_skip = LABEL_ALIGN_MAX_SKIP;
944 }
945 }
fc470718 946 LABEL_TO_ALIGNMENT (insn) = max_log;
9e423e6d 947 LABEL_TO_MAX_SKIP (insn) = max_skip;
fc470718 948 max_log = 0;
9e423e6d 949 max_skip = 0;
fc470718 950 }
4b4bf941 951 else if (BARRIER_P (insn))
fc470718
R
952 {
953 rtx label;
954
2c3c49de 955 for (label = insn; label && ! INSN_P (label);
fc470718 956 label = NEXT_INSN (label))
4b4bf941 957 if (LABEL_P (label))
fc470718
R
958 {
959 log = LABEL_ALIGN_AFTER_BARRIER (insn);
960 if (max_log < log)
9e423e6d
JW
961 {
962 max_log = log;
963 max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP;
964 }
fc470718
R
965 break;
966 }
967 }
fc470718
R
968 }
969#ifdef HAVE_ATTR_length
970
971 /* Allocate the rest of the arrays. */
5ed6ace5 972 insn_lengths = XNEWVEC (int, max_uid);
ea3cbda5 973 insn_lengths_max_uid = max_uid;
af035616
R
974 /* Syntax errors can lead to labels being outside of the main insn stream.
975 Initialize insn_addresses, so that we get reproducible results. */
9d98a694 976 INSN_ADDRESSES_ALLOC (max_uid);
fc470718 977
5ed6ace5 978 varying_length = XCNEWVEC (char, max_uid);
fc470718
R
979
980 /* Initialize uid_align. We scan instructions
981 from end to start, and keep in align_tab[n] the last seen insn
982 that does an alignment of at least n+1, i.e. the successor
983 in the alignment chain for an insn that does / has a known
984 alignment of n. */
5ed6ace5 985 uid_align = XCNEWVEC (rtx, max_uid);
fc470718 986
f5d927c0 987 for (i = MAX_CODE_ALIGN; --i >= 0;)
fc470718
R
988 align_tab[i] = NULL_RTX;
989 seq = get_last_insn ();
33f7f353 990 for (; seq; seq = PREV_INSN (seq))
fc470718
R
991 {
992 int uid = INSN_UID (seq);
993 int log;
4b4bf941 994 log = (LABEL_P (seq) ? LABEL_TO_ALIGNMENT (seq) : 0);
fc470718 995 uid_align[uid] = align_tab[0];
fc470718
R
996 if (log)
997 {
998 /* Found an alignment label. */
999 uid_align[uid] = align_tab[log];
1000 for (i = log - 1; i >= 0; i--)
1001 align_tab[i] = seq;
1002 }
33f7f353
JR
1003 }
1004#ifdef CASE_VECTOR_SHORTEN_MODE
1005 if (optimize)
1006 {
1007 /* Look for ADDR_DIFF_VECs, and initialize their minimum and maximum
1008 label fields. */
1009
1010 int min_shuid = INSN_SHUID (get_insns ()) - 1;
1011 int max_shuid = INSN_SHUID (get_last_insn ()) + 1;
1012 int rel;
1013
1014 for (insn = first; insn != 0; insn = NEXT_INSN (insn))
fc470718 1015 {
33f7f353
JR
1016 rtx min_lab = NULL_RTX, max_lab = NULL_RTX, pat;
1017 int len, i, min, max, insn_shuid;
1018 int min_align;
1019 addr_diff_vec_flags flags;
1020
4b4bf941 1021 if (!JUMP_P (insn)
33f7f353
JR
1022 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
1023 continue;
1024 pat = PATTERN (insn);
1025 len = XVECLEN (pat, 1);
0bccc606 1026 gcc_assert (len > 0);
33f7f353
JR
1027 min_align = MAX_CODE_ALIGN;
1028 for (min = max_shuid, max = min_shuid, i = len - 1; i >= 0; i--)
1029 {
1030 rtx lab = XEXP (XVECEXP (pat, 1, i), 0);
1031 int shuid = INSN_SHUID (lab);
1032 if (shuid < min)
1033 {
1034 min = shuid;
1035 min_lab = lab;
1036 }
1037 if (shuid > max)
1038 {
1039 max = shuid;
1040 max_lab = lab;
1041 }
1042 if (min_align > LABEL_TO_ALIGNMENT (lab))
1043 min_align = LABEL_TO_ALIGNMENT (lab);
1044 }
4c33cb26
R
1045 XEXP (pat, 2) = gen_rtx_LABEL_REF (Pmode, min_lab);
1046 XEXP (pat, 3) = gen_rtx_LABEL_REF (Pmode, max_lab);
33f7f353
JR
1047 insn_shuid = INSN_SHUID (insn);
1048 rel = INSN_SHUID (XEXP (XEXP (pat, 0), 0));
5921f276 1049 memset (&flags, 0, sizeof (flags));
33f7f353
JR
1050 flags.min_align = min_align;
1051 flags.base_after_vec = rel > insn_shuid;
1052 flags.min_after_vec = min > insn_shuid;
1053 flags.max_after_vec = max > insn_shuid;
1054 flags.min_after_base = min > rel;
1055 flags.max_after_base = max > rel;
1056 ADDR_DIFF_VEC_FLAGS (pat) = flags;
fc470718
R
1057 }
1058 }
33f7f353 1059#endif /* CASE_VECTOR_SHORTEN_MODE */
3cf2715d 1060
3cf2715d 1061 /* Compute initial lengths, addresses, and varying flags for each insn. */
b816f339 1062 for (insn_current_address = 0, insn = first;
3cf2715d
DE
1063 insn != 0;
1064 insn_current_address += insn_lengths[uid], insn = NEXT_INSN (insn))
1065 {
1066 uid = INSN_UID (insn);
fc470718 1067
3cf2715d 1068 insn_lengths[uid] = 0;
fc470718 1069
4b4bf941 1070 if (LABEL_P (insn))
fc470718
R
1071 {
1072 int log = LABEL_TO_ALIGNMENT (insn);
1073 if (log)
1074 {
1075 int align = 1 << log;
ecb06768 1076 int new_address = (insn_current_address + align - 1) & -align;
fc470718 1077 insn_lengths[uid] = new_address - insn_current_address;
fc470718
R
1078 }
1079 }
1080
5a09edba 1081 INSN_ADDRESSES (uid) = insn_current_address + insn_lengths[uid];
f5d927c0 1082
4b4bf941 1083 if (NOTE_P (insn) || BARRIER_P (insn)
f90f4827 1084 || LABEL_P (insn) || DEBUG_INSN_P(insn))
3cf2715d 1085 continue;
04da53bd
R
1086 if (INSN_DELETED_P (insn))
1087 continue;
3cf2715d
DE
1088
1089 body = PATTERN (insn);
1090 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
5a32a90c
JR
1091 {
1092 /* This only takes room if read-only data goes into the text
1093 section. */
d6b5193b
RS
1094 if (JUMP_TABLES_IN_TEXT_SECTION
1095 || readonly_data_section == text_section)
75197b37
BS
1096 insn_lengths[uid] = (XVECLEN (body,
1097 GET_CODE (body) == ADDR_DIFF_VEC)
1098 * GET_MODE_SIZE (GET_MODE (body)));
5a32a90c 1099 /* Alignment is handled by ADDR_VEC_ALIGN. */
5a32a90c 1100 }
a30caf5c 1101 else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0)
3cf2715d
DE
1102 insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn);
1103 else if (GET_CODE (body) == SEQUENCE)
1104 {
1105 int i;
1106 int const_delay_slots;
1107#ifdef DELAY_SLOTS
1108 const_delay_slots = const_num_delay_slots (XVECEXP (body, 0, 0));
1109#else
1110 const_delay_slots = 0;
1111#endif
1112 /* Inside a delay slot sequence, we do not do any branch shortening
1113 if the shortening could change the number of delay slots
0f41302f 1114 of the branch. */
3cf2715d
DE
1115 for (i = 0; i < XVECLEN (body, 0); i++)
1116 {
1117 rtx inner_insn = XVECEXP (body, 0, i);
1118 int inner_uid = INSN_UID (inner_insn);
1119 int inner_length;
1120
a30caf5c
DC
1121 if (GET_CODE (body) == ASM_INPUT
1122 || asm_noperands (PATTERN (XVECEXP (body, 0, i))) >= 0)
3cf2715d
DE
1123 inner_length = (asm_insn_count (PATTERN (inner_insn))
1124 * insn_default_length (inner_insn));
1125 else
1126 inner_length = insn_default_length (inner_insn);
f5d927c0 1127
3cf2715d
DE
1128 insn_lengths[inner_uid] = inner_length;
1129 if (const_delay_slots)
1130 {
1131 if ((varying_length[inner_uid]
1132 = insn_variable_length_p (inner_insn)) != 0)
1133 varying_length[uid] = 1;
9d98a694
AO
1134 INSN_ADDRESSES (inner_uid) = (insn_current_address
1135 + insn_lengths[uid]);
3cf2715d
DE
1136 }
1137 else
1138 varying_length[inner_uid] = 0;
1139 insn_lengths[uid] += inner_length;
1140 }
1141 }
1142 else if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER)
1143 {
1144 insn_lengths[uid] = insn_default_length (insn);
1145 varying_length[uid] = insn_variable_length_p (insn);
1146 }
1147
1148 /* If needed, do any adjustment. */
1149#ifdef ADJUST_INSN_LENGTH
1150 ADJUST_INSN_LENGTH (insn, insn_lengths[uid]);
04b6000c 1151 if (insn_lengths[uid] < 0)
c725bd79 1152 fatal_insn ("negative insn length", insn);
3cf2715d
DE
1153#endif
1154 }
1155
1156 /* Now loop over all the insns finding varying length insns. For each,
1157 get the current insn length. If it has changed, reflect the change.
1158 When nothing changes for a full pass, we are done. */
1159
1160 while (something_changed)
1161 {
1162 something_changed = 0;
fc470718 1163 insn_current_align = MAX_CODE_ALIGN - 1;
b816f339 1164 for (insn_current_address = 0, insn = first;
3cf2715d
DE
1165 insn != 0;
1166 insn = NEXT_INSN (insn))
1167 {
1168 int new_length;
b729186a 1169#ifdef ADJUST_INSN_LENGTH
3cf2715d 1170 int tmp_length;
b729186a 1171#endif
fc470718 1172 int length_align;
3cf2715d
DE
1173
1174 uid = INSN_UID (insn);
fc470718 1175
4b4bf941 1176 if (LABEL_P (insn))
fc470718
R
1177 {
1178 int log = LABEL_TO_ALIGNMENT (insn);
1179 if (log > insn_current_align)
1180 {
1181 int align = 1 << log;
ecb06768 1182 int new_address= (insn_current_address + align - 1) & -align;
fc470718
R
1183 insn_lengths[uid] = new_address - insn_current_address;
1184 insn_current_align = log;
1185 insn_current_address = new_address;
1186 }
1187 else
1188 insn_lengths[uid] = 0;
9d98a694 1189 INSN_ADDRESSES (uid) = insn_current_address;
fc470718
R
1190 continue;
1191 }
1192
1193 length_align = INSN_LENGTH_ALIGNMENT (insn);
1194 if (length_align < insn_current_align)
1195 insn_current_align = length_align;
1196
9d98a694
AO
1197 insn_last_address = INSN_ADDRESSES (uid);
1198 INSN_ADDRESSES (uid) = insn_current_address;
fc470718 1199
5e75ef4a 1200#ifdef CASE_VECTOR_SHORTEN_MODE
4b4bf941 1201 if (optimize && JUMP_P (insn)
33f7f353
JR
1202 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
1203 {
33f7f353
JR
1204 rtx body = PATTERN (insn);
1205 int old_length = insn_lengths[uid];
1206 rtx rel_lab = XEXP (XEXP (body, 0), 0);
1207 rtx min_lab = XEXP (XEXP (body, 2), 0);
1208 rtx max_lab = XEXP (XEXP (body, 3), 0);
9d98a694
AO
1209 int rel_addr = INSN_ADDRESSES (INSN_UID (rel_lab));
1210 int min_addr = INSN_ADDRESSES (INSN_UID (min_lab));
1211 int max_addr = INSN_ADDRESSES (INSN_UID (max_lab));
33f7f353
JR
1212 rtx prev;
1213 int rel_align = 0;
950a3816
KG
1214 addr_diff_vec_flags flags;
1215
1216 /* Avoid automatic aggregate initialization. */
1217 flags = ADDR_DIFF_VEC_FLAGS (body);
33f7f353
JR
1218
1219 /* Try to find a known alignment for rel_lab. */
1220 for (prev = rel_lab;
1221 prev
1222 && ! insn_lengths[INSN_UID (prev)]
1223 && ! (varying_length[INSN_UID (prev)] & 1);
1224 prev = PREV_INSN (prev))
1225 if (varying_length[INSN_UID (prev)] & 2)
1226 {
1227 rel_align = LABEL_TO_ALIGNMENT (prev);
1228 break;
1229 }
1230
1231 /* See the comment on addr_diff_vec_flags in rtl.h for the
1232 meaning of the flags values. base: REL_LAB vec: INSN */
1233 /* Anything after INSN has still addresses from the last
1234 pass; adjust these so that they reflect our current
1235 estimate for this pass. */
1236 if (flags.base_after_vec)
1237 rel_addr += insn_current_address - insn_last_address;
1238 if (flags.min_after_vec)
1239 min_addr += insn_current_address - insn_last_address;
1240 if (flags.max_after_vec)
1241 max_addr += insn_current_address - insn_last_address;
1242 /* We want to know the worst case, i.e. lowest possible value
1243 for the offset of MIN_LAB. If MIN_LAB is after REL_LAB,
1244 its offset is positive, and we have to be wary of code shrink;
1245 otherwise, it is negative, and we have to be vary of code
1246 size increase. */
1247 if (flags.min_after_base)
1248 {
1249 /* If INSN is between REL_LAB and MIN_LAB, the size
1250 changes we are about to make can change the alignment
1251 within the observed offset, therefore we have to break
1252 it up into two parts that are independent. */
1253 if (! flags.base_after_vec && flags.min_after_vec)
1254 {
1255 min_addr -= align_fuzz (rel_lab, insn, rel_align, 0);
1256 min_addr -= align_fuzz (insn, min_lab, 0, 0);
1257 }
1258 else
1259 min_addr -= align_fuzz (rel_lab, min_lab, rel_align, 0);
1260 }
1261 else
1262 {
1263 if (flags.base_after_vec && ! flags.min_after_vec)
1264 {
1265 min_addr -= align_fuzz (min_lab, insn, 0, ~0);
1266 min_addr -= align_fuzz (insn, rel_lab, 0, ~0);
1267 }
1268 else
1269 min_addr -= align_fuzz (min_lab, rel_lab, 0, ~0);
1270 }
1271 /* Likewise, determine the highest lowest possible value
1272 for the offset of MAX_LAB. */
1273 if (flags.max_after_base)
1274 {
1275 if (! flags.base_after_vec && flags.max_after_vec)
1276 {
1277 max_addr += align_fuzz (rel_lab, insn, rel_align, ~0);
1278 max_addr += align_fuzz (insn, max_lab, 0, ~0);
1279 }
1280 else
1281 max_addr += align_fuzz (rel_lab, max_lab, rel_align, ~0);
1282 }
1283 else
1284 {
1285 if (flags.base_after_vec && ! flags.max_after_vec)
1286 {
1287 max_addr += align_fuzz (max_lab, insn, 0, 0);
1288 max_addr += align_fuzz (insn, rel_lab, 0, 0);
1289 }
1290 else
1291 max_addr += align_fuzz (max_lab, rel_lab, 0, 0);
1292 }
1293 PUT_MODE (body, CASE_VECTOR_SHORTEN_MODE (min_addr - rel_addr,
1294 max_addr - rel_addr,
1295 body));
d6b5193b
RS
1296 if (JUMP_TABLES_IN_TEXT_SECTION
1297 || readonly_data_section == text_section)
75197b37
BS
1298 {
1299 insn_lengths[uid]
1300 = (XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)));
1301 insn_current_address += insn_lengths[uid];
1302 if (insn_lengths[uid] != old_length)
1303 something_changed = 1;
1304 }
1305
33f7f353 1306 continue;
33f7f353 1307 }
5e75ef4a
JL
1308#endif /* CASE_VECTOR_SHORTEN_MODE */
1309
1310 if (! (varying_length[uid]))
3cf2715d 1311 {
4b4bf941 1312 if (NONJUMP_INSN_P (insn)
674fc07d
GS
1313 && GET_CODE (PATTERN (insn)) == SEQUENCE)
1314 {
1315 int i;
1316
1317 body = PATTERN (insn);
1318 for (i = 0; i < XVECLEN (body, 0); i++)
1319 {
1320 rtx inner_insn = XVECEXP (body, 0, i);
1321 int inner_uid = INSN_UID (inner_insn);
1322
1323 INSN_ADDRESSES (inner_uid) = insn_current_address;
1324
1325 insn_current_address += insn_lengths[inner_uid];
1326 }
dd3f0101 1327 }
674fc07d
GS
1328 else
1329 insn_current_address += insn_lengths[uid];
1330
3cf2715d
DE
1331 continue;
1332 }
674fc07d 1333
4b4bf941 1334 if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
3cf2715d
DE
1335 {
1336 int i;
f5d927c0 1337
3cf2715d
DE
1338 body = PATTERN (insn);
1339 new_length = 0;
1340 for (i = 0; i < XVECLEN (body, 0); i++)
1341 {
1342 rtx inner_insn = XVECEXP (body, 0, i);
1343 int inner_uid = INSN_UID (inner_insn);
1344 int inner_length;
1345
9d98a694 1346 INSN_ADDRESSES (inner_uid) = insn_current_address;
3cf2715d
DE
1347
1348 /* insn_current_length returns 0 for insns with a
1349 non-varying length. */
1350 if (! varying_length[inner_uid])
1351 inner_length = insn_lengths[inner_uid];
1352 else
1353 inner_length = insn_current_length (inner_insn);
1354
1355 if (inner_length != insn_lengths[inner_uid])
1356 {
1357 insn_lengths[inner_uid] = inner_length;
1358 something_changed = 1;
1359 }
1360 insn_current_address += insn_lengths[inner_uid];
1361 new_length += inner_length;
1362 }
1363 }
1364 else
1365 {
1366 new_length = insn_current_length (insn);
1367 insn_current_address += new_length;
1368 }
1369
3cf2715d
DE
1370#ifdef ADJUST_INSN_LENGTH
1371 /* If needed, do any adjustment. */
1372 tmp_length = new_length;
1373 ADJUST_INSN_LENGTH (insn, new_length);
1374 insn_current_address += (new_length - tmp_length);
3cf2715d
DE
1375#endif
1376
1377 if (new_length != insn_lengths[uid])
1378 {
1379 insn_lengths[uid] = new_length;
1380 something_changed = 1;
1381 }
1382 }
bb4aaf18
TG
1383 /* For a non-optimizing compile, do only a single pass. */
1384 if (!optimize)
1385 break;
3cf2715d 1386 }
fc470718
R
1387
1388 free (varying_length);
1389
3cf2715d
DE
1390#endif /* HAVE_ATTR_length */
1391}
1392
1393#ifdef HAVE_ATTR_length
1394/* Given the body of an INSN known to be generated by an ASM statement, return
1395 the number of machine instructions likely to be generated for this insn.
1396 This is used to compute its length. */
1397
1398static int
6cf9ac28 1399asm_insn_count (rtx body)
3cf2715d 1400{
48c54229 1401 const char *templ;
3cf2715d
DE
1402 int count = 1;
1403
5d0930ea 1404 if (GET_CODE (body) == ASM_INPUT)
48c54229 1405 templ = XSTR (body, 0);
5d0930ea 1406 else
48c54229 1407 templ = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
5d0930ea 1408
48c54229 1409 if (!*templ)
5bc4fa7c
MS
1410 return 0;
1411
48c54229
KG
1412 for (; *templ; templ++)
1413 if (IS_ASM_LOGICAL_LINE_SEPARATOR (*templ, templ)
1414 || *templ == '\n')
3cf2715d
DE
1415 count++;
1416
1417 return count;
1418}
1419#endif
1420\f
c8aea42c
PB
1421/* ??? This is probably the wrong place for these. */
1422/* Structure recording the mapping from source file and directory
1423 names at compile time to those to be embedded in debug
1424 information. */
1425typedef struct debug_prefix_map
1426{
1427 const char *old_prefix;
1428 const char *new_prefix;
1429 size_t old_len;
1430 size_t new_len;
1431 struct debug_prefix_map *next;
1432} debug_prefix_map;
1433
1434/* Linked list of such structures. */
1435debug_prefix_map *debug_prefix_maps;
1436
1437
1438/* Record a debug file prefix mapping. ARG is the argument to
1439 -fdebug-prefix-map and must be of the form OLD=NEW. */
1440
1441void
1442add_debug_prefix_map (const char *arg)
1443{
1444 debug_prefix_map *map;
1445 const char *p;
1446
1447 p = strchr (arg, '=');
1448 if (!p)
1449 {
1450 error ("invalid argument %qs to -fdebug-prefix-map", arg);
1451 return;
1452 }
1453 map = XNEW (debug_prefix_map);
fe83055d 1454 map->old_prefix = xstrndup (arg, p - arg);
c8aea42c
PB
1455 map->old_len = p - arg;
1456 p++;
fe83055d 1457 map->new_prefix = xstrdup (p);
c8aea42c
PB
1458 map->new_len = strlen (p);
1459 map->next = debug_prefix_maps;
1460 debug_prefix_maps = map;
1461}
1462
1463/* Perform user-specified mapping of debug filename prefixes. Return
1464 the new name corresponding to FILENAME. */
1465
1466const char *
1467remap_debug_filename (const char *filename)
1468{
1469 debug_prefix_map *map;
1470 char *s;
1471 const char *name;
1472 size_t name_len;
1473
1474 for (map = debug_prefix_maps; map; map = map->next)
1475 if (strncmp (filename, map->old_prefix, map->old_len) == 0)
1476 break;
1477 if (!map)
1478 return filename;
1479 name = filename + map->old_len;
1480 name_len = strlen (name) + 1;
1481 s = (char *) alloca (name_len + map->new_len);
1482 memcpy (s, map->new_prefix, map->new_len);
1483 memcpy (s + map->new_len, name, name_len);
1484 return ggc_strdup (s);
1485}
1486\f
3cf2715d
DE
1487/* Output assembler code for the start of a function,
1488 and initialize some of the variables in this file
1489 for the new function. The label for the function and associated
1490 assembler pseudo-ops have already been output in `assemble_start_function'.
1491
1492 FIRST is the first insn of the rtl for the function being compiled.
1493 FILE is the file to write assembler code to.
1494 OPTIMIZE is nonzero if we should eliminate redundant
1495 test and compare insns. */
1496
1497void
6cf9ac28
AJ
1498final_start_function (rtx first ATTRIBUTE_UNUSED, FILE *file,
1499 int optimize ATTRIBUTE_UNUSED)
3cf2715d
DE
1500{
1501 block_depth = 0;
1502
1503 this_is_asm_operands = 0;
1504
9ae130f8
JH
1505 last_filename = locator_file (prologue_locator);
1506 last_linenum = locator_line (prologue_locator);
6c52e687 1507 last_discriminator = discriminator = 0;
9ae130f8 1508
653e276c 1509 high_block_linenum = high_function_linenum = last_linenum;
eac40081 1510
653e276c 1511 (*debug_hooks->begin_prologue) (last_linenum, last_filename);
d291dd49 1512
951120ea 1513#if defined (DWARF2_UNWIND_INFO) || defined (TARGET_UNWIND_INFO)
7a0c8d71 1514 if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG)
653e276c 1515 dwarf2out_begin_prologue (0, NULL);
f5d927c0 1516#endif
3cf2715d
DE
1517
1518#ifdef LEAF_REG_REMAP
54ff41b7 1519 if (current_function_uses_only_leaf_regs)
3cf2715d
DE
1520 leaf_renumber_regs (first);
1521#endif
1522
1523 /* The Sun386i and perhaps other machines don't work right
1524 if the profiling code comes after the prologue. */
1525#ifdef PROFILE_BEFORE_PROLOGUE
e3b5732b 1526 if (crtl->profile)
3cf2715d
DE
1527 profile_function (file);
1528#endif /* PROFILE_BEFORE_PROLOGUE */
1529
0021b564
JM
1530#if defined (DWARF2_UNWIND_INFO) && defined (HAVE_prologue)
1531 if (dwarf2out_do_frame ())
e0c0490b 1532 dwarf2out_frame_debug (NULL_RTX, false);
0021b564
JM
1533#endif
1534
18c038b9
MM
1535 /* If debugging, assign block numbers to all of the blocks in this
1536 function. */
1537 if (write_symbols)
1538 {
0435312e 1539 reemit_insn_block_notes ();
a20612aa 1540 number_blocks (current_function_decl);
18c038b9
MM
1541 /* We never actually put out begin/end notes for the top-level
1542 block in the function. But, conceptually, that block is
1543 always needed. */
1544 TREE_ASM_WRITTEN (DECL_INITIAL (current_function_decl)) = 1;
1545 }
1546
a214518f
SP
1547 if (warn_frame_larger_than
1548 && get_frame_size () > frame_larger_than_size)
1549 {
1550 /* Issue a warning */
1551 warning (OPT_Wframe_larger_than_,
1552 "the frame size of %wd bytes is larger than %wd bytes",
1553 get_frame_size (), frame_larger_than_size);
1554 }
1555
3cf2715d 1556 /* First output the function prologue: code to set up the stack frame. */
5fd9b178 1557 targetm.asm_out.function_prologue (file, get_frame_size ());
3cf2715d 1558
3cf2715d
DE
1559 /* If the machine represents the prologue as RTL, the profiling code must
1560 be emitted when NOTE_INSN_PROLOGUE_END is scanned. */
1561#ifdef HAVE_prologue
1562 if (! HAVE_prologue)
1563#endif
1564 profile_after_prologue (file);
3cf2715d
DE
1565}
1566
1567static void
6cf9ac28 1568profile_after_prologue (FILE *file ATTRIBUTE_UNUSED)
3cf2715d 1569{
3cf2715d 1570#ifndef PROFILE_BEFORE_PROLOGUE
e3b5732b 1571 if (crtl->profile)
3cf2715d
DE
1572 profile_function (file);
1573#endif /* not PROFILE_BEFORE_PROLOGUE */
1574}
1575
1576static void
6cf9ac28 1577profile_function (FILE *file ATTRIBUTE_UNUSED)
3cf2715d 1578{
dcacfa04 1579#ifndef NO_PROFILE_COUNTERS
9739c90c 1580# define NO_PROFILE_COUNTERS 0
dcacfa04 1581#endif
b729186a 1582#if defined(ASM_OUTPUT_REG_PUSH)
e3b5732b 1583 int sval = cfun->returns_struct;
61f71b34 1584 rtx svrtx = targetm.calls.struct_value_rtx (TREE_TYPE (current_function_decl), 1);
b729186a 1585#if defined(STATIC_CHAIN_INCOMING_REGNUM) || defined(STATIC_CHAIN_REGNUM)
6de9cd9a 1586 int cxt = cfun->static_chain_decl != NULL;
b729186a
JL
1587#endif
1588#endif /* ASM_OUTPUT_REG_PUSH */
3cf2715d 1589
9739c90c
JJ
1590 if (! NO_PROFILE_COUNTERS)
1591 {
1592 int align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
d6b5193b 1593 switch_to_section (data_section);
9739c90c 1594 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
5fd9b178 1595 targetm.asm_out.internal_label (file, "LP", current_function_funcdef_no);
9739c90c
JJ
1596 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
1597 }
3cf2715d 1598
d6b5193b 1599 switch_to_section (current_function_section ());
3cf2715d 1600
61f71b34 1601#if defined(ASM_OUTPUT_REG_PUSH)
f8cfc6aa 1602 if (sval && svrtx != NULL_RTX && REG_P (svrtx))
586de218
KG
1603 {
1604 ASM_OUTPUT_REG_PUSH (file, REGNO (svrtx));
1605 }
3cf2715d
DE
1606#endif
1607
65ed39df 1608#if defined(STATIC_CHAIN_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH)
3cf2715d
DE
1609 if (cxt)
1610 ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_INCOMING_REGNUM);
1611#else
65ed39df 1612#if defined(STATIC_CHAIN_REGNUM) && defined(ASM_OUTPUT_REG_PUSH)
3cf2715d 1613 if (cxt)
51723711
KG
1614 {
1615 ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_REGNUM);
1616 }
3cf2715d
DE
1617#endif
1618#endif
3cf2715d 1619
df696a75 1620 FUNCTION_PROFILER (file, current_function_funcdef_no);
3cf2715d 1621
65ed39df 1622#if defined(STATIC_CHAIN_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH)
3cf2715d
DE
1623 if (cxt)
1624 ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_INCOMING_REGNUM);
1625#else
65ed39df 1626#if defined(STATIC_CHAIN_REGNUM) && defined(ASM_OUTPUT_REG_PUSH)
3cf2715d 1627 if (cxt)
51723711
KG
1628 {
1629 ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_REGNUM);
1630 }
3cf2715d
DE
1631#endif
1632#endif
3cf2715d 1633
61f71b34 1634#if defined(ASM_OUTPUT_REG_PUSH)
f8cfc6aa 1635 if (sval && svrtx != NULL_RTX && REG_P (svrtx))
586de218
KG
1636 {
1637 ASM_OUTPUT_REG_POP (file, REGNO (svrtx));
1638 }
3cf2715d
DE
1639#endif
1640}
1641
1642/* Output assembler code for the end of a function.
1643 For clarity, args are same as those of `final_start_function'
1644 even though not all of them are needed. */
1645
1646void
6cf9ac28 1647final_end_function (void)
3cf2715d 1648{
be1bb652 1649 app_disable ();
3cf2715d 1650
e2a12aca 1651 (*debug_hooks->end_function) (high_function_linenum);
3cf2715d 1652
3cf2715d
DE
1653 /* Finally, output the function epilogue:
1654 code to restore the stack frame and return to the caller. */
5fd9b178 1655 targetm.asm_out.function_epilogue (asm_out_file, get_frame_size ());
3cf2715d 1656
e2a12aca 1657 /* And debug output. */
702ada3d 1658 (*debug_hooks->end_epilogue) (last_linenum, last_filename);
3cf2715d 1659
e2a12aca 1660#if defined (DWARF2_UNWIND_INFO)
7a0c8d71
DR
1661 if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG
1662 && dwarf2out_do_frame ())
702ada3d 1663 dwarf2out_end_epilogue (last_linenum, last_filename);
9a666dda 1664#endif
3cf2715d
DE
1665}
1666\f
3cf2715d 1667/* Output assembler code for some insns: all or part of a function.
c9d691e9 1668 For description of args, see `final_start_function', above. */
3cf2715d
DE
1669
1670void
c9d691e9 1671final (rtx first, FILE *file, int optimize)
3cf2715d 1672{
b3694847 1673 rtx insn;
a8c3510c 1674 int max_uid = 0;
589fe865 1675 int seen = 0;
3cf2715d
DE
1676
1677 last_ignored_compare = 0;
3cf2715d 1678
3cf2715d 1679 for (insn = first; insn; insn = NEXT_INSN (insn))
a8c3510c 1680 {
938d968e 1681 if (INSN_UID (insn) > max_uid) /* Find largest UID. */
f5d927c0 1682 max_uid = INSN_UID (insn);
9ef4c6ef
JC
1683#ifdef HAVE_cc0
1684 /* If CC tracking across branches is enabled, record the insn which
1685 jumps to each branch only reached from one place. */
4b4bf941 1686 if (optimize && JUMP_P (insn))
9ef4c6ef
JC
1687 {
1688 rtx lab = JUMP_LABEL (insn);
1689 if (lab && LABEL_NUSES (lab) == 1)
1690 {
1691 LABEL_REFS (lab) = insn;
1692 }
1693 }
1694#endif
a8c3510c
AM
1695 }
1696
3cf2715d
DE
1697 init_recog ();
1698
1699 CC_STATUS_INIT;
1700
1701 /* Output the insns. */
9ff57809 1702 for (insn = first; insn;)
2f16edb1
TG
1703 {
1704#ifdef HAVE_ATTR_length
b9f22704 1705 if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
0ac76ad9 1706 {
0ac76ad9
RH
1707 /* This can be triggered by bugs elsewhere in the compiler if
1708 new insns are created after init_insn_lengths is called. */
0bccc606
NS
1709 gcc_assert (NOTE_P (insn));
1710 insn_current_address = -1;
0ac76ad9
RH
1711 }
1712 else
9d98a694 1713 insn_current_address = INSN_ADDRESSES (INSN_UID (insn));
0ac76ad9
RH
1714#endif /* HAVE_ATTR_length */
1715
c9d691e9 1716 insn = final_scan_insn (insn, file, optimize, 0, &seen);
2f16edb1 1717 }
3cf2715d
DE
1718}
1719\f
4bbf910e 1720const char *
6cf9ac28 1721get_insn_template (int code, rtx insn)
4bbf910e 1722{
4bbf910e
RH
1723 switch (insn_data[code].output_format)
1724 {
1725 case INSN_OUTPUT_FORMAT_SINGLE:
3897f229 1726 return insn_data[code].output.single;
4bbf910e 1727 case INSN_OUTPUT_FORMAT_MULTI:
3897f229 1728 return insn_data[code].output.multi[which_alternative];
4bbf910e 1729 case INSN_OUTPUT_FORMAT_FUNCTION:
0bccc606 1730 gcc_assert (insn);
3897f229 1731 return (*insn_data[code].output.function) (recog_data.operand, insn);
4bbf910e
RH
1732
1733 default:
0bccc606 1734 gcc_unreachable ();
4bbf910e
RH
1735 }
1736}
f5d927c0 1737
0dc36574
ZW
1738/* Emit the appropriate declaration for an alternate-entry-point
1739 symbol represented by INSN, to FILE. INSN is a CODE_LABEL with
1740 LABEL_KIND != LABEL_NORMAL.
1741
1742 The case fall-through in this function is intentional. */
1743static void
6cf9ac28 1744output_alternate_entry_point (FILE *file, rtx insn)
0dc36574
ZW
1745{
1746 const char *name = LABEL_NAME (insn);
1747
1748 switch (LABEL_KIND (insn))
1749 {
1750 case LABEL_WEAK_ENTRY:
1751#ifdef ASM_WEAKEN_LABEL
1752 ASM_WEAKEN_LABEL (file, name);
1753#endif
1754 case LABEL_GLOBAL_ENTRY:
5fd9b178 1755 targetm.asm_out.globalize_label (file, name);
0dc36574 1756 case LABEL_STATIC_ENTRY:
905173eb
ZW
1757#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
1758 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
1759#endif
0dc36574
ZW
1760 ASM_OUTPUT_LABEL (file, name);
1761 break;
1762
1763 case LABEL_NORMAL:
1764 default:
0bccc606 1765 gcc_unreachable ();
0dc36574
ZW
1766 }
1767}
1768
f410e1b3
RAE
1769/* Given a CALL_INSN, find and return the nested CALL. */
1770static rtx
1771call_from_call_insn (rtx insn)
1772{
1773 rtx x;
1774 gcc_assert (CALL_P (insn));
1775 x = PATTERN (insn);
1776
1777 while (GET_CODE (x) != CALL)
1778 {
1779 switch (GET_CODE (x))
1780 {
1781 default:
1782 gcc_unreachable ();
b8c71e40
RAE
1783 case COND_EXEC:
1784 x = COND_EXEC_CODE (x);
1785 break;
f410e1b3
RAE
1786 case PARALLEL:
1787 x = XVECEXP (x, 0, 0);
1788 break;
1789 case SET:
1790 x = XEXP (x, 1);
1791 break;
1792 }
1793 }
1794 return x;
1795}
1796
3cf2715d
DE
1797/* The final scan for one insn, INSN.
1798 Args are same as in `final', except that INSN
1799 is the insn being scanned.
1800 Value returned is the next insn to be scanned.
1801
ff8cea7e
EB
1802 NOPEEPHOLES is the flag to disallow peephole processing (currently
1803 used for within delayed branch sequence output).
3cf2715d 1804
589fe865
DJ
1805 SEEN is used to track the end of the prologue, for emitting
1806 debug information. We force the emission of a line note after
1807 both NOTE_INSN_PROLOGUE_END and NOTE_INSN_FUNCTION_BEG, or
1808 at the beginning of the second basic block, whichever comes
1809 first. */
1810
5cfc5f84 1811rtx
6cf9ac28 1812final_scan_insn (rtx insn, FILE *file, int optimize ATTRIBUTE_UNUSED,
c9d691e9 1813 int nopeepholes ATTRIBUTE_UNUSED, int *seen)
3cf2715d 1814{
90ca38bb
MM
1815#ifdef HAVE_cc0
1816 rtx set;
1817#endif
b2a6a2fb 1818 rtx next;
90ca38bb 1819
3cf2715d
DE
1820 insn_counter++;
1821
1822 /* Ignore deleted insns. These can occur when we split insns (due to a
1823 template of "#") while not optimizing. */
1824 if (INSN_DELETED_P (insn))
1825 return NEXT_INSN (insn);
1826
1827 switch (GET_CODE (insn))
1828 {
1829 case NOTE:
a38e7aa5 1830 switch (NOTE_KIND (insn))
be1bb652
RH
1831 {
1832 case NOTE_INSN_DELETED:
be1bb652 1833 break;
3cf2715d 1834
87c8b4be 1835 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
c543ca49 1836 in_cold_section_p = !in_cold_section_p;
a4b6974e
UB
1837#ifdef DWARF2_UNWIND_INFO
1838 if (dwarf2out_do_frame ())
1839 dwarf2out_switch_text_section ();
1840 else
1841#endif
1842 (*debug_hooks->switch_text_section) ();
1843
c543ca49 1844 switch_to_section (current_function_section ());
750054a2 1845 break;
b0efb46b 1846
be1bb652 1847 case NOTE_INSN_BASIC_BLOCK:
951120ea
PB
1848#ifdef TARGET_UNWIND_INFO
1849 targetm.asm_out.unwind_emit (asm_out_file, insn);
ad0fc698 1850#endif
951120ea 1851
be1bb652
RH
1852 if (flag_debug_asm)
1853 fprintf (asm_out_file, "\t%s basic block %d\n",
0b17ab2f 1854 ASM_COMMENT_START, NOTE_BASIC_BLOCK (insn)->index);
589fe865
DJ
1855
1856 if ((*seen & (SEEN_EMITTED | SEEN_BB)) == SEEN_BB)
1857 {
1858 *seen |= SEEN_EMITTED;
b8176fe4 1859 force_source_line = true;
589fe865
DJ
1860 }
1861 else
1862 *seen |= SEEN_BB;
1863
6c52e687
CC
1864 discriminator = NOTE_BASIC_BLOCK (insn)->discriminator;
1865
be1bb652 1866 break;
3cf2715d 1867
be1bb652 1868 case NOTE_INSN_EH_REGION_BEG:
52a11cbf
RH
1869 ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHB",
1870 NOTE_EH_HANDLER (insn));
3d195391 1871 break;
3d195391 1872
be1bb652 1873 case NOTE_INSN_EH_REGION_END:
52a11cbf
RH
1874 ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHE",
1875 NOTE_EH_HANDLER (insn));
3d195391 1876 break;
3d195391 1877
be1bb652 1878 case NOTE_INSN_PROLOGUE_END:
5fd9b178 1879 targetm.asm_out.function_end_prologue (file);
3cf2715d 1880 profile_after_prologue (file);
589fe865
DJ
1881
1882 if ((*seen & (SEEN_EMITTED | SEEN_NOTE)) == SEEN_NOTE)
1883 {
1884 *seen |= SEEN_EMITTED;
b8176fe4 1885 force_source_line = true;
589fe865
DJ
1886 }
1887 else
1888 *seen |= SEEN_NOTE;
1889
3cf2715d 1890 break;
3cf2715d 1891
be1bb652 1892 case NOTE_INSN_EPILOGUE_BEG:
cd9c1ca8
RH
1893#if defined (DWARF2_UNWIND_INFO) && defined (HAVE_epilogue)
1894 if (dwarf2out_do_frame ())
1895 dwarf2out_begin_epilogue (insn);
1896#endif
5fd9b178 1897 targetm.asm_out.function_begin_epilogue (file);
be1bb652 1898 break;
3cf2715d 1899
cd9c1ca8
RH
1900 case NOTE_INSN_CFA_RESTORE_STATE:
1901#if defined (DWARF2_UNWIND_INFO)
1902 dwarf2out_frame_debug_restore_state ();
1903#endif
1904 break;
1905
be1bb652 1906 case NOTE_INSN_FUNCTION_BEG:
653e276c 1907 app_disable ();
702ada3d 1908 (*debug_hooks->end_prologue) (last_linenum, last_filename);
589fe865
DJ
1909
1910 if ((*seen & (SEEN_EMITTED | SEEN_NOTE)) == SEEN_NOTE)
1911 {
1912 *seen |= SEEN_EMITTED;
b8176fe4 1913 force_source_line = true;
589fe865
DJ
1914 }
1915 else
1916 *seen |= SEEN_NOTE;
1917
3cf2715d 1918 break;
be1bb652
RH
1919
1920 case NOTE_INSN_BLOCK_BEG:
1921 if (debug_info_level == DINFO_LEVEL_NORMAL
3cf2715d 1922 || debug_info_level == DINFO_LEVEL_VERBOSE
7a0c8d71
DR
1923 || write_symbols == DWARF2_DEBUG
1924 || write_symbols == VMS_AND_DWARF2_DEBUG
1925 || write_symbols == VMS_DEBUG)
be1bb652
RH
1926 {
1927 int n = BLOCK_NUMBER (NOTE_BLOCK (insn));
3cf2715d 1928
be1bb652
RH
1929 app_disable ();
1930 ++block_depth;
1931 high_block_linenum = last_linenum;
eac40081 1932
a5a42b92 1933 /* Output debugging info about the symbol-block beginning. */
e2a12aca 1934 (*debug_hooks->begin_block) (last_linenum, n);
3cf2715d 1935
be1bb652
RH
1936 /* Mark this block as output. */
1937 TREE_ASM_WRITTEN (NOTE_BLOCK (insn)) = 1;
1938 }
d752cfdb
JJ
1939 if (write_symbols == DBX_DEBUG
1940 || write_symbols == SDB_DEBUG)
1941 {
1942 location_t *locus_ptr
1943 = block_nonartificial_location (NOTE_BLOCK (insn));
1944
1945 if (locus_ptr != NULL)
1946 {
1947 override_filename = LOCATION_FILE (*locus_ptr);
1948 override_linenum = LOCATION_LINE (*locus_ptr);
1949 }
1950 }
be1bb652 1951 break;
18c038b9 1952
be1bb652
RH
1953 case NOTE_INSN_BLOCK_END:
1954 if (debug_info_level == DINFO_LEVEL_NORMAL
1955 || debug_info_level == DINFO_LEVEL_VERBOSE
7a0c8d71
DR
1956 || write_symbols == DWARF2_DEBUG
1957 || write_symbols == VMS_AND_DWARF2_DEBUG
1958 || write_symbols == VMS_DEBUG)
be1bb652
RH
1959 {
1960 int n = BLOCK_NUMBER (NOTE_BLOCK (insn));
3cf2715d 1961
be1bb652
RH
1962 app_disable ();
1963
1964 /* End of a symbol-block. */
1965 --block_depth;
0bccc606 1966 gcc_assert (block_depth >= 0);
3cf2715d 1967
e2a12aca 1968 (*debug_hooks->end_block) (high_block_linenum, n);
be1bb652 1969 }
d752cfdb
JJ
1970 if (write_symbols == DBX_DEBUG
1971 || write_symbols == SDB_DEBUG)
1972 {
1973 tree outer_block = BLOCK_SUPERCONTEXT (NOTE_BLOCK (insn));
1974 location_t *locus_ptr
1975 = block_nonartificial_location (outer_block);
1976
1977 if (locus_ptr != NULL)
1978 {
1979 override_filename = LOCATION_FILE (*locus_ptr);
1980 override_linenum = LOCATION_LINE (*locus_ptr);
1981 }
1982 else
1983 {
1984 override_filename = NULL;
1985 override_linenum = 0;
1986 }
1987 }
be1bb652
RH
1988 break;
1989
1990 case NOTE_INSN_DELETED_LABEL:
1991 /* Emit the label. We may have deleted the CODE_LABEL because
1992 the label could be proved to be unreachable, though still
1993 referenced (in the form of having its address taken. */
8215347e 1994 ASM_OUTPUT_DEBUG_LABEL (file, "L", CODE_LABEL_NUMBER (insn));
be1bb652 1995 break;
3cf2715d 1996
014a1138
JZ
1997 case NOTE_INSN_VAR_LOCATION:
1998 (*debug_hooks->var_location) (insn);
1999 break;
2000
be1bb652 2001 default:
a38e7aa5 2002 gcc_unreachable ();
f5d927c0 2003 break;
3cf2715d
DE
2004 }
2005 break;
2006
2007 case BARRIER:
f73ad30e 2008#if defined (DWARF2_UNWIND_INFO)
fbfa55b0 2009 if (dwarf2out_do_frame ())
e0c0490b 2010 dwarf2out_frame_debug (insn, false);
3cf2715d
DE
2011#endif
2012 break;
2013
2014 case CODE_LABEL:
1dd8faa8
R
2015 /* The target port might emit labels in the output function for
2016 some insn, e.g. sh.c output_branchy_insn. */
de7987a6
R
2017 if (CODE_LABEL_NUMBER (insn) <= max_labelno)
2018 {
2019 int align = LABEL_TO_ALIGNMENT (insn);
50b2596f 2020#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
9e423e6d 2021 int max_skip = LABEL_TO_MAX_SKIP (insn);
50b2596f 2022#endif
fc470718 2023
1dd8faa8 2024 if (align && NEXT_INSN (insn))
40cdfca6 2025 {
9e423e6d 2026#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
40cdfca6 2027 ASM_OUTPUT_MAX_SKIP_ALIGN (file, align, max_skip);
8e16ab99
SF
2028#else
2029#ifdef ASM_OUTPUT_ALIGN_WITH_NOP
2030 ASM_OUTPUT_ALIGN_WITH_NOP (file, align);
9e423e6d 2031#else
40cdfca6 2032 ASM_OUTPUT_ALIGN (file, align);
8e16ab99 2033#endif
9e423e6d 2034#endif
40cdfca6 2035 }
de7987a6 2036 }
9ef4c6ef 2037#ifdef HAVE_cc0
3cf2715d 2038 CC_STATUS_INIT;
9ef4c6ef 2039#endif
03ffa171 2040
e1772ac0
NB
2041 if (LABEL_NAME (insn))
2042 (*debug_hooks->label) (insn);
2043
bad4f40b 2044 app_disable ();
b2a6a2fb
JJ
2045
2046 next = next_nonnote_insn (insn);
0676c393
MM
2047 /* If this label is followed by a jump-table, make sure we put
2048 the label in the read-only section. Also possibly write the
2049 label and jump table together. */
2050 if (next != 0 && JUMP_TABLE_DATA_P (next))
3cf2715d 2051 {
e0d80184 2052#if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
0676c393
MM
2053 /* In this case, the case vector is being moved by the
2054 target, so don't output the label at all. Leave that
2055 to the back end macros. */
e0d80184 2056#else
0676c393
MM
2057 if (! JUMP_TABLES_IN_TEXT_SECTION)
2058 {
2059 int log_align;
340f7e7c 2060
0676c393
MM
2061 switch_to_section (targetm.asm_out.function_rodata_section
2062 (current_function_decl));
340f7e7c
RH
2063
2064#ifdef ADDR_VEC_ALIGN
0676c393 2065 log_align = ADDR_VEC_ALIGN (next);
340f7e7c 2066#else
0676c393 2067 log_align = exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT);
340f7e7c 2068#endif
0676c393
MM
2069 ASM_OUTPUT_ALIGN (file, log_align);
2070 }
2071 else
2072 switch_to_section (current_function_section ());
75197b37 2073
3cf2715d 2074#ifdef ASM_OUTPUT_CASE_LABEL
0676c393
MM
2075 ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn),
2076 next);
3cf2715d 2077#else
0676c393 2078 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn));
e0d80184 2079#endif
3cf2715d 2080#endif
0676c393 2081 break;
3cf2715d 2082 }
0dc36574
ZW
2083 if (LABEL_ALT_ENTRY_P (insn))
2084 output_alternate_entry_point (file, insn);
8cd0faaf 2085 else
5fd9b178 2086 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn));
3cf2715d
DE
2087 break;
2088
2089 default:
2090 {
b3694847 2091 rtx body = PATTERN (insn);
3cf2715d 2092 int insn_code_number;
48c54229 2093 const char *templ;
ed5ef2e4 2094 bool is_stmt;
3cf2715d 2095
9a1a4737
PB
2096#ifdef HAVE_conditional_execution
2097 /* Reset this early so it is correct for ASM statements. */
2098 current_insn_predicate = NULL_RTX;
2099#endif
3cf2715d
DE
2100 /* An INSN, JUMP_INSN or CALL_INSN.
2101 First check for special kinds that recog doesn't recognize. */
2102
6614fd40 2103 if (GET_CODE (body) == USE /* These are just declarations. */
3cf2715d
DE
2104 || GET_CODE (body) == CLOBBER)
2105 break;
2106
2107#ifdef HAVE_cc0
4928181c
SB
2108 {
2109 /* If there is a REG_CC_SETTER note on this insn, it means that
2110 the setting of the condition code was done in the delay slot
2111 of the insn that branched here. So recover the cc status
2112 from the insn that set it. */
3cf2715d 2113
4928181c
SB
2114 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
2115 if (note)
2116 {
2117 NOTICE_UPDATE_CC (PATTERN (XEXP (note, 0)), XEXP (note, 0));
2118 cc_prev_status = cc_status;
2119 }
2120 }
3cf2715d
DE
2121#endif
2122
2123 /* Detect insns that are really jump-tables
2124 and output them as such. */
2125
2126 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
2127 {
7f7f8214 2128#if !(defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC))
b3694847 2129 int vlen, idx;
7f7f8214 2130#endif
3cf2715d 2131
b2a6a2fb 2132 if (! JUMP_TABLES_IN_TEXT_SECTION)
d6b5193b
RS
2133 switch_to_section (targetm.asm_out.function_rodata_section
2134 (current_function_decl));
b2a6a2fb 2135 else
d6b5193b 2136 switch_to_section (current_function_section ());
b2a6a2fb 2137
bad4f40b 2138 app_disable ();
3cf2715d 2139
e0d80184
DM
2140#if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
2141 if (GET_CODE (body) == ADDR_VEC)
2142 {
2143#ifdef ASM_OUTPUT_ADDR_VEC
2144 ASM_OUTPUT_ADDR_VEC (PREV_INSN (insn), body);
2145#else
0bccc606 2146 gcc_unreachable ();
e0d80184
DM
2147#endif
2148 }
2149 else
2150 {
2151#ifdef ASM_OUTPUT_ADDR_DIFF_VEC
2152 ASM_OUTPUT_ADDR_DIFF_VEC (PREV_INSN (insn), body);
2153#else
0bccc606 2154 gcc_unreachable ();
e0d80184
DM
2155#endif
2156 }
2157#else
3cf2715d
DE
2158 vlen = XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC);
2159 for (idx = 0; idx < vlen; idx++)
2160 {
2161 if (GET_CODE (body) == ADDR_VEC)
2162 {
2163#ifdef ASM_OUTPUT_ADDR_VEC_ELT
2164 ASM_OUTPUT_ADDR_VEC_ELT
2165 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
2166#else
0bccc606 2167 gcc_unreachable ();
3cf2715d
DE
2168#endif
2169 }
2170 else
2171 {
2172#ifdef ASM_OUTPUT_ADDR_DIFF_ELT
2173 ASM_OUTPUT_ADDR_DIFF_ELT
2174 (file,
33f7f353 2175 body,
3cf2715d
DE
2176 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
2177 CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0)));
2178#else
0bccc606 2179 gcc_unreachable ();
3cf2715d
DE
2180#endif
2181 }
2182 }
2183#ifdef ASM_OUTPUT_CASE_END
2184 ASM_OUTPUT_CASE_END (file,
2185 CODE_LABEL_NUMBER (PREV_INSN (insn)),
2186 insn);
e0d80184 2187#endif
3cf2715d
DE
2188#endif
2189
d6b5193b 2190 switch_to_section (current_function_section ());
3cf2715d
DE
2191
2192 break;
2193 }
0435312e
JH
2194 /* Output this line note if it is the first or the last line
2195 note in a row. */
ed5ef2e4 2196 if (notice_source_line (insn, &is_stmt))
0435312e 2197 {
6c52e687
CC
2198 (*debug_hooks->source_line) (last_linenum,
2199 last_filename,
ed5ef2e4
CC
2200 last_discriminator,
2201 is_stmt);
0435312e 2202 }
3cf2715d 2203
3cf2715d
DE
2204 if (GET_CODE (body) == ASM_INPUT)
2205 {
36d7136e
RH
2206 const char *string = XSTR (body, 0);
2207
3cf2715d
DE
2208 /* There's no telling what that did to the condition codes. */
2209 CC_STATUS_INIT;
36d7136e
RH
2210
2211 if (string[0])
3cf2715d 2212 {
5ffeb913 2213 expanded_location loc;
bff4b63d 2214
3a694d86 2215 app_enable ();
5ffeb913 2216 loc = expand_location (ASM_INPUT_SOURCE_LOCATION (body));
0de2ae02 2217 if (*loc.file && loc.line)
bff4b63d
AO
2218 fprintf (asm_out_file, "%s %i \"%s\" 1\n",
2219 ASM_COMMENT_START, loc.line, loc.file);
36d7136e 2220 fprintf (asm_out_file, "\t%s\n", string);
03943c05
AO
2221#if HAVE_AS_LINE_ZERO
2222 if (*loc.file && loc.line)
bff4b63d 2223 fprintf (asm_out_file, "%s 0 \"\" 2\n", ASM_COMMENT_START);
03943c05 2224#endif
3cf2715d 2225 }
3cf2715d
DE
2226 break;
2227 }
2228
2229 /* Detect `asm' construct with operands. */
2230 if (asm_noperands (body) >= 0)
2231 {
22bf4422 2232 unsigned int noperands = asm_noperands (body);
1b4572a8 2233 rtx *ops = XALLOCAVEC (rtx, noperands);
3cce094d 2234 const char *string;
bff4b63d 2235 location_t loc;
5ffeb913 2236 expanded_location expanded;
3cf2715d
DE
2237
2238 /* There's no telling what that did to the condition codes. */
2239 CC_STATUS_INIT;
3cf2715d 2240
3cf2715d 2241 /* Get out the operand values. */
bff4b63d 2242 string = decode_asm_operands (body, ops, NULL, NULL, NULL, &loc);
41129be2 2243 /* Inhibit dying on what would otherwise be compiler bugs. */
3cf2715d
DE
2244 insn_noperands = noperands;
2245 this_is_asm_operands = insn;
5ffeb913 2246 expanded = expand_location (loc);
3cf2715d 2247
ad7e39ca
AO
2248#ifdef FINAL_PRESCAN_INSN
2249 FINAL_PRESCAN_INSN (insn, ops, insn_noperands);
2250#endif
2251
3cf2715d 2252 /* Output the insn using them. */
36d7136e
RH
2253 if (string[0])
2254 {
3a694d86 2255 app_enable ();
5ffeb913 2256 if (expanded.file && expanded.line)
bff4b63d 2257 fprintf (asm_out_file, "%s %i \"%s\" 1\n",
5ffeb913 2258 ASM_COMMENT_START, expanded.line, expanded.file);
36d7136e 2259 output_asm_insn (string, ops);
03943c05 2260#if HAVE_AS_LINE_ZERO
5ffeb913 2261 if (expanded.file && expanded.line)
bff4b63d 2262 fprintf (asm_out_file, "%s 0 \"\" 2\n", ASM_COMMENT_START);
03943c05 2263#endif
36d7136e
RH
2264 }
2265
1afc5373
CF
2266 if (targetm.asm_out.final_postscan_insn)
2267 targetm.asm_out.final_postscan_insn (file, insn, ops,
2268 insn_noperands);
2269
3cf2715d
DE
2270 this_is_asm_operands = 0;
2271 break;
2272 }
2273
bad4f40b 2274 app_disable ();
3cf2715d
DE
2275
2276 if (GET_CODE (body) == SEQUENCE)
2277 {
2278 /* A delayed-branch sequence */
b3694847 2279 int i;
3cf2715d 2280
3cf2715d
DE
2281 final_sequence = body;
2282
d660cefe
RS
2283 /* Record the delay slots' frame information before the branch.
2284 This is needed for delayed calls: see execute_cfa_program(). */
2285#if defined (DWARF2_UNWIND_INFO)
2286 if (dwarf2out_do_frame ())
2287 for (i = 1; i < XVECLEN (body, 0); i++)
e0c0490b 2288 dwarf2out_frame_debug (XVECEXP (body, 0, i), false);
d660cefe
RS
2289#endif
2290
3cf2715d
DE
2291 /* The first insn in this SEQUENCE might be a JUMP_INSN that will
2292 force the restoration of a comparison that was previously
2293 thought unnecessary. If that happens, cancel this sequence
2294 and cause that insn to be restored. */
2295
c9d691e9 2296 next = final_scan_insn (XVECEXP (body, 0, 0), file, 0, 1, seen);
3cf2715d
DE
2297 if (next != XVECEXP (body, 0, 1))
2298 {
2299 final_sequence = 0;
2300 return next;
2301 }
2302
2303 for (i = 1; i < XVECLEN (body, 0); i++)
c7eee2df
RK
2304 {
2305 rtx insn = XVECEXP (body, 0, i);
2306 rtx next = NEXT_INSN (insn);
2307 /* We loop in case any instruction in a delay slot gets
2308 split. */
2309 do
c9d691e9 2310 insn = final_scan_insn (insn, file, 0, 1, seen);
c7eee2df
RK
2311 while (insn != next);
2312 }
3cf2715d
DE
2313#ifdef DBR_OUTPUT_SEQEND
2314 DBR_OUTPUT_SEQEND (file);
2315#endif
2316 final_sequence = 0;
2317
2318 /* If the insn requiring the delay slot was a CALL_INSN, the
2319 insns in the delay slot are actually executed before the
2320 called function. Hence we don't preserve any CC-setting
2321 actions in these insns and the CC must be marked as being
2322 clobbered by the function. */
4b4bf941 2323 if (CALL_P (XVECEXP (body, 0, 0)))
b729186a
JL
2324 {
2325 CC_STATUS_INIT;
2326 }
3cf2715d
DE
2327 break;
2328 }
2329
2330 /* We have a real machine instruction as rtl. */
2331
2332 body = PATTERN (insn);
2333
2334#ifdef HAVE_cc0
f5d927c0 2335 set = single_set (insn);
b88c92cc 2336
3cf2715d
DE
2337 /* Check for redundant test and compare instructions
2338 (when the condition codes are already set up as desired).
2339 This is done only when optimizing; if not optimizing,
2340 it should be possible for the user to alter a variable
2341 with the debugger in between statements
2342 and the next statement should reexamine the variable
2343 to compute the condition codes. */
2344
30f5e9f5 2345 if (optimize)
3cf2715d 2346 {
30f5e9f5
RK
2347 if (set
2348 && GET_CODE (SET_DEST (set)) == CC0
2349 && insn != last_ignored_compare)
3cf2715d 2350 {
f90b7a5a 2351 rtx src1, src2;
30f5e9f5 2352 if (GET_CODE (SET_SRC (set)) == SUBREG)
49d801d3 2353 SET_SRC (set) = alter_subreg (&SET_SRC (set));
f90b7a5a
PB
2354
2355 src1 = SET_SRC (set);
2356 src2 = NULL_RTX;
2357 if (GET_CODE (SET_SRC (set)) == COMPARE)
30f5e9f5
RK
2358 {
2359 if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
2360 XEXP (SET_SRC (set), 0)
49d801d3 2361 = alter_subreg (&XEXP (SET_SRC (set), 0));
30f5e9f5
RK
2362 if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG)
2363 XEXP (SET_SRC (set), 1)
49d801d3 2364 = alter_subreg (&XEXP (SET_SRC (set), 1));
f90b7a5a
PB
2365 if (XEXP (SET_SRC (set), 1)
2366 == CONST0_RTX (GET_MODE (XEXP (SET_SRC (set), 0))))
2367 src2 = XEXP (SET_SRC (set), 0);
30f5e9f5
RK
2368 }
2369 if ((cc_status.value1 != 0
f90b7a5a 2370 && rtx_equal_p (src1, cc_status.value1))
30f5e9f5 2371 || (cc_status.value2 != 0
f90b7a5a
PB
2372 && rtx_equal_p (src1, cc_status.value2))
2373 || (src2 != 0 && cc_status.value1 != 0
2374 && rtx_equal_p (src2, cc_status.value1))
2375 || (src2 != 0 && cc_status.value2 != 0
2376 && rtx_equal_p (src2, cc_status.value2)))
3cf2715d 2377 {
30f5e9f5 2378 /* Don't delete insn if it has an addressing side-effect. */
ff81832f 2379 if (! FIND_REG_INC_NOTE (insn, NULL_RTX)
30f5e9f5
RK
2380 /* or if anything in it is volatile. */
2381 && ! volatile_refs_p (PATTERN (insn)))
2382 {
2383 /* We don't really delete the insn; just ignore it. */
2384 last_ignored_compare = insn;
2385 break;
2386 }
3cf2715d
DE
2387 }
2388 }
2389 }
3cf2715d 2390
3cf2715d
DE
2391 /* If this is a conditional branch, maybe modify it
2392 if the cc's are in a nonstandard state
2393 so that it accomplishes the same thing that it would
2394 do straightforwardly if the cc's were set up normally. */
2395
2396 if (cc_status.flags != 0
4b4bf941 2397 && JUMP_P (insn)
3cf2715d
DE
2398 && GET_CODE (body) == SET
2399 && SET_DEST (body) == pc_rtx
2400 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
ec8e098d 2401 && COMPARISON_P (XEXP (SET_SRC (body), 0))
c9d691e9 2402 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
3cf2715d
DE
2403 {
2404 /* This function may alter the contents of its argument
2405 and clear some of the cc_status.flags bits.
2406 It may also return 1 meaning condition now always true
2407 or -1 meaning condition now always false
2408 or 2 meaning condition nontrivial but altered. */
b3694847 2409 int result = alter_cond (XEXP (SET_SRC (body), 0));
3cf2715d
DE
2410 /* If condition now has fixed value, replace the IF_THEN_ELSE
2411 with its then-operand or its else-operand. */
2412 if (result == 1)
2413 SET_SRC (body) = XEXP (SET_SRC (body), 1);
2414 if (result == -1)
2415 SET_SRC (body) = XEXP (SET_SRC (body), 2);
2416
2417 /* The jump is now either unconditional or a no-op.
2418 If it has become a no-op, don't try to output it.
2419 (It would not be recognized.) */
2420 if (SET_SRC (body) == pc_rtx)
2421 {
ca6c03ca 2422 delete_insn (insn);
3cf2715d
DE
2423 break;
2424 }
2425 else if (GET_CODE (SET_SRC (body)) == RETURN)
2426 /* Replace (set (pc) (return)) with (return). */
2427 PATTERN (insn) = body = SET_SRC (body);
2428
2429 /* Rerecognize the instruction if it has changed. */
2430 if (result != 0)
2431 INSN_CODE (insn) = -1;
2432 }
2433
604e4ce3 2434 /* If this is a conditional trap, maybe modify it if the cc's
604e4ce3
KH
2435 are in a nonstandard state so that it accomplishes the same
2436 thing that it would do straightforwardly if the cc's were
2437 set up normally. */
2438 if (cc_status.flags != 0
2439 && NONJUMP_INSN_P (insn)
2440 && GET_CODE (body) == TRAP_IF
2441 && COMPARISON_P (TRAP_CONDITION (body))
2442 && XEXP (TRAP_CONDITION (body), 0) == cc0_rtx)
2443 {
2444 /* This function may alter the contents of its argument
2445 and clear some of the cc_status.flags bits.
2446 It may also return 1 meaning condition now always true
2447 or -1 meaning condition now always false
2448 or 2 meaning condition nontrivial but altered. */
2449 int result = alter_cond (TRAP_CONDITION (body));
2450
2451 /* If TRAP_CONDITION has become always false, delete the
2452 instruction. */
2453 if (result == -1)
2454 {
2455 delete_insn (insn);
2456 break;
2457 }
2458
2459 /* If TRAP_CONDITION has become always true, replace
2460 TRAP_CONDITION with const_true_rtx. */
2461 if (result == 1)
2462 TRAP_CONDITION (body) = const_true_rtx;
2463
2464 /* Rerecognize the instruction if it has changed. */
2465 if (result != 0)
2466 INSN_CODE (insn) = -1;
2467 }
2468
3cf2715d 2469 /* Make same adjustments to instructions that examine the
462da2af
SC
2470 condition codes without jumping and instructions that
2471 handle conditional moves (if this machine has either one). */
3cf2715d
DE
2472
2473 if (cc_status.flags != 0
b88c92cc 2474 && set != 0)
3cf2715d 2475 {
462da2af 2476 rtx cond_rtx, then_rtx, else_rtx;
f5d927c0 2477
4b4bf941 2478 if (!JUMP_P (insn)
b88c92cc 2479 && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE)
462da2af 2480 {
b88c92cc
RK
2481 cond_rtx = XEXP (SET_SRC (set), 0);
2482 then_rtx = XEXP (SET_SRC (set), 1);
2483 else_rtx = XEXP (SET_SRC (set), 2);
462da2af
SC
2484 }
2485 else
2486 {
b88c92cc 2487 cond_rtx = SET_SRC (set);
462da2af
SC
2488 then_rtx = const_true_rtx;
2489 else_rtx = const0_rtx;
2490 }
f5d927c0 2491
462da2af 2492 switch (GET_CODE (cond_rtx))
3cf2715d
DE
2493 {
2494 case GTU:
2495 case GT:
2496 case LTU:
2497 case LT:
2498 case GEU:
2499 case GE:
2500 case LEU:
2501 case LE:
2502 case EQ:
2503 case NE:
2504 {
b3694847 2505 int result;
462da2af 2506 if (XEXP (cond_rtx, 0) != cc0_rtx)
3cf2715d 2507 break;
462da2af 2508 result = alter_cond (cond_rtx);
3cf2715d 2509 if (result == 1)
b88c92cc 2510 validate_change (insn, &SET_SRC (set), then_rtx, 0);
3cf2715d 2511 else if (result == -1)
b88c92cc 2512 validate_change (insn, &SET_SRC (set), else_rtx, 0);
3cf2715d
DE
2513 else if (result == 2)
2514 INSN_CODE (insn) = -1;
b88c92cc 2515 if (SET_DEST (set) == SET_SRC (set))
ca6c03ca 2516 delete_insn (insn);
3cf2715d 2517 }
e9a25f70
JL
2518 break;
2519
2520 default:
2521 break;
3cf2715d
DE
2522 }
2523 }
462da2af 2524
3cf2715d
DE
2525#endif
2526
ede7cd44 2527#ifdef HAVE_peephole
3cf2715d
DE
2528 /* Do machine-specific peephole optimizations if desired. */
2529
2530 if (optimize && !flag_no_peephole && !nopeepholes)
2531 {
2532 rtx next = peephole (insn);
2533 /* When peepholing, if there were notes within the peephole,
2534 emit them before the peephole. */
2535 if (next != 0 && next != NEXT_INSN (insn))
2536 {
a2785739 2537 rtx note, prev = PREV_INSN (insn);
3cf2715d
DE
2538
2539 for (note = NEXT_INSN (insn); note != next;
2540 note = NEXT_INSN (note))
c9d691e9 2541 final_scan_insn (note, file, optimize, nopeepholes, seen);
a2785739
ILT
2542
2543 /* Put the notes in the proper position for a later
2544 rescan. For example, the SH target can do this
2545 when generating a far jump in a delayed branch
2546 sequence. */
2547 note = NEXT_INSN (insn);
2548 PREV_INSN (note) = prev;
2549 NEXT_INSN (prev) = note;
2550 NEXT_INSN (PREV_INSN (next)) = insn;
2551 PREV_INSN (insn) = PREV_INSN (next);
2552 NEXT_INSN (insn) = next;
2553 PREV_INSN (next) = insn;
3cf2715d
DE
2554 }
2555
2556 /* PEEPHOLE might have changed this. */
2557 body = PATTERN (insn);
2558 }
ede7cd44 2559#endif
3cf2715d
DE
2560
2561 /* Try to recognize the instruction.
2562 If successful, verify that the operands satisfy the
2563 constraints for the instruction. Crash if they don't,
2564 since `reload' should have changed them so that they do. */
2565
2566 insn_code_number = recog_memoized (insn);
0304f787 2567 cleanup_subreg_operands (insn);
3cf2715d 2568
dd3f0101
KH
2569 /* Dump the insn in the assembly for debugging. */
2570 if (flag_dump_rtl_in_asm)
2571 {
2572 print_rtx_head = ASM_COMMENT_START;
2573 print_rtl_single (asm_out_file, insn);
2574 print_rtx_head = "";
2575 }
b9f22704 2576
6c698a6d 2577 if (! constrain_operands_cached (1))
3cf2715d 2578 fatal_insn_not_found (insn);
3cf2715d
DE
2579
2580 /* Some target machines need to prescan each insn before
2581 it is output. */
2582
2583#ifdef FINAL_PRESCAN_INSN
1ccbefce 2584 FINAL_PRESCAN_INSN (insn, recog_data.operand, recog_data.n_operands);
3cf2715d
DE
2585#endif
2586
afe48e06
RH
2587#ifdef HAVE_conditional_execution
2588 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
2589 current_insn_predicate = COND_EXEC_TEST (PATTERN (insn));
afe48e06
RH
2590#endif
2591
3cf2715d
DE
2592#ifdef HAVE_cc0
2593 cc_prev_status = cc_status;
2594
2595 /* Update `cc_status' for this instruction.
2596 The instruction's output routine may change it further.
2597 If the output routine for a jump insn needs to depend
2598 on the cc status, it should look at cc_prev_status. */
2599
2600 NOTICE_UPDATE_CC (body, insn);
2601#endif
2602
b1a9f6a0 2603 current_output_insn = debug_insn = insn;
3cf2715d 2604
f73ad30e 2605#if defined (DWARF2_UNWIND_INFO)
4b4bf941 2606 if (CALL_P (insn) && dwarf2out_do_frame ())
e0c0490b 2607 dwarf2out_frame_debug (insn, false);
b57d9225
JM
2608#endif
2609
4bbf910e 2610 /* Find the proper template for this insn. */
48c54229 2611 templ = get_insn_template (insn_code_number, insn);
3cf2715d 2612
4bbf910e
RH
2613 /* If the C code returns 0, it means that it is a jump insn
2614 which follows a deleted test insn, and that test insn
2615 needs to be reinserted. */
48c54229 2616 if (templ == 0)
3cf2715d 2617 {
efd0378b
HPN
2618 rtx prev;
2619
0bccc606 2620 gcc_assert (prev_nonnote_insn (insn) == last_ignored_compare);
efd0378b
HPN
2621
2622 /* We have already processed the notes between the setter and
2623 the user. Make sure we don't process them again, this is
2624 particularly important if one of the notes is a block
2625 scope note or an EH note. */
2626 for (prev = insn;
2627 prev != last_ignored_compare;
2628 prev = PREV_INSN (prev))
2629 {
4b4bf941 2630 if (NOTE_P (prev))
ca6c03ca 2631 delete_insn (prev); /* Use delete_note. */
efd0378b
HPN
2632 }
2633
2634 return prev;
3cf2715d
DE
2635 }
2636
2637 /* If the template is the string "#", it means that this insn must
2638 be split. */
48c54229 2639 if (templ[0] == '#' && templ[1] == '\0')
3cf2715d 2640 {
48c54229 2641 rtx new_rtx = try_split (body, insn, 0);
3cf2715d
DE
2642
2643 /* If we didn't split the insn, go away. */
48c54229 2644 if (new_rtx == insn && PATTERN (new_rtx) == body)
c725bd79 2645 fatal_insn ("could not split insn", insn);
f5d927c0 2646
3d14e82f
JW
2647#ifdef HAVE_ATTR_length
2648 /* This instruction should have been split in shorten_branches,
2649 to ensure that we would have valid length info for the
2650 splitees. */
0bccc606 2651 gcc_unreachable ();
3d14e82f
JW
2652#endif
2653
48c54229 2654 return new_rtx;
3cf2715d 2655 }
f5d927c0 2656
951120ea
PB
2657#ifdef TARGET_UNWIND_INFO
2658 /* ??? This will put the directives in the wrong place if
2659 get_insn_template outputs assembly directly. However calling it
2660 before get_insn_template breaks if the insns is split. */
2661 targetm.asm_out.unwind_emit (asm_out_file, insn);
ce152ef8 2662#endif
3cf2715d 2663
f410e1b3
RAE
2664 if (CALL_P (insn))
2665 {
2666 rtx x = call_from_call_insn (insn);
2667 x = XEXP (x, 0);
2668 if (x && MEM_P (x) && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2669 {
2670 tree t;
2671 x = XEXP (x, 0);
2672 t = SYMBOL_REF_DECL (x);
2673 if (t)
2674 assemble_external (t);
2675 }
2676 }
2677
951120ea 2678 /* Output assembler code from the template. */
48c54229 2679 output_asm_insn (templ, recog_data.operand);
3cf2715d 2680
1afc5373
CF
2681 /* Some target machines need to postscan each insn after
2682 it is output. */
2683 if (targetm.asm_out.final_postscan_insn)
2684 targetm.asm_out.final_postscan_insn (file, insn, recog_data.operand,
2685 recog_data.n_operands);
2686
d660cefe
RS
2687 /* If necessary, report the effect that the instruction has on
2688 the unwind info. We've already done this for delay slots
2689 and call instructions. */
0021b564 2690#if defined (DWARF2_UNWIND_INFO)
e0c0490b 2691 if (final_sequence == 0
d660cefe
RS
2692#if !defined (HAVE_prologue)
2693 && !ACCUMULATE_OUTGOING_ARGS
2694#endif
fbfa55b0 2695 && dwarf2out_do_frame ())
e0c0490b 2696 dwarf2out_frame_debug (insn, true);
0021b564 2697#endif
469ac993 2698
b1a9f6a0 2699 current_output_insn = debug_insn = 0;
3cf2715d
DE
2700 }
2701 }
2702 return NEXT_INSN (insn);
2703}
2704\f
ed5ef2e4
CC
2705/* Return whether a source line note needs to be emitted before INSN.
2706 Sets IS_STMT to TRUE if the line should be marked as a possible
2707 breakpoint location. */
3cf2715d 2708
0435312e 2709static bool
ed5ef2e4 2710notice_source_line (rtx insn, bool *is_stmt)
3cf2715d 2711{
d752cfdb
JJ
2712 const char *filename;
2713 int linenum;
2714
2715 if (override_filename)
2716 {
2717 filename = override_filename;
2718 linenum = override_linenum;
2719 }
2720 else
2721 {
2722 filename = insn_file (insn);
2723 linenum = insn_line (insn);
2724 }
3cf2715d 2725
ed5ef2e4
CC
2726 if (filename == NULL)
2727 return false;
2728
2729 if (force_source_line
2730 || filename != last_filename
2731 || last_linenum != linenum)
0435312e 2732 {
b8176fe4 2733 force_source_line = false;
0435312e
JH
2734 last_filename = filename;
2735 last_linenum = linenum;
6c52e687 2736 last_discriminator = discriminator;
ed5ef2e4 2737 *is_stmt = true;
0435312e
JH
2738 high_block_linenum = MAX (last_linenum, high_block_linenum);
2739 high_function_linenum = MAX (last_linenum, high_function_linenum);
2740 return true;
2741 }
ed5ef2e4
CC
2742
2743 if (SUPPORTS_DISCRIMINATOR && last_discriminator != discriminator)
2744 {
2745 /* If the discriminator changed, but the line number did not,
2746 output the line table entry with is_stmt false so the
2747 debugger does not treat this as a breakpoint location. */
2748 last_discriminator = discriminator;
2749 *is_stmt = false;
2750 return true;
2751 }
2752
0435312e 2753 return false;
3cf2715d
DE
2754}
2755\f
0304f787
JL
2756/* For each operand in INSN, simplify (subreg (reg)) so that it refers
2757 directly to the desired hard register. */
f5d927c0 2758
0304f787 2759void
6cf9ac28 2760cleanup_subreg_operands (rtx insn)
0304f787 2761{
f62a15e3 2762 int i;
6fb5fa3c 2763 bool changed = false;
6c698a6d 2764 extract_insn_cached (insn);
1ccbefce 2765 for (i = 0; i < recog_data.n_operands; i++)
0304f787 2766 {
2067c116 2767 /* The following test cannot use recog_data.operand when testing
9f4524f2
RE
2768 for a SUBREG: the underlying object might have been changed
2769 already if we are inside a match_operator expression that
2770 matches the else clause. Instead we test the underlying
2771 expression directly. */
2772 if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
6fb5fa3c
DB
2773 {
2774 recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i]);
2775 changed = true;
2776 }
1ccbefce 2777 else if (GET_CODE (recog_data.operand[i]) == PLUS
04337620 2778 || GET_CODE (recog_data.operand[i]) == MULT
3c0cb5de 2779 || MEM_P (recog_data.operand[i]))
6fb5fa3c 2780 recog_data.operand[i] = walk_alter_subreg (recog_data.operand_loc[i], &changed);
0304f787
JL
2781 }
2782
1ccbefce 2783 for (i = 0; i < recog_data.n_dups; i++)
0304f787 2784 {
1ccbefce 2785 if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG)
6fb5fa3c
DB
2786 {
2787 *recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i]);
2788 changed = true;
2789 }
1ccbefce 2790 else if (GET_CODE (*recog_data.dup_loc[i]) == PLUS
04337620 2791 || GET_CODE (*recog_data.dup_loc[i]) == MULT
3c0cb5de 2792 || MEM_P (*recog_data.dup_loc[i]))
6fb5fa3c 2793 *recog_data.dup_loc[i] = walk_alter_subreg (recog_data.dup_loc[i], &changed);
0304f787 2794 }
6fb5fa3c
DB
2795 if (changed)
2796 df_insn_rescan (insn);
0304f787
JL
2797}
2798
3cf2715d
DE
2799/* If X is a SUBREG, replace it with a REG or a MEM,
2800 based on the thing it is a subreg of. */
2801
2802rtx
6cf9ac28 2803alter_subreg (rtx *xp)
3cf2715d 2804{
49d801d3 2805 rtx x = *xp;
b3694847 2806 rtx y = SUBREG_REG (x);
f5963e61 2807
49d801d3
JH
2808 /* simplify_subreg does not remove subreg from volatile references.
2809 We are required to. */
3c0cb5de 2810 if (MEM_P (y))
fd326ba8
UW
2811 {
2812 int offset = SUBREG_BYTE (x);
2813
2814 /* For paradoxical subregs on big-endian machines, SUBREG_BYTE
2815 contains 0 instead of the proper offset. See simplify_subreg. */
2816 if (offset == 0
2817 && GET_MODE_SIZE (GET_MODE (y)) < GET_MODE_SIZE (GET_MODE (x)))
2818 {
2819 int difference = GET_MODE_SIZE (GET_MODE (y))
2820 - GET_MODE_SIZE (GET_MODE (x));
2821 if (WORDS_BIG_ENDIAN)
2822 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
2823 if (BYTES_BIG_ENDIAN)
2824 offset += difference % UNITS_PER_WORD;
2825 }
2826
2827 *xp = adjust_address (y, GET_MODE (x), offset);
2828 }
49d801d3 2829 else
fea54805 2830 {
48c54229 2831 rtx new_rtx = simplify_subreg (GET_MODE (x), y, GET_MODE (y),
fea54805
RK
2832 SUBREG_BYTE (x));
2833
48c54229
KG
2834 if (new_rtx != 0)
2835 *xp = new_rtx;
bbe37912 2836 else if (REG_P (y))
fea54805 2837 {
0bccc606 2838 /* Simplify_subreg can't handle some REG cases, but we have to. */
38ae7651
RS
2839 unsigned int regno;
2840 HOST_WIDE_INT offset;
2841
2842 regno = subreg_regno (x);
2843 if (subreg_lowpart_p (x))
2844 offset = byte_lowpart_offset (GET_MODE (x), GET_MODE (y));
2845 else
2846 offset = SUBREG_BYTE (x);
2847 *xp = gen_rtx_REG_offset (y, GET_MODE (x), regno, offset);
fea54805 2848 }
fea54805
RK
2849 }
2850
49d801d3 2851 return *xp;
3cf2715d
DE
2852}
2853
2854/* Do alter_subreg on all the SUBREGs contained in X. */
2855
2856static rtx
6fb5fa3c 2857walk_alter_subreg (rtx *xp, bool *changed)
3cf2715d 2858{
49d801d3 2859 rtx x = *xp;
3cf2715d
DE
2860 switch (GET_CODE (x))
2861 {
2862 case PLUS:
2863 case MULT:
beed8fc0 2864 case AND:
6fb5fa3c
DB
2865 XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0), changed);
2866 XEXP (x, 1) = walk_alter_subreg (&XEXP (x, 1), changed);
3cf2715d
DE
2867 break;
2868
2869 case MEM:
beed8fc0 2870 case ZERO_EXTEND:
6fb5fa3c 2871 XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0), changed);
3cf2715d
DE
2872 break;
2873
2874 case SUBREG:
6fb5fa3c 2875 *changed = true;
49d801d3 2876 return alter_subreg (xp);
f5d927c0 2877
e9a25f70
JL
2878 default:
2879 break;
3cf2715d
DE
2880 }
2881
5bc72aeb 2882 return *xp;
3cf2715d
DE
2883}
2884\f
2885#ifdef HAVE_cc0
2886
2887/* Given BODY, the body of a jump instruction, alter the jump condition
2888 as required by the bits that are set in cc_status.flags.
2889 Not all of the bits there can be handled at this level in all cases.
2890
2891 The value is normally 0.
2892 1 means that the condition has become always true.
2893 -1 means that the condition has become always false.
2894 2 means that COND has been altered. */
2895
2896static int
6cf9ac28 2897alter_cond (rtx cond)
3cf2715d
DE
2898{
2899 int value = 0;
2900
2901 if (cc_status.flags & CC_REVERSED)
2902 {
2903 value = 2;
2904 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
2905 }
2906
2907 if (cc_status.flags & CC_INVERTED)
2908 {
2909 value = 2;
2910 PUT_CODE (cond, reverse_condition (GET_CODE (cond)));
2911 }
2912
2913 if (cc_status.flags & CC_NOT_POSITIVE)
2914 switch (GET_CODE (cond))
2915 {
2916 case LE:
2917 case LEU:
2918 case GEU:
2919 /* Jump becomes unconditional. */
2920 return 1;
2921
2922 case GT:
2923 case GTU:
2924 case LTU:
2925 /* Jump becomes no-op. */
2926 return -1;
2927
2928 case GE:
2929 PUT_CODE (cond, EQ);
2930 value = 2;
2931 break;
2932
2933 case LT:
2934 PUT_CODE (cond, NE);
2935 value = 2;
2936 break;
f5d927c0 2937
e9a25f70
JL
2938 default:
2939 break;
3cf2715d
DE
2940 }
2941
2942 if (cc_status.flags & CC_NOT_NEGATIVE)
2943 switch (GET_CODE (cond))
2944 {
2945 case GE:
2946 case GEU:
2947 /* Jump becomes unconditional. */
2948 return 1;
2949
2950 case LT:
2951 case LTU:
2952 /* Jump becomes no-op. */
2953 return -1;
2954
2955 case LE:
2956 case LEU:
2957 PUT_CODE (cond, EQ);
2958 value = 2;
2959 break;
2960
2961 case GT:
2962 case GTU:
2963 PUT_CODE (cond, NE);
2964 value = 2;
2965 break;
f5d927c0 2966
e9a25f70
JL
2967 default:
2968 break;
3cf2715d
DE
2969 }
2970
2971 if (cc_status.flags & CC_NO_OVERFLOW)
2972 switch (GET_CODE (cond))
2973 {
2974 case GEU:
2975 /* Jump becomes unconditional. */
2976 return 1;
2977
2978 case LEU:
2979 PUT_CODE (cond, EQ);
2980 value = 2;
2981 break;
2982
2983 case GTU:
2984 PUT_CODE (cond, NE);
2985 value = 2;
2986 break;
2987
2988 case LTU:
2989 /* Jump becomes no-op. */
2990 return -1;
f5d927c0 2991
e9a25f70
JL
2992 default:
2993 break;
3cf2715d
DE
2994 }
2995
2996 if (cc_status.flags & (CC_Z_IN_NOT_N | CC_Z_IN_N))
2997 switch (GET_CODE (cond))
2998 {
e9a25f70 2999 default:
0bccc606 3000 gcc_unreachable ();
3cf2715d
DE
3001
3002 case NE:
3003 PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? GE : LT);
3004 value = 2;
3005 break;
3006
3007 case EQ:
3008 PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? LT : GE);
3009 value = 2;
3010 break;
3011 }
3012
3013 if (cc_status.flags & CC_NOT_SIGNED)
3014 /* The flags are valid if signed condition operators are converted
3015 to unsigned. */
3016 switch (GET_CODE (cond))
3017 {
3018 case LE:
3019 PUT_CODE (cond, LEU);
3020 value = 2;
3021 break;
3022
3023 case LT:
3024 PUT_CODE (cond, LTU);
3025 value = 2;
3026 break;
3027
3028 case GT:
3029 PUT_CODE (cond, GTU);
3030 value = 2;
3031 break;
3032
3033 case GE:
3034 PUT_CODE (cond, GEU);
3035 value = 2;
3036 break;
e9a25f70
JL
3037
3038 default:
3039 break;
3cf2715d
DE
3040 }
3041
3042 return value;
3043}
3044#endif
3045\f
3046/* Report inconsistency between the assembler template and the operands.
3047 In an `asm', it's the user's fault; otherwise, the compiler's fault. */
3048
3049void
4b794eaf 3050output_operand_lossage (const char *cmsgid, ...)
3cf2715d 3051{
a52453cc
PT
3052 char *fmt_string;
3053 char *new_message;
fd478a0a 3054 const char *pfx_str;
e34d07f2 3055 va_list ap;
6cf9ac28 3056
4b794eaf 3057 va_start (ap, cmsgid);
a52453cc 3058
9e637a26 3059 pfx_str = this_is_asm_operands ? _("invalid 'asm': ") : "output_operand: ";
4b794eaf 3060 asprintf (&fmt_string, "%s%s", pfx_str, _(cmsgid));
a52453cc 3061 vasprintf (&new_message, fmt_string, ap);
dd3f0101 3062
3cf2715d 3063 if (this_is_asm_operands)
a52453cc 3064 error_for_asm (this_is_asm_operands, "%s", new_message);
3cf2715d 3065 else
a52453cc
PT
3066 internal_error ("%s", new_message);
3067
3068 free (fmt_string);
3069 free (new_message);
e34d07f2 3070 va_end (ap);
3cf2715d
DE
3071}
3072\f
3073/* Output of assembler code from a template, and its subroutines. */
3074
0d4903b8
RK
3075/* Annotate the assembly with a comment describing the pattern and
3076 alternative used. */
3077
3078static void
6cf9ac28 3079output_asm_name (void)
0d4903b8
RK
3080{
3081 if (debug_insn)
3082 {
3083 int num = INSN_CODE (debug_insn);
3084 fprintf (asm_out_file, "\t%s %d\t%s",
3085 ASM_COMMENT_START, INSN_UID (debug_insn),
3086 insn_data[num].name);
3087 if (insn_data[num].n_alternatives > 1)
3088 fprintf (asm_out_file, "/%d", which_alternative + 1);
3089#ifdef HAVE_ATTR_length
3090 fprintf (asm_out_file, "\t[length = %d]",
3091 get_attr_length (debug_insn));
3092#endif
3093 /* Clear this so only the first assembler insn
3094 of any rtl insn will get the special comment for -dp. */
3095 debug_insn = 0;
3096 }
3097}
3098
998d7deb
RH
3099/* If OP is a REG or MEM and we can find a MEM_EXPR corresponding to it
3100 or its address, return that expr . Set *PADDRESSP to 1 if the expr
c5adc06a
RK
3101 corresponds to the address of the object and 0 if to the object. */
3102
3103static tree
6cf9ac28 3104get_mem_expr_from_op (rtx op, int *paddressp)
c5adc06a 3105{
998d7deb 3106 tree expr;
c5adc06a
RK
3107 int inner_addressp;
3108
3109 *paddressp = 0;
3110
f8cfc6aa 3111 if (REG_P (op))
a560d4d4 3112 return REG_EXPR (op);
3c0cb5de 3113 else if (!MEM_P (op))
c5adc06a
RK
3114 return 0;
3115
998d7deb
RH
3116 if (MEM_EXPR (op) != 0)
3117 return MEM_EXPR (op);
c5adc06a
RK
3118
3119 /* Otherwise we have an address, so indicate it and look at the address. */
3120 *paddressp = 1;
3121 op = XEXP (op, 0);
3122
3123 /* First check if we have a decl for the address, then look at the right side
3124 if it is a PLUS. Otherwise, strip off arithmetic and keep looking.
3125 But don't allow the address to itself be indirect. */
998d7deb
RH
3126 if ((expr = get_mem_expr_from_op (op, &inner_addressp)) && ! inner_addressp)
3127 return expr;
c5adc06a 3128 else if (GET_CODE (op) == PLUS
998d7deb
RH
3129 && (expr = get_mem_expr_from_op (XEXP (op, 1), &inner_addressp)))
3130 return expr;
c5adc06a 3131
481683e1 3132 while (UNARY_P (op)
ec8e098d 3133 || GET_RTX_CLASS (GET_CODE (op)) == RTX_BIN_ARITH)
c5adc06a
RK
3134 op = XEXP (op, 0);
3135
998d7deb
RH
3136 expr = get_mem_expr_from_op (op, &inner_addressp);
3137 return inner_addressp ? 0 : expr;
c5adc06a 3138}
ff81832f 3139
4f9b4029
RK
3140/* Output operand names for assembler instructions. OPERANDS is the
3141 operand vector, OPORDER is the order to write the operands, and NOPS
3142 is the number of operands to write. */
3143
3144static void
6cf9ac28 3145output_asm_operand_names (rtx *operands, int *oporder, int nops)
4f9b4029
RK
3146{
3147 int wrote = 0;
3148 int i;
3149
3150 for (i = 0; i < nops; i++)
3151 {
3152 int addressp;
a560d4d4
JH
3153 rtx op = operands[oporder[i]];
3154 tree expr = get_mem_expr_from_op (op, &addressp);
4f9b4029 3155
a560d4d4
JH
3156 fprintf (asm_out_file, "%c%s",
3157 wrote ? ',' : '\t', wrote ? "" : ASM_COMMENT_START);
3158 wrote = 1;
998d7deb 3159 if (expr)
4f9b4029 3160 {
a560d4d4 3161 fprintf (asm_out_file, "%s",
998d7deb
RH
3162 addressp ? "*" : "");
3163 print_mem_expr (asm_out_file, expr);
4f9b4029
RK
3164 wrote = 1;
3165 }
a560d4d4
JH
3166 else if (REG_P (op) && ORIGINAL_REGNO (op)
3167 && ORIGINAL_REGNO (op) != REGNO (op))
3168 fprintf (asm_out_file, " tmp%i", ORIGINAL_REGNO (op));
4f9b4029
RK
3169 }
3170}
3171
3cf2715d
DE
3172/* Output text from TEMPLATE to the assembler output file,
3173 obeying %-directions to substitute operands taken from
3174 the vector OPERANDS.
3175
3176 %N (for N a digit) means print operand N in usual manner.
3177 %lN means require operand N to be a CODE_LABEL or LABEL_REF
3178 and print the label name with no punctuation.
3179 %cN means require operand N to be a constant
3180 and print the constant expression with no punctuation.
3181 %aN means expect operand N to be a memory address
3182 (not a memory reference!) and print a reference
3183 to that address.
3184 %nN means expect operand N to be a constant
3185 and print a constant expression for minus the value
3186 of the operand, with no other punctuation. */
3187
3188void
48c54229 3189output_asm_insn (const char *templ, rtx *operands)
3cf2715d 3190{
b3694847
SS
3191 const char *p;
3192 int c;
8554d9a4
JJ
3193#ifdef ASSEMBLER_DIALECT
3194 int dialect = 0;
3195#endif
0d4903b8 3196 int oporder[MAX_RECOG_OPERANDS];
4f9b4029 3197 char opoutput[MAX_RECOG_OPERANDS];
0d4903b8 3198 int ops = 0;
3cf2715d
DE
3199
3200 /* An insn may return a null string template
3201 in a case where no assembler code is needed. */
48c54229 3202 if (*templ == 0)
3cf2715d
DE
3203 return;
3204
4f9b4029 3205 memset (opoutput, 0, sizeof opoutput);
48c54229 3206 p = templ;
3cf2715d
DE
3207 putc ('\t', asm_out_file);
3208
3209#ifdef ASM_OUTPUT_OPCODE
3210 ASM_OUTPUT_OPCODE (asm_out_file, p);
3211#endif
3212
b729186a 3213 while ((c = *p++))
3cf2715d
DE
3214 switch (c)
3215 {
3cf2715d 3216 case '\n':
4f9b4029
RK
3217 if (flag_verbose_asm)
3218 output_asm_operand_names (operands, oporder, ops);
0d4903b8
RK
3219 if (flag_print_asm_name)
3220 output_asm_name ();
3221
4f9b4029
RK
3222 ops = 0;
3223 memset (opoutput, 0, sizeof opoutput);
3224
3cf2715d 3225 putc (c, asm_out_file);
cb649530 3226#ifdef ASM_OUTPUT_OPCODE
3cf2715d
DE
3227 while ((c = *p) == '\t')
3228 {
3229 putc (c, asm_out_file);
3230 p++;
3231 }
3232 ASM_OUTPUT_OPCODE (asm_out_file, p);
3cf2715d 3233#endif
cb649530 3234 break;
3cf2715d
DE
3235
3236#ifdef ASSEMBLER_DIALECT
3237 case '{':
b729186a 3238 {
b3694847 3239 int i;
f5d927c0 3240
8554d9a4
JJ
3241 if (dialect)
3242 output_operand_lossage ("nested assembly dialect alternatives");
3243 else
3244 dialect = 1;
3245
b729186a
JL
3246 /* If we want the first dialect, do nothing. Otherwise, skip
3247 DIALECT_NUMBER of strings ending with '|'. */
3248 for (i = 0; i < dialect_number; i++)
3249 {
463a8384 3250 while (*p && *p != '}' && *p++ != '|')
b729186a 3251 ;
463a8384
BS
3252 if (*p == '}')
3253 break;
b729186a
JL
3254 if (*p == '|')
3255 p++;
3256 }
8554d9a4
JJ
3257
3258 if (*p == '\0')
3259 output_operand_lossage ("unterminated assembly dialect alternative");
b729186a 3260 }
3cf2715d
DE
3261 break;
3262
3263 case '|':
8554d9a4
JJ
3264 if (dialect)
3265 {
3266 /* Skip to close brace. */
3267 do
3268 {
3269 if (*p == '\0')
3270 {
3271 output_operand_lossage ("unterminated assembly dialect alternative");
3272 break;
3273 }
ff81832f 3274 }
8554d9a4
JJ
3275 while (*p++ != '}');
3276 dialect = 0;
3277 }
3278 else
3279 putc (c, asm_out_file);
3cf2715d
DE
3280 break;
3281
3282 case '}':
8554d9a4
JJ
3283 if (! dialect)
3284 putc (c, asm_out_file);
3285 dialect = 0;
3cf2715d
DE
3286 break;
3287#endif
3288
3289 case '%':
3290 /* %% outputs a single %. */
3291 if (*p == '%')
3292 {
3293 p++;
3294 putc (c, asm_out_file);
3295 }
3296 /* %= outputs a number which is unique to each insn in the entire
3297 compilation. This is useful for making local labels that are
3298 referred to more than once in a given insn. */
3299 else if (*p == '=')
3300 {
3301 p++;
3302 fprintf (asm_out_file, "%d", insn_counter);
3303 }
3304 /* % followed by a letter and some digits
3305 outputs an operand in a special way depending on the letter.
3306 Letters `acln' are implemented directly.
3307 Other letters are passed to `output_operand' so that
3308 the PRINT_OPERAND macro can define them. */
0df6c2c7 3309 else if (ISALPHA (*p))
3cf2715d
DE
3310 {
3311 int letter = *p++;
c383c15f
GK
3312 unsigned long opnum;
3313 char *endptr;
b0efb46b 3314
c383c15f
GK
3315 opnum = strtoul (p, &endptr, 10);
3316
3317 if (endptr == p)
3318 output_operand_lossage ("operand number missing "
3319 "after %%-letter");
3320 else if (this_is_asm_operands && opnum >= insn_noperands)
3cf2715d
DE
3321 output_operand_lossage ("operand number out of range");
3322 else if (letter == 'l')
c383c15f 3323 output_asm_label (operands[opnum]);
3cf2715d 3324 else if (letter == 'a')
c383c15f 3325 output_address (operands[opnum]);
3cf2715d
DE
3326 else if (letter == 'c')
3327 {
c383c15f
GK
3328 if (CONSTANT_ADDRESS_P (operands[opnum]))
3329 output_addr_const (asm_out_file, operands[opnum]);
3cf2715d 3330 else
c383c15f 3331 output_operand (operands[opnum], 'c');
3cf2715d
DE
3332 }
3333 else if (letter == 'n')
3334 {
481683e1 3335 if (CONST_INT_P (operands[opnum]))
21e3a81b 3336 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC,
c383c15f 3337 - INTVAL (operands[opnum]));
3cf2715d
DE
3338 else
3339 {
3340 putc ('-', asm_out_file);
c383c15f 3341 output_addr_const (asm_out_file, operands[opnum]);
3cf2715d
DE
3342 }
3343 }
3344 else
c383c15f 3345 output_operand (operands[opnum], letter);
f5d927c0 3346
c383c15f 3347 if (!opoutput[opnum])
dc9d0b14 3348 oporder[ops++] = opnum;
c383c15f 3349 opoutput[opnum] = 1;
0d4903b8 3350
c383c15f
GK
3351 p = endptr;
3352 c = *p;
3cf2715d
DE
3353 }
3354 /* % followed by a digit outputs an operand the default way. */
0df6c2c7 3355 else if (ISDIGIT (*p))
3cf2715d 3356 {
c383c15f
GK
3357 unsigned long opnum;
3358 char *endptr;
b0efb46b 3359
c383c15f
GK
3360 opnum = strtoul (p, &endptr, 10);
3361 if (this_is_asm_operands && opnum >= insn_noperands)
3cf2715d
DE
3362 output_operand_lossage ("operand number out of range");
3363 else
c383c15f 3364 output_operand (operands[opnum], 0);
0d4903b8 3365
c383c15f 3366 if (!opoutput[opnum])
dc9d0b14 3367 oporder[ops++] = opnum;
c383c15f 3368 opoutput[opnum] = 1;
4f9b4029 3369
c383c15f
GK
3370 p = endptr;
3371 c = *p;
3cf2715d
DE
3372 }
3373 /* % followed by punctuation: output something for that
3374 punctuation character alone, with no operand.
3375 The PRINT_OPERAND macro decides what is actually done. */
3376#ifdef PRINT_OPERAND_PUNCT_VALID_P
f5d927c0 3377 else if (PRINT_OPERAND_PUNCT_VALID_P ((unsigned char) *p))
3cf2715d
DE
3378 output_operand (NULL_RTX, *p++);
3379#endif
3380 else
3381 output_operand_lossage ("invalid %%-code");
3382 break;
3383
3384 default:
3385 putc (c, asm_out_file);
3386 }
3387
0d4903b8
RK
3388 /* Write out the variable names for operands, if we know them. */
3389 if (flag_verbose_asm)
4f9b4029 3390 output_asm_operand_names (operands, oporder, ops);
0d4903b8
RK
3391 if (flag_print_asm_name)
3392 output_asm_name ();
3cf2715d
DE
3393
3394 putc ('\n', asm_out_file);
3395}
3396\f
3397/* Output a LABEL_REF, or a bare CODE_LABEL, as an assembler symbol. */
3398
3399void
6cf9ac28 3400output_asm_label (rtx x)
3cf2715d
DE
3401{
3402 char buf[256];
3403
3404 if (GET_CODE (x) == LABEL_REF)
be1bb652 3405 x = XEXP (x, 0);
4b4bf941
JQ
3406 if (LABEL_P (x)
3407 || (NOTE_P (x)
a38e7aa5 3408 && NOTE_KIND (x) == NOTE_INSN_DELETED_LABEL))
3cf2715d
DE
3409 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
3410 else
9e637a26 3411 output_operand_lossage ("'%%l' operand isn't a label");
3cf2715d
DE
3412
3413 assemble_name (asm_out_file, buf);
3414}
3415
a7fe25b8
JJ
3416/* Helper rtx-iteration-function for mark_symbol_refs_as_used and
3417 output_operand. Marks SYMBOL_REFs as referenced through use of
3418 assemble_external. */
c70d0414
HPN
3419
3420static int
3421mark_symbol_ref_as_used (rtx *xp, void *dummy ATTRIBUTE_UNUSED)
3422{
3423 rtx x = *xp;
3424
3425 /* If we have a used symbol, we may have to emit assembly
3426 annotations corresponding to whether the symbol is external, weak
3427 or has non-default visibility. */
3428 if (GET_CODE (x) == SYMBOL_REF)
3429 {
3430 tree t;
3431
3432 t = SYMBOL_REF_DECL (x);
3433 if (t)
3434 assemble_external (t);
3435
3436 return -1;
3437 }
3438
3439 return 0;
3440}
3441
a7fe25b8
JJ
3442/* Marks SYMBOL_REFs in x as referenced through use of assemble_external. */
3443
3444void
3445mark_symbol_refs_as_used (rtx x)
3446{
3447 for_each_rtx (&x, mark_symbol_ref_as_used, NULL);
3448}
3449
3cf2715d
DE
3450/* Print operand X using machine-dependent assembler syntax.
3451 The macro PRINT_OPERAND is defined just to control this function.
3452 CODE is a non-digit that preceded the operand-number in the % spec,
3453 such as 'z' if the spec was `%z3'. CODE is 0 if there was no char
3454 between the % and the digits.
3455 When CODE is a non-letter, X is 0.
3456
3457 The meanings of the letters are machine-dependent and controlled
3458 by PRINT_OPERAND. */
3459
3460static void
6cf9ac28 3461output_operand (rtx x, int code ATTRIBUTE_UNUSED)
3cf2715d
DE
3462{
3463 if (x && GET_CODE (x) == SUBREG)
49d801d3 3464 x = alter_subreg (&x);
3cf2715d 3465
04c7ae48 3466 /* X must not be a pseudo reg. */
0bccc606 3467 gcc_assert (!x || !REG_P (x) || REGNO (x) < FIRST_PSEUDO_REGISTER);
3cf2715d
DE
3468
3469 PRINT_OPERAND (asm_out_file, x, code);
c70d0414
HPN
3470
3471 if (x == NULL_RTX)
3472 return;
3473
3474 for_each_rtx (&x, mark_symbol_ref_as_used, NULL);
3cf2715d
DE
3475}
3476
3477/* Print a memory reference operand for address X
3478 using machine-dependent assembler syntax.
3479 The macro PRINT_OPERAND_ADDRESS exists just to control this function. */
3480
3481void
6cf9ac28 3482output_address (rtx x)
3cf2715d 3483{
6fb5fa3c
DB
3484 bool changed = false;
3485 walk_alter_subreg (&x, &changed);
3cf2715d
DE
3486 PRINT_OPERAND_ADDRESS (asm_out_file, x);
3487}
3488\f
3489/* Print an integer constant expression in assembler syntax.
3490 Addition and subtraction are the only arithmetic
3491 that may appear in these expressions. */
3492
3493void
6cf9ac28 3494output_addr_const (FILE *file, rtx x)
3cf2715d
DE
3495{
3496 char buf[256];
3497
3498 restart:
3499 switch (GET_CODE (x))
3500 {
3501 case PC:
eac50d7a 3502 putc ('.', file);
3cf2715d
DE
3503 break;
3504
3505 case SYMBOL_REF:
21dad7e6 3506 if (SYMBOL_REF_DECL (x))
0462b9b5
EB
3507 {
3508 mark_decl_referenced (SYMBOL_REF_DECL (x));
3509 assemble_external (SYMBOL_REF_DECL (x));
3510 }
99c8c61c
AO
3511#ifdef ASM_OUTPUT_SYMBOL_REF
3512 ASM_OUTPUT_SYMBOL_REF (file, x);
3513#else
3cf2715d 3514 assemble_name (file, XSTR (x, 0));
99c8c61c 3515#endif
3cf2715d
DE
3516 break;
3517
3518 case LABEL_REF:
422be3c3
AO
3519 x = XEXP (x, 0);
3520 /* Fall through. */
3cf2715d
DE
3521 case CODE_LABEL:
3522 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2f0b7af6
GK
3523#ifdef ASM_OUTPUT_LABEL_REF
3524 ASM_OUTPUT_LABEL_REF (file, buf);
3525#else
3cf2715d 3526 assemble_name (file, buf);
2f0b7af6 3527#endif
3cf2715d
DE
3528 break;
3529
3530 case CONST_INT:
21e3a81b 3531 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
3cf2715d
DE
3532 break;
3533
3534 case CONST:
3535 /* This used to output parentheses around the expression,
3536 but that does not work on the 386 (either ATT or BSD assembler). */
3537 output_addr_const (file, XEXP (x, 0));
3538 break;
3539
3540 case CONST_DOUBLE:
3541 if (GET_MODE (x) == VOIDmode)
3542 {
3543 /* We can use %d if the number is one word and positive. */
3544 if (CONST_DOUBLE_HIGH (x))
21e3a81b 3545 fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX,
3d57d7ce
DK
3546 (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (x),
3547 (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x));
f5d927c0 3548 else if (CONST_DOUBLE_LOW (x) < 0)
3d57d7ce
DK
3549 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
3550 (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x));
3cf2715d 3551 else
21e3a81b 3552 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
3cf2715d
DE
3553 }
3554 else
3555 /* We can't handle floating point constants;
3556 PRINT_OPERAND must handle them. */
3557 output_operand_lossage ("floating constant misused");
3558 break;
3559
14c931f1 3560 case CONST_FIXED:
3d57d7ce
DK
3561 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
3562 (unsigned HOST_WIDE_INT) CONST_FIXED_VALUE_LOW (x));
14c931f1
CF
3563 break;
3564
3cf2715d
DE
3565 case PLUS:
3566 /* Some assemblers need integer constants to appear last (eg masm). */
481683e1 3567 if (CONST_INT_P (XEXP (x, 0)))
3cf2715d
DE
3568 {
3569 output_addr_const (file, XEXP (x, 1));
3570 if (INTVAL (XEXP (x, 0)) >= 0)
3571 fprintf (file, "+");
3572 output_addr_const (file, XEXP (x, 0));
3573 }
3574 else
3575 {
3576 output_addr_const (file, XEXP (x, 0));
481683e1 3577 if (!CONST_INT_P (XEXP (x, 1))
08106825 3578 || INTVAL (XEXP (x, 1)) >= 0)
3cf2715d
DE
3579 fprintf (file, "+");
3580 output_addr_const (file, XEXP (x, 1));
3581 }
3582 break;
3583
3584 case MINUS:
3585 /* Avoid outputting things like x-x or x+5-x,
3586 since some assemblers can't handle that. */
3587 x = simplify_subtraction (x);
3588 if (GET_CODE (x) != MINUS)
3589 goto restart;
3590
3591 output_addr_const (file, XEXP (x, 0));
3592 fprintf (file, "-");
481683e1 3593 if ((CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0)
301d03af
RS
3594 || GET_CODE (XEXP (x, 1)) == PC
3595 || GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
3596 output_addr_const (file, XEXP (x, 1));
3597 else
3cf2715d 3598 {
17b53c33 3599 fputs (targetm.asm_out.open_paren, file);
3cf2715d 3600 output_addr_const (file, XEXP (x, 1));
17b53c33 3601 fputs (targetm.asm_out.close_paren, file);
3cf2715d 3602 }
3cf2715d
DE
3603 break;
3604
3605 case ZERO_EXTEND:
3606 case SIGN_EXTEND:
fdf473ae 3607 case SUBREG:
c01e4479 3608 case TRUNCATE:
3cf2715d
DE
3609 output_addr_const (file, XEXP (x, 0));
3610 break;
3611
3612 default:
422be3c3
AO
3613#ifdef OUTPUT_ADDR_CONST_EXTRA
3614 OUTPUT_ADDR_CONST_EXTRA (file, x, fail);
3615 break;
3616
3617 fail:
3618#endif
3cf2715d
DE
3619 output_operand_lossage ("invalid expression as operand");
3620 }
3621}
3622\f
3623/* A poor man's fprintf, with the added features of %I, %R, %L, and %U.
3624 %R prints the value of REGISTER_PREFIX.
3625 %L prints the value of LOCAL_LABEL_PREFIX.
3626 %U prints the value of USER_LABEL_PREFIX.
3627 %I prints the value of IMMEDIATE_PREFIX.
3628 %O runs ASM_OUTPUT_OPCODE to transform what follows in the string.
b1721339 3629 Also supported are %d, %i, %u, %x, %X, %o, %c, %s and %%.
3cf2715d
DE
3630
3631 We handle alternate assembler dialects here, just like output_asm_insn. */
3632
3633void
e34d07f2 3634asm_fprintf (FILE *file, const char *p, ...)
3cf2715d 3635{
3cf2715d
DE
3636 char buf[10];
3637 char *q, c;
e34d07f2 3638 va_list argptr;
6cf9ac28 3639
e34d07f2 3640 va_start (argptr, p);
3cf2715d
DE
3641
3642 buf[0] = '%';
3643
b729186a 3644 while ((c = *p++))
3cf2715d
DE
3645 switch (c)
3646 {
3647#ifdef ASSEMBLER_DIALECT
3648 case '{':
b729186a
JL
3649 {
3650 int i;
3cf2715d 3651
b729186a
JL
3652 /* If we want the first dialect, do nothing. Otherwise, skip
3653 DIALECT_NUMBER of strings ending with '|'. */
3654 for (i = 0; i < dialect_number; i++)
3655 {
3656 while (*p && *p++ != '|')
3657 ;
3658
3659 if (*p == '|')
3660 p++;
f5d927c0 3661 }
b729186a 3662 }
3cf2715d
DE
3663 break;
3664
3665 case '|':
3666 /* Skip to close brace. */
3667 while (*p && *p++ != '}')
3668 ;
3669 break;
3670
3671 case '}':
3672 break;
3673#endif
3674
3675 case '%':
3676 c = *p++;
3677 q = &buf[1];
b1721339
KG
3678 while (strchr ("-+ #0", c))
3679 {
3680 *q++ = c;
3681 c = *p++;
3682 }
0df6c2c7 3683 while (ISDIGIT (c) || c == '.')
3cf2715d
DE
3684 {
3685 *q++ = c;
3686 c = *p++;
3687 }
3688 switch (c)
3689 {
3690 case '%':
b1721339 3691 putc ('%', file);
3cf2715d
DE
3692 break;
3693
3694 case 'd': case 'i': case 'u':
b1721339
KG
3695 case 'x': case 'X': case 'o':
3696 case 'c':
3cf2715d
DE
3697 *q++ = c;
3698 *q = 0;
3699 fprintf (file, buf, va_arg (argptr, int));
3700 break;
3701
3702 case 'w':
b1721339
KG
3703 /* This is a prefix to the 'd', 'i', 'u', 'x', 'X', and
3704 'o' cases, but we do not check for those cases. It
3705 means that the value is a HOST_WIDE_INT, which may be
3706 either `long' or `long long'. */
85f015e1
KG
3707 memcpy (q, HOST_WIDE_INT_PRINT, strlen (HOST_WIDE_INT_PRINT));
3708 q += strlen (HOST_WIDE_INT_PRINT);
3cf2715d
DE
3709 *q++ = *p++;
3710 *q = 0;
3711 fprintf (file, buf, va_arg (argptr, HOST_WIDE_INT));
3712 break;
3713
3714 case 'l':
3715 *q++ = c;
b1721339
KG
3716#ifdef HAVE_LONG_LONG
3717 if (*p == 'l')
3718 {
3719 *q++ = *p++;
3720 *q++ = *p++;
3721 *q = 0;
3722 fprintf (file, buf, va_arg (argptr, long long));
3723 }
3724 else
3725#endif
3726 {
3727 *q++ = *p++;
3728 *q = 0;
3729 fprintf (file, buf, va_arg (argptr, long));
3730 }
6cf9ac28 3731
3cf2715d
DE
3732 break;
3733
3734 case 's':
3735 *q++ = c;
3736 *q = 0;
3737 fprintf (file, buf, va_arg (argptr, char *));
3738 break;
3739
3740 case 'O':
3741#ifdef ASM_OUTPUT_OPCODE
3742 ASM_OUTPUT_OPCODE (asm_out_file, p);
3743#endif
3744 break;
3745
3746 case 'R':
3747#ifdef REGISTER_PREFIX
3748 fprintf (file, "%s", REGISTER_PREFIX);
3749#endif
3750 break;
3751
3752 case 'I':
3753#ifdef IMMEDIATE_PREFIX
3754 fprintf (file, "%s", IMMEDIATE_PREFIX);
3755#endif
3756 break;
3757
3758 case 'L':
3759#ifdef LOCAL_LABEL_PREFIX
3760 fprintf (file, "%s", LOCAL_LABEL_PREFIX);
3761#endif
3762 break;
3763
3764 case 'U':
19283265 3765 fputs (user_label_prefix, file);
3cf2715d
DE
3766 break;
3767
fe0503ea 3768#ifdef ASM_FPRINTF_EXTENSIONS
7ef0daad 3769 /* Uppercase letters are reserved for general use by asm_fprintf
fe0503ea
NC
3770 and so are not available to target specific code. In order to
3771 prevent the ASM_FPRINTF_EXTENSIONS macro from using them then,
3772 they are defined here. As they get turned into real extensions
3773 to asm_fprintf they should be removed from this list. */
3774 case 'A': case 'B': case 'C': case 'D': case 'E':
3775 case 'F': case 'G': case 'H': case 'J': case 'K':
3776 case 'M': case 'N': case 'P': case 'Q': case 'S':
3777 case 'T': case 'V': case 'W': case 'Y': case 'Z':
3778 break;
f5d927c0 3779
fe0503ea
NC
3780 ASM_FPRINTF_EXTENSIONS (file, argptr, p)
3781#endif
3cf2715d 3782 default:
0bccc606 3783 gcc_unreachable ();
3cf2715d
DE
3784 }
3785 break;
3786
3787 default:
b1721339 3788 putc (c, file);
3cf2715d 3789 }
e34d07f2 3790 va_end (argptr);
3cf2715d
DE
3791}
3792\f
3793/* Split up a CONST_DOUBLE or integer constant rtx
3794 into two rtx's for single words,
3795 storing in *FIRST the word that comes first in memory in the target
3796 and in *SECOND the other. */
3797
3798void
6cf9ac28 3799split_double (rtx value, rtx *first, rtx *second)
3cf2715d 3800{
481683e1 3801 if (CONST_INT_P (value))
3cf2715d 3802 {
5a1a6efd 3803 if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
f76b9db2 3804 {
5a1a6efd 3805 /* In this case the CONST_INT holds both target words.
27eef9ce
JC
3806 Extract the bits from it into two word-sized pieces.
3807 Sign extend each half to HOST_WIDE_INT. */
7f251dee
AO
3808 unsigned HOST_WIDE_INT low, high;
3809 unsigned HOST_WIDE_INT mask, sign_bit, sign_extend;
3810
3811 /* Set sign_bit to the most significant bit of a word. */
3812 sign_bit = 1;
3813 sign_bit <<= BITS_PER_WORD - 1;
3814
3815 /* Set mask so that all bits of the word are set. We could
3816 have used 1 << BITS_PER_WORD instead of basing the
3817 calculation on sign_bit. However, on machines where
3818 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
3819 compiler warning, even though the code would never be
3820 executed. */
3821 mask = sign_bit << 1;
3822 mask--;
3823
3824 /* Set sign_extend as any remaining bits. */
3825 sign_extend = ~mask;
f5d927c0 3826
7f251dee
AO
3827 /* Pick the lower word and sign-extend it. */
3828 low = INTVAL (value);
3829 low &= mask;
3830 if (low & sign_bit)
3831 low |= sign_extend;
3832
3833 /* Pick the higher word, shifted to the least significant
3834 bits, and sign-extend it. */
3835 high = INTVAL (value);
3836 high >>= BITS_PER_WORD - 1;
3837 high >>= 1;
3838 high &= mask;
3839 if (high & sign_bit)
3840 high |= sign_extend;
3841
3842 /* Store the words in the target machine order. */
5a1a6efd
RK
3843 if (WORDS_BIG_ENDIAN)
3844 {
7f251dee
AO
3845 *first = GEN_INT (high);
3846 *second = GEN_INT (low);
5a1a6efd
RK
3847 }
3848 else
3849 {
7f251dee
AO
3850 *first = GEN_INT (low);
3851 *second = GEN_INT (high);
5a1a6efd 3852 }
f76b9db2
ILT
3853 }
3854 else
3855 {
5a1a6efd
RK
3856 /* The rule for using CONST_INT for a wider mode
3857 is that we regard the value as signed.
3858 So sign-extend it. */
3859 rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx);
3860 if (WORDS_BIG_ENDIAN)
3861 {
3862 *first = high;
3863 *second = value;
3864 }
3865 else
3866 {
3867 *first = value;
3868 *second = high;
3869 }
f76b9db2 3870 }
3cf2715d
DE
3871 }
3872 else if (GET_CODE (value) != CONST_DOUBLE)
3873 {
f76b9db2
ILT
3874 if (WORDS_BIG_ENDIAN)
3875 {
3876 *first = const0_rtx;
3877 *second = value;
3878 }
3879 else
3880 {
3881 *first = value;
3882 *second = const0_rtx;
3883 }
3cf2715d
DE
3884 }
3885 else if (GET_MODE (value) == VOIDmode
3886 /* This is the old way we did CONST_DOUBLE integers. */
3887 || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT)
3888 {
3889 /* In an integer, the words are defined as most and least significant.
3890 So order them by the target's convention. */
f76b9db2
ILT
3891 if (WORDS_BIG_ENDIAN)
3892 {
3893 *first = GEN_INT (CONST_DOUBLE_HIGH (value));
3894 *second = GEN_INT (CONST_DOUBLE_LOW (value));
3895 }
3896 else
3897 {
3898 *first = GEN_INT (CONST_DOUBLE_LOW (value));
3899 *second = GEN_INT (CONST_DOUBLE_HIGH (value));
3900 }
3cf2715d
DE
3901 }
3902 else
3903 {
f5d927c0
KH
3904 REAL_VALUE_TYPE r;
3905 long l[2];
3cf2715d
DE
3906 REAL_VALUE_FROM_CONST_DOUBLE (r, value);
3907
3908 /* Note, this converts the REAL_VALUE_TYPE to the target's
3909 format, splits up the floating point double and outputs
3910 exactly 32 bits of it into each of l[0] and l[1] --
0f41302f 3911 not necessarily BITS_PER_WORD bits. */
3cf2715d
DE
3912 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
3913
b5a3eb84
JW
3914 /* If 32 bits is an entire word for the target, but not for the host,
3915 then sign-extend on the host so that the number will look the same
3916 way on the host that it would on the target. See for instance
3917 simplify_unary_operation. The #if is needed to avoid compiler
3918 warnings. */
3919
3920#if HOST_BITS_PER_LONG > 32
3921 if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32)
3922 {
3923 if (l[0] & ((long) 1 << 31))
3924 l[0] |= ((long) (-1) << 32);
3925 if (l[1] & ((long) 1 << 31))
3926 l[1] |= ((long) (-1) << 32);
3927 }
3928#endif
3929
3e95a7cb
ZW
3930 *first = GEN_INT (l[0]);
3931 *second = GEN_INT (l[1]);
3cf2715d
DE
3932 }
3933}
3934\f
3935/* Return nonzero if this function has no function calls. */
3936
3937int
6cf9ac28 3938leaf_function_p (void)
3cf2715d
DE
3939{
3940 rtx insn;
b660f82f 3941 rtx link;
3cf2715d 3942
e3b5732b 3943 if (crtl->profile || profile_arc_flag)
3cf2715d
DE
3944 return 0;
3945
3946 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
3947 {
4b4bf941 3948 if (CALL_P (insn)
7d167afd 3949 && ! SIBLING_CALL_P (insn))
3cf2715d 3950 return 0;
4b4bf941 3951 if (NONJUMP_INSN_P (insn)
3cf2715d 3952 && GET_CODE (PATTERN (insn)) == SEQUENCE
4b4bf941 3953 && CALL_P (XVECEXP (PATTERN (insn), 0, 0))
0a1c58a2 3954 && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0)))
3cf2715d
DE
3955 return 0;
3956 }
cb91fab0 3957 for (link = crtl->epilogue_delay_list;
b660f82f
JW
3958 link;
3959 link = XEXP (link, 1))
3cf2715d 3960 {
b660f82f
JW
3961 insn = XEXP (link, 0);
3962
4b4bf941 3963 if (CALL_P (insn)
7d167afd 3964 && ! SIBLING_CALL_P (insn))
3cf2715d 3965 return 0;
4b4bf941 3966 if (NONJUMP_INSN_P (insn)
b660f82f 3967 && GET_CODE (PATTERN (insn)) == SEQUENCE
4b4bf941 3968 && CALL_P (XVECEXP (PATTERN (insn), 0, 0))
b660f82f 3969 && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0)))
3cf2715d
DE
3970 return 0;
3971 }
3972
3973 return 1;
3974}
3975
09da1532 3976/* Return 1 if branch is a forward branch.
ef6257cd
JH
3977 Uses insn_shuid array, so it works only in the final pass. May be used by
3978 output templates to customary add branch prediction hints.
3979 */
3980int
6cf9ac28 3981final_forward_branch_p (rtx insn)
ef6257cd
JH
3982{
3983 int insn_id, label_id;
b0efb46b 3984
0bccc606 3985 gcc_assert (uid_shuid);
ef6257cd
JH
3986 insn_id = INSN_SHUID (insn);
3987 label_id = INSN_SHUID (JUMP_LABEL (insn));
3988 /* We've hit some insns that does not have id information available. */
0bccc606 3989 gcc_assert (insn_id && label_id);
ef6257cd
JH
3990 return insn_id < label_id;
3991}
3992
3cf2715d
DE
3993/* On some machines, a function with no call insns
3994 can run faster if it doesn't create its own register window.
3995 When output, the leaf function should use only the "output"
3996 registers. Ordinarily, the function would be compiled to use
3997 the "input" registers to find its arguments; it is a candidate
3998 for leaf treatment if it uses only the "input" registers.
3999 Leaf function treatment means renumbering so the function
4000 uses the "output" registers instead. */
4001
4002#ifdef LEAF_REGISTERS
4003
3cf2715d
DE
4004/* Return 1 if this function uses only the registers that can be
4005 safely renumbered. */
4006
4007int
6cf9ac28 4008only_leaf_regs_used (void)
3cf2715d
DE
4009{
4010 int i;
4977bab6 4011 const char *const permitted_reg_in_leaf_functions = LEAF_REGISTERS;
3cf2715d
DE
4012
4013 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6fb5fa3c 4014 if ((df_regs_ever_live_p (i) || global_regs[i])
e5e809f4
JL
4015 && ! permitted_reg_in_leaf_functions[i])
4016 return 0;
4017
e3b5732b 4018 if (crtl->uses_pic_offset_table
e5e809f4 4019 && pic_offset_table_rtx != 0
f8cfc6aa 4020 && REG_P (pic_offset_table_rtx)
e5e809f4
JL
4021 && ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)])
4022 return 0;
4023
3cf2715d
DE
4024 return 1;
4025}
4026
4027/* Scan all instructions and renumber all registers into those
4028 available in leaf functions. */
4029
4030static void
6cf9ac28 4031leaf_renumber_regs (rtx first)
3cf2715d
DE
4032{
4033 rtx insn;
4034
4035 /* Renumber only the actual patterns.
4036 The reg-notes can contain frame pointer refs,
4037 and renumbering them could crash, and should not be needed. */
4038 for (insn = first; insn; insn = NEXT_INSN (insn))
2c3c49de 4039 if (INSN_P (insn))
3cf2715d 4040 leaf_renumber_regs_insn (PATTERN (insn));
cb91fab0 4041 for (insn = crtl->epilogue_delay_list;
f5d927c0
KH
4042 insn;
4043 insn = XEXP (insn, 1))
2c3c49de 4044 if (INSN_P (XEXP (insn, 0)))
3cf2715d
DE
4045 leaf_renumber_regs_insn (PATTERN (XEXP (insn, 0)));
4046}
4047
4048/* Scan IN_RTX and its subexpressions, and renumber all regs into those
4049 available in leaf functions. */
4050
4051void
6cf9ac28 4052leaf_renumber_regs_insn (rtx in_rtx)
3cf2715d 4053{
b3694847
SS
4054 int i, j;
4055 const char *format_ptr;
3cf2715d
DE
4056
4057 if (in_rtx == 0)
4058 return;
4059
4060 /* Renumber all input-registers into output-registers.
4061 renumbered_regs would be 1 for an output-register;
4062 they */
4063
f8cfc6aa 4064 if (REG_P (in_rtx))
3cf2715d
DE
4065 {
4066 int newreg;
4067
4068 /* Don't renumber the same reg twice. */
4069 if (in_rtx->used)
4070 return;
4071
4072 newreg = REGNO (in_rtx);
4073 /* Don't try to renumber pseudo regs. It is possible for a pseudo reg
4074 to reach here as part of a REG_NOTE. */
4075 if (newreg >= FIRST_PSEUDO_REGISTER)
4076 {
4077 in_rtx->used = 1;
4078 return;
4079 }
4080 newreg = LEAF_REG_REMAP (newreg);
0bccc606 4081 gcc_assert (newreg >= 0);
6fb5fa3c
DB
4082 df_set_regs_ever_live (REGNO (in_rtx), false);
4083 df_set_regs_ever_live (newreg, true);
4084 SET_REGNO (in_rtx, newreg);
3cf2715d
DE
4085 in_rtx->used = 1;
4086 }
4087
2c3c49de 4088 if (INSN_P (in_rtx))
3cf2715d
DE
4089 {
4090 /* Inside a SEQUENCE, we find insns.
4091 Renumber just the patterns of these insns,
4092 just as we do for the top-level insns. */
4093 leaf_renumber_regs_insn (PATTERN (in_rtx));
4094 return;
4095 }
4096
4097 format_ptr = GET_RTX_FORMAT (GET_CODE (in_rtx));
4098
4099 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (in_rtx)); i++)
4100 switch (*format_ptr++)
4101 {
4102 case 'e':
4103 leaf_renumber_regs_insn (XEXP (in_rtx, i));
4104 break;
4105
4106 case 'E':
4107 if (NULL != XVEC (in_rtx, i))
4108 {
4109 for (j = 0; j < XVECLEN (in_rtx, i); j++)
4110 leaf_renumber_regs_insn (XVECEXP (in_rtx, i, j));
4111 }
4112 break;
4113
4114 case 'S':
4115 case 's':
4116 case '0':
4117 case 'i':
4118 case 'w':
4119 case 'n':
4120 case 'u':
4121 break;
4122
4123 default:
0bccc606 4124 gcc_unreachable ();
3cf2715d
DE
4125 }
4126}
4127#endif
6a08f7b3
DP
4128
4129
4130/* When -gused is used, emit debug info for only used symbols. But in
4131 addition to the standard intercepted debug_hooks there are some direct
4132 calls into this file, i.e., dbxout_symbol, dbxout_parms, and dbxout_reg_params.
4133 Those routines may also be called from a higher level intercepted routine. So
4134 to prevent recording data for an inner call to one of these for an intercept,
5d3cc252 4135 we maintain an intercept nesting counter (debug_nesting). We only save the
6a08f7b3
DP
4136 intercepted arguments if the nesting is 1. */
4137int debug_nesting = 0;
4138
4139static tree *symbol_queue;
4140int symbol_queue_index = 0;
4141static int symbol_queue_size = 0;
4142
4143/* Generate the symbols for any queued up type symbols we encountered
4144 while generating the type info for some originally used symbol.
4145 This might generate additional entries in the queue. Only when
4146 the nesting depth goes to 0 is this routine called. */
4147
4148void
6cf9ac28 4149debug_flush_symbol_queue (void)
6a08f7b3
DP
4150{
4151 int i;
6cf9ac28 4152
6a08f7b3
DP
4153 /* Make sure that additionally queued items are not flushed
4154 prematurely. */
6cf9ac28 4155
6a08f7b3 4156 ++debug_nesting;
6cf9ac28 4157
6a08f7b3
DP
4158 for (i = 0; i < symbol_queue_index; ++i)
4159 {
b0efb46b 4160 /* If we pushed queued symbols then such symbols must be
6a08f7b3
DP
4161 output no matter what anyone else says. Specifically,
4162 we need to make sure dbxout_symbol() thinks the symbol was
4163 used and also we need to override TYPE_DECL_SUPPRESS_DEBUG
4164 which may be set for outside reasons. */
4165 int saved_tree_used = TREE_USED (symbol_queue[i]);
4166 int saved_suppress_debug = TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]);
4167 TREE_USED (symbol_queue[i]) = 1;
4168 TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]) = 0;
4169
4170#ifdef DBX_DEBUGGING_INFO
4171 dbxout_symbol (symbol_queue[i], 0);
4172#endif
4173
4174 TREE_USED (symbol_queue[i]) = saved_tree_used;
4175 TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]) = saved_suppress_debug;
4176 }
4177
4178 symbol_queue_index = 0;
6cf9ac28 4179 --debug_nesting;
6a08f7b3
DP
4180}
4181
4182/* Queue a type symbol needed as part of the definition of a decl
4183 symbol. These symbols are generated when debug_flush_symbol_queue()
4184 is called. */
4185
6cf9ac28 4186void
6a08f7b3
DP
4187debug_queue_symbol (tree decl)
4188{
6cf9ac28 4189 if (symbol_queue_index >= symbol_queue_size)
6a08f7b3
DP
4190 {
4191 symbol_queue_size += 10;
1b4572a8 4192 symbol_queue = XRESIZEVEC (tree, symbol_queue, symbol_queue_size);
6a08f7b3
DP
4193 }
4194
4195 symbol_queue[symbol_queue_index++] = decl;
6cf9ac28 4196}
6a08f7b3 4197
f9da5064 4198/* Free symbol queue. */
6a08f7b3 4199void
6cf9ac28 4200debug_free_queue (void)
6a08f7b3
DP
4201{
4202 if (symbol_queue)
4203 {
4204 free (symbol_queue);
4205 symbol_queue = NULL;
4206 symbol_queue_size = 0;
4207 }
4208}
ef330312
PB
4209\f
4210/* Turn the RTL into assembly. */
c2924966 4211static unsigned int
ef330312
PB
4212rest_of_handle_final (void)
4213{
4214 rtx x;
4215 const char *fnname;
4216
4217 /* Get the function's name, as described by its RTL. This may be
4218 different from the DECL_NAME name used in the source file. */
4219
4220 x = DECL_RTL (current_function_decl);
4221 gcc_assert (MEM_P (x));
4222 x = XEXP (x, 0);
4223 gcc_assert (GET_CODE (x) == SYMBOL_REF);
4224 fnname = XSTR (x, 0);
4225
4226 assemble_start_function (current_function_decl, fnname);
4227 final_start_function (get_insns (), asm_out_file, optimize);
4228 final (get_insns (), asm_out_file, optimize);
4229 final_end_function ();
4230
4231#ifdef TARGET_UNWIND_INFO
4232 /* ??? The IA-64 ".handlerdata" directive must be issued before
4233 the ".endp" directive that closes the procedure descriptor. */
22ba88ef 4234 output_function_exception_table (fnname);
ef330312
PB
4235#endif
4236
4237 assemble_end_function (current_function_decl, fnname);
4238
4239#ifndef TARGET_UNWIND_INFO
4240 /* Otherwise, it feels unclean to switch sections in the middle. */
22ba88ef 4241 output_function_exception_table (fnname);
ef330312
PB
4242#endif
4243
4244 user_defined_section_attribute = false;
4245
6fb5fa3c
DB
4246 /* Free up reg info memory. */
4247 free_reg_info ();
4248
ef330312
PB
4249 if (! quiet_flag)
4250 fflush (asm_out_file);
4251
ef330312
PB
4252 /* Write DBX symbols if requested. */
4253
4254 /* Note that for those inline functions where we don't initially
4255 know for certain that we will be generating an out-of-line copy,
4256 the first invocation of this routine (rest_of_compilation) will
4257 skip over this code by doing a `goto exit_rest_of_compilation;'.
4258 Later on, wrapup_global_declarations will (indirectly) call
4259 rest_of_compilation again for those inline functions that need
4260 to have out-of-line copies generated. During that call, we
4261 *will* be routed past here. */
4262
4263 timevar_push (TV_SYMOUT);
4264 (*debug_hooks->function_decl) (current_function_decl);
4265 timevar_pop (TV_SYMOUT);
6b20f353
DS
4266
4267 /* Release the blocks that are linked to DECL_INITIAL() to free the memory. */
4268 DECL_INITIAL (current_function_decl) = error_mark_node;
4269
395a40e0
JH
4270 if (DECL_STATIC_CONSTRUCTOR (current_function_decl)
4271 && targetm.have_ctors_dtors)
4272 targetm.asm_out.constructor (XEXP (DECL_RTL (current_function_decl), 0),
4273 decl_init_priority_lookup
4274 (current_function_decl));
4275 if (DECL_STATIC_DESTRUCTOR (current_function_decl)
4276 && targetm.have_ctors_dtors)
4277 targetm.asm_out.destructor (XEXP (DECL_RTL (current_function_decl), 0),
4278 decl_fini_priority_lookup
4279 (current_function_decl));
c2924966 4280 return 0;
ef330312
PB
4281}
4282
8ddbbcae 4283struct rtl_opt_pass pass_final =
ef330312 4284{
8ddbbcae
JH
4285 {
4286 RTL_PASS,
ef330312
PB
4287 NULL, /* name */
4288 NULL, /* gate */
4289 rest_of_handle_final, /* execute */
4290 NULL, /* sub */
4291 NULL, /* next */
4292 0, /* static_pass_number */
4293 TV_FINAL, /* tv_id */
4294 0, /* properties_required */
4295 0, /* properties_provided */
4296 0, /* properties_destroyed */
4297 0, /* todo_flags_start */
8ddbbcae
JH
4298 TODO_ggc_collect /* todo_flags_finish */
4299 }
ef330312
PB
4300};
4301
4302
c2924966 4303static unsigned int
ef330312
PB
4304rest_of_handle_shorten_branches (void)
4305{
4306 /* Shorten branches. */
4307 shorten_branches (get_insns ());
c2924966 4308 return 0;
ef330312 4309}
b0efb46b 4310
8ddbbcae 4311struct rtl_opt_pass pass_shorten_branches =
ef330312 4312{
8ddbbcae
JH
4313 {
4314 RTL_PASS,
defb77dc 4315 "shorten", /* name */
ef330312
PB
4316 NULL, /* gate */
4317 rest_of_handle_shorten_branches, /* execute */
4318 NULL, /* sub */
4319 NULL, /* next */
4320 0, /* static_pass_number */
4321 TV_FINAL, /* tv_id */
4322 0, /* properties_required */
4323 0, /* properties_provided */
4324 0, /* properties_destroyed */
4325 0, /* todo_flags_start */
8ddbbcae
JH
4326 TODO_dump_func /* todo_flags_finish */
4327 }
ef330312
PB
4328};
4329
4330
c2924966 4331static unsigned int
ef330312
PB
4332rest_of_clean_state (void)
4333{
4334 rtx insn, next;
2153915d
AO
4335 FILE *final_output = NULL;
4336 int save_unnumbered = flag_dump_unnumbered;
4337 int save_noaddr = flag_dump_noaddr;
4338
4339 if (flag_dump_final_insns)
4340 {
4341 final_output = fopen (flag_dump_final_insns, "a");
4342 if (!final_output)
4343 {
4344 error ("could not open final insn dump file %qs: %s",
4345 flag_dump_final_insns, strerror (errno));
4346 flag_dump_final_insns = NULL;
4347 }
4348 else
4349 {
4350 const char *aname;
4351
4352 aname = (IDENTIFIER_POINTER
4353 (DECL_ASSEMBLER_NAME (current_function_decl)));
4354 fprintf (final_output, "\n;; Function (%s) %s\n\n", aname,
4355 cfun->function_frequency == FUNCTION_FREQUENCY_HOT
4356 ? " (hot)"
4357 : cfun->function_frequency == FUNCTION_FREQUENCY_UNLIKELY_EXECUTED
4358 ? " (unlikely executed)"
4359 : "");
4360
4361 flag_dump_noaddr = flag_dump_unnumbered = 1;
4362
4363 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4364 if (LABEL_P (insn))
4365 INSN_UID (insn) = CODE_LABEL_NUMBER (insn);
4366 else
4367 INSN_UID (insn) = 0;
4368 }
4369 }
ef330312
PB
4370
4371 /* It is very important to decompose the RTL instruction chain here:
4372 debug information keeps pointing into CODE_LABEL insns inside the function
4373 body. If these remain pointing to the other insns, we end up preserving
4374 whole RTL chain and attached detailed debug info in memory. */
4375 for (insn = get_insns (); insn; insn = next)
4376 {
4377 next = NEXT_INSN (insn);
4378 NEXT_INSN (insn) = NULL;
4379 PREV_INSN (insn) = NULL;
2153915d
AO
4380
4381 if (final_output
4382 && (!NOTE_P (insn) ||
4383 (NOTE_KIND (insn) != NOTE_INSN_VAR_LOCATION
4384 && NOTE_KIND (insn) != NOTE_INSN_BLOCK_BEG
b5b8b0ac
AO
4385 && NOTE_KIND (insn) != NOTE_INSN_BLOCK_END
4386 && NOTE_KIND (insn) != NOTE_INSN_CFA_RESTORE_STATE)))
2153915d
AO
4387 print_rtl_single (final_output, insn);
4388
4389 }
4390
4391 if (final_output)
4392 {
4393 flag_dump_noaddr = save_noaddr;
4394 flag_dump_unnumbered = save_unnumbered;
4395
4396 if (fclose (final_output))
4397 {
4398 error ("could not close final insn dump file %qs: %s",
4399 flag_dump_final_insns, strerror (errno));
4400 flag_dump_final_insns = NULL;
4401 }
ef330312
PB
4402 }
4403
4404 /* In case the function was not output,
4405 don't leave any temporary anonymous types
4406 queued up for sdb output. */
4407#ifdef SDB_DEBUGGING_INFO
4408 if (write_symbols == SDB_DEBUG)
4409 sdbout_types (NULL_TREE);
4410#endif
4411
5f39ad47 4412 flag_rerun_cse_after_global_opts = 0;
ef330312
PB
4413 reload_completed = 0;
4414 epilogue_completed = 0;
23249ac4
DB
4415#ifdef STACK_REGS
4416 regstack_completed = 0;
4417#endif
ef330312
PB
4418
4419 /* Clear out the insn_length contents now that they are no
4420 longer valid. */
4421 init_insn_lengths ();
4422
4423 /* Show no temporary slots allocated. */
4424 init_temp_slots ();
4425
ef330312
PB
4426 free_bb_for_insn ();
4427
55b34b5f
RG
4428 delete_tree_ssa ();
4429
ef330312
PB
4430 if (targetm.binds_local_p (current_function_decl))
4431 {
17b29c0a 4432 unsigned int pref = crtl->preferred_stack_boundary;
cb91fab0
JH
4433 if (crtl->stack_alignment_needed > crtl->preferred_stack_boundary)
4434 pref = crtl->stack_alignment_needed;
ef330312
PB
4435 cgraph_rtl_info (current_function_decl)->preferred_incoming_stack_boundary
4436 = pref;
4437 }
4438
4439 /* Make sure volatile mem refs aren't considered valid operands for
4440 arithmetic insns. We must call this here if this is a nested inline
4441 function, since the above code leaves us in the init_recog state,
4442 and the function context push/pop code does not save/restore volatile_ok.
4443
4444 ??? Maybe it isn't necessary for expand_start_function to call this
4445 anymore if we do it here? */
4446
4447 init_recog_no_volatile ();
4448
4449 /* We're done with this function. Free up memory if we can. */
4450 free_after_parsing (cfun);
4451 free_after_compilation (cfun);
c2924966 4452 return 0;
ef330312
PB
4453}
4454
8ddbbcae 4455struct rtl_opt_pass pass_clean_state =
ef330312 4456{
8ddbbcae
JH
4457 {
4458 RTL_PASS,
cf400ddb 4459 "*clean_state", /* name */
ef330312
PB
4460 NULL, /* gate */
4461 rest_of_clean_state, /* execute */
4462 NULL, /* sub */
4463 NULL, /* next */
4464 0, /* static_pass_number */
4465 TV_FINAL, /* tv_id */
4466 0, /* properties_required */
4467 0, /* properties_provided */
4468 PROP_rtl, /* properties_destroyed */
4469 0, /* todo_flags_start */
8ddbbcae
JH
4470 0 /* todo_flags_finish */
4471 }
ef330312 4472};