]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/final.c
Daily bump.
[thirdparty/gcc.git] / gcc / final.c
CommitLineData
3cf2715d 1/* Convert RTL to assembler code and output it, for GNU compiler.
3b708058 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
6ca5d1f6 3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
17ac08e2 4 Free Software Foundation, Inc.
3cf2715d 5
1322177d 6This file is part of GCC.
3cf2715d 7
1322177d
LB
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
9dcd6f09 10Software Foundation; either version 3, or (at your option) any later
1322177d 11version.
3cf2715d 12
1322177d
LB
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
3cf2715d
DE
17
18You should have received a copy of the GNU General Public License
9dcd6f09
NC
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
3cf2715d 21
3cf2715d
DE
22/* This is the final pass of the compiler.
23 It looks at the rtl code for a function and outputs assembler code.
24
25 Call `final_start_function' to output the assembler code for function entry,
26 `final' to output assembler code for some RTL code,
27 `final_end_function' to output assembler code for function exit.
28 If a function is compiled in several pieces, each piece is
29 output separately with `final'.
30
31 Some optimizations are also done at this level.
32 Move instructions that were made unnecessary by good register allocation
33 are detected and omitted from the output. (Though most of these
34 are removed by the last jump pass.)
35
36 Instructions to set the condition codes are omitted when it can be
37 seen that the condition codes already had the desired values.
38
39 In some cases it is sufficient if the inherited condition codes
40 have related values, but this may require the following insn
41 (the one that tests the condition codes) to be modified.
42
43 The code for the function prologue and epilogue are generated
08c148a8
NB
44 directly in assembler by the target functions function_prologue and
45 function_epilogue. Those instructions never exist as rtl. */
3cf2715d
DE
46
47#include "config.h"
670ee920 48#include "system.h"
4977bab6
ZW
49#include "coretypes.h"
50#include "tm.h"
3cf2715d
DE
51
52#include "tree.h"
53#include "rtl.h"
6baf1cc8 54#include "tm_p.h"
3cf2715d
DE
55#include "regs.h"
56#include "insn-config.h"
3cf2715d 57#include "insn-attr.h"
3cf2715d
DE
58#include "recog.h"
59#include "conditions.h"
60#include "flags.h"
3cf2715d 61#include "hard-reg-set.h"
3cf2715d 62#include "output.h"
3d195391 63#include "except.h"
49ad7cfa 64#include "function.h"
10f0ad3d 65#include "toplev.h"
d6f4ec51 66#include "reload.h"
ab87f8c8 67#include "intl.h"
be1bb652 68#include "basic-block.h"
08c148a8 69#include "target.h"
a5a42b92 70#include "debug.h"
49d801d3 71#include "expr.h"
ba4f7968 72#include "cfglayout.h"
ef330312 73#include "tree-pass.h"
55b34b5f 74#include "tree-flow.h"
ef330312
PB
75#include "timevar.h"
76#include "cgraph.h"
77#include "coverage.h"
6fb5fa3c 78#include "df.h"
294340bf 79#include "vecprim.h"
c8aea42c 80#include "ggc.h"
edbed3d3
JH
81#include "cfgloop.h"
82#include "params.h"
3cf2715d 83
440aabf8
NB
84#ifdef XCOFF_DEBUGGING_INFO
85#include "xcoffout.h" /* Needed for external data
86 declarations for e.g. AIX 4.x. */
87#endif
88
76ead72b
RL
89#if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO)
90#include "dwarf2out.h"
91#endif
92
6a08f7b3
DP
93#ifdef DBX_DEBUGGING_INFO
94#include "dbxout.h"
95#endif
96
ce82daed
DB
97#ifdef SDB_DEBUGGING_INFO
98#include "sdbout.h"
99#endif
100
3cf2715d
DE
101/* If we aren't using cc0, CC_STATUS_INIT shouldn't exist. So define a
102 null default for it to save conditionalization later. */
103#ifndef CC_STATUS_INIT
104#define CC_STATUS_INIT
105#endif
106
107/* How to start an assembler comment. */
108#ifndef ASM_COMMENT_START
109#define ASM_COMMENT_START ";#"
110#endif
111
112/* Is the given character a logical line separator for the assembler? */
113#ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
980d8882 114#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
3cf2715d
DE
115#endif
116
75197b37
BS
117#ifndef JUMP_TABLES_IN_TEXT_SECTION
118#define JUMP_TABLES_IN_TEXT_SECTION 0
119#endif
120
589fe865
DJ
121/* Bitflags used by final_scan_insn. */
122#define SEEN_BB 1
123#define SEEN_NOTE 2
124#define SEEN_EMITTED 4
125
3cf2715d 126/* Last insn processed by final_scan_insn. */
b1a9f6a0
RH
127static rtx debug_insn;
128rtx current_output_insn;
3cf2715d
DE
129
130/* Line number of last NOTE. */
131static int last_linenum;
132
6c52e687
CC
133/* Last discriminator written to assembly. */
134static int last_discriminator;
135
136/* Discriminator of current block. */
137static int discriminator;
138
eac40081
RK
139/* Highest line number in current block. */
140static int high_block_linenum;
141
142/* Likewise for function. */
143static int high_function_linenum;
144
3cf2715d 145/* Filename of last NOTE. */
3cce094d 146static const char *last_filename;
3cf2715d 147
d752cfdb
JJ
148/* Override filename and line number. */
149static const char *override_filename;
150static int override_linenum;
151
b8176fe4
EB
152/* Whether to force emission of a line note before the next insn. */
153static bool force_source_line = false;
b0efb46b 154
5f2f0edd 155extern const int length_unit_log; /* This is defined in insn-attrtab.c. */
fc470718 156
3cf2715d 157/* Nonzero while outputting an `asm' with operands.
535a42b1 158 This means that inconsistencies are the user's fault, so don't die.
3cf2715d 159 The precise value is the insn being output, to pass to error_for_asm. */
c8b94768 160rtx this_is_asm_operands;
3cf2715d
DE
161
162/* Number of operands of this insn, for an `asm' with operands. */
22bf4422 163static unsigned int insn_noperands;
3cf2715d
DE
164
165/* Compare optimization flag. */
166
167static rtx last_ignored_compare = 0;
168
3cf2715d
DE
169/* Assign a unique number to each insn that is output.
170 This can be used to generate unique local labels. */
171
172static int insn_counter = 0;
173
174#ifdef HAVE_cc0
175/* This variable contains machine-dependent flags (defined in tm.h)
176 set and examined by output routines
177 that describe how to interpret the condition codes properly. */
178
179CC_STATUS cc_status;
180
181/* During output of an insn, this contains a copy of cc_status
182 from before the insn. */
183
184CC_STATUS cc_prev_status;
185#endif
186
18c038b9 187/* Number of unmatched NOTE_INSN_BLOCK_BEG notes we have seen. */
3cf2715d
DE
188
189static int block_depth;
190
191/* Nonzero if have enabled APP processing of our assembler output. */
192
193static int app_on;
194
195/* If we are outputting an insn sequence, this contains the sequence rtx.
196 Zero otherwise. */
197
198rtx final_sequence;
199
200#ifdef ASSEMBLER_DIALECT
201
202/* Number of the assembler dialect to use, starting at 0. */
203static int dialect_number;
204#endif
205
afe48e06
RH
206/* Nonnull if the insn currently being emitted was a COND_EXEC pattern. */
207rtx current_insn_predicate;
afe48e06 208
6ca5d1f6
JJ
209/* True if printing into -fdump-final-insns= dump. */
210bool final_insns_dump_p;
211
1d300e19 212#ifdef HAVE_ATTR_length
6cf9ac28
AJ
213static int asm_insn_count (rtx);
214#endif
215static void profile_function (FILE *);
216static void profile_after_prologue (FILE *);
ed5ef2e4 217static bool notice_source_line (rtx, bool *);
6fb5fa3c 218static rtx walk_alter_subreg (rtx *, bool *);
6cf9ac28
AJ
219static void output_asm_name (void);
220static void output_alternate_entry_point (FILE *, rtx);
221static tree get_mem_expr_from_op (rtx, int *);
222static void output_asm_operand_names (rtx *, int *, int);
223static void output_operand (rtx, int);
e9a25f70 224#ifdef LEAF_REGISTERS
6cf9ac28 225static void leaf_renumber_regs (rtx);
e9a25f70
JL
226#endif
227#ifdef HAVE_cc0
6cf9ac28 228static int alter_cond (rtx);
e9a25f70 229#endif
ca3075bd 230#ifndef ADDR_VEC_ALIGN
6cf9ac28 231static int final_addr_vec_align (rtx);
ca3075bd 232#endif
7bdb32b9 233#ifdef HAVE_ATTR_length
6cf9ac28 234static int align_fuzz (rtx, rtx, int, unsigned);
7bdb32b9 235#endif
3cf2715d
DE
236\f
237/* Initialize data in final at the beginning of a compilation. */
238
239void
6cf9ac28 240init_final (const char *filename ATTRIBUTE_UNUSED)
3cf2715d 241{
3cf2715d 242 app_on = 0;
3cf2715d
DE
243 final_sequence = 0;
244
245#ifdef ASSEMBLER_DIALECT
246 dialect_number = ASSEMBLER_DIALECT;
247#endif
248}
249
08c148a8 250/* Default target function prologue and epilogue assembler output.
b9f22704 251
08c148a8
NB
252 If not overridden for epilogue code, then the function body itself
253 contains return instructions wherever needed. */
254void
6cf9ac28
AJ
255default_function_pro_epilogue (FILE *file ATTRIBUTE_UNUSED,
256 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
08c148a8
NB
257{
258}
259
b4c25db2
NB
260/* Default target hook that outputs nothing to a stream. */
261void
6cf9ac28 262no_asm_to_stream (FILE *file ATTRIBUTE_UNUSED)
b4c25db2
NB
263{
264}
265
3cf2715d
DE
266/* Enable APP processing of subsequent output.
267 Used before the output from an `asm' statement. */
268
269void
6cf9ac28 270app_enable (void)
3cf2715d
DE
271{
272 if (! app_on)
273 {
51723711 274 fputs (ASM_APP_ON, asm_out_file);
3cf2715d
DE
275 app_on = 1;
276 }
277}
278
279/* Disable APP processing of subsequent output.
280 Called from varasm.c before most kinds of output. */
281
282void
6cf9ac28 283app_disable (void)
3cf2715d
DE
284{
285 if (app_on)
286 {
51723711 287 fputs (ASM_APP_OFF, asm_out_file);
3cf2715d
DE
288 app_on = 0;
289 }
290}
291\f
f5d927c0 292/* Return the number of slots filled in the current
3cf2715d
DE
293 delayed branch sequence (we don't count the insn needing the
294 delay slot). Zero if not in a delayed branch sequence. */
295
296#ifdef DELAY_SLOTS
297int
6cf9ac28 298dbr_sequence_length (void)
3cf2715d
DE
299{
300 if (final_sequence != 0)
301 return XVECLEN (final_sequence, 0) - 1;
302 else
303 return 0;
304}
305#endif
306\f
307/* The next two pages contain routines used to compute the length of an insn
308 and to shorten branches. */
309
310/* Arrays for insn lengths, and addresses. The latter is referenced by
311 `insn_current_length'. */
312
addd7df6 313static int *insn_lengths;
9d98a694 314
294340bf 315VEC(int,heap) *insn_addresses_;
3cf2715d 316
ea3cbda5
R
317/* Max uid for which the above arrays are valid. */
318static int insn_lengths_max_uid;
319
3cf2715d
DE
320/* Address of insn being processed. Used by `insn_current_length'. */
321int insn_current_address;
322
fc470718
R
323/* Address of insn being processed in previous iteration. */
324int insn_last_address;
325
d6a7951f 326/* known invariant alignment of insn being processed. */
fc470718
R
327int insn_current_align;
328
95707627
R
329/* After shorten_branches, for any insn, uid_align[INSN_UID (insn)]
330 gives the next following alignment insn that increases the known
331 alignment, or NULL_RTX if there is no such insn.
332 For any alignment obtained this way, we can again index uid_align with
333 its uid to obtain the next following align that in turn increases the
334 alignment, till we reach NULL_RTX; the sequence obtained this way
335 for each insn we'll call the alignment chain of this insn in the following
336 comments. */
337
f5d927c0
KH
338struct label_alignment
339{
9e423e6d
JW
340 short alignment;
341 short max_skip;
342};
343
344static rtx *uid_align;
345static int *uid_shuid;
346static struct label_alignment *label_align;
95707627 347
3cf2715d
DE
348/* Indicate that branch shortening hasn't yet been done. */
349
350void
6cf9ac28 351init_insn_lengths (void)
3cf2715d 352{
95707627
R
353 if (uid_shuid)
354 {
355 free (uid_shuid);
356 uid_shuid = 0;
357 }
358 if (insn_lengths)
359 {
360 free (insn_lengths);
361 insn_lengths = 0;
ea3cbda5 362 insn_lengths_max_uid = 0;
95707627 363 }
9d98a694
AO
364#ifdef HAVE_ATTR_length
365 INSN_ADDRESSES_FREE ();
366#endif
95707627
R
367 if (uid_align)
368 {
369 free (uid_align);
370 uid_align = 0;
371 }
3cf2715d
DE
372}
373
374/* Obtain the current length of an insn. If branch shortening has been done,
6fc0bb99 375 get its actual length. Otherwise, use FALLBACK_FN to calculate the
070a7956
R
376 length. */
377static inline int
378get_attr_length_1 (rtx insn ATTRIBUTE_UNUSED,
379 int (*fallback_fn) (rtx) ATTRIBUTE_UNUSED)
3cf2715d
DE
380{
381#ifdef HAVE_ATTR_length
382 rtx body;
383 int i;
384 int length = 0;
385
ea3cbda5 386 if (insn_lengths_max_uid > INSN_UID (insn))
3cf2715d
DE
387 return insn_lengths[INSN_UID (insn)];
388 else
389 switch (GET_CODE (insn))
390 {
391 case NOTE:
392 case BARRIER:
393 case CODE_LABEL:
b5b8b0ac 394 case DEBUG_INSN:
3cf2715d
DE
395 return 0;
396
397 case CALL_INSN:
070a7956 398 length = fallback_fn (insn);
3cf2715d
DE
399 break;
400
401 case JUMP_INSN:
402 body = PATTERN (insn);
dd3f0101 403 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
3cf2715d 404 {
fc470718
R
405 /* Alignment is machine-dependent and should be handled by
406 ADDR_VEC_ALIGN. */
3cf2715d
DE
407 }
408 else
070a7956 409 length = fallback_fn (insn);
3cf2715d
DE
410 break;
411
412 case INSN:
413 body = PATTERN (insn);
414 if (GET_CODE (body) == USE || GET_CODE (body) == CLOBBER)
415 return 0;
416
417 else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0)
070a7956 418 length = asm_insn_count (body) * fallback_fn (insn);
3cf2715d
DE
419 else if (GET_CODE (body) == SEQUENCE)
420 for (i = 0; i < XVECLEN (body, 0); i++)
47d268d0 421 length += get_attr_length_1 (XVECEXP (body, 0, i), fallback_fn);
3cf2715d 422 else
070a7956 423 length = fallback_fn (insn);
e9a25f70
JL
424 break;
425
426 default:
427 break;
3cf2715d
DE
428 }
429
430#ifdef ADJUST_INSN_LENGTH
431 ADJUST_INSN_LENGTH (insn, length);
432#endif
433 return length;
434#else /* not HAVE_ATTR_length */
435 return 0;
a9305dcb
R
436#define insn_default_length 0
437#define insn_min_length 0
3cf2715d
DE
438#endif /* not HAVE_ATTR_length */
439}
070a7956
R
440
441/* Obtain the current length of an insn. If branch shortening has been done,
442 get its actual length. Otherwise, get its maximum length. */
443int
444get_attr_length (rtx insn)
445{
446 return get_attr_length_1 (insn, insn_default_length);
447}
448
449/* Obtain the current length of an insn. If branch shortening has been done,
450 get its actual length. Otherwise, get its minimum length. */
451int
452get_attr_min_length (rtx insn)
453{
454 return get_attr_length_1 (insn, insn_min_length);
455}
3cf2715d 456\f
fc470718
R
457/* Code to handle alignment inside shorten_branches. */
458
459/* Here is an explanation how the algorithm in align_fuzz can give
460 proper results:
461
462 Call a sequence of instructions beginning with alignment point X
463 and continuing until the next alignment point `block X'. When `X'
f5d927c0 464 is used in an expression, it means the alignment value of the
fc470718 465 alignment point.
f5d927c0 466
fc470718
R
467 Call the distance between the start of the first insn of block X, and
468 the end of the last insn of block X `IX', for the `inner size of X'.
469 This is clearly the sum of the instruction lengths.
f5d927c0 470
fc470718
R
471 Likewise with the next alignment-delimited block following X, which we
472 shall call block Y.
f5d927c0 473
fc470718
R
474 Call the distance between the start of the first insn of block X, and
475 the start of the first insn of block Y `OX', for the `outer size of X'.
f5d927c0 476
fc470718 477 The estimated padding is then OX - IX.
f5d927c0 478
fc470718 479 OX can be safely estimated as
f5d927c0 480
fc470718
R
481 if (X >= Y)
482 OX = round_up(IX, Y)
483 else
484 OX = round_up(IX, X) + Y - X
f5d927c0 485
fc470718
R
486 Clearly est(IX) >= real(IX), because that only depends on the
487 instruction lengths, and those being overestimated is a given.
f5d927c0 488
fc470718
R
489 Clearly round_up(foo, Z) >= round_up(bar, Z) if foo >= bar, so
490 we needn't worry about that when thinking about OX.
f5d927c0 491
fc470718
R
492 When X >= Y, the alignment provided by Y adds no uncertainty factor
493 for branch ranges starting before X, so we can just round what we have.
494 But when X < Y, we don't know anything about the, so to speak,
495 `middle bits', so we have to assume the worst when aligning up from an
496 address mod X to one mod Y, which is Y - X. */
497
498#ifndef LABEL_ALIGN
efa3896a 499#define LABEL_ALIGN(LABEL) align_labels_log
fc470718
R
500#endif
501
9e423e6d 502#ifndef LABEL_ALIGN_MAX_SKIP
2cca7283 503#define LABEL_ALIGN_MAX_SKIP align_labels_max_skip
9e423e6d
JW
504#endif
505
fc470718 506#ifndef LOOP_ALIGN
efa3896a 507#define LOOP_ALIGN(LABEL) align_loops_log
fc470718
R
508#endif
509
9e423e6d 510#ifndef LOOP_ALIGN_MAX_SKIP
2cca7283 511#define LOOP_ALIGN_MAX_SKIP align_loops_max_skip
9e423e6d
JW
512#endif
513
fc470718 514#ifndef LABEL_ALIGN_AFTER_BARRIER
340f7e7c 515#define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0
fc470718
R
516#endif
517
9e423e6d 518#ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
247a370b
JH
519#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0
520#endif
521
522#ifndef JUMP_ALIGN
523#define JUMP_ALIGN(LABEL) align_jumps_log
524#endif
525
526#ifndef JUMP_ALIGN_MAX_SKIP
2cca7283 527#define JUMP_ALIGN_MAX_SKIP align_jumps_max_skip
9e423e6d
JW
528#endif
529
fc470718 530#ifndef ADDR_VEC_ALIGN
ca3075bd 531static int
6cf9ac28 532final_addr_vec_align (rtx addr_vec)
fc470718 533{
2a841588 534 int align = GET_MODE_SIZE (GET_MODE (PATTERN (addr_vec)));
fc470718
R
535
536 if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT)
537 align = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
2a841588 538 return exact_log2 (align);
fc470718
R
539
540}
f5d927c0 541
fc470718
R
542#define ADDR_VEC_ALIGN(ADDR_VEC) final_addr_vec_align (ADDR_VEC)
543#endif
544
545#ifndef INSN_LENGTH_ALIGNMENT
546#define INSN_LENGTH_ALIGNMENT(INSN) length_unit_log
547#endif
548
fc470718
R
549#define INSN_SHUID(INSN) (uid_shuid[INSN_UID (INSN)])
550
de7987a6 551static int min_labelno, max_labelno;
fc470718
R
552
553#define LABEL_TO_ALIGNMENT(LABEL) \
9e423e6d
JW
554 (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].alignment)
555
556#define LABEL_TO_MAX_SKIP(LABEL) \
557 (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].max_skip)
fc470718
R
558
559/* For the benefit of port specific code do this also as a function. */
f5d927c0 560
fc470718 561int
6cf9ac28 562label_to_alignment (rtx label)
fc470718 563{
40a8f07a
JJ
564 if (CODE_LABEL_NUMBER (label) <= max_labelno)
565 return LABEL_TO_ALIGNMENT (label);
566 return 0;
567}
568
569int
570label_to_max_skip (rtx label)
571{
572 if (CODE_LABEL_NUMBER (label) <= max_labelno)
573 return LABEL_TO_MAX_SKIP (label);
574 return 0;
fc470718
R
575}
576
577#ifdef HAVE_ATTR_length
578/* The differences in addresses
579 between a branch and its target might grow or shrink depending on
580 the alignment the start insn of the range (the branch for a forward
581 branch or the label for a backward branch) starts out on; if these
582 differences are used naively, they can even oscillate infinitely.
583 We therefore want to compute a 'worst case' address difference that
584 is independent of the alignment the start insn of the range end
585 up on, and that is at least as large as the actual difference.
586 The function align_fuzz calculates the amount we have to add to the
587 naively computed difference, by traversing the part of the alignment
588 chain of the start insn of the range that is in front of the end insn
589 of the range, and considering for each alignment the maximum amount
590 that it might contribute to a size increase.
591
592 For casesi tables, we also want to know worst case minimum amounts of
593 address difference, in case a machine description wants to introduce
594 some common offset that is added to all offsets in a table.
d6a7951f 595 For this purpose, align_fuzz with a growth argument of 0 computes the
fc470718
R
596 appropriate adjustment. */
597
fc470718
R
598/* Compute the maximum delta by which the difference of the addresses of
599 START and END might grow / shrink due to a different address for start
600 which changes the size of alignment insns between START and END.
601 KNOWN_ALIGN_LOG is the alignment known for START.
602 GROWTH should be ~0 if the objective is to compute potential code size
603 increase, and 0 if the objective is to compute potential shrink.
604 The return value is undefined for any other value of GROWTH. */
f5d927c0 605
ca3075bd 606static int
6cf9ac28 607align_fuzz (rtx start, rtx end, int known_align_log, unsigned int growth)
fc470718
R
608{
609 int uid = INSN_UID (start);
610 rtx align_label;
611 int known_align = 1 << known_align_log;
612 int end_shuid = INSN_SHUID (end);
613 int fuzz = 0;
614
615 for (align_label = uid_align[uid]; align_label; align_label = uid_align[uid])
616 {
617 int align_addr, new_align;
618
619 uid = INSN_UID (align_label);
9d98a694 620 align_addr = INSN_ADDRESSES (uid) - insn_lengths[uid];
fc470718
R
621 if (uid_shuid[uid] > end_shuid)
622 break;
623 known_align_log = LABEL_TO_ALIGNMENT (align_label);
624 new_align = 1 << known_align_log;
625 if (new_align < known_align)
626 continue;
627 fuzz += (-align_addr ^ growth) & (new_align - known_align);
628 known_align = new_align;
629 }
630 return fuzz;
631}
632
633/* Compute a worst-case reference address of a branch so that it
634 can be safely used in the presence of aligned labels. Since the
635 size of the branch itself is unknown, the size of the branch is
636 not included in the range. I.e. for a forward branch, the reference
637 address is the end address of the branch as known from the previous
638 branch shortening pass, minus a value to account for possible size
639 increase due to alignment. For a backward branch, it is the start
640 address of the branch as known from the current pass, plus a value
641 to account for possible size increase due to alignment.
642 NB.: Therefore, the maximum offset allowed for backward branches needs
643 to exclude the branch size. */
f5d927c0 644
fc470718 645int
6cf9ac28 646insn_current_reference_address (rtx branch)
fc470718 647{
5527bf14
RH
648 rtx dest, seq;
649 int seq_uid;
650
651 if (! INSN_ADDRESSES_SET_P ())
652 return 0;
653
654 seq = NEXT_INSN (PREV_INSN (branch));
655 seq_uid = INSN_UID (seq);
4b4bf941 656 if (!JUMP_P (branch))
fc470718
R
657 /* This can happen for example on the PA; the objective is to know the
658 offset to address something in front of the start of the function.
659 Thus, we can treat it like a backward branch.
660 We assume here that FUNCTION_BOUNDARY / BITS_PER_UNIT is larger than
661 any alignment we'd encounter, so we skip the call to align_fuzz. */
662 return insn_current_address;
663 dest = JUMP_LABEL (branch);
5527bf14 664
b9f22704 665 /* BRANCH has no proper alignment chain set, so use SEQ.
afc6898e
BS
666 BRANCH also has no INSN_SHUID. */
667 if (INSN_SHUID (seq) < INSN_SHUID (dest))
fc470718 668 {
f5d927c0 669 /* Forward branch. */
fc470718 670 return (insn_last_address + insn_lengths[seq_uid]
26024475 671 - align_fuzz (seq, dest, length_unit_log, ~0));
fc470718
R
672 }
673 else
674 {
f5d927c0 675 /* Backward branch. */
fc470718 676 return (insn_current_address
923f7cf9 677 + align_fuzz (dest, seq, length_unit_log, ~0));
fc470718
R
678 }
679}
680#endif /* HAVE_ATTR_length */
681\f
65727068
KH
682/* Compute branch alignments based on frequency information in the
683 CFG. */
684
e855c69d 685unsigned int
6cf9ac28 686compute_alignments (void)
247a370b 687{
247a370b 688 int log, max_skip, max_log;
e0082a72 689 basic_block bb;
edbed3d3
JH
690 int freq_max = 0;
691 int freq_threshold = 0;
247a370b
JH
692
693 if (label_align)
694 {
695 free (label_align);
696 label_align = 0;
697 }
698
699 max_labelno = max_label_num ();
700 min_labelno = get_first_label_num ();
5ed6ace5 701 label_align = XCNEWVEC (struct label_alignment, max_labelno - min_labelno + 1);
247a370b
JH
702
703 /* If not optimizing or optimizing for size, don't assign any alignments. */
efd8f750 704 if (! optimize || optimize_function_for_size_p (cfun))
c2924966 705 return 0;
247a370b 706
edbed3d3
JH
707 if (dump_file)
708 {
709 dump_flow_info (dump_file, TDF_DETAILS);
710 flow_loops_dump (dump_file, NULL, 1);
711 loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
712 }
713 FOR_EACH_BB (bb)
714 if (bb->frequency > freq_max)
715 freq_max = bb->frequency;
716 freq_threshold = freq_max / PARAM_VALUE (PARAM_ALIGN_THRESHOLD);
717
718 if (dump_file)
719 fprintf(dump_file, "freq_max: %i\n",freq_max);
e0082a72 720 FOR_EACH_BB (bb)
247a370b 721 {
a813c111 722 rtx label = BB_HEAD (bb);
247a370b
JH
723 int fallthru_frequency = 0, branch_frequency = 0, has_fallthru = 0;
724 edge e;
628f6a4e 725 edge_iterator ei;
247a370b 726
4b4bf941 727 if (!LABEL_P (label)
8bcf15f6 728 || optimize_bb_for_size_p (bb))
edbed3d3
JH
729 {
730 if (dump_file)
731 fprintf(dump_file, "BB %4i freq %4i loop %2i loop_depth %2i skipped.\n",
732 bb->index, bb->frequency, bb->loop_father->num, bb->loop_depth);
733 continue;
734 }
247a370b
JH
735 max_log = LABEL_ALIGN (label);
736 max_skip = LABEL_ALIGN_MAX_SKIP;
737
628f6a4e 738 FOR_EACH_EDGE (e, ei, bb->preds)
247a370b
JH
739 {
740 if (e->flags & EDGE_FALLTHRU)
741 has_fallthru = 1, fallthru_frequency += EDGE_FREQUENCY (e);
742 else
743 branch_frequency += EDGE_FREQUENCY (e);
744 }
edbed3d3
JH
745 if (dump_file)
746 {
747 fprintf(dump_file, "BB %4i freq %4i loop %2i loop_depth %2i fall %4i branch %4i",
748 bb->index, bb->frequency, bb->loop_father->num,
749 bb->loop_depth,
750 fallthru_frequency, branch_frequency);
751 if (!bb->loop_father->inner && bb->loop_father->num)
752 fprintf (dump_file, " inner_loop");
753 if (bb->loop_father->header == bb)
754 fprintf (dump_file, " loop_header");
755 fprintf (dump_file, "\n");
756 }
247a370b 757
f63d1bf7 758 /* There are two purposes to align block with no fallthru incoming edge:
247a370b 759 1) to avoid fetch stalls when branch destination is near cache boundary
d6a7951f 760 2) to improve cache efficiency in case the previous block is not executed
247a370b
JH
761 (so it does not need to be in the cache).
762
763 We to catch first case, we align frequently executed blocks.
764 To catch the second, we align blocks that are executed more frequently
eaec9b3d 765 than the predecessor and the predecessor is likely to not be executed
247a370b
JH
766 when function is called. */
767
768 if (!has_fallthru
edbed3d3 769 && (branch_frequency > freq_threshold
f6366fc7
ZD
770 || (bb->frequency > bb->prev_bb->frequency * 10
771 && (bb->prev_bb->frequency
247a370b
JH
772 <= ENTRY_BLOCK_PTR->frequency / 2))))
773 {
774 log = JUMP_ALIGN (label);
edbed3d3
JH
775 if (dump_file)
776 fprintf(dump_file, " jump alignment added.\n");
247a370b
JH
777 if (max_log < log)
778 {
779 max_log = log;
780 max_skip = JUMP_ALIGN_MAX_SKIP;
781 }
782 }
783 /* In case block is frequent and reached mostly by non-fallthru edge,
09da1532 784 align it. It is most likely a first block of loop. */
247a370b 785 if (has_fallthru
efd8f750 786 && optimize_bb_for_speed_p (bb)
edbed3d3
JH
787 && branch_frequency + fallthru_frequency > freq_threshold
788 && (branch_frequency
789 > fallthru_frequency * PARAM_VALUE (PARAM_ALIGN_LOOP_ITERATIONS)))
247a370b
JH
790 {
791 log = LOOP_ALIGN (label);
edbed3d3
JH
792 if (dump_file)
793 fprintf(dump_file, " internal loop alignment added.\n");
247a370b
JH
794 if (max_log < log)
795 {
796 max_log = log;
797 max_skip = LOOP_ALIGN_MAX_SKIP;
798 }
799 }
800 LABEL_TO_ALIGNMENT (label) = max_log;
801 LABEL_TO_MAX_SKIP (label) = max_skip;
802 }
edbed3d3
JH
803
804 if (dump_file)
e855c69d
AB
805 {
806 loop_optimizer_finalize ();
807 free_dominance_info (CDI_DOMINATORS);
808 }
c2924966 809 return 0;
247a370b 810}
ef330312 811
8ddbbcae 812struct rtl_opt_pass pass_compute_alignments =
ef330312 813{
8ddbbcae
JH
814 {
815 RTL_PASS,
edbed3d3 816 "alignments", /* name */
ef330312
PB
817 NULL, /* gate */
818 compute_alignments, /* execute */
819 NULL, /* sub */
820 NULL, /* next */
821 0, /* static_pass_number */
7072a650 822 TV_NONE, /* tv_id */
ef330312
PB
823 0, /* properties_required */
824 0, /* properties_provided */
825 0, /* properties_destroyed */
826 0, /* todo_flags_start */
edbed3d3 827 TODO_dump_func | TODO_verify_rtl_sharing
8ddbbcae
JH
828 | TODO_ggc_collect /* todo_flags_finish */
829 }
ef330312
PB
830};
831
247a370b 832\f
3cf2715d
DE
833/* Make a pass over all insns and compute their actual lengths by shortening
834 any branches of variable length if possible. */
835
fc470718
R
836/* shorten_branches might be called multiple times: for example, the SH
837 port splits out-of-range conditional branches in MACHINE_DEPENDENT_REORG.
838 In order to do this, it needs proper length information, which it obtains
839 by calling shorten_branches. This cannot be collapsed with
d6a7951f 840 shorten_branches itself into a single pass unless we also want to integrate
fc470718
R
841 reorg.c, since the branch splitting exposes new instructions with delay
842 slots. */
843
3cf2715d 844void
6cf9ac28 845shorten_branches (rtx first ATTRIBUTE_UNUSED)
3cf2715d 846{
3cf2715d 847 rtx insn;
fc470718
R
848 int max_uid;
849 int i;
fc470718 850 int max_log;
9e423e6d 851 int max_skip;
fc470718
R
852#ifdef HAVE_ATTR_length
853#define MAX_CODE_ALIGN 16
854 rtx seq;
3cf2715d 855 int something_changed = 1;
3cf2715d
DE
856 char *varying_length;
857 rtx body;
858 int uid;
fc470718 859 rtx align_tab[MAX_CODE_ALIGN];
3cf2715d 860
fc470718 861#endif
3d14e82f 862
3446405d
JH
863 /* Compute maximum UID and allocate label_align / uid_shuid. */
864 max_uid = get_max_uid ();
d9b6874b 865
471854f8 866 /* Free uid_shuid before reallocating it. */
07a1f795 867 free (uid_shuid);
b0efb46b 868
5ed6ace5 869 uid_shuid = XNEWVEC (int, max_uid);
25e22dc0 870
247a370b
JH
871 if (max_labelno != max_label_num ())
872 {
873 int old = max_labelno;
874 int n_labels;
875 int n_old_labels;
876
877 max_labelno = max_label_num ();
878
879 n_labels = max_labelno - min_labelno + 1;
880 n_old_labels = old - min_labelno + 1;
881
1b4572a8 882 label_align = XRESIZEVEC (struct label_alignment, label_align, n_labels);
247a370b 883
535a42b1 884 /* Range of labels grows monotonically in the function. Failing here
247a370b 885 means that the initialization of array got lost. */
0bccc606 886 gcc_assert (n_old_labels <= n_labels);
247a370b
JH
887
888 memset (label_align + n_old_labels, 0,
889 (n_labels - n_old_labels) * sizeof (struct label_alignment));
890 }
891
fc470718
R
892 /* Initialize label_align and set up uid_shuid to be strictly
893 monotonically rising with insn order. */
e2faec75
R
894 /* We use max_log here to keep track of the maximum alignment we want to
895 impose on the next CODE_LABEL (or the current one if we are processing
896 the CODE_LABEL itself). */
f5d927c0 897
9e423e6d
JW
898 max_log = 0;
899 max_skip = 0;
900
901 for (insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn))
fc470718
R
902 {
903 int log;
904
905 INSN_SHUID (insn) = i++;
2c3c49de 906 if (INSN_P (insn))
80838531 907 continue;
b0efb46b 908
80838531 909 if (LABEL_P (insn))
fc470718
R
910 {
911 rtx next;
0676c393 912 bool next_is_jumptable;
ff81832f 913
247a370b
JH
914 /* Merge in alignments computed by compute_alignments. */
915 log = LABEL_TO_ALIGNMENT (insn);
916 if (max_log < log)
917 {
918 max_log = log;
919 max_skip = LABEL_TO_MAX_SKIP (insn);
920 }
fc470718 921
0676c393
MM
922 next = next_nonnote_insn (insn);
923 next_is_jumptable = next && JUMP_TABLE_DATA_P (next);
924 if (!next_is_jumptable)
9e423e6d 925 {
0676c393
MM
926 log = LABEL_ALIGN (insn);
927 if (max_log < log)
928 {
929 max_log = log;
930 max_skip = LABEL_ALIGN_MAX_SKIP;
931 }
9e423e6d 932 }
75197b37
BS
933 /* ADDR_VECs only take room if read-only data goes into the text
934 section. */
0676c393
MM
935 if ((JUMP_TABLES_IN_TEXT_SECTION
936 || readonly_data_section == text_section)
937 && next_is_jumptable)
938 {
939 log = ADDR_VEC_ALIGN (next);
940 if (max_log < log)
941 {
942 max_log = log;
943 max_skip = LABEL_ALIGN_MAX_SKIP;
944 }
945 }
fc470718 946 LABEL_TO_ALIGNMENT (insn) = max_log;
9e423e6d 947 LABEL_TO_MAX_SKIP (insn) = max_skip;
fc470718 948 max_log = 0;
9e423e6d 949 max_skip = 0;
fc470718 950 }
4b4bf941 951 else if (BARRIER_P (insn))
fc470718
R
952 {
953 rtx label;
954
2c3c49de 955 for (label = insn; label && ! INSN_P (label);
fc470718 956 label = NEXT_INSN (label))
4b4bf941 957 if (LABEL_P (label))
fc470718
R
958 {
959 log = LABEL_ALIGN_AFTER_BARRIER (insn);
960 if (max_log < log)
9e423e6d
JW
961 {
962 max_log = log;
963 max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP;
964 }
fc470718
R
965 break;
966 }
967 }
fc470718
R
968 }
969#ifdef HAVE_ATTR_length
970
971 /* Allocate the rest of the arrays. */
5ed6ace5 972 insn_lengths = XNEWVEC (int, max_uid);
ea3cbda5 973 insn_lengths_max_uid = max_uid;
af035616
R
974 /* Syntax errors can lead to labels being outside of the main insn stream.
975 Initialize insn_addresses, so that we get reproducible results. */
9d98a694 976 INSN_ADDRESSES_ALLOC (max_uid);
fc470718 977
5ed6ace5 978 varying_length = XCNEWVEC (char, max_uid);
fc470718
R
979
980 /* Initialize uid_align. We scan instructions
981 from end to start, and keep in align_tab[n] the last seen insn
982 that does an alignment of at least n+1, i.e. the successor
983 in the alignment chain for an insn that does / has a known
984 alignment of n. */
5ed6ace5 985 uid_align = XCNEWVEC (rtx, max_uid);
fc470718 986
f5d927c0 987 for (i = MAX_CODE_ALIGN; --i >= 0;)
fc470718
R
988 align_tab[i] = NULL_RTX;
989 seq = get_last_insn ();
33f7f353 990 for (; seq; seq = PREV_INSN (seq))
fc470718
R
991 {
992 int uid = INSN_UID (seq);
993 int log;
4b4bf941 994 log = (LABEL_P (seq) ? LABEL_TO_ALIGNMENT (seq) : 0);
fc470718 995 uid_align[uid] = align_tab[0];
fc470718
R
996 if (log)
997 {
998 /* Found an alignment label. */
999 uid_align[uid] = align_tab[log];
1000 for (i = log - 1; i >= 0; i--)
1001 align_tab[i] = seq;
1002 }
33f7f353
JR
1003 }
1004#ifdef CASE_VECTOR_SHORTEN_MODE
1005 if (optimize)
1006 {
1007 /* Look for ADDR_DIFF_VECs, and initialize their minimum and maximum
1008 label fields. */
1009
1010 int min_shuid = INSN_SHUID (get_insns ()) - 1;
1011 int max_shuid = INSN_SHUID (get_last_insn ()) + 1;
1012 int rel;
1013
1014 for (insn = first; insn != 0; insn = NEXT_INSN (insn))
fc470718 1015 {
33f7f353
JR
1016 rtx min_lab = NULL_RTX, max_lab = NULL_RTX, pat;
1017 int len, i, min, max, insn_shuid;
1018 int min_align;
1019 addr_diff_vec_flags flags;
1020
4b4bf941 1021 if (!JUMP_P (insn)
33f7f353
JR
1022 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
1023 continue;
1024 pat = PATTERN (insn);
1025 len = XVECLEN (pat, 1);
0bccc606 1026 gcc_assert (len > 0);
33f7f353
JR
1027 min_align = MAX_CODE_ALIGN;
1028 for (min = max_shuid, max = min_shuid, i = len - 1; i >= 0; i--)
1029 {
1030 rtx lab = XEXP (XVECEXP (pat, 1, i), 0);
1031 int shuid = INSN_SHUID (lab);
1032 if (shuid < min)
1033 {
1034 min = shuid;
1035 min_lab = lab;
1036 }
1037 if (shuid > max)
1038 {
1039 max = shuid;
1040 max_lab = lab;
1041 }
1042 if (min_align > LABEL_TO_ALIGNMENT (lab))
1043 min_align = LABEL_TO_ALIGNMENT (lab);
1044 }
4c33cb26
R
1045 XEXP (pat, 2) = gen_rtx_LABEL_REF (Pmode, min_lab);
1046 XEXP (pat, 3) = gen_rtx_LABEL_REF (Pmode, max_lab);
33f7f353
JR
1047 insn_shuid = INSN_SHUID (insn);
1048 rel = INSN_SHUID (XEXP (XEXP (pat, 0), 0));
5921f276 1049 memset (&flags, 0, sizeof (flags));
33f7f353
JR
1050 flags.min_align = min_align;
1051 flags.base_after_vec = rel > insn_shuid;
1052 flags.min_after_vec = min > insn_shuid;
1053 flags.max_after_vec = max > insn_shuid;
1054 flags.min_after_base = min > rel;
1055 flags.max_after_base = max > rel;
1056 ADDR_DIFF_VEC_FLAGS (pat) = flags;
fc470718
R
1057 }
1058 }
33f7f353 1059#endif /* CASE_VECTOR_SHORTEN_MODE */
3cf2715d 1060
3cf2715d 1061 /* Compute initial lengths, addresses, and varying flags for each insn. */
b816f339 1062 for (insn_current_address = 0, insn = first;
3cf2715d
DE
1063 insn != 0;
1064 insn_current_address += insn_lengths[uid], insn = NEXT_INSN (insn))
1065 {
1066 uid = INSN_UID (insn);
fc470718 1067
3cf2715d 1068 insn_lengths[uid] = 0;
fc470718 1069
4b4bf941 1070 if (LABEL_P (insn))
fc470718
R
1071 {
1072 int log = LABEL_TO_ALIGNMENT (insn);
1073 if (log)
1074 {
1075 int align = 1 << log;
ecb06768 1076 int new_address = (insn_current_address + align - 1) & -align;
fc470718 1077 insn_lengths[uid] = new_address - insn_current_address;
fc470718
R
1078 }
1079 }
1080
5a09edba 1081 INSN_ADDRESSES (uid) = insn_current_address + insn_lengths[uid];
f5d927c0 1082
4b4bf941 1083 if (NOTE_P (insn) || BARRIER_P (insn)
f90f4827 1084 || LABEL_P (insn) || DEBUG_INSN_P(insn))
3cf2715d 1085 continue;
04da53bd
R
1086 if (INSN_DELETED_P (insn))
1087 continue;
3cf2715d
DE
1088
1089 body = PATTERN (insn);
1090 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
5a32a90c
JR
1091 {
1092 /* This only takes room if read-only data goes into the text
1093 section. */
d6b5193b
RS
1094 if (JUMP_TABLES_IN_TEXT_SECTION
1095 || readonly_data_section == text_section)
75197b37
BS
1096 insn_lengths[uid] = (XVECLEN (body,
1097 GET_CODE (body) == ADDR_DIFF_VEC)
1098 * GET_MODE_SIZE (GET_MODE (body)));
5a32a90c 1099 /* Alignment is handled by ADDR_VEC_ALIGN. */
5a32a90c 1100 }
a30caf5c 1101 else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0)
3cf2715d
DE
1102 insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn);
1103 else if (GET_CODE (body) == SEQUENCE)
1104 {
1105 int i;
1106 int const_delay_slots;
1107#ifdef DELAY_SLOTS
1108 const_delay_slots = const_num_delay_slots (XVECEXP (body, 0, 0));
1109#else
1110 const_delay_slots = 0;
1111#endif
1112 /* Inside a delay slot sequence, we do not do any branch shortening
1113 if the shortening could change the number of delay slots
0f41302f 1114 of the branch. */
3cf2715d
DE
1115 for (i = 0; i < XVECLEN (body, 0); i++)
1116 {
1117 rtx inner_insn = XVECEXP (body, 0, i);
1118 int inner_uid = INSN_UID (inner_insn);
1119 int inner_length;
1120
a30caf5c
DC
1121 if (GET_CODE (body) == ASM_INPUT
1122 || asm_noperands (PATTERN (XVECEXP (body, 0, i))) >= 0)
3cf2715d
DE
1123 inner_length = (asm_insn_count (PATTERN (inner_insn))
1124 * insn_default_length (inner_insn));
1125 else
1126 inner_length = insn_default_length (inner_insn);
f5d927c0 1127
3cf2715d
DE
1128 insn_lengths[inner_uid] = inner_length;
1129 if (const_delay_slots)
1130 {
1131 if ((varying_length[inner_uid]
1132 = insn_variable_length_p (inner_insn)) != 0)
1133 varying_length[uid] = 1;
9d98a694
AO
1134 INSN_ADDRESSES (inner_uid) = (insn_current_address
1135 + insn_lengths[uid]);
3cf2715d
DE
1136 }
1137 else
1138 varying_length[inner_uid] = 0;
1139 insn_lengths[uid] += inner_length;
1140 }
1141 }
1142 else if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER)
1143 {
1144 insn_lengths[uid] = insn_default_length (insn);
1145 varying_length[uid] = insn_variable_length_p (insn);
1146 }
1147
1148 /* If needed, do any adjustment. */
1149#ifdef ADJUST_INSN_LENGTH
1150 ADJUST_INSN_LENGTH (insn, insn_lengths[uid]);
04b6000c 1151 if (insn_lengths[uid] < 0)
c725bd79 1152 fatal_insn ("negative insn length", insn);
3cf2715d
DE
1153#endif
1154 }
1155
1156 /* Now loop over all the insns finding varying length insns. For each,
1157 get the current insn length. If it has changed, reflect the change.
1158 When nothing changes for a full pass, we are done. */
1159
1160 while (something_changed)
1161 {
1162 something_changed = 0;
fc470718 1163 insn_current_align = MAX_CODE_ALIGN - 1;
b816f339 1164 for (insn_current_address = 0, insn = first;
3cf2715d
DE
1165 insn != 0;
1166 insn = NEXT_INSN (insn))
1167 {
1168 int new_length;
b729186a 1169#ifdef ADJUST_INSN_LENGTH
3cf2715d 1170 int tmp_length;
b729186a 1171#endif
fc470718 1172 int length_align;
3cf2715d
DE
1173
1174 uid = INSN_UID (insn);
fc470718 1175
4b4bf941 1176 if (LABEL_P (insn))
fc470718
R
1177 {
1178 int log = LABEL_TO_ALIGNMENT (insn);
1179 if (log > insn_current_align)
1180 {
1181 int align = 1 << log;
ecb06768 1182 int new_address= (insn_current_address + align - 1) & -align;
fc470718
R
1183 insn_lengths[uid] = new_address - insn_current_address;
1184 insn_current_align = log;
1185 insn_current_address = new_address;
1186 }
1187 else
1188 insn_lengths[uid] = 0;
9d98a694 1189 INSN_ADDRESSES (uid) = insn_current_address;
fc470718
R
1190 continue;
1191 }
1192
1193 length_align = INSN_LENGTH_ALIGNMENT (insn);
1194 if (length_align < insn_current_align)
1195 insn_current_align = length_align;
1196
9d98a694
AO
1197 insn_last_address = INSN_ADDRESSES (uid);
1198 INSN_ADDRESSES (uid) = insn_current_address;
fc470718 1199
5e75ef4a 1200#ifdef CASE_VECTOR_SHORTEN_MODE
4b4bf941 1201 if (optimize && JUMP_P (insn)
33f7f353
JR
1202 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
1203 {
33f7f353
JR
1204 rtx body = PATTERN (insn);
1205 int old_length = insn_lengths[uid];
1206 rtx rel_lab = XEXP (XEXP (body, 0), 0);
1207 rtx min_lab = XEXP (XEXP (body, 2), 0);
1208 rtx max_lab = XEXP (XEXP (body, 3), 0);
9d98a694
AO
1209 int rel_addr = INSN_ADDRESSES (INSN_UID (rel_lab));
1210 int min_addr = INSN_ADDRESSES (INSN_UID (min_lab));
1211 int max_addr = INSN_ADDRESSES (INSN_UID (max_lab));
33f7f353
JR
1212 rtx prev;
1213 int rel_align = 0;
950a3816
KG
1214 addr_diff_vec_flags flags;
1215
1216 /* Avoid automatic aggregate initialization. */
1217 flags = ADDR_DIFF_VEC_FLAGS (body);
33f7f353
JR
1218
1219 /* Try to find a known alignment for rel_lab. */
1220 for (prev = rel_lab;
1221 prev
1222 && ! insn_lengths[INSN_UID (prev)]
1223 && ! (varying_length[INSN_UID (prev)] & 1);
1224 prev = PREV_INSN (prev))
1225 if (varying_length[INSN_UID (prev)] & 2)
1226 {
1227 rel_align = LABEL_TO_ALIGNMENT (prev);
1228 break;
1229 }
1230
1231 /* See the comment on addr_diff_vec_flags in rtl.h for the
1232 meaning of the flags values. base: REL_LAB vec: INSN */
1233 /* Anything after INSN has still addresses from the last
1234 pass; adjust these so that they reflect our current
1235 estimate for this pass. */
1236 if (flags.base_after_vec)
1237 rel_addr += insn_current_address - insn_last_address;
1238 if (flags.min_after_vec)
1239 min_addr += insn_current_address - insn_last_address;
1240 if (flags.max_after_vec)
1241 max_addr += insn_current_address - insn_last_address;
1242 /* We want to know the worst case, i.e. lowest possible value
1243 for the offset of MIN_LAB. If MIN_LAB is after REL_LAB,
1244 its offset is positive, and we have to be wary of code shrink;
1245 otherwise, it is negative, and we have to be vary of code
1246 size increase. */
1247 if (flags.min_after_base)
1248 {
1249 /* If INSN is between REL_LAB and MIN_LAB, the size
1250 changes we are about to make can change the alignment
1251 within the observed offset, therefore we have to break
1252 it up into two parts that are independent. */
1253 if (! flags.base_after_vec && flags.min_after_vec)
1254 {
1255 min_addr -= align_fuzz (rel_lab, insn, rel_align, 0);
1256 min_addr -= align_fuzz (insn, min_lab, 0, 0);
1257 }
1258 else
1259 min_addr -= align_fuzz (rel_lab, min_lab, rel_align, 0);
1260 }
1261 else
1262 {
1263 if (flags.base_after_vec && ! flags.min_after_vec)
1264 {
1265 min_addr -= align_fuzz (min_lab, insn, 0, ~0);
1266 min_addr -= align_fuzz (insn, rel_lab, 0, ~0);
1267 }
1268 else
1269 min_addr -= align_fuzz (min_lab, rel_lab, 0, ~0);
1270 }
1271 /* Likewise, determine the highest lowest possible value
1272 for the offset of MAX_LAB. */
1273 if (flags.max_after_base)
1274 {
1275 if (! flags.base_after_vec && flags.max_after_vec)
1276 {
1277 max_addr += align_fuzz (rel_lab, insn, rel_align, ~0);
1278 max_addr += align_fuzz (insn, max_lab, 0, ~0);
1279 }
1280 else
1281 max_addr += align_fuzz (rel_lab, max_lab, rel_align, ~0);
1282 }
1283 else
1284 {
1285 if (flags.base_after_vec && ! flags.max_after_vec)
1286 {
1287 max_addr += align_fuzz (max_lab, insn, 0, 0);
1288 max_addr += align_fuzz (insn, rel_lab, 0, 0);
1289 }
1290 else
1291 max_addr += align_fuzz (max_lab, rel_lab, 0, 0);
1292 }
1293 PUT_MODE (body, CASE_VECTOR_SHORTEN_MODE (min_addr - rel_addr,
1294 max_addr - rel_addr,
1295 body));
d6b5193b
RS
1296 if (JUMP_TABLES_IN_TEXT_SECTION
1297 || readonly_data_section == text_section)
75197b37
BS
1298 {
1299 insn_lengths[uid]
1300 = (XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body)));
1301 insn_current_address += insn_lengths[uid];
1302 if (insn_lengths[uid] != old_length)
1303 something_changed = 1;
1304 }
1305
33f7f353 1306 continue;
33f7f353 1307 }
5e75ef4a
JL
1308#endif /* CASE_VECTOR_SHORTEN_MODE */
1309
1310 if (! (varying_length[uid]))
3cf2715d 1311 {
4b4bf941 1312 if (NONJUMP_INSN_P (insn)
674fc07d
GS
1313 && GET_CODE (PATTERN (insn)) == SEQUENCE)
1314 {
1315 int i;
1316
1317 body = PATTERN (insn);
1318 for (i = 0; i < XVECLEN (body, 0); i++)
1319 {
1320 rtx inner_insn = XVECEXP (body, 0, i);
1321 int inner_uid = INSN_UID (inner_insn);
1322
1323 INSN_ADDRESSES (inner_uid) = insn_current_address;
1324
1325 insn_current_address += insn_lengths[inner_uid];
1326 }
dd3f0101 1327 }
674fc07d
GS
1328 else
1329 insn_current_address += insn_lengths[uid];
1330
3cf2715d
DE
1331 continue;
1332 }
674fc07d 1333
4b4bf941 1334 if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
3cf2715d
DE
1335 {
1336 int i;
f5d927c0 1337
3cf2715d
DE
1338 body = PATTERN (insn);
1339 new_length = 0;
1340 for (i = 0; i < XVECLEN (body, 0); i++)
1341 {
1342 rtx inner_insn = XVECEXP (body, 0, i);
1343 int inner_uid = INSN_UID (inner_insn);
1344 int inner_length;
1345
9d98a694 1346 INSN_ADDRESSES (inner_uid) = insn_current_address;
3cf2715d
DE
1347
1348 /* insn_current_length returns 0 for insns with a
1349 non-varying length. */
1350 if (! varying_length[inner_uid])
1351 inner_length = insn_lengths[inner_uid];
1352 else
1353 inner_length = insn_current_length (inner_insn);
1354
1355 if (inner_length != insn_lengths[inner_uid])
1356 {
1357 insn_lengths[inner_uid] = inner_length;
1358 something_changed = 1;
1359 }
1360 insn_current_address += insn_lengths[inner_uid];
1361 new_length += inner_length;
1362 }
1363 }
1364 else
1365 {
1366 new_length = insn_current_length (insn);
1367 insn_current_address += new_length;
1368 }
1369
3cf2715d
DE
1370#ifdef ADJUST_INSN_LENGTH
1371 /* If needed, do any adjustment. */
1372 tmp_length = new_length;
1373 ADJUST_INSN_LENGTH (insn, new_length);
1374 insn_current_address += (new_length - tmp_length);
3cf2715d
DE
1375#endif
1376
1377 if (new_length != insn_lengths[uid])
1378 {
1379 insn_lengths[uid] = new_length;
1380 something_changed = 1;
1381 }
1382 }
bb4aaf18
TG
1383 /* For a non-optimizing compile, do only a single pass. */
1384 if (!optimize)
1385 break;
3cf2715d 1386 }
fc470718
R
1387
1388 free (varying_length);
1389
3cf2715d
DE
1390#endif /* HAVE_ATTR_length */
1391}
1392
1393#ifdef HAVE_ATTR_length
1394/* Given the body of an INSN known to be generated by an ASM statement, return
1395 the number of machine instructions likely to be generated for this insn.
1396 This is used to compute its length. */
1397
1398static int
6cf9ac28 1399asm_insn_count (rtx body)
3cf2715d 1400{
48c54229 1401 const char *templ;
3cf2715d 1402
5d0930ea 1403 if (GET_CODE (body) == ASM_INPUT)
48c54229 1404 templ = XSTR (body, 0);
5d0930ea 1405 else
48c54229 1406 templ = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
5d0930ea 1407
2bd1d2c8
AP
1408 return asm_str_count (templ);
1409}
1410#endif
1411
1412/* Return the number of machine instructions likely to be generated for the
1413 inline-asm template. */
1414int
1415asm_str_count (const char *templ)
1416{
1417 int count = 1;
b8698a0f 1418
48c54229 1419 if (!*templ)
5bc4fa7c
MS
1420 return 0;
1421
48c54229
KG
1422 for (; *templ; templ++)
1423 if (IS_ASM_LOGICAL_LINE_SEPARATOR (*templ, templ)
1424 || *templ == '\n')
3cf2715d
DE
1425 count++;
1426
1427 return count;
1428}
3cf2715d 1429\f
c8aea42c
PB
1430/* ??? This is probably the wrong place for these. */
1431/* Structure recording the mapping from source file and directory
1432 names at compile time to those to be embedded in debug
1433 information. */
1434typedef struct debug_prefix_map
1435{
1436 const char *old_prefix;
1437 const char *new_prefix;
1438 size_t old_len;
1439 size_t new_len;
1440 struct debug_prefix_map *next;
1441} debug_prefix_map;
1442
1443/* Linked list of such structures. */
1444debug_prefix_map *debug_prefix_maps;
1445
1446
1447/* Record a debug file prefix mapping. ARG is the argument to
1448 -fdebug-prefix-map and must be of the form OLD=NEW. */
1449
1450void
1451add_debug_prefix_map (const char *arg)
1452{
1453 debug_prefix_map *map;
1454 const char *p;
1455
1456 p = strchr (arg, '=');
1457 if (!p)
1458 {
1459 error ("invalid argument %qs to -fdebug-prefix-map", arg);
1460 return;
1461 }
1462 map = XNEW (debug_prefix_map);
fe83055d 1463 map->old_prefix = xstrndup (arg, p - arg);
c8aea42c
PB
1464 map->old_len = p - arg;
1465 p++;
fe83055d 1466 map->new_prefix = xstrdup (p);
c8aea42c
PB
1467 map->new_len = strlen (p);
1468 map->next = debug_prefix_maps;
1469 debug_prefix_maps = map;
1470}
1471
1472/* Perform user-specified mapping of debug filename prefixes. Return
1473 the new name corresponding to FILENAME. */
1474
1475const char *
1476remap_debug_filename (const char *filename)
1477{
1478 debug_prefix_map *map;
1479 char *s;
1480 const char *name;
1481 size_t name_len;
1482
1483 for (map = debug_prefix_maps; map; map = map->next)
1484 if (strncmp (filename, map->old_prefix, map->old_len) == 0)
1485 break;
1486 if (!map)
1487 return filename;
1488 name = filename + map->old_len;
1489 name_len = strlen (name) + 1;
1490 s = (char *) alloca (name_len + map->new_len);
1491 memcpy (s, map->new_prefix, map->new_len);
1492 memcpy (s + map->new_len, name, name_len);
1493 return ggc_strdup (s);
1494}
1495\f
725730f2
EB
1496/* Return true if DWARF2 debug info can be emitted for DECL. */
1497
1498static bool
1499dwarf2_debug_info_emitted_p (tree decl)
1500{
1501 if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG)
1502 return false;
1503
1504 if (DECL_IGNORED_P (decl))
1505 return false;
1506
1507 return true;
1508}
1509
3cf2715d
DE
1510/* Output assembler code for the start of a function,
1511 and initialize some of the variables in this file
1512 for the new function. The label for the function and associated
1513 assembler pseudo-ops have already been output in `assemble_start_function'.
1514
1515 FIRST is the first insn of the rtl for the function being compiled.
1516 FILE is the file to write assembler code to.
1517 OPTIMIZE is nonzero if we should eliminate redundant
1518 test and compare insns. */
1519
1520void
6cf9ac28
AJ
1521final_start_function (rtx first ATTRIBUTE_UNUSED, FILE *file,
1522 int optimize ATTRIBUTE_UNUSED)
3cf2715d
DE
1523{
1524 block_depth = 0;
1525
1526 this_is_asm_operands = 0;
1527
9ae130f8
JH
1528 last_filename = locator_file (prologue_locator);
1529 last_linenum = locator_line (prologue_locator);
6c52e687 1530 last_discriminator = discriminator = 0;
9ae130f8 1531
653e276c 1532 high_block_linenum = high_function_linenum = last_linenum;
eac40081 1533
725730f2
EB
1534 if (!DECL_IGNORED_P (current_function_decl))
1535 debug_hooks->begin_prologue (last_linenum, last_filename);
d291dd49 1536
951120ea 1537#if defined (DWARF2_UNWIND_INFO) || defined (TARGET_UNWIND_INFO)
725730f2 1538 if (!dwarf2_debug_info_emitted_p (current_function_decl))
653e276c 1539 dwarf2out_begin_prologue (0, NULL);
f5d927c0 1540#endif
3cf2715d
DE
1541
1542#ifdef LEAF_REG_REMAP
54ff41b7 1543 if (current_function_uses_only_leaf_regs)
3cf2715d
DE
1544 leaf_renumber_regs (first);
1545#endif
1546
1547 /* The Sun386i and perhaps other machines don't work right
1548 if the profiling code comes after the prologue. */
1549#ifdef PROFILE_BEFORE_PROLOGUE
e3b5732b 1550 if (crtl->profile)
3cf2715d
DE
1551 profile_function (file);
1552#endif /* PROFILE_BEFORE_PROLOGUE */
1553
0021b564
JM
1554#if defined (DWARF2_UNWIND_INFO) && defined (HAVE_prologue)
1555 if (dwarf2out_do_frame ())
e0c0490b 1556 dwarf2out_frame_debug (NULL_RTX, false);
0021b564
JM
1557#endif
1558
18c038b9
MM
1559 /* If debugging, assign block numbers to all of the blocks in this
1560 function. */
1561 if (write_symbols)
1562 {
0435312e 1563 reemit_insn_block_notes ();
a20612aa 1564 number_blocks (current_function_decl);
18c038b9
MM
1565 /* We never actually put out begin/end notes for the top-level
1566 block in the function. But, conceptually, that block is
1567 always needed. */
1568 TREE_ASM_WRITTEN (DECL_INITIAL (current_function_decl)) = 1;
1569 }
1570
a214518f
SP
1571 if (warn_frame_larger_than
1572 && get_frame_size () > frame_larger_than_size)
1573 {
1574 /* Issue a warning */
1575 warning (OPT_Wframe_larger_than_,
1576 "the frame size of %wd bytes is larger than %wd bytes",
1577 get_frame_size (), frame_larger_than_size);
1578 }
1579
3cf2715d 1580 /* First output the function prologue: code to set up the stack frame. */
5fd9b178 1581 targetm.asm_out.function_prologue (file, get_frame_size ());
3cf2715d 1582
3cf2715d
DE
1583 /* If the machine represents the prologue as RTL, the profiling code must
1584 be emitted when NOTE_INSN_PROLOGUE_END is scanned. */
1585#ifdef HAVE_prologue
1586 if (! HAVE_prologue)
1587#endif
1588 profile_after_prologue (file);
3cf2715d
DE
1589}
1590
1591static void
6cf9ac28 1592profile_after_prologue (FILE *file ATTRIBUTE_UNUSED)
3cf2715d 1593{
3cf2715d 1594#ifndef PROFILE_BEFORE_PROLOGUE
e3b5732b 1595 if (crtl->profile)
3cf2715d
DE
1596 profile_function (file);
1597#endif /* not PROFILE_BEFORE_PROLOGUE */
1598}
1599
1600static void
6cf9ac28 1601profile_function (FILE *file ATTRIBUTE_UNUSED)
3cf2715d 1602{
dcacfa04 1603#ifndef NO_PROFILE_COUNTERS
9739c90c 1604# define NO_PROFILE_COUNTERS 0
dcacfa04 1605#endif
531ca746
RH
1606#ifdef ASM_OUTPUT_REG_PUSH
1607 rtx sval = NULL, chain = NULL;
1608
1609 if (cfun->returns_struct)
1610 sval = targetm.calls.struct_value_rtx (TREE_TYPE (current_function_decl),
1611 true);
1612 if (cfun->static_chain_decl)
1613 chain = targetm.calls.static_chain (current_function_decl, true);
b729186a 1614#endif /* ASM_OUTPUT_REG_PUSH */
3cf2715d 1615
9739c90c
JJ
1616 if (! NO_PROFILE_COUNTERS)
1617 {
1618 int align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
d6b5193b 1619 switch_to_section (data_section);
9739c90c 1620 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
5fd9b178 1621 targetm.asm_out.internal_label (file, "LP", current_function_funcdef_no);
9739c90c
JJ
1622 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
1623 }
3cf2715d 1624
d6b5193b 1625 switch_to_section (current_function_section ());
3cf2715d 1626
531ca746
RH
1627#ifdef ASM_OUTPUT_REG_PUSH
1628 if (sval && REG_P (sval))
1629 ASM_OUTPUT_REG_PUSH (file, REGNO (sval));
1630 if (chain && REG_P (chain))
1631 ASM_OUTPUT_REG_PUSH (file, REGNO (chain));
3cf2715d 1632#endif
3cf2715d 1633
df696a75 1634 FUNCTION_PROFILER (file, current_function_funcdef_no);
3cf2715d 1635
531ca746
RH
1636#ifdef ASM_OUTPUT_REG_PUSH
1637 if (chain && REG_P (chain))
1638 ASM_OUTPUT_REG_POP (file, REGNO (chain));
1639 if (sval && REG_P (sval))
1640 ASM_OUTPUT_REG_POP (file, REGNO (sval));
3cf2715d
DE
1641#endif
1642}
1643
1644/* Output assembler code for the end of a function.
1645 For clarity, args are same as those of `final_start_function'
1646 even though not all of them are needed. */
1647
1648void
6cf9ac28 1649final_end_function (void)
3cf2715d 1650{
be1bb652 1651 app_disable ();
3cf2715d 1652
725730f2
EB
1653 if (!DECL_IGNORED_P (current_function_decl))
1654 debug_hooks->end_function (high_function_linenum);
3cf2715d 1655
3cf2715d
DE
1656 /* Finally, output the function epilogue:
1657 code to restore the stack frame and return to the caller. */
5fd9b178 1658 targetm.asm_out.function_epilogue (asm_out_file, get_frame_size ());
3cf2715d 1659
e2a12aca 1660 /* And debug output. */
725730f2
EB
1661 if (!DECL_IGNORED_P (current_function_decl))
1662 debug_hooks->end_epilogue (last_linenum, last_filename);
3cf2715d 1663
e2a12aca 1664#if defined (DWARF2_UNWIND_INFO)
725730f2 1665 if (!dwarf2_debug_info_emitted_p (current_function_decl)
7a0c8d71 1666 && dwarf2out_do_frame ())
702ada3d 1667 dwarf2out_end_epilogue (last_linenum, last_filename);
9a666dda 1668#endif
3cf2715d
DE
1669}
1670\f
3cf2715d 1671/* Output assembler code for some insns: all or part of a function.
c9d691e9 1672 For description of args, see `final_start_function', above. */
3cf2715d
DE
1673
1674void
c9d691e9 1675final (rtx first, FILE *file, int optimize)
3cf2715d 1676{
b3694847 1677 rtx insn;
a8c3510c 1678 int max_uid = 0;
589fe865 1679 int seen = 0;
3cf2715d
DE
1680
1681 last_ignored_compare = 0;
3cf2715d 1682
3cf2715d 1683 for (insn = first; insn; insn = NEXT_INSN (insn))
a8c3510c 1684 {
938d968e 1685 if (INSN_UID (insn) > max_uid) /* Find largest UID. */
f5d927c0 1686 max_uid = INSN_UID (insn);
9ef4c6ef
JC
1687#ifdef HAVE_cc0
1688 /* If CC tracking across branches is enabled, record the insn which
1689 jumps to each branch only reached from one place. */
4b4bf941 1690 if (optimize && JUMP_P (insn))
9ef4c6ef
JC
1691 {
1692 rtx lab = JUMP_LABEL (insn);
1693 if (lab && LABEL_NUSES (lab) == 1)
1694 {
1695 LABEL_REFS (lab) = insn;
1696 }
1697 }
1698#endif
a8c3510c
AM
1699 }
1700
3cf2715d
DE
1701 init_recog ();
1702
1703 CC_STATUS_INIT;
1704
1705 /* Output the insns. */
9ff57809 1706 for (insn = first; insn;)
2f16edb1
TG
1707 {
1708#ifdef HAVE_ATTR_length
b9f22704 1709 if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
0ac76ad9 1710 {
0ac76ad9
RH
1711 /* This can be triggered by bugs elsewhere in the compiler if
1712 new insns are created after init_insn_lengths is called. */
0bccc606
NS
1713 gcc_assert (NOTE_P (insn));
1714 insn_current_address = -1;
0ac76ad9
RH
1715 }
1716 else
9d98a694 1717 insn_current_address = INSN_ADDRESSES (INSN_UID (insn));
0ac76ad9
RH
1718#endif /* HAVE_ATTR_length */
1719
c9d691e9 1720 insn = final_scan_insn (insn, file, optimize, 0, &seen);
2f16edb1 1721 }
3cf2715d
DE
1722}
1723\f
4bbf910e 1724const char *
6cf9ac28 1725get_insn_template (int code, rtx insn)
4bbf910e 1726{
4bbf910e
RH
1727 switch (insn_data[code].output_format)
1728 {
1729 case INSN_OUTPUT_FORMAT_SINGLE:
3897f229 1730 return insn_data[code].output.single;
4bbf910e 1731 case INSN_OUTPUT_FORMAT_MULTI:
3897f229 1732 return insn_data[code].output.multi[which_alternative];
4bbf910e 1733 case INSN_OUTPUT_FORMAT_FUNCTION:
0bccc606 1734 gcc_assert (insn);
3897f229 1735 return (*insn_data[code].output.function) (recog_data.operand, insn);
4bbf910e
RH
1736
1737 default:
0bccc606 1738 gcc_unreachable ();
4bbf910e
RH
1739 }
1740}
f5d927c0 1741
0dc36574
ZW
1742/* Emit the appropriate declaration for an alternate-entry-point
1743 symbol represented by INSN, to FILE. INSN is a CODE_LABEL with
1744 LABEL_KIND != LABEL_NORMAL.
1745
1746 The case fall-through in this function is intentional. */
1747static void
6cf9ac28 1748output_alternate_entry_point (FILE *file, rtx insn)
0dc36574
ZW
1749{
1750 const char *name = LABEL_NAME (insn);
1751
1752 switch (LABEL_KIND (insn))
1753 {
1754 case LABEL_WEAK_ENTRY:
1755#ifdef ASM_WEAKEN_LABEL
1756 ASM_WEAKEN_LABEL (file, name);
1757#endif
1758 case LABEL_GLOBAL_ENTRY:
5fd9b178 1759 targetm.asm_out.globalize_label (file, name);
0dc36574 1760 case LABEL_STATIC_ENTRY:
905173eb
ZW
1761#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
1762 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
1763#endif
0dc36574
ZW
1764 ASM_OUTPUT_LABEL (file, name);
1765 break;
1766
1767 case LABEL_NORMAL:
1768 default:
0bccc606 1769 gcc_unreachable ();
0dc36574
ZW
1770 }
1771}
1772
f410e1b3
RAE
1773/* Given a CALL_INSN, find and return the nested CALL. */
1774static rtx
1775call_from_call_insn (rtx insn)
1776{
1777 rtx x;
1778 gcc_assert (CALL_P (insn));
1779 x = PATTERN (insn);
1780
1781 while (GET_CODE (x) != CALL)
1782 {
1783 switch (GET_CODE (x))
1784 {
1785 default:
1786 gcc_unreachable ();
b8c71e40
RAE
1787 case COND_EXEC:
1788 x = COND_EXEC_CODE (x);
1789 break;
f410e1b3
RAE
1790 case PARALLEL:
1791 x = XVECEXP (x, 0, 0);
1792 break;
1793 case SET:
1794 x = XEXP (x, 1);
1795 break;
1796 }
1797 }
1798 return x;
1799}
1800
3cf2715d
DE
1801/* The final scan for one insn, INSN.
1802 Args are same as in `final', except that INSN
1803 is the insn being scanned.
1804 Value returned is the next insn to be scanned.
1805
ff8cea7e
EB
1806 NOPEEPHOLES is the flag to disallow peephole processing (currently
1807 used for within delayed branch sequence output).
3cf2715d 1808
589fe865
DJ
1809 SEEN is used to track the end of the prologue, for emitting
1810 debug information. We force the emission of a line note after
1811 both NOTE_INSN_PROLOGUE_END and NOTE_INSN_FUNCTION_BEG, or
1812 at the beginning of the second basic block, whichever comes
1813 first. */
1814
5cfc5f84 1815rtx
6cf9ac28 1816final_scan_insn (rtx insn, FILE *file, int optimize ATTRIBUTE_UNUSED,
c9d691e9 1817 int nopeepholes ATTRIBUTE_UNUSED, int *seen)
3cf2715d 1818{
90ca38bb
MM
1819#ifdef HAVE_cc0
1820 rtx set;
1821#endif
b2a6a2fb 1822 rtx next;
90ca38bb 1823
3cf2715d
DE
1824 insn_counter++;
1825
1826 /* Ignore deleted insns. These can occur when we split insns (due to a
1827 template of "#") while not optimizing. */
1828 if (INSN_DELETED_P (insn))
1829 return NEXT_INSN (insn);
1830
1831 switch (GET_CODE (insn))
1832 {
1833 case NOTE:
a38e7aa5 1834 switch (NOTE_KIND (insn))
be1bb652
RH
1835 {
1836 case NOTE_INSN_DELETED:
be1bb652 1837 break;
3cf2715d 1838
87c8b4be 1839 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
c543ca49 1840 in_cold_section_p = !in_cold_section_p;
a4b6974e
UB
1841#ifdef DWARF2_UNWIND_INFO
1842 if (dwarf2out_do_frame ())
1843 dwarf2out_switch_text_section ();
1844 else
1845#endif
725730f2
EB
1846 if (!DECL_IGNORED_P (current_function_decl))
1847 debug_hooks->switch_text_section ();
a4b6974e 1848
c543ca49 1849 switch_to_section (current_function_section ());
750054a2 1850 break;
b0efb46b 1851
be1bb652 1852 case NOTE_INSN_BASIC_BLOCK:
951120ea
PB
1853#ifdef TARGET_UNWIND_INFO
1854 targetm.asm_out.unwind_emit (asm_out_file, insn);
ad0fc698 1855#endif
951120ea 1856
be1bb652
RH
1857 if (flag_debug_asm)
1858 fprintf (asm_out_file, "\t%s basic block %d\n",
0b17ab2f 1859 ASM_COMMENT_START, NOTE_BASIC_BLOCK (insn)->index);
589fe865
DJ
1860
1861 if ((*seen & (SEEN_EMITTED | SEEN_BB)) == SEEN_BB)
1862 {
1863 *seen |= SEEN_EMITTED;
b8176fe4 1864 force_source_line = true;
589fe865
DJ
1865 }
1866 else
1867 *seen |= SEEN_BB;
1868
6c52e687
CC
1869 discriminator = NOTE_BASIC_BLOCK (insn)->discriminator;
1870
be1bb652 1871 break;
3cf2715d 1872
be1bb652 1873 case NOTE_INSN_EH_REGION_BEG:
52a11cbf
RH
1874 ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHB",
1875 NOTE_EH_HANDLER (insn));
3d195391 1876 break;
3d195391 1877
be1bb652 1878 case NOTE_INSN_EH_REGION_END:
52a11cbf
RH
1879 ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHE",
1880 NOTE_EH_HANDLER (insn));
3d195391 1881 break;
3d195391 1882
be1bb652 1883 case NOTE_INSN_PROLOGUE_END:
5fd9b178 1884 targetm.asm_out.function_end_prologue (file);
3cf2715d 1885 profile_after_prologue (file);
589fe865
DJ
1886
1887 if ((*seen & (SEEN_EMITTED | SEEN_NOTE)) == SEEN_NOTE)
1888 {
1889 *seen |= SEEN_EMITTED;
b8176fe4 1890 force_source_line = true;
589fe865
DJ
1891 }
1892 else
1893 *seen |= SEEN_NOTE;
1894
3cf2715d 1895 break;
3cf2715d 1896
be1bb652 1897 case NOTE_INSN_EPILOGUE_BEG:
cd9c1ca8
RH
1898#if defined (DWARF2_UNWIND_INFO) && defined (HAVE_epilogue)
1899 if (dwarf2out_do_frame ())
1900 dwarf2out_begin_epilogue (insn);
1901#endif
5fd9b178 1902 targetm.asm_out.function_begin_epilogue (file);
be1bb652 1903 break;
3cf2715d 1904
cd9c1ca8
RH
1905 case NOTE_INSN_CFA_RESTORE_STATE:
1906#if defined (DWARF2_UNWIND_INFO)
1907 dwarf2out_frame_debug_restore_state ();
1908#endif
1909 break;
1910
be1bb652 1911 case NOTE_INSN_FUNCTION_BEG:
653e276c 1912 app_disable ();
725730f2
EB
1913 if (!DECL_IGNORED_P (current_function_decl))
1914 debug_hooks->end_prologue (last_linenum, last_filename);
589fe865
DJ
1915
1916 if ((*seen & (SEEN_EMITTED | SEEN_NOTE)) == SEEN_NOTE)
1917 {
1918 *seen |= SEEN_EMITTED;
b8176fe4 1919 force_source_line = true;
589fe865
DJ
1920 }
1921 else
1922 *seen |= SEEN_NOTE;
1923
3cf2715d 1924 break;
be1bb652
RH
1925
1926 case NOTE_INSN_BLOCK_BEG:
1927 if (debug_info_level == DINFO_LEVEL_NORMAL
3cf2715d 1928 || debug_info_level == DINFO_LEVEL_VERBOSE
7a0c8d71
DR
1929 || write_symbols == DWARF2_DEBUG
1930 || write_symbols == VMS_AND_DWARF2_DEBUG
1931 || write_symbols == VMS_DEBUG)
be1bb652
RH
1932 {
1933 int n = BLOCK_NUMBER (NOTE_BLOCK (insn));
3cf2715d 1934
be1bb652
RH
1935 app_disable ();
1936 ++block_depth;
1937 high_block_linenum = last_linenum;
eac40081 1938
a5a42b92 1939 /* Output debugging info about the symbol-block beginning. */
725730f2
EB
1940 if (!DECL_IGNORED_P (current_function_decl))
1941 debug_hooks->begin_block (last_linenum, n);
3cf2715d 1942
be1bb652
RH
1943 /* Mark this block as output. */
1944 TREE_ASM_WRITTEN (NOTE_BLOCK (insn)) = 1;
1945 }
d752cfdb
JJ
1946 if (write_symbols == DBX_DEBUG
1947 || write_symbols == SDB_DEBUG)
1948 {
1949 location_t *locus_ptr
1950 = block_nonartificial_location (NOTE_BLOCK (insn));
1951
1952 if (locus_ptr != NULL)
1953 {
1954 override_filename = LOCATION_FILE (*locus_ptr);
1955 override_linenum = LOCATION_LINE (*locus_ptr);
1956 }
1957 }
be1bb652 1958 break;
18c038b9 1959
be1bb652
RH
1960 case NOTE_INSN_BLOCK_END:
1961 if (debug_info_level == DINFO_LEVEL_NORMAL
1962 || debug_info_level == DINFO_LEVEL_VERBOSE
7a0c8d71
DR
1963 || write_symbols == DWARF2_DEBUG
1964 || write_symbols == VMS_AND_DWARF2_DEBUG
1965 || write_symbols == VMS_DEBUG)
be1bb652
RH
1966 {
1967 int n = BLOCK_NUMBER (NOTE_BLOCK (insn));
3cf2715d 1968
be1bb652
RH
1969 app_disable ();
1970
1971 /* End of a symbol-block. */
1972 --block_depth;
0bccc606 1973 gcc_assert (block_depth >= 0);
3cf2715d 1974
725730f2
EB
1975 if (!DECL_IGNORED_P (current_function_decl))
1976 debug_hooks->end_block (high_block_linenum, n);
be1bb652 1977 }
d752cfdb
JJ
1978 if (write_symbols == DBX_DEBUG
1979 || write_symbols == SDB_DEBUG)
1980 {
1981 tree outer_block = BLOCK_SUPERCONTEXT (NOTE_BLOCK (insn));
1982 location_t *locus_ptr
1983 = block_nonartificial_location (outer_block);
1984
1985 if (locus_ptr != NULL)
1986 {
1987 override_filename = LOCATION_FILE (*locus_ptr);
1988 override_linenum = LOCATION_LINE (*locus_ptr);
1989 }
1990 else
1991 {
1992 override_filename = NULL;
1993 override_linenum = 0;
1994 }
1995 }
be1bb652
RH
1996 break;
1997
1998 case NOTE_INSN_DELETED_LABEL:
1999 /* Emit the label. We may have deleted the CODE_LABEL because
2000 the label could be proved to be unreachable, though still
2001 referenced (in the form of having its address taken. */
8215347e 2002 ASM_OUTPUT_DEBUG_LABEL (file, "L", CODE_LABEL_NUMBER (insn));
be1bb652 2003 break;
3cf2715d 2004
014a1138 2005 case NOTE_INSN_VAR_LOCATION:
725730f2
EB
2006 if (!DECL_IGNORED_P (current_function_decl))
2007 debug_hooks->var_location (insn);
014a1138
JZ
2008 break;
2009
be1bb652 2010 default:
a38e7aa5 2011 gcc_unreachable ();
f5d927c0 2012 break;
3cf2715d
DE
2013 }
2014 break;
2015
2016 case BARRIER:
f73ad30e 2017#if defined (DWARF2_UNWIND_INFO)
fbfa55b0 2018 if (dwarf2out_do_frame ())
e0c0490b 2019 dwarf2out_frame_debug (insn, false);
3cf2715d
DE
2020#endif
2021 break;
2022
2023 case CODE_LABEL:
1dd8faa8
R
2024 /* The target port might emit labels in the output function for
2025 some insn, e.g. sh.c output_branchy_insn. */
de7987a6
R
2026 if (CODE_LABEL_NUMBER (insn) <= max_labelno)
2027 {
2028 int align = LABEL_TO_ALIGNMENT (insn);
50b2596f 2029#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
9e423e6d 2030 int max_skip = LABEL_TO_MAX_SKIP (insn);
50b2596f 2031#endif
fc470718 2032
1dd8faa8 2033 if (align && NEXT_INSN (insn))
40cdfca6 2034 {
9e423e6d 2035#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
40cdfca6 2036 ASM_OUTPUT_MAX_SKIP_ALIGN (file, align, max_skip);
8e16ab99
SF
2037#else
2038#ifdef ASM_OUTPUT_ALIGN_WITH_NOP
2039 ASM_OUTPUT_ALIGN_WITH_NOP (file, align);
9e423e6d 2040#else
40cdfca6 2041 ASM_OUTPUT_ALIGN (file, align);
8e16ab99 2042#endif
9e423e6d 2043#endif
40cdfca6 2044 }
de7987a6 2045 }
9ef4c6ef 2046#ifdef HAVE_cc0
3cf2715d 2047 CC_STATUS_INIT;
9ef4c6ef 2048#endif
03ffa171 2049
725730f2
EB
2050 if (!DECL_IGNORED_P (current_function_decl) && LABEL_NAME (insn))
2051 debug_hooks->label (insn);
e1772ac0 2052
bad4f40b 2053 app_disable ();
b2a6a2fb
JJ
2054
2055 next = next_nonnote_insn (insn);
0676c393
MM
2056 /* If this label is followed by a jump-table, make sure we put
2057 the label in the read-only section. Also possibly write the
2058 label and jump table together. */
2059 if (next != 0 && JUMP_TABLE_DATA_P (next))
3cf2715d 2060 {
e0d80184 2061#if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
0676c393
MM
2062 /* In this case, the case vector is being moved by the
2063 target, so don't output the label at all. Leave that
2064 to the back end macros. */
e0d80184 2065#else
0676c393
MM
2066 if (! JUMP_TABLES_IN_TEXT_SECTION)
2067 {
2068 int log_align;
340f7e7c 2069
0676c393
MM
2070 switch_to_section (targetm.asm_out.function_rodata_section
2071 (current_function_decl));
340f7e7c
RH
2072
2073#ifdef ADDR_VEC_ALIGN
0676c393 2074 log_align = ADDR_VEC_ALIGN (next);
340f7e7c 2075#else
0676c393 2076 log_align = exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT);
340f7e7c 2077#endif
0676c393
MM
2078 ASM_OUTPUT_ALIGN (file, log_align);
2079 }
2080 else
2081 switch_to_section (current_function_section ());
75197b37 2082
3cf2715d 2083#ifdef ASM_OUTPUT_CASE_LABEL
0676c393
MM
2084 ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn),
2085 next);
3cf2715d 2086#else
0676c393 2087 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn));
e0d80184 2088#endif
3cf2715d 2089#endif
0676c393 2090 break;
3cf2715d 2091 }
0dc36574
ZW
2092 if (LABEL_ALT_ENTRY_P (insn))
2093 output_alternate_entry_point (file, insn);
8cd0faaf 2094 else
5fd9b178 2095 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn));
3cf2715d
DE
2096 break;
2097
2098 default:
2099 {
b3694847 2100 rtx body = PATTERN (insn);
3cf2715d 2101 int insn_code_number;
48c54229 2102 const char *templ;
ed5ef2e4 2103 bool is_stmt;
3cf2715d 2104
9a1a4737
PB
2105 /* Reset this early so it is correct for ASM statements. */
2106 current_insn_predicate = NULL_RTX;
2929029c 2107
3cf2715d
DE
2108 /* An INSN, JUMP_INSN or CALL_INSN.
2109 First check for special kinds that recog doesn't recognize. */
2110
6614fd40 2111 if (GET_CODE (body) == USE /* These are just declarations. */
3cf2715d
DE
2112 || GET_CODE (body) == CLOBBER)
2113 break;
2114
2115#ifdef HAVE_cc0
4928181c
SB
2116 {
2117 /* If there is a REG_CC_SETTER note on this insn, it means that
2118 the setting of the condition code was done in the delay slot
2119 of the insn that branched here. So recover the cc status
2120 from the insn that set it. */
3cf2715d 2121
4928181c
SB
2122 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
2123 if (note)
2124 {
2125 NOTICE_UPDATE_CC (PATTERN (XEXP (note, 0)), XEXP (note, 0));
2126 cc_prev_status = cc_status;
2127 }
2128 }
3cf2715d
DE
2129#endif
2130
2131 /* Detect insns that are really jump-tables
2132 and output them as such. */
2133
2134 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
2135 {
7f7f8214 2136#if !(defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC))
b3694847 2137 int vlen, idx;
7f7f8214 2138#endif
3cf2715d 2139
b2a6a2fb 2140 if (! JUMP_TABLES_IN_TEXT_SECTION)
d6b5193b
RS
2141 switch_to_section (targetm.asm_out.function_rodata_section
2142 (current_function_decl));
b2a6a2fb 2143 else
d6b5193b 2144 switch_to_section (current_function_section ());
b2a6a2fb 2145
bad4f40b 2146 app_disable ();
3cf2715d 2147
e0d80184
DM
2148#if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
2149 if (GET_CODE (body) == ADDR_VEC)
2150 {
2151#ifdef ASM_OUTPUT_ADDR_VEC
2152 ASM_OUTPUT_ADDR_VEC (PREV_INSN (insn), body);
2153#else
0bccc606 2154 gcc_unreachable ();
e0d80184
DM
2155#endif
2156 }
2157 else
2158 {
2159#ifdef ASM_OUTPUT_ADDR_DIFF_VEC
2160 ASM_OUTPUT_ADDR_DIFF_VEC (PREV_INSN (insn), body);
2161#else
0bccc606 2162 gcc_unreachable ();
e0d80184
DM
2163#endif
2164 }
2165#else
3cf2715d
DE
2166 vlen = XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC);
2167 for (idx = 0; idx < vlen; idx++)
2168 {
2169 if (GET_CODE (body) == ADDR_VEC)
2170 {
2171#ifdef ASM_OUTPUT_ADDR_VEC_ELT
2172 ASM_OUTPUT_ADDR_VEC_ELT
2173 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
2174#else
0bccc606 2175 gcc_unreachable ();
3cf2715d
DE
2176#endif
2177 }
2178 else
2179 {
2180#ifdef ASM_OUTPUT_ADDR_DIFF_ELT
2181 ASM_OUTPUT_ADDR_DIFF_ELT
2182 (file,
33f7f353 2183 body,
3cf2715d
DE
2184 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
2185 CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0)));
2186#else
0bccc606 2187 gcc_unreachable ();
3cf2715d
DE
2188#endif
2189 }
2190 }
2191#ifdef ASM_OUTPUT_CASE_END
2192 ASM_OUTPUT_CASE_END (file,
2193 CODE_LABEL_NUMBER (PREV_INSN (insn)),
2194 insn);
e0d80184 2195#endif
3cf2715d
DE
2196#endif
2197
d6b5193b 2198 switch_to_section (current_function_section ());
3cf2715d
DE
2199
2200 break;
2201 }
0435312e
JH
2202 /* Output this line note if it is the first or the last line
2203 note in a row. */
725730f2
EB
2204 if (!DECL_IGNORED_P (current_function_decl)
2205 && notice_source_line (insn, &is_stmt))
2206 (*debug_hooks->source_line) (last_linenum, last_filename,
2207 last_discriminator, is_stmt);
3cf2715d 2208
3cf2715d
DE
2209 if (GET_CODE (body) == ASM_INPUT)
2210 {
36d7136e
RH
2211 const char *string = XSTR (body, 0);
2212
3cf2715d
DE
2213 /* There's no telling what that did to the condition codes. */
2214 CC_STATUS_INIT;
36d7136e
RH
2215
2216 if (string[0])
3cf2715d 2217 {
5ffeb913 2218 expanded_location loc;
bff4b63d 2219
3a694d86 2220 app_enable ();
5ffeb913 2221 loc = expand_location (ASM_INPUT_SOURCE_LOCATION (body));
0de2ae02 2222 if (*loc.file && loc.line)
bff4b63d
AO
2223 fprintf (asm_out_file, "%s %i \"%s\" 1\n",
2224 ASM_COMMENT_START, loc.line, loc.file);
36d7136e 2225 fprintf (asm_out_file, "\t%s\n", string);
03943c05
AO
2226#if HAVE_AS_LINE_ZERO
2227 if (*loc.file && loc.line)
bff4b63d 2228 fprintf (asm_out_file, "%s 0 \"\" 2\n", ASM_COMMENT_START);
03943c05 2229#endif
3cf2715d 2230 }
3cf2715d
DE
2231 break;
2232 }
2233
2234 /* Detect `asm' construct with operands. */
2235 if (asm_noperands (body) >= 0)
2236 {
22bf4422 2237 unsigned int noperands = asm_noperands (body);
1b4572a8 2238 rtx *ops = XALLOCAVEC (rtx, noperands);
3cce094d 2239 const char *string;
bff4b63d 2240 location_t loc;
5ffeb913 2241 expanded_location expanded;
3cf2715d
DE
2242
2243 /* There's no telling what that did to the condition codes. */
2244 CC_STATUS_INIT;
3cf2715d 2245
3cf2715d 2246 /* Get out the operand values. */
bff4b63d 2247 string = decode_asm_operands (body, ops, NULL, NULL, NULL, &loc);
41129be2 2248 /* Inhibit dying on what would otherwise be compiler bugs. */
3cf2715d
DE
2249 insn_noperands = noperands;
2250 this_is_asm_operands = insn;
5ffeb913 2251 expanded = expand_location (loc);
3cf2715d 2252
ad7e39ca
AO
2253#ifdef FINAL_PRESCAN_INSN
2254 FINAL_PRESCAN_INSN (insn, ops, insn_noperands);
2255#endif
2256
3cf2715d 2257 /* Output the insn using them. */
36d7136e
RH
2258 if (string[0])
2259 {
3a694d86 2260 app_enable ();
5ffeb913 2261 if (expanded.file && expanded.line)
bff4b63d 2262 fprintf (asm_out_file, "%s %i \"%s\" 1\n",
5ffeb913 2263 ASM_COMMENT_START, expanded.line, expanded.file);
36d7136e 2264 output_asm_insn (string, ops);
03943c05 2265#if HAVE_AS_LINE_ZERO
5ffeb913 2266 if (expanded.file && expanded.line)
bff4b63d 2267 fprintf (asm_out_file, "%s 0 \"\" 2\n", ASM_COMMENT_START);
03943c05 2268#endif
36d7136e
RH
2269 }
2270
1afc5373
CF
2271 if (targetm.asm_out.final_postscan_insn)
2272 targetm.asm_out.final_postscan_insn (file, insn, ops,
2273 insn_noperands);
2274
3cf2715d
DE
2275 this_is_asm_operands = 0;
2276 break;
2277 }
2278
bad4f40b 2279 app_disable ();
3cf2715d
DE
2280
2281 if (GET_CODE (body) == SEQUENCE)
2282 {
2283 /* A delayed-branch sequence */
b3694847 2284 int i;
3cf2715d 2285
3cf2715d
DE
2286 final_sequence = body;
2287
d660cefe
RS
2288 /* Record the delay slots' frame information before the branch.
2289 This is needed for delayed calls: see execute_cfa_program(). */
2290#if defined (DWARF2_UNWIND_INFO)
2291 if (dwarf2out_do_frame ())
2292 for (i = 1; i < XVECLEN (body, 0); i++)
e0c0490b 2293 dwarf2out_frame_debug (XVECEXP (body, 0, i), false);
d660cefe
RS
2294#endif
2295
3cf2715d
DE
2296 /* The first insn in this SEQUENCE might be a JUMP_INSN that will
2297 force the restoration of a comparison that was previously
2298 thought unnecessary. If that happens, cancel this sequence
2299 and cause that insn to be restored. */
2300
c9d691e9 2301 next = final_scan_insn (XVECEXP (body, 0, 0), file, 0, 1, seen);
3cf2715d
DE
2302 if (next != XVECEXP (body, 0, 1))
2303 {
2304 final_sequence = 0;
2305 return next;
2306 }
2307
2308 for (i = 1; i < XVECLEN (body, 0); i++)
c7eee2df
RK
2309 {
2310 rtx insn = XVECEXP (body, 0, i);
2311 rtx next = NEXT_INSN (insn);
2312 /* We loop in case any instruction in a delay slot gets
2313 split. */
2314 do
c9d691e9 2315 insn = final_scan_insn (insn, file, 0, 1, seen);
c7eee2df
RK
2316 while (insn != next);
2317 }
3cf2715d
DE
2318#ifdef DBR_OUTPUT_SEQEND
2319 DBR_OUTPUT_SEQEND (file);
2320#endif
2321 final_sequence = 0;
2322
2323 /* If the insn requiring the delay slot was a CALL_INSN, the
2324 insns in the delay slot are actually executed before the
2325 called function. Hence we don't preserve any CC-setting
2326 actions in these insns and the CC must be marked as being
2327 clobbered by the function. */
4b4bf941 2328 if (CALL_P (XVECEXP (body, 0, 0)))
b729186a
JL
2329 {
2330 CC_STATUS_INIT;
2331 }
3cf2715d
DE
2332 break;
2333 }
2334
2335 /* We have a real machine instruction as rtl. */
2336
2337 body = PATTERN (insn);
2338
2339#ifdef HAVE_cc0
f5d927c0 2340 set = single_set (insn);
b88c92cc 2341
3cf2715d
DE
2342 /* Check for redundant test and compare instructions
2343 (when the condition codes are already set up as desired).
2344 This is done only when optimizing; if not optimizing,
2345 it should be possible for the user to alter a variable
2346 with the debugger in between statements
2347 and the next statement should reexamine the variable
2348 to compute the condition codes. */
2349
30f5e9f5 2350 if (optimize)
3cf2715d 2351 {
30f5e9f5
RK
2352 if (set
2353 && GET_CODE (SET_DEST (set)) == CC0
2354 && insn != last_ignored_compare)
3cf2715d 2355 {
f90b7a5a 2356 rtx src1, src2;
30f5e9f5 2357 if (GET_CODE (SET_SRC (set)) == SUBREG)
49d801d3 2358 SET_SRC (set) = alter_subreg (&SET_SRC (set));
f90b7a5a
PB
2359
2360 src1 = SET_SRC (set);
2361 src2 = NULL_RTX;
2362 if (GET_CODE (SET_SRC (set)) == COMPARE)
30f5e9f5
RK
2363 {
2364 if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
2365 XEXP (SET_SRC (set), 0)
49d801d3 2366 = alter_subreg (&XEXP (SET_SRC (set), 0));
30f5e9f5
RK
2367 if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG)
2368 XEXP (SET_SRC (set), 1)
49d801d3 2369 = alter_subreg (&XEXP (SET_SRC (set), 1));
f90b7a5a
PB
2370 if (XEXP (SET_SRC (set), 1)
2371 == CONST0_RTX (GET_MODE (XEXP (SET_SRC (set), 0))))
2372 src2 = XEXP (SET_SRC (set), 0);
30f5e9f5
RK
2373 }
2374 if ((cc_status.value1 != 0
f90b7a5a 2375 && rtx_equal_p (src1, cc_status.value1))
30f5e9f5 2376 || (cc_status.value2 != 0
f90b7a5a
PB
2377 && rtx_equal_p (src1, cc_status.value2))
2378 || (src2 != 0 && cc_status.value1 != 0
2379 && rtx_equal_p (src2, cc_status.value1))
2380 || (src2 != 0 && cc_status.value2 != 0
2381 && rtx_equal_p (src2, cc_status.value2)))
3cf2715d 2382 {
30f5e9f5 2383 /* Don't delete insn if it has an addressing side-effect. */
ff81832f 2384 if (! FIND_REG_INC_NOTE (insn, NULL_RTX)
30f5e9f5
RK
2385 /* or if anything in it is volatile. */
2386 && ! volatile_refs_p (PATTERN (insn)))
2387 {
2388 /* We don't really delete the insn; just ignore it. */
2389 last_ignored_compare = insn;
2390 break;
2391 }
3cf2715d
DE
2392 }
2393 }
2394 }
3cf2715d 2395
3cf2715d
DE
2396 /* If this is a conditional branch, maybe modify it
2397 if the cc's are in a nonstandard state
2398 so that it accomplishes the same thing that it would
2399 do straightforwardly if the cc's were set up normally. */
2400
2401 if (cc_status.flags != 0
4b4bf941 2402 && JUMP_P (insn)
3cf2715d
DE
2403 && GET_CODE (body) == SET
2404 && SET_DEST (body) == pc_rtx
2405 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
ec8e098d 2406 && COMPARISON_P (XEXP (SET_SRC (body), 0))
c9d691e9 2407 && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx)
3cf2715d
DE
2408 {
2409 /* This function may alter the contents of its argument
2410 and clear some of the cc_status.flags bits.
2411 It may also return 1 meaning condition now always true
2412 or -1 meaning condition now always false
2413 or 2 meaning condition nontrivial but altered. */
b3694847 2414 int result = alter_cond (XEXP (SET_SRC (body), 0));
3cf2715d
DE
2415 /* If condition now has fixed value, replace the IF_THEN_ELSE
2416 with its then-operand or its else-operand. */
2417 if (result == 1)
2418 SET_SRC (body) = XEXP (SET_SRC (body), 1);
2419 if (result == -1)
2420 SET_SRC (body) = XEXP (SET_SRC (body), 2);
2421
2422 /* The jump is now either unconditional or a no-op.
2423 If it has become a no-op, don't try to output it.
2424 (It would not be recognized.) */
2425 if (SET_SRC (body) == pc_rtx)
2426 {
ca6c03ca 2427 delete_insn (insn);
3cf2715d
DE
2428 break;
2429 }
2430 else if (GET_CODE (SET_SRC (body)) == RETURN)
2431 /* Replace (set (pc) (return)) with (return). */
2432 PATTERN (insn) = body = SET_SRC (body);
2433
2434 /* Rerecognize the instruction if it has changed. */
2435 if (result != 0)
2436 INSN_CODE (insn) = -1;
2437 }
2438
604e4ce3 2439 /* If this is a conditional trap, maybe modify it if the cc's
604e4ce3
KH
2440 are in a nonstandard state so that it accomplishes the same
2441 thing that it would do straightforwardly if the cc's were
2442 set up normally. */
2443 if (cc_status.flags != 0
2444 && NONJUMP_INSN_P (insn)
2445 && GET_CODE (body) == TRAP_IF
2446 && COMPARISON_P (TRAP_CONDITION (body))
2447 && XEXP (TRAP_CONDITION (body), 0) == cc0_rtx)
2448 {
2449 /* This function may alter the contents of its argument
2450 and clear some of the cc_status.flags bits.
2451 It may also return 1 meaning condition now always true
2452 or -1 meaning condition now always false
2453 or 2 meaning condition nontrivial but altered. */
2454 int result = alter_cond (TRAP_CONDITION (body));
2455
2456 /* If TRAP_CONDITION has become always false, delete the
2457 instruction. */
2458 if (result == -1)
2459 {
2460 delete_insn (insn);
2461 break;
2462 }
2463
2464 /* If TRAP_CONDITION has become always true, replace
2465 TRAP_CONDITION with const_true_rtx. */
2466 if (result == 1)
2467 TRAP_CONDITION (body) = const_true_rtx;
2468
2469 /* Rerecognize the instruction if it has changed. */
2470 if (result != 0)
2471 INSN_CODE (insn) = -1;
2472 }
2473
3cf2715d 2474 /* Make same adjustments to instructions that examine the
462da2af
SC
2475 condition codes without jumping and instructions that
2476 handle conditional moves (if this machine has either one). */
3cf2715d
DE
2477
2478 if (cc_status.flags != 0
b88c92cc 2479 && set != 0)
3cf2715d 2480 {
462da2af 2481 rtx cond_rtx, then_rtx, else_rtx;
f5d927c0 2482
4b4bf941 2483 if (!JUMP_P (insn)
b88c92cc 2484 && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE)
462da2af 2485 {
b88c92cc
RK
2486 cond_rtx = XEXP (SET_SRC (set), 0);
2487 then_rtx = XEXP (SET_SRC (set), 1);
2488 else_rtx = XEXP (SET_SRC (set), 2);
462da2af
SC
2489 }
2490 else
2491 {
b88c92cc 2492 cond_rtx = SET_SRC (set);
462da2af
SC
2493 then_rtx = const_true_rtx;
2494 else_rtx = const0_rtx;
2495 }
f5d927c0 2496
462da2af 2497 switch (GET_CODE (cond_rtx))
3cf2715d
DE
2498 {
2499 case GTU:
2500 case GT:
2501 case LTU:
2502 case LT:
2503 case GEU:
2504 case GE:
2505 case LEU:
2506 case LE:
2507 case EQ:
2508 case NE:
2509 {
b3694847 2510 int result;
462da2af 2511 if (XEXP (cond_rtx, 0) != cc0_rtx)
3cf2715d 2512 break;
462da2af 2513 result = alter_cond (cond_rtx);
3cf2715d 2514 if (result == 1)
b88c92cc 2515 validate_change (insn, &SET_SRC (set), then_rtx, 0);
3cf2715d 2516 else if (result == -1)
b88c92cc 2517 validate_change (insn, &SET_SRC (set), else_rtx, 0);
3cf2715d
DE
2518 else if (result == 2)
2519 INSN_CODE (insn) = -1;
b88c92cc 2520 if (SET_DEST (set) == SET_SRC (set))
ca6c03ca 2521 delete_insn (insn);
3cf2715d 2522 }
e9a25f70
JL
2523 break;
2524
2525 default:
2526 break;
3cf2715d
DE
2527 }
2528 }
462da2af 2529
3cf2715d
DE
2530#endif
2531
ede7cd44 2532#ifdef HAVE_peephole
3cf2715d
DE
2533 /* Do machine-specific peephole optimizations if desired. */
2534
2535 if (optimize && !flag_no_peephole && !nopeepholes)
2536 {
2537 rtx next = peephole (insn);
2538 /* When peepholing, if there were notes within the peephole,
2539 emit them before the peephole. */
2540 if (next != 0 && next != NEXT_INSN (insn))
2541 {
a2785739 2542 rtx note, prev = PREV_INSN (insn);
3cf2715d
DE
2543
2544 for (note = NEXT_INSN (insn); note != next;
2545 note = NEXT_INSN (note))
c9d691e9 2546 final_scan_insn (note, file, optimize, nopeepholes, seen);
a2785739
ILT
2547
2548 /* Put the notes in the proper position for a later
2549 rescan. For example, the SH target can do this
2550 when generating a far jump in a delayed branch
2551 sequence. */
2552 note = NEXT_INSN (insn);
2553 PREV_INSN (note) = prev;
2554 NEXT_INSN (prev) = note;
2555 NEXT_INSN (PREV_INSN (next)) = insn;
2556 PREV_INSN (insn) = PREV_INSN (next);
2557 NEXT_INSN (insn) = next;
2558 PREV_INSN (next) = insn;
3cf2715d
DE
2559 }
2560
2561 /* PEEPHOLE might have changed this. */
2562 body = PATTERN (insn);
2563 }
ede7cd44 2564#endif
3cf2715d
DE
2565
2566 /* Try to recognize the instruction.
2567 If successful, verify that the operands satisfy the
2568 constraints for the instruction. Crash if they don't,
2569 since `reload' should have changed them so that they do. */
2570
2571 insn_code_number = recog_memoized (insn);
0304f787 2572 cleanup_subreg_operands (insn);
3cf2715d 2573
dd3f0101
KH
2574 /* Dump the insn in the assembly for debugging. */
2575 if (flag_dump_rtl_in_asm)
2576 {
2577 print_rtx_head = ASM_COMMENT_START;
2578 print_rtl_single (asm_out_file, insn);
2579 print_rtx_head = "";
2580 }
b9f22704 2581
6c698a6d 2582 if (! constrain_operands_cached (1))
3cf2715d 2583 fatal_insn_not_found (insn);
3cf2715d
DE
2584
2585 /* Some target machines need to prescan each insn before
2586 it is output. */
2587
2588#ifdef FINAL_PRESCAN_INSN
1ccbefce 2589 FINAL_PRESCAN_INSN (insn, recog_data.operand, recog_data.n_operands);
3cf2715d
DE
2590#endif
2591
2929029c
WG
2592 if (targetm.have_conditional_execution ()
2593 && GET_CODE (PATTERN (insn)) == COND_EXEC)
afe48e06 2594 current_insn_predicate = COND_EXEC_TEST (PATTERN (insn));
afe48e06 2595
3cf2715d
DE
2596#ifdef HAVE_cc0
2597 cc_prev_status = cc_status;
2598
2599 /* Update `cc_status' for this instruction.
2600 The instruction's output routine may change it further.
2601 If the output routine for a jump insn needs to depend
2602 on the cc status, it should look at cc_prev_status. */
2603
2604 NOTICE_UPDATE_CC (body, insn);
2605#endif
2606
b1a9f6a0 2607 current_output_insn = debug_insn = insn;
3cf2715d 2608
f73ad30e 2609#if defined (DWARF2_UNWIND_INFO)
4b4bf941 2610 if (CALL_P (insn) && dwarf2out_do_frame ())
e0c0490b 2611 dwarf2out_frame_debug (insn, false);
b57d9225
JM
2612#endif
2613
4bbf910e 2614 /* Find the proper template for this insn. */
48c54229 2615 templ = get_insn_template (insn_code_number, insn);
3cf2715d 2616
4bbf910e
RH
2617 /* If the C code returns 0, it means that it is a jump insn
2618 which follows a deleted test insn, and that test insn
2619 needs to be reinserted. */
48c54229 2620 if (templ == 0)
3cf2715d 2621 {
efd0378b
HPN
2622 rtx prev;
2623
0bccc606 2624 gcc_assert (prev_nonnote_insn (insn) == last_ignored_compare);
efd0378b
HPN
2625
2626 /* We have already processed the notes between the setter and
2627 the user. Make sure we don't process them again, this is
2628 particularly important if one of the notes is a block
2629 scope note or an EH note. */
2630 for (prev = insn;
2631 prev != last_ignored_compare;
2632 prev = PREV_INSN (prev))
2633 {
4b4bf941 2634 if (NOTE_P (prev))
ca6c03ca 2635 delete_insn (prev); /* Use delete_note. */
efd0378b
HPN
2636 }
2637
2638 return prev;
3cf2715d
DE
2639 }
2640
2641 /* If the template is the string "#", it means that this insn must
2642 be split. */
48c54229 2643 if (templ[0] == '#' && templ[1] == '\0')
3cf2715d 2644 {
48c54229 2645 rtx new_rtx = try_split (body, insn, 0);
3cf2715d
DE
2646
2647 /* If we didn't split the insn, go away. */
48c54229 2648 if (new_rtx == insn && PATTERN (new_rtx) == body)
c725bd79 2649 fatal_insn ("could not split insn", insn);
f5d927c0 2650
3d14e82f
JW
2651#ifdef HAVE_ATTR_length
2652 /* This instruction should have been split in shorten_branches,
2653 to ensure that we would have valid length info for the
2654 splitees. */
0bccc606 2655 gcc_unreachable ();
3d14e82f
JW
2656#endif
2657
48c54229 2658 return new_rtx;
3cf2715d 2659 }
f5d927c0 2660
951120ea
PB
2661#ifdef TARGET_UNWIND_INFO
2662 /* ??? This will put the directives in the wrong place if
2663 get_insn_template outputs assembly directly. However calling it
2664 before get_insn_template breaks if the insns is split. */
2665 targetm.asm_out.unwind_emit (asm_out_file, insn);
ce152ef8 2666#endif
3cf2715d 2667
f410e1b3
RAE
2668 if (CALL_P (insn))
2669 {
2670 rtx x = call_from_call_insn (insn);
2671 x = XEXP (x, 0);
2672 if (x && MEM_P (x) && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2673 {
2674 tree t;
2675 x = XEXP (x, 0);
2676 t = SYMBOL_REF_DECL (x);
2677 if (t)
2678 assemble_external (t);
2679 }
2680 }
2681
951120ea 2682 /* Output assembler code from the template. */
48c54229 2683 output_asm_insn (templ, recog_data.operand);
3cf2715d 2684
77831620
CC
2685 /* Record point-of-call information for ICF debugging. */
2686 if (flag_enable_icf_debug && CALL_P (insn))
2687 {
2688 rtx x = call_from_call_insn (insn);
2689 x = XEXP (x, 0);
2690 if (x && MEM_P (x))
2691 {
2692 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2693 {
2694 tree t;
2695 x = XEXP (x, 0);
2696 t = SYMBOL_REF_DECL (x);
2697 if (t)
2698 (*debug_hooks->direct_call) (t);
2699 }
2700 else
2701 (*debug_hooks->virtual_call) (INSN_UID (insn));
2702 }
2703 }
2704
1afc5373
CF
2705 /* Some target machines need to postscan each insn after
2706 it is output. */
2707 if (targetm.asm_out.final_postscan_insn)
2708 targetm.asm_out.final_postscan_insn (file, insn, recog_data.operand,
2709 recog_data.n_operands);
2710
d660cefe
RS
2711 /* If necessary, report the effect that the instruction has on
2712 the unwind info. We've already done this for delay slots
2713 and call instructions. */
0021b564 2714#if defined (DWARF2_UNWIND_INFO)
e0c0490b 2715 if (final_sequence == 0
d660cefe
RS
2716#if !defined (HAVE_prologue)
2717 && !ACCUMULATE_OUTGOING_ARGS
2718#endif
fbfa55b0 2719 && dwarf2out_do_frame ())
e0c0490b 2720 dwarf2out_frame_debug (insn, true);
0021b564 2721#endif
469ac993 2722
b1a9f6a0 2723 current_output_insn = debug_insn = 0;
3cf2715d
DE
2724 }
2725 }
2726 return NEXT_INSN (insn);
2727}
2728\f
ed5ef2e4
CC
2729/* Return whether a source line note needs to be emitted before INSN.
2730 Sets IS_STMT to TRUE if the line should be marked as a possible
2731 breakpoint location. */
3cf2715d 2732
0435312e 2733static bool
ed5ef2e4 2734notice_source_line (rtx insn, bool *is_stmt)
3cf2715d 2735{
d752cfdb
JJ
2736 const char *filename;
2737 int linenum;
2738
2739 if (override_filename)
2740 {
2741 filename = override_filename;
2742 linenum = override_linenum;
2743 }
2744 else
2745 {
2746 filename = insn_file (insn);
2747 linenum = insn_line (insn);
2748 }
3cf2715d 2749
ed5ef2e4
CC
2750 if (filename == NULL)
2751 return false;
2752
2753 if (force_source_line
2754 || filename != last_filename
2755 || last_linenum != linenum)
0435312e 2756 {
b8176fe4 2757 force_source_line = false;
0435312e
JH
2758 last_filename = filename;
2759 last_linenum = linenum;
6c52e687 2760 last_discriminator = discriminator;
ed5ef2e4 2761 *is_stmt = true;
0435312e
JH
2762 high_block_linenum = MAX (last_linenum, high_block_linenum);
2763 high_function_linenum = MAX (last_linenum, high_function_linenum);
2764 return true;
2765 }
ed5ef2e4
CC
2766
2767 if (SUPPORTS_DISCRIMINATOR && last_discriminator != discriminator)
2768 {
2769 /* If the discriminator changed, but the line number did not,
2770 output the line table entry with is_stmt false so the
2771 debugger does not treat this as a breakpoint location. */
2772 last_discriminator = discriminator;
2773 *is_stmt = false;
2774 return true;
2775 }
2776
0435312e 2777 return false;
3cf2715d
DE
2778}
2779\f
0304f787
JL
2780/* For each operand in INSN, simplify (subreg (reg)) so that it refers
2781 directly to the desired hard register. */
f5d927c0 2782
0304f787 2783void
6cf9ac28 2784cleanup_subreg_operands (rtx insn)
0304f787 2785{
f62a15e3 2786 int i;
6fb5fa3c 2787 bool changed = false;
6c698a6d 2788 extract_insn_cached (insn);
1ccbefce 2789 for (i = 0; i < recog_data.n_operands; i++)
0304f787 2790 {
2067c116 2791 /* The following test cannot use recog_data.operand when testing
9f4524f2
RE
2792 for a SUBREG: the underlying object might have been changed
2793 already if we are inside a match_operator expression that
2794 matches the else clause. Instead we test the underlying
2795 expression directly. */
2796 if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
6fb5fa3c
DB
2797 {
2798 recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i]);
2799 changed = true;
2800 }
1ccbefce 2801 else if (GET_CODE (recog_data.operand[i]) == PLUS
04337620 2802 || GET_CODE (recog_data.operand[i]) == MULT
3c0cb5de 2803 || MEM_P (recog_data.operand[i]))
6fb5fa3c 2804 recog_data.operand[i] = walk_alter_subreg (recog_data.operand_loc[i], &changed);
0304f787
JL
2805 }
2806
1ccbefce 2807 for (i = 0; i < recog_data.n_dups; i++)
0304f787 2808 {
1ccbefce 2809 if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG)
6fb5fa3c
DB
2810 {
2811 *recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i]);
2812 changed = true;
2813 }
1ccbefce 2814 else if (GET_CODE (*recog_data.dup_loc[i]) == PLUS
04337620 2815 || GET_CODE (*recog_data.dup_loc[i]) == MULT
3c0cb5de 2816 || MEM_P (*recog_data.dup_loc[i]))
6fb5fa3c 2817 *recog_data.dup_loc[i] = walk_alter_subreg (recog_data.dup_loc[i], &changed);
0304f787 2818 }
6fb5fa3c
DB
2819 if (changed)
2820 df_insn_rescan (insn);
0304f787
JL
2821}
2822
3cf2715d
DE
2823/* If X is a SUBREG, replace it with a REG or a MEM,
2824 based on the thing it is a subreg of. */
2825
2826rtx
6cf9ac28 2827alter_subreg (rtx *xp)
3cf2715d 2828{
49d801d3 2829 rtx x = *xp;
b3694847 2830 rtx y = SUBREG_REG (x);
f5963e61 2831
49d801d3
JH
2832 /* simplify_subreg does not remove subreg from volatile references.
2833 We are required to. */
3c0cb5de 2834 if (MEM_P (y))
fd326ba8
UW
2835 {
2836 int offset = SUBREG_BYTE (x);
2837
2838 /* For paradoxical subregs on big-endian machines, SUBREG_BYTE
2839 contains 0 instead of the proper offset. See simplify_subreg. */
2840 if (offset == 0
2841 && GET_MODE_SIZE (GET_MODE (y)) < GET_MODE_SIZE (GET_MODE (x)))
2842 {
2843 int difference = GET_MODE_SIZE (GET_MODE (y))
2844 - GET_MODE_SIZE (GET_MODE (x));
2845 if (WORDS_BIG_ENDIAN)
2846 offset += (difference / UNITS_PER_WORD) * UNITS_PER_WORD;
2847 if (BYTES_BIG_ENDIAN)
2848 offset += difference % UNITS_PER_WORD;
2849 }
2850
2851 *xp = adjust_address (y, GET_MODE (x), offset);
2852 }
49d801d3 2853 else
fea54805 2854 {
48c54229 2855 rtx new_rtx = simplify_subreg (GET_MODE (x), y, GET_MODE (y),
fea54805
RK
2856 SUBREG_BYTE (x));
2857
48c54229
KG
2858 if (new_rtx != 0)
2859 *xp = new_rtx;
bbe37912 2860 else if (REG_P (y))
fea54805 2861 {
0bccc606 2862 /* Simplify_subreg can't handle some REG cases, but we have to. */
38ae7651
RS
2863 unsigned int regno;
2864 HOST_WIDE_INT offset;
2865
2866 regno = subreg_regno (x);
2867 if (subreg_lowpart_p (x))
2868 offset = byte_lowpart_offset (GET_MODE (x), GET_MODE (y));
2869 else
2870 offset = SUBREG_BYTE (x);
2871 *xp = gen_rtx_REG_offset (y, GET_MODE (x), regno, offset);
fea54805 2872 }
fea54805
RK
2873 }
2874
49d801d3 2875 return *xp;
3cf2715d
DE
2876}
2877
2878/* Do alter_subreg on all the SUBREGs contained in X. */
2879
2880static rtx
6fb5fa3c 2881walk_alter_subreg (rtx *xp, bool *changed)
3cf2715d 2882{
49d801d3 2883 rtx x = *xp;
3cf2715d
DE
2884 switch (GET_CODE (x))
2885 {
2886 case PLUS:
2887 case MULT:
beed8fc0 2888 case AND:
6fb5fa3c
DB
2889 XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0), changed);
2890 XEXP (x, 1) = walk_alter_subreg (&XEXP (x, 1), changed);
3cf2715d
DE
2891 break;
2892
2893 case MEM:
beed8fc0 2894 case ZERO_EXTEND:
6fb5fa3c 2895 XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0), changed);
3cf2715d
DE
2896 break;
2897
2898 case SUBREG:
6fb5fa3c 2899 *changed = true;
49d801d3 2900 return alter_subreg (xp);
f5d927c0 2901
e9a25f70
JL
2902 default:
2903 break;
3cf2715d
DE
2904 }
2905
5bc72aeb 2906 return *xp;
3cf2715d
DE
2907}
2908\f
2909#ifdef HAVE_cc0
2910
2911/* Given BODY, the body of a jump instruction, alter the jump condition
2912 as required by the bits that are set in cc_status.flags.
2913 Not all of the bits there can be handled at this level in all cases.
2914
2915 The value is normally 0.
2916 1 means that the condition has become always true.
2917 -1 means that the condition has become always false.
2918 2 means that COND has been altered. */
2919
2920static int
6cf9ac28 2921alter_cond (rtx cond)
3cf2715d
DE
2922{
2923 int value = 0;
2924
2925 if (cc_status.flags & CC_REVERSED)
2926 {
2927 value = 2;
2928 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
2929 }
2930
2931 if (cc_status.flags & CC_INVERTED)
2932 {
2933 value = 2;
2934 PUT_CODE (cond, reverse_condition (GET_CODE (cond)));
2935 }
2936
2937 if (cc_status.flags & CC_NOT_POSITIVE)
2938 switch (GET_CODE (cond))
2939 {
2940 case LE:
2941 case LEU:
2942 case GEU:
2943 /* Jump becomes unconditional. */
2944 return 1;
2945
2946 case GT:
2947 case GTU:
2948 case LTU:
2949 /* Jump becomes no-op. */
2950 return -1;
2951
2952 case GE:
2953 PUT_CODE (cond, EQ);
2954 value = 2;
2955 break;
2956
2957 case LT:
2958 PUT_CODE (cond, NE);
2959 value = 2;
2960 break;
f5d927c0 2961
e9a25f70
JL
2962 default:
2963 break;
3cf2715d
DE
2964 }
2965
2966 if (cc_status.flags & CC_NOT_NEGATIVE)
2967 switch (GET_CODE (cond))
2968 {
2969 case GE:
2970 case GEU:
2971 /* Jump becomes unconditional. */
2972 return 1;
2973
2974 case LT:
2975 case LTU:
2976 /* Jump becomes no-op. */
2977 return -1;
2978
2979 case LE:
2980 case LEU:
2981 PUT_CODE (cond, EQ);
2982 value = 2;
2983 break;
2984
2985 case GT:
2986 case GTU:
2987 PUT_CODE (cond, NE);
2988 value = 2;
2989 break;
f5d927c0 2990
e9a25f70
JL
2991 default:
2992 break;
3cf2715d
DE
2993 }
2994
2995 if (cc_status.flags & CC_NO_OVERFLOW)
2996 switch (GET_CODE (cond))
2997 {
2998 case GEU:
2999 /* Jump becomes unconditional. */
3000 return 1;
3001
3002 case LEU:
3003 PUT_CODE (cond, EQ);
3004 value = 2;
3005 break;
3006
3007 case GTU:
3008 PUT_CODE (cond, NE);
3009 value = 2;
3010 break;
3011
3012 case LTU:
3013 /* Jump becomes no-op. */
3014 return -1;
f5d927c0 3015
e9a25f70
JL
3016 default:
3017 break;
3cf2715d
DE
3018 }
3019
3020 if (cc_status.flags & (CC_Z_IN_NOT_N | CC_Z_IN_N))
3021 switch (GET_CODE (cond))
3022 {
e9a25f70 3023 default:
0bccc606 3024 gcc_unreachable ();
3cf2715d
DE
3025
3026 case NE:
3027 PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? GE : LT);
3028 value = 2;
3029 break;
3030
3031 case EQ:
3032 PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? LT : GE);
3033 value = 2;
3034 break;
3035 }
3036
3037 if (cc_status.flags & CC_NOT_SIGNED)
3038 /* The flags are valid if signed condition operators are converted
3039 to unsigned. */
3040 switch (GET_CODE (cond))
3041 {
3042 case LE:
3043 PUT_CODE (cond, LEU);
3044 value = 2;
3045 break;
3046
3047 case LT:
3048 PUT_CODE (cond, LTU);
3049 value = 2;
3050 break;
3051
3052 case GT:
3053 PUT_CODE (cond, GTU);
3054 value = 2;
3055 break;
3056
3057 case GE:
3058 PUT_CODE (cond, GEU);
3059 value = 2;
3060 break;
e9a25f70
JL
3061
3062 default:
3063 break;
3cf2715d
DE
3064 }
3065
3066 return value;
3067}
3068#endif
3069\f
3070/* Report inconsistency between the assembler template and the operands.
3071 In an `asm', it's the user's fault; otherwise, the compiler's fault. */
3072
3073void
4b794eaf 3074output_operand_lossage (const char *cmsgid, ...)
3cf2715d 3075{
a52453cc
PT
3076 char *fmt_string;
3077 char *new_message;
fd478a0a 3078 const char *pfx_str;
e34d07f2 3079 va_list ap;
6cf9ac28 3080
4b794eaf 3081 va_start (ap, cmsgid);
a52453cc 3082
9e637a26 3083 pfx_str = this_is_asm_operands ? _("invalid 'asm': ") : "output_operand: ";
4b794eaf 3084 asprintf (&fmt_string, "%s%s", pfx_str, _(cmsgid));
a52453cc 3085 vasprintf (&new_message, fmt_string, ap);
dd3f0101 3086
3cf2715d 3087 if (this_is_asm_operands)
a52453cc 3088 error_for_asm (this_is_asm_operands, "%s", new_message);
3cf2715d 3089 else
a52453cc
PT
3090 internal_error ("%s", new_message);
3091
3092 free (fmt_string);
3093 free (new_message);
e34d07f2 3094 va_end (ap);
3cf2715d
DE
3095}
3096\f
3097/* Output of assembler code from a template, and its subroutines. */
3098
0d4903b8
RK
3099/* Annotate the assembly with a comment describing the pattern and
3100 alternative used. */
3101
3102static void
6cf9ac28 3103output_asm_name (void)
0d4903b8
RK
3104{
3105 if (debug_insn)
3106 {
3107 int num = INSN_CODE (debug_insn);
3108 fprintf (asm_out_file, "\t%s %d\t%s",
3109 ASM_COMMENT_START, INSN_UID (debug_insn),
3110 insn_data[num].name);
3111 if (insn_data[num].n_alternatives > 1)
3112 fprintf (asm_out_file, "/%d", which_alternative + 1);
3113#ifdef HAVE_ATTR_length
3114 fprintf (asm_out_file, "\t[length = %d]",
3115 get_attr_length (debug_insn));
3116#endif
3117 /* Clear this so only the first assembler insn
3118 of any rtl insn will get the special comment for -dp. */
3119 debug_insn = 0;
3120 }
3121}
3122
998d7deb
RH
3123/* If OP is a REG or MEM and we can find a MEM_EXPR corresponding to it
3124 or its address, return that expr . Set *PADDRESSP to 1 if the expr
c5adc06a
RK
3125 corresponds to the address of the object and 0 if to the object. */
3126
3127static tree
6cf9ac28 3128get_mem_expr_from_op (rtx op, int *paddressp)
c5adc06a 3129{
998d7deb 3130 tree expr;
c5adc06a
RK
3131 int inner_addressp;
3132
3133 *paddressp = 0;
3134
f8cfc6aa 3135 if (REG_P (op))
a560d4d4 3136 return REG_EXPR (op);
3c0cb5de 3137 else if (!MEM_P (op))
c5adc06a
RK
3138 return 0;
3139
998d7deb
RH
3140 if (MEM_EXPR (op) != 0)
3141 return MEM_EXPR (op);
c5adc06a
RK
3142
3143 /* Otherwise we have an address, so indicate it and look at the address. */
3144 *paddressp = 1;
3145 op = XEXP (op, 0);
3146
3147 /* First check if we have a decl for the address, then look at the right side
3148 if it is a PLUS. Otherwise, strip off arithmetic and keep looking.
3149 But don't allow the address to itself be indirect. */
998d7deb
RH
3150 if ((expr = get_mem_expr_from_op (op, &inner_addressp)) && ! inner_addressp)
3151 return expr;
c5adc06a 3152 else if (GET_CODE (op) == PLUS
998d7deb
RH
3153 && (expr = get_mem_expr_from_op (XEXP (op, 1), &inner_addressp)))
3154 return expr;
c5adc06a 3155
481683e1 3156 while (UNARY_P (op)
ec8e098d 3157 || GET_RTX_CLASS (GET_CODE (op)) == RTX_BIN_ARITH)
c5adc06a
RK
3158 op = XEXP (op, 0);
3159
998d7deb
RH
3160 expr = get_mem_expr_from_op (op, &inner_addressp);
3161 return inner_addressp ? 0 : expr;
c5adc06a 3162}
ff81832f 3163
4f9b4029
RK
3164/* Output operand names for assembler instructions. OPERANDS is the
3165 operand vector, OPORDER is the order to write the operands, and NOPS
3166 is the number of operands to write. */
3167
3168static void
6cf9ac28 3169output_asm_operand_names (rtx *operands, int *oporder, int nops)
4f9b4029
RK
3170{
3171 int wrote = 0;
3172 int i;
3173
3174 for (i = 0; i < nops; i++)
3175 {
3176 int addressp;
a560d4d4
JH
3177 rtx op = operands[oporder[i]];
3178 tree expr = get_mem_expr_from_op (op, &addressp);
4f9b4029 3179
a560d4d4
JH
3180 fprintf (asm_out_file, "%c%s",
3181 wrote ? ',' : '\t', wrote ? "" : ASM_COMMENT_START);
3182 wrote = 1;
998d7deb 3183 if (expr)
4f9b4029 3184 {
a560d4d4 3185 fprintf (asm_out_file, "%s",
998d7deb
RH
3186 addressp ? "*" : "");
3187 print_mem_expr (asm_out_file, expr);
4f9b4029
RK
3188 wrote = 1;
3189 }
a560d4d4
JH
3190 else if (REG_P (op) && ORIGINAL_REGNO (op)
3191 && ORIGINAL_REGNO (op) != REGNO (op))
3192 fprintf (asm_out_file, " tmp%i", ORIGINAL_REGNO (op));
4f9b4029
RK
3193 }
3194}
3195
3cf2715d
DE
3196/* Output text from TEMPLATE to the assembler output file,
3197 obeying %-directions to substitute operands taken from
3198 the vector OPERANDS.
3199
3200 %N (for N a digit) means print operand N in usual manner.
3201 %lN means require operand N to be a CODE_LABEL or LABEL_REF
3202 and print the label name with no punctuation.
3203 %cN means require operand N to be a constant
3204 and print the constant expression with no punctuation.
3205 %aN means expect operand N to be a memory address
3206 (not a memory reference!) and print a reference
3207 to that address.
3208 %nN means expect operand N to be a constant
3209 and print a constant expression for minus the value
3210 of the operand, with no other punctuation. */
3211
3212void
48c54229 3213output_asm_insn (const char *templ, rtx *operands)
3cf2715d 3214{
b3694847
SS
3215 const char *p;
3216 int c;
8554d9a4
JJ
3217#ifdef ASSEMBLER_DIALECT
3218 int dialect = 0;
3219#endif
0d4903b8 3220 int oporder[MAX_RECOG_OPERANDS];
4f9b4029 3221 char opoutput[MAX_RECOG_OPERANDS];
0d4903b8 3222 int ops = 0;
3cf2715d
DE
3223
3224 /* An insn may return a null string template
3225 in a case where no assembler code is needed. */
48c54229 3226 if (*templ == 0)
3cf2715d
DE
3227 return;
3228
4f9b4029 3229 memset (opoutput, 0, sizeof opoutput);
48c54229 3230 p = templ;
3cf2715d
DE
3231 putc ('\t', asm_out_file);
3232
3233#ifdef ASM_OUTPUT_OPCODE
3234 ASM_OUTPUT_OPCODE (asm_out_file, p);
3235#endif
3236
b729186a 3237 while ((c = *p++))
3cf2715d
DE
3238 switch (c)
3239 {
3cf2715d 3240 case '\n':
4f9b4029
RK
3241 if (flag_verbose_asm)
3242 output_asm_operand_names (operands, oporder, ops);
0d4903b8
RK
3243 if (flag_print_asm_name)
3244 output_asm_name ();
3245
4f9b4029
RK
3246 ops = 0;
3247 memset (opoutput, 0, sizeof opoutput);
3248
3cf2715d 3249 putc (c, asm_out_file);
cb649530 3250#ifdef ASM_OUTPUT_OPCODE
3cf2715d
DE
3251 while ((c = *p) == '\t')
3252 {
3253 putc (c, asm_out_file);
3254 p++;
3255 }
3256 ASM_OUTPUT_OPCODE (asm_out_file, p);
3cf2715d 3257#endif
cb649530 3258 break;
3cf2715d
DE
3259
3260#ifdef ASSEMBLER_DIALECT
3261 case '{':
b729186a 3262 {
b3694847 3263 int i;
f5d927c0 3264
8554d9a4
JJ
3265 if (dialect)
3266 output_operand_lossage ("nested assembly dialect alternatives");
3267 else
3268 dialect = 1;
3269
b729186a
JL
3270 /* If we want the first dialect, do nothing. Otherwise, skip
3271 DIALECT_NUMBER of strings ending with '|'. */
3272 for (i = 0; i < dialect_number; i++)
3273 {
463a8384 3274 while (*p && *p != '}' && *p++ != '|')
b729186a 3275 ;
463a8384
BS
3276 if (*p == '}')
3277 break;
b729186a
JL
3278 if (*p == '|')
3279 p++;
3280 }
8554d9a4
JJ
3281
3282 if (*p == '\0')
3283 output_operand_lossage ("unterminated assembly dialect alternative");
b729186a 3284 }
3cf2715d
DE
3285 break;
3286
3287 case '|':
8554d9a4
JJ
3288 if (dialect)
3289 {
3290 /* Skip to close brace. */
3291 do
3292 {
3293 if (*p == '\0')
3294 {
3295 output_operand_lossage ("unterminated assembly dialect alternative");
3296 break;
3297 }
ff81832f 3298 }
8554d9a4
JJ
3299 while (*p++ != '}');
3300 dialect = 0;
3301 }
3302 else
3303 putc (c, asm_out_file);
3cf2715d
DE
3304 break;
3305
3306 case '}':
8554d9a4
JJ
3307 if (! dialect)
3308 putc (c, asm_out_file);
3309 dialect = 0;
3cf2715d
DE
3310 break;
3311#endif
3312
3313 case '%':
3314 /* %% outputs a single %. */
3315 if (*p == '%')
3316 {
3317 p++;
3318 putc (c, asm_out_file);
3319 }
3320 /* %= outputs a number which is unique to each insn in the entire
3321 compilation. This is useful for making local labels that are
3322 referred to more than once in a given insn. */
3323 else if (*p == '=')
3324 {
3325 p++;
3326 fprintf (asm_out_file, "%d", insn_counter);
3327 }
3328 /* % followed by a letter and some digits
3329 outputs an operand in a special way depending on the letter.
3330 Letters `acln' are implemented directly.
3331 Other letters are passed to `output_operand' so that
3332 the PRINT_OPERAND macro can define them. */
0df6c2c7 3333 else if (ISALPHA (*p))
3cf2715d
DE
3334 {
3335 int letter = *p++;
c383c15f
GK
3336 unsigned long opnum;
3337 char *endptr;
b0efb46b 3338
c383c15f
GK
3339 opnum = strtoul (p, &endptr, 10);
3340
3341 if (endptr == p)
3342 output_operand_lossage ("operand number missing "
3343 "after %%-letter");
3344 else if (this_is_asm_operands && opnum >= insn_noperands)
3cf2715d
DE
3345 output_operand_lossage ("operand number out of range");
3346 else if (letter == 'l')
c383c15f 3347 output_asm_label (operands[opnum]);
3cf2715d 3348 else if (letter == 'a')
c383c15f 3349 output_address (operands[opnum]);
3cf2715d
DE
3350 else if (letter == 'c')
3351 {
c383c15f
GK
3352 if (CONSTANT_ADDRESS_P (operands[opnum]))
3353 output_addr_const (asm_out_file, operands[opnum]);
3cf2715d 3354 else
c383c15f 3355 output_operand (operands[opnum], 'c');
3cf2715d
DE
3356 }
3357 else if (letter == 'n')
3358 {
481683e1 3359 if (CONST_INT_P (operands[opnum]))
21e3a81b 3360 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC,
c383c15f 3361 - INTVAL (operands[opnum]));
3cf2715d
DE
3362 else
3363 {
3364 putc ('-', asm_out_file);
c383c15f 3365 output_addr_const (asm_out_file, operands[opnum]);
3cf2715d
DE
3366 }
3367 }
3368 else
c383c15f 3369 output_operand (operands[opnum], letter);
f5d927c0 3370
c383c15f 3371 if (!opoutput[opnum])
dc9d0b14 3372 oporder[ops++] = opnum;
c383c15f 3373 opoutput[opnum] = 1;
0d4903b8 3374
c383c15f
GK
3375 p = endptr;
3376 c = *p;
3cf2715d
DE
3377 }
3378 /* % followed by a digit outputs an operand the default way. */
0df6c2c7 3379 else if (ISDIGIT (*p))
3cf2715d 3380 {
c383c15f
GK
3381 unsigned long opnum;
3382 char *endptr;
b0efb46b 3383
c383c15f
GK
3384 opnum = strtoul (p, &endptr, 10);
3385 if (this_is_asm_operands && opnum >= insn_noperands)
3cf2715d
DE
3386 output_operand_lossage ("operand number out of range");
3387 else
c383c15f 3388 output_operand (operands[opnum], 0);
0d4903b8 3389
c383c15f 3390 if (!opoutput[opnum])
dc9d0b14 3391 oporder[ops++] = opnum;
c383c15f 3392 opoutput[opnum] = 1;
4f9b4029 3393
c383c15f
GK
3394 p = endptr;
3395 c = *p;
3cf2715d
DE
3396 }
3397 /* % followed by punctuation: output something for that
3398 punctuation character alone, with no operand.
3399 The PRINT_OPERAND macro decides what is actually done. */
3400#ifdef PRINT_OPERAND_PUNCT_VALID_P
f5d927c0 3401 else if (PRINT_OPERAND_PUNCT_VALID_P ((unsigned char) *p))
3cf2715d
DE
3402 output_operand (NULL_RTX, *p++);
3403#endif
3404 else
3405 output_operand_lossage ("invalid %%-code");
3406 break;
3407
3408 default:
3409 putc (c, asm_out_file);
3410 }
3411
0d4903b8
RK
3412 /* Write out the variable names for operands, if we know them. */
3413 if (flag_verbose_asm)
4f9b4029 3414 output_asm_operand_names (operands, oporder, ops);
0d4903b8
RK
3415 if (flag_print_asm_name)
3416 output_asm_name ();
3cf2715d
DE
3417
3418 putc ('\n', asm_out_file);
3419}
3420\f
3421/* Output a LABEL_REF, or a bare CODE_LABEL, as an assembler symbol. */
3422
3423void
6cf9ac28 3424output_asm_label (rtx x)
3cf2715d
DE
3425{
3426 char buf[256];
3427
3428 if (GET_CODE (x) == LABEL_REF)
be1bb652 3429 x = XEXP (x, 0);
4b4bf941
JQ
3430 if (LABEL_P (x)
3431 || (NOTE_P (x)
a38e7aa5 3432 && NOTE_KIND (x) == NOTE_INSN_DELETED_LABEL))
3cf2715d
DE
3433 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
3434 else
9e637a26 3435 output_operand_lossage ("'%%l' operand isn't a label");
3cf2715d
DE
3436
3437 assemble_name (asm_out_file, buf);
3438}
3439
a7fe25b8
JJ
3440/* Helper rtx-iteration-function for mark_symbol_refs_as_used and
3441 output_operand. Marks SYMBOL_REFs as referenced through use of
3442 assemble_external. */
c70d0414
HPN
3443
3444static int
3445mark_symbol_ref_as_used (rtx *xp, void *dummy ATTRIBUTE_UNUSED)
3446{
3447 rtx x = *xp;
3448
3449 /* If we have a used symbol, we may have to emit assembly
3450 annotations corresponding to whether the symbol is external, weak
3451 or has non-default visibility. */
3452 if (GET_CODE (x) == SYMBOL_REF)
3453 {
3454 tree t;
3455
3456 t = SYMBOL_REF_DECL (x);
3457 if (t)
3458 assemble_external (t);
3459
3460 return -1;
3461 }
3462
3463 return 0;
3464}
3465
a7fe25b8
JJ
3466/* Marks SYMBOL_REFs in x as referenced through use of assemble_external. */
3467
3468void
3469mark_symbol_refs_as_used (rtx x)
3470{
3471 for_each_rtx (&x, mark_symbol_ref_as_used, NULL);
3472}
3473
3cf2715d
DE
3474/* Print operand X using machine-dependent assembler syntax.
3475 The macro PRINT_OPERAND is defined just to control this function.
3476 CODE is a non-digit that preceded the operand-number in the % spec,
3477 such as 'z' if the spec was `%z3'. CODE is 0 if there was no char
3478 between the % and the digits.
3479 When CODE is a non-letter, X is 0.
3480
3481 The meanings of the letters are machine-dependent and controlled
3482 by PRINT_OPERAND. */
3483
3484static void
6cf9ac28 3485output_operand (rtx x, int code ATTRIBUTE_UNUSED)
3cf2715d
DE
3486{
3487 if (x && GET_CODE (x) == SUBREG)
49d801d3 3488 x = alter_subreg (&x);
3cf2715d 3489
04c7ae48 3490 /* X must not be a pseudo reg. */
0bccc606 3491 gcc_assert (!x || !REG_P (x) || REGNO (x) < FIRST_PSEUDO_REGISTER);
3cf2715d
DE
3492
3493 PRINT_OPERAND (asm_out_file, x, code);
c70d0414
HPN
3494
3495 if (x == NULL_RTX)
3496 return;
3497
3498 for_each_rtx (&x, mark_symbol_ref_as_used, NULL);
3cf2715d
DE
3499}
3500
3501/* Print a memory reference operand for address X
3502 using machine-dependent assembler syntax.
3503 The macro PRINT_OPERAND_ADDRESS exists just to control this function. */
3504
3505void
6cf9ac28 3506output_address (rtx x)
3cf2715d 3507{
6fb5fa3c
DB
3508 bool changed = false;
3509 walk_alter_subreg (&x, &changed);
3cf2715d
DE
3510 PRINT_OPERAND_ADDRESS (asm_out_file, x);
3511}
3512\f
3513/* Print an integer constant expression in assembler syntax.
3514 Addition and subtraction are the only arithmetic
3515 that may appear in these expressions. */
3516
3517void
6cf9ac28 3518output_addr_const (FILE *file, rtx x)
3cf2715d
DE
3519{
3520 char buf[256];
3521
3522 restart:
3523 switch (GET_CODE (x))
3524 {
3525 case PC:
eac50d7a 3526 putc ('.', file);
3cf2715d
DE
3527 break;
3528
3529 case SYMBOL_REF:
21dad7e6 3530 if (SYMBOL_REF_DECL (x))
152464d2 3531 assemble_external (SYMBOL_REF_DECL (x));
99c8c61c
AO
3532#ifdef ASM_OUTPUT_SYMBOL_REF
3533 ASM_OUTPUT_SYMBOL_REF (file, x);
3534#else
3cf2715d 3535 assemble_name (file, XSTR (x, 0));
99c8c61c 3536#endif
3cf2715d
DE
3537 break;
3538
3539 case LABEL_REF:
422be3c3
AO
3540 x = XEXP (x, 0);
3541 /* Fall through. */
3cf2715d
DE
3542 case CODE_LABEL:
3543 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2f0b7af6
GK
3544#ifdef ASM_OUTPUT_LABEL_REF
3545 ASM_OUTPUT_LABEL_REF (file, buf);
3546#else
3cf2715d 3547 assemble_name (file, buf);
2f0b7af6 3548#endif
3cf2715d
DE
3549 break;
3550
3551 case CONST_INT:
21e3a81b 3552 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
3cf2715d
DE
3553 break;
3554
3555 case CONST:
3556 /* This used to output parentheses around the expression,
3557 but that does not work on the 386 (either ATT or BSD assembler). */
3558 output_addr_const (file, XEXP (x, 0));
3559 break;
3560
3561 case CONST_DOUBLE:
3562 if (GET_MODE (x) == VOIDmode)
3563 {
3564 /* We can use %d if the number is one word and positive. */
3565 if (CONST_DOUBLE_HIGH (x))
21e3a81b 3566 fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX,
3d57d7ce
DK
3567 (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (x),
3568 (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x));
f5d927c0 3569 else if (CONST_DOUBLE_LOW (x) < 0)
3d57d7ce
DK
3570 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
3571 (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x));
3cf2715d 3572 else
21e3a81b 3573 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
3cf2715d
DE
3574 }
3575 else
3576 /* We can't handle floating point constants;
3577 PRINT_OPERAND must handle them. */
3578 output_operand_lossage ("floating constant misused");
3579 break;
3580
14c931f1 3581 case CONST_FIXED:
3d57d7ce
DK
3582 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
3583 (unsigned HOST_WIDE_INT) CONST_FIXED_VALUE_LOW (x));
14c931f1
CF
3584 break;
3585
3cf2715d
DE
3586 case PLUS:
3587 /* Some assemblers need integer constants to appear last (eg masm). */
481683e1 3588 if (CONST_INT_P (XEXP (x, 0)))
3cf2715d
DE
3589 {
3590 output_addr_const (file, XEXP (x, 1));
3591 if (INTVAL (XEXP (x, 0)) >= 0)
3592 fprintf (file, "+");
3593 output_addr_const (file, XEXP (x, 0));
3594 }
3595 else
3596 {
3597 output_addr_const (file, XEXP (x, 0));
481683e1 3598 if (!CONST_INT_P (XEXP (x, 1))
08106825 3599 || INTVAL (XEXP (x, 1)) >= 0)
3cf2715d
DE
3600 fprintf (file, "+");
3601 output_addr_const (file, XEXP (x, 1));
3602 }
3603 break;
3604
3605 case MINUS:
3606 /* Avoid outputting things like x-x or x+5-x,
3607 since some assemblers can't handle that. */
3608 x = simplify_subtraction (x);
3609 if (GET_CODE (x) != MINUS)
3610 goto restart;
3611
3612 output_addr_const (file, XEXP (x, 0));
3613 fprintf (file, "-");
481683e1 3614 if ((CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0)
301d03af
RS
3615 || GET_CODE (XEXP (x, 1)) == PC
3616 || GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
3617 output_addr_const (file, XEXP (x, 1));
3618 else
3cf2715d 3619 {
17b53c33 3620 fputs (targetm.asm_out.open_paren, file);
3cf2715d 3621 output_addr_const (file, XEXP (x, 1));
17b53c33 3622 fputs (targetm.asm_out.close_paren, file);
3cf2715d 3623 }
3cf2715d
DE
3624 break;
3625
3626 case ZERO_EXTEND:
3627 case SIGN_EXTEND:
fdf473ae 3628 case SUBREG:
c01e4479 3629 case TRUNCATE:
3cf2715d
DE
3630 output_addr_const (file, XEXP (x, 0));
3631 break;
3632
3633 default:
422be3c3
AO
3634#ifdef OUTPUT_ADDR_CONST_EXTRA
3635 OUTPUT_ADDR_CONST_EXTRA (file, x, fail);
3636 break;
3637
3638 fail:
3639#endif
3cf2715d
DE
3640 output_operand_lossage ("invalid expression as operand");
3641 }
3642}
3643\f
3644/* A poor man's fprintf, with the added features of %I, %R, %L, and %U.
3645 %R prints the value of REGISTER_PREFIX.
3646 %L prints the value of LOCAL_LABEL_PREFIX.
3647 %U prints the value of USER_LABEL_PREFIX.
3648 %I prints the value of IMMEDIATE_PREFIX.
3649 %O runs ASM_OUTPUT_OPCODE to transform what follows in the string.
b1721339 3650 Also supported are %d, %i, %u, %x, %X, %o, %c, %s and %%.
3cf2715d
DE
3651
3652 We handle alternate assembler dialects here, just like output_asm_insn. */
3653
3654void
e34d07f2 3655asm_fprintf (FILE *file, const char *p, ...)
3cf2715d 3656{
3cf2715d
DE
3657 char buf[10];
3658 char *q, c;
e34d07f2 3659 va_list argptr;
6cf9ac28 3660
e34d07f2 3661 va_start (argptr, p);
3cf2715d
DE
3662
3663 buf[0] = '%';
3664
b729186a 3665 while ((c = *p++))
3cf2715d
DE
3666 switch (c)
3667 {
3668#ifdef ASSEMBLER_DIALECT
3669 case '{':
b729186a
JL
3670 {
3671 int i;
3cf2715d 3672
b729186a
JL
3673 /* If we want the first dialect, do nothing. Otherwise, skip
3674 DIALECT_NUMBER of strings ending with '|'. */
3675 for (i = 0; i < dialect_number; i++)
3676 {
3677 while (*p && *p++ != '|')
3678 ;
3679
3680 if (*p == '|')
3681 p++;
f5d927c0 3682 }
b729186a 3683 }
3cf2715d
DE
3684 break;
3685
3686 case '|':
3687 /* Skip to close brace. */
3688 while (*p && *p++ != '}')
3689 ;
3690 break;
3691
3692 case '}':
3693 break;
3694#endif
3695
3696 case '%':
3697 c = *p++;
3698 q = &buf[1];
b1721339
KG
3699 while (strchr ("-+ #0", c))
3700 {
3701 *q++ = c;
3702 c = *p++;
3703 }
0df6c2c7 3704 while (ISDIGIT (c) || c == '.')
3cf2715d
DE
3705 {
3706 *q++ = c;
3707 c = *p++;
3708 }
3709 switch (c)
3710 {
3711 case '%':
b1721339 3712 putc ('%', file);
3cf2715d
DE
3713 break;
3714
3715 case 'd': case 'i': case 'u':
b1721339
KG
3716 case 'x': case 'X': case 'o':
3717 case 'c':
3cf2715d
DE
3718 *q++ = c;
3719 *q = 0;
3720 fprintf (file, buf, va_arg (argptr, int));
3721 break;
3722
3723 case 'w':
b1721339
KG
3724 /* This is a prefix to the 'd', 'i', 'u', 'x', 'X', and
3725 'o' cases, but we do not check for those cases. It
3726 means that the value is a HOST_WIDE_INT, which may be
3727 either `long' or `long long'. */
85f015e1
KG
3728 memcpy (q, HOST_WIDE_INT_PRINT, strlen (HOST_WIDE_INT_PRINT));
3729 q += strlen (HOST_WIDE_INT_PRINT);
3cf2715d
DE
3730 *q++ = *p++;
3731 *q = 0;
3732 fprintf (file, buf, va_arg (argptr, HOST_WIDE_INT));
3733 break;
3734
3735 case 'l':
3736 *q++ = c;
b1721339
KG
3737#ifdef HAVE_LONG_LONG
3738 if (*p == 'l')
3739 {
3740 *q++ = *p++;
3741 *q++ = *p++;
3742 *q = 0;
3743 fprintf (file, buf, va_arg (argptr, long long));
3744 }
3745 else
3746#endif
3747 {
3748 *q++ = *p++;
3749 *q = 0;
3750 fprintf (file, buf, va_arg (argptr, long));
3751 }
6cf9ac28 3752
3cf2715d
DE
3753 break;
3754
3755 case 's':
3756 *q++ = c;
3757 *q = 0;
3758 fprintf (file, buf, va_arg (argptr, char *));
3759 break;
3760
3761 case 'O':
3762#ifdef ASM_OUTPUT_OPCODE
3763 ASM_OUTPUT_OPCODE (asm_out_file, p);
3764#endif
3765 break;
3766
3767 case 'R':
3768#ifdef REGISTER_PREFIX
3769 fprintf (file, "%s", REGISTER_PREFIX);
3770#endif
3771 break;
3772
3773 case 'I':
3774#ifdef IMMEDIATE_PREFIX
3775 fprintf (file, "%s", IMMEDIATE_PREFIX);
3776#endif
3777 break;
3778
3779 case 'L':
3780#ifdef LOCAL_LABEL_PREFIX
3781 fprintf (file, "%s", LOCAL_LABEL_PREFIX);
3782#endif
3783 break;
3784
3785 case 'U':
19283265 3786 fputs (user_label_prefix, file);
3cf2715d
DE
3787 break;
3788
fe0503ea 3789#ifdef ASM_FPRINTF_EXTENSIONS
7ef0daad 3790 /* Uppercase letters are reserved for general use by asm_fprintf
fe0503ea
NC
3791 and so are not available to target specific code. In order to
3792 prevent the ASM_FPRINTF_EXTENSIONS macro from using them then,
3793 they are defined here. As they get turned into real extensions
3794 to asm_fprintf they should be removed from this list. */
3795 case 'A': case 'B': case 'C': case 'D': case 'E':
3796 case 'F': case 'G': case 'H': case 'J': case 'K':
3797 case 'M': case 'N': case 'P': case 'Q': case 'S':
3798 case 'T': case 'V': case 'W': case 'Y': case 'Z':
3799 break;
f5d927c0 3800
fe0503ea
NC
3801 ASM_FPRINTF_EXTENSIONS (file, argptr, p)
3802#endif
3cf2715d 3803 default:
0bccc606 3804 gcc_unreachable ();
3cf2715d
DE
3805 }
3806 break;
3807
3808 default:
b1721339 3809 putc (c, file);
3cf2715d 3810 }
e34d07f2 3811 va_end (argptr);
3cf2715d
DE
3812}
3813\f
3814/* Split up a CONST_DOUBLE or integer constant rtx
3815 into two rtx's for single words,
3816 storing in *FIRST the word that comes first in memory in the target
3817 and in *SECOND the other. */
3818
3819void
6cf9ac28 3820split_double (rtx value, rtx *first, rtx *second)
3cf2715d 3821{
481683e1 3822 if (CONST_INT_P (value))
3cf2715d 3823 {
5a1a6efd 3824 if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
f76b9db2 3825 {
5a1a6efd 3826 /* In this case the CONST_INT holds both target words.
27eef9ce
JC
3827 Extract the bits from it into two word-sized pieces.
3828 Sign extend each half to HOST_WIDE_INT. */
7f251dee
AO
3829 unsigned HOST_WIDE_INT low, high;
3830 unsigned HOST_WIDE_INT mask, sign_bit, sign_extend;
3831
3832 /* Set sign_bit to the most significant bit of a word. */
3833 sign_bit = 1;
3834 sign_bit <<= BITS_PER_WORD - 1;
3835
3836 /* Set mask so that all bits of the word are set. We could
3837 have used 1 << BITS_PER_WORD instead of basing the
3838 calculation on sign_bit. However, on machines where
3839 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
3840 compiler warning, even though the code would never be
3841 executed. */
3842 mask = sign_bit << 1;
3843 mask--;
3844
3845 /* Set sign_extend as any remaining bits. */
3846 sign_extend = ~mask;
f5d927c0 3847
7f251dee
AO
3848 /* Pick the lower word and sign-extend it. */
3849 low = INTVAL (value);
3850 low &= mask;
3851 if (low & sign_bit)
3852 low |= sign_extend;
3853
3854 /* Pick the higher word, shifted to the least significant
3855 bits, and sign-extend it. */
3856 high = INTVAL (value);
3857 high >>= BITS_PER_WORD - 1;
3858 high >>= 1;
3859 high &= mask;
3860 if (high & sign_bit)
3861 high |= sign_extend;
3862
3863 /* Store the words in the target machine order. */
5a1a6efd
RK
3864 if (WORDS_BIG_ENDIAN)
3865 {
7f251dee
AO
3866 *first = GEN_INT (high);
3867 *second = GEN_INT (low);
5a1a6efd
RK
3868 }
3869 else
3870 {
7f251dee
AO
3871 *first = GEN_INT (low);
3872 *second = GEN_INT (high);
5a1a6efd 3873 }
f76b9db2
ILT
3874 }
3875 else
3876 {
5a1a6efd
RK
3877 /* The rule for using CONST_INT for a wider mode
3878 is that we regard the value as signed.
3879 So sign-extend it. */
3880 rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx);
3881 if (WORDS_BIG_ENDIAN)
3882 {
3883 *first = high;
3884 *second = value;
3885 }
3886 else
3887 {
3888 *first = value;
3889 *second = high;
3890 }
f76b9db2 3891 }
3cf2715d
DE
3892 }
3893 else if (GET_CODE (value) != CONST_DOUBLE)
3894 {
f76b9db2
ILT
3895 if (WORDS_BIG_ENDIAN)
3896 {
3897 *first = const0_rtx;
3898 *second = value;
3899 }
3900 else
3901 {
3902 *first = value;
3903 *second = const0_rtx;
3904 }
3cf2715d
DE
3905 }
3906 else if (GET_MODE (value) == VOIDmode
3907 /* This is the old way we did CONST_DOUBLE integers. */
3908 || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT)
3909 {
3910 /* In an integer, the words are defined as most and least significant.
3911 So order them by the target's convention. */
f76b9db2
ILT
3912 if (WORDS_BIG_ENDIAN)
3913 {
3914 *first = GEN_INT (CONST_DOUBLE_HIGH (value));
3915 *second = GEN_INT (CONST_DOUBLE_LOW (value));
3916 }
3917 else
3918 {
3919 *first = GEN_INT (CONST_DOUBLE_LOW (value));
3920 *second = GEN_INT (CONST_DOUBLE_HIGH (value));
3921 }
3cf2715d
DE
3922 }
3923 else
3924 {
f5d927c0
KH
3925 REAL_VALUE_TYPE r;
3926 long l[2];
3cf2715d
DE
3927 REAL_VALUE_FROM_CONST_DOUBLE (r, value);
3928
3929 /* Note, this converts the REAL_VALUE_TYPE to the target's
3930 format, splits up the floating point double and outputs
3931 exactly 32 bits of it into each of l[0] and l[1] --
0f41302f 3932 not necessarily BITS_PER_WORD bits. */
3cf2715d
DE
3933 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
3934
b5a3eb84
JW
3935 /* If 32 bits is an entire word for the target, but not for the host,
3936 then sign-extend on the host so that the number will look the same
3937 way on the host that it would on the target. See for instance
3938 simplify_unary_operation. The #if is needed to avoid compiler
3939 warnings. */
3940
3941#if HOST_BITS_PER_LONG > 32
3942 if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32)
3943 {
3944 if (l[0] & ((long) 1 << 31))
3945 l[0] |= ((long) (-1) << 32);
3946 if (l[1] & ((long) 1 << 31))
3947 l[1] |= ((long) (-1) << 32);
3948 }
3949#endif
3950
3e95a7cb
ZW
3951 *first = GEN_INT (l[0]);
3952 *second = GEN_INT (l[1]);
3cf2715d
DE
3953 }
3954}
3955\f
3956/* Return nonzero if this function has no function calls. */
3957
3958int
6cf9ac28 3959leaf_function_p (void)
3cf2715d
DE
3960{
3961 rtx insn;
b660f82f 3962 rtx link;
3cf2715d 3963
e3b5732b 3964 if (crtl->profile || profile_arc_flag)
3cf2715d
DE
3965 return 0;
3966
3967 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
3968 {
4b4bf941 3969 if (CALL_P (insn)
7d167afd 3970 && ! SIBLING_CALL_P (insn))
3cf2715d 3971 return 0;
4b4bf941 3972 if (NONJUMP_INSN_P (insn)
3cf2715d 3973 && GET_CODE (PATTERN (insn)) == SEQUENCE
4b4bf941 3974 && CALL_P (XVECEXP (PATTERN (insn), 0, 0))
0a1c58a2 3975 && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0)))
3cf2715d
DE
3976 return 0;
3977 }
cb91fab0 3978 for (link = crtl->epilogue_delay_list;
b660f82f
JW
3979 link;
3980 link = XEXP (link, 1))
3cf2715d 3981 {
b660f82f
JW
3982 insn = XEXP (link, 0);
3983
4b4bf941 3984 if (CALL_P (insn)
7d167afd 3985 && ! SIBLING_CALL_P (insn))
3cf2715d 3986 return 0;
4b4bf941 3987 if (NONJUMP_INSN_P (insn)
b660f82f 3988 && GET_CODE (PATTERN (insn)) == SEQUENCE
4b4bf941 3989 && CALL_P (XVECEXP (PATTERN (insn), 0, 0))
b660f82f 3990 && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0)))
3cf2715d
DE
3991 return 0;
3992 }
3993
3994 return 1;
3995}
3996
09da1532 3997/* Return 1 if branch is a forward branch.
ef6257cd
JH
3998 Uses insn_shuid array, so it works only in the final pass. May be used by
3999 output templates to customary add branch prediction hints.
4000 */
4001int
6cf9ac28 4002final_forward_branch_p (rtx insn)
ef6257cd
JH
4003{
4004 int insn_id, label_id;
b0efb46b 4005
0bccc606 4006 gcc_assert (uid_shuid);
ef6257cd
JH
4007 insn_id = INSN_SHUID (insn);
4008 label_id = INSN_SHUID (JUMP_LABEL (insn));
4009 /* We've hit some insns that does not have id information available. */
0bccc606 4010 gcc_assert (insn_id && label_id);
ef6257cd
JH
4011 return insn_id < label_id;
4012}
4013
3cf2715d
DE
4014/* On some machines, a function with no call insns
4015 can run faster if it doesn't create its own register window.
4016 When output, the leaf function should use only the "output"
4017 registers. Ordinarily, the function would be compiled to use
4018 the "input" registers to find its arguments; it is a candidate
4019 for leaf treatment if it uses only the "input" registers.
4020 Leaf function treatment means renumbering so the function
4021 uses the "output" registers instead. */
4022
4023#ifdef LEAF_REGISTERS
4024
3cf2715d
DE
4025/* Return 1 if this function uses only the registers that can be
4026 safely renumbered. */
4027
4028int
6cf9ac28 4029only_leaf_regs_used (void)
3cf2715d
DE
4030{
4031 int i;
4977bab6 4032 const char *const permitted_reg_in_leaf_functions = LEAF_REGISTERS;
3cf2715d
DE
4033
4034 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6fb5fa3c 4035 if ((df_regs_ever_live_p (i) || global_regs[i])
e5e809f4
JL
4036 && ! permitted_reg_in_leaf_functions[i])
4037 return 0;
4038
e3b5732b 4039 if (crtl->uses_pic_offset_table
e5e809f4 4040 && pic_offset_table_rtx != 0
f8cfc6aa 4041 && REG_P (pic_offset_table_rtx)
e5e809f4
JL
4042 && ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)])
4043 return 0;
4044
3cf2715d
DE
4045 return 1;
4046}
4047
4048/* Scan all instructions and renumber all registers into those
4049 available in leaf functions. */
4050
4051static void
6cf9ac28 4052leaf_renumber_regs (rtx first)
3cf2715d
DE
4053{
4054 rtx insn;
4055
4056 /* Renumber only the actual patterns.
4057 The reg-notes can contain frame pointer refs,
4058 and renumbering them could crash, and should not be needed. */
4059 for (insn = first; insn; insn = NEXT_INSN (insn))
2c3c49de 4060 if (INSN_P (insn))
3cf2715d 4061 leaf_renumber_regs_insn (PATTERN (insn));
cb91fab0 4062 for (insn = crtl->epilogue_delay_list;
f5d927c0
KH
4063 insn;
4064 insn = XEXP (insn, 1))
2c3c49de 4065 if (INSN_P (XEXP (insn, 0)))
3cf2715d
DE
4066 leaf_renumber_regs_insn (PATTERN (XEXP (insn, 0)));
4067}
4068
4069/* Scan IN_RTX and its subexpressions, and renumber all regs into those
4070 available in leaf functions. */
4071
4072void
6cf9ac28 4073leaf_renumber_regs_insn (rtx in_rtx)
3cf2715d 4074{
b3694847
SS
4075 int i, j;
4076 const char *format_ptr;
3cf2715d
DE
4077
4078 if (in_rtx == 0)
4079 return;
4080
4081 /* Renumber all input-registers into output-registers.
4082 renumbered_regs would be 1 for an output-register;
4083 they */
4084
f8cfc6aa 4085 if (REG_P (in_rtx))
3cf2715d
DE
4086 {
4087 int newreg;
4088
4089 /* Don't renumber the same reg twice. */
4090 if (in_rtx->used)
4091 return;
4092
4093 newreg = REGNO (in_rtx);
4094 /* Don't try to renumber pseudo regs. It is possible for a pseudo reg
4095 to reach here as part of a REG_NOTE. */
4096 if (newreg >= FIRST_PSEUDO_REGISTER)
4097 {
4098 in_rtx->used = 1;
4099 return;
4100 }
4101 newreg = LEAF_REG_REMAP (newreg);
0bccc606 4102 gcc_assert (newreg >= 0);
6fb5fa3c
DB
4103 df_set_regs_ever_live (REGNO (in_rtx), false);
4104 df_set_regs_ever_live (newreg, true);
4105 SET_REGNO (in_rtx, newreg);
3cf2715d
DE
4106 in_rtx->used = 1;
4107 }
4108
2c3c49de 4109 if (INSN_P (in_rtx))
3cf2715d
DE
4110 {
4111 /* Inside a SEQUENCE, we find insns.
4112 Renumber just the patterns of these insns,
4113 just as we do for the top-level insns. */
4114 leaf_renumber_regs_insn (PATTERN (in_rtx));
4115 return;
4116 }
4117
4118 format_ptr = GET_RTX_FORMAT (GET_CODE (in_rtx));
4119
4120 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (in_rtx)); i++)
4121 switch (*format_ptr++)
4122 {
4123 case 'e':
4124 leaf_renumber_regs_insn (XEXP (in_rtx, i));
4125 break;
4126
4127 case 'E':
4128 if (NULL != XVEC (in_rtx, i))
4129 {
4130 for (j = 0; j < XVECLEN (in_rtx, i); j++)
4131 leaf_renumber_regs_insn (XVECEXP (in_rtx, i, j));
4132 }
4133 break;
4134
4135 case 'S':
4136 case 's':
4137 case '0':
4138 case 'i':
4139 case 'w':
4140 case 'n':
4141 case 'u':
4142 break;
4143
4144 default:
0bccc606 4145 gcc_unreachable ();
3cf2715d
DE
4146 }
4147}
4148#endif
6a08f7b3
DP
4149
4150
4151/* When -gused is used, emit debug info for only used symbols. But in
4152 addition to the standard intercepted debug_hooks there are some direct
4153 calls into this file, i.e., dbxout_symbol, dbxout_parms, and dbxout_reg_params.
4154 Those routines may also be called from a higher level intercepted routine. So
4155 to prevent recording data for an inner call to one of these for an intercept,
5d3cc252 4156 we maintain an intercept nesting counter (debug_nesting). We only save the
6a08f7b3
DP
4157 intercepted arguments if the nesting is 1. */
4158int debug_nesting = 0;
4159
4160static tree *symbol_queue;
4161int symbol_queue_index = 0;
4162static int symbol_queue_size = 0;
4163
4164/* Generate the symbols for any queued up type symbols we encountered
4165 while generating the type info for some originally used symbol.
4166 This might generate additional entries in the queue. Only when
4167 the nesting depth goes to 0 is this routine called. */
4168
4169void
6cf9ac28 4170debug_flush_symbol_queue (void)
6a08f7b3
DP
4171{
4172 int i;
6cf9ac28 4173
6a08f7b3
DP
4174 /* Make sure that additionally queued items are not flushed
4175 prematurely. */
6cf9ac28 4176
6a08f7b3 4177 ++debug_nesting;
6cf9ac28 4178
6a08f7b3
DP
4179 for (i = 0; i < symbol_queue_index; ++i)
4180 {
b0efb46b 4181 /* If we pushed queued symbols then such symbols must be
6a08f7b3
DP
4182 output no matter what anyone else says. Specifically,
4183 we need to make sure dbxout_symbol() thinks the symbol was
4184 used and also we need to override TYPE_DECL_SUPPRESS_DEBUG
4185 which may be set for outside reasons. */
4186 int saved_tree_used = TREE_USED (symbol_queue[i]);
4187 int saved_suppress_debug = TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]);
4188 TREE_USED (symbol_queue[i]) = 1;
4189 TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]) = 0;
4190
4191#ifdef DBX_DEBUGGING_INFO
4192 dbxout_symbol (symbol_queue[i], 0);
4193#endif
4194
4195 TREE_USED (symbol_queue[i]) = saved_tree_used;
4196 TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]) = saved_suppress_debug;
4197 }
4198
4199 symbol_queue_index = 0;
6cf9ac28 4200 --debug_nesting;
6a08f7b3
DP
4201}
4202
4203/* Queue a type symbol needed as part of the definition of a decl
4204 symbol. These symbols are generated when debug_flush_symbol_queue()
4205 is called. */
4206
6cf9ac28 4207void
6a08f7b3
DP
4208debug_queue_symbol (tree decl)
4209{
6cf9ac28 4210 if (symbol_queue_index >= symbol_queue_size)
6a08f7b3
DP
4211 {
4212 symbol_queue_size += 10;
1b4572a8 4213 symbol_queue = XRESIZEVEC (tree, symbol_queue, symbol_queue_size);
6a08f7b3
DP
4214 }
4215
4216 symbol_queue[symbol_queue_index++] = decl;
6cf9ac28 4217}
6a08f7b3 4218
f9da5064 4219/* Free symbol queue. */
6a08f7b3 4220void
6cf9ac28 4221debug_free_queue (void)
6a08f7b3
DP
4222{
4223 if (symbol_queue)
4224 {
4225 free (symbol_queue);
4226 symbol_queue = NULL;
4227 symbol_queue_size = 0;
4228 }
4229}
ef330312
PB
4230\f
4231/* Turn the RTL into assembly. */
c2924966 4232static unsigned int
ef330312
PB
4233rest_of_handle_final (void)
4234{
4235 rtx x;
4236 const char *fnname;
4237
4238 /* Get the function's name, as described by its RTL. This may be
4239 different from the DECL_NAME name used in the source file. */
4240
4241 x = DECL_RTL (current_function_decl);
4242 gcc_assert (MEM_P (x));
4243 x = XEXP (x, 0);
4244 gcc_assert (GET_CODE (x) == SYMBOL_REF);
4245 fnname = XSTR (x, 0);
4246
4247 assemble_start_function (current_function_decl, fnname);
4248 final_start_function (get_insns (), asm_out_file, optimize);
4249 final (get_insns (), asm_out_file, optimize);
4250 final_end_function ();
4251
4252#ifdef TARGET_UNWIND_INFO
4253 /* ??? The IA-64 ".handlerdata" directive must be issued before
4254 the ".endp" directive that closes the procedure descriptor. */
22ba88ef 4255 output_function_exception_table (fnname);
ef330312
PB
4256#endif
4257
4258 assemble_end_function (current_function_decl, fnname);
4259
4260#ifndef TARGET_UNWIND_INFO
4261 /* Otherwise, it feels unclean to switch sections in the middle. */
22ba88ef 4262 output_function_exception_table (fnname);
ef330312
PB
4263#endif
4264
4265 user_defined_section_attribute = false;
4266
6fb5fa3c
DB
4267 /* Free up reg info memory. */
4268 free_reg_info ();
4269
ef330312
PB
4270 if (! quiet_flag)
4271 fflush (asm_out_file);
4272
ef330312
PB
4273 /* Write DBX symbols if requested. */
4274
4275 /* Note that for those inline functions where we don't initially
4276 know for certain that we will be generating an out-of-line copy,
4277 the first invocation of this routine (rest_of_compilation) will
4278 skip over this code by doing a `goto exit_rest_of_compilation;'.
4279 Later on, wrapup_global_declarations will (indirectly) call
4280 rest_of_compilation again for those inline functions that need
4281 to have out-of-line copies generated. During that call, we
4282 *will* be routed past here. */
4283
4284 timevar_push (TV_SYMOUT);
725730f2
EB
4285 if (!DECL_IGNORED_P (current_function_decl))
4286 debug_hooks->function_decl (current_function_decl);
ef330312 4287 timevar_pop (TV_SYMOUT);
6b20f353
DS
4288
4289 /* Release the blocks that are linked to DECL_INITIAL() to free the memory. */
4290 DECL_INITIAL (current_function_decl) = error_mark_node;
4291
395a40e0
JH
4292 if (DECL_STATIC_CONSTRUCTOR (current_function_decl)
4293 && targetm.have_ctors_dtors)
4294 targetm.asm_out.constructor (XEXP (DECL_RTL (current_function_decl), 0),
4295 decl_init_priority_lookup
4296 (current_function_decl));
4297 if (DECL_STATIC_DESTRUCTOR (current_function_decl)
4298 && targetm.have_ctors_dtors)
4299 targetm.asm_out.destructor (XEXP (DECL_RTL (current_function_decl), 0),
4300 decl_fini_priority_lookup
4301 (current_function_decl));
c2924966 4302 return 0;
ef330312
PB
4303}
4304
8ddbbcae 4305struct rtl_opt_pass pass_final =
ef330312 4306{
8ddbbcae
JH
4307 {
4308 RTL_PASS,
e7f373fa 4309 "final", /* name */
ef330312
PB
4310 NULL, /* gate */
4311 rest_of_handle_final, /* execute */
4312 NULL, /* sub */
4313 NULL, /* next */
4314 0, /* static_pass_number */
4315 TV_FINAL, /* tv_id */
4316 0, /* properties_required */
4317 0, /* properties_provided */
4318 0, /* properties_destroyed */
4319 0, /* todo_flags_start */
8ddbbcae
JH
4320 TODO_ggc_collect /* todo_flags_finish */
4321 }
ef330312
PB
4322};
4323
4324
c2924966 4325static unsigned int
ef330312
PB
4326rest_of_handle_shorten_branches (void)
4327{
4328 /* Shorten branches. */
4329 shorten_branches (get_insns ());
c2924966 4330 return 0;
ef330312 4331}
b0efb46b 4332
8ddbbcae 4333struct rtl_opt_pass pass_shorten_branches =
ef330312 4334{
8ddbbcae
JH
4335 {
4336 RTL_PASS,
defb77dc 4337 "shorten", /* name */
ef330312
PB
4338 NULL, /* gate */
4339 rest_of_handle_shorten_branches, /* execute */
4340 NULL, /* sub */
4341 NULL, /* next */
4342 0, /* static_pass_number */
4343 TV_FINAL, /* tv_id */
4344 0, /* properties_required */
4345 0, /* properties_provided */
4346 0, /* properties_destroyed */
4347 0, /* todo_flags_start */
8ddbbcae
JH
4348 TODO_dump_func /* todo_flags_finish */
4349 }
ef330312
PB
4350};
4351
4352
c2924966 4353static unsigned int
ef330312
PB
4354rest_of_clean_state (void)
4355{
4356 rtx insn, next;
2153915d
AO
4357 FILE *final_output = NULL;
4358 int save_unnumbered = flag_dump_unnumbered;
4359 int save_noaddr = flag_dump_noaddr;
4360
4361 if (flag_dump_final_insns)
4362 {
4363 final_output = fopen (flag_dump_final_insns, "a");
4364 if (!final_output)
4365 {
7ca92787
JM
4366 error ("could not open final insn dump file %qs: %m",
4367 flag_dump_final_insns);
2153915d
AO
4368 flag_dump_final_insns = NULL;
4369 }
4370 else
4371 {
4372 const char *aname;
5fefcf92 4373 struct cgraph_node *node = cgraph_node (current_function_decl);
2153915d
AO
4374
4375 aname = (IDENTIFIER_POINTER
4376 (DECL_ASSEMBLER_NAME (current_function_decl)));
4377 fprintf (final_output, "\n;; Function (%s) %s\n\n", aname,
5fefcf92 4378 node->frequency == NODE_FREQUENCY_HOT
2153915d 4379 ? " (hot)"
5fefcf92 4380 : node->frequency == NODE_FREQUENCY_UNLIKELY_EXECUTED
2153915d 4381 ? " (unlikely executed)"
5fefcf92
JH
4382 : node->frequency == NODE_FREQUENCY_EXECUTED_ONCE
4383 ? " (executed once)"
2153915d
AO
4384 : "");
4385
4386 flag_dump_noaddr = flag_dump_unnumbered = 1;
c7ba0cfb
RG
4387 if (flag_compare_debug_opt || flag_compare_debug)
4388 dump_flags |= TDF_NOUID;
6ca5d1f6 4389 final_insns_dump_p = true;
2153915d
AO
4390
4391 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4392 if (LABEL_P (insn))
4393 INSN_UID (insn) = CODE_LABEL_NUMBER (insn);
4394 else
4395 INSN_UID (insn) = 0;
4396 }
4397 }
ef330312
PB
4398
4399 /* It is very important to decompose the RTL instruction chain here:
4400 debug information keeps pointing into CODE_LABEL insns inside the function
4401 body. If these remain pointing to the other insns, we end up preserving
4402 whole RTL chain and attached detailed debug info in memory. */
4403 for (insn = get_insns (); insn; insn = next)
4404 {
4405 next = NEXT_INSN (insn);
4406 NEXT_INSN (insn) = NULL;
4407 PREV_INSN (insn) = NULL;
2153915d
AO
4408
4409 if (final_output
4410 && (!NOTE_P (insn) ||
4411 (NOTE_KIND (insn) != NOTE_INSN_VAR_LOCATION
4412 && NOTE_KIND (insn) != NOTE_INSN_BLOCK_BEG
b5b8b0ac
AO
4413 && NOTE_KIND (insn) != NOTE_INSN_BLOCK_END
4414 && NOTE_KIND (insn) != NOTE_INSN_CFA_RESTORE_STATE)))
2153915d
AO
4415 print_rtl_single (final_output, insn);
4416
4417 }
4418
4419 if (final_output)
4420 {
4421 flag_dump_noaddr = save_noaddr;
4422 flag_dump_unnumbered = save_unnumbered;
6ca5d1f6 4423 final_insns_dump_p = false;
2153915d
AO
4424
4425 if (fclose (final_output))
4426 {
7ca92787
JM
4427 error ("could not close final insn dump file %qs: %m",
4428 flag_dump_final_insns);
2153915d
AO
4429 flag_dump_final_insns = NULL;
4430 }
ef330312
PB
4431 }
4432
4433 /* In case the function was not output,
4434 don't leave any temporary anonymous types
4435 queued up for sdb output. */
4436#ifdef SDB_DEBUGGING_INFO
4437 if (write_symbols == SDB_DEBUG)
4438 sdbout_types (NULL_TREE);
4439#endif
4440
5f39ad47 4441 flag_rerun_cse_after_global_opts = 0;
ef330312
PB
4442 reload_completed = 0;
4443 epilogue_completed = 0;
23249ac4
DB
4444#ifdef STACK_REGS
4445 regstack_completed = 0;
4446#endif
ef330312
PB
4447
4448 /* Clear out the insn_length contents now that they are no
4449 longer valid. */
4450 init_insn_lengths ();
4451
4452 /* Show no temporary slots allocated. */
4453 init_temp_slots ();
4454
ef330312
PB
4455 free_bb_for_insn ();
4456
55b34b5f
RG
4457 delete_tree_ssa ();
4458
ef330312
PB
4459 if (targetm.binds_local_p (current_function_decl))
4460 {
17b29c0a 4461 unsigned int pref = crtl->preferred_stack_boundary;
cb91fab0
JH
4462 if (crtl->stack_alignment_needed > crtl->preferred_stack_boundary)
4463 pref = crtl->stack_alignment_needed;
ef330312
PB
4464 cgraph_rtl_info (current_function_decl)->preferred_incoming_stack_boundary
4465 = pref;
4466 }
4467
4468 /* Make sure volatile mem refs aren't considered valid operands for
4469 arithmetic insns. We must call this here if this is a nested inline
4470 function, since the above code leaves us in the init_recog state,
4471 and the function context push/pop code does not save/restore volatile_ok.
4472
4473 ??? Maybe it isn't necessary for expand_start_function to call this
4474 anymore if we do it here? */
4475
4476 init_recog_no_volatile ();
4477
4478 /* We're done with this function. Free up memory if we can. */
4479 free_after_parsing (cfun);
4480 free_after_compilation (cfun);
c2924966 4481 return 0;
ef330312
PB
4482}
4483
8ddbbcae 4484struct rtl_opt_pass pass_clean_state =
ef330312 4485{
8ddbbcae
JH
4486 {
4487 RTL_PASS,
cf400ddb 4488 "*clean_state", /* name */
ef330312
PB
4489 NULL, /* gate */
4490 rest_of_clean_state, /* execute */
4491 NULL, /* sub */
4492 NULL, /* next */
4493 0, /* static_pass_number */
4494 TV_FINAL, /* tv_id */
4495 0, /* properties_required */
4496 0, /* properties_provided */
4497 PROP_rtl, /* properties_destroyed */
4498 0, /* todo_flags_start */
8ddbbcae
JH
4499 0 /* todo_flags_finish */
4500 }
ef330312 4501};