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3cf2715d | 1 | /* Convert RTL to assembler code and output it, for GNU compiler. |
3b708058 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, |
ff81832f | 3 | 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
3cf2715d | 4 | |
1322177d | 5 | This file is part of GCC. |
3cf2715d | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
3cf2715d | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
3cf2715d DE |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
3cf2715d | 21 | |
3cf2715d DE |
22 | /* This is the final pass of the compiler. |
23 | It looks at the rtl code for a function and outputs assembler code. | |
24 | ||
25 | Call `final_start_function' to output the assembler code for function entry, | |
26 | `final' to output assembler code for some RTL code, | |
27 | `final_end_function' to output assembler code for function exit. | |
28 | If a function is compiled in several pieces, each piece is | |
29 | output separately with `final'. | |
30 | ||
31 | Some optimizations are also done at this level. | |
32 | Move instructions that were made unnecessary by good register allocation | |
33 | are detected and omitted from the output. (Though most of these | |
34 | are removed by the last jump pass.) | |
35 | ||
36 | Instructions to set the condition codes are omitted when it can be | |
37 | seen that the condition codes already had the desired values. | |
38 | ||
39 | In some cases it is sufficient if the inherited condition codes | |
40 | have related values, but this may require the following insn | |
41 | (the one that tests the condition codes) to be modified. | |
42 | ||
43 | The code for the function prologue and epilogue are generated | |
08c148a8 NB |
44 | directly in assembler by the target functions function_prologue and |
45 | function_epilogue. Those instructions never exist as rtl. */ | |
3cf2715d DE |
46 | |
47 | #include "config.h" | |
670ee920 | 48 | #include "system.h" |
3cf2715d DE |
49 | |
50 | #include "tree.h" | |
51 | #include "rtl.h" | |
6baf1cc8 | 52 | #include "tm_p.h" |
3cf2715d DE |
53 | #include "regs.h" |
54 | #include "insn-config.h" | |
3cf2715d | 55 | #include "insn-attr.h" |
3cf2715d DE |
56 | #include "recog.h" |
57 | #include "conditions.h" | |
58 | #include "flags.h" | |
59 | #include "real.h" | |
60 | #include "hard-reg-set.h" | |
3cf2715d | 61 | #include "output.h" |
3d195391 | 62 | #include "except.h" |
49ad7cfa | 63 | #include "function.h" |
10f0ad3d | 64 | #include "toplev.h" |
d6f4ec51 | 65 | #include "reload.h" |
ab87f8c8 | 66 | #include "intl.h" |
be1bb652 | 67 | #include "basic-block.h" |
08c148a8 | 68 | #include "target.h" |
a5a42b92 | 69 | #include "debug.h" |
49d801d3 | 70 | #include "expr.h" |
b7c9bf28 | 71 | #include "profile.h" |
ba4f7968 | 72 | #include "cfglayout.h" |
3cf2715d | 73 | |
440aabf8 NB |
74 | #ifdef XCOFF_DEBUGGING_INFO |
75 | #include "xcoffout.h" /* Needed for external data | |
76 | declarations for e.g. AIX 4.x. */ | |
77 | #endif | |
78 | ||
76ead72b RL |
79 | #if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO) |
80 | #include "dwarf2out.h" | |
81 | #endif | |
82 | ||
3cf2715d DE |
83 | /* If we aren't using cc0, CC_STATUS_INIT shouldn't exist. So define a |
84 | null default for it to save conditionalization later. */ | |
85 | #ifndef CC_STATUS_INIT | |
86 | #define CC_STATUS_INIT | |
87 | #endif | |
88 | ||
89 | /* How to start an assembler comment. */ | |
90 | #ifndef ASM_COMMENT_START | |
91 | #define ASM_COMMENT_START ";#" | |
92 | #endif | |
93 | ||
94 | /* Is the given character a logical line separator for the assembler? */ | |
95 | #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR | |
96 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';') | |
97 | #endif | |
98 | ||
75197b37 BS |
99 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
100 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
101 | #endif | |
102 | ||
d48bc59a RH |
103 | #if defined(READONLY_DATA_SECTION) || defined(READONLY_DATA_SECTION_ASM_OP) |
104 | #define HAVE_READONLY_DATA_SECTION 1 | |
105 | #else | |
106 | #define HAVE_READONLY_DATA_SECTION 0 | |
107 | #endif | |
108 | ||
3cf2715d | 109 | /* Last insn processed by final_scan_insn. */ |
b1a9f6a0 RH |
110 | static rtx debug_insn; |
111 | rtx current_output_insn; | |
3cf2715d DE |
112 | |
113 | /* Line number of last NOTE. */ | |
114 | static int last_linenum; | |
115 | ||
eac40081 RK |
116 | /* Highest line number in current block. */ |
117 | static int high_block_linenum; | |
118 | ||
119 | /* Likewise for function. */ | |
120 | static int high_function_linenum; | |
121 | ||
3cf2715d | 122 | /* Filename of last NOTE. */ |
3cce094d | 123 | static const char *last_filename; |
3cf2715d | 124 | |
fc470718 R |
125 | extern int length_unit_log; /* This is defined in insn-attrtab.c. */ |
126 | ||
3cf2715d DE |
127 | /* Nonzero while outputting an `asm' with operands. |
128 | This means that inconsistencies are the user's fault, so don't abort. | |
129 | The precise value is the insn being output, to pass to error_for_asm. */ | |
c8b94768 | 130 | rtx this_is_asm_operands; |
3cf2715d DE |
131 | |
132 | /* Number of operands of this insn, for an `asm' with operands. */ | |
22bf4422 | 133 | static unsigned int insn_noperands; |
3cf2715d DE |
134 | |
135 | /* Compare optimization flag. */ | |
136 | ||
137 | static rtx last_ignored_compare = 0; | |
138 | ||
139 | /* Flag indicating this insn is the start of a new basic block. */ | |
140 | ||
141 | static int new_block = 1; | |
142 | ||
3cf2715d DE |
143 | /* Assign a unique number to each insn that is output. |
144 | This can be used to generate unique local labels. */ | |
145 | ||
146 | static int insn_counter = 0; | |
147 | ||
148 | #ifdef HAVE_cc0 | |
149 | /* This variable contains machine-dependent flags (defined in tm.h) | |
150 | set and examined by output routines | |
151 | that describe how to interpret the condition codes properly. */ | |
152 | ||
153 | CC_STATUS cc_status; | |
154 | ||
155 | /* During output of an insn, this contains a copy of cc_status | |
156 | from before the insn. */ | |
157 | ||
158 | CC_STATUS cc_prev_status; | |
159 | #endif | |
160 | ||
161 | /* Indexed by hardware reg number, is 1 if that register is ever | |
162 | used in the current function. | |
163 | ||
164 | In life_analysis, or in stupid_life_analysis, this is set | |
165 | up to record the hard regs used explicitly. Reload adds | |
166 | in the hard regs used for holding pseudo regs. Final uses | |
167 | it to generate the code in the function prologue and epilogue | |
168 | to save and restore registers as needed. */ | |
169 | ||
170 | char regs_ever_live[FIRST_PSEUDO_REGISTER]; | |
171 | ||
172 | /* Nonzero means current function must be given a frame pointer. | |
173 | Set in stmt.c if anything is allocated on the stack there. | |
174 | Set in reload1.c if anything is allocated on the stack there. */ | |
175 | ||
176 | int frame_pointer_needed; | |
177 | ||
18c038b9 | 178 | /* Number of unmatched NOTE_INSN_BLOCK_BEG notes we have seen. */ |
3cf2715d DE |
179 | |
180 | static int block_depth; | |
181 | ||
182 | /* Nonzero if have enabled APP processing of our assembler output. */ | |
183 | ||
184 | static int app_on; | |
185 | ||
186 | /* If we are outputting an insn sequence, this contains the sequence rtx. | |
187 | Zero otherwise. */ | |
188 | ||
189 | rtx final_sequence; | |
190 | ||
191 | #ifdef ASSEMBLER_DIALECT | |
192 | ||
193 | /* Number of the assembler dialect to use, starting at 0. */ | |
194 | static int dialect_number; | |
195 | #endif | |
196 | ||
197 | /* Indexed by line number, nonzero if there is a note for that line. */ | |
198 | ||
199 | static char *line_note_exists; | |
200 | ||
afe48e06 RH |
201 | #ifdef HAVE_conditional_execution |
202 | /* Nonnull if the insn currently being emitted was a COND_EXEC pattern. */ | |
203 | rtx current_insn_predicate; | |
204 | #endif | |
205 | ||
b7c9bf28 JH |
206 | struct function_list |
207 | { | |
208 | struct function_list *next; /* next function */ | |
209 | const char *name; /* function name */ | |
210 | long cfg_checksum; /* function checksum */ | |
211 | long count_edges; /* number of intrumented edges in this function */ | |
212 | }; | |
213 | ||
214 | static struct function_list *functions_head = 0; | |
215 | static struct function_list **functions_tail = &functions_head; | |
216 | ||
1d300e19 | 217 | #ifdef HAVE_ATTR_length |
711d877c KG |
218 | static int asm_insn_count PARAMS ((rtx)); |
219 | #endif | |
220 | static void profile_function PARAMS ((FILE *)); | |
221 | static void profile_after_prologue PARAMS ((FILE *)); | |
653e276c | 222 | static void notice_source_line PARAMS ((rtx)); |
49d801d3 | 223 | static rtx walk_alter_subreg PARAMS ((rtx *)); |
711d877c | 224 | static void output_asm_name PARAMS ((void)); |
998d7deb | 225 | static tree get_mem_expr_from_op PARAMS ((rtx, int *)); |
4f9b4029 | 226 | static void output_asm_operand_names PARAMS ((rtx *, int *, int)); |
711d877c | 227 | static void output_operand PARAMS ((rtx, int)); |
e9a25f70 | 228 | #ifdef LEAF_REGISTERS |
711d877c | 229 | static void leaf_renumber_regs PARAMS ((rtx)); |
e9a25f70 JL |
230 | #endif |
231 | #ifdef HAVE_cc0 | |
711d877c | 232 | static int alter_cond PARAMS ((rtx)); |
e9a25f70 | 233 | #endif |
ca3075bd | 234 | #ifndef ADDR_VEC_ALIGN |
711d877c | 235 | static int final_addr_vec_align PARAMS ((rtx)); |
ca3075bd | 236 | #endif |
7bdb32b9 | 237 | #ifdef HAVE_ATTR_length |
711d877c | 238 | static int align_fuzz PARAMS ((rtx, rtx, int, unsigned)); |
7bdb32b9 | 239 | #endif |
3cf2715d DE |
240 | \f |
241 | /* Initialize data in final at the beginning of a compilation. */ | |
242 | ||
243 | void | |
244 | init_final (filename) | |
6a651371 | 245 | const char *filename ATTRIBUTE_UNUSED; |
3cf2715d | 246 | { |
3cf2715d | 247 | app_on = 0; |
3cf2715d DE |
248 | final_sequence = 0; |
249 | ||
250 | #ifdef ASSEMBLER_DIALECT | |
251 | dialect_number = ASSEMBLER_DIALECT; | |
252 | #endif | |
253 | } | |
254 | ||
255 | /* Called at end of source file, | |
b7c9bf28 | 256 | to output the arc-profiling table for this entire compilation. */ |
3cf2715d DE |
257 | |
258 | void | |
259 | end_final (filename) | |
f5d927c0 | 260 | const char *filename; |
3cf2715d | 261 | { |
4d604303 | 262 | if (profile_arc_flag && profile_info.count_instrumented_edges) |
3cf2715d DE |
263 | { |
264 | char name[20]; | |
b7c9bf28 JH |
265 | tree string_type, string_cst; |
266 | tree structure_decl, structure_value, structure_pointer_type; | |
267 | tree field_decl, decl_chain, value_chain; | |
2292e8fc | 268 | tree sizeof_field_value, domain_type; |
b7c9bf28 JH |
269 | |
270 | /* Build types. */ | |
271 | string_type = build_pointer_type (char_type_node); | |
272 | ||
273 | /* Libgcc2 bb structure. */ | |
274 | structure_decl = make_node (RECORD_TYPE); | |
b7c9bf28 JH |
275 | structure_pointer_type = build_pointer_type (structure_decl); |
276 | ||
277 | /* Output the main header, of 7 words: | |
278 | 0: 1 if this file is initialized, else 0. | |
279 | 1: address of file name (LPBX1). | |
280 | 2: address of table of counts (LPBX2). | |
281 | 3: number of counts in the table. | |
282 | 4: always 0, libgcc2 uses this as a pointer to next ``struct bb'' | |
3cf2715d DE |
283 | |
284 | The following are GNU extensions: | |
285 | ||
b7c9bf28 JH |
286 | 5: Number of bytes in this header. |
287 | 6: address of table of function checksums (LPBX7). */ | |
3cf2715d | 288 | |
b7c9bf28 JH |
289 | /* The zero word. */ |
290 | decl_chain = | |
291 | build_decl (FIELD_DECL, get_identifier ("zero_word"), | |
292 | long_integer_type_node); | |
2292e8fc RH |
293 | value_chain = build_tree_list (decl_chain, |
294 | convert (long_integer_type_node, | |
295 | integer_zero_node)); | |
c8af3574 RH |
296 | |
297 | /* Address of filename. */ | |
b7c9bf28 | 298 | { |
2292e8fc RH |
299 | char *cwd, *da_filename; |
300 | int da_filename_len; | |
b7c9bf28 | 301 | |
2292e8fc RH |
302 | field_decl = |
303 | build_decl (FIELD_DECL, get_identifier ("filename"), string_type); | |
304 | TREE_CHAIN (field_decl) = decl_chain; | |
305 | decl_chain = field_decl; | |
306 | ||
307 | cwd = getpwd (); | |
308 | da_filename_len = strlen (filename) + strlen (cwd) + 4 + 1; | |
309 | da_filename = (char *) alloca (da_filename_len); | |
b7c9bf28 JH |
310 | strcpy (da_filename, cwd); |
311 | strcat (da_filename, "/"); | |
312 | strcat (da_filename, filename); | |
313 | strip_off_ending (da_filename, da_filename_len - 3); | |
314 | strcat (da_filename, ".da"); | |
2292e8fc RH |
315 | da_filename_len = strlen (da_filename); |
316 | string_cst = build_string (da_filename_len + 1, da_filename); | |
317 | domain_type = build_index_type (build_int_2 (da_filename_len, 0)); | |
318 | TREE_TYPE (string_cst) | |
319 | = build_array_type (char_type_node, domain_type); | |
b7c9bf28 JH |
320 | value_chain = tree_cons (field_decl, |
321 | build1 (ADDR_EXPR, string_type, string_cst), | |
322 | value_chain); | |
b7c9bf28 | 323 | } |
3cf2715d | 324 | |
b7c9bf28 JH |
325 | /* Table of counts. */ |
326 | { | |
327 | tree gcov_type_type = make_unsigned_type (GCOV_TYPE_SIZE); | |
328 | tree gcov_type_pointer_type = build_pointer_type (gcov_type_type); | |
2292e8fc RH |
329 | tree domain_tree |
330 | = build_index_type (build_int_2 (profile_info. | |
331 | count_instrumented_edges - 1, 0)); | |
332 | tree gcov_type_array_type | |
333 | = build_array_type (gcov_type_type, domain_tree); | |
334 | tree gcov_type_array_pointer_type | |
335 | = build_pointer_type (gcov_type_array_type); | |
b7c9bf28 JH |
336 | tree counts_table; |
337 | ||
2292e8fc RH |
338 | field_decl = |
339 | build_decl (FIELD_DECL, get_identifier ("counts"), | |
340 | gcov_type_pointer_type); | |
341 | TREE_CHAIN (field_decl) = decl_chain; | |
342 | decl_chain = field_decl; | |
b7c9bf28 JH |
343 | |
344 | /* No values. */ | |
2292e8fc RH |
345 | counts_table |
346 | = build (VAR_DECL, gcov_type_array_type, NULL_TREE, NULL_TREE); | |
b7c9bf28 JH |
347 | TREE_STATIC (counts_table) = 1; |
348 | ASM_GENERATE_INTERNAL_LABEL (name, "LPBX", 2); | |
349 | DECL_NAME (counts_table) = get_identifier (name); | |
350 | assemble_variable (counts_table, 0, 0, 0); | |
351 | ||
b7c9bf28 JH |
352 | value_chain = tree_cons (field_decl, |
353 | build1 (ADDR_EXPR, | |
354 | gcov_type_array_pointer_type, | |
355 | counts_table), value_chain); | |
b7c9bf28 | 356 | } |
3cf2715d | 357 | |
8456b95a | 358 | /* Count of the # of instrumented arcs. */ |
2292e8fc RH |
359 | field_decl |
360 | = build_decl (FIELD_DECL, get_identifier ("ncounts"), | |
361 | long_integer_type_node); | |
362 | TREE_CHAIN (field_decl) = decl_chain; | |
363 | decl_chain = field_decl; | |
364 | ||
b7c9bf28 JH |
365 | value_chain = tree_cons (field_decl, |
366 | convert (long_integer_type_node, | |
367 | build_int_2 (profile_info. | |
368 | count_instrumented_edges, | |
369 | 0)), value_chain); | |
2292e8fc RH |
370 | /* Pointer to the next bb. */ |
371 | field_decl | |
372 | = build_decl (FIELD_DECL, get_identifier ("next"), | |
373 | structure_pointer_type); | |
b7c9bf28 JH |
374 | TREE_CHAIN (field_decl) = decl_chain; |
375 | decl_chain = field_decl; | |
376 | ||
b7c9bf28 | 377 | value_chain = tree_cons (field_decl, null_pointer_node, value_chain); |
b7c9bf28 | 378 | |
2292e8fc RH |
379 | /* sizeof(struct bb). We'll set this after entire structure |
380 | is laid out. */ | |
381 | field_decl | |
382 | = build_decl (FIELD_DECL, get_identifier ("sizeof_bb"), | |
383 | long_integer_type_node); | |
b7c9bf28 JH |
384 | TREE_CHAIN (field_decl) = decl_chain; |
385 | decl_chain = field_decl; | |
386 | ||
2292e8fc RH |
387 | sizeof_field_value = tree_cons (field_decl, NULL, value_chain); |
388 | value_chain = sizeof_field_value; | |
389 | ||
b7c9bf28 JH |
390 | /* struct bb_function []. */ |
391 | { | |
392 | struct function_list *item; | |
393 | int num_nodes; | |
394 | tree checksum_field, arc_count_field, name_field; | |
395 | tree domain; | |
396 | tree array_value_chain = NULL_TREE; | |
397 | tree bb_fn_struct_type; | |
398 | tree bb_fn_struct_array_type; | |
399 | tree bb_fn_struct_array_pointer_type; | |
400 | tree bb_fn_struct_pointer_type; | |
401 | tree field_value, field_value_chain; | |
402 | ||
403 | bb_fn_struct_type = make_node (RECORD_TYPE); | |
b7c9bf28 JH |
404 | |
405 | checksum_field = build_decl (FIELD_DECL, get_identifier ("checksum"), | |
406 | long_integer_type_node); | |
2292e8fc RH |
407 | |
408 | arc_count_field | |
409 | = build_decl (FIELD_DECL, get_identifier ("arc_count"), | |
410 | integer_type_node); | |
b7c9bf28 | 411 | TREE_CHAIN (checksum_field) = arc_count_field; |
2292e8fc RH |
412 | |
413 | name_field | |
414 | = build_decl (FIELD_DECL, get_identifier ("name"), string_type); | |
b7c9bf28 JH |
415 | TREE_CHAIN (arc_count_field) = name_field; |
416 | ||
417 | TYPE_FIELDS (bb_fn_struct_type) = checksum_field; | |
418 | ||
419 | num_nodes = 0; | |
420 | ||
421 | for (item = functions_head; item != 0; item = item->next) | |
422 | num_nodes++; | |
423 | ||
424 | /* Note that the array contains a terminator, hence no - 1. */ | |
425 | domain = build_index_type (build_int_2 (num_nodes, 0)); | |
426 | ||
427 | bb_fn_struct_pointer_type = build_pointer_type (bb_fn_struct_type); | |
2292e8fc RH |
428 | bb_fn_struct_array_type |
429 | = build_array_type (bb_fn_struct_type, domain); | |
430 | bb_fn_struct_array_pointer_type | |
431 | = build_pointer_type (bb_fn_struct_array_type); | |
b7c9bf28 JH |
432 | |
433 | layout_type (bb_fn_struct_type); | |
434 | layout_type (bb_fn_struct_pointer_type); | |
435 | layout_type (bb_fn_struct_array_type); | |
436 | layout_type (bb_fn_struct_array_pointer_type); | |
437 | ||
438 | for (item = functions_head; item != 0; item = item->next) | |
439 | { | |
2292e8fc RH |
440 | size_t name_len; |
441 | ||
b7c9bf28 | 442 | /* create constructor for structure. */ |
2292e8fc RH |
443 | field_value_chain |
444 | = build_tree_list (checksum_field, | |
445 | convert (long_integer_type_node, | |
446 | build_int_2 (item->cfg_checksum, 0))); | |
447 | field_value_chain | |
448 | = tree_cons (arc_count_field, | |
449 | convert (integer_type_node, | |
450 | build_int_2 (item->count_edges, 0)), | |
451 | field_value_chain); | |
452 | ||
453 | name_len = strlen (item->name); | |
454 | string_cst = build_string (name_len + 1, item->name); | |
455 | domain_type = build_index_type (build_int_2 (name_len, 0)); | |
456 | TREE_TYPE (string_cst) | |
457 | = build_array_type (char_type_node, domain_type); | |
b7c9bf28 JH |
458 | field_value_chain = tree_cons (name_field, |
459 | build1 (ADDR_EXPR, string_type, | |
460 | string_cst), | |
461 | field_value_chain); | |
462 | ||
463 | /* Add to chain. */ | |
2292e8fc RH |
464 | array_value_chain |
465 | = tree_cons (NULL_TREE, build (CONSTRUCTOR, | |
466 | bb_fn_struct_type, NULL_TREE, | |
467 | nreverse (field_value_chain)), | |
468 | array_value_chain); | |
b7c9bf28 | 469 | } |
3cf2715d | 470 | |
b7c9bf28 JH |
471 | /* Add terminator. */ |
472 | field_value = build_tree_list (arc_count_field, | |
473 | convert (integer_type_node, | |
474 | build_int_2 (-1, 0))); | |
475 | ||
476 | array_value_chain = tree_cons (NULL_TREE, | |
477 | build (CONSTRUCTOR, bb_fn_struct_type, | |
478 | NULL_TREE, field_value), | |
479 | array_value_chain); | |
480 | ||
481 | ||
482 | /* Create constructor for array. */ | |
2292e8fc RH |
483 | field_decl |
484 | = build_decl (FIELD_DECL, get_identifier ("function_infos"), | |
485 | bb_fn_struct_pointer_type); | |
b7c9bf28 JH |
486 | value_chain = tree_cons (field_decl, |
487 | build1 (ADDR_EXPR, | |
488 | bb_fn_struct_array_pointer_type, | |
489 | build (CONSTRUCTOR, | |
490 | bb_fn_struct_array_type, | |
491 | NULL_TREE, | |
492 | nreverse | |
493 | (array_value_chain))), | |
494 | value_chain); | |
495 | TREE_CHAIN (field_decl) = decl_chain; | |
496 | decl_chain = field_decl; | |
497 | } | |
3cf2715d | 498 | |
b7c9bf28 JH |
499 | /* Finish structure. */ |
500 | TYPE_FIELDS (structure_decl) = nreverse (decl_chain); | |
501 | layout_type (structure_decl); | |
3cf2715d | 502 | |
2292e8fc RH |
503 | structure_value |
504 | = build (VAR_DECL, structure_decl, NULL_TREE, NULL_TREE); | |
505 | DECL_INITIAL (structure_value) | |
506 | = build (CONSTRUCTOR, structure_decl, NULL_TREE, | |
507 | nreverse (value_chain)); | |
b7c9bf28 JH |
508 | TREE_STATIC (structure_value) = 1; |
509 | ASM_GENERATE_INTERNAL_LABEL (name, "LPBX", 0); | |
510 | DECL_NAME (structure_value) = get_identifier (name); | |
3cf2715d | 511 | |
dd3f0101 | 512 | /* Size of this structure. */ |
2292e8fc RH |
513 | TREE_VALUE (sizeof_field_value) |
514 | = convert (long_integer_type_node, | |
515 | build_int_2 (int_size_in_bytes (structure_decl), 0)); | |
3cf2715d | 516 | |
b7c9bf28 JH |
517 | /* Build structure. */ |
518 | assemble_variable (structure_value, 0, 0, 0); | |
3cf2715d DE |
519 | } |
520 | } | |
521 | ||
08c148a8 | 522 | /* Default target function prologue and epilogue assembler output. |
b9f22704 | 523 | |
08c148a8 NB |
524 | If not overridden for epilogue code, then the function body itself |
525 | contains return instructions wherever needed. */ | |
526 | void | |
527 | default_function_pro_epilogue (file, size) | |
528 | FILE *file ATTRIBUTE_UNUSED; | |
529 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; | |
530 | { | |
531 | } | |
532 | ||
b4c25db2 NB |
533 | /* Default target hook that outputs nothing to a stream. */ |
534 | void | |
535 | no_asm_to_stream (file) | |
536 | FILE *file ATTRIBUTE_UNUSED; | |
537 | { | |
538 | } | |
539 | ||
3cf2715d DE |
540 | /* Enable APP processing of subsequent output. |
541 | Used before the output from an `asm' statement. */ | |
542 | ||
543 | void | |
544 | app_enable () | |
545 | { | |
546 | if (! app_on) | |
547 | { | |
51723711 | 548 | fputs (ASM_APP_ON, asm_out_file); |
3cf2715d DE |
549 | app_on = 1; |
550 | } | |
551 | } | |
552 | ||
553 | /* Disable APP processing of subsequent output. | |
554 | Called from varasm.c before most kinds of output. */ | |
555 | ||
556 | void | |
557 | app_disable () | |
558 | { | |
559 | if (app_on) | |
560 | { | |
51723711 | 561 | fputs (ASM_APP_OFF, asm_out_file); |
3cf2715d DE |
562 | app_on = 0; |
563 | } | |
564 | } | |
565 | \f | |
f5d927c0 | 566 | /* Return the number of slots filled in the current |
3cf2715d DE |
567 | delayed branch sequence (we don't count the insn needing the |
568 | delay slot). Zero if not in a delayed branch sequence. */ | |
569 | ||
570 | #ifdef DELAY_SLOTS | |
571 | int | |
572 | dbr_sequence_length () | |
573 | { | |
574 | if (final_sequence != 0) | |
575 | return XVECLEN (final_sequence, 0) - 1; | |
576 | else | |
577 | return 0; | |
578 | } | |
579 | #endif | |
580 | \f | |
581 | /* The next two pages contain routines used to compute the length of an insn | |
582 | and to shorten branches. */ | |
583 | ||
584 | /* Arrays for insn lengths, and addresses. The latter is referenced by | |
585 | `insn_current_length'. */ | |
586 | ||
addd7df6 | 587 | static int *insn_lengths; |
9d98a694 | 588 | |
9d98a694 | 589 | varray_type insn_addresses_; |
3cf2715d | 590 | |
ea3cbda5 R |
591 | /* Max uid for which the above arrays are valid. */ |
592 | static int insn_lengths_max_uid; | |
593 | ||
3cf2715d DE |
594 | /* Address of insn being processed. Used by `insn_current_length'. */ |
595 | int insn_current_address; | |
596 | ||
fc470718 R |
597 | /* Address of insn being processed in previous iteration. */ |
598 | int insn_last_address; | |
599 | ||
d6a7951f | 600 | /* known invariant alignment of insn being processed. */ |
fc470718 R |
601 | int insn_current_align; |
602 | ||
95707627 R |
603 | /* After shorten_branches, for any insn, uid_align[INSN_UID (insn)] |
604 | gives the next following alignment insn that increases the known | |
605 | alignment, or NULL_RTX if there is no such insn. | |
606 | For any alignment obtained this way, we can again index uid_align with | |
607 | its uid to obtain the next following align that in turn increases the | |
608 | alignment, till we reach NULL_RTX; the sequence obtained this way | |
609 | for each insn we'll call the alignment chain of this insn in the following | |
610 | comments. */ | |
611 | ||
f5d927c0 KH |
612 | struct label_alignment |
613 | { | |
9e423e6d JW |
614 | short alignment; |
615 | short max_skip; | |
616 | }; | |
617 | ||
618 | static rtx *uid_align; | |
619 | static int *uid_shuid; | |
620 | static struct label_alignment *label_align; | |
95707627 | 621 | |
3cf2715d DE |
622 | /* Indicate that branch shortening hasn't yet been done. */ |
623 | ||
624 | void | |
625 | init_insn_lengths () | |
626 | { | |
95707627 R |
627 | if (uid_shuid) |
628 | { | |
629 | free (uid_shuid); | |
630 | uid_shuid = 0; | |
631 | } | |
632 | if (insn_lengths) | |
633 | { | |
634 | free (insn_lengths); | |
635 | insn_lengths = 0; | |
ea3cbda5 | 636 | insn_lengths_max_uid = 0; |
95707627 | 637 | } |
9d98a694 AO |
638 | #ifdef HAVE_ATTR_length |
639 | INSN_ADDRESSES_FREE (); | |
640 | #endif | |
95707627 R |
641 | if (uid_align) |
642 | { | |
643 | free (uid_align); | |
644 | uid_align = 0; | |
645 | } | |
3cf2715d DE |
646 | } |
647 | ||
648 | /* Obtain the current length of an insn. If branch shortening has been done, | |
649 | get its actual length. Otherwise, get its maximum length. */ | |
650 | ||
651 | int | |
652 | get_attr_length (insn) | |
7bdb32b9 | 653 | rtx insn ATTRIBUTE_UNUSED; |
3cf2715d DE |
654 | { |
655 | #ifdef HAVE_ATTR_length | |
656 | rtx body; | |
657 | int i; | |
658 | int length = 0; | |
659 | ||
ea3cbda5 | 660 | if (insn_lengths_max_uid > INSN_UID (insn)) |
3cf2715d DE |
661 | return insn_lengths[INSN_UID (insn)]; |
662 | else | |
663 | switch (GET_CODE (insn)) | |
664 | { | |
665 | case NOTE: | |
666 | case BARRIER: | |
667 | case CODE_LABEL: | |
668 | return 0; | |
669 | ||
670 | case CALL_INSN: | |
671 | length = insn_default_length (insn); | |
672 | break; | |
673 | ||
674 | case JUMP_INSN: | |
675 | body = PATTERN (insn); | |
dd3f0101 | 676 | if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) |
3cf2715d | 677 | { |
fc470718 R |
678 | /* Alignment is machine-dependent and should be handled by |
679 | ADDR_VEC_ALIGN. */ | |
3cf2715d DE |
680 | } |
681 | else | |
682 | length = insn_default_length (insn); | |
683 | break; | |
684 | ||
685 | case INSN: | |
686 | body = PATTERN (insn); | |
687 | if (GET_CODE (body) == USE || GET_CODE (body) == CLOBBER) | |
688 | return 0; | |
689 | ||
690 | else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0) | |
691 | length = asm_insn_count (body) * insn_default_length (insn); | |
692 | else if (GET_CODE (body) == SEQUENCE) | |
693 | for (i = 0; i < XVECLEN (body, 0); i++) | |
694 | length += get_attr_length (XVECEXP (body, 0, i)); | |
695 | else | |
696 | length = insn_default_length (insn); | |
e9a25f70 JL |
697 | break; |
698 | ||
699 | default: | |
700 | break; | |
3cf2715d DE |
701 | } |
702 | ||
703 | #ifdef ADJUST_INSN_LENGTH | |
704 | ADJUST_INSN_LENGTH (insn, length); | |
705 | #endif | |
706 | return length; | |
707 | #else /* not HAVE_ATTR_length */ | |
708 | return 0; | |
709 | #endif /* not HAVE_ATTR_length */ | |
710 | } | |
711 | \f | |
fc470718 R |
712 | /* Code to handle alignment inside shorten_branches. */ |
713 | ||
714 | /* Here is an explanation how the algorithm in align_fuzz can give | |
715 | proper results: | |
716 | ||
717 | Call a sequence of instructions beginning with alignment point X | |
718 | and continuing until the next alignment point `block X'. When `X' | |
f5d927c0 | 719 | is used in an expression, it means the alignment value of the |
fc470718 | 720 | alignment point. |
f5d927c0 | 721 | |
fc470718 R |
722 | Call the distance between the start of the first insn of block X, and |
723 | the end of the last insn of block X `IX', for the `inner size of X'. | |
724 | This is clearly the sum of the instruction lengths. | |
f5d927c0 | 725 | |
fc470718 R |
726 | Likewise with the next alignment-delimited block following X, which we |
727 | shall call block Y. | |
f5d927c0 | 728 | |
fc470718 R |
729 | Call the distance between the start of the first insn of block X, and |
730 | the start of the first insn of block Y `OX', for the `outer size of X'. | |
f5d927c0 | 731 | |
fc470718 | 732 | The estimated padding is then OX - IX. |
f5d927c0 | 733 | |
fc470718 | 734 | OX can be safely estimated as |
f5d927c0 | 735 | |
fc470718 R |
736 | if (X >= Y) |
737 | OX = round_up(IX, Y) | |
738 | else | |
739 | OX = round_up(IX, X) + Y - X | |
f5d927c0 | 740 | |
fc470718 R |
741 | Clearly est(IX) >= real(IX), because that only depends on the |
742 | instruction lengths, and those being overestimated is a given. | |
f5d927c0 | 743 | |
fc470718 R |
744 | Clearly round_up(foo, Z) >= round_up(bar, Z) if foo >= bar, so |
745 | we needn't worry about that when thinking about OX. | |
f5d927c0 | 746 | |
fc470718 R |
747 | When X >= Y, the alignment provided by Y adds no uncertainty factor |
748 | for branch ranges starting before X, so we can just round what we have. | |
749 | But when X < Y, we don't know anything about the, so to speak, | |
750 | `middle bits', so we have to assume the worst when aligning up from an | |
751 | address mod X to one mod Y, which is Y - X. */ | |
752 | ||
753 | #ifndef LABEL_ALIGN | |
efa3896a | 754 | #define LABEL_ALIGN(LABEL) align_labels_log |
fc470718 R |
755 | #endif |
756 | ||
9e423e6d | 757 | #ifndef LABEL_ALIGN_MAX_SKIP |
2cca7283 | 758 | #define LABEL_ALIGN_MAX_SKIP align_labels_max_skip |
9e423e6d JW |
759 | #endif |
760 | ||
fc470718 | 761 | #ifndef LOOP_ALIGN |
efa3896a | 762 | #define LOOP_ALIGN(LABEL) align_loops_log |
fc470718 R |
763 | #endif |
764 | ||
9e423e6d | 765 | #ifndef LOOP_ALIGN_MAX_SKIP |
2cca7283 | 766 | #define LOOP_ALIGN_MAX_SKIP align_loops_max_skip |
9e423e6d JW |
767 | #endif |
768 | ||
fc470718 | 769 | #ifndef LABEL_ALIGN_AFTER_BARRIER |
340f7e7c | 770 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0 |
fc470718 R |
771 | #endif |
772 | ||
9e423e6d | 773 | #ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP |
247a370b JH |
774 | #define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0 |
775 | #endif | |
776 | ||
777 | #ifndef JUMP_ALIGN | |
778 | #define JUMP_ALIGN(LABEL) align_jumps_log | |
779 | #endif | |
780 | ||
781 | #ifndef JUMP_ALIGN_MAX_SKIP | |
2cca7283 | 782 | #define JUMP_ALIGN_MAX_SKIP align_jumps_max_skip |
9e423e6d JW |
783 | #endif |
784 | ||
fc470718 | 785 | #ifndef ADDR_VEC_ALIGN |
ca3075bd | 786 | static int |
fc470718 R |
787 | final_addr_vec_align (addr_vec) |
788 | rtx addr_vec; | |
789 | { | |
2a841588 | 790 | int align = GET_MODE_SIZE (GET_MODE (PATTERN (addr_vec))); |
fc470718 R |
791 | |
792 | if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT) | |
793 | align = BIGGEST_ALIGNMENT / BITS_PER_UNIT; | |
2a841588 | 794 | return exact_log2 (align); |
fc470718 R |
795 | |
796 | } | |
f5d927c0 | 797 | |
fc470718 R |
798 | #define ADDR_VEC_ALIGN(ADDR_VEC) final_addr_vec_align (ADDR_VEC) |
799 | #endif | |
800 | ||
801 | #ifndef INSN_LENGTH_ALIGNMENT | |
802 | #define INSN_LENGTH_ALIGNMENT(INSN) length_unit_log | |
803 | #endif | |
804 | ||
fc470718 R |
805 | #define INSN_SHUID(INSN) (uid_shuid[INSN_UID (INSN)]) |
806 | ||
de7987a6 | 807 | static int min_labelno, max_labelno; |
fc470718 R |
808 | |
809 | #define LABEL_TO_ALIGNMENT(LABEL) \ | |
9e423e6d JW |
810 | (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].alignment) |
811 | ||
812 | #define LABEL_TO_MAX_SKIP(LABEL) \ | |
813 | (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].max_skip) | |
fc470718 R |
814 | |
815 | /* For the benefit of port specific code do this also as a function. */ | |
f5d927c0 | 816 | |
fc470718 R |
817 | int |
818 | label_to_alignment (label) | |
819 | rtx label; | |
820 | { | |
821 | return LABEL_TO_ALIGNMENT (label); | |
822 | } | |
823 | ||
824 | #ifdef HAVE_ATTR_length | |
825 | /* The differences in addresses | |
826 | between a branch and its target might grow or shrink depending on | |
827 | the alignment the start insn of the range (the branch for a forward | |
828 | branch or the label for a backward branch) starts out on; if these | |
829 | differences are used naively, they can even oscillate infinitely. | |
830 | We therefore want to compute a 'worst case' address difference that | |
831 | is independent of the alignment the start insn of the range end | |
832 | up on, and that is at least as large as the actual difference. | |
833 | The function align_fuzz calculates the amount we have to add to the | |
834 | naively computed difference, by traversing the part of the alignment | |
835 | chain of the start insn of the range that is in front of the end insn | |
836 | of the range, and considering for each alignment the maximum amount | |
837 | that it might contribute to a size increase. | |
838 | ||
839 | For casesi tables, we also want to know worst case minimum amounts of | |
840 | address difference, in case a machine description wants to introduce | |
841 | some common offset that is added to all offsets in a table. | |
d6a7951f | 842 | For this purpose, align_fuzz with a growth argument of 0 computes the |
fc470718 R |
843 | appropriate adjustment. */ |
844 | ||
fc470718 R |
845 | /* Compute the maximum delta by which the difference of the addresses of |
846 | START and END might grow / shrink due to a different address for start | |
847 | which changes the size of alignment insns between START and END. | |
848 | KNOWN_ALIGN_LOG is the alignment known for START. | |
849 | GROWTH should be ~0 if the objective is to compute potential code size | |
850 | increase, and 0 if the objective is to compute potential shrink. | |
851 | The return value is undefined for any other value of GROWTH. */ | |
f5d927c0 | 852 | |
ca3075bd | 853 | static int |
687d0ab6 | 854 | align_fuzz (start, end, known_align_log, growth) |
fc470718 R |
855 | rtx start, end; |
856 | int known_align_log; | |
857 | unsigned growth; | |
858 | { | |
859 | int uid = INSN_UID (start); | |
860 | rtx align_label; | |
861 | int known_align = 1 << known_align_log; | |
862 | int end_shuid = INSN_SHUID (end); | |
863 | int fuzz = 0; | |
864 | ||
865 | for (align_label = uid_align[uid]; align_label; align_label = uid_align[uid]) | |
866 | { | |
867 | int align_addr, new_align; | |
868 | ||
869 | uid = INSN_UID (align_label); | |
9d98a694 | 870 | align_addr = INSN_ADDRESSES (uid) - insn_lengths[uid]; |
fc470718 R |
871 | if (uid_shuid[uid] > end_shuid) |
872 | break; | |
873 | known_align_log = LABEL_TO_ALIGNMENT (align_label); | |
874 | new_align = 1 << known_align_log; | |
875 | if (new_align < known_align) | |
876 | continue; | |
877 | fuzz += (-align_addr ^ growth) & (new_align - known_align); | |
878 | known_align = new_align; | |
879 | } | |
880 | return fuzz; | |
881 | } | |
882 | ||
883 | /* Compute a worst-case reference address of a branch so that it | |
884 | can be safely used in the presence of aligned labels. Since the | |
885 | size of the branch itself is unknown, the size of the branch is | |
886 | not included in the range. I.e. for a forward branch, the reference | |
887 | address is the end address of the branch as known from the previous | |
888 | branch shortening pass, minus a value to account for possible size | |
889 | increase due to alignment. For a backward branch, it is the start | |
890 | address of the branch as known from the current pass, plus a value | |
891 | to account for possible size increase due to alignment. | |
892 | NB.: Therefore, the maximum offset allowed for backward branches needs | |
893 | to exclude the branch size. */ | |
f5d927c0 | 894 | |
fc470718 R |
895 | int |
896 | insn_current_reference_address (branch) | |
897 | rtx branch; | |
898 | { | |
5527bf14 RH |
899 | rtx dest, seq; |
900 | int seq_uid; | |
901 | ||
902 | if (! INSN_ADDRESSES_SET_P ()) | |
903 | return 0; | |
904 | ||
905 | seq = NEXT_INSN (PREV_INSN (branch)); | |
906 | seq_uid = INSN_UID (seq); | |
fc470718 R |
907 | if (GET_CODE (branch) != JUMP_INSN) |
908 | /* This can happen for example on the PA; the objective is to know the | |
909 | offset to address something in front of the start of the function. | |
910 | Thus, we can treat it like a backward branch. | |
911 | We assume here that FUNCTION_BOUNDARY / BITS_PER_UNIT is larger than | |
912 | any alignment we'd encounter, so we skip the call to align_fuzz. */ | |
913 | return insn_current_address; | |
914 | dest = JUMP_LABEL (branch); | |
5527bf14 | 915 | |
b9f22704 | 916 | /* BRANCH has no proper alignment chain set, so use SEQ. |
afc6898e BS |
917 | BRANCH also has no INSN_SHUID. */ |
918 | if (INSN_SHUID (seq) < INSN_SHUID (dest)) | |
fc470718 | 919 | { |
f5d927c0 | 920 | /* Forward branch. */ |
fc470718 | 921 | return (insn_last_address + insn_lengths[seq_uid] |
26024475 | 922 | - align_fuzz (seq, dest, length_unit_log, ~0)); |
fc470718 R |
923 | } |
924 | else | |
925 | { | |
f5d927c0 | 926 | /* Backward branch. */ |
fc470718 | 927 | return (insn_current_address |
923f7cf9 | 928 | + align_fuzz (dest, seq, length_unit_log, ~0)); |
fc470718 R |
929 | } |
930 | } | |
931 | #endif /* HAVE_ATTR_length */ | |
932 | \f | |
247a370b JH |
933 | void |
934 | compute_alignments () | |
935 | { | |
247a370b | 936 | int log, max_skip, max_log; |
e0082a72 | 937 | basic_block bb; |
247a370b JH |
938 | |
939 | if (label_align) | |
940 | { | |
941 | free (label_align); | |
942 | label_align = 0; | |
943 | } | |
944 | ||
945 | max_labelno = max_label_num (); | |
946 | min_labelno = get_first_label_num (); | |
947 | label_align = (struct label_alignment *) | |
948 | xcalloc (max_labelno - min_labelno + 1, sizeof (struct label_alignment)); | |
949 | ||
950 | /* If not optimizing or optimizing for size, don't assign any alignments. */ | |
ba712955 | 951 | if (! optimize || optimize_size) |
247a370b JH |
952 | return; |
953 | ||
e0082a72 | 954 | FOR_EACH_BB (bb) |
247a370b | 955 | { |
247a370b JH |
956 | rtx label = bb->head; |
957 | int fallthru_frequency = 0, branch_frequency = 0, has_fallthru = 0; | |
958 | edge e; | |
959 | ||
960 | if (GET_CODE (label) != CODE_LABEL) | |
961 | continue; | |
962 | max_log = LABEL_ALIGN (label); | |
963 | max_skip = LABEL_ALIGN_MAX_SKIP; | |
964 | ||
965 | for (e = bb->pred; e; e = e->pred_next) | |
966 | { | |
967 | if (e->flags & EDGE_FALLTHRU) | |
968 | has_fallthru = 1, fallthru_frequency += EDGE_FREQUENCY (e); | |
969 | else | |
970 | branch_frequency += EDGE_FREQUENCY (e); | |
971 | } | |
972 | ||
f63d1bf7 | 973 | /* There are two purposes to align block with no fallthru incoming edge: |
247a370b | 974 | 1) to avoid fetch stalls when branch destination is near cache boundary |
d6a7951f | 975 | 2) to improve cache efficiency in case the previous block is not executed |
247a370b JH |
976 | (so it does not need to be in the cache). |
977 | ||
978 | We to catch first case, we align frequently executed blocks. | |
979 | To catch the second, we align blocks that are executed more frequently | |
eaec9b3d | 980 | than the predecessor and the predecessor is likely to not be executed |
247a370b JH |
981 | when function is called. */ |
982 | ||
983 | if (!has_fallthru | |
984 | && (branch_frequency > BB_FREQ_MAX / 10 | |
f6366fc7 ZD |
985 | || (bb->frequency > bb->prev_bb->frequency * 10 |
986 | && (bb->prev_bb->frequency | |
247a370b JH |
987 | <= ENTRY_BLOCK_PTR->frequency / 2)))) |
988 | { | |
989 | log = JUMP_ALIGN (label); | |
990 | if (max_log < log) | |
991 | { | |
992 | max_log = log; | |
993 | max_skip = JUMP_ALIGN_MAX_SKIP; | |
994 | } | |
995 | } | |
996 | /* In case block is frequent and reached mostly by non-fallthru edge, | |
997 | align it. It is most likely an first block of loop. */ | |
998 | if (has_fallthru | |
999 | && branch_frequency + fallthru_frequency > BB_FREQ_MAX / 10 | |
1000 | && branch_frequency > fallthru_frequency * 5) | |
1001 | { | |
1002 | log = LOOP_ALIGN (label); | |
1003 | if (max_log < log) | |
1004 | { | |
1005 | max_log = log; | |
1006 | max_skip = LOOP_ALIGN_MAX_SKIP; | |
1007 | } | |
1008 | } | |
1009 | LABEL_TO_ALIGNMENT (label) = max_log; | |
1010 | LABEL_TO_MAX_SKIP (label) = max_skip; | |
1011 | } | |
1012 | } | |
1013 | \f | |
3cf2715d DE |
1014 | /* Make a pass over all insns and compute their actual lengths by shortening |
1015 | any branches of variable length if possible. */ | |
1016 | ||
1017 | /* Give a default value for the lowest address in a function. */ | |
1018 | ||
1019 | #ifndef FIRST_INSN_ADDRESS | |
1020 | #define FIRST_INSN_ADDRESS 0 | |
1021 | #endif | |
1022 | ||
fc470718 R |
1023 | /* shorten_branches might be called multiple times: for example, the SH |
1024 | port splits out-of-range conditional branches in MACHINE_DEPENDENT_REORG. | |
1025 | In order to do this, it needs proper length information, which it obtains | |
1026 | by calling shorten_branches. This cannot be collapsed with | |
d6a7951f | 1027 | shorten_branches itself into a single pass unless we also want to integrate |
fc470718 R |
1028 | reorg.c, since the branch splitting exposes new instructions with delay |
1029 | slots. */ | |
1030 | ||
3cf2715d DE |
1031 | void |
1032 | shorten_branches (first) | |
7bdb32b9 | 1033 | rtx first ATTRIBUTE_UNUSED; |
3cf2715d | 1034 | { |
3cf2715d | 1035 | rtx insn; |
fc470718 R |
1036 | int max_uid; |
1037 | int i; | |
fc470718 | 1038 | int max_log; |
9e423e6d | 1039 | int max_skip; |
fc470718 R |
1040 | #ifdef HAVE_ATTR_length |
1041 | #define MAX_CODE_ALIGN 16 | |
1042 | rtx seq; | |
3cf2715d | 1043 | int something_changed = 1; |
3cf2715d DE |
1044 | char *varying_length; |
1045 | rtx body; | |
1046 | int uid; | |
fc470718 | 1047 | rtx align_tab[MAX_CODE_ALIGN]; |
3cf2715d | 1048 | |
fc470718 | 1049 | #endif |
3d14e82f | 1050 | |
3446405d JH |
1051 | /* Compute maximum UID and allocate label_align / uid_shuid. */ |
1052 | max_uid = get_max_uid (); | |
d9b6874b | 1053 | |
3446405d | 1054 | uid_shuid = (int *) xmalloc (max_uid * sizeof *uid_shuid); |
25e22dc0 | 1055 | |
247a370b JH |
1056 | if (max_labelno != max_label_num ()) |
1057 | { | |
1058 | int old = max_labelno; | |
1059 | int n_labels; | |
1060 | int n_old_labels; | |
1061 | ||
1062 | max_labelno = max_label_num (); | |
1063 | ||
1064 | n_labels = max_labelno - min_labelno + 1; | |
1065 | n_old_labels = old - min_labelno + 1; | |
1066 | ||
1067 | label_align = (struct label_alignment *) xrealloc | |
1068 | (label_align, n_labels * sizeof (struct label_alignment)); | |
1069 | ||
1070 | /* Range of labels grows monotonically in the function. Abort here | |
1071 | means that the initialization of array got lost. */ | |
1072 | if (n_old_labels > n_labels) | |
1073 | abort (); | |
1074 | ||
1075 | memset (label_align + n_old_labels, 0, | |
1076 | (n_labels - n_old_labels) * sizeof (struct label_alignment)); | |
1077 | } | |
1078 | ||
fc470718 R |
1079 | /* Initialize label_align and set up uid_shuid to be strictly |
1080 | monotonically rising with insn order. */ | |
e2faec75 R |
1081 | /* We use max_log here to keep track of the maximum alignment we want to |
1082 | impose on the next CODE_LABEL (or the current one if we are processing | |
1083 | the CODE_LABEL itself). */ | |
f5d927c0 | 1084 | |
9e423e6d JW |
1085 | max_log = 0; |
1086 | max_skip = 0; | |
1087 | ||
1088 | for (insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn)) | |
fc470718 R |
1089 | { |
1090 | int log; | |
1091 | ||
1092 | INSN_SHUID (insn) = i++; | |
2c3c49de | 1093 | if (INSN_P (insn)) |
e2faec75 R |
1094 | { |
1095 | /* reorg might make the first insn of a loop being run once only, | |
1096 | and delete the label in front of it. Then we want to apply | |
1097 | the loop alignment to the new label created by reorg, which | |
1098 | is separated by the former loop start insn from the | |
1099 | NOTE_INSN_LOOP_BEG. */ | |
1100 | } | |
fc470718 R |
1101 | else if (GET_CODE (insn) == CODE_LABEL) |
1102 | { | |
1103 | rtx next; | |
ff81832f | 1104 | |
247a370b JH |
1105 | /* Merge in alignments computed by compute_alignments. */ |
1106 | log = LABEL_TO_ALIGNMENT (insn); | |
1107 | if (max_log < log) | |
1108 | { | |
1109 | max_log = log; | |
1110 | max_skip = LABEL_TO_MAX_SKIP (insn); | |
1111 | } | |
fc470718 R |
1112 | |
1113 | log = LABEL_ALIGN (insn); | |
1114 | if (max_log < log) | |
9e423e6d JW |
1115 | { |
1116 | max_log = log; | |
1117 | max_skip = LABEL_ALIGN_MAX_SKIP; | |
1118 | } | |
fc470718 | 1119 | next = NEXT_INSN (insn); |
75197b37 BS |
1120 | /* ADDR_VECs only take room if read-only data goes into the text |
1121 | section. */ | |
d48bc59a | 1122 | if (JUMP_TABLES_IN_TEXT_SECTION || !HAVE_READONLY_DATA_SECTION) |
75197b37 BS |
1123 | if (next && GET_CODE (next) == JUMP_INSN) |
1124 | { | |
1125 | rtx nextbody = PATTERN (next); | |
1126 | if (GET_CODE (nextbody) == ADDR_VEC | |
1127 | || GET_CODE (nextbody) == ADDR_DIFF_VEC) | |
1128 | { | |
1129 | log = ADDR_VEC_ALIGN (next); | |
1130 | if (max_log < log) | |
1131 | { | |
1132 | max_log = log; | |
1133 | max_skip = LABEL_ALIGN_MAX_SKIP; | |
1134 | } | |
1135 | } | |
1136 | } | |
fc470718 | 1137 | LABEL_TO_ALIGNMENT (insn) = max_log; |
9e423e6d | 1138 | LABEL_TO_MAX_SKIP (insn) = max_skip; |
fc470718 | 1139 | max_log = 0; |
9e423e6d | 1140 | max_skip = 0; |
fc470718 R |
1141 | } |
1142 | else if (GET_CODE (insn) == BARRIER) | |
1143 | { | |
1144 | rtx label; | |
1145 | ||
2c3c49de | 1146 | for (label = insn; label && ! INSN_P (label); |
fc470718 R |
1147 | label = NEXT_INSN (label)) |
1148 | if (GET_CODE (label) == CODE_LABEL) | |
1149 | { | |
1150 | log = LABEL_ALIGN_AFTER_BARRIER (insn); | |
1151 | if (max_log < log) | |
9e423e6d JW |
1152 | { |
1153 | max_log = log; | |
1154 | max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP; | |
1155 | } | |
fc470718 R |
1156 | break; |
1157 | } | |
1158 | } | |
fc470718 R |
1159 | } |
1160 | #ifdef HAVE_ATTR_length | |
1161 | ||
1162 | /* Allocate the rest of the arrays. */ | |
addd7df6 | 1163 | insn_lengths = (int *) xmalloc (max_uid * sizeof (*insn_lengths)); |
ea3cbda5 | 1164 | insn_lengths_max_uid = max_uid; |
af035616 R |
1165 | /* Syntax errors can lead to labels being outside of the main insn stream. |
1166 | Initialize insn_addresses, so that we get reproducible results. */ | |
9d98a694 | 1167 | INSN_ADDRESSES_ALLOC (max_uid); |
fc470718 | 1168 | |
3de90026 | 1169 | varying_length = (char *) xcalloc (max_uid, sizeof (char)); |
fc470718 R |
1170 | |
1171 | /* Initialize uid_align. We scan instructions | |
1172 | from end to start, and keep in align_tab[n] the last seen insn | |
1173 | that does an alignment of at least n+1, i.e. the successor | |
1174 | in the alignment chain for an insn that does / has a known | |
1175 | alignment of n. */ | |
3de90026 | 1176 | uid_align = (rtx *) xcalloc (max_uid, sizeof *uid_align); |
fc470718 | 1177 | |
f5d927c0 | 1178 | for (i = MAX_CODE_ALIGN; --i >= 0;) |
fc470718 R |
1179 | align_tab[i] = NULL_RTX; |
1180 | seq = get_last_insn (); | |
33f7f353 | 1181 | for (; seq; seq = PREV_INSN (seq)) |
fc470718 R |
1182 | { |
1183 | int uid = INSN_UID (seq); | |
1184 | int log; | |
fc470718 R |
1185 | log = (GET_CODE (seq) == CODE_LABEL ? LABEL_TO_ALIGNMENT (seq) : 0); |
1186 | uid_align[uid] = align_tab[0]; | |
fc470718 R |
1187 | if (log) |
1188 | { | |
1189 | /* Found an alignment label. */ | |
1190 | uid_align[uid] = align_tab[log]; | |
1191 | for (i = log - 1; i >= 0; i--) | |
1192 | align_tab[i] = seq; | |
1193 | } | |
33f7f353 JR |
1194 | } |
1195 | #ifdef CASE_VECTOR_SHORTEN_MODE | |
1196 | if (optimize) | |
1197 | { | |
1198 | /* Look for ADDR_DIFF_VECs, and initialize their minimum and maximum | |
1199 | label fields. */ | |
1200 | ||
1201 | int min_shuid = INSN_SHUID (get_insns ()) - 1; | |
1202 | int max_shuid = INSN_SHUID (get_last_insn ()) + 1; | |
1203 | int rel; | |
1204 | ||
1205 | for (insn = first; insn != 0; insn = NEXT_INSN (insn)) | |
fc470718 | 1206 | { |
33f7f353 JR |
1207 | rtx min_lab = NULL_RTX, max_lab = NULL_RTX, pat; |
1208 | int len, i, min, max, insn_shuid; | |
1209 | int min_align; | |
1210 | addr_diff_vec_flags flags; | |
1211 | ||
1212 | if (GET_CODE (insn) != JUMP_INSN | |
1213 | || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
1214 | continue; | |
1215 | pat = PATTERN (insn); | |
1216 | len = XVECLEN (pat, 1); | |
1217 | if (len <= 0) | |
1218 | abort (); | |
1219 | min_align = MAX_CODE_ALIGN; | |
1220 | for (min = max_shuid, max = min_shuid, i = len - 1; i >= 0; i--) | |
1221 | { | |
1222 | rtx lab = XEXP (XVECEXP (pat, 1, i), 0); | |
1223 | int shuid = INSN_SHUID (lab); | |
1224 | if (shuid < min) | |
1225 | { | |
1226 | min = shuid; | |
1227 | min_lab = lab; | |
1228 | } | |
1229 | if (shuid > max) | |
1230 | { | |
1231 | max = shuid; | |
1232 | max_lab = lab; | |
1233 | } | |
1234 | if (min_align > LABEL_TO_ALIGNMENT (lab)) | |
1235 | min_align = LABEL_TO_ALIGNMENT (lab); | |
1236 | } | |
1237 | XEXP (pat, 2) = gen_rtx_LABEL_REF (VOIDmode, min_lab); | |
1238 | XEXP (pat, 3) = gen_rtx_LABEL_REF (VOIDmode, max_lab); | |
1239 | insn_shuid = INSN_SHUID (insn); | |
1240 | rel = INSN_SHUID (XEXP (XEXP (pat, 0), 0)); | |
1241 | flags.min_align = min_align; | |
1242 | flags.base_after_vec = rel > insn_shuid; | |
1243 | flags.min_after_vec = min > insn_shuid; | |
1244 | flags.max_after_vec = max > insn_shuid; | |
1245 | flags.min_after_base = min > rel; | |
1246 | flags.max_after_base = max > rel; | |
1247 | ADDR_DIFF_VEC_FLAGS (pat) = flags; | |
fc470718 R |
1248 | } |
1249 | } | |
33f7f353 | 1250 | #endif /* CASE_VECTOR_SHORTEN_MODE */ |
3cf2715d | 1251 | |
3cf2715d DE |
1252 | /* Compute initial lengths, addresses, and varying flags for each insn. */ |
1253 | for (insn_current_address = FIRST_INSN_ADDRESS, insn = first; | |
1254 | insn != 0; | |
1255 | insn_current_address += insn_lengths[uid], insn = NEXT_INSN (insn)) | |
1256 | { | |
1257 | uid = INSN_UID (insn); | |
fc470718 | 1258 | |
3cf2715d | 1259 | insn_lengths[uid] = 0; |
fc470718 R |
1260 | |
1261 | if (GET_CODE (insn) == CODE_LABEL) | |
1262 | { | |
1263 | int log = LABEL_TO_ALIGNMENT (insn); | |
1264 | if (log) | |
1265 | { | |
1266 | int align = 1 << log; | |
ecb06768 | 1267 | int new_address = (insn_current_address + align - 1) & -align; |
fc470718 | 1268 | insn_lengths[uid] = new_address - insn_current_address; |
fc470718 R |
1269 | } |
1270 | } | |
1271 | ||
9d98a694 | 1272 | INSN_ADDRESSES (uid) = insn_current_address; |
f5d927c0 | 1273 | |
3cf2715d DE |
1274 | if (GET_CODE (insn) == NOTE || GET_CODE (insn) == BARRIER |
1275 | || GET_CODE (insn) == CODE_LABEL) | |
1276 | continue; | |
04da53bd R |
1277 | if (INSN_DELETED_P (insn)) |
1278 | continue; | |
3cf2715d DE |
1279 | |
1280 | body = PATTERN (insn); | |
1281 | if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) | |
5a32a90c JR |
1282 | { |
1283 | /* This only takes room if read-only data goes into the text | |
1284 | section. */ | |
d48bc59a | 1285 | if (JUMP_TABLES_IN_TEXT_SECTION || !HAVE_READONLY_DATA_SECTION) |
75197b37 BS |
1286 | insn_lengths[uid] = (XVECLEN (body, |
1287 | GET_CODE (body) == ADDR_DIFF_VEC) | |
1288 | * GET_MODE_SIZE (GET_MODE (body))); | |
5a32a90c | 1289 | /* Alignment is handled by ADDR_VEC_ALIGN. */ |
5a32a90c | 1290 | } |
a30caf5c | 1291 | else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0) |
3cf2715d DE |
1292 | insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn); |
1293 | else if (GET_CODE (body) == SEQUENCE) | |
1294 | { | |
1295 | int i; | |
1296 | int const_delay_slots; | |
1297 | #ifdef DELAY_SLOTS | |
1298 | const_delay_slots = const_num_delay_slots (XVECEXP (body, 0, 0)); | |
1299 | #else | |
1300 | const_delay_slots = 0; | |
1301 | #endif | |
1302 | /* Inside a delay slot sequence, we do not do any branch shortening | |
1303 | if the shortening could change the number of delay slots | |
0f41302f | 1304 | of the branch. */ |
3cf2715d DE |
1305 | for (i = 0; i < XVECLEN (body, 0); i++) |
1306 | { | |
1307 | rtx inner_insn = XVECEXP (body, 0, i); | |
1308 | int inner_uid = INSN_UID (inner_insn); | |
1309 | int inner_length; | |
1310 | ||
a30caf5c DC |
1311 | if (GET_CODE (body) == ASM_INPUT |
1312 | || asm_noperands (PATTERN (XVECEXP (body, 0, i))) >= 0) | |
3cf2715d DE |
1313 | inner_length = (asm_insn_count (PATTERN (inner_insn)) |
1314 | * insn_default_length (inner_insn)); | |
1315 | else | |
1316 | inner_length = insn_default_length (inner_insn); | |
f5d927c0 | 1317 | |
3cf2715d DE |
1318 | insn_lengths[inner_uid] = inner_length; |
1319 | if (const_delay_slots) | |
1320 | { | |
1321 | if ((varying_length[inner_uid] | |
1322 | = insn_variable_length_p (inner_insn)) != 0) | |
1323 | varying_length[uid] = 1; | |
9d98a694 AO |
1324 | INSN_ADDRESSES (inner_uid) = (insn_current_address |
1325 | + insn_lengths[uid]); | |
3cf2715d DE |
1326 | } |
1327 | else | |
1328 | varying_length[inner_uid] = 0; | |
1329 | insn_lengths[uid] += inner_length; | |
1330 | } | |
1331 | } | |
1332 | else if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER) | |
1333 | { | |
1334 | insn_lengths[uid] = insn_default_length (insn); | |
1335 | varying_length[uid] = insn_variable_length_p (insn); | |
1336 | } | |
1337 | ||
1338 | /* If needed, do any adjustment. */ | |
1339 | #ifdef ADJUST_INSN_LENGTH | |
1340 | ADJUST_INSN_LENGTH (insn, insn_lengths[uid]); | |
04b6000c | 1341 | if (insn_lengths[uid] < 0) |
c725bd79 | 1342 | fatal_insn ("negative insn length", insn); |
3cf2715d DE |
1343 | #endif |
1344 | } | |
1345 | ||
1346 | /* Now loop over all the insns finding varying length insns. For each, | |
1347 | get the current insn length. If it has changed, reflect the change. | |
1348 | When nothing changes for a full pass, we are done. */ | |
1349 | ||
1350 | while (something_changed) | |
1351 | { | |
1352 | something_changed = 0; | |
fc470718 | 1353 | insn_current_align = MAX_CODE_ALIGN - 1; |
3cf2715d DE |
1354 | for (insn_current_address = FIRST_INSN_ADDRESS, insn = first; |
1355 | insn != 0; | |
1356 | insn = NEXT_INSN (insn)) | |
1357 | { | |
1358 | int new_length; | |
b729186a | 1359 | #ifdef ADJUST_INSN_LENGTH |
3cf2715d | 1360 | int tmp_length; |
b729186a | 1361 | #endif |
fc470718 | 1362 | int length_align; |
3cf2715d DE |
1363 | |
1364 | uid = INSN_UID (insn); | |
fc470718 R |
1365 | |
1366 | if (GET_CODE (insn) == CODE_LABEL) | |
1367 | { | |
1368 | int log = LABEL_TO_ALIGNMENT (insn); | |
1369 | if (log > insn_current_align) | |
1370 | { | |
1371 | int align = 1 << log; | |
ecb06768 | 1372 | int new_address= (insn_current_address + align - 1) & -align; |
fc470718 R |
1373 | insn_lengths[uid] = new_address - insn_current_address; |
1374 | insn_current_align = log; | |
1375 | insn_current_address = new_address; | |
1376 | } | |
1377 | else | |
1378 | insn_lengths[uid] = 0; | |
9d98a694 | 1379 | INSN_ADDRESSES (uid) = insn_current_address; |
fc470718 R |
1380 | continue; |
1381 | } | |
1382 | ||
1383 | length_align = INSN_LENGTH_ALIGNMENT (insn); | |
1384 | if (length_align < insn_current_align) | |
1385 | insn_current_align = length_align; | |
1386 | ||
9d98a694 AO |
1387 | insn_last_address = INSN_ADDRESSES (uid); |
1388 | INSN_ADDRESSES (uid) = insn_current_address; | |
fc470718 | 1389 | |
5e75ef4a | 1390 | #ifdef CASE_VECTOR_SHORTEN_MODE |
33f7f353 JR |
1391 | if (optimize && GET_CODE (insn) == JUMP_INSN |
1392 | && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) | |
1393 | { | |
33f7f353 JR |
1394 | rtx body = PATTERN (insn); |
1395 | int old_length = insn_lengths[uid]; | |
1396 | rtx rel_lab = XEXP (XEXP (body, 0), 0); | |
1397 | rtx min_lab = XEXP (XEXP (body, 2), 0); | |
1398 | rtx max_lab = XEXP (XEXP (body, 3), 0); | |
9d98a694 AO |
1399 | int rel_addr = INSN_ADDRESSES (INSN_UID (rel_lab)); |
1400 | int min_addr = INSN_ADDRESSES (INSN_UID (min_lab)); | |
1401 | int max_addr = INSN_ADDRESSES (INSN_UID (max_lab)); | |
33f7f353 JR |
1402 | rtx prev; |
1403 | int rel_align = 0; | |
950a3816 KG |
1404 | addr_diff_vec_flags flags; |
1405 | ||
1406 | /* Avoid automatic aggregate initialization. */ | |
1407 | flags = ADDR_DIFF_VEC_FLAGS (body); | |
33f7f353 JR |
1408 | |
1409 | /* Try to find a known alignment for rel_lab. */ | |
1410 | for (prev = rel_lab; | |
1411 | prev | |
1412 | && ! insn_lengths[INSN_UID (prev)] | |
1413 | && ! (varying_length[INSN_UID (prev)] & 1); | |
1414 | prev = PREV_INSN (prev)) | |
1415 | if (varying_length[INSN_UID (prev)] & 2) | |
1416 | { | |
1417 | rel_align = LABEL_TO_ALIGNMENT (prev); | |
1418 | break; | |
1419 | } | |
1420 | ||
1421 | /* See the comment on addr_diff_vec_flags in rtl.h for the | |
1422 | meaning of the flags values. base: REL_LAB vec: INSN */ | |
1423 | /* Anything after INSN has still addresses from the last | |
1424 | pass; adjust these so that they reflect our current | |
1425 | estimate for this pass. */ | |
1426 | if (flags.base_after_vec) | |
1427 | rel_addr += insn_current_address - insn_last_address; | |
1428 | if (flags.min_after_vec) | |
1429 | min_addr += insn_current_address - insn_last_address; | |
1430 | if (flags.max_after_vec) | |
1431 | max_addr += insn_current_address - insn_last_address; | |
1432 | /* We want to know the worst case, i.e. lowest possible value | |
1433 | for the offset of MIN_LAB. If MIN_LAB is after REL_LAB, | |
1434 | its offset is positive, and we have to be wary of code shrink; | |
1435 | otherwise, it is negative, and we have to be vary of code | |
1436 | size increase. */ | |
1437 | if (flags.min_after_base) | |
1438 | { | |
1439 | /* If INSN is between REL_LAB and MIN_LAB, the size | |
1440 | changes we are about to make can change the alignment | |
1441 | within the observed offset, therefore we have to break | |
1442 | it up into two parts that are independent. */ | |
1443 | if (! flags.base_after_vec && flags.min_after_vec) | |
1444 | { | |
1445 | min_addr -= align_fuzz (rel_lab, insn, rel_align, 0); | |
1446 | min_addr -= align_fuzz (insn, min_lab, 0, 0); | |
1447 | } | |
1448 | else | |
1449 | min_addr -= align_fuzz (rel_lab, min_lab, rel_align, 0); | |
1450 | } | |
1451 | else | |
1452 | { | |
1453 | if (flags.base_after_vec && ! flags.min_after_vec) | |
1454 | { | |
1455 | min_addr -= align_fuzz (min_lab, insn, 0, ~0); | |
1456 | min_addr -= align_fuzz (insn, rel_lab, 0, ~0); | |
1457 | } | |
1458 | else | |
1459 | min_addr -= align_fuzz (min_lab, rel_lab, 0, ~0); | |
1460 | } | |
1461 | /* Likewise, determine the highest lowest possible value | |
1462 | for the offset of MAX_LAB. */ | |
1463 | if (flags.max_after_base) | |
1464 | { | |
1465 | if (! flags.base_after_vec && flags.max_after_vec) | |
1466 | { | |
1467 | max_addr += align_fuzz (rel_lab, insn, rel_align, ~0); | |
1468 | max_addr += align_fuzz (insn, max_lab, 0, ~0); | |
1469 | } | |
1470 | else | |
1471 | max_addr += align_fuzz (rel_lab, max_lab, rel_align, ~0); | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | if (flags.base_after_vec && ! flags.max_after_vec) | |
1476 | { | |
1477 | max_addr += align_fuzz (max_lab, insn, 0, 0); | |
1478 | max_addr += align_fuzz (insn, rel_lab, 0, 0); | |
1479 | } | |
1480 | else | |
1481 | max_addr += align_fuzz (max_lab, rel_lab, 0, 0); | |
1482 | } | |
1483 | PUT_MODE (body, CASE_VECTOR_SHORTEN_MODE (min_addr - rel_addr, | |
1484 | max_addr - rel_addr, | |
1485 | body)); | |
d48bc59a | 1486 | if (JUMP_TABLES_IN_TEXT_SECTION || !HAVE_READONLY_DATA_SECTION) |
75197b37 BS |
1487 | { |
1488 | insn_lengths[uid] | |
1489 | = (XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body))); | |
1490 | insn_current_address += insn_lengths[uid]; | |
1491 | if (insn_lengths[uid] != old_length) | |
1492 | something_changed = 1; | |
1493 | } | |
1494 | ||
33f7f353 | 1495 | continue; |
33f7f353 | 1496 | } |
5e75ef4a JL |
1497 | #endif /* CASE_VECTOR_SHORTEN_MODE */ |
1498 | ||
1499 | if (! (varying_length[uid])) | |
3cf2715d | 1500 | { |
674fc07d GS |
1501 | if (GET_CODE (insn) == INSN |
1502 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
1503 | { | |
1504 | int i; | |
1505 | ||
1506 | body = PATTERN (insn); | |
1507 | for (i = 0; i < XVECLEN (body, 0); i++) | |
1508 | { | |
1509 | rtx inner_insn = XVECEXP (body, 0, i); | |
1510 | int inner_uid = INSN_UID (inner_insn); | |
1511 | ||
1512 | INSN_ADDRESSES (inner_uid) = insn_current_address; | |
1513 | ||
1514 | insn_current_address += insn_lengths[inner_uid]; | |
1515 | } | |
dd3f0101 | 1516 | } |
674fc07d GS |
1517 | else |
1518 | insn_current_address += insn_lengths[uid]; | |
1519 | ||
3cf2715d DE |
1520 | continue; |
1521 | } | |
674fc07d | 1522 | |
3cf2715d DE |
1523 | if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) |
1524 | { | |
1525 | int i; | |
f5d927c0 | 1526 | |
3cf2715d DE |
1527 | body = PATTERN (insn); |
1528 | new_length = 0; | |
1529 | for (i = 0; i < XVECLEN (body, 0); i++) | |
1530 | { | |
1531 | rtx inner_insn = XVECEXP (body, 0, i); | |
1532 | int inner_uid = INSN_UID (inner_insn); | |
1533 | int inner_length; | |
1534 | ||
9d98a694 | 1535 | INSN_ADDRESSES (inner_uid) = insn_current_address; |
3cf2715d DE |
1536 | |
1537 | /* insn_current_length returns 0 for insns with a | |
1538 | non-varying length. */ | |
1539 | if (! varying_length[inner_uid]) | |
1540 | inner_length = insn_lengths[inner_uid]; | |
1541 | else | |
1542 | inner_length = insn_current_length (inner_insn); | |
1543 | ||
1544 | if (inner_length != insn_lengths[inner_uid]) | |
1545 | { | |
1546 | insn_lengths[inner_uid] = inner_length; | |
1547 | something_changed = 1; | |
1548 | } | |
1549 | insn_current_address += insn_lengths[inner_uid]; | |
1550 | new_length += inner_length; | |
1551 | } | |
1552 | } | |
1553 | else | |
1554 | { | |
1555 | new_length = insn_current_length (insn); | |
1556 | insn_current_address += new_length; | |
1557 | } | |
1558 | ||
3cf2715d DE |
1559 | #ifdef ADJUST_INSN_LENGTH |
1560 | /* If needed, do any adjustment. */ | |
1561 | tmp_length = new_length; | |
1562 | ADJUST_INSN_LENGTH (insn, new_length); | |
1563 | insn_current_address += (new_length - tmp_length); | |
3cf2715d DE |
1564 | #endif |
1565 | ||
1566 | if (new_length != insn_lengths[uid]) | |
1567 | { | |
1568 | insn_lengths[uid] = new_length; | |
1569 | something_changed = 1; | |
1570 | } | |
1571 | } | |
bb4aaf18 TG |
1572 | /* For a non-optimizing compile, do only a single pass. */ |
1573 | if (!optimize) | |
1574 | break; | |
3cf2715d | 1575 | } |
fc470718 R |
1576 | |
1577 | free (varying_length); | |
1578 | ||
3cf2715d DE |
1579 | #endif /* HAVE_ATTR_length */ |
1580 | } | |
1581 | ||
1582 | #ifdef HAVE_ATTR_length | |
1583 | /* Given the body of an INSN known to be generated by an ASM statement, return | |
1584 | the number of machine instructions likely to be generated for this insn. | |
1585 | This is used to compute its length. */ | |
1586 | ||
1587 | static int | |
1588 | asm_insn_count (body) | |
1589 | rtx body; | |
1590 | { | |
3cce094d | 1591 | const char *template; |
3cf2715d DE |
1592 | int count = 1; |
1593 | ||
5d0930ea DE |
1594 | if (GET_CODE (body) == ASM_INPUT) |
1595 | template = XSTR (body, 0); | |
1596 | else | |
df4ae160 | 1597 | template = decode_asm_operands (body, NULL, NULL, NULL, NULL); |
5d0930ea | 1598 | |
f5d927c0 KH |
1599 | for (; *template; template++) |
1600 | if (IS_ASM_LOGICAL_LINE_SEPARATOR (*template) || *template == '\n') | |
3cf2715d DE |
1601 | count++; |
1602 | ||
1603 | return count; | |
1604 | } | |
1605 | #endif | |
1606 | \f | |
1607 | /* Output assembler code for the start of a function, | |
1608 | and initialize some of the variables in this file | |
1609 | for the new function. The label for the function and associated | |
1610 | assembler pseudo-ops have already been output in `assemble_start_function'. | |
1611 | ||
1612 | FIRST is the first insn of the rtl for the function being compiled. | |
1613 | FILE is the file to write assembler code to. | |
1614 | OPTIMIZE is nonzero if we should eliminate redundant | |
1615 | test and compare insns. */ | |
1616 | ||
1617 | void | |
1618 | final_start_function (first, file, optimize) | |
1619 | rtx first; | |
1620 | FILE *file; | |
6a651371 | 1621 | int optimize ATTRIBUTE_UNUSED; |
3cf2715d DE |
1622 | { |
1623 | block_depth = 0; | |
1624 | ||
1625 | this_is_asm_operands = 0; | |
1626 | ||
1627 | #ifdef NON_SAVING_SETJMP | |
1628 | /* A function that calls setjmp should save and restore all the | |
1629 | call-saved registers on a system where longjmp clobbers them. */ | |
1630 | if (NON_SAVING_SETJMP && current_function_calls_setjmp) | |
1631 | { | |
1632 | int i; | |
1633 | ||
1634 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
252f342a | 1635 | if (!call_used_regs[i]) |
3cf2715d DE |
1636 | regs_ever_live[i] = 1; |
1637 | } | |
1638 | #endif | |
f5d927c0 | 1639 | |
3cf2715d | 1640 | if (NOTE_LINE_NUMBER (first) != NOTE_INSN_DELETED) |
653e276c NB |
1641 | notice_source_line (first); |
1642 | high_block_linenum = high_function_linenum = last_linenum; | |
eac40081 | 1643 | |
653e276c | 1644 | (*debug_hooks->begin_prologue) (last_linenum, last_filename); |
d291dd49 | 1645 | |
653e276c | 1646 | #if defined (DWARF2_UNWIND_INFO) || defined (IA64_UNWIND_INFO) |
7a0c8d71 | 1647 | if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG) |
653e276c | 1648 | dwarf2out_begin_prologue (0, NULL); |
f5d927c0 | 1649 | #endif |
3cf2715d DE |
1650 | |
1651 | #ifdef LEAF_REG_REMAP | |
54ff41b7 | 1652 | if (current_function_uses_only_leaf_regs) |
3cf2715d DE |
1653 | leaf_renumber_regs (first); |
1654 | #endif | |
1655 | ||
1656 | /* The Sun386i and perhaps other machines don't work right | |
1657 | if the profiling code comes after the prologue. */ | |
1658 | #ifdef PROFILE_BEFORE_PROLOGUE | |
70f4f91c | 1659 | if (current_function_profile) |
3cf2715d DE |
1660 | profile_function (file); |
1661 | #endif /* PROFILE_BEFORE_PROLOGUE */ | |
1662 | ||
0021b564 JM |
1663 | #if defined (DWARF2_UNWIND_INFO) && defined (HAVE_prologue) |
1664 | if (dwarf2out_do_frame ()) | |
1665 | dwarf2out_frame_debug (NULL_RTX); | |
1666 | #endif | |
1667 | ||
18c038b9 MM |
1668 | /* If debugging, assign block numbers to all of the blocks in this |
1669 | function. */ | |
1670 | if (write_symbols) | |
1671 | { | |
3ac79482 | 1672 | remove_unnecessary_notes (); |
ba4f7968 | 1673 | scope_to_insns_finalize (); |
a20612aa | 1674 | number_blocks (current_function_decl); |
18c038b9 MM |
1675 | /* We never actually put out begin/end notes for the top-level |
1676 | block in the function. But, conceptually, that block is | |
1677 | always needed. */ | |
1678 | TREE_ASM_WRITTEN (DECL_INITIAL (current_function_decl)) = 1; | |
1679 | } | |
1680 | ||
3cf2715d | 1681 | /* First output the function prologue: code to set up the stack frame. */ |
f6897b10 | 1682 | (*targetm.asm_out.function_prologue) (file, get_frame_size ()); |
3cf2715d | 1683 | |
7a0c8d71 DR |
1684 | #ifdef VMS_DEBUGGING_INFO |
1685 | /* Output label after the prologue of the function. */ | |
1686 | if (write_symbols == VMS_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG) | |
1687 | vmsdbgout_after_prologue (); | |
1688 | #endif | |
1689 | ||
3cf2715d DE |
1690 | /* If the machine represents the prologue as RTL, the profiling code must |
1691 | be emitted when NOTE_INSN_PROLOGUE_END is scanned. */ | |
1692 | #ifdef HAVE_prologue | |
1693 | if (! HAVE_prologue) | |
1694 | #endif | |
1695 | profile_after_prologue (file); | |
3cf2715d DE |
1696 | } |
1697 | ||
1698 | static void | |
1699 | profile_after_prologue (file) | |
7bdb32b9 | 1700 | FILE *file ATTRIBUTE_UNUSED; |
3cf2715d | 1701 | { |
3cf2715d | 1702 | #ifndef PROFILE_BEFORE_PROLOGUE |
70f4f91c | 1703 | if (current_function_profile) |
3cf2715d DE |
1704 | profile_function (file); |
1705 | #endif /* not PROFILE_BEFORE_PROLOGUE */ | |
1706 | } | |
1707 | ||
1708 | static void | |
1709 | profile_function (file) | |
b3656137 | 1710 | FILE *file ATTRIBUTE_UNUSED; |
3cf2715d | 1711 | { |
dcacfa04 | 1712 | #ifndef NO_PROFILE_COUNTERS |
9e2f9a7f | 1713 | int align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE); |
dcacfa04 | 1714 | #endif |
b729186a JL |
1715 | #if defined(ASM_OUTPUT_REG_PUSH) |
1716 | #if defined(STRUCT_VALUE_INCOMING_REGNUM) || defined(STRUCT_VALUE_REGNUM) | |
3cf2715d | 1717 | int sval = current_function_returns_struct; |
b729186a JL |
1718 | #endif |
1719 | #if defined(STATIC_CHAIN_INCOMING_REGNUM) || defined(STATIC_CHAIN_REGNUM) | |
3cf2715d | 1720 | int cxt = current_function_needs_context; |
b729186a JL |
1721 | #endif |
1722 | #endif /* ASM_OUTPUT_REG_PUSH */ | |
3cf2715d | 1723 | |
dcacfa04 | 1724 | #ifndef NO_PROFILE_COUNTERS |
3cf2715d DE |
1725 | data_section (); |
1726 | ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT)); | |
f6f315fe | 1727 | ASM_OUTPUT_INTERNAL_LABEL (file, "LP", current_function_profile_label_no); |
c8af3574 | 1728 | assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1); |
dcacfa04 | 1729 | #endif |
3cf2715d | 1730 | |
499df339 | 1731 | function_section (current_function_decl); |
3cf2715d | 1732 | |
65ed39df | 1733 | #if defined(STRUCT_VALUE_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d DE |
1734 | if (sval) |
1735 | ASM_OUTPUT_REG_PUSH (file, STRUCT_VALUE_INCOMING_REGNUM); | |
1736 | #else | |
65ed39df | 1737 | #if defined(STRUCT_VALUE_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1738 | if (sval) |
51723711 KG |
1739 | { |
1740 | ASM_OUTPUT_REG_PUSH (file, STRUCT_VALUE_REGNUM); | |
1741 | } | |
3cf2715d DE |
1742 | #endif |
1743 | #endif | |
1744 | ||
65ed39df | 1745 | #if defined(STATIC_CHAIN_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d DE |
1746 | if (cxt) |
1747 | ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_INCOMING_REGNUM); | |
1748 | #else | |
65ed39df | 1749 | #if defined(STATIC_CHAIN_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1750 | if (cxt) |
51723711 KG |
1751 | { |
1752 | ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_REGNUM); | |
1753 | } | |
3cf2715d DE |
1754 | #endif |
1755 | #endif | |
3cf2715d | 1756 | |
f6f315fe | 1757 | FUNCTION_PROFILER (file, current_function_profile_label_no); |
3cf2715d | 1758 | |
65ed39df | 1759 | #if defined(STATIC_CHAIN_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d DE |
1760 | if (cxt) |
1761 | ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_INCOMING_REGNUM); | |
1762 | #else | |
65ed39df | 1763 | #if defined(STATIC_CHAIN_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1764 | if (cxt) |
51723711 KG |
1765 | { |
1766 | ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_REGNUM); | |
1767 | } | |
3cf2715d DE |
1768 | #endif |
1769 | #endif | |
3cf2715d | 1770 | |
65ed39df | 1771 | #if defined(STRUCT_VALUE_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d DE |
1772 | if (sval) |
1773 | ASM_OUTPUT_REG_POP (file, STRUCT_VALUE_INCOMING_REGNUM); | |
1774 | #else | |
65ed39df | 1775 | #if defined(STRUCT_VALUE_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1776 | if (sval) |
51723711 KG |
1777 | { |
1778 | ASM_OUTPUT_REG_POP (file, STRUCT_VALUE_REGNUM); | |
1779 | } | |
3cf2715d DE |
1780 | #endif |
1781 | #endif | |
1782 | } | |
1783 | ||
1784 | /* Output assembler code for the end of a function. | |
1785 | For clarity, args are same as those of `final_start_function' | |
1786 | even though not all of them are needed. */ | |
1787 | ||
1788 | void | |
e2a12aca | 1789 | final_end_function () |
3cf2715d | 1790 | { |
be1bb652 | 1791 | app_disable (); |
3cf2715d | 1792 | |
e2a12aca | 1793 | (*debug_hooks->end_function) (high_function_linenum); |
3cf2715d | 1794 | |
3cf2715d DE |
1795 | /* Finally, output the function epilogue: |
1796 | code to restore the stack frame and return to the caller. */ | |
e2a12aca | 1797 | (*targetm.asm_out.function_epilogue) (asm_out_file, get_frame_size ()); |
3cf2715d | 1798 | |
e2a12aca NB |
1799 | /* And debug output. */ |
1800 | (*debug_hooks->end_epilogue) (); | |
3cf2715d | 1801 | |
e2a12aca | 1802 | #if defined (DWARF2_UNWIND_INFO) |
7a0c8d71 DR |
1803 | if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG |
1804 | && dwarf2out_do_frame ()) | |
9a666dda JM |
1805 | dwarf2out_end_epilogue (); |
1806 | #endif | |
3cf2715d DE |
1807 | } |
1808 | \f | |
3cf2715d DE |
1809 | /* Output assembler code for some insns: all or part of a function. |
1810 | For description of args, see `final_start_function', above. | |
1811 | ||
1812 | PRESCAN is 1 if we are not really outputting, | |
1813 | just scanning as if we were outputting. | |
1814 | Prescanning deletes and rearranges insns just like ordinary output. | |
1815 | PRESCAN is -2 if we are outputting after having prescanned. | |
1816 | In this case, don't try to delete or rearrange insns | |
1817 | because that has already been done. | |
1818 | Prescanning is done only on certain machines. */ | |
1819 | ||
1820 | void | |
1821 | final (first, file, optimize, prescan) | |
1822 | rtx first; | |
1823 | FILE *file; | |
1824 | int optimize; | |
1825 | int prescan; | |
1826 | { | |
b3694847 | 1827 | rtx insn; |
3cf2715d | 1828 | int max_line = 0; |
a8c3510c | 1829 | int max_uid = 0; |
3cf2715d DE |
1830 | |
1831 | last_ignored_compare = 0; | |
1832 | new_block = 1; | |
1833 | ||
1834 | /* Make a map indicating which line numbers appear in this function. | |
1835 | When producing SDB debugging info, delete troublesome line number | |
1836 | notes from inlined functions in other files as well as duplicate | |
1837 | line number notes. */ | |
1838 | #ifdef SDB_DEBUGGING_INFO | |
1839 | if (write_symbols == SDB_DEBUG) | |
1840 | { | |
1841 | rtx last = 0; | |
1842 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1843 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
1844 | { | |
1845 | if ((RTX_INTEGRATED_P (insn) | |
1846 | && strcmp (NOTE_SOURCE_FILE (insn), main_input_filename) != 0) | |
1847 | || (last != 0 | |
1848 | && NOTE_LINE_NUMBER (insn) == NOTE_LINE_NUMBER (last) | |
1849 | && NOTE_SOURCE_FILE (insn) == NOTE_SOURCE_FILE (last))) | |
1850 | { | |
2e106602 | 1851 | delete_insn (insn); /* Use delete_note. */ |
3cf2715d DE |
1852 | continue; |
1853 | } | |
1854 | last = insn; | |
1855 | if (NOTE_LINE_NUMBER (insn) > max_line) | |
1856 | max_line = NOTE_LINE_NUMBER (insn); | |
1857 | } | |
1858 | } | |
1859 | else | |
1860 | #endif | |
1861 | { | |
1862 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1863 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > max_line) | |
1864 | max_line = NOTE_LINE_NUMBER (insn); | |
1865 | } | |
1866 | ||
bedda2da | 1867 | line_note_exists = (char *) xcalloc (max_line + 1, sizeof (char)); |
3cf2715d DE |
1868 | |
1869 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
a8c3510c AM |
1870 | { |
1871 | if (INSN_UID (insn) > max_uid) /* find largest UID */ | |
f5d927c0 | 1872 | max_uid = INSN_UID (insn); |
a8c3510c | 1873 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) |
f5d927c0 | 1874 | line_note_exists[NOTE_LINE_NUMBER (insn)] = 1; |
9ef4c6ef JC |
1875 | #ifdef HAVE_cc0 |
1876 | /* If CC tracking across branches is enabled, record the insn which | |
1877 | jumps to each branch only reached from one place. */ | |
7ad7f828 | 1878 | if (optimize && GET_CODE (insn) == JUMP_INSN) |
9ef4c6ef JC |
1879 | { |
1880 | rtx lab = JUMP_LABEL (insn); | |
1881 | if (lab && LABEL_NUSES (lab) == 1) | |
1882 | { | |
1883 | LABEL_REFS (lab) = insn; | |
1884 | } | |
1885 | } | |
1886 | #endif | |
a8c3510c AM |
1887 | } |
1888 | ||
3cf2715d DE |
1889 | init_recog (); |
1890 | ||
1891 | CC_STATUS_INIT; | |
1892 | ||
1893 | /* Output the insns. */ | |
1894 | for (insn = NEXT_INSN (first); insn;) | |
2f16edb1 TG |
1895 | { |
1896 | #ifdef HAVE_ATTR_length | |
b9f22704 | 1897 | if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ()) |
0ac76ad9 | 1898 | { |
0ac76ad9 RH |
1899 | /* This can be triggered by bugs elsewhere in the compiler if |
1900 | new insns are created after init_insn_lengths is called. */ | |
0acb0203 JH |
1901 | if (GET_CODE (insn) == NOTE) |
1902 | insn_current_address = -1; | |
1903 | else | |
1904 | abort (); | |
0ac76ad9 RH |
1905 | } |
1906 | else | |
9d98a694 | 1907 | insn_current_address = INSN_ADDRESSES (INSN_UID (insn)); |
0ac76ad9 RH |
1908 | #endif /* HAVE_ATTR_length */ |
1909 | ||
2f16edb1 TG |
1910 | insn = final_scan_insn (insn, file, optimize, prescan, 0); |
1911 | } | |
3cf2715d | 1912 | |
b7c9bf28 | 1913 | /* Store function names for edge-profiling. */ |
2292e8fc | 1914 | /* ??? Probably should re-use the existing struct function. */ |
b7c9bf28 | 1915 | |
2292e8fc RH |
1916 | if (cfun->arc_profile) |
1917 | { | |
1918 | struct function_list *new_item = xmalloc (sizeof (struct function_list)); | |
1919 | ||
1920 | *functions_tail = new_item; | |
1921 | functions_tail = &new_item->next; | |
1922 | ||
1923 | new_item->next = 0; | |
1924 | new_item->name = xstrdup (current_function_name); | |
1925 | new_item->cfg_checksum = profile_info.current_function_cfg_checksum; | |
1926 | new_item->count_edges = profile_info.count_edges_instrumented_now; | |
1927 | } | |
dd3f0101 | 1928 | |
bedda2da MM |
1929 | free (line_note_exists); |
1930 | line_note_exists = NULL; | |
3cf2715d DE |
1931 | } |
1932 | \f | |
4bbf910e RH |
1933 | const char * |
1934 | get_insn_template (code, insn) | |
1935 | int code; | |
1936 | rtx insn; | |
1937 | { | |
1938 | const void *output = insn_data[code].output; | |
1939 | switch (insn_data[code].output_format) | |
1940 | { | |
1941 | case INSN_OUTPUT_FORMAT_SINGLE: | |
1942 | return (const char *) output; | |
1943 | case INSN_OUTPUT_FORMAT_MULTI: | |
f5d927c0 | 1944 | return ((const char *const *) output)[which_alternative]; |
4bbf910e RH |
1945 | case INSN_OUTPUT_FORMAT_FUNCTION: |
1946 | if (insn == NULL) | |
1947 | abort (); | |
f5d927c0 | 1948 | return (*(insn_output_fn) output) (recog_data.operand, insn); |
4bbf910e RH |
1949 | |
1950 | default: | |
1951 | abort (); | |
1952 | } | |
1953 | } | |
f5d927c0 | 1954 | |
3cf2715d DE |
1955 | /* The final scan for one insn, INSN. |
1956 | Args are same as in `final', except that INSN | |
1957 | is the insn being scanned. | |
1958 | Value returned is the next insn to be scanned. | |
1959 | ||
1960 | NOPEEPHOLES is the flag to disallow peephole processing (currently | |
1961 | used for within delayed branch sequence output). */ | |
1962 | ||
1963 | rtx | |
1964 | final_scan_insn (insn, file, optimize, prescan, nopeepholes) | |
1965 | rtx insn; | |
1966 | FILE *file; | |
272df862 | 1967 | int optimize ATTRIBUTE_UNUSED; |
3cf2715d | 1968 | int prescan; |
272df862 | 1969 | int nopeepholes ATTRIBUTE_UNUSED; |
3cf2715d | 1970 | { |
90ca38bb MM |
1971 | #ifdef HAVE_cc0 |
1972 | rtx set; | |
1973 | #endif | |
1974 | ||
3cf2715d DE |
1975 | insn_counter++; |
1976 | ||
1977 | /* Ignore deleted insns. These can occur when we split insns (due to a | |
1978 | template of "#") while not optimizing. */ | |
1979 | if (INSN_DELETED_P (insn)) | |
1980 | return NEXT_INSN (insn); | |
1981 | ||
1982 | switch (GET_CODE (insn)) | |
1983 | { | |
1984 | case NOTE: | |
1985 | if (prescan > 0) | |
1986 | break; | |
1987 | ||
be1bb652 RH |
1988 | switch (NOTE_LINE_NUMBER (insn)) |
1989 | { | |
1990 | case NOTE_INSN_DELETED: | |
1991 | case NOTE_INSN_LOOP_BEG: | |
1992 | case NOTE_INSN_LOOP_END: | |
2c79137a | 1993 | case NOTE_INSN_LOOP_END_TOP_COND: |
be1bb652 RH |
1994 | case NOTE_INSN_LOOP_CONT: |
1995 | case NOTE_INSN_LOOP_VTOP: | |
1996 | case NOTE_INSN_FUNCTION_END: | |
be1bb652 RH |
1997 | case NOTE_INSN_REPEATED_LINE_NUMBER: |
1998 | case NOTE_INSN_RANGE_BEG: | |
1999 | case NOTE_INSN_RANGE_END: | |
2000 | case NOTE_INSN_LIVE: | |
2001 | case NOTE_INSN_EXPECTED_VALUE: | |
2002 | break; | |
3cf2715d | 2003 | |
be1bb652 | 2004 | case NOTE_INSN_BASIC_BLOCK: |
ad0fc698 JW |
2005 | #ifdef IA64_UNWIND_INFO |
2006 | IA64_UNWIND_EMIT (asm_out_file, insn); | |
2007 | #endif | |
be1bb652 RH |
2008 | if (flag_debug_asm) |
2009 | fprintf (asm_out_file, "\t%s basic block %d\n", | |
0b17ab2f | 2010 | ASM_COMMENT_START, NOTE_BASIC_BLOCK (insn)->index); |
be1bb652 | 2011 | break; |
3cf2715d | 2012 | |
be1bb652 | 2013 | case NOTE_INSN_EH_REGION_BEG: |
52a11cbf RH |
2014 | ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHB", |
2015 | NOTE_EH_HANDLER (insn)); | |
3d195391 | 2016 | break; |
3d195391 | 2017 | |
be1bb652 | 2018 | case NOTE_INSN_EH_REGION_END: |
52a11cbf RH |
2019 | ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHE", |
2020 | NOTE_EH_HANDLER (insn)); | |
3d195391 | 2021 | break; |
3d195391 | 2022 | |
be1bb652 | 2023 | case NOTE_INSN_PROLOGUE_END: |
b9f22704 | 2024 | (*targetm.asm_out.function_end_prologue) (file); |
3cf2715d DE |
2025 | profile_after_prologue (file); |
2026 | break; | |
3cf2715d | 2027 | |
be1bb652 | 2028 | case NOTE_INSN_EPILOGUE_BEG: |
b9f22704 | 2029 | (*targetm.asm_out.function_begin_epilogue) (file); |
be1bb652 | 2030 | break; |
3cf2715d | 2031 | |
be1bb652 | 2032 | case NOTE_INSN_FUNCTION_BEG: |
653e276c NB |
2033 | app_disable (); |
2034 | (*debug_hooks->end_prologue) (last_linenum); | |
3cf2715d | 2035 | break; |
be1bb652 RH |
2036 | |
2037 | case NOTE_INSN_BLOCK_BEG: | |
2038 | if (debug_info_level == DINFO_LEVEL_NORMAL | |
3cf2715d | 2039 | || debug_info_level == DINFO_LEVEL_VERBOSE |
3cf2715d | 2040 | || write_symbols == DWARF_DEBUG |
7a0c8d71 DR |
2041 | || write_symbols == DWARF2_DEBUG |
2042 | || write_symbols == VMS_AND_DWARF2_DEBUG | |
2043 | || write_symbols == VMS_DEBUG) | |
be1bb652 RH |
2044 | { |
2045 | int n = BLOCK_NUMBER (NOTE_BLOCK (insn)); | |
3cf2715d | 2046 | |
be1bb652 RH |
2047 | app_disable (); |
2048 | ++block_depth; | |
2049 | high_block_linenum = last_linenum; | |
eac40081 | 2050 | |
a5a42b92 | 2051 | /* Output debugging info about the symbol-block beginning. */ |
e2a12aca | 2052 | (*debug_hooks->begin_block) (last_linenum, n); |
3cf2715d | 2053 | |
be1bb652 RH |
2054 | /* Mark this block as output. */ |
2055 | TREE_ASM_WRITTEN (NOTE_BLOCK (insn)) = 1; | |
2056 | } | |
2057 | break; | |
18c038b9 | 2058 | |
be1bb652 RH |
2059 | case NOTE_INSN_BLOCK_END: |
2060 | if (debug_info_level == DINFO_LEVEL_NORMAL | |
2061 | || debug_info_level == DINFO_LEVEL_VERBOSE | |
2062 | || write_symbols == DWARF_DEBUG | |
7a0c8d71 DR |
2063 | || write_symbols == DWARF2_DEBUG |
2064 | || write_symbols == VMS_AND_DWARF2_DEBUG | |
2065 | || write_symbols == VMS_DEBUG) | |
be1bb652 RH |
2066 | { |
2067 | int n = BLOCK_NUMBER (NOTE_BLOCK (insn)); | |
3cf2715d | 2068 | |
be1bb652 RH |
2069 | app_disable (); |
2070 | ||
2071 | /* End of a symbol-block. */ | |
2072 | --block_depth; | |
2073 | if (block_depth < 0) | |
2074 | abort (); | |
3cf2715d | 2075 | |
e2a12aca | 2076 | (*debug_hooks->end_block) (high_block_linenum, n); |
be1bb652 RH |
2077 | } |
2078 | break; | |
2079 | ||
2080 | case NOTE_INSN_DELETED_LABEL: | |
2081 | /* Emit the label. We may have deleted the CODE_LABEL because | |
2082 | the label could be proved to be unreachable, though still | |
2083 | referenced (in the form of having its address taken. */ | |
8215347e | 2084 | ASM_OUTPUT_DEBUG_LABEL (file, "L", CODE_LABEL_NUMBER (insn)); |
be1bb652 | 2085 | break; |
3cf2715d | 2086 | |
21835d9b JJ |
2087 | case 0: |
2088 | break; | |
2089 | ||
be1bb652 RH |
2090 | default: |
2091 | if (NOTE_LINE_NUMBER (insn) <= 0) | |
2092 | abort (); | |
3cf2715d | 2093 | |
be1bb652 RH |
2094 | /* This note is a line-number. */ |
2095 | { | |
b3694847 | 2096 | rtx note; |
be1bb652 RH |
2097 | int note_after = 0; |
2098 | ||
f5d927c0 | 2099 | /* If there is anything real after this note, output it. |
be1bb652 RH |
2100 | If another line note follows, omit this one. */ |
2101 | for (note = NEXT_INSN (insn); note; note = NEXT_INSN (note)) | |
2102 | { | |
2103 | if (GET_CODE (note) != NOTE && GET_CODE (note) != CODE_LABEL) | |
3cf2715d | 2104 | break; |
3cf2715d | 2105 | |
be1bb652 RH |
2106 | /* These types of notes can be significant |
2107 | so make sure the preceding line number stays. */ | |
2108 | else if (GET_CODE (note) == NOTE | |
2109 | && (NOTE_LINE_NUMBER (note) == NOTE_INSN_BLOCK_BEG | |
2110 | || NOTE_LINE_NUMBER (note) == NOTE_INSN_BLOCK_END | |
2111 | || NOTE_LINE_NUMBER (note) == NOTE_INSN_FUNCTION_BEG)) | |
2112 | break; | |
2113 | else if (GET_CODE (note) == NOTE && NOTE_LINE_NUMBER (note) > 0) | |
2114 | { | |
2115 | /* Another line note follows; we can delete this note | |
2116 | if no intervening line numbers have notes elsewhere. */ | |
2117 | int num; | |
2118 | for (num = NOTE_LINE_NUMBER (insn) + 1; | |
2119 | num < NOTE_LINE_NUMBER (note); | |
2120 | num++) | |
2121 | if (line_note_exists[num]) | |
2122 | break; | |
2123 | ||
2124 | if (num >= NOTE_LINE_NUMBER (note)) | |
2125 | note_after = 1; | |
2126 | break; | |
2127 | } | |
2128 | } | |
2129 | ||
2130 | /* Output this line note if it is the first or the last line | |
2131 | note in a row. */ | |
2132 | if (!note_after) | |
653e276c NB |
2133 | { |
2134 | notice_source_line (insn); | |
2135 | (*debug_hooks->source_line) (last_linenum, last_filename); | |
2136 | } | |
be1bb652 | 2137 | } |
f5d927c0 | 2138 | break; |
3cf2715d DE |
2139 | } |
2140 | break; | |
2141 | ||
2142 | case BARRIER: | |
f73ad30e | 2143 | #if defined (DWARF2_UNWIND_INFO) |
fbfa55b0 | 2144 | if (dwarf2out_do_frame ()) |
be1bb652 | 2145 | dwarf2out_frame_debug (insn); |
3cf2715d DE |
2146 | #endif |
2147 | break; | |
2148 | ||
2149 | case CODE_LABEL: | |
1dd8faa8 R |
2150 | /* The target port might emit labels in the output function for |
2151 | some insn, e.g. sh.c output_branchy_insn. */ | |
de7987a6 R |
2152 | if (CODE_LABEL_NUMBER (insn) <= max_labelno) |
2153 | { | |
2154 | int align = LABEL_TO_ALIGNMENT (insn); | |
50b2596f | 2155 | #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN |
9e423e6d | 2156 | int max_skip = LABEL_TO_MAX_SKIP (insn); |
50b2596f | 2157 | #endif |
fc470718 | 2158 | |
1dd8faa8 | 2159 | if (align && NEXT_INSN (insn)) |
40cdfca6 | 2160 | { |
9e423e6d | 2161 | #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN |
40cdfca6 | 2162 | ASM_OUTPUT_MAX_SKIP_ALIGN (file, align, max_skip); |
9e423e6d | 2163 | #else |
40cdfca6 | 2164 | ASM_OUTPUT_ALIGN (file, align); |
9e423e6d | 2165 | #endif |
40cdfca6 | 2166 | } |
de7987a6 | 2167 | } |
9ef4c6ef | 2168 | #ifdef HAVE_cc0 |
3cf2715d | 2169 | CC_STATUS_INIT; |
9ef4c6ef JC |
2170 | /* If this label is reached from only one place, set the condition |
2171 | codes from the instruction just before the branch. */ | |
7ad7f828 JC |
2172 | |
2173 | /* Disabled because some insns set cc_status in the C output code | |
2174 | and NOTICE_UPDATE_CC alone can set incorrect status. */ | |
2175 | if (0 /* optimize && LABEL_NUSES (insn) == 1*/) | |
9ef4c6ef JC |
2176 | { |
2177 | rtx jump = LABEL_REFS (insn); | |
2178 | rtx barrier = prev_nonnote_insn (insn); | |
2179 | rtx prev; | |
2180 | /* If the LABEL_REFS field of this label has been set to point | |
2181 | at a branch, the predecessor of the branch is a regular | |
2182 | insn, and that branch is the only way to reach this label, | |
2183 | set the condition codes based on the branch and its | |
2184 | predecessor. */ | |
2185 | if (barrier && GET_CODE (barrier) == BARRIER | |
2186 | && jump && GET_CODE (jump) == JUMP_INSN | |
2187 | && (prev = prev_nonnote_insn (jump)) | |
2188 | && GET_CODE (prev) == INSN) | |
2189 | { | |
2190 | NOTICE_UPDATE_CC (PATTERN (prev), prev); | |
2191 | NOTICE_UPDATE_CC (PATTERN (jump), jump); | |
2192 | } | |
2193 | } | |
2194 | #endif | |
3cf2715d DE |
2195 | if (prescan > 0) |
2196 | break; | |
2197 | new_block = 1; | |
03ffa171 RK |
2198 | |
2199 | #ifdef FINAL_PRESCAN_LABEL | |
df4ae160 | 2200 | FINAL_PRESCAN_INSN (insn, NULL, 0); |
03ffa171 RK |
2201 | #endif |
2202 | ||
e1772ac0 NB |
2203 | if (LABEL_NAME (insn)) |
2204 | (*debug_hooks->label) (insn); | |
2205 | ||
3cf2715d DE |
2206 | if (app_on) |
2207 | { | |
51723711 | 2208 | fputs (ASM_APP_OFF, file); |
3cf2715d DE |
2209 | app_on = 0; |
2210 | } | |
2211 | if (NEXT_INSN (insn) != 0 | |
2212 | && GET_CODE (NEXT_INSN (insn)) == JUMP_INSN) | |
2213 | { | |
2214 | rtx nextbody = PATTERN (NEXT_INSN (insn)); | |
2215 | ||
2216 | /* If this label is followed by a jump-table, | |
2217 | make sure we put the label in the read-only section. Also | |
2218 | possibly write the label and jump table together. */ | |
2219 | ||
2220 | if (GET_CODE (nextbody) == ADDR_VEC | |
2221 | || GET_CODE (nextbody) == ADDR_DIFF_VEC) | |
2222 | { | |
e0d80184 DM |
2223 | #if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC) |
2224 | /* In this case, the case vector is being moved by the | |
2225 | target, so don't output the label at all. Leave that | |
2226 | to the back end macros. */ | |
2227 | #else | |
75197b37 BS |
2228 | if (! JUMP_TABLES_IN_TEXT_SECTION) |
2229 | { | |
340f7e7c RH |
2230 | int log_align; |
2231 | ||
75197b37 | 2232 | readonly_data_section (); |
340f7e7c RH |
2233 | |
2234 | #ifdef ADDR_VEC_ALIGN | |
3e4eece3 | 2235 | log_align = ADDR_VEC_ALIGN (NEXT_INSN (insn)); |
340f7e7c RH |
2236 | #else |
2237 | log_align = exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT); | |
2238 | #endif | |
2239 | ASM_OUTPUT_ALIGN (file, log_align); | |
75197b37 BS |
2240 | } |
2241 | else | |
2242 | function_section (current_function_decl); | |
2243 | ||
3cf2715d DE |
2244 | #ifdef ASM_OUTPUT_CASE_LABEL |
2245 | ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn), | |
2246 | NEXT_INSN (insn)); | |
2247 | #else | |
f5d927c0 KH |
2248 | if (LABEL_ALTERNATE_NAME (insn)) |
2249 | ASM_OUTPUT_ALTERNATE_LABEL_NAME (file, insn); | |
2250 | else | |
2251 | ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (insn)); | |
e0d80184 | 2252 | #endif |
3cf2715d DE |
2253 | #endif |
2254 | break; | |
2255 | } | |
2256 | } | |
8cd0faaf | 2257 | if (LABEL_ALTERNATE_NAME (insn)) |
f5d927c0 | 2258 | ASM_OUTPUT_ALTERNATE_LABEL_NAME (file, insn); |
8cd0faaf | 2259 | else |
f5d927c0 | 2260 | ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (insn)); |
3cf2715d DE |
2261 | break; |
2262 | ||
2263 | default: | |
2264 | { | |
b3694847 | 2265 | rtx body = PATTERN (insn); |
3cf2715d | 2266 | int insn_code_number; |
9b3142b3 | 2267 | const char *template; |
3cf2715d DE |
2268 | rtx note; |
2269 | ||
2270 | /* An INSN, JUMP_INSN or CALL_INSN. | |
2271 | First check for special kinds that recog doesn't recognize. */ | |
2272 | ||
2273 | if (GET_CODE (body) == USE /* These are just declarations */ | |
2274 | || GET_CODE (body) == CLOBBER) | |
2275 | break; | |
2276 | ||
2277 | #ifdef HAVE_cc0 | |
2278 | /* If there is a REG_CC_SETTER note on this insn, it means that | |
2279 | the setting of the condition code was done in the delay slot | |
2280 | of the insn that branched here. So recover the cc status | |
2281 | from the insn that set it. */ | |
2282 | ||
2283 | note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); | |
2284 | if (note) | |
2285 | { | |
2286 | NOTICE_UPDATE_CC (PATTERN (XEXP (note, 0)), XEXP (note, 0)); | |
2287 | cc_prev_status = cc_status; | |
2288 | } | |
2289 | #endif | |
2290 | ||
2291 | /* Detect insns that are really jump-tables | |
2292 | and output them as such. */ | |
2293 | ||
2294 | if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) | |
2295 | { | |
7f7f8214 | 2296 | #if !(defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)) |
b3694847 | 2297 | int vlen, idx; |
7f7f8214 | 2298 | #endif |
3cf2715d DE |
2299 | |
2300 | if (prescan > 0) | |
2301 | break; | |
2302 | ||
2303 | if (app_on) | |
2304 | { | |
51723711 | 2305 | fputs (ASM_APP_OFF, file); |
3cf2715d DE |
2306 | app_on = 0; |
2307 | } | |
2308 | ||
e0d80184 DM |
2309 | #if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC) |
2310 | if (GET_CODE (body) == ADDR_VEC) | |
2311 | { | |
2312 | #ifdef ASM_OUTPUT_ADDR_VEC | |
2313 | ASM_OUTPUT_ADDR_VEC (PREV_INSN (insn), body); | |
2314 | #else | |
f5d927c0 | 2315 | abort (); |
e0d80184 DM |
2316 | #endif |
2317 | } | |
2318 | else | |
2319 | { | |
2320 | #ifdef ASM_OUTPUT_ADDR_DIFF_VEC | |
2321 | ASM_OUTPUT_ADDR_DIFF_VEC (PREV_INSN (insn), body); | |
2322 | #else | |
f5d927c0 | 2323 | abort (); |
e0d80184 DM |
2324 | #endif |
2325 | } | |
2326 | #else | |
3cf2715d DE |
2327 | vlen = XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC); |
2328 | for (idx = 0; idx < vlen; idx++) | |
2329 | { | |
2330 | if (GET_CODE (body) == ADDR_VEC) | |
2331 | { | |
2332 | #ifdef ASM_OUTPUT_ADDR_VEC_ELT | |
2333 | ASM_OUTPUT_ADDR_VEC_ELT | |
2334 | (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
2335 | #else | |
2336 | abort (); | |
2337 | #endif | |
2338 | } | |
2339 | else | |
2340 | { | |
2341 | #ifdef ASM_OUTPUT_ADDR_DIFF_ELT | |
2342 | ASM_OUTPUT_ADDR_DIFF_ELT | |
2343 | (file, | |
33f7f353 | 2344 | body, |
3cf2715d DE |
2345 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), |
2346 | CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0))); | |
2347 | #else | |
2348 | abort (); | |
2349 | #endif | |
2350 | } | |
2351 | } | |
2352 | #ifdef ASM_OUTPUT_CASE_END | |
2353 | ASM_OUTPUT_CASE_END (file, | |
2354 | CODE_LABEL_NUMBER (PREV_INSN (insn)), | |
2355 | insn); | |
e0d80184 | 2356 | #endif |
3cf2715d DE |
2357 | #endif |
2358 | ||
4d1065ed | 2359 | function_section (current_function_decl); |
3cf2715d DE |
2360 | |
2361 | break; | |
2362 | } | |
2363 | ||
3cf2715d DE |
2364 | if (GET_CODE (body) == ASM_INPUT) |
2365 | { | |
36d7136e RH |
2366 | const char *string = XSTR (body, 0); |
2367 | ||
3cf2715d DE |
2368 | /* There's no telling what that did to the condition codes. */ |
2369 | CC_STATUS_INIT; | |
2370 | if (prescan > 0) | |
2371 | break; | |
36d7136e RH |
2372 | |
2373 | if (string[0]) | |
3cf2715d | 2374 | { |
36d7136e RH |
2375 | if (! app_on) |
2376 | { | |
2377 | fputs (ASM_APP_ON, file); | |
2378 | app_on = 1; | |
2379 | } | |
2380 | fprintf (asm_out_file, "\t%s\n", string); | |
3cf2715d | 2381 | } |
3cf2715d DE |
2382 | break; |
2383 | } | |
2384 | ||
2385 | /* Detect `asm' construct with operands. */ | |
2386 | if (asm_noperands (body) >= 0) | |
2387 | { | |
22bf4422 | 2388 | unsigned int noperands = asm_noperands (body); |
3cf2715d | 2389 | rtx *ops = (rtx *) alloca (noperands * sizeof (rtx)); |
3cce094d | 2390 | const char *string; |
3cf2715d DE |
2391 | |
2392 | /* There's no telling what that did to the condition codes. */ | |
2393 | CC_STATUS_INIT; | |
2394 | if (prescan > 0) | |
2395 | break; | |
2396 | ||
3cf2715d | 2397 | /* Get out the operand values. */ |
df4ae160 | 2398 | string = decode_asm_operands (body, ops, NULL, NULL, NULL); |
3cf2715d DE |
2399 | /* Inhibit aborts on what would otherwise be compiler bugs. */ |
2400 | insn_noperands = noperands; | |
2401 | this_is_asm_operands = insn; | |
2402 | ||
2403 | /* Output the insn using them. */ | |
36d7136e RH |
2404 | if (string[0]) |
2405 | { | |
2406 | if (! app_on) | |
2407 | { | |
2408 | fputs (ASM_APP_ON, file); | |
2409 | app_on = 1; | |
2410 | } | |
2411 | output_asm_insn (string, ops); | |
2412 | } | |
2413 | ||
3cf2715d DE |
2414 | this_is_asm_operands = 0; |
2415 | break; | |
2416 | } | |
2417 | ||
2418 | if (prescan <= 0 && app_on) | |
2419 | { | |
51723711 | 2420 | fputs (ASM_APP_OFF, file); |
3cf2715d DE |
2421 | app_on = 0; |
2422 | } | |
2423 | ||
2424 | if (GET_CODE (body) == SEQUENCE) | |
2425 | { | |
2426 | /* A delayed-branch sequence */ | |
b3694847 | 2427 | int i; |
3cf2715d DE |
2428 | rtx next; |
2429 | ||
2430 | if (prescan > 0) | |
2431 | break; | |
2432 | final_sequence = body; | |
2433 | ||
2434 | /* The first insn in this SEQUENCE might be a JUMP_INSN that will | |
2435 | force the restoration of a comparison that was previously | |
2436 | thought unnecessary. If that happens, cancel this sequence | |
2437 | and cause that insn to be restored. */ | |
2438 | ||
2439 | next = final_scan_insn (XVECEXP (body, 0, 0), file, 0, prescan, 1); | |
2440 | if (next != XVECEXP (body, 0, 1)) | |
2441 | { | |
2442 | final_sequence = 0; | |
2443 | return next; | |
2444 | } | |
2445 | ||
2446 | for (i = 1; i < XVECLEN (body, 0); i++) | |
c7eee2df RK |
2447 | { |
2448 | rtx insn = XVECEXP (body, 0, i); | |
2449 | rtx next = NEXT_INSN (insn); | |
2450 | /* We loop in case any instruction in a delay slot gets | |
2451 | split. */ | |
2452 | do | |
2453 | insn = final_scan_insn (insn, file, 0, prescan, 1); | |
2454 | while (insn != next); | |
2455 | } | |
3cf2715d DE |
2456 | #ifdef DBR_OUTPUT_SEQEND |
2457 | DBR_OUTPUT_SEQEND (file); | |
2458 | #endif | |
2459 | final_sequence = 0; | |
2460 | ||
2461 | /* If the insn requiring the delay slot was a CALL_INSN, the | |
2462 | insns in the delay slot are actually executed before the | |
2463 | called function. Hence we don't preserve any CC-setting | |
2464 | actions in these insns and the CC must be marked as being | |
2465 | clobbered by the function. */ | |
2466 | if (GET_CODE (XVECEXP (body, 0, 0)) == CALL_INSN) | |
b729186a JL |
2467 | { |
2468 | CC_STATUS_INIT; | |
2469 | } | |
3cf2715d DE |
2470 | break; |
2471 | } | |
2472 | ||
2473 | /* We have a real machine instruction as rtl. */ | |
2474 | ||
2475 | body = PATTERN (insn); | |
2476 | ||
2477 | #ifdef HAVE_cc0 | |
f5d927c0 | 2478 | set = single_set (insn); |
b88c92cc | 2479 | |
3cf2715d DE |
2480 | /* Check for redundant test and compare instructions |
2481 | (when the condition codes are already set up as desired). | |
2482 | This is done only when optimizing; if not optimizing, | |
2483 | it should be possible for the user to alter a variable | |
2484 | with the debugger in between statements | |
2485 | and the next statement should reexamine the variable | |
2486 | to compute the condition codes. */ | |
2487 | ||
30f5e9f5 | 2488 | if (optimize) |
3cf2715d | 2489 | { |
b88c92cc | 2490 | #if 0 |
f5d927c0 | 2491 | rtx set = single_set (insn); |
b88c92cc | 2492 | #endif |
30f5e9f5 RK |
2493 | |
2494 | if (set | |
2495 | && GET_CODE (SET_DEST (set)) == CC0 | |
2496 | && insn != last_ignored_compare) | |
3cf2715d | 2497 | { |
30f5e9f5 | 2498 | if (GET_CODE (SET_SRC (set)) == SUBREG) |
49d801d3 | 2499 | SET_SRC (set) = alter_subreg (&SET_SRC (set)); |
30f5e9f5 RK |
2500 | else if (GET_CODE (SET_SRC (set)) == COMPARE) |
2501 | { | |
2502 | if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG) | |
2503 | XEXP (SET_SRC (set), 0) | |
49d801d3 | 2504 | = alter_subreg (&XEXP (SET_SRC (set), 0)); |
30f5e9f5 RK |
2505 | if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG) |
2506 | XEXP (SET_SRC (set), 1) | |
49d801d3 | 2507 | = alter_subreg (&XEXP (SET_SRC (set), 1)); |
30f5e9f5 RK |
2508 | } |
2509 | if ((cc_status.value1 != 0 | |
2510 | && rtx_equal_p (SET_SRC (set), cc_status.value1)) | |
2511 | || (cc_status.value2 != 0 | |
2512 | && rtx_equal_p (SET_SRC (set), cc_status.value2))) | |
3cf2715d | 2513 | { |
30f5e9f5 | 2514 | /* Don't delete insn if it has an addressing side-effect. */ |
ff81832f | 2515 | if (! FIND_REG_INC_NOTE (insn, NULL_RTX) |
30f5e9f5 RK |
2516 | /* or if anything in it is volatile. */ |
2517 | && ! volatile_refs_p (PATTERN (insn))) | |
2518 | { | |
2519 | /* We don't really delete the insn; just ignore it. */ | |
2520 | last_ignored_compare = insn; | |
2521 | break; | |
2522 | } | |
3cf2715d DE |
2523 | } |
2524 | } | |
2525 | } | |
2526 | #endif | |
2527 | ||
3cf2715d DE |
2528 | #ifndef STACK_REGS |
2529 | /* Don't bother outputting obvious no-ops, even without -O. | |
2530 | This optimization is fast and doesn't interfere with debugging. | |
2531 | Don't do this if the insn is in a delay slot, since this | |
2532 | will cause an improper number of delay insns to be written. */ | |
2533 | if (final_sequence == 0 | |
2534 | && prescan >= 0 | |
2535 | && GET_CODE (insn) == INSN && GET_CODE (body) == SET | |
2536 | && GET_CODE (SET_SRC (body)) == REG | |
2537 | && GET_CODE (SET_DEST (body)) == REG | |
2538 | && REGNO (SET_SRC (body)) == REGNO (SET_DEST (body))) | |
2539 | break; | |
2540 | #endif | |
2541 | ||
2542 | #ifdef HAVE_cc0 | |
2543 | /* If this is a conditional branch, maybe modify it | |
2544 | if the cc's are in a nonstandard state | |
2545 | so that it accomplishes the same thing that it would | |
2546 | do straightforwardly if the cc's were set up normally. */ | |
2547 | ||
2548 | if (cc_status.flags != 0 | |
2549 | && GET_CODE (insn) == JUMP_INSN | |
2550 | && GET_CODE (body) == SET | |
2551 | && SET_DEST (body) == pc_rtx | |
2552 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
de2b56f9 | 2553 | && GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (body), 0))) == '<' |
fff752ad | 2554 | && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx |
3cf2715d DE |
2555 | /* This is done during prescan; it is not done again |
2556 | in final scan when prescan has been done. */ | |
2557 | && prescan >= 0) | |
2558 | { | |
2559 | /* This function may alter the contents of its argument | |
2560 | and clear some of the cc_status.flags bits. | |
2561 | It may also return 1 meaning condition now always true | |
2562 | or -1 meaning condition now always false | |
2563 | or 2 meaning condition nontrivial but altered. */ | |
b3694847 | 2564 | int result = alter_cond (XEXP (SET_SRC (body), 0)); |
3cf2715d DE |
2565 | /* If condition now has fixed value, replace the IF_THEN_ELSE |
2566 | with its then-operand or its else-operand. */ | |
2567 | if (result == 1) | |
2568 | SET_SRC (body) = XEXP (SET_SRC (body), 1); | |
2569 | if (result == -1) | |
2570 | SET_SRC (body) = XEXP (SET_SRC (body), 2); | |
2571 | ||
2572 | /* The jump is now either unconditional or a no-op. | |
2573 | If it has become a no-op, don't try to output it. | |
2574 | (It would not be recognized.) */ | |
2575 | if (SET_SRC (body) == pc_rtx) | |
2576 | { | |
ca6c03ca | 2577 | delete_insn (insn); |
3cf2715d DE |
2578 | break; |
2579 | } | |
2580 | else if (GET_CODE (SET_SRC (body)) == RETURN) | |
2581 | /* Replace (set (pc) (return)) with (return). */ | |
2582 | PATTERN (insn) = body = SET_SRC (body); | |
2583 | ||
2584 | /* Rerecognize the instruction if it has changed. */ | |
2585 | if (result != 0) | |
2586 | INSN_CODE (insn) = -1; | |
2587 | } | |
2588 | ||
2589 | /* Make same adjustments to instructions that examine the | |
462da2af SC |
2590 | condition codes without jumping and instructions that |
2591 | handle conditional moves (if this machine has either one). */ | |
3cf2715d DE |
2592 | |
2593 | if (cc_status.flags != 0 | |
b88c92cc | 2594 | && set != 0) |
3cf2715d | 2595 | { |
462da2af | 2596 | rtx cond_rtx, then_rtx, else_rtx; |
f5d927c0 | 2597 | |
462da2af | 2598 | if (GET_CODE (insn) != JUMP_INSN |
b88c92cc | 2599 | && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE) |
462da2af | 2600 | { |
b88c92cc RK |
2601 | cond_rtx = XEXP (SET_SRC (set), 0); |
2602 | then_rtx = XEXP (SET_SRC (set), 1); | |
2603 | else_rtx = XEXP (SET_SRC (set), 2); | |
462da2af SC |
2604 | } |
2605 | else | |
2606 | { | |
b88c92cc | 2607 | cond_rtx = SET_SRC (set); |
462da2af SC |
2608 | then_rtx = const_true_rtx; |
2609 | else_rtx = const0_rtx; | |
2610 | } | |
f5d927c0 | 2611 | |
462da2af | 2612 | switch (GET_CODE (cond_rtx)) |
3cf2715d DE |
2613 | { |
2614 | case GTU: | |
2615 | case GT: | |
2616 | case LTU: | |
2617 | case LT: | |
2618 | case GEU: | |
2619 | case GE: | |
2620 | case LEU: | |
2621 | case LE: | |
2622 | case EQ: | |
2623 | case NE: | |
2624 | { | |
b3694847 | 2625 | int result; |
462da2af | 2626 | if (XEXP (cond_rtx, 0) != cc0_rtx) |
3cf2715d | 2627 | break; |
462da2af | 2628 | result = alter_cond (cond_rtx); |
3cf2715d | 2629 | if (result == 1) |
b88c92cc | 2630 | validate_change (insn, &SET_SRC (set), then_rtx, 0); |
3cf2715d | 2631 | else if (result == -1) |
b88c92cc | 2632 | validate_change (insn, &SET_SRC (set), else_rtx, 0); |
3cf2715d DE |
2633 | else if (result == 2) |
2634 | INSN_CODE (insn) = -1; | |
b88c92cc | 2635 | if (SET_DEST (set) == SET_SRC (set)) |
ca6c03ca | 2636 | delete_insn (insn); |
3cf2715d | 2637 | } |
e9a25f70 JL |
2638 | break; |
2639 | ||
2640 | default: | |
2641 | break; | |
3cf2715d DE |
2642 | } |
2643 | } | |
462da2af | 2644 | |
3cf2715d DE |
2645 | #endif |
2646 | ||
ede7cd44 | 2647 | #ifdef HAVE_peephole |
3cf2715d DE |
2648 | /* Do machine-specific peephole optimizations if desired. */ |
2649 | ||
2650 | if (optimize && !flag_no_peephole && !nopeepholes) | |
2651 | { | |
2652 | rtx next = peephole (insn); | |
2653 | /* When peepholing, if there were notes within the peephole, | |
2654 | emit them before the peephole. */ | |
2655 | if (next != 0 && next != NEXT_INSN (insn)) | |
2656 | { | |
2657 | rtx prev = PREV_INSN (insn); | |
3cf2715d DE |
2658 | |
2659 | for (note = NEXT_INSN (insn); note != next; | |
2660 | note = NEXT_INSN (note)) | |
2661 | final_scan_insn (note, file, optimize, prescan, nopeepholes); | |
2662 | ||
2663 | /* In case this is prescan, put the notes | |
2664 | in proper position for later rescan. */ | |
2665 | note = NEXT_INSN (insn); | |
2666 | PREV_INSN (note) = prev; | |
2667 | NEXT_INSN (prev) = note; | |
2668 | NEXT_INSN (PREV_INSN (next)) = insn; | |
2669 | PREV_INSN (insn) = PREV_INSN (next); | |
2670 | NEXT_INSN (insn) = next; | |
2671 | PREV_INSN (next) = insn; | |
2672 | } | |
2673 | ||
2674 | /* PEEPHOLE might have changed this. */ | |
2675 | body = PATTERN (insn); | |
2676 | } | |
ede7cd44 | 2677 | #endif |
3cf2715d DE |
2678 | |
2679 | /* Try to recognize the instruction. | |
2680 | If successful, verify that the operands satisfy the | |
2681 | constraints for the instruction. Crash if they don't, | |
2682 | since `reload' should have changed them so that they do. */ | |
2683 | ||
2684 | insn_code_number = recog_memoized (insn); | |
0304f787 | 2685 | cleanup_subreg_operands (insn); |
3cf2715d | 2686 | |
dd3f0101 KH |
2687 | /* Dump the insn in the assembly for debugging. */ |
2688 | if (flag_dump_rtl_in_asm) | |
2689 | { | |
2690 | print_rtx_head = ASM_COMMENT_START; | |
2691 | print_rtl_single (asm_out_file, insn); | |
2692 | print_rtx_head = ""; | |
2693 | } | |
b9f22704 | 2694 | |
6c698a6d | 2695 | if (! constrain_operands_cached (1)) |
3cf2715d | 2696 | fatal_insn_not_found (insn); |
3cf2715d DE |
2697 | |
2698 | /* Some target machines need to prescan each insn before | |
2699 | it is output. */ | |
2700 | ||
2701 | #ifdef FINAL_PRESCAN_INSN | |
1ccbefce | 2702 | FINAL_PRESCAN_INSN (insn, recog_data.operand, recog_data.n_operands); |
3cf2715d DE |
2703 | #endif |
2704 | ||
afe48e06 RH |
2705 | #ifdef HAVE_conditional_execution |
2706 | if (GET_CODE (PATTERN (insn)) == COND_EXEC) | |
2707 | current_insn_predicate = COND_EXEC_TEST (PATTERN (insn)); | |
2708 | else | |
2709 | current_insn_predicate = NULL_RTX; | |
2710 | #endif | |
2711 | ||
3cf2715d DE |
2712 | #ifdef HAVE_cc0 |
2713 | cc_prev_status = cc_status; | |
2714 | ||
2715 | /* Update `cc_status' for this instruction. | |
2716 | The instruction's output routine may change it further. | |
2717 | If the output routine for a jump insn needs to depend | |
2718 | on the cc status, it should look at cc_prev_status. */ | |
2719 | ||
2720 | NOTICE_UPDATE_CC (body, insn); | |
2721 | #endif | |
2722 | ||
b1a9f6a0 | 2723 | current_output_insn = debug_insn = insn; |
3cf2715d | 2724 | |
f73ad30e | 2725 | #if defined (DWARF2_UNWIND_INFO) |
fbfa55b0 | 2726 | if (GET_CODE (insn) == CALL_INSN && dwarf2out_do_frame ()) |
b57d9225 JM |
2727 | dwarf2out_frame_debug (insn); |
2728 | #endif | |
2729 | ||
4bbf910e RH |
2730 | /* Find the proper template for this insn. */ |
2731 | template = get_insn_template (insn_code_number, insn); | |
3cf2715d | 2732 | |
4bbf910e RH |
2733 | /* If the C code returns 0, it means that it is a jump insn |
2734 | which follows a deleted test insn, and that test insn | |
2735 | needs to be reinserted. */ | |
3cf2715d DE |
2736 | if (template == 0) |
2737 | { | |
efd0378b HPN |
2738 | rtx prev; |
2739 | ||
4bbf910e RH |
2740 | if (prev_nonnote_insn (insn) != last_ignored_compare) |
2741 | abort (); | |
2742 | new_block = 0; | |
efd0378b HPN |
2743 | |
2744 | /* We have already processed the notes between the setter and | |
2745 | the user. Make sure we don't process them again, this is | |
2746 | particularly important if one of the notes is a block | |
2747 | scope note or an EH note. */ | |
2748 | for (prev = insn; | |
2749 | prev != last_ignored_compare; | |
2750 | prev = PREV_INSN (prev)) | |
2751 | { | |
2752 | if (GET_CODE (prev) == NOTE) | |
ca6c03ca | 2753 | delete_insn (prev); /* Use delete_note. */ |
efd0378b HPN |
2754 | } |
2755 | ||
2756 | return prev; | |
3cf2715d DE |
2757 | } |
2758 | ||
2759 | /* If the template is the string "#", it means that this insn must | |
2760 | be split. */ | |
2761 | if (template[0] == '#' && template[1] == '\0') | |
2762 | { | |
2763 | rtx new = try_split (body, insn, 0); | |
2764 | ||
2765 | /* If we didn't split the insn, go away. */ | |
2766 | if (new == insn && PATTERN (new) == body) | |
c725bd79 | 2767 | fatal_insn ("could not split insn", insn); |
f5d927c0 | 2768 | |
3d14e82f JW |
2769 | #ifdef HAVE_ATTR_length |
2770 | /* This instruction should have been split in shorten_branches, | |
2771 | to ensure that we would have valid length info for the | |
2772 | splitees. */ | |
2773 | abort (); | |
2774 | #endif | |
2775 | ||
3cf2715d DE |
2776 | new_block = 0; |
2777 | return new; | |
2778 | } | |
f5d927c0 | 2779 | |
3cf2715d DE |
2780 | if (prescan > 0) |
2781 | break; | |
2782 | ||
ce152ef8 AM |
2783 | #ifdef IA64_UNWIND_INFO |
2784 | IA64_UNWIND_EMIT (asm_out_file, insn); | |
2785 | #endif | |
3cf2715d DE |
2786 | /* Output assembler code from the template. */ |
2787 | ||
1ccbefce | 2788 | output_asm_insn (template, recog_data.operand); |
3cf2715d | 2789 | |
0021b564 | 2790 | #if defined (DWARF2_UNWIND_INFO) |
0021b564 | 2791 | #if defined (HAVE_prologue) |
fbfa55b0 RH |
2792 | if (GET_CODE (insn) == INSN && dwarf2out_do_frame ()) |
2793 | dwarf2out_frame_debug (insn); | |
2794 | #else | |
2795 | if (!ACCUMULATE_OUTGOING_ARGS | |
2796 | && GET_CODE (insn) == INSN | |
2797 | && dwarf2out_do_frame ()) | |
2798 | dwarf2out_frame_debug (insn); | |
0021b564 JM |
2799 | #endif |
2800 | #endif | |
469ac993 | 2801 | |
3cf2715d DE |
2802 | #if 0 |
2803 | /* It's not at all clear why we did this and doing so interferes | |
2804 | with tests we'd like to do to use REG_WAS_0 notes, so let's try | |
2805 | with this out. */ | |
2806 | ||
2807 | /* Mark this insn as having been output. */ | |
2808 | INSN_DELETED_P (insn) = 1; | |
2809 | #endif | |
2810 | ||
4a8d0c9c RH |
2811 | /* Emit information for vtable gc. */ |
2812 | note = find_reg_note (insn, REG_VTABLE_REF, NULL_RTX); | |
2813 | if (note) | |
2814 | assemble_vtable_entry (XEXP (XEXP (note, 0), 0), | |
2815 | INTVAL (XEXP (XEXP (note, 0), 1))); | |
2816 | ||
b1a9f6a0 | 2817 | current_output_insn = debug_insn = 0; |
3cf2715d DE |
2818 | } |
2819 | } | |
2820 | return NEXT_INSN (insn); | |
2821 | } | |
2822 | \f | |
2823 | /* Output debugging info to the assembler file FILE | |
2824 | based on the NOTE-insn INSN, assumed to be a line number. */ | |
2825 | ||
2826 | static void | |
653e276c | 2827 | notice_source_line (insn) |
3cf2715d DE |
2828 | rtx insn; |
2829 | { | |
b3694847 | 2830 | const char *filename = NOTE_SOURCE_FILE (insn); |
3cf2715d | 2831 | |
3cf2715d DE |
2832 | last_filename = filename; |
2833 | last_linenum = NOTE_LINE_NUMBER (insn); | |
eac40081 RK |
2834 | high_block_linenum = MAX (last_linenum, high_block_linenum); |
2835 | high_function_linenum = MAX (last_linenum, high_function_linenum); | |
3cf2715d DE |
2836 | } |
2837 | \f | |
0304f787 JL |
2838 | /* For each operand in INSN, simplify (subreg (reg)) so that it refers |
2839 | directly to the desired hard register. */ | |
f5d927c0 | 2840 | |
0304f787 JL |
2841 | void |
2842 | cleanup_subreg_operands (insn) | |
2843 | rtx insn; | |
2844 | { | |
f62a15e3 | 2845 | int i; |
6c698a6d | 2846 | extract_insn_cached (insn); |
1ccbefce | 2847 | for (i = 0; i < recog_data.n_operands; i++) |
0304f787 | 2848 | { |
9f4524f2 RE |
2849 | /* The following test cannot use recog_data.operand when tesing |
2850 | for a SUBREG: the underlying object might have been changed | |
2851 | already if we are inside a match_operator expression that | |
2852 | matches the else clause. Instead we test the underlying | |
2853 | expression directly. */ | |
2854 | if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG) | |
49d801d3 | 2855 | recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i]); |
1ccbefce | 2856 | else if (GET_CODE (recog_data.operand[i]) == PLUS |
04337620 BS |
2857 | || GET_CODE (recog_data.operand[i]) == MULT |
2858 | || GET_CODE (recog_data.operand[i]) == MEM) | |
49d801d3 | 2859 | recog_data.operand[i] = walk_alter_subreg (recog_data.operand_loc[i]); |
0304f787 JL |
2860 | } |
2861 | ||
1ccbefce | 2862 | for (i = 0; i < recog_data.n_dups; i++) |
0304f787 | 2863 | { |
1ccbefce | 2864 | if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG) |
49d801d3 | 2865 | *recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i]); |
1ccbefce | 2866 | else if (GET_CODE (*recog_data.dup_loc[i]) == PLUS |
04337620 BS |
2867 | || GET_CODE (*recog_data.dup_loc[i]) == MULT |
2868 | || GET_CODE (*recog_data.dup_loc[i]) == MEM) | |
49d801d3 | 2869 | *recog_data.dup_loc[i] = walk_alter_subreg (recog_data.dup_loc[i]); |
0304f787 JL |
2870 | } |
2871 | } | |
2872 | ||
3cf2715d DE |
2873 | /* If X is a SUBREG, replace it with a REG or a MEM, |
2874 | based on the thing it is a subreg of. */ | |
2875 | ||
2876 | rtx | |
49d801d3 JH |
2877 | alter_subreg (xp) |
2878 | rtx *xp; | |
3cf2715d | 2879 | { |
49d801d3 | 2880 | rtx x = *xp; |
b3694847 | 2881 | rtx y = SUBREG_REG (x); |
f5963e61 | 2882 | |
49d801d3 JH |
2883 | /* simplify_subreg does not remove subreg from volatile references. |
2884 | We are required to. */ | |
2885 | if (GET_CODE (y) == MEM) | |
2886 | *xp = adjust_address (y, GET_MODE (x), SUBREG_BYTE (x)); | |
2887 | else | |
fea54805 RK |
2888 | { |
2889 | rtx new = simplify_subreg (GET_MODE (x), y, GET_MODE (y), | |
2890 | SUBREG_BYTE (x)); | |
2891 | ||
2892 | if (new != 0) | |
2893 | *xp = new; | |
2894 | /* Simplify_subreg can't handle some REG cases, but we have to. */ | |
2895 | else if (GET_CODE (y) == REG) | |
2896 | { | |
7687c5b8 | 2897 | unsigned int regno = subreg_hard_regno (x, 1); |
fea54805 | 2898 | PUT_CODE (x, REG); |
7687c5b8 | 2899 | REGNO (x) = regno; |
fea54805 RK |
2900 | ORIGINAL_REGNO (x) = ORIGINAL_REGNO (y); |
2901 | /* This field has a different meaning for REGs and SUBREGs. Make | |
2902 | sure to clear it! */ | |
2adc7f12 | 2903 | RTX_FLAG (x, used) = 0; |
fea54805 RK |
2904 | } |
2905 | else | |
2906 | abort (); | |
2907 | } | |
2908 | ||
49d801d3 | 2909 | return *xp; |
3cf2715d DE |
2910 | } |
2911 | ||
2912 | /* Do alter_subreg on all the SUBREGs contained in X. */ | |
2913 | ||
2914 | static rtx | |
49d801d3 JH |
2915 | walk_alter_subreg (xp) |
2916 | rtx *xp; | |
3cf2715d | 2917 | { |
49d801d3 | 2918 | rtx x = *xp; |
3cf2715d DE |
2919 | switch (GET_CODE (x)) |
2920 | { | |
2921 | case PLUS: | |
2922 | case MULT: | |
49d801d3 JH |
2923 | XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0)); |
2924 | XEXP (x, 1) = walk_alter_subreg (&XEXP (x, 1)); | |
3cf2715d DE |
2925 | break; |
2926 | ||
2927 | case MEM: | |
49d801d3 | 2928 | XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0)); |
3cf2715d DE |
2929 | break; |
2930 | ||
2931 | case SUBREG: | |
49d801d3 | 2932 | return alter_subreg (xp); |
f5d927c0 | 2933 | |
e9a25f70 JL |
2934 | default: |
2935 | break; | |
3cf2715d DE |
2936 | } |
2937 | ||
5bc72aeb | 2938 | return *xp; |
3cf2715d DE |
2939 | } |
2940 | \f | |
2941 | #ifdef HAVE_cc0 | |
2942 | ||
2943 | /* Given BODY, the body of a jump instruction, alter the jump condition | |
2944 | as required by the bits that are set in cc_status.flags. | |
2945 | Not all of the bits there can be handled at this level in all cases. | |
2946 | ||
2947 | The value is normally 0. | |
2948 | 1 means that the condition has become always true. | |
2949 | -1 means that the condition has become always false. | |
2950 | 2 means that COND has been altered. */ | |
2951 | ||
2952 | static int | |
2953 | alter_cond (cond) | |
b3694847 | 2954 | rtx cond; |
3cf2715d DE |
2955 | { |
2956 | int value = 0; | |
2957 | ||
2958 | if (cc_status.flags & CC_REVERSED) | |
2959 | { | |
2960 | value = 2; | |
2961 | PUT_CODE (cond, swap_condition (GET_CODE (cond))); | |
2962 | } | |
2963 | ||
2964 | if (cc_status.flags & CC_INVERTED) | |
2965 | { | |
2966 | value = 2; | |
2967 | PUT_CODE (cond, reverse_condition (GET_CODE (cond))); | |
2968 | } | |
2969 | ||
2970 | if (cc_status.flags & CC_NOT_POSITIVE) | |
2971 | switch (GET_CODE (cond)) | |
2972 | { | |
2973 | case LE: | |
2974 | case LEU: | |
2975 | case GEU: | |
2976 | /* Jump becomes unconditional. */ | |
2977 | return 1; | |
2978 | ||
2979 | case GT: | |
2980 | case GTU: | |
2981 | case LTU: | |
2982 | /* Jump becomes no-op. */ | |
2983 | return -1; | |
2984 | ||
2985 | case GE: | |
2986 | PUT_CODE (cond, EQ); | |
2987 | value = 2; | |
2988 | break; | |
2989 | ||
2990 | case LT: | |
2991 | PUT_CODE (cond, NE); | |
2992 | value = 2; | |
2993 | break; | |
f5d927c0 | 2994 | |
e9a25f70 JL |
2995 | default: |
2996 | break; | |
3cf2715d DE |
2997 | } |
2998 | ||
2999 | if (cc_status.flags & CC_NOT_NEGATIVE) | |
3000 | switch (GET_CODE (cond)) | |
3001 | { | |
3002 | case GE: | |
3003 | case GEU: | |
3004 | /* Jump becomes unconditional. */ | |
3005 | return 1; | |
3006 | ||
3007 | case LT: | |
3008 | case LTU: | |
3009 | /* Jump becomes no-op. */ | |
3010 | return -1; | |
3011 | ||
3012 | case LE: | |
3013 | case LEU: | |
3014 | PUT_CODE (cond, EQ); | |
3015 | value = 2; | |
3016 | break; | |
3017 | ||
3018 | case GT: | |
3019 | case GTU: | |
3020 | PUT_CODE (cond, NE); | |
3021 | value = 2; | |
3022 | break; | |
f5d927c0 | 3023 | |
e9a25f70 JL |
3024 | default: |
3025 | break; | |
3cf2715d DE |
3026 | } |
3027 | ||
3028 | if (cc_status.flags & CC_NO_OVERFLOW) | |
3029 | switch (GET_CODE (cond)) | |
3030 | { | |
3031 | case GEU: | |
3032 | /* Jump becomes unconditional. */ | |
3033 | return 1; | |
3034 | ||
3035 | case LEU: | |
3036 | PUT_CODE (cond, EQ); | |
3037 | value = 2; | |
3038 | break; | |
3039 | ||
3040 | case GTU: | |
3041 | PUT_CODE (cond, NE); | |
3042 | value = 2; | |
3043 | break; | |
3044 | ||
3045 | case LTU: | |
3046 | /* Jump becomes no-op. */ | |
3047 | return -1; | |
f5d927c0 | 3048 | |
e9a25f70 JL |
3049 | default: |
3050 | break; | |
3cf2715d DE |
3051 | } |
3052 | ||
3053 | if (cc_status.flags & (CC_Z_IN_NOT_N | CC_Z_IN_N)) | |
3054 | switch (GET_CODE (cond)) | |
3055 | { | |
e9a25f70 | 3056 | default: |
3cf2715d DE |
3057 | abort (); |
3058 | ||
3059 | case NE: | |
3060 | PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? GE : LT); | |
3061 | value = 2; | |
3062 | break; | |
3063 | ||
3064 | case EQ: | |
3065 | PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? LT : GE); | |
3066 | value = 2; | |
3067 | break; | |
3068 | } | |
3069 | ||
3070 | if (cc_status.flags & CC_NOT_SIGNED) | |
3071 | /* The flags are valid if signed condition operators are converted | |
3072 | to unsigned. */ | |
3073 | switch (GET_CODE (cond)) | |
3074 | { | |
3075 | case LE: | |
3076 | PUT_CODE (cond, LEU); | |
3077 | value = 2; | |
3078 | break; | |
3079 | ||
3080 | case LT: | |
3081 | PUT_CODE (cond, LTU); | |
3082 | value = 2; | |
3083 | break; | |
3084 | ||
3085 | case GT: | |
3086 | PUT_CODE (cond, GTU); | |
3087 | value = 2; | |
3088 | break; | |
3089 | ||
3090 | case GE: | |
3091 | PUT_CODE (cond, GEU); | |
3092 | value = 2; | |
3093 | break; | |
e9a25f70 JL |
3094 | |
3095 | default: | |
3096 | break; | |
3cf2715d DE |
3097 | } |
3098 | ||
3099 | return value; | |
3100 | } | |
3101 | #endif | |
3102 | \f | |
3103 | /* Report inconsistency between the assembler template and the operands. | |
3104 | In an `asm', it's the user's fault; otherwise, the compiler's fault. */ | |
3105 | ||
3106 | void | |
a52453cc | 3107 | output_operand_lossage VPARAMS ((const char *msgid, ...)) |
3cf2715d | 3108 | { |
a52453cc PT |
3109 | char *fmt_string; |
3110 | char *new_message; | |
fd478a0a | 3111 | const char *pfx_str; |
a52453cc PT |
3112 | VA_OPEN (ap, msgid); |
3113 | VA_FIXEDARG (ap, const char *, msgid); | |
3114 | ||
3115 | pfx_str = this_is_asm_operands ? _("invalid `asm': ") : "output_operand: "; | |
3116 | asprintf (&fmt_string, "%s%s", pfx_str, _(msgid)); | |
3117 | vasprintf (&new_message, fmt_string, ap); | |
dd3f0101 | 3118 | |
3cf2715d | 3119 | if (this_is_asm_operands) |
a52453cc | 3120 | error_for_asm (this_is_asm_operands, "%s", new_message); |
3cf2715d | 3121 | else |
a52453cc PT |
3122 | internal_error ("%s", new_message); |
3123 | ||
3124 | free (fmt_string); | |
3125 | free (new_message); | |
3126 | VA_CLOSE (ap); | |
3cf2715d DE |
3127 | } |
3128 | \f | |
3129 | /* Output of assembler code from a template, and its subroutines. */ | |
3130 | ||
0d4903b8 RK |
3131 | /* Annotate the assembly with a comment describing the pattern and |
3132 | alternative used. */ | |
3133 | ||
3134 | static void | |
3135 | output_asm_name () | |
3136 | { | |
3137 | if (debug_insn) | |
3138 | { | |
3139 | int num = INSN_CODE (debug_insn); | |
3140 | fprintf (asm_out_file, "\t%s %d\t%s", | |
3141 | ASM_COMMENT_START, INSN_UID (debug_insn), | |
3142 | insn_data[num].name); | |
3143 | if (insn_data[num].n_alternatives > 1) | |
3144 | fprintf (asm_out_file, "/%d", which_alternative + 1); | |
3145 | #ifdef HAVE_ATTR_length | |
3146 | fprintf (asm_out_file, "\t[length = %d]", | |
3147 | get_attr_length (debug_insn)); | |
3148 | #endif | |
3149 | /* Clear this so only the first assembler insn | |
3150 | of any rtl insn will get the special comment for -dp. */ | |
3151 | debug_insn = 0; | |
3152 | } | |
3153 | } | |
3154 | ||
998d7deb RH |
3155 | /* If OP is a REG or MEM and we can find a MEM_EXPR corresponding to it |
3156 | or its address, return that expr . Set *PADDRESSP to 1 if the expr | |
c5adc06a RK |
3157 | corresponds to the address of the object and 0 if to the object. */ |
3158 | ||
3159 | static tree | |
998d7deb | 3160 | get_mem_expr_from_op (op, paddressp) |
c5adc06a RK |
3161 | rtx op; |
3162 | int *paddressp; | |
3163 | { | |
998d7deb | 3164 | tree expr; |
c5adc06a RK |
3165 | int inner_addressp; |
3166 | ||
3167 | *paddressp = 0; | |
3168 | ||
90442291 JJ |
3169 | if (op == NULL) |
3170 | return 0; | |
3171 | ||
1285011e | 3172 | if (GET_CODE (op) == REG && ORIGINAL_REGNO (op) >= FIRST_PSEUDO_REGISTER) |
c5adc06a RK |
3173 | return REGNO_DECL (ORIGINAL_REGNO (op)); |
3174 | else if (GET_CODE (op) != MEM) | |
3175 | return 0; | |
3176 | ||
998d7deb RH |
3177 | if (MEM_EXPR (op) != 0) |
3178 | return MEM_EXPR (op); | |
c5adc06a RK |
3179 | |
3180 | /* Otherwise we have an address, so indicate it and look at the address. */ | |
3181 | *paddressp = 1; | |
3182 | op = XEXP (op, 0); | |
3183 | ||
3184 | /* First check if we have a decl for the address, then look at the right side | |
3185 | if it is a PLUS. Otherwise, strip off arithmetic and keep looking. | |
3186 | But don't allow the address to itself be indirect. */ | |
998d7deb RH |
3187 | if ((expr = get_mem_expr_from_op (op, &inner_addressp)) && ! inner_addressp) |
3188 | return expr; | |
c5adc06a | 3189 | else if (GET_CODE (op) == PLUS |
998d7deb RH |
3190 | && (expr = get_mem_expr_from_op (XEXP (op, 1), &inner_addressp))) |
3191 | return expr; | |
c5adc06a RK |
3192 | |
3193 | while (GET_RTX_CLASS (GET_CODE (op)) == '1' | |
3194 | || GET_RTX_CLASS (GET_CODE (op)) == '2') | |
3195 | op = XEXP (op, 0); | |
3196 | ||
998d7deb RH |
3197 | expr = get_mem_expr_from_op (op, &inner_addressp); |
3198 | return inner_addressp ? 0 : expr; | |
c5adc06a | 3199 | } |
ff81832f | 3200 | |
4f9b4029 RK |
3201 | /* Output operand names for assembler instructions. OPERANDS is the |
3202 | operand vector, OPORDER is the order to write the operands, and NOPS | |
3203 | is the number of operands to write. */ | |
3204 | ||
3205 | static void | |
3206 | output_asm_operand_names (operands, oporder, nops) | |
3207 | rtx *operands; | |
3208 | int *oporder; | |
3209 | int nops; | |
3210 | { | |
3211 | int wrote = 0; | |
3212 | int i; | |
3213 | ||
3214 | for (i = 0; i < nops; i++) | |
3215 | { | |
3216 | int addressp; | |
998d7deb | 3217 | tree expr = get_mem_expr_from_op (operands[oporder[i]], &addressp); |
4f9b4029 | 3218 | |
998d7deb | 3219 | if (expr) |
4f9b4029 | 3220 | { |
998d7deb | 3221 | fprintf (asm_out_file, "%c%s %s", |
1285011e | 3222 | wrote ? ',' : '\t', wrote ? "" : ASM_COMMENT_START, |
998d7deb RH |
3223 | addressp ? "*" : ""); |
3224 | print_mem_expr (asm_out_file, expr); | |
4f9b4029 RK |
3225 | wrote = 1; |
3226 | } | |
3227 | } | |
3228 | } | |
3229 | ||
3cf2715d DE |
3230 | /* Output text from TEMPLATE to the assembler output file, |
3231 | obeying %-directions to substitute operands taken from | |
3232 | the vector OPERANDS. | |
3233 | ||
3234 | %N (for N a digit) means print operand N in usual manner. | |
3235 | %lN means require operand N to be a CODE_LABEL or LABEL_REF | |
3236 | and print the label name with no punctuation. | |
3237 | %cN means require operand N to be a constant | |
3238 | and print the constant expression with no punctuation. | |
3239 | %aN means expect operand N to be a memory address | |
3240 | (not a memory reference!) and print a reference | |
3241 | to that address. | |
3242 | %nN means expect operand N to be a constant | |
3243 | and print a constant expression for minus the value | |
3244 | of the operand, with no other punctuation. */ | |
3245 | ||
3246 | void | |
3247 | output_asm_insn (template, operands) | |
9b3142b3 | 3248 | const char *template; |
3cf2715d DE |
3249 | rtx *operands; |
3250 | { | |
b3694847 SS |
3251 | const char *p; |
3252 | int c; | |
8554d9a4 JJ |
3253 | #ifdef ASSEMBLER_DIALECT |
3254 | int dialect = 0; | |
3255 | #endif | |
0d4903b8 | 3256 | int oporder[MAX_RECOG_OPERANDS]; |
4f9b4029 | 3257 | char opoutput[MAX_RECOG_OPERANDS]; |
0d4903b8 | 3258 | int ops = 0; |
3cf2715d DE |
3259 | |
3260 | /* An insn may return a null string template | |
3261 | in a case where no assembler code is needed. */ | |
3262 | if (*template == 0) | |
3263 | return; | |
3264 | ||
4f9b4029 | 3265 | memset (opoutput, 0, sizeof opoutput); |
3cf2715d DE |
3266 | p = template; |
3267 | putc ('\t', asm_out_file); | |
3268 | ||
3269 | #ifdef ASM_OUTPUT_OPCODE | |
3270 | ASM_OUTPUT_OPCODE (asm_out_file, p); | |
3271 | #endif | |
3272 | ||
b729186a | 3273 | while ((c = *p++)) |
3cf2715d DE |
3274 | switch (c) |
3275 | { | |
3cf2715d | 3276 | case '\n': |
4f9b4029 RK |
3277 | if (flag_verbose_asm) |
3278 | output_asm_operand_names (operands, oporder, ops); | |
0d4903b8 RK |
3279 | if (flag_print_asm_name) |
3280 | output_asm_name (); | |
3281 | ||
4f9b4029 RK |
3282 | ops = 0; |
3283 | memset (opoutput, 0, sizeof opoutput); | |
3284 | ||
3cf2715d | 3285 | putc (c, asm_out_file); |
cb649530 | 3286 | #ifdef ASM_OUTPUT_OPCODE |
3cf2715d DE |
3287 | while ((c = *p) == '\t') |
3288 | { | |
3289 | putc (c, asm_out_file); | |
3290 | p++; | |
3291 | } | |
3292 | ASM_OUTPUT_OPCODE (asm_out_file, p); | |
3cf2715d | 3293 | #endif |
cb649530 | 3294 | break; |
3cf2715d DE |
3295 | |
3296 | #ifdef ASSEMBLER_DIALECT | |
3297 | case '{': | |
b729186a | 3298 | { |
b3694847 | 3299 | int i; |
f5d927c0 | 3300 | |
8554d9a4 JJ |
3301 | if (dialect) |
3302 | output_operand_lossage ("nested assembly dialect alternatives"); | |
3303 | else | |
3304 | dialect = 1; | |
3305 | ||
b729186a JL |
3306 | /* If we want the first dialect, do nothing. Otherwise, skip |
3307 | DIALECT_NUMBER of strings ending with '|'. */ | |
3308 | for (i = 0; i < dialect_number; i++) | |
3309 | { | |
463a8384 | 3310 | while (*p && *p != '}' && *p++ != '|') |
b729186a | 3311 | ; |
463a8384 BS |
3312 | if (*p == '}') |
3313 | break; | |
b729186a JL |
3314 | if (*p == '|') |
3315 | p++; | |
3316 | } | |
8554d9a4 JJ |
3317 | |
3318 | if (*p == '\0') | |
3319 | output_operand_lossage ("unterminated assembly dialect alternative"); | |
b729186a | 3320 | } |
3cf2715d DE |
3321 | break; |
3322 | ||
3323 | case '|': | |
8554d9a4 JJ |
3324 | if (dialect) |
3325 | { | |
3326 | /* Skip to close brace. */ | |
3327 | do | |
3328 | { | |
3329 | if (*p == '\0') | |
3330 | { | |
3331 | output_operand_lossage ("unterminated assembly dialect alternative"); | |
3332 | break; | |
3333 | } | |
ff81832f | 3334 | } |
8554d9a4 JJ |
3335 | while (*p++ != '}'); |
3336 | dialect = 0; | |
3337 | } | |
3338 | else | |
3339 | putc (c, asm_out_file); | |
3cf2715d DE |
3340 | break; |
3341 | ||
3342 | case '}': | |
8554d9a4 JJ |
3343 | if (! dialect) |
3344 | putc (c, asm_out_file); | |
3345 | dialect = 0; | |
3cf2715d DE |
3346 | break; |
3347 | #endif | |
3348 | ||
3349 | case '%': | |
3350 | /* %% outputs a single %. */ | |
3351 | if (*p == '%') | |
3352 | { | |
3353 | p++; | |
3354 | putc (c, asm_out_file); | |
3355 | } | |
3356 | /* %= outputs a number which is unique to each insn in the entire | |
3357 | compilation. This is useful for making local labels that are | |
3358 | referred to more than once in a given insn. */ | |
3359 | else if (*p == '=') | |
3360 | { | |
3361 | p++; | |
3362 | fprintf (asm_out_file, "%d", insn_counter); | |
3363 | } | |
3364 | /* % followed by a letter and some digits | |
3365 | outputs an operand in a special way depending on the letter. | |
3366 | Letters `acln' are implemented directly. | |
3367 | Other letters are passed to `output_operand' so that | |
3368 | the PRINT_OPERAND macro can define them. */ | |
0df6c2c7 | 3369 | else if (ISALPHA (*p)) |
3cf2715d DE |
3370 | { |
3371 | int letter = *p++; | |
3372 | c = atoi (p); | |
3373 | ||
0df6c2c7 | 3374 | if (! ISDIGIT (*p)) |
a52453cc | 3375 | output_operand_lossage ("operand number missing after %%-letter"); |
0d4903b8 RK |
3376 | else if (this_is_asm_operands |
3377 | && (c < 0 || (unsigned int) c >= insn_noperands)) | |
3cf2715d DE |
3378 | output_operand_lossage ("operand number out of range"); |
3379 | else if (letter == 'l') | |
3380 | output_asm_label (operands[c]); | |
3381 | else if (letter == 'a') | |
3382 | output_address (operands[c]); | |
3383 | else if (letter == 'c') | |
3384 | { | |
3385 | if (CONSTANT_ADDRESS_P (operands[c])) | |
3386 | output_addr_const (asm_out_file, operands[c]); | |
3387 | else | |
3388 | output_operand (operands[c], 'c'); | |
3389 | } | |
3390 | else if (letter == 'n') | |
3391 | { | |
3392 | if (GET_CODE (operands[c]) == CONST_INT) | |
21e3a81b | 3393 | fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, |
3cf2715d DE |
3394 | - INTVAL (operands[c])); |
3395 | else | |
3396 | { | |
3397 | putc ('-', asm_out_file); | |
3398 | output_addr_const (asm_out_file, operands[c]); | |
3399 | } | |
3400 | } | |
3401 | else | |
3402 | output_operand (operands[c], letter); | |
f5d927c0 | 3403 | |
4f9b4029 RK |
3404 | if (!opoutput[c]) |
3405 | oporder[ops++] = c; | |
3406 | opoutput[c] = 1; | |
0d4903b8 | 3407 | |
0df6c2c7 | 3408 | while (ISDIGIT (c = *p)) |
f5d927c0 | 3409 | p++; |
3cf2715d DE |
3410 | } |
3411 | /* % followed by a digit outputs an operand the default way. */ | |
0df6c2c7 | 3412 | else if (ISDIGIT (*p)) |
3cf2715d DE |
3413 | { |
3414 | c = atoi (p); | |
f5d927c0 KH |
3415 | if (this_is_asm_operands |
3416 | && (c < 0 || (unsigned int) c >= insn_noperands)) | |
3cf2715d DE |
3417 | output_operand_lossage ("operand number out of range"); |
3418 | else | |
3419 | output_operand (operands[c], 0); | |
0d4903b8 | 3420 | |
4f9b4029 RK |
3421 | if (!opoutput[c]) |
3422 | oporder[ops++] = c; | |
3423 | opoutput[c] = 1; | |
3424 | ||
0df6c2c7 | 3425 | while (ISDIGIT (c = *p)) |
f5d927c0 | 3426 | p++; |
3cf2715d DE |
3427 | } |
3428 | /* % followed by punctuation: output something for that | |
3429 | punctuation character alone, with no operand. | |
3430 | The PRINT_OPERAND macro decides what is actually done. */ | |
3431 | #ifdef PRINT_OPERAND_PUNCT_VALID_P | |
f5d927c0 | 3432 | else if (PRINT_OPERAND_PUNCT_VALID_P ((unsigned char) *p)) |
3cf2715d DE |
3433 | output_operand (NULL_RTX, *p++); |
3434 | #endif | |
3435 | else | |
3436 | output_operand_lossage ("invalid %%-code"); | |
3437 | break; | |
3438 | ||
3439 | default: | |
3440 | putc (c, asm_out_file); | |
3441 | } | |
3442 | ||
0d4903b8 RK |
3443 | /* Write out the variable names for operands, if we know them. */ |
3444 | if (flag_verbose_asm) | |
4f9b4029 | 3445 | output_asm_operand_names (operands, oporder, ops); |
0d4903b8 RK |
3446 | if (flag_print_asm_name) |
3447 | output_asm_name (); | |
3cf2715d DE |
3448 | |
3449 | putc ('\n', asm_out_file); | |
3450 | } | |
3451 | \f | |
3452 | /* Output a LABEL_REF, or a bare CODE_LABEL, as an assembler symbol. */ | |
3453 | ||
3454 | void | |
3455 | output_asm_label (x) | |
3456 | rtx x; | |
3457 | { | |
3458 | char buf[256]; | |
3459 | ||
3460 | if (GET_CODE (x) == LABEL_REF) | |
be1bb652 RH |
3461 | x = XEXP (x, 0); |
3462 | if (GET_CODE (x) == CODE_LABEL | |
3463 | || (GET_CODE (x) == NOTE | |
3464 | && NOTE_LINE_NUMBER (x) == NOTE_INSN_DELETED_LABEL)) | |
3cf2715d DE |
3465 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); |
3466 | else | |
a52453cc | 3467 | output_operand_lossage ("`%%l' operand isn't a label"); |
3cf2715d DE |
3468 | |
3469 | assemble_name (asm_out_file, buf); | |
3470 | } | |
3471 | ||
3472 | /* Print operand X using machine-dependent assembler syntax. | |
3473 | The macro PRINT_OPERAND is defined just to control this function. | |
3474 | CODE is a non-digit that preceded the operand-number in the % spec, | |
3475 | such as 'z' if the spec was `%z3'. CODE is 0 if there was no char | |
3476 | between the % and the digits. | |
3477 | When CODE is a non-letter, X is 0. | |
3478 | ||
3479 | The meanings of the letters are machine-dependent and controlled | |
3480 | by PRINT_OPERAND. */ | |
3481 | ||
3482 | static void | |
3483 | output_operand (x, code) | |
3484 | rtx x; | |
962f1324 | 3485 | int code ATTRIBUTE_UNUSED; |
3cf2715d DE |
3486 | { |
3487 | if (x && GET_CODE (x) == SUBREG) | |
49d801d3 | 3488 | x = alter_subreg (&x); |
3cf2715d DE |
3489 | |
3490 | /* If X is a pseudo-register, abort now rather than writing trash to the | |
3491 | assembler file. */ | |
3492 | ||
3493 | if (x && GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER) | |
3494 | abort (); | |
3495 | ||
3496 | PRINT_OPERAND (asm_out_file, x, code); | |
3497 | } | |
3498 | ||
3499 | /* Print a memory reference operand for address X | |
3500 | using machine-dependent assembler syntax. | |
3501 | The macro PRINT_OPERAND_ADDRESS exists just to control this function. */ | |
3502 | ||
3503 | void | |
3504 | output_address (x) | |
3505 | rtx x; | |
3506 | { | |
49d801d3 | 3507 | walk_alter_subreg (&x); |
3cf2715d DE |
3508 | PRINT_OPERAND_ADDRESS (asm_out_file, x); |
3509 | } | |
3510 | \f | |
3511 | /* Print an integer constant expression in assembler syntax. | |
3512 | Addition and subtraction are the only arithmetic | |
3513 | that may appear in these expressions. */ | |
3514 | ||
3515 | void | |
3516 | output_addr_const (file, x) | |
3517 | FILE *file; | |
3518 | rtx x; | |
3519 | { | |
3520 | char buf[256]; | |
3521 | ||
3522 | restart: | |
3523 | switch (GET_CODE (x)) | |
3524 | { | |
3525 | case PC: | |
eac50d7a | 3526 | putc ('.', file); |
3cf2715d DE |
3527 | break; |
3528 | ||
3529 | case SYMBOL_REF: | |
99c8c61c AO |
3530 | #ifdef ASM_OUTPUT_SYMBOL_REF |
3531 | ASM_OUTPUT_SYMBOL_REF (file, x); | |
3532 | #else | |
3cf2715d | 3533 | assemble_name (file, XSTR (x, 0)); |
99c8c61c | 3534 | #endif |
3cf2715d DE |
3535 | break; |
3536 | ||
3537 | case LABEL_REF: | |
422be3c3 AO |
3538 | x = XEXP (x, 0); |
3539 | /* Fall through. */ | |
3cf2715d DE |
3540 | case CODE_LABEL: |
3541 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); | |
2f0b7af6 GK |
3542 | #ifdef ASM_OUTPUT_LABEL_REF |
3543 | ASM_OUTPUT_LABEL_REF (file, buf); | |
3544 | #else | |
3cf2715d | 3545 | assemble_name (file, buf); |
2f0b7af6 | 3546 | #endif |
3cf2715d DE |
3547 | break; |
3548 | ||
3549 | case CONST_INT: | |
21e3a81b | 3550 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); |
3cf2715d DE |
3551 | break; |
3552 | ||
3553 | case CONST: | |
3554 | /* This used to output parentheses around the expression, | |
3555 | but that does not work on the 386 (either ATT or BSD assembler). */ | |
3556 | output_addr_const (file, XEXP (x, 0)); | |
3557 | break; | |
3558 | ||
3559 | case CONST_DOUBLE: | |
3560 | if (GET_MODE (x) == VOIDmode) | |
3561 | { | |
3562 | /* We can use %d if the number is one word and positive. */ | |
3563 | if (CONST_DOUBLE_HIGH (x)) | |
21e3a81b | 3564 | fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX, |
3cf2715d | 3565 | CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); |
f5d927c0 | 3566 | else if (CONST_DOUBLE_LOW (x) < 0) |
21e3a81b | 3567 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); |
3cf2715d | 3568 | else |
21e3a81b | 3569 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x)); |
3cf2715d DE |
3570 | } |
3571 | else | |
3572 | /* We can't handle floating point constants; | |
3573 | PRINT_OPERAND must handle them. */ | |
3574 | output_operand_lossage ("floating constant misused"); | |
3575 | break; | |
3576 | ||
3577 | case PLUS: | |
3578 | /* Some assemblers need integer constants to appear last (eg masm). */ | |
3579 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) | |
3580 | { | |
3581 | output_addr_const (file, XEXP (x, 1)); | |
3582 | if (INTVAL (XEXP (x, 0)) >= 0) | |
3583 | fprintf (file, "+"); | |
3584 | output_addr_const (file, XEXP (x, 0)); | |
3585 | } | |
3586 | else | |
3587 | { | |
3588 | output_addr_const (file, XEXP (x, 0)); | |
08106825 AO |
3589 | if (GET_CODE (XEXP (x, 1)) != CONST_INT |
3590 | || INTVAL (XEXP (x, 1)) >= 0) | |
3cf2715d DE |
3591 | fprintf (file, "+"); |
3592 | output_addr_const (file, XEXP (x, 1)); | |
3593 | } | |
3594 | break; | |
3595 | ||
3596 | case MINUS: | |
3597 | /* Avoid outputting things like x-x or x+5-x, | |
3598 | since some assemblers can't handle that. */ | |
3599 | x = simplify_subtraction (x); | |
3600 | if (GET_CODE (x) != MINUS) | |
3601 | goto restart; | |
3602 | ||
3603 | output_addr_const (file, XEXP (x, 0)); | |
3604 | fprintf (file, "-"); | |
301d03af RS |
3605 | if ((GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0) |
3606 | || GET_CODE (XEXP (x, 1)) == PC | |
3607 | || GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
3608 | output_addr_const (file, XEXP (x, 1)); | |
3609 | else | |
3cf2715d | 3610 | { |
17b53c33 | 3611 | fputs (targetm.asm_out.open_paren, file); |
3cf2715d | 3612 | output_addr_const (file, XEXP (x, 1)); |
17b53c33 | 3613 | fputs (targetm.asm_out.close_paren, file); |
3cf2715d | 3614 | } |
3cf2715d DE |
3615 | break; |
3616 | ||
3617 | case ZERO_EXTEND: | |
3618 | case SIGN_EXTEND: | |
fdf473ae | 3619 | case SUBREG: |
3cf2715d DE |
3620 | output_addr_const (file, XEXP (x, 0)); |
3621 | break; | |
3622 | ||
3623 | default: | |
422be3c3 AO |
3624 | #ifdef OUTPUT_ADDR_CONST_EXTRA |
3625 | OUTPUT_ADDR_CONST_EXTRA (file, x, fail); | |
3626 | break; | |
3627 | ||
3628 | fail: | |
3629 | #endif | |
3cf2715d DE |
3630 | output_operand_lossage ("invalid expression as operand"); |
3631 | } | |
3632 | } | |
3633 | \f | |
3634 | /* A poor man's fprintf, with the added features of %I, %R, %L, and %U. | |
3635 | %R prints the value of REGISTER_PREFIX. | |
3636 | %L prints the value of LOCAL_LABEL_PREFIX. | |
3637 | %U prints the value of USER_LABEL_PREFIX. | |
3638 | %I prints the value of IMMEDIATE_PREFIX. | |
3639 | %O runs ASM_OUTPUT_OPCODE to transform what follows in the string. | |
3640 | Also supported are %d, %x, %s, %e, %f, %g and %%. | |
3641 | ||
3642 | We handle alternate assembler dialects here, just like output_asm_insn. */ | |
3643 | ||
3644 | void | |
711d877c | 3645 | asm_fprintf VPARAMS ((FILE *file, const char *p, ...)) |
3cf2715d | 3646 | { |
3cf2715d DE |
3647 | char buf[10]; |
3648 | char *q, c; | |
3cf2715d | 3649 | |
7a75edb7 AJ |
3650 | VA_OPEN (argptr, p); |
3651 | VA_FIXEDARG (argptr, FILE *, file); | |
3652 | VA_FIXEDARG (argptr, const char *, p); | |
3cf2715d DE |
3653 | |
3654 | buf[0] = '%'; | |
3655 | ||
b729186a | 3656 | while ((c = *p++)) |
3cf2715d DE |
3657 | switch (c) |
3658 | { | |
3659 | #ifdef ASSEMBLER_DIALECT | |
3660 | case '{': | |
b729186a JL |
3661 | { |
3662 | int i; | |
3cf2715d | 3663 | |
b729186a JL |
3664 | /* If we want the first dialect, do nothing. Otherwise, skip |
3665 | DIALECT_NUMBER of strings ending with '|'. */ | |
3666 | for (i = 0; i < dialect_number; i++) | |
3667 | { | |
3668 | while (*p && *p++ != '|') | |
3669 | ; | |
3670 | ||
3671 | if (*p == '|') | |
3672 | p++; | |
f5d927c0 | 3673 | } |
b729186a | 3674 | } |
3cf2715d DE |
3675 | break; |
3676 | ||
3677 | case '|': | |
3678 | /* Skip to close brace. */ | |
3679 | while (*p && *p++ != '}') | |
3680 | ; | |
3681 | break; | |
3682 | ||
3683 | case '}': | |
3684 | break; | |
3685 | #endif | |
3686 | ||
3687 | case '%': | |
3688 | c = *p++; | |
3689 | q = &buf[1]; | |
0df6c2c7 | 3690 | while (ISDIGIT (c) || c == '.') |
3cf2715d DE |
3691 | { |
3692 | *q++ = c; | |
3693 | c = *p++; | |
3694 | } | |
3695 | switch (c) | |
3696 | { | |
3697 | case '%': | |
3698 | fprintf (file, "%%"); | |
3699 | break; | |
3700 | ||
3701 | case 'd': case 'i': case 'u': | |
3702 | case 'x': case 'p': case 'X': | |
3703 | case 'o': | |
3704 | *q++ = c; | |
3705 | *q = 0; | |
3706 | fprintf (file, buf, va_arg (argptr, int)); | |
3707 | break; | |
3708 | ||
3709 | case 'w': | |
3710 | /* This is a prefix to the 'd', 'i', 'u', 'x', 'p', and 'X' cases, | |
3711 | but we do not check for those cases. It means that the value | |
3712 | is a HOST_WIDE_INT, which may be either `int' or `long'. */ | |
3713 | ||
21e3a81b RK |
3714 | #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT |
3715 | #else | |
3716 | #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG | |
3717 | *q++ = 'l'; | |
3718 | #else | |
3719 | *q++ = 'l'; | |
3cf2715d | 3720 | *q++ = 'l'; |
21e3a81b | 3721 | #endif |
3cf2715d DE |
3722 | #endif |
3723 | ||
3724 | *q++ = *p++; | |
3725 | *q = 0; | |
3726 | fprintf (file, buf, va_arg (argptr, HOST_WIDE_INT)); | |
3727 | break; | |
3728 | ||
3729 | case 'l': | |
3730 | *q++ = c; | |
3731 | *q++ = *p++; | |
3732 | *q = 0; | |
3733 | fprintf (file, buf, va_arg (argptr, long)); | |
3734 | break; | |
3735 | ||
3736 | case 'e': | |
3737 | case 'f': | |
3738 | case 'g': | |
3739 | *q++ = c; | |
3740 | *q = 0; | |
3741 | fprintf (file, buf, va_arg (argptr, double)); | |
3742 | break; | |
3743 | ||
3744 | case 's': | |
3745 | *q++ = c; | |
3746 | *q = 0; | |
3747 | fprintf (file, buf, va_arg (argptr, char *)); | |
3748 | break; | |
3749 | ||
3750 | case 'O': | |
3751 | #ifdef ASM_OUTPUT_OPCODE | |
3752 | ASM_OUTPUT_OPCODE (asm_out_file, p); | |
3753 | #endif | |
3754 | break; | |
3755 | ||
3756 | case 'R': | |
3757 | #ifdef REGISTER_PREFIX | |
3758 | fprintf (file, "%s", REGISTER_PREFIX); | |
3759 | #endif | |
3760 | break; | |
3761 | ||
3762 | case 'I': | |
3763 | #ifdef IMMEDIATE_PREFIX | |
3764 | fprintf (file, "%s", IMMEDIATE_PREFIX); | |
3765 | #endif | |
3766 | break; | |
3767 | ||
3768 | case 'L': | |
3769 | #ifdef LOCAL_LABEL_PREFIX | |
3770 | fprintf (file, "%s", LOCAL_LABEL_PREFIX); | |
3771 | #endif | |
3772 | break; | |
3773 | ||
3774 | case 'U': | |
19283265 | 3775 | fputs (user_label_prefix, file); |
3cf2715d DE |
3776 | break; |
3777 | ||
fe0503ea NC |
3778 | #ifdef ASM_FPRINTF_EXTENSIONS |
3779 | /* Upper case letters are reserved for general use by asm_fprintf | |
3780 | and so are not available to target specific code. In order to | |
3781 | prevent the ASM_FPRINTF_EXTENSIONS macro from using them then, | |
3782 | they are defined here. As they get turned into real extensions | |
3783 | to asm_fprintf they should be removed from this list. */ | |
3784 | case 'A': case 'B': case 'C': case 'D': case 'E': | |
3785 | case 'F': case 'G': case 'H': case 'J': case 'K': | |
3786 | case 'M': case 'N': case 'P': case 'Q': case 'S': | |
3787 | case 'T': case 'V': case 'W': case 'Y': case 'Z': | |
3788 | break; | |
f5d927c0 | 3789 | |
fe0503ea NC |
3790 | ASM_FPRINTF_EXTENSIONS (file, argptr, p) |
3791 | #endif | |
3cf2715d DE |
3792 | default: |
3793 | abort (); | |
3794 | } | |
3795 | break; | |
3796 | ||
3797 | default: | |
3798 | fputc (c, file); | |
3799 | } | |
7a75edb7 | 3800 | VA_CLOSE (argptr); |
3cf2715d DE |
3801 | } |
3802 | \f | |
3803 | /* Split up a CONST_DOUBLE or integer constant rtx | |
3804 | into two rtx's for single words, | |
3805 | storing in *FIRST the word that comes first in memory in the target | |
3806 | and in *SECOND the other. */ | |
3807 | ||
3808 | void | |
3809 | split_double (value, first, second) | |
3810 | rtx value; | |
3811 | rtx *first, *second; | |
3812 | { | |
3813 | if (GET_CODE (value) == CONST_INT) | |
3814 | { | |
5a1a6efd | 3815 | if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD)) |
f76b9db2 | 3816 | { |
5a1a6efd | 3817 | /* In this case the CONST_INT holds both target words. |
27eef9ce JC |
3818 | Extract the bits from it into two word-sized pieces. |
3819 | Sign extend each half to HOST_WIDE_INT. */ | |
7f251dee AO |
3820 | unsigned HOST_WIDE_INT low, high; |
3821 | unsigned HOST_WIDE_INT mask, sign_bit, sign_extend; | |
3822 | ||
3823 | /* Set sign_bit to the most significant bit of a word. */ | |
3824 | sign_bit = 1; | |
3825 | sign_bit <<= BITS_PER_WORD - 1; | |
3826 | ||
3827 | /* Set mask so that all bits of the word are set. We could | |
3828 | have used 1 << BITS_PER_WORD instead of basing the | |
3829 | calculation on sign_bit. However, on machines where | |
3830 | HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a | |
3831 | compiler warning, even though the code would never be | |
3832 | executed. */ | |
3833 | mask = sign_bit << 1; | |
3834 | mask--; | |
3835 | ||
3836 | /* Set sign_extend as any remaining bits. */ | |
3837 | sign_extend = ~mask; | |
f5d927c0 | 3838 | |
7f251dee AO |
3839 | /* Pick the lower word and sign-extend it. */ |
3840 | low = INTVAL (value); | |
3841 | low &= mask; | |
3842 | if (low & sign_bit) | |
3843 | low |= sign_extend; | |
3844 | ||
3845 | /* Pick the higher word, shifted to the least significant | |
3846 | bits, and sign-extend it. */ | |
3847 | high = INTVAL (value); | |
3848 | high >>= BITS_PER_WORD - 1; | |
3849 | high >>= 1; | |
3850 | high &= mask; | |
3851 | if (high & sign_bit) | |
3852 | high |= sign_extend; | |
3853 | ||
3854 | /* Store the words in the target machine order. */ | |
5a1a6efd RK |
3855 | if (WORDS_BIG_ENDIAN) |
3856 | { | |
7f251dee AO |
3857 | *first = GEN_INT (high); |
3858 | *second = GEN_INT (low); | |
5a1a6efd RK |
3859 | } |
3860 | else | |
3861 | { | |
7f251dee AO |
3862 | *first = GEN_INT (low); |
3863 | *second = GEN_INT (high); | |
5a1a6efd | 3864 | } |
f76b9db2 ILT |
3865 | } |
3866 | else | |
3867 | { | |
5a1a6efd RK |
3868 | /* The rule for using CONST_INT for a wider mode |
3869 | is that we regard the value as signed. | |
3870 | So sign-extend it. */ | |
3871 | rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx); | |
3872 | if (WORDS_BIG_ENDIAN) | |
3873 | { | |
3874 | *first = high; | |
3875 | *second = value; | |
3876 | } | |
3877 | else | |
3878 | { | |
3879 | *first = value; | |
3880 | *second = high; | |
3881 | } | |
f76b9db2 | 3882 | } |
3cf2715d DE |
3883 | } |
3884 | else if (GET_CODE (value) != CONST_DOUBLE) | |
3885 | { | |
f76b9db2 ILT |
3886 | if (WORDS_BIG_ENDIAN) |
3887 | { | |
3888 | *first = const0_rtx; | |
3889 | *second = value; | |
3890 | } | |
3891 | else | |
3892 | { | |
3893 | *first = value; | |
3894 | *second = const0_rtx; | |
3895 | } | |
3cf2715d DE |
3896 | } |
3897 | else if (GET_MODE (value) == VOIDmode | |
3898 | /* This is the old way we did CONST_DOUBLE integers. */ | |
3899 | || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT) | |
3900 | { | |
3901 | /* In an integer, the words are defined as most and least significant. | |
3902 | So order them by the target's convention. */ | |
f76b9db2 ILT |
3903 | if (WORDS_BIG_ENDIAN) |
3904 | { | |
3905 | *first = GEN_INT (CONST_DOUBLE_HIGH (value)); | |
3906 | *second = GEN_INT (CONST_DOUBLE_LOW (value)); | |
3907 | } | |
3908 | else | |
3909 | { | |
3910 | *first = GEN_INT (CONST_DOUBLE_LOW (value)); | |
3911 | *second = GEN_INT (CONST_DOUBLE_HIGH (value)); | |
3912 | } | |
3cf2715d DE |
3913 | } |
3914 | else | |
3915 | { | |
f5d927c0 KH |
3916 | REAL_VALUE_TYPE r; |
3917 | long l[2]; | |
3cf2715d DE |
3918 | REAL_VALUE_FROM_CONST_DOUBLE (r, value); |
3919 | ||
3920 | /* Note, this converts the REAL_VALUE_TYPE to the target's | |
3921 | format, splits up the floating point double and outputs | |
3922 | exactly 32 bits of it into each of l[0] and l[1] -- | |
0f41302f | 3923 | not necessarily BITS_PER_WORD bits. */ |
3cf2715d DE |
3924 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); |
3925 | ||
b5a3eb84 JW |
3926 | /* If 32 bits is an entire word for the target, but not for the host, |
3927 | then sign-extend on the host so that the number will look the same | |
3928 | way on the host that it would on the target. See for instance | |
3929 | simplify_unary_operation. The #if is needed to avoid compiler | |
3930 | warnings. */ | |
3931 | ||
3932 | #if HOST_BITS_PER_LONG > 32 | |
3933 | if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32) | |
3934 | { | |
3935 | if (l[0] & ((long) 1 << 31)) | |
3936 | l[0] |= ((long) (-1) << 32); | |
3937 | if (l[1] & ((long) 1 << 31)) | |
3938 | l[1] |= ((long) (-1) << 32); | |
3939 | } | |
3940 | #endif | |
3941 | ||
3cf2715d DE |
3942 | *first = GEN_INT ((HOST_WIDE_INT) l[0]); |
3943 | *second = GEN_INT ((HOST_WIDE_INT) l[1]); | |
3cf2715d DE |
3944 | } |
3945 | } | |
3946 | \f | |
3947 | /* Return nonzero if this function has no function calls. */ | |
3948 | ||
3949 | int | |
3950 | leaf_function_p () | |
3951 | { | |
3952 | rtx insn; | |
b660f82f | 3953 | rtx link; |
3cf2715d | 3954 | |
70f4f91c | 3955 | if (current_function_profile || profile_arc_flag) |
3cf2715d DE |
3956 | return 0; |
3957 | ||
3958 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3959 | { | |
7d167afd JJ |
3960 | if (GET_CODE (insn) == CALL_INSN |
3961 | && ! SIBLING_CALL_P (insn)) | |
3cf2715d DE |
3962 | return 0; |
3963 | if (GET_CODE (insn) == INSN | |
3964 | && GET_CODE (PATTERN (insn)) == SEQUENCE | |
0a1c58a2 JL |
3965 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN |
3966 | && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0))) | |
3cf2715d DE |
3967 | return 0; |
3968 | } | |
b660f82f JW |
3969 | for (link = current_function_epilogue_delay_list; |
3970 | link; | |
3971 | link = XEXP (link, 1)) | |
3cf2715d | 3972 | { |
b660f82f JW |
3973 | insn = XEXP (link, 0); |
3974 | ||
3975 | if (GET_CODE (insn) == CALL_INSN | |
7d167afd | 3976 | && ! SIBLING_CALL_P (insn)) |
3cf2715d | 3977 | return 0; |
b660f82f JW |
3978 | if (GET_CODE (insn) == INSN |
3979 | && GET_CODE (PATTERN (insn)) == SEQUENCE | |
3980 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN | |
3981 | && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0))) | |
3cf2715d DE |
3982 | return 0; |
3983 | } | |
3984 | ||
3985 | return 1; | |
3986 | } | |
3987 | ||
ef6257cd JH |
3988 | /* Return 1 if branch is an forward branch. |
3989 | Uses insn_shuid array, so it works only in the final pass. May be used by | |
3990 | output templates to customary add branch prediction hints. | |
3991 | */ | |
3992 | int | |
3993 | final_forward_branch_p (insn) | |
3994 | rtx insn; | |
3995 | { | |
3996 | int insn_id, label_id; | |
3997 | if (!uid_shuid) | |
3998 | abort (); | |
3999 | insn_id = INSN_SHUID (insn); | |
4000 | label_id = INSN_SHUID (JUMP_LABEL (insn)); | |
4001 | /* We've hit some insns that does not have id information available. */ | |
4002 | if (!insn_id || !label_id) | |
4003 | abort (); | |
4004 | return insn_id < label_id; | |
4005 | } | |
4006 | ||
3cf2715d DE |
4007 | /* On some machines, a function with no call insns |
4008 | can run faster if it doesn't create its own register window. | |
4009 | When output, the leaf function should use only the "output" | |
4010 | registers. Ordinarily, the function would be compiled to use | |
4011 | the "input" registers to find its arguments; it is a candidate | |
4012 | for leaf treatment if it uses only the "input" registers. | |
4013 | Leaf function treatment means renumbering so the function | |
4014 | uses the "output" registers instead. */ | |
4015 | ||
4016 | #ifdef LEAF_REGISTERS | |
4017 | ||
3cf2715d DE |
4018 | /* Return 1 if this function uses only the registers that can be |
4019 | safely renumbered. */ | |
4020 | ||
4021 | int | |
4022 | only_leaf_regs_used () | |
4023 | { | |
4024 | int i; | |
7d167afd | 4025 | char *permitted_reg_in_leaf_functions = LEAF_REGISTERS; |
3cf2715d DE |
4026 | |
4027 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
e5e809f4 JL |
4028 | if ((regs_ever_live[i] || global_regs[i]) |
4029 | && ! permitted_reg_in_leaf_functions[i]) | |
4030 | return 0; | |
4031 | ||
4032 | if (current_function_uses_pic_offset_table | |
4033 | && pic_offset_table_rtx != 0 | |
4034 | && GET_CODE (pic_offset_table_rtx) == REG | |
4035 | && ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)]) | |
4036 | return 0; | |
4037 | ||
3cf2715d DE |
4038 | return 1; |
4039 | } | |
4040 | ||
4041 | /* Scan all instructions and renumber all registers into those | |
4042 | available in leaf functions. */ | |
4043 | ||
4044 | static void | |
4045 | leaf_renumber_regs (first) | |
4046 | rtx first; | |
4047 | { | |
4048 | rtx insn; | |
4049 | ||
4050 | /* Renumber only the actual patterns. | |
4051 | The reg-notes can contain frame pointer refs, | |
4052 | and renumbering them could crash, and should not be needed. */ | |
4053 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 4054 | if (INSN_P (insn)) |
3cf2715d | 4055 | leaf_renumber_regs_insn (PATTERN (insn)); |
f5d927c0 KH |
4056 | for (insn = current_function_epilogue_delay_list; |
4057 | insn; | |
4058 | insn = XEXP (insn, 1)) | |
2c3c49de | 4059 | if (INSN_P (XEXP (insn, 0))) |
3cf2715d DE |
4060 | leaf_renumber_regs_insn (PATTERN (XEXP (insn, 0))); |
4061 | } | |
4062 | ||
4063 | /* Scan IN_RTX and its subexpressions, and renumber all regs into those | |
4064 | available in leaf functions. */ | |
4065 | ||
4066 | void | |
4067 | leaf_renumber_regs_insn (in_rtx) | |
b3694847 | 4068 | rtx in_rtx; |
3cf2715d | 4069 | { |
b3694847 SS |
4070 | int i, j; |
4071 | const char *format_ptr; | |
3cf2715d DE |
4072 | |
4073 | if (in_rtx == 0) | |
4074 | return; | |
4075 | ||
4076 | /* Renumber all input-registers into output-registers. | |
4077 | renumbered_regs would be 1 for an output-register; | |
4078 | they */ | |
4079 | ||
4080 | if (GET_CODE (in_rtx) == REG) | |
4081 | { | |
4082 | int newreg; | |
4083 | ||
4084 | /* Don't renumber the same reg twice. */ | |
4085 | if (in_rtx->used) | |
4086 | return; | |
4087 | ||
4088 | newreg = REGNO (in_rtx); | |
4089 | /* Don't try to renumber pseudo regs. It is possible for a pseudo reg | |
4090 | to reach here as part of a REG_NOTE. */ | |
4091 | if (newreg >= FIRST_PSEUDO_REGISTER) | |
4092 | { | |
4093 | in_rtx->used = 1; | |
4094 | return; | |
4095 | } | |
4096 | newreg = LEAF_REG_REMAP (newreg); | |
4097 | if (newreg < 0) | |
4098 | abort (); | |
4099 | regs_ever_live[REGNO (in_rtx)] = 0; | |
4100 | regs_ever_live[newreg] = 1; | |
4101 | REGNO (in_rtx) = newreg; | |
4102 | in_rtx->used = 1; | |
4103 | } | |
4104 | ||
2c3c49de | 4105 | if (INSN_P (in_rtx)) |
3cf2715d DE |
4106 | { |
4107 | /* Inside a SEQUENCE, we find insns. | |
4108 | Renumber just the patterns of these insns, | |
4109 | just as we do for the top-level insns. */ | |
4110 | leaf_renumber_regs_insn (PATTERN (in_rtx)); | |
4111 | return; | |
4112 | } | |
4113 | ||
4114 | format_ptr = GET_RTX_FORMAT (GET_CODE (in_rtx)); | |
4115 | ||
4116 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (in_rtx)); i++) | |
4117 | switch (*format_ptr++) | |
4118 | { | |
4119 | case 'e': | |
4120 | leaf_renumber_regs_insn (XEXP (in_rtx, i)); | |
4121 | break; | |
4122 | ||
4123 | case 'E': | |
4124 | if (NULL != XVEC (in_rtx, i)) | |
4125 | { | |
4126 | for (j = 0; j < XVECLEN (in_rtx, i); j++) | |
4127 | leaf_renumber_regs_insn (XVECEXP (in_rtx, i, j)); | |
4128 | } | |
4129 | break; | |
4130 | ||
4131 | case 'S': | |
4132 | case 's': | |
4133 | case '0': | |
4134 | case 'i': | |
4135 | case 'w': | |
4136 | case 'n': | |
4137 | case 'u': | |
4138 | break; | |
4139 | ||
4140 | default: | |
4141 | abort (); | |
4142 | } | |
4143 | } | |
4144 | #endif |