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d7429b6a 1/* Data flow analysis for GNU compiler.
c9bacfdb 2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1e4e95d6 3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
d7429b6a 4
1322177d 5This file is part of GCC.
d7429b6a 6
1322177d
LB
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
d7429b6a 11
1322177d
LB
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
d7429b6a
RK
16
17You should have received a copy of the GNU General Public License
1322177d
LB
18along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
d7429b6a 21
e881bb1b
RH
22/* This file contains the data flow analysis pass of the compiler. It
23 computes data flow information which tells combine_instructions
24 which insns to consider combining and controls register allocation.
d7429b6a 25
e881bb1b
RH
26 Additional data flow information that is too bulky to record is
27 generated during the analysis, and is used at that time to create
28 autoincrement and autodecrement addressing.
d7429b6a
RK
29
30 The first step is dividing the function into basic blocks.
31 find_basic_blocks does this. Then life_analysis determines
32 where each register is live and where it is dead.
33
34 ** find_basic_blocks **
35
e881bb1b
RH
36 find_basic_blocks divides the current function's rtl into basic
37 blocks and constructs the CFG. The blocks are recorded in the
38 basic_block_info array; the CFG exists in the edge structures
39 referenced by the blocks.
d7429b6a 40
e881bb1b 41 find_basic_blocks also finds any unreachable loops and deletes them.
d7429b6a
RK
42
43 ** life_analysis **
44
45 life_analysis is called immediately after find_basic_blocks.
46 It uses the basic block information to determine where each
47 hard or pseudo register is live.
48
49 ** live-register info **
50
51 The information about where each register is live is in two parts:
e881bb1b 52 the REG_NOTES of insns, and the vector basic_block->global_live_at_start.
d7429b6a 53
e881bb1b
RH
54 basic_block->global_live_at_start has an element for each basic
55 block, and the element is a bit-vector with a bit for each hard or
56 pseudo register. The bit is 1 if the register is live at the
57 beginning of the basic block.
d7429b6a 58
c9bacfdb 59 Two types of elements can be added to an insn's REG_NOTES.
d7429b6a
RK
60 A REG_DEAD note is added to an insn's REG_NOTES for any register
61 that meets both of two conditions: The value in the register is not
62 needed in subsequent insns and the insn does not replace the value in
63 the register (in the case of multi-word hard registers, the value in
64 each register must be replaced by the insn to avoid a REG_DEAD note).
65
66 In the vast majority of cases, an object in a REG_DEAD note will be
67 used somewhere in the insn. The (rare) exception to this is if an
68 insn uses a multi-word hard register and only some of the registers are
69 needed in subsequent insns. In that case, REG_DEAD notes will be
70 provided for those hard registers that are not subsequently needed.
71 Partial REG_DEAD notes of this type do not occur when an insn sets
72 only some of the hard registers used in such a multi-word operand;
73 omitting REG_DEAD notes for objects stored in an insn is optional and
74 the desire to do so does not justify the complexity of the partial
75 REG_DEAD notes.
76
77 REG_UNUSED notes are added for each register that is set by the insn
78 but is unused subsequently (if every register set by the insn is unused
79 and the insn does not reference memory or have some other side-effect,
80 the insn is deleted instead). If only part of a multi-word hard
81 register is used in a subsequent insn, REG_UNUSED notes are made for
82 the parts that will not be used.
83
84 To determine which registers are live after any insn, one can
85 start from the beginning of the basic block and scan insns, noting
86 which registers are set by each insn and which die there.
87
88 ** Other actions of life_analysis **
89
90 life_analysis sets up the LOG_LINKS fields of insns because the
91 information needed to do so is readily available.
92
93 life_analysis deletes insns whose only effect is to store a value
94 that is never used.
95
96 life_analysis notices cases where a reference to a register as
97 a memory address can be combined with a preceding or following
98 incrementation or decrementation of the register. The separate
99 instruction to increment or decrement is deleted and the address
100 is changed to a POST_INC or similar rtx.
101
102 Each time an incrementing or decrementing address is created,
103 a REG_INC element is added to the insn's REG_NOTES list.
104
105 life_analysis fills in certain vectors containing information about
d4b60170
RK
106 register usage: REG_N_REFS, REG_N_DEATHS, REG_N_SETS, REG_LIVE_LENGTH,
107 REG_N_CALLS_CROSSED and REG_BASIC_BLOCK.
fdb8a883
JW
108
109 life_analysis sets current_function_sp_is_unchanging if the function
110 doesn't modify the stack pointer. */
e881bb1b 111
c9bacfdb 112/* TODO:
e881bb1b
RH
113
114 Split out from life_analysis:
115 - local property discovery (bb->local_live, bb->local_set)
116 - global property computation
117 - log links creation
118 - pre/post modify transformation
119*/
d7429b6a 120\f
d7429b6a 121#include "config.h"
670ee920 122#include "system.h"
d3a923ee 123#include "tree.h"
d7429b6a 124#include "rtl.h"
6baf1cc8 125#include "tm_p.h"
efc9bd41 126#include "hard-reg-set.h"
d7429b6a
RK
127#include "basic-block.h"
128#include "insn-config.h"
129#include "regs.h"
d7429b6a
RK
130#include "flags.h"
131#include "output.h"
b384405b 132#include "function.h"
3d195391 133#include "except.h"
2e107e9e 134#include "toplev.h"
79c9824e 135#include "recog.h"
11bdd2ae 136#include "expr.h"
b53978a3 137#include "ssa.h"
4793dca1 138#include "timevar.h"
d7429b6a
RK
139
140#include "obstack.h"
11ae508b 141#include "splay-tree.h"
c5c76735 142
e881bb1b
RH
143/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
144 the stack pointer does not matter. The value is tested only in
145 functions that have frame pointers.
146 No definition is equivalent to always zero. */
147#ifndef EXIT_IGNORE_STACK
148#define EXIT_IGNORE_STACK 0
149#endif
150
d3a923ee
RH
151#ifndef HAVE_epilogue
152#define HAVE_epilogue 0
153#endif
d3a923ee
RH
154#ifndef HAVE_prologue
155#define HAVE_prologue 0
156#endif
0a1c58a2
JL
157#ifndef HAVE_sibcall_epilogue
158#define HAVE_sibcall_epilogue 0
159#endif
d3a923ee 160
2a3e384f
RH
161#ifndef LOCAL_REGNO
162#define LOCAL_REGNO(REGNO) 0
163#endif
164#ifndef EPILOGUE_USES
165#define EPILOGUE_USES(REGNO) 0
166#endif
15b5aef3
RH
167#ifndef EH_USES
168#define EH_USES(REGNO) 0
169#endif
2a3e384f 170
7e6d8ba1
AH
171#ifdef HAVE_conditional_execution
172#ifndef REVERSE_CONDEXEC_PREDICATES_P
173#define REVERSE_CONDEXEC_PREDICATES_P(x, y) ((x) == reverse_condition (y))
174#endif
175#endif
176
56744d1a
JL
177/* Nonzero if the second flow pass has completed. */
178int flow2_completed;
179
d7429b6a
RK
180/* Maximum register number used in this function, plus one. */
181
182int max_regno;
183
b1f21e0a 184/* Indexed by n, giving various register information */
d7429b6a 185
6feacd09 186varray_type reg_n_info;
d7429b6a 187
d7429b6a
RK
188/* Size of a regset for the current function,
189 in (1) bytes and (2) elements. */
190
191int regset_bytes;
192int regset_size;
193
d7429b6a 194/* Regset of regs live when calls to `setjmp'-like functions happen. */
e881bb1b 195/* ??? Does this exist only for the setjmp-clobbered warning message? */
d7429b6a
RK
196
197regset regs_live_at_setjmp;
198
199/* List made of EXPR_LIST rtx's which gives pairs of pseudo registers
200 that have to go in the same hard reg.
201 The first two regs in the list are a pair, and the next two
202 are another pair, etc. */
203rtx regs_may_share;
204
21c7361e
AJ
205/* Callback that determines if it's ok for a function to have no
206 noreturn attribute. */
207int (*lang_missing_noreturn_ok_p) PARAMS ((tree));
208
d7429b6a
RK
209/* Set of registers that may be eliminable. These are handled specially
210 in updating regs_ever_live. */
211
212static HARD_REG_SET elim_reg_set;
213
11ae508b
RH
214/* Holds information for tracking conditional register life information. */
215struct reg_cond_life_info
216{
685af3af 217 /* A boolean expression of conditions under which a register is dead. */
11ae508b 218 rtx condition;
685af3af
JW
219 /* Conditions under which a register is dead at the basic block end. */
220 rtx orig_condition;
221
222 /* A boolean expression of conditions under which a register has been
223 stored into. */
224 rtx stores;
11ae508b
RH
225
226 /* ??? Could store mask of bytes that are dead, so that we could finally
227 track lifetimes of multi-word registers accessed via subregs. */
228};
229
62828c00
RH
230/* For use in communicating between propagate_block and its subroutines.
231 Holds all information needed to compute life and def-use information. */
232
233struct propagate_block_info
234{
235 /* The basic block we're considering. */
236 basic_block bb;
237
238 /* Bit N is set if register N is conditionally or unconditionally live. */
239 regset reg_live;
240
9785c68d
RH
241 /* Bit N is set if register N is set this insn. */
242 regset new_set;
8e3f9094 243
62828c00
RH
244 /* Element N is the next insn that uses (hard or pseudo) register N
245 within the current basic block; or zero, if there is no such insn. */
246 rtx *reg_next_use;
247
248 /* Contains a list of all the MEMs we are tracking for dead store
249 elimination. */
250 rtx mem_set_list;
251
7dfc0fbe
BS
252 /* If non-null, record the set of registers set unconditionally in the
253 basic block. */
62828c00
RH
254 regset local_set;
255
7dfc0fbe
BS
256 /* If non-null, record the set of registers set conditionally in the
257 basic block. */
258 regset cond_local_set;
259
11ae508b
RH
260#ifdef HAVE_conditional_execution
261 /* Indexed by register number, holds a reg_cond_life_info for each
262 register that is not unconditionally live or dead. */
263 splay_tree reg_cond_dead;
264
265 /* Bit N is set if register N is in an expression in reg_cond_dead. */
266 regset reg_cond_reg;
267#endif
268
0875baa0
RH
269 /* The length of mem_set_list. */
270 int mem_set_list_len;
271
62828c00
RH
272 /* Non-zero if the value of CC0 is live. */
273 int cc0_live;
274
275 /* Flags controling the set of information propagate_block collects. */
276 int flags;
277};
278
3dec4024
JH
279/* Number of dead insns removed. */
280static int ndead;
281
0875baa0
RH
282/* Maximum length of pbi->mem_set_list before we start dropping
283 new elements on the floor. */
284#define MAX_MEM_SET_LIST_LEN 100
285
d7429b6a 286/* Forward declarations */
711d877c 287static int verify_wide_reg_1 PARAMS ((rtx *, void *));
08ef5437 288static void verify_wide_reg PARAMS ((int, basic_block));
711d877c 289static void verify_local_live_at_start PARAMS ((regset, basic_block));
3ea8083f
JL
290static void notice_stack_pointer_modification_1 PARAMS ((rtx, rtx, void *));
291static void notice_stack_pointer_modification PARAMS ((rtx));
c13fde05 292static void mark_reg PARAMS ((rtx, void *));
711d877c 293static void mark_regs_live_at_end PARAMS ((regset));
4e872036 294static int set_phi_alternative_reg PARAMS ((rtx, int, int, void *));
711d877c 295static void calculate_global_regs_live PARAMS ((sbitmap, sbitmap, int));
3dec4024 296static void propagate_block_delete_insn PARAMS ((rtx));
607a6500 297static rtx propagate_block_delete_libcall PARAMS ((rtx, rtx));
62828c00
RH
298static int insn_dead_p PARAMS ((struct propagate_block_info *,
299 rtx, int, rtx));
300static int libcall_dead_p PARAMS ((struct propagate_block_info *,
01fbc97d 301 rtx, rtx));
62828c00 302static void mark_set_regs PARAMS ((struct propagate_block_info *,
8e3f9094 303 rtx, rtx));
62828c00 304static void mark_set_1 PARAMS ((struct propagate_block_info *,
b4593d17
RH
305 enum rtx_code, rtx, rtx,
306 rtx, int));
0626ef8a
AM
307static int find_regno_partial PARAMS ((rtx *, void *));
308
11ae508b
RH
309#ifdef HAVE_conditional_execution
310static int mark_regno_cond_dead PARAMS ((struct propagate_block_info *,
311 int, rtx));
312static void free_reg_cond_life_info PARAMS ((splay_tree_value));
313static int flush_reg_cond_reg_1 PARAMS ((splay_tree_node, void *));
314static void flush_reg_cond_reg PARAMS ((struct propagate_block_info *,
315 int));
288c2c9e
BS
316static rtx elim_reg_cond PARAMS ((rtx, unsigned int));
317static rtx ior_reg_cond PARAMS ((rtx, rtx, int));
11ae508b 318static rtx not_reg_cond PARAMS ((rtx));
288c2c9e 319static rtx and_reg_cond PARAMS ((rtx, rtx, int));
11ae508b 320#endif
1d300e19 321#ifdef AUTO_INC_DEC
4b983fdc
RH
322static void attempt_auto_inc PARAMS ((struct propagate_block_info *,
323 rtx, rtx, rtx, rtx, rtx));
62828c00
RH
324static void find_auto_inc PARAMS ((struct propagate_block_info *,
325 rtx, rtx));
326static int try_pre_increment_1 PARAMS ((struct propagate_block_info *,
327 rtx));
711d877c 328static int try_pre_increment PARAMS ((rtx, rtx, HOST_WIDE_INT));
1d300e19 329#endif
62828c00 330static void mark_used_reg PARAMS ((struct propagate_block_info *,
8e3f9094 331 rtx, rtx, rtx));
62828c00 332static void mark_used_regs PARAMS ((struct propagate_block_info *,
8e3f9094 333 rtx, rtx, rtx));
711d877c
KG
334void dump_flow_info PARAMS ((FILE *));
335void debug_flow_info PARAMS ((void));
91d84fad
RH
336static void add_to_mem_set_list PARAMS ((struct propagate_block_info *,
337 rtx));
fe4b3c79 338static int invalidate_mems_from_autoinc PARAMS ((rtx *, void *));
1288c070
RH
339static void invalidate_mems_from_set PARAMS ((struct propagate_block_info *,
340 rtx));
b932f770 341static void clear_log_links PARAMS ((sbitmap));
d7429b6a 342\f
5ece9746 343
b313a0fe
RH
344void
345check_function_return_warnings ()
346{
347 if (warn_missing_noreturn
348 && !TREE_THIS_VOLATILE (cfun->decl)
21c7361e
AJ
349 && EXIT_BLOCK_PTR->pred == NULL
350 && (lang_missing_noreturn_ok_p
351 && !lang_missing_noreturn_ok_p (cfun->decl)))
b313a0fe
RH
352 warning ("function might be possible candidate for attribute `noreturn'");
353
354 /* If we have a path to EXIT, then we do return. */
355 if (TREE_THIS_VOLATILE (cfun->decl)
356 && EXIT_BLOCK_PTR->pred != NULL)
357 warning ("`noreturn' function does return");
358
359 /* If the clobber_return_insn appears in some basic block, then we
360 do reach the end without returning a value. */
361 else if (warn_return_type
362 && cfun->x_clobber_return_insn != NULL
363 && EXIT_BLOCK_PTR->pred != NULL)
364 {
365 int max_uid = get_max_uid ();
366
367 /* If clobber_return_insn was excised by jump1, then renumber_insns
368 can make max_uid smaller than the number still recorded in our rtx.
369 That's fine, since this is a quick way of verifying that the insn
370 is no longer in the chain. */
371 if (INSN_UID (cfun->x_clobber_return_insn) < max_uid)
372 {
ba4f7968
JH
373 rtx insn;
374
375 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
376 if (insn == cfun->x_clobber_return_insn)
377 {
378 warning ("control reaches end of non-void function");
379 break;
380 }
b313a0fe
RH
381 }
382 }
383}
402209ff
JH
384\f
385/* Return the INSN immediately following the NOTE_INSN_BASIC_BLOCK
386 note associated with the BLOCK. */
387
388rtx
389first_insn_after_basic_block_note (block)
390 basic_block block;
391{
392 rtx insn;
b313a0fe 393
402209ff
JH
394 /* Get the first instruction in the block. */
395 insn = block->head;
dc2ede84 396
402209ff
JH
397 if (insn == NULL_RTX)
398 return NULL_RTX;
399 if (GET_CODE (insn) == CODE_LABEL)
400 insn = NEXT_INSN (insn);
401 if (!NOTE_INSN_BASIC_BLOCK_P (insn))
402 abort ();
403
404 return NEXT_INSN (insn);
405}
406\f
407/* Perform data flow analysis.
408 F is the first insn of the function; FLAGS is a set of PROP_* flags
409 to be used in accumulating flow info. */
410
411void
412life_analysis (f, file, flags)
e881bb1b 413 rtx f;
402209ff
JH
414 FILE *file;
415 int flags;
e881bb1b 416{
402209ff 417#ifdef ELIMINABLE_REGS
b3694847 418 int i;
8b60264b 419 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
402209ff 420#endif
dc2ede84 421
402209ff
JH
422 /* Record which registers will be eliminated. We use this in
423 mark_used_regs. */
e881bb1b 424
402209ff 425 CLEAR_HARD_REG_SET (elim_reg_set);
314883b8 426
402209ff
JH
427#ifdef ELIMINABLE_REGS
428 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
429 SET_HARD_REG_BIT (elim_reg_set, eliminables[i].from);
430#else
431 SET_HARD_REG_BIT (elim_reg_set, FRAME_POINTER_REGNUM);
432#endif
52a11cbf 433
402209ff
JH
434 if (! optimize)
435 flags &= ~(PROP_LOG_LINKS | PROP_AUTOINC | PROP_ALLOW_CFG_CHANGES);
52a11cbf 436
402209ff
JH
437 /* The post-reload life analysis have (on a global basis) the same
438 registers live as was computed by reload itself. elimination
439 Otherwise offsets and such may be incorrect.
e881bb1b 440
402209ff
JH
441 Reload will make some registers as live even though they do not
442 appear in the rtl.
e881bb1b 443
402209ff
JH
444 We don't want to create new auto-incs after reload, since they
445 are unlikely to be useful and can cause problems with shared
446 stack slots. */
447 if (reload_completed)
448 flags &= ~(PROP_REG_INFO | PROP_AUTOINC);
e881bb1b 449
402209ff 450 /* We want alias analysis information for local dead store elimination. */
5149f070 451 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
402209ff 452 init_alias_analysis ();
dc2ede84 453
402209ff
JH
454 /* Always remove no-op moves. Do this before other processing so
455 that we don't have to keep re-scanning them. */
456 delete_noop_moves (f);
1bc48f82 457
402209ff
JH
458 /* Some targets can emit simpler epilogues if they know that sp was
459 not ever modified during the function. After reload, of course,
460 we've already emitted the epilogue so there's no sense searching. */
461 if (! reload_completed)
462 notice_stack_pointer_modification (f);
1bc48f82 463
402209ff
JH
464 /* Allocate and zero out data structures that will record the
465 data from lifetime analysis. */
466 allocate_reg_life_data ();
467 allocate_bb_life_data ();
1bc48f82 468
402209ff
JH
469 /* Find the set of registers live on function exit. */
470 mark_regs_live_at_end (EXIT_BLOCK_PTR->global_live_at_start);
1bc48f82 471
402209ff
JH
472 /* "Update" life info from zero. It'd be nice to begin the
473 relaxation with just the exit and noreturn blocks, but that set
474 is not immediately handy. */
c9bacfdb 475
402209ff
JH
476 if (flags & PROP_REG_INFO)
477 memset (regs_ever_live, 0, sizeof (regs_ever_live));
478 update_life_info (NULL, UPDATE_LIFE_GLOBAL, flags);
1bc48f82 479
402209ff 480 /* Clean up. */
5149f070 481 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
402209ff 482 end_alias_analysis ();
1bc48f82 483
402209ff
JH
484 if (file)
485 dump_flow_info (file);
0005550b 486
402209ff 487 free_basic_block_vars (1);
a686dbf8 488
402209ff
JH
489 /* Removing dead insns should've made jumptables really dead. */
490 delete_dead_jumptables ();
491}
0005550b 492
402209ff 493/* A subroutine of verify_wide_reg, called through for_each_rtx.
08ef5437
RH
494 Search for REGNO. If found, return 2 if it is not wider than
495 word_mode. */
a686dbf8 496
402209ff
JH
497static int
498verify_wide_reg_1 (px, pregno)
499 rtx *px;
500 void *pregno;
501{
502 rtx x = *px;
503 unsigned int regno = *(int *) pregno;
134d3a2e 504
402209ff 505 if (GET_CODE (x) == REG && REGNO (x) == regno)
134d3a2e 506 {
402209ff 507 if (GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD)
08ef5437 508 return 2;
402209ff 509 return 1;
134d3a2e 510 }
402209ff 511 return 0;
a686dbf8
JH
512}
513
402209ff 514/* A subroutine of verify_local_live_at_start. Search through insns
08ef5437 515 of BB looking for register REGNO. */
8329b5ec 516
be1bb652 517static void
08ef5437 518verify_wide_reg (regno, bb)
402209ff 519 int regno;
08ef5437 520 basic_block bb;
e881bb1b 521{
08ef5437
RH
522 rtx head = bb->head, end = bb->end;
523
402209ff 524 while (1)
e881bb1b 525 {
08ef5437
RH
526 if (INSN_P (head))
527 {
528 int r = for_each_rtx (&PATTERN (head), verify_wide_reg_1, &regno);
529 if (r == 1)
530 return;
531 if (r == 2)
532 break;
533 }
402209ff
JH
534 if (head == end)
535 break;
536 head = NEXT_INSN (head);
537 }
d7429b6a 538
402209ff 539 if (rtl_dump_file)
08ef5437
RH
540 {
541 fprintf (rtl_dump_file, "Register %d died unexpectedly.\n", regno);
542 dump_bb (bb, rtl_dump_file);
543 }
544 abort ();
402209ff 545}
314883b8 546
402209ff
JH
547/* A subroutine of update_life_info. Verify that there are no untoward
548 changes in live_at_start during a local update. */
d06c6389 549
402209ff
JH
550static void
551verify_local_live_at_start (new_live_at_start, bb)
552 regset new_live_at_start;
553 basic_block bb;
554{
555 if (reload_completed)
556 {
557 /* After reload, there are no pseudos, nor subregs of multi-word
558 registers. The regsets should exactly match. */
559 if (! REG_SET_EQUAL_P (new_live_at_start, bb->global_live_at_start))
560 {
561 if (rtl_dump_file)
e881bb1b 562 {
402209ff 563 fprintf (rtl_dump_file,
08ef5437 564 "live_at_start mismatch in bb %d, aborting\nNew:\n",
0b17ab2f 565 bb->index);
402209ff 566 debug_bitmap_file (rtl_dump_file, new_live_at_start);
08ef5437
RH
567 fputs ("Old:\n", rtl_dump_file);
568 dump_bb (bb, rtl_dump_file);
e881bb1b 569 }
08ef5437 570 abort ();
e881bb1b 571 }
402209ff
JH
572 }
573 else
574 {
575 int i;
d7429b6a 576
402209ff
JH
577 /* Find the set of changed registers. */
578 XOR_REG_SET (new_live_at_start, bb->global_live_at_start);
421382ac 579
402209ff
JH
580 EXECUTE_IF_SET_IN_REG_SET (new_live_at_start, 0, i,
581 {
dd3f0101 582 /* No registers should die. */
402209ff
JH
583 if (REGNO_REG_SET_P (bb->global_live_at_start, i))
584 {
585 if (rtl_dump_file)
08ef5437
RH
586 {
587 fprintf (rtl_dump_file,
588 "Register %d died unexpectedly.\n", i);
589 dump_bb (bb, rtl_dump_file);
590 }
591 abort ();
402209ff 592 }
c9bacfdb 593
dd3f0101 594 /* Verify that the now-live register is wider than word_mode. */
08ef5437 595 verify_wide_reg (i, bb);
402209ff 596 });
e881bb1b 597 }
402209ff 598}
d7429b6a 599
402209ff
JH
600/* Updates life information starting with the basic blocks set in BLOCKS.
601 If BLOCKS is null, consider it to be the universal set.
af14ce9c 602
402209ff
JH
603 If EXTENT is UPDATE_LIFE_LOCAL, such as after splitting or peepholeing,
604 we are only expecting local modifications to basic blocks. If we find
605 extra registers live at the beginning of a block, then we either killed
606 useful data, or we have a broken split that wants data not provided.
607 If we find registers removed from live_at_start, that means we have
608 a broken peephole that is killing a register it shouldn't.
af14ce9c 609
402209ff
JH
610 ??? This is not true in one situation -- when a pre-reload splitter
611 generates subregs of a multi-word pseudo, current life analysis will
612 lose the kill. So we _can_ have a pseudo go live. How irritating.
5ece9746 613
402209ff
JH
614 Including PROP_REG_INFO does not properly refresh regs_ever_live
615 unless the caller resets it to zero. */
19d3c25c 616
3dec4024 617int
402209ff
JH
618update_life_info (blocks, extent, prop_flags)
619 sbitmap blocks;
620 enum update_life_extent extent;
621 int prop_flags;
19d3c25c 622{
402209ff
JH
623 regset tmp;
624 regset_head tmp_head;
006844a3 625 int i;
566576e7 626 int stabilized_prop_flags = prop_flags;
e0082a72 627 basic_block bb;
006844a3 628
402209ff 629 tmp = INITIALIZE_REG_SET (tmp_head);
3dec4024 630 ndead = 0;
2cade2ad 631
b932f770
JH
632 timevar_push ((extent == UPDATE_LIFE_LOCAL || blocks)
633 ? TV_LIFE_UPDATE : TV_LIFE);
634
402209ff
JH
635 /* Changes to the CFG are only allowed when
636 doing a global update for the entire CFG. */
637 if ((prop_flags & PROP_ALLOW_CFG_CHANGES)
638 && (extent == UPDATE_LIFE_LOCAL || blocks))
639 abort ();
006844a3 640
402209ff
JH
641 /* For a global update, we go through the relaxation process again. */
642 if (extent != UPDATE_LIFE_LOCAL)
643 {
644 for ( ; ; )
645 {
646 int changed = 0;
19d3c25c 647
402209ff
JH
648 calculate_global_regs_live (blocks, blocks,
649 prop_flags & (PROP_SCAN_DEAD_CODE
5149f070 650 | PROP_SCAN_DEAD_STORES
402209ff 651 | PROP_ALLOW_CFG_CHANGES));
5ece9746 652
402209ff
JH
653 if ((prop_flags & (PROP_KILL_DEAD_CODE | PROP_ALLOW_CFG_CHANGES))
654 != (PROP_KILL_DEAD_CODE | PROP_ALLOW_CFG_CHANGES))
655 break;
e881bb1b 656
402209ff
JH
657 /* Removing dead code may allow the CFG to be simplified which
658 in turn may allow for further dead code detection / removal. */
e0082a72 659 FOR_EACH_BB_REVERSE (bb)
402209ff 660 {
402209ff
JH
661 COPY_REG_SET (tmp, bb->global_live_at_end);
662 changed |= propagate_block (bb, tmp, NULL, NULL,
663 prop_flags & (PROP_SCAN_DEAD_CODE
5149f070 664 | PROP_SCAN_DEAD_STORES
402209ff
JH
665 | PROP_KILL_DEAD_CODE));
666 }
47095bfc 667
566576e7
HPN
668 /* Don't pass PROP_SCAN_DEAD_CODE or PROP_KILL_DEAD_CODE to
669 subsequent propagate_block calls, since removing or acting as
670 removing dead code can affect global register liveness, which
671 is supposed to be finalized for this call after this loop. */
672 stabilized_prop_flags
5149f070
JH
673 &= ~(PROP_SCAN_DEAD_CODE | PROP_SCAN_DEAD_STORES
674 | PROP_KILL_DEAD_CODE);
566576e7
HPN
675
676 if (! changed)
402209ff 677 break;
566576e7
HPN
678
679 /* We repeat regardless of what cleanup_cfg says. If there were
680 instructions deleted above, that might have been only a
681 partial improvement (see MAX_MEM_SET_LIST_LEN usage).
682 Further improvement may be possible. */
683 cleanup_cfg (CLEANUP_EXPENSIVE);
e881bb1b 684 }
47095bfc 685
402209ff
JH
686 /* If asked, remove notes from the blocks we'll update. */
687 if (extent == UPDATE_LIFE_GLOBAL_RM_NOTES)
688 count_or_remove_death_notes (blocks, 1);
689 }
690
38c1593d
JH
691 /* Clear log links in case we are asked to (re)compute them. */
692 if (prop_flags & PROP_LOG_LINKS)
693 clear_log_links (blocks);
694
402209ff
JH
695 if (blocks)
696 {
697 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
698 {
e0082a72 699 bb = BASIC_BLOCK (i);
402209ff
JH
700
701 COPY_REG_SET (tmp, bb->global_live_at_end);
566576e7 702 propagate_block (bb, tmp, NULL, NULL, stabilized_prop_flags);
402209ff
JH
703
704 if (extent == UPDATE_LIFE_LOCAL)
705 verify_local_live_at_start (tmp, bb);
706 });
5ece9746 707 }
e881bb1b
RH
708 else
709 {
e0082a72 710 FOR_EACH_BB_REVERSE (bb)
355e4ec4 711 {
402209ff 712 COPY_REG_SET (tmp, bb->global_live_at_end);
566576e7
HPN
713
714 propagate_block (bb, tmp, NULL, NULL, stabilized_prop_flags);
421382ac 715
402209ff
JH
716 if (extent == UPDATE_LIFE_LOCAL)
717 verify_local_live_at_start (tmp, bb);
e881bb1b 718 }
e881bb1b
RH
719 }
720
402209ff 721 FREE_REG_SET (tmp);
eeea333e 722
402209ff
JH
723 if (prop_flags & PROP_REG_INFO)
724 {
725 /* The only pseudos that are live at the beginning of the function
726 are those that were not set anywhere in the function. local-alloc
727 doesn't know how to handle these correctly, so mark them as not
728 local to any one basic block. */
729 EXECUTE_IF_SET_IN_REG_SET (ENTRY_BLOCK_PTR->global_live_at_end,
730 FIRST_PSEUDO_REGISTER, i,
731 { REG_BASIC_BLOCK (i) = REG_BLOCK_GLOBAL; });
e881bb1b 732
402209ff
JH
733 /* We have a problem with any pseudoreg that lives across the setjmp.
734 ANSI says that if a user variable does not change in value between
735 the setjmp and the longjmp, then the longjmp preserves it. This
736 includes longjmp from a place where the pseudo appears dead.
737 (In principle, the value still exists if it is in scope.)
738 If the pseudo goes in a hard reg, some other value may occupy
739 that hard reg where this pseudo is dead, thus clobbering the pseudo.
740 Conclusion: such a pseudo must not go in a hard reg. */
741 EXECUTE_IF_SET_IN_REG_SET (regs_live_at_setjmp,
742 FIRST_PSEUDO_REGISTER, i,
743 {
744 if (regno_reg_rtx[i] != 0)
745 {
746 REG_LIVE_LENGTH (i) = -1;
747 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
748 }
749 });
750 }
b932f770
JH
751 timevar_pop ((extent == UPDATE_LIFE_LOCAL || blocks)
752 ? TV_LIFE_UPDATE : TV_LIFE);
3dec4024
JH
753 if (ndead && rtl_dump_file)
754 fprintf (rtl_dump_file, "deleted %i dead insns\n", ndead);
755 return ndead;
421382ac 756}
b62c8881 757
38c1593d
JH
758/* Update life information in all blocks where BB_DIRTY is set. */
759
3dec4024 760int
38c1593d
JH
761update_life_info_in_dirty_blocks (extent, prop_flags)
762 enum update_life_extent extent;
763 int prop_flags;
764{
d55bc081 765 sbitmap update_life_blocks = sbitmap_alloc (last_basic_block);
38c1593d 766 int n = 0;
e0082a72 767 basic_block bb;
0a2ed1f1 768 int retval = 0;
38c1593d
JH
769
770 sbitmap_zero (update_life_blocks);
e0082a72 771 FOR_EACH_BB (bb)
e0e577a2
RH
772 {
773 if (extent == UPDATE_LIFE_LOCAL)
774 {
775 if (bb->flags & BB_DIRTY)
776 {
777 SET_BIT (update_life_blocks, bb->index);
778 n++;
779 }
780 }
781 else
782 {
783 /* ??? Bootstrap with -march=pentium4 fails to terminate
784 with only a partial life update. */
785 SET_BIT (update_life_blocks, bb->index);
786 if (bb->flags & BB_DIRTY)
787 n++;
788 }
789 }
38c1593d
JH
790
791 if (n)
0a2ed1f1 792 retval = update_life_info (update_life_blocks, extent, prop_flags);
38c1593d
JH
793
794 sbitmap_free (update_life_blocks);
0a2ed1f1 795 return retval;
38c1593d
JH
796}
797
402209ff 798/* Free the variables allocated by find_basic_blocks.
b62c8881 799
402209ff 800 KEEP_HEAD_END_P is non-zero if basic_block_info is not to be freed. */
421382ac 801
2307e372 802void
402209ff
JH
803free_basic_block_vars (keep_head_end_p)
804 int keep_head_end_p;
421382ac 805{
402209ff
JH
806 if (! keep_head_end_p)
807 {
808 if (basic_block_info)
e881bb1b 809 {
402209ff
JH
810 clear_edges ();
811 VARRAY_FREE (basic_block_info);
e881bb1b 812 }
0b17ab2f 813 n_basic_blocks = 0;
d55bc081 814 last_basic_block = 0;
402209ff
JH
815
816 ENTRY_BLOCK_PTR->aux = NULL;
817 ENTRY_BLOCK_PTR->global_live_at_end = NULL;
818 EXIT_BLOCK_PTR->aux = NULL;
819 EXIT_BLOCK_PTR->global_live_at_start = NULL;
e881bb1b 820 }
421382ac
BS
821}
822
402209ff 823/* Delete any insns that copy a register to itself. */
421382ac 824
3dec4024 825int
402209ff
JH
826delete_noop_moves (f)
827 rtx f ATTRIBUTE_UNUSED;
421382ac 828{
402209ff
JH
829 rtx insn, next;
830 basic_block bb;
3dec4024 831 int nnoops = 0;
421382ac 832
e0082a72 833 FOR_EACH_BB (bb)
421382ac 834 {
402209ff 835 for (insn = bb->head; insn != NEXT_INSN (bb->end); insn = next)
421382ac 836 {
402209ff
JH
837 next = NEXT_INSN (insn);
838 if (INSN_P (insn) && noop_move_p (insn))
839 {
eb9d8e4d
JW
840 rtx note;
841
842 /* If we're about to remove the first insn of a libcall
843 then move the libcall note to the next real insn and
844 update the retval note. */
845 if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
846 && XEXP (note, 0) != insn)
847 {
848 rtx new_libcall_insn = next_real_insn (insn);
849 rtx retval_note = find_reg_note (XEXP (note, 0),
850 REG_RETVAL, NULL_RTX);
851 REG_NOTES (new_libcall_insn)
852 = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
853 REG_NOTES (new_libcall_insn));
854 XEXP (retval_note, 0) = new_libcall_insn;
855 }
856
3dec4024
JH
857 delete_insn_and_edges (insn);
858 nnoops++;
402209ff 859 }
421382ac
BS
860 }
861 }
3dec4024
JH
862 if (nnoops && rtl_dump_file)
863 fprintf (rtl_dump_file, "deleted %i noop moves", nnoops);
864 return nnoops;
421382ac
BS
865}
866
402209ff 867/* Delete any jump tables never referenced. We can't delete them at the
eaec9b3d 868 time of removing tablejump insn as they are referenced by the preceding
402209ff
JH
869 insns computing the destination, so we delay deleting and garbagecollect
870 them once life information is computed. */
0010687d 871void
402209ff
JH
872delete_dead_jumptables ()
873{
874 rtx insn, next;
875 for (insn = get_insns (); insn; insn = next)
421382ac 876 {
402209ff
JH
877 next = NEXT_INSN (insn);
878 if (GET_CODE (insn) == CODE_LABEL
967bd823 879 && LABEL_NUSES (insn) == LABEL_PRESERVE_P (insn)
402209ff
JH
880 && GET_CODE (next) == JUMP_INSN
881 && (GET_CODE (PATTERN (next)) == ADDR_VEC
882 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))
e881bb1b 883 {
402209ff
JH
884 if (rtl_dump_file)
885 fprintf (rtl_dump_file, "Dead jumptable %i removed\n", INSN_UID (insn));
53c17031
JH
886 delete_insn (NEXT_INSN (insn));
887 delete_insn (insn);
402209ff 888 next = NEXT_INSN (next);
e881bb1b 889 }
dc2ede84 890 }
e881bb1b
RH
891}
892
402209ff
JH
893/* Determine if the stack pointer is constant over the life of the function.
894 Only useful before prologues have been emitted. */
e881bb1b
RH
895
896static void
402209ff
JH
897notice_stack_pointer_modification_1 (x, pat, data)
898 rtx x;
899 rtx pat ATTRIBUTE_UNUSED;
900 void *data ATTRIBUTE_UNUSED;
e881bb1b 901{
402209ff
JH
902 if (x == stack_pointer_rtx
903 /* The stack pointer is only modified indirectly as the result
904 of a push until later in flow. See the comments in rtl.texi
905 regarding Embedded Side-Effects on Addresses. */
906 || (GET_CODE (x) == MEM
907 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'a'
908 && XEXP (XEXP (x, 0), 0) == stack_pointer_rtx))
909 current_function_sp_is_unchanging = 0;
e881bb1b 910}
e6cfb550 911
336a6399 912static void
402209ff
JH
913notice_stack_pointer_modification (f)
914 rtx f;
e881bb1b 915{
402209ff 916 rtx insn;
e881bb1b 917
402209ff
JH
918 /* Assume that the stack pointer is unchanging if alloca hasn't
919 been used. */
920 current_function_sp_is_unchanging = !current_function_calls_alloca;
921 if (! current_function_sp_is_unchanging)
922 return;
e881bb1b 923
402209ff 924 for (insn = f; insn; insn = NEXT_INSN (insn))
e6cfb550 925 {
402209ff 926 if (INSN_P (insn))
e881bb1b 927 {
402209ff
JH
928 /* Check if insn modifies the stack pointer. */
929 note_stores (PATTERN (insn), notice_stack_pointer_modification_1,
930 NULL);
931 if (! current_function_sp_is_unchanging)
932 return;
e881bb1b 933 }
e6cfb550 934 }
e881bb1b 935}
0ecf09f9 936
402209ff
JH
937/* Mark a register in SET. Hard registers in large modes get all
938 of their component registers set as well. */
0ecf09f9 939
402209ff
JH
940static void
941mark_reg (reg, xset)
942 rtx reg;
943 void *xset;
0ecf09f9 944{
402209ff
JH
945 regset set = (regset) xset;
946 int regno = REGNO (reg);
0ecf09f9 947
402209ff
JH
948 if (GET_MODE (reg) == BLKmode)
949 abort ();
0ecf09f9 950
402209ff
JH
951 SET_REGNO_REG_SET (set, regno);
952 if (regno < FIRST_PSEUDO_REGISTER)
0ecf09f9 953 {
402209ff
JH
954 int n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
955 while (--n > 0)
956 SET_REGNO_REG_SET (set, regno + n);
0ecf09f9 957 }
0ecf09f9 958}
c586192c 959
402209ff
JH
960/* Mark those regs which are needed at the end of the function as live
961 at the end of the last basic block. */
c586192c 962
402209ff
JH
963static void
964mark_regs_live_at_end (set)
965 regset set;
966{
967 unsigned int i;
c586192c 968
402209ff
JH
969 /* If exiting needs the right stack value, consider the stack pointer
970 live at the end of the function. */
971 if ((HAVE_epilogue && reload_completed)
972 || ! EXIT_IGNORE_STACK
973 || (! FRAME_POINTER_REQUIRED
974 && ! current_function_calls_alloca
975 && flag_omit_frame_pointer)
976 || current_function_sp_is_unchanging)
c586192c 977 {
402209ff 978 SET_REGNO_REG_SET (set, STACK_POINTER_REGNUM);
c586192c
MH
979 }
980
402209ff
JH
981 /* Mark the frame pointer if needed at the end of the function. If
982 we end up eliminating it, it will be removed from the live list
983 of each basic block by reload. */
c586192c 984
402209ff 985 if (! reload_completed || frame_pointer_needed)
a686dbf8 986 {
402209ff
JH
987 SET_REGNO_REG_SET (set, FRAME_POINTER_REGNUM);
988#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
989 /* If they are different, also mark the hard frame pointer as live. */
990 if (! LOCAL_REGNO (HARD_FRAME_POINTER_REGNUM))
dd3f0101 991 SET_REGNO_REG_SET (set, HARD_FRAME_POINTER_REGNUM);
402209ff 992#endif
a686dbf8 993 }
c586192c 994
402209ff
JH
995#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
996 /* Many architectures have a GP register even without flag_pic.
997 Assume the pic register is not in use, or will be handled by
998 other means, if it is not fixed. */
999 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
1000 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
1001 SET_REGNO_REG_SET (set, PIC_OFFSET_TABLE_REGNUM);
1002#endif
c586192c 1003
402209ff
JH
1004 /* Mark all global registers, and all registers used by the epilogue
1005 as being live at the end of the function since they may be
1006 referenced by our caller. */
1007 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1008 if (global_regs[i] || EPILOGUE_USES (i))
1009 SET_REGNO_REG_SET (set, i);
c586192c 1010
402209ff 1011 if (HAVE_epilogue && reload_completed)
ca9fef16 1012 {
402209ff
JH
1013 /* Mark all call-saved registers that we actually used. */
1014 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1015 if (regs_ever_live[i] && ! LOCAL_REGNO (i)
1016 && ! TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
1017 SET_REGNO_REG_SET (set, i);
ca9fef16 1018 }
b9b2c339 1019
402209ff
JH
1020#ifdef EH_RETURN_DATA_REGNO
1021 /* Mark the registers that will contain data for the handler. */
1022 if (reload_completed && current_function_calls_eh_return)
1023 for (i = 0; ; ++i)
1024 {
1025 unsigned regno = EH_RETURN_DATA_REGNO(i);
1026 if (regno == INVALID_REGNUM)
1027 break;
1028 SET_REGNO_REG_SET (set, regno);
1029 }
e9644cfe 1030#endif
402209ff
JH
1031#ifdef EH_RETURN_STACKADJ_RTX
1032 if ((! HAVE_epilogue || ! reload_completed)
1033 && current_function_calls_eh_return)
7a442791 1034 {
402209ff
JH
1035 rtx tmp = EH_RETURN_STACKADJ_RTX;
1036 if (tmp && REG_P (tmp))
1037 mark_reg (tmp, set);
7a442791 1038 }
402209ff
JH
1039#endif
1040#ifdef EH_RETURN_HANDLER_RTX
1041 if ((! HAVE_epilogue || ! reload_completed)
1042 && current_function_calls_eh_return)
2b2c8b3e 1043 {
402209ff
JH
1044 rtx tmp = EH_RETURN_HANDLER_RTX;
1045 if (tmp && REG_P (tmp))
1046 mark_reg (tmp, set);
2b2c8b3e 1047 }
402209ff 1048#endif
7a442791 1049
402209ff
JH
1050 /* Mark function return value. */
1051 diddle_return_value (mark_reg, set);
7a442791
JH
1052}
1053
402209ff
JH
1054/* Callback function for for_each_successor_phi. DATA is a regset.
1055 Sets the SRC_REGNO, the regno of the phi alternative for phi node
1056 INSN, in the regset. */
d69d0316 1057
402209ff
JH
1058static int
1059set_phi_alternative_reg (insn, dest_regno, src_regno, data)
1060 rtx insn ATTRIBUTE_UNUSED;
1061 int dest_regno ATTRIBUTE_UNUSED;
1062 int src_regno;
1063 void *data;
d69d0316 1064{
402209ff
JH
1065 regset live = (regset) data;
1066 SET_REGNO_REG_SET (live, src_regno);
1067 return 0;
d69d0316
JH
1068}
1069
402209ff
JH
1070/* Propagate global life info around the graph of basic blocks. Begin
1071 considering blocks with their corresponding bit set in BLOCKS_IN.
1072 If BLOCKS_IN is null, consider it the universal set.
b9b2c339 1073
402209ff 1074 BLOCKS_OUT is set for every block that was changed. */
b9b2c339 1075
402209ff
JH
1076static void
1077calculate_global_regs_live (blocks_in, blocks_out, flags)
1078 sbitmap blocks_in, blocks_out;
1079 int flags;
1080{
e0082a72 1081 basic_block *queue, *qhead, *qtail, *qend, bb;
f3ea5f6a
RH
1082 regset tmp, new_live_at_end, invalidated_by_call;
1083 regset_head tmp_head, invalidated_by_call_head;
402209ff
JH
1084 regset_head new_live_at_end_head;
1085 int i;
b9b2c339 1086
1540f9eb
JH
1087 /* Some passes used to forget clear aux field of basic block causing
1088 sick behaviour here. */
1089#ifdef ENABLE_CHECKING
e0082a72
ZD
1090 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR, NULL, next_bb)
1091 if (bb->aux)
1540f9eb
JH
1092 abort ();
1093#endif
1094
402209ff
JH
1095 tmp = INITIALIZE_REG_SET (tmp_head);
1096 new_live_at_end = INITIALIZE_REG_SET (new_live_at_end_head);
f3ea5f6a 1097 invalidated_by_call = INITIALIZE_REG_SET (invalidated_by_call_head);
b9b2c339 1098
d6a7951f 1099 /* Inconveniently, this is only readily available in hard reg set form. */
402209ff 1100 for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
f3ea5f6a
RH
1101 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
1102 SET_REGNO_REG_SET (invalidated_by_call, i);
2b2c8b3e 1103
402209ff
JH
1104 /* Create a worklist. Allocate an extra slot for ENTRY_BLOCK, and one
1105 because the `head == tail' style test for an empty queue doesn't
1106 work with a full queue. */
0b17ab2f 1107 queue = (basic_block *) xmalloc ((n_basic_blocks + 2) * sizeof (*queue));
402209ff 1108 qtail = queue;
0b17ab2f 1109 qhead = qend = queue + n_basic_blocks + 2;
2b2c8b3e 1110
402209ff
JH
1111 /* Queue the blocks set in the initial mask. Do this in reverse block
1112 number order so that we are more likely for the first round to do
1113 useful work. We use AUX non-null to flag that the block is queued. */
1114 if (blocks_in)
c319629b 1115 {
e0082a72
ZD
1116 FOR_EACH_BB (bb)
1117 if (TEST_BIT (blocks_in, bb->index))
1118 {
1119 *--qhead = bb;
1120 bb->aux = bb;
1121 }
2b2c8b3e 1122 }
402209ff 1123 else
e881bb1b 1124 {
bf77398c 1125 FOR_EACH_BB (bb)
402209ff 1126 {
402209ff
JH
1127 *--qhead = bb;
1128 bb->aux = bb;
1129 }
e881bb1b 1130 }
e881bb1b 1131
70e0ccd0
AO
1132 /* We clean aux when we remove the initially-enqueued bbs, but we
1133 don't enqueue ENTRY and EXIT initially, so clean them upfront and
1134 unconditionally. */
1135 ENTRY_BLOCK_PTR->aux = EXIT_BLOCK_PTR->aux = NULL;
1136
402209ff
JH
1137 if (blocks_out)
1138 sbitmap_zero (blocks_out);
e881bb1b 1139
402209ff
JH
1140 /* We work through the queue until there are no more blocks. What
1141 is live at the end of this block is precisely the union of what
1142 is live at the beginning of all its successors. So, we set its
1143 GLOBAL_LIVE_AT_END field based on the GLOBAL_LIVE_AT_START field
1144 for its successors. Then, we compute GLOBAL_LIVE_AT_START for
1145 this block by walking through the instructions in this block in
1146 reverse order and updating as we go. If that changed
1147 GLOBAL_LIVE_AT_START, we add the predecessors of the block to the
1148 queue; they will now need to recalculate GLOBAL_LIVE_AT_END.
e881bb1b 1149
402209ff
JH
1150 We are guaranteed to terminate, because GLOBAL_LIVE_AT_START
1151 never shrinks. If a register appears in GLOBAL_LIVE_AT_START, it
1152 must either be live at the end of the block, or used within the
1153 block. In the latter case, it will certainly never disappear
1154 from GLOBAL_LIVE_AT_START. In the former case, the register
1155 could go away only if it disappeared from GLOBAL_LIVE_AT_START
1156 for one of the successor blocks. By induction, that cannot
1157 occur. */
1158 while (qhead != qtail)
e881bb1b 1159 {
402209ff
JH
1160 int rescan, changed;
1161 basic_block bb;
e881bb1b 1162 edge e;
e881bb1b 1163
402209ff
JH
1164 bb = *qhead++;
1165 if (qhead == qend)
1166 qhead = queue;
1167 bb->aux = NULL;
1168
1169 /* Begin by propagating live_at_start from the successor blocks. */
1170 CLEAR_REG_SET (new_live_at_end);
e881bb1b 1171
15b5aef3
RH
1172 if (bb->succ)
1173 for (e = bb->succ; e; e = e->succ_next)
1174 {
1175 basic_block sb = e->dest;
1176
1177 /* Call-clobbered registers die across exception and
1178 call edges. */
1179 /* ??? Abnormal call edges ignored for the moment, as this gets
1180 confused by sibling call edges, which crashes reg-stack. */
1181 if (e->flags & EDGE_EH)
1182 {
1183 bitmap_operation (tmp, sb->global_live_at_start,
f3ea5f6a 1184 invalidated_by_call, BITMAP_AND_COMPL);
15b5aef3
RH
1185 IOR_REG_SET (new_live_at_end, tmp);
1186 }
1187 else
1188 IOR_REG_SET (new_live_at_end, sb->global_live_at_start);
1189
1190 /* If a target saves one register in another (instead of on
1191 the stack) the save register will need to be live for EH. */
1192 if (e->flags & EDGE_EH)
1193 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1194 if (EH_USES (i))
1195 SET_REGNO_REG_SET (new_live_at_end, i);
1196 }
1197 else
1198 {
1199 /* This might be a noreturn function that throws. And
1200 even if it isn't, getting the unwind info right helps
1201 debugging. */
1202 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1203 if (EH_USES (i))
1204 SET_REGNO_REG_SET (new_live_at_end, i);
402209ff 1205 }
e881bb1b 1206
402209ff
JH
1207 /* The all-important stack pointer must always be live. */
1208 SET_REGNO_REG_SET (new_live_at_end, STACK_POINTER_REGNUM);
1e7d57a3 1209
402209ff
JH
1210 /* Before reload, there are a few registers that must be forced
1211 live everywhere -- which might not already be the case for
1212 blocks within infinite loops. */
1213 if (! reload_completed)
1214 {
1215 /* Any reference to any pseudo before reload is a potential
1216 reference of the frame pointer. */
1217 SET_REGNO_REG_SET (new_live_at_end, FRAME_POINTER_REGNUM);
c9bacfdb 1218
402209ff
JH
1219#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1220 /* Pseudos with argument area equivalences may require
1221 reloading via the argument pointer. */
1222 if (fixed_regs[ARG_POINTER_REGNUM])
1223 SET_REGNO_REG_SET (new_live_at_end, ARG_POINTER_REGNUM);
1224#endif
e881bb1b 1225
402209ff
JH
1226 /* Any constant, or pseudo with constant equivalences, may
1227 require reloading from memory using the pic register. */
1228 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
1229 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
1230 SET_REGNO_REG_SET (new_live_at_end, PIC_OFFSET_TABLE_REGNUM);
e881bb1b 1231 }
e881bb1b 1232
402209ff
JH
1233 /* Regs used in phi nodes are not included in
1234 global_live_at_start, since they are live only along a
1235 particular edge. Set those regs that are live because of a
1236 phi node alternative corresponding to this particular block. */
1237 if (in_ssa_form)
1238 for_each_successor_phi (bb, &set_phi_alternative_reg,
1239 new_live_at_end);
e881bb1b 1240
402209ff
JH
1241 if (bb == ENTRY_BLOCK_PTR)
1242 {
1243 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
1244 continue;
1245 }
e881bb1b 1246
402209ff
JH
1247 /* On our first pass through this block, we'll go ahead and continue.
1248 Recognize first pass by local_set NULL. On subsequent passes, we
1249 get to skip out early if live_at_end wouldn't have changed. */
e881bb1b 1250
402209ff
JH
1251 if (bb->local_set == NULL)
1252 {
1253 bb->local_set = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1254 bb->cond_local_set = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1255 rescan = 1;
1256 }
1257 else
1258 {
1259 /* If any bits were removed from live_at_end, we'll have to
1260 rescan the block. This wouldn't be necessary if we had
1261 precalculated local_live, however with PROP_SCAN_DEAD_CODE
1262 local_live is really dependent on live_at_end. */
1263 CLEAR_REG_SET (tmp);
1264 rescan = bitmap_operation (tmp, bb->global_live_at_end,
1265 new_live_at_end, BITMAP_AND_COMPL);
e881bb1b 1266
402209ff
JH
1267 if (! rescan)
1268 {
1269 /* If any of the registers in the new live_at_end set are
1270 conditionally set in this basic block, we must rescan.
1271 This is because conditional lifetimes at the end of the
1272 block do not just take the live_at_end set into account,
1273 but also the liveness at the start of each successor
1274 block. We can miss changes in those sets if we only
1275 compare the new live_at_end against the previous one. */
1276 CLEAR_REG_SET (tmp);
1277 rescan = bitmap_operation (tmp, new_live_at_end,
1278 bb->cond_local_set, BITMAP_AND);
1279 }
e881bb1b 1280
402209ff
JH
1281 if (! rescan)
1282 {
1283 /* Find the set of changed bits. Take this opportunity
1284 to notice that this set is empty and early out. */
1285 CLEAR_REG_SET (tmp);
1286 changed = bitmap_operation (tmp, bb->global_live_at_end,
1287 new_live_at_end, BITMAP_XOR);
1288 if (! changed)
1289 continue;
e881bb1b 1290
402209ff
JH
1291 /* If any of the changed bits overlap with local_set,
1292 we'll have to rescan the block. Detect overlap by
1293 the AND with ~local_set turning off bits. */
1294 rescan = bitmap_operation (tmp, tmp, bb->local_set,
1295 BITMAP_AND_COMPL);
1296 }
1297 }
e881bb1b 1298
402209ff
JH
1299 /* Let our caller know that BB changed enough to require its
1300 death notes updated. */
1301 if (blocks_out)
0b17ab2f 1302 SET_BIT (blocks_out, bb->index);
e881bb1b 1303
402209ff
JH
1304 if (! rescan)
1305 {
1306 /* Add to live_at_start the set of all registers in
1307 new_live_at_end that aren't in the old live_at_end. */
19d3c25c 1308
402209ff
JH
1309 bitmap_operation (tmp, new_live_at_end, bb->global_live_at_end,
1310 BITMAP_AND_COMPL);
1311 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
c9bacfdb 1312
402209ff
JH
1313 changed = bitmap_operation (bb->global_live_at_start,
1314 bb->global_live_at_start,
1315 tmp, BITMAP_IOR);
1316 if (! changed)
1317 continue;
e881bb1b
RH
1318 }
1319 else
1320 {
402209ff 1321 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
e881bb1b 1322
402209ff
JH
1323 /* Rescan the block insn by insn to turn (a copy of) live_at_end
1324 into live_at_start. */
1325 propagate_block (bb, new_live_at_end, bb->local_set,
1326 bb->cond_local_set, flags);
e881bb1b 1327
402209ff
JH
1328 /* If live_at start didn't change, no need to go farther. */
1329 if (REG_SET_EQUAL_P (bb->global_live_at_start, new_live_at_end))
1330 continue;
e881bb1b 1331
402209ff
JH
1332 COPY_REG_SET (bb->global_live_at_start, new_live_at_end);
1333 }
a8688bd6 1334
402209ff
JH
1335 /* Queue all predecessors of BB so that we may re-examine
1336 their live_at_end. */
1337 for (e = bb->pred; e; e = e->pred_next)
1338 {
1339 basic_block pb = e->src;
1340 if (pb->aux == NULL)
1341 {
1342 *qtail++ = pb;
1343 if (qtail == qend)
1344 qtail = queue;
1345 pb->aux = pb;
1346 }
1347 }
a8688bd6
AM
1348 }
1349
402209ff
JH
1350 FREE_REG_SET (tmp);
1351 FREE_REG_SET (new_live_at_end);
f3ea5f6a 1352 FREE_REG_SET (invalidated_by_call);
f5540cd4 1353
402209ff
JH
1354 if (blocks_out)
1355 {
1356 EXECUTE_IF_SET_IN_SBITMAP (blocks_out, 0, i,
1357 {
0b17ab2f 1358 basic_block bb = BASIC_BLOCK (i);
402209ff
JH
1359 FREE_REG_SET (bb->local_set);
1360 FREE_REG_SET (bb->cond_local_set);
1361 });
e881bb1b
RH
1362 }
1363 else
1364 {
e0082a72 1365 FOR_EACH_BB (bb)
402209ff 1366 {
402209ff
JH
1367 FREE_REG_SET (bb->local_set);
1368 FREE_REG_SET (bb->cond_local_set);
1369 }
f5540cd4 1370 }
19d3c25c 1371
402209ff 1372 free (queue);
e881bb1b 1373}
0626ef8a
AM
1374
1375\f
1376/* This structure is used to pass parameters to an from the
4a913dd6
EC
1377 the function find_regno_partial(). It is used to pass in the
1378 register number we are looking, as well as to return any rtx
0626ef8a
AM
1379 we find. */
1380
1381typedef struct {
1382 unsigned regno_to_find;
1383 rtx retval;
1384} find_regno_partial_param;
1385
1386
1387/* Find the rtx for the reg numbers specified in 'data' if it is
1388 part of an expression which only uses part of the register. Return
1389 it in the structure passed in. */
4a913dd6 1390static int
0626ef8a
AM
1391find_regno_partial (ptr, data)
1392 rtx *ptr;
1393 void *data;
1394{
1395 find_regno_partial_param *param = (find_regno_partial_param *)data;
1396 unsigned reg = param->regno_to_find;
1397 param->retval = NULL_RTX;
1398
1399 if (*ptr == NULL_RTX)
1400 return 0;
1401
4a913dd6 1402 switch (GET_CODE (*ptr))
0626ef8a 1403 {
448cad06
AH
1404 case ZERO_EXTRACT:
1405 case SIGN_EXTRACT:
1406 case STRICT_LOW_PART:
1407 if (GET_CODE (XEXP (*ptr, 0)) == REG && REGNO (XEXP (*ptr, 0)) == reg)
1408 {
1409 param->retval = XEXP (*ptr, 0);
1410 return 1;
1411 }
1412 break;
0626ef8a 1413
448cad06 1414 case SUBREG:
4a913dd6 1415 if (GET_CODE (SUBREG_REG (*ptr)) == REG
448cad06
AH
1416 && REGNO (SUBREG_REG (*ptr)) == reg)
1417 {
1418 param->retval = SUBREG_REG (*ptr);
1419 return 1;
1420 }
1421 break;
1422
1423 default:
1424 break;
0626ef8a
AM
1425 }
1426
1427 return 0;
1428}
1429
1430/* Process all immediate successors of the entry block looking for pseudo
4a913dd6
EC
1431 registers which are live on entry. Find all of those whose first
1432 instance is a partial register reference of some kind, and initialize
0626ef8a 1433 them to 0 after the entry block. This will prevent bit sets within
4a913dd6 1434 registers whose value is unknown, and may contain some kind of sticky
0626ef8a
AM
1435 bits we don't want. */
1436
1437int
4a913dd6 1438initialize_uninitialized_subregs ()
0626ef8a
AM
1439{
1440 rtx insn;
1441 edge e;
1442 int reg, did_something = 0;
1443 find_regno_partial_param param;
1444
1445 for (e = ENTRY_BLOCK_PTR->succ; e; e = e->succ_next)
1446 {
1447 basic_block bb = e->dest;
1448 regset map = bb->global_live_at_start;
1449 EXECUTE_IF_SET_IN_REG_SET (map,
1450 FIRST_PSEUDO_REGISTER, reg,
1451 {
1452 int uid = REGNO_FIRST_UID (reg);
1453 rtx i;
1454
1455 /* Find an insn which mentions the register we are looking for.
1456 Its preferable to have an instance of the register's rtl since
4a913dd6 1457 there may be various flags set which we need to duplicate.
0626ef8a 1458 If we can't find it, its probably an automatic whose initial
23d1aac4 1459 value doesn't matter, or hopefully something we don't care about. */
0626ef8a
AM
1460 for (i = get_insns (); i && INSN_UID (i) != uid; i = NEXT_INSN (i))
1461 ;
1462 if (i != NULL_RTX)
1463 {
1464 /* Found the insn, now get the REG rtx, if we can. */
1465 param.regno_to_find = reg;
1466 for_each_rtx (&i, find_regno_partial, &param);
1467 if (param.retval != NULL_RTX)
1468 {
4a913dd6 1469 insn = gen_move_insn (param.retval,
0626ef8a
AM
1470 CONST0_RTX (GET_MODE (param.retval)));
1471 insert_insn_on_edge (insn, e);
1472 did_something = 1;
1473 }
1474 }
1475 });
1476 }
1477
1478 if (did_something)
1479 commit_edge_insertions ();
1480 return did_something;
1481}
1482
402209ff
JH
1483\f
1484/* Subroutines of life analysis. */
e881bb1b 1485
402209ff
JH
1486/* Allocate the permanent data structures that represent the results
1487 of life analysis. Not static since used also for stupid life analysis. */
e881bb1b
RH
1488
1489void
402209ff 1490allocate_bb_life_data ()
e881bb1b 1491{
e0082a72 1492 basic_block bb;
c9bacfdb 1493
e0082a72 1494 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR, NULL, next_bb)
e881bb1b 1495 {
402209ff
JH
1496 bb->global_live_at_start = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1497 bb->global_live_at_end = OBSTACK_ALLOC_REG_SET (&flow_obstack);
e881bb1b 1498 }
f1330226 1499
402209ff
JH
1500 regs_live_at_setjmp = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1501}
0ab409ed 1502
402209ff
JH
1503void
1504allocate_reg_life_data ()
0ab409ed
MH
1505{
1506 int i;
0ab409ed 1507
402209ff 1508 max_regno = max_reg_num ();
0ab409ed 1509
402209ff
JH
1510 /* Recalculate the register space, in case it has grown. Old style
1511 vector oriented regsets would set regset_{size,bytes} here also. */
1512 allocate_reg_info (max_regno, FALSE, FALSE);
0ab409ed 1513
402209ff
JH
1514 /* Reset all the data we'll collect in propagate_block and its
1515 subroutines. */
1516 for (i = 0; i < max_regno; i++)
0ab409ed 1517 {
402209ff
JH
1518 REG_N_SETS (i) = 0;
1519 REG_N_REFS (i) = 0;
1520 REG_N_DEATHS (i) = 0;
1521 REG_N_CALLS_CROSSED (i) = 0;
1522 REG_LIVE_LENGTH (i) = 0;
1523 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
0ab409ed 1524 }
402209ff 1525}
0ab409ed 1526
402209ff 1527/* Delete dead instructions for propagate_block. */
f1330226 1528
402209ff 1529static void
3dec4024 1530propagate_block_delete_insn (insn)
402209ff
JH
1531 rtx insn;
1532{
1533 rtx inote = find_reg_note (insn, REG_LABEL, NULL_RTX);
f1330226 1534
402209ff
JH
1535 /* If the insn referred to a label, and that label was attached to
1536 an ADDR_VEC, it's safe to delete the ADDR_VEC. In fact, it's
1537 pretty much mandatory to delete it, because the ADDR_VEC may be
1538 referencing labels that no longer exist.
f1330226 1539
402209ff
JH
1540 INSN may reference a deleted label, particularly when a jump
1541 table has been optimized into a direct jump. There's no
1542 real good way to fix up the reference to the deleted label
19f71cd7 1543 when the label is deleted, so we just allow it here. */
0ab409ed 1544
402209ff 1545 if (inote && GET_CODE (inote) == CODE_LABEL)
0ab409ed 1546 {
402209ff
JH
1547 rtx label = XEXP (inote, 0);
1548 rtx next;
0ab409ed 1549
402209ff
JH
1550 /* The label may be forced if it has been put in the constant
1551 pool. If that is the only use we must discard the table
1552 jump following it, but not the label itself. */
1553 if (LABEL_NUSES (label) == 1 + LABEL_PRESERVE_P (label)
1554 && (next = next_nonnote_insn (label)) != NULL
1555 && GET_CODE (next) == JUMP_INSN
1556 && (GET_CODE (PATTERN (next)) == ADDR_VEC
1557 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))
0ab409ed 1558 {
402209ff
JH
1559 rtx pat = PATTERN (next);
1560 int diff_vec_p = GET_CODE (pat) == ADDR_DIFF_VEC;
1561 int len = XVECLEN (pat, diff_vec_p);
1562 int i;
f1330226 1563
402209ff
JH
1564 for (i = 0; i < len; i++)
1565 LABEL_NUSES (XEXP (XVECEXP (pat, diff_vec_p, i), 0))--;
0ab409ed 1566
3dec4024
JH
1567 delete_insn_and_edges (next);
1568 ndead++;
0ab409ed
MH
1569 }
1570 }
1571
3dec4024
JH
1572 delete_insn_and_edges (insn);
1573 ndead++;
0ab409ed 1574}
e881bb1b 1575
402209ff
JH
1576/* Delete dead libcalls for propagate_block. Return the insn
1577 before the libcall. */
e881bb1b 1578
402209ff 1579static rtx
607a6500 1580propagate_block_delete_libcall ( insn, note)
402209ff
JH
1581 rtx insn, note;
1582{
1583 rtx first = XEXP (note, 0);
1584 rtx before = PREV_INSN (first);
e881bb1b 1585
3dec4024
JH
1586 delete_insn_chain_and_edges (first, insn);
1587 ndead++;
402209ff 1588 return before;
1e29ee12
JL
1589}
1590
402209ff
JH
1591/* Update the life-status of regs for one insn. Return the previous insn. */
1592
1593rtx
1594propagate_one_insn (pbi, insn)
1595 struct propagate_block_info *pbi;
1596 rtx insn;
1e29ee12 1597{
402209ff
JH
1598 rtx prev = PREV_INSN (insn);
1599 int flags = pbi->flags;
1600 int insn_is_dead = 0;
1601 int libcall_is_dead = 0;
1602 rtx note;
1e29ee12
JL
1603 int i;
1604
402209ff
JH
1605 if (! INSN_P (insn))
1606 return prev;
164d59e0 1607
402209ff
JH
1608 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
1609 if (flags & PROP_SCAN_DEAD_CODE)
1610 {
1611 insn_is_dead = insn_dead_p (pbi, PATTERN (insn), 0, REG_NOTES (insn));
1612 libcall_is_dead = (insn_is_dead && note != 0
1613 && libcall_dead_p (pbi, note, insn));
1614 }
e881bb1b 1615
402209ff
JH
1616 /* If an instruction consists of just dead store(s) on final pass,
1617 delete it. */
1618 if ((flags & PROP_KILL_DEAD_CODE) && insn_is_dead)
e881bb1b 1619 {
402209ff
JH
1620 /* If we're trying to delete a prologue or epilogue instruction
1621 that isn't flagged as possibly being dead, something is wrong.
1622 But if we are keeping the stack pointer depressed, we might well
1623 be deleting insns that are used to compute the amount to update
1624 it by, so they are fine. */
1625 if (reload_completed
1626 && !(TREE_CODE (TREE_TYPE (current_function_decl)) == FUNCTION_TYPE
1627 && (TYPE_RETURNS_STACK_DEPRESSED
1628 (TREE_TYPE (current_function_decl))))
1629 && (((HAVE_epilogue || HAVE_prologue)
1630 && prologue_epilogue_contains (insn))
1631 || (HAVE_sibcall_epilogue
1632 && sibcall_epilogue_contains (insn)))
1633 && find_reg_note (insn, REG_MAYBE_DEAD, NULL_RTX) == 0)
31fce3c4 1634 fatal_insn ("Attempt to delete prologue/epilogue insn:", insn);
e881bb1b 1635
402209ff
JH
1636 /* Record sets. Do this even for dead instructions, since they
1637 would have killed the values if they hadn't been deleted. */
1638 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1639
402209ff
JH
1640 /* CC0 is now known to be dead. Either this insn used it,
1641 in which case it doesn't anymore, or clobbered it,
1642 so the next insn can't use it. */
1643 pbi->cc0_live = 0;
e881bb1b 1644
402209ff 1645 if (libcall_is_dead)
607a6500 1646 prev = propagate_block_delete_libcall ( insn, note);
d35dfca9
JL
1647 else
1648 {
1649
b0ac73f8
JL
1650 /* If INSN contains a RETVAL note and is dead, but the libcall
1651 as a whole is not dead, then we want to remove INSN, but
1652 not the whole libcall sequence.
1653
1654 However, we need to also remove the dangling REG_LIBCALL
1655 note so that we do not have mis-matched LIBCALL/RETVAL
1656 notes. In theory we could find a new location for the
1657 REG_RETVAL note, but it hardly seems worth the effort.
1658
1659 NOTE at this point will be the RETVAL note if it exists. */
d35dfca9
JL
1660 if (note)
1661 {
d35dfca9
JL
1662 rtx libcall_note;
1663
1664 libcall_note
1665 = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
1666 remove_note (XEXP (note, 0), libcall_note);
1667 }
b0ac73f8
JL
1668
1669 /* Similarly if INSN contains a LIBCALL note, remove the
1670 dnagling REG_RETVAL note. */
1671 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
1672 if (note)
1673 {
1674 rtx retval_note;
1675
1676 retval_note
1677 = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
1678 remove_note (XEXP (note, 0), retval_note);
1679 }
1680
1681 /* Now delete INSN. */
d35dfca9
JL
1682 propagate_block_delete_insn (insn);
1683 }
e881bb1b 1684
402209ff
JH
1685 return prev;
1686 }
e881bb1b 1687
402209ff
JH
1688 /* See if this is an increment or decrement that can be merged into
1689 a following memory address. */
1690#ifdef AUTO_INC_DEC
1691 {
b3694847 1692 rtx x = single_set (insn);
e881bb1b 1693
402209ff
JH
1694 /* Does this instruction increment or decrement a register? */
1695 if ((flags & PROP_AUTOINC)
1696 && x != 0
1697 && GET_CODE (SET_DEST (x)) == REG
1698 && (GET_CODE (SET_SRC (x)) == PLUS
1699 || GET_CODE (SET_SRC (x)) == MINUS)
1700 && XEXP (SET_SRC (x), 0) == SET_DEST (x)
1701 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1702 /* Ok, look for a following memory ref we can combine with.
1703 If one is found, change the memory ref to a PRE_INC
1704 or PRE_DEC, cancel this insn, and return 1.
1705 Return 0 if nothing has been done. */
1706 && try_pre_increment_1 (pbi, insn))
1707 return prev;
1708 }
1709#endif /* AUTO_INC_DEC */
e881bb1b 1710
402209ff 1711 CLEAR_REG_SET (pbi->new_set);
e881bb1b 1712
402209ff
JH
1713 /* If this is not the final pass, and this insn is copying the value of
1714 a library call and it's dead, don't scan the insns that perform the
1715 library call, so that the call's arguments are not marked live. */
1716 if (libcall_is_dead)
e881bb1b 1717 {
402209ff
JH
1718 /* Record the death of the dest reg. */
1719 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1720
402209ff
JH
1721 insn = XEXP (note, 0);
1722 return PREV_INSN (insn);
e881bb1b 1723 }
402209ff
JH
1724 else if (GET_CODE (PATTERN (insn)) == SET
1725 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx
1726 && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
1727 && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx
1728 && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
1729 /* We have an insn to pop a constant amount off the stack.
1730 (Such insns use PLUS regardless of the direction of the stack,
1731 and any insn to adjust the stack by a constant is always a pop.)
fe4b3c79
JL
1732 These insns, if not dead stores, have no effect on life, though
1733 they do have an effect on the memory stores we are tracking. */
1734 invalidate_mems_from_set (pbi, stack_pointer_rtx);
402209ff
JH
1735 else
1736 {
5a133afd 1737 rtx note;
402209ff
JH
1738 /* Any regs live at the time of a call instruction must not go
1739 in a register clobbered by calls. Find all regs now live and
1740 record this for them. */
e881bb1b 1741
402209ff
JH
1742 if (GET_CODE (insn) == CALL_INSN && (flags & PROP_REG_INFO))
1743 EXECUTE_IF_SET_IN_REG_SET (pbi->reg_live, 0, i,
1744 { REG_N_CALLS_CROSSED (i)++; });
e881bb1b 1745
402209ff
JH
1746 /* Record sets. Do this even for dead instructions, since they
1747 would have killed the values if they hadn't been deleted. */
1748 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1749
402209ff
JH
1750 if (GET_CODE (insn) == CALL_INSN)
1751 {
b3694847 1752 int i;
402209ff 1753 rtx note, cond;
e881bb1b 1754
402209ff
JH
1755 cond = NULL_RTX;
1756 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
1757 cond = COND_EXEC_TEST (PATTERN (insn));
e881bb1b 1758
fe4b3c79
JL
1759 /* Non-constant calls clobber memory, constant calls do not
1760 clobber memory, though they may clobber outgoing arguments
1761 on the stack. */
402209ff
JH
1762 if (! CONST_OR_PURE_CALL_P (insn))
1763 {
1764 free_EXPR_LIST_list (&pbi->mem_set_list);
1765 pbi->mem_set_list_len = 0;
1766 }
dd3f0101 1767 else
fe4b3c79 1768 invalidate_mems_from_set (pbi, stack_pointer_rtx);
e881bb1b 1769
402209ff
JH
1770 /* There may be extra registers to be clobbered. */
1771 for (note = CALL_INSN_FUNCTION_USAGE (insn);
1772 note;
1773 note = XEXP (note, 1))
1774 if (GET_CODE (XEXP (note, 0)) == CLOBBER)
1775 mark_set_1 (pbi, CLOBBER, XEXP (XEXP (note, 0), 0),
1776 cond, insn, pbi->flags);
c9bacfdb 1777
402209ff
JH
1778 /* Calls change all call-used and global registers. */
1779 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1780 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
1781 {
1782 /* We do not want REG_UNUSED notes for these registers. */
e50126e8 1783 mark_set_1 (pbi, CLOBBER, regno_reg_rtx[i], cond, insn,
402209ff
JH
1784 pbi->flags & ~(PROP_DEATH_NOTES | PROP_REG_INFO));
1785 }
1786 }
312f6255 1787
402209ff
JH
1788 /* If an insn doesn't use CC0, it becomes dead since we assume
1789 that every insn clobbers it. So show it dead here;
1790 mark_used_regs will set it live if it is referenced. */
1791 pbi->cc0_live = 0;
e881bb1b 1792
402209ff
JH
1793 /* Record uses. */
1794 if (! insn_is_dead)
1795 mark_used_regs (pbi, PATTERN (insn), NULL_RTX, insn);
5a133afd
JH
1796 if ((flags & PROP_EQUAL_NOTES)
1797 && ((note = find_reg_note (insn, REG_EQUAL, NULL_RTX))
1798 || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX))))
1799 mark_used_regs (pbi, XEXP (note, 0), NULL_RTX, insn);
e881bb1b 1800
402209ff
JH
1801 /* Sometimes we may have inserted something before INSN (such as a move)
1802 when we make an auto-inc. So ensure we will scan those insns. */
1803#ifdef AUTO_INC_DEC
1804 prev = PREV_INSN (insn);
1805#endif
e881bb1b 1806
402209ff
JH
1807 if (! insn_is_dead && GET_CODE (insn) == CALL_INSN)
1808 {
b3694847 1809 int i;
402209ff 1810 rtx note, cond;
e881bb1b 1811
402209ff
JH
1812 cond = NULL_RTX;
1813 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
1814 cond = COND_EXEC_TEST (PATTERN (insn));
e881bb1b 1815
402209ff
JH
1816 /* Calls use their arguments. */
1817 for (note = CALL_INSN_FUNCTION_USAGE (insn);
1818 note;
1819 note = XEXP (note, 1))
1820 if (GET_CODE (XEXP (note, 0)) == USE)
1821 mark_used_regs (pbi, XEXP (XEXP (note, 0), 0),
1822 cond, insn);
e881bb1b 1823
402209ff
JH
1824 /* The stack ptr is used (honorarily) by a CALL insn. */
1825 SET_REGNO_REG_SET (pbi->reg_live, STACK_POINTER_REGNUM);
e881bb1b 1826
402209ff
JH
1827 /* Calls may also reference any of the global registers,
1828 so they are made live. */
1829 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1830 if (global_regs[i])
e50126e8 1831 mark_used_reg (pbi, regno_reg_rtx[i], cond, insn);
402209ff 1832 }
e881bb1b
RH
1833 }
1834
402209ff
JH
1835 /* On final pass, update counts of how many insns in which each reg
1836 is live. */
1837 if (flags & PROP_REG_INFO)
1838 EXECUTE_IF_SET_IN_REG_SET (pbi->reg_live, 0, i,
1839 { REG_LIVE_LENGTH (i)++; });
1840
1841 return prev;
e881bb1b
RH
1842}
1843
402209ff
JH
1844/* Initialize a propagate_block_info struct for public consumption.
1845 Note that the structure itself is opaque to this file, but that
1846 the user can use the regsets provided here. */
e881bb1b 1847
402209ff
JH
1848struct propagate_block_info *
1849init_propagate_block_info (bb, live, local_set, cond_local_set, flags)
1850 basic_block bb;
1851 regset live, local_set, cond_local_set;
1852 int flags;
e881bb1b 1853{
402209ff 1854 struct propagate_block_info *pbi = xmalloc (sizeof (*pbi));
e881bb1b 1855
402209ff
JH
1856 pbi->bb = bb;
1857 pbi->reg_live = live;
1858 pbi->mem_set_list = NULL_RTX;
1859 pbi->mem_set_list_len = 0;
1860 pbi->local_set = local_set;
1861 pbi->cond_local_set = cond_local_set;
1862 pbi->cc0_live = 0;
1863 pbi->flags = flags;
c9bacfdb 1864
402209ff
JH
1865 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
1866 pbi->reg_next_use = (rtx *) xcalloc (max_reg_num (), sizeof (rtx));
e881bb1b 1867 else
402209ff 1868 pbi->reg_next_use = NULL;
e6cfb550 1869
402209ff 1870 pbi->new_set = BITMAP_XMALLOC ();
7a442791 1871
402209ff
JH
1872#ifdef HAVE_conditional_execution
1873 pbi->reg_cond_dead = splay_tree_new (splay_tree_compare_ints, NULL,
1874 free_reg_cond_life_info);
1875 pbi->reg_cond_reg = BITMAP_XMALLOC ();
7a442791 1876
402209ff
JH
1877 /* If this block ends in a conditional branch, for each register live
1878 from one side of the branch and not the other, record the register
1879 as conditionally dead. */
1880 if (GET_CODE (bb->end) == JUMP_INSN
1881 && any_condjump_p (bb->end))
1882 {
1883 regset_head diff_head;
1884 regset diff = INITIALIZE_REG_SET (diff_head);
1885 basic_block bb_true, bb_false;
1886 rtx cond_true, cond_false, set_src;
1887 int i;
421382ac 1888
402209ff
JH
1889 /* Identify the successor blocks. */
1890 bb_true = bb->succ->dest;
1891 if (bb->succ->succ_next != NULL)
1892 {
1893 bb_false = bb->succ->succ_next->dest;
c9bacfdb 1894
402209ff
JH
1895 if (bb->succ->flags & EDGE_FALLTHRU)
1896 {
1897 basic_block t = bb_false;
1898 bb_false = bb_true;
1899 bb_true = t;
1900 }
1901 else if (! (bb->succ->succ_next->flags & EDGE_FALLTHRU))
1902 abort ();
1903 }
1904 else
1905 {
1906 /* This can happen with a conditional jump to the next insn. */
1907 if (JUMP_LABEL (bb->end) != bb_true->head)
1908 abort ();
421382ac 1909
402209ff
JH
1910 /* Simplest way to do nothing. */
1911 bb_false = bb_true;
1912 }
be1bb652 1913
402209ff
JH
1914 /* Extract the condition from the branch. */
1915 set_src = SET_SRC (pc_set (bb->end));
1916 cond_true = XEXP (set_src, 0);
1917 cond_false = gen_rtx_fmt_ee (reverse_condition (GET_CODE (cond_true)),
1918 GET_MODE (cond_true), XEXP (cond_true, 0),
1919 XEXP (cond_true, 1));
1920 if (GET_CODE (XEXP (set_src, 1)) == PC)
1921 {
1922 rtx t = cond_false;
1923 cond_false = cond_true;
1924 cond_true = t;
1925 }
be1bb652 1926
402209ff
JH
1927 /* Compute which register lead different lives in the successors. */
1928 if (bitmap_operation (diff, bb_true->global_live_at_start,
1929 bb_false->global_live_at_start, BITMAP_XOR))
1930 {
1931 rtx reg = XEXP (cond_true, 0);
be1bb652 1932
402209ff
JH
1933 if (GET_CODE (reg) == SUBREG)
1934 reg = SUBREG_REG (reg);
dc108b7a 1935
402209ff
JH
1936 if (GET_CODE (reg) != REG)
1937 abort ();
dc108b7a 1938
402209ff 1939 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (reg));
dc108b7a 1940
402209ff
JH
1941 /* For each such register, mark it conditionally dead. */
1942 EXECUTE_IF_SET_IN_REG_SET
1943 (diff, 0, i,
1944 {
1945 struct reg_cond_life_info *rcli;
1946 rtx cond;
dc108b7a 1947
402209ff 1948 rcli = (struct reg_cond_life_info *) xmalloc (sizeof (*rcli));
dc108b7a 1949
402209ff
JH
1950 if (REGNO_REG_SET_P (bb_true->global_live_at_start, i))
1951 cond = cond_false;
1952 else
1953 cond = cond_true;
1954 rcli->condition = cond;
1955 rcli->stores = const0_rtx;
1956 rcli->orig_condition = cond;
dc108b7a 1957
402209ff
JH
1958 splay_tree_insert (pbi->reg_cond_dead, i,
1959 (splay_tree_value) rcli);
1960 });
dc108b7a 1961 }
dc108b7a 1962
402209ff 1963 FREE_REG_SET (diff);
dc108b7a 1964 }
402209ff
JH
1965#endif
1966
1967 /* If this block has no successors, any stores to the frame that aren't
1968 used later in the block are dead. So make a pass over the block
1969 recording any such that are made and show them dead at the end. We do
1970 a very conservative and simple job here. */
1971 if (optimize
1972 && ! (TREE_CODE (TREE_TYPE (current_function_decl)) == FUNCTION_TYPE
1973 && (TYPE_RETURNS_STACK_DEPRESSED
1974 (TREE_TYPE (current_function_decl))))
5149f070 1975 && (flags & PROP_SCAN_DEAD_STORES)
402209ff
JH
1976 && (bb->succ == NULL
1977 || (bb->succ->succ_next == NULL
1978 && bb->succ->dest == EXIT_BLOCK_PTR
1979 && ! current_function_calls_eh_return)))
dc108b7a 1980 {
402209ff
JH
1981 rtx insn, set;
1982 for (insn = bb->end; insn != bb->head; insn = PREV_INSN (insn))
1983 if (GET_CODE (insn) == INSN
1984 && (set = single_set (insn))
1985 && GET_CODE (SET_DEST (set)) == MEM)
1986 {
1987 rtx mem = SET_DEST (set);
1988 rtx canon_mem = canon_rtx (mem);
1989
1990 /* This optimization is performed by faking a store to the
1991 memory at the end of the block. This doesn't work for
1992 unchanging memories because multiple stores to unchanging
1993 memory is illegal and alias analysis doesn't consider it. */
1994 if (RTX_UNCHANGING_P (canon_mem))
1995 continue;
1996
1997 if (XEXP (canon_mem, 0) == frame_pointer_rtx
1998 || (GET_CODE (XEXP (canon_mem, 0)) == PLUS
1999 && XEXP (XEXP (canon_mem, 0), 0) == frame_pointer_rtx
2000 && GET_CODE (XEXP (XEXP (canon_mem, 0), 1)) == CONST_INT))
2001 add_to_mem_set_list (pbi, canon_mem);
2002 }
dc108b7a 2003 }
dc108b7a 2004
402209ff 2005 return pbi;
dc108b7a
RH
2006}
2007
402209ff 2008/* Release a propagate_block_info struct. */
558389e3 2009
402209ff
JH
2010void
2011free_propagate_block_info (pbi)
2012 struct propagate_block_info *pbi;
558389e3 2013{
402209ff 2014 free_EXPR_LIST_list (&pbi->mem_set_list);
558389e3 2015
402209ff 2016 BITMAP_XFREE (pbi->new_set);
558389e3 2017
402209ff
JH
2018#ifdef HAVE_conditional_execution
2019 splay_tree_delete (pbi->reg_cond_dead);
2020 BITMAP_XFREE (pbi->reg_cond_reg);
2021#endif
558389e3 2022
402209ff
JH
2023 if (pbi->reg_next_use)
2024 free (pbi->reg_next_use);
558389e3 2025
402209ff
JH
2026 free (pbi);
2027}
336a6399 2028
402209ff
JH
2029/* Compute the registers live at the beginning of a basic block BB from
2030 those live at the end.
c9bacfdb 2031
402209ff
JH
2032 When called, REG_LIVE contains those live at the end. On return, it
2033 contains those live at the beginning.
ee7b8369 2034
402209ff
JH
2035 LOCAL_SET, if non-null, will be set with all registers killed
2036 unconditionally by this basic block.
2037 Likewise, COND_LOCAL_SET, if non-null, will be set with all registers
2038 killed conditionally by this basic block. If there is any unconditional
2039 set of a register, then the corresponding bit will be set in LOCAL_SET
2040 and cleared in COND_LOCAL_SET.
2041 It is valid for LOCAL_SET and COND_LOCAL_SET to be the same set. In this
2042 case, the resulting set will be equal to the union of the two sets that
2043 would otherwise be computed.
558389e3 2044
402209ff 2045 Return non-zero if an INSN is deleted (i.e. by dead code removal). */
558389e3 2046
402209ff
JH
2047int
2048propagate_block (bb, live, local_set, cond_local_set, flags)
2049 basic_block bb;
2050 regset live;
2051 regset local_set;
2052 regset cond_local_set;
2053 int flags;
558389e3 2054{
402209ff
JH
2055 struct propagate_block_info *pbi;
2056 rtx insn, prev;
2057 int changed;
558389e3 2058
402209ff 2059 pbi = init_propagate_block_info (bb, live, local_set, cond_local_set, flags);
be1bb652 2060
402209ff 2061 if (flags & PROP_REG_INFO)
be1bb652 2062 {
b3694847 2063 int i;
558389e3 2064
402209ff
JH
2065 /* Process the regs live at the end of the block.
2066 Mark them as not local to any one basic block. */
2067 EXECUTE_IF_SET_IN_REG_SET (live, 0, i,
2068 { REG_BASIC_BLOCK (i) = REG_BLOCK_GLOBAL; });
2069 }
558389e3 2070
402209ff 2071 /* Scan the block an insn at a time from end to beginning. */
558389e3 2072
402209ff
JH
2073 changed = 0;
2074 for (insn = bb->end;; insn = prev)
2075 {
2076 /* If this is a call to `setjmp' et al, warn if any
2077 non-volatile datum is live. */
2078 if ((flags & PROP_REG_INFO)
2079 && GET_CODE (insn) == CALL_INSN
2080 && find_reg_note (insn, REG_SETJMP, NULL))
2081 IOR_REG_SET (regs_live_at_setjmp, pbi->reg_live);
558389e3 2082
402209ff
JH
2083 prev = propagate_one_insn (pbi, insn);
2084 changed |= NEXT_INSN (prev) != insn;
336a6399 2085
402209ff
JH
2086 if (insn == bb->head)
2087 break;
336a6399
RH
2088 }
2089
402209ff
JH
2090 free_propagate_block_info (pbi);
2091
2092 return changed;
558389e3 2093}
402209ff
JH
2094\f
2095/* Return 1 if X (the body of an insn, or part of it) is just dead stores
2096 (SET expressions whose destinations are registers dead after the insn).
2097 NEEDED is the regset that says which regs are alive after the insn.
2098
2099 Unless CALL_OK is non-zero, an insn is needed if it contains a CALL.
558389e3 2100
402209ff
JH
2101 If X is the entire body of an insn, NOTES contains the reg notes
2102 pertaining to the insn. */
dc2ede84 2103
dc2ede84 2104static int
402209ff
JH
2105insn_dead_p (pbi, x, call_ok, notes)
2106 struct propagate_block_info *pbi;
2107 rtx x;
2108 int call_ok;
2109 rtx notes ATTRIBUTE_UNUSED;
dc2ede84 2110{
402209ff 2111 enum rtx_code code = GET_CODE (x);
be1bb652 2112
402209ff 2113#ifdef AUTO_INC_DEC
ff6051b7
GK
2114 /* As flow is invoked after combine, we must take existing AUTO_INC
2115 expressions into account. */
2116 for (; notes; notes = XEXP (notes, 1))
e881bb1b 2117 {
ff6051b7 2118 if (REG_NOTE_KIND (notes) == REG_INC)
336a6399 2119 {
ff6051b7 2120 int regno = REGNO (XEXP (notes, 0));
4a913dd6 2121
ff6051b7
GK
2122 /* Don't delete insns to set global regs. */
2123 if ((regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2124 || REGNO_REG_SET_P (pbi->reg_live, regno))
2125 return 0;
402209ff 2126 }
336a6399 2127 }
402209ff 2128#endif
4793dca1 2129
402209ff
JH
2130 /* If setting something that's a reg or part of one,
2131 see if that register's altered value will be live. */
558389e3 2132
402209ff 2133 if (code == SET)
7a442791 2134 {
402209ff 2135 rtx r = SET_DEST (x);
b02eea61 2136
402209ff
JH
2137#ifdef HAVE_cc0
2138 if (GET_CODE (r) == CC0)
2139 return ! pbi->cc0_live;
2140#endif
b9f22704 2141
402209ff
JH
2142 /* A SET that is a subroutine call cannot be dead. */
2143 if (GET_CODE (SET_SRC (x)) == CALL)
2144 {
2145 if (! call_ok)
2146 return 0;
2147 }
b02eea61 2148
402209ff
JH
2149 /* Don't eliminate loads from volatile memory or volatile asms. */
2150 else if (volatile_refs_p (SET_SRC (x)))
2151 return 0;
7a442791 2152
402209ff 2153 if (GET_CODE (r) == MEM)
7a442791 2154 {
402209ff 2155 rtx temp, canon_r;
b9f22704 2156
402209ff
JH
2157 if (MEM_VOLATILE_P (r) || GET_MODE (r) == BLKmode)
2158 return 0;
0068fd96 2159
402209ff 2160 canon_r = canon_rtx (r);
0068fd96 2161
402209ff
JH
2162 /* Walk the set of memory locations we are currently tracking
2163 and see if one is an identical match to this memory location.
2164 If so, this memory write is dead (remember, we're walking
2165 backwards from the end of the block to the start). Since
2166 rtx_equal_p does not check the alias set or flags, we also
2167 must have the potential for them to conflict (anti_dependence). */
2168 for (temp = pbi->mem_set_list; temp != 0; temp = XEXP (temp, 1))
2169 if (anti_dependence (r, XEXP (temp, 0)))
2170 {
2171 rtx mem = XEXP (temp, 0);
0068fd96 2172
402209ff
JH
2173 if (rtx_equal_p (XEXP (canon_r, 0), XEXP (mem, 0))
2174 && (GET_MODE_SIZE (GET_MODE (canon_r))
2175 <= GET_MODE_SIZE (GET_MODE (mem))))
2176 return 1;
7a442791 2177
402209ff
JH
2178#ifdef AUTO_INC_DEC
2179 /* Check if memory reference matches an auto increment. Only
2180 post increment/decrement or modify are valid. */
2181 if (GET_MODE (mem) == GET_MODE (r)
2182 && (GET_CODE (XEXP (mem, 0)) == POST_DEC
2183 || GET_CODE (XEXP (mem, 0)) == POST_INC
2184 || GET_CODE (XEXP (mem, 0)) == POST_MODIFY)
2185 && GET_MODE (XEXP (mem, 0)) == GET_MODE (r)
2186 && rtx_equal_p (XEXP (XEXP (mem, 0), 0), XEXP (r, 0)))
2187 return 1;
2188#endif
2189 }
b02eea61 2190 }
d69d0316 2191 else
7a442791 2192 {
402209ff
JH
2193 while (GET_CODE (r) == SUBREG
2194 || GET_CODE (r) == STRICT_LOW_PART
2195 || GET_CODE (r) == ZERO_EXTRACT)
2196 r = XEXP (r, 0);
b02eea61 2197
402209ff 2198 if (GET_CODE (r) == REG)
d69d0316 2199 {
402209ff 2200 int regno = REGNO (r);
b02eea61 2201
402209ff
JH
2202 /* Obvious. */
2203 if (REGNO_REG_SET_P (pbi->reg_live, regno))
2204 return 0;
7a442791 2205
402209ff
JH
2206 /* If this is a hard register, verify that subsequent
2207 words are not needed. */
2208 if (regno < FIRST_PSEUDO_REGISTER)
2209 {
2210 int n = HARD_REGNO_NREGS (regno, GET_MODE (r));
46fac664 2211
402209ff
JH
2212 while (--n > 0)
2213 if (REGNO_REG_SET_P (pbi->reg_live, regno+n))
2214 return 0;
2215 }
46fac664 2216
402209ff
JH
2217 /* Don't delete insns to set global regs. */
2218 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2219 return 0;
46fac664 2220
402209ff
JH
2221 /* Make sure insns to set the stack pointer aren't deleted. */
2222 if (regno == STACK_POINTER_REGNUM)
2223 return 0;
b02eea61 2224
402209ff
JH
2225 /* ??? These bits might be redundant with the force live bits
2226 in calculate_global_regs_live. We would delete from
2227 sequential sets; whether this actually affects real code
2228 for anything but the stack pointer I don't know. */
2229 /* Make sure insns to set the frame pointer aren't deleted. */
2230 if (regno == FRAME_POINTER_REGNUM
2231 && (! reload_completed || frame_pointer_needed))
2232 return 0;
2233#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2234 if (regno == HARD_FRAME_POINTER_REGNUM
2235 && (! reload_completed || frame_pointer_needed))
2236 return 0;
2237#endif
b02eea61 2238
402209ff
JH
2239#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2240 /* Make sure insns to set arg pointer are never deleted
2241 (if the arg pointer isn't fixed, there will be a USE
2242 for it, so we can treat it normally). */
2243 if (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
2244 return 0;
2245#endif
46fac664 2246
402209ff
JH
2247 /* Otherwise, the set is dead. */
2248 return 1;
2249 }
2250 }
2251 }
46fac664 2252
402209ff
JH
2253 /* If performing several activities, insn is dead if each activity
2254 is individually dead. Also, CLOBBERs and USEs can be ignored; a
2255 CLOBBER or USE that's inside a PARALLEL doesn't make the insn
2256 worth keeping. */
2257 else if (code == PARALLEL)
2258 {
2259 int i = XVECLEN (x, 0);
46fac664 2260
402209ff
JH
2261 for (i--; i >= 0; i--)
2262 if (GET_CODE (XVECEXP (x, 0, i)) != CLOBBER
2263 && GET_CODE (XVECEXP (x, 0, i)) != USE
2264 && ! insn_dead_p (pbi, XVECEXP (x, 0, i), call_ok, NULL_RTX))
2265 return 0;
46fac664 2266
402209ff
JH
2267 return 1;
2268 }
46fac664 2269
402209ff
JH
2270 /* A CLOBBER of a pseudo-register that is dead serves no purpose. That
2271 is not necessarily true for hard registers. */
2272 else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == REG
2273 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER
2274 && ! REGNO_REG_SET_P (pbi->reg_live, REGNO (XEXP (x, 0))))
2275 return 1;
46fac664 2276
402209ff
JH
2277 /* We do not check other CLOBBER or USE here. An insn consisting of just
2278 a CLOBBER or just a USE should not be deleted. */
2279 return 0;
2280}
46fac664 2281
402209ff
JH
2282/* If INSN is the last insn in a libcall, and assuming INSN is dead,
2283 return 1 if the entire library call is dead.
2284 This is true if INSN copies a register (hard or pseudo)
2285 and if the hard return reg of the call insn is dead.
2286 (The caller should have tested the destination of the SET inside
2287 INSN already for death.)
46fac664 2288
402209ff
JH
2289 If this insn doesn't just copy a register, then we don't
2290 have an ordinary libcall. In that case, cse could not have
2291 managed to substitute the source for the dest later on,
2292 so we can assume the libcall is dead.
46fac664 2293
402209ff
JH
2294 PBI is the block info giving pseudoregs live before this insn.
2295 NOTE is the REG_RETVAL note of the insn. */
46fac664 2296
402209ff
JH
2297static int
2298libcall_dead_p (pbi, note, insn)
2299 struct propagate_block_info *pbi;
2300 rtx note;
2301 rtx insn;
2302{
2303 rtx x = single_set (insn);
46fac664 2304
402209ff
JH
2305 if (x)
2306 {
b3694847 2307 rtx r = SET_SRC (x);
46fac664 2308
402209ff
JH
2309 if (GET_CODE (r) == REG)
2310 {
2311 rtx call = XEXP (note, 0);
2312 rtx call_pat;
b3694847 2313 int i;
46fac664 2314
402209ff
JH
2315 /* Find the call insn. */
2316 while (call != insn && GET_CODE (call) != CALL_INSN)
2317 call = NEXT_INSN (call);
46fac664 2318
402209ff
JH
2319 /* If there is none, do nothing special,
2320 since ordinary death handling can understand these insns. */
2321 if (call == insn)
2322 return 0;
b02eea61 2323
402209ff
JH
2324 /* See if the hard reg holding the value is dead.
2325 If this is a PARALLEL, find the call within it. */
2326 call_pat = PATTERN (call);
2327 if (GET_CODE (call_pat) == PARALLEL)
46fac664 2328 {
402209ff
JH
2329 for (i = XVECLEN (call_pat, 0) - 1; i >= 0; i--)
2330 if (GET_CODE (XVECEXP (call_pat, 0, i)) == SET
2331 && GET_CODE (SET_SRC (XVECEXP (call_pat, 0, i))) == CALL)
2332 break;
2333
2334 /* This may be a library call that is returning a value
2335 via invisible pointer. Do nothing special, since
2336 ordinary death handling can understand these insns. */
2337 if (i < 0)
2338 return 0;
2339
2340 call_pat = XVECEXP (call_pat, 0, i);
46fac664 2341 }
46fac664 2342
402209ff 2343 return insn_dead_p (pbi, call_pat, 1, REG_NOTES (call));
46fac664 2344 }
46fac664 2345 }
402209ff
JH
2346 return 1;
2347}
46fac664 2348
402209ff
JH
2349/* Return 1 if register REGNO was used before it was set, i.e. if it is
2350 live at function entry. Don't count global register variables, variables
2351 in registers that can be used for function arg passing, or variables in
2352 fixed hard registers. */
b02eea61 2353
402209ff
JH
2354int
2355regno_uninitialized (regno)
e817125d 2356 unsigned int regno;
402209ff 2357{
0b17ab2f 2358 if (n_basic_blocks == 0
402209ff
JH
2359 || (regno < FIRST_PSEUDO_REGISTER
2360 && (global_regs[regno]
2361 || fixed_regs[regno]
2362 || FUNCTION_ARG_REGNO_P (regno))))
2363 return 0;
46fac664 2364
f6366fc7 2365 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno);
46fac664
JH
2366}
2367
402209ff
JH
2368/* 1 if register REGNO was alive at a place where `setjmp' was called
2369 and was set more than once or is an argument.
2370 Such regs may be clobbered by `longjmp'. */
b02eea61 2371
402209ff
JH
2372int
2373regno_clobbered_at_setjmp (regno)
2374 int regno;
2375{
0b17ab2f 2376 if (n_basic_blocks == 0)
402209ff
JH
2377 return 0;
2378
2379 return ((REG_N_SETS (regno) > 1
f6366fc7 2380 || REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno))
402209ff
JH
2381 && REGNO_REG_SET_P (regs_live_at_setjmp, regno));
2382}
2383\f
2384/* Add MEM to PBI->MEM_SET_LIST. MEM should be canonical. Respect the
2385 maximal list size; look for overlaps in mode and select the largest. */
2386static void
2387add_to_mem_set_list (pbi, mem)
2388 struct propagate_block_info *pbi;
2389 rtx mem;
46fac664 2390{
402209ff
JH
2391 rtx i;
2392
2393 /* We don't know how large a BLKmode store is, so we must not
2394 take them into consideration. */
2395 if (GET_MODE (mem) == BLKmode)
2396 return;
2397
2398 for (i = pbi->mem_set_list; i ; i = XEXP (i, 1))
46fac664 2399 {
402209ff
JH
2400 rtx e = XEXP (i, 0);
2401 if (rtx_equal_p (XEXP (mem, 0), XEXP (e, 0)))
46fac664 2402 {
402209ff 2403 if (GET_MODE_SIZE (GET_MODE (mem)) > GET_MODE_SIZE (GET_MODE (e)))
b02eea61 2404 {
402209ff
JH
2405#ifdef AUTO_INC_DEC
2406 /* If we must store a copy of the mem, we can just modify
2407 the mode of the stored copy. */
2408 if (pbi->flags & PROP_AUTOINC)
2409 PUT_MODE (e, GET_MODE (mem));
2410 else
2411#endif
2412 XEXP (i, 0) = mem;
b02eea61 2413 }
402209ff 2414 return;
46fac664 2415 }
46fac664 2416 }
b02eea61 2417
402209ff
JH
2418 if (pbi->mem_set_list_len < MAX_MEM_SET_LIST_LEN)
2419 {
2420#ifdef AUTO_INC_DEC
2421 /* Store a copy of mem, otherwise the address may be
2422 scrogged by find_auto_inc. */
2423 if (pbi->flags & PROP_AUTOINC)
2424 mem = shallow_copy_rtx (mem);
2425#endif
2426 pbi->mem_set_list = alloc_EXPR_LIST (0, mem, pbi->mem_set_list);
2427 pbi->mem_set_list_len++;
2428 }
46fac664
JH
2429}
2430
402209ff
JH
2431/* INSN references memory, possibly using autoincrement addressing modes.
2432 Find any entries on the mem_set_list that need to be invalidated due
2433 to an address change. */
b02eea61 2434
fe4b3c79
JL
2435static int
2436invalidate_mems_from_autoinc (px, data)
2437 rtx *px;
2438 void *data;
46fac664 2439{
fe4b3c79
JL
2440 rtx x = *px;
2441 struct propagate_block_info *pbi = data;
2442
2443 if (GET_RTX_CLASS (GET_CODE (x)) == 'a')
2444 {
2445 invalidate_mems_from_set (pbi, XEXP (x, 0));
2446 return -1;
2447 }
2448
2449 return 0;
402209ff 2450}
46fac664 2451
ff7cc307 2452/* EXP is a REG. Remove any dependent entries from pbi->mem_set_list. */
46fac664 2453
402209ff
JH
2454static void
2455invalidate_mems_from_set (pbi, exp)
2456 struct propagate_block_info *pbi;
2457 rtx exp;
2458{
2459 rtx temp = pbi->mem_set_list;
2460 rtx prev = NULL_RTX;
2461 rtx next;
46fac664 2462
402209ff 2463 while (temp)
46fac664 2464 {
402209ff
JH
2465 next = XEXP (temp, 1);
2466 if (reg_overlap_mentioned_p (exp, XEXP (temp, 0)))
46fac664 2467 {
402209ff
JH
2468 /* Splice this entry out of the list. */
2469 if (prev)
2470 XEXP (prev, 1) = next;
2471 else
2472 pbi->mem_set_list = next;
2473 free_EXPR_LIST_node (temp);
2474 pbi->mem_set_list_len--;
46fac664 2475 }
46fac664 2476 else
402209ff
JH
2477 prev = temp;
2478 temp = next;
46fac664 2479 }
402209ff 2480}
46fac664 2481
402209ff
JH
2482/* Process the registers that are set within X. Their bits are set to
2483 1 in the regset DEAD, because they are dead prior to this insn.
b02eea61 2484
402209ff 2485 If INSN is nonzero, it is the insn being processed.
46fac664 2486
402209ff 2487 FLAGS is the set of operations to perform. */
b02eea61 2488
402209ff
JH
2489static void
2490mark_set_regs (pbi, x, insn)
2491 struct propagate_block_info *pbi;
2492 rtx x, insn;
46fac664 2493{
402209ff
JH
2494 rtx cond = NULL_RTX;
2495 rtx link;
2496 enum rtx_code code;
46fac664 2497
402209ff
JH
2498 if (insn)
2499 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2500 {
2501 if (REG_NOTE_KIND (link) == REG_INC)
2502 mark_set_1 (pbi, SET, XEXP (link, 0),
2503 (GET_CODE (x) == COND_EXEC
2504 ? COND_EXEC_TEST (x) : NULL_RTX),
2505 insn, pbi->flags);
2506 }
2507 retry:
2508 switch (code = GET_CODE (x))
46fac664 2509 {
402209ff
JH
2510 case SET:
2511 case CLOBBER:
2512 mark_set_1 (pbi, code, SET_DEST (x), cond, insn, pbi->flags);
2513 return;
b02eea61 2514
402209ff
JH
2515 case COND_EXEC:
2516 cond = COND_EXEC_TEST (x);
2517 x = COND_EXEC_CODE (x);
2518 goto retry;
b02eea61 2519
402209ff
JH
2520 case PARALLEL:
2521 {
b3694847
SS
2522 int i;
2523
402209ff
JH
2524 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2525 {
2526 rtx sub = XVECEXP (x, 0, i);
2527 switch (code = GET_CODE (sub))
2528 {
2529 case COND_EXEC:
2530 if (cond != NULL_RTX)
2531 abort ();
b02eea61 2532
402209ff
JH
2533 cond = COND_EXEC_TEST (sub);
2534 sub = COND_EXEC_CODE (sub);
2535 if (GET_CODE (sub) != SET && GET_CODE (sub) != CLOBBER)
2536 break;
2537 /* Fall through. */
b02eea61 2538
402209ff
JH
2539 case SET:
2540 case CLOBBER:
2541 mark_set_1 (pbi, code, SET_DEST (sub), cond, insn, pbi->flags);
2542 break;
b02eea61 2543
402209ff
JH
2544 default:
2545 break;
2546 }
2547 }
2548 break;
2549 }
b02eea61 2550
402209ff
JH
2551 default:
2552 break;
46fac664 2553 }
46fac664
JH
2554}
2555
402209ff
JH
2556/* Process a single set, which appears in INSN. REG (which may not
2557 actually be a REG, it may also be a SUBREG, PARALLEL, etc.) is
2558 being set using the CODE (which may be SET, CLOBBER, or COND_EXEC).
2559 If the set is conditional (because it appear in a COND_EXEC), COND
2560 will be the condition. */
7a442791 2561
402209ff
JH
2562static void
2563mark_set_1 (pbi, code, reg, cond, insn, flags)
2564 struct propagate_block_info *pbi;
2565 enum rtx_code code;
2566 rtx reg, cond, insn;
2567 int flags;
336a6399 2568{
402209ff
JH
2569 int regno_first = -1, regno_last = -1;
2570 unsigned long not_dead = 0;
336a6399
RH
2571 int i;
2572
402209ff
JH
2573 /* Modifying just one hardware register of a multi-reg value or just a
2574 byte field of a register does not mean the value from before this insn
2575 is now dead. Of course, if it was dead after it's unused now. */
336a6399 2576
402209ff 2577 switch (GET_CODE (reg))
336a6399 2578 {
402209ff
JH
2579 case PARALLEL:
2580 /* Some targets place small structures in registers for return values of
2581 functions. We have to detect this case specially here to get correct
2582 flow information. */
2583 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2584 if (XEXP (XVECEXP (reg, 0, i), 0) != 0)
2585 mark_set_1 (pbi, code, XEXP (XVECEXP (reg, 0, i), 0), cond, insn,
2586 flags);
2587 return;
2588
2589 case ZERO_EXTRACT:
2590 case SIGN_EXTRACT:
2591 case STRICT_LOW_PART:
2592 /* ??? Assumes STRICT_LOW_PART not used on multi-word registers. */
2593 do
2594 reg = XEXP (reg, 0);
2595 while (GET_CODE (reg) == SUBREG
2596 || GET_CODE (reg) == ZERO_EXTRACT
2597 || GET_CODE (reg) == SIGN_EXTRACT
2598 || GET_CODE (reg) == STRICT_LOW_PART);
2599 if (GET_CODE (reg) == MEM)
2600 break;
2601 not_dead = (unsigned long) REGNO_REG_SET_P (pbi->reg_live, REGNO (reg));
2602 /* Fall through. */
b02eea61 2603
402209ff
JH
2604 case REG:
2605 regno_last = regno_first = REGNO (reg);
2606 if (regno_first < FIRST_PSEUDO_REGISTER)
2607 regno_last += HARD_REGNO_NREGS (regno_first, GET_MODE (reg)) - 1;
2608 break;
b02eea61 2609
402209ff
JH
2610 case SUBREG:
2611 if (GET_CODE (SUBREG_REG (reg)) == REG)
7a442791 2612 {
402209ff
JH
2613 enum machine_mode outer_mode = GET_MODE (reg);
2614 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (reg));
7a442791 2615
402209ff
JH
2616 /* Identify the range of registers affected. This is moderately
2617 tricky for hard registers. See alter_subreg. */
b02eea61 2618
402209ff
JH
2619 regno_last = regno_first = REGNO (SUBREG_REG (reg));
2620 if (regno_first < FIRST_PSEUDO_REGISTER)
4793dca1 2621 {
402209ff
JH
2622 regno_first += subreg_regno_offset (regno_first, inner_mode,
2623 SUBREG_BYTE (reg),
2624 outer_mode);
2625 regno_last = (regno_first
2626 + HARD_REGNO_NREGS (regno_first, outer_mode) - 1);
3e28fe44 2627
402209ff
JH
2628 /* Since we've just adjusted the register number ranges, make
2629 sure REG matches. Otherwise some_was_live will be clear
2630 when it shouldn't have been, and we'll create incorrect
2631 REG_UNUSED notes. */
2632 reg = gen_rtx_REG (outer_mode, regno_first);
62828c00 2633 }
402209ff 2634 else
d3a923ee 2635 {
402209ff
JH
2636 /* If the number of words in the subreg is less than the number
2637 of words in the full register, we have a well-defined partial
2638 set. Otherwise the high bits are undefined.
d3a923ee 2639
402209ff
JH
2640 This is only really applicable to pseudos, since we just took
2641 care of multi-word hard registers. */
2642 if (((GET_MODE_SIZE (outer_mode)
2643 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2644 < ((GET_MODE_SIZE (inner_mode)
2645 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
2646 not_dead = (unsigned long) REGNO_REG_SET_P (pbi->reg_live,
2647 regno_first);
d3a923ee 2648
402209ff 2649 reg = SUBREG_REG (reg);
d3a923ee 2650 }
d3a923ee 2651 }
402209ff
JH
2652 else
2653 reg = SUBREG_REG (reg);
2654 break;
c586192c 2655
402209ff
JH
2656 default:
2657 break;
c586192c 2658 }
c586192c 2659
402209ff
JH
2660 /* If this set is a MEM, then it kills any aliased writes.
2661 If this set is a REG, then it kills any MEMs which use the reg. */
5149f070 2662 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
e881bb1b 2663 {
402209ff
JH
2664 if (GET_CODE (reg) == REG)
2665 invalidate_mems_from_set (pbi, reg);
e881bb1b 2666
402209ff
JH
2667 /* If the memory reference had embedded side effects (autoincrement
2668 address modes. Then we may need to kill some entries on the
2669 memory set list. */
2670 if (insn && GET_CODE (reg) == MEM)
fe4b3c79 2671 for_each_rtx (&PATTERN (insn), invalidate_mems_from_autoinc, pbi);
ccbaf064 2672
402209ff
JH
2673 if (GET_CODE (reg) == MEM && ! side_effects_p (reg)
2674 /* ??? With more effort we could track conditional memory life. */
fe4b3c79 2675 && ! cond)
dd3f0101 2676 add_to_mem_set_list (pbi, canon_rtx (reg));
ccbaf064 2677 }
f2a1bc02 2678
402209ff
JH
2679 if (GET_CODE (reg) == REG
2680 && ! (regno_first == FRAME_POINTER_REGNUM
2681 && (! reload_completed || frame_pointer_needed))
2682#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2683 && ! (regno_first == HARD_FRAME_POINTER_REGNUM
2684 && (! reload_completed || frame_pointer_needed))
2685#endif
2686#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2687 && ! (regno_first == ARG_POINTER_REGNUM && fixed_regs[regno_first])
2688#endif
2689 )
f2a1bc02 2690 {
402209ff 2691 int some_was_live = 0, some_was_dead = 0;
f2a1bc02 2692
402209ff 2693 for (i = regno_first; i <= regno_last; ++i)
f2a1bc02 2694 {
402209ff
JH
2695 int needed_regno = REGNO_REG_SET_P (pbi->reg_live, i);
2696 if (pbi->local_set)
f2a1bc02 2697 {
402209ff
JH
2698 /* Order of the set operation matters here since both
2699 sets may be the same. */
2700 CLEAR_REGNO_REG_SET (pbi->cond_local_set, i);
2701 if (cond != NULL_RTX
2702 && ! REGNO_REG_SET_P (pbi->local_set, i))
2703 SET_REGNO_REG_SET (pbi->cond_local_set, i);
2704 else
2705 SET_REGNO_REG_SET (pbi->local_set, i);
f2a1bc02 2706 }
402209ff
JH
2707 if (code != CLOBBER)
2708 SET_REGNO_REG_SET (pbi->new_set, i);
d3a923ee 2709
402209ff
JH
2710 some_was_live |= needed_regno;
2711 some_was_dead |= ! needed_regno;
f2a1bc02 2712 }
402209ff
JH
2713
2714#ifdef HAVE_conditional_execution
2715 /* Consider conditional death in deciding that the register needs
2716 a death note. */
2717 if (some_was_live && ! not_dead
2718 /* The stack pointer is never dead. Well, not strictly true,
2719 but it's very difficult to tell from here. Hopefully
2720 combine_stack_adjustments will fix up the most egregious
2721 errors. */
2722 && regno_first != STACK_POINTER_REGNUM)
d3a923ee 2723 {
402209ff
JH
2724 for (i = regno_first; i <= regno_last; ++i)
2725 if (! mark_regno_cond_dead (pbi, i, cond))
2726 not_dead |= ((unsigned long) 1) << (i - regno_first);
d3a923ee 2727 }
402209ff 2728#endif
6ff71a97 2729
402209ff
JH
2730 /* Additional data to record if this is the final pass. */
2731 if (flags & (PROP_LOG_LINKS | PROP_REG_INFO
2732 | PROP_DEATH_NOTES | PROP_AUTOINC))
f2a1bc02 2733 {
b3694847 2734 rtx y;
0b17ab2f 2735 int blocknum = pbi->bb->index;
402209ff
JH
2736
2737 y = NULL_RTX;
2738 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
ca9fef16 2739 {
402209ff 2740 y = pbi->reg_next_use[regno_first];
ca9fef16 2741
402209ff
JH
2742 /* The next use is no longer next, since a store intervenes. */
2743 for (i = regno_first; i <= regno_last; ++i)
2744 pbi->reg_next_use[i] = 0;
2745 }
6e64a52a 2746
402209ff 2747 if (flags & PROP_REG_INFO)
46fac664 2748 {
402209ff
JH
2749 for (i = regno_first; i <= regno_last; ++i)
2750 {
2751 /* Count (weighted) references, stores, etc. This counts a
2752 register twice if it is modified, but that is correct. */
2753 REG_N_SETS (i) += 1;
2754 REG_N_REFS (i) += 1;
2755 REG_FREQ (i) += REG_FREQ_FROM_BB (pbi->bb);
2756
2757 /* The insns where a reg is live are normally counted
2758 elsewhere, but we want the count to include the insn
2759 where the reg is set, and the normal counting mechanism
2760 would not count it. */
2761 REG_LIVE_LENGTH (i) += 1;
2762 }
2763
2764 /* If this is a hard reg, record this function uses the reg. */
2765 if (regno_first < FIRST_PSEUDO_REGISTER)
6e64a52a 2766 {
402209ff
JH
2767 for (i = regno_first; i <= regno_last; i++)
2768 regs_ever_live[i] = 1;
6e64a52a
JH
2769 }
2770 else
6e64a52a 2771 {
402209ff
JH
2772 /* Keep track of which basic blocks each reg appears in. */
2773 if (REG_BASIC_BLOCK (regno_first) == REG_BLOCK_UNKNOWN)
2774 REG_BASIC_BLOCK (regno_first) = blocknum;
2775 else if (REG_BASIC_BLOCK (regno_first) != blocknum)
2776 REG_BASIC_BLOCK (regno_first) = REG_BLOCK_GLOBAL;
6e64a52a 2777 }
402209ff 2778 }
f2a1bc02 2779
402209ff 2780 if (! some_was_dead)
f2a1bc02 2781 {
402209ff
JH
2782 if (flags & PROP_LOG_LINKS)
2783 {
2784 /* Make a logical link from the next following insn
2785 that uses this register, back to this insn.
2786 The following insns have already been processed.
2787
2788 We don't build a LOG_LINK for hard registers containing
2789 in ASM_OPERANDs. If these registers get replaced,
2790 we might wind up changing the semantics of the insn,
2791 even if reload can make what appear to be valid
2792 assignments later. */
2793 if (y && (BLOCK_NUM (y) == blocknum)
2794 && (regno_first >= FIRST_PSEUDO_REGISTER
2795 || asm_noperands (PATTERN (y)) < 0))
2796 LOG_LINKS (y) = alloc_INSN_LIST (insn, LOG_LINKS (y));
2797 }
34487bf8 2798 }
402209ff
JH
2799 else if (not_dead)
2800 ;
2801 else if (! some_was_live)
2802 {
2803 if (flags & PROP_REG_INFO)
2804 REG_N_DEATHS (regno_first) += 1;
34487bf8 2805
402209ff
JH
2806 if (flags & PROP_DEATH_NOTES)
2807 {
2808 /* Note that dead stores have already been deleted
2809 when possible. If we get here, we have found a
2810 dead store that cannot be eliminated (because the
2811 same insn does something useful). Indicate this
2812 by marking the reg being set as dying here. */
2813 REG_NOTES (insn)
2814 = alloc_EXPR_LIST (REG_UNUSED, reg, REG_NOTES (insn));
2815 }
2816 }
2817 else
34487bf8 2818 {
402209ff
JH
2819 if (flags & PROP_DEATH_NOTES)
2820 {
2821 /* This is a case where we have a multi-word hard register
2822 and some, but not all, of the words of the register are
2823 needed in subsequent insns. Write REG_UNUSED notes
2824 for those parts that were not needed. This case should
2825 be rare. */
2826
2827 for (i = regno_first; i <= regno_last; ++i)
2828 if (! REGNO_REG_SET_P (pbi->reg_live, i))
2829 REG_NOTES (insn)
2830 = alloc_EXPR_LIST (REG_UNUSED,
e50126e8 2831 regno_reg_rtx[i],
402209ff
JH
2832 REG_NOTES (insn));
2833 }
34487bf8 2834 }
34487bf8 2835 }
402209ff
JH
2836
2837 /* Mark the register as being dead. */
2838 if (some_was_live
2839 /* The stack pointer is never dead. Well, not strictly true,
2840 but it's very difficult to tell from here. Hopefully
2841 combine_stack_adjustments will fix up the most egregious
2842 errors. */
2843 && regno_first != STACK_POINTER_REGNUM)
34487bf8 2844 {
402209ff
JH
2845 for (i = regno_first; i <= regno_last; ++i)
2846 if (!(not_dead & (((unsigned long) 1) << (i - regno_first))))
2847 CLEAR_REGNO_REG_SET (pbi->reg_live, i);
34487bf8 2848 }
402209ff
JH
2849 }
2850 else if (GET_CODE (reg) == REG)
2851 {
2852 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
2853 pbi->reg_next_use[regno_first] = 0;
2854 }
2855
2856 /* If this is the last pass and this is a SCRATCH, show it will be dying
2857 here and count it. */
2858 else if (GET_CODE (reg) == SCRATCH)
2859 {
2860 if (flags & PROP_DEATH_NOTES)
2861 REG_NOTES (insn)
2862 = alloc_EXPR_LIST (REG_UNUSED, reg, REG_NOTES (insn));
2863 }
2864}
2865\f
2866#ifdef HAVE_conditional_execution
2867/* Mark REGNO conditionally dead.
2868 Return true if the register is now unconditionally dead. */
2869
2870static int
2871mark_regno_cond_dead (pbi, regno, cond)
2872 struct propagate_block_info *pbi;
2873 int regno;
2874 rtx cond;
2875{
2876 /* If this is a store to a predicate register, the value of the
2877 predicate is changing, we don't know that the predicate as seen
2878 before is the same as that seen after. Flush all dependent
2879 conditions from reg_cond_dead. This will make all such
2880 conditionally live registers unconditionally live. */
2881 if (REGNO_REG_SET_P (pbi->reg_cond_reg, regno))
2882 flush_reg_cond_reg (pbi, regno);
2883
2884 /* If this is an unconditional store, remove any conditional
2885 life that may have existed. */
2886 if (cond == NULL_RTX)
2887 splay_tree_remove (pbi->reg_cond_dead, regno);
2888 else
2889 {
2890 splay_tree_node node;
2891 struct reg_cond_life_info *rcli;
2892 rtx ncond;
2893
2894 /* Otherwise this is a conditional set. Record that fact.
2895 It may have been conditionally used, or there may be a
2896 subsequent set with a complimentary condition. */
34487bf8 2897
402209ff
JH
2898 node = splay_tree_lookup (pbi->reg_cond_dead, regno);
2899 if (node == NULL)
34487bf8 2900 {
402209ff
JH
2901 /* The register was unconditionally live previously.
2902 Record the current condition as the condition under
2903 which it is dead. */
2904 rcli = (struct reg_cond_life_info *) xmalloc (sizeof (*rcli));
2905 rcli->condition = cond;
2906 rcli->stores = cond;
2907 rcli->orig_condition = const0_rtx;
2908 splay_tree_insert (pbi->reg_cond_dead, regno,
2909 (splay_tree_value) rcli);
2910
2911 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
2912
d6a7951f 2913 /* Not unconditionally dead. */
402209ff 2914 return 0;
34487bf8
RH
2915 }
2916 else
2917 {
402209ff
JH
2918 /* The register was conditionally live previously.
2919 Add the new condition to the old. */
2920 rcli = (struct reg_cond_life_info *) node->value;
2921 ncond = rcli->condition;
2922 ncond = ior_reg_cond (ncond, cond, 1);
2923 if (rcli->stores == const0_rtx)
2924 rcli->stores = cond;
2925 else if (rcli->stores != const1_rtx)
2926 rcli->stores = ior_reg_cond (rcli->stores, cond, 1);
34487bf8 2927
402209ff
JH
2928 /* If the register is now unconditionally dead, remove the entry
2929 in the splay_tree. A register is unconditionally dead if the
2930 dead condition ncond is true. A register is also unconditionally
2931 dead if the sum of all conditional stores is an unconditional
2932 store (stores is true), and the dead condition is identically the
2933 same as the original dead condition initialized at the end of
2934 the block. This is a pointer compare, not an rtx_equal_p
2935 compare. */
2936 if (ncond == const1_rtx
2937 || (ncond == rcli->orig_condition && rcli->stores == const1_rtx))
2938 splay_tree_remove (pbi->reg_cond_dead, regno);
2939 else
2940 {
2941 rcli->condition = ncond;
34487bf8 2942
402209ff 2943 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
34487bf8 2944
d6a7951f 2945 /* Not unconditionally dead. */
402209ff 2946 return 0;
34487bf8
RH
2947 }
2948 }
2949 }
2950
402209ff
JH
2951 return 1;
2952}
bce7bfe8 2953
402209ff 2954/* Called from splay_tree_delete for pbi->reg_cond_life. */
b9f22704 2955
402209ff
JH
2956static void
2957free_reg_cond_life_info (value)
2958 splay_tree_value value;
2959{
2960 struct reg_cond_life_info *rcli = (struct reg_cond_life_info *) value;
2961 free (rcli);
2962}
18ca529b 2963
402209ff 2964/* Helper function for flush_reg_cond_reg. */
34487bf8 2965
402209ff
JH
2966static int
2967flush_reg_cond_reg_1 (node, data)
2968 splay_tree_node node;
2969 void *data;
2970{
2971 struct reg_cond_life_info *rcli;
2972 int *xdata = (int *) data;
2973 unsigned int regno = xdata[0];
34487bf8 2974
402209ff
JH
2975 /* Don't need to search if last flushed value was farther on in
2976 the in-order traversal. */
2977 if (xdata[1] >= (int) node->key)
2978 return 0;
34487bf8 2979
402209ff
JH
2980 /* Splice out portions of the expression that refer to regno. */
2981 rcli = (struct reg_cond_life_info *) node->value;
2982 rcli->condition = elim_reg_cond (rcli->condition, regno);
2983 if (rcli->stores != const0_rtx && rcli->stores != const1_rtx)
2984 rcli->stores = elim_reg_cond (rcli->stores, regno);
0edd203b 2985
402209ff
JH
2986 /* If the entire condition is now false, signal the node to be removed. */
2987 if (rcli->condition == const0_rtx)
2988 {
2989 xdata[1] = node->key;
2990 return -1;
34487bf8 2991 }
402209ff
JH
2992 else if (rcli->condition == const1_rtx)
2993 abort ();
d3a923ee 2994
402209ff 2995 return 0;
34487bf8 2996}
410538ea 2997
402209ff 2998/* Flush all (sub) expressions referring to REGNO from REG_COND_LIVE. */
410538ea 2999
402209ff
JH
3000static void
3001flush_reg_cond_reg (pbi, regno)
3002 struct propagate_block_info *pbi;
3003 int regno;
3004{
3005 int pair[2];
410538ea 3006
402209ff
JH
3007 pair[0] = regno;
3008 pair[1] = -1;
3009 while (splay_tree_foreach (pbi->reg_cond_dead,
3010 flush_reg_cond_reg_1, pair) == -1)
3011 splay_tree_remove (pbi->reg_cond_dead, pair[1]);
410538ea 3012
402209ff
JH
3013 CLEAR_REGNO_REG_SET (pbi->reg_cond_reg, regno);
3014}
410538ea 3015
402209ff
JH
3016/* Logical arithmetic on predicate conditions. IOR, NOT and AND.
3017 For ior/and, the ADD flag determines whether we want to add the new
3018 condition X to the old one unconditionally. If it is zero, we will
3019 only return a new expression if X allows us to simplify part of
b318748f 3020 OLD, otherwise we return NULL to the caller.
402209ff
JH
3021 If ADD is nonzero, we will return a new condition in all cases. The
3022 toplevel caller of one of these functions should always pass 1 for
3023 ADD. */
410538ea 3024
402209ff
JH
3025static rtx
3026ior_reg_cond (old, x, add)
3027 rtx old, x;
3028 int add;
3029{
3030 rtx op0, op1;
410538ea 3031
402209ff 3032 if (GET_RTX_CLASS (GET_CODE (old)) == '<')
410538ea 3033 {
402209ff
JH
3034 if (GET_RTX_CLASS (GET_CODE (x)) == '<'
3035 && REVERSE_CONDEXEC_PREDICATES_P (GET_CODE (x), GET_CODE (old))
3036 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3037 return const1_rtx;
3038 if (GET_CODE (x) == GET_CODE (old)
3039 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3040 return old;
3041 if (! add)
b318748f 3042 return NULL;
402209ff 3043 return gen_rtx_IOR (0, old, x);
410538ea 3044 }
c9bacfdb 3045
402209ff 3046 switch (GET_CODE (old))
410538ea 3047 {
402209ff
JH
3048 case IOR:
3049 op0 = ior_reg_cond (XEXP (old, 0), x, 0);
3050 op1 = ior_reg_cond (XEXP (old, 1), x, 0);
b318748f 3051 if (op0 != NULL || op1 != NULL)
402209ff
JH
3052 {
3053 if (op0 == const0_rtx)
b318748f 3054 return op1 ? op1 : gen_rtx_IOR (0, XEXP (old, 1), x);
402209ff 3055 if (op1 == const0_rtx)
b318748f 3056 return op0 ? op0 : gen_rtx_IOR (0, XEXP (old, 0), x);
402209ff
JH
3057 if (op0 == const1_rtx || op1 == const1_rtx)
3058 return const1_rtx;
b318748f
JJ
3059 if (op0 == NULL)
3060 op0 = gen_rtx_IOR (0, XEXP (old, 0), x);
3061 else if (rtx_equal_p (x, op0))
3062 /* (x | A) | x ~ (x | A). */
3063 return old;
3064 if (op1 == NULL)
3065 op1 = gen_rtx_IOR (0, XEXP (old, 1), x);
3066 else if (rtx_equal_p (x, op1))
3067 /* (A | x) | x ~ (A | x). */
3068 return old;
402209ff
JH
3069 return gen_rtx_IOR (0, op0, op1);
3070 }
3071 if (! add)
b318748f 3072 return NULL;
402209ff 3073 return gen_rtx_IOR (0, old, x);
410538ea 3074
402209ff
JH
3075 case AND:
3076 op0 = ior_reg_cond (XEXP (old, 0), x, 0);
3077 op1 = ior_reg_cond (XEXP (old, 1), x, 0);
b318748f 3078 if (op0 != NULL || op1 != NULL)
410538ea 3079 {
402209ff 3080 if (op0 == const1_rtx)
b318748f 3081 return op1 ? op1 : gen_rtx_IOR (0, XEXP (old, 1), x);
402209ff 3082 if (op1 == const1_rtx)
b318748f 3083 return op0 ? op0 : gen_rtx_IOR (0, XEXP (old, 0), x);
402209ff
JH
3084 if (op0 == const0_rtx || op1 == const0_rtx)
3085 return const0_rtx;
b318748f
JJ
3086 if (op0 == NULL)
3087 op0 = gen_rtx_IOR (0, XEXP (old, 0), x);
3088 else if (rtx_equal_p (x, op0))
3089 /* (x & A) | x ~ x. */
3090 return op0;
3091 if (op1 == NULL)
3092 op1 = gen_rtx_IOR (0, XEXP (old, 1), x);
3093 else if (rtx_equal_p (x, op1))
3094 /* (A & x) | x ~ x. */
3095 return op1;
402209ff 3096 return gen_rtx_AND (0, op0, op1);
410538ea 3097 }
402209ff 3098 if (! add)
b318748f 3099 return NULL;
402209ff 3100 return gen_rtx_IOR (0, old, x);
410538ea 3101
402209ff
JH
3102 case NOT:
3103 op0 = and_reg_cond (XEXP (old, 0), not_reg_cond (x), 0);
b318748f 3104 if (op0 != NULL)
402209ff
JH
3105 return not_reg_cond (op0);
3106 if (! add)
b318748f 3107 return NULL;
402209ff 3108 return gen_rtx_IOR (0, old, x);
c9bacfdb 3109
402209ff
JH
3110 default:
3111 abort ();
410538ea
AM
3112 }
3113}
3114
402209ff
JH
3115static rtx
3116not_reg_cond (x)
3117 rtx x;
410538ea 3118{
402209ff 3119 enum rtx_code x_code;
410538ea 3120
402209ff
JH
3121 if (x == const0_rtx)
3122 return const1_rtx;
3123 else if (x == const1_rtx)
3124 return const0_rtx;
3125 x_code = GET_CODE (x);
3126 if (x_code == NOT)
3127 return XEXP (x, 0);
3128 if (GET_RTX_CLASS (x_code) == '<'
3129 && GET_CODE (XEXP (x, 0)) == REG)
410538ea 3130 {
402209ff
JH
3131 if (XEXP (x, 1) != const0_rtx)
3132 abort ();
410538ea 3133
402209ff
JH
3134 return gen_rtx_fmt_ee (reverse_condition (x_code),
3135 VOIDmode, XEXP (x, 0), const0_rtx);
410538ea 3136 }
402209ff 3137 return gen_rtx_NOT (0, x);
410538ea
AM
3138}
3139
402209ff
JH
3140static rtx
3141and_reg_cond (old, x, add)
3142 rtx old, x;
3143 int add;
410538ea 3144{
402209ff 3145 rtx op0, op1;
410538ea 3146
402209ff 3147 if (GET_RTX_CLASS (GET_CODE (old)) == '<')
410538ea 3148 {
402209ff
JH
3149 if (GET_RTX_CLASS (GET_CODE (x)) == '<'
3150 && GET_CODE (x) == reverse_condition (GET_CODE (old))
3151 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3152 return const0_rtx;
3153 if (GET_CODE (x) == GET_CODE (old)
3154 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3155 return old;
3156 if (! add)
b318748f 3157 return NULL;
402209ff
JH
3158 return gen_rtx_AND (0, old, x);
3159 }
410538ea 3160
402209ff
JH
3161 switch (GET_CODE (old))
3162 {
3163 case IOR:
3164 op0 = and_reg_cond (XEXP (old, 0), x, 0);
3165 op1 = and_reg_cond (XEXP (old, 1), x, 0);
b318748f 3166 if (op0 != NULL || op1 != NULL)
410538ea 3167 {
402209ff 3168 if (op0 == const0_rtx)
b318748f 3169 return op1 ? op1 : gen_rtx_AND (0, XEXP (old, 1), x);
402209ff 3170 if (op1 == const0_rtx)
b318748f 3171 return op0 ? op0 : gen_rtx_AND (0, XEXP (old, 0), x);
402209ff
JH
3172 if (op0 == const1_rtx || op1 == const1_rtx)
3173 return const1_rtx;
b318748f
JJ
3174 if (op0 == NULL)
3175 op0 = gen_rtx_AND (0, XEXP (old, 0), x);
3176 else if (rtx_equal_p (x, op0))
3177 /* (x | A) & x ~ x. */
3178 return op0;
3179 if (op1 == NULL)
3180 op1 = gen_rtx_AND (0, XEXP (old, 1), x);
3181 else if (rtx_equal_p (x, op1))
3182 /* (A | x) & x ~ x. */
3183 return op1;
402209ff 3184 return gen_rtx_IOR (0, op0, op1);
410538ea 3185 }
402209ff 3186 if (! add)
b318748f 3187 return NULL;
402209ff
JH
3188 return gen_rtx_AND (0, old, x);
3189
3190 case AND:
3191 op0 = and_reg_cond (XEXP (old, 0), x, 0);
3192 op1 = and_reg_cond (XEXP (old, 1), x, 0);
b318748f 3193 if (op0 != NULL || op1 != NULL)
410538ea 3194 {
402209ff 3195 if (op0 == const1_rtx)
b318748f 3196 return op1 ? op1 : gen_rtx_AND (0, XEXP (old, 1), x);
402209ff 3197 if (op1 == const1_rtx)
b318748f 3198 return op0 ? op0 : gen_rtx_AND (0, XEXP (old, 0), x);
402209ff
JH
3199 if (op0 == const0_rtx || op1 == const0_rtx)
3200 return const0_rtx;
b318748f
JJ
3201 if (op0 == NULL)
3202 op0 = gen_rtx_AND (0, XEXP (old, 0), x);
3203 else if (rtx_equal_p (x, op0))
3204 /* (x & A) & x ~ (x & A). */
3205 return old;
3206 if (op1 == NULL)
3207 op1 = gen_rtx_AND (0, XEXP (old, 1), x);
3208 else if (rtx_equal_p (x, op1))
3209 /* (A & x) & x ~ (A & x). */
3210 return old;
402209ff 3211 return gen_rtx_AND (0, op0, op1);
410538ea 3212 }
402209ff 3213 if (! add)
b318748f 3214 return NULL;
402209ff 3215 return gen_rtx_AND (0, old, x);
410538ea 3216
402209ff
JH
3217 case NOT:
3218 op0 = ior_reg_cond (XEXP (old, 0), not_reg_cond (x), 0);
b318748f 3219 if (op0 != NULL)
402209ff
JH
3220 return not_reg_cond (op0);
3221 if (! add)
b318748f 3222 return NULL;
402209ff 3223 return gen_rtx_AND (0, old, x);
410538ea 3224
402209ff
JH
3225 default:
3226 abort ();
c9bacfdb 3227 }
410538ea
AM
3228}
3229
402209ff
JH
3230/* Given a condition X, remove references to reg REGNO and return the
3231 new condition. The removal will be done so that all conditions
3232 involving REGNO are considered to evaluate to false. This function
3233 is used when the value of REGNO changes. */
c9bacfdb 3234
402209ff
JH
3235static rtx
3236elim_reg_cond (x, regno)
3237 rtx x;
3238 unsigned int regno;
410538ea 3239{
402209ff
JH
3240 rtx op0, op1;
3241
3242 if (GET_RTX_CLASS (GET_CODE (x)) == '<')
410538ea 3243 {
402209ff
JH
3244 if (REGNO (XEXP (x, 0)) == regno)
3245 return const0_rtx;
3246 return x;
410538ea 3247 }
c9bacfdb 3248
402209ff
JH
3249 switch (GET_CODE (x))
3250 {
3251 case AND:
3252 op0 = elim_reg_cond (XEXP (x, 0), regno);
3253 op1 = elim_reg_cond (XEXP (x, 1), regno);
3254 if (op0 == const0_rtx || op1 == const0_rtx)
3255 return const0_rtx;
3256 if (op0 == const1_rtx)
3257 return op1;
3258 if (op1 == const1_rtx)
3259 return op0;
3260 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
3261 return x;
3262 return gen_rtx_AND (0, op0, op1);
87fdf7ff 3263
402209ff
JH
3264 case IOR:
3265 op0 = elim_reg_cond (XEXP (x, 0), regno);
3266 op1 = elim_reg_cond (XEXP (x, 1), regno);
3267 if (op0 == const1_rtx || op1 == const1_rtx)
3268 return const1_rtx;
3269 if (op0 == const0_rtx)
3270 return op1;
3271 if (op1 == const0_rtx)
3272 return op0;
3273 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
3274 return x;
3275 return gen_rtx_IOR (0, op0, op1);
87fdf7ff 3276
402209ff
JH
3277 case NOT:
3278 op0 = elim_reg_cond (XEXP (x, 0), regno);
3279 if (op0 == const0_rtx)
3280 return const1_rtx;
3281 if (op0 == const1_rtx)
3282 return const0_rtx;
3283 if (op0 != XEXP (x, 0))
3284 return not_reg_cond (op0);
3285 return x;
87fdf7ff 3286
402209ff
JH
3287 default:
3288 abort ();
3289 }
87fdf7ff 3290}
402209ff
JH
3291#endif /* HAVE_conditional_execution */
3292\f
3293#ifdef AUTO_INC_DEC
87fdf7ff 3294
402209ff
JH
3295/* Try to substitute the auto-inc expression INC as the address inside
3296 MEM which occurs in INSN. Currently, the address of MEM is an expression
3297 involving INCR_REG, and INCR is the next use of INCR_REG; it is an insn
3298 that has a single set whose source is a PLUS of INCR_REG and something
3299 else. */
c9bacfdb 3300
87fdf7ff 3301static void
402209ff
JH
3302attempt_auto_inc (pbi, inc, insn, mem, incr, incr_reg)
3303 struct propagate_block_info *pbi;
3304 rtx inc, insn, mem, incr, incr_reg;
87fdf7ff 3305{
402209ff
JH
3306 int regno = REGNO (incr_reg);
3307 rtx set = single_set (incr);
3308 rtx q = SET_DEST (set);
3309 rtx y = SET_SRC (set);
3310 int opnum = XEXP (y, 0) == incr_reg ? 0 : 1;
c9bacfdb 3311
402209ff
JH
3312 /* Make sure this reg appears only once in this insn. */
3313 if (count_occurrences (PATTERN (insn), incr_reg, 1) != 1)
3314 return;
87fdf7ff 3315
402209ff
JH
3316 if (dead_or_set_p (incr, incr_reg)
3317 /* Mustn't autoinc an eliminable register. */
3318 && (regno >= FIRST_PSEUDO_REGISTER
3319 || ! TEST_HARD_REG_BIT (elim_reg_set, regno)))
3320 {
3321 /* This is the simple case. Try to make the auto-inc. If
3322 we can't, we are done. Otherwise, we will do any
3323 needed updates below. */
3324 if (! validate_change (insn, &XEXP (mem, 0), inc, 0))
3325 return;
3326 }
3327 else if (GET_CODE (q) == REG
3328 /* PREV_INSN used here to check the semi-open interval
3329 [insn,incr). */
3330 && ! reg_used_between_p (q, PREV_INSN (insn), incr)
3331 /* We must also check for sets of q as q may be
3332 a call clobbered hard register and there may
3333 be a call between PREV_INSN (insn) and incr. */
3334 && ! reg_set_between_p (q, PREV_INSN (insn), incr))
3335 {
3336 /* We have *p followed sometime later by q = p+size.
3337 Both p and q must be live afterward,
3338 and q is not used between INSN and its assignment.
3339 Change it to q = p, ...*q..., q = q+size.
3340 Then fall into the usual case. */
3341 rtx insns, temp;
d3a923ee 3342
402209ff
JH
3343 start_sequence ();
3344 emit_move_insn (q, incr_reg);
3345 insns = get_insns ();
3346 end_sequence ();
87fdf7ff 3347
402209ff
JH
3348 /* If we can't make the auto-inc, or can't make the
3349 replacement into Y, exit. There's no point in making
3350 the change below if we can't do the auto-inc and doing
3351 so is not correct in the pre-inc case. */
87fdf7ff 3352
402209ff
JH
3353 XEXP (inc, 0) = q;
3354 validate_change (insn, &XEXP (mem, 0), inc, 1);
3355 validate_change (incr, &XEXP (y, opnum), q, 1);
3356 if (! apply_change_group ())
3357 return;
f008a564 3358
402209ff
JH
3359 /* We now know we'll be doing this change, so emit the
3360 new insn(s) and do the updates. */
2f937369 3361 emit_insn_before (insns, insn);
f008a564 3362
402209ff
JH
3363 if (pbi->bb->head == insn)
3364 pbi->bb->head = insns;
b53978a3 3365
402209ff
JH
3366 /* INCR will become a NOTE and INSN won't contain a
3367 use of INCR_REG. If a use of INCR_REG was just placed in
3368 the insn before INSN, make that the next use.
3369 Otherwise, invalidate it. */
3370 if (GET_CODE (PREV_INSN (insn)) == INSN
3371 && GET_CODE (PATTERN (PREV_INSN (insn))) == SET
3372 && SET_SRC (PATTERN (PREV_INSN (insn))) == incr_reg)
3373 pbi->reg_next_use[regno] = PREV_INSN (insn);
3374 else
3375 pbi->reg_next_use[regno] = 0;
c9bacfdb 3376
402209ff
JH
3377 incr_reg = q;
3378 regno = REGNO (q);
b53978a3 3379
402209ff
JH
3380 /* REGNO is now used in INCR which is below INSN, but
3381 it previously wasn't live here. If we don't mark
3382 it as live, we'll put a REG_DEAD note for it
3383 on this insn, which is incorrect. */
3384 SET_REGNO_REG_SET (pbi->reg_live, regno);
b53978a3 3385
402209ff
JH
3386 /* If there are any calls between INSN and INCR, show
3387 that REGNO now crosses them. */
3388 for (temp = insn; temp != incr; temp = NEXT_INSN (temp))
3389 if (GET_CODE (temp) == CALL_INSN)
3390 REG_N_CALLS_CROSSED (regno)++;
c9bacfdb 3391
402209ff
JH
3392 /* Invalidate alias info for Q since we just changed its value. */
3393 clear_reg_alias_info (q);
b53978a3 3394 }
402209ff
JH
3395 else
3396 return;
b53978a3 3397
402209ff
JH
3398 /* If we haven't returned, it means we were able to make the
3399 auto-inc, so update the status. First, record that this insn
3400 has an implicit side effect. */
f008a564 3401
402209ff 3402 REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, incr_reg, REG_NOTES (insn));
f008a564 3403
402209ff
JH
3404 /* Modify the old increment-insn to simply copy
3405 the already-incremented value of our register. */
3406 if (! validate_change (incr, &SET_SRC (set), incr_reg, 0))
3407 abort ();
ca9fef16 3408
402209ff
JH
3409 /* If that makes it a no-op (copying the register into itself) delete
3410 it so it won't appear to be a "use" and a "set" of this
3411 register. */
3412 if (REGNO (SET_DEST (set)) == REGNO (incr_reg))
ca9fef16 3413 {
402209ff
JH
3414 /* If the original source was dead, it's dead now. */
3415 rtx note;
ca9fef16 3416
402209ff
JH
3417 while ((note = find_reg_note (incr, REG_DEAD, NULL_RTX)) != NULL_RTX)
3418 {
3419 remove_note (incr, note);
3420 if (XEXP (note, 0) != incr_reg)
3421 CLEAR_REGNO_REG_SET (pbi->reg_live, REGNO (XEXP (note, 0)));
3422 }
c9bacfdb 3423
402209ff
JH
3424 PUT_CODE (incr, NOTE);
3425 NOTE_LINE_NUMBER (incr) = NOTE_INSN_DELETED;
3426 NOTE_SOURCE_FILE (incr) = 0;
3427 }
f008a564 3428
402209ff
JH
3429 if (regno >= FIRST_PSEUDO_REGISTER)
3430 {
3431 /* Count an extra reference to the reg. When a reg is
3432 incremented, spilling it is worse, so we want to make
3433 that less likely. */
3434 REG_FREQ (regno) += REG_FREQ_FROM_BB (pbi->bb);
f008a564 3435
402209ff
JH
3436 /* Count the increment as a setting of the register,
3437 even though it isn't a SET in rtl. */
3438 REG_N_SETS (regno)++;
3439 }
f008a564 3440}
402209ff
JH
3441
3442/* X is a MEM found in INSN. See if we can convert it into an auto-increment
3443 reference. */
c9bacfdb 3444
21c7361e 3445static void
402209ff
JH
3446find_auto_inc (pbi, x, insn)
3447 struct propagate_block_info *pbi;
3448 rtx x;
3449 rtx insn;
4dc9341c 3450{
402209ff
JH
3451 rtx addr = XEXP (x, 0);
3452 HOST_WIDE_INT offset = 0;
3453 rtx set, y, incr, inc_val;
3454 int regno;
3455 int size = GET_MODE_SIZE (GET_MODE (x));
4dc9341c 3456
402209ff 3457 if (GET_CODE (insn) == JUMP_INSN)
135ebc36
MH
3458 return;
3459
402209ff
JH
3460 /* Here we detect use of an index register which might be good for
3461 postincrement, postdecrement, preincrement, or predecrement. */
3462
3463 if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3464 offset = INTVAL (XEXP (addr, 1)), addr = XEXP (addr, 0);
4dc9341c 3465
402209ff
JH
3466 if (GET_CODE (addr) != REG)
3467 return;
c9bacfdb 3468
402209ff 3469 regno = REGNO (addr);
135ebc36 3470
402209ff
JH
3471 /* Is the next use an increment that might make auto-increment? */
3472 incr = pbi->reg_next_use[regno];
3473 if (incr == 0 || BLOCK_NUM (incr) != BLOCK_NUM (insn))
3474 return;
3475 set = single_set (incr);
3476 if (set == 0 || GET_CODE (set) != SET)
3477 return;
3478 y = SET_SRC (set);
4dc9341c 3479
402209ff 3480 if (GET_CODE (y) != PLUS)
135ebc36
MH
3481 return;
3482
402209ff
JH
3483 if (REG_P (XEXP (y, 0)) && REGNO (XEXP (y, 0)) == REGNO (addr))
3484 inc_val = XEXP (y, 1);
3485 else if (REG_P (XEXP (y, 1)) && REGNO (XEXP (y, 1)) == REGNO (addr))
3486 inc_val = XEXP (y, 0);
3487 else
3488 return;
4dc9341c 3489
402209ff
JH
3490 if (GET_CODE (inc_val) == CONST_INT)
3491 {
3492 if (HAVE_POST_INCREMENT
3493 && (INTVAL (inc_val) == size && offset == 0))
3494 attempt_auto_inc (pbi, gen_rtx_POST_INC (Pmode, addr), insn, x,
3495 incr, addr);
3496 else if (HAVE_POST_DECREMENT
3497 && (INTVAL (inc_val) == -size && offset == 0))
3498 attempt_auto_inc (pbi, gen_rtx_POST_DEC (Pmode, addr), insn, x,
3499 incr, addr);
3500 else if (HAVE_PRE_INCREMENT
3501 && (INTVAL (inc_val) == size && offset == size))
3502 attempt_auto_inc (pbi, gen_rtx_PRE_INC (Pmode, addr), insn, x,
3503 incr, addr);
3504 else if (HAVE_PRE_DECREMENT
3505 && (INTVAL (inc_val) == -size && offset == -size))
3506 attempt_auto_inc (pbi, gen_rtx_PRE_DEC (Pmode, addr), insn, x,
3507 incr, addr);
3508 else if (HAVE_POST_MODIFY_DISP && offset == 0)
3509 attempt_auto_inc (pbi, gen_rtx_POST_MODIFY (Pmode, addr,
3510 gen_rtx_PLUS (Pmode,
3511 addr,
3512 inc_val)),
3513 insn, x, incr, addr);
3514 }
3515 else if (GET_CODE (inc_val) == REG
3516 && ! reg_set_between_p (inc_val, PREV_INSN (insn),
3517 NEXT_INSN (incr)))
135ebc36 3518
402209ff
JH
3519 {
3520 if (HAVE_POST_MODIFY_REG && offset == 0)
3521 attempt_auto_inc (pbi, gen_rtx_POST_MODIFY (Pmode, addr,
3522 gen_rtx_PLUS (Pmode,
3523 addr,
3524 inc_val)),
3525 insn, x, incr, addr);
3526 }
3527}
c9bacfdb 3528
402209ff
JH
3529#endif /* AUTO_INC_DEC */
3530\f
4dc9341c 3531static void
402209ff
JH
3532mark_used_reg (pbi, reg, cond, insn)
3533 struct propagate_block_info *pbi;
3534 rtx reg;
3535 rtx cond ATTRIBUTE_UNUSED;
3536 rtx insn;
4dc9341c 3537{
402209ff
JH
3538 unsigned int regno_first, regno_last, i;
3539 int some_was_live, some_was_dead, some_not_set;
4dc9341c 3540
402209ff
JH
3541 regno_last = regno_first = REGNO (reg);
3542 if (regno_first < FIRST_PSEUDO_REGISTER)
3543 regno_last += HARD_REGNO_NREGS (regno_first, GET_MODE (reg)) - 1;
4dc9341c 3544
402209ff
JH
3545 /* Find out if any of this register is live after this instruction. */
3546 some_was_live = some_was_dead = 0;
3547 for (i = regno_first; i <= regno_last; ++i)
4dc9341c 3548 {
402209ff
JH
3549 int needed_regno = REGNO_REG_SET_P (pbi->reg_live, i);
3550 some_was_live |= needed_regno;
3551 some_was_dead |= ! needed_regno;
4dc9341c
MH
3552 }
3553
402209ff
JH
3554 /* Find out if any of the register was set this insn. */
3555 some_not_set = 0;
3556 for (i = regno_first; i <= regno_last; ++i)
3557 some_not_set |= ! REGNO_REG_SET_P (pbi->new_set, i);
3558
3559 if (pbi->flags & (PROP_LOG_LINKS | PROP_AUTOINC))
c34d5374 3560 {
402209ff
JH
3561 /* Record where each reg is used, so when the reg is set we know
3562 the next insn that uses it. */
3563 pbi->reg_next_use[regno_first] = insn;
c34d5374 3564 }
c9bacfdb 3565
402209ff
JH
3566 if (pbi->flags & PROP_REG_INFO)
3567 {
3568 if (regno_first < FIRST_PSEUDO_REGISTER)
3569 {
3570 /* If this is a register we are going to try to eliminate,
3571 don't mark it live here. If we are successful in
3572 eliminating it, it need not be live unless it is used for
3573 pseudos, in which case it will have been set live when it
3574 was allocated to the pseudos. If the register will not
3575 be eliminated, reload will set it live at that point.
4dc9341c 3576
402209ff
JH
3577 Otherwise, record that this function uses this register. */
3578 /* ??? The PPC backend tries to "eliminate" on the pic
3579 register to itself. This should be fixed. In the mean
3580 time, hack around it. */
c9bacfdb 3581
402209ff
JH
3582 if (! (TEST_HARD_REG_BIT (elim_reg_set, regno_first)
3583 && (regno_first == FRAME_POINTER_REGNUM
3584 || regno_first == ARG_POINTER_REGNUM)))
3585 for (i = regno_first; i <= regno_last; ++i)
3586 regs_ever_live[i] = 1;
3587 }
3588 else
3589 {
3590 /* Keep track of which basic block each reg appears in. */
6057c0e6 3591
0b17ab2f 3592 int blocknum = pbi->bb->index;
402209ff
JH
3593 if (REG_BASIC_BLOCK (regno_first) == REG_BLOCK_UNKNOWN)
3594 REG_BASIC_BLOCK (regno_first) = blocknum;
3595 else if (REG_BASIC_BLOCK (regno_first) != blocknum)
3596 REG_BASIC_BLOCK (regno_first) = REG_BLOCK_GLOBAL;
6057c0e6 3597
402209ff
JH
3598 /* Count (weighted) number of uses of each reg. */
3599 REG_FREQ (regno_first) += REG_FREQ_FROM_BB (pbi->bb);
3600 REG_N_REFS (regno_first)++;
3601 }
3602 }
6057c0e6 3603
402209ff
JH
3604 /* Record and count the insns in which a reg dies. If it is used in
3605 this insn and was dead below the insn then it dies in this insn.
3606 If it was set in this insn, we do not make a REG_DEAD note;
3607 likewise if we already made such a note. */
3608 if ((pbi->flags & (PROP_DEATH_NOTES | PROP_REG_INFO))
3609 && some_was_dead
3610 && some_not_set)
3611 {
3612 /* Check for the case where the register dying partially
3613 overlaps the register set by this insn. */
3614 if (regno_first != regno_last)
3615 for (i = regno_first; i <= regno_last; ++i)
3616 some_was_live |= REGNO_REG_SET_P (pbi->new_set, i);
4dc9341c 3617
402209ff
JH
3618 /* If none of the words in X is needed, make a REG_DEAD note.
3619 Otherwise, we must make partial REG_DEAD notes. */
3620 if (! some_was_live)
3621 {
3622 if ((pbi->flags & PROP_DEATH_NOTES)
3623 && ! find_regno_note (insn, REG_DEAD, regno_first))
3624 REG_NOTES (insn)
3625 = alloc_EXPR_LIST (REG_DEAD, reg, REG_NOTES (insn));
4dc9341c 3626
402209ff
JH
3627 if (pbi->flags & PROP_REG_INFO)
3628 REG_N_DEATHS (regno_first)++;
3629 }
3630 else
3631 {
3632 /* Don't make a REG_DEAD note for a part of a register
3633 that is set in the insn. */
3634 for (i = regno_first; i <= regno_last; ++i)
3635 if (! REGNO_REG_SET_P (pbi->reg_live, i)
3636 && ! dead_or_set_regno_p (insn, i))
3637 REG_NOTES (insn)
3638 = alloc_EXPR_LIST (REG_DEAD,
e50126e8 3639 regno_reg_rtx[i],
402209ff
JH
3640 REG_NOTES (insn));
3641 }
3642 }
4dc9341c 3643
402209ff
JH
3644 /* Mark the register as being live. */
3645 for (i = regno_first; i <= regno_last; ++i)
4dc9341c 3646 {
9be40833
RH
3647#ifdef HAVE_conditional_execution
3648 int this_was_live = REGNO_REG_SET_P (pbi->reg_live, i);
3649#endif
3650
402209ff 3651 SET_REGNO_REG_SET (pbi->reg_live, i);
4dc9341c 3652
402209ff
JH
3653#ifdef HAVE_conditional_execution
3654 /* If this is a conditional use, record that fact. If it is later
3655 conditionally set, we'll know to kill the register. */
3656 if (cond != NULL_RTX)
4dc9341c 3657 {
402209ff
JH
3658 splay_tree_node node;
3659 struct reg_cond_life_info *rcli;
3660 rtx ncond;
3661
9be40833 3662 if (this_was_live)
402209ff
JH
3663 {
3664 node = splay_tree_lookup (pbi->reg_cond_dead, i);
3665 if (node == NULL)
3666 {
3667 /* The register was unconditionally live previously.
3668 No need to do anything. */
3669 }
3670 else
3671 {
3672 /* The register was conditionally live previously.
3673 Subtract the new life cond from the old death cond. */
3674 rcli = (struct reg_cond_life_info *) node->value;
3675 ncond = rcli->condition;
3676 ncond = and_reg_cond (ncond, not_reg_cond (cond), 1);
4dc9341c 3677
402209ff
JH
3678 /* If the register is now unconditionally live,
3679 remove the entry in the splay_tree. */
3680 if (ncond == const0_rtx)
3681 splay_tree_remove (pbi->reg_cond_dead, i);
3682 else
3683 {
3684 rcli->condition = ncond;
3685 SET_REGNO_REG_SET (pbi->reg_cond_reg,
3686 REGNO (XEXP (cond, 0)));
3687 }
3688 }
3689 }
3690 else
4dc9341c 3691 {
402209ff
JH
3692 /* The register was not previously live at all. Record
3693 the condition under which it is still dead. */
3694 rcli = (struct reg_cond_life_info *) xmalloc (sizeof (*rcli));
3695 rcli->condition = not_reg_cond (cond);
3696 rcli->stores = const0_rtx;
3697 rcli->orig_condition = const0_rtx;
3698 splay_tree_insert (pbi->reg_cond_dead, i,
3699 (splay_tree_value) rcli);
4dc9341c 3700
402209ff 3701 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
4dc9341c
MH
3702 }
3703 }
9be40833 3704 else if (this_was_live)
4dc9341c 3705 {
402209ff
JH
3706 /* The register may have been conditionally live previously, but
3707 is now unconditionally live. Remove it from the conditionally
3708 dead list, so that a conditional set won't cause us to think
3709 it dead. */
3710 splay_tree_remove (pbi->reg_cond_dead, i);
4dc9341c 3711 }
402209ff 3712#endif
4dc9341c
MH
3713 }
3714}
3715
402209ff
JH
3716/* Scan expression X and store a 1-bit in NEW_LIVE for each reg it uses.
3717 This is done assuming the registers needed from X are those that
3718 have 1-bits in PBI->REG_LIVE.
6057c0e6 3719
402209ff
JH
3720 INSN is the containing instruction. If INSN is dead, this function
3721 is not called. */
135ebc36 3722
402209ff
JH
3723static void
3724mark_used_regs (pbi, x, cond, insn)
3725 struct propagate_block_info *pbi;
3726 rtx x, cond, insn;
135ebc36 3727{
b3694847
SS
3728 RTX_CODE code;
3729 int regno;
402209ff 3730 int flags = pbi->flags;
135ebc36 3731
402209ff 3732 retry:
5a133afd
JH
3733 if (!x)
3734 return;
402209ff
JH
3735 code = GET_CODE (x);
3736 switch (code)
135ebc36 3737 {
402209ff
JH
3738 case LABEL_REF:
3739 case SYMBOL_REF:
3740 case CONST_INT:
3741 case CONST:
3742 case CONST_DOUBLE:
69ef87e2 3743 case CONST_VECTOR:
402209ff
JH
3744 case PC:
3745 case ADDR_VEC:
3746 case ADDR_DIFF_VEC:
3747 return;
4dc9341c 3748
402209ff
JH
3749#ifdef HAVE_cc0
3750 case CC0:
3751 pbi->cc0_live = 1;
3752 return;
3753#endif
4dc9341c 3754
402209ff
JH
3755 case CLOBBER:
3756 /* If we are clobbering a MEM, mark any registers inside the address
3757 as being used. */
3758 if (GET_CODE (XEXP (x, 0)) == MEM)
3759 mark_used_regs (pbi, XEXP (XEXP (x, 0), 0), cond, insn);
3760 return;
4dc9341c 3761
402209ff
JH
3762 case MEM:
3763 /* Don't bother watching stores to mems if this is not the
3764 final pass. We'll not be deleting dead stores this round. */
5149f070 3765 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
4dc9341c 3766 {
402209ff
JH
3767 /* Invalidate the data for the last MEM stored, but only if MEM is
3768 something that can be stored into. */
3769 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
3770 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3771 /* Needn't clear the memory set list. */
3772 ;
3773 else
4dc9341c 3774 {
402209ff
JH
3775 rtx temp = pbi->mem_set_list;
3776 rtx prev = NULL_RTX;
3777 rtx next;
3778
3779 while (temp)
3780 {
3781 next = XEXP (temp, 1);
3782 if (anti_dependence (XEXP (temp, 0), x))
3783 {
3784 /* Splice temp out of the list. */
3785 if (prev)
3786 XEXP (prev, 1) = next;
3787 else
3788 pbi->mem_set_list = next;
3789 free_EXPR_LIST_node (temp);
3790 pbi->mem_set_list_len--;
3791 }
3792 else
3793 prev = temp;
3794 temp = next;
3795 }
4dc9341c 3796 }
402209ff
JH
3797
3798 /* If the memory reference had embedded side effects (autoincrement
3799 address modes. Then we may need to kill some entries on the
3800 memory set list. */
3801 if (insn)
fe4b3c79 3802 for_each_rtx (&PATTERN (insn), invalidate_mems_from_autoinc, pbi);
4dc9341c 3803 }
4dc9341c 3804
402209ff
JH
3805#ifdef AUTO_INC_DEC
3806 if (flags & PROP_AUTOINC)
dd3f0101 3807 find_auto_inc (pbi, x, insn);
402209ff
JH
3808#endif
3809 break;
d59c5346 3810
402209ff
JH
3811 case SUBREG:
3812#ifdef CLASS_CANNOT_CHANGE_MODE
3813 if (GET_CODE (SUBREG_REG (x)) == REG
3814 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER
3815 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (x),
3816 GET_MODE (SUBREG_REG (x))))
3817 REG_CHANGES_MODE (REGNO (SUBREG_REG (x))) = 1;
3818#endif
d59c5346 3819
402209ff
JH
3820 /* While we're here, optimize this case. */
3821 x = SUBREG_REG (x);
3822 if (GET_CODE (x) != REG)
3823 goto retry;
3824 /* Fall through. */
d59c5346 3825
402209ff
JH
3826 case REG:
3827 /* See a register other than being set => mark it as needed. */
3828 mark_used_reg (pbi, x, cond, insn);
3829 return;
d59c5346 3830
402209ff
JH
3831 case SET:
3832 {
b3694847 3833 rtx testreg = SET_DEST (x);
402209ff 3834 int mark_dest = 0;
d59c5346 3835
402209ff
JH
3836 /* If storing into MEM, don't show it as being used. But do
3837 show the address as being used. */
3838 if (GET_CODE (testreg) == MEM)
3839 {
3840#ifdef AUTO_INC_DEC
3841 if (flags & PROP_AUTOINC)
3842 find_auto_inc (pbi, testreg, insn);
3843#endif
3844 mark_used_regs (pbi, XEXP (testreg, 0), cond, insn);
3845 mark_used_regs (pbi, SET_SRC (x), cond, insn);
3846 return;
3847 }
d59c5346 3848
402209ff
JH
3849 /* Storing in STRICT_LOW_PART is like storing in a reg
3850 in that this SET might be dead, so ignore it in TESTREG.
3851 but in some other ways it is like using the reg.
d59c5346 3852
402209ff
JH
3853 Storing in a SUBREG or a bit field is like storing the entire
3854 register in that if the register's value is not used
3855 then this SET is not needed. */
3856 while (GET_CODE (testreg) == STRICT_LOW_PART
3857 || GET_CODE (testreg) == ZERO_EXTRACT
3858 || GET_CODE (testreg) == SIGN_EXTRACT
3859 || GET_CODE (testreg) == SUBREG)
3860 {
3861#ifdef CLASS_CANNOT_CHANGE_MODE
3862 if (GET_CODE (testreg) == SUBREG
3863 && GET_CODE (SUBREG_REG (testreg)) == REG
3864 && REGNO (SUBREG_REG (testreg)) >= FIRST_PSEUDO_REGISTER
3865 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (SUBREG_REG (testreg)),
3866 GET_MODE (testreg)))
3867 REG_CHANGES_MODE (REGNO (SUBREG_REG (testreg))) = 1;
3868#endif
d59c5346 3869
402209ff
JH
3870 /* Modifying a single register in an alternate mode
3871 does not use any of the old value. But these other
3872 ways of storing in a register do use the old value. */
3873 if (GET_CODE (testreg) == SUBREG
ec8e621d
KG
3874 && !((REG_BYTES (SUBREG_REG (testreg))
3875 + UNITS_PER_WORD - 1) / UNITS_PER_WORD
3876 > (REG_BYTES (testreg)
3877 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
402209ff
JH
3878 ;
3879 else
3880 mark_dest = 1;
d59c5346 3881
402209ff
JH
3882 testreg = XEXP (testreg, 0);
3883 }
d59c5346 3884
402209ff
JH
3885 /* If this is a store into a register or group of registers,
3886 recursively scan the value being stored. */
d59c5346 3887
402209ff
JH
3888 if ((GET_CODE (testreg) == PARALLEL
3889 && GET_MODE (testreg) == BLKmode)
3890 || (GET_CODE (testreg) == REG
3891 && (regno = REGNO (testreg),
3892 ! (regno == FRAME_POINTER_REGNUM
3893 && (! reload_completed || frame_pointer_needed)))
3894#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
3895 && ! (regno == HARD_FRAME_POINTER_REGNUM
3896 && (! reload_completed || frame_pointer_needed))
3897#endif
3898#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3899 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
3900#endif
3901 ))
3902 {
3903 if (mark_dest)
3904 mark_used_regs (pbi, SET_DEST (x), cond, insn);
3905 mark_used_regs (pbi, SET_SRC (x), cond, insn);
3906 return;
3907 }
3908 }
3909 break;
c9bacfdb 3910
402209ff
JH
3911 case ASM_OPERANDS:
3912 case UNSPEC_VOLATILE:
3913 case TRAP_IF:
3914 case ASM_INPUT:
3915 {
3916 /* Traditional and volatile asm instructions must be considered to use
3917 and clobber all hard registers, all pseudo-registers and all of
3918 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
4dc9341c 3919
402209ff
JH
3920 Consider for instance a volatile asm that changes the fpu rounding
3921 mode. An insn should not be moved across this even if it only uses
3922 pseudo-regs because it might give an incorrectly rounded result.
4dc9341c 3923
402209ff
JH
3924 ?!? Unfortunately, marking all hard registers as live causes massive
3925 problems for the register allocator and marking all pseudos as live
3926 creates mountains of uninitialized variable warnings.
4dc9341c 3927
402209ff
JH
3928 So for now, just clear the memory set list and mark any regs
3929 we can find in ASM_OPERANDS as used. */
3930 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
3931 {
3932 free_EXPR_LIST_list (&pbi->mem_set_list);
3933 pbi->mem_set_list_len = 0;
3934 }
c9bacfdb 3935
402209ff
JH
3936 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
3937 We can not just fall through here since then we would be confused
3938 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
3939 traditional asms unlike their normal usage. */
3940 if (code == ASM_OPERANDS)
3941 {
3942 int j;
628f05b4 3943
402209ff
JH
3944 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
3945 mark_used_regs (pbi, ASM_OPERANDS_INPUT (x, j), cond, insn);
3946 }
3947 break;
3948 }
628f05b4 3949
402209ff
JH
3950 case COND_EXEC:
3951 if (cond != NULL_RTX)
3952 abort ();
c9bacfdb 3953
402209ff 3954 mark_used_regs (pbi, COND_EXEC_TEST (x), NULL_RTX, insn);
c9bacfdb 3955
402209ff
JH
3956 cond = COND_EXEC_TEST (x);
3957 x = COND_EXEC_CODE (x);
3958 goto retry;
628f05b4 3959
402209ff
JH
3960 case PHI:
3961 /* We _do_not_ want to scan operands of phi nodes. Operands of
3962 a phi function are evaluated only when control reaches this
3963 block along a particular edge. Therefore, regs that appear
3964 as arguments to phi should not be added to the global live at
3965 start. */
3966 return;
c9bacfdb 3967
402209ff
JH
3968 default:
3969 break;
4dc9341c 3970 }
628f05b4 3971
402209ff 3972 /* Recursively scan the operands of this expression. */
4dc9341c 3973
402209ff 3974 {
b3694847
SS
3975 const char * const fmt = GET_RTX_FORMAT (code);
3976 int i;
4dc9341c 3977
402209ff
JH
3978 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3979 {
3980 if (fmt[i] == 'e')
3981 {
3982 /* Tail recursive case: save a function call level. */
3983 if (i == 0)
3984 {
3985 x = XEXP (x, 0);
3986 goto retry;
3987 }
3988 mark_used_regs (pbi, XEXP (x, i), cond, insn);
3989 }
3990 else if (fmt[i] == 'E')
3991 {
b3694847 3992 int j;
402209ff
JH
3993 for (j = 0; j < XVECLEN (x, i); j++)
3994 mark_used_regs (pbi, XVECEXP (x, i, j), cond, insn);
3995 }
3996 }
3997 }
4dc9341c 3998}
402209ff
JH
3999\f
4000#ifdef AUTO_INC_DEC
4dc9341c 4001
402209ff
JH
4002static int
4003try_pre_increment_1 (pbi, insn)
4004 struct propagate_block_info *pbi;
4005 rtx insn;
4006{
4007 /* Find the next use of this reg. If in same basic block,
4008 make it do pre-increment or pre-decrement if appropriate. */
4009 rtx x = single_set (insn);
4010 HOST_WIDE_INT amount = ((GET_CODE (SET_SRC (x)) == PLUS ? 1 : -1)
4011 * INTVAL (XEXP (SET_SRC (x), 1)));
4012 int regno = REGNO (SET_DEST (x));
4013 rtx y = pbi->reg_next_use[regno];
4014 if (y != 0
4015 && SET_DEST (x) != stack_pointer_rtx
4016 && BLOCK_NUM (y) == BLOCK_NUM (insn)
4017 /* Don't do this if the reg dies, or gets set in y; a standard addressing
4018 mode would be better. */
4019 && ! dead_or_set_p (y, SET_DEST (x))
4020 && try_pre_increment (y, SET_DEST (x), amount))
4021 {
4022 /* We have found a suitable auto-increment and already changed
4023 insn Y to do it. So flush this increment instruction. */
3dec4024 4024 propagate_block_delete_insn (insn);
b53978a3 4025
402209ff
JH
4026 /* Count a reference to this reg for the increment insn we are
4027 deleting. When a reg is incremented, spilling it is worse,
4028 so we want to make that less likely. */
4029 if (regno >= FIRST_PSEUDO_REGISTER)
4030 {
4031 REG_FREQ (regno) += REG_FREQ_FROM_BB (pbi->bb);
4032 REG_N_SETS (regno)++;
4033 }
b53978a3 4034
402209ff
JH
4035 /* Flush any remembered memories depending on the value of
4036 the incremented register. */
4037 invalidate_mems_from_set (pbi, SET_DEST (x));
b53978a3 4038
402209ff
JH
4039 return 1;
4040 }
4041 return 0;
4042}
b53978a3 4043
402209ff
JH
4044/* Try to change INSN so that it does pre-increment or pre-decrement
4045 addressing on register REG in order to add AMOUNT to REG.
4046 AMOUNT is negative for pre-decrement.
4047 Returns 1 if the change could be made.
4048 This checks all about the validity of the result of modifying INSN. */
b53978a3 4049
402209ff
JH
4050static int
4051try_pre_increment (insn, reg, amount)
4052 rtx insn, reg;
4053 HOST_WIDE_INT amount;
b53978a3 4054{
b3694847 4055 rtx use;
b53978a3 4056
402209ff
JH
4057 /* Nonzero if we can try to make a pre-increment or pre-decrement.
4058 For example, addl $4,r1; movl (r1),... can become movl +(r1),... */
4059 int pre_ok = 0;
4060 /* Nonzero if we can try to make a post-increment or post-decrement.
4061 For example, addl $4,r1; movl -4(r1),... can become movl (r1)+,...
4062 It is possible for both PRE_OK and POST_OK to be nonzero if the machine
4063 supports both pre-inc and post-inc, or both pre-dec and post-dec. */
4064 int post_ok = 0;
b53978a3 4065
402209ff
JH
4066 /* Nonzero if the opportunity actually requires post-inc or post-dec. */
4067 int do_post = 0;
b53978a3 4068
402209ff
JH
4069 /* From the sign of increment, see which possibilities are conceivable
4070 on this target machine. */
4071 if (HAVE_PRE_INCREMENT && amount > 0)
4072 pre_ok = 1;
4073 if (HAVE_POST_INCREMENT && amount > 0)
4074 post_ok = 1;
b53978a3 4075
402209ff
JH
4076 if (HAVE_PRE_DECREMENT && amount < 0)
4077 pre_ok = 1;
4078 if (HAVE_POST_DECREMENT && amount < 0)
4079 post_ok = 1;
b53978a3 4080
402209ff
JH
4081 if (! (pre_ok || post_ok))
4082 return 0;
b53978a3 4083
402209ff
JH
4084 /* It is not safe to add a side effect to a jump insn
4085 because if the incremented register is spilled and must be reloaded
4086 there would be no way to store the incremented value back in memory. */
c9bacfdb 4087
402209ff
JH
4088 if (GET_CODE (insn) == JUMP_INSN)
4089 return 0;
b53978a3 4090
402209ff
JH
4091 use = 0;
4092 if (pre_ok)
4093 use = find_use_as_address (PATTERN (insn), reg, 0);
60e8b9f0 4094 if (post_ok && (use == 0 || use == (rtx) (size_t) 1))
b53978a3 4095 {
402209ff
JH
4096 use = find_use_as_address (PATTERN (insn), reg, -amount);
4097 do_post = 1;
b53978a3
JO
4098 }
4099
60e8b9f0 4100 if (use == 0 || use == (rtx) (size_t) 1)
402209ff
JH
4101 return 0;
4102
4103 if (GET_MODE_SIZE (GET_MODE (use)) != (amount > 0 ? amount : - amount))
4104 return 0;
b53978a3 4105
402209ff
JH
4106 /* See if this combination of instruction and addressing mode exists. */
4107 if (! validate_change (insn, &XEXP (use, 0),
4108 gen_rtx_fmt_e (amount > 0
4109 ? (do_post ? POST_INC : PRE_INC)
4110 : (do_post ? POST_DEC : PRE_DEC),
4111 Pmode, reg), 0))
4112 return 0;
b53978a3 4113
402209ff
JH
4114 /* Record that this insn now has an implicit side effect on X. */
4115 REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, reg, REG_NOTES (insn));
4116 return 1;
b53978a3
JO
4117}
4118
402209ff
JH
4119#endif /* AUTO_INC_DEC */
4120\f
4121/* Find the place in the rtx X where REG is used as a memory address.
4122 Return the MEM rtx that so uses it.
4123 If PLUSCONST is nonzero, search instead for a memory address equivalent to
4124 (plus REG (const_int PLUSCONST)).
5d6a16e2 4125
402209ff
JH
4126 If such an address does not appear, return 0.
4127 If REG appears more than once, or is used other than in such an address,
60e8b9f0 4128 return (rtx) 1. */
5d6a16e2 4129
402209ff
JH
4130rtx
4131find_use_as_address (x, reg, plusconst)
b3694847 4132 rtx x;
402209ff
JH
4133 rtx reg;
4134 HOST_WIDE_INT plusconst;
5d6a16e2 4135{
402209ff
JH
4136 enum rtx_code code = GET_CODE (x);
4137 const char * const fmt = GET_RTX_FORMAT (code);
b3694847
SS
4138 int i;
4139 rtx value = 0;
4140 rtx tem;
4a7da9b5 4141
402209ff
JH
4142 if (code == MEM && XEXP (x, 0) == reg && plusconst == 0)
4143 return x;
5d6a16e2 4144
402209ff
JH
4145 if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS
4146 && XEXP (XEXP (x, 0), 0) == reg
4147 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4148 && INTVAL (XEXP (XEXP (x, 0), 1)) == plusconst)
4149 return x;
ef120fc0 4150
402209ff 4151 if (code == SIGN_EXTRACT || code == ZERO_EXTRACT)
5d6a16e2 4152 {
402209ff
JH
4153 /* If REG occurs inside a MEM used in a bit-field reference,
4154 that is unacceptable. */
4155 if (find_use_as_address (XEXP (x, 0), reg, 0) != 0)
60e8b9f0 4156 return (rtx) (size_t) 1;
5d6a16e2 4157 }
5d6a16e2 4158
402209ff 4159 if (x == reg)
60e8b9f0 4160 return (rtx) (size_t) 1;
4dc9341c 4161
402209ff 4162 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4dc9341c 4163 {
402209ff
JH
4164 if (fmt[i] == 'e')
4165 {
4166 tem = find_use_as_address (XEXP (x, i), reg, plusconst);
4167 if (value == 0)
4168 value = tem;
4169 else if (tem != 0)
60e8b9f0 4170 return (rtx) (size_t) 1;
402209ff
JH
4171 }
4172 else if (fmt[i] == 'E')
4dc9341c 4173 {
b3694847 4174 int j;
402209ff 4175 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4dc9341c 4176 {
402209ff
JH
4177 tem = find_use_as_address (XVECEXP (x, i, j), reg, plusconst);
4178 if (value == 0)
4179 value = tem;
4180 else if (tem != 0)
60e8b9f0 4181 return (rtx) (size_t) 1;
4dc9341c
MH
4182 }
4183 }
4184 }
4dc9341c 4185
402209ff
JH
4186 return value;
4187}
4188\f
4189/* Write information about registers and basic blocks into FILE.
4190 This is part of making a debugging dump. */
c9bacfdb 4191
402209ff
JH
4192void
4193dump_regset (r, outf)
4194 regset r;
4195 FILE *outf;
4dc9341c 4196{
402209ff
JH
4197 int i;
4198 if (r == NULL)
3abd3239 4199 {
402209ff 4200 fputs (" (nil)", outf);
3abd3239
MH
4201 return;
4202 }
4dc9341c 4203
402209ff 4204 EXECUTE_IF_SET_IN_REG_SET (r, 0, i,
4dc9341c 4205 {
402209ff
JH
4206 fprintf (outf, " %d", i);
4207 if (i < FIRST_PSEUDO_REGISTER)
4208 fprintf (outf, " [%s]",
4209 reg_names[i]);
4210 });
4dc9341c
MH
4211}
4212
402209ff
JH
4213/* Print a human-reaable representation of R on the standard error
4214 stream. This function is designed to be used from within the
4215 debugger. */
c9bacfdb 4216
402209ff
JH
4217void
4218debug_regset (r)
4219 regset r;
4dc9341c 4220{
402209ff
JH
4221 dump_regset (r, stderr);
4222 putc ('\n', stderr);
4dc9341c
MH
4223}
4224
402209ff
JH
4225/* Recompute register set/reference counts immediately prior to register
4226 allocation.
5d6a16e2 4227
402209ff
JH
4228 This avoids problems with set/reference counts changing to/from values
4229 which have special meanings to the register allocators.
eab02feb 4230
402209ff
JH
4231 Additionally, the reference counts are the primary component used by the
4232 register allocators to prioritize pseudos for allocation to hard regs.
4233 More accurate reference counts generally lead to better register allocation.
eab02feb 4234
402209ff 4235 F is the first insn to be scanned.
eab02feb 4236
402209ff
JH
4237 LOOP_STEP denotes how much loop_depth should be incremented per
4238 loop nesting level in order to increase the ref count more for
4239 references in a loop.
b9f22704 4240
402209ff
JH
4241 It might be worthwhile to update REG_LIVE_LENGTH, REG_BASIC_BLOCK and
4242 possibly other information which is used by the register allocators. */
eab02feb 4243
402209ff
JH
4244void
4245recompute_reg_usage (f, loop_step)
4246 rtx f ATTRIBUTE_UNUSED;
4247 int loop_step ATTRIBUTE_UNUSED;
4248{
4249 allocate_reg_life_data ();
4250 update_life_info (NULL, UPDATE_LIFE_LOCAL, PROP_REG_INFO);
eab02feb
MH
4251}
4252
402209ff
JH
4253/* Optionally removes all the REG_DEAD and REG_UNUSED notes from a set of
4254 blocks. If BLOCKS is NULL, assume the universal set. Returns a count
4255 of the number of registers that died. */
d4b60170 4256
c9bacfdb 4257int
402209ff
JH
4258count_or_remove_death_notes (blocks, kill)
4259 sbitmap blocks;
4260 int kill;
4dc9341c 4261{
e0082a72
ZD
4262 int count = 0;
4263 basic_block bb;
ce4bbac7 4264
e0082a72 4265 FOR_EACH_BB_REVERSE (bb)
4dc9341c 4266 {
402209ff 4267 rtx insn;
5d6a16e2 4268
e0082a72 4269 if (blocks && ! TEST_BIT (blocks, bb->index))
402209ff 4270 continue;
5d6a16e2 4271
402209ff 4272 for (insn = bb->head;; insn = NEXT_INSN (insn))
4dc9341c 4273 {
402209ff 4274 if (INSN_P (insn))
4dc9341c 4275 {
402209ff
JH
4276 rtx *pprev = &REG_NOTES (insn);
4277 rtx link = *pprev;
4278
4279 while (link)
4dc9341c 4280 {
402209ff
JH
4281 switch (REG_NOTE_KIND (link))
4282 {
4283 case REG_DEAD:
4284 if (GET_CODE (XEXP (link, 0)) == REG)
4285 {
4286 rtx reg = XEXP (link, 0);
4287 int n;
c9bacfdb 4288
402209ff
JH
4289 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
4290 n = 1;
4291 else
4292 n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
4293 count += n;
4294 }
4295 /* Fall through. */
c9bacfdb 4296
402209ff
JH
4297 case REG_UNUSED:
4298 if (kill)
4299 {
4300 rtx next = XEXP (link, 1);
4301 free_EXPR_LIST_node (link);
4302 *pprev = link = next;
4303 break;
4304 }
4305 /* Fall through. */
c9bacfdb 4306
402209ff
JH
4307 default:
4308 pprev = &XEXP (link, 1);
4309 link = *pprev;
4310 break;
4311 }
4dc9341c
MH
4312 }
4313 }
c9bacfdb 4314
402209ff
JH
4315 if (insn == bb->end)
4316 break;
5d6a16e2 4317 }
5a660bff 4318 }
4dc9341c 4319
402209ff 4320 return count;
4dc9341c 4321}
b932f770
JH
4322/* Clear LOG_LINKS fields of insns in a selected blocks or whole chain
4323 if blocks is NULL. */
efc9bd41 4324
b932f770
JH
4325static void
4326clear_log_links (blocks)
4327 sbitmap blocks;
d9d4fb43 4328{
b932f770
JH
4329 rtx insn;
4330 int i;
1868b439 4331
b932f770 4332 if (!blocks)
1868b439 4333 {
b932f770
JH
4334 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4335 if (INSN_P (insn))
e9cf0934 4336 free_INSN_LIST_list (&LOG_LINKS (insn));
1868b439 4337 }
b932f770
JH
4338 else
4339 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
4340 {
4341 basic_block bb = BASIC_BLOCK (i);
16e99e29 4342
b932f770
JH
4343 for (insn = bb->head; insn != NEXT_INSN (bb->end);
4344 insn = NEXT_INSN (insn))
4345 if (INSN_P (insn))
e9cf0934 4346 free_INSN_LIST_list (&LOG_LINKS (insn));
b932f770 4347 });
d9d4fb43 4348}
efc9bd41
RK
4349
4350/* Given a register bitmap, turn on the bits in a HARD_REG_SET that
4351 correspond to the hard registers, if any, set in that map. This
4352 could be done far more efficiently by having all sorts of special-cases
4353 with moving single words, but probably isn't worth the trouble. */
4354
4355void
4356reg_set_to_hard_reg_set (to, from)
4357 HARD_REG_SET *to;
4358 bitmap from;
4359{
4360 int i;
4361
4362 EXECUTE_IF_SET_IN_BITMAP
4363 (from, 0, i,
4364 {
4365 if (i >= FIRST_PSEUDO_REGISTER)
4366 return;
4367 SET_HARD_REG_BIT (*to, i);
4368 });
4369}