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d7429b6a 1/* Data flow analysis for GNU compiler.
c9bacfdb 2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
ad616de1 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
d7429b6a 4
1322177d 5This file is part of GCC.
d7429b6a 6
1322177d
LB
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
d7429b6a 11
1322177d
LB
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
d7429b6a
RK
16
17You should have received a copy of the GNU General Public License
1322177d
LB
18along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
d7429b6a 21
e881bb1b
RH
22/* This file contains the data flow analysis pass of the compiler. It
23 computes data flow information which tells combine_instructions
24 which insns to consider combining and controls register allocation.
d7429b6a 25
e881bb1b
RH
26 Additional data flow information that is too bulky to record is
27 generated during the analysis, and is used at that time to create
28 autoincrement and autodecrement addressing.
d7429b6a
RK
29
30 The first step is dividing the function into basic blocks.
31 find_basic_blocks does this. Then life_analysis determines
32 where each register is live and where it is dead.
33
34 ** find_basic_blocks **
35
e881bb1b
RH
36 find_basic_blocks divides the current function's rtl into basic
37 blocks and constructs the CFG. The blocks are recorded in the
38 basic_block_info array; the CFG exists in the edge structures
39 referenced by the blocks.
d7429b6a 40
e881bb1b 41 find_basic_blocks also finds any unreachable loops and deletes them.
d7429b6a
RK
42
43 ** life_analysis **
44
45 life_analysis is called immediately after find_basic_blocks.
46 It uses the basic block information to determine where each
47 hard or pseudo register is live.
48
49 ** live-register info **
50
51 The information about where each register is live is in two parts:
e881bb1b 52 the REG_NOTES of insns, and the vector basic_block->global_live_at_start.
d7429b6a 53
e881bb1b
RH
54 basic_block->global_live_at_start has an element for each basic
55 block, and the element is a bit-vector with a bit for each hard or
56 pseudo register. The bit is 1 if the register is live at the
57 beginning of the basic block.
d7429b6a 58
c9bacfdb 59 Two types of elements can be added to an insn's REG_NOTES.
d7429b6a
RK
60 A REG_DEAD note is added to an insn's REG_NOTES for any register
61 that meets both of two conditions: The value in the register is not
62 needed in subsequent insns and the insn does not replace the value in
63 the register (in the case of multi-word hard registers, the value in
64 each register must be replaced by the insn to avoid a REG_DEAD note).
65
66 In the vast majority of cases, an object in a REG_DEAD note will be
67 used somewhere in the insn. The (rare) exception to this is if an
68 insn uses a multi-word hard register and only some of the registers are
69 needed in subsequent insns. In that case, REG_DEAD notes will be
70 provided for those hard registers that are not subsequently needed.
71 Partial REG_DEAD notes of this type do not occur when an insn sets
72 only some of the hard registers used in such a multi-word operand;
73 omitting REG_DEAD notes for objects stored in an insn is optional and
74 the desire to do so does not justify the complexity of the partial
75 REG_DEAD notes.
76
77 REG_UNUSED notes are added for each register that is set by the insn
78 but is unused subsequently (if every register set by the insn is unused
79 and the insn does not reference memory or have some other side-effect,
80 the insn is deleted instead). If only part of a multi-word hard
81 register is used in a subsequent insn, REG_UNUSED notes are made for
82 the parts that will not be used.
83
84 To determine which registers are live after any insn, one can
85 start from the beginning of the basic block and scan insns, noting
86 which registers are set by each insn and which die there.
87
88 ** Other actions of life_analysis **
89
90 life_analysis sets up the LOG_LINKS fields of insns because the
91 information needed to do so is readily available.
92
93 life_analysis deletes insns whose only effect is to store a value
94 that is never used.
95
96 life_analysis notices cases where a reference to a register as
97 a memory address can be combined with a preceding or following
98 incrementation or decrementation of the register. The separate
99 instruction to increment or decrement is deleted and the address
100 is changed to a POST_INC or similar rtx.
101
102 Each time an incrementing or decrementing address is created,
103 a REG_INC element is added to the insn's REG_NOTES list.
104
105 life_analysis fills in certain vectors containing information about
d4b60170
RK
106 register usage: REG_N_REFS, REG_N_DEATHS, REG_N_SETS, REG_LIVE_LENGTH,
107 REG_N_CALLS_CROSSED and REG_BASIC_BLOCK.
fdb8a883
JW
108
109 life_analysis sets current_function_sp_is_unchanging if the function
110 doesn't modify the stack pointer. */
e881bb1b 111
c9bacfdb 112/* TODO:
e881bb1b
RH
113
114 Split out from life_analysis:
dda49b66 115 - local property discovery
e881bb1b
RH
116 - global property computation
117 - log links creation
118 - pre/post modify transformation
119*/
d7429b6a 120\f
d7429b6a 121#include "config.h"
670ee920 122#include "system.h"
4977bab6
ZW
123#include "coretypes.h"
124#include "tm.h"
d3a923ee 125#include "tree.h"
d7429b6a 126#include "rtl.h"
6baf1cc8 127#include "tm_p.h"
efc9bd41 128#include "hard-reg-set.h"
d7429b6a
RK
129#include "basic-block.h"
130#include "insn-config.h"
131#include "regs.h"
d7429b6a
RK
132#include "flags.h"
133#include "output.h"
b384405b 134#include "function.h"
3d195391 135#include "except.h"
2e107e9e 136#include "toplev.h"
79c9824e 137#include "recog.h"
11bdd2ae 138#include "expr.h"
4793dca1 139#include "timevar.h"
d7429b6a
RK
140
141#include "obstack.h"
11ae508b 142#include "splay-tree.h"
c5c76735 143
d3a923ee
RH
144#ifndef HAVE_epilogue
145#define HAVE_epilogue 0
146#endif
d3a923ee
RH
147#ifndef HAVE_prologue
148#define HAVE_prologue 0
149#endif
0a1c58a2
JL
150#ifndef HAVE_sibcall_epilogue
151#define HAVE_sibcall_epilogue 0
152#endif
d3a923ee 153
2a3e384f
RH
154#ifndef EPILOGUE_USES
155#define EPILOGUE_USES(REGNO) 0
156#endif
15b5aef3
RH
157#ifndef EH_USES
158#define EH_USES(REGNO) 0
159#endif
2a3e384f 160
7e6d8ba1
AH
161#ifdef HAVE_conditional_execution
162#ifndef REVERSE_CONDEXEC_PREDICATES_P
15dce812
RE
163#define REVERSE_CONDEXEC_PREDICATES_P(x, y) \
164 (GET_CODE ((x)) == reversed_comparison_code ((y), NULL))
7e6d8ba1
AH
165#endif
166#endif
167
56744d1a
JL
168/* Nonzero if the second flow pass has completed. */
169int flow2_completed;
170
d7429b6a
RK
171/* Maximum register number used in this function, plus one. */
172
173int max_regno;
174
b1f21e0a 175/* Indexed by n, giving various register information */
d7429b6a 176
6feacd09 177varray_type reg_n_info;
d7429b6a 178
d7429b6a 179/* Regset of regs live when calls to `setjmp'-like functions happen. */
e881bb1b 180/* ??? Does this exist only for the setjmp-clobbered warning message? */
d7429b6a
RK
181
182regset regs_live_at_setjmp;
183
184/* List made of EXPR_LIST rtx's which gives pairs of pseudo registers
185 that have to go in the same hard reg.
186 The first two regs in the list are a pair, and the next two
187 are another pair, etc. */
188rtx regs_may_share;
189
d7429b6a
RK
190/* Set of registers that may be eliminable. These are handled specially
191 in updating regs_ever_live. */
192
193static HARD_REG_SET elim_reg_set;
194
11ae508b
RH
195/* Holds information for tracking conditional register life information. */
196struct reg_cond_life_info
197{
685af3af 198 /* A boolean expression of conditions under which a register is dead. */
11ae508b 199 rtx condition;
685af3af
JW
200 /* Conditions under which a register is dead at the basic block end. */
201 rtx orig_condition;
202
203 /* A boolean expression of conditions under which a register has been
204 stored into. */
205 rtx stores;
11ae508b
RH
206
207 /* ??? Could store mask of bytes that are dead, so that we could finally
208 track lifetimes of multi-word registers accessed via subregs. */
209};
210
62828c00
RH
211/* For use in communicating between propagate_block and its subroutines.
212 Holds all information needed to compute life and def-use information. */
213
214struct propagate_block_info
215{
216 /* The basic block we're considering. */
217 basic_block bb;
218
219 /* Bit N is set if register N is conditionally or unconditionally live. */
220 regset reg_live;
221
9785c68d
RH
222 /* Bit N is set if register N is set this insn. */
223 regset new_set;
8e3f9094 224
62828c00
RH
225 /* Element N is the next insn that uses (hard or pseudo) register N
226 within the current basic block; or zero, if there is no such insn. */
227 rtx *reg_next_use;
228
229 /* Contains a list of all the MEMs we are tracking for dead store
230 elimination. */
231 rtx mem_set_list;
232
7dfc0fbe
BS
233 /* If non-null, record the set of registers set unconditionally in the
234 basic block. */
62828c00
RH
235 regset local_set;
236
7dfc0fbe
BS
237 /* If non-null, record the set of registers set conditionally in the
238 basic block. */
239 regset cond_local_set;
240
11ae508b
RH
241#ifdef HAVE_conditional_execution
242 /* Indexed by register number, holds a reg_cond_life_info for each
243 register that is not unconditionally live or dead. */
244 splay_tree reg_cond_dead;
245
246 /* Bit N is set if register N is in an expression in reg_cond_dead. */
247 regset reg_cond_reg;
248#endif
249
0875baa0
RH
250 /* The length of mem_set_list. */
251 int mem_set_list_len;
252
cc2902df 253 /* Nonzero if the value of CC0 is live. */
62828c00
RH
254 int cc0_live;
255
fbe5a4a6 256 /* Flags controlling the set of information propagate_block collects. */
62828c00 257 int flags;
736b64dd
JH
258 /* Index of instruction being processed. */
259 int insn_num;
62828c00
RH
260};
261
3dec4024
JH
262/* Number of dead insns removed. */
263static int ndead;
264
736b64dd
JH
265/* When PROP_REG_INFO set, array contains pbi->insn_num of instruction
266 where given register died. When the register is marked alive, we use the
267 information to compute amount of instructions life range cross.
268 (remember, we are walking backward). This can be computed as current
269 pbi->insn_num - reg_deaths[regno].
270 At the end of processing each basic block, the remaining live registers
271 are inspected and liferanges are increased same way so liverange of global
272 registers are computed correctly.
273
274 The array is maintained clear for dead registers, so it can be safely reused
275 for next basic block without expensive memset of the whole array after
276 reseting pbi->insn_num to 0. */
277
278static int *reg_deaths;
279
0875baa0
RH
280/* Maximum length of pbi->mem_set_list before we start dropping
281 new elements on the floor. */
282#define MAX_MEM_SET_LIST_LEN 100
283
d7429b6a 284/* Forward declarations */
6cf9ac28
AJ
285static int verify_wide_reg_1 (rtx *, void *);
286static void verify_wide_reg (int, basic_block);
287static void verify_local_live_at_start (regset, basic_block);
288static void notice_stack_pointer_modification_1 (rtx, rtx, void *);
827c06b6 289static void notice_stack_pointer_modification (void);
6cf9ac28
AJ
290static void mark_reg (rtx, void *);
291static void mark_regs_live_at_end (regset);
6cf9ac28
AJ
292static void calculate_global_regs_live (sbitmap, sbitmap, int);
293static void propagate_block_delete_insn (rtx);
294static rtx propagate_block_delete_libcall (rtx, rtx);
295static int insn_dead_p (struct propagate_block_info *, rtx, int, rtx);
296static int libcall_dead_p (struct propagate_block_info *, rtx, rtx);
297static void mark_set_regs (struct propagate_block_info *, rtx, rtx);
298static void mark_set_1 (struct propagate_block_info *, enum rtx_code, rtx,
299 rtx, rtx, int);
300static int find_regno_partial (rtx *, void *);
0626ef8a 301
11ae508b 302#ifdef HAVE_conditional_execution
6cf9ac28
AJ
303static int mark_regno_cond_dead (struct propagate_block_info *, int, rtx);
304static void free_reg_cond_life_info (splay_tree_value);
305static int flush_reg_cond_reg_1 (splay_tree_node, void *);
306static void flush_reg_cond_reg (struct propagate_block_info *, int);
307static rtx elim_reg_cond (rtx, unsigned int);
308static rtx ior_reg_cond (rtx, rtx, int);
309static rtx not_reg_cond (rtx);
310static rtx and_reg_cond (rtx, rtx, int);
11ae508b 311#endif
1d300e19 312#ifdef AUTO_INC_DEC
6cf9ac28
AJ
313static void attempt_auto_inc (struct propagate_block_info *, rtx, rtx, rtx,
314 rtx, rtx);
315static void find_auto_inc (struct propagate_block_info *, rtx, rtx);
316static int try_pre_increment_1 (struct propagate_block_info *, rtx);
317static int try_pre_increment (rtx, rtx, HOST_WIDE_INT);
1d300e19 318#endif
6cf9ac28
AJ
319static void mark_used_reg (struct propagate_block_info *, rtx, rtx, rtx);
320static void mark_used_regs (struct propagate_block_info *, rtx, rtx, rtx);
321void debug_flow_info (void);
322static void add_to_mem_set_list (struct propagate_block_info *, rtx);
323static int invalidate_mems_from_autoinc (rtx *, void *);
324static void invalidate_mems_from_set (struct propagate_block_info *, rtx);
325static void clear_log_links (sbitmap);
095c3bbd 326static int count_or_remove_death_notes_bb (basic_block, int);
60580286 327static void allocate_bb_life_data (void);
d7429b6a 328\f
402209ff
JH
329/* Return the INSN immediately following the NOTE_INSN_BASIC_BLOCK
330 note associated with the BLOCK. */
331
332rtx
6cf9ac28 333first_insn_after_basic_block_note (basic_block block)
402209ff
JH
334{
335 rtx insn;
b313a0fe 336
402209ff 337 /* Get the first instruction in the block. */
a813c111 338 insn = BB_HEAD (block);
dc2ede84 339
402209ff
JH
340 if (insn == NULL_RTX)
341 return NULL_RTX;
4b4bf941 342 if (LABEL_P (insn))
402209ff 343 insn = NEXT_INSN (insn);
0bccc606 344 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (insn));
402209ff
JH
345
346 return NEXT_INSN (insn);
347}
348\f
827c06b6
SB
349/* Perform data flow analysis for the whole control flow graph.
350 FLAGS is a set of PROP_* flags to be used in accumulating flow info. */
402209ff
JH
351
352void
827c06b6 353life_analysis (FILE *file, int flags)
e881bb1b 354{
cff9f8d5 355#ifdef ELIMINABLE_REGS
c1b50e49 356 int i;
8b60264b 357 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
402209ff 358#endif
dc2ede84 359
402209ff
JH
360 /* Record which registers will be eliminated. We use this in
361 mark_used_regs. */
e881bb1b 362
402209ff 363 CLEAR_HARD_REG_SET (elim_reg_set);
314883b8 364
402209ff
JH
365#ifdef ELIMINABLE_REGS
366 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
367 SET_HARD_REG_BIT (elim_reg_set, eliminables[i].from);
368#else
369 SET_HARD_REG_BIT (elim_reg_set, FRAME_POINTER_REGNUM);
370#endif
52a11cbf 371
cff9f8d5
AH
372
373#ifdef CANNOT_CHANGE_MODE_CLASS
374 if (flags & PROP_REG_INFO)
41bf2a8b 375 init_subregs_of_mode ();
cff9f8d5
AH
376#endif
377
402209ff
JH
378 if (! optimize)
379 flags &= ~(PROP_LOG_LINKS | PROP_AUTOINC | PROP_ALLOW_CFG_CHANGES);
52a11cbf 380
402209ff
JH
381 /* The post-reload life analysis have (on a global basis) the same
382 registers live as was computed by reload itself. elimination
383 Otherwise offsets and such may be incorrect.
e881bb1b 384
402209ff
JH
385 Reload will make some registers as live even though they do not
386 appear in the rtl.
e881bb1b 387
402209ff
JH
388 We don't want to create new auto-incs after reload, since they
389 are unlikely to be useful and can cause problems with shared
390 stack slots. */
391 if (reload_completed)
392 flags &= ~(PROP_REG_INFO | PROP_AUTOINC);
e881bb1b 393
402209ff 394 /* We want alias analysis information for local dead store elimination. */
5149f070 395 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
402209ff 396 init_alias_analysis ();
dc2ede84 397
402209ff
JH
398 /* Always remove no-op moves. Do this before other processing so
399 that we don't have to keep re-scanning them. */
827c06b6 400 delete_noop_moves ();
1bc48f82 401
402209ff
JH
402 /* Some targets can emit simpler epilogues if they know that sp was
403 not ever modified during the function. After reload, of course,
404 we've already emitted the epilogue so there's no sense searching. */
405 if (! reload_completed)
827c06b6 406 notice_stack_pointer_modification ();
1bc48f82 407
402209ff
JH
408 /* Allocate and zero out data structures that will record the
409 data from lifetime analysis. */
410 allocate_reg_life_data ();
411 allocate_bb_life_data ();
1bc48f82 412
402209ff
JH
413 /* Find the set of registers live on function exit. */
414 mark_regs_live_at_end (EXIT_BLOCK_PTR->global_live_at_start);
1bc48f82 415
402209ff
JH
416 /* "Update" life info from zero. It'd be nice to begin the
417 relaxation with just the exit and noreturn blocks, but that set
418 is not immediately handy. */
c9bacfdb 419
402209ff 420 if (flags & PROP_REG_INFO)
df2ef49b
AM
421 {
422 memset (regs_ever_live, 0, sizeof (regs_ever_live));
423 memset (regs_asm_clobbered, 0, sizeof (regs_asm_clobbered));
424 }
402209ff 425 update_life_info (NULL, UPDATE_LIFE_GLOBAL, flags);
736b64dd
JH
426 if (reg_deaths)
427 {
428 free (reg_deaths);
429 reg_deaths = NULL;
430 }
1bc48f82 431
402209ff 432 /* Clean up. */
5149f070 433 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
402209ff 434 end_alias_analysis ();
1bc48f82 435
402209ff
JH
436 if (file)
437 dump_flow_info (file);
0005550b 438
1f52178b 439 /* Removing dead insns should have made jumptables really dead. */
402209ff
JH
440 delete_dead_jumptables ();
441}
0005550b 442
402209ff 443/* A subroutine of verify_wide_reg, called through for_each_rtx.
08ef5437
RH
444 Search for REGNO. If found, return 2 if it is not wider than
445 word_mode. */
a686dbf8 446
402209ff 447static int
6cf9ac28 448verify_wide_reg_1 (rtx *px, void *pregno)
402209ff
JH
449{
450 rtx x = *px;
451 unsigned int regno = *(int *) pregno;
134d3a2e 452
f8cfc6aa 453 if (REG_P (x) && REGNO (x) == regno)
134d3a2e 454 {
402209ff 455 if (GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD)
08ef5437 456 return 2;
402209ff 457 return 1;
134d3a2e 458 }
402209ff 459 return 0;
a686dbf8
JH
460}
461
402209ff 462/* A subroutine of verify_local_live_at_start. Search through insns
08ef5437 463 of BB looking for register REGNO. */
8329b5ec 464
be1bb652 465static void
6cf9ac28 466verify_wide_reg (int regno, basic_block bb)
e881bb1b 467{
a813c111 468 rtx head = BB_HEAD (bb), end = BB_END (bb);
08ef5437 469
402209ff 470 while (1)
e881bb1b 471 {
08ef5437
RH
472 if (INSN_P (head))
473 {
474 int r = for_each_rtx (&PATTERN (head), verify_wide_reg_1, &regno);
475 if (r == 1)
476 return;
477 if (r == 2)
478 break;
479 }
402209ff
JH
480 if (head == end)
481 break;
482 head = NEXT_INSN (head);
483 }
c263766c 484 if (dump_file)
08ef5437 485 {
c263766c
RH
486 fprintf (dump_file, "Register %d died unexpectedly.\n", regno);
487 dump_bb (bb, dump_file, 0);
08ef5437 488 }
0bccc606 489 fatal_error ("internal consistency failure");
402209ff 490}
314883b8 491
402209ff
JH
492/* A subroutine of update_life_info. Verify that there are no untoward
493 changes in live_at_start during a local update. */
d06c6389 494
402209ff 495static void
6cf9ac28 496verify_local_live_at_start (regset new_live_at_start, basic_block bb)
402209ff
JH
497{
498 if (reload_completed)
499 {
500 /* After reload, there are no pseudos, nor subregs of multi-word
501 registers. The regsets should exactly match. */
502 if (! REG_SET_EQUAL_P (new_live_at_start, bb->global_live_at_start))
503 {
c263766c 504 if (dump_file)
e881bb1b 505 {
c263766c 506 fprintf (dump_file,
08ef5437 507 "live_at_start mismatch in bb %d, aborting\nNew:\n",
0b17ab2f 508 bb->index);
c263766c
RH
509 debug_bitmap_file (dump_file, new_live_at_start);
510 fputs ("Old:\n", dump_file);
511 dump_bb (bb, dump_file, 0);
e881bb1b 512 }
0bccc606 513 fatal_error ("internal consistency failure");
e881bb1b 514 }
402209ff
JH
515 }
516 else
517 {
3cd8c58a 518 unsigned i;
a2041967 519 reg_set_iterator rsi;
d7429b6a 520
402209ff
JH
521 /* Find the set of changed registers. */
522 XOR_REG_SET (new_live_at_start, bb->global_live_at_start);
421382ac 523
a2041967 524 EXECUTE_IF_SET_IN_REG_SET (new_live_at_start, 0, i, rsi)
402209ff 525 {
dd3f0101 526 /* No registers should die. */
402209ff
JH
527 if (REGNO_REG_SET_P (bb->global_live_at_start, i))
528 {
c263766c 529 if (dump_file)
08ef5437 530 {
c263766c 531 fprintf (dump_file,
08ef5437 532 "Register %d died unexpectedly.\n", i);
c263766c 533 dump_bb (bb, dump_file, 0);
08ef5437 534 }
0bccc606 535 fatal_error ("internal consistency failure");
402209ff 536 }
dd3f0101 537 /* Verify that the now-live register is wider than word_mode. */
08ef5437 538 verify_wide_reg (i, bb);
a2041967 539 }
e881bb1b 540 }
402209ff 541}
d7429b6a 542
402209ff
JH
543/* Updates life information starting with the basic blocks set in BLOCKS.
544 If BLOCKS is null, consider it to be the universal set.
af14ce9c 545
e0bb17a8 546 If EXTENT is UPDATE_LIFE_LOCAL, such as after splitting or peepholing,
402209ff
JH
547 we are only expecting local modifications to basic blocks. If we find
548 extra registers live at the beginning of a block, then we either killed
549 useful data, or we have a broken split that wants data not provided.
550 If we find registers removed from live_at_start, that means we have
551 a broken peephole that is killing a register it shouldn't.
af14ce9c 552
402209ff
JH
553 ??? This is not true in one situation -- when a pre-reload splitter
554 generates subregs of a multi-word pseudo, current life analysis will
555 lose the kill. So we _can_ have a pseudo go live. How irritating.
5ece9746 556
24908375
R
557 It is also not true when a peephole decides that it doesn't need one
558 or more of the inputs.
559
402209ff
JH
560 Including PROP_REG_INFO does not properly refresh regs_ever_live
561 unless the caller resets it to zero. */
19d3c25c 562
3dec4024 563int
7932a3db
NS
564update_life_info (sbitmap blocks, enum update_life_extent extent,
565 int prop_flags)
19d3c25c 566{
402209ff 567 regset tmp;
3cd8c58a 568 unsigned i;
566576e7 569 int stabilized_prop_flags = prop_flags;
e0082a72 570 basic_block bb;
006844a3 571
04389919 572 tmp = ALLOC_REG_SET (&reg_obstack);
3dec4024 573 ndead = 0;
2cade2ad 574
298c28a8
JH
575 if ((prop_flags & PROP_REG_INFO) && !reg_deaths)
576 reg_deaths = xcalloc (sizeof (*reg_deaths), max_regno);
577
b932f770
JH
578 timevar_push ((extent == UPDATE_LIFE_LOCAL || blocks)
579 ? TV_LIFE_UPDATE : TV_LIFE);
580
402209ff
JH
581 /* Changes to the CFG are only allowed when
582 doing a global update for the entire CFG. */
0bccc606
NS
583 gcc_assert (!(prop_flags & PROP_ALLOW_CFG_CHANGES)
584 || (extent != UPDATE_LIFE_LOCAL && !blocks));
006844a3 585
402209ff
JH
586 /* For a global update, we go through the relaxation process again. */
587 if (extent != UPDATE_LIFE_LOCAL)
588 {
589 for ( ; ; )
590 {
591 int changed = 0;
19d3c25c 592
402209ff
JH
593 calculate_global_regs_live (blocks, blocks,
594 prop_flags & (PROP_SCAN_DEAD_CODE
5149f070 595 | PROP_SCAN_DEAD_STORES
402209ff 596 | PROP_ALLOW_CFG_CHANGES));
5ece9746 597
402209ff
JH
598 if ((prop_flags & (PROP_KILL_DEAD_CODE | PROP_ALLOW_CFG_CHANGES))
599 != (PROP_KILL_DEAD_CODE | PROP_ALLOW_CFG_CHANGES))
600 break;
e881bb1b 601
402209ff
JH
602 /* Removing dead code may allow the CFG to be simplified which
603 in turn may allow for further dead code detection / removal. */
e0082a72 604 FOR_EACH_BB_REVERSE (bb)
402209ff 605 {
402209ff
JH
606 COPY_REG_SET (tmp, bb->global_live_at_end);
607 changed |= propagate_block (bb, tmp, NULL, NULL,
608 prop_flags & (PROP_SCAN_DEAD_CODE
5149f070 609 | PROP_SCAN_DEAD_STORES
402209ff
JH
610 | PROP_KILL_DEAD_CODE));
611 }
47095bfc 612
566576e7
HPN
613 /* Don't pass PROP_SCAN_DEAD_CODE or PROP_KILL_DEAD_CODE to
614 subsequent propagate_block calls, since removing or acting as
615 removing dead code can affect global register liveness, which
616 is supposed to be finalized for this call after this loop. */
617 stabilized_prop_flags
5149f070
JH
618 &= ~(PROP_SCAN_DEAD_CODE | PROP_SCAN_DEAD_STORES
619 | PROP_KILL_DEAD_CODE);
566576e7
HPN
620
621 if (! changed)
402209ff 622 break;
566576e7
HPN
623
624 /* We repeat regardless of what cleanup_cfg says. If there were
625 instructions deleted above, that might have been only a
626 partial improvement (see MAX_MEM_SET_LIST_LEN usage).
627 Further improvement may be possible. */
628 cleanup_cfg (CLEANUP_EXPENSIVE);
cdd1f01b 629
6cf9ac28 630 /* Zap the life information from the last round. If we don't
cdd1f01b 631 do this, we can wind up with registers that no longer appear
6de9cd9a 632 in the code being marked live at entry. */
cdd1f01b
RH
633 FOR_EACH_BB (bb)
634 {
635 CLEAR_REG_SET (bb->global_live_at_start);
636 CLEAR_REG_SET (bb->global_live_at_end);
637 }
e881bb1b 638 }
47095bfc 639
402209ff
JH
640 /* If asked, remove notes from the blocks we'll update. */
641 if (extent == UPDATE_LIFE_GLOBAL_RM_NOTES)
642 count_or_remove_death_notes (blocks, 1);
643 }
644
38c1593d
JH
645 /* Clear log links in case we are asked to (re)compute them. */
646 if (prop_flags & PROP_LOG_LINKS)
647 clear_log_links (blocks);
648
402209ff
JH
649 if (blocks)
650 {
651 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
652 {
e0082a72 653 bb = BASIC_BLOCK (i);
402209ff
JH
654
655 COPY_REG_SET (tmp, bb->global_live_at_end);
566576e7 656 propagate_block (bb, tmp, NULL, NULL, stabilized_prop_flags);
402209ff
JH
657
658 if (extent == UPDATE_LIFE_LOCAL)
659 verify_local_live_at_start (tmp, bb);
660 });
5ece9746 661 }
e881bb1b
RH
662 else
663 {
e0082a72 664 FOR_EACH_BB_REVERSE (bb)
355e4ec4 665 {
402209ff 666 COPY_REG_SET (tmp, bb->global_live_at_end);
566576e7
HPN
667
668 propagate_block (bb, tmp, NULL, NULL, stabilized_prop_flags);
421382ac 669
402209ff
JH
670 if (extent == UPDATE_LIFE_LOCAL)
671 verify_local_live_at_start (tmp, bb);
e881bb1b 672 }
e881bb1b
RH
673 }
674
402209ff 675 FREE_REG_SET (tmp);
eeea333e 676
402209ff
JH
677 if (prop_flags & PROP_REG_INFO)
678 {
a2041967
KH
679 reg_set_iterator rsi;
680
402209ff
JH
681 /* The only pseudos that are live at the beginning of the function
682 are those that were not set anywhere in the function. local-alloc
683 doesn't know how to handle these correctly, so mark them as not
684 local to any one basic block. */
685 EXECUTE_IF_SET_IN_REG_SET (ENTRY_BLOCK_PTR->global_live_at_end,
a2041967
KH
686 FIRST_PSEUDO_REGISTER, i, rsi)
687 REG_BASIC_BLOCK (i) = REG_BLOCK_GLOBAL;
e881bb1b 688
402209ff
JH
689 /* We have a problem with any pseudoreg that lives across the setjmp.
690 ANSI says that if a user variable does not change in value between
691 the setjmp and the longjmp, then the longjmp preserves it. This
692 includes longjmp from a place where the pseudo appears dead.
693 (In principle, the value still exists if it is in scope.)
694 If the pseudo goes in a hard reg, some other value may occupy
695 that hard reg where this pseudo is dead, thus clobbering the pseudo.
696 Conclusion: such a pseudo must not go in a hard reg. */
697 EXECUTE_IF_SET_IN_REG_SET (regs_live_at_setjmp,
a2041967
KH
698 FIRST_PSEUDO_REGISTER, i, rsi)
699 {
700 if (regno_reg_rtx[i] != 0)
701 {
702 REG_LIVE_LENGTH (i) = -1;
703 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
704 }
705 }
402209ff 706 }
736b64dd
JH
707 if (reg_deaths)
708 {
709 free (reg_deaths);
710 reg_deaths = NULL;
711 }
b932f770
JH
712 timevar_pop ((extent == UPDATE_LIFE_LOCAL || blocks)
713 ? TV_LIFE_UPDATE : TV_LIFE);
c263766c
RH
714 if (ndead && dump_file)
715 fprintf (dump_file, "deleted %i dead insns\n", ndead);
3dec4024 716 return ndead;
421382ac 717}
b62c8881 718
38c1593d
JH
719/* Update life information in all blocks where BB_DIRTY is set. */
720
3dec4024 721int
6cf9ac28 722update_life_info_in_dirty_blocks (enum update_life_extent extent, int prop_flags)
38c1593d 723{
d55bc081 724 sbitmap update_life_blocks = sbitmap_alloc (last_basic_block);
38c1593d 725 int n = 0;
e0082a72 726 basic_block bb;
0a2ed1f1 727 int retval = 0;
38c1593d
JH
728
729 sbitmap_zero (update_life_blocks);
e0082a72 730 FOR_EACH_BB (bb)
e0e577a2
RH
731 {
732 if (extent == UPDATE_LIFE_LOCAL)
733 {
734 if (bb->flags & BB_DIRTY)
735 {
736 SET_BIT (update_life_blocks, bb->index);
737 n++;
738 }
739 }
740 else
741 {
742 /* ??? Bootstrap with -march=pentium4 fails to terminate
743 with only a partial life update. */
744 SET_BIT (update_life_blocks, bb->index);
745 if (bb->flags & BB_DIRTY)
746 n++;
747 }
748 }
38c1593d
JH
749
750 if (n)
0a2ed1f1 751 retval = update_life_info (update_life_blocks, extent, prop_flags);
38c1593d
JH
752
753 sbitmap_free (update_life_blocks);
0a2ed1f1 754 return retval;
38c1593d
JH
755}
756
bb8a619e 757/* Free the variables allocated by find_basic_blocks. */
421382ac 758
2307e372 759void
bb8a619e 760free_basic_block_vars (void)
421382ac 761{
bb8a619e 762 if (basic_block_info)
402209ff 763 {
bb8a619e 764 clear_edges ();
6de9cd9a 765 basic_block_info = NULL;
e881bb1b 766 }
bb8a619e
SB
767 n_basic_blocks = 0;
768 last_basic_block = 0;
769
770 ENTRY_BLOCK_PTR->aux = NULL;
771 ENTRY_BLOCK_PTR->global_live_at_end = NULL;
772 EXIT_BLOCK_PTR->aux = NULL;
773 EXIT_BLOCK_PTR->global_live_at_start = NULL;
421382ac
BS
774}
775
402209ff 776/* Delete any insns that copy a register to itself. */
421382ac 777
3dec4024 778int
827c06b6 779delete_noop_moves (void)
421382ac 780{
402209ff
JH
781 rtx insn, next;
782 basic_block bb;
3dec4024 783 int nnoops = 0;
421382ac 784
e0082a72 785 FOR_EACH_BB (bb)
421382ac 786 {
a813c111 787 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
421382ac 788 {
402209ff
JH
789 next = NEXT_INSN (insn);
790 if (INSN_P (insn) && noop_move_p (insn))
791 {
eb9d8e4d
JW
792 rtx note;
793
794 /* If we're about to remove the first insn of a libcall
795 then move the libcall note to the next real insn and
796 update the retval note. */
797 if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
798 && XEXP (note, 0) != insn)
799 {
800 rtx new_libcall_insn = next_real_insn (insn);
801 rtx retval_note = find_reg_note (XEXP (note, 0),
802 REG_RETVAL, NULL_RTX);
803 REG_NOTES (new_libcall_insn)
804 = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
805 REG_NOTES (new_libcall_insn));
806 XEXP (retval_note, 0) = new_libcall_insn;
807 }
808
3dec4024
JH
809 delete_insn_and_edges (insn);
810 nnoops++;
402209ff 811 }
421382ac
BS
812 }
813 }
c263766c
RH
814 if (nnoops && dump_file)
815 fprintf (dump_file, "deleted %i noop moves", nnoops);
3dec4024 816 return nnoops;
421382ac
BS
817}
818
402209ff 819/* Delete any jump tables never referenced. We can't delete them at the
eaec9b3d 820 time of removing tablejump insn as they are referenced by the preceding
402209ff
JH
821 insns computing the destination, so we delay deleting and garbagecollect
822 them once life information is computed. */
0010687d 823void
6cf9ac28 824delete_dead_jumptables (void)
402209ff
JH
825{
826 rtx insn, next;
827 for (insn = get_insns (); insn; insn = next)
421382ac 828 {
402209ff 829 next = NEXT_INSN (insn);
4b4bf941 830 if (LABEL_P (insn)
967bd823 831 && LABEL_NUSES (insn) == LABEL_PRESERVE_P (insn)
4b4bf941 832 && JUMP_P (next)
402209ff
JH
833 && (GET_CODE (PATTERN (next)) == ADDR_VEC
834 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))
e881bb1b 835 {
c263766c
RH
836 if (dump_file)
837 fprintf (dump_file, "Dead jumptable %i removed\n", INSN_UID (insn));
53c17031
JH
838 delete_insn (NEXT_INSN (insn));
839 delete_insn (insn);
402209ff 840 next = NEXT_INSN (next);
e881bb1b 841 }
dc2ede84 842 }
e881bb1b
RH
843}
844
402209ff
JH
845/* Determine if the stack pointer is constant over the life of the function.
846 Only useful before prologues have been emitted. */
e881bb1b
RH
847
848static void
6cf9ac28
AJ
849notice_stack_pointer_modification_1 (rtx x, rtx pat ATTRIBUTE_UNUSED,
850 void *data ATTRIBUTE_UNUSED)
e881bb1b 851{
402209ff
JH
852 if (x == stack_pointer_rtx
853 /* The stack pointer is only modified indirectly as the result
854 of a push until later in flow. See the comments in rtl.texi
855 regarding Embedded Side-Effects on Addresses. */
3c0cb5de 856 || (MEM_P (x)
ec8e098d 857 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_AUTOINC
402209ff
JH
858 && XEXP (XEXP (x, 0), 0) == stack_pointer_rtx))
859 current_function_sp_is_unchanging = 0;
e881bb1b 860}
e6cfb550 861
336a6399 862static void
827c06b6 863notice_stack_pointer_modification (void)
e881bb1b 864{
827c06b6 865 basic_block bb;
402209ff 866 rtx insn;
e881bb1b 867
402209ff
JH
868 /* Assume that the stack pointer is unchanging if alloca hasn't
869 been used. */
870 current_function_sp_is_unchanging = !current_function_calls_alloca;
871 if (! current_function_sp_is_unchanging)
872 return;
e881bb1b 873
827c06b6
SB
874 FOR_EACH_BB (bb)
875 FOR_BB_INSNS (bb, insn)
876 {
877 if (INSN_P (insn))
878 {
879 /* Check if insn modifies the stack pointer. */
880 note_stores (PATTERN (insn),
881 notice_stack_pointer_modification_1,
882 NULL);
883 if (! current_function_sp_is_unchanging)
884 return;
885 }
886 }
e881bb1b 887}
0ecf09f9 888
402209ff
JH
889/* Mark a register in SET. Hard registers in large modes get all
890 of their component registers set as well. */
0ecf09f9 891
402209ff 892static void
6cf9ac28 893mark_reg (rtx reg, void *xset)
0ecf09f9 894{
402209ff
JH
895 regset set = (regset) xset;
896 int regno = REGNO (reg);
0ecf09f9 897
0bccc606 898 gcc_assert (GET_MODE (reg) != BLKmode);
0ecf09f9 899
402209ff
JH
900 SET_REGNO_REG_SET (set, regno);
901 if (regno < FIRST_PSEUDO_REGISTER)
0ecf09f9 902 {
66fd46b6 903 int n = hard_regno_nregs[regno][GET_MODE (reg)];
402209ff
JH
904 while (--n > 0)
905 SET_REGNO_REG_SET (set, regno + n);
0ecf09f9 906 }
0ecf09f9 907}
c586192c 908
402209ff
JH
909/* Mark those regs which are needed at the end of the function as live
910 at the end of the last basic block. */
c586192c 911
402209ff 912static void
6cf9ac28 913mark_regs_live_at_end (regset set)
402209ff
JH
914{
915 unsigned int i;
c586192c 916
402209ff
JH
917 /* If exiting needs the right stack value, consider the stack pointer
918 live at the end of the function. */
fe3ad572 919 if ((HAVE_epilogue && epilogue_completed)
402209ff
JH
920 || ! EXIT_IGNORE_STACK
921 || (! FRAME_POINTER_REQUIRED
922 && ! current_function_calls_alloca
923 && flag_omit_frame_pointer)
924 || current_function_sp_is_unchanging)
c586192c 925 {
402209ff 926 SET_REGNO_REG_SET (set, STACK_POINTER_REGNUM);
c586192c
MH
927 }
928
402209ff
JH
929 /* Mark the frame pointer if needed at the end of the function. If
930 we end up eliminating it, it will be removed from the live list
931 of each basic block by reload. */
c586192c 932
402209ff 933 if (! reload_completed || frame_pointer_needed)
a686dbf8 934 {
402209ff
JH
935 SET_REGNO_REG_SET (set, FRAME_POINTER_REGNUM);
936#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
937 /* If they are different, also mark the hard frame pointer as live. */
938 if (! LOCAL_REGNO (HARD_FRAME_POINTER_REGNUM))
dd3f0101 939 SET_REGNO_REG_SET (set, HARD_FRAME_POINTER_REGNUM);
402209ff 940#endif
a686dbf8 941 }
c586192c 942
402209ff
JH
943#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
944 /* Many architectures have a GP register even without flag_pic.
945 Assume the pic register is not in use, or will be handled by
946 other means, if it is not fixed. */
fc555370 947 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
402209ff
JH
948 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
949 SET_REGNO_REG_SET (set, PIC_OFFSET_TABLE_REGNUM);
950#endif
c586192c 951
402209ff
JH
952 /* Mark all global registers, and all registers used by the epilogue
953 as being live at the end of the function since they may be
954 referenced by our caller. */
955 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
956 if (global_regs[i] || EPILOGUE_USES (i))
957 SET_REGNO_REG_SET (set, i);
c586192c 958
fe3ad572 959 if (HAVE_epilogue && epilogue_completed)
ca9fef16 960 {
402209ff
JH
961 /* Mark all call-saved registers that we actually used. */
962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
963 if (regs_ever_live[i] && ! LOCAL_REGNO (i)
964 && ! TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
965 SET_REGNO_REG_SET (set, i);
ca9fef16 966 }
b9b2c339 967
402209ff
JH
968#ifdef EH_RETURN_DATA_REGNO
969 /* Mark the registers that will contain data for the handler. */
970 if (reload_completed && current_function_calls_eh_return)
971 for (i = 0; ; ++i)
972 {
973 unsigned regno = EH_RETURN_DATA_REGNO(i);
974 if (regno == INVALID_REGNUM)
975 break;
976 SET_REGNO_REG_SET (set, regno);
977 }
e9644cfe 978#endif
402209ff 979#ifdef EH_RETURN_STACKADJ_RTX
fe3ad572 980 if ((! HAVE_epilogue || ! epilogue_completed)
402209ff 981 && current_function_calls_eh_return)
7a442791 982 {
402209ff
JH
983 rtx tmp = EH_RETURN_STACKADJ_RTX;
984 if (tmp && REG_P (tmp))
985 mark_reg (tmp, set);
7a442791 986 }
402209ff
JH
987#endif
988#ifdef EH_RETURN_HANDLER_RTX
fe3ad572 989 if ((! HAVE_epilogue || ! epilogue_completed)
402209ff 990 && current_function_calls_eh_return)
2b2c8b3e 991 {
402209ff
JH
992 rtx tmp = EH_RETURN_HANDLER_RTX;
993 if (tmp && REG_P (tmp))
994 mark_reg (tmp, set);
2b2c8b3e 995 }
402209ff 996#endif
7a442791 997
402209ff
JH
998 /* Mark function return value. */
999 diddle_return_value (mark_reg, set);
7a442791
JH
1000}
1001
402209ff
JH
1002/* Propagate global life info around the graph of basic blocks. Begin
1003 considering blocks with their corresponding bit set in BLOCKS_IN.
1004 If BLOCKS_IN is null, consider it the universal set.
b9b2c339 1005
402209ff 1006 BLOCKS_OUT is set for every block that was changed. */
b9b2c339 1007
402209ff 1008static void
6cf9ac28 1009calculate_global_regs_live (sbitmap blocks_in, sbitmap blocks_out, int flags)
402209ff 1010{
e0082a72 1011 basic_block *queue, *qhead, *qtail, *qend, bb;
f3ea5f6a 1012 regset tmp, new_live_at_end, invalidated_by_call;
dda49b66
SB
1013
1014 /* The registers that are modified within this in block. */
1015 regset *local_sets;
1016
1017 /* The registers that are conditionally modified within this block.
1018 In other words, regs that are set only as part of a COND_EXEC. */
1019 regset *cond_local_sets;
1020
402209ff 1021 int i;
b9b2c339 1022
1540f9eb 1023 /* Some passes used to forget clear aux field of basic block causing
8d9afc4e 1024 sick behavior here. */
1540f9eb 1025#ifdef ENABLE_CHECKING
e0082a72 1026 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR, NULL, next_bb)
0bccc606 1027 gcc_assert (!bb->aux);
1540f9eb
JH
1028#endif
1029
04389919
NS
1030 tmp = ALLOC_REG_SET (&reg_obstack);
1031 new_live_at_end = ALLOC_REG_SET (&reg_obstack);
1032 invalidated_by_call = ALLOC_REG_SET (&reg_obstack);
b9b2c339 1033
d6a7951f 1034 /* Inconveniently, this is only readily available in hard reg set form. */
402209ff 1035 for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
f3ea5f6a
RH
1036 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
1037 SET_REGNO_REG_SET (invalidated_by_call, i);
2b2c8b3e 1038
dda49b66
SB
1039 /* Allocate space for the sets of local properties. */
1040 local_sets = xcalloc (last_basic_block - (INVALID_BLOCK + 1),
1041 sizeof (regset));
1042 cond_local_sets = xcalloc (last_basic_block - (INVALID_BLOCK + 1),
1043 sizeof (regset));
1044
402209ff
JH
1045 /* Create a worklist. Allocate an extra slot for ENTRY_BLOCK, and one
1046 because the `head == tail' style test for an empty queue doesn't
1047 work with a full queue. */
dda49b66 1048 queue = xmalloc ((n_basic_blocks - (INVALID_BLOCK + 1)) * sizeof (*queue));
402209ff 1049 qtail = queue;
dda49b66 1050 qhead = qend = queue + n_basic_blocks - (INVALID_BLOCK + 1);
2b2c8b3e 1051
402209ff
JH
1052 /* Queue the blocks set in the initial mask. Do this in reverse block
1053 number order so that we are more likely for the first round to do
1054 useful work. We use AUX non-null to flag that the block is queued. */
1055 if (blocks_in)
c319629b 1056 {
e0082a72
ZD
1057 FOR_EACH_BB (bb)
1058 if (TEST_BIT (blocks_in, bb->index))
1059 {
1060 *--qhead = bb;
1061 bb->aux = bb;
1062 }
2b2c8b3e 1063 }
402209ff 1064 else
e881bb1b 1065 {
bf77398c 1066 FOR_EACH_BB (bb)
402209ff 1067 {
402209ff
JH
1068 *--qhead = bb;
1069 bb->aux = bb;
1070 }
e881bb1b 1071 }
e881bb1b 1072
70e0ccd0
AO
1073 /* We clean aux when we remove the initially-enqueued bbs, but we
1074 don't enqueue ENTRY and EXIT initially, so clean them upfront and
1075 unconditionally. */
1076 ENTRY_BLOCK_PTR->aux = EXIT_BLOCK_PTR->aux = NULL;
1077
402209ff
JH
1078 if (blocks_out)
1079 sbitmap_zero (blocks_out);
e881bb1b 1080
402209ff
JH
1081 /* We work through the queue until there are no more blocks. What
1082 is live at the end of this block is precisely the union of what
1083 is live at the beginning of all its successors. So, we set its
1084 GLOBAL_LIVE_AT_END field based on the GLOBAL_LIVE_AT_START field
1085 for its successors. Then, we compute GLOBAL_LIVE_AT_START for
1086 this block by walking through the instructions in this block in
1087 reverse order and updating as we go. If that changed
1088 GLOBAL_LIVE_AT_START, we add the predecessors of the block to the
1089 queue; they will now need to recalculate GLOBAL_LIVE_AT_END.
e881bb1b 1090
402209ff
JH
1091 We are guaranteed to terminate, because GLOBAL_LIVE_AT_START
1092 never shrinks. If a register appears in GLOBAL_LIVE_AT_START, it
1093 must either be live at the end of the block, or used within the
1094 block. In the latter case, it will certainly never disappear
1095 from GLOBAL_LIVE_AT_START. In the former case, the register
1096 could go away only if it disappeared from GLOBAL_LIVE_AT_START
1097 for one of the successor blocks. By induction, that cannot
1098 occur. */
1099 while (qhead != qtail)
e881bb1b 1100 {
402209ff
JH
1101 int rescan, changed;
1102 basic_block bb;
e881bb1b 1103 edge e;
628f6a4e 1104 edge_iterator ei;
e881bb1b 1105
402209ff
JH
1106 bb = *qhead++;
1107 if (qhead == qend)
1108 qhead = queue;
1109 bb->aux = NULL;
1110
1111 /* Begin by propagating live_at_start from the successor blocks. */
1112 CLEAR_REG_SET (new_live_at_end);
e881bb1b 1113
628f6a4e
BE
1114 if (EDGE_COUNT (bb->succs) > 0)
1115 FOR_EACH_EDGE (e, ei, bb->succs)
15b5aef3
RH
1116 {
1117 basic_block sb = e->dest;
1118
1119 /* Call-clobbered registers die across exception and
1120 call edges. */
1121 /* ??? Abnormal call edges ignored for the moment, as this gets
1122 confused by sibling call edges, which crashes reg-stack. */
1123 if (e->flags & EDGE_EH)
eb59b8de
NS
1124 bitmap_ior_and_compl_into (new_live_at_end,
1125 sb->global_live_at_start,
1126 invalidated_by_call);
15b5aef3
RH
1127 else
1128 IOR_REG_SET (new_live_at_end, sb->global_live_at_start);
1129
1130 /* If a target saves one register in another (instead of on
1131 the stack) the save register will need to be live for EH. */
1132 if (e->flags & EDGE_EH)
1133 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1134 if (EH_USES (i))
1135 SET_REGNO_REG_SET (new_live_at_end, i);
1136 }
1137 else
1138 {
1139 /* This might be a noreturn function that throws. And
1140 even if it isn't, getting the unwind info right helps
1141 debugging. */
1142 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1143 if (EH_USES (i))
1144 SET_REGNO_REG_SET (new_live_at_end, i);
402209ff 1145 }
e881bb1b 1146
402209ff
JH
1147 /* The all-important stack pointer must always be live. */
1148 SET_REGNO_REG_SET (new_live_at_end, STACK_POINTER_REGNUM);
1e7d57a3 1149
402209ff
JH
1150 /* Before reload, there are a few registers that must be forced
1151 live everywhere -- which might not already be the case for
1152 blocks within infinite loops. */
1153 if (! reload_completed)
1154 {
1155 /* Any reference to any pseudo before reload is a potential
1156 reference of the frame pointer. */
1157 SET_REGNO_REG_SET (new_live_at_end, FRAME_POINTER_REGNUM);
c9bacfdb 1158
402209ff
JH
1159#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1160 /* Pseudos with argument area equivalences may require
1161 reloading via the argument pointer. */
1162 if (fixed_regs[ARG_POINTER_REGNUM])
1163 SET_REGNO_REG_SET (new_live_at_end, ARG_POINTER_REGNUM);
1164#endif
e881bb1b 1165
402209ff
JH
1166 /* Any constant, or pseudo with constant equivalences, may
1167 require reloading from memory using the pic register. */
fc555370 1168 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
402209ff
JH
1169 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
1170 SET_REGNO_REG_SET (new_live_at_end, PIC_OFFSET_TABLE_REGNUM);
e881bb1b 1171 }
e881bb1b 1172
402209ff
JH
1173 if (bb == ENTRY_BLOCK_PTR)
1174 {
1175 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
1176 continue;
1177 }
e881bb1b 1178
402209ff 1179 /* On our first pass through this block, we'll go ahead and continue.
dda49b66
SB
1180 Recognize first pass by checking if local_set is NULL for this
1181 basic block. On subsequent passes, we get to skip out early if
1182 live_at_end wouldn't have changed. */
e881bb1b 1183
dda49b66 1184 if (local_sets[bb->index - (INVALID_BLOCK + 1)] == NULL)
402209ff 1185 {
04389919
NS
1186 local_sets[bb->index - (INVALID_BLOCK + 1)]
1187 = ALLOC_REG_SET (&reg_obstack);
1188 cond_local_sets[bb->index - (INVALID_BLOCK + 1)]
1189 = ALLOC_REG_SET (&reg_obstack);
402209ff
JH
1190 rescan = 1;
1191 }
1192 else
1193 {
1194 /* If any bits were removed from live_at_end, we'll have to
1195 rescan the block. This wouldn't be necessary if we had
1196 precalculated local_live, however with PROP_SCAN_DEAD_CODE
1197 local_live is really dependent on live_at_end. */
55994078
NS
1198 rescan = bitmap_intersect_compl_p (bb->global_live_at_end,
1199 new_live_at_end);
1200
1201 if (!rescan)
dda49b66
SB
1202 {
1203 regset cond_local_set;
1204
1205 /* If any of the registers in the new live_at_end set are
1206 conditionally set in this basic block, we must rescan.
1207 This is because conditional lifetimes at the end of the
1208 block do not just take the live_at_end set into
1209 account, but also the liveness at the start of each
1210 successor block. We can miss changes in those sets if
1211 we only compare the new live_at_end against the
1212 previous one. */
1213 cond_local_set = cond_local_sets[bb->index - (INVALID_BLOCK + 1)];
1214 rescan = bitmap_intersect_p (new_live_at_end, cond_local_set);
1215 }
55994078
NS
1216
1217 if (!rescan)
402209ff 1218 {
dda49b66
SB
1219 regset local_set;
1220
402209ff
JH
1221 /* Find the set of changed bits. Take this opportunity
1222 to notice that this set is empty and early out. */
55994078
NS
1223 bitmap_xor (tmp, bb->global_live_at_end, new_live_at_end);
1224 if (bitmap_empty_p (tmp))
402209ff 1225 continue;
55994078 1226
dda49b66 1227 /* If any of the changed bits overlap with local_sets[bb],
55994078 1228 we'll have to rescan the block. */
dda49b66
SB
1229 local_set = local_sets[bb->index - (INVALID_BLOCK + 1)];
1230 rescan = bitmap_intersect_p (tmp, local_set);
402209ff
JH
1231 }
1232 }
e881bb1b 1233
402209ff
JH
1234 /* Let our caller know that BB changed enough to require its
1235 death notes updated. */
1236 if (blocks_out)
0b17ab2f 1237 SET_BIT (blocks_out, bb->index);
e881bb1b 1238
402209ff
JH
1239 if (! rescan)
1240 {
1241 /* Add to live_at_start the set of all registers in
1242 new_live_at_end that aren't in the old live_at_end. */
eb59b8de
NS
1243
1244 changed = bitmap_ior_and_compl_into (bb->global_live_at_start,
1245 new_live_at_end,
1246 bb->global_live_at_end);
402209ff 1247 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
402209ff
JH
1248 if (! changed)
1249 continue;
e881bb1b
RH
1250 }
1251 else
1252 {
402209ff 1253 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
e881bb1b 1254
402209ff
JH
1255 /* Rescan the block insn by insn to turn (a copy of) live_at_end
1256 into live_at_start. */
dda49b66
SB
1257 propagate_block (bb, new_live_at_end,
1258 local_sets[bb->index - (INVALID_BLOCK + 1)],
1259 cond_local_sets[bb->index - (INVALID_BLOCK + 1)],
1260 flags);
e881bb1b 1261
402209ff
JH
1262 /* If live_at start didn't change, no need to go farther. */
1263 if (REG_SET_EQUAL_P (bb->global_live_at_start, new_live_at_end))
1264 continue;
e881bb1b 1265
402209ff
JH
1266 COPY_REG_SET (bb->global_live_at_start, new_live_at_end);
1267 }
a8688bd6 1268
402209ff
JH
1269 /* Queue all predecessors of BB so that we may re-examine
1270 their live_at_end. */
628f6a4e 1271 FOR_EACH_EDGE (e, ei, bb->preds)
402209ff
JH
1272 {
1273 basic_block pb = e->src;
1274 if (pb->aux == NULL)
1275 {
1276 *qtail++ = pb;
1277 if (qtail == qend)
1278 qtail = queue;
1279 pb->aux = pb;
1280 }
1281 }
a8688bd6
AM
1282 }
1283
402209ff
JH
1284 FREE_REG_SET (tmp);
1285 FREE_REG_SET (new_live_at_end);
f3ea5f6a 1286 FREE_REG_SET (invalidated_by_call);
f5540cd4 1287
402209ff
JH
1288 if (blocks_out)
1289 {
1290 EXECUTE_IF_SET_IN_SBITMAP (blocks_out, 0, i,
1291 {
0b17ab2f 1292 basic_block bb = BASIC_BLOCK (i);
04389919
NS
1293 FREE_REG_SET (local_sets[bb->index - (INVALID_BLOCK + 1)]);
1294 FREE_REG_SET (cond_local_sets[bb->index - (INVALID_BLOCK + 1)]);
402209ff 1295 });
e881bb1b
RH
1296 }
1297 else
1298 {
e0082a72 1299 FOR_EACH_BB (bb)
402209ff 1300 {
04389919
NS
1301 FREE_REG_SET (local_sets[bb->index - (INVALID_BLOCK + 1)]);
1302 FREE_REG_SET (cond_local_sets[bb->index - (INVALID_BLOCK + 1)]);
402209ff 1303 }
f5540cd4 1304 }
19d3c25c 1305
402209ff 1306 free (queue);
dda49b66
SB
1307 free (cond_local_sets);
1308 free (local_sets);
e881bb1b 1309}
0626ef8a
AM
1310
1311\f
09da1532 1312/* This structure is used to pass parameters to and from the
4a913dd6
EC
1313 the function find_regno_partial(). It is used to pass in the
1314 register number we are looking, as well as to return any rtx
0626ef8a
AM
1315 we find. */
1316
1317typedef struct {
1318 unsigned regno_to_find;
1319 rtx retval;
1320} find_regno_partial_param;
1321
1322
1323/* Find the rtx for the reg numbers specified in 'data' if it is
1324 part of an expression which only uses part of the register. Return
1325 it in the structure passed in. */
4a913dd6 1326static int
6cf9ac28 1327find_regno_partial (rtx *ptr, void *data)
0626ef8a
AM
1328{
1329 find_regno_partial_param *param = (find_regno_partial_param *)data;
1330 unsigned reg = param->regno_to_find;
1331 param->retval = NULL_RTX;
1332
1333 if (*ptr == NULL_RTX)
1334 return 0;
1335
4a913dd6 1336 switch (GET_CODE (*ptr))
0626ef8a 1337 {
448cad06
AH
1338 case ZERO_EXTRACT:
1339 case SIGN_EXTRACT:
1340 case STRICT_LOW_PART:
f8cfc6aa 1341 if (REG_P (XEXP (*ptr, 0)) && REGNO (XEXP (*ptr, 0)) == reg)
448cad06
AH
1342 {
1343 param->retval = XEXP (*ptr, 0);
1344 return 1;
1345 }
1346 break;
0626ef8a 1347
448cad06 1348 case SUBREG:
f8cfc6aa 1349 if (REG_P (SUBREG_REG (*ptr))
448cad06
AH
1350 && REGNO (SUBREG_REG (*ptr)) == reg)
1351 {
1352 param->retval = SUBREG_REG (*ptr);
1353 return 1;
1354 }
1355 break;
1356
1357 default:
1358 break;
0626ef8a
AM
1359 }
1360
1361 return 0;
1362}
1363
1364/* Process all immediate successors of the entry block looking for pseudo
4a913dd6
EC
1365 registers which are live on entry. Find all of those whose first
1366 instance is a partial register reference of some kind, and initialize
0626ef8a 1367 them to 0 after the entry block. This will prevent bit sets within
4a913dd6 1368 registers whose value is unknown, and may contain some kind of sticky
0626ef8a
AM
1369 bits we don't want. */
1370
1371int
6cf9ac28 1372initialize_uninitialized_subregs (void)
0626ef8a
AM
1373{
1374 rtx insn;
1375 edge e;
3cd8c58a 1376 unsigned reg, did_something = 0;
0626ef8a 1377 find_regno_partial_param param;
628f6a4e 1378 edge_iterator ei;
0626ef8a 1379
628f6a4e 1380 FOR_EACH_EDGE (e, ei, ENTRY_BLOCK_PTR->succs)
0626ef8a
AM
1381 {
1382 basic_block bb = e->dest;
1383 regset map = bb->global_live_at_start;
a2041967
KH
1384 reg_set_iterator rsi;
1385
1386 EXECUTE_IF_SET_IN_REG_SET (map, FIRST_PSEUDO_REGISTER, reg, rsi)
0626ef8a
AM
1387 {
1388 int uid = REGNO_FIRST_UID (reg);
1389 rtx i;
1390
1391 /* Find an insn which mentions the register we are looking for.
1392 Its preferable to have an instance of the register's rtl since
4a913dd6 1393 there may be various flags set which we need to duplicate.
0626ef8a 1394 If we can't find it, its probably an automatic whose initial
23d1aac4 1395 value doesn't matter, or hopefully something we don't care about. */
0626ef8a
AM
1396 for (i = get_insns (); i && INSN_UID (i) != uid; i = NEXT_INSN (i))
1397 ;
1398 if (i != NULL_RTX)
1399 {
1400 /* Found the insn, now get the REG rtx, if we can. */
1401 param.regno_to_find = reg;
1402 for_each_rtx (&i, find_regno_partial, &param);
1403 if (param.retval != NULL_RTX)
1404 {
a7a7d7ac
KH
1405 start_sequence ();
1406 emit_move_insn (param.retval,
1407 CONST0_RTX (GET_MODE (param.retval)));
1408 insn = get_insns ();
1409 end_sequence ();
0626ef8a
AM
1410 insert_insn_on_edge (insn, e);
1411 did_something = 1;
1412 }
1413 }
a2041967 1414 }
0626ef8a
AM
1415 }
1416
1417 if (did_something)
1418 commit_edge_insertions ();
1419 return did_something;
1420}
1421
402209ff
JH
1422\f
1423/* Subroutines of life analysis. */
e881bb1b 1424
402209ff 1425/* Allocate the permanent data structures that represent the results
60580286 1426 of life analysis. */
e881bb1b 1427
60580286 1428static void
6cf9ac28 1429allocate_bb_life_data (void)
e881bb1b 1430{
e0082a72 1431 basic_block bb;
c9bacfdb 1432
e0082a72 1433 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR, NULL, next_bb)
e881bb1b 1434 {
04389919
NS
1435 bb->global_live_at_start = ALLOC_REG_SET (&reg_obstack);
1436 bb->global_live_at_end = ALLOC_REG_SET (&reg_obstack);
e881bb1b 1437 }
f1330226 1438
04389919 1439 regs_live_at_setjmp = ALLOC_REG_SET (&reg_obstack);
402209ff 1440}
0ab409ed 1441
402209ff 1442void
6cf9ac28 1443allocate_reg_life_data (void)
0ab409ed
MH
1444{
1445 int i;
0ab409ed 1446
402209ff 1447 max_regno = max_reg_num ();
0bccc606 1448 gcc_assert (!reg_deaths);
736b64dd 1449 reg_deaths = xcalloc (sizeof (*reg_deaths), max_regno);
0ab409ed 1450
402209ff
JH
1451 /* Recalculate the register space, in case it has grown. Old style
1452 vector oriented regsets would set regset_{size,bytes} here also. */
1453 allocate_reg_info (max_regno, FALSE, FALSE);
0ab409ed 1454
402209ff
JH
1455 /* Reset all the data we'll collect in propagate_block and its
1456 subroutines. */
1457 for (i = 0; i < max_regno; i++)
0ab409ed 1458 {
402209ff
JH
1459 REG_N_SETS (i) = 0;
1460 REG_N_REFS (i) = 0;
1461 REG_N_DEATHS (i) = 0;
1462 REG_N_CALLS_CROSSED (i) = 0;
1463 REG_LIVE_LENGTH (i) = 0;
e505be85 1464 REG_FREQ (i) = 0;
402209ff 1465 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
0ab409ed 1466 }
402209ff 1467}
0ab409ed 1468
402209ff 1469/* Delete dead instructions for propagate_block. */
f1330226 1470
402209ff 1471static void
6cf9ac28 1472propagate_block_delete_insn (rtx insn)
402209ff
JH
1473{
1474 rtx inote = find_reg_note (insn, REG_LABEL, NULL_RTX);
f1330226 1475
402209ff
JH
1476 /* If the insn referred to a label, and that label was attached to
1477 an ADDR_VEC, it's safe to delete the ADDR_VEC. In fact, it's
1478 pretty much mandatory to delete it, because the ADDR_VEC may be
1479 referencing labels that no longer exist.
f1330226 1480
402209ff
JH
1481 INSN may reference a deleted label, particularly when a jump
1482 table has been optimized into a direct jump. There's no
1483 real good way to fix up the reference to the deleted label
19f71cd7 1484 when the label is deleted, so we just allow it here. */
0ab409ed 1485
4b4bf941 1486 if (inote && LABEL_P (inote))
0ab409ed 1487 {
402209ff
JH
1488 rtx label = XEXP (inote, 0);
1489 rtx next;
0ab409ed 1490
402209ff
JH
1491 /* The label may be forced if it has been put in the constant
1492 pool. If that is the only use we must discard the table
1493 jump following it, but not the label itself. */
1494 if (LABEL_NUSES (label) == 1 + LABEL_PRESERVE_P (label)
1495 && (next = next_nonnote_insn (label)) != NULL
4b4bf941 1496 && JUMP_P (next)
402209ff
JH
1497 && (GET_CODE (PATTERN (next)) == ADDR_VEC
1498 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))
0ab409ed 1499 {
402209ff
JH
1500 rtx pat = PATTERN (next);
1501 int diff_vec_p = GET_CODE (pat) == ADDR_DIFF_VEC;
1502 int len = XVECLEN (pat, diff_vec_p);
1503 int i;
f1330226 1504
402209ff
JH
1505 for (i = 0; i < len; i++)
1506 LABEL_NUSES (XEXP (XVECEXP (pat, diff_vec_p, i), 0))--;
0ab409ed 1507
3dec4024
JH
1508 delete_insn_and_edges (next);
1509 ndead++;
0ab409ed
MH
1510 }
1511 }
1512
3dec4024
JH
1513 delete_insn_and_edges (insn);
1514 ndead++;
0ab409ed 1515}
e881bb1b 1516
402209ff
JH
1517/* Delete dead libcalls for propagate_block. Return the insn
1518 before the libcall. */
e881bb1b 1519
402209ff 1520static rtx
6cf9ac28 1521propagate_block_delete_libcall (rtx insn, rtx note)
402209ff
JH
1522{
1523 rtx first = XEXP (note, 0);
1524 rtx before = PREV_INSN (first);
e881bb1b 1525
3dec4024
JH
1526 delete_insn_chain_and_edges (first, insn);
1527 ndead++;
402209ff 1528 return before;
1e29ee12
JL
1529}
1530
402209ff
JH
1531/* Update the life-status of regs for one insn. Return the previous insn. */
1532
1533rtx
6cf9ac28 1534propagate_one_insn (struct propagate_block_info *pbi, rtx insn)
1e29ee12 1535{
402209ff
JH
1536 rtx prev = PREV_INSN (insn);
1537 int flags = pbi->flags;
1538 int insn_is_dead = 0;
1539 int libcall_is_dead = 0;
1540 rtx note;
3cd8c58a 1541 unsigned i;
1e29ee12 1542
402209ff
JH
1543 if (! INSN_P (insn))
1544 return prev;
164d59e0 1545
402209ff
JH
1546 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
1547 if (flags & PROP_SCAN_DEAD_CODE)
1548 {
1549 insn_is_dead = insn_dead_p (pbi, PATTERN (insn), 0, REG_NOTES (insn));
1550 libcall_is_dead = (insn_is_dead && note != 0
1551 && libcall_dead_p (pbi, note, insn));
1552 }
e881bb1b 1553
402209ff
JH
1554 /* If an instruction consists of just dead store(s) on final pass,
1555 delete it. */
1556 if ((flags & PROP_KILL_DEAD_CODE) && insn_is_dead)
e881bb1b 1557 {
402209ff
JH
1558 /* If we're trying to delete a prologue or epilogue instruction
1559 that isn't flagged as possibly being dead, something is wrong.
1560 But if we are keeping the stack pointer depressed, we might well
1561 be deleting insns that are used to compute the amount to update
1562 it by, so they are fine. */
1563 if (reload_completed
1564 && !(TREE_CODE (TREE_TYPE (current_function_decl)) == FUNCTION_TYPE
1565 && (TYPE_RETURNS_STACK_DEPRESSED
1566 (TREE_TYPE (current_function_decl))))
1567 && (((HAVE_epilogue || HAVE_prologue)
1568 && prologue_epilogue_contains (insn))
1569 || (HAVE_sibcall_epilogue
1570 && sibcall_epilogue_contains (insn)))
1571 && find_reg_note (insn, REG_MAYBE_DEAD, NULL_RTX) == 0)
31fce3c4 1572 fatal_insn ("Attempt to delete prologue/epilogue insn:", insn);
e881bb1b 1573
402209ff
JH
1574 /* Record sets. Do this even for dead instructions, since they
1575 would have killed the values if they hadn't been deleted. */
1576 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1577
402209ff
JH
1578 /* CC0 is now known to be dead. Either this insn used it,
1579 in which case it doesn't anymore, or clobbered it,
1580 so the next insn can't use it. */
1581 pbi->cc0_live = 0;
e881bb1b 1582
402209ff 1583 if (libcall_is_dead)
b77302be 1584 prev = propagate_block_delete_libcall (insn, note);
d35dfca9
JL
1585 else
1586 {
1587
b0ac73f8
JL
1588 /* If INSN contains a RETVAL note and is dead, but the libcall
1589 as a whole is not dead, then we want to remove INSN, but
1590 not the whole libcall sequence.
1591
6cf9ac28 1592 However, we need to also remove the dangling REG_LIBCALL
b0ac73f8
JL
1593 note so that we do not have mis-matched LIBCALL/RETVAL
1594 notes. In theory we could find a new location for the
6cf9ac28 1595 REG_RETVAL note, but it hardly seems worth the effort.
b0ac73f8
JL
1596
1597 NOTE at this point will be the RETVAL note if it exists. */
d35dfca9
JL
1598 if (note)
1599 {
d35dfca9 1600 rtx libcall_note;
6cf9ac28 1601
d35dfca9
JL
1602 libcall_note
1603 = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
1604 remove_note (XEXP (note, 0), libcall_note);
1605 }
b0ac73f8
JL
1606
1607 /* Similarly if INSN contains a LIBCALL note, remove the
fbe5a4a6 1608 dangling REG_RETVAL note. */
b0ac73f8
JL
1609 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
1610 if (note)
1611 {
1612 rtx retval_note;
1613
1614 retval_note
1615 = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
1616 remove_note (XEXP (note, 0), retval_note);
1617 }
1618
1619 /* Now delete INSN. */
d35dfca9
JL
1620 propagate_block_delete_insn (insn);
1621 }
e881bb1b 1622
402209ff
JH
1623 return prev;
1624 }
e881bb1b 1625
402209ff
JH
1626 /* See if this is an increment or decrement that can be merged into
1627 a following memory address. */
1628#ifdef AUTO_INC_DEC
1629 {
b3694847 1630 rtx x = single_set (insn);
e881bb1b 1631
402209ff
JH
1632 /* Does this instruction increment or decrement a register? */
1633 if ((flags & PROP_AUTOINC)
1634 && x != 0
f8cfc6aa 1635 && REG_P (SET_DEST (x))
402209ff
JH
1636 && (GET_CODE (SET_SRC (x)) == PLUS
1637 || GET_CODE (SET_SRC (x)) == MINUS)
1638 && XEXP (SET_SRC (x), 0) == SET_DEST (x)
1639 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1640 /* Ok, look for a following memory ref we can combine with.
1641 If one is found, change the memory ref to a PRE_INC
1642 or PRE_DEC, cancel this insn, and return 1.
1643 Return 0 if nothing has been done. */
1644 && try_pre_increment_1 (pbi, insn))
1645 return prev;
1646 }
1647#endif /* AUTO_INC_DEC */
e881bb1b 1648
402209ff 1649 CLEAR_REG_SET (pbi->new_set);
e881bb1b 1650
402209ff
JH
1651 /* If this is not the final pass, and this insn is copying the value of
1652 a library call and it's dead, don't scan the insns that perform the
1653 library call, so that the call's arguments are not marked live. */
1654 if (libcall_is_dead)
e881bb1b 1655 {
402209ff
JH
1656 /* Record the death of the dest reg. */
1657 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1658
402209ff
JH
1659 insn = XEXP (note, 0);
1660 return PREV_INSN (insn);
e881bb1b 1661 }
402209ff
JH
1662 else if (GET_CODE (PATTERN (insn)) == SET
1663 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx
1664 && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
1665 && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx
1666 && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
e344dbf3
R
1667 {
1668 /* We have an insn to pop a constant amount off the stack.
1669 (Such insns use PLUS regardless of the direction of the stack,
1670 and any insn to adjust the stack by a constant is always a pop
1671 or part of a push.)
1672 These insns, if not dead stores, have no effect on life, though
1673 they do have an effect on the memory stores we are tracking. */
1674 invalidate_mems_from_set (pbi, stack_pointer_rtx);
1675 /* Still, we need to update local_set, lest ifcvt.c:dead_or_predicable
1676 concludes that the stack pointer is not modified. */
1677 mark_set_regs (pbi, PATTERN (insn), insn);
1678 }
402209ff
JH
1679 else
1680 {
5a133afd 1681 rtx note;
402209ff
JH
1682 /* Any regs live at the time of a call instruction must not go
1683 in a register clobbered by calls. Find all regs now live and
1684 record this for them. */
e881bb1b 1685
4b4bf941 1686 if (CALL_P (insn) && (flags & PROP_REG_INFO))
a2041967
KH
1687 {
1688 reg_set_iterator rsi;
1689 EXECUTE_IF_SET_IN_REG_SET (pbi->reg_live, 0, i, rsi)
1690 REG_N_CALLS_CROSSED (i)++;
1691 }
e881bb1b 1692
402209ff
JH
1693 /* Record sets. Do this even for dead instructions, since they
1694 would have killed the values if they hadn't been deleted. */
1695 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1696
4b4bf941 1697 if (CALL_P (insn))
402209ff 1698 {
d444b5e8
RH
1699 regset live_at_end;
1700 bool sibcall_p;
402209ff 1701 rtx note, cond;
d444b5e8 1702 int i;
e881bb1b 1703
402209ff
JH
1704 cond = NULL_RTX;
1705 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
1706 cond = COND_EXEC_TEST (PATTERN (insn));
e881bb1b 1707
fe4b3c79
JL
1708 /* Non-constant calls clobber memory, constant calls do not
1709 clobber memory, though they may clobber outgoing arguments
1710 on the stack. */
402209ff
JH
1711 if (! CONST_OR_PURE_CALL_P (insn))
1712 {
1713 free_EXPR_LIST_list (&pbi->mem_set_list);
1714 pbi->mem_set_list_len = 0;
1715 }
dd3f0101 1716 else
fe4b3c79 1717 invalidate_mems_from_set (pbi, stack_pointer_rtx);
e881bb1b 1718
402209ff
JH
1719 /* There may be extra registers to be clobbered. */
1720 for (note = CALL_INSN_FUNCTION_USAGE (insn);
1721 note;
1722 note = XEXP (note, 1))
1723 if (GET_CODE (XEXP (note, 0)) == CLOBBER)
1724 mark_set_1 (pbi, CLOBBER, XEXP (XEXP (note, 0), 0),
1725 cond, insn, pbi->flags);
c9bacfdb 1726
d444b5e8 1727 /* Calls change all call-used and global registers; sibcalls do not
99af0d26
RH
1728 clobber anything that must be preserved at end-of-function,
1729 except for return values. */
d444b5e8
RH
1730
1731 sibcall_p = SIBLING_CALL_P (insn);
1732 live_at_end = EXIT_BLOCK_PTR->global_live_at_start;
402209ff 1733 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
d444b5e8 1734 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)
99af0d26
RH
1735 && ! (sibcall_p
1736 && REGNO_REG_SET_P (live_at_end, i)
57856e4d
R
1737 && ! refers_to_regno_p (i, i+1,
1738 current_function_return_rtx,
1739 (rtx *) 0)))
402209ff 1740 {
a10016d3 1741 enum rtx_code code = global_regs[i] ? SET : CLOBBER;
402209ff 1742 /* We do not want REG_UNUSED notes for these registers. */
a10016d3 1743 mark_set_1 (pbi, code, regno_reg_rtx[i], cond, insn,
402209ff
JH
1744 pbi->flags & ~(PROP_DEATH_NOTES | PROP_REG_INFO));
1745 }
1746 }
312f6255 1747
402209ff
JH
1748 /* If an insn doesn't use CC0, it becomes dead since we assume
1749 that every insn clobbers it. So show it dead here;
1750 mark_used_regs will set it live if it is referenced. */
1751 pbi->cc0_live = 0;
e881bb1b 1752
402209ff
JH
1753 /* Record uses. */
1754 if (! insn_is_dead)
1755 mark_used_regs (pbi, PATTERN (insn), NULL_RTX, insn);
5a133afd
JH
1756 if ((flags & PROP_EQUAL_NOTES)
1757 && ((note = find_reg_note (insn, REG_EQUAL, NULL_RTX))
1758 || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX))))
1759 mark_used_regs (pbi, XEXP (note, 0), NULL_RTX, insn);
e881bb1b 1760
402209ff
JH
1761 /* Sometimes we may have inserted something before INSN (such as a move)
1762 when we make an auto-inc. So ensure we will scan those insns. */
1763#ifdef AUTO_INC_DEC
1764 prev = PREV_INSN (insn);
1765#endif
e881bb1b 1766
4b4bf941 1767 if (! insn_is_dead && CALL_P (insn))
402209ff 1768 {
b3694847 1769 int i;
402209ff 1770 rtx note, cond;
e881bb1b 1771
402209ff
JH
1772 cond = NULL_RTX;
1773 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
1774 cond = COND_EXEC_TEST (PATTERN (insn));
e881bb1b 1775
ee960939
OH
1776 /* Calls use their arguments, and may clobber memory which
1777 address involves some register. */
402209ff
JH
1778 for (note = CALL_INSN_FUNCTION_USAGE (insn);
1779 note;
1780 note = XEXP (note, 1))
ee960939
OH
1781 /* We find USE or CLOBBER entities in a FUNCTION_USAGE list: both
1782 of which mark_used_regs knows how to handle. */
1783 mark_used_regs (pbi, XEXP (XEXP (note, 0), 0), cond, insn);
e881bb1b 1784
402209ff 1785 /* The stack ptr is used (honorarily) by a CALL insn. */
736b64dd
JH
1786 if ((flags & PROP_REG_INFO)
1787 && !REGNO_REG_SET_P (pbi->reg_live, STACK_POINTER_REGNUM))
1788 reg_deaths[STACK_POINTER_REGNUM] = pbi->insn_num;
402209ff 1789 SET_REGNO_REG_SET (pbi->reg_live, STACK_POINTER_REGNUM);
e881bb1b 1790
402209ff
JH
1791 /* Calls may also reference any of the global registers,
1792 so they are made live. */
1793 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1794 if (global_regs[i])
e50126e8 1795 mark_used_reg (pbi, regno_reg_rtx[i], cond, insn);
402209ff 1796 }
e881bb1b
RH
1797 }
1798
736b64dd 1799 pbi->insn_num++;
402209ff
JH
1800
1801 return prev;
e881bb1b
RH
1802}
1803
402209ff
JH
1804/* Initialize a propagate_block_info struct for public consumption.
1805 Note that the structure itself is opaque to this file, but that
1806 the user can use the regsets provided here. */
e881bb1b 1807
402209ff 1808struct propagate_block_info *
6cf9ac28
AJ
1809init_propagate_block_info (basic_block bb, regset live, regset local_set,
1810 regset cond_local_set, int flags)
e881bb1b 1811{
402209ff 1812 struct propagate_block_info *pbi = xmalloc (sizeof (*pbi));
e881bb1b 1813
402209ff
JH
1814 pbi->bb = bb;
1815 pbi->reg_live = live;
1816 pbi->mem_set_list = NULL_RTX;
1817 pbi->mem_set_list_len = 0;
1818 pbi->local_set = local_set;
1819 pbi->cond_local_set = cond_local_set;
1820 pbi->cc0_live = 0;
1821 pbi->flags = flags;
736b64dd 1822 pbi->insn_num = 0;
c9bacfdb 1823
402209ff 1824 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
703ad42b 1825 pbi->reg_next_use = xcalloc (max_reg_num (), sizeof (rtx));
e881bb1b 1826 else
402209ff 1827 pbi->reg_next_use = NULL;
e6cfb550 1828
8bdbfff5 1829 pbi->new_set = BITMAP_ALLOC (NULL);
7a442791 1830
402209ff
JH
1831#ifdef HAVE_conditional_execution
1832 pbi->reg_cond_dead = splay_tree_new (splay_tree_compare_ints, NULL,
1833 free_reg_cond_life_info);
8bdbfff5 1834 pbi->reg_cond_reg = BITMAP_ALLOC (NULL);
7a442791 1835
38b2a605
RE
1836 /* If this block ends in a conditional branch, for each register
1837 live from one side of the branch and not the other, record the
1838 register as conditionally dead. */
4b4bf941 1839 if (JUMP_P (BB_END (bb))
a813c111 1840 && any_condjump_p (BB_END (bb)))
402209ff 1841 {
04389919 1842 regset diff = ALLOC_REG_SET (&reg_obstack);
402209ff 1843 basic_block bb_true, bb_false;
db20bd62 1844 unsigned i;
421382ac 1845
402209ff 1846 /* Identify the successor blocks. */
628f6a4e
BE
1847 bb_true = EDGE_SUCC (bb, 0)->dest;
1848 if (EDGE_COUNT (bb->succs) > 1)
402209ff 1849 {
628f6a4e 1850 bb_false = EDGE_SUCC (bb, 1)->dest;
c9bacfdb 1851
628f6a4e 1852 if (EDGE_SUCC (bb, 0)->flags & EDGE_FALLTHRU)
402209ff
JH
1853 {
1854 basic_block t = bb_false;
1855 bb_false = bb_true;
1856 bb_true = t;
1857 }
0bccc606 1858 else
628f6a4e 1859 gcc_assert (EDGE_SUCC (bb, 1)->flags & EDGE_FALLTHRU);
402209ff
JH
1860 }
1861 else
1862 {
1863 /* This can happen with a conditional jump to the next insn. */
0bccc606 1864 gcc_assert (JUMP_LABEL (BB_END (bb)) == BB_HEAD (bb_true));
421382ac 1865
402209ff
JH
1866 /* Simplest way to do nothing. */
1867 bb_false = bb_true;
1868 }
be1bb652 1869
402209ff 1870 /* Compute which register lead different lives in the successors. */
f7569f3a
NS
1871 bitmap_xor (diff, bb_true->global_live_at_start,
1872 bb_false->global_live_at_start);
1873
1874 if (!bitmap_empty_p (diff))
1875 {
38b2a605 1876 /* Extract the condition from the branch. */
a813c111 1877 rtx set_src = SET_SRC (pc_set (BB_END (bb)));
38b2a605 1878 rtx cond_true = XEXP (set_src, 0);
402209ff 1879 rtx reg = XEXP (cond_true, 0);
8965ece1 1880 enum rtx_code inv_cond;
be1bb652 1881
402209ff
JH
1882 if (GET_CODE (reg) == SUBREG)
1883 reg = SUBREG_REG (reg);
dc108b7a 1884
38b2a605 1885 /* We can only track conditional lifetimes if the condition is
8965ece1
PB
1886 in the form of a reversible comparison of a register against
1887 zero. If the condition is more complex than that, then it is
1888 safe not to record any information. */
1889 inv_cond = reversed_comparison_code (cond_true, BB_END (bb));
1890 if (inv_cond != UNKNOWN
1891 && REG_P (reg)
38b2a605
RE
1892 && XEXP (cond_true, 1) == const0_rtx)
1893 {
1894 rtx cond_false
8965ece1 1895 = gen_rtx_fmt_ee (inv_cond,
38b2a605
RE
1896 GET_MODE (cond_true), XEXP (cond_true, 0),
1897 XEXP (cond_true, 1));
a2041967
KH
1898 reg_set_iterator rsi;
1899
38b2a605
RE
1900 if (GET_CODE (XEXP (set_src, 1)) == PC)
1901 {
1902 rtx t = cond_false;
1903 cond_false = cond_true;
1904 cond_true = t;
1905 }
dc108b7a 1906
38b2a605 1907 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (reg));
dc108b7a 1908
38b2a605 1909 /* For each such register, mark it conditionally dead. */
a2041967
KH
1910 EXECUTE_IF_SET_IN_REG_SET (diff, 0, i, rsi)
1911 {
1912 struct reg_cond_life_info *rcli;
1913 rtx cond;
1914
1915 rcli = xmalloc (sizeof (*rcli));
1916
1917 if (REGNO_REG_SET_P (bb_true->global_live_at_start, i))
1918 cond = cond_false;
1919 else
1920 cond = cond_true;
1921 rcli->condition = cond;
1922 rcli->stores = const0_rtx;
1923 rcli->orig_condition = cond;
1924
1925 splay_tree_insert (pbi->reg_cond_dead, i,
1926 (splay_tree_value) rcli);
1927 }
38b2a605 1928 }
dc108b7a 1929 }
dc108b7a 1930
402209ff 1931 FREE_REG_SET (diff);
dc108b7a 1932 }
402209ff
JH
1933#endif
1934
1935 /* If this block has no successors, any stores to the frame that aren't
1936 used later in the block are dead. So make a pass over the block
1937 recording any such that are made and show them dead at the end. We do
1938 a very conservative and simple job here. */
1939 if (optimize
1940 && ! (TREE_CODE (TREE_TYPE (current_function_decl)) == FUNCTION_TYPE
1941 && (TYPE_RETURNS_STACK_DEPRESSED
1942 (TREE_TYPE (current_function_decl))))
5149f070 1943 && (flags & PROP_SCAN_DEAD_STORES)
628f6a4e
BE
1944 && (EDGE_COUNT (bb->succs) == 0
1945 || (EDGE_COUNT (bb->succs) == 1
1946 && EDGE_SUCC (bb, 0)->dest == EXIT_BLOCK_PTR
402209ff 1947 && ! current_function_calls_eh_return)))
dc108b7a 1948 {
402209ff 1949 rtx insn, set;
a813c111 1950 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
4b4bf941 1951 if (NONJUMP_INSN_P (insn)
402209ff 1952 && (set = single_set (insn))
3c0cb5de 1953 && MEM_P (SET_DEST (set)))
402209ff
JH
1954 {
1955 rtx mem = SET_DEST (set);
1956 rtx canon_mem = canon_rtx (mem);
1957
402209ff
JH
1958 if (XEXP (canon_mem, 0) == frame_pointer_rtx
1959 || (GET_CODE (XEXP (canon_mem, 0)) == PLUS
1960 && XEXP (XEXP (canon_mem, 0), 0) == frame_pointer_rtx
1961 && GET_CODE (XEXP (XEXP (canon_mem, 0), 1)) == CONST_INT))
1962 add_to_mem_set_list (pbi, canon_mem);
1963 }
dc108b7a 1964 }
dc108b7a 1965
402209ff 1966 return pbi;
dc108b7a
RH
1967}
1968
402209ff 1969/* Release a propagate_block_info struct. */
558389e3 1970
402209ff 1971void
6cf9ac28 1972free_propagate_block_info (struct propagate_block_info *pbi)
558389e3 1973{
402209ff 1974 free_EXPR_LIST_list (&pbi->mem_set_list);
558389e3 1975
8bdbfff5 1976 BITMAP_FREE (pbi->new_set);
558389e3 1977
402209ff
JH
1978#ifdef HAVE_conditional_execution
1979 splay_tree_delete (pbi->reg_cond_dead);
8bdbfff5 1980 BITMAP_FREE (pbi->reg_cond_reg);
402209ff 1981#endif
558389e3 1982
736b64dd
JH
1983 if (pbi->flags & PROP_REG_INFO)
1984 {
1985 int num = pbi->insn_num;
3cd8c58a 1986 unsigned i;
a2041967 1987 reg_set_iterator rsi;
736b64dd 1988
a2041967
KH
1989 EXECUTE_IF_SET_IN_REG_SET (pbi->reg_live, 0, i, rsi)
1990 {
1991 REG_LIVE_LENGTH (i) += num - reg_deaths[i];
1992 reg_deaths[i] = 0;
1993 }
736b64dd 1994 }
402209ff
JH
1995 if (pbi->reg_next_use)
1996 free (pbi->reg_next_use);
558389e3 1997
402209ff
JH
1998 free (pbi);
1999}
336a6399 2000
402209ff
JH
2001/* Compute the registers live at the beginning of a basic block BB from
2002 those live at the end.
c9bacfdb 2003
402209ff
JH
2004 When called, REG_LIVE contains those live at the end. On return, it
2005 contains those live at the beginning.
ee7b8369 2006
402209ff
JH
2007 LOCAL_SET, if non-null, will be set with all registers killed
2008 unconditionally by this basic block.
2009 Likewise, COND_LOCAL_SET, if non-null, will be set with all registers
2010 killed conditionally by this basic block. If there is any unconditional
2011 set of a register, then the corresponding bit will be set in LOCAL_SET
2012 and cleared in COND_LOCAL_SET.
2013 It is valid for LOCAL_SET and COND_LOCAL_SET to be the same set. In this
2014 case, the resulting set will be equal to the union of the two sets that
2015 would otherwise be computed.
558389e3 2016
cc2902df 2017 Return nonzero if an INSN is deleted (i.e. by dead code removal). */
558389e3 2018
402209ff 2019int
6cf9ac28
AJ
2020propagate_block (basic_block bb, regset live, regset local_set,
2021 regset cond_local_set, int flags)
558389e3 2022{
402209ff
JH
2023 struct propagate_block_info *pbi;
2024 rtx insn, prev;
2025 int changed;
558389e3 2026
402209ff 2027 pbi = init_propagate_block_info (bb, live, local_set, cond_local_set, flags);
be1bb652 2028
402209ff 2029 if (flags & PROP_REG_INFO)
be1bb652 2030 {
3cd8c58a 2031 unsigned i;
a2041967 2032 reg_set_iterator rsi;
558389e3 2033
402209ff
JH
2034 /* Process the regs live at the end of the block.
2035 Mark them as not local to any one basic block. */
a2041967
KH
2036 EXECUTE_IF_SET_IN_REG_SET (live, 0, i, rsi)
2037 REG_BASIC_BLOCK (i) = REG_BLOCK_GLOBAL;
402209ff 2038 }
558389e3 2039
402209ff 2040 /* Scan the block an insn at a time from end to beginning. */
558389e3 2041
402209ff 2042 changed = 0;
a813c111 2043 for (insn = BB_END (bb); ; insn = prev)
402209ff
JH
2044 {
2045 /* If this is a call to `setjmp' et al, warn if any
2046 non-volatile datum is live. */
2047 if ((flags & PROP_REG_INFO)
4b4bf941 2048 && CALL_P (insn)
402209ff
JH
2049 && find_reg_note (insn, REG_SETJMP, NULL))
2050 IOR_REG_SET (regs_live_at_setjmp, pbi->reg_live);
558389e3 2051
402209ff 2052 prev = propagate_one_insn (pbi, insn);
bc35512f
JH
2053 if (!prev)
2054 changed |= insn != get_insns ();
2055 else
2056 changed |= NEXT_INSN (prev) != insn;
336a6399 2057
a813c111 2058 if (insn == BB_HEAD (bb))
402209ff 2059 break;
336a6399
RH
2060 }
2061
402209ff
JH
2062 free_propagate_block_info (pbi);
2063
2064 return changed;
558389e3 2065}
402209ff
JH
2066\f
2067/* Return 1 if X (the body of an insn, or part of it) is just dead stores
2068 (SET expressions whose destinations are registers dead after the insn).
2069 NEEDED is the regset that says which regs are alive after the insn.
2070
cc2902df 2071 Unless CALL_OK is nonzero, an insn is needed if it contains a CALL.
558389e3 2072
402209ff
JH
2073 If X is the entire body of an insn, NOTES contains the reg notes
2074 pertaining to the insn. */
dc2ede84 2075
dc2ede84 2076static int
6cf9ac28
AJ
2077insn_dead_p (struct propagate_block_info *pbi, rtx x, int call_ok,
2078 rtx notes ATTRIBUTE_UNUSED)
dc2ede84 2079{
402209ff 2080 enum rtx_code code = GET_CODE (x);
be1bb652 2081
a646f6cc
AH
2082 /* Don't eliminate insns that may trap. */
2083 if (flag_non_call_exceptions && may_trap_p (x))
2084 return 0;
2085
402209ff 2086#ifdef AUTO_INC_DEC
ff6051b7
GK
2087 /* As flow is invoked after combine, we must take existing AUTO_INC
2088 expressions into account. */
2089 for (; notes; notes = XEXP (notes, 1))
e881bb1b 2090 {
ff6051b7 2091 if (REG_NOTE_KIND (notes) == REG_INC)
336a6399 2092 {
ff6051b7 2093 int regno = REGNO (XEXP (notes, 0));
4a913dd6 2094
ff6051b7
GK
2095 /* Don't delete insns to set global regs. */
2096 if ((regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2097 || REGNO_REG_SET_P (pbi->reg_live, regno))
2098 return 0;
402209ff 2099 }
336a6399 2100 }
402209ff 2101#endif
4793dca1 2102
402209ff
JH
2103 /* If setting something that's a reg or part of one,
2104 see if that register's altered value will be live. */
558389e3 2105
402209ff 2106 if (code == SET)
7a442791 2107 {
402209ff 2108 rtx r = SET_DEST (x);
b02eea61 2109
402209ff
JH
2110#ifdef HAVE_cc0
2111 if (GET_CODE (r) == CC0)
2112 return ! pbi->cc0_live;
2113#endif
b9f22704 2114
402209ff
JH
2115 /* A SET that is a subroutine call cannot be dead. */
2116 if (GET_CODE (SET_SRC (x)) == CALL)
2117 {
2118 if (! call_ok)
2119 return 0;
2120 }
b02eea61 2121
402209ff
JH
2122 /* Don't eliminate loads from volatile memory or volatile asms. */
2123 else if (volatile_refs_p (SET_SRC (x)))
2124 return 0;
7a442791 2125
3c0cb5de 2126 if (MEM_P (r))
7a442791 2127 {
402209ff 2128 rtx temp, canon_r;
b9f22704 2129
402209ff
JH
2130 if (MEM_VOLATILE_P (r) || GET_MODE (r) == BLKmode)
2131 return 0;
0068fd96 2132
402209ff 2133 canon_r = canon_rtx (r);
0068fd96 2134
402209ff
JH
2135 /* Walk the set of memory locations we are currently tracking
2136 and see if one is an identical match to this memory location.
2137 If so, this memory write is dead (remember, we're walking
2138 backwards from the end of the block to the start). Since
2139 rtx_equal_p does not check the alias set or flags, we also
2140 must have the potential for them to conflict (anti_dependence). */
2141 for (temp = pbi->mem_set_list; temp != 0; temp = XEXP (temp, 1))
389fdba0 2142 if (anti_dependence (r, XEXP (temp, 0)))
402209ff
JH
2143 {
2144 rtx mem = XEXP (temp, 0);
0068fd96 2145
402209ff
JH
2146 if (rtx_equal_p (XEXP (canon_r, 0), XEXP (mem, 0))
2147 && (GET_MODE_SIZE (GET_MODE (canon_r))
2148 <= GET_MODE_SIZE (GET_MODE (mem))))
2149 return 1;
7a442791 2150
402209ff
JH
2151#ifdef AUTO_INC_DEC
2152 /* Check if memory reference matches an auto increment. Only
2153 post increment/decrement or modify are valid. */
2154 if (GET_MODE (mem) == GET_MODE (r)
2155 && (GET_CODE (XEXP (mem, 0)) == POST_DEC
2156 || GET_CODE (XEXP (mem, 0)) == POST_INC
2157 || GET_CODE (XEXP (mem, 0)) == POST_MODIFY)
2158 && GET_MODE (XEXP (mem, 0)) == GET_MODE (r)
2159 && rtx_equal_p (XEXP (XEXP (mem, 0), 0), XEXP (r, 0)))
2160 return 1;
2161#endif
2162 }
b02eea61 2163 }
d69d0316 2164 else
7a442791 2165 {
402209ff
JH
2166 while (GET_CODE (r) == SUBREG
2167 || GET_CODE (r) == STRICT_LOW_PART
2168 || GET_CODE (r) == ZERO_EXTRACT)
2169 r = XEXP (r, 0);
b02eea61 2170
f8cfc6aa 2171 if (REG_P (r))
d69d0316 2172 {
402209ff 2173 int regno = REGNO (r);
b02eea61 2174
402209ff
JH
2175 /* Obvious. */
2176 if (REGNO_REG_SET_P (pbi->reg_live, regno))
2177 return 0;
7a442791 2178
402209ff
JH
2179 /* If this is a hard register, verify that subsequent
2180 words are not needed. */
2181 if (regno < FIRST_PSEUDO_REGISTER)
2182 {
66fd46b6 2183 int n = hard_regno_nregs[regno][GET_MODE (r)];
46fac664 2184
402209ff
JH
2185 while (--n > 0)
2186 if (REGNO_REG_SET_P (pbi->reg_live, regno+n))
2187 return 0;
2188 }
46fac664 2189
402209ff
JH
2190 /* Don't delete insns to set global regs. */
2191 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2192 return 0;
46fac664 2193
402209ff
JH
2194 /* Make sure insns to set the stack pointer aren't deleted. */
2195 if (regno == STACK_POINTER_REGNUM)
2196 return 0;
b02eea61 2197
402209ff
JH
2198 /* ??? These bits might be redundant with the force live bits
2199 in calculate_global_regs_live. We would delete from
2200 sequential sets; whether this actually affects real code
2201 for anything but the stack pointer I don't know. */
2202 /* Make sure insns to set the frame pointer aren't deleted. */
2203 if (regno == FRAME_POINTER_REGNUM
2204 && (! reload_completed || frame_pointer_needed))
2205 return 0;
2206#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2207 if (regno == HARD_FRAME_POINTER_REGNUM
2208 && (! reload_completed || frame_pointer_needed))
2209 return 0;
2210#endif
b02eea61 2211
402209ff
JH
2212#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2213 /* Make sure insns to set arg pointer are never deleted
2214 (if the arg pointer isn't fixed, there will be a USE
2215 for it, so we can treat it normally). */
2216 if (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
2217 return 0;
2218#endif
46fac664 2219
402209ff
JH
2220 /* Otherwise, the set is dead. */
2221 return 1;
2222 }
2223 }
2224 }
46fac664 2225
402209ff
JH
2226 /* If performing several activities, insn is dead if each activity
2227 is individually dead. Also, CLOBBERs and USEs can be ignored; a
2228 CLOBBER or USE that's inside a PARALLEL doesn't make the insn
2229 worth keeping. */
2230 else if (code == PARALLEL)
2231 {
2232 int i = XVECLEN (x, 0);
46fac664 2233
402209ff
JH
2234 for (i--; i >= 0; i--)
2235 if (GET_CODE (XVECEXP (x, 0, i)) != CLOBBER
2236 && GET_CODE (XVECEXP (x, 0, i)) != USE
2237 && ! insn_dead_p (pbi, XVECEXP (x, 0, i), call_ok, NULL_RTX))
2238 return 0;
46fac664 2239
402209ff
JH
2240 return 1;
2241 }
46fac664 2242
402209ff 2243 /* A CLOBBER of a pseudo-register that is dead serves no purpose. That
a6abdce3
RH
2244 is not necessarily true for hard registers until after reload. */
2245 else if (code == CLOBBER)
2246 {
f8cfc6aa 2247 if (REG_P (XEXP (x, 0))
a6abdce3
RH
2248 && (REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER
2249 || reload_completed)
2250 && ! REGNO_REG_SET_P (pbi->reg_live, REGNO (XEXP (x, 0))))
2251 return 1;
2252 }
2253
2254 /* ??? A base USE is a historical relic. It ought not be needed anymore.
2255 Instances where it is still used are either (1) temporary and the USE
2256 escaped the pass, (2) cruft and the USE need not be emitted anymore,
2257 or (3) hiding bugs elsewhere that are not properly representing data
2258 flow. */
2259
402209ff
JH
2260 return 0;
2261}
46fac664 2262
402209ff
JH
2263/* If INSN is the last insn in a libcall, and assuming INSN is dead,
2264 return 1 if the entire library call is dead.
2265 This is true if INSN copies a register (hard or pseudo)
2266 and if the hard return reg of the call insn is dead.
2267 (The caller should have tested the destination of the SET inside
2268 INSN already for death.)
46fac664 2269
402209ff
JH
2270 If this insn doesn't just copy a register, then we don't
2271 have an ordinary libcall. In that case, cse could not have
2272 managed to substitute the source for the dest later on,
2273 so we can assume the libcall is dead.
46fac664 2274
402209ff
JH
2275 PBI is the block info giving pseudoregs live before this insn.
2276 NOTE is the REG_RETVAL note of the insn. */
46fac664 2277
402209ff 2278static int
6cf9ac28 2279libcall_dead_p (struct propagate_block_info *pbi, rtx note, rtx insn)
402209ff
JH
2280{
2281 rtx x = single_set (insn);
46fac664 2282
402209ff
JH
2283 if (x)
2284 {
b3694847 2285 rtx r = SET_SRC (x);
46fac664 2286
b77302be 2287 if (REG_P (r) || GET_CODE (r) == SUBREG)
402209ff
JH
2288 {
2289 rtx call = XEXP (note, 0);
2290 rtx call_pat;
b3694847 2291 int i;
46fac664 2292
402209ff 2293 /* Find the call insn. */
4b4bf941 2294 while (call != insn && !CALL_P (call))
402209ff 2295 call = NEXT_INSN (call);
46fac664 2296
402209ff
JH
2297 /* If there is none, do nothing special,
2298 since ordinary death handling can understand these insns. */
2299 if (call == insn)
2300 return 0;
b02eea61 2301
402209ff
JH
2302 /* See if the hard reg holding the value is dead.
2303 If this is a PARALLEL, find the call within it. */
2304 call_pat = PATTERN (call);
2305 if (GET_CODE (call_pat) == PARALLEL)
46fac664 2306 {
402209ff
JH
2307 for (i = XVECLEN (call_pat, 0) - 1; i >= 0; i--)
2308 if (GET_CODE (XVECEXP (call_pat, 0, i)) == SET
2309 && GET_CODE (SET_SRC (XVECEXP (call_pat, 0, i))) == CALL)
2310 break;
2311
2312 /* This may be a library call that is returning a value
2313 via invisible pointer. Do nothing special, since
2314 ordinary death handling can understand these insns. */
2315 if (i < 0)
2316 return 0;
2317
2318 call_pat = XVECEXP (call_pat, 0, i);
46fac664 2319 }
46fac664 2320
b77302be
JJ
2321 if (! insn_dead_p (pbi, call_pat, 1, REG_NOTES (call)))
2322 return 0;
2323
2324 while ((insn = PREV_INSN (insn)) != call)
2325 {
2326 if (! INSN_P (insn))
2327 continue;
2328 if (! insn_dead_p (pbi, PATTERN (insn), 0, REG_NOTES (insn)))
2329 return 0;
2330 }
2331 return 1;
46fac664 2332 }
46fac664 2333 }
b77302be 2334 return 0;
402209ff 2335}
46fac664 2336
402209ff
JH
2337/* 1 if register REGNO was alive at a place where `setjmp' was called
2338 and was set more than once or is an argument.
2339 Such regs may be clobbered by `longjmp'. */
b02eea61 2340
402209ff 2341int
6cf9ac28 2342regno_clobbered_at_setjmp (int regno)
402209ff 2343{
0b17ab2f 2344 if (n_basic_blocks == 0)
402209ff
JH
2345 return 0;
2346
2347 return ((REG_N_SETS (regno) > 1
cdd1f01b 2348 || REGNO_REG_SET_P (ENTRY_BLOCK_PTR->global_live_at_end, regno))
402209ff
JH
2349 && REGNO_REG_SET_P (regs_live_at_setjmp, regno));
2350}
2351\f
2352/* Add MEM to PBI->MEM_SET_LIST. MEM should be canonical. Respect the
2353 maximal list size; look for overlaps in mode and select the largest. */
2354static void
6cf9ac28 2355add_to_mem_set_list (struct propagate_block_info *pbi, rtx mem)
46fac664 2356{
402209ff
JH
2357 rtx i;
2358
2359 /* We don't know how large a BLKmode store is, so we must not
2360 take them into consideration. */
2361 if (GET_MODE (mem) == BLKmode)
2362 return;
2363
2364 for (i = pbi->mem_set_list; i ; i = XEXP (i, 1))
46fac664 2365 {
402209ff
JH
2366 rtx e = XEXP (i, 0);
2367 if (rtx_equal_p (XEXP (mem, 0), XEXP (e, 0)))
46fac664 2368 {
402209ff 2369 if (GET_MODE_SIZE (GET_MODE (mem)) > GET_MODE_SIZE (GET_MODE (e)))
b02eea61 2370 {
402209ff
JH
2371#ifdef AUTO_INC_DEC
2372 /* If we must store a copy of the mem, we can just modify
2373 the mode of the stored copy. */
2374 if (pbi->flags & PROP_AUTOINC)
2375 PUT_MODE (e, GET_MODE (mem));
2376 else
2377#endif
2378 XEXP (i, 0) = mem;
b02eea61 2379 }
402209ff 2380 return;
46fac664 2381 }
46fac664 2382 }
b02eea61 2383
402209ff
JH
2384 if (pbi->mem_set_list_len < MAX_MEM_SET_LIST_LEN)
2385 {
2386#ifdef AUTO_INC_DEC
2387 /* Store a copy of mem, otherwise the address may be
2388 scrogged by find_auto_inc. */
2389 if (pbi->flags & PROP_AUTOINC)
2390 mem = shallow_copy_rtx (mem);
2391#endif
2392 pbi->mem_set_list = alloc_EXPR_LIST (0, mem, pbi->mem_set_list);
2393 pbi->mem_set_list_len++;
2394 }
46fac664
JH
2395}
2396
402209ff
JH
2397/* INSN references memory, possibly using autoincrement addressing modes.
2398 Find any entries on the mem_set_list that need to be invalidated due
2399 to an address change. */
b02eea61 2400
fe4b3c79 2401static int
6cf9ac28 2402invalidate_mems_from_autoinc (rtx *px, void *data)
46fac664 2403{
fe4b3c79
JL
2404 rtx x = *px;
2405 struct propagate_block_info *pbi = data;
2406
ec8e098d 2407 if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
fe4b3c79
JL
2408 {
2409 invalidate_mems_from_set (pbi, XEXP (x, 0));
2410 return -1;
2411 }
2412
2413 return 0;
402209ff 2414}
46fac664 2415
ff7cc307 2416/* EXP is a REG. Remove any dependent entries from pbi->mem_set_list. */
46fac664 2417
402209ff 2418static void
6cf9ac28 2419invalidate_mems_from_set (struct propagate_block_info *pbi, rtx exp)
402209ff
JH
2420{
2421 rtx temp = pbi->mem_set_list;
2422 rtx prev = NULL_RTX;
2423 rtx next;
46fac664 2424
402209ff 2425 while (temp)
46fac664 2426 {
402209ff
JH
2427 next = XEXP (temp, 1);
2428 if (reg_overlap_mentioned_p (exp, XEXP (temp, 0)))
46fac664 2429 {
402209ff
JH
2430 /* Splice this entry out of the list. */
2431 if (prev)
2432 XEXP (prev, 1) = next;
2433 else
2434 pbi->mem_set_list = next;
2435 free_EXPR_LIST_node (temp);
2436 pbi->mem_set_list_len--;
46fac664 2437 }
46fac664 2438 else
402209ff
JH
2439 prev = temp;
2440 temp = next;
46fac664 2441 }
402209ff 2442}
46fac664 2443
402209ff
JH
2444/* Process the registers that are set within X. Their bits are set to
2445 1 in the regset DEAD, because they are dead prior to this insn.
b02eea61 2446
402209ff 2447 If INSN is nonzero, it is the insn being processed.
46fac664 2448
402209ff 2449 FLAGS is the set of operations to perform. */
b02eea61 2450
402209ff 2451static void
6cf9ac28 2452mark_set_regs (struct propagate_block_info *pbi, rtx x, rtx insn)
46fac664 2453{
402209ff
JH
2454 rtx cond = NULL_RTX;
2455 rtx link;
2456 enum rtx_code code;
df2ef49b 2457 int flags = pbi->flags;
46fac664 2458
402209ff
JH
2459 if (insn)
2460 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2461 {
2462 if (REG_NOTE_KIND (link) == REG_INC)
2463 mark_set_1 (pbi, SET, XEXP (link, 0),
2464 (GET_CODE (x) == COND_EXEC
2465 ? COND_EXEC_TEST (x) : NULL_RTX),
df2ef49b 2466 insn, flags);
402209ff
JH
2467 }
2468 retry:
2469 switch (code = GET_CODE (x))
46fac664 2470 {
402209ff 2471 case SET:
df2ef49b
AM
2472 if (GET_CODE (XEXP (x, 1)) == ASM_OPERANDS)
2473 flags |= PROP_ASM_SCAN;
ba228239 2474 /* Fall through */
402209ff 2475 case CLOBBER:
df2ef49b 2476 mark_set_1 (pbi, code, SET_DEST (x), cond, insn, flags);
402209ff 2477 return;
b02eea61 2478
402209ff
JH
2479 case COND_EXEC:
2480 cond = COND_EXEC_TEST (x);
2481 x = COND_EXEC_CODE (x);
2482 goto retry;
b02eea61 2483
402209ff
JH
2484 case PARALLEL:
2485 {
b3694847
SS
2486 int i;
2487
a06f01ba
JW
2488 /* We must scan forwards. If we have an asm, we need to set
2489 the PROP_ASM_SCAN flag before scanning the clobbers. */
2490 for (i = 0; i < XVECLEN (x, 0); i++)
402209ff
JH
2491 {
2492 rtx sub = XVECEXP (x, 0, i);
2493 switch (code = GET_CODE (sub))
2494 {
2495 case COND_EXEC:
0bccc606 2496 gcc_assert (!cond);
b02eea61 2497
402209ff
JH
2498 cond = COND_EXEC_TEST (sub);
2499 sub = COND_EXEC_CODE (sub);
df2ef49b
AM
2500 if (GET_CODE (sub) == SET)
2501 goto mark_set;
2502 if (GET_CODE (sub) == CLOBBER)
2503 goto mark_clob;
2504 break;
b02eea61 2505
402209ff 2506 case SET:
df2ef49b
AM
2507 mark_set:
2508 if (GET_CODE (XEXP (sub, 1)) == ASM_OPERANDS)
2509 flags |= PROP_ASM_SCAN;
ba228239 2510 /* Fall through */
402209ff 2511 case CLOBBER:
df2ef49b
AM
2512 mark_clob:
2513 mark_set_1 (pbi, code, SET_DEST (sub), cond, insn, flags);
402209ff 2514 break;
b02eea61 2515
a06f01ba
JW
2516 case ASM_OPERANDS:
2517 flags |= PROP_ASM_SCAN;
2518 break;
2519
402209ff
JH
2520 default:
2521 break;
2522 }
2523 }
2524 break;
2525 }
b02eea61 2526
402209ff
JH
2527 default:
2528 break;
46fac664 2529 }
46fac664
JH
2530}
2531
402209ff
JH
2532/* Process a single set, which appears in INSN. REG (which may not
2533 actually be a REG, it may also be a SUBREG, PARALLEL, etc.) is
2534 being set using the CODE (which may be SET, CLOBBER, or COND_EXEC).
2535 If the set is conditional (because it appear in a COND_EXEC), COND
2536 will be the condition. */
7a442791 2537
402209ff 2538static void
6cf9ac28 2539mark_set_1 (struct propagate_block_info *pbi, enum rtx_code code, rtx reg, rtx cond, rtx insn, int flags)
336a6399 2540{
402209ff
JH
2541 int regno_first = -1, regno_last = -1;
2542 unsigned long not_dead = 0;
336a6399
RH
2543 int i;
2544
402209ff
JH
2545 /* Modifying just one hardware register of a multi-reg value or just a
2546 byte field of a register does not mean the value from before this insn
2547 is now dead. Of course, if it was dead after it's unused now. */
336a6399 2548
402209ff 2549 switch (GET_CODE (reg))
336a6399 2550 {
402209ff
JH
2551 case PARALLEL:
2552 /* Some targets place small structures in registers for return values of
2553 functions. We have to detect this case specially here to get correct
2554 flow information. */
2555 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2556 if (XEXP (XVECEXP (reg, 0, i), 0) != 0)
2557 mark_set_1 (pbi, code, XEXP (XVECEXP (reg, 0, i), 0), cond, insn,
2558 flags);
2559 return;
2560
402209ff 2561 case SIGN_EXTRACT:
46d096a3
SB
2562 /* SIGN_EXTRACT cannot be an lvalue. */
2563 gcc_unreachable ();
2564
2565 case ZERO_EXTRACT:
402209ff
JH
2566 case STRICT_LOW_PART:
2567 /* ??? Assumes STRICT_LOW_PART not used on multi-word registers. */
2568 do
2569 reg = XEXP (reg, 0);
2570 while (GET_CODE (reg) == SUBREG
2571 || GET_CODE (reg) == ZERO_EXTRACT
402209ff 2572 || GET_CODE (reg) == STRICT_LOW_PART);
3c0cb5de 2573 if (MEM_P (reg))
402209ff
JH
2574 break;
2575 not_dead = (unsigned long) REGNO_REG_SET_P (pbi->reg_live, REGNO (reg));
2576 /* Fall through. */
b02eea61 2577
402209ff
JH
2578 case REG:
2579 regno_last = regno_first = REGNO (reg);
2580 if (regno_first < FIRST_PSEUDO_REGISTER)
66fd46b6 2581 regno_last += hard_regno_nregs[regno_first][GET_MODE (reg)] - 1;
402209ff 2582 break;
b02eea61 2583
402209ff 2584 case SUBREG:
f8cfc6aa 2585 if (REG_P (SUBREG_REG (reg)))
7a442791 2586 {
402209ff
JH
2587 enum machine_mode outer_mode = GET_MODE (reg);
2588 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (reg));
7a442791 2589
402209ff
JH
2590 /* Identify the range of registers affected. This is moderately
2591 tricky for hard registers. See alter_subreg. */
b02eea61 2592
402209ff
JH
2593 regno_last = regno_first = REGNO (SUBREG_REG (reg));
2594 if (regno_first < FIRST_PSEUDO_REGISTER)
4793dca1 2595 {
402209ff
JH
2596 regno_first += subreg_regno_offset (regno_first, inner_mode,
2597 SUBREG_BYTE (reg),
2598 outer_mode);
2599 regno_last = (regno_first
66fd46b6 2600 + hard_regno_nregs[regno_first][outer_mode] - 1);
3e28fe44 2601
402209ff
JH
2602 /* Since we've just adjusted the register number ranges, make
2603 sure REG matches. Otherwise some_was_live will be clear
2604 when it shouldn't have been, and we'll create incorrect
2605 REG_UNUSED notes. */
2606 reg = gen_rtx_REG (outer_mode, regno_first);
62828c00 2607 }
402209ff 2608 else
d3a923ee 2609 {
402209ff
JH
2610 /* If the number of words in the subreg is less than the number
2611 of words in the full register, we have a well-defined partial
2612 set. Otherwise the high bits are undefined.
d3a923ee 2613
402209ff
JH
2614 This is only really applicable to pseudos, since we just took
2615 care of multi-word hard registers. */
2616 if (((GET_MODE_SIZE (outer_mode)
2617 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2618 < ((GET_MODE_SIZE (inner_mode)
2619 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
2620 not_dead = (unsigned long) REGNO_REG_SET_P (pbi->reg_live,
2621 regno_first);
d3a923ee 2622
402209ff 2623 reg = SUBREG_REG (reg);
d3a923ee 2624 }
d3a923ee 2625 }
402209ff
JH
2626 else
2627 reg = SUBREG_REG (reg);
2628 break;
c586192c 2629
402209ff
JH
2630 default:
2631 break;
c586192c 2632 }
c586192c 2633
402209ff
JH
2634 /* If this set is a MEM, then it kills any aliased writes.
2635 If this set is a REG, then it kills any MEMs which use the reg. */
5149f070 2636 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
e881bb1b 2637 {
f8cfc6aa 2638 if (REG_P (reg))
402209ff 2639 invalidate_mems_from_set (pbi, reg);
e881bb1b 2640
402209ff 2641 /* If the memory reference had embedded side effects (autoincrement
d67fb775 2642 address modes) then we may need to kill some entries on the
402209ff 2643 memory set list. */
3c0cb5de 2644 if (insn && MEM_P (reg))
fe4b3c79 2645 for_each_rtx (&PATTERN (insn), invalidate_mems_from_autoinc, pbi);
ccbaf064 2646
3c0cb5de 2647 if (MEM_P (reg) && ! side_effects_p (reg)
402209ff 2648 /* ??? With more effort we could track conditional memory life. */
fe4b3c79 2649 && ! cond)
dd3f0101 2650 add_to_mem_set_list (pbi, canon_rtx (reg));
ccbaf064 2651 }
f2a1bc02 2652
f8cfc6aa 2653 if (REG_P (reg)
402209ff
JH
2654 && ! (regno_first == FRAME_POINTER_REGNUM
2655 && (! reload_completed || frame_pointer_needed))
2656#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2657 && ! (regno_first == HARD_FRAME_POINTER_REGNUM
2658 && (! reload_completed || frame_pointer_needed))
2659#endif
2660#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2661 && ! (regno_first == ARG_POINTER_REGNUM && fixed_regs[regno_first])
2662#endif
2663 )
f2a1bc02 2664 {
402209ff 2665 int some_was_live = 0, some_was_dead = 0;
f2a1bc02 2666
402209ff 2667 for (i = regno_first; i <= regno_last; ++i)
f2a1bc02 2668 {
402209ff
JH
2669 int needed_regno = REGNO_REG_SET_P (pbi->reg_live, i);
2670 if (pbi->local_set)
f2a1bc02 2671 {
402209ff
JH
2672 /* Order of the set operation matters here since both
2673 sets may be the same. */
2674 CLEAR_REGNO_REG_SET (pbi->cond_local_set, i);
2675 if (cond != NULL_RTX
2676 && ! REGNO_REG_SET_P (pbi->local_set, i))
2677 SET_REGNO_REG_SET (pbi->cond_local_set, i);
2678 else
2679 SET_REGNO_REG_SET (pbi->local_set, i);
f2a1bc02 2680 }
402209ff
JH
2681 if (code != CLOBBER)
2682 SET_REGNO_REG_SET (pbi->new_set, i);
d3a923ee 2683
402209ff
JH
2684 some_was_live |= needed_regno;
2685 some_was_dead |= ! needed_regno;
f2a1bc02 2686 }
402209ff
JH
2687
2688#ifdef HAVE_conditional_execution
2689 /* Consider conditional death in deciding that the register needs
2690 a death note. */
2691 if (some_was_live && ! not_dead
2692 /* The stack pointer is never dead. Well, not strictly true,
2693 but it's very difficult to tell from here. Hopefully
2694 combine_stack_adjustments will fix up the most egregious
2695 errors. */
2696 && regno_first != STACK_POINTER_REGNUM)
d3a923ee 2697 {
402209ff
JH
2698 for (i = regno_first; i <= regno_last; ++i)
2699 if (! mark_regno_cond_dead (pbi, i, cond))
2700 not_dead |= ((unsigned long) 1) << (i - regno_first);
d3a923ee 2701 }
402209ff 2702#endif
6ff71a97 2703
402209ff
JH
2704 /* Additional data to record if this is the final pass. */
2705 if (flags & (PROP_LOG_LINKS | PROP_REG_INFO
2706 | PROP_DEATH_NOTES | PROP_AUTOINC))
f2a1bc02 2707 {
b3694847 2708 rtx y;
0b17ab2f 2709 int blocknum = pbi->bb->index;
402209ff
JH
2710
2711 y = NULL_RTX;
2712 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
ca9fef16 2713 {
402209ff 2714 y = pbi->reg_next_use[regno_first];
ca9fef16 2715
402209ff
JH
2716 /* The next use is no longer next, since a store intervenes. */
2717 for (i = regno_first; i <= regno_last; ++i)
2718 pbi->reg_next_use[i] = 0;
2719 }
6e64a52a 2720
402209ff 2721 if (flags & PROP_REG_INFO)
46fac664 2722 {
402209ff
JH
2723 for (i = regno_first; i <= regno_last; ++i)
2724 {
2725 /* Count (weighted) references, stores, etc. This counts a
2726 register twice if it is modified, but that is correct. */
2727 REG_N_SETS (i) += 1;
2728 REG_N_REFS (i) += 1;
2729 REG_FREQ (i) += REG_FREQ_FROM_BB (pbi->bb);
2730
2731 /* The insns where a reg is live are normally counted
2732 elsewhere, but we want the count to include the insn
2733 where the reg is set, and the normal counting mechanism
2734 would not count it. */
2735 REG_LIVE_LENGTH (i) += 1;
2736 }
2737
2738 /* If this is a hard reg, record this function uses the reg. */
2739 if (regno_first < FIRST_PSEUDO_REGISTER)
6e64a52a 2740 {
402209ff
JH
2741 for (i = regno_first; i <= regno_last; i++)
2742 regs_ever_live[i] = 1;
df2ef49b
AM
2743 if (flags & PROP_ASM_SCAN)
2744 for (i = regno_first; i <= regno_last; i++)
2745 regs_asm_clobbered[i] = 1;
6e64a52a
JH
2746 }
2747 else
6e64a52a 2748 {
402209ff
JH
2749 /* Keep track of which basic blocks each reg appears in. */
2750 if (REG_BASIC_BLOCK (regno_first) == REG_BLOCK_UNKNOWN)
2751 REG_BASIC_BLOCK (regno_first) = blocknum;
2752 else if (REG_BASIC_BLOCK (regno_first) != blocknum)
2753 REG_BASIC_BLOCK (regno_first) = REG_BLOCK_GLOBAL;
6e64a52a 2754 }
402209ff 2755 }
f2a1bc02 2756
402209ff 2757 if (! some_was_dead)
f2a1bc02 2758 {
402209ff
JH
2759 if (flags & PROP_LOG_LINKS)
2760 {
2761 /* Make a logical link from the next following insn
2762 that uses this register, back to this insn.
2763 The following insns have already been processed.
2764
2765 We don't build a LOG_LINK for hard registers containing
2766 in ASM_OPERANDs. If these registers get replaced,
2767 we might wind up changing the semantics of the insn,
2768 even if reload can make what appear to be valid
a10016d3
ILT
2769 assignments later.
2770
2771 We don't build a LOG_LINK for global registers to
2772 or from a function call. We don't want to let
2773 combine think that it knows what is going on with
2774 global registers. */
402209ff
JH
2775 if (y && (BLOCK_NUM (y) == blocknum)
2776 && (regno_first >= FIRST_PSEUDO_REGISTER
a10016d3 2777 || (asm_noperands (PATTERN (y)) < 0
4b4bf941
JQ
2778 && ! ((CALL_P (insn)
2779 || CALL_P (y))
a10016d3 2780 && global_regs[regno_first]))))
402209ff
JH
2781 LOG_LINKS (y) = alloc_INSN_LIST (insn, LOG_LINKS (y));
2782 }
34487bf8 2783 }
402209ff
JH
2784 else if (not_dead)
2785 ;
2786 else if (! some_was_live)
2787 {
2788 if (flags & PROP_REG_INFO)
2789 REG_N_DEATHS (regno_first) += 1;
34487bf8 2790
402209ff
JH
2791 if (flags & PROP_DEATH_NOTES)
2792 {
2793 /* Note that dead stores have already been deleted
2794 when possible. If we get here, we have found a
2795 dead store that cannot be eliminated (because the
2796 same insn does something useful). Indicate this
2797 by marking the reg being set as dying here. */
2798 REG_NOTES (insn)
2799 = alloc_EXPR_LIST (REG_UNUSED, reg, REG_NOTES (insn));
2800 }
2801 }
2802 else
34487bf8 2803 {
402209ff
JH
2804 if (flags & PROP_DEATH_NOTES)
2805 {
2806 /* This is a case where we have a multi-word hard register
2807 and some, but not all, of the words of the register are
2808 needed in subsequent insns. Write REG_UNUSED notes
2809 for those parts that were not needed. This case should
2810 be rare. */
2811
2812 for (i = regno_first; i <= regno_last; ++i)
2813 if (! REGNO_REG_SET_P (pbi->reg_live, i))
2814 REG_NOTES (insn)
2815 = alloc_EXPR_LIST (REG_UNUSED,
e50126e8 2816 regno_reg_rtx[i],
402209ff
JH
2817 REG_NOTES (insn));
2818 }
34487bf8 2819 }
34487bf8 2820 }
402209ff
JH
2821
2822 /* Mark the register as being dead. */
2823 if (some_was_live
2824 /* The stack pointer is never dead. Well, not strictly true,
2825 but it's very difficult to tell from here. Hopefully
2826 combine_stack_adjustments will fix up the most egregious
2827 errors. */
2828 && regno_first != STACK_POINTER_REGNUM)
34487bf8 2829 {
402209ff
JH
2830 for (i = regno_first; i <= regno_last; ++i)
2831 if (!(not_dead & (((unsigned long) 1) << (i - regno_first))))
736b64dd
JH
2832 {
2833 if ((pbi->flags & PROP_REG_INFO)
2834 && REGNO_REG_SET_P (pbi->reg_live, i))
2835 {
2836 REG_LIVE_LENGTH (i) += pbi->insn_num - reg_deaths[i];
2837 reg_deaths[i] = 0;
2838 }
2839 CLEAR_REGNO_REG_SET (pbi->reg_live, i);
2840 }
34487bf8 2841 }
402209ff 2842 }
f8cfc6aa 2843 else if (REG_P (reg))
402209ff
JH
2844 {
2845 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
2846 pbi->reg_next_use[regno_first] = 0;
df2ef49b
AM
2847
2848 if ((flags & PROP_REG_INFO) != 0
2849 && (flags & PROP_ASM_SCAN) != 0
2850 && regno_first < FIRST_PSEUDO_REGISTER)
2851 {
2852 for (i = regno_first; i <= regno_last; i++)
2853 regs_asm_clobbered[i] = 1;
2854 }
402209ff
JH
2855 }
2856
2857 /* If this is the last pass and this is a SCRATCH, show it will be dying
2858 here and count it. */
2859 else if (GET_CODE (reg) == SCRATCH)
2860 {
2861 if (flags & PROP_DEATH_NOTES)
2862 REG_NOTES (insn)
2863 = alloc_EXPR_LIST (REG_UNUSED, reg, REG_NOTES (insn));
2864 }
2865}
2866\f
2867#ifdef HAVE_conditional_execution
2868/* Mark REGNO conditionally dead.
2869 Return true if the register is now unconditionally dead. */
2870
2871static int
6cf9ac28 2872mark_regno_cond_dead (struct propagate_block_info *pbi, int regno, rtx cond)
402209ff
JH
2873{
2874 /* If this is a store to a predicate register, the value of the
2875 predicate is changing, we don't know that the predicate as seen
2876 before is the same as that seen after. Flush all dependent
2877 conditions from reg_cond_dead. This will make all such
2878 conditionally live registers unconditionally live. */
2879 if (REGNO_REG_SET_P (pbi->reg_cond_reg, regno))
2880 flush_reg_cond_reg (pbi, regno);
2881
2882 /* If this is an unconditional store, remove any conditional
2883 life that may have existed. */
2884 if (cond == NULL_RTX)
2885 splay_tree_remove (pbi->reg_cond_dead, regno);
2886 else
2887 {
2888 splay_tree_node node;
2889 struct reg_cond_life_info *rcli;
2890 rtx ncond;
2891
2892 /* Otherwise this is a conditional set. Record that fact.
2893 It may have been conditionally used, or there may be a
647eea9d 2894 subsequent set with a complementary condition. */
34487bf8 2895
402209ff
JH
2896 node = splay_tree_lookup (pbi->reg_cond_dead, regno);
2897 if (node == NULL)
34487bf8 2898 {
402209ff
JH
2899 /* The register was unconditionally live previously.
2900 Record the current condition as the condition under
2901 which it is dead. */
703ad42b 2902 rcli = xmalloc (sizeof (*rcli));
402209ff
JH
2903 rcli->condition = cond;
2904 rcli->stores = cond;
2905 rcli->orig_condition = const0_rtx;
2906 splay_tree_insert (pbi->reg_cond_dead, regno,
2907 (splay_tree_value) rcli);
2908
2909 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
2910
d6a7951f 2911 /* Not unconditionally dead. */
402209ff 2912 return 0;
34487bf8
RH
2913 }
2914 else
2915 {
402209ff
JH
2916 /* The register was conditionally live previously.
2917 Add the new condition to the old. */
2918 rcli = (struct reg_cond_life_info *) node->value;
2919 ncond = rcli->condition;
2920 ncond = ior_reg_cond (ncond, cond, 1);
2921 if (rcli->stores == const0_rtx)
2922 rcli->stores = cond;
2923 else if (rcli->stores != const1_rtx)
2924 rcli->stores = ior_reg_cond (rcli->stores, cond, 1);
34487bf8 2925
402209ff
JH
2926 /* If the register is now unconditionally dead, remove the entry
2927 in the splay_tree. A register is unconditionally dead if the
2928 dead condition ncond is true. A register is also unconditionally
2929 dead if the sum of all conditional stores is an unconditional
2930 store (stores is true), and the dead condition is identically the
2931 same as the original dead condition initialized at the end of
2932 the block. This is a pointer compare, not an rtx_equal_p
2933 compare. */
2934 if (ncond == const1_rtx
2935 || (ncond == rcli->orig_condition && rcli->stores == const1_rtx))
2936 splay_tree_remove (pbi->reg_cond_dead, regno);
2937 else
2938 {
2939 rcli->condition = ncond;
34487bf8 2940
402209ff 2941 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
34487bf8 2942
d6a7951f 2943 /* Not unconditionally dead. */
402209ff 2944 return 0;
34487bf8
RH
2945 }
2946 }
2947 }
2948
402209ff
JH
2949 return 1;
2950}
bce7bfe8 2951
402209ff 2952/* Called from splay_tree_delete for pbi->reg_cond_life. */
b9f22704 2953
402209ff 2954static void
6cf9ac28 2955free_reg_cond_life_info (splay_tree_value value)
402209ff
JH
2956{
2957 struct reg_cond_life_info *rcli = (struct reg_cond_life_info *) value;
2958 free (rcli);
2959}
18ca529b 2960
402209ff 2961/* Helper function for flush_reg_cond_reg. */
34487bf8 2962
402209ff 2963static int
6cf9ac28 2964flush_reg_cond_reg_1 (splay_tree_node node, void *data)
402209ff
JH
2965{
2966 struct reg_cond_life_info *rcli;
2967 int *xdata = (int *) data;
2968 unsigned int regno = xdata[0];
34487bf8 2969
402209ff
JH
2970 /* Don't need to search if last flushed value was farther on in
2971 the in-order traversal. */
2972 if (xdata[1] >= (int) node->key)
2973 return 0;
34487bf8 2974
402209ff
JH
2975 /* Splice out portions of the expression that refer to regno. */
2976 rcli = (struct reg_cond_life_info *) node->value;
2977 rcli->condition = elim_reg_cond (rcli->condition, regno);
2978 if (rcli->stores != const0_rtx && rcli->stores != const1_rtx)
2979 rcli->stores = elim_reg_cond (rcli->stores, regno);
0edd203b 2980
402209ff
JH
2981 /* If the entire condition is now false, signal the node to be removed. */
2982 if (rcli->condition == const0_rtx)
2983 {
2984 xdata[1] = node->key;
2985 return -1;
34487bf8 2986 }
0bccc606
NS
2987 else
2988 gcc_assert (rcli->condition != const1_rtx);
d3a923ee 2989
402209ff 2990 return 0;
34487bf8 2991}
410538ea 2992
402209ff 2993/* Flush all (sub) expressions referring to REGNO from REG_COND_LIVE. */
410538ea 2994
402209ff 2995static void
6cf9ac28 2996flush_reg_cond_reg (struct propagate_block_info *pbi, int regno)
402209ff
JH
2997{
2998 int pair[2];
410538ea 2999
402209ff
JH
3000 pair[0] = regno;
3001 pair[1] = -1;
3002 while (splay_tree_foreach (pbi->reg_cond_dead,
3003 flush_reg_cond_reg_1, pair) == -1)
3004 splay_tree_remove (pbi->reg_cond_dead, pair[1]);
410538ea 3005
402209ff
JH
3006 CLEAR_REGNO_REG_SET (pbi->reg_cond_reg, regno);
3007}
410538ea 3008
402209ff
JH
3009/* Logical arithmetic on predicate conditions. IOR, NOT and AND.
3010 For ior/and, the ADD flag determines whether we want to add the new
3011 condition X to the old one unconditionally. If it is zero, we will
3012 only return a new expression if X allows us to simplify part of
b318748f 3013 OLD, otherwise we return NULL to the caller.
402209ff
JH
3014 If ADD is nonzero, we will return a new condition in all cases. The
3015 toplevel caller of one of these functions should always pass 1 for
3016 ADD. */
410538ea 3017
402209ff 3018static rtx
6cf9ac28 3019ior_reg_cond (rtx old, rtx x, int add)
402209ff
JH
3020{
3021 rtx op0, op1;
410538ea 3022
ec8e098d 3023 if (COMPARISON_P (old))
410538ea 3024 {
33e6a97a 3025 if (COMPARISON_P (x)
15dce812 3026 && REVERSE_CONDEXEC_PREDICATES_P (x, old)
402209ff
JH
3027 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3028 return const1_rtx;
3029 if (GET_CODE (x) == GET_CODE (old)
3030 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3031 return old;
3032 if (! add)
b318748f 3033 return NULL;
402209ff 3034 return gen_rtx_IOR (0, old, x);
410538ea 3035 }
c9bacfdb 3036
402209ff 3037 switch (GET_CODE (old))
410538ea 3038 {
402209ff
JH
3039 case IOR:
3040 op0 = ior_reg_cond (XEXP (old, 0), x, 0);
3041 op1 = ior_reg_cond (XEXP (old, 1), x, 0);
b318748f 3042 if (op0 != NULL || op1 != NULL)
402209ff
JH
3043 {
3044 if (op0 == const0_rtx)
b318748f 3045 return op1 ? op1 : gen_rtx_IOR (0, XEXP (old, 1), x);
402209ff 3046 if (op1 == const0_rtx)
b318748f 3047 return op0 ? op0 : gen_rtx_IOR (0, XEXP (old, 0), x);
402209ff
JH
3048 if (op0 == const1_rtx || op1 == const1_rtx)
3049 return const1_rtx;
b318748f
JJ
3050 if (op0 == NULL)
3051 op0 = gen_rtx_IOR (0, XEXP (old, 0), x);
3052 else if (rtx_equal_p (x, op0))
3053 /* (x | A) | x ~ (x | A). */
3054 return old;
3055 if (op1 == NULL)
3056 op1 = gen_rtx_IOR (0, XEXP (old, 1), x);
3057 else if (rtx_equal_p (x, op1))
3058 /* (A | x) | x ~ (A | x). */
3059 return old;
402209ff
JH
3060 return gen_rtx_IOR (0, op0, op1);
3061 }
3062 if (! add)
b318748f 3063 return NULL;
402209ff 3064 return gen_rtx_IOR (0, old, x);
410538ea 3065
402209ff
JH
3066 case AND:
3067 op0 = ior_reg_cond (XEXP (old, 0), x, 0);
3068 op1 = ior_reg_cond (XEXP (old, 1), x, 0);
b318748f 3069 if (op0 != NULL || op1 != NULL)
410538ea 3070 {
402209ff 3071 if (op0 == const1_rtx)
b318748f 3072 return op1 ? op1 : gen_rtx_IOR (0, XEXP (old, 1), x);
402209ff 3073 if (op1 == const1_rtx)
b318748f 3074 return op0 ? op0 : gen_rtx_IOR (0, XEXP (old, 0), x);
402209ff
JH
3075 if (op0 == const0_rtx || op1 == const0_rtx)
3076 return const0_rtx;
b318748f
JJ
3077 if (op0 == NULL)
3078 op0 = gen_rtx_IOR (0, XEXP (old, 0), x);
3079 else if (rtx_equal_p (x, op0))
3080 /* (x & A) | x ~ x. */
3081 return op0;
3082 if (op1 == NULL)
3083 op1 = gen_rtx_IOR (0, XEXP (old, 1), x);
3084 else if (rtx_equal_p (x, op1))
3085 /* (A & x) | x ~ x. */
3086 return op1;
402209ff 3087 return gen_rtx_AND (0, op0, op1);
410538ea 3088 }
402209ff 3089 if (! add)
b318748f 3090 return NULL;
402209ff 3091 return gen_rtx_IOR (0, old, x);
410538ea 3092
402209ff
JH
3093 case NOT:
3094 op0 = and_reg_cond (XEXP (old, 0), not_reg_cond (x), 0);
b318748f 3095 if (op0 != NULL)
402209ff
JH
3096 return not_reg_cond (op0);
3097 if (! add)
b318748f 3098 return NULL;
402209ff 3099 return gen_rtx_IOR (0, old, x);
c9bacfdb 3100
402209ff 3101 default:
0bccc606 3102 gcc_unreachable ();
410538ea
AM
3103 }
3104}
3105
402209ff 3106static rtx
6cf9ac28 3107not_reg_cond (rtx x)
410538ea 3108{
402209ff
JH
3109 if (x == const0_rtx)
3110 return const1_rtx;
3111 else if (x == const1_rtx)
3112 return const0_rtx;
15dce812 3113 if (GET_CODE (x) == NOT)
402209ff 3114 return XEXP (x, 0);
ec8e098d 3115 if (COMPARISON_P (x)
f8cfc6aa 3116 && REG_P (XEXP (x, 0)))
410538ea 3117 {
0bccc606 3118 gcc_assert (XEXP (x, 1) == const0_rtx);
410538ea 3119
15dce812 3120 return gen_rtx_fmt_ee (reversed_comparison_code (x, NULL),
402209ff 3121 VOIDmode, XEXP (x, 0), const0_rtx);
410538ea 3122 }
402209ff 3123 return gen_rtx_NOT (0, x);
410538ea
AM
3124}
3125
402209ff 3126static rtx
6cf9ac28 3127and_reg_cond (rtx old, rtx x, int add)
410538ea 3128{
402209ff 3129 rtx op0, op1;
410538ea 3130
ec8e098d 3131 if (COMPARISON_P (old))
410538ea 3132 {
33e6a97a 3133 if (COMPARISON_P (x)
15dce812 3134 && GET_CODE (x) == reversed_comparison_code (old, NULL)
402209ff
JH
3135 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3136 return const0_rtx;
3137 if (GET_CODE (x) == GET_CODE (old)
3138 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3139 return old;
3140 if (! add)
b318748f 3141 return NULL;
402209ff
JH
3142 return gen_rtx_AND (0, old, x);
3143 }
410538ea 3144
402209ff
JH
3145 switch (GET_CODE (old))
3146 {
3147 case IOR:
3148 op0 = and_reg_cond (XEXP (old, 0), x, 0);
3149 op1 = and_reg_cond (XEXP (old, 1), x, 0);
b318748f 3150 if (op0 != NULL || op1 != NULL)
410538ea 3151 {
402209ff 3152 if (op0 == const0_rtx)
b318748f 3153 return op1 ? op1 : gen_rtx_AND (0, XEXP (old, 1), x);
402209ff 3154 if (op1 == const0_rtx)
b318748f 3155 return op0 ? op0 : gen_rtx_AND (0, XEXP (old, 0), x);
402209ff
JH
3156 if (op0 == const1_rtx || op1 == const1_rtx)
3157 return const1_rtx;
b318748f
JJ
3158 if (op0 == NULL)
3159 op0 = gen_rtx_AND (0, XEXP (old, 0), x);
3160 else if (rtx_equal_p (x, op0))
3161 /* (x | A) & x ~ x. */
3162 return op0;
3163 if (op1 == NULL)
3164 op1 = gen_rtx_AND (0, XEXP (old, 1), x);
3165 else if (rtx_equal_p (x, op1))
3166 /* (A | x) & x ~ x. */
3167 return op1;
402209ff 3168 return gen_rtx_IOR (0, op0, op1);
410538ea 3169 }
402209ff 3170 if (! add)
b318748f 3171 return NULL;
402209ff
JH
3172 return gen_rtx_AND (0, old, x);
3173
3174 case AND:
3175 op0 = and_reg_cond (XEXP (old, 0), x, 0);
3176 op1 = and_reg_cond (XEXP (old, 1), x, 0);
b318748f 3177 if (op0 != NULL || op1 != NULL)
410538ea 3178 {
402209ff 3179 if (op0 == const1_rtx)
b318748f 3180 return op1 ? op1 : gen_rtx_AND (0, XEXP (old, 1), x);
402209ff 3181 if (op1 == const1_rtx)
b318748f 3182 return op0 ? op0 : gen_rtx_AND (0, XEXP (old, 0), x);
402209ff
JH
3183 if (op0 == const0_rtx || op1 == const0_rtx)
3184 return const0_rtx;
b318748f
JJ
3185 if (op0 == NULL)
3186 op0 = gen_rtx_AND (0, XEXP (old, 0), x);
3187 else if (rtx_equal_p (x, op0))
3188 /* (x & A) & x ~ (x & A). */
3189 return old;
3190 if (op1 == NULL)
3191 op1 = gen_rtx_AND (0, XEXP (old, 1), x);
3192 else if (rtx_equal_p (x, op1))
3193 /* (A & x) & x ~ (A & x). */
3194 return old;
402209ff 3195 return gen_rtx_AND (0, op0, op1);
410538ea 3196 }
402209ff 3197 if (! add)
b318748f 3198 return NULL;
402209ff 3199 return gen_rtx_AND (0, old, x);
410538ea 3200
402209ff
JH
3201 case NOT:
3202 op0 = ior_reg_cond (XEXP (old, 0), not_reg_cond (x), 0);
b318748f 3203 if (op0 != NULL)
402209ff
JH
3204 return not_reg_cond (op0);
3205 if (! add)
b318748f 3206 return NULL;
402209ff 3207 return gen_rtx_AND (0, old, x);
410538ea 3208
402209ff 3209 default:
0bccc606 3210 gcc_unreachable ();
c9bacfdb 3211 }
410538ea
AM
3212}
3213
402209ff
JH
3214/* Given a condition X, remove references to reg REGNO and return the
3215 new condition. The removal will be done so that all conditions
3216 involving REGNO are considered to evaluate to false. This function
3217 is used when the value of REGNO changes. */
c9bacfdb 3218
402209ff 3219static rtx
6cf9ac28 3220elim_reg_cond (rtx x, unsigned int regno)
410538ea 3221{
402209ff
JH
3222 rtx op0, op1;
3223
ec8e098d 3224 if (COMPARISON_P (x))
410538ea 3225 {
402209ff
JH
3226 if (REGNO (XEXP (x, 0)) == regno)
3227 return const0_rtx;
3228 return x;
410538ea 3229 }
c9bacfdb 3230
402209ff
JH
3231 switch (GET_CODE (x))
3232 {
3233 case AND:
3234 op0 = elim_reg_cond (XEXP (x, 0), regno);
3235 op1 = elim_reg_cond (XEXP (x, 1), regno);
3236 if (op0 == const0_rtx || op1 == const0_rtx)
3237 return const0_rtx;
3238 if (op0 == const1_rtx)
3239 return op1;
3240 if (op1 == const1_rtx)
3241 return op0;
3242 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
3243 return x;
3244 return gen_rtx_AND (0, op0, op1);
87fdf7ff 3245
402209ff
JH
3246 case IOR:
3247 op0 = elim_reg_cond (XEXP (x, 0), regno);
3248 op1 = elim_reg_cond (XEXP (x, 1), regno);
3249 if (op0 == const1_rtx || op1 == const1_rtx)
3250 return const1_rtx;
3251 if (op0 == const0_rtx)
3252 return op1;
3253 if (op1 == const0_rtx)
3254 return op0;
3255 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
3256 return x;
3257 return gen_rtx_IOR (0, op0, op1);
87fdf7ff 3258
402209ff
JH
3259 case NOT:
3260 op0 = elim_reg_cond (XEXP (x, 0), regno);
3261 if (op0 == const0_rtx)
3262 return const1_rtx;
3263 if (op0 == const1_rtx)
3264 return const0_rtx;
3265 if (op0 != XEXP (x, 0))
3266 return not_reg_cond (op0);
3267 return x;
87fdf7ff 3268
402209ff 3269 default:
0bccc606 3270 gcc_unreachable ();
402209ff 3271 }
87fdf7ff 3272}
402209ff
JH
3273#endif /* HAVE_conditional_execution */
3274\f
3275#ifdef AUTO_INC_DEC
87fdf7ff 3276
402209ff
JH
3277/* Try to substitute the auto-inc expression INC as the address inside
3278 MEM which occurs in INSN. Currently, the address of MEM is an expression
3279 involving INCR_REG, and INCR is the next use of INCR_REG; it is an insn
3280 that has a single set whose source is a PLUS of INCR_REG and something
3281 else. */
c9bacfdb 3282
87fdf7ff 3283static void
6cf9ac28
AJ
3284attempt_auto_inc (struct propagate_block_info *pbi, rtx inc, rtx insn,
3285 rtx mem, rtx incr, rtx incr_reg)
87fdf7ff 3286{
402209ff
JH
3287 int regno = REGNO (incr_reg);
3288 rtx set = single_set (incr);
3289 rtx q = SET_DEST (set);
3290 rtx y = SET_SRC (set);
3291 int opnum = XEXP (y, 0) == incr_reg ? 0 : 1;
0bccc606 3292 int changed;
c9bacfdb 3293
402209ff
JH
3294 /* Make sure this reg appears only once in this insn. */
3295 if (count_occurrences (PATTERN (insn), incr_reg, 1) != 1)
3296 return;
87fdf7ff 3297
402209ff
JH
3298 if (dead_or_set_p (incr, incr_reg)
3299 /* Mustn't autoinc an eliminable register. */
3300 && (regno >= FIRST_PSEUDO_REGISTER
3301 || ! TEST_HARD_REG_BIT (elim_reg_set, regno)))
3302 {
3303 /* This is the simple case. Try to make the auto-inc. If
3304 we can't, we are done. Otherwise, we will do any
3305 needed updates below. */
3306 if (! validate_change (insn, &XEXP (mem, 0), inc, 0))
3307 return;
3308 }
f8cfc6aa 3309 else if (REG_P (q)
402209ff
JH
3310 /* PREV_INSN used here to check the semi-open interval
3311 [insn,incr). */
3312 && ! reg_used_between_p (q, PREV_INSN (insn), incr)
3313 /* We must also check for sets of q as q may be
3314 a call clobbered hard register and there may
3315 be a call between PREV_INSN (insn) and incr. */
3316 && ! reg_set_between_p (q, PREV_INSN (insn), incr))
3317 {
3318 /* We have *p followed sometime later by q = p+size.
3319 Both p and q must be live afterward,
3320 and q is not used between INSN and its assignment.
3321 Change it to q = p, ...*q..., q = q+size.
3322 Then fall into the usual case. */
3323 rtx insns, temp;
d3a923ee 3324
402209ff
JH
3325 start_sequence ();
3326 emit_move_insn (q, incr_reg);
3327 insns = get_insns ();
3328 end_sequence ();
87fdf7ff 3329
402209ff
JH
3330 /* If we can't make the auto-inc, or can't make the
3331 replacement into Y, exit. There's no point in making
3332 the change below if we can't do the auto-inc and doing
3333 so is not correct in the pre-inc case. */
87fdf7ff 3334
402209ff
JH
3335 XEXP (inc, 0) = q;
3336 validate_change (insn, &XEXP (mem, 0), inc, 1);
3337 validate_change (incr, &XEXP (y, opnum), q, 1);
3338 if (! apply_change_group ())
3339 return;
f008a564 3340
402209ff
JH
3341 /* We now know we'll be doing this change, so emit the
3342 new insn(s) and do the updates. */
2f937369 3343 emit_insn_before (insns, insn);
f008a564 3344
a813c111
SB
3345 if (BB_HEAD (pbi->bb) == insn)
3346 BB_HEAD (pbi->bb) = insns;
b53978a3 3347
402209ff
JH
3348 /* INCR will become a NOTE and INSN won't contain a
3349 use of INCR_REG. If a use of INCR_REG was just placed in
3350 the insn before INSN, make that the next use.
3351 Otherwise, invalidate it. */
4b4bf941 3352 if (NONJUMP_INSN_P (PREV_INSN (insn))
402209ff
JH
3353 && GET_CODE (PATTERN (PREV_INSN (insn))) == SET
3354 && SET_SRC (PATTERN (PREV_INSN (insn))) == incr_reg)
3355 pbi->reg_next_use[regno] = PREV_INSN (insn);
3356 else
3357 pbi->reg_next_use[regno] = 0;
c9bacfdb 3358
402209ff
JH
3359 incr_reg = q;
3360 regno = REGNO (q);
b53978a3 3361
298c28a8
JH
3362 if ((pbi->flags & PROP_REG_INFO)
3363 && !REGNO_REG_SET_P (pbi->reg_live, regno))
3364 reg_deaths[regno] = pbi->insn_num;
3365
402209ff
JH
3366 /* REGNO is now used in INCR which is below INSN, but
3367 it previously wasn't live here. If we don't mark
3368 it as live, we'll put a REG_DEAD note for it
3369 on this insn, which is incorrect. */
3370 SET_REGNO_REG_SET (pbi->reg_live, regno);
b53978a3 3371
402209ff
JH
3372 /* If there are any calls between INSN and INCR, show
3373 that REGNO now crosses them. */
3374 for (temp = insn; temp != incr; temp = NEXT_INSN (temp))
4b4bf941 3375 if (CALL_P (temp))
402209ff 3376 REG_N_CALLS_CROSSED (regno)++;
c9bacfdb 3377
402209ff
JH
3378 /* Invalidate alias info for Q since we just changed its value. */
3379 clear_reg_alias_info (q);
b53978a3 3380 }
402209ff
JH
3381 else
3382 return;
b53978a3 3383
402209ff
JH
3384 /* If we haven't returned, it means we were able to make the
3385 auto-inc, so update the status. First, record that this insn
3386 has an implicit side effect. */
f008a564 3387
402209ff 3388 REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, incr_reg, REG_NOTES (insn));
f008a564 3389
402209ff
JH
3390 /* Modify the old increment-insn to simply copy
3391 the already-incremented value of our register. */
0bccc606
NS
3392 changed = validate_change (incr, &SET_SRC (set), incr_reg, 0);
3393 gcc_assert (changed);
ca9fef16 3394
402209ff
JH
3395 /* If that makes it a no-op (copying the register into itself) delete
3396 it so it won't appear to be a "use" and a "set" of this
3397 register. */
3398 if (REGNO (SET_DEST (set)) == REGNO (incr_reg))
ca9fef16 3399 {
402209ff
JH
3400 /* If the original source was dead, it's dead now. */
3401 rtx note;
ca9fef16 3402
402209ff
JH
3403 while ((note = find_reg_note (incr, REG_DEAD, NULL_RTX)) != NULL_RTX)
3404 {
3405 remove_note (incr, note);
3406 if (XEXP (note, 0) != incr_reg)
298c28a8
JH
3407 {
3408 unsigned int regno = REGNO (XEXP (note, 0));
3409
3410 if ((pbi->flags & PROP_REG_INFO)
3411 && REGNO_REG_SET_P (pbi->reg_live, regno))
3412 {
3413 REG_LIVE_LENGTH (regno) += pbi->insn_num - reg_deaths[regno];
3414 reg_deaths[regno] = 0;
3415 }
3416 CLEAR_REGNO_REG_SET (pbi->reg_live, REGNO (XEXP (note, 0)));
3417 }
402209ff 3418 }
c9bacfdb 3419
6773e15f 3420 SET_INSN_DELETED (incr);
402209ff 3421 }
f008a564 3422
402209ff
JH
3423 if (regno >= FIRST_PSEUDO_REGISTER)
3424 {
3425 /* Count an extra reference to the reg. When a reg is
3426 incremented, spilling it is worse, so we want to make
3427 that less likely. */
3428 REG_FREQ (regno) += REG_FREQ_FROM_BB (pbi->bb);
f008a564 3429
402209ff
JH
3430 /* Count the increment as a setting of the register,
3431 even though it isn't a SET in rtl. */
3432 REG_N_SETS (regno)++;
3433 }
f008a564 3434}
402209ff
JH
3435
3436/* X is a MEM found in INSN. See if we can convert it into an auto-increment
3437 reference. */
c9bacfdb 3438
21c7361e 3439static void
6cf9ac28 3440find_auto_inc (struct propagate_block_info *pbi, rtx x, rtx insn)
4dc9341c 3441{
402209ff
JH
3442 rtx addr = XEXP (x, 0);
3443 HOST_WIDE_INT offset = 0;
3444 rtx set, y, incr, inc_val;
3445 int regno;
3446 int size = GET_MODE_SIZE (GET_MODE (x));
4dc9341c 3447
4b4bf941 3448 if (JUMP_P (insn))
135ebc36
MH
3449 return;
3450
402209ff
JH
3451 /* Here we detect use of an index register which might be good for
3452 postincrement, postdecrement, preincrement, or predecrement. */
3453
3454 if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3455 offset = INTVAL (XEXP (addr, 1)), addr = XEXP (addr, 0);
4dc9341c 3456
f8cfc6aa 3457 if (!REG_P (addr))
402209ff 3458 return;
c9bacfdb 3459
402209ff 3460 regno = REGNO (addr);
135ebc36 3461
402209ff
JH
3462 /* Is the next use an increment that might make auto-increment? */
3463 incr = pbi->reg_next_use[regno];
3464 if (incr == 0 || BLOCK_NUM (incr) != BLOCK_NUM (insn))
3465 return;
3466 set = single_set (incr);
3467 if (set == 0 || GET_CODE (set) != SET)
3468 return;
3469 y = SET_SRC (set);
4dc9341c 3470
402209ff 3471 if (GET_CODE (y) != PLUS)
135ebc36
MH
3472 return;
3473
402209ff
JH
3474 if (REG_P (XEXP (y, 0)) && REGNO (XEXP (y, 0)) == REGNO (addr))
3475 inc_val = XEXP (y, 1);
3476 else if (REG_P (XEXP (y, 1)) && REGNO (XEXP (y, 1)) == REGNO (addr))
3477 inc_val = XEXP (y, 0);
3478 else
3479 return;
4dc9341c 3480
402209ff
JH
3481 if (GET_CODE (inc_val) == CONST_INT)
3482 {
3483 if (HAVE_POST_INCREMENT
3484 && (INTVAL (inc_val) == size && offset == 0))
3485 attempt_auto_inc (pbi, gen_rtx_POST_INC (Pmode, addr), insn, x,
3486 incr, addr);
3487 else if (HAVE_POST_DECREMENT
3488 && (INTVAL (inc_val) == -size && offset == 0))
3489 attempt_auto_inc (pbi, gen_rtx_POST_DEC (Pmode, addr), insn, x,
3490 incr, addr);
3491 else if (HAVE_PRE_INCREMENT
3492 && (INTVAL (inc_val) == size && offset == size))
3493 attempt_auto_inc (pbi, gen_rtx_PRE_INC (Pmode, addr), insn, x,
3494 incr, addr);
3495 else if (HAVE_PRE_DECREMENT
3496 && (INTVAL (inc_val) == -size && offset == -size))
3497 attempt_auto_inc (pbi, gen_rtx_PRE_DEC (Pmode, addr), insn, x,
3498 incr, addr);
3499 else if (HAVE_POST_MODIFY_DISP && offset == 0)
3500 attempt_auto_inc (pbi, gen_rtx_POST_MODIFY (Pmode, addr,
3501 gen_rtx_PLUS (Pmode,
3502 addr,
3503 inc_val)),
3504 insn, x, incr, addr);
89c4b810
RE
3505 else if (HAVE_PRE_MODIFY_DISP && offset == INTVAL (inc_val))
3506 attempt_auto_inc (pbi, gen_rtx_PRE_MODIFY (Pmode, addr,
3507 gen_rtx_PLUS (Pmode,
3508 addr,
3509 inc_val)),
3510 insn, x, incr, addr);
402209ff 3511 }
f8cfc6aa 3512 else if (REG_P (inc_val)
402209ff
JH
3513 && ! reg_set_between_p (inc_val, PREV_INSN (insn),
3514 NEXT_INSN (incr)))
135ebc36 3515
402209ff
JH
3516 {
3517 if (HAVE_POST_MODIFY_REG && offset == 0)
3518 attempt_auto_inc (pbi, gen_rtx_POST_MODIFY (Pmode, addr,
3519 gen_rtx_PLUS (Pmode,
3520 addr,
3521 inc_val)),
3522 insn, x, incr, addr);
3523 }
3524}
c9bacfdb 3525
402209ff
JH
3526#endif /* AUTO_INC_DEC */
3527\f
4dc9341c 3528static void
6cf9ac28
AJ
3529mark_used_reg (struct propagate_block_info *pbi, rtx reg,
3530 rtx cond ATTRIBUTE_UNUSED, rtx insn)
4dc9341c 3531{
402209ff
JH
3532 unsigned int regno_first, regno_last, i;
3533 int some_was_live, some_was_dead, some_not_set;
4dc9341c 3534
402209ff
JH
3535 regno_last = regno_first = REGNO (reg);
3536 if (regno_first < FIRST_PSEUDO_REGISTER)
66fd46b6 3537 regno_last += hard_regno_nregs[regno_first][GET_MODE (reg)] - 1;
4dc9341c 3538
402209ff
JH
3539 /* Find out if any of this register is live after this instruction. */
3540 some_was_live = some_was_dead = 0;
3541 for (i = regno_first; i <= regno_last; ++i)
4dc9341c 3542 {
402209ff
JH
3543 int needed_regno = REGNO_REG_SET_P (pbi->reg_live, i);
3544 some_was_live |= needed_regno;
3545 some_was_dead |= ! needed_regno;
4dc9341c
MH
3546 }
3547
402209ff
JH
3548 /* Find out if any of the register was set this insn. */
3549 some_not_set = 0;
3550 for (i = regno_first; i <= regno_last; ++i)
3551 some_not_set |= ! REGNO_REG_SET_P (pbi->new_set, i);
3552
3553 if (pbi->flags & (PROP_LOG_LINKS | PROP_AUTOINC))
c34d5374 3554 {
402209ff
JH
3555 /* Record where each reg is used, so when the reg is set we know
3556 the next insn that uses it. */
3557 pbi->reg_next_use[regno_first] = insn;
c34d5374 3558 }
c9bacfdb 3559
402209ff
JH
3560 if (pbi->flags & PROP_REG_INFO)
3561 {
3562 if (regno_first < FIRST_PSEUDO_REGISTER)
3563 {
3564 /* If this is a register we are going to try to eliminate,
3565 don't mark it live here. If we are successful in
3566 eliminating it, it need not be live unless it is used for
3567 pseudos, in which case it will have been set live when it
3568 was allocated to the pseudos. If the register will not
3569 be eliminated, reload will set it live at that point.
4dc9341c 3570
402209ff
JH
3571 Otherwise, record that this function uses this register. */
3572 /* ??? The PPC backend tries to "eliminate" on the pic
3573 register to itself. This should be fixed. In the mean
3574 time, hack around it. */
c9bacfdb 3575
402209ff
JH
3576 if (! (TEST_HARD_REG_BIT (elim_reg_set, regno_first)
3577 && (regno_first == FRAME_POINTER_REGNUM
3578 || regno_first == ARG_POINTER_REGNUM)))
3579 for (i = regno_first; i <= regno_last; ++i)
3580 regs_ever_live[i] = 1;
3581 }
3582 else
3583 {
3584 /* Keep track of which basic block each reg appears in. */
6057c0e6 3585
0b17ab2f 3586 int blocknum = pbi->bb->index;
402209ff
JH
3587 if (REG_BASIC_BLOCK (regno_first) == REG_BLOCK_UNKNOWN)
3588 REG_BASIC_BLOCK (regno_first) = blocknum;
3589 else if (REG_BASIC_BLOCK (regno_first) != blocknum)
3590 REG_BASIC_BLOCK (regno_first) = REG_BLOCK_GLOBAL;
6057c0e6 3591
402209ff
JH
3592 /* Count (weighted) number of uses of each reg. */
3593 REG_FREQ (regno_first) += REG_FREQ_FROM_BB (pbi->bb);
3594 REG_N_REFS (regno_first)++;
3595 }
736b64dd
JH
3596 for (i = regno_first; i <= regno_last; ++i)
3597 if (! REGNO_REG_SET_P (pbi->reg_live, i))
3598 {
0bccc606 3599 gcc_assert (!reg_deaths[i]);
736b64dd
JH
3600 reg_deaths[i] = pbi->insn_num;
3601 }
402209ff 3602 }
6057c0e6 3603
402209ff
JH
3604 /* Record and count the insns in which a reg dies. If it is used in
3605 this insn and was dead below the insn then it dies in this insn.
3606 If it was set in this insn, we do not make a REG_DEAD note;
3607 likewise if we already made such a note. */
3608 if ((pbi->flags & (PROP_DEATH_NOTES | PROP_REG_INFO))
3609 && some_was_dead
3610 && some_not_set)
3611 {
3612 /* Check for the case where the register dying partially
3613 overlaps the register set by this insn. */
3614 if (regno_first != regno_last)
3615 for (i = regno_first; i <= regno_last; ++i)
3616 some_was_live |= REGNO_REG_SET_P (pbi->new_set, i);
4dc9341c 3617
402209ff
JH
3618 /* If none of the words in X is needed, make a REG_DEAD note.
3619 Otherwise, we must make partial REG_DEAD notes. */
3620 if (! some_was_live)
3621 {
3622 if ((pbi->flags & PROP_DEATH_NOTES)
3623 && ! find_regno_note (insn, REG_DEAD, regno_first))
3624 REG_NOTES (insn)
3625 = alloc_EXPR_LIST (REG_DEAD, reg, REG_NOTES (insn));
4dc9341c 3626
402209ff
JH
3627 if (pbi->flags & PROP_REG_INFO)
3628 REG_N_DEATHS (regno_first)++;
3629 }
3630 else
3631 {
3632 /* Don't make a REG_DEAD note for a part of a register
3633 that is set in the insn. */
3634 for (i = regno_first; i <= regno_last; ++i)
3635 if (! REGNO_REG_SET_P (pbi->reg_live, i)
3636 && ! dead_or_set_regno_p (insn, i))
3637 REG_NOTES (insn)
3638 = alloc_EXPR_LIST (REG_DEAD,
e50126e8 3639 regno_reg_rtx[i],
402209ff
JH
3640 REG_NOTES (insn));
3641 }
3642 }
4dc9341c 3643
402209ff
JH
3644 /* Mark the register as being live. */
3645 for (i = regno_first; i <= regno_last; ++i)
4dc9341c 3646 {
9be40833
RH
3647#ifdef HAVE_conditional_execution
3648 int this_was_live = REGNO_REG_SET_P (pbi->reg_live, i);
3649#endif
3650
402209ff 3651 SET_REGNO_REG_SET (pbi->reg_live, i);
4dc9341c 3652
402209ff
JH
3653#ifdef HAVE_conditional_execution
3654 /* If this is a conditional use, record that fact. If it is later
3655 conditionally set, we'll know to kill the register. */
3656 if (cond != NULL_RTX)
4dc9341c 3657 {
402209ff
JH
3658 splay_tree_node node;
3659 struct reg_cond_life_info *rcli;
3660 rtx ncond;
3661
9be40833 3662 if (this_was_live)
402209ff
JH
3663 {
3664 node = splay_tree_lookup (pbi->reg_cond_dead, i);
3665 if (node == NULL)
3666 {
3667 /* The register was unconditionally live previously.
3668 No need to do anything. */
3669 }
3670 else
3671 {
3672 /* The register was conditionally live previously.
3673 Subtract the new life cond from the old death cond. */
3674 rcli = (struct reg_cond_life_info *) node->value;
3675 ncond = rcli->condition;
3676 ncond = and_reg_cond (ncond, not_reg_cond (cond), 1);
4dc9341c 3677
402209ff
JH
3678 /* If the register is now unconditionally live,
3679 remove the entry in the splay_tree. */
3680 if (ncond == const0_rtx)
3681 splay_tree_remove (pbi->reg_cond_dead, i);
3682 else
3683 {
3684 rcli->condition = ncond;
3685 SET_REGNO_REG_SET (pbi->reg_cond_reg,
3686 REGNO (XEXP (cond, 0)));
3687 }
3688 }
3689 }
3690 else
4dc9341c 3691 {
402209ff
JH
3692 /* The register was not previously live at all. Record
3693 the condition under which it is still dead. */
703ad42b 3694 rcli = xmalloc (sizeof (*rcli));
402209ff
JH
3695 rcli->condition = not_reg_cond (cond);
3696 rcli->stores = const0_rtx;
3697 rcli->orig_condition = const0_rtx;
3698 splay_tree_insert (pbi->reg_cond_dead, i,
3699 (splay_tree_value) rcli);
4dc9341c 3700
402209ff 3701 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
4dc9341c
MH
3702 }
3703 }
9be40833 3704 else if (this_was_live)
4dc9341c 3705 {
402209ff
JH
3706 /* The register may have been conditionally live previously, but
3707 is now unconditionally live. Remove it from the conditionally
3708 dead list, so that a conditional set won't cause us to think
3709 it dead. */
3710 splay_tree_remove (pbi->reg_cond_dead, i);
4dc9341c 3711 }
402209ff 3712#endif
4dc9341c
MH
3713 }
3714}
3715
402209ff
JH
3716/* Scan expression X and store a 1-bit in NEW_LIVE for each reg it uses.
3717 This is done assuming the registers needed from X are those that
3718 have 1-bits in PBI->REG_LIVE.
6057c0e6 3719
402209ff
JH
3720 INSN is the containing instruction. If INSN is dead, this function
3721 is not called. */
135ebc36 3722
402209ff 3723static void
6cf9ac28 3724mark_used_regs (struct propagate_block_info *pbi, rtx x, rtx cond, rtx insn)
135ebc36 3725{
b3694847
SS
3726 RTX_CODE code;
3727 int regno;
402209ff 3728 int flags = pbi->flags;
135ebc36 3729
402209ff 3730 retry:
5a133afd
JH
3731 if (!x)
3732 return;
402209ff
JH
3733 code = GET_CODE (x);
3734 switch (code)
135ebc36 3735 {
402209ff
JH
3736 case LABEL_REF:
3737 case SYMBOL_REF:
3738 case CONST_INT:
3739 case CONST:
3740 case CONST_DOUBLE:
69ef87e2 3741 case CONST_VECTOR:
402209ff
JH
3742 case PC:
3743 case ADDR_VEC:
3744 case ADDR_DIFF_VEC:
3745 return;
4dc9341c 3746
402209ff
JH
3747#ifdef HAVE_cc0
3748 case CC0:
3749 pbi->cc0_live = 1;
3750 return;
3751#endif
4dc9341c 3752
402209ff
JH
3753 case CLOBBER:
3754 /* If we are clobbering a MEM, mark any registers inside the address
3755 as being used. */
3c0cb5de 3756 if (MEM_P (XEXP (x, 0)))
402209ff
JH
3757 mark_used_regs (pbi, XEXP (XEXP (x, 0), 0), cond, insn);
3758 return;
4dc9341c 3759
402209ff
JH
3760 case MEM:
3761 /* Don't bother watching stores to mems if this is not the
3762 final pass. We'll not be deleting dead stores this round. */
5149f070 3763 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
4dc9341c 3764 {
402209ff
JH
3765 /* Invalidate the data for the last MEM stored, but only if MEM is
3766 something that can be stored into. */
3767 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
3768 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3769 /* Needn't clear the memory set list. */
3770 ;
3771 else
4dc9341c 3772 {
402209ff
JH
3773 rtx temp = pbi->mem_set_list;
3774 rtx prev = NULL_RTX;
3775 rtx next;
3776
3777 while (temp)
3778 {
3779 next = XEXP (temp, 1);
389fdba0 3780 if (anti_dependence (XEXP (temp, 0), x))
402209ff
JH
3781 {
3782 /* Splice temp out of the list. */
3783 if (prev)
3784 XEXP (prev, 1) = next;
3785 else
3786 pbi->mem_set_list = next;
3787 free_EXPR_LIST_node (temp);
3788 pbi->mem_set_list_len--;
3789 }
3790 else
3791 prev = temp;
3792 temp = next;
3793 }
4dc9341c 3794 }
402209ff
JH
3795
3796 /* If the memory reference had embedded side effects (autoincrement
3797 address modes. Then we may need to kill some entries on the
3798 memory set list. */
3799 if (insn)
fe4b3c79 3800 for_each_rtx (&PATTERN (insn), invalidate_mems_from_autoinc, pbi);
4dc9341c 3801 }
4dc9341c 3802
402209ff
JH
3803#ifdef AUTO_INC_DEC
3804 if (flags & PROP_AUTOINC)
dd3f0101 3805 find_auto_inc (pbi, x, insn);
402209ff
JH
3806#endif
3807 break;
d59c5346 3808
402209ff 3809 case SUBREG:
cff9f8d5 3810#ifdef CANNOT_CHANGE_MODE_CLASS
41bf2a8b
RH
3811 if (flags & PROP_REG_INFO)
3812 record_subregs_of_mode (x);
402209ff 3813#endif
d59c5346 3814
402209ff
JH
3815 /* While we're here, optimize this case. */
3816 x = SUBREG_REG (x);
f8cfc6aa 3817 if (!REG_P (x))
402209ff
JH
3818 goto retry;
3819 /* Fall through. */
d59c5346 3820
402209ff
JH
3821 case REG:
3822 /* See a register other than being set => mark it as needed. */
3823 mark_used_reg (pbi, x, cond, insn);
3824 return;
d59c5346 3825
402209ff
JH
3826 case SET:
3827 {
b3694847 3828 rtx testreg = SET_DEST (x);
402209ff 3829 int mark_dest = 0;
d59c5346 3830
402209ff
JH
3831 /* If storing into MEM, don't show it as being used. But do
3832 show the address as being used. */
3c0cb5de 3833 if (MEM_P (testreg))
402209ff
JH
3834 {
3835#ifdef AUTO_INC_DEC
3836 if (flags & PROP_AUTOINC)
3837 find_auto_inc (pbi, testreg, insn);
3838#endif
3839 mark_used_regs (pbi, XEXP (testreg, 0), cond, insn);
3840 mark_used_regs (pbi, SET_SRC (x), cond, insn);
3841 return;
3842 }
d59c5346 3843
402209ff
JH
3844 /* Storing in STRICT_LOW_PART is like storing in a reg
3845 in that this SET might be dead, so ignore it in TESTREG.
3846 but in some other ways it is like using the reg.
d59c5346 3847
402209ff
JH
3848 Storing in a SUBREG or a bit field is like storing the entire
3849 register in that if the register's value is not used
3850 then this SET is not needed. */
3851 while (GET_CODE (testreg) == STRICT_LOW_PART
3852 || GET_CODE (testreg) == ZERO_EXTRACT
402209ff
JH
3853 || GET_CODE (testreg) == SUBREG)
3854 {
cff9f8d5 3855#ifdef CANNOT_CHANGE_MODE_CLASS
41bf2a8b
RH
3856 if ((flags & PROP_REG_INFO) && GET_CODE (testreg) == SUBREG)
3857 record_subregs_of_mode (testreg);
402209ff 3858#endif
d59c5346 3859
402209ff
JH
3860 /* Modifying a single register in an alternate mode
3861 does not use any of the old value. But these other
3862 ways of storing in a register do use the old value. */
3863 if (GET_CODE (testreg) == SUBREG
ec8e621d
KG
3864 && !((REG_BYTES (SUBREG_REG (testreg))
3865 + UNITS_PER_WORD - 1) / UNITS_PER_WORD
3866 > (REG_BYTES (testreg)
3867 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
402209ff
JH
3868 ;
3869 else
3870 mark_dest = 1;
d59c5346 3871
402209ff
JH
3872 testreg = XEXP (testreg, 0);
3873 }
d59c5346 3874
402209ff
JH
3875 /* If this is a store into a register or group of registers,
3876 recursively scan the value being stored. */
d59c5346 3877
402209ff
JH
3878 if ((GET_CODE (testreg) == PARALLEL
3879 && GET_MODE (testreg) == BLKmode)
f8cfc6aa 3880 || (REG_P (testreg)
402209ff
JH
3881 && (regno = REGNO (testreg),
3882 ! (regno == FRAME_POINTER_REGNUM
3883 && (! reload_completed || frame_pointer_needed)))
3884#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
3885 && ! (regno == HARD_FRAME_POINTER_REGNUM
3886 && (! reload_completed || frame_pointer_needed))
3887#endif
3888#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3889 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
3890#endif
3891 ))
3892 {
3893 if (mark_dest)
3894 mark_used_regs (pbi, SET_DEST (x), cond, insn);
3895 mark_used_regs (pbi, SET_SRC (x), cond, insn);
3896 return;
3897 }
3898 }
3899 break;
c9bacfdb 3900
402209ff
JH
3901 case ASM_OPERANDS:
3902 case UNSPEC_VOLATILE:
3903 case TRAP_IF:
3904 case ASM_INPUT:
3905 {
3906 /* Traditional and volatile asm instructions must be considered to use
3907 and clobber all hard registers, all pseudo-registers and all of
3908 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
4dc9341c 3909
402209ff
JH
3910 Consider for instance a volatile asm that changes the fpu rounding
3911 mode. An insn should not be moved across this even if it only uses
3912 pseudo-regs because it might give an incorrectly rounded result.
4dc9341c 3913
402209ff
JH
3914 ?!? Unfortunately, marking all hard registers as live causes massive
3915 problems for the register allocator and marking all pseudos as live
3916 creates mountains of uninitialized variable warnings.
4dc9341c 3917
402209ff
JH
3918 So for now, just clear the memory set list and mark any regs
3919 we can find in ASM_OPERANDS as used. */
3920 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
3921 {
3922 free_EXPR_LIST_list (&pbi->mem_set_list);
3923 pbi->mem_set_list_len = 0;
3924 }
c9bacfdb 3925
402209ff
JH
3926 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
3927 We can not just fall through here since then we would be confused
3928 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
3929 traditional asms unlike their normal usage. */
3930 if (code == ASM_OPERANDS)
3931 {
3932 int j;
628f05b4 3933
402209ff
JH
3934 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
3935 mark_used_regs (pbi, ASM_OPERANDS_INPUT (x, j), cond, insn);
3936 }
3937 break;
3938 }
628f05b4 3939
402209ff 3940 case COND_EXEC:
0bccc606 3941 gcc_assert (!cond);
c9bacfdb 3942
402209ff 3943 mark_used_regs (pbi, COND_EXEC_TEST (x), NULL_RTX, insn);
c9bacfdb 3944
402209ff
JH
3945 cond = COND_EXEC_TEST (x);
3946 x = COND_EXEC_CODE (x);
3947 goto retry;
628f05b4 3948
402209ff
JH
3949 default:
3950 break;
4dc9341c 3951 }
628f05b4 3952
402209ff 3953 /* Recursively scan the operands of this expression. */
4dc9341c 3954
402209ff 3955 {
b3694847
SS
3956 const char * const fmt = GET_RTX_FORMAT (code);
3957 int i;
4dc9341c 3958
402209ff
JH
3959 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3960 {
3961 if (fmt[i] == 'e')
3962 {
3963 /* Tail recursive case: save a function call level. */
3964 if (i == 0)
3965 {
3966 x = XEXP (x, 0);
3967 goto retry;
3968 }
3969 mark_used_regs (pbi, XEXP (x, i), cond, insn);
3970 }
3971 else if (fmt[i] == 'E')
3972 {
b3694847 3973 int j;
402209ff
JH
3974 for (j = 0; j < XVECLEN (x, i); j++)
3975 mark_used_regs (pbi, XVECEXP (x, i, j), cond, insn);
3976 }
3977 }
3978 }
4dc9341c 3979}
402209ff
JH
3980\f
3981#ifdef AUTO_INC_DEC
4dc9341c 3982
402209ff 3983static int
6cf9ac28 3984try_pre_increment_1 (struct propagate_block_info *pbi, rtx insn)
402209ff
JH
3985{
3986 /* Find the next use of this reg. If in same basic block,
3987 make it do pre-increment or pre-decrement if appropriate. */
3988 rtx x = single_set (insn);
3989 HOST_WIDE_INT amount = ((GET_CODE (SET_SRC (x)) == PLUS ? 1 : -1)
3990 * INTVAL (XEXP (SET_SRC (x), 1)));
3991 int regno = REGNO (SET_DEST (x));
3992 rtx y = pbi->reg_next_use[regno];
3993 if (y != 0
3994 && SET_DEST (x) != stack_pointer_rtx
3995 && BLOCK_NUM (y) == BLOCK_NUM (insn)
3996 /* Don't do this if the reg dies, or gets set in y; a standard addressing
3997 mode would be better. */
3998 && ! dead_or_set_p (y, SET_DEST (x))
3999 && try_pre_increment (y, SET_DEST (x), amount))
4000 {
4001 /* We have found a suitable auto-increment and already changed
4002 insn Y to do it. So flush this increment instruction. */
3dec4024 4003 propagate_block_delete_insn (insn);
b53978a3 4004
402209ff
JH
4005 /* Count a reference to this reg for the increment insn we are
4006 deleting. When a reg is incremented, spilling it is worse,
4007 so we want to make that less likely. */
4008 if (regno >= FIRST_PSEUDO_REGISTER)
4009 {
4010 REG_FREQ (regno) += REG_FREQ_FROM_BB (pbi->bb);
4011 REG_N_SETS (regno)++;
4012 }
b53978a3 4013
402209ff
JH
4014 /* Flush any remembered memories depending on the value of
4015 the incremented register. */
4016 invalidate_mems_from_set (pbi, SET_DEST (x));
b53978a3 4017
402209ff
JH
4018 return 1;
4019 }
4020 return 0;
4021}
b53978a3 4022
402209ff
JH
4023/* Try to change INSN so that it does pre-increment or pre-decrement
4024 addressing on register REG in order to add AMOUNT to REG.
4025 AMOUNT is negative for pre-decrement.
4026 Returns 1 if the change could be made.
4027 This checks all about the validity of the result of modifying INSN. */
b53978a3 4028
402209ff 4029static int
6cf9ac28 4030try_pre_increment (rtx insn, rtx reg, HOST_WIDE_INT amount)
b53978a3 4031{
b3694847 4032 rtx use;
b53978a3 4033
402209ff
JH
4034 /* Nonzero if we can try to make a pre-increment or pre-decrement.
4035 For example, addl $4,r1; movl (r1),... can become movl +(r1),... */
4036 int pre_ok = 0;
4037 /* Nonzero if we can try to make a post-increment or post-decrement.
4038 For example, addl $4,r1; movl -4(r1),... can become movl (r1)+,...
4039 It is possible for both PRE_OK and POST_OK to be nonzero if the machine
4040 supports both pre-inc and post-inc, or both pre-dec and post-dec. */
4041 int post_ok = 0;
b53978a3 4042
402209ff
JH
4043 /* Nonzero if the opportunity actually requires post-inc or post-dec. */
4044 int do_post = 0;
b53978a3 4045
402209ff
JH
4046 /* From the sign of increment, see which possibilities are conceivable
4047 on this target machine. */
4048 if (HAVE_PRE_INCREMENT && amount > 0)
4049 pre_ok = 1;
4050 if (HAVE_POST_INCREMENT && amount > 0)
4051 post_ok = 1;
b53978a3 4052
402209ff
JH
4053 if (HAVE_PRE_DECREMENT && amount < 0)
4054 pre_ok = 1;
4055 if (HAVE_POST_DECREMENT && amount < 0)
4056 post_ok = 1;
b53978a3 4057
402209ff
JH
4058 if (! (pre_ok || post_ok))
4059 return 0;
b53978a3 4060
402209ff
JH
4061 /* It is not safe to add a side effect to a jump insn
4062 because if the incremented register is spilled and must be reloaded
4063 there would be no way to store the incremented value back in memory. */
c9bacfdb 4064
4b4bf941 4065 if (JUMP_P (insn))
402209ff 4066 return 0;
b53978a3 4067
402209ff
JH
4068 use = 0;
4069 if (pre_ok)
4070 use = find_use_as_address (PATTERN (insn), reg, 0);
60e8b9f0 4071 if (post_ok && (use == 0 || use == (rtx) (size_t) 1))
b53978a3 4072 {
402209ff
JH
4073 use = find_use_as_address (PATTERN (insn), reg, -amount);
4074 do_post = 1;
b53978a3
JO
4075 }
4076
60e8b9f0 4077 if (use == 0 || use == (rtx) (size_t) 1)
402209ff
JH
4078 return 0;
4079
4080 if (GET_MODE_SIZE (GET_MODE (use)) != (amount > 0 ? amount : - amount))
4081 return 0;
b53978a3 4082
402209ff
JH
4083 /* See if this combination of instruction and addressing mode exists. */
4084 if (! validate_change (insn, &XEXP (use, 0),
4085 gen_rtx_fmt_e (amount > 0
4086 ? (do_post ? POST_INC : PRE_INC)
4087 : (do_post ? POST_DEC : PRE_DEC),
4088 Pmode, reg), 0))
4089 return 0;
b53978a3 4090
402209ff
JH
4091 /* Record that this insn now has an implicit side effect on X. */
4092 REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, reg, REG_NOTES (insn));
4093 return 1;
b53978a3
JO
4094}
4095
402209ff
JH
4096#endif /* AUTO_INC_DEC */
4097\f
4098/* Find the place in the rtx X where REG is used as a memory address.
4099 Return the MEM rtx that so uses it.
4100 If PLUSCONST is nonzero, search instead for a memory address equivalent to
4101 (plus REG (const_int PLUSCONST)).
5d6a16e2 4102
402209ff
JH
4103 If such an address does not appear, return 0.
4104 If REG appears more than once, or is used other than in such an address,
60e8b9f0 4105 return (rtx) 1. */
5d6a16e2 4106
402209ff 4107rtx
6cf9ac28 4108find_use_as_address (rtx x, rtx reg, HOST_WIDE_INT plusconst)
5d6a16e2 4109{
402209ff
JH
4110 enum rtx_code code = GET_CODE (x);
4111 const char * const fmt = GET_RTX_FORMAT (code);
b3694847
SS
4112 int i;
4113 rtx value = 0;
4114 rtx tem;
4a7da9b5 4115
402209ff
JH
4116 if (code == MEM && XEXP (x, 0) == reg && plusconst == 0)
4117 return x;
5d6a16e2 4118
402209ff
JH
4119 if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS
4120 && XEXP (XEXP (x, 0), 0) == reg
4121 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4122 && INTVAL (XEXP (XEXP (x, 0), 1)) == plusconst)
4123 return x;
ef120fc0 4124
402209ff 4125 if (code == SIGN_EXTRACT || code == ZERO_EXTRACT)
5d6a16e2 4126 {
402209ff
JH
4127 /* If REG occurs inside a MEM used in a bit-field reference,
4128 that is unacceptable. */
4129 if (find_use_as_address (XEXP (x, 0), reg, 0) != 0)
60e8b9f0 4130 return (rtx) (size_t) 1;
5d6a16e2 4131 }
5d6a16e2 4132
402209ff 4133 if (x == reg)
60e8b9f0 4134 return (rtx) (size_t) 1;
4dc9341c 4135
402209ff 4136 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4dc9341c 4137 {
402209ff
JH
4138 if (fmt[i] == 'e')
4139 {
4140 tem = find_use_as_address (XEXP (x, i), reg, plusconst);
4141 if (value == 0)
4142 value = tem;
4143 else if (tem != 0)
60e8b9f0 4144 return (rtx) (size_t) 1;
402209ff
JH
4145 }
4146 else if (fmt[i] == 'E')
4dc9341c 4147 {
b3694847 4148 int j;
402209ff 4149 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4dc9341c 4150 {
402209ff
JH
4151 tem = find_use_as_address (XVECEXP (x, i, j), reg, plusconst);
4152 if (value == 0)
4153 value = tem;
4154 else if (tem != 0)
60e8b9f0 4155 return (rtx) (size_t) 1;
4dc9341c
MH
4156 }
4157 }
4158 }
4dc9341c 4159
402209ff
JH
4160 return value;
4161}
4162\f
4163/* Write information about registers and basic blocks into FILE.
4164 This is part of making a debugging dump. */
c9bacfdb 4165
402209ff 4166void
6cf9ac28 4167dump_regset (regset r, FILE *outf)
4dc9341c 4168{
3cd8c58a 4169 unsigned i;
a2041967
KH
4170 reg_set_iterator rsi;
4171
402209ff 4172 if (r == NULL)
3abd3239 4173 {
402209ff 4174 fputs (" (nil)", outf);
3abd3239
MH
4175 return;
4176 }
4dc9341c 4177
a2041967 4178 EXECUTE_IF_SET_IN_REG_SET (r, 0, i, rsi)
4dc9341c 4179 {
402209ff
JH
4180 fprintf (outf, " %d", i);
4181 if (i < FIRST_PSEUDO_REGISTER)
4182 fprintf (outf, " [%s]",
4183 reg_names[i]);
a2041967 4184 }
4dc9341c
MH
4185}
4186
fbe5a4a6 4187/* Print a human-readable representation of R on the standard error
402209ff
JH
4188 stream. This function is designed to be used from within the
4189 debugger. */
c9bacfdb 4190
402209ff 4191void
6cf9ac28 4192debug_regset (regset r)
4dc9341c 4193{
402209ff
JH
4194 dump_regset (r, stderr);
4195 putc ('\n', stderr);
4dc9341c
MH
4196}
4197
402209ff
JH
4198/* Recompute register set/reference counts immediately prior to register
4199 allocation.
5d6a16e2 4200
402209ff
JH
4201 This avoids problems with set/reference counts changing to/from values
4202 which have special meanings to the register allocators.
eab02feb 4203
402209ff
JH
4204 Additionally, the reference counts are the primary component used by the
4205 register allocators to prioritize pseudos for allocation to hard regs.
4206 More accurate reference counts generally lead to better register allocation.
eab02feb 4207
402209ff
JH
4208 It might be worthwhile to update REG_LIVE_LENGTH, REG_BASIC_BLOCK and
4209 possibly other information which is used by the register allocators. */
eab02feb 4210
402209ff 4211void
e22857eb 4212recompute_reg_usage (void)
402209ff
JH
4213{
4214 allocate_reg_life_data ();
58565a33
SKG
4215 /* distribute_notes in combiner fails to convert some of the REG_UNUSED notes
4216 to REG_DEAD notes. This causes CHECK_DEAD_NOTES in sched1 to abort. To
4217 solve this update the DEATH_NOTES here. */
4218 update_life_info (NULL, UPDATE_LIFE_LOCAL, PROP_REG_INFO | PROP_DEATH_NOTES);
eab02feb
MH
4219}
4220
402209ff
JH
4221/* Optionally removes all the REG_DEAD and REG_UNUSED notes from a set of
4222 blocks. If BLOCKS is NULL, assume the universal set. Returns a count
4223 of the number of registers that died. */
d4b60170 4224
c9bacfdb 4225int
6cf9ac28 4226count_or_remove_death_notes (sbitmap blocks, int kill)
4dc9341c 4227{
e0082a72 4228 int count = 0;
095c3bbd 4229 int i;
e0082a72 4230 basic_block bb;
ce4bbac7 4231
095c3bbd
JL
4232 /* This used to be a loop over all the blocks with a membership test
4233 inside the loop. That can be amazingly expensive on a large CFG
4234 when only a small number of bits are set in BLOCKs (for example,
4235 the calls from the scheduler typically have very few bits set).
4236
4237 For extra credit, someone should convert BLOCKS to a bitmap rather
4238 than an sbitmap. */
4239 if (blocks)
4240 {
4241 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
4242 {
4243 count += count_or_remove_death_notes_bb (BASIC_BLOCK (i), kill);
4244 });
4245 }
4246 else
4dc9341c 4247 {
095c3bbd
JL
4248 FOR_EACH_BB (bb)
4249 {
4250 count += count_or_remove_death_notes_bb (bb, kill);
4251 }
4252 }
5d6a16e2 4253
095c3bbd
JL
4254 return count;
4255}
4256
4257/* Optionally removes all the REG_DEAD and REG_UNUSED notes from basic
4258 block BB. Returns a count of the number of registers that died. */
5d6a16e2 4259
095c3bbd
JL
4260static int
4261count_or_remove_death_notes_bb (basic_block bb, int kill)
4262{
4263 int count = 0;
4264 rtx insn;
4265
a813c111 4266 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
095c3bbd
JL
4267 {
4268 if (INSN_P (insn))
4dc9341c 4269 {
095c3bbd
JL
4270 rtx *pprev = &REG_NOTES (insn);
4271 rtx link = *pprev;
402209ff 4272
095c3bbd
JL
4273 while (link)
4274 {
4275 switch (REG_NOTE_KIND (link))
4dc9341c 4276 {
095c3bbd 4277 case REG_DEAD:
f8cfc6aa 4278 if (REG_P (XEXP (link, 0)))
095c3bbd
JL
4279 {
4280 rtx reg = XEXP (link, 0);
4281 int n;
4282
4283 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
4284 n = 1;
4285 else
66fd46b6 4286 n = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
095c3bbd
JL
4287 count += n;
4288 }
4289
4290 /* Fall through. */
4291
4292 case REG_UNUSED:
4293 if (kill)
402209ff 4294 {
095c3bbd
JL
4295 rtx next = XEXP (link, 1);
4296 free_EXPR_LIST_node (link);
4297 *pprev = link = next;
402209ff
JH
4298 break;
4299 }
095c3bbd
JL
4300 /* Fall through. */
4301
4302 default:
4303 pprev = &XEXP (link, 1);
4304 link = *pprev;
4305 break;
4dc9341c
MH
4306 }
4307 }
5d6a16e2 4308 }
095c3bbd 4309
a813c111 4310 if (insn == BB_END (bb))
095c3bbd 4311 break;
5a660bff 4312 }
4dc9341c 4313
402209ff 4314 return count;
4dc9341c 4315}
095c3bbd 4316
b932f770
JH
4317/* Clear LOG_LINKS fields of insns in a selected blocks or whole chain
4318 if blocks is NULL. */
efc9bd41 4319
b932f770 4320static void
6cf9ac28 4321clear_log_links (sbitmap blocks)
d9d4fb43 4322{
b932f770
JH
4323 rtx insn;
4324 int i;
1868b439 4325
b932f770 4326 if (!blocks)
1868b439 4327 {
b932f770
JH
4328 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4329 if (INSN_P (insn))
e9cf0934 4330 free_INSN_LIST_list (&LOG_LINKS (insn));
1868b439 4331 }
b932f770
JH
4332 else
4333 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
4334 {
4335 basic_block bb = BASIC_BLOCK (i);
16e99e29 4336
a813c111 4337 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
b932f770
JH
4338 insn = NEXT_INSN (insn))
4339 if (INSN_P (insn))
e9cf0934 4340 free_INSN_LIST_list (&LOG_LINKS (insn));
b932f770 4341 });
d9d4fb43 4342}
efc9bd41
RK
4343
4344/* Given a register bitmap, turn on the bits in a HARD_REG_SET that
4345 correspond to the hard registers, if any, set in that map. This
4346 could be done far more efficiently by having all sorts of special-cases
4347 with moving single words, but probably isn't worth the trouble. */
4348
4349void
6cf9ac28 4350reg_set_to_hard_reg_set (HARD_REG_SET *to, bitmap from)
efc9bd41 4351{
3cd8c58a 4352 unsigned i;
87c476a2 4353 bitmap_iterator bi;
efc9bd41 4354
87c476a2
ZD
4355 EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
4356 {
4357 if (i >= FIRST_PSEUDO_REGISTER)
4358 return;
4359 SET_HARD_REG_BIT (*to, i);
4360 }
efc9bd41 4361}