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a52b023a | 1 | /* RTL-based forward propagation pass for GNU compiler. |
5624e564 | 2 | Copyright (C) 2005-2015 Free Software Foundation, Inc. |
a52b023a PB |
3 | Contributed by Paolo Bonzini and Steven Bosscher. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 9 | Software Foundation; either version 3, or (at your option) any later |
a52b023a PB |
10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
a52b023a PB |
20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
c7131fb2 AM |
24 | #include "backend.h" |
25 | #include "rtl.h" | |
26 | #include "df.h" | |
718f9c0f | 27 | #include "diagnostic-core.h" |
a52b023a | 28 | |
dc007c1f | 29 | #include "sparseset.h" |
a52b023a | 30 | #include "tm_p.h" |
a52b023a PB |
31 | #include "insn-config.h" |
32 | #include "recog.h" | |
33 | #include "flags.h" | |
34 | #include "obstack.h" | |
60393bbc AM |
35 | #include "cfgrtl.h" |
36 | #include "cfgcleanup.h" | |
a52b023a PB |
37 | #include "target.h" |
38 | #include "cfgloop.h" | |
39 | #include "tree-pass.h" | |
c6741572 | 40 | #include "domwalk.h" |
5936d944 | 41 | #include "emit-rtl.h" |
aa4e2d7e | 42 | #include "rtl-iter.h" |
a52b023a PB |
43 | |
44 | ||
45 | /* This pass does simple forward propagation and simplification when an | |
46 | operand of an insn can only come from a single def. This pass uses | |
47 | df.c, so it is global. However, we only do limited analysis of | |
48 | available expressions. | |
49 | ||
50 | 1) The pass tries to propagate the source of the def into the use, | |
51 | and checks if the result is independent of the substituted value. | |
52 | For example, the high word of a (zero_extend:DI (reg:SI M)) is always | |
53 | zero, independent of the source register. | |
54 | ||
55 | In particular, we propagate constants into the use site. Sometimes | |
56 | RTL expansion did not put the constant in the same insn on purpose, | |
57 | to satisfy a predicate, and the result will fail to be recognized; | |
58 | but this happens rarely and in this case we can still create a | |
59 | REG_EQUAL note. For multi-word operations, this | |
60 | ||
61 | (set (subreg:SI (reg:DI 120) 0) (const_int 0)) | |
62 | (set (subreg:SI (reg:DI 120) 4) (const_int -1)) | |
63 | (set (subreg:SI (reg:DI 122) 0) | |
64 | (ior:SI (subreg:SI (reg:DI 119) 0) (subreg:SI (reg:DI 120) 0))) | |
65 | (set (subreg:SI (reg:DI 122) 4) | |
66 | (ior:SI (subreg:SI (reg:DI 119) 4) (subreg:SI (reg:DI 120) 4))) | |
67 | ||
68 | can be simplified to the much simpler | |
69 | ||
70 | (set (subreg:SI (reg:DI 122) 0) (subreg:SI (reg:DI 119))) | |
71 | (set (subreg:SI (reg:DI 122) 4) (const_int -1)) | |
72 | ||
73 | This particular propagation is also effective at putting together | |
74 | complex addressing modes. We are more aggressive inside MEMs, in | |
75 | that all definitions are propagated if the use is in a MEM; if the | |
76 | result is a valid memory address we check address_cost to decide | |
77 | whether the substitution is worthwhile. | |
78 | ||
79 | 2) The pass propagates register copies. This is not as effective as | |
80 | the copy propagation done by CSE's canon_reg, which works by walking | |
81 | the instruction chain, it can help the other transformations. | |
82 | ||
83 | We should consider removing this optimization, and instead reorder the | |
84 | RTL passes, because GCSE does this transformation too. With some luck, | |
85 | the CSE pass at the end of rest_of_handle_gcse could also go away. | |
86 | ||
87 | 3) The pass looks for paradoxical subregs that are actually unnecessary. | |
88 | Things like this: | |
89 | ||
90 | (set (reg:QI 120) (subreg:QI (reg:SI 118) 0)) | |
91 | (set (reg:QI 121) (subreg:QI (reg:SI 119) 0)) | |
92 | (set (reg:SI 122) (plus:SI (subreg:SI (reg:QI 120) 0) | |
93 | (subreg:SI (reg:QI 121) 0))) | |
94 | ||
95 | are very common on machines that can only do word-sized operations. | |
96 | For each use of a paradoxical subreg (subreg:WIDER (reg:NARROW N) 0), | |
97 | if it has a single def and it is (subreg:NARROW (reg:WIDE M) 0), | |
98 | we can replace the paradoxical subreg with simply (reg:WIDE M). The | |
99 | above will simplify this to | |
100 | ||
101 | (set (reg:QI 120) (subreg:QI (reg:SI 118) 0)) | |
102 | (set (reg:QI 121) (subreg:QI (reg:SI 119) 0)) | |
103 | (set (reg:SI 122) (plus:SI (reg:SI 118) (reg:SI 119))) | |
104 | ||
c6741572 PB |
105 | where the first two insns are now dead. |
106 | ||
107 | We used to use reaching definitions to find which uses have a | |
108 | single reaching definition (sounds obvious...), but this is too | |
109 | complex a problem in nasty testcases like PR33928. Now we use the | |
110 | multiple definitions problem in df-problems.c. The similarity | |
111 | between that problem and SSA form creation is taken further, in | |
112 | that fwprop does a dominator walk to create its chains; however, | |
113 | instead of creating a PHI function where multiple definitions meet | |
114 | I just punt and record only singleton use-def chains, which is | |
115 | all that is needed by fwprop. */ | |
a52b023a PB |
116 | |
117 | ||
a52b023a PB |
118 | static int num_changes; |
119 | ||
9771b263 DN |
120 | static vec<df_ref> use_def_ref; |
121 | static vec<df_ref> reg_defs; | |
122 | static vec<df_ref> reg_defs_stack; | |
00952e97 | 123 | |
f8682ff6 PB |
124 | /* The MD bitmaps are trimmed to include only live registers to cut |
125 | memory usage on testcases like insn-recog.c. Track live registers | |
126 | in the basic block and do not perform forward propagation if the | |
127 | destination is a dead pseudo occurring in a note. */ | |
128 | static bitmap local_md; | |
129 | static bitmap local_lr; | |
00952e97 PB |
130 | |
131 | /* Return the only def in USE's use-def chain, or NULL if there is | |
132 | more than one def in the chain. */ | |
133 | ||
134 | static inline df_ref | |
135 | get_def_for_use (df_ref use) | |
136 | { | |
9771b263 | 137 | return use_def_ref[DF_REF_ID (use)]; |
00952e97 PB |
138 | } |
139 | ||
140 | ||
c6741572 PB |
141 | /* Update the reg_defs vector with non-partial definitions in DEF_REC. |
142 | TOP_FLAG says which artificials uses should be used, when DEF_REC | |
143 | is an artificial def vector. LOCAL_MD is modified as after a | |
144 | df_md_simulate_* function; we do more or less the same processing | |
145 | done there, so we do not use those functions. */ | |
146 | ||
147 | #define DF_MD_GEN_FLAGS \ | |
148 | (DF_REF_PARTIAL | DF_REF_CONDITIONAL | DF_REF_MAY_CLOBBER) | |
00952e97 | 149 | |
c6741572 | 150 | static void |
b512946c | 151 | process_defs (df_ref def, int top_flag) |
00952e97 | 152 | { |
b512946c | 153 | for (; def; def = DF_REF_NEXT_LOC (def)) |
c6741572 | 154 | { |
9771b263 | 155 | df_ref curr_def = reg_defs[DF_REF_REGNO (def)]; |
c6741572 | 156 | unsigned int dregno; |
00952e97 | 157 | |
c6741572 PB |
158 | if ((DF_REF_FLAGS (def) & DF_REF_AT_TOP) != top_flag) |
159 | continue; | |
00952e97 | 160 | |
c6741572 PB |
161 | dregno = DF_REF_REGNO (def); |
162 | if (curr_def) | |
9771b263 | 163 | reg_defs_stack.safe_push (curr_def); |
c6741572 PB |
164 | else |
165 | { | |
166 | /* Do not store anything if "transitioning" from NULL to NULL. But | |
167 | otherwise, push a special entry on the stack to tell the | |
168 | leave_block callback that the entry in reg_defs was NULL. */ | |
169 | if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS) | |
170 | ; | |
171 | else | |
9771b263 | 172 | reg_defs_stack.safe_push (def); |
c6741572 PB |
173 | } |
174 | ||
175 | if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS) | |
176 | { | |
177 | bitmap_set_bit (local_md, dregno); | |
9771b263 | 178 | reg_defs[dregno] = NULL; |
c6741572 PB |
179 | } |
180 | else | |
181 | { | |
182 | bitmap_clear_bit (local_md, dregno); | |
9771b263 | 183 | reg_defs[dregno] = def; |
c6741572 | 184 | } |
00952e97 | 185 | } |
00952e97 PB |
186 | } |
187 | ||
188 | ||
189 | /* Fill the use_def_ref vector with values for the uses in USE_REC, | |
c6741572 PB |
190 | taking reaching definitions info from LOCAL_MD and REG_DEFS. |
191 | TOP_FLAG says which artificials uses should be used, when USE_REC | |
192 | is an artificial use vector. */ | |
00952e97 PB |
193 | |
194 | static void | |
b512946c | 195 | process_uses (df_ref use, int top_flag) |
00952e97 | 196 | { |
b512946c | 197 | for (; use; use = DF_REF_NEXT_LOC (use)) |
c6741572 | 198 | if ((DF_REF_FLAGS (use) & DF_REF_AT_TOP) == top_flag) |
00952e97 | 199 | { |
c6741572 | 200 | unsigned int uregno = DF_REF_REGNO (use); |
9771b263 | 201 | if (reg_defs[uregno] |
f8682ff6 PB |
202 | && !bitmap_bit_p (local_md, uregno) |
203 | && bitmap_bit_p (local_lr, uregno)) | |
9771b263 | 204 | use_def_ref[DF_REF_ID (use)] = reg_defs[uregno]; |
c6741572 PB |
205 | } |
206 | } | |
207 | ||
4d9192b5 TS |
208 | class single_def_use_dom_walker : public dom_walker |
209 | { | |
210 | public: | |
211 | single_def_use_dom_walker (cdi_direction direction) | |
212 | : dom_walker (direction) {} | |
213 | virtual void before_dom_children (basic_block); | |
214 | virtual void after_dom_children (basic_block); | |
215 | }; | |
216 | ||
217 | void | |
218 | single_def_use_dom_walker::before_dom_children (basic_block bb) | |
c6741572 | 219 | { |
c6741572 | 220 | int bb_index = bb->index; |
f8682ff6 PB |
221 | struct df_md_bb_info *md_bb_info = df_md_get_bb_info (bb_index); |
222 | struct df_lr_bb_info *lr_bb_info = df_lr_get_bb_info (bb_index); | |
d362bd85 | 223 | rtx_insn *insn; |
c6741572 | 224 | |
b33a91c9 JH |
225 | bitmap_copy (local_md, &md_bb_info->in); |
226 | bitmap_copy (local_lr, &lr_bb_info->in); | |
c6741572 PB |
227 | |
228 | /* Push a marker for the leave_block callback. */ | |
9771b263 | 229 | reg_defs_stack.safe_push (NULL); |
c6741572 | 230 | |
f8682ff6 PB |
231 | process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP); |
232 | process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP); | |
823ff7b4 BS |
233 | |
234 | /* We don't call df_simulate_initialize_forwards, as it may overestimate | |
235 | the live registers if there are unused artificial defs. We prefer | |
236 | liveness to be underestimated. */ | |
c6741572 PB |
237 | |
238 | FOR_BB_INSNS (bb, insn) | |
239 | if (INSN_P (insn)) | |
240 | { | |
241 | unsigned int uid = INSN_UID (insn); | |
f8682ff6 PB |
242 | process_uses (DF_INSN_UID_USES (uid), 0); |
243 | process_uses (DF_INSN_UID_EQ_USES (uid), 0); | |
244 | process_defs (DF_INSN_UID_DEFS (uid), 0); | |
245 | df_simulate_one_insn_forwards (bb, insn, local_lr); | |
00952e97 | 246 | } |
c6741572 | 247 | |
f8682ff6 PB |
248 | process_uses (df_get_artificial_uses (bb_index), 0); |
249 | process_defs (df_get_artificial_defs (bb_index), 0); | |
c6741572 PB |
250 | } |
251 | ||
252 | /* Pop the definitions created in this basic block when leaving its | |
253 | dominated parts. */ | |
254 | ||
4d9192b5 TS |
255 | void |
256 | single_def_use_dom_walker::after_dom_children (basic_block bb ATTRIBUTE_UNUSED) | |
c6741572 PB |
257 | { |
258 | df_ref saved_def; | |
9771b263 | 259 | while ((saved_def = reg_defs_stack.pop ()) != NULL) |
c6741572 PB |
260 | { |
261 | unsigned int dregno = DF_REF_REGNO (saved_def); | |
262 | ||
263 | /* See also process_defs. */ | |
9771b263 DN |
264 | if (saved_def == reg_defs[dregno]) |
265 | reg_defs[dregno] = NULL; | |
c6741572 | 266 | else |
9771b263 | 267 | reg_defs[dregno] = saved_def; |
c6741572 | 268 | } |
00952e97 PB |
269 | } |
270 | ||
271 | ||
c6741572 PB |
272 | /* Build a vector holding the reaching definitions of uses reached by a |
273 | single dominating definition. */ | |
00952e97 PB |
274 | |
275 | static void | |
276 | build_single_def_use_links (void) | |
277 | { | |
c6741572 PB |
278 | /* We use the multiple definitions problem to compute our restricted |
279 | use-def chains. */ | |
00952e97 | 280 | df_set_flags (DF_EQ_NOTES); |
c6741572 | 281 | df_md_add_problem (); |
f8682ff6 | 282 | df_note_add_problem (); |
00952e97 PB |
283 | df_analyze (); |
284 | df_maybe_reorganize_use_refs (DF_REF_ORDER_BY_INSN_WITH_NOTES); | |
285 | ||
9771b263 DN |
286 | use_def_ref.create (DF_USES_TABLE_SIZE ()); |
287 | use_def_ref.safe_grow_cleared (DF_USES_TABLE_SIZE ()); | |
00952e97 | 288 | |
9771b263 DN |
289 | reg_defs.create (max_reg_num ()); |
290 | reg_defs.safe_grow_cleared (max_reg_num ()); | |
00952e97 | 291 | |
0cae8d31 | 292 | reg_defs_stack.create (n_basic_blocks_for_fn (cfun) * 10); |
c6741572 | 293 | local_md = BITMAP_ALLOC (NULL); |
f8682ff6 | 294 | local_lr = BITMAP_ALLOC (NULL); |
c6741572 PB |
295 | |
296 | /* Walk the dominator tree looking for single reaching definitions | |
297 | dominating the uses. This is similar to how SSA form is built. */ | |
4d9192b5 TS |
298 | single_def_use_dom_walker (CDI_DOMINATORS) |
299 | .walk (cfun->cfg->x_entry_block_ptr); | |
c6741572 | 300 | |
f8682ff6 | 301 | BITMAP_FREE (local_lr); |
c6741572 | 302 | BITMAP_FREE (local_md); |
9771b263 DN |
303 | reg_defs.release (); |
304 | reg_defs_stack.release (); | |
00952e97 | 305 | } |
c6741572 | 306 | |
a52b023a PB |
307 | \f |
308 | /* Do not try to replace constant addresses or addresses of local and | |
309 | argument slots. These MEM expressions are made only once and inserted | |
310 | in many instructions, as well as being used to control symbol table | |
311 | output. It is not safe to clobber them. | |
312 | ||
313 | There are some uncommon cases where the address is already in a register | |
314 | for some reason, but we cannot take advantage of that because we have | |
315 | no easy way to unshare the MEM. In addition, looking up all stack | |
316 | addresses is costly. */ | |
317 | ||
318 | static bool | |
319 | can_simplify_addr (rtx addr) | |
320 | { | |
321 | rtx reg; | |
322 | ||
323 | if (CONSTANT_ADDRESS_P (addr)) | |
324 | return false; | |
325 | ||
326 | if (GET_CODE (addr) == PLUS) | |
327 | reg = XEXP (addr, 0); | |
328 | else | |
329 | reg = addr; | |
330 | ||
331 | return (!REG_P (reg) | |
332 | || (REGNO (reg) != FRAME_POINTER_REGNUM | |
333 | && REGNO (reg) != HARD_FRAME_POINTER_REGNUM | |
334 | && REGNO (reg) != ARG_POINTER_REGNUM)); | |
335 | } | |
336 | ||
337 | /* Returns a canonical version of X for the address, from the point of view, | |
338 | that all multiplications are represented as MULT instead of the multiply | |
339 | by a power of 2 being represented as ASHIFT. | |
340 | ||
341 | Every ASHIFT we find has been made by simplify_gen_binary and was not | |
342 | there before, so it is not shared. So we can do this in place. */ | |
343 | ||
344 | static void | |
345 | canonicalize_address (rtx x) | |
346 | { | |
347 | for (;;) | |
348 | switch (GET_CODE (x)) | |
349 | { | |
350 | case ASHIFT: | |
481683e1 | 351 | if (CONST_INT_P (XEXP (x, 1)) |
a52b023a PB |
352 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (GET_MODE (x)) |
353 | && INTVAL (XEXP (x, 1)) >= 0) | |
354 | { | |
355 | HOST_WIDE_INT shift = INTVAL (XEXP (x, 1)); | |
356 | PUT_CODE (x, MULT); | |
357 | XEXP (x, 1) = gen_int_mode ((HOST_WIDE_INT) 1 << shift, | |
358 | GET_MODE (x)); | |
359 | } | |
360 | ||
361 | x = XEXP (x, 0); | |
362 | break; | |
363 | ||
364 | case PLUS: | |
365 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
366 | || GET_CODE (XEXP (x, 0)) == ASHIFT | |
367 | || GET_CODE (XEXP (x, 0)) == CONST) | |
368 | canonicalize_address (XEXP (x, 0)); | |
369 | ||
370 | x = XEXP (x, 1); | |
371 | break; | |
372 | ||
373 | case CONST: | |
374 | x = XEXP (x, 0); | |
375 | break; | |
376 | ||
377 | default: | |
378 | return; | |
379 | } | |
380 | } | |
381 | ||
382 | /* OLD is a memory address. Return whether it is good to use NEW instead, | |
383 | for a memory access in the given MODE. */ | |
384 | ||
385 | static bool | |
ef4bddc2 | 386 | should_replace_address (rtx old_rtx, rtx new_rtx, machine_mode mode, |
09e881c9 | 387 | addr_space_t as, bool speed) |
a52b023a PB |
388 | { |
389 | int gain; | |
390 | ||
09e881c9 BE |
391 | if (rtx_equal_p (old_rtx, new_rtx) |
392 | || !memory_address_addr_space_p (mode, new_rtx, as)) | |
a52b023a PB |
393 | return false; |
394 | ||
395 | /* Copy propagation is always ok. */ | |
60564289 | 396 | if (REG_P (old_rtx) && REG_P (new_rtx)) |
a52b023a PB |
397 | return true; |
398 | ||
399 | /* Prefer the new address if it is less expensive. */ | |
09e881c9 BE |
400 | gain = (address_cost (old_rtx, mode, as, speed) |
401 | - address_cost (new_rtx, mode, as, speed)); | |
a52b023a PB |
402 | |
403 | /* If the addresses have equivalent cost, prefer the new address | |
5e8f01f4 | 404 | if it has the highest `set_src_cost'. That has the potential of |
a52b023a PB |
405 | eliminating the most insns without additional costs, and it |
406 | is the same that cse.c used to do. */ | |
407 | if (gain == 0) | |
5e8f01f4 | 408 | gain = set_src_cost (new_rtx, speed) - set_src_cost (old_rtx, speed); |
a52b023a PB |
409 | |
410 | return (gain > 0); | |
411 | } | |
412 | ||
460d667d PB |
413 | |
414 | /* Flags for the last parameter of propagate_rtx_1. */ | |
415 | ||
416 | enum { | |
417 | /* If PR_CAN_APPEAR is true, propagate_rtx_1 always returns true; | |
418 | if it is false, propagate_rtx_1 returns false if, for at least | |
419 | one occurrence OLD, it failed to collapse the result to a constant. | |
420 | For example, (mult:M (reg:M A) (minus:M (reg:M B) (reg:M A))) may | |
421 | collapse to zero if replacing (reg:M B) with (reg:M A). | |
422 | ||
423 | PR_CAN_APPEAR is disregarded inside MEMs: in that case, | |
424 | propagate_rtx_1 just tries to make cheaper and valid memory | |
425 | addresses. */ | |
426 | PR_CAN_APPEAR = 1, | |
427 | ||
428 | /* If PR_HANDLE_MEM is not set, propagate_rtx_1 won't attempt any replacement | |
429 | outside memory addresses. This is needed because propagate_rtx_1 does | |
430 | not do any analysis on memory; thus it is very conservative and in general | |
431 | it will fail if non-read-only MEMs are found in the source expression. | |
432 | ||
433 | PR_HANDLE_MEM is set when the source of the propagation was not | |
434 | another MEM. Then, it is safe not to treat non-read-only MEMs as | |
435 | ``opaque'' objects. */ | |
f40751dd JH |
436 | PR_HANDLE_MEM = 2, |
437 | ||
438 | /* Set when costs should be optimized for speed. */ | |
439 | PR_OPTIMIZE_FOR_SPEED = 4 | |
460d667d PB |
440 | }; |
441 | ||
442 | ||
a52b023a PB |
443 | /* Replace all occurrences of OLD in *PX with NEW and try to simplify the |
444 | resulting expression. Replace *PX with a new RTL expression if an | |
445 | occurrence of OLD was found. | |
446 | ||
a52b023a PB |
447 | This is only a wrapper around simplify-rtx.c: do not add any pattern |
448 | matching code here. (The sole exception is the handling of LO_SUM, but | |
449 | that is because there is no simplify_gen_* function for LO_SUM). */ | |
450 | ||
451 | static bool | |
60564289 | 452 | propagate_rtx_1 (rtx *px, rtx old_rtx, rtx new_rtx, int flags) |
a52b023a PB |
453 | { |
454 | rtx x = *px, tem = NULL_RTX, op0, op1, op2; | |
455 | enum rtx_code code = GET_CODE (x); | |
ef4bddc2 RS |
456 | machine_mode mode = GET_MODE (x); |
457 | machine_mode op_mode; | |
460d667d | 458 | bool can_appear = (flags & PR_CAN_APPEAR) != 0; |
a52b023a PB |
459 | bool valid_ops = true; |
460 | ||
460d667d PB |
461 | if (!(flags & PR_HANDLE_MEM) && MEM_P (x) && !MEM_READONLY_P (x)) |
462 | { | |
463 | /* If unsafe, change MEMs to CLOBBERs or SCRATCHes (to preserve whether | |
464 | they have side effects or not). */ | |
465 | *px = (side_effects_p (x) | |
466 | ? gen_rtx_CLOBBER (GET_MODE (x), const0_rtx) | |
467 | : gen_rtx_SCRATCH (GET_MODE (x))); | |
468 | return false; | |
469 | } | |
a52b023a | 470 | |
460d667d PB |
471 | /* If X is OLD_RTX, return NEW_RTX. But not if replacing only within an |
472 | address, and we are *not* inside one. */ | |
60564289 | 473 | if (x == old_rtx) |
a52b023a | 474 | { |
60564289 | 475 | *px = new_rtx; |
a52b023a PB |
476 | return can_appear; |
477 | } | |
478 | ||
460d667d | 479 | /* If this is an expression, try recursive substitution. */ |
a52b023a PB |
480 | switch (GET_RTX_CLASS (code)) |
481 | { | |
482 | case RTX_UNARY: | |
483 | op0 = XEXP (x, 0); | |
484 | op_mode = GET_MODE (op0); | |
60564289 | 485 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
a52b023a PB |
486 | if (op0 == XEXP (x, 0)) |
487 | return true; | |
488 | tem = simplify_gen_unary (code, mode, op0, op_mode); | |
489 | break; | |
490 | ||
491 | case RTX_BIN_ARITH: | |
492 | case RTX_COMM_ARITH: | |
493 | op0 = XEXP (x, 0); | |
494 | op1 = XEXP (x, 1); | |
60564289 KG |
495 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
496 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
a52b023a PB |
497 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
498 | return true; | |
499 | tem = simplify_gen_binary (code, mode, op0, op1); | |
500 | break; | |
501 | ||
502 | case RTX_COMPARE: | |
503 | case RTX_COMM_COMPARE: | |
504 | op0 = XEXP (x, 0); | |
505 | op1 = XEXP (x, 1); | |
506 | op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1); | |
60564289 KG |
507 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
508 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
a52b023a PB |
509 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
510 | return true; | |
511 | tem = simplify_gen_relational (code, mode, op_mode, op0, op1); | |
512 | break; | |
513 | ||
514 | case RTX_TERNARY: | |
515 | case RTX_BITFIELD_OPS: | |
516 | op0 = XEXP (x, 0); | |
517 | op1 = XEXP (x, 1); | |
518 | op2 = XEXP (x, 2); | |
519 | op_mode = GET_MODE (op0); | |
60564289 KG |
520 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
521 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
522 | valid_ops &= propagate_rtx_1 (&op2, old_rtx, new_rtx, flags); | |
a52b023a PB |
523 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2)) |
524 | return true; | |
525 | if (op_mode == VOIDmode) | |
526 | op_mode = GET_MODE (op0); | |
527 | tem = simplify_gen_ternary (code, mode, op_mode, op0, op1, op2); | |
528 | break; | |
529 | ||
530 | case RTX_EXTRA: | |
531 | /* The only case we try to handle is a SUBREG. */ | |
532 | if (code == SUBREG) | |
533 | { | |
534 | op0 = XEXP (x, 0); | |
60564289 | 535 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
a52b023a PB |
536 | if (op0 == XEXP (x, 0)) |
537 | return true; | |
538 | tem = simplify_gen_subreg (mode, op0, GET_MODE (SUBREG_REG (x)), | |
539 | SUBREG_BYTE (x)); | |
540 | } | |
541 | break; | |
542 | ||
543 | case RTX_OBJ: | |
60564289 | 544 | if (code == MEM && x != new_rtx) |
a52b023a PB |
545 | { |
546 | rtx new_op0; | |
547 | op0 = XEXP (x, 0); | |
548 | ||
549 | /* There are some addresses that we cannot work on. */ | |
550 | if (!can_simplify_addr (op0)) | |
551 | return true; | |
552 | ||
553 | op0 = new_op0 = targetm.delegitimize_address (op0); | |
60564289 | 554 | valid_ops &= propagate_rtx_1 (&new_op0, old_rtx, new_rtx, |
460d667d | 555 | flags | PR_CAN_APPEAR); |
a52b023a PB |
556 | |
557 | /* Dismiss transformation that we do not want to carry on. */ | |
558 | if (!valid_ops | |
559 | || new_op0 == op0 | |
c0729306 PB |
560 | || !(GET_MODE (new_op0) == GET_MODE (op0) |
561 | || GET_MODE (new_op0) == VOIDmode)) | |
a52b023a PB |
562 | return true; |
563 | ||
564 | canonicalize_address (new_op0); | |
565 | ||
566 | /* Copy propagations are always ok. Otherwise check the costs. */ | |
60564289 | 567 | if (!(REG_P (old_rtx) && REG_P (new_rtx)) |
f40751dd | 568 | && !should_replace_address (op0, new_op0, GET_MODE (x), |
09e881c9 | 569 | MEM_ADDR_SPACE (x), |
f40751dd | 570 | flags & PR_OPTIMIZE_FOR_SPEED)) |
a52b023a PB |
571 | return true; |
572 | ||
573 | tem = replace_equiv_address_nv (x, new_op0); | |
574 | } | |
575 | ||
576 | else if (code == LO_SUM) | |
577 | { | |
578 | op0 = XEXP (x, 0); | |
579 | op1 = XEXP (x, 1); | |
580 | ||
581 | /* The only simplification we do attempts to remove references to op0 | |
582 | or make it constant -- in both cases, op0's invalidity will not | |
583 | make the result invalid. */ | |
60564289 KG |
584 | propagate_rtx_1 (&op0, old_rtx, new_rtx, flags | PR_CAN_APPEAR); |
585 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
a52b023a PB |
586 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
587 | return true; | |
588 | ||
589 | /* (lo_sum (high x) x) -> x */ | |
590 | if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1)) | |
591 | tem = op1; | |
592 | else | |
593 | tem = gen_rtx_LO_SUM (mode, op0, op1); | |
594 | ||
595 | /* OP1 is likely not a legitimate address, otherwise there would have | |
596 | been no LO_SUM. We want it to disappear if it is invalid, return | |
597 | false in that case. */ | |
598 | return memory_address_p (mode, tem); | |
599 | } | |
600 | ||
601 | else if (code == REG) | |
602 | { | |
60564289 | 603 | if (rtx_equal_p (x, old_rtx)) |
a52b023a | 604 | { |
60564289 | 605 | *px = new_rtx; |
a52b023a PB |
606 | return can_appear; |
607 | } | |
608 | } | |
609 | break; | |
610 | ||
611 | default: | |
612 | break; | |
613 | } | |
614 | ||
615 | /* No change, no trouble. */ | |
616 | if (tem == NULL_RTX) | |
617 | return true; | |
618 | ||
619 | *px = tem; | |
620 | ||
621 | /* The replacement we made so far is valid, if all of the recursive | |
622 | replacements were valid, or we could simplify everything to | |
623 | a constant. */ | |
624 | return valid_ops || can_appear || CONSTANT_P (tem); | |
625 | } | |
626 | ||
460d667d | 627 | |
aa4e2d7e | 628 | /* Return true if X constains a non-constant mem. */ |
460d667d | 629 | |
aa4e2d7e RS |
630 | static bool |
631 | varying_mem_p (const_rtx x) | |
460d667d | 632 | { |
aa4e2d7e RS |
633 | subrtx_iterator::array_type array; |
634 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
635 | if (MEM_P (*iter) && !MEM_READONLY_P (*iter)) | |
636 | return true; | |
637 | return false; | |
460d667d PB |
638 | } |
639 | ||
640 | ||
a52b023a | 641 | /* Replace all occurrences of OLD in X with NEW and try to simplify the |
2f8e468b | 642 | resulting expression (in mode MODE). Return a new expression if it is |
a52b023a PB |
643 | a constant, otherwise X. |
644 | ||
645 | Simplifications where occurrences of NEW collapse to a constant are always | |
646 | accepted. All simplifications are accepted if NEW is a pseudo too. | |
647 | Otherwise, we accept simplifications that have a lower or equal cost. */ | |
648 | ||
649 | static rtx | |
ef4bddc2 | 650 | propagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx, |
f40751dd | 651 | bool speed) |
a52b023a PB |
652 | { |
653 | rtx tem; | |
654 | bool collapsed; | |
460d667d | 655 | int flags; |
a52b023a | 656 | |
60564289 | 657 | if (REG_P (new_rtx) && REGNO (new_rtx) < FIRST_PSEUDO_REGISTER) |
a52b023a PB |
658 | return NULL_RTX; |
659 | ||
460d667d | 660 | flags = 0; |
ca18edc5 UW |
661 | if (REG_P (new_rtx) |
662 | || CONSTANT_P (new_rtx) | |
663 | || (GET_CODE (new_rtx) == SUBREG | |
664 | && REG_P (SUBREG_REG (new_rtx)) | |
665 | && (GET_MODE_SIZE (mode) | |
666 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (new_rtx)))))) | |
460d667d | 667 | flags |= PR_CAN_APPEAR; |
aa4e2d7e | 668 | if (!varying_mem_p (new_rtx)) |
460d667d | 669 | flags |= PR_HANDLE_MEM; |
a52b023a | 670 | |
f40751dd JH |
671 | if (speed) |
672 | flags |= PR_OPTIMIZE_FOR_SPEED; | |
673 | ||
a52b023a | 674 | tem = x; |
60564289 | 675 | collapsed = propagate_rtx_1 (&tem, old_rtx, copy_rtx (new_rtx), flags); |
a52b023a PB |
676 | if (tem == x || !collapsed) |
677 | return NULL_RTX; | |
678 | ||
679 | /* gen_lowpart_common will not be able to process VOIDmode entities other | |
680 | than CONST_INTs. */ | |
481683e1 | 681 | if (GET_MODE (tem) == VOIDmode && !CONST_INT_P (tem)) |
a52b023a PB |
682 | return NULL_RTX; |
683 | ||
684 | if (GET_MODE (tem) == VOIDmode) | |
685 | tem = rtl_hooks.gen_lowpart_no_emit (mode, tem); | |
686 | else | |
687 | gcc_assert (GET_MODE (tem) == mode); | |
688 | ||
689 | return tem; | |
690 | } | |
691 | ||
692 | ||
693 | \f | |
694 | ||
695 | /* Return true if the register from reference REF is killed | |
696 | between FROM to (but not including) TO. */ | |
697 | ||
6fb5fa3c | 698 | static bool |
51c7dd98 | 699 | local_ref_killed_between_p (df_ref ref, rtx_insn *from, rtx_insn *to) |
a52b023a | 700 | { |
51c7dd98 | 701 | rtx_insn *insn; |
a52b023a PB |
702 | |
703 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) | |
704 | { | |
bfac633a | 705 | df_ref def; |
a52b023a PB |
706 | if (!INSN_P (insn)) |
707 | continue; | |
708 | ||
bfac633a RS |
709 | FOR_EACH_INSN_DEF (def, insn) |
710 | if (DF_REF_REGNO (ref) == DF_REF_REGNO (def)) | |
711 | return true; | |
a52b023a PB |
712 | } |
713 | return false; | |
714 | } | |
715 | ||
716 | ||
717 | /* Check if the given DEF is available in INSN. This would require full | |
718 | computation of available expressions; we check only restricted conditions: | |
719 | - if DEF is the sole definition of its register, go ahead; | |
720 | - in the same basic block, we check for no definitions killing the | |
721 | definition of DEF_INSN; | |
722 | - if USE's basic block has DEF's basic block as the sole predecessor, | |
723 | we check if the definition is killed after DEF_INSN or before | |
724 | TARGET_INSN insn, in their respective basic blocks. */ | |
725 | static bool | |
d362bd85 | 726 | use_killed_between (df_ref use, rtx_insn *def_insn, rtx_insn *target_insn) |
a52b023a | 727 | { |
6e0b633f PB |
728 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); |
729 | basic_block target_bb = BLOCK_FOR_INSN (target_insn); | |
a52b023a | 730 | int regno; |
57512f53 | 731 | df_ref def; |
a52b023a | 732 | |
c6741572 PB |
733 | /* We used to have a def reaching a use that is _before_ the def, |
734 | with the def not dominating the use even though the use and def | |
735 | are in the same basic block, when a register may be used | |
736 | uninitialized in a loop. This should not happen anymore since | |
737 | we do not use reaching definitions, but still we test for such | |
738 | cases and assume that DEF is not available. */ | |
6e0b633f | 739 | if (def_bb == target_bb |
6fb5fa3c | 740 | ? DF_INSN_LUID (def_insn) >= DF_INSN_LUID (target_insn) |
6e0b633f PB |
741 | : !dominated_by_p (CDI_DOMINATORS, target_bb, def_bb)) |
742 | return true; | |
743 | ||
a52b023a | 744 | /* Check if the reg in USE has only one definition. We already |
b08c5108 PB |
745 | know that this definition reaches use, or we wouldn't be here. |
746 | However, this is invalid for hard registers because if they are | |
747 | live at the beginning of the function it does not mean that we | |
748 | have an uninitialized access. */ | |
a52b023a | 749 | regno = DF_REF_REGNO (use); |
6fb5fa3c | 750 | def = DF_REG_DEF_CHAIN (regno); |
b08c5108 | 751 | if (def |
57512f53 | 752 | && DF_REF_NEXT_REG (def) == NULL |
b08c5108 | 753 | && regno >= FIRST_PSEUDO_REGISTER) |
a52b023a PB |
754 | return false; |
755 | ||
6e0b633f | 756 | /* Check locally if we are in the same basic block. */ |
a52b023a | 757 | if (def_bb == target_bb) |
6e0b633f | 758 | return local_ref_killed_between_p (use, def_insn, target_insn); |
a52b023a PB |
759 | |
760 | /* Finally, if DEF_BB is the sole predecessor of TARGET_BB. */ | |
761 | if (single_pred_p (target_bb) | |
762 | && single_pred (target_bb) == def_bb) | |
763 | { | |
57512f53 | 764 | df_ref x; |
a52b023a PB |
765 | |
766 | /* See if USE is killed between DEF_INSN and the last insn in the | |
767 | basic block containing DEF_INSN. */ | |
6fb5fa3c | 768 | x = df_bb_regno_last_def_find (def_bb, regno); |
50e94c7e | 769 | if (x && DF_INSN_LUID (DF_REF_INSN (x)) >= DF_INSN_LUID (def_insn)) |
a52b023a PB |
770 | return true; |
771 | ||
772 | /* See if USE is killed between TARGET_INSN and the first insn in the | |
773 | basic block containing TARGET_INSN. */ | |
6fb5fa3c | 774 | x = df_bb_regno_first_def_find (target_bb, regno); |
50e94c7e | 775 | if (x && DF_INSN_LUID (DF_REF_INSN (x)) < DF_INSN_LUID (target_insn)) |
a52b023a PB |
776 | return true; |
777 | ||
778 | return false; | |
779 | } | |
780 | ||
781 | /* Otherwise assume the worst case. */ | |
782 | return true; | |
783 | } | |
784 | ||
785 | ||
a52b023a PB |
786 | /* Check if all uses in DEF_INSN can be used in TARGET_INSN. This |
787 | would require full computation of available expressions; | |
788 | we check only restricted conditions, see use_killed_between. */ | |
789 | static bool | |
d362bd85 | 790 | all_uses_available_at (rtx_insn *def_insn, rtx_insn *target_insn) |
a52b023a | 791 | { |
bfac633a | 792 | df_ref use; |
50e94c7e | 793 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn); |
a52b023a | 794 | rtx def_set = single_set (def_insn); |
d362bd85 | 795 | rtx_insn *next; |
a52b023a PB |
796 | |
797 | gcc_assert (def_set); | |
798 | ||
799 | /* If target_insn comes right after def_insn, which is very common | |
07bc8ae8 JJ |
800 | for addresses, we can use a quicker test. Ignore debug insns |
801 | other than target insns for this. */ | |
802 | next = NEXT_INSN (def_insn); | |
803 | while (next && next != target_insn && DEBUG_INSN_P (next)) | |
804 | next = NEXT_INSN (next); | |
805 | if (next == target_insn && REG_P (SET_DEST (def_set))) | |
a52b023a PB |
806 | { |
807 | rtx def_reg = SET_DEST (def_set); | |
808 | ||
809 | /* If the insn uses the reg that it defines, the substitution is | |
810 | invalid. */ | |
bfac633a RS |
811 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
812 | if (rtx_equal_p (DF_REF_REG (use), def_reg)) | |
813 | return false; | |
814 | FOR_EACH_INSN_INFO_EQ_USE (use, insn_info) | |
815 | if (rtx_equal_p (DF_REF_REG (use), def_reg)) | |
816 | return false; | |
a52b023a PB |
817 | } |
818 | else | |
819 | { | |
2178b0f9 JJ |
820 | rtx def_reg = REG_P (SET_DEST (def_set)) ? SET_DEST (def_set) : NULL_RTX; |
821 | ||
a52b023a PB |
822 | /* Look at all the uses of DEF_INSN, and see if they are not |
823 | killed between DEF_INSN and TARGET_INSN. */ | |
bfac633a | 824 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
6fb5fa3c | 825 | { |
2178b0f9 JJ |
826 | if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg)) |
827 | return false; | |
6fb5fa3c DB |
828 | if (use_killed_between (use, def_insn, target_insn)) |
829 | return false; | |
830 | } | |
bfac633a | 831 | FOR_EACH_INSN_INFO_EQ_USE (use, insn_info) |
6fb5fa3c | 832 | { |
2178b0f9 JJ |
833 | if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg)) |
834 | return false; | |
6fb5fa3c DB |
835 | if (use_killed_between (use, def_insn, target_insn)) |
836 | return false; | |
837 | } | |
a52b023a PB |
838 | } |
839 | ||
460d667d | 840 | return true; |
a52b023a PB |
841 | } |
842 | ||
843 | \f | |
dc007c1f PB |
844 | static df_ref *active_defs; |
845 | #ifdef ENABLE_CHECKING | |
846 | static sparseset active_defs_check; | |
847 | #endif | |
a52b023a | 848 | |
dc007c1f PB |
849 | /* Fill the ACTIVE_DEFS array with the use->def link for the registers |
850 | mentioned in USE_REC. Register the valid entries in ACTIVE_DEFS_CHECK | |
851 | too, for checking purposes. */ | |
a52b023a | 852 | |
dc007c1f | 853 | static void |
b512946c | 854 | register_active_defs (df_ref use) |
a52b023a | 855 | { |
b512946c | 856 | for (; use; use = DF_REF_NEXT_LOC (use)) |
a52b023a | 857 | { |
dc007c1f PB |
858 | df_ref def = get_def_for_use (use); |
859 | int regno = DF_REF_REGNO (use); | |
a52b023a | 860 | |
dc007c1f PB |
861 | #ifdef ENABLE_CHECKING |
862 | sparseset_set_bit (active_defs_check, regno); | |
863 | #endif | |
864 | active_defs[regno] = def; | |
865 | } | |
a52b023a PB |
866 | } |
867 | ||
a52b023a | 868 | |
dc007c1f PB |
869 | /* Build the use->def links that we use to update the dataflow info |
870 | for new uses. Note that building the links is very cheap and if | |
871 | it were done earlier, they could be used to rule out invalid | |
872 | propagations (in addition to what is done in all_uses_available_at). | |
873 | I'm not doing this yet, though. */ | |
874 | ||
875 | static void | |
d362bd85 | 876 | update_df_init (rtx_insn *def_insn, rtx_insn *insn) |
a52b023a | 877 | { |
dc007c1f PB |
878 | #ifdef ENABLE_CHECKING |
879 | sparseset_clear (active_defs_check); | |
880 | #endif | |
881 | register_active_defs (DF_INSN_USES (def_insn)); | |
882 | register_active_defs (DF_INSN_USES (insn)); | |
883 | register_active_defs (DF_INSN_EQ_USES (insn)); | |
884 | } | |
a52b023a | 885 | |
a52b023a | 886 | |
dc007c1f PB |
887 | /* Update the USE_DEF_REF array for the given use, using the active definitions |
888 | in the ACTIVE_DEFS array to match pseudos to their def. */ | |
a52b023a | 889 | |
dc007c1f | 890 | static inline void |
b512946c | 891 | update_uses (df_ref use) |
a52b023a | 892 | { |
b512946c | 893 | for (; use; use = DF_REF_NEXT_LOC (use)) |
a52b023a | 894 | { |
dc007c1f | 895 | int regno = DF_REF_REGNO (use); |
a52b023a | 896 | |
dc007c1f | 897 | /* Set up the use-def chain. */ |
9771b263 DN |
898 | if (DF_REF_ID (use) >= (int) use_def_ref.length ()) |
899 | use_def_ref.safe_grow_cleared (DF_REF_ID (use) + 1); | |
a52b023a | 900 | |
dc007c1f PB |
901 | #ifdef ENABLE_CHECKING |
902 | gcc_assert (sparseset_bit_p (active_defs_check, regno)); | |
903 | #endif | |
9771b263 | 904 | use_def_ref[DF_REF_ID (use)] = active_defs[regno]; |
dc007c1f PB |
905 | } |
906 | } | |
a52b023a | 907 | |
dc007c1f PB |
908 | |
909 | /* Update the USE_DEF_REF array for the uses in INSN. Only update note | |
910 | uses if NOTES_ONLY is true. */ | |
911 | ||
912 | static void | |
d362bd85 | 913 | update_df (rtx_insn *insn, rtx note) |
dc007c1f PB |
914 | { |
915 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); | |
916 | ||
917 | if (note) | |
918 | { | |
919 | df_uses_create (&XEXP (note, 0), insn, DF_REF_IN_NOTE); | |
920 | df_notes_rescan (insn); | |
921 | } | |
922 | else | |
923 | { | |
924 | df_uses_create (&PATTERN (insn), insn, 0); | |
925 | df_insn_rescan (insn); | |
926 | update_uses (DF_INSN_INFO_USES (insn_info)); | |
a52b023a | 927 | } |
dc007c1f PB |
928 | |
929 | update_uses (DF_INSN_INFO_EQ_USES (insn_info)); | |
a52b023a PB |
930 | } |
931 | ||
932 | ||
933 | /* Try substituting NEW into LOC, which originated from forward propagation | |
934 | of USE's value from DEF_INSN. SET_REG_EQUAL says whether we are | |
935 | substituting the whole SET_SRC, so we can set a REG_EQUAL note if the | |
936 | new insn is not recognized. Return whether the substitution was | |
937 | performed. */ | |
938 | ||
939 | static bool | |
d362bd85 DM |
940 | try_fwprop_subst (df_ref use, rtx *loc, rtx new_rtx, rtx_insn *def_insn, |
941 | bool set_reg_equal) | |
a52b023a | 942 | { |
d362bd85 | 943 | rtx_insn *insn = DF_REF_INSN (use); |
de266950 | 944 | rtx set = single_set (insn); |
dc007c1f | 945 | rtx note = NULL_RTX; |
f40751dd | 946 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
e25b7843 | 947 | int old_cost = 0; |
de266950 | 948 | bool ok; |
a52b023a | 949 | |
dc007c1f PB |
950 | update_df_init (def_insn, insn); |
951 | ||
e25b7843 AM |
952 | /* forward_propagate_subreg may be operating on an instruction with |
953 | multiple sets. If so, assume the cost of the new instruction is | |
954 | not greater than the old one. */ | |
955 | if (set) | |
5e8f01f4 | 956 | old_cost = set_src_cost (SET_SRC (set), speed); |
a52b023a PB |
957 | if (dump_file) |
958 | { | |
959 | fprintf (dump_file, "\nIn insn %d, replacing\n ", INSN_UID (insn)); | |
960 | print_inline_rtx (dump_file, *loc, 2); | |
961 | fprintf (dump_file, "\n with "); | |
60564289 | 962 | print_inline_rtx (dump_file, new_rtx, 2); |
a52b023a PB |
963 | fprintf (dump_file, "\n"); |
964 | } | |
965 | ||
60564289 | 966 | validate_unshare_change (insn, loc, new_rtx, true); |
de266950 PB |
967 | if (!verify_changes (0)) |
968 | { | |
969 | if (dump_file) | |
970 | fprintf (dump_file, "Changes to insn %d not recognized\n", | |
971 | INSN_UID (insn)); | |
972 | ok = false; | |
973 | } | |
974 | ||
ea668464 | 975 | else if (DF_REF_TYPE (use) == DF_REF_REG_USE |
e25b7843 | 976 | && set |
5e8f01f4 | 977 | && set_src_cost (SET_SRC (set), speed) > old_cost) |
de266950 PB |
978 | { |
979 | if (dump_file) | |
980 | fprintf (dump_file, "Changes to insn %d not profitable\n", | |
981 | INSN_UID (insn)); | |
982 | ok = false; | |
983 | } | |
984 | ||
985 | else | |
a52b023a | 986 | { |
a52b023a PB |
987 | if (dump_file) |
988 | fprintf (dump_file, "Changed insn %d\n", INSN_UID (insn)); | |
de266950 PB |
989 | ok = true; |
990 | } | |
991 | ||
992 | if (ok) | |
993 | { | |
994 | confirm_change_group (); | |
995 | num_changes++; | |
a52b023a PB |
996 | } |
997 | else | |
998 | { | |
de266950 | 999 | cancel_changes (0); |
a52b023a | 1000 | |
3e836a31 | 1001 | /* Can also record a simplified value in a REG_EQUAL note, |
4a8cae83 SB |
1002 | making a new one if one does not already exist. */ |
1003 | if (set_reg_equal) | |
a52b023a PB |
1004 | { |
1005 | if (dump_file) | |
1006 | fprintf (dump_file, " Setting REG_EQUAL note\n"); | |
1007 | ||
dc007c1f | 1008 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (new_rtx)); |
a52b023a | 1009 | } |
a52b023a | 1010 | } |
de266950 | 1011 | |
dc007c1f PB |
1012 | if ((ok || note) && !CONSTANT_P (new_rtx)) |
1013 | update_df (insn, note); | |
1014 | ||
de266950 | 1015 | return ok; |
a52b023a PB |
1016 | } |
1017 | ||
e85122be AM |
1018 | /* For the given single_set INSN, containing SRC known to be a |
1019 | ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN | |
1020 | is redundant due to the register being set by a LOAD_EXTEND_OP | |
1021 | load from memory. */ | |
1022 | ||
1023 | static bool | |
d362bd85 | 1024 | free_load_extend (rtx src, rtx_insn *insn) |
e25b7843 | 1025 | { |
e85122be | 1026 | rtx reg; |
bfac633a | 1027 | df_ref def, use; |
e85122be AM |
1028 | |
1029 | reg = XEXP (src, 0); | |
1030 | #ifdef LOAD_EXTEND_OP | |
1031 | if (LOAD_EXTEND_OP (GET_MODE (reg)) != GET_CODE (src)) | |
1032 | #endif | |
1033 | return false; | |
e25b7843 | 1034 | |
bfac633a RS |
1035 | FOR_EACH_INSN_USE (use, insn) |
1036 | if (!DF_REF_IS_ARTIFICIAL (use) | |
1037 | && DF_REF_TYPE (use) == DF_REF_REG_USE | |
1038 | && DF_REF_REG (use) == reg) | |
1039 | break; | |
e85122be AM |
1040 | if (!use) |
1041 | return false; | |
1042 | ||
1043 | def = get_def_for_use (use); | |
1044 | if (!def) | |
1045 | return false; | |
1046 | ||
1047 | if (DF_REF_IS_ARTIFICIAL (def)) | |
1048 | return false; | |
1049 | ||
1050 | if (NONJUMP_INSN_P (DF_REF_INSN (def))) | |
1051 | { | |
1052 | rtx patt = PATTERN (DF_REF_INSN (def)); | |
1053 | ||
1054 | if (GET_CODE (patt) == SET | |
1055 | && GET_CODE (SET_SRC (patt)) == MEM | |
1056 | && rtx_equal_p (SET_DEST (patt), reg)) | |
1057 | return true; | |
e25b7843 | 1058 | } |
e85122be | 1059 | return false; |
e25b7843 | 1060 | } |
e25b7843 AM |
1061 | |
1062 | /* If USE is a subreg, see if it can be replaced by a pseudo. */ | |
a52b023a PB |
1063 | |
1064 | static bool | |
d362bd85 | 1065 | forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set) |
a52b023a PB |
1066 | { |
1067 | rtx use_reg = DF_REF_REG (use); | |
d362bd85 DM |
1068 | rtx_insn *use_insn; |
1069 | rtx src; | |
a52b023a | 1070 | |
e25b7843 | 1071 | /* Only consider subregs... */ |
ef4bddc2 | 1072 | machine_mode use_mode = GET_MODE (use_reg); |
a52b023a | 1073 | if (GET_CODE (use_reg) != SUBREG |
e25b7843 | 1074 | || !REG_P (SET_DEST (def_set))) |
a52b023a PB |
1075 | return false; |
1076 | ||
e25b7843 AM |
1077 | /* If this is a paradoxical SUBREG... */ |
1078 | if (GET_MODE_SIZE (use_mode) | |
1079 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (use_reg)))) | |
1080 | { | |
1081 | /* If this is a paradoxical SUBREG, we have no idea what value the | |
1082 | extra bits would have. However, if the operand is equivalent to | |
1083 | a SUBREG whose operand is the same as our mode, and all the modes | |
1084 | are within a word, we can just use the inner operand because | |
1085 | these SUBREGs just say how to treat the register. */ | |
1086 | use_insn = DF_REF_INSN (use); | |
1087 | src = SET_SRC (def_set); | |
1088 | if (GET_CODE (src) == SUBREG | |
1089 | && REG_P (SUBREG_REG (src)) | |
509a31f8 | 1090 | && REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER |
e25b7843 AM |
1091 | && GET_MODE (SUBREG_REG (src)) == use_mode |
1092 | && subreg_lowpart_p (src) | |
1093 | && all_uses_available_at (def_insn, use_insn)) | |
1094 | return try_fwprop_subst (use, DF_REF_LOC (use), SUBREG_REG (src), | |
1095 | def_insn, false); | |
1096 | } | |
1097 | ||
1098 | /* If this is a SUBREG of a ZERO_EXTEND or SIGN_EXTEND, and the SUBREG | |
1099 | is the low part of the reg being extended then just use the inner | |
1100 | operand. Don't do this if the ZERO_EXTEND or SIGN_EXTEND insn will | |
7a613929 RS |
1101 | be removed due to it matching a LOAD_EXTEND_OP load from memory, |
1102 | or due to the operation being a no-op when applied to registers. | |
1103 | For example, if we have: | |
1104 | ||
1105 | A: (set (reg:DI X) (sign_extend:DI (reg:SI Y))) | |
1106 | B: (... (subreg:SI (reg:DI X)) ...) | |
1107 | ||
1108 | and mode_rep_extended says that Y is already sign-extended, | |
1109 | the backend will typically allow A to be combined with the | |
1110 | definition of Y or, failing that, allow A to be deleted after | |
1111 | reload through register tying. Introducing more uses of Y | |
1112 | prevents both optimisations. */ | |
e25b7843 AM |
1113 | else if (subreg_lowpart_p (use_reg)) |
1114 | { | |
e25b7843 AM |
1115 | use_insn = DF_REF_INSN (use); |
1116 | src = SET_SRC (def_set); | |
1117 | if ((GET_CODE (src) == ZERO_EXTEND | |
1118 | || GET_CODE (src) == SIGN_EXTEND) | |
1119 | && REG_P (XEXP (src, 0)) | |
509a31f8 | 1120 | && REGNO (XEXP (src, 0)) >= FIRST_PSEUDO_REGISTER |
e25b7843 | 1121 | && GET_MODE (XEXP (src, 0)) == use_mode |
e85122be | 1122 | && !free_load_extend (src, def_insn) |
7a613929 RS |
1123 | && (targetm.mode_rep_extended (use_mode, GET_MODE (src)) |
1124 | != (int) GET_CODE (src)) | |
e25b7843 AM |
1125 | && all_uses_available_at (def_insn, use_insn)) |
1126 | return try_fwprop_subst (use, DF_REF_LOC (use), XEXP (src, 0), | |
1127 | def_insn, false); | |
1128 | } | |
1129 | ||
1130 | return false; | |
a52b023a PB |
1131 | } |
1132 | ||
ce372372 JJ |
1133 | /* Try to replace USE with SRC (defined in DEF_INSN) in __asm. */ |
1134 | ||
1135 | static bool | |
d362bd85 | 1136 | forward_propagate_asm (df_ref use, rtx_insn *def_insn, rtx def_set, rtx reg) |
ce372372 | 1137 | { |
d362bd85 DM |
1138 | rtx_insn *use_insn = DF_REF_INSN (use); |
1139 | rtx src, use_pat, asm_operands, new_rtx, *loc; | |
ce372372 | 1140 | int speed_p, i; |
b512946c | 1141 | df_ref uses; |
ce372372 JJ |
1142 | |
1143 | gcc_assert ((DF_REF_FLAGS (use) & DF_REF_IN_NOTE) == 0); | |
1144 | ||
1145 | src = SET_SRC (def_set); | |
1146 | use_pat = PATTERN (use_insn); | |
1147 | ||
1148 | /* In __asm don't replace if src might need more registers than | |
1149 | reg, as that could increase register pressure on the __asm. */ | |
b512946c RS |
1150 | uses = DF_INSN_USES (def_insn); |
1151 | if (uses && DF_REF_NEXT_LOC (uses)) | |
ce372372 JJ |
1152 | return false; |
1153 | ||
dc007c1f | 1154 | update_df_init (def_insn, use_insn); |
ce372372 JJ |
1155 | speed_p = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); |
1156 | asm_operands = NULL_RTX; | |
1157 | switch (GET_CODE (use_pat)) | |
1158 | { | |
1159 | case ASM_OPERANDS: | |
1160 | asm_operands = use_pat; | |
1161 | break; | |
1162 | case SET: | |
1163 | if (MEM_P (SET_DEST (use_pat))) | |
1164 | { | |
1165 | loc = &SET_DEST (use_pat); | |
1166 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p); | |
1167 | if (new_rtx) | |
1168 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1169 | } | |
1170 | asm_operands = SET_SRC (use_pat); | |
1171 | break; | |
1172 | case PARALLEL: | |
1173 | for (i = 0; i < XVECLEN (use_pat, 0); i++) | |
1174 | if (GET_CODE (XVECEXP (use_pat, 0, i)) == SET) | |
1175 | { | |
1176 | if (MEM_P (SET_DEST (XVECEXP (use_pat, 0, i)))) | |
1177 | { | |
1178 | loc = &SET_DEST (XVECEXP (use_pat, 0, i)); | |
1179 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, | |
1180 | src, speed_p); | |
1181 | if (new_rtx) | |
1182 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1183 | } | |
1184 | asm_operands = SET_SRC (XVECEXP (use_pat, 0, i)); | |
1185 | } | |
1186 | else if (GET_CODE (XVECEXP (use_pat, 0, i)) == ASM_OPERANDS) | |
1187 | asm_operands = XVECEXP (use_pat, 0, i); | |
1188 | break; | |
1189 | default: | |
1190 | gcc_unreachable (); | |
1191 | } | |
1192 | ||
1193 | gcc_assert (asm_operands && GET_CODE (asm_operands) == ASM_OPERANDS); | |
1194 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (asm_operands); i++) | |
1195 | { | |
1196 | loc = &ASM_OPERANDS_INPUT (asm_operands, i); | |
1197 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p); | |
1198 | if (new_rtx) | |
1199 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1200 | } | |
1201 | ||
1202 | if (num_changes_pending () == 0 || !apply_change_group ()) | |
1203 | return false; | |
1204 | ||
dc007c1f | 1205 | update_df (use_insn, NULL); |
ce372372 JJ |
1206 | num_changes++; |
1207 | return true; | |
1208 | } | |
1209 | ||
a52b023a PB |
1210 | /* Try to replace USE with SRC (defined in DEF_INSN) and simplify the |
1211 | result. */ | |
1212 | ||
1213 | static bool | |
d362bd85 | 1214 | forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set) |
a52b023a | 1215 | { |
d362bd85 | 1216 | rtx_insn *use_insn = DF_REF_INSN (use); |
a52b023a | 1217 | rtx use_set = single_set (use_insn); |
60564289 | 1218 | rtx src, reg, new_rtx, *loc; |
a52b023a | 1219 | bool set_reg_equal; |
ef4bddc2 | 1220 | machine_mode mode; |
ce372372 JJ |
1221 | int asm_use = -1; |
1222 | ||
1223 | if (INSN_CODE (use_insn) < 0) | |
1224 | asm_use = asm_noperands (PATTERN (use_insn)); | |
a52b023a | 1225 | |
b5b8b0ac | 1226 | if (!use_set && asm_use < 0 && !DEBUG_INSN_P (use_insn)) |
a52b023a PB |
1227 | return false; |
1228 | ||
1229 | /* Do not propagate into PC, CC0, etc. */ | |
ce372372 | 1230 | if (use_set && GET_MODE (SET_DEST (use_set)) == VOIDmode) |
a52b023a PB |
1231 | return false; |
1232 | ||
1233 | /* If def and use are subreg, check if they match. */ | |
1234 | reg = DF_REF_REG (use); | |
8e8af9b7 RS |
1235 | if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG) |
1236 | { | |
1237 | if (SUBREG_BYTE (SET_DEST (def_set)) != SUBREG_BYTE (reg)) | |
1238 | return false; | |
1239 | } | |
a52b023a | 1240 | /* Check if the def had a subreg, but the use has the whole reg. */ |
8e8af9b7 | 1241 | else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG) |
a52b023a | 1242 | return false; |
a52b023a PB |
1243 | /* Check if the use has a subreg, but the def had the whole reg. Unlike the |
1244 | previous case, the optimization is possible and often useful indeed. */ | |
8e8af9b7 | 1245 | else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set))) |
a52b023a PB |
1246 | reg = SUBREG_REG (reg); |
1247 | ||
8e8af9b7 RS |
1248 | /* Make sure that we can treat REG as having the same mode as the |
1249 | source of DEF_SET. */ | |
1250 | if (GET_MODE (SET_DEST (def_set)) != GET_MODE (reg)) | |
1251 | return false; | |
1252 | ||
a52b023a PB |
1253 | /* Check if the substitution is valid (last, because it's the most |
1254 | expensive check!). */ | |
1255 | src = SET_SRC (def_set); | |
1256 | if (!CONSTANT_P (src) && !all_uses_available_at (def_insn, use_insn)) | |
1257 | return false; | |
1258 | ||
1259 | /* Check if the def is loading something from the constant pool; in this | |
1260 | case we would undo optimization such as compress_float_constant. | |
1261 | Still, we can set a REG_EQUAL note. */ | |
1262 | if (MEM_P (src) && MEM_READONLY_P (src)) | |
1263 | { | |
1264 | rtx x = avoid_constant_pool_reference (src); | |
ce372372 | 1265 | if (x != src && use_set) |
a52b023a PB |
1266 | { |
1267 | rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
60564289 KG |
1268 | rtx old_rtx = note ? XEXP (note, 0) : SET_SRC (use_set); |
1269 | rtx new_rtx = simplify_replace_rtx (old_rtx, src, x); | |
1270 | if (old_rtx != new_rtx) | |
1271 | set_unique_reg_note (use_insn, REG_EQUAL, copy_rtx (new_rtx)); | |
a52b023a PB |
1272 | } |
1273 | return false; | |
1274 | } | |
1275 | ||
ce372372 JJ |
1276 | if (asm_use >= 0) |
1277 | return forward_propagate_asm (use, def_insn, def_set, reg); | |
1278 | ||
a52b023a PB |
1279 | /* Else try simplifying. */ |
1280 | ||
1281 | if (DF_REF_TYPE (use) == DF_REF_REG_MEM_STORE) | |
1282 | { | |
1283 | loc = &SET_DEST (use_set); | |
1284 | set_reg_equal = false; | |
1285 | } | |
b5b8b0ac AO |
1286 | else if (!use_set) |
1287 | { | |
1288 | loc = &INSN_VAR_LOCATION_LOC (use_insn); | |
1289 | set_reg_equal = false; | |
1290 | } | |
a52b023a PB |
1291 | else |
1292 | { | |
1293 | rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
1294 | if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE) | |
1295 | loc = &XEXP (note, 0); | |
1296 | else | |
1297 | loc = &SET_SRC (use_set); | |
6fb5fa3c | 1298 | |
a52b023a | 1299 | /* Do not replace an existing REG_EQUAL note if the insn is not |
2f434b97 OH |
1300 | recognized. Either we're already replacing in the note, or we'll |
1301 | separately try plugging the definition in the note and simplifying. | |
853f8f1c SB |
1302 | And only install a REQ_EQUAL note when the destination is a REG |
1303 | that isn't mentioned in USE_SET, as the note would be invalid | |
73dd3123 EB |
1304 | otherwise. We also don't want to install a note if we are merely |
1305 | propagating a pseudo since verifying that this pseudo isn't dead | |
1306 | is a pain; moreover such a note won't help anything. */ | |
1307 | set_reg_equal = (note == NULL_RTX | |
1308 | && REG_P (SET_DEST (use_set)) | |
1309 | && !REG_P (src) | |
1310 | && !(GET_CODE (src) == SUBREG | |
1311 | && REG_P (SUBREG_REG (src))) | |
1312 | && !reg_mentioned_p (SET_DEST (use_set), | |
1313 | SET_SRC (use_set))); | |
a52b023a PB |
1314 | } |
1315 | ||
1316 | if (GET_MODE (*loc) == VOIDmode) | |
1317 | mode = GET_MODE (SET_DEST (use_set)); | |
1318 | else | |
1319 | mode = GET_MODE (*loc); | |
1320 | ||
f40751dd JH |
1321 | new_rtx = propagate_rtx (*loc, mode, reg, src, |
1322 | optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn))); | |
6fb5fa3c | 1323 | |
60564289 | 1324 | if (!new_rtx) |
a52b023a PB |
1325 | return false; |
1326 | ||
60564289 | 1327 | return try_fwprop_subst (use, loc, new_rtx, def_insn, set_reg_equal); |
a52b023a PB |
1328 | } |
1329 | ||
1330 | ||
1331 | /* Given a use USE of an insn, if it has a single reaching | |
7360d2ac JJ |
1332 | definition, try to forward propagate it into that insn. |
1333 | Return true if cfg cleanup will be needed. */ | |
a52b023a | 1334 | |
7360d2ac | 1335 | static bool |
57512f53 | 1336 | forward_propagate_into (df_ref use) |
a52b023a | 1337 | { |
57512f53 | 1338 | df_ref def; |
d362bd85 DM |
1339 | rtx_insn *def_insn, *use_insn; |
1340 | rtx def_set; | |
6fb5fa3c | 1341 | rtx parent; |
a52b023a PB |
1342 | |
1343 | if (DF_REF_FLAGS (use) & DF_REF_READ_WRITE) | |
7360d2ac | 1344 | return false; |
6fb5fa3c | 1345 | if (DF_REF_IS_ARTIFICIAL (use)) |
7360d2ac | 1346 | return false; |
a52b023a PB |
1347 | |
1348 | /* Only consider uses that have a single definition. */ | |
00952e97 PB |
1349 | def = get_def_for_use (use); |
1350 | if (!def) | |
7360d2ac | 1351 | return false; |
a52b023a | 1352 | if (DF_REF_FLAGS (def) & DF_REF_READ_WRITE) |
7360d2ac | 1353 | return false; |
6fb5fa3c | 1354 | if (DF_REF_IS_ARTIFICIAL (def)) |
7360d2ac | 1355 | return false; |
a52b023a | 1356 | |
fb406162 PB |
1357 | /* Do not propagate loop invariant definitions inside the loop. */ |
1358 | if (DF_REF_BB (def)->loop_father != DF_REF_BB (use)->loop_father) | |
7360d2ac | 1359 | return false; |
a52b023a PB |
1360 | |
1361 | /* Check if the use is still present in the insn! */ | |
1362 | use_insn = DF_REF_INSN (use); | |
1363 | if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE) | |
1364 | parent = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
1365 | else | |
1366 | parent = PATTERN (use_insn); | |
1367 | ||
4fefbcdb | 1368 | if (!reg_mentioned_p (DF_REF_REG (use), parent)) |
7360d2ac | 1369 | return false; |
a52b023a PB |
1370 | |
1371 | def_insn = DF_REF_INSN (def); | |
6fb5fa3c | 1372 | if (multiple_sets (def_insn)) |
7360d2ac | 1373 | return false; |
a52b023a PB |
1374 | def_set = single_set (def_insn); |
1375 | if (!def_set) | |
7360d2ac | 1376 | return false; |
a52b023a PB |
1377 | |
1378 | /* Only try one kind of propagation. If two are possible, we'll | |
1379 | do it on the following iterations. */ | |
7360d2ac JJ |
1380 | if (forward_propagate_and_simplify (use, def_insn, def_set) |
1381 | || forward_propagate_subreg (use, def_insn, def_set)) | |
1382 | { | |
1383 | if (cfun->can_throw_non_call_exceptions | |
1384 | && find_reg_note (use_insn, REG_EH_REGION, NULL_RTX) | |
1385 | && purge_dead_edges (DF_REF_BB (use))) | |
1386 | return true; | |
1387 | } | |
1388 | return false; | |
a52b023a PB |
1389 | } |
1390 | ||
1391 | \f | |
1392 | static void | |
1393 | fwprop_init (void) | |
1394 | { | |
1395 | num_changes = 0; | |
6e0b633f | 1396 | calculate_dominance_info (CDI_DOMINATORS); |
a52b023a PB |
1397 | |
1398 | /* We do not always want to propagate into loops, so we have to find | |
c5f4be84 SB |
1399 | loops and be careful about them. Avoid CFG modifications so that |
1400 | we don't have to update dominance information afterwards for | |
1401 | build_single_def_use_links. */ | |
1402 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
a52b023a | 1403 | |
00952e97 | 1404 | build_single_def_use_links (); |
6fb5fa3c | 1405 | df_set_flags (DF_DEFER_INSN_RESCAN); |
dc007c1f PB |
1406 | |
1407 | active_defs = XNEWVEC (df_ref, max_reg_num ()); | |
1408 | #ifdef ENABLE_CHECKING | |
1409 | active_defs_check = sparseset_alloc (max_reg_num ()); | |
1410 | #endif | |
a52b023a PB |
1411 | } |
1412 | ||
1413 | static void | |
1414 | fwprop_done (void) | |
1415 | { | |
fb406162 | 1416 | loop_optimizer_finalize (); |
6fb5fa3c | 1417 | |
9771b263 | 1418 | use_def_ref.release (); |
dc007c1f PB |
1419 | free (active_defs); |
1420 | #ifdef ENABLE_CHECKING | |
1421 | sparseset_free (active_defs_check); | |
1422 | #endif | |
1423 | ||
6e0b633f | 1424 | free_dominance_info (CDI_DOMINATORS); |
a52b023a PB |
1425 | cleanup_cfg (0); |
1426 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); | |
1427 | ||
1428 | if (dump_file) | |
1429 | fprintf (dump_file, | |
1430 | "\nNumber of successful forward propagations: %d\n\n", | |
1431 | num_changes); | |
1432 | } | |
1433 | ||
1434 | ||
a52b023a PB |
1435 | /* Main entry point. */ |
1436 | ||
1437 | static bool | |
1438 | gate_fwprop (void) | |
1439 | { | |
1440 | return optimize > 0 && flag_forward_propagate; | |
1441 | } | |
1442 | ||
1443 | static unsigned int | |
1444 | fwprop (void) | |
1445 | { | |
1446 | unsigned i; | |
7360d2ac | 1447 | bool need_cleanup = false; |
a52b023a PB |
1448 | |
1449 | fwprop_init (); | |
1450 | ||
dc007c1f | 1451 | /* Go through all the uses. df_uses_create will create new ones at the |
a52b023a PB |
1452 | end, and we'll go through them as well. |
1453 | ||
1454 | Do not forward propagate addresses into loops until after unrolling. | |
1455 | CSE did so because it was able to fix its own mess, but we are not. */ | |
1456 | ||
6fb5fa3c | 1457 | for (i = 0; i < DF_USES_TABLE_SIZE (); i++) |
a52b023a | 1458 | { |
57512f53 | 1459 | df_ref use = DF_USES_GET (i); |
a52b023a | 1460 | if (use) |
fb406162 | 1461 | if (DF_REF_TYPE (use) == DF_REF_REG_USE |
24713e85 AP |
1462 | || DF_REF_BB (use)->loop_father == NULL |
1463 | /* The outer most loop is not really a loop. */ | |
1464 | || loop_outer (DF_REF_BB (use)->loop_father) == NULL) | |
7360d2ac | 1465 | need_cleanup |= forward_propagate_into (use); |
a52b023a PB |
1466 | } |
1467 | ||
1468 | fwprop_done (); | |
7360d2ac JJ |
1469 | if (need_cleanup) |
1470 | cleanup_cfg (0); | |
a52b023a PB |
1471 | return 0; |
1472 | } | |
1473 | ||
27a4cd48 DM |
1474 | namespace { |
1475 | ||
1476 | const pass_data pass_data_rtl_fwprop = | |
a52b023a | 1477 | { |
27a4cd48 DM |
1478 | RTL_PASS, /* type */ |
1479 | "fwprop1", /* name */ | |
1480 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1481 | TV_FWPROP, /* tv_id */ |
1482 | 0, /* properties_required */ | |
1483 | 0, /* properties_provided */ | |
1484 | 0, /* properties_destroyed */ | |
1485 | 0, /* todo_flags_start */ | |
3bea341f | 1486 | TODO_df_finish, /* todo_flags_finish */ |
a52b023a PB |
1487 | }; |
1488 | ||
27a4cd48 DM |
1489 | class pass_rtl_fwprop : public rtl_opt_pass |
1490 | { | |
1491 | public: | |
c3284718 RS |
1492 | pass_rtl_fwprop (gcc::context *ctxt) |
1493 | : rtl_opt_pass (pass_data_rtl_fwprop, ctxt) | |
27a4cd48 DM |
1494 | {} |
1495 | ||
1496 | /* opt_pass methods: */ | |
1a3d085c | 1497 | virtual bool gate (function *) { return gate_fwprop (); } |
be55bfe6 | 1498 | virtual unsigned int execute (function *) { return fwprop (); } |
27a4cd48 DM |
1499 | |
1500 | }; // class pass_rtl_fwprop | |
1501 | ||
1502 | } // anon namespace | |
1503 | ||
1504 | rtl_opt_pass * | |
1505 | make_pass_rtl_fwprop (gcc::context *ctxt) | |
1506 | { | |
1507 | return new pass_rtl_fwprop (ctxt); | |
1508 | } | |
1509 | ||
a52b023a PB |
1510 | static unsigned int |
1511 | fwprop_addr (void) | |
1512 | { | |
1513 | unsigned i; | |
7360d2ac JJ |
1514 | bool need_cleanup = false; |
1515 | ||
a52b023a PB |
1516 | fwprop_init (); |
1517 | ||
dc007c1f | 1518 | /* Go through all the uses. df_uses_create will create new ones at the |
a52b023a | 1519 | end, and we'll go through them as well. */ |
6fb5fa3c | 1520 | for (i = 0; i < DF_USES_TABLE_SIZE (); i++) |
a52b023a | 1521 | { |
57512f53 | 1522 | df_ref use = DF_USES_GET (i); |
a52b023a PB |
1523 | if (use) |
1524 | if (DF_REF_TYPE (use) != DF_REF_REG_USE | |
24713e85 AP |
1525 | && DF_REF_BB (use)->loop_father != NULL |
1526 | /* The outer most loop is not really a loop. */ | |
1527 | && loop_outer (DF_REF_BB (use)->loop_father) != NULL) | |
7360d2ac | 1528 | need_cleanup |= forward_propagate_into (use); |
a52b023a PB |
1529 | } |
1530 | ||
1531 | fwprop_done (); | |
1532 | ||
7360d2ac JJ |
1533 | if (need_cleanup) |
1534 | cleanup_cfg (0); | |
a52b023a PB |
1535 | return 0; |
1536 | } | |
1537 | ||
27a4cd48 DM |
1538 | namespace { |
1539 | ||
1540 | const pass_data pass_data_rtl_fwprop_addr = | |
a52b023a | 1541 | { |
27a4cd48 DM |
1542 | RTL_PASS, /* type */ |
1543 | "fwprop2", /* name */ | |
1544 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
1545 | TV_FWPROP, /* tv_id */ |
1546 | 0, /* properties_required */ | |
1547 | 0, /* properties_provided */ | |
1548 | 0, /* properties_destroyed */ | |
1549 | 0, /* todo_flags_start */ | |
3bea341f | 1550 | TODO_df_finish, /* todo_flags_finish */ |
a52b023a | 1551 | }; |
27a4cd48 DM |
1552 | |
1553 | class pass_rtl_fwprop_addr : public rtl_opt_pass | |
1554 | { | |
1555 | public: | |
c3284718 RS |
1556 | pass_rtl_fwprop_addr (gcc::context *ctxt) |
1557 | : rtl_opt_pass (pass_data_rtl_fwprop_addr, ctxt) | |
27a4cd48 DM |
1558 | {} |
1559 | ||
1560 | /* opt_pass methods: */ | |
1a3d085c | 1561 | virtual bool gate (function *) { return gate_fwprop (); } |
be55bfe6 | 1562 | virtual unsigned int execute (function *) { return fwprop_addr (); } |
27a4cd48 DM |
1563 | |
1564 | }; // class pass_rtl_fwprop_addr | |
1565 | ||
1566 | } // anon namespace | |
1567 | ||
1568 | rtl_opt_pass * | |
1569 | make_pass_rtl_fwprop_addr (gcc::context *ctxt) | |
1570 | { | |
1571 | return new pass_rtl_fwprop_addr (ctxt); | |
1572 | } |