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42a3a38b | 1 | /* RTL-based forward propagation pass for GNU compiler. |
711789cc | 2 | Copyright (C) 2005-2013 Free Software Foundation, Inc. |
42a3a38b | 3 | Contributed by Paolo Bonzini and Steven Bosscher. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 9 | Software Foundation; either version 3, or (at your option) any later |
42a3a38b | 10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
42a3a38b | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
0b205f4c | 25 | #include "diagnostic-core.h" |
42a3a38b | 26 | |
4ffe0526 | 27 | #include "sparseset.h" |
42a3a38b | 28 | #include "rtl.h" |
29 | #include "tm_p.h" | |
42a3a38b | 30 | #include "insn-config.h" |
31 | #include "recog.h" | |
32 | #include "flags.h" | |
33 | #include "obstack.h" | |
34 | #include "basic-block.h" | |
42a3a38b | 35 | #include "df.h" |
36 | #include "target.h" | |
37 | #include "cfgloop.h" | |
38 | #include "tree-pass.h" | |
2355a966 | 39 | #include "domwalk.h" |
06f9d6ef | 40 | #include "emit-rtl.h" |
42a3a38b | 41 | |
42 | ||
43 | /* This pass does simple forward propagation and simplification when an | |
44 | operand of an insn can only come from a single def. This pass uses | |
45 | df.c, so it is global. However, we only do limited analysis of | |
46 | available expressions. | |
47 | ||
48 | 1) The pass tries to propagate the source of the def into the use, | |
49 | and checks if the result is independent of the substituted value. | |
50 | For example, the high word of a (zero_extend:DI (reg:SI M)) is always | |
51 | zero, independent of the source register. | |
52 | ||
53 | In particular, we propagate constants into the use site. Sometimes | |
54 | RTL expansion did not put the constant in the same insn on purpose, | |
55 | to satisfy a predicate, and the result will fail to be recognized; | |
56 | but this happens rarely and in this case we can still create a | |
57 | REG_EQUAL note. For multi-word operations, this | |
58 | ||
59 | (set (subreg:SI (reg:DI 120) 0) (const_int 0)) | |
60 | (set (subreg:SI (reg:DI 120) 4) (const_int -1)) | |
61 | (set (subreg:SI (reg:DI 122) 0) | |
62 | (ior:SI (subreg:SI (reg:DI 119) 0) (subreg:SI (reg:DI 120) 0))) | |
63 | (set (subreg:SI (reg:DI 122) 4) | |
64 | (ior:SI (subreg:SI (reg:DI 119) 4) (subreg:SI (reg:DI 120) 4))) | |
65 | ||
66 | can be simplified to the much simpler | |
67 | ||
68 | (set (subreg:SI (reg:DI 122) 0) (subreg:SI (reg:DI 119))) | |
69 | (set (subreg:SI (reg:DI 122) 4) (const_int -1)) | |
70 | ||
71 | This particular propagation is also effective at putting together | |
72 | complex addressing modes. We are more aggressive inside MEMs, in | |
73 | that all definitions are propagated if the use is in a MEM; if the | |
74 | result is a valid memory address we check address_cost to decide | |
75 | whether the substitution is worthwhile. | |
76 | ||
77 | 2) The pass propagates register copies. This is not as effective as | |
78 | the copy propagation done by CSE's canon_reg, which works by walking | |
79 | the instruction chain, it can help the other transformations. | |
80 | ||
81 | We should consider removing this optimization, and instead reorder the | |
82 | RTL passes, because GCSE does this transformation too. With some luck, | |
83 | the CSE pass at the end of rest_of_handle_gcse could also go away. | |
84 | ||
85 | 3) The pass looks for paradoxical subregs that are actually unnecessary. | |
86 | Things like this: | |
87 | ||
88 | (set (reg:QI 120) (subreg:QI (reg:SI 118) 0)) | |
89 | (set (reg:QI 121) (subreg:QI (reg:SI 119) 0)) | |
90 | (set (reg:SI 122) (plus:SI (subreg:SI (reg:QI 120) 0) | |
91 | (subreg:SI (reg:QI 121) 0))) | |
92 | ||
93 | are very common on machines that can only do word-sized operations. | |
94 | For each use of a paradoxical subreg (subreg:WIDER (reg:NARROW N) 0), | |
95 | if it has a single def and it is (subreg:NARROW (reg:WIDE M) 0), | |
96 | we can replace the paradoxical subreg with simply (reg:WIDE M). The | |
97 | above will simplify this to | |
98 | ||
99 | (set (reg:QI 120) (subreg:QI (reg:SI 118) 0)) | |
100 | (set (reg:QI 121) (subreg:QI (reg:SI 119) 0)) | |
101 | (set (reg:SI 122) (plus:SI (reg:SI 118) (reg:SI 119))) | |
102 | ||
2355a966 | 103 | where the first two insns are now dead. |
104 | ||
105 | We used to use reaching definitions to find which uses have a | |
106 | single reaching definition (sounds obvious...), but this is too | |
107 | complex a problem in nasty testcases like PR33928. Now we use the | |
108 | multiple definitions problem in df-problems.c. The similarity | |
109 | between that problem and SSA form creation is taken further, in | |
110 | that fwprop does a dominator walk to create its chains; however, | |
111 | instead of creating a PHI function where multiple definitions meet | |
112 | I just punt and record only singleton use-def chains, which is | |
113 | all that is needed by fwprop. */ | |
42a3a38b | 114 | |
115 | ||
42a3a38b | 116 | static int num_changes; |
117 | ||
f1f41a6c | 118 | static vec<df_ref> use_def_ref; |
119 | static vec<df_ref> reg_defs; | |
120 | static vec<df_ref> reg_defs_stack; | |
e0bd4156 | 121 | |
426e6c73 | 122 | /* The MD bitmaps are trimmed to include only live registers to cut |
123 | memory usage on testcases like insn-recog.c. Track live registers | |
124 | in the basic block and do not perform forward propagation if the | |
125 | destination is a dead pseudo occurring in a note. */ | |
126 | static bitmap local_md; | |
127 | static bitmap local_lr; | |
e0bd4156 | 128 | |
129 | /* Return the only def in USE's use-def chain, or NULL if there is | |
130 | more than one def in the chain. */ | |
131 | ||
132 | static inline df_ref | |
133 | get_def_for_use (df_ref use) | |
134 | { | |
f1f41a6c | 135 | return use_def_ref[DF_REF_ID (use)]; |
e0bd4156 | 136 | } |
137 | ||
138 | ||
2355a966 | 139 | /* Update the reg_defs vector with non-partial definitions in DEF_REC. |
140 | TOP_FLAG says which artificials uses should be used, when DEF_REC | |
141 | is an artificial def vector. LOCAL_MD is modified as after a | |
142 | df_md_simulate_* function; we do more or less the same processing | |
143 | done there, so we do not use those functions. */ | |
144 | ||
145 | #define DF_MD_GEN_FLAGS \ | |
146 | (DF_REF_PARTIAL | DF_REF_CONDITIONAL | DF_REF_MAY_CLOBBER) | |
e0bd4156 | 147 | |
2355a966 | 148 | static void |
426e6c73 | 149 | process_defs (df_ref *def_rec, int top_flag) |
e0bd4156 | 150 | { |
2355a966 | 151 | df_ref def; |
152 | while ((def = *def_rec++) != NULL) | |
153 | { | |
f1f41a6c | 154 | df_ref curr_def = reg_defs[DF_REF_REGNO (def)]; |
2355a966 | 155 | unsigned int dregno; |
e0bd4156 | 156 | |
2355a966 | 157 | if ((DF_REF_FLAGS (def) & DF_REF_AT_TOP) != top_flag) |
158 | continue; | |
e0bd4156 | 159 | |
2355a966 | 160 | dregno = DF_REF_REGNO (def); |
161 | if (curr_def) | |
f1f41a6c | 162 | reg_defs_stack.safe_push (curr_def); |
2355a966 | 163 | else |
164 | { | |
165 | /* Do not store anything if "transitioning" from NULL to NULL. But | |
166 | otherwise, push a special entry on the stack to tell the | |
167 | leave_block callback that the entry in reg_defs was NULL. */ | |
168 | if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS) | |
169 | ; | |
170 | else | |
f1f41a6c | 171 | reg_defs_stack.safe_push (def); |
2355a966 | 172 | } |
173 | ||
174 | if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS) | |
175 | { | |
176 | bitmap_set_bit (local_md, dregno); | |
f1f41a6c | 177 | reg_defs[dregno] = NULL; |
2355a966 | 178 | } |
179 | else | |
180 | { | |
181 | bitmap_clear_bit (local_md, dregno); | |
f1f41a6c | 182 | reg_defs[dregno] = def; |
2355a966 | 183 | } |
e0bd4156 | 184 | } |
e0bd4156 | 185 | } |
186 | ||
187 | ||
188 | /* Fill the use_def_ref vector with values for the uses in USE_REC, | |
2355a966 | 189 | taking reaching definitions info from LOCAL_MD and REG_DEFS. |
190 | TOP_FLAG says which artificials uses should be used, when USE_REC | |
191 | is an artificial use vector. */ | |
e0bd4156 | 192 | |
193 | static void | |
426e6c73 | 194 | process_uses (df_ref *use_rec, int top_flag) |
e0bd4156 | 195 | { |
196 | df_ref use; | |
197 | while ((use = *use_rec++) != NULL) | |
2355a966 | 198 | if ((DF_REF_FLAGS (use) & DF_REF_AT_TOP) == top_flag) |
e0bd4156 | 199 | { |
2355a966 | 200 | unsigned int uregno = DF_REF_REGNO (use); |
f1f41a6c | 201 | if (reg_defs[uregno] |
426e6c73 | 202 | && !bitmap_bit_p (local_md, uregno) |
203 | && bitmap_bit_p (local_lr, uregno)) | |
f1f41a6c | 204 | use_def_ref[DF_REF_ID (use)] = reg_defs[uregno]; |
2355a966 | 205 | } |
206 | } | |
207 | ||
e0bd4156 | 208 | |
2355a966 | 209 | static void |
426e6c73 | 210 | single_def_use_enter_block (struct dom_walk_data *walk_data ATTRIBUTE_UNUSED, |
211 | basic_block bb) | |
2355a966 | 212 | { |
2355a966 | 213 | int bb_index = bb->index; |
426e6c73 | 214 | struct df_md_bb_info *md_bb_info = df_md_get_bb_info (bb_index); |
215 | struct df_lr_bb_info *lr_bb_info = df_lr_get_bb_info (bb_index); | |
2355a966 | 216 | rtx insn; |
217 | ||
f53d14b1 | 218 | bitmap_copy (local_md, &md_bb_info->in); |
219 | bitmap_copy (local_lr, &lr_bb_info->in); | |
2355a966 | 220 | |
221 | /* Push a marker for the leave_block callback. */ | |
f1f41a6c | 222 | reg_defs_stack.safe_push (NULL); |
2355a966 | 223 | |
426e6c73 | 224 | process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP); |
225 | process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP); | |
330ce56e | 226 | |
227 | /* We don't call df_simulate_initialize_forwards, as it may overestimate | |
228 | the live registers if there are unused artificial defs. We prefer | |
229 | liveness to be underestimated. */ | |
2355a966 | 230 | |
231 | FOR_BB_INSNS (bb, insn) | |
232 | if (INSN_P (insn)) | |
233 | { | |
234 | unsigned int uid = INSN_UID (insn); | |
426e6c73 | 235 | process_uses (DF_INSN_UID_USES (uid), 0); |
236 | process_uses (DF_INSN_UID_EQ_USES (uid), 0); | |
237 | process_defs (DF_INSN_UID_DEFS (uid), 0); | |
238 | df_simulate_one_insn_forwards (bb, insn, local_lr); | |
e0bd4156 | 239 | } |
2355a966 | 240 | |
426e6c73 | 241 | process_uses (df_get_artificial_uses (bb_index), 0); |
242 | process_defs (df_get_artificial_defs (bb_index), 0); | |
2355a966 | 243 | } |
244 | ||
245 | /* Pop the definitions created in this basic block when leaving its | |
246 | dominated parts. */ | |
247 | ||
248 | static void | |
249 | single_def_use_leave_block (struct dom_walk_data *walk_data ATTRIBUTE_UNUSED, | |
250 | basic_block bb ATTRIBUTE_UNUSED) | |
251 | { | |
252 | df_ref saved_def; | |
f1f41a6c | 253 | while ((saved_def = reg_defs_stack.pop ()) != NULL) |
2355a966 | 254 | { |
255 | unsigned int dregno = DF_REF_REGNO (saved_def); | |
256 | ||
257 | /* See also process_defs. */ | |
f1f41a6c | 258 | if (saved_def == reg_defs[dregno]) |
259 | reg_defs[dregno] = NULL; | |
2355a966 | 260 | else |
f1f41a6c | 261 | reg_defs[dregno] = saved_def; |
2355a966 | 262 | } |
e0bd4156 | 263 | } |
264 | ||
265 | ||
2355a966 | 266 | /* Build a vector holding the reaching definitions of uses reached by a |
267 | single dominating definition. */ | |
e0bd4156 | 268 | |
269 | static void | |
270 | build_single_def_use_links (void) | |
271 | { | |
2355a966 | 272 | struct dom_walk_data walk_data; |
e0bd4156 | 273 | |
2355a966 | 274 | /* We use the multiple definitions problem to compute our restricted |
275 | use-def chains. */ | |
e0bd4156 | 276 | df_set_flags (DF_EQ_NOTES); |
2355a966 | 277 | df_md_add_problem (); |
426e6c73 | 278 | df_note_add_problem (); |
e0bd4156 | 279 | df_analyze (); |
280 | df_maybe_reorganize_use_refs (DF_REF_ORDER_BY_INSN_WITH_NOTES); | |
281 | ||
f1f41a6c | 282 | use_def_ref.create (DF_USES_TABLE_SIZE ()); |
283 | use_def_ref.safe_grow_cleared (DF_USES_TABLE_SIZE ()); | |
e0bd4156 | 284 | |
f1f41a6c | 285 | reg_defs.create (max_reg_num ()); |
286 | reg_defs.safe_grow_cleared (max_reg_num ()); | |
e0bd4156 | 287 | |
f1f41a6c | 288 | reg_defs_stack.create (n_basic_blocks * 10); |
2355a966 | 289 | local_md = BITMAP_ALLOC (NULL); |
426e6c73 | 290 | local_lr = BITMAP_ALLOC (NULL); |
2355a966 | 291 | |
292 | /* Walk the dominator tree looking for single reaching definitions | |
293 | dominating the uses. This is similar to how SSA form is built. */ | |
294 | walk_data.dom_direction = CDI_DOMINATORS; | |
295 | walk_data.initialize_block_local_data = NULL; | |
296 | walk_data.before_dom_children = single_def_use_enter_block; | |
297 | walk_data.after_dom_children = single_def_use_leave_block; | |
e0bd4156 | 298 | |
2355a966 | 299 | init_walk_dominator_tree (&walk_data); |
300 | walk_dominator_tree (&walk_data, ENTRY_BLOCK_PTR); | |
301 | fini_walk_dominator_tree (&walk_data); | |
302 | ||
426e6c73 | 303 | BITMAP_FREE (local_lr); |
2355a966 | 304 | BITMAP_FREE (local_md); |
f1f41a6c | 305 | reg_defs.release (); |
306 | reg_defs_stack.release (); | |
e0bd4156 | 307 | } |
2355a966 | 308 | |
42a3a38b | 309 | \f |
310 | /* Do not try to replace constant addresses or addresses of local and | |
311 | argument slots. These MEM expressions are made only once and inserted | |
312 | in many instructions, as well as being used to control symbol table | |
313 | output. It is not safe to clobber them. | |
314 | ||
315 | There are some uncommon cases where the address is already in a register | |
316 | for some reason, but we cannot take advantage of that because we have | |
317 | no easy way to unshare the MEM. In addition, looking up all stack | |
318 | addresses is costly. */ | |
319 | ||
320 | static bool | |
321 | can_simplify_addr (rtx addr) | |
322 | { | |
323 | rtx reg; | |
324 | ||
325 | if (CONSTANT_ADDRESS_P (addr)) | |
326 | return false; | |
327 | ||
328 | if (GET_CODE (addr) == PLUS) | |
329 | reg = XEXP (addr, 0); | |
330 | else | |
331 | reg = addr; | |
332 | ||
333 | return (!REG_P (reg) | |
334 | || (REGNO (reg) != FRAME_POINTER_REGNUM | |
335 | && REGNO (reg) != HARD_FRAME_POINTER_REGNUM | |
336 | && REGNO (reg) != ARG_POINTER_REGNUM)); | |
337 | } | |
338 | ||
339 | /* Returns a canonical version of X for the address, from the point of view, | |
340 | that all multiplications are represented as MULT instead of the multiply | |
341 | by a power of 2 being represented as ASHIFT. | |
342 | ||
343 | Every ASHIFT we find has been made by simplify_gen_binary and was not | |
344 | there before, so it is not shared. So we can do this in place. */ | |
345 | ||
346 | static void | |
347 | canonicalize_address (rtx x) | |
348 | { | |
349 | for (;;) | |
350 | switch (GET_CODE (x)) | |
351 | { | |
352 | case ASHIFT: | |
971ba038 | 353 | if (CONST_INT_P (XEXP (x, 1)) |
42a3a38b | 354 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (GET_MODE (x)) |
355 | && INTVAL (XEXP (x, 1)) >= 0) | |
356 | { | |
357 | HOST_WIDE_INT shift = INTVAL (XEXP (x, 1)); | |
358 | PUT_CODE (x, MULT); | |
359 | XEXP (x, 1) = gen_int_mode ((HOST_WIDE_INT) 1 << shift, | |
360 | GET_MODE (x)); | |
361 | } | |
362 | ||
363 | x = XEXP (x, 0); | |
364 | break; | |
365 | ||
366 | case PLUS: | |
367 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
368 | || GET_CODE (XEXP (x, 0)) == ASHIFT | |
369 | || GET_CODE (XEXP (x, 0)) == CONST) | |
370 | canonicalize_address (XEXP (x, 0)); | |
371 | ||
372 | x = XEXP (x, 1); | |
373 | break; | |
374 | ||
375 | case CONST: | |
376 | x = XEXP (x, 0); | |
377 | break; | |
378 | ||
379 | default: | |
380 | return; | |
381 | } | |
382 | } | |
383 | ||
384 | /* OLD is a memory address. Return whether it is good to use NEW instead, | |
385 | for a memory access in the given MODE. */ | |
386 | ||
387 | static bool | |
f529eb25 | 388 | should_replace_address (rtx old_rtx, rtx new_rtx, enum machine_mode mode, |
bd1a81f7 | 389 | addr_space_t as, bool speed) |
42a3a38b | 390 | { |
391 | int gain; | |
392 | ||
bd1a81f7 | 393 | if (rtx_equal_p (old_rtx, new_rtx) |
394 | || !memory_address_addr_space_p (mode, new_rtx, as)) | |
42a3a38b | 395 | return false; |
396 | ||
397 | /* Copy propagation is always ok. */ | |
9ce37fa7 | 398 | if (REG_P (old_rtx) && REG_P (new_rtx)) |
42a3a38b | 399 | return true; |
400 | ||
401 | /* Prefer the new address if it is less expensive. */ | |
bd1a81f7 | 402 | gain = (address_cost (old_rtx, mode, as, speed) |
403 | - address_cost (new_rtx, mode, as, speed)); | |
42a3a38b | 404 | |
405 | /* If the addresses have equivalent cost, prefer the new address | |
7013e87c | 406 | if it has the highest `set_src_cost'. That has the potential of |
42a3a38b | 407 | eliminating the most insns without additional costs, and it |
408 | is the same that cse.c used to do. */ | |
409 | if (gain == 0) | |
7013e87c | 410 | gain = set_src_cost (new_rtx, speed) - set_src_cost (old_rtx, speed); |
42a3a38b | 411 | |
412 | return (gain > 0); | |
413 | } | |
414 | ||
f8f13645 | 415 | |
416 | /* Flags for the last parameter of propagate_rtx_1. */ | |
417 | ||
418 | enum { | |
419 | /* If PR_CAN_APPEAR is true, propagate_rtx_1 always returns true; | |
420 | if it is false, propagate_rtx_1 returns false if, for at least | |
421 | one occurrence OLD, it failed to collapse the result to a constant. | |
422 | For example, (mult:M (reg:M A) (minus:M (reg:M B) (reg:M A))) may | |
423 | collapse to zero if replacing (reg:M B) with (reg:M A). | |
424 | ||
425 | PR_CAN_APPEAR is disregarded inside MEMs: in that case, | |
426 | propagate_rtx_1 just tries to make cheaper and valid memory | |
427 | addresses. */ | |
428 | PR_CAN_APPEAR = 1, | |
429 | ||
430 | /* If PR_HANDLE_MEM is not set, propagate_rtx_1 won't attempt any replacement | |
431 | outside memory addresses. This is needed because propagate_rtx_1 does | |
432 | not do any analysis on memory; thus it is very conservative and in general | |
433 | it will fail if non-read-only MEMs are found in the source expression. | |
434 | ||
435 | PR_HANDLE_MEM is set when the source of the propagation was not | |
436 | another MEM. Then, it is safe not to treat non-read-only MEMs as | |
437 | ``opaque'' objects. */ | |
f529eb25 | 438 | PR_HANDLE_MEM = 2, |
439 | ||
440 | /* Set when costs should be optimized for speed. */ | |
441 | PR_OPTIMIZE_FOR_SPEED = 4 | |
f8f13645 | 442 | }; |
443 | ||
444 | ||
42a3a38b | 445 | /* Replace all occurrences of OLD in *PX with NEW and try to simplify the |
446 | resulting expression. Replace *PX with a new RTL expression if an | |
447 | occurrence of OLD was found. | |
448 | ||
42a3a38b | 449 | This is only a wrapper around simplify-rtx.c: do not add any pattern |
450 | matching code here. (The sole exception is the handling of LO_SUM, but | |
451 | that is because there is no simplify_gen_* function for LO_SUM). */ | |
452 | ||
453 | static bool | |
9ce37fa7 | 454 | propagate_rtx_1 (rtx *px, rtx old_rtx, rtx new_rtx, int flags) |
42a3a38b | 455 | { |
456 | rtx x = *px, tem = NULL_RTX, op0, op1, op2; | |
457 | enum rtx_code code = GET_CODE (x); | |
458 | enum machine_mode mode = GET_MODE (x); | |
459 | enum machine_mode op_mode; | |
f8f13645 | 460 | bool can_appear = (flags & PR_CAN_APPEAR) != 0; |
42a3a38b | 461 | bool valid_ops = true; |
462 | ||
f8f13645 | 463 | if (!(flags & PR_HANDLE_MEM) && MEM_P (x) && !MEM_READONLY_P (x)) |
464 | { | |
465 | /* If unsafe, change MEMs to CLOBBERs or SCRATCHes (to preserve whether | |
466 | they have side effects or not). */ | |
467 | *px = (side_effects_p (x) | |
468 | ? gen_rtx_CLOBBER (GET_MODE (x), const0_rtx) | |
469 | : gen_rtx_SCRATCH (GET_MODE (x))); | |
470 | return false; | |
471 | } | |
42a3a38b | 472 | |
f8f13645 | 473 | /* If X is OLD_RTX, return NEW_RTX. But not if replacing only within an |
474 | address, and we are *not* inside one. */ | |
9ce37fa7 | 475 | if (x == old_rtx) |
42a3a38b | 476 | { |
9ce37fa7 | 477 | *px = new_rtx; |
42a3a38b | 478 | return can_appear; |
479 | } | |
480 | ||
f8f13645 | 481 | /* If this is an expression, try recursive substitution. */ |
42a3a38b | 482 | switch (GET_RTX_CLASS (code)) |
483 | { | |
484 | case RTX_UNARY: | |
485 | op0 = XEXP (x, 0); | |
486 | op_mode = GET_MODE (op0); | |
9ce37fa7 | 487 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
42a3a38b | 488 | if (op0 == XEXP (x, 0)) |
489 | return true; | |
490 | tem = simplify_gen_unary (code, mode, op0, op_mode); | |
491 | break; | |
492 | ||
493 | case RTX_BIN_ARITH: | |
494 | case RTX_COMM_ARITH: | |
495 | op0 = XEXP (x, 0); | |
496 | op1 = XEXP (x, 1); | |
9ce37fa7 | 497 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
498 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
42a3a38b | 499 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
500 | return true; | |
501 | tem = simplify_gen_binary (code, mode, op0, op1); | |
502 | break; | |
503 | ||
504 | case RTX_COMPARE: | |
505 | case RTX_COMM_COMPARE: | |
506 | op0 = XEXP (x, 0); | |
507 | op1 = XEXP (x, 1); | |
508 | op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1); | |
9ce37fa7 | 509 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
510 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
42a3a38b | 511 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
512 | return true; | |
513 | tem = simplify_gen_relational (code, mode, op_mode, op0, op1); | |
514 | break; | |
515 | ||
516 | case RTX_TERNARY: | |
517 | case RTX_BITFIELD_OPS: | |
518 | op0 = XEXP (x, 0); | |
519 | op1 = XEXP (x, 1); | |
520 | op2 = XEXP (x, 2); | |
521 | op_mode = GET_MODE (op0); | |
9ce37fa7 | 522 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
523 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
524 | valid_ops &= propagate_rtx_1 (&op2, old_rtx, new_rtx, flags); | |
42a3a38b | 525 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2)) |
526 | return true; | |
527 | if (op_mode == VOIDmode) | |
528 | op_mode = GET_MODE (op0); | |
529 | tem = simplify_gen_ternary (code, mode, op_mode, op0, op1, op2); | |
530 | break; | |
531 | ||
532 | case RTX_EXTRA: | |
533 | /* The only case we try to handle is a SUBREG. */ | |
534 | if (code == SUBREG) | |
535 | { | |
536 | op0 = XEXP (x, 0); | |
9ce37fa7 | 537 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
42a3a38b | 538 | if (op0 == XEXP (x, 0)) |
539 | return true; | |
540 | tem = simplify_gen_subreg (mode, op0, GET_MODE (SUBREG_REG (x)), | |
541 | SUBREG_BYTE (x)); | |
542 | } | |
543 | break; | |
544 | ||
545 | case RTX_OBJ: | |
9ce37fa7 | 546 | if (code == MEM && x != new_rtx) |
42a3a38b | 547 | { |
548 | rtx new_op0; | |
549 | op0 = XEXP (x, 0); | |
550 | ||
551 | /* There are some addresses that we cannot work on. */ | |
552 | if (!can_simplify_addr (op0)) | |
553 | return true; | |
554 | ||
555 | op0 = new_op0 = targetm.delegitimize_address (op0); | |
9ce37fa7 | 556 | valid_ops &= propagate_rtx_1 (&new_op0, old_rtx, new_rtx, |
f8f13645 | 557 | flags | PR_CAN_APPEAR); |
42a3a38b | 558 | |
559 | /* Dismiss transformation that we do not want to carry on. */ | |
560 | if (!valid_ops | |
561 | || new_op0 == op0 | |
deb3d513 | 562 | || !(GET_MODE (new_op0) == GET_MODE (op0) |
563 | || GET_MODE (new_op0) == VOIDmode)) | |
42a3a38b | 564 | return true; |
565 | ||
566 | canonicalize_address (new_op0); | |
567 | ||
568 | /* Copy propagations are always ok. Otherwise check the costs. */ | |
9ce37fa7 | 569 | if (!(REG_P (old_rtx) && REG_P (new_rtx)) |
f529eb25 | 570 | && !should_replace_address (op0, new_op0, GET_MODE (x), |
bd1a81f7 | 571 | MEM_ADDR_SPACE (x), |
f529eb25 | 572 | flags & PR_OPTIMIZE_FOR_SPEED)) |
42a3a38b | 573 | return true; |
574 | ||
575 | tem = replace_equiv_address_nv (x, new_op0); | |
576 | } | |
577 | ||
578 | else if (code == LO_SUM) | |
579 | { | |
580 | op0 = XEXP (x, 0); | |
581 | op1 = XEXP (x, 1); | |
582 | ||
583 | /* The only simplification we do attempts to remove references to op0 | |
584 | or make it constant -- in both cases, op0's invalidity will not | |
585 | make the result invalid. */ | |
9ce37fa7 | 586 | propagate_rtx_1 (&op0, old_rtx, new_rtx, flags | PR_CAN_APPEAR); |
587 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
42a3a38b | 588 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
589 | return true; | |
590 | ||
591 | /* (lo_sum (high x) x) -> x */ | |
592 | if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1)) | |
593 | tem = op1; | |
594 | else | |
595 | tem = gen_rtx_LO_SUM (mode, op0, op1); | |
596 | ||
597 | /* OP1 is likely not a legitimate address, otherwise there would have | |
598 | been no LO_SUM. We want it to disappear if it is invalid, return | |
599 | false in that case. */ | |
600 | return memory_address_p (mode, tem); | |
601 | } | |
602 | ||
603 | else if (code == REG) | |
604 | { | |
9ce37fa7 | 605 | if (rtx_equal_p (x, old_rtx)) |
42a3a38b | 606 | { |
9ce37fa7 | 607 | *px = new_rtx; |
42a3a38b | 608 | return can_appear; |
609 | } | |
610 | } | |
611 | break; | |
612 | ||
613 | default: | |
614 | break; | |
615 | } | |
616 | ||
617 | /* No change, no trouble. */ | |
618 | if (tem == NULL_RTX) | |
619 | return true; | |
620 | ||
621 | *px = tem; | |
622 | ||
623 | /* The replacement we made so far is valid, if all of the recursive | |
624 | replacements were valid, or we could simplify everything to | |
625 | a constant. */ | |
626 | return valid_ops || can_appear || CONSTANT_P (tem); | |
627 | } | |
628 | ||
f8f13645 | 629 | |
630 | /* for_each_rtx traversal function that returns 1 if BODY points to | |
631 | a non-constant mem. */ | |
632 | ||
633 | static int | |
634 | varying_mem_p (rtx *body, void *data ATTRIBUTE_UNUSED) | |
635 | { | |
636 | rtx x = *body; | |
637 | return MEM_P (x) && !MEM_READONLY_P (x); | |
638 | } | |
639 | ||
640 | ||
42a3a38b | 641 | /* Replace all occurrences of OLD in X with NEW and try to simplify the |
fa7637bd | 642 | resulting expression (in mode MODE). Return a new expression if it is |
42a3a38b | 643 | a constant, otherwise X. |
644 | ||
645 | Simplifications where occurrences of NEW collapse to a constant are always | |
646 | accepted. All simplifications are accepted if NEW is a pseudo too. | |
647 | Otherwise, we accept simplifications that have a lower or equal cost. */ | |
648 | ||
649 | static rtx | |
f529eb25 | 650 | propagate_rtx (rtx x, enum machine_mode mode, rtx old_rtx, rtx new_rtx, |
651 | bool speed) | |
42a3a38b | 652 | { |
653 | rtx tem; | |
654 | bool collapsed; | |
f8f13645 | 655 | int flags; |
42a3a38b | 656 | |
9ce37fa7 | 657 | if (REG_P (new_rtx) && REGNO (new_rtx) < FIRST_PSEUDO_REGISTER) |
42a3a38b | 658 | return NULL_RTX; |
659 | ||
f8f13645 | 660 | flags = 0; |
03ad17bf | 661 | if (REG_P (new_rtx) |
662 | || CONSTANT_P (new_rtx) | |
663 | || (GET_CODE (new_rtx) == SUBREG | |
664 | && REG_P (SUBREG_REG (new_rtx)) | |
665 | && (GET_MODE_SIZE (mode) | |
666 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (new_rtx)))))) | |
f8f13645 | 667 | flags |= PR_CAN_APPEAR; |
9ce37fa7 | 668 | if (!for_each_rtx (&new_rtx, varying_mem_p, NULL)) |
f8f13645 | 669 | flags |= PR_HANDLE_MEM; |
42a3a38b | 670 | |
f529eb25 | 671 | if (speed) |
672 | flags |= PR_OPTIMIZE_FOR_SPEED; | |
673 | ||
42a3a38b | 674 | tem = x; |
9ce37fa7 | 675 | collapsed = propagate_rtx_1 (&tem, old_rtx, copy_rtx (new_rtx), flags); |
42a3a38b | 676 | if (tem == x || !collapsed) |
677 | return NULL_RTX; | |
678 | ||
679 | /* gen_lowpart_common will not be able to process VOIDmode entities other | |
680 | than CONST_INTs. */ | |
971ba038 | 681 | if (GET_MODE (tem) == VOIDmode && !CONST_INT_P (tem)) |
42a3a38b | 682 | return NULL_RTX; |
683 | ||
684 | if (GET_MODE (tem) == VOIDmode) | |
685 | tem = rtl_hooks.gen_lowpart_no_emit (mode, tem); | |
686 | else | |
687 | gcc_assert (GET_MODE (tem) == mode); | |
688 | ||
689 | return tem; | |
690 | } | |
691 | ||
692 | ||
693 | \f | |
694 | ||
695 | /* Return true if the register from reference REF is killed | |
696 | between FROM to (but not including) TO. */ | |
697 | ||
3072d30e | 698 | static bool |
ed6e85ae | 699 | local_ref_killed_between_p (df_ref ref, rtx from, rtx to) |
42a3a38b | 700 | { |
701 | rtx insn; | |
42a3a38b | 702 | |
703 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) | |
704 | { | |
ed6e85ae | 705 | df_ref *def_rec; |
42a3a38b | 706 | if (!INSN_P (insn)) |
707 | continue; | |
708 | ||
3072d30e | 709 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) |
42a3a38b | 710 | { |
ed6e85ae | 711 | df_ref def = *def_rec; |
42a3a38b | 712 | if (DF_REF_REGNO (ref) == DF_REF_REGNO (def)) |
713 | return true; | |
42a3a38b | 714 | } |
715 | } | |
716 | return false; | |
717 | } | |
718 | ||
719 | ||
720 | /* Check if the given DEF is available in INSN. This would require full | |
721 | computation of available expressions; we check only restricted conditions: | |
722 | - if DEF is the sole definition of its register, go ahead; | |
723 | - in the same basic block, we check for no definitions killing the | |
724 | definition of DEF_INSN; | |
725 | - if USE's basic block has DEF's basic block as the sole predecessor, | |
726 | we check if the definition is killed after DEF_INSN or before | |
727 | TARGET_INSN insn, in their respective basic blocks. */ | |
728 | static bool | |
ed6e85ae | 729 | use_killed_between (df_ref use, rtx def_insn, rtx target_insn) |
42a3a38b | 730 | { |
a39fe687 | 731 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); |
732 | basic_block target_bb = BLOCK_FOR_INSN (target_insn); | |
42a3a38b | 733 | int regno; |
ed6e85ae | 734 | df_ref def; |
42a3a38b | 735 | |
2355a966 | 736 | /* We used to have a def reaching a use that is _before_ the def, |
737 | with the def not dominating the use even though the use and def | |
738 | are in the same basic block, when a register may be used | |
739 | uninitialized in a loop. This should not happen anymore since | |
740 | we do not use reaching definitions, but still we test for such | |
741 | cases and assume that DEF is not available. */ | |
a39fe687 | 742 | if (def_bb == target_bb |
3072d30e | 743 | ? DF_INSN_LUID (def_insn) >= DF_INSN_LUID (target_insn) |
a39fe687 | 744 | : !dominated_by_p (CDI_DOMINATORS, target_bb, def_bb)) |
745 | return true; | |
746 | ||
42a3a38b | 747 | /* Check if the reg in USE has only one definition. We already |
1a665a74 | 748 | know that this definition reaches use, or we wouldn't be here. |
749 | However, this is invalid for hard registers because if they are | |
750 | live at the beginning of the function it does not mean that we | |
751 | have an uninitialized access. */ | |
42a3a38b | 752 | regno = DF_REF_REGNO (use); |
3072d30e | 753 | def = DF_REG_DEF_CHAIN (regno); |
1a665a74 | 754 | if (def |
ed6e85ae | 755 | && DF_REF_NEXT_REG (def) == NULL |
1a665a74 | 756 | && regno >= FIRST_PSEUDO_REGISTER) |
42a3a38b | 757 | return false; |
758 | ||
a39fe687 | 759 | /* Check locally if we are in the same basic block. */ |
42a3a38b | 760 | if (def_bb == target_bb) |
a39fe687 | 761 | return local_ref_killed_between_p (use, def_insn, target_insn); |
42a3a38b | 762 | |
763 | /* Finally, if DEF_BB is the sole predecessor of TARGET_BB. */ | |
764 | if (single_pred_p (target_bb) | |
765 | && single_pred (target_bb) == def_bb) | |
766 | { | |
ed6e85ae | 767 | df_ref x; |
42a3a38b | 768 | |
769 | /* See if USE is killed between DEF_INSN and the last insn in the | |
770 | basic block containing DEF_INSN. */ | |
3072d30e | 771 | x = df_bb_regno_last_def_find (def_bb, regno); |
158b6cc9 | 772 | if (x && DF_INSN_LUID (DF_REF_INSN (x)) >= DF_INSN_LUID (def_insn)) |
42a3a38b | 773 | return true; |
774 | ||
775 | /* See if USE is killed between TARGET_INSN and the first insn in the | |
776 | basic block containing TARGET_INSN. */ | |
3072d30e | 777 | x = df_bb_regno_first_def_find (target_bb, regno); |
158b6cc9 | 778 | if (x && DF_INSN_LUID (DF_REF_INSN (x)) < DF_INSN_LUID (target_insn)) |
42a3a38b | 779 | return true; |
780 | ||
781 | return false; | |
782 | } | |
783 | ||
784 | /* Otherwise assume the worst case. */ | |
785 | return true; | |
786 | } | |
787 | ||
788 | ||
42a3a38b | 789 | /* Check if all uses in DEF_INSN can be used in TARGET_INSN. This |
790 | would require full computation of available expressions; | |
791 | we check only restricted conditions, see use_killed_between. */ | |
792 | static bool | |
793 | all_uses_available_at (rtx def_insn, rtx target_insn) | |
794 | { | |
ed6e85ae | 795 | df_ref *use_rec; |
158b6cc9 | 796 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn); |
42a3a38b | 797 | rtx def_set = single_set (def_insn); |
29b2949c | 798 | rtx next; |
42a3a38b | 799 | |
800 | gcc_assert (def_set); | |
801 | ||
802 | /* If target_insn comes right after def_insn, which is very common | |
29b2949c | 803 | for addresses, we can use a quicker test. Ignore debug insns |
804 | other than target insns for this. */ | |
805 | next = NEXT_INSN (def_insn); | |
806 | while (next && next != target_insn && DEBUG_INSN_P (next)) | |
807 | next = NEXT_INSN (next); | |
808 | if (next == target_insn && REG_P (SET_DEST (def_set))) | |
42a3a38b | 809 | { |
810 | rtx def_reg = SET_DEST (def_set); | |
811 | ||
812 | /* If the insn uses the reg that it defines, the substitution is | |
813 | invalid. */ | |
158b6cc9 | 814 | for (use_rec = DF_INSN_INFO_USES (insn_info); *use_rec; use_rec++) |
3072d30e | 815 | { |
ed6e85ae | 816 | df_ref use = *use_rec; |
3072d30e | 817 | if (rtx_equal_p (DF_REF_REG (use), def_reg)) |
818 | return false; | |
819 | } | |
158b6cc9 | 820 | for (use_rec = DF_INSN_INFO_EQ_USES (insn_info); *use_rec; use_rec++) |
3072d30e | 821 | { |
ed6e85ae | 822 | df_ref use = *use_rec; |
823 | if (rtx_equal_p (DF_REF_REG (use), def_reg)) | |
3072d30e | 824 | return false; |
825 | } | |
42a3a38b | 826 | } |
827 | else | |
828 | { | |
c4b594c1 | 829 | rtx def_reg = REG_P (SET_DEST (def_set)) ? SET_DEST (def_set) : NULL_RTX; |
830 | ||
42a3a38b | 831 | /* Look at all the uses of DEF_INSN, and see if they are not |
832 | killed between DEF_INSN and TARGET_INSN. */ | |
158b6cc9 | 833 | for (use_rec = DF_INSN_INFO_USES (insn_info); *use_rec; use_rec++) |
3072d30e | 834 | { |
ed6e85ae | 835 | df_ref use = *use_rec; |
c4b594c1 | 836 | if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg)) |
837 | return false; | |
3072d30e | 838 | if (use_killed_between (use, def_insn, target_insn)) |
839 | return false; | |
840 | } | |
158b6cc9 | 841 | for (use_rec = DF_INSN_INFO_EQ_USES (insn_info); *use_rec; use_rec++) |
3072d30e | 842 | { |
ed6e85ae | 843 | df_ref use = *use_rec; |
c4b594c1 | 844 | if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg)) |
845 | return false; | |
3072d30e | 846 | if (use_killed_between (use, def_insn, target_insn)) |
847 | return false; | |
848 | } | |
42a3a38b | 849 | } |
850 | ||
f8f13645 | 851 | return true; |
42a3a38b | 852 | } |
853 | ||
854 | \f | |
4ffe0526 | 855 | static df_ref *active_defs; |
856 | #ifdef ENABLE_CHECKING | |
857 | static sparseset active_defs_check; | |
858 | #endif | |
42a3a38b | 859 | |
4ffe0526 | 860 | /* Fill the ACTIVE_DEFS array with the use->def link for the registers |
861 | mentioned in USE_REC. Register the valid entries in ACTIVE_DEFS_CHECK | |
862 | too, for checking purposes. */ | |
42a3a38b | 863 | |
4ffe0526 | 864 | static void |
865 | register_active_defs (df_ref *use_rec) | |
42a3a38b | 866 | { |
4ffe0526 | 867 | while (*use_rec) |
42a3a38b | 868 | { |
4ffe0526 | 869 | df_ref use = *use_rec++; |
870 | df_ref def = get_def_for_use (use); | |
871 | int regno = DF_REF_REGNO (use); | |
42a3a38b | 872 | |
4ffe0526 | 873 | #ifdef ENABLE_CHECKING |
874 | sparseset_set_bit (active_defs_check, regno); | |
875 | #endif | |
876 | active_defs[regno] = def; | |
877 | } | |
42a3a38b | 878 | } |
879 | ||
42a3a38b | 880 | |
4ffe0526 | 881 | /* Build the use->def links that we use to update the dataflow info |
882 | for new uses. Note that building the links is very cheap and if | |
883 | it were done earlier, they could be used to rule out invalid | |
884 | propagations (in addition to what is done in all_uses_available_at). | |
885 | I'm not doing this yet, though. */ | |
886 | ||
887 | static void | |
888 | update_df_init (rtx def_insn, rtx insn) | |
42a3a38b | 889 | { |
4ffe0526 | 890 | #ifdef ENABLE_CHECKING |
891 | sparseset_clear (active_defs_check); | |
892 | #endif | |
893 | register_active_defs (DF_INSN_USES (def_insn)); | |
894 | register_active_defs (DF_INSN_USES (insn)); | |
895 | register_active_defs (DF_INSN_EQ_USES (insn)); | |
896 | } | |
42a3a38b | 897 | |
42a3a38b | 898 | |
4ffe0526 | 899 | /* Update the USE_DEF_REF array for the given use, using the active definitions |
900 | in the ACTIVE_DEFS array to match pseudos to their def. */ | |
42a3a38b | 901 | |
4ffe0526 | 902 | static inline void |
903 | update_uses (df_ref *use_rec) | |
42a3a38b | 904 | { |
3072d30e | 905 | while (*use_rec) |
42a3a38b | 906 | { |
4ffe0526 | 907 | df_ref use = *use_rec++; |
908 | int regno = DF_REF_REGNO (use); | |
42a3a38b | 909 | |
4ffe0526 | 910 | /* Set up the use-def chain. */ |
f1f41a6c | 911 | if (DF_REF_ID (use) >= (int) use_def_ref.length ()) |
912 | use_def_ref.safe_grow_cleared (DF_REF_ID (use) + 1); | |
42a3a38b | 913 | |
4ffe0526 | 914 | #ifdef ENABLE_CHECKING |
915 | gcc_assert (sparseset_bit_p (active_defs_check, regno)); | |
916 | #endif | |
f1f41a6c | 917 | use_def_ref[DF_REF_ID (use)] = active_defs[regno]; |
4ffe0526 | 918 | } |
919 | } | |
42a3a38b | 920 | |
4ffe0526 | 921 | |
922 | /* Update the USE_DEF_REF array for the uses in INSN. Only update note | |
923 | uses if NOTES_ONLY is true. */ | |
924 | ||
925 | static void | |
926 | update_df (rtx insn, rtx note) | |
927 | { | |
928 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); | |
929 | ||
930 | if (note) | |
931 | { | |
932 | df_uses_create (&XEXP (note, 0), insn, DF_REF_IN_NOTE); | |
933 | df_notes_rescan (insn); | |
934 | } | |
935 | else | |
936 | { | |
937 | df_uses_create (&PATTERN (insn), insn, 0); | |
938 | df_insn_rescan (insn); | |
939 | update_uses (DF_INSN_INFO_USES (insn_info)); | |
42a3a38b | 940 | } |
4ffe0526 | 941 | |
942 | update_uses (DF_INSN_INFO_EQ_USES (insn_info)); | |
42a3a38b | 943 | } |
944 | ||
945 | ||
946 | /* Try substituting NEW into LOC, which originated from forward propagation | |
947 | of USE's value from DEF_INSN. SET_REG_EQUAL says whether we are | |
948 | substituting the whole SET_SRC, so we can set a REG_EQUAL note if the | |
949 | new insn is not recognized. Return whether the substitution was | |
950 | performed. */ | |
951 | ||
952 | static bool | |
ed6e85ae | 953 | try_fwprop_subst (df_ref use, rtx *loc, rtx new_rtx, rtx def_insn, bool set_reg_equal) |
42a3a38b | 954 | { |
955 | rtx insn = DF_REF_INSN (use); | |
91bd874e | 956 | rtx set = single_set (insn); |
4ffe0526 | 957 | rtx note = NULL_RTX; |
f529eb25 | 958 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
f92bd2dd | 959 | int old_cost = 0; |
91bd874e | 960 | bool ok; |
42a3a38b | 961 | |
4ffe0526 | 962 | update_df_init (def_insn, insn); |
963 | ||
f92bd2dd | 964 | /* forward_propagate_subreg may be operating on an instruction with |
965 | multiple sets. If so, assume the cost of the new instruction is | |
966 | not greater than the old one. */ | |
967 | if (set) | |
7013e87c | 968 | old_cost = set_src_cost (SET_SRC (set), speed); |
42a3a38b | 969 | if (dump_file) |
970 | { | |
971 | fprintf (dump_file, "\nIn insn %d, replacing\n ", INSN_UID (insn)); | |
972 | print_inline_rtx (dump_file, *loc, 2); | |
973 | fprintf (dump_file, "\n with "); | |
9ce37fa7 | 974 | print_inline_rtx (dump_file, new_rtx, 2); |
42a3a38b | 975 | fprintf (dump_file, "\n"); |
976 | } | |
977 | ||
9ce37fa7 | 978 | validate_unshare_change (insn, loc, new_rtx, true); |
91bd874e | 979 | if (!verify_changes (0)) |
980 | { | |
981 | if (dump_file) | |
982 | fprintf (dump_file, "Changes to insn %d not recognized\n", | |
983 | INSN_UID (insn)); | |
984 | ok = false; | |
985 | } | |
986 | ||
f4d72632 | 987 | else if (DF_REF_TYPE (use) == DF_REF_REG_USE |
f92bd2dd | 988 | && set |
7013e87c | 989 | && set_src_cost (SET_SRC (set), speed) > old_cost) |
91bd874e | 990 | { |
991 | if (dump_file) | |
992 | fprintf (dump_file, "Changes to insn %d not profitable\n", | |
993 | INSN_UID (insn)); | |
994 | ok = false; | |
995 | } | |
996 | ||
997 | else | |
42a3a38b | 998 | { |
42a3a38b | 999 | if (dump_file) |
1000 | fprintf (dump_file, "Changed insn %d\n", INSN_UID (insn)); | |
91bd874e | 1001 | ok = true; |
1002 | } | |
1003 | ||
1004 | if (ok) | |
1005 | { | |
1006 | confirm_change_group (); | |
1007 | num_changes++; | |
42a3a38b | 1008 | } |
1009 | else | |
1010 | { | |
91bd874e | 1011 | cancel_changes (0); |
42a3a38b | 1012 | |
dec9a6b8 | 1013 | /* Can also record a simplified value in a REG_EQUAL note, |
1e5b92fa | 1014 | making a new one if one does not already exist. */ |
1015 | if (set_reg_equal) | |
42a3a38b | 1016 | { |
1017 | if (dump_file) | |
1018 | fprintf (dump_file, " Setting REG_EQUAL note\n"); | |
1019 | ||
4ffe0526 | 1020 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (new_rtx)); |
42a3a38b | 1021 | } |
42a3a38b | 1022 | } |
91bd874e | 1023 | |
4ffe0526 | 1024 | if ((ok || note) && !CONSTANT_P (new_rtx)) |
1025 | update_df (insn, note); | |
1026 | ||
91bd874e | 1027 | return ok; |
42a3a38b | 1028 | } |
1029 | ||
42ed3b17 | 1030 | /* For the given single_set INSN, containing SRC known to be a |
1031 | ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN | |
1032 | is redundant due to the register being set by a LOAD_EXTEND_OP | |
1033 | load from memory. */ | |
1034 | ||
1035 | static bool | |
1036 | free_load_extend (rtx src, rtx insn) | |
f92bd2dd | 1037 | { |
42ed3b17 | 1038 | rtx reg; |
f92bd2dd | 1039 | df_ref *use_vec; |
74f0ee70 | 1040 | df_ref use = 0, def; |
42ed3b17 | 1041 | |
1042 | reg = XEXP (src, 0); | |
1043 | #ifdef LOAD_EXTEND_OP | |
1044 | if (LOAD_EXTEND_OP (GET_MODE (reg)) != GET_CODE (src)) | |
1045 | #endif | |
1046 | return false; | |
f92bd2dd | 1047 | |
1048 | for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++) | |
1049 | { | |
42ed3b17 | 1050 | use = *use_vec; |
42a3a38b | 1051 | |
f92bd2dd | 1052 | if (!DF_REF_IS_ARTIFICIAL (use) |
1053 | && DF_REF_TYPE (use) == DF_REF_REG_USE | |
1054 | && DF_REF_REG (use) == reg) | |
42ed3b17 | 1055 | break; |
1056 | } | |
1057 | if (!use) | |
1058 | return false; | |
1059 | ||
1060 | def = get_def_for_use (use); | |
1061 | if (!def) | |
1062 | return false; | |
1063 | ||
1064 | if (DF_REF_IS_ARTIFICIAL (def)) | |
1065 | return false; | |
1066 | ||
1067 | if (NONJUMP_INSN_P (DF_REF_INSN (def))) | |
1068 | { | |
1069 | rtx patt = PATTERN (DF_REF_INSN (def)); | |
1070 | ||
1071 | if (GET_CODE (patt) == SET | |
1072 | && GET_CODE (SET_SRC (patt)) == MEM | |
1073 | && rtx_equal_p (SET_DEST (patt), reg)) | |
1074 | return true; | |
f92bd2dd | 1075 | } |
42ed3b17 | 1076 | return false; |
f92bd2dd | 1077 | } |
f92bd2dd | 1078 | |
1079 | /* If USE is a subreg, see if it can be replaced by a pseudo. */ | |
42a3a38b | 1080 | |
1081 | static bool | |
ed6e85ae | 1082 | forward_propagate_subreg (df_ref use, rtx def_insn, rtx def_set) |
42a3a38b | 1083 | { |
1084 | rtx use_reg = DF_REF_REG (use); | |
1085 | rtx use_insn, src; | |
1086 | ||
f92bd2dd | 1087 | /* Only consider subregs... */ |
42a3a38b | 1088 | enum machine_mode use_mode = GET_MODE (use_reg); |
1089 | if (GET_CODE (use_reg) != SUBREG | |
f92bd2dd | 1090 | || !REG_P (SET_DEST (def_set))) |
42a3a38b | 1091 | return false; |
1092 | ||
f92bd2dd | 1093 | /* If this is a paradoxical SUBREG... */ |
1094 | if (GET_MODE_SIZE (use_mode) | |
1095 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (use_reg)))) | |
1096 | { | |
1097 | /* If this is a paradoxical SUBREG, we have no idea what value the | |
1098 | extra bits would have. However, if the operand is equivalent to | |
1099 | a SUBREG whose operand is the same as our mode, and all the modes | |
1100 | are within a word, we can just use the inner operand because | |
1101 | these SUBREGs just say how to treat the register. */ | |
1102 | use_insn = DF_REF_INSN (use); | |
1103 | src = SET_SRC (def_set); | |
1104 | if (GET_CODE (src) == SUBREG | |
1105 | && REG_P (SUBREG_REG (src)) | |
3014ed2c | 1106 | && REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER |
f92bd2dd | 1107 | && GET_MODE (SUBREG_REG (src)) == use_mode |
1108 | && subreg_lowpart_p (src) | |
1109 | && all_uses_available_at (def_insn, use_insn)) | |
1110 | return try_fwprop_subst (use, DF_REF_LOC (use), SUBREG_REG (src), | |
1111 | def_insn, false); | |
1112 | } | |
1113 | ||
1114 | /* If this is a SUBREG of a ZERO_EXTEND or SIGN_EXTEND, and the SUBREG | |
1115 | is the low part of the reg being extended then just use the inner | |
1116 | operand. Don't do this if the ZERO_EXTEND or SIGN_EXTEND insn will | |
7947d89c | 1117 | be removed due to it matching a LOAD_EXTEND_OP load from memory, |
1118 | or due to the operation being a no-op when applied to registers. | |
1119 | For example, if we have: | |
1120 | ||
1121 | A: (set (reg:DI X) (sign_extend:DI (reg:SI Y))) | |
1122 | B: (... (subreg:SI (reg:DI X)) ...) | |
1123 | ||
1124 | and mode_rep_extended says that Y is already sign-extended, | |
1125 | the backend will typically allow A to be combined with the | |
1126 | definition of Y or, failing that, allow A to be deleted after | |
1127 | reload through register tying. Introducing more uses of Y | |
1128 | prevents both optimisations. */ | |
f92bd2dd | 1129 | else if (subreg_lowpart_p (use_reg)) |
1130 | { | |
f92bd2dd | 1131 | use_insn = DF_REF_INSN (use); |
1132 | src = SET_SRC (def_set); | |
1133 | if ((GET_CODE (src) == ZERO_EXTEND | |
1134 | || GET_CODE (src) == SIGN_EXTEND) | |
1135 | && REG_P (XEXP (src, 0)) | |
3014ed2c | 1136 | && REGNO (XEXP (src, 0)) >= FIRST_PSEUDO_REGISTER |
f92bd2dd | 1137 | && GET_MODE (XEXP (src, 0)) == use_mode |
42ed3b17 | 1138 | && !free_load_extend (src, def_insn) |
7947d89c | 1139 | && (targetm.mode_rep_extended (use_mode, GET_MODE (src)) |
1140 | != (int) GET_CODE (src)) | |
f92bd2dd | 1141 | && all_uses_available_at (def_insn, use_insn)) |
1142 | return try_fwprop_subst (use, DF_REF_LOC (use), XEXP (src, 0), | |
1143 | def_insn, false); | |
1144 | } | |
1145 | ||
1146 | return false; | |
42a3a38b | 1147 | } |
1148 | ||
abe2d6dd | 1149 | /* Try to replace USE with SRC (defined in DEF_INSN) in __asm. */ |
1150 | ||
1151 | static bool | |
1152 | forward_propagate_asm (df_ref use, rtx def_insn, rtx def_set, rtx reg) | |
1153 | { | |
1154 | rtx use_insn = DF_REF_INSN (use), src, use_pat, asm_operands, new_rtx, *loc; | |
1155 | int speed_p, i; | |
1156 | df_ref *use_vec; | |
1157 | ||
1158 | gcc_assert ((DF_REF_FLAGS (use) & DF_REF_IN_NOTE) == 0); | |
1159 | ||
1160 | src = SET_SRC (def_set); | |
1161 | use_pat = PATTERN (use_insn); | |
1162 | ||
1163 | /* In __asm don't replace if src might need more registers than | |
1164 | reg, as that could increase register pressure on the __asm. */ | |
1165 | use_vec = DF_INSN_USES (def_insn); | |
1166 | if (use_vec[0] && use_vec[1]) | |
1167 | return false; | |
1168 | ||
4ffe0526 | 1169 | update_df_init (def_insn, use_insn); |
abe2d6dd | 1170 | speed_p = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); |
1171 | asm_operands = NULL_RTX; | |
1172 | switch (GET_CODE (use_pat)) | |
1173 | { | |
1174 | case ASM_OPERANDS: | |
1175 | asm_operands = use_pat; | |
1176 | break; | |
1177 | case SET: | |
1178 | if (MEM_P (SET_DEST (use_pat))) | |
1179 | { | |
1180 | loc = &SET_DEST (use_pat); | |
1181 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p); | |
1182 | if (new_rtx) | |
1183 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1184 | } | |
1185 | asm_operands = SET_SRC (use_pat); | |
1186 | break; | |
1187 | case PARALLEL: | |
1188 | for (i = 0; i < XVECLEN (use_pat, 0); i++) | |
1189 | if (GET_CODE (XVECEXP (use_pat, 0, i)) == SET) | |
1190 | { | |
1191 | if (MEM_P (SET_DEST (XVECEXP (use_pat, 0, i)))) | |
1192 | { | |
1193 | loc = &SET_DEST (XVECEXP (use_pat, 0, i)); | |
1194 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, | |
1195 | src, speed_p); | |
1196 | if (new_rtx) | |
1197 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1198 | } | |
1199 | asm_operands = SET_SRC (XVECEXP (use_pat, 0, i)); | |
1200 | } | |
1201 | else if (GET_CODE (XVECEXP (use_pat, 0, i)) == ASM_OPERANDS) | |
1202 | asm_operands = XVECEXP (use_pat, 0, i); | |
1203 | break; | |
1204 | default: | |
1205 | gcc_unreachable (); | |
1206 | } | |
1207 | ||
1208 | gcc_assert (asm_operands && GET_CODE (asm_operands) == ASM_OPERANDS); | |
1209 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (asm_operands); i++) | |
1210 | { | |
1211 | loc = &ASM_OPERANDS_INPUT (asm_operands, i); | |
1212 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p); | |
1213 | if (new_rtx) | |
1214 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1215 | } | |
1216 | ||
1217 | if (num_changes_pending () == 0 || !apply_change_group ()) | |
1218 | return false; | |
1219 | ||
4ffe0526 | 1220 | update_df (use_insn, NULL); |
abe2d6dd | 1221 | num_changes++; |
1222 | return true; | |
1223 | } | |
1224 | ||
42a3a38b | 1225 | /* Try to replace USE with SRC (defined in DEF_INSN) and simplify the |
1226 | result. */ | |
1227 | ||
1228 | static bool | |
ed6e85ae | 1229 | forward_propagate_and_simplify (df_ref use, rtx def_insn, rtx def_set) |
42a3a38b | 1230 | { |
1231 | rtx use_insn = DF_REF_INSN (use); | |
1232 | rtx use_set = single_set (use_insn); | |
9ce37fa7 | 1233 | rtx src, reg, new_rtx, *loc; |
42a3a38b | 1234 | bool set_reg_equal; |
1235 | enum machine_mode mode; | |
abe2d6dd | 1236 | int asm_use = -1; |
1237 | ||
1238 | if (INSN_CODE (use_insn) < 0) | |
1239 | asm_use = asm_noperands (PATTERN (use_insn)); | |
42a3a38b | 1240 | |
9845d120 | 1241 | if (!use_set && asm_use < 0 && !DEBUG_INSN_P (use_insn)) |
42a3a38b | 1242 | return false; |
1243 | ||
1244 | /* Do not propagate into PC, CC0, etc. */ | |
abe2d6dd | 1245 | if (use_set && GET_MODE (SET_DEST (use_set)) == VOIDmode) |
42a3a38b | 1246 | return false; |
1247 | ||
1248 | /* If def and use are subreg, check if they match. */ | |
1249 | reg = DF_REF_REG (use); | |
d2efb29d | 1250 | if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG) |
1251 | { | |
1252 | if (SUBREG_BYTE (SET_DEST (def_set)) != SUBREG_BYTE (reg)) | |
1253 | return false; | |
1254 | } | |
42a3a38b | 1255 | /* Check if the def had a subreg, but the use has the whole reg. */ |
d2efb29d | 1256 | else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG) |
42a3a38b | 1257 | return false; |
42a3a38b | 1258 | /* Check if the use has a subreg, but the def had the whole reg. Unlike the |
1259 | previous case, the optimization is possible and often useful indeed. */ | |
d2efb29d | 1260 | else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set))) |
42a3a38b | 1261 | reg = SUBREG_REG (reg); |
1262 | ||
d2efb29d | 1263 | /* Make sure that we can treat REG as having the same mode as the |
1264 | source of DEF_SET. */ | |
1265 | if (GET_MODE (SET_DEST (def_set)) != GET_MODE (reg)) | |
1266 | return false; | |
1267 | ||
42a3a38b | 1268 | /* Check if the substitution is valid (last, because it's the most |
1269 | expensive check!). */ | |
1270 | src = SET_SRC (def_set); | |
1271 | if (!CONSTANT_P (src) && !all_uses_available_at (def_insn, use_insn)) | |
1272 | return false; | |
1273 | ||
1274 | /* Check if the def is loading something from the constant pool; in this | |
1275 | case we would undo optimization such as compress_float_constant. | |
1276 | Still, we can set a REG_EQUAL note. */ | |
1277 | if (MEM_P (src) && MEM_READONLY_P (src)) | |
1278 | { | |
1279 | rtx x = avoid_constant_pool_reference (src); | |
abe2d6dd | 1280 | if (x != src && use_set) |
42a3a38b | 1281 | { |
1282 | rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
9ce37fa7 | 1283 | rtx old_rtx = note ? XEXP (note, 0) : SET_SRC (use_set); |
1284 | rtx new_rtx = simplify_replace_rtx (old_rtx, src, x); | |
1285 | if (old_rtx != new_rtx) | |
1286 | set_unique_reg_note (use_insn, REG_EQUAL, copy_rtx (new_rtx)); | |
42a3a38b | 1287 | } |
1288 | return false; | |
1289 | } | |
1290 | ||
abe2d6dd | 1291 | if (asm_use >= 0) |
1292 | return forward_propagate_asm (use, def_insn, def_set, reg); | |
1293 | ||
42a3a38b | 1294 | /* Else try simplifying. */ |
1295 | ||
1296 | if (DF_REF_TYPE (use) == DF_REF_REG_MEM_STORE) | |
1297 | { | |
1298 | loc = &SET_DEST (use_set); | |
1299 | set_reg_equal = false; | |
1300 | } | |
9845d120 | 1301 | else if (!use_set) |
1302 | { | |
1303 | loc = &INSN_VAR_LOCATION_LOC (use_insn); | |
1304 | set_reg_equal = false; | |
1305 | } | |
42a3a38b | 1306 | else |
1307 | { | |
1308 | rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
1309 | if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE) | |
1310 | loc = &XEXP (note, 0); | |
1311 | else | |
1312 | loc = &SET_SRC (use_set); | |
3072d30e | 1313 | |
42a3a38b | 1314 | /* Do not replace an existing REG_EQUAL note if the insn is not |
93d89886 | 1315 | recognized. Either we're already replacing in the note, or we'll |
1316 | separately try plugging the definition in the note and simplifying. | |
44433d3b | 1317 | And only install a REQ_EQUAL note when the destination is a REG |
1318 | that isn't mentioned in USE_SET, as the note would be invalid | |
a24ec999 | 1319 | otherwise. We also don't want to install a note if we are merely |
1320 | propagating a pseudo since verifying that this pseudo isn't dead | |
1321 | is a pain; moreover such a note won't help anything. */ | |
1322 | set_reg_equal = (note == NULL_RTX | |
1323 | && REG_P (SET_DEST (use_set)) | |
1324 | && !REG_P (src) | |
1325 | && !(GET_CODE (src) == SUBREG | |
1326 | && REG_P (SUBREG_REG (src))) | |
1327 | && !reg_mentioned_p (SET_DEST (use_set), | |
1328 | SET_SRC (use_set))); | |
42a3a38b | 1329 | } |
1330 | ||
1331 | if (GET_MODE (*loc) == VOIDmode) | |
1332 | mode = GET_MODE (SET_DEST (use_set)); | |
1333 | else | |
1334 | mode = GET_MODE (*loc); | |
1335 | ||
f529eb25 | 1336 | new_rtx = propagate_rtx (*loc, mode, reg, src, |
1337 | optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn))); | |
3072d30e | 1338 | |
9ce37fa7 | 1339 | if (!new_rtx) |
42a3a38b | 1340 | return false; |
1341 | ||
9ce37fa7 | 1342 | return try_fwprop_subst (use, loc, new_rtx, def_insn, set_reg_equal); |
42a3a38b | 1343 | } |
1344 | ||
1345 | ||
1346 | /* Given a use USE of an insn, if it has a single reaching | |
f9460785 | 1347 | definition, try to forward propagate it into that insn. |
1348 | Return true if cfg cleanup will be needed. */ | |
42a3a38b | 1349 | |
f9460785 | 1350 | static bool |
ed6e85ae | 1351 | forward_propagate_into (df_ref use) |
42a3a38b | 1352 | { |
ed6e85ae | 1353 | df_ref def; |
42a3a38b | 1354 | rtx def_insn, def_set, use_insn; |
3072d30e | 1355 | rtx parent; |
42a3a38b | 1356 | |
1357 | if (DF_REF_FLAGS (use) & DF_REF_READ_WRITE) | |
f9460785 | 1358 | return false; |
3072d30e | 1359 | if (DF_REF_IS_ARTIFICIAL (use)) |
f9460785 | 1360 | return false; |
42a3a38b | 1361 | |
1362 | /* Only consider uses that have a single definition. */ | |
e0bd4156 | 1363 | def = get_def_for_use (use); |
1364 | if (!def) | |
f9460785 | 1365 | return false; |
42a3a38b | 1366 | if (DF_REF_FLAGS (def) & DF_REF_READ_WRITE) |
f9460785 | 1367 | return false; |
3072d30e | 1368 | if (DF_REF_IS_ARTIFICIAL (def)) |
f9460785 | 1369 | return false; |
42a3a38b | 1370 | |
243f24c5 | 1371 | /* Do not propagate loop invariant definitions inside the loop. */ |
1372 | if (DF_REF_BB (def)->loop_father != DF_REF_BB (use)->loop_father) | |
f9460785 | 1373 | return false; |
42a3a38b | 1374 | |
1375 | /* Check if the use is still present in the insn! */ | |
1376 | use_insn = DF_REF_INSN (use); | |
1377 | if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE) | |
1378 | parent = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
1379 | else | |
1380 | parent = PATTERN (use_insn); | |
1381 | ||
f533acbe | 1382 | if (!reg_mentioned_p (DF_REF_REG (use), parent)) |
f9460785 | 1383 | return false; |
42a3a38b | 1384 | |
1385 | def_insn = DF_REF_INSN (def); | |
3072d30e | 1386 | if (multiple_sets (def_insn)) |
f9460785 | 1387 | return false; |
42a3a38b | 1388 | def_set = single_set (def_insn); |
1389 | if (!def_set) | |
f9460785 | 1390 | return false; |
42a3a38b | 1391 | |
1392 | /* Only try one kind of propagation. If two are possible, we'll | |
1393 | do it on the following iterations. */ | |
f9460785 | 1394 | if (forward_propagate_and_simplify (use, def_insn, def_set) |
1395 | || forward_propagate_subreg (use, def_insn, def_set)) | |
1396 | { | |
1397 | if (cfun->can_throw_non_call_exceptions | |
1398 | && find_reg_note (use_insn, REG_EH_REGION, NULL_RTX) | |
1399 | && purge_dead_edges (DF_REF_BB (use))) | |
1400 | return true; | |
1401 | } | |
1402 | return false; | |
42a3a38b | 1403 | } |
1404 | ||
1405 | \f | |
1406 | static void | |
1407 | fwprop_init (void) | |
1408 | { | |
1409 | num_changes = 0; | |
a39fe687 | 1410 | calculate_dominance_info (CDI_DOMINATORS); |
42a3a38b | 1411 | |
1412 | /* We do not always want to propagate into loops, so we have to find | |
9add6570 | 1413 | loops and be careful about them. Avoid CFG modifications so that |
1414 | we don't have to update dominance information afterwards for | |
1415 | build_single_def_use_links. */ | |
1416 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
42a3a38b | 1417 | |
e0bd4156 | 1418 | build_single_def_use_links (); |
3072d30e | 1419 | df_set_flags (DF_DEFER_INSN_RESCAN); |
4ffe0526 | 1420 | |
1421 | active_defs = XNEWVEC (df_ref, max_reg_num ()); | |
1422 | #ifdef ENABLE_CHECKING | |
1423 | active_defs_check = sparseset_alloc (max_reg_num ()); | |
1424 | #endif | |
42a3a38b | 1425 | } |
1426 | ||
1427 | static void | |
1428 | fwprop_done (void) | |
1429 | { | |
243f24c5 | 1430 | loop_optimizer_finalize (); |
3072d30e | 1431 | |
f1f41a6c | 1432 | use_def_ref.release (); |
4ffe0526 | 1433 | free (active_defs); |
1434 | #ifdef ENABLE_CHECKING | |
1435 | sparseset_free (active_defs_check); | |
1436 | #endif | |
1437 | ||
a39fe687 | 1438 | free_dominance_info (CDI_DOMINATORS); |
42a3a38b | 1439 | cleanup_cfg (0); |
1440 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); | |
1441 | ||
1442 | if (dump_file) | |
1443 | fprintf (dump_file, | |
1444 | "\nNumber of successful forward propagations: %d\n\n", | |
1445 | num_changes); | |
1446 | } | |
1447 | ||
1448 | ||
42a3a38b | 1449 | /* Main entry point. */ |
1450 | ||
1451 | static bool | |
1452 | gate_fwprop (void) | |
1453 | { | |
1454 | return optimize > 0 && flag_forward_propagate; | |
1455 | } | |
1456 | ||
1457 | static unsigned int | |
1458 | fwprop (void) | |
1459 | { | |
1460 | unsigned i; | |
f9460785 | 1461 | bool need_cleanup = false; |
42a3a38b | 1462 | |
1463 | fwprop_init (); | |
1464 | ||
4ffe0526 | 1465 | /* Go through all the uses. df_uses_create will create new ones at the |
42a3a38b | 1466 | end, and we'll go through them as well. |
1467 | ||
1468 | Do not forward propagate addresses into loops until after unrolling. | |
1469 | CSE did so because it was able to fix its own mess, but we are not. */ | |
1470 | ||
3072d30e | 1471 | for (i = 0; i < DF_USES_TABLE_SIZE (); i++) |
42a3a38b | 1472 | { |
ed6e85ae | 1473 | df_ref use = DF_USES_GET (i); |
42a3a38b | 1474 | if (use) |
243f24c5 | 1475 | if (DF_REF_TYPE (use) == DF_REF_REG_USE |
526548ea | 1476 | || DF_REF_BB (use)->loop_father == NULL |
1477 | /* The outer most loop is not really a loop. */ | |
1478 | || loop_outer (DF_REF_BB (use)->loop_father) == NULL) | |
f9460785 | 1479 | need_cleanup |= forward_propagate_into (use); |
42a3a38b | 1480 | } |
1481 | ||
1482 | fwprop_done (); | |
f9460785 | 1483 | if (need_cleanup) |
1484 | cleanup_cfg (0); | |
42a3a38b | 1485 | return 0; |
1486 | } | |
1487 | ||
cbe8bda8 | 1488 | namespace { |
1489 | ||
1490 | const pass_data pass_data_rtl_fwprop = | |
42a3a38b | 1491 | { |
cbe8bda8 | 1492 | RTL_PASS, /* type */ |
1493 | "fwprop1", /* name */ | |
1494 | OPTGROUP_NONE, /* optinfo_flags */ | |
1495 | true, /* has_gate */ | |
1496 | true, /* has_execute */ | |
1497 | TV_FWPROP, /* tv_id */ | |
1498 | 0, /* properties_required */ | |
1499 | 0, /* properties_provided */ | |
1500 | 0, /* properties_destroyed */ | |
1501 | 0, /* todo_flags_start */ | |
1502 | ( TODO_df_finish | TODO_verify_flow | |
1503 | | TODO_verify_rtl_sharing ), /* todo_flags_finish */ | |
42a3a38b | 1504 | }; |
1505 | ||
cbe8bda8 | 1506 | class pass_rtl_fwprop : public rtl_opt_pass |
1507 | { | |
1508 | public: | |
1509 | pass_rtl_fwprop(gcc::context *ctxt) | |
1510 | : rtl_opt_pass(pass_data_rtl_fwprop, ctxt) | |
1511 | {} | |
1512 | ||
1513 | /* opt_pass methods: */ | |
1514 | bool gate () { return gate_fwprop (); } | |
1515 | unsigned int execute () { return fwprop (); } | |
1516 | ||
1517 | }; // class pass_rtl_fwprop | |
1518 | ||
1519 | } // anon namespace | |
1520 | ||
1521 | rtl_opt_pass * | |
1522 | make_pass_rtl_fwprop (gcc::context *ctxt) | |
1523 | { | |
1524 | return new pass_rtl_fwprop (ctxt); | |
1525 | } | |
1526 | ||
42a3a38b | 1527 | static unsigned int |
1528 | fwprop_addr (void) | |
1529 | { | |
1530 | unsigned i; | |
f9460785 | 1531 | bool need_cleanup = false; |
1532 | ||
42a3a38b | 1533 | fwprop_init (); |
1534 | ||
4ffe0526 | 1535 | /* Go through all the uses. df_uses_create will create new ones at the |
42a3a38b | 1536 | end, and we'll go through them as well. */ |
3072d30e | 1537 | for (i = 0; i < DF_USES_TABLE_SIZE (); i++) |
42a3a38b | 1538 | { |
ed6e85ae | 1539 | df_ref use = DF_USES_GET (i); |
42a3a38b | 1540 | if (use) |
1541 | if (DF_REF_TYPE (use) != DF_REF_REG_USE | |
526548ea | 1542 | && DF_REF_BB (use)->loop_father != NULL |
1543 | /* The outer most loop is not really a loop. */ | |
1544 | && loop_outer (DF_REF_BB (use)->loop_father) != NULL) | |
f9460785 | 1545 | need_cleanup |= forward_propagate_into (use); |
42a3a38b | 1546 | } |
1547 | ||
1548 | fwprop_done (); | |
1549 | ||
f9460785 | 1550 | if (need_cleanup) |
1551 | cleanup_cfg (0); | |
42a3a38b | 1552 | return 0; |
1553 | } | |
1554 | ||
cbe8bda8 | 1555 | namespace { |
1556 | ||
1557 | const pass_data pass_data_rtl_fwprop_addr = | |
42a3a38b | 1558 | { |
cbe8bda8 | 1559 | RTL_PASS, /* type */ |
1560 | "fwprop2", /* name */ | |
1561 | OPTGROUP_NONE, /* optinfo_flags */ | |
1562 | true, /* has_gate */ | |
1563 | true, /* has_execute */ | |
1564 | TV_FWPROP, /* tv_id */ | |
1565 | 0, /* properties_required */ | |
1566 | 0, /* properties_provided */ | |
1567 | 0, /* properties_destroyed */ | |
1568 | 0, /* todo_flags_start */ | |
1569 | ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */ | |
42a3a38b | 1570 | }; |
cbe8bda8 | 1571 | |
1572 | class pass_rtl_fwprop_addr : public rtl_opt_pass | |
1573 | { | |
1574 | public: | |
1575 | pass_rtl_fwprop_addr(gcc::context *ctxt) | |
1576 | : rtl_opt_pass(pass_data_rtl_fwprop_addr, ctxt) | |
1577 | {} | |
1578 | ||
1579 | /* opt_pass methods: */ | |
1580 | bool gate () { return gate_fwprop (); } | |
1581 | unsigned int execute () { return fwprop_addr (); } | |
1582 | ||
1583 | }; // class pass_rtl_fwprop_addr | |
1584 | ||
1585 | } // anon namespace | |
1586 | ||
1587 | rtl_opt_pass * | |
1588 | make_pass_rtl_fwprop_addr (gcc::context *ctxt) | |
1589 | { | |
1590 | return new pass_rtl_fwprop_addr (ctxt); | |
1591 | } |