]>
Commit | Line | Data |
---|---|---|
42a3a38b | 1 | /* RTL-based forward propagation pass for GNU compiler. |
f1717362 | 2 | Copyright (C) 2005-2016 Free Software Foundation, Inc. |
42a3a38b | 3 | Contributed by Paolo Bonzini and Steven Bosscher. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 9 | Software Foundation; either version 3, or (at your option) any later |
42a3a38b | 10 | version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
42a3a38b | 20 | |
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
9ef16211 | 24 | #include "backend.h" |
7c29e30e | 25 | #include "target.h" |
9ef16211 | 26 | #include "rtl.h" |
7c29e30e | 27 | #include "predict.h" |
9ef16211 | 28 | #include "df.h" |
42a3a38b | 29 | #include "tm_p.h" |
42a3a38b | 30 | #include "insn-config.h" |
7c29e30e | 31 | #include "emit-rtl.h" |
42a3a38b | 32 | #include "recog.h" |
7c29e30e | 33 | |
34 | #include "sparseset.h" | |
94ea8568 | 35 | #include "cfgrtl.h" |
36 | #include "cfgcleanup.h" | |
42a3a38b | 37 | #include "cfgloop.h" |
38 | #include "tree-pass.h" | |
2355a966 | 39 | #include "domwalk.h" |
e32f8fb9 | 40 | #include "rtl-iter.h" |
42a3a38b | 41 | |
42 | ||
43 | /* This pass does simple forward propagation and simplification when an | |
44 | operand of an insn can only come from a single def. This pass uses | |
45 | df.c, so it is global. However, we only do limited analysis of | |
46 | available expressions. | |
47 | ||
48 | 1) The pass tries to propagate the source of the def into the use, | |
49 | and checks if the result is independent of the substituted value. | |
50 | For example, the high word of a (zero_extend:DI (reg:SI M)) is always | |
51 | zero, independent of the source register. | |
52 | ||
53 | In particular, we propagate constants into the use site. Sometimes | |
54 | RTL expansion did not put the constant in the same insn on purpose, | |
55 | to satisfy a predicate, and the result will fail to be recognized; | |
56 | but this happens rarely and in this case we can still create a | |
57 | REG_EQUAL note. For multi-word operations, this | |
58 | ||
59 | (set (subreg:SI (reg:DI 120) 0) (const_int 0)) | |
60 | (set (subreg:SI (reg:DI 120) 4) (const_int -1)) | |
61 | (set (subreg:SI (reg:DI 122) 0) | |
62 | (ior:SI (subreg:SI (reg:DI 119) 0) (subreg:SI (reg:DI 120) 0))) | |
63 | (set (subreg:SI (reg:DI 122) 4) | |
64 | (ior:SI (subreg:SI (reg:DI 119) 4) (subreg:SI (reg:DI 120) 4))) | |
65 | ||
66 | can be simplified to the much simpler | |
67 | ||
68 | (set (subreg:SI (reg:DI 122) 0) (subreg:SI (reg:DI 119))) | |
69 | (set (subreg:SI (reg:DI 122) 4) (const_int -1)) | |
70 | ||
71 | This particular propagation is also effective at putting together | |
72 | complex addressing modes. We are more aggressive inside MEMs, in | |
73 | that all definitions are propagated if the use is in a MEM; if the | |
74 | result is a valid memory address we check address_cost to decide | |
75 | whether the substitution is worthwhile. | |
76 | ||
77 | 2) The pass propagates register copies. This is not as effective as | |
78 | the copy propagation done by CSE's canon_reg, which works by walking | |
79 | the instruction chain, it can help the other transformations. | |
80 | ||
81 | We should consider removing this optimization, and instead reorder the | |
82 | RTL passes, because GCSE does this transformation too. With some luck, | |
83 | the CSE pass at the end of rest_of_handle_gcse could also go away. | |
84 | ||
85 | 3) The pass looks for paradoxical subregs that are actually unnecessary. | |
86 | Things like this: | |
87 | ||
88 | (set (reg:QI 120) (subreg:QI (reg:SI 118) 0)) | |
89 | (set (reg:QI 121) (subreg:QI (reg:SI 119) 0)) | |
90 | (set (reg:SI 122) (plus:SI (subreg:SI (reg:QI 120) 0) | |
91 | (subreg:SI (reg:QI 121) 0))) | |
92 | ||
93 | are very common on machines that can only do word-sized operations. | |
94 | For each use of a paradoxical subreg (subreg:WIDER (reg:NARROW N) 0), | |
95 | if it has a single def and it is (subreg:NARROW (reg:WIDE M) 0), | |
96 | we can replace the paradoxical subreg with simply (reg:WIDE M). The | |
97 | above will simplify this to | |
98 | ||
99 | (set (reg:QI 120) (subreg:QI (reg:SI 118) 0)) | |
100 | (set (reg:QI 121) (subreg:QI (reg:SI 119) 0)) | |
101 | (set (reg:SI 122) (plus:SI (reg:SI 118) (reg:SI 119))) | |
102 | ||
2355a966 | 103 | where the first two insns are now dead. |
104 | ||
105 | We used to use reaching definitions to find which uses have a | |
106 | single reaching definition (sounds obvious...), but this is too | |
107 | complex a problem in nasty testcases like PR33928. Now we use the | |
108 | multiple definitions problem in df-problems.c. The similarity | |
109 | between that problem and SSA form creation is taken further, in | |
110 | that fwprop does a dominator walk to create its chains; however, | |
111 | instead of creating a PHI function where multiple definitions meet | |
112 | I just punt and record only singleton use-def chains, which is | |
113 | all that is needed by fwprop. */ | |
42a3a38b | 114 | |
115 | ||
42a3a38b | 116 | static int num_changes; |
117 | ||
f1f41a6c | 118 | static vec<df_ref> use_def_ref; |
119 | static vec<df_ref> reg_defs; | |
120 | static vec<df_ref> reg_defs_stack; | |
e0bd4156 | 121 | |
426e6c73 | 122 | /* The MD bitmaps are trimmed to include only live registers to cut |
123 | memory usage on testcases like insn-recog.c. Track live registers | |
124 | in the basic block and do not perform forward propagation if the | |
125 | destination is a dead pseudo occurring in a note. */ | |
126 | static bitmap local_md; | |
127 | static bitmap local_lr; | |
e0bd4156 | 128 | |
129 | /* Return the only def in USE's use-def chain, or NULL if there is | |
130 | more than one def in the chain. */ | |
131 | ||
132 | static inline df_ref | |
133 | get_def_for_use (df_ref use) | |
134 | { | |
f1f41a6c | 135 | return use_def_ref[DF_REF_ID (use)]; |
e0bd4156 | 136 | } |
137 | ||
138 | ||
2355a966 | 139 | /* Update the reg_defs vector with non-partial definitions in DEF_REC. |
140 | TOP_FLAG says which artificials uses should be used, when DEF_REC | |
141 | is an artificial def vector. LOCAL_MD is modified as after a | |
142 | df_md_simulate_* function; we do more or less the same processing | |
143 | done there, so we do not use those functions. */ | |
144 | ||
145 | #define DF_MD_GEN_FLAGS \ | |
146 | (DF_REF_PARTIAL | DF_REF_CONDITIONAL | DF_REF_MAY_CLOBBER) | |
e0bd4156 | 147 | |
2355a966 | 148 | static void |
ddc2d0e3 | 149 | process_defs (df_ref def, int top_flag) |
e0bd4156 | 150 | { |
ddc2d0e3 | 151 | for (; def; def = DF_REF_NEXT_LOC (def)) |
2355a966 | 152 | { |
f1f41a6c | 153 | df_ref curr_def = reg_defs[DF_REF_REGNO (def)]; |
2355a966 | 154 | unsigned int dregno; |
e0bd4156 | 155 | |
2355a966 | 156 | if ((DF_REF_FLAGS (def) & DF_REF_AT_TOP) != top_flag) |
157 | continue; | |
e0bd4156 | 158 | |
2355a966 | 159 | dregno = DF_REF_REGNO (def); |
160 | if (curr_def) | |
f1f41a6c | 161 | reg_defs_stack.safe_push (curr_def); |
2355a966 | 162 | else |
163 | { | |
164 | /* Do not store anything if "transitioning" from NULL to NULL. But | |
165 | otherwise, push a special entry on the stack to tell the | |
166 | leave_block callback that the entry in reg_defs was NULL. */ | |
167 | if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS) | |
168 | ; | |
169 | else | |
f1f41a6c | 170 | reg_defs_stack.safe_push (def); |
2355a966 | 171 | } |
172 | ||
173 | if (DF_REF_FLAGS (def) & DF_MD_GEN_FLAGS) | |
174 | { | |
175 | bitmap_set_bit (local_md, dregno); | |
f1f41a6c | 176 | reg_defs[dregno] = NULL; |
2355a966 | 177 | } |
178 | else | |
179 | { | |
180 | bitmap_clear_bit (local_md, dregno); | |
f1f41a6c | 181 | reg_defs[dregno] = def; |
2355a966 | 182 | } |
e0bd4156 | 183 | } |
e0bd4156 | 184 | } |
185 | ||
186 | ||
187 | /* Fill the use_def_ref vector with values for the uses in USE_REC, | |
2355a966 | 188 | taking reaching definitions info from LOCAL_MD and REG_DEFS. |
189 | TOP_FLAG says which artificials uses should be used, when USE_REC | |
190 | is an artificial use vector. */ | |
e0bd4156 | 191 | |
192 | static void | |
ddc2d0e3 | 193 | process_uses (df_ref use, int top_flag) |
e0bd4156 | 194 | { |
ddc2d0e3 | 195 | for (; use; use = DF_REF_NEXT_LOC (use)) |
2355a966 | 196 | if ((DF_REF_FLAGS (use) & DF_REF_AT_TOP) == top_flag) |
e0bd4156 | 197 | { |
2355a966 | 198 | unsigned int uregno = DF_REF_REGNO (use); |
f1f41a6c | 199 | if (reg_defs[uregno] |
426e6c73 | 200 | && !bitmap_bit_p (local_md, uregno) |
201 | && bitmap_bit_p (local_lr, uregno)) | |
f1f41a6c | 202 | use_def_ref[DF_REF_ID (use)] = reg_defs[uregno]; |
2355a966 | 203 | } |
204 | } | |
205 | ||
54c91640 | 206 | class single_def_use_dom_walker : public dom_walker |
207 | { | |
208 | public: | |
209 | single_def_use_dom_walker (cdi_direction direction) | |
210 | : dom_walker (direction) {} | |
96752458 | 211 | virtual edge before_dom_children (basic_block); |
54c91640 | 212 | virtual void after_dom_children (basic_block); |
213 | }; | |
214 | ||
96752458 | 215 | edge |
54c91640 | 216 | single_def_use_dom_walker::before_dom_children (basic_block bb) |
2355a966 | 217 | { |
2355a966 | 218 | int bb_index = bb->index; |
426e6c73 | 219 | struct df_md_bb_info *md_bb_info = df_md_get_bb_info (bb_index); |
220 | struct df_lr_bb_info *lr_bb_info = df_lr_get_bb_info (bb_index); | |
dea92746 | 221 | rtx_insn *insn; |
2355a966 | 222 | |
f53d14b1 | 223 | bitmap_copy (local_md, &md_bb_info->in); |
224 | bitmap_copy (local_lr, &lr_bb_info->in); | |
2355a966 | 225 | |
226 | /* Push a marker for the leave_block callback. */ | |
f1f41a6c | 227 | reg_defs_stack.safe_push (NULL); |
2355a966 | 228 | |
426e6c73 | 229 | process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP); |
230 | process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP); | |
330ce56e | 231 | |
232 | /* We don't call df_simulate_initialize_forwards, as it may overestimate | |
233 | the live registers if there are unused artificial defs. We prefer | |
234 | liveness to be underestimated. */ | |
2355a966 | 235 | |
236 | FOR_BB_INSNS (bb, insn) | |
237 | if (INSN_P (insn)) | |
238 | { | |
239 | unsigned int uid = INSN_UID (insn); | |
426e6c73 | 240 | process_uses (DF_INSN_UID_USES (uid), 0); |
241 | process_uses (DF_INSN_UID_EQ_USES (uid), 0); | |
242 | process_defs (DF_INSN_UID_DEFS (uid), 0); | |
243 | df_simulate_one_insn_forwards (bb, insn, local_lr); | |
e0bd4156 | 244 | } |
2355a966 | 245 | |
426e6c73 | 246 | process_uses (df_get_artificial_uses (bb_index), 0); |
247 | process_defs (df_get_artificial_defs (bb_index), 0); | |
96752458 | 248 | |
249 | return NULL; | |
2355a966 | 250 | } |
251 | ||
252 | /* Pop the definitions created in this basic block when leaving its | |
253 | dominated parts. */ | |
254 | ||
54c91640 | 255 | void |
256 | single_def_use_dom_walker::after_dom_children (basic_block bb ATTRIBUTE_UNUSED) | |
2355a966 | 257 | { |
258 | df_ref saved_def; | |
f1f41a6c | 259 | while ((saved_def = reg_defs_stack.pop ()) != NULL) |
2355a966 | 260 | { |
261 | unsigned int dregno = DF_REF_REGNO (saved_def); | |
262 | ||
263 | /* See also process_defs. */ | |
f1f41a6c | 264 | if (saved_def == reg_defs[dregno]) |
265 | reg_defs[dregno] = NULL; | |
2355a966 | 266 | else |
f1f41a6c | 267 | reg_defs[dregno] = saved_def; |
2355a966 | 268 | } |
e0bd4156 | 269 | } |
270 | ||
271 | ||
2355a966 | 272 | /* Build a vector holding the reaching definitions of uses reached by a |
273 | single dominating definition. */ | |
e0bd4156 | 274 | |
275 | static void | |
276 | build_single_def_use_links (void) | |
277 | { | |
2355a966 | 278 | /* We use the multiple definitions problem to compute our restricted |
279 | use-def chains. */ | |
e0bd4156 | 280 | df_set_flags (DF_EQ_NOTES); |
2355a966 | 281 | df_md_add_problem (); |
426e6c73 | 282 | df_note_add_problem (); |
e0bd4156 | 283 | df_analyze (); |
284 | df_maybe_reorganize_use_refs (DF_REF_ORDER_BY_INSN_WITH_NOTES); | |
285 | ||
f1f41a6c | 286 | use_def_ref.create (DF_USES_TABLE_SIZE ()); |
287 | use_def_ref.safe_grow_cleared (DF_USES_TABLE_SIZE ()); | |
e0bd4156 | 288 | |
f1f41a6c | 289 | reg_defs.create (max_reg_num ()); |
290 | reg_defs.safe_grow_cleared (max_reg_num ()); | |
e0bd4156 | 291 | |
a28770e1 | 292 | reg_defs_stack.create (n_basic_blocks_for_fn (cfun) * 10); |
2355a966 | 293 | local_md = BITMAP_ALLOC (NULL); |
426e6c73 | 294 | local_lr = BITMAP_ALLOC (NULL); |
2355a966 | 295 | |
296 | /* Walk the dominator tree looking for single reaching definitions | |
297 | dominating the uses. This is similar to how SSA form is built. */ | |
54c91640 | 298 | single_def_use_dom_walker (CDI_DOMINATORS) |
299 | .walk (cfun->cfg->x_entry_block_ptr); | |
2355a966 | 300 | |
426e6c73 | 301 | BITMAP_FREE (local_lr); |
2355a966 | 302 | BITMAP_FREE (local_md); |
f1f41a6c | 303 | reg_defs.release (); |
304 | reg_defs_stack.release (); | |
e0bd4156 | 305 | } |
2355a966 | 306 | |
42a3a38b | 307 | \f |
308 | /* Do not try to replace constant addresses or addresses of local and | |
309 | argument slots. These MEM expressions are made only once and inserted | |
310 | in many instructions, as well as being used to control symbol table | |
311 | output. It is not safe to clobber them. | |
312 | ||
313 | There are some uncommon cases where the address is already in a register | |
314 | for some reason, but we cannot take advantage of that because we have | |
315 | no easy way to unshare the MEM. In addition, looking up all stack | |
316 | addresses is costly. */ | |
317 | ||
318 | static bool | |
319 | can_simplify_addr (rtx addr) | |
320 | { | |
321 | rtx reg; | |
322 | ||
323 | if (CONSTANT_ADDRESS_P (addr)) | |
324 | return false; | |
325 | ||
326 | if (GET_CODE (addr) == PLUS) | |
327 | reg = XEXP (addr, 0); | |
328 | else | |
329 | reg = addr; | |
330 | ||
331 | return (!REG_P (reg) | |
332 | || (REGNO (reg) != FRAME_POINTER_REGNUM | |
333 | && REGNO (reg) != HARD_FRAME_POINTER_REGNUM | |
334 | && REGNO (reg) != ARG_POINTER_REGNUM)); | |
335 | } | |
336 | ||
337 | /* Returns a canonical version of X for the address, from the point of view, | |
338 | that all multiplications are represented as MULT instead of the multiply | |
339 | by a power of 2 being represented as ASHIFT. | |
340 | ||
341 | Every ASHIFT we find has been made by simplify_gen_binary and was not | |
342 | there before, so it is not shared. So we can do this in place. */ | |
343 | ||
344 | static void | |
345 | canonicalize_address (rtx x) | |
346 | { | |
347 | for (;;) | |
348 | switch (GET_CODE (x)) | |
349 | { | |
350 | case ASHIFT: | |
971ba038 | 351 | if (CONST_INT_P (XEXP (x, 1)) |
42a3a38b | 352 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (GET_MODE (x)) |
353 | && INTVAL (XEXP (x, 1)) >= 0) | |
354 | { | |
355 | HOST_WIDE_INT shift = INTVAL (XEXP (x, 1)); | |
356 | PUT_CODE (x, MULT); | |
357 | XEXP (x, 1) = gen_int_mode ((HOST_WIDE_INT) 1 << shift, | |
358 | GET_MODE (x)); | |
359 | } | |
360 | ||
361 | x = XEXP (x, 0); | |
362 | break; | |
363 | ||
364 | case PLUS: | |
365 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
366 | || GET_CODE (XEXP (x, 0)) == ASHIFT | |
367 | || GET_CODE (XEXP (x, 0)) == CONST) | |
368 | canonicalize_address (XEXP (x, 0)); | |
369 | ||
370 | x = XEXP (x, 1); | |
371 | break; | |
372 | ||
373 | case CONST: | |
374 | x = XEXP (x, 0); | |
375 | break; | |
376 | ||
377 | default: | |
378 | return; | |
379 | } | |
380 | } | |
381 | ||
382 | /* OLD is a memory address. Return whether it is good to use NEW instead, | |
383 | for a memory access in the given MODE. */ | |
384 | ||
385 | static bool | |
3754d046 | 386 | should_replace_address (rtx old_rtx, rtx new_rtx, machine_mode mode, |
bd1a81f7 | 387 | addr_space_t as, bool speed) |
42a3a38b | 388 | { |
389 | int gain; | |
390 | ||
bd1a81f7 | 391 | if (rtx_equal_p (old_rtx, new_rtx) |
392 | || !memory_address_addr_space_p (mode, new_rtx, as)) | |
42a3a38b | 393 | return false; |
394 | ||
395 | /* Copy propagation is always ok. */ | |
9ce37fa7 | 396 | if (REG_P (old_rtx) && REG_P (new_rtx)) |
42a3a38b | 397 | return true; |
398 | ||
399 | /* Prefer the new address if it is less expensive. */ | |
bd1a81f7 | 400 | gain = (address_cost (old_rtx, mode, as, speed) |
401 | - address_cost (new_rtx, mode, as, speed)); | |
42a3a38b | 402 | |
403 | /* If the addresses have equivalent cost, prefer the new address | |
7013e87c | 404 | if it has the highest `set_src_cost'. That has the potential of |
42a3a38b | 405 | eliminating the most insns without additional costs, and it |
406 | is the same that cse.c used to do. */ | |
407 | if (gain == 0) | |
5ae4887d | 408 | gain = (set_src_cost (new_rtx, VOIDmode, speed) |
409 | - set_src_cost (old_rtx, VOIDmode, speed)); | |
42a3a38b | 410 | |
411 | return (gain > 0); | |
412 | } | |
413 | ||
f8f13645 | 414 | |
415 | /* Flags for the last parameter of propagate_rtx_1. */ | |
416 | ||
417 | enum { | |
418 | /* If PR_CAN_APPEAR is true, propagate_rtx_1 always returns true; | |
419 | if it is false, propagate_rtx_1 returns false if, for at least | |
420 | one occurrence OLD, it failed to collapse the result to a constant. | |
421 | For example, (mult:M (reg:M A) (minus:M (reg:M B) (reg:M A))) may | |
422 | collapse to zero if replacing (reg:M B) with (reg:M A). | |
423 | ||
424 | PR_CAN_APPEAR is disregarded inside MEMs: in that case, | |
425 | propagate_rtx_1 just tries to make cheaper and valid memory | |
426 | addresses. */ | |
427 | PR_CAN_APPEAR = 1, | |
428 | ||
429 | /* If PR_HANDLE_MEM is not set, propagate_rtx_1 won't attempt any replacement | |
430 | outside memory addresses. This is needed because propagate_rtx_1 does | |
431 | not do any analysis on memory; thus it is very conservative and in general | |
432 | it will fail if non-read-only MEMs are found in the source expression. | |
433 | ||
434 | PR_HANDLE_MEM is set when the source of the propagation was not | |
435 | another MEM. Then, it is safe not to treat non-read-only MEMs as | |
436 | ``opaque'' objects. */ | |
f529eb25 | 437 | PR_HANDLE_MEM = 2, |
438 | ||
439 | /* Set when costs should be optimized for speed. */ | |
440 | PR_OPTIMIZE_FOR_SPEED = 4 | |
f8f13645 | 441 | }; |
442 | ||
443 | ||
42a3a38b | 444 | /* Replace all occurrences of OLD in *PX with NEW and try to simplify the |
445 | resulting expression. Replace *PX with a new RTL expression if an | |
446 | occurrence of OLD was found. | |
447 | ||
42a3a38b | 448 | This is only a wrapper around simplify-rtx.c: do not add any pattern |
449 | matching code here. (The sole exception is the handling of LO_SUM, but | |
450 | that is because there is no simplify_gen_* function for LO_SUM). */ | |
451 | ||
452 | static bool | |
9ce37fa7 | 453 | propagate_rtx_1 (rtx *px, rtx old_rtx, rtx new_rtx, int flags) |
42a3a38b | 454 | { |
455 | rtx x = *px, tem = NULL_RTX, op0, op1, op2; | |
456 | enum rtx_code code = GET_CODE (x); | |
3754d046 | 457 | machine_mode mode = GET_MODE (x); |
458 | machine_mode op_mode; | |
f8f13645 | 459 | bool can_appear = (flags & PR_CAN_APPEAR) != 0; |
42a3a38b | 460 | bool valid_ops = true; |
461 | ||
f8f13645 | 462 | if (!(flags & PR_HANDLE_MEM) && MEM_P (x) && !MEM_READONLY_P (x)) |
463 | { | |
464 | /* If unsafe, change MEMs to CLOBBERs or SCRATCHes (to preserve whether | |
465 | they have side effects or not). */ | |
466 | *px = (side_effects_p (x) | |
467 | ? gen_rtx_CLOBBER (GET_MODE (x), const0_rtx) | |
468 | : gen_rtx_SCRATCH (GET_MODE (x))); | |
469 | return false; | |
470 | } | |
42a3a38b | 471 | |
f8f13645 | 472 | /* If X is OLD_RTX, return NEW_RTX. But not if replacing only within an |
473 | address, and we are *not* inside one. */ | |
9ce37fa7 | 474 | if (x == old_rtx) |
42a3a38b | 475 | { |
9ce37fa7 | 476 | *px = new_rtx; |
42a3a38b | 477 | return can_appear; |
478 | } | |
479 | ||
f8f13645 | 480 | /* If this is an expression, try recursive substitution. */ |
42a3a38b | 481 | switch (GET_RTX_CLASS (code)) |
482 | { | |
483 | case RTX_UNARY: | |
484 | op0 = XEXP (x, 0); | |
485 | op_mode = GET_MODE (op0); | |
9ce37fa7 | 486 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
42a3a38b | 487 | if (op0 == XEXP (x, 0)) |
488 | return true; | |
489 | tem = simplify_gen_unary (code, mode, op0, op_mode); | |
490 | break; | |
491 | ||
492 | case RTX_BIN_ARITH: | |
493 | case RTX_COMM_ARITH: | |
494 | op0 = XEXP (x, 0); | |
495 | op1 = XEXP (x, 1); | |
9ce37fa7 | 496 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
497 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
42a3a38b | 498 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
499 | return true; | |
500 | tem = simplify_gen_binary (code, mode, op0, op1); | |
501 | break; | |
502 | ||
503 | case RTX_COMPARE: | |
504 | case RTX_COMM_COMPARE: | |
505 | op0 = XEXP (x, 0); | |
506 | op1 = XEXP (x, 1); | |
507 | op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1); | |
9ce37fa7 | 508 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
509 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
42a3a38b | 510 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
511 | return true; | |
512 | tem = simplify_gen_relational (code, mode, op_mode, op0, op1); | |
513 | break; | |
514 | ||
515 | case RTX_TERNARY: | |
516 | case RTX_BITFIELD_OPS: | |
517 | op0 = XEXP (x, 0); | |
518 | op1 = XEXP (x, 1); | |
519 | op2 = XEXP (x, 2); | |
520 | op_mode = GET_MODE (op0); | |
9ce37fa7 | 521 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
522 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
523 | valid_ops &= propagate_rtx_1 (&op2, old_rtx, new_rtx, flags); | |
42a3a38b | 524 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2)) |
525 | return true; | |
526 | if (op_mode == VOIDmode) | |
527 | op_mode = GET_MODE (op0); | |
528 | tem = simplify_gen_ternary (code, mode, op_mode, op0, op1, op2); | |
529 | break; | |
530 | ||
531 | case RTX_EXTRA: | |
532 | /* The only case we try to handle is a SUBREG. */ | |
533 | if (code == SUBREG) | |
534 | { | |
535 | op0 = XEXP (x, 0); | |
9ce37fa7 | 536 | valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags); |
42a3a38b | 537 | if (op0 == XEXP (x, 0)) |
538 | return true; | |
539 | tem = simplify_gen_subreg (mode, op0, GET_MODE (SUBREG_REG (x)), | |
540 | SUBREG_BYTE (x)); | |
541 | } | |
542 | break; | |
543 | ||
544 | case RTX_OBJ: | |
9ce37fa7 | 545 | if (code == MEM && x != new_rtx) |
42a3a38b | 546 | { |
547 | rtx new_op0; | |
548 | op0 = XEXP (x, 0); | |
549 | ||
550 | /* There are some addresses that we cannot work on. */ | |
551 | if (!can_simplify_addr (op0)) | |
552 | return true; | |
553 | ||
554 | op0 = new_op0 = targetm.delegitimize_address (op0); | |
9ce37fa7 | 555 | valid_ops &= propagate_rtx_1 (&new_op0, old_rtx, new_rtx, |
f8f13645 | 556 | flags | PR_CAN_APPEAR); |
42a3a38b | 557 | |
558 | /* Dismiss transformation that we do not want to carry on. */ | |
559 | if (!valid_ops | |
560 | || new_op0 == op0 | |
deb3d513 | 561 | || !(GET_MODE (new_op0) == GET_MODE (op0) |
562 | || GET_MODE (new_op0) == VOIDmode)) | |
42a3a38b | 563 | return true; |
564 | ||
565 | canonicalize_address (new_op0); | |
566 | ||
567 | /* Copy propagations are always ok. Otherwise check the costs. */ | |
9ce37fa7 | 568 | if (!(REG_P (old_rtx) && REG_P (new_rtx)) |
f529eb25 | 569 | && !should_replace_address (op0, new_op0, GET_MODE (x), |
bd1a81f7 | 570 | MEM_ADDR_SPACE (x), |
f529eb25 | 571 | flags & PR_OPTIMIZE_FOR_SPEED)) |
42a3a38b | 572 | return true; |
573 | ||
574 | tem = replace_equiv_address_nv (x, new_op0); | |
575 | } | |
576 | ||
577 | else if (code == LO_SUM) | |
578 | { | |
579 | op0 = XEXP (x, 0); | |
580 | op1 = XEXP (x, 1); | |
581 | ||
582 | /* The only simplification we do attempts to remove references to op0 | |
583 | or make it constant -- in both cases, op0's invalidity will not | |
584 | make the result invalid. */ | |
9ce37fa7 | 585 | propagate_rtx_1 (&op0, old_rtx, new_rtx, flags | PR_CAN_APPEAR); |
586 | valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags); | |
42a3a38b | 587 | if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1)) |
588 | return true; | |
589 | ||
590 | /* (lo_sum (high x) x) -> x */ | |
591 | if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1)) | |
592 | tem = op1; | |
593 | else | |
594 | tem = gen_rtx_LO_SUM (mode, op0, op1); | |
595 | ||
596 | /* OP1 is likely not a legitimate address, otherwise there would have | |
597 | been no LO_SUM. We want it to disappear if it is invalid, return | |
598 | false in that case. */ | |
599 | return memory_address_p (mode, tem); | |
600 | } | |
601 | ||
602 | else if (code == REG) | |
603 | { | |
9ce37fa7 | 604 | if (rtx_equal_p (x, old_rtx)) |
42a3a38b | 605 | { |
9ce37fa7 | 606 | *px = new_rtx; |
42a3a38b | 607 | return can_appear; |
608 | } | |
609 | } | |
610 | break; | |
611 | ||
612 | default: | |
613 | break; | |
614 | } | |
615 | ||
616 | /* No change, no trouble. */ | |
617 | if (tem == NULL_RTX) | |
618 | return true; | |
619 | ||
620 | *px = tem; | |
621 | ||
622 | /* The replacement we made so far is valid, if all of the recursive | |
623 | replacements were valid, or we could simplify everything to | |
624 | a constant. */ | |
625 | return valid_ops || can_appear || CONSTANT_P (tem); | |
626 | } | |
627 | ||
f8f13645 | 628 | |
e32f8fb9 | 629 | /* Return true if X constains a non-constant mem. */ |
f8f13645 | 630 | |
e32f8fb9 | 631 | static bool |
632 | varying_mem_p (const_rtx x) | |
f8f13645 | 633 | { |
e32f8fb9 | 634 | subrtx_iterator::array_type array; |
635 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
636 | if (MEM_P (*iter) && !MEM_READONLY_P (*iter)) | |
637 | return true; | |
638 | return false; | |
f8f13645 | 639 | } |
640 | ||
641 | ||
42a3a38b | 642 | /* Replace all occurrences of OLD in X with NEW and try to simplify the |
fa7637bd | 643 | resulting expression (in mode MODE). Return a new expression if it is |
42a3a38b | 644 | a constant, otherwise X. |
645 | ||
646 | Simplifications where occurrences of NEW collapse to a constant are always | |
647 | accepted. All simplifications are accepted if NEW is a pseudo too. | |
648 | Otherwise, we accept simplifications that have a lower or equal cost. */ | |
649 | ||
650 | static rtx | |
3754d046 | 651 | propagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx, |
f529eb25 | 652 | bool speed) |
42a3a38b | 653 | { |
654 | rtx tem; | |
655 | bool collapsed; | |
f8f13645 | 656 | int flags; |
42a3a38b | 657 | |
9ce37fa7 | 658 | if (REG_P (new_rtx) && REGNO (new_rtx) < FIRST_PSEUDO_REGISTER) |
42a3a38b | 659 | return NULL_RTX; |
660 | ||
f8f13645 | 661 | flags = 0; |
03ad17bf | 662 | if (REG_P (new_rtx) |
663 | || CONSTANT_P (new_rtx) | |
664 | || (GET_CODE (new_rtx) == SUBREG | |
665 | && REG_P (SUBREG_REG (new_rtx)) | |
666 | && (GET_MODE_SIZE (mode) | |
667 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (new_rtx)))))) | |
f8f13645 | 668 | flags |= PR_CAN_APPEAR; |
e32f8fb9 | 669 | if (!varying_mem_p (new_rtx)) |
f8f13645 | 670 | flags |= PR_HANDLE_MEM; |
42a3a38b | 671 | |
f529eb25 | 672 | if (speed) |
673 | flags |= PR_OPTIMIZE_FOR_SPEED; | |
674 | ||
42a3a38b | 675 | tem = x; |
9ce37fa7 | 676 | collapsed = propagate_rtx_1 (&tem, old_rtx, copy_rtx (new_rtx), flags); |
42a3a38b | 677 | if (tem == x || !collapsed) |
678 | return NULL_RTX; | |
679 | ||
680 | /* gen_lowpart_common will not be able to process VOIDmode entities other | |
681 | than CONST_INTs. */ | |
971ba038 | 682 | if (GET_MODE (tem) == VOIDmode && !CONST_INT_P (tem)) |
42a3a38b | 683 | return NULL_RTX; |
684 | ||
685 | if (GET_MODE (tem) == VOIDmode) | |
686 | tem = rtl_hooks.gen_lowpart_no_emit (mode, tem); | |
687 | else | |
688 | gcc_assert (GET_MODE (tem) == mode); | |
689 | ||
690 | return tem; | |
691 | } | |
692 | ||
693 | ||
694 | \f | |
695 | ||
696 | /* Return true if the register from reference REF is killed | |
697 | between FROM to (but not including) TO. */ | |
698 | ||
3072d30e | 699 | static bool |
51e49a15 | 700 | local_ref_killed_between_p (df_ref ref, rtx_insn *from, rtx_insn *to) |
42a3a38b | 701 | { |
51e49a15 | 702 | rtx_insn *insn; |
42a3a38b | 703 | |
704 | for (insn = from; insn != to; insn = NEXT_INSN (insn)) | |
705 | { | |
be10bb5a | 706 | df_ref def; |
42a3a38b | 707 | if (!INSN_P (insn)) |
708 | continue; | |
709 | ||
be10bb5a | 710 | FOR_EACH_INSN_DEF (def, insn) |
711 | if (DF_REF_REGNO (ref) == DF_REF_REGNO (def)) | |
712 | return true; | |
42a3a38b | 713 | } |
714 | return false; | |
715 | } | |
716 | ||
717 | ||
718 | /* Check if the given DEF is available in INSN. This would require full | |
719 | computation of available expressions; we check only restricted conditions: | |
720 | - if DEF is the sole definition of its register, go ahead; | |
721 | - in the same basic block, we check for no definitions killing the | |
722 | definition of DEF_INSN; | |
723 | - if USE's basic block has DEF's basic block as the sole predecessor, | |
724 | we check if the definition is killed after DEF_INSN or before | |
725 | TARGET_INSN insn, in their respective basic blocks. */ | |
726 | static bool | |
dea92746 | 727 | use_killed_between (df_ref use, rtx_insn *def_insn, rtx_insn *target_insn) |
42a3a38b | 728 | { |
a39fe687 | 729 | basic_block def_bb = BLOCK_FOR_INSN (def_insn); |
730 | basic_block target_bb = BLOCK_FOR_INSN (target_insn); | |
42a3a38b | 731 | int regno; |
ed6e85ae | 732 | df_ref def; |
42a3a38b | 733 | |
2355a966 | 734 | /* We used to have a def reaching a use that is _before_ the def, |
735 | with the def not dominating the use even though the use and def | |
736 | are in the same basic block, when a register may be used | |
737 | uninitialized in a loop. This should not happen anymore since | |
738 | we do not use reaching definitions, but still we test for such | |
739 | cases and assume that DEF is not available. */ | |
a39fe687 | 740 | if (def_bb == target_bb |
3072d30e | 741 | ? DF_INSN_LUID (def_insn) >= DF_INSN_LUID (target_insn) |
a39fe687 | 742 | : !dominated_by_p (CDI_DOMINATORS, target_bb, def_bb)) |
743 | return true; | |
744 | ||
42a3a38b | 745 | /* Check if the reg in USE has only one definition. We already |
1a665a74 | 746 | know that this definition reaches use, or we wouldn't be here. |
747 | However, this is invalid for hard registers because if they are | |
748 | live at the beginning of the function it does not mean that we | |
749 | have an uninitialized access. */ | |
42a3a38b | 750 | regno = DF_REF_REGNO (use); |
3072d30e | 751 | def = DF_REG_DEF_CHAIN (regno); |
1a665a74 | 752 | if (def |
ed6e85ae | 753 | && DF_REF_NEXT_REG (def) == NULL |
1a665a74 | 754 | && regno >= FIRST_PSEUDO_REGISTER) |
42a3a38b | 755 | return false; |
756 | ||
a39fe687 | 757 | /* Check locally if we are in the same basic block. */ |
42a3a38b | 758 | if (def_bb == target_bb) |
a39fe687 | 759 | return local_ref_killed_between_p (use, def_insn, target_insn); |
42a3a38b | 760 | |
761 | /* Finally, if DEF_BB is the sole predecessor of TARGET_BB. */ | |
762 | if (single_pred_p (target_bb) | |
763 | && single_pred (target_bb) == def_bb) | |
764 | { | |
ed6e85ae | 765 | df_ref x; |
42a3a38b | 766 | |
767 | /* See if USE is killed between DEF_INSN and the last insn in the | |
768 | basic block containing DEF_INSN. */ | |
3072d30e | 769 | x = df_bb_regno_last_def_find (def_bb, regno); |
158b6cc9 | 770 | if (x && DF_INSN_LUID (DF_REF_INSN (x)) >= DF_INSN_LUID (def_insn)) |
42a3a38b | 771 | return true; |
772 | ||
773 | /* See if USE is killed between TARGET_INSN and the first insn in the | |
774 | basic block containing TARGET_INSN. */ | |
3072d30e | 775 | x = df_bb_regno_first_def_find (target_bb, regno); |
158b6cc9 | 776 | if (x && DF_INSN_LUID (DF_REF_INSN (x)) < DF_INSN_LUID (target_insn)) |
42a3a38b | 777 | return true; |
778 | ||
779 | return false; | |
780 | } | |
781 | ||
782 | /* Otherwise assume the worst case. */ | |
783 | return true; | |
784 | } | |
785 | ||
786 | ||
42a3a38b | 787 | /* Check if all uses in DEF_INSN can be used in TARGET_INSN. This |
788 | would require full computation of available expressions; | |
789 | we check only restricted conditions, see use_killed_between. */ | |
790 | static bool | |
dea92746 | 791 | all_uses_available_at (rtx_insn *def_insn, rtx_insn *target_insn) |
42a3a38b | 792 | { |
be10bb5a | 793 | df_ref use; |
158b6cc9 | 794 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn); |
42a3a38b | 795 | rtx def_set = single_set (def_insn); |
dea92746 | 796 | rtx_insn *next; |
42a3a38b | 797 | |
798 | gcc_assert (def_set); | |
799 | ||
800 | /* If target_insn comes right after def_insn, which is very common | |
29b2949c | 801 | for addresses, we can use a quicker test. Ignore debug insns |
802 | other than target insns for this. */ | |
803 | next = NEXT_INSN (def_insn); | |
804 | while (next && next != target_insn && DEBUG_INSN_P (next)) | |
805 | next = NEXT_INSN (next); | |
806 | if (next == target_insn && REG_P (SET_DEST (def_set))) | |
42a3a38b | 807 | { |
808 | rtx def_reg = SET_DEST (def_set); | |
809 | ||
810 | /* If the insn uses the reg that it defines, the substitution is | |
811 | invalid. */ | |
be10bb5a | 812 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
813 | if (rtx_equal_p (DF_REF_REG (use), def_reg)) | |
814 | return false; | |
815 | FOR_EACH_INSN_INFO_EQ_USE (use, insn_info) | |
816 | if (rtx_equal_p (DF_REF_REG (use), def_reg)) | |
817 | return false; | |
42a3a38b | 818 | } |
819 | else | |
820 | { | |
c4b594c1 | 821 | rtx def_reg = REG_P (SET_DEST (def_set)) ? SET_DEST (def_set) : NULL_RTX; |
822 | ||
42a3a38b | 823 | /* Look at all the uses of DEF_INSN, and see if they are not |
824 | killed between DEF_INSN and TARGET_INSN. */ | |
be10bb5a | 825 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
3072d30e | 826 | { |
c4b594c1 | 827 | if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg)) |
828 | return false; | |
3072d30e | 829 | if (use_killed_between (use, def_insn, target_insn)) |
830 | return false; | |
831 | } | |
be10bb5a | 832 | FOR_EACH_INSN_INFO_EQ_USE (use, insn_info) |
3072d30e | 833 | { |
c4b594c1 | 834 | if (def_reg && rtx_equal_p (DF_REF_REG (use), def_reg)) |
835 | return false; | |
3072d30e | 836 | if (use_killed_between (use, def_insn, target_insn)) |
837 | return false; | |
838 | } | |
42a3a38b | 839 | } |
840 | ||
f8f13645 | 841 | return true; |
42a3a38b | 842 | } |
843 | ||
844 | \f | |
4ffe0526 | 845 | static df_ref *active_defs; |
4ffe0526 | 846 | static sparseset active_defs_check; |
42a3a38b | 847 | |
4ffe0526 | 848 | /* Fill the ACTIVE_DEFS array with the use->def link for the registers |
849 | mentioned in USE_REC. Register the valid entries in ACTIVE_DEFS_CHECK | |
850 | too, for checking purposes. */ | |
42a3a38b | 851 | |
4ffe0526 | 852 | static void |
ddc2d0e3 | 853 | register_active_defs (df_ref use) |
42a3a38b | 854 | { |
ddc2d0e3 | 855 | for (; use; use = DF_REF_NEXT_LOC (use)) |
42a3a38b | 856 | { |
4ffe0526 | 857 | df_ref def = get_def_for_use (use); |
858 | int regno = DF_REF_REGNO (use); | |
42a3a38b | 859 | |
382ecba7 | 860 | if (flag_checking) |
861 | sparseset_set_bit (active_defs_check, regno); | |
4ffe0526 | 862 | active_defs[regno] = def; |
863 | } | |
42a3a38b | 864 | } |
865 | ||
42a3a38b | 866 | |
4ffe0526 | 867 | /* Build the use->def links that we use to update the dataflow info |
868 | for new uses. Note that building the links is very cheap and if | |
869 | it were done earlier, they could be used to rule out invalid | |
870 | propagations (in addition to what is done in all_uses_available_at). | |
871 | I'm not doing this yet, though. */ | |
872 | ||
873 | static void | |
dea92746 | 874 | update_df_init (rtx_insn *def_insn, rtx_insn *insn) |
42a3a38b | 875 | { |
382ecba7 | 876 | if (flag_checking) |
877 | sparseset_clear (active_defs_check); | |
4ffe0526 | 878 | register_active_defs (DF_INSN_USES (def_insn)); |
879 | register_active_defs (DF_INSN_USES (insn)); | |
880 | register_active_defs (DF_INSN_EQ_USES (insn)); | |
881 | } | |
42a3a38b | 882 | |
42a3a38b | 883 | |
4ffe0526 | 884 | /* Update the USE_DEF_REF array for the given use, using the active definitions |
885 | in the ACTIVE_DEFS array to match pseudos to their def. */ | |
42a3a38b | 886 | |
4ffe0526 | 887 | static inline void |
ddc2d0e3 | 888 | update_uses (df_ref use) |
42a3a38b | 889 | { |
ddc2d0e3 | 890 | for (; use; use = DF_REF_NEXT_LOC (use)) |
42a3a38b | 891 | { |
4ffe0526 | 892 | int regno = DF_REF_REGNO (use); |
42a3a38b | 893 | |
4ffe0526 | 894 | /* Set up the use-def chain. */ |
f1f41a6c | 895 | if (DF_REF_ID (use) >= (int) use_def_ref.length ()) |
896 | use_def_ref.safe_grow_cleared (DF_REF_ID (use) + 1); | |
42a3a38b | 897 | |
376f7257 | 898 | if (flag_checking) |
899 | gcc_assert (sparseset_bit_p (active_defs_check, regno)); | |
f1f41a6c | 900 | use_def_ref[DF_REF_ID (use)] = active_defs[regno]; |
4ffe0526 | 901 | } |
902 | } | |
42a3a38b | 903 | |
4ffe0526 | 904 | |
905 | /* Update the USE_DEF_REF array for the uses in INSN. Only update note | |
906 | uses if NOTES_ONLY is true. */ | |
907 | ||
908 | static void | |
dea92746 | 909 | update_df (rtx_insn *insn, rtx note) |
4ffe0526 | 910 | { |
911 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); | |
912 | ||
913 | if (note) | |
914 | { | |
915 | df_uses_create (&XEXP (note, 0), insn, DF_REF_IN_NOTE); | |
916 | df_notes_rescan (insn); | |
917 | } | |
918 | else | |
919 | { | |
920 | df_uses_create (&PATTERN (insn), insn, 0); | |
921 | df_insn_rescan (insn); | |
922 | update_uses (DF_INSN_INFO_USES (insn_info)); | |
42a3a38b | 923 | } |
4ffe0526 | 924 | |
925 | update_uses (DF_INSN_INFO_EQ_USES (insn_info)); | |
42a3a38b | 926 | } |
927 | ||
928 | ||
929 | /* Try substituting NEW into LOC, which originated from forward propagation | |
930 | of USE's value from DEF_INSN. SET_REG_EQUAL says whether we are | |
931 | substituting the whole SET_SRC, so we can set a REG_EQUAL note if the | |
932 | new insn is not recognized. Return whether the substitution was | |
933 | performed. */ | |
934 | ||
935 | static bool | |
dea92746 | 936 | try_fwprop_subst (df_ref use, rtx *loc, rtx new_rtx, rtx_insn *def_insn, |
937 | bool set_reg_equal) | |
42a3a38b | 938 | { |
dea92746 | 939 | rtx_insn *insn = DF_REF_INSN (use); |
91bd874e | 940 | rtx set = single_set (insn); |
4ffe0526 | 941 | rtx note = NULL_RTX; |
f529eb25 | 942 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
f92bd2dd | 943 | int old_cost = 0; |
91bd874e | 944 | bool ok; |
42a3a38b | 945 | |
4ffe0526 | 946 | update_df_init (def_insn, insn); |
947 | ||
f92bd2dd | 948 | /* forward_propagate_subreg may be operating on an instruction with |
949 | multiple sets. If so, assume the cost of the new instruction is | |
950 | not greater than the old one. */ | |
951 | if (set) | |
5ae4887d | 952 | old_cost = set_src_cost (SET_SRC (set), GET_MODE (SET_DEST (set)), speed); |
42a3a38b | 953 | if (dump_file) |
954 | { | |
955 | fprintf (dump_file, "\nIn insn %d, replacing\n ", INSN_UID (insn)); | |
956 | print_inline_rtx (dump_file, *loc, 2); | |
957 | fprintf (dump_file, "\n with "); | |
9ce37fa7 | 958 | print_inline_rtx (dump_file, new_rtx, 2); |
42a3a38b | 959 | fprintf (dump_file, "\n"); |
960 | } | |
961 | ||
9ce37fa7 | 962 | validate_unshare_change (insn, loc, new_rtx, true); |
91bd874e | 963 | if (!verify_changes (0)) |
964 | { | |
965 | if (dump_file) | |
966 | fprintf (dump_file, "Changes to insn %d not recognized\n", | |
967 | INSN_UID (insn)); | |
968 | ok = false; | |
969 | } | |
970 | ||
f4d72632 | 971 | else if (DF_REF_TYPE (use) == DF_REF_REG_USE |
f92bd2dd | 972 | && set |
5ae4887d | 973 | && (set_src_cost (SET_SRC (set), GET_MODE (SET_DEST (set)), speed) |
974 | > old_cost)) | |
91bd874e | 975 | { |
976 | if (dump_file) | |
977 | fprintf (dump_file, "Changes to insn %d not profitable\n", | |
978 | INSN_UID (insn)); | |
979 | ok = false; | |
980 | } | |
981 | ||
982 | else | |
42a3a38b | 983 | { |
42a3a38b | 984 | if (dump_file) |
985 | fprintf (dump_file, "Changed insn %d\n", INSN_UID (insn)); | |
91bd874e | 986 | ok = true; |
987 | } | |
988 | ||
989 | if (ok) | |
990 | { | |
991 | confirm_change_group (); | |
992 | num_changes++; | |
42a3a38b | 993 | } |
994 | else | |
995 | { | |
91bd874e | 996 | cancel_changes (0); |
42a3a38b | 997 | |
dec9a6b8 | 998 | /* Can also record a simplified value in a REG_EQUAL note, |
1e5b92fa | 999 | making a new one if one does not already exist. */ |
1000 | if (set_reg_equal) | |
42a3a38b | 1001 | { |
1002 | if (dump_file) | |
1003 | fprintf (dump_file, " Setting REG_EQUAL note\n"); | |
1004 | ||
4ffe0526 | 1005 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (new_rtx)); |
42a3a38b | 1006 | } |
42a3a38b | 1007 | } |
91bd874e | 1008 | |
4ffe0526 | 1009 | if ((ok || note) && !CONSTANT_P (new_rtx)) |
1010 | update_df (insn, note); | |
1011 | ||
91bd874e | 1012 | return ok; |
42a3a38b | 1013 | } |
1014 | ||
42ed3b17 | 1015 | /* For the given single_set INSN, containing SRC known to be a |
1016 | ZERO_EXTEND or SIGN_EXTEND of a register, return true if INSN | |
1017 | is redundant due to the register being set by a LOAD_EXTEND_OP | |
1018 | load from memory. */ | |
1019 | ||
1020 | static bool | |
dea92746 | 1021 | free_load_extend (rtx src, rtx_insn *insn) |
f92bd2dd | 1022 | { |
42ed3b17 | 1023 | rtx reg; |
be10bb5a | 1024 | df_ref def, use; |
42ed3b17 | 1025 | |
1026 | reg = XEXP (src, 0); | |
1027 | #ifdef LOAD_EXTEND_OP | |
1028 | if (LOAD_EXTEND_OP (GET_MODE (reg)) != GET_CODE (src)) | |
1029 | #endif | |
1030 | return false; | |
f92bd2dd | 1031 | |
be10bb5a | 1032 | FOR_EACH_INSN_USE (use, insn) |
1033 | if (!DF_REF_IS_ARTIFICIAL (use) | |
1034 | && DF_REF_TYPE (use) == DF_REF_REG_USE | |
1035 | && DF_REF_REG (use) == reg) | |
1036 | break; | |
42ed3b17 | 1037 | if (!use) |
1038 | return false; | |
1039 | ||
1040 | def = get_def_for_use (use); | |
1041 | if (!def) | |
1042 | return false; | |
1043 | ||
1044 | if (DF_REF_IS_ARTIFICIAL (def)) | |
1045 | return false; | |
1046 | ||
1047 | if (NONJUMP_INSN_P (DF_REF_INSN (def))) | |
1048 | { | |
1049 | rtx patt = PATTERN (DF_REF_INSN (def)); | |
1050 | ||
1051 | if (GET_CODE (patt) == SET | |
1052 | && GET_CODE (SET_SRC (patt)) == MEM | |
1053 | && rtx_equal_p (SET_DEST (patt), reg)) | |
1054 | return true; | |
f92bd2dd | 1055 | } |
42ed3b17 | 1056 | return false; |
f92bd2dd | 1057 | } |
f92bd2dd | 1058 | |
1059 | /* If USE is a subreg, see if it can be replaced by a pseudo. */ | |
42a3a38b | 1060 | |
1061 | static bool | |
dea92746 | 1062 | forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set) |
42a3a38b | 1063 | { |
1064 | rtx use_reg = DF_REF_REG (use); | |
dea92746 | 1065 | rtx_insn *use_insn; |
1066 | rtx src; | |
42a3a38b | 1067 | |
f92bd2dd | 1068 | /* Only consider subregs... */ |
3754d046 | 1069 | machine_mode use_mode = GET_MODE (use_reg); |
42a3a38b | 1070 | if (GET_CODE (use_reg) != SUBREG |
f92bd2dd | 1071 | || !REG_P (SET_DEST (def_set))) |
42a3a38b | 1072 | return false; |
1073 | ||
f92bd2dd | 1074 | /* If this is a paradoxical SUBREG... */ |
1075 | if (GET_MODE_SIZE (use_mode) | |
1076 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (use_reg)))) | |
1077 | { | |
1078 | /* If this is a paradoxical SUBREG, we have no idea what value the | |
1079 | extra bits would have. However, if the operand is equivalent to | |
1080 | a SUBREG whose operand is the same as our mode, and all the modes | |
1081 | are within a word, we can just use the inner operand because | |
1082 | these SUBREGs just say how to treat the register. */ | |
1083 | use_insn = DF_REF_INSN (use); | |
1084 | src = SET_SRC (def_set); | |
1085 | if (GET_CODE (src) == SUBREG | |
1086 | && REG_P (SUBREG_REG (src)) | |
3014ed2c | 1087 | && REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER |
f92bd2dd | 1088 | && GET_MODE (SUBREG_REG (src)) == use_mode |
1089 | && subreg_lowpart_p (src) | |
1090 | && all_uses_available_at (def_insn, use_insn)) | |
1091 | return try_fwprop_subst (use, DF_REF_LOC (use), SUBREG_REG (src), | |
1092 | def_insn, false); | |
1093 | } | |
1094 | ||
1095 | /* If this is a SUBREG of a ZERO_EXTEND or SIGN_EXTEND, and the SUBREG | |
1096 | is the low part of the reg being extended then just use the inner | |
1097 | operand. Don't do this if the ZERO_EXTEND or SIGN_EXTEND insn will | |
7947d89c | 1098 | be removed due to it matching a LOAD_EXTEND_OP load from memory, |
1099 | or due to the operation being a no-op when applied to registers. | |
1100 | For example, if we have: | |
1101 | ||
1102 | A: (set (reg:DI X) (sign_extend:DI (reg:SI Y))) | |
1103 | B: (... (subreg:SI (reg:DI X)) ...) | |
1104 | ||
1105 | and mode_rep_extended says that Y is already sign-extended, | |
1106 | the backend will typically allow A to be combined with the | |
1107 | definition of Y or, failing that, allow A to be deleted after | |
1108 | reload through register tying. Introducing more uses of Y | |
1109 | prevents both optimisations. */ | |
f92bd2dd | 1110 | else if (subreg_lowpart_p (use_reg)) |
1111 | { | |
f92bd2dd | 1112 | use_insn = DF_REF_INSN (use); |
1113 | src = SET_SRC (def_set); | |
1114 | if ((GET_CODE (src) == ZERO_EXTEND | |
1115 | || GET_CODE (src) == SIGN_EXTEND) | |
1116 | && REG_P (XEXP (src, 0)) | |
3014ed2c | 1117 | && REGNO (XEXP (src, 0)) >= FIRST_PSEUDO_REGISTER |
f92bd2dd | 1118 | && GET_MODE (XEXP (src, 0)) == use_mode |
42ed3b17 | 1119 | && !free_load_extend (src, def_insn) |
7947d89c | 1120 | && (targetm.mode_rep_extended (use_mode, GET_MODE (src)) |
1121 | != (int) GET_CODE (src)) | |
f92bd2dd | 1122 | && all_uses_available_at (def_insn, use_insn)) |
1123 | return try_fwprop_subst (use, DF_REF_LOC (use), XEXP (src, 0), | |
1124 | def_insn, false); | |
1125 | } | |
1126 | ||
1127 | return false; | |
42a3a38b | 1128 | } |
1129 | ||
abe2d6dd | 1130 | /* Try to replace USE with SRC (defined in DEF_INSN) in __asm. */ |
1131 | ||
1132 | static bool | |
dea92746 | 1133 | forward_propagate_asm (df_ref use, rtx_insn *def_insn, rtx def_set, rtx reg) |
abe2d6dd | 1134 | { |
dea92746 | 1135 | rtx_insn *use_insn = DF_REF_INSN (use); |
1136 | rtx src, use_pat, asm_operands, new_rtx, *loc; | |
abe2d6dd | 1137 | int speed_p, i; |
ddc2d0e3 | 1138 | df_ref uses; |
abe2d6dd | 1139 | |
1140 | gcc_assert ((DF_REF_FLAGS (use) & DF_REF_IN_NOTE) == 0); | |
1141 | ||
1142 | src = SET_SRC (def_set); | |
1143 | use_pat = PATTERN (use_insn); | |
1144 | ||
1145 | /* In __asm don't replace if src might need more registers than | |
1146 | reg, as that could increase register pressure on the __asm. */ | |
ddc2d0e3 | 1147 | uses = DF_INSN_USES (def_insn); |
1148 | if (uses && DF_REF_NEXT_LOC (uses)) | |
abe2d6dd | 1149 | return false; |
1150 | ||
4ffe0526 | 1151 | update_df_init (def_insn, use_insn); |
abe2d6dd | 1152 | speed_p = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); |
1153 | asm_operands = NULL_RTX; | |
1154 | switch (GET_CODE (use_pat)) | |
1155 | { | |
1156 | case ASM_OPERANDS: | |
1157 | asm_operands = use_pat; | |
1158 | break; | |
1159 | case SET: | |
1160 | if (MEM_P (SET_DEST (use_pat))) | |
1161 | { | |
1162 | loc = &SET_DEST (use_pat); | |
1163 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p); | |
1164 | if (new_rtx) | |
1165 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1166 | } | |
1167 | asm_operands = SET_SRC (use_pat); | |
1168 | break; | |
1169 | case PARALLEL: | |
1170 | for (i = 0; i < XVECLEN (use_pat, 0); i++) | |
1171 | if (GET_CODE (XVECEXP (use_pat, 0, i)) == SET) | |
1172 | { | |
1173 | if (MEM_P (SET_DEST (XVECEXP (use_pat, 0, i)))) | |
1174 | { | |
1175 | loc = &SET_DEST (XVECEXP (use_pat, 0, i)); | |
1176 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, | |
1177 | src, speed_p); | |
1178 | if (new_rtx) | |
1179 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1180 | } | |
1181 | asm_operands = SET_SRC (XVECEXP (use_pat, 0, i)); | |
1182 | } | |
1183 | else if (GET_CODE (XVECEXP (use_pat, 0, i)) == ASM_OPERANDS) | |
1184 | asm_operands = XVECEXP (use_pat, 0, i); | |
1185 | break; | |
1186 | default: | |
1187 | gcc_unreachable (); | |
1188 | } | |
1189 | ||
1190 | gcc_assert (asm_operands && GET_CODE (asm_operands) == ASM_OPERANDS); | |
1191 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (asm_operands); i++) | |
1192 | { | |
1193 | loc = &ASM_OPERANDS_INPUT (asm_operands, i); | |
1194 | new_rtx = propagate_rtx (*loc, GET_MODE (*loc), reg, src, speed_p); | |
1195 | if (new_rtx) | |
1196 | validate_unshare_change (use_insn, loc, new_rtx, true); | |
1197 | } | |
1198 | ||
1199 | if (num_changes_pending () == 0 || !apply_change_group ()) | |
1200 | return false; | |
1201 | ||
4ffe0526 | 1202 | update_df (use_insn, NULL); |
abe2d6dd | 1203 | num_changes++; |
1204 | return true; | |
1205 | } | |
1206 | ||
42a3a38b | 1207 | /* Try to replace USE with SRC (defined in DEF_INSN) and simplify the |
1208 | result. */ | |
1209 | ||
1210 | static bool | |
dea92746 | 1211 | forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set) |
42a3a38b | 1212 | { |
dea92746 | 1213 | rtx_insn *use_insn = DF_REF_INSN (use); |
42a3a38b | 1214 | rtx use_set = single_set (use_insn); |
9ce37fa7 | 1215 | rtx src, reg, new_rtx, *loc; |
42a3a38b | 1216 | bool set_reg_equal; |
3754d046 | 1217 | machine_mode mode; |
abe2d6dd | 1218 | int asm_use = -1; |
1219 | ||
1220 | if (INSN_CODE (use_insn) < 0) | |
1221 | asm_use = asm_noperands (PATTERN (use_insn)); | |
42a3a38b | 1222 | |
9845d120 | 1223 | if (!use_set && asm_use < 0 && !DEBUG_INSN_P (use_insn)) |
42a3a38b | 1224 | return false; |
1225 | ||
1226 | /* Do not propagate into PC, CC0, etc. */ | |
abe2d6dd | 1227 | if (use_set && GET_MODE (SET_DEST (use_set)) == VOIDmode) |
42a3a38b | 1228 | return false; |
1229 | ||
1230 | /* If def and use are subreg, check if they match. */ | |
1231 | reg = DF_REF_REG (use); | |
d2efb29d | 1232 | if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG) |
1233 | { | |
1234 | if (SUBREG_BYTE (SET_DEST (def_set)) != SUBREG_BYTE (reg)) | |
1235 | return false; | |
1236 | } | |
42a3a38b | 1237 | /* Check if the def had a subreg, but the use has the whole reg. */ |
d2efb29d | 1238 | else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG) |
42a3a38b | 1239 | return false; |
42a3a38b | 1240 | /* Check if the use has a subreg, but the def had the whole reg. Unlike the |
1241 | previous case, the optimization is possible and often useful indeed. */ | |
d2efb29d | 1242 | else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set))) |
42a3a38b | 1243 | reg = SUBREG_REG (reg); |
1244 | ||
d2efb29d | 1245 | /* Make sure that we can treat REG as having the same mode as the |
1246 | source of DEF_SET. */ | |
1247 | if (GET_MODE (SET_DEST (def_set)) != GET_MODE (reg)) | |
1248 | return false; | |
1249 | ||
42a3a38b | 1250 | /* Check if the substitution is valid (last, because it's the most |
1251 | expensive check!). */ | |
1252 | src = SET_SRC (def_set); | |
1253 | if (!CONSTANT_P (src) && !all_uses_available_at (def_insn, use_insn)) | |
1254 | return false; | |
1255 | ||
1256 | /* Check if the def is loading something from the constant pool; in this | |
1257 | case we would undo optimization such as compress_float_constant. | |
1258 | Still, we can set a REG_EQUAL note. */ | |
1259 | if (MEM_P (src) && MEM_READONLY_P (src)) | |
1260 | { | |
1261 | rtx x = avoid_constant_pool_reference (src); | |
abe2d6dd | 1262 | if (x != src && use_set) |
42a3a38b | 1263 | { |
1264 | rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
9ce37fa7 | 1265 | rtx old_rtx = note ? XEXP (note, 0) : SET_SRC (use_set); |
1266 | rtx new_rtx = simplify_replace_rtx (old_rtx, src, x); | |
1267 | if (old_rtx != new_rtx) | |
1268 | set_unique_reg_note (use_insn, REG_EQUAL, copy_rtx (new_rtx)); | |
42a3a38b | 1269 | } |
1270 | return false; | |
1271 | } | |
1272 | ||
abe2d6dd | 1273 | if (asm_use >= 0) |
1274 | return forward_propagate_asm (use, def_insn, def_set, reg); | |
1275 | ||
42a3a38b | 1276 | /* Else try simplifying. */ |
1277 | ||
1278 | if (DF_REF_TYPE (use) == DF_REF_REG_MEM_STORE) | |
1279 | { | |
1280 | loc = &SET_DEST (use_set); | |
1281 | set_reg_equal = false; | |
1282 | } | |
9845d120 | 1283 | else if (!use_set) |
1284 | { | |
1285 | loc = &INSN_VAR_LOCATION_LOC (use_insn); | |
1286 | set_reg_equal = false; | |
1287 | } | |
42a3a38b | 1288 | else |
1289 | { | |
1290 | rtx note = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
1291 | if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE) | |
1292 | loc = &XEXP (note, 0); | |
1293 | else | |
1294 | loc = &SET_SRC (use_set); | |
3072d30e | 1295 | |
42a3a38b | 1296 | /* Do not replace an existing REG_EQUAL note if the insn is not |
93d89886 | 1297 | recognized. Either we're already replacing in the note, or we'll |
1298 | separately try plugging the definition in the note and simplifying. | |
44433d3b | 1299 | And only install a REQ_EQUAL note when the destination is a REG |
1300 | that isn't mentioned in USE_SET, as the note would be invalid | |
a24ec999 | 1301 | otherwise. We also don't want to install a note if we are merely |
1302 | propagating a pseudo since verifying that this pseudo isn't dead | |
1303 | is a pain; moreover such a note won't help anything. */ | |
1304 | set_reg_equal = (note == NULL_RTX | |
1305 | && REG_P (SET_DEST (use_set)) | |
1306 | && !REG_P (src) | |
1307 | && !(GET_CODE (src) == SUBREG | |
1308 | && REG_P (SUBREG_REG (src))) | |
1309 | && !reg_mentioned_p (SET_DEST (use_set), | |
1310 | SET_SRC (use_set))); | |
42a3a38b | 1311 | } |
1312 | ||
1313 | if (GET_MODE (*loc) == VOIDmode) | |
1314 | mode = GET_MODE (SET_DEST (use_set)); | |
1315 | else | |
1316 | mode = GET_MODE (*loc); | |
1317 | ||
f529eb25 | 1318 | new_rtx = propagate_rtx (*loc, mode, reg, src, |
1319 | optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn))); | |
3072d30e | 1320 | |
9ce37fa7 | 1321 | if (!new_rtx) |
42a3a38b | 1322 | return false; |
1323 | ||
9ce37fa7 | 1324 | return try_fwprop_subst (use, loc, new_rtx, def_insn, set_reg_equal); |
42a3a38b | 1325 | } |
1326 | ||
1327 | ||
1328 | /* Given a use USE of an insn, if it has a single reaching | |
f9460785 | 1329 | definition, try to forward propagate it into that insn. |
1330 | Return true if cfg cleanup will be needed. */ | |
42a3a38b | 1331 | |
f9460785 | 1332 | static bool |
ed6e85ae | 1333 | forward_propagate_into (df_ref use) |
42a3a38b | 1334 | { |
ed6e85ae | 1335 | df_ref def; |
dea92746 | 1336 | rtx_insn *def_insn, *use_insn; |
1337 | rtx def_set; | |
3072d30e | 1338 | rtx parent; |
42a3a38b | 1339 | |
1340 | if (DF_REF_FLAGS (use) & DF_REF_READ_WRITE) | |
f9460785 | 1341 | return false; |
3072d30e | 1342 | if (DF_REF_IS_ARTIFICIAL (use)) |
f9460785 | 1343 | return false; |
42a3a38b | 1344 | |
1345 | /* Only consider uses that have a single definition. */ | |
e0bd4156 | 1346 | def = get_def_for_use (use); |
1347 | if (!def) | |
f9460785 | 1348 | return false; |
42a3a38b | 1349 | if (DF_REF_FLAGS (def) & DF_REF_READ_WRITE) |
f9460785 | 1350 | return false; |
3072d30e | 1351 | if (DF_REF_IS_ARTIFICIAL (def)) |
f9460785 | 1352 | return false; |
42a3a38b | 1353 | |
243f24c5 | 1354 | /* Do not propagate loop invariant definitions inside the loop. */ |
1355 | if (DF_REF_BB (def)->loop_father != DF_REF_BB (use)->loop_father) | |
f9460785 | 1356 | return false; |
42a3a38b | 1357 | |
1358 | /* Check if the use is still present in the insn! */ | |
1359 | use_insn = DF_REF_INSN (use); | |
1360 | if (DF_REF_FLAGS (use) & DF_REF_IN_NOTE) | |
1361 | parent = find_reg_note (use_insn, REG_EQUAL, NULL_RTX); | |
1362 | else | |
1363 | parent = PATTERN (use_insn); | |
1364 | ||
f533acbe | 1365 | if (!reg_mentioned_p (DF_REF_REG (use), parent)) |
f9460785 | 1366 | return false; |
42a3a38b | 1367 | |
1368 | def_insn = DF_REF_INSN (def); | |
3072d30e | 1369 | if (multiple_sets (def_insn)) |
f9460785 | 1370 | return false; |
42a3a38b | 1371 | def_set = single_set (def_insn); |
1372 | if (!def_set) | |
f9460785 | 1373 | return false; |
42a3a38b | 1374 | |
1375 | /* Only try one kind of propagation. If two are possible, we'll | |
1376 | do it on the following iterations. */ | |
f9460785 | 1377 | if (forward_propagate_and_simplify (use, def_insn, def_set) |
1378 | || forward_propagate_subreg (use, def_insn, def_set)) | |
1379 | { | |
1380 | if (cfun->can_throw_non_call_exceptions | |
1381 | && find_reg_note (use_insn, REG_EH_REGION, NULL_RTX) | |
1382 | && purge_dead_edges (DF_REF_BB (use))) | |
1383 | return true; | |
1384 | } | |
1385 | return false; | |
42a3a38b | 1386 | } |
1387 | ||
1388 | \f | |
1389 | static void | |
1390 | fwprop_init (void) | |
1391 | { | |
1392 | num_changes = 0; | |
a39fe687 | 1393 | calculate_dominance_info (CDI_DOMINATORS); |
42a3a38b | 1394 | |
1395 | /* We do not always want to propagate into loops, so we have to find | |
9add6570 | 1396 | loops and be careful about them. Avoid CFG modifications so that |
1397 | we don't have to update dominance information afterwards for | |
1398 | build_single_def_use_links. */ | |
1399 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
42a3a38b | 1400 | |
e0bd4156 | 1401 | build_single_def_use_links (); |
3072d30e | 1402 | df_set_flags (DF_DEFER_INSN_RESCAN); |
4ffe0526 | 1403 | |
1404 | active_defs = XNEWVEC (df_ref, max_reg_num ()); | |
382ecba7 | 1405 | if (flag_checking) |
1406 | active_defs_check = sparseset_alloc (max_reg_num ()); | |
42a3a38b | 1407 | } |
1408 | ||
1409 | static void | |
1410 | fwprop_done (void) | |
1411 | { | |
243f24c5 | 1412 | loop_optimizer_finalize (); |
3072d30e | 1413 | |
f1f41a6c | 1414 | use_def_ref.release (); |
4ffe0526 | 1415 | free (active_defs); |
382ecba7 | 1416 | if (flag_checking) |
1417 | sparseset_free (active_defs_check); | |
4ffe0526 | 1418 | |
a39fe687 | 1419 | free_dominance_info (CDI_DOMINATORS); |
42a3a38b | 1420 | cleanup_cfg (0); |
1421 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); | |
1422 | ||
1423 | if (dump_file) | |
1424 | fprintf (dump_file, | |
1425 | "\nNumber of successful forward propagations: %d\n\n", | |
1426 | num_changes); | |
1427 | } | |
1428 | ||
1429 | ||
42a3a38b | 1430 | /* Main entry point. */ |
1431 | ||
1432 | static bool | |
1433 | gate_fwprop (void) | |
1434 | { | |
1435 | return optimize > 0 && flag_forward_propagate; | |
1436 | } | |
1437 | ||
1438 | static unsigned int | |
1439 | fwprop (void) | |
1440 | { | |
1441 | unsigned i; | |
f9460785 | 1442 | bool need_cleanup = false; |
42a3a38b | 1443 | |
1444 | fwprop_init (); | |
1445 | ||
4ffe0526 | 1446 | /* Go through all the uses. df_uses_create will create new ones at the |
42a3a38b | 1447 | end, and we'll go through them as well. |
1448 | ||
1449 | Do not forward propagate addresses into loops until after unrolling. | |
1450 | CSE did so because it was able to fix its own mess, but we are not. */ | |
1451 | ||
3072d30e | 1452 | for (i = 0; i < DF_USES_TABLE_SIZE (); i++) |
42a3a38b | 1453 | { |
ed6e85ae | 1454 | df_ref use = DF_USES_GET (i); |
42a3a38b | 1455 | if (use) |
243f24c5 | 1456 | if (DF_REF_TYPE (use) == DF_REF_REG_USE |
526548ea | 1457 | || DF_REF_BB (use)->loop_father == NULL |
1458 | /* The outer most loop is not really a loop. */ | |
1459 | || loop_outer (DF_REF_BB (use)->loop_father) == NULL) | |
f9460785 | 1460 | need_cleanup |= forward_propagate_into (use); |
42a3a38b | 1461 | } |
1462 | ||
1463 | fwprop_done (); | |
f9460785 | 1464 | if (need_cleanup) |
1465 | cleanup_cfg (0); | |
42a3a38b | 1466 | return 0; |
1467 | } | |
1468 | ||
cbe8bda8 | 1469 | namespace { |
1470 | ||
1471 | const pass_data pass_data_rtl_fwprop = | |
42a3a38b | 1472 | { |
cbe8bda8 | 1473 | RTL_PASS, /* type */ |
1474 | "fwprop1", /* name */ | |
1475 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 1476 | TV_FWPROP, /* tv_id */ |
1477 | 0, /* properties_required */ | |
1478 | 0, /* properties_provided */ | |
1479 | 0, /* properties_destroyed */ | |
1480 | 0, /* todo_flags_start */ | |
8b88439e | 1481 | TODO_df_finish, /* todo_flags_finish */ |
42a3a38b | 1482 | }; |
1483 | ||
cbe8bda8 | 1484 | class pass_rtl_fwprop : public rtl_opt_pass |
1485 | { | |
1486 | public: | |
9af5ce0c | 1487 | pass_rtl_fwprop (gcc::context *ctxt) |
1488 | : rtl_opt_pass (pass_data_rtl_fwprop, ctxt) | |
cbe8bda8 | 1489 | {} |
1490 | ||
1491 | /* opt_pass methods: */ | |
31315c24 | 1492 | virtual bool gate (function *) { return gate_fwprop (); } |
65b0537f | 1493 | virtual unsigned int execute (function *) { return fwprop (); } |
cbe8bda8 | 1494 | |
1495 | }; // class pass_rtl_fwprop | |
1496 | ||
1497 | } // anon namespace | |
1498 | ||
1499 | rtl_opt_pass * | |
1500 | make_pass_rtl_fwprop (gcc::context *ctxt) | |
1501 | { | |
1502 | return new pass_rtl_fwprop (ctxt); | |
1503 | } | |
1504 | ||
42a3a38b | 1505 | static unsigned int |
1506 | fwprop_addr (void) | |
1507 | { | |
1508 | unsigned i; | |
f9460785 | 1509 | bool need_cleanup = false; |
1510 | ||
42a3a38b | 1511 | fwprop_init (); |
1512 | ||
4ffe0526 | 1513 | /* Go through all the uses. df_uses_create will create new ones at the |
42a3a38b | 1514 | end, and we'll go through them as well. */ |
3072d30e | 1515 | for (i = 0; i < DF_USES_TABLE_SIZE (); i++) |
42a3a38b | 1516 | { |
ed6e85ae | 1517 | df_ref use = DF_USES_GET (i); |
42a3a38b | 1518 | if (use) |
1519 | if (DF_REF_TYPE (use) != DF_REF_REG_USE | |
526548ea | 1520 | && DF_REF_BB (use)->loop_father != NULL |
1521 | /* The outer most loop is not really a loop. */ | |
1522 | && loop_outer (DF_REF_BB (use)->loop_father) != NULL) | |
f9460785 | 1523 | need_cleanup |= forward_propagate_into (use); |
42a3a38b | 1524 | } |
1525 | ||
1526 | fwprop_done (); | |
1527 | ||
f9460785 | 1528 | if (need_cleanup) |
1529 | cleanup_cfg (0); | |
42a3a38b | 1530 | return 0; |
1531 | } | |
1532 | ||
cbe8bda8 | 1533 | namespace { |
1534 | ||
1535 | const pass_data pass_data_rtl_fwprop_addr = | |
42a3a38b | 1536 | { |
cbe8bda8 | 1537 | RTL_PASS, /* type */ |
1538 | "fwprop2", /* name */ | |
1539 | OPTGROUP_NONE, /* optinfo_flags */ | |
cbe8bda8 | 1540 | TV_FWPROP, /* tv_id */ |
1541 | 0, /* properties_required */ | |
1542 | 0, /* properties_provided */ | |
1543 | 0, /* properties_destroyed */ | |
1544 | 0, /* todo_flags_start */ | |
8b88439e | 1545 | TODO_df_finish, /* todo_flags_finish */ |
42a3a38b | 1546 | }; |
cbe8bda8 | 1547 | |
1548 | class pass_rtl_fwprop_addr : public rtl_opt_pass | |
1549 | { | |
1550 | public: | |
9af5ce0c | 1551 | pass_rtl_fwprop_addr (gcc::context *ctxt) |
1552 | : rtl_opt_pass (pass_data_rtl_fwprop_addr, ctxt) | |
cbe8bda8 | 1553 | {} |
1554 | ||
1555 | /* opt_pass methods: */ | |
31315c24 | 1556 | virtual bool gate (function *) { return gate_fwprop (); } |
65b0537f | 1557 | virtual unsigned int execute (function *) { return fwprop_addr (); } |
cbe8bda8 | 1558 | |
1559 | }; // class pass_rtl_fwprop_addr | |
1560 | ||
1561 | } // anon namespace | |
1562 | ||
1563 | rtl_opt_pass * | |
1564 | make_pass_rtl_fwprop_addr (gcc::context *ctxt) | |
1565 | { | |
1566 | return new pass_rtl_fwprop_addr (ctxt); | |
1567 | } |