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f4e584dc 1/* Global common subexpression elimination/Partial redundancy elimination
7506f491 2 and global constant/copy propagation for GNU compiler.
ad616de1 3 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
8e42ace1 4 Free Software Foundation, Inc.
7506f491 5
1322177d 6This file is part of GCC.
7506f491 7
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8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2, or (at your option) any later
11version.
7506f491 12
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13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
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17
18You should have received a copy of the GNU General Public License
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19along with GCC; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
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22
23/* TODO
24 - reordering of memory allocation and freeing to be more space efficient
25 - do rough calc of how many regs are needed in each block, and a rough
26 calc of how many regs are available in each class and use that to
27 throttle back the code in cases where RTX_COST is minimal.
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28 - a store to the same address as a load does not kill the load if the
29 source of the store is also the destination of the load. Handling this
30 allows more load motion, particularly out of loops.
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31 - ability to realloc sbitmap vectors would allow one initial computation
32 of reg_set_in_block with only subsequent additions, rather than
33 recomputing it for each pass
34
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35*/
36
37/* References searched while implementing this.
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38
39 Compilers Principles, Techniques and Tools
40 Aho, Sethi, Ullman
41 Addison-Wesley, 1988
42
43 Global Optimization by Suppression of Partial Redundancies
44 E. Morel, C. Renvoise
45 communications of the acm, Vol. 22, Num. 2, Feb. 1979
46
47 A Portable Machine-Independent Global Optimizer - Design and Measurements
48 Frederick Chow
49 Stanford Ph.D. thesis, Dec. 1983
50
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51 A Fast Algorithm for Code Movement Optimization
52 D.M. Dhamdhere
53 SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988
54
55 A Solution to a Problem with Morel and Renvoise's
56 Global Optimization by Suppression of Partial Redundancies
57 K-H Drechsler, M.P. Stadel
58 ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988
59
60 Practical Adaptation of the Global Optimization
61 Algorithm of Morel and Renvoise
62 D.M. Dhamdhere
63 ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991
64
65 Efficiently Computing Static Single Assignment Form and the Control
66 Dependence Graph
67 R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck
68 ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991
69
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70 Lazy Code Motion
71 J. Knoop, O. Ruthing, B. Steffen
72 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
73
74 What's In a Region? Or Computing Control Dependence Regions in Near-Linear
75 Time for Reducible Flow Control
76 Thomas Ball
77 ACM Letters on Programming Languages and Systems,
78 Vol. 2, Num. 1-4, Mar-Dec 1993
79
80 An Efficient Representation for Sparse Sets
81 Preston Briggs, Linda Torczon
82 ACM Letters on Programming Languages and Systems,
83 Vol. 2, Num. 1-4, Mar-Dec 1993
84
85 A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion
86 K-H Drechsler, M.P. Stadel
87 ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993
88
89 Partial Dead Code Elimination
90 J. Knoop, O. Ruthing, B. Steffen
91 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
92
93 Effective Partial Redundancy Elimination
94 P. Briggs, K.D. Cooper
95 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
96
97 The Program Structure Tree: Computing Control Regions in Linear Time
98 R. Johnson, D. Pearson, K. Pingali
99 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
100
101 Optimal Code Motion: Theory and Practice
102 J. Knoop, O. Ruthing, B. Steffen
103 ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994
104
105 The power of assignment motion
106 J. Knoop, O. Ruthing, B. Steffen
107 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
108
109 Global code motion / global value numbering
110 C. Click
111 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
112
113 Value Driven Redundancy Elimination
114 L.T. Simpson
115 Rice University Ph.D. thesis, Apr. 1996
116
117 Value Numbering
118 L.T. Simpson
119 Massively Scalar Compiler Project, Rice University, Sep. 1996
120
121 High Performance Compilers for Parallel Computing
122 Michael Wolfe
123 Addison-Wesley, 1996
124
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125 Advanced Compiler Design and Implementation
126 Steven Muchnick
127 Morgan Kaufmann, 1997
128
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129 Building an Optimizing Compiler
130 Robert Morgan
131 Digital Press, 1998
132
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133 People wishing to speed up the code here should read:
134 Elimination Algorithms for Data Flow Analysis
135 B.G. Ryder, M.C. Paull
136 ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986
137
138 How to Analyze Large Programs Efficiently and Informatively
139 D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck
140 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
141
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142 People wishing to do something different can find various possibilities
143 in the above papers and elsewhere.
144*/
145
146#include "config.h"
50b2596f 147#include "system.h"
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148#include "coretypes.h"
149#include "tm.h"
01198c2f 150#include "toplev.h"
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151
152#include "rtl.h"
b0656d8b 153#include "tree.h"
6baf1cc8 154#include "tm_p.h"
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155#include "regs.h"
156#include "hard-reg-set.h"
157#include "flags.h"
158#include "real.h"
159#include "insn-config.h"
160#include "recog.h"
161#include "basic-block.h"
50b2596f 162#include "output.h"
49ad7cfa 163#include "function.h"
589005ff 164#include "expr.h"
e7d482b9 165#include "except.h"
fb0c0a12 166#include "ggc.h"
f1fa37ff 167#include "params.h"
ae860ff7 168#include "cselib.h"
d128effb 169#include "intl.h"
7506f491 170#include "obstack.h"
27fb79ad 171#include "timevar.h"
4fa31c2a 172
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173/* Propagate flow information through back edges and thus enable PRE's
174 moving loop invariant calculations out of loops.
175
176 Originally this tended to create worse overall code, but several
177 improvements during the development of PRE seem to have made following
178 back edges generally a win.
179
180 Note much of the loop invariant code motion done here would normally
181 be done by loop.c, which has more heuristics for when to move invariants
182 out of loops. At some point we might need to move some of those
183 heuristics into gcse.c. */
7506f491 184
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185/* We support GCSE via Partial Redundancy Elimination. PRE optimizations
186 are a superset of those done by GCSE.
7506f491 187
f4e584dc 188 We perform the following steps:
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189
190 1) Compute basic block information.
191
192 2) Compute table of places where registers are set.
193
194 3) Perform copy/constant propagation.
195
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196 4) Perform global cse using lazy code motion if not optimizing
197 for size, or code hoisting if we are.
7506f491 198
e78d9500 199 5) Perform another pass of copy/constant propagation.
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200
201 Two passes of copy/constant propagation are done because the first one
202 enables more GCSE and the second one helps to clean up the copies that
203 GCSE creates. This is needed more for PRE than for Classic because Classic
204 GCSE will try to use an existing register containing the common
205 subexpression rather than create a new one. This is harder to do for PRE
206 because of the code motion (which Classic GCSE doesn't do).
207
208 Expressions we are interested in GCSE-ing are of the form
209 (set (pseudo-reg) (expression)).
210 Function want_to_gcse_p says what these are.
211
212 PRE handles moving invariant expressions out of loops (by treating them as
f4e584dc 213 partially redundant).
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214
215 Eventually it would be nice to replace cse.c/gcse.c with SSA (static single
216 assignment) based GVN (global value numbering). L. T. Simpson's paper
217 (Rice University) on value numbering is a useful reference for this.
218
219 **********************
220
221 We used to support multiple passes but there are diminishing returns in
222 doing so. The first pass usually makes 90% of the changes that are doable.
223 A second pass can make a few more changes made possible by the first pass.
224 Experiments show any further passes don't make enough changes to justify
225 the expense.
226
227 A study of spec92 using an unlimited number of passes:
228 [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83,
229 [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2,
230 [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1
231
232 It was found doing copy propagation between each pass enables further
233 substitutions.
234
235 PRE is quite expensive in complicated functions because the DFA can take
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236 a while to converge. Hence we only perform one pass. The parameter
237 max-gcse-passes can be modified if one wants to experiment.
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238
239 **********************
240
241 The steps for PRE are:
242
243 1) Build the hash table of expressions we wish to GCSE (expr_hash_table).
244
245 2) Perform the data flow analysis for PRE.
246
247 3) Delete the redundant instructions
248
249 4) Insert the required copies [if any] that make the partially
250 redundant instructions fully redundant.
251
252 5) For other reaching expressions, insert an instruction to copy the value
253 to a newly created pseudo that will reach the redundant instruction.
254
255 The deletion is done first so that when we do insertions we
256 know which pseudo reg to use.
257
258 Various papers have argued that PRE DFA is expensive (O(n^2)) and others
259 argue it is not. The number of iterations for the algorithm to converge
260 is typically 2-4 so I don't view it as that expensive (relatively speaking).
261
f4e584dc 262 PRE GCSE depends heavily on the second CSE pass to clean up the copies
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263 we create. To make an expression reach the place where it's redundant,
264 the result of the expression is copied to a new register, and the redundant
265 expression is deleted by replacing it with this new register. Classic GCSE
266 doesn't have this problem as much as it computes the reaching defs of
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267 each register in each block and thus can try to use an existing
268 register. */
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269\f
270/* GCSE global vars. */
271
272/* -dG dump file. */
273static FILE *gcse_file;
274
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275/* Note whether or not we should run jump optimization after gcse. We
276 want to do this for two cases.
277
278 * If we changed any jumps via cprop.
279
280 * If we added any labels via edge splitting. */
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281static int run_jump_opt_after_gcse;
282
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283/* Bitmaps are normally not included in debugging dumps.
284 However it's useful to be able to print them from GDB.
285 We could create special functions for this, but it's simpler to
286 just allow passing stderr to the dump_foo fns. Since stderr can
287 be a macro, we store a copy here. */
288static FILE *debug_stderr;
289
290/* An obstack for our working variables. */
291static struct obstack gcse_obstack;
292
c4c81601 293struct reg_use {rtx reg_rtx; };
abd535b6 294
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295/* Hash table of expressions. */
296
297struct expr
298{
299 /* The expression (SET_SRC for expressions, PATTERN for assignments). */
300 rtx expr;
301 /* Index in the available expression bitmaps. */
302 int bitmap_index;
303 /* Next entry with the same hash. */
304 struct expr *next_same_hash;
305 /* List of anticipatable occurrences in basic blocks in the function.
306 An "anticipatable occurrence" is one that is the first occurrence in the
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307 basic block, the operands are not modified in the basic block prior
308 to the occurrence and the output is not used between the start of
309 the block and the occurrence. */
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310 struct occr *antic_occr;
311 /* List of available occurrence in basic blocks in the function.
312 An "available occurrence" is one that is the last occurrence in the
313 basic block and the operands are not modified by following statements in
314 the basic block [including this insn]. */
315 struct occr *avail_occr;
316 /* Non-null if the computation is PRE redundant.
317 The value is the newly created pseudo-reg to record a copy of the
318 expression in all the places that reach the redundant copy. */
319 rtx reaching_reg;
320};
321
322/* Occurrence of an expression.
323 There is one per basic block. If a pattern appears more than once the
324 last appearance is used [or first for anticipatable expressions]. */
325
326struct occr
327{
328 /* Next occurrence of this expression. */
329 struct occr *next;
330 /* The insn that computes the expression. */
331 rtx insn;
cc2902df 332 /* Nonzero if this [anticipatable] occurrence has been deleted. */
7506f491 333 char deleted_p;
cc2902df 334 /* Nonzero if this [available] occurrence has been copied to
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335 reaching_reg. */
336 /* ??? This is mutually exclusive with deleted_p, so they could share
337 the same byte. */
338 char copied_p;
339};
340
341/* Expression and copy propagation hash tables.
342 Each hash table is an array of buckets.
343 ??? It is known that if it were an array of entries, structure elements
344 `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is
345 not clear whether in the final analysis a sufficient amount of memory would
346 be saved as the size of the available expression bitmaps would be larger
347 [one could build a mapping table without holes afterwards though].
c4c81601 348 Someday I'll perform the computation and figure it out. */
7506f491 349
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350struct hash_table
351{
352 /* The table itself.
353 This is an array of `expr_hash_table_size' elements. */
354 struct expr **table;
355
356 /* Size of the hash table, in elements. */
357 unsigned int size;
2e653e39 358
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359 /* Number of hash table elements. */
360 unsigned int n_elems;
7506f491 361
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362 /* Whether the table is expression of copy propagation one. */
363 int set_p;
364};
c4c81601 365
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366/* Expression hash table. */
367static struct hash_table expr_hash_table;
368
369/* Copy propagation hash table. */
370static struct hash_table set_hash_table;
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371
372/* Mapping of uids to cuids.
373 Only real insns get cuids. */
374static int *uid_cuid;
375
376/* Highest UID in UID_CUID. */
377static int max_uid;
378
379/* Get the cuid of an insn. */
b86db3eb 380#ifdef ENABLE_CHECKING
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381#define INSN_CUID(INSN) \
382 (gcc_assert (INSN_UID (INSN) <= max_uid), uid_cuid[INSN_UID (INSN)])
b86db3eb 383#else
7506f491 384#define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
b86db3eb 385#endif
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386
387/* Number of cuids. */
388static int max_cuid;
389
390/* Mapping of cuids to insns. */
391static rtx *cuid_insn;
392
393/* Get insn from cuid. */
394#define CUID_INSN(CUID) (cuid_insn[CUID])
395
396/* Maximum register number in function prior to doing gcse + 1.
397 Registers created during this pass have regno >= max_gcse_regno.
398 This is named with "gcse" to not collide with global of same name. */
770ae6cc 399static unsigned int max_gcse_regno;
7506f491 400
7506f491 401/* Table of registers that are modified.
c4c81601 402
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403 For each register, each element is a list of places where the pseudo-reg
404 is set.
405
406 For simplicity, GCSE is done on sets of pseudo-regs only. PRE GCSE only
407 requires knowledge of which blocks kill which regs [and thus could use
f4e584dc 408 a bitmap instead of the lists `reg_set_table' uses].
7506f491 409
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410 `reg_set_table' and could be turned into an array of bitmaps (num-bbs x
411 num-regs) [however perhaps it may be useful to keep the data as is]. One
412 advantage of recording things this way is that `reg_set_table' is fairly
413 sparse with respect to pseudo regs but for hard regs could be fairly dense
414 [relatively speaking]. And recording sets of pseudo-regs in lists speeds
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415 up functions like compute_transp since in the case of pseudo-regs we only
416 need to iterate over the number of times a pseudo-reg is set, not over the
417 number of basic blocks [clearly there is a bit of a slow down in the cases
418 where a pseudo is set more than once in a block, however it is believed
419 that the net effect is to speed things up]. This isn't done for hard-regs
420 because recording call-clobbered hard-regs in `reg_set_table' at each
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421 function call can consume a fair bit of memory, and iterating over
422 hard-regs stored this way in compute_transp will be more expensive. */
7506f491 423
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424typedef struct reg_set
425{
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426 /* The next setting of this register. */
427 struct reg_set *next;
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428 /* The index of the block where it was set. */
429 int bb_index;
7506f491 430} reg_set;
c4c81601 431
7506f491 432static reg_set **reg_set_table;
c4c81601 433
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434/* Size of `reg_set_table'.
435 The table starts out at max_gcse_regno + slop, and is enlarged as
436 necessary. */
437static int reg_set_table_size;
c4c81601 438
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439/* Amount to grow `reg_set_table' by when it's full. */
440#define REG_SET_TABLE_SLOP 100
441
a13d4ebf 442/* This is a list of expressions which are MEMs and will be used by load
589005ff 443 or store motion.
a13d4ebf 444 Load motion tracks MEMs which aren't killed by
454ff5cb 445 anything except itself. (i.e., loads and stores to a single location).
589005ff 446 We can then allow movement of these MEM refs with a little special
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447 allowance. (all stores copy the same value to the reaching reg used
448 for the loads). This means all values used to store into memory must have
589005ff 449 no side effects so we can re-issue the setter value.
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450 Store Motion uses this structure as an expression table to track stores
451 which look interesting, and might be moveable towards the exit block. */
452
453struct ls_expr
454{
455 struct expr * expr; /* Gcse expression reference for LM. */
456 rtx pattern; /* Pattern of this mem. */
47a3dae1 457 rtx pattern_regs; /* List of registers mentioned by the mem. */
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458 rtx loads; /* INSN list of loads seen. */
459 rtx stores; /* INSN list of stores seen. */
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460 struct ls_expr * next; /* Next in the list. */
461 int invalid; /* Invalid for some reason. */
462 int index; /* If it maps to a bitmap index. */
b58b21d5 463 unsigned int hash_index; /* Index when in a hash table. */
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464 rtx reaching_reg; /* Register to use when re-writing. */
465};
466
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467/* Array of implicit set patterns indexed by basic block index. */
468static rtx *implicit_sets;
469
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470/* Head of the list of load/store memory refs. */
471static struct ls_expr * pre_ldst_mems = NULL;
472
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473/* Bitmap containing one bit for each register in the program.
474 Used when performing GCSE to track which registers have been set since
475 the start of the basic block. */
73991d6a 476static regset reg_set_bitmap;
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477
478/* For each block, a bitmap of registers set in the block.
e83f4801 479 This is used by compute_transp.
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480 It is computed during hash table computation and not by compute_sets
481 as it includes registers added since the last pass (or between cprop and
482 gcse) and it's currently not easy to realloc sbitmap vectors. */
483static sbitmap *reg_set_in_block;
484
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485/* Array, indexed by basic block number for a list of insns which modify
486 memory within that block. */
487static rtx * modify_mem_list;
0516f6fe 488static bitmap modify_mem_list_set;
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489
490/* This array parallels modify_mem_list, but is kept canonicalized. */
491static rtx * canon_modify_mem_list;
0516f6fe 492
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493/* Bitmap indexed by block numbers to record which blocks contain
494 function calls. */
495static bitmap blocks_with_calls;
496
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497/* Various variables for statistics gathering. */
498
499/* Memory used in a pass.
500 This isn't intended to be absolutely precise. Its intent is only
501 to keep an eye on memory usage. */
502static int bytes_used;
c4c81601 503
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504/* GCSE substitutions made. */
505static int gcse_subst_count;
506/* Number of copy instructions created. */
507static int gcse_create_count;
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508/* Number of local constants propagated. */
509static int local_const_prop_count;
510/* Number of local copys propagated. */
511static int local_copy_prop_count;
512/* Number of global constants propagated. */
513static int global_const_prop_count;
514/* Number of global copys propagated. */
515static int global_copy_prop_count;
7506f491 516\f
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517/* For available exprs */
518static sbitmap *ae_kill, *ae_gen;
7506f491 519\f
1d088dee 520static void compute_can_copy (void);
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521static void *gmalloc (size_t) ATTRIBUTE_MALLOC;
522static void *gcalloc (size_t, size_t) ATTRIBUTE_MALLOC;
523static void *grealloc (void *, size_t);
703ad42b 524static void *gcse_alloc (unsigned long);
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525static void alloc_gcse_mem (rtx);
526static void free_gcse_mem (void);
527static void alloc_reg_set_mem (int);
528static void free_reg_set_mem (void);
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529static void record_one_set (int, rtx);
530static void record_set_info (rtx, rtx, void *);
531static void compute_sets (rtx);
532static void hash_scan_insn (rtx, struct hash_table *, int);
533static void hash_scan_set (rtx, rtx, struct hash_table *);
534static void hash_scan_clobber (rtx, rtx, struct hash_table *);
535static void hash_scan_call (rtx, rtx, struct hash_table *);
536static int want_to_gcse_p (rtx);
1707bafa 537static bool can_assign_to_reg_p (rtx);
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538static bool gcse_constant_p (rtx);
539static int oprs_unchanged_p (rtx, rtx, int);
540static int oprs_anticipatable_p (rtx, rtx);
541static int oprs_available_p (rtx, rtx);
542static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int,
543 struct hash_table *);
544static void insert_set_in_table (rtx, rtx, struct hash_table *);
545static unsigned int hash_expr (rtx, enum machine_mode, int *, int);
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546static unsigned int hash_set (int, int);
547static int expr_equiv_p (rtx, rtx);
548static void record_last_reg_set_info (rtx, int);
549static void record_last_mem_set_info (rtx);
550static void record_last_set_info (rtx, rtx, void *);
551static void compute_hash_table (struct hash_table *);
552static void alloc_hash_table (int, struct hash_table *, int);
553static void free_hash_table (struct hash_table *);
554static void compute_hash_table_work (struct hash_table *);
555static void dump_hash_table (FILE *, const char *, struct hash_table *);
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556static struct expr *lookup_set (unsigned int, struct hash_table *);
557static struct expr *next_set (unsigned int, struct expr *);
558static void reset_opr_set_tables (void);
559static int oprs_not_set_p (rtx, rtx);
560static void mark_call (rtx);
561static void mark_set (rtx, rtx);
562static void mark_clobber (rtx, rtx);
563static void mark_oprs_set (rtx);
564static void alloc_cprop_mem (int, int);
565static void free_cprop_mem (void);
566static void compute_transp (rtx, int, sbitmap *, int);
567static void compute_transpout (void);
568static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *,
569 struct hash_table *);
570static void compute_cprop_data (void);
571static void find_used_regs (rtx *, void *);
572static int try_replace_reg (rtx, rtx, rtx);
573static struct expr *find_avail_set (int, rtx);
574static int cprop_jump (basic_block, rtx, rtx, rtx, rtx);
575static void mems_conflict_for_gcse_p (rtx, rtx, void *);
576static int load_killed_in_block_p (basic_block, int, rtx, int);
577static void canon_list_insert (rtx, rtx, void *);
578static int cprop_insn (rtx, int);
579static int cprop (int);
580static void find_implicit_sets (void);
581static int one_cprop_pass (int, int, int);
582static bool constprop_register (rtx, rtx, rtx, int);
583static struct expr *find_bypass_set (int, int);
584static bool reg_killed_on_edge (rtx, edge);
585static int bypass_block (basic_block, rtx, rtx);
586static int bypass_conditional_jumps (void);
587static void alloc_pre_mem (int, int);
588static void free_pre_mem (void);
589static void compute_pre_data (void);
590static int pre_expr_reaches_here_p (basic_block, struct expr *,
591 basic_block);
592static void insert_insn_end_bb (struct expr *, basic_block, int);
593static void pre_insert_copy_insn (struct expr *, rtx);
594static void pre_insert_copies (void);
595static int pre_delete (void);
596static int pre_gcse (void);
597static int one_pre_gcse_pass (int);
598static void add_label_notes (rtx, rtx);
599static void alloc_code_hoist_mem (int, int);
600static void free_code_hoist_mem (void);
601static void compute_code_hoist_vbeinout (void);
602static void compute_code_hoist_data (void);
603static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *);
604static void hoist_code (void);
605static int one_code_hoisting_pass (void);
1d088dee
AJ
606static rtx process_insert_insn (struct expr *);
607static int pre_edge_insert (struct edge_list *, struct expr **);
1d088dee
AJ
608static int pre_expr_reaches_here_p_work (basic_block, struct expr *,
609 basic_block, char *);
610static struct ls_expr * ldst_entry (rtx);
611static void free_ldst_entry (struct ls_expr *);
612static void free_ldst_mems (void);
613static void print_ldst_list (FILE *);
614static struct ls_expr * find_rtx_in_ldst (rtx);
615static int enumerate_ldsts (void);
616static inline struct ls_expr * first_ls_expr (void);
617static inline struct ls_expr * next_ls_expr (struct ls_expr *);
618static int simple_mem (rtx);
619static void invalidate_any_buried_refs (rtx);
620static void compute_ld_motion_mems (void);
621static void trim_ld_motion_mems (void);
622static void update_ld_motion_stores (struct expr *);
623static void reg_set_info (rtx, rtx, void *);
01c43039 624static void reg_clear_last_set (rtx, rtx, void *);
1d088dee
AJ
625static bool store_ops_ok (rtx, int *);
626static rtx extract_mentioned_regs (rtx);
627static rtx extract_mentioned_regs_helper (rtx, rtx);
628static void find_moveable_store (rtx, int *, int *);
629static int compute_store_table (void);
3b14e3af
ZD
630static bool load_kills_store (rtx, rtx, int);
631static bool find_loads (rtx, rtx, int);
632static bool store_killed_in_insn (rtx, rtx, rtx, int);
1d088dee
AJ
633static bool store_killed_after (rtx, rtx, rtx, basic_block, int *, rtx *);
634static bool store_killed_before (rtx, rtx, rtx, basic_block, int *);
635static void build_store_vectors (void);
636static void insert_insn_start_bb (rtx, basic_block);
637static int insert_store (struct ls_expr *, edge);
d088acea
ZD
638static void remove_reachable_equiv_notes (basic_block, struct ls_expr *);
639static void replace_store_insn (rtx, rtx, basic_block, struct ls_expr *);
1d088dee
AJ
640static void delete_store (struct ls_expr *, basic_block);
641static void free_store_memory (void);
642static void store_motion (void);
643static void free_insn_expr_list_list (rtx *);
644static void clear_modify_mem_tables (void);
645static void free_modify_mem_tables (void);
646static rtx gcse_emit_move_after (rtx, rtx, rtx);
647static void local_cprop_find_used_regs (rtx *, void *);
648static bool do_local_cprop (rtx, rtx, int, rtx*);
649static bool adjust_libcall_notes (rtx, rtx, rtx, rtx*);
650static void local_cprop_pass (int);
d128effb 651static bool is_too_expensive (const char *);
7506f491 652\f
d128effb 653
7506f491 654/* Entry point for global common subexpression elimination.
b732f36f
KH
655 F is the first instruction in the function. Return nonzero if a
656 change is mode. */
7506f491 657
e78d9500 658int
1d088dee 659gcse_main (rtx f, FILE *file)
7506f491
DE
660{
661 int changed, pass;
662 /* Bytes used at start of pass. */
663 int initial_bytes_used;
664 /* Maximum number of bytes used by a pass. */
665 int max_pass_bytes;
666 /* Point to release obstack data from for each pass. */
667 char *gcse_obstack_bottom;
668
b5ce41ff
JL
669 /* We do not construct an accurate cfg in functions which call
670 setjmp, so just punt to be safe. */
7506f491 671 if (current_function_calls_setjmp)
e78d9500 672 return 0;
589005ff 673
b5ce41ff
JL
674 /* Assume that we do not need to run jump optimizations after gcse. */
675 run_jump_opt_after_gcse = 0;
676
7506f491
DE
677 /* For calling dump_foo fns from gdb. */
678 debug_stderr = stderr;
b5ce41ff 679 gcse_file = file;
7506f491 680
b5ce41ff
JL
681 /* Identify the basic block information for this function, including
682 successors and predecessors. */
7506f491 683 max_gcse_regno = max_reg_num ();
7506f491 684
a42cd965
AM
685 if (file)
686 dump_flow_info (file);
687
d128effb
NS
688 /* Return if there's nothing to do, or it is too expensive. */
689 if (n_basic_blocks <= 1 || is_too_expensive (_("GCSE disabled")))
a18820c6 690 return 0;
7b1b4aed 691
7506f491 692 gcc_obstack_init (&gcse_obstack);
a42cd965 693 bytes_used = 0;
7506f491 694
a13d4ebf
AM
695 /* We need alias. */
696 init_alias_analysis ();
c4c81601
RK
697 /* Record where pseudo-registers are set. This data is kept accurate
698 during each pass. ??? We could also record hard-reg information here
699 [since it's unchanging], however it is currently done during hash table
700 computation.
b5ce41ff 701
c4c81601
RK
702 It may be tempting to compute MEM set information here too, but MEM sets
703 will be subject to code motion one day and thus we need to compute
b5ce41ff 704 information about memory sets when we build the hash tables. */
7506f491
DE
705
706 alloc_reg_set_mem (max_gcse_regno);
707 compute_sets (f);
708
709 pass = 0;
710 initial_bytes_used = bytes_used;
711 max_pass_bytes = 0;
712 gcse_obstack_bottom = gcse_alloc (1);
713 changed = 1;
740f35a0 714 while (changed && pass < MAX_GCSE_PASSES)
7506f491
DE
715 {
716 changed = 0;
717 if (file)
718 fprintf (file, "GCSE pass %d\n\n", pass + 1);
719
720 /* Initialize bytes_used to the space for the pred/succ lists,
721 and the reg_set_table data. */
722 bytes_used = initial_bytes_used;
723
724 /* Each pass may create new registers, so recalculate each time. */
725 max_gcse_regno = max_reg_num ();
726
727 alloc_gcse_mem (f);
728
b5ce41ff
JL
729 /* Don't allow constant propagation to modify jumps
730 during this pass. */
27fb79ad 731 timevar_push (TV_CPROP1);
a0134312 732 changed = one_cprop_pass (pass + 1, 0, 0);
27fb79ad 733 timevar_pop (TV_CPROP1);
7506f491
DE
734
735 if (optimize_size)
e83f4801 736 /* Do nothing. */ ;
7506f491 737 else
589005ff 738 {
27fb79ad 739 timevar_push (TV_PRE);
a42cd965 740 changed |= one_pre_gcse_pass (pass + 1);
a13d4ebf
AM
741 /* We may have just created new basic blocks. Release and
742 recompute various things which are sized on the number of
743 basic blocks. */
744 if (changed)
745 {
73991d6a 746 free_modify_mem_tables ();
9fe15a12
KG
747 modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
748 canon_modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
a13d4ebf 749 }
a42cd965
AM
750 free_reg_set_mem ();
751 alloc_reg_set_mem (max_reg_num ());
752 compute_sets (f);
753 run_jump_opt_after_gcse = 1;
27fb79ad 754 timevar_pop (TV_PRE);
a42cd965 755 }
7506f491
DE
756
757 if (max_pass_bytes < bytes_used)
758 max_pass_bytes = bytes_used;
759
bb457bd9
JL
760 /* Free up memory, then reallocate for code hoisting. We can
761 not re-use the existing allocated memory because the tables
762 will not have info for the insns or registers created by
763 partial redundancy elimination. */
7506f491
DE
764 free_gcse_mem ();
765
5d3cc252 766 /* It does not make sense to run code hoisting unless we are optimizing
bb457bd9
JL
767 for code size -- it rarely makes programs faster, and can make
768 them bigger if we did partial redundancy elimination (when optimizing
e83f4801 769 for space, we don't run the partial redundancy algorithms). */
bb457bd9 770 if (optimize_size)
589005ff 771 {
27fb79ad 772 timevar_push (TV_HOIST);
bb457bd9
JL
773 max_gcse_regno = max_reg_num ();
774 alloc_gcse_mem (f);
775 changed |= one_code_hoisting_pass ();
776 free_gcse_mem ();
777
778 if (max_pass_bytes < bytes_used)
779 max_pass_bytes = bytes_used;
27fb79ad 780 timevar_pop (TV_HOIST);
589005ff 781 }
bb457bd9 782
7506f491
DE
783 if (file)
784 {
785 fprintf (file, "\n");
786 fflush (file);
787 }
c4c81601 788
7506f491
DE
789 obstack_free (&gcse_obstack, gcse_obstack_bottom);
790 pass++;
791 }
792
b5ce41ff
JL
793 /* Do one last pass of copy propagation, including cprop into
794 conditional jumps. */
795
796 max_gcse_regno = max_reg_num ();
797 alloc_gcse_mem (f);
798 /* This time, go ahead and allow cprop to alter jumps. */
27fb79ad 799 timevar_push (TV_CPROP2);
a0134312 800 one_cprop_pass (pass + 1, 1, 0);
27fb79ad 801 timevar_pop (TV_CPROP2);
b5ce41ff 802 free_gcse_mem ();
7506f491
DE
803
804 if (file)
805 {
806 fprintf (file, "GCSE of %s: %d basic blocks, ",
faed5cc3 807 current_function_name (), n_basic_blocks);
7506f491
DE
808 fprintf (file, "%d pass%s, %d bytes\n\n",
809 pass, pass > 1 ? "es" : "", max_pass_bytes);
810 }
811
6496a589 812 obstack_free (&gcse_obstack, NULL);
7506f491 813 free_reg_set_mem ();
7b1b4aed 814
a13d4ebf
AM
815 /* We are finished with alias. */
816 end_alias_analysis ();
817 allocate_reg_info (max_reg_num (), FALSE, FALSE);
818
47a3dae1 819 if (!optimize_size && flag_gcse_sm)
27fb79ad
SB
820 {
821 timevar_push (TV_LSM);
822 store_motion ();
823 timevar_pop (TV_LSM);
824 }
47a3dae1 825
a13d4ebf 826 /* Record where pseudo-registers are set. */
e78d9500 827 return run_jump_opt_after_gcse;
7506f491
DE
828}
829\f
830/* Misc. utilities. */
831
773eae39
EB
832/* Nonzero for each mode that supports (set (reg) (reg)).
833 This is trivially true for integer and floating point values.
834 It may or may not be true for condition codes. */
835static char can_copy[(int) NUM_MACHINE_MODES];
836
7506f491
DE
837/* Compute which modes support reg/reg copy operations. */
838
839static void
1d088dee 840compute_can_copy (void)
7506f491
DE
841{
842 int i;
50b2596f 843#ifndef AVOID_CCMODE_COPIES
8e42ace1 844 rtx reg, insn;
50b2596f 845#endif
773eae39 846 memset (can_copy, 0, NUM_MACHINE_MODES);
7506f491
DE
847
848 start_sequence ();
849 for (i = 0; i < NUM_MACHINE_MODES; i++)
c4c81601
RK
850 if (GET_MODE_CLASS (i) == MODE_CC)
851 {
7506f491 852#ifdef AVOID_CCMODE_COPIES
773eae39 853 can_copy[i] = 0;
7506f491 854#else
c4c81601
RK
855 reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1);
856 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg));
9714cf43 857 if (recog (PATTERN (insn), insn, NULL) >= 0)
773eae39 858 can_copy[i] = 1;
7506f491 859#endif
c4c81601 860 }
141b5810 861 else
773eae39 862 can_copy[i] = 1;
c4c81601 863
7506f491 864 end_sequence ();
7506f491 865}
773eae39
EB
866
867/* Returns whether the mode supports reg/reg copy operations. */
868
869bool
1d088dee 870can_copy_p (enum machine_mode mode)
773eae39
EB
871{
872 static bool can_copy_init_p = false;
873
874 if (! can_copy_init_p)
875 {
876 compute_can_copy ();
877 can_copy_init_p = true;
878 }
879
880 return can_copy[mode] != 0;
881}
7506f491
DE
882\f
883/* Cover function to xmalloc to record bytes allocated. */
884
703ad42b 885static void *
4ac11022 886gmalloc (size_t size)
7506f491
DE
887{
888 bytes_used += size;
889 return xmalloc (size);
890}
891
9fe15a12
KG
892/* Cover function to xcalloc to record bytes allocated. */
893
894static void *
895gcalloc (size_t nelem, size_t elsize)
896{
897 bytes_used += nelem * elsize;
898 return xcalloc (nelem, elsize);
899}
900
7506f491
DE
901/* Cover function to xrealloc.
902 We don't record the additional size since we don't know it.
903 It won't affect memory usage stats much anyway. */
904
703ad42b 905static void *
9fe15a12 906grealloc (void *ptr, size_t size)
7506f491
DE
907{
908 return xrealloc (ptr, size);
909}
910
77bbd421 911/* Cover function to obstack_alloc. */
7506f491 912
703ad42b 913static void *
1d088dee 914gcse_alloc (unsigned long size)
7506f491 915{
77bbd421 916 bytes_used += size;
703ad42b 917 return obstack_alloc (&gcse_obstack, size);
7506f491
DE
918}
919
920/* Allocate memory for the cuid mapping array,
921 and reg/memory set tracking tables.
922
923 This is called at the start of each pass. */
924
925static void
1d088dee 926alloc_gcse_mem (rtx f)
7506f491 927{
9fe15a12 928 int i;
7506f491
DE
929 rtx insn;
930
931 /* Find the largest UID and create a mapping from UIDs to CUIDs.
932 CUIDs are like UIDs except they increase monotonically, have no gaps,
933 and only apply to real insns. */
934
935 max_uid = get_max_uid ();
9fe15a12 936 uid_cuid = gcalloc (max_uid + 1, sizeof (int));
7506f491
DE
937 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
938 {
2c3c49de 939 if (INSN_P (insn))
b86db3eb 940 uid_cuid[INSN_UID (insn)] = i++;
7506f491 941 else
b86db3eb 942 uid_cuid[INSN_UID (insn)] = i;
7506f491
DE
943 }
944
945 /* Create a table mapping cuids to insns. */
946
947 max_cuid = i;
9fe15a12 948 cuid_insn = gcalloc (max_cuid + 1, sizeof (rtx));
7506f491 949 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
2c3c49de 950 if (INSN_P (insn))
c4c81601 951 CUID_INSN (i++) = insn;
7506f491
DE
952
953 /* Allocate vars to track sets of regs. */
8bdbfff5 954 reg_set_bitmap = BITMAP_ALLOC (NULL);
7506f491
DE
955
956 /* Allocate vars to track sets of regs, memory per block. */
703ad42b 957 reg_set_in_block = sbitmap_vector_alloc (last_basic_block, max_gcse_regno);
a13d4ebf
AM
958 /* Allocate array to keep a list of insns which modify memory in each
959 basic block. */
9fe15a12
KG
960 modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
961 canon_modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
8bdbfff5
NS
962 modify_mem_list_set = BITMAP_ALLOC (NULL);
963 blocks_with_calls = BITMAP_ALLOC (NULL);
7506f491
DE
964}
965
966/* Free memory allocated by alloc_gcse_mem. */
967
968static void
1d088dee 969free_gcse_mem (void)
7506f491
DE
970{
971 free (uid_cuid);
972 free (cuid_insn);
973
8bdbfff5 974 BITMAP_FREE (reg_set_bitmap);
7506f491 975
5a660bff 976 sbitmap_vector_free (reg_set_in_block);
73991d6a 977 free_modify_mem_tables ();
8bdbfff5
NS
978 BITMAP_FREE (modify_mem_list_set);
979 BITMAP_FREE (blocks_with_calls);
7506f491 980}
b5ce41ff
JL
981\f
982/* Compute the local properties of each recorded expression.
c4c81601
RK
983
984 Local properties are those that are defined by the block, irrespective of
985 other blocks.
b5ce41ff
JL
986
987 An expression is transparent in a block if its operands are not modified
988 in the block.
989
990 An expression is computed (locally available) in a block if it is computed
991 at least once and expression would contain the same value if the
992 computation was moved to the end of the block.
993
994 An expression is locally anticipatable in a block if it is computed at
995 least once and expression would contain the same value if the computation
996 was moved to the beginning of the block.
997
c4c81601
RK
998 We call this routine for cprop, pre and code hoisting. They all compute
999 basically the same information and thus can easily share this code.
7506f491 1000
c4c81601
RK
1001 TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local
1002 properties. If NULL, then it is not necessary to compute or record that
1003 particular property.
b5ce41ff 1004
02280659
ZD
1005 TABLE controls which hash table to look at. If it is set hash table,
1006 additionally, TRANSP is computed as ~TRANSP, since this is really cprop's
c4c81601 1007 ABSALTERED. */
589005ff 1008
b5ce41ff 1009static void
7b1b4aed
SB
1010compute_local_properties (sbitmap *transp, sbitmap *comp, sbitmap *antloc,
1011 struct hash_table *table)
b5ce41ff 1012{
02280659 1013 unsigned int i;
589005ff 1014
b5ce41ff
JL
1015 /* Initialize any bitmaps that were passed in. */
1016 if (transp)
695ab36a 1017 {
02280659 1018 if (table->set_p)
d55bc081 1019 sbitmap_vector_zero (transp, last_basic_block);
695ab36a 1020 else
d55bc081 1021 sbitmap_vector_ones (transp, last_basic_block);
695ab36a 1022 }
c4c81601 1023
b5ce41ff 1024 if (comp)
d55bc081 1025 sbitmap_vector_zero (comp, last_basic_block);
b5ce41ff 1026 if (antloc)
d55bc081 1027 sbitmap_vector_zero (antloc, last_basic_block);
b5ce41ff 1028
02280659 1029 for (i = 0; i < table->size; i++)
7506f491 1030 {
b5ce41ff
JL
1031 struct expr *expr;
1032
02280659 1033 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
b5ce41ff 1034 {
b5ce41ff 1035 int indx = expr->bitmap_index;
c4c81601 1036 struct occr *occr;
b5ce41ff
JL
1037
1038 /* The expression is transparent in this block if it is not killed.
1039 We start by assuming all are transparent [none are killed], and
1040 then reset the bits for those that are. */
b5ce41ff 1041 if (transp)
02280659 1042 compute_transp (expr->expr, indx, transp, table->set_p);
b5ce41ff
JL
1043
1044 /* The occurrences recorded in antic_occr are exactly those that
cc2902df 1045 we want to set to nonzero in ANTLOC. */
b5ce41ff 1046 if (antloc)
c4c81601
RK
1047 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
1048 {
1049 SET_BIT (antloc[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1050
c4c81601
RK
1051 /* While we're scanning the table, this is a good place to
1052 initialize this. */
1053 occr->deleted_p = 0;
1054 }
b5ce41ff
JL
1055
1056 /* The occurrences recorded in avail_occr are exactly those that
cc2902df 1057 we want to set to nonzero in COMP. */
b5ce41ff 1058 if (comp)
c4c81601
RK
1059 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
1060 {
1061 SET_BIT (comp[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1062
c4c81601
RK
1063 /* While we're scanning the table, this is a good place to
1064 initialize this. */
1065 occr->copied_p = 0;
1066 }
b5ce41ff
JL
1067
1068 /* While we're scanning the table, this is a good place to
1069 initialize this. */
1070 expr->reaching_reg = 0;
1071 }
7506f491 1072 }
7506f491
DE
1073}
1074\f
1075/* Register set information.
1076
1077 `reg_set_table' records where each register is set or otherwise
1078 modified. */
1079
1080static struct obstack reg_set_obstack;
1081
1082static void
1d088dee 1083alloc_reg_set_mem (int n_regs)
7506f491 1084{
7506f491 1085 reg_set_table_size = n_regs + REG_SET_TABLE_SLOP;
9fe15a12 1086 reg_set_table = gcalloc (reg_set_table_size, sizeof (struct reg_set *));
7506f491
DE
1087
1088 gcc_obstack_init (&reg_set_obstack);
1089}
1090
1091static void
1d088dee 1092free_reg_set_mem (void)
7506f491
DE
1093{
1094 free (reg_set_table);
6496a589 1095 obstack_free (&reg_set_obstack, NULL);
7506f491
DE
1096}
1097
1098/* Record REGNO in the reg_set table. */
1099
1100static void
1d088dee 1101record_one_set (int regno, rtx insn)
7506f491 1102{
172890a2 1103 /* Allocate a new reg_set element and link it onto the list. */
63bc1d05 1104 struct reg_set *new_reg_info;
7506f491
DE
1105
1106 /* If the table isn't big enough, enlarge it. */
1107 if (regno >= reg_set_table_size)
1108 {
1109 int new_size = regno + REG_SET_TABLE_SLOP;
c4c81601 1110
703ad42b
KG
1111 reg_set_table = grealloc (reg_set_table,
1112 new_size * sizeof (struct reg_set *));
1113 memset (reg_set_table + reg_set_table_size, 0,
8e42ace1 1114 (new_size - reg_set_table_size) * sizeof (struct reg_set *));
7506f491
DE
1115 reg_set_table_size = new_size;
1116 }
1117
703ad42b 1118 new_reg_info = obstack_alloc (&reg_set_obstack, sizeof (struct reg_set));
7506f491 1119 bytes_used += sizeof (struct reg_set);
ed425871 1120 new_reg_info->bb_index = BLOCK_NUM (insn);
274969ea
MM
1121 new_reg_info->next = reg_set_table[regno];
1122 reg_set_table[regno] = new_reg_info;
7506f491
DE
1123}
1124
c4c81601
RK
1125/* Called from compute_sets via note_stores to handle one SET or CLOBBER in
1126 an insn. The DATA is really the instruction in which the SET is
1127 occurring. */
7506f491
DE
1128
1129static void
1d088dee 1130record_set_info (rtx dest, rtx setter ATTRIBUTE_UNUSED, void *data)
7506f491 1131{
84832317
MM
1132 rtx record_set_insn = (rtx) data;
1133
7b1b4aed 1134 if (REG_P (dest) && REGNO (dest) >= FIRST_PSEUDO_REGISTER)
c4c81601 1135 record_one_set (REGNO (dest), record_set_insn);
7506f491
DE
1136}
1137
1138/* Scan the function and record each set of each pseudo-register.
1139
c4c81601 1140 This is called once, at the start of the gcse pass. See the comments for
fbe5a4a6 1141 `reg_set_table' for further documentation. */
7506f491
DE
1142
1143static void
1d088dee 1144compute_sets (rtx f)
7506f491 1145{
c4c81601 1146 rtx insn;
7506f491 1147
c4c81601 1148 for (insn = f; insn != 0; insn = NEXT_INSN (insn))
2c3c49de 1149 if (INSN_P (insn))
c4c81601 1150 note_stores (PATTERN (insn), record_set_info, insn);
7506f491
DE
1151}
1152\f
1153/* Hash table support. */
1154
80c29cc4
RZ
1155struct reg_avail_info
1156{
e0082a72 1157 basic_block last_bb;
80c29cc4
RZ
1158 int first_set;
1159 int last_set;
1160};
1161
1162static struct reg_avail_info *reg_avail_info;
e0082a72 1163static basic_block current_bb;
7506f491 1164
7506f491 1165
fb0c0a12
RK
1166/* See whether X, the source of a set, is something we want to consider for
1167 GCSE. */
7506f491
DE
1168
1169static int
1d088dee 1170want_to_gcse_p (rtx x)
7506f491 1171{
c4c81601 1172 switch (GET_CODE (x))
7506f491
DE
1173 {
1174 case REG:
1175 case SUBREG:
1176 case CONST_INT:
1177 case CONST_DOUBLE:
69ef87e2 1178 case CONST_VECTOR:
7506f491
DE
1179 case CALL:
1180 return 0;
1181
1182 default:
1707bafa 1183 return can_assign_to_reg_p (x);
7506f491 1184 }
1707bafa
RS
1185}
1186
1187/* Used internally by can_assign_to_reg_p. */
1188
1189static GTY(()) rtx test_insn;
1190
1191/* Return true if we can assign X to a pseudo register. */
1192
1193static bool
1194can_assign_to_reg_p (rtx x)
1195{
1196 int num_clobbers = 0;
1197 int icode;
7506f491 1198
fb0c0a12
RK
1199 /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */
1200 if (general_operand (x, GET_MODE (x)))
1201 return 1;
1202 else if (GET_MODE (x) == VOIDmode)
1203 return 0;
1204
1205 /* Otherwise, check if we can make a valid insn from it. First initialize
1206 our test insn if we haven't already. */
1207 if (test_insn == 0)
1208 {
1209 test_insn
1210 = make_insn_raw (gen_rtx_SET (VOIDmode,
1211 gen_rtx_REG (word_mode,
1212 FIRST_PSEUDO_REGISTER * 2),
1213 const0_rtx));
1214 NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0;
fb0c0a12
RK
1215 }
1216
1217 /* Now make an insn like the one we would make when GCSE'ing and see if
1218 valid. */
1219 PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x));
1220 SET_SRC (PATTERN (test_insn)) = x;
1221 return ((icode = recog (PATTERN (test_insn), test_insn, &num_clobbers)) >= 0
1222 && (num_clobbers == 0 || ! added_clobbers_hard_reg_p (icode)));
7506f491
DE
1223}
1224
cc2902df 1225/* Return nonzero if the operands of expression X are unchanged from the
7506f491
DE
1226 start of INSN's basic block up to but not including INSN (if AVAIL_P == 0),
1227 or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */
1228
1229static int
1d088dee 1230oprs_unchanged_p (rtx x, rtx insn, int avail_p)
7506f491 1231{
c4c81601 1232 int i, j;
7506f491 1233 enum rtx_code code;
6f7d635c 1234 const char *fmt;
7506f491 1235
7506f491
DE
1236 if (x == 0)
1237 return 1;
1238
1239 code = GET_CODE (x);
1240 switch (code)
1241 {
1242 case REG:
80c29cc4
RZ
1243 {
1244 struct reg_avail_info *info = &reg_avail_info[REGNO (x)];
1245
1246 if (info->last_bb != current_bb)
1247 return 1;
589005ff 1248 if (avail_p)
80c29cc4
RZ
1249 return info->last_set < INSN_CUID (insn);
1250 else
1251 return info->first_set >= INSN_CUID (insn);
1252 }
7506f491
DE
1253
1254 case MEM:
e0082a72 1255 if (load_killed_in_block_p (current_bb, INSN_CUID (insn),
a13d4ebf
AM
1256 x, avail_p))
1257 return 0;
7506f491 1258 else
c4c81601 1259 return oprs_unchanged_p (XEXP (x, 0), insn, avail_p);
7506f491
DE
1260
1261 case PRE_DEC:
1262 case PRE_INC:
1263 case POST_DEC:
1264 case POST_INC:
4b983fdc
RH
1265 case PRE_MODIFY:
1266 case POST_MODIFY:
7506f491
DE
1267 return 0;
1268
1269 case PC:
1270 case CC0: /*FIXME*/
1271 case CONST:
1272 case CONST_INT:
1273 case CONST_DOUBLE:
69ef87e2 1274 case CONST_VECTOR:
7506f491
DE
1275 case SYMBOL_REF:
1276 case LABEL_REF:
1277 case ADDR_VEC:
1278 case ADDR_DIFF_VEC:
1279 return 1;
1280
1281 default:
1282 break;
1283 }
1284
c4c81601 1285 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1286 {
1287 if (fmt[i] == 'e')
1288 {
c4c81601
RK
1289 /* If we are about to do the last recursive call needed at this
1290 level, change it into iteration. This function is called enough
1291 to be worth it. */
7506f491 1292 if (i == 0)
c4c81601
RK
1293 return oprs_unchanged_p (XEXP (x, i), insn, avail_p);
1294
1295 else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p))
7506f491
DE
1296 return 0;
1297 }
1298 else if (fmt[i] == 'E')
c4c81601
RK
1299 for (j = 0; j < XVECLEN (x, i); j++)
1300 if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p))
1301 return 0;
7506f491
DE
1302 }
1303
1304 return 1;
1305}
1306
a13d4ebf
AM
1307/* Used for communication between mems_conflict_for_gcse_p and
1308 load_killed_in_block_p. Nonzero if mems_conflict_for_gcse_p finds a
1309 conflict between two memory references. */
1310static int gcse_mems_conflict_p;
1311
1312/* Used for communication between mems_conflict_for_gcse_p and
1313 load_killed_in_block_p. A memory reference for a load instruction,
1314 mems_conflict_for_gcse_p will see if a memory store conflicts with
1315 this memory load. */
1316static rtx gcse_mem_operand;
1317
1318/* DEST is the output of an instruction. If it is a memory reference, and
1319 possibly conflicts with the load found in gcse_mem_operand, then set
1320 gcse_mems_conflict_p to a nonzero value. */
1321
1322static void
1d088dee
AJ
1323mems_conflict_for_gcse_p (rtx dest, rtx setter ATTRIBUTE_UNUSED,
1324 void *data ATTRIBUTE_UNUSED)
a13d4ebf
AM
1325{
1326 while (GET_CODE (dest) == SUBREG
1327 || GET_CODE (dest) == ZERO_EXTRACT
a13d4ebf
AM
1328 || GET_CODE (dest) == STRICT_LOW_PART)
1329 dest = XEXP (dest, 0);
1330
1331 /* If DEST is not a MEM, then it will not conflict with the load. Note
1332 that function calls are assumed to clobber memory, but are handled
1333 elsewhere. */
7b1b4aed 1334 if (! MEM_P (dest))
a13d4ebf 1335 return;
aaa4ca30 1336
a13d4ebf 1337 /* If we are setting a MEM in our list of specially recognized MEMs,
589005ff
KH
1338 don't mark as killed this time. */
1339
47a3dae1 1340 if (expr_equiv_p (dest, gcse_mem_operand) && pre_ldst_mems != NULL)
a13d4ebf
AM
1341 {
1342 if (!find_rtx_in_ldst (dest))
1343 gcse_mems_conflict_p = 1;
1344 return;
1345 }
aaa4ca30 1346
a13d4ebf
AM
1347 if (true_dependence (dest, GET_MODE (dest), gcse_mem_operand,
1348 rtx_addr_varies_p))
1349 gcse_mems_conflict_p = 1;
1350}
1351
1352/* Return nonzero if the expression in X (a memory reference) is killed
1353 in block BB before or after the insn with the CUID in UID_LIMIT.
1354 AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills
1355 before UID_LIMIT.
1356
1357 To check the entire block, set UID_LIMIT to max_uid + 1 and
1358 AVAIL_P to 0. */
1359
1360static int
1d088dee 1361load_killed_in_block_p (basic_block bb, int uid_limit, rtx x, int avail_p)
a13d4ebf 1362{
0b17ab2f 1363 rtx list_entry = modify_mem_list[bb->index];
a13d4ebf
AM
1364 while (list_entry)
1365 {
1366 rtx setter;
1367 /* Ignore entries in the list that do not apply. */
1368 if ((avail_p
1369 && INSN_CUID (XEXP (list_entry, 0)) < uid_limit)
1370 || (! avail_p
1371 && INSN_CUID (XEXP (list_entry, 0)) > uid_limit))
1372 {
1373 list_entry = XEXP (list_entry, 1);
1374 continue;
1375 }
1376
1377 setter = XEXP (list_entry, 0);
1378
1379 /* If SETTER is a call everything is clobbered. Note that calls
1380 to pure functions are never put on the list, so we need not
1381 worry about them. */
7b1b4aed 1382 if (CALL_P (setter))
a13d4ebf
AM
1383 return 1;
1384
1385 /* SETTER must be an INSN of some kind that sets memory. Call
589005ff 1386 note_stores to examine each hunk of memory that is modified.
a13d4ebf
AM
1387
1388 The note_stores interface is pretty limited, so we have to
1389 communicate via global variables. Yuk. */
1390 gcse_mem_operand = x;
1391 gcse_mems_conflict_p = 0;
1392 note_stores (PATTERN (setter), mems_conflict_for_gcse_p, NULL);
1393 if (gcse_mems_conflict_p)
1394 return 1;
1395 list_entry = XEXP (list_entry, 1);
1396 }
1397 return 0;
1398}
1399
cc2902df 1400/* Return nonzero if the operands of expression X are unchanged from
7506f491
DE
1401 the start of INSN's basic block up to but not including INSN. */
1402
1403static int
1d088dee 1404oprs_anticipatable_p (rtx x, rtx insn)
7506f491
DE
1405{
1406 return oprs_unchanged_p (x, insn, 0);
1407}
1408
cc2902df 1409/* Return nonzero if the operands of expression X are unchanged from
7506f491
DE
1410 INSN to the end of INSN's basic block. */
1411
1412static int
1d088dee 1413oprs_available_p (rtx x, rtx insn)
7506f491
DE
1414{
1415 return oprs_unchanged_p (x, insn, 1);
1416}
1417
1418/* Hash expression X.
c4c81601
RK
1419
1420 MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean
1421 indicating if a volatile operand is found or if the expression contains
b58b21d5 1422 something we don't want to insert in the table. HASH_TABLE_SIZE is
0516f6fe 1423 the current size of the hash table to be probed. */
7506f491
DE
1424
1425static unsigned int
b58b21d5
RS
1426hash_expr (rtx x, enum machine_mode mode, int *do_not_record_p,
1427 int hash_table_size)
7506f491
DE
1428{
1429 unsigned int hash;
1430
1431 *do_not_record_p = 0;
1432
0516f6fe
SB
1433 hash = hash_rtx (x, mode, do_not_record_p,
1434 NULL, /*have_reg_qty=*/false);
7506f491
DE
1435 return hash % hash_table_size;
1436}
172890a2 1437
7506f491
DE
1438/* Hash a set of register REGNO.
1439
c4c81601
RK
1440 Sets are hashed on the register that is set. This simplifies the PRE copy
1441 propagation code.
7506f491
DE
1442
1443 ??? May need to make things more elaborate. Later, as necessary. */
1444
1445static unsigned int
1d088dee 1446hash_set (int regno, int hash_table_size)
7506f491
DE
1447{
1448 unsigned int hash;
1449
1450 hash = regno;
1451 return hash % hash_table_size;
1452}
1453
0516f6fe 1454/* Return nonzero if exp1 is equivalent to exp2. */
7506f491
DE
1455
1456static int
1d088dee 1457expr_equiv_p (rtx x, rtx y)
7506f491 1458{
0516f6fe 1459 return exp_equiv_p (x, y, 0, true);
7506f491
DE
1460}
1461
02280659 1462/* Insert expression X in INSN in the hash TABLE.
7506f491
DE
1463 If it is already present, record it as the last occurrence in INSN's
1464 basic block.
1465
1466 MODE is the mode of the value X is being stored into.
1467 It is only used if X is a CONST_INT.
1468
cc2902df
KH
1469 ANTIC_P is nonzero if X is an anticipatable expression.
1470 AVAIL_P is nonzero if X is an available expression. */
7506f491
DE
1471
1472static void
1d088dee
AJ
1473insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p,
1474 int avail_p, struct hash_table *table)
7506f491
DE
1475{
1476 int found, do_not_record_p;
1477 unsigned int hash;
1478 struct expr *cur_expr, *last_expr = NULL;
1479 struct occr *antic_occr, *avail_occr;
7506f491 1480
02280659 1481 hash = hash_expr (x, mode, &do_not_record_p, table->size);
7506f491
DE
1482
1483 /* Do not insert expression in table if it contains volatile operands,
1484 or if hash_expr determines the expression is something we don't want
1485 to or can't handle. */
1486 if (do_not_record_p)
1487 return;
1488
02280659 1489 cur_expr = table->table[hash];
7506f491
DE
1490 found = 0;
1491
c4c81601 1492 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1493 {
1494 /* If the expression isn't found, save a pointer to the end of
1495 the list. */
1496 last_expr = cur_expr;
1497 cur_expr = cur_expr->next_same_hash;
1498 }
1499
1500 if (! found)
1501 {
703ad42b 1502 cur_expr = gcse_alloc (sizeof (struct expr));
7506f491 1503 bytes_used += sizeof (struct expr);
02280659 1504 if (table->table[hash] == NULL)
c4c81601 1505 /* This is the first pattern that hashed to this index. */
02280659 1506 table->table[hash] = cur_expr;
7506f491 1507 else
c4c81601
RK
1508 /* Add EXPR to end of this hash chain. */
1509 last_expr->next_same_hash = cur_expr;
1510
589005ff 1511 /* Set the fields of the expr element. */
7506f491 1512 cur_expr->expr = x;
02280659 1513 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1514 cur_expr->next_same_hash = NULL;
1515 cur_expr->antic_occr = NULL;
1516 cur_expr->avail_occr = NULL;
1517 }
1518
1519 /* Now record the occurrence(s). */
7506f491
DE
1520 if (antic_p)
1521 {
1522 antic_occr = cur_expr->antic_occr;
1523
b6e47ceb
JL
1524 if (antic_occr && BLOCK_NUM (antic_occr->insn) != BLOCK_NUM (insn))
1525 antic_occr = NULL;
7506f491
DE
1526
1527 if (antic_occr)
c4c81601
RK
1528 /* Found another instance of the expression in the same basic block.
1529 Prefer the currently recorded one. We want the first one in the
1530 block and the block is scanned from start to end. */
1531 ; /* nothing to do */
7506f491
DE
1532 else
1533 {
1534 /* First occurrence of this expression in this basic block. */
703ad42b 1535 antic_occr = gcse_alloc (sizeof (struct occr));
7506f491 1536 bytes_used += sizeof (struct occr);
7506f491 1537 antic_occr->insn = insn;
b6e47ceb 1538 antic_occr->next = cur_expr->antic_occr;
f9957958 1539 antic_occr->deleted_p = 0;
b6e47ceb 1540 cur_expr->antic_occr = antic_occr;
7506f491
DE
1541 }
1542 }
1543
1544 if (avail_p)
1545 {
1546 avail_occr = cur_expr->avail_occr;
1547
b6e47ceb 1548 if (avail_occr && BLOCK_NUM (avail_occr->insn) == BLOCK_NUM (insn))
7506f491 1549 {
b6e47ceb
JL
1550 /* Found another instance of the expression in the same basic block.
1551 Prefer this occurrence to the currently recorded one. We want
1552 the last one in the block and the block is scanned from start
1553 to end. */
1554 avail_occr->insn = insn;
7506f491 1555 }
7506f491
DE
1556 else
1557 {
1558 /* First occurrence of this expression in this basic block. */
703ad42b 1559 avail_occr = gcse_alloc (sizeof (struct occr));
7506f491 1560 bytes_used += sizeof (struct occr);
7506f491 1561 avail_occr->insn = insn;
b6e47ceb 1562 avail_occr->next = cur_expr->avail_occr;
f9957958 1563 avail_occr->deleted_p = 0;
b6e47ceb 1564 cur_expr->avail_occr = avail_occr;
7506f491
DE
1565 }
1566 }
1567}
1568
1569/* Insert pattern X in INSN in the hash table.
1570 X is a SET of a reg to either another reg or a constant.
1571 If it is already present, record it as the last occurrence in INSN's
1572 basic block. */
1573
1574static void
1d088dee 1575insert_set_in_table (rtx x, rtx insn, struct hash_table *table)
7506f491
DE
1576{
1577 int found;
1578 unsigned int hash;
1579 struct expr *cur_expr, *last_expr = NULL;
b6e47ceb 1580 struct occr *cur_occr;
7506f491 1581
282899df 1582 gcc_assert (GET_CODE (x) == SET && REG_P (SET_DEST (x)));
7506f491 1583
02280659 1584 hash = hash_set (REGNO (SET_DEST (x)), table->size);
7506f491 1585
02280659 1586 cur_expr = table->table[hash];
7506f491
DE
1587 found = 0;
1588
c4c81601 1589 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1590 {
1591 /* If the expression isn't found, save a pointer to the end of
1592 the list. */
1593 last_expr = cur_expr;
1594 cur_expr = cur_expr->next_same_hash;
1595 }
1596
1597 if (! found)
1598 {
703ad42b 1599 cur_expr = gcse_alloc (sizeof (struct expr));
7506f491 1600 bytes_used += sizeof (struct expr);
02280659 1601 if (table->table[hash] == NULL)
c4c81601 1602 /* This is the first pattern that hashed to this index. */
02280659 1603 table->table[hash] = cur_expr;
7506f491 1604 else
c4c81601
RK
1605 /* Add EXPR to end of this hash chain. */
1606 last_expr->next_same_hash = cur_expr;
1607
7506f491
DE
1608 /* Set the fields of the expr element.
1609 We must copy X because it can be modified when copy propagation is
1610 performed on its operands. */
7506f491 1611 cur_expr->expr = copy_rtx (x);
02280659 1612 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1613 cur_expr->next_same_hash = NULL;
1614 cur_expr->antic_occr = NULL;
1615 cur_expr->avail_occr = NULL;
1616 }
1617
1618 /* Now record the occurrence. */
7506f491
DE
1619 cur_occr = cur_expr->avail_occr;
1620
b6e47ceb 1621 if (cur_occr && BLOCK_NUM (cur_occr->insn) == BLOCK_NUM (insn))
7506f491 1622 {
b6e47ceb
JL
1623 /* Found another instance of the expression in the same basic block.
1624 Prefer this occurrence to the currently recorded one. We want
1625 the last one in the block and the block is scanned from start
1626 to end. */
1627 cur_occr->insn = insn;
7506f491 1628 }
7506f491
DE
1629 else
1630 {
1631 /* First occurrence of this expression in this basic block. */
703ad42b 1632 cur_occr = gcse_alloc (sizeof (struct occr));
7506f491 1633 bytes_used += sizeof (struct occr);
c4c81601 1634
b6e47ceb
JL
1635 cur_occr->insn = insn;
1636 cur_occr->next = cur_expr->avail_occr;
1637 cur_occr->deleted_p = 0;
1638 cur_expr->avail_occr = cur_occr;
7506f491
DE
1639 }
1640}
1641
6b2d1c9e
RS
1642/* Determine whether the rtx X should be treated as a constant for
1643 the purposes of GCSE's constant propagation. */
1644
1645static bool
1d088dee 1646gcse_constant_p (rtx x)
6b2d1c9e
RS
1647{
1648 /* Consider a COMPARE of two integers constant. */
1649 if (GET_CODE (x) == COMPARE
1650 && GET_CODE (XEXP (x, 0)) == CONST_INT
1651 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1652 return true;
1653
db2f435b 1654 /* Consider a COMPARE of the same registers is a constant
7b1b4aed 1655 if they are not floating point registers. */
db2f435b 1656 if (GET_CODE(x) == COMPARE
7b1b4aed 1657 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))
db2f435b
AP
1658 && REGNO (XEXP (x, 0)) == REGNO (XEXP (x, 1))
1659 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
1660 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 1))))
1661 return true;
1662
6b2d1c9e
RS
1663 return CONSTANT_P (x);
1664}
1665
02280659
ZD
1666/* Scan pattern PAT of INSN and add an entry to the hash TABLE (set or
1667 expression one). */
7506f491
DE
1668
1669static void
1d088dee 1670hash_scan_set (rtx pat, rtx insn, struct hash_table *table)
7506f491
DE
1671{
1672 rtx src = SET_SRC (pat);
1673 rtx dest = SET_DEST (pat);
172890a2 1674 rtx note;
7506f491 1675
6e72d1e9 1676 if (GET_CODE (src) == CALL)
02280659 1677 hash_scan_call (src, insn, table);
7506f491 1678
7b1b4aed 1679 else if (REG_P (dest))
7506f491 1680 {
172890a2 1681 unsigned int regno = REGNO (dest);
7506f491
DE
1682 rtx tmp;
1683
172890a2
RK
1684 /* If this is a single set and we are doing constant propagation,
1685 see if a REG_NOTE shows this equivalent to a constant. */
02280659 1686 if (table->set_p && (note = find_reg_equal_equiv_note (insn)) != 0
6b2d1c9e 1687 && gcse_constant_p (XEXP (note, 0)))
172890a2
RK
1688 src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src);
1689
7506f491 1690 /* Only record sets of pseudo-regs in the hash table. */
02280659 1691 if (! table->set_p
7506f491
DE
1692 && regno >= FIRST_PSEUDO_REGISTER
1693 /* Don't GCSE something if we can't do a reg/reg copy. */
773eae39 1694 && can_copy_p (GET_MODE (dest))
068473ec
JH
1695 /* GCSE commonly inserts instruction after the insn. We can't
1696 do that easily for EH_REGION notes so disable GCSE on these
1697 for now. */
1698 && !find_reg_note (insn, REG_EH_REGION, NULL_RTX)
7506f491 1699 /* Is SET_SRC something we want to gcse? */
172890a2
RK
1700 && want_to_gcse_p (src)
1701 /* Don't CSE a nop. */
43e72072
JJ
1702 && ! set_noop_p (pat)
1703 /* Don't GCSE if it has attached REG_EQUIV note.
1704 At this point this only function parameters should have
1705 REG_EQUIV notes and if the argument slot is used somewhere
a1f300c0 1706 explicitly, it means address of parameter has been taken,
43e72072
JJ
1707 so we should not extend the lifetime of the pseudo. */
1708 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
7b1b4aed 1709 || ! MEM_P (XEXP (note, 0))))
7506f491
DE
1710 {
1711 /* An expression is not anticipatable if its operands are
52d76e11
RK
1712 modified before this insn or if this is not the only SET in
1713 this insn. */
1714 int antic_p = oprs_anticipatable_p (src, insn) && single_set (insn);
7506f491 1715 /* An expression is not available if its operands are
eb296bd9
GK
1716 subsequently modified, including this insn. It's also not
1717 available if this is a branch, because we can't insert
1718 a set after the branch. */
1719 int avail_p = (oprs_available_p (src, insn)
1720 && ! JUMP_P (insn));
c4c81601 1721
02280659 1722 insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table);
7506f491 1723 }
c4c81601 1724
7506f491 1725 /* Record sets for constant/copy propagation. */
02280659 1726 else if (table->set_p
7506f491 1727 && regno >= FIRST_PSEUDO_REGISTER
7b1b4aed 1728 && ((REG_P (src)
7506f491 1729 && REGNO (src) >= FIRST_PSEUDO_REGISTER
773eae39 1730 && can_copy_p (GET_MODE (dest))
172890a2 1731 && REGNO (src) != regno)
6b2d1c9e 1732 || gcse_constant_p (src))
7506f491
DE
1733 /* A copy is not available if its src or dest is subsequently
1734 modified. Here we want to search from INSN+1 on, but
1735 oprs_available_p searches from INSN on. */
a813c111 1736 && (insn == BB_END (BLOCK_FOR_INSN (insn))
7506f491
DE
1737 || ((tmp = next_nonnote_insn (insn)) != NULL_RTX
1738 && oprs_available_p (pat, tmp))))
02280659 1739 insert_set_in_table (pat, insn, table);
7506f491 1740 }
d91edf86 1741 /* In case of store we want to consider the memory value as available in
f5f2e3cd
MH
1742 the REG stored in that memory. This makes it possible to remove
1743 redundant loads from due to stores to the same location. */
7b1b4aed 1744 else if (flag_gcse_las && REG_P (src) && MEM_P (dest))
f5f2e3cd
MH
1745 {
1746 unsigned int regno = REGNO (src);
1747
1748 /* Do not do this for constant/copy propagation. */
1749 if (! table->set_p
1750 /* Only record sets of pseudo-regs in the hash table. */
1751 && regno >= FIRST_PSEUDO_REGISTER
1752 /* Don't GCSE something if we can't do a reg/reg copy. */
1753 && can_copy_p (GET_MODE (src))
1754 /* GCSE commonly inserts instruction after the insn. We can't
1755 do that easily for EH_REGION notes so disable GCSE on these
1756 for now. */
1757 && ! find_reg_note (insn, REG_EH_REGION, NULL_RTX)
1758 /* Is SET_DEST something we want to gcse? */
1759 && want_to_gcse_p (dest)
1760 /* Don't CSE a nop. */
1761 && ! set_noop_p (pat)
1762 /* Don't GCSE if it has attached REG_EQUIV note.
1763 At this point this only function parameters should have
1764 REG_EQUIV notes and if the argument slot is used somewhere
1765 explicitly, it means address of parameter has been taken,
1766 so we should not extend the lifetime of the pseudo. */
1767 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
7b1b4aed 1768 || ! MEM_P (XEXP (note, 0))))
f5f2e3cd
MH
1769 {
1770 /* Stores are never anticipatable. */
1771 int antic_p = 0;
1772 /* An expression is not available if its operands are
1773 subsequently modified, including this insn. It's also not
1774 available if this is a branch, because we can't insert
1775 a set after the branch. */
1776 int avail_p = oprs_available_p (dest, insn)
1777 && ! JUMP_P (insn);
1778
1779 /* Record the memory expression (DEST) in the hash table. */
1780 insert_expr_in_table (dest, GET_MODE (dest), insn,
1781 antic_p, avail_p, table);
1782 }
1783 }
7506f491
DE
1784}
1785
1786static void
1d088dee
AJ
1787hash_scan_clobber (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED,
1788 struct hash_table *table ATTRIBUTE_UNUSED)
7506f491
DE
1789{
1790 /* Currently nothing to do. */
1791}
1792
1793static void
1d088dee
AJ
1794hash_scan_call (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED,
1795 struct hash_table *table ATTRIBUTE_UNUSED)
7506f491
DE
1796{
1797 /* Currently nothing to do. */
1798}
1799
1800/* Process INSN and add hash table entries as appropriate.
1801
1802 Only available expressions that set a single pseudo-reg are recorded.
1803
1804 Single sets in a PARALLEL could be handled, but it's an extra complication
1805 that isn't dealt with right now. The trick is handling the CLOBBERs that
1806 are also in the PARALLEL. Later.
1807
cc2902df 1808 If SET_P is nonzero, this is for the assignment hash table,
ed79bb3d
R
1809 otherwise it is for the expression hash table.
1810 If IN_LIBCALL_BLOCK nonzero, we are in a libcall block, and should
1811 not record any expressions. */
7506f491
DE
1812
1813static void
1d088dee 1814hash_scan_insn (rtx insn, struct hash_table *table, int in_libcall_block)
7506f491
DE
1815{
1816 rtx pat = PATTERN (insn);
c4c81601 1817 int i;
7506f491 1818
172890a2
RK
1819 if (in_libcall_block)
1820 return;
1821
7506f491
DE
1822 /* Pick out the sets of INSN and for other forms of instructions record
1823 what's been modified. */
1824
172890a2 1825 if (GET_CODE (pat) == SET)
02280659 1826 hash_scan_set (pat, insn, table);
7506f491 1827 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
1828 for (i = 0; i < XVECLEN (pat, 0); i++)
1829 {
1830 rtx x = XVECEXP (pat, 0, i);
7506f491 1831
c4c81601 1832 if (GET_CODE (x) == SET)
02280659 1833 hash_scan_set (x, insn, table);
c4c81601 1834 else if (GET_CODE (x) == CLOBBER)
02280659 1835 hash_scan_clobber (x, insn, table);
6e72d1e9 1836 else if (GET_CODE (x) == CALL)
02280659 1837 hash_scan_call (x, insn, table);
c4c81601 1838 }
7506f491 1839
7506f491 1840 else if (GET_CODE (pat) == CLOBBER)
02280659 1841 hash_scan_clobber (pat, insn, table);
6e72d1e9 1842 else if (GET_CODE (pat) == CALL)
02280659 1843 hash_scan_call (pat, insn, table);
7506f491
DE
1844}
1845
1846static void
1d088dee 1847dump_hash_table (FILE *file, const char *name, struct hash_table *table)
7506f491
DE
1848{
1849 int i;
1850 /* Flattened out table, so it's printed in proper order. */
4da896b2
MM
1851 struct expr **flat_table;
1852 unsigned int *hash_val;
c4c81601 1853 struct expr *expr;
4da896b2 1854
703ad42b
KG
1855 flat_table = xcalloc (table->n_elems, sizeof (struct expr *));
1856 hash_val = xmalloc (table->n_elems * sizeof (unsigned int));
7506f491 1857
02280659
ZD
1858 for (i = 0; i < (int) table->size; i++)
1859 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
1860 {
1861 flat_table[expr->bitmap_index] = expr;
1862 hash_val[expr->bitmap_index] = i;
1863 }
7506f491
DE
1864
1865 fprintf (file, "%s hash table (%d buckets, %d entries)\n",
02280659 1866 name, table->size, table->n_elems);
7506f491 1867
02280659 1868 for (i = 0; i < (int) table->n_elems; i++)
21318741
RK
1869 if (flat_table[i] != 0)
1870 {
a0ac9e5a 1871 expr = flat_table[i];
21318741
RK
1872 fprintf (file, "Index %d (hash value %d)\n ",
1873 expr->bitmap_index, hash_val[i]);
a0ac9e5a 1874 print_rtl (file, expr->expr);
21318741
RK
1875 fprintf (file, "\n");
1876 }
7506f491
DE
1877
1878 fprintf (file, "\n");
4da896b2 1879
4da896b2
MM
1880 free (flat_table);
1881 free (hash_val);
7506f491
DE
1882}
1883
1884/* Record register first/last/block set information for REGNO in INSN.
c4c81601 1885
80c29cc4 1886 first_set records the first place in the block where the register
7506f491 1887 is set and is used to compute "anticipatability".
c4c81601 1888
80c29cc4 1889 last_set records the last place in the block where the register
7506f491 1890 is set and is used to compute "availability".
c4c81601 1891
80c29cc4
RZ
1892 last_bb records the block for which first_set and last_set are
1893 valid, as a quick test to invalidate them.
1894
7506f491
DE
1895 reg_set_in_block records whether the register is set in the block
1896 and is used to compute "transparency". */
1897
1898static void
1d088dee 1899record_last_reg_set_info (rtx insn, int regno)
7506f491 1900{
80c29cc4
RZ
1901 struct reg_avail_info *info = &reg_avail_info[regno];
1902 int cuid = INSN_CUID (insn);
c4c81601 1903
80c29cc4
RZ
1904 info->last_set = cuid;
1905 if (info->last_bb != current_bb)
1906 {
1907 info->last_bb = current_bb;
1908 info->first_set = cuid;
e0082a72 1909 SET_BIT (reg_set_in_block[current_bb->index], regno);
80c29cc4 1910 }
7506f491
DE
1911}
1912
a13d4ebf
AM
1913
1914/* Record all of the canonicalized MEMs of record_last_mem_set_info's insn.
1915 Note we store a pair of elements in the list, so they have to be
1916 taken off pairwise. */
1917
589005ff 1918static void
1d088dee
AJ
1919canon_list_insert (rtx dest ATTRIBUTE_UNUSED, rtx unused1 ATTRIBUTE_UNUSED,
1920 void * v_insn)
a13d4ebf
AM
1921{
1922 rtx dest_addr, insn;
0fe854a7 1923 int bb;
a13d4ebf
AM
1924
1925 while (GET_CODE (dest) == SUBREG
1926 || GET_CODE (dest) == ZERO_EXTRACT
a13d4ebf
AM
1927 || GET_CODE (dest) == STRICT_LOW_PART)
1928 dest = XEXP (dest, 0);
1929
1930 /* If DEST is not a MEM, then it will not conflict with a load. Note
1931 that function calls are assumed to clobber memory, but are handled
1932 elsewhere. */
1933
7b1b4aed 1934 if (! MEM_P (dest))
a13d4ebf
AM
1935 return;
1936
1937 dest_addr = get_addr (XEXP (dest, 0));
1938 dest_addr = canon_rtx (dest_addr);
589005ff 1939 insn = (rtx) v_insn;
0fe854a7 1940 bb = BLOCK_NUM (insn);
a13d4ebf 1941
589005ff 1942 canon_modify_mem_list[bb] =
0fe854a7 1943 alloc_EXPR_LIST (VOIDmode, dest_addr, canon_modify_mem_list[bb]);
589005ff 1944 canon_modify_mem_list[bb] =
0fe854a7 1945 alloc_EXPR_LIST (VOIDmode, dest, canon_modify_mem_list[bb]);
a13d4ebf
AM
1946}
1947
a13d4ebf
AM
1948/* Record memory modification information for INSN. We do not actually care
1949 about the memory location(s) that are set, or even how they are set (consider
1950 a CALL_INSN). We merely need to record which insns modify memory. */
7506f491
DE
1951
1952static void
1d088dee 1953record_last_mem_set_info (rtx insn)
7506f491 1954{
0fe854a7
RH
1955 int bb = BLOCK_NUM (insn);
1956
ccef9ef5 1957 /* load_killed_in_block_p will handle the case of calls clobbering
dc297297 1958 everything. */
0fe854a7
RH
1959 modify_mem_list[bb] = alloc_INSN_LIST (insn, modify_mem_list[bb]);
1960 bitmap_set_bit (modify_mem_list_set, bb);
a13d4ebf 1961
7b1b4aed 1962 if (CALL_P (insn))
a13d4ebf
AM
1963 {
1964 /* Note that traversals of this loop (other than for free-ing)
1965 will break after encountering a CALL_INSN. So, there's no
dc297297 1966 need to insert a pair of items, as canon_list_insert does. */
589005ff
KH
1967 canon_modify_mem_list[bb] =
1968 alloc_INSN_LIST (insn, canon_modify_mem_list[bb]);
aa47fcfa 1969 bitmap_set_bit (blocks_with_calls, bb);
a13d4ebf
AM
1970 }
1971 else
0fe854a7 1972 note_stores (PATTERN (insn), canon_list_insert, (void*) insn);
7506f491
DE
1973}
1974
7506f491 1975/* Called from compute_hash_table via note_stores to handle one
84832317
MM
1976 SET or CLOBBER in an insn. DATA is really the instruction in which
1977 the SET is taking place. */
7506f491
DE
1978
1979static void
1d088dee 1980record_last_set_info (rtx dest, rtx setter ATTRIBUTE_UNUSED, void *data)
7506f491 1981{
84832317
MM
1982 rtx last_set_insn = (rtx) data;
1983
7506f491
DE
1984 if (GET_CODE (dest) == SUBREG)
1985 dest = SUBREG_REG (dest);
1986
7b1b4aed 1987 if (REG_P (dest))
7506f491 1988 record_last_reg_set_info (last_set_insn, REGNO (dest));
7b1b4aed 1989 else if (MEM_P (dest)
7506f491
DE
1990 /* Ignore pushes, they clobber nothing. */
1991 && ! push_operand (dest, GET_MODE (dest)))
1992 record_last_mem_set_info (last_set_insn);
1993}
1994
1995/* Top level function to create an expression or assignment hash table.
1996
1997 Expression entries are placed in the hash table if
1998 - they are of the form (set (pseudo-reg) src),
1999 - src is something we want to perform GCSE on,
2000 - none of the operands are subsequently modified in the block
2001
2002 Assignment entries are placed in the hash table if
2003 - they are of the form (set (pseudo-reg) src),
2004 - src is something we want to perform const/copy propagation on,
2005 - none of the operands or target are subsequently modified in the block
c4c81601 2006
7506f491
DE
2007 Currently src must be a pseudo-reg or a const_int.
2008
02280659 2009 TABLE is the table computed. */
7506f491
DE
2010
2011static void
1d088dee 2012compute_hash_table_work (struct hash_table *table)
7506f491 2013{
80c29cc4 2014 unsigned int i;
7506f491
DE
2015
2016 /* While we compute the hash table we also compute a bit array of which
2017 registers are set in which blocks.
7506f491
DE
2018 ??? This isn't needed during const/copy propagation, but it's cheap to
2019 compute. Later. */
d55bc081 2020 sbitmap_vector_zero (reg_set_in_block, last_basic_block);
7506f491 2021
a13d4ebf 2022 /* re-Cache any INSN_LIST nodes we have allocated. */
73991d6a 2023 clear_modify_mem_tables ();
7506f491 2024 /* Some working arrays used to track first and last set in each block. */
703ad42b 2025 reg_avail_info = gmalloc (max_gcse_regno * sizeof (struct reg_avail_info));
80c29cc4
RZ
2026
2027 for (i = 0; i < max_gcse_regno; ++i)
e0082a72 2028 reg_avail_info[i].last_bb = NULL;
7506f491 2029
e0082a72 2030 FOR_EACH_BB (current_bb)
7506f491
DE
2031 {
2032 rtx insn;
770ae6cc 2033 unsigned int regno;
ed79bb3d 2034 int in_libcall_block;
7506f491
DE
2035
2036 /* First pass over the instructions records information used to
2037 determine when registers and memory are first and last set.
ccef9ef5 2038 ??? hard-reg reg_set_in_block computation
7506f491
DE
2039 could be moved to compute_sets since they currently don't change. */
2040
a813c111
SB
2041 for (insn = BB_HEAD (current_bb);
2042 insn && insn != NEXT_INSN (BB_END (current_bb));
7506f491
DE
2043 insn = NEXT_INSN (insn))
2044 {
2c3c49de 2045 if (! INSN_P (insn))
7506f491
DE
2046 continue;
2047
7b1b4aed 2048 if (CALL_P (insn))
7506f491
DE
2049 {
2050 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6e14af16 2051 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
7506f491 2052 record_last_reg_set_info (insn, regno);
c4c81601 2053
24a28584 2054 mark_call (insn);
7506f491
DE
2055 }
2056
84832317 2057 note_stores (PATTERN (insn), record_last_set_info, insn);
7506f491
DE
2058 }
2059
fbef91d8
RS
2060 /* Insert implicit sets in the hash table. */
2061 if (table->set_p
2062 && implicit_sets[current_bb->index] != NULL_RTX)
2063 hash_scan_set (implicit_sets[current_bb->index],
a813c111 2064 BB_HEAD (current_bb), table);
fbef91d8 2065
7506f491
DE
2066 /* The next pass builds the hash table. */
2067
a813c111
SB
2068 for (insn = BB_HEAD (current_bb), in_libcall_block = 0;
2069 insn && insn != NEXT_INSN (BB_END (current_bb));
7506f491 2070 insn = NEXT_INSN (insn))
2c3c49de 2071 if (INSN_P (insn))
c4c81601
RK
2072 {
2073 if (find_reg_note (insn, REG_LIBCALL, NULL_RTX))
589005ff 2074 in_libcall_block = 1;
02280659 2075 else if (table->set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
589005ff 2076 in_libcall_block = 0;
02280659
ZD
2077 hash_scan_insn (insn, table, in_libcall_block);
2078 if (!table->set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
589005ff 2079 in_libcall_block = 0;
8e42ace1 2080 }
7506f491
DE
2081 }
2082
80c29cc4
RZ
2083 free (reg_avail_info);
2084 reg_avail_info = NULL;
7506f491
DE
2085}
2086
02280659 2087/* Allocate space for the set/expr hash TABLE.
7506f491 2088 N_INSNS is the number of instructions in the function.
02280659
ZD
2089 It is used to determine the number of buckets to use.
2090 SET_P determines whether set or expression table will
2091 be created. */
7506f491
DE
2092
2093static void
1d088dee 2094alloc_hash_table (int n_insns, struct hash_table *table, int set_p)
7506f491
DE
2095{
2096 int n;
2097
02280659
ZD
2098 table->size = n_insns / 4;
2099 if (table->size < 11)
2100 table->size = 11;
c4c81601 2101
7506f491
DE
2102 /* Attempt to maintain efficient use of hash table.
2103 Making it an odd number is simplest for now.
2104 ??? Later take some measurements. */
02280659
ZD
2105 table->size |= 1;
2106 n = table->size * sizeof (struct expr *);
703ad42b 2107 table->table = gmalloc (n);
02280659 2108 table->set_p = set_p;
7506f491
DE
2109}
2110
02280659 2111/* Free things allocated by alloc_hash_table. */
7506f491
DE
2112
2113static void
1d088dee 2114free_hash_table (struct hash_table *table)
7506f491 2115{
02280659 2116 free (table->table);
7506f491
DE
2117}
2118
02280659
ZD
2119/* Compute the hash TABLE for doing copy/const propagation or
2120 expression hash table. */
7506f491
DE
2121
2122static void
1d088dee 2123compute_hash_table (struct hash_table *table)
7506f491
DE
2124{
2125 /* Initialize count of number of entries in hash table. */
02280659 2126 table->n_elems = 0;
703ad42b 2127 memset (table->table, 0, table->size * sizeof (struct expr *));
7506f491 2128
02280659 2129 compute_hash_table_work (table);
7506f491
DE
2130}
2131\f
2132/* Expression tracking support. */
2133
ceda50e9
RH
2134/* Lookup REGNO in the set TABLE. The result is a pointer to the
2135 table entry, or NULL if not found. */
7506f491
DE
2136
2137static struct expr *
1d088dee 2138lookup_set (unsigned int regno, struct hash_table *table)
7506f491 2139{
02280659 2140 unsigned int hash = hash_set (regno, table->size);
7506f491
DE
2141 struct expr *expr;
2142
02280659 2143 expr = table->table[hash];
7506f491 2144
ceda50e9
RH
2145 while (expr && REGNO (SET_DEST (expr->expr)) != regno)
2146 expr = expr->next_same_hash;
7506f491
DE
2147
2148 return expr;
2149}
2150
2151/* Return the next entry for REGNO in list EXPR. */
2152
2153static struct expr *
1d088dee 2154next_set (unsigned int regno, struct expr *expr)
7506f491
DE
2155{
2156 do
2157 expr = expr->next_same_hash;
2158 while (expr && REGNO (SET_DEST (expr->expr)) != regno);
c4c81601 2159
7506f491
DE
2160 return expr;
2161}
2162
0fe854a7
RH
2163/* Like free_INSN_LIST_list or free_EXPR_LIST_list, except that the node
2164 types may be mixed. */
2165
2166static void
1d088dee 2167free_insn_expr_list_list (rtx *listp)
0fe854a7
RH
2168{
2169 rtx list, next;
2170
2171 for (list = *listp; list ; list = next)
2172 {
2173 next = XEXP (list, 1);
2174 if (GET_CODE (list) == EXPR_LIST)
2175 free_EXPR_LIST_node (list);
2176 else
2177 free_INSN_LIST_node (list);
2178 }
2179
2180 *listp = NULL;
2181}
2182
73991d6a
JH
2183/* Clear canon_modify_mem_list and modify_mem_list tables. */
2184static void
1d088dee 2185clear_modify_mem_tables (void)
73991d6a 2186{
3cd8c58a 2187 unsigned i;
87c476a2 2188 bitmap_iterator bi;
73991d6a 2189
87c476a2
ZD
2190 EXECUTE_IF_SET_IN_BITMAP (modify_mem_list_set, 0, i, bi)
2191 {
2192 free_INSN_LIST_list (modify_mem_list + i);
87c476a2
ZD
2193 free_insn_expr_list_list (canon_modify_mem_list + i);
2194 }
9a6cf911 2195 bitmap_clear (modify_mem_list_set);
aa47fcfa 2196 bitmap_clear (blocks_with_calls);
73991d6a
JH
2197}
2198
9a6cf911 2199/* Release memory used by modify_mem_list_set. */
73991d6a
JH
2200
2201static void
1d088dee 2202free_modify_mem_tables (void)
73991d6a
JH
2203{
2204 clear_modify_mem_tables ();
2205 free (modify_mem_list);
2206 free (canon_modify_mem_list);
2207 modify_mem_list = 0;
2208 canon_modify_mem_list = 0;
2209}
2210
7506f491
DE
2211/* Reset tables used to keep track of what's still available [since the
2212 start of the block]. */
2213
2214static void
1d088dee 2215reset_opr_set_tables (void)
7506f491
DE
2216{
2217 /* Maintain a bitmap of which regs have been set since beginning of
2218 the block. */
73991d6a 2219 CLEAR_REG_SET (reg_set_bitmap);
c4c81601 2220
7506f491
DE
2221 /* Also keep a record of the last instruction to modify memory.
2222 For now this is very trivial, we only record whether any memory
2223 location has been modified. */
73991d6a 2224 clear_modify_mem_tables ();
7506f491
DE
2225}
2226
cc2902df 2227/* Return nonzero if the operands of X are not set before INSN in
7506f491
DE
2228 INSN's basic block. */
2229
2230static int
1d088dee 2231oprs_not_set_p (rtx x, rtx insn)
7506f491 2232{
c4c81601 2233 int i, j;
7506f491 2234 enum rtx_code code;
6f7d635c 2235 const char *fmt;
7506f491 2236
7506f491
DE
2237 if (x == 0)
2238 return 1;
2239
2240 code = GET_CODE (x);
2241 switch (code)
2242 {
2243 case PC:
2244 case CC0:
2245 case CONST:
2246 case CONST_INT:
2247 case CONST_DOUBLE:
69ef87e2 2248 case CONST_VECTOR:
7506f491
DE
2249 case SYMBOL_REF:
2250 case LABEL_REF:
2251 case ADDR_VEC:
2252 case ADDR_DIFF_VEC:
2253 return 1;
2254
2255 case MEM:
589005ff 2256 if (load_killed_in_block_p (BLOCK_FOR_INSN (insn),
e2d2ed72 2257 INSN_CUID (insn), x, 0))
a13d4ebf 2258 return 0;
c4c81601
RK
2259 else
2260 return oprs_not_set_p (XEXP (x, 0), insn);
7506f491
DE
2261
2262 case REG:
73991d6a 2263 return ! REGNO_REG_SET_P (reg_set_bitmap, REGNO (x));
7506f491
DE
2264
2265 default:
2266 break;
2267 }
2268
c4c81601 2269 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2270 {
2271 if (fmt[i] == 'e')
2272 {
7506f491
DE
2273 /* If we are about to do the last recursive call
2274 needed at this level, change it into iteration.
2275 This function is called enough to be worth it. */
2276 if (i == 0)
c4c81601
RK
2277 return oprs_not_set_p (XEXP (x, i), insn);
2278
2279 if (! oprs_not_set_p (XEXP (x, i), insn))
7506f491
DE
2280 return 0;
2281 }
2282 else if (fmt[i] == 'E')
c4c81601
RK
2283 for (j = 0; j < XVECLEN (x, i); j++)
2284 if (! oprs_not_set_p (XVECEXP (x, i, j), insn))
2285 return 0;
7506f491
DE
2286 }
2287
2288 return 1;
2289}
2290
2291/* Mark things set by a CALL. */
2292
2293static void
1d088dee 2294mark_call (rtx insn)
7506f491 2295{
24a28584 2296 if (! CONST_OR_PURE_CALL_P (insn))
a13d4ebf 2297 record_last_mem_set_info (insn);
7506f491
DE
2298}
2299
2300/* Mark things set by a SET. */
2301
2302static void
1d088dee 2303mark_set (rtx pat, rtx insn)
7506f491
DE
2304{
2305 rtx dest = SET_DEST (pat);
2306
2307 while (GET_CODE (dest) == SUBREG
2308 || GET_CODE (dest) == ZERO_EXTRACT
7506f491
DE
2309 || GET_CODE (dest) == STRICT_LOW_PART)
2310 dest = XEXP (dest, 0);
2311
7b1b4aed 2312 if (REG_P (dest))
73991d6a 2313 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (dest));
7b1b4aed 2314 else if (MEM_P (dest))
a13d4ebf
AM
2315 record_last_mem_set_info (insn);
2316
6e72d1e9 2317 if (GET_CODE (SET_SRC (pat)) == CALL)
b5ce41ff 2318 mark_call (insn);
7506f491
DE
2319}
2320
2321/* Record things set by a CLOBBER. */
2322
2323static void
1d088dee 2324mark_clobber (rtx pat, rtx insn)
7506f491
DE
2325{
2326 rtx clob = XEXP (pat, 0);
2327
2328 while (GET_CODE (clob) == SUBREG || GET_CODE (clob) == STRICT_LOW_PART)
2329 clob = XEXP (clob, 0);
2330
7b1b4aed 2331 if (REG_P (clob))
73991d6a 2332 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (clob));
a13d4ebf
AM
2333 else
2334 record_last_mem_set_info (insn);
7506f491
DE
2335}
2336
2337/* Record things set by INSN.
2338 This data is used by oprs_not_set_p. */
2339
2340static void
1d088dee 2341mark_oprs_set (rtx insn)
7506f491
DE
2342{
2343 rtx pat = PATTERN (insn);
c4c81601 2344 int i;
7506f491
DE
2345
2346 if (GET_CODE (pat) == SET)
2347 mark_set (pat, insn);
2348 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
2349 for (i = 0; i < XVECLEN (pat, 0); i++)
2350 {
2351 rtx x = XVECEXP (pat, 0, i);
2352
2353 if (GET_CODE (x) == SET)
2354 mark_set (x, insn);
2355 else if (GET_CODE (x) == CLOBBER)
2356 mark_clobber (x, insn);
6e72d1e9 2357 else if (GET_CODE (x) == CALL)
c4c81601
RK
2358 mark_call (insn);
2359 }
7506f491 2360
7506f491
DE
2361 else if (GET_CODE (pat) == CLOBBER)
2362 mark_clobber (pat, insn);
6e72d1e9 2363 else if (GET_CODE (pat) == CALL)
b5ce41ff 2364 mark_call (insn);
7506f491 2365}
b5ce41ff 2366
7506f491
DE
2367\f
2368/* Compute copy/constant propagation working variables. */
2369
2370/* Local properties of assignments. */
7506f491
DE
2371static sbitmap *cprop_pavloc;
2372static sbitmap *cprop_absaltered;
2373
2374/* Global properties of assignments (computed from the local properties). */
7506f491
DE
2375static sbitmap *cprop_avin;
2376static sbitmap *cprop_avout;
2377
c4c81601
RK
2378/* Allocate vars used for copy/const propagation. N_BLOCKS is the number of
2379 basic blocks. N_SETS is the number of sets. */
7506f491
DE
2380
2381static void
1d088dee 2382alloc_cprop_mem (int n_blocks, int n_sets)
7506f491
DE
2383{
2384 cprop_pavloc = sbitmap_vector_alloc (n_blocks, n_sets);
2385 cprop_absaltered = sbitmap_vector_alloc (n_blocks, n_sets);
2386
2387 cprop_avin = sbitmap_vector_alloc (n_blocks, n_sets);
2388 cprop_avout = sbitmap_vector_alloc (n_blocks, n_sets);
2389}
2390
2391/* Free vars used by copy/const propagation. */
2392
2393static void
1d088dee 2394free_cprop_mem (void)
7506f491 2395{
5a660bff
DB
2396 sbitmap_vector_free (cprop_pavloc);
2397 sbitmap_vector_free (cprop_absaltered);
2398 sbitmap_vector_free (cprop_avin);
2399 sbitmap_vector_free (cprop_avout);
7506f491
DE
2400}
2401
c4c81601
RK
2402/* For each block, compute whether X is transparent. X is either an
2403 expression or an assignment [though we don't care which, for this context
2404 an assignment is treated as an expression]. For each block where an
2405 element of X is modified, set (SET_P == 1) or reset (SET_P == 0) the INDX
2406 bit in BMAP. */
7506f491
DE
2407
2408static void
1d088dee 2409compute_transp (rtx x, int indx, sbitmap *bmap, int set_p)
7506f491 2410{
e0082a72
ZD
2411 int i, j;
2412 basic_block bb;
7506f491 2413 enum rtx_code code;
c4c81601 2414 reg_set *r;
6f7d635c 2415 const char *fmt;
7506f491 2416
c4c81601
RK
2417 /* repeat is used to turn tail-recursion into iteration since GCC
2418 can't do it when there's no return value. */
7506f491
DE
2419 repeat:
2420
2421 if (x == 0)
2422 return;
2423
2424 code = GET_CODE (x);
2425 switch (code)
2426 {
2427 case REG:
c4c81601
RK
2428 if (set_p)
2429 {
2430 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
2431 {
e0082a72
ZD
2432 FOR_EACH_BB (bb)
2433 if (TEST_BIT (reg_set_in_block[bb->index], REGNO (x)))
2434 SET_BIT (bmap[bb->index], indx);
c4c81601
RK
2435 }
2436 else
2437 {
2438 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
ed425871 2439 SET_BIT (bmap[r->bb_index], indx);
c4c81601
RK
2440 }
2441 }
2442 else
2443 {
2444 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
2445 {
e0082a72
ZD
2446 FOR_EACH_BB (bb)
2447 if (TEST_BIT (reg_set_in_block[bb->index], REGNO (x)))
2448 RESET_BIT (bmap[bb->index], indx);
c4c81601
RK
2449 }
2450 else
2451 {
2452 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
ed425871 2453 RESET_BIT (bmap[r->bb_index], indx);
c4c81601
RK
2454 }
2455 }
7506f491 2456
c4c81601 2457 return;
7506f491
DE
2458
2459 case MEM:
aa47fcfa
JL
2460 {
2461 bitmap_iterator bi;
2462 unsigned bb_index;
a13d4ebf 2463
aa47fcfa
JL
2464 /* First handle all the blocks with calls. We don't need to
2465 do any list walking for them. */
2466 EXECUTE_IF_SET_IN_BITMAP (blocks_with_calls, 0, bb_index, bi)
2467 {
2468 if (set_p)
2469 SET_BIT (bmap[bb_index], indx);
2470 else
2471 RESET_BIT (bmap[bb_index], indx);
2472 }
2473
2474 /* Now iterate over the blocks which have memory modifications
2475 but which do not have any calls. */
2476 EXECUTE_IF_AND_COMPL_IN_BITMAP (modify_mem_list_set, blocks_with_calls,
2477 0, bb_index, bi)
2478 {
2479 rtx list_entry = canon_modify_mem_list[bb_index];
2480
2481 while (list_entry)
2482 {
2483 rtx dest, dest_addr;
2484
2485 /* LIST_ENTRY must be an INSN of some kind that sets memory.
2486 Examine each hunk of memory that is modified. */
2487
2488 dest = XEXP (list_entry, 0);
2489 list_entry = XEXP (list_entry, 1);
2490 dest_addr = XEXP (list_entry, 0);
2491
2492 if (canon_true_dependence (dest, GET_MODE (dest), dest_addr,
2493 x, rtx_addr_varies_p))
2494 {
2495 if (set_p)
2496 SET_BIT (bmap[bb_index], indx);
2497 else
2498 RESET_BIT (bmap[bb_index], indx);
2499 break;
2500 }
2501 list_entry = XEXP (list_entry, 1);
2502 }
2503 }
2504 }
c4c81601 2505
7506f491
DE
2506 x = XEXP (x, 0);
2507 goto repeat;
2508
2509 case PC:
2510 case CC0: /*FIXME*/
2511 case CONST:
2512 case CONST_INT:
2513 case CONST_DOUBLE:
69ef87e2 2514 case CONST_VECTOR:
7506f491
DE
2515 case SYMBOL_REF:
2516 case LABEL_REF:
2517 case ADDR_VEC:
2518 case ADDR_DIFF_VEC:
2519 return;
2520
2521 default:
2522 break;
2523 }
2524
c4c81601 2525 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2526 {
2527 if (fmt[i] == 'e')
2528 {
7506f491
DE
2529 /* If we are about to do the last recursive call
2530 needed at this level, change it into iteration.
2531 This function is called enough to be worth it. */
2532 if (i == 0)
2533 {
c4c81601 2534 x = XEXP (x, i);
7506f491
DE
2535 goto repeat;
2536 }
c4c81601
RK
2537
2538 compute_transp (XEXP (x, i), indx, bmap, set_p);
7506f491
DE
2539 }
2540 else if (fmt[i] == 'E')
c4c81601
RK
2541 for (j = 0; j < XVECLEN (x, i); j++)
2542 compute_transp (XVECEXP (x, i, j), indx, bmap, set_p);
7506f491
DE
2543 }
2544}
2545
7506f491
DE
2546/* Top level routine to do the dataflow analysis needed by copy/const
2547 propagation. */
2548
2549static void
1d088dee 2550compute_cprop_data (void)
7506f491 2551{
02280659 2552 compute_local_properties (cprop_absaltered, cprop_pavloc, NULL, &set_hash_table);
ce724250
JL
2553 compute_available (cprop_pavloc, cprop_absaltered,
2554 cprop_avout, cprop_avin);
7506f491
DE
2555}
2556\f
2557/* Copy/constant propagation. */
2558
7506f491
DE
2559/* Maximum number of register uses in an insn that we handle. */
2560#define MAX_USES 8
2561
2562/* Table of uses found in an insn.
2563 Allocated statically to avoid alloc/free complexity and overhead. */
2564static struct reg_use reg_use_table[MAX_USES];
2565
2566/* Index into `reg_use_table' while building it. */
2567static int reg_use_count;
2568
c4c81601
RK
2569/* Set up a list of register numbers used in INSN. The found uses are stored
2570 in `reg_use_table'. `reg_use_count' is initialized to zero before entry,
2571 and contains the number of uses in the table upon exit.
7506f491 2572
c4c81601
RK
2573 ??? If a register appears multiple times we will record it multiple times.
2574 This doesn't hurt anything but it will slow things down. */
7506f491
DE
2575
2576static void
1d088dee 2577find_used_regs (rtx *xptr, void *data ATTRIBUTE_UNUSED)
7506f491 2578{
c4c81601 2579 int i, j;
7506f491 2580 enum rtx_code code;
6f7d635c 2581 const char *fmt;
9e71c818 2582 rtx x = *xptr;
7506f491 2583
c4c81601
RK
2584 /* repeat is used to turn tail-recursion into iteration since GCC
2585 can't do it when there's no return value. */
7506f491 2586 repeat:
7506f491
DE
2587 if (x == 0)
2588 return;
2589
2590 code = GET_CODE (x);
9e71c818 2591 if (REG_P (x))
7506f491 2592 {
7506f491
DE
2593 if (reg_use_count == MAX_USES)
2594 return;
c4c81601 2595
7506f491
DE
2596 reg_use_table[reg_use_count].reg_rtx = x;
2597 reg_use_count++;
7506f491
DE
2598 }
2599
2600 /* Recursively scan the operands of this expression. */
2601
c4c81601 2602 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2603 {
2604 if (fmt[i] == 'e')
2605 {
2606 /* If we are about to do the last recursive call
2607 needed at this level, change it into iteration.
2608 This function is called enough to be worth it. */
2609 if (i == 0)
2610 {
2611 x = XEXP (x, 0);
2612 goto repeat;
2613 }
c4c81601 2614
9e71c818 2615 find_used_regs (&XEXP (x, i), data);
7506f491
DE
2616 }
2617 else if (fmt[i] == 'E')
c4c81601 2618 for (j = 0; j < XVECLEN (x, i); j++)
9e71c818 2619 find_used_regs (&XVECEXP (x, i, j), data);
7506f491
DE
2620 }
2621}
2622
2623/* Try to replace all non-SET_DEST occurrences of FROM in INSN with TO.
cc2902df 2624 Returns nonzero is successful. */
7506f491
DE
2625
2626static int
1d088dee 2627try_replace_reg (rtx from, rtx to, rtx insn)
7506f491 2628{
172890a2 2629 rtx note = find_reg_equal_equiv_note (insn);
fb0c0a12 2630 rtx src = 0;
172890a2
RK
2631 int success = 0;
2632 rtx set = single_set (insn);
833fc3ad 2633
2b773ee2
JH
2634 validate_replace_src_group (from, to, insn);
2635 if (num_changes_pending () && apply_change_group ())
2636 success = 1;
9e71c818 2637
9feff114
JDA
2638 /* Try to simplify SET_SRC if we have substituted a constant. */
2639 if (success && set && CONSTANT_P (to))
2640 {
2641 src = simplify_rtx (SET_SRC (set));
2642
2643 if (src)
2644 validate_change (insn, &SET_SRC (set), src, 0);
2645 }
2646
ed8395a0
JZ
2647 /* If there is already a NOTE, update the expression in it with our
2648 replacement. */
2649 if (note != 0)
2650 XEXP (note, 0) = simplify_replace_rtx (XEXP (note, 0), from, to);
2651
f305679f 2652 if (!success && set && reg_mentioned_p (from, SET_SRC (set)))
833fc3ad 2653 {
f305679f
JH
2654 /* If above failed and this is a single set, try to simplify the source of
2655 the set given our substitution. We could perhaps try this for multiple
2656 SETs, but it probably won't buy us anything. */
172890a2
RK
2657 src = simplify_replace_rtx (SET_SRC (set), from, to);
2658
9e71c818
JH
2659 if (!rtx_equal_p (src, SET_SRC (set))
2660 && validate_change (insn, &SET_SRC (set), src, 0))
172890a2 2661 success = 1;
833fc3ad 2662
bbd288a4
FS
2663 /* If we've failed to do replacement, have a single SET, don't already
2664 have a note, and have no special SET, add a REG_EQUAL note to not
2665 lose information. */
2666 if (!success && note == 0 && set != 0
46d096a3 2667 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT)
f305679f
JH
2668 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
2669 }
e251e2a2 2670
172890a2
RK
2671 /* REG_EQUAL may get simplified into register.
2672 We don't allow that. Remove that note. This code ought
fbe5a4a6 2673 not to happen, because previous code ought to synthesize
172890a2
RK
2674 reg-reg move, but be on the safe side. */
2675 if (note && REG_P (XEXP (note, 0)))
2676 remove_note (insn, note);
833fc3ad 2677
833fc3ad
JH
2678 return success;
2679}
c4c81601
RK
2680
2681/* Find a set of REGNOs that are available on entry to INSN's block. Returns
2682 NULL no such set is found. */
7506f491
DE
2683
2684static struct expr *
1d088dee 2685find_avail_set (int regno, rtx insn)
7506f491 2686{
cafba495
BS
2687 /* SET1 contains the last set found that can be returned to the caller for
2688 use in a substitution. */
2689 struct expr *set1 = 0;
589005ff 2690
cafba495 2691 /* Loops are not possible here. To get a loop we would need two sets
454ff5cb 2692 available at the start of the block containing INSN. i.e. we would
cafba495
BS
2693 need two sets like this available at the start of the block:
2694
2695 (set (reg X) (reg Y))
2696 (set (reg Y) (reg X))
2697
2698 This can not happen since the set of (reg Y) would have killed the
2699 set of (reg X) making it unavailable at the start of this block. */
2700 while (1)
8e42ace1 2701 {
cafba495 2702 rtx src;
ceda50e9 2703 struct expr *set = lookup_set (regno, &set_hash_table);
cafba495
BS
2704
2705 /* Find a set that is available at the start of the block
2706 which contains INSN. */
2707 while (set)
2708 {
2709 if (TEST_BIT (cprop_avin[BLOCK_NUM (insn)], set->bitmap_index))
2710 break;
2711 set = next_set (regno, set);
2712 }
7506f491 2713
cafba495
BS
2714 /* If no available set was found we've reached the end of the
2715 (possibly empty) copy chain. */
2716 if (set == 0)
589005ff 2717 break;
cafba495 2718
282899df 2719 gcc_assert (GET_CODE (set->expr) == SET);
cafba495
BS
2720
2721 src = SET_SRC (set->expr);
2722
2723 /* We know the set is available.
2724 Now check that SRC is ANTLOC (i.e. none of the source operands
589005ff 2725 have changed since the start of the block).
cafba495
BS
2726
2727 If the source operand changed, we may still use it for the next
2728 iteration of this loop, but we may not use it for substitutions. */
c4c81601 2729
6b2d1c9e 2730 if (gcse_constant_p (src) || oprs_not_set_p (src, insn))
cafba495
BS
2731 set1 = set;
2732
2733 /* If the source of the set is anything except a register, then
2734 we have reached the end of the copy chain. */
7b1b4aed 2735 if (! REG_P (src))
7506f491 2736 break;
7506f491 2737
454ff5cb 2738 /* Follow the copy chain, i.e. start another iteration of the loop
cafba495
BS
2739 and see if we have an available copy into SRC. */
2740 regno = REGNO (src);
8e42ace1 2741 }
cafba495
BS
2742
2743 /* SET1 holds the last set that was available and anticipatable at
2744 INSN. */
2745 return set1;
7506f491
DE
2746}
2747
abd535b6 2748/* Subroutine of cprop_insn that tries to propagate constants into
0e3f0221 2749 JUMP_INSNS. JUMP must be a conditional jump. If SETCC is non-NULL
fbe5a4a6 2750 it is the instruction that immediately precedes JUMP, and must be a
818b6b7f 2751 single SET of a register. FROM is what we will try to replace,
0e3f0221 2752 SRC is the constant we will try to substitute for it. Returns nonzero
589005ff 2753 if a change was made. */
c4c81601 2754
abd535b6 2755static int
1d088dee 2756cprop_jump (basic_block bb, rtx setcc, rtx jump, rtx from, rtx src)
abd535b6 2757{
bc6688b4 2758 rtx new, set_src, note_src;
0e3f0221 2759 rtx set = pc_set (jump);
bc6688b4 2760 rtx note = find_reg_equal_equiv_note (jump);
0e3f0221 2761
bc6688b4
RS
2762 if (note)
2763 {
2764 note_src = XEXP (note, 0);
2765 if (GET_CODE (note_src) == EXPR_LIST)
2766 note_src = NULL_RTX;
2767 }
2768 else note_src = NULL_RTX;
2769
2770 /* Prefer REG_EQUAL notes except those containing EXPR_LISTs. */
2771 set_src = note_src ? note_src : SET_SRC (set);
2772
2773 /* First substitute the SETCC condition into the JUMP instruction,
2774 then substitute that given values into this expanded JUMP. */
2775 if (setcc != NULL_RTX
48ddd46c
JH
2776 && !modified_between_p (from, setcc, jump)
2777 && !modified_between_p (src, setcc, jump))
b2f02503 2778 {
bc6688b4 2779 rtx setcc_src;
b2f02503 2780 rtx setcc_set = single_set (setcc);
bc6688b4
RS
2781 rtx setcc_note = find_reg_equal_equiv_note (setcc);
2782 setcc_src = (setcc_note && GET_CODE (XEXP (setcc_note, 0)) != EXPR_LIST)
2783 ? XEXP (setcc_note, 0) : SET_SRC (setcc_set);
2784 set_src = simplify_replace_rtx (set_src, SET_DEST (setcc_set),
2785 setcc_src);
b2f02503 2786 }
0e3f0221 2787 else
bc6688b4 2788 setcc = NULL_RTX;
0e3f0221 2789
bc6688b4 2790 new = simplify_replace_rtx (set_src, from, src);
abd535b6 2791
bc6688b4
RS
2792 /* If no simplification can be made, then try the next register. */
2793 if (rtx_equal_p (new, SET_SRC (set)))
9e48c409 2794 return 0;
589005ff 2795
7d5ab30e 2796 /* If this is now a no-op delete it, otherwise this must be a valid insn. */
172890a2 2797 if (new == pc_rtx)
0e3f0221 2798 delete_insn (jump);
7d5ab30e 2799 else
abd535b6 2800 {
48ddd46c
JH
2801 /* Ensure the value computed inside the jump insn to be equivalent
2802 to one computed by setcc. */
bc6688b4 2803 if (setcc && modified_in_p (new, setcc))
48ddd46c 2804 return 0;
0e3f0221 2805 if (! validate_change (jump, &SET_SRC (set), new, 0))
bc6688b4
RS
2806 {
2807 /* When (some) constants are not valid in a comparison, and there
2808 are two registers to be replaced by constants before the entire
2809 comparison can be folded into a constant, we need to keep
2810 intermediate information in REG_EQUAL notes. For targets with
2811 separate compare insns, such notes are added by try_replace_reg.
2812 When we have a combined compare-and-branch instruction, however,
2813 we need to attach a note to the branch itself to make this
2814 optimization work. */
2815
2816 if (!rtx_equal_p (new, note_src))
2817 set_unique_reg_note (jump, REG_EQUAL, copy_rtx (new));
2818 return 0;
2819 }
2820
2821 /* Remove REG_EQUAL note after simplification. */
2822 if (note_src)
2823 remove_note (jump, note);
abd535b6 2824
7d5ab30e
JH
2825 /* If this has turned into an unconditional jump,
2826 then put a barrier after it so that the unreachable
2827 code will be deleted. */
2828 if (GET_CODE (SET_SRC (set)) == LABEL_REF)
0e3f0221 2829 emit_barrier_after (jump);
7d5ab30e 2830 }
abd535b6 2831
0e3f0221
RS
2832#ifdef HAVE_cc0
2833 /* Delete the cc0 setter. */
818b6b7f 2834 if (setcc != NULL && CC0_P (SET_DEST (single_set (setcc))))
0e3f0221
RS
2835 delete_insn (setcc);
2836#endif
2837
172890a2 2838 run_jump_opt_after_gcse = 1;
c4c81601 2839
27fb79ad 2840 global_const_prop_count++;
172890a2
RK
2841 if (gcse_file != NULL)
2842 {
2843 fprintf (gcse_file,
27fb79ad 2844 "GLOBAL CONST-PROP: Replacing reg %d in jump_insn %d with constant ",
0e3f0221 2845 REGNO (from), INSN_UID (jump));
172890a2
RK
2846 print_rtl (gcse_file, src);
2847 fprintf (gcse_file, "\n");
abd535b6 2848 }
0005550b 2849 purge_dead_edges (bb);
172890a2
RK
2850
2851 return 1;
abd535b6
BS
2852}
2853
ae860ff7 2854static bool
1d088dee 2855constprop_register (rtx insn, rtx from, rtx to, int alter_jumps)
ae860ff7
JH
2856{
2857 rtx sset;
2858
2859 /* Check for reg or cc0 setting instructions followed by
2860 conditional branch instructions first. */
2861 if (alter_jumps
2862 && (sset = single_set (insn)) != NULL
244d05fb 2863 && NEXT_INSN (insn)
ae860ff7
JH
2864 && any_condjump_p (NEXT_INSN (insn)) && onlyjump_p (NEXT_INSN (insn)))
2865 {
2866 rtx dest = SET_DEST (sset);
2867 if ((REG_P (dest) || CC0_P (dest))
2868 && cprop_jump (BLOCK_FOR_INSN (insn), insn, NEXT_INSN (insn), from, to))
2869 return 1;
2870 }
2871
2872 /* Handle normal insns next. */
4b4bf941 2873 if (NONJUMP_INSN_P (insn)
ae860ff7
JH
2874 && try_replace_reg (from, to, insn))
2875 return 1;
2876
2877 /* Try to propagate a CONST_INT into a conditional jump.
2878 We're pretty specific about what we will handle in this
2879 code, we can extend this as necessary over time.
2880
2881 Right now the insn in question must look like
2882 (set (pc) (if_then_else ...)) */
2883 else if (alter_jumps && any_condjump_p (insn) && onlyjump_p (insn))
2884 return cprop_jump (BLOCK_FOR_INSN (insn), NULL, insn, from, to);
2885 return 0;
2886}
2887
7506f491 2888/* Perform constant and copy propagation on INSN.
cc2902df 2889 The result is nonzero if a change was made. */
7506f491
DE
2890
2891static int
1d088dee 2892cprop_insn (rtx insn, int alter_jumps)
7506f491
DE
2893{
2894 struct reg_use *reg_used;
2895 int changed = 0;
833fc3ad 2896 rtx note;
7506f491 2897
9e71c818 2898 if (!INSN_P (insn))
7506f491
DE
2899 return 0;
2900
2901 reg_use_count = 0;
9e71c818 2902 note_uses (&PATTERN (insn), find_used_regs, NULL);
589005ff 2903
172890a2 2904 note = find_reg_equal_equiv_note (insn);
833fc3ad 2905
dc297297 2906 /* We may win even when propagating constants into notes. */
833fc3ad 2907 if (note)
9e71c818 2908 find_used_regs (&XEXP (note, 0), NULL);
7506f491 2909
c4c81601
RK
2910 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
2911 reg_used++, reg_use_count--)
7506f491 2912 {
770ae6cc 2913 unsigned int regno = REGNO (reg_used->reg_rtx);
7506f491
DE
2914 rtx pat, src;
2915 struct expr *set;
7506f491
DE
2916
2917 /* Ignore registers created by GCSE.
dc297297 2918 We do this because ... */
7506f491
DE
2919 if (regno >= max_gcse_regno)
2920 continue;
2921
2922 /* If the register has already been set in this block, there's
2923 nothing we can do. */
2924 if (! oprs_not_set_p (reg_used->reg_rtx, insn))
2925 continue;
2926
2927 /* Find an assignment that sets reg_used and is available
2928 at the start of the block. */
2929 set = find_avail_set (regno, insn);
2930 if (! set)
2931 continue;
589005ff 2932
7506f491
DE
2933 pat = set->expr;
2934 /* ??? We might be able to handle PARALLELs. Later. */
282899df 2935 gcc_assert (GET_CODE (pat) == SET);
c4c81601 2936
7506f491
DE
2937 src = SET_SRC (pat);
2938
e78d9500 2939 /* Constant propagation. */
6b2d1c9e 2940 if (gcse_constant_p (src))
7506f491 2941 {
ae860ff7 2942 if (constprop_register (insn, reg_used->reg_rtx, src, alter_jumps))
7506f491
DE
2943 {
2944 changed = 1;
27fb79ad 2945 global_const_prop_count++;
7506f491
DE
2946 if (gcse_file != NULL)
2947 {
ae860ff7
JH
2948 fprintf (gcse_file, "GLOBAL CONST-PROP: Replacing reg %d in ", regno);
2949 fprintf (gcse_file, "insn %d with constant ", INSN_UID (insn));
e78d9500 2950 print_rtl (gcse_file, src);
7506f491
DE
2951 fprintf (gcse_file, "\n");
2952 }
bc6688b4
RS
2953 if (INSN_DELETED_P (insn))
2954 return 1;
7506f491
DE
2955 }
2956 }
7b1b4aed 2957 else if (REG_P (src)
7506f491
DE
2958 && REGNO (src) >= FIRST_PSEUDO_REGISTER
2959 && REGNO (src) != regno)
2960 {
cafba495 2961 if (try_replace_reg (reg_used->reg_rtx, src, insn))
7506f491 2962 {
cafba495 2963 changed = 1;
27fb79ad 2964 global_copy_prop_count++;
cafba495 2965 if (gcse_file != NULL)
7506f491 2966 {
ae860ff7 2967 fprintf (gcse_file, "GLOBAL COPY-PROP: Replacing reg %d in insn %d",
c4c81601
RK
2968 regno, INSN_UID (insn));
2969 fprintf (gcse_file, " with reg %d\n", REGNO (src));
7506f491 2970 }
cafba495
BS
2971
2972 /* The original insn setting reg_used may or may not now be
2973 deletable. We leave the deletion to flow. */
2974 /* FIXME: If it turns out that the insn isn't deletable,
2975 then we may have unnecessarily extended register lifetimes
2976 and made things worse. */
7506f491
DE
2977 }
2978 }
2979 }
2980
2981 return changed;
2982}
2983
710ee3ed
RH
2984/* Like find_used_regs, but avoid recording uses that appear in
2985 input-output contexts such as zero_extract or pre_dec. This
2986 restricts the cases we consider to those for which local cprop
2987 can legitimately make replacements. */
2988
2989static void
1d088dee 2990local_cprop_find_used_regs (rtx *xptr, void *data)
710ee3ed
RH
2991{
2992 rtx x = *xptr;
2993
2994 if (x == 0)
2995 return;
2996
2997 switch (GET_CODE (x))
2998 {
2999 case ZERO_EXTRACT:
3000 case SIGN_EXTRACT:
3001 case STRICT_LOW_PART:
3002 return;
3003
3004 case PRE_DEC:
3005 case PRE_INC:
3006 case POST_DEC:
3007 case POST_INC:
3008 case PRE_MODIFY:
3009 case POST_MODIFY:
3010 /* Can only legitimately appear this early in the context of
3011 stack pushes for function arguments, but handle all of the
3012 codes nonetheless. */
3013 return;
3014
3015 case SUBREG:
3016 /* Setting a subreg of a register larger than word_mode leaves
3017 the non-written words unchanged. */
3018 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) > BITS_PER_WORD)
3019 return;
3020 break;
3021
3022 default:
3023 break;
3024 }
3025
3026 find_used_regs (xptr, data);
3027}
1d088dee 3028
8ba46434
R
3029/* LIBCALL_SP is a zero-terminated array of insns at the end of a libcall;
3030 their REG_EQUAL notes need updating. */
e197b6fc 3031
ae860ff7 3032static bool
1d088dee 3033do_local_cprop (rtx x, rtx insn, int alter_jumps, rtx *libcall_sp)
ae860ff7
JH
3034{
3035 rtx newreg = NULL, newcnst = NULL;
3036
e197b6fc
RH
3037 /* Rule out USE instructions and ASM statements as we don't want to
3038 change the hard registers mentioned. */
7b1b4aed 3039 if (REG_P (x)
ae860ff7 3040 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
e197b6fc
RH
3041 || (GET_CODE (PATTERN (insn)) != USE
3042 && asm_noperands (PATTERN (insn)) < 0)))
ae860ff7
JH
3043 {
3044 cselib_val *val = cselib_lookup (x, GET_MODE (x), 0);
3045 struct elt_loc_list *l;
3046
3047 if (!val)
3048 return false;
3049 for (l = val->locs; l; l = l->next)
3050 {
3051 rtx this_rtx = l->loc;
46690369
JH
3052 rtx note;
3053
5976e643
RS
3054 /* Don't CSE non-constant values out of libcall blocks. */
3055 if (l->in_libcall && ! CONSTANT_P (this_rtx))
9635cfad
JH
3056 continue;
3057
6b2d1c9e 3058 if (gcse_constant_p (this_rtx))
ae860ff7 3059 newcnst = this_rtx;
46690369
JH
3060 if (REG_P (this_rtx) && REGNO (this_rtx) >= FIRST_PSEUDO_REGISTER
3061 /* Don't copy propagate if it has attached REG_EQUIV note.
3062 At this point this only function parameters should have
3063 REG_EQUIV notes and if the argument slot is used somewhere
3064 explicitly, it means address of parameter has been taken,
3065 so we should not extend the lifetime of the pseudo. */
3066 && (!(note = find_reg_note (l->setting_insn, REG_EQUIV, NULL_RTX))
7b1b4aed 3067 || ! MEM_P (XEXP (note, 0))))
ae860ff7
JH
3068 newreg = this_rtx;
3069 }
3070 if (newcnst && constprop_register (insn, x, newcnst, alter_jumps))
3071 {
8ba46434 3072 /* If we find a case where we can't fix the retval REG_EQUAL notes
fbe5a4a6 3073 match the new register, we either have to abandon this replacement
8ba46434
R
3074 or fix delete_trivially_dead_insns to preserve the setting insn,
3075 or make it delete the REG_EUAQL note, and fix up all passes that
3076 require the REG_EQUAL note there. */
282899df
NS
3077 bool adjusted;
3078
3079 adjusted = adjust_libcall_notes (x, newcnst, insn, libcall_sp);
3080 gcc_assert (adjusted);
3081
ae860ff7
JH
3082 if (gcse_file != NULL)
3083 {
3084 fprintf (gcse_file, "LOCAL CONST-PROP: Replacing reg %d in ",
3085 REGNO (x));
3086 fprintf (gcse_file, "insn %d with constant ",
3087 INSN_UID (insn));
3088 print_rtl (gcse_file, newcnst);
3089 fprintf (gcse_file, "\n");
3090 }
27fb79ad 3091 local_const_prop_count++;
ae860ff7
JH
3092 return true;
3093 }
3094 else if (newreg && newreg != x && try_replace_reg (x, newreg, insn))
3095 {
8ba46434 3096 adjust_libcall_notes (x, newreg, insn, libcall_sp);
ae860ff7
JH
3097 if (gcse_file != NULL)
3098 {
3099 fprintf (gcse_file,
3100 "LOCAL COPY-PROP: Replacing reg %d in insn %d",
3101 REGNO (x), INSN_UID (insn));
3102 fprintf (gcse_file, " with reg %d\n", REGNO (newreg));
3103 }
27fb79ad 3104 local_copy_prop_count++;
ae860ff7
JH
3105 return true;
3106 }
3107 }
3108 return false;
3109}
3110
8ba46434
R
3111/* LIBCALL_SP is a zero-terminated array of insns at the end of a libcall;
3112 their REG_EQUAL notes need updating to reflect that OLDREG has been
f4e3e618
RH
3113 replaced with NEWVAL in INSN. Return true if all substitutions could
3114 be made. */
8ba46434 3115static bool
1d088dee 3116adjust_libcall_notes (rtx oldreg, rtx newval, rtx insn, rtx *libcall_sp)
8ba46434 3117{
f4e3e618 3118 rtx end;
8ba46434
R
3119
3120 while ((end = *libcall_sp++))
3121 {
f4e3e618 3122 rtx note = find_reg_equal_equiv_note (end);
8ba46434
R
3123
3124 if (! note)
3125 continue;
3126
3127 if (REG_P (newval))
3128 {
3129 if (reg_set_between_p (newval, PREV_INSN (insn), end))
3130 {
3131 do
3132 {
3133 note = find_reg_equal_equiv_note (end);
3134 if (! note)
3135 continue;
3136 if (reg_mentioned_p (newval, XEXP (note, 0)))
3137 return false;
3138 }
3139 while ((end = *libcall_sp++));
3140 return true;
3141 }
3142 }
5976e643 3143 XEXP (note, 0) = simplify_replace_rtx (XEXP (note, 0), oldreg, newval);
8ba46434
R
3144 insn = end;
3145 }
3146 return true;
3147}
3148
3149#define MAX_NESTED_LIBCALLS 9
3150
ae860ff7 3151static void
1d088dee 3152local_cprop_pass (int alter_jumps)
ae860ff7
JH
3153{
3154 rtx insn;
3155 struct reg_use *reg_used;
8ba46434 3156 rtx libcall_stack[MAX_NESTED_LIBCALLS + 1], *libcall_sp;
1649d92f 3157 bool changed = false;
ae860ff7 3158
463301c3 3159 cselib_init (false);
8ba46434
R
3160 libcall_sp = &libcall_stack[MAX_NESTED_LIBCALLS];
3161 *libcall_sp = 0;
ae860ff7
JH
3162 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
3163 {
3164 if (INSN_P (insn))
3165 {
8ba46434 3166 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
ae860ff7 3167
8ba46434
R
3168 if (note)
3169 {
282899df 3170 gcc_assert (libcall_sp != libcall_stack);
8ba46434
R
3171 *--libcall_sp = XEXP (note, 0);
3172 }
3173 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
3174 if (note)
3175 libcall_sp++;
3176 note = find_reg_equal_equiv_note (insn);
ae860ff7
JH
3177 do
3178 {
3179 reg_use_count = 0;
710ee3ed 3180 note_uses (&PATTERN (insn), local_cprop_find_used_regs, NULL);
ae860ff7 3181 if (note)
710ee3ed 3182 local_cprop_find_used_regs (&XEXP (note, 0), NULL);
ae860ff7
JH
3183
3184 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
3185 reg_used++, reg_use_count--)
8ba46434
R
3186 if (do_local_cprop (reg_used->reg_rtx, insn, alter_jumps,
3187 libcall_sp))
1649d92f
JH
3188 {
3189 changed = true;
3190 break;
3191 }
bc6688b4
RS
3192 if (INSN_DELETED_P (insn))
3193 break;
ae860ff7
JH
3194 }
3195 while (reg_use_count);
3196 }
3197 cselib_process_insn (insn);
3198 }
3199 cselib_finish ();
1649d92f
JH
3200 /* Global analysis may get into infinite loops for unreachable blocks. */
3201 if (changed && alter_jumps)
5f0bea72
JH
3202 {
3203 delete_unreachable_blocks ();
3204 free_reg_set_mem ();
3205 alloc_reg_set_mem (max_reg_num ());
3206 compute_sets (get_insns ());
3207 }
ae860ff7
JH
3208}
3209
c4c81601 3210/* Forward propagate copies. This includes copies and constants. Return
cc2902df 3211 nonzero if a change was made. */
7506f491
DE
3212
3213static int
1d088dee 3214cprop (int alter_jumps)
7506f491 3215{
e0082a72
ZD
3216 int changed;
3217 basic_block bb;
7506f491
DE
3218 rtx insn;
3219
3220 /* Note we start at block 1. */
e0082a72
ZD
3221 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
3222 {
3223 if (gcse_file != NULL)
3224 fprintf (gcse_file, "\n");
3225 return 0;
3226 }
7506f491
DE
3227
3228 changed = 0;
e0082a72 3229 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb, EXIT_BLOCK_PTR, next_bb)
7506f491
DE
3230 {
3231 /* Reset tables used to keep track of what's still valid [since the
3232 start of the block]. */
3233 reset_opr_set_tables ();
3234
a813c111
SB
3235 for (insn = BB_HEAD (bb);
3236 insn != NULL && insn != NEXT_INSN (BB_END (bb));
7506f491 3237 insn = NEXT_INSN (insn))
172890a2
RK
3238 if (INSN_P (insn))
3239 {
ae860ff7 3240 changed |= cprop_insn (insn, alter_jumps);
7506f491 3241
172890a2
RK
3242 /* Keep track of everything modified by this insn. */
3243 /* ??? Need to be careful w.r.t. mods done to INSN. Don't
3244 call mark_oprs_set if we turned the insn into a NOTE. */
7b1b4aed 3245 if (! NOTE_P (insn))
172890a2 3246 mark_oprs_set (insn);
8e42ace1 3247 }
7506f491
DE
3248 }
3249
3250 if (gcse_file != NULL)
3251 fprintf (gcse_file, "\n");
3252
3253 return changed;
3254}
3255
fbef91d8
RS
3256/* Similar to get_condition, only the resulting condition must be
3257 valid at JUMP, instead of at EARLIEST.
3258
3259 This differs from noce_get_condition in ifcvt.c in that we prefer not to
3260 settle for the condition variable in the jump instruction being integral.
3261 We prefer to be able to record the value of a user variable, rather than
3262 the value of a temporary used in a condition. This could be solved by
3263 recording the value of *every* register scaned by canonicalize_condition,
3264 but this would require some code reorganization. */
3265
2fa4a849 3266rtx
1d088dee 3267fis_get_condition (rtx jump)
fbef91d8 3268{
45d09c02 3269 return get_condition (jump, NULL, false, true);
fbef91d8
RS
3270}
3271
b0656d8b
JW
3272/* Check the comparison COND to see if we can safely form an implicit set from
3273 it. COND is either an EQ or NE comparison. */
3274
3275static bool
3276implicit_set_cond_p (rtx cond)
3277{
3278 enum machine_mode mode = GET_MODE (XEXP (cond, 0));
3279 rtx cst = XEXP (cond, 1);
3280
3281 /* We can't perform this optimization if either operand might be or might
3282 contain a signed zero. */
3283 if (HONOR_SIGNED_ZEROS (mode))
3284 {
3285 /* It is sufficient to check if CST is or contains a zero. We must
3286 handle float, complex, and vector. If any subpart is a zero, then
3287 the optimization can't be performed. */
3288 /* ??? The complex and vector checks are not implemented yet. We just
3289 always return zero for them. */
3290 if (GET_CODE (cst) == CONST_DOUBLE)
3291 {
3292 REAL_VALUE_TYPE d;
3293 REAL_VALUE_FROM_CONST_DOUBLE (d, cst);
3294 if (REAL_VALUES_EQUAL (d, dconst0))
3295 return 0;
3296 }
3297 else
3298 return 0;
3299 }
3300
3301 return gcse_constant_p (cst);
3302}
3303
fbef91d8
RS
3304/* Find the implicit sets of a function. An "implicit set" is a constraint
3305 on the value of a variable, implied by a conditional jump. For example,
3306 following "if (x == 2)", the then branch may be optimized as though the
3307 conditional performed an "explicit set", in this example, "x = 2". This
3308 function records the set patterns that are implicit at the start of each
3309 basic block. */
3310
3311static void
1d088dee 3312find_implicit_sets (void)
fbef91d8
RS
3313{
3314 basic_block bb, dest;
3315 unsigned int count;
3316 rtx cond, new;
3317
3318 count = 0;
3319 FOR_EACH_BB (bb)
a98ebe2e 3320 /* Check for more than one successor. */
628f6a4e 3321 if (EDGE_COUNT (bb->succs) > 1)
fbef91d8 3322 {
a813c111 3323 cond = fis_get_condition (BB_END (bb));
fbef91d8
RS
3324
3325 if (cond
3326 && (GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7b1b4aed 3327 && REG_P (XEXP (cond, 0))
fbef91d8 3328 && REGNO (XEXP (cond, 0)) >= FIRST_PSEUDO_REGISTER
b0656d8b 3329 && implicit_set_cond_p (cond))
fbef91d8
RS
3330 {
3331 dest = GET_CODE (cond) == EQ ? BRANCH_EDGE (bb)->dest
3332 : FALLTHRU_EDGE (bb)->dest;
3333
628f6a4e 3334 if (dest && EDGE_COUNT (dest->preds) == 1
fbef91d8
RS
3335 && dest != EXIT_BLOCK_PTR)
3336 {
3337 new = gen_rtx_SET (VOIDmode, XEXP (cond, 0),
3338 XEXP (cond, 1));
3339 implicit_sets[dest->index] = new;
3340 if (gcse_file)
3341 {
3342 fprintf(gcse_file, "Implicit set of reg %d in ",
3343 REGNO (XEXP (cond, 0)));
3344 fprintf(gcse_file, "basic block %d\n", dest->index);
3345 }
3346 count++;
3347 }
3348 }
3349 }
3350
3351 if (gcse_file)
3352 fprintf (gcse_file, "Found %d implicit sets\n", count);
3353}
3354
7506f491 3355/* Perform one copy/constant propagation pass.
a0134312
RS
3356 PASS is the pass count. If CPROP_JUMPS is true, perform constant
3357 propagation into conditional jumps. If BYPASS_JUMPS is true,
3358 perform conditional jump bypassing optimizations. */
7506f491
DE
3359
3360static int
1d088dee 3361one_cprop_pass (int pass, int cprop_jumps, int bypass_jumps)
7506f491
DE
3362{
3363 int changed = 0;
3364
27fb79ad
SB
3365 global_const_prop_count = local_const_prop_count = 0;
3366 global_copy_prop_count = local_copy_prop_count = 0;
7506f491 3367
a0134312 3368 local_cprop_pass (cprop_jumps);
ae860ff7 3369
fbef91d8 3370 /* Determine implicit sets. */
703ad42b 3371 implicit_sets = xcalloc (last_basic_block, sizeof (rtx));
fbef91d8
RS
3372 find_implicit_sets ();
3373
02280659
ZD
3374 alloc_hash_table (max_cuid, &set_hash_table, 1);
3375 compute_hash_table (&set_hash_table);
fbef91d8
RS
3376
3377 /* Free implicit_sets before peak usage. */
3378 free (implicit_sets);
3379 implicit_sets = NULL;
3380
7506f491 3381 if (gcse_file)
02280659
ZD
3382 dump_hash_table (gcse_file, "SET", &set_hash_table);
3383 if (set_hash_table.n_elems > 0)
7506f491 3384 {
02280659 3385 alloc_cprop_mem (last_basic_block, set_hash_table.n_elems);
7506f491 3386 compute_cprop_data ();
a0134312
RS
3387 changed = cprop (cprop_jumps);
3388 if (bypass_jumps)
0e3f0221 3389 changed |= bypass_conditional_jumps ();
7506f491
DE
3390 free_cprop_mem ();
3391 }
c4c81601 3392
02280659 3393 free_hash_table (&set_hash_table);
7506f491
DE
3394
3395 if (gcse_file)
3396 {
c4c81601 3397 fprintf (gcse_file, "CPROP of %s, pass %d: %d bytes needed, ",
faed5cc3 3398 current_function_name (), pass, bytes_used);
27fb79ad
SB
3399 fprintf (gcse_file, "%d local const props, %d local copy props\n\n",
3400 local_const_prop_count, local_copy_prop_count);
3401 fprintf (gcse_file, "%d global const props, %d global copy props\n\n",
3402 global_const_prop_count, global_copy_prop_count);
7506f491 3403 }
1649d92f
JH
3404 /* Global analysis may get into infinite loops for unreachable blocks. */
3405 if (changed && cprop_jumps)
3406 delete_unreachable_blocks ();
7506f491
DE
3407
3408 return changed;
3409}
3410\f
0e3f0221
RS
3411/* Bypass conditional jumps. */
3412
7821bfc7
RS
3413/* The value of last_basic_block at the beginning of the jump_bypass
3414 pass. The use of redirect_edge_and_branch_force may introduce new
3415 basic blocks, but the data flow analysis is only valid for basic
3416 block indices less than bypass_last_basic_block. */
3417
3418static int bypass_last_basic_block;
3419
0e3f0221
RS
3420/* Find a set of REGNO to a constant that is available at the end of basic
3421 block BB. Returns NULL if no such set is found. Based heavily upon
3422 find_avail_set. */
3423
3424static struct expr *
1d088dee 3425find_bypass_set (int regno, int bb)
0e3f0221
RS
3426{
3427 struct expr *result = 0;
3428
3429 for (;;)
3430 {
3431 rtx src;
ceda50e9 3432 struct expr *set = lookup_set (regno, &set_hash_table);
0e3f0221
RS
3433
3434 while (set)
3435 {
3436 if (TEST_BIT (cprop_avout[bb], set->bitmap_index))
3437 break;
3438 set = next_set (regno, set);
3439 }
3440
3441 if (set == 0)
3442 break;
3443
282899df 3444 gcc_assert (GET_CODE (set->expr) == SET);
0e3f0221
RS
3445
3446 src = SET_SRC (set->expr);
6b2d1c9e 3447 if (gcse_constant_p (src))
0e3f0221
RS
3448 result = set;
3449
7b1b4aed 3450 if (! REG_P (src))
0e3f0221
RS
3451 break;
3452
3453 regno = REGNO (src);
3454 }
3455 return result;
3456}
3457
3458
e129b3f9
RS
3459/* Subroutine of bypass_block that checks whether a pseudo is killed by
3460 any of the instructions inserted on an edge. Jump bypassing places
3461 condition code setters on CFG edges using insert_insn_on_edge. This
3462 function is required to check that our data flow analysis is still
3463 valid prior to commit_edge_insertions. */
3464
3465static bool
1d088dee 3466reg_killed_on_edge (rtx reg, edge e)
e129b3f9
RS
3467{
3468 rtx insn;
3469
6de9cd9a 3470 for (insn = e->insns.r; insn; insn = NEXT_INSN (insn))
e129b3f9
RS
3471 if (INSN_P (insn) && reg_set_p (reg, insn))
3472 return true;
3473
3474 return false;
3475}
3476
0e3f0221
RS
3477/* Subroutine of bypass_conditional_jumps that attempts to bypass the given
3478 basic block BB which has more than one predecessor. If not NULL, SETCC
3479 is the first instruction of BB, which is immediately followed by JUMP_INSN
3480 JUMP. Otherwise, SETCC is NULL, and JUMP is the first insn of BB.
e129b3f9
RS
3481 Returns nonzero if a change was made.
3482
e0bb17a8 3483 During the jump bypassing pass, we may place copies of SETCC instructions
e129b3f9
RS
3484 on CFG edges. The following routine must be careful to pay attention to
3485 these inserted insns when performing its transformations. */
0e3f0221
RS
3486
3487static int
1d088dee 3488bypass_block (basic_block bb, rtx setcc, rtx jump)
0e3f0221
RS
3489{
3490 rtx insn, note;
628f6a4e 3491 edge e, edest;
818b6b7f 3492 int i, change;
72b8d451 3493 int may_be_loop_header;
628f6a4e
BE
3494 unsigned removed_p;
3495 edge_iterator ei;
0e3f0221
RS
3496
3497 insn = (setcc != NULL) ? setcc : jump;
3498
3499 /* Determine set of register uses in INSN. */
3500 reg_use_count = 0;
3501 note_uses (&PATTERN (insn), find_used_regs, NULL);
3502 note = find_reg_equal_equiv_note (insn);
3503 if (note)
3504 find_used_regs (&XEXP (note, 0), NULL);
3505
72b8d451 3506 may_be_loop_header = false;
628f6a4e 3507 FOR_EACH_EDGE (e, ei, bb->preds)
72b8d451
ZD
3508 if (e->flags & EDGE_DFS_BACK)
3509 {
3510 may_be_loop_header = true;
3511 break;
3512 }
3513
0e3f0221 3514 change = 0;
628f6a4e 3515 for (ei = ei_start (bb->preds); (e = ei_safe_edge (ei)); )
0e3f0221 3516 {
628f6a4e
BE
3517 removed_p = 0;
3518
7821bfc7 3519 if (e->flags & EDGE_COMPLEX)
628f6a4e
BE
3520 {
3521 ei_next (&ei);
3522 continue;
3523 }
7821bfc7
RS
3524
3525 /* We can't redirect edges from new basic blocks. */
3526 if (e->src->index >= bypass_last_basic_block)
628f6a4e
BE
3527 {
3528 ei_next (&ei);
3529 continue;
3530 }
7821bfc7 3531
72b8d451 3532 /* The irreducible loops created by redirecting of edges entering the
e0bb17a8
KH
3533 loop from outside would decrease effectiveness of some of the following
3534 optimizations, so prevent this. */
72b8d451
ZD
3535 if (may_be_loop_header
3536 && !(e->flags & EDGE_DFS_BACK))
628f6a4e
BE
3537 {
3538 ei_next (&ei);
3539 continue;
3540 }
72b8d451 3541
0e3f0221
RS
3542 for (i = 0; i < reg_use_count; i++)
3543 {
3544 struct reg_use *reg_used = &reg_use_table[i];
589005ff 3545 unsigned int regno = REGNO (reg_used->reg_rtx);
818b6b7f 3546 basic_block dest, old_dest;
589005ff
KH
3547 struct expr *set;
3548 rtx src, new;
0e3f0221 3549
589005ff
KH
3550 if (regno >= max_gcse_regno)
3551 continue;
0e3f0221 3552
589005ff 3553 set = find_bypass_set (regno, e->src->index);
0e3f0221
RS
3554
3555 if (! set)
3556 continue;
3557
e129b3f9 3558 /* Check the data flow is valid after edge insertions. */
6de9cd9a 3559 if (e->insns.r && reg_killed_on_edge (reg_used->reg_rtx, e))
e129b3f9
RS
3560 continue;
3561
589005ff 3562 src = SET_SRC (pc_set (jump));
0e3f0221
RS
3563
3564 if (setcc != NULL)
3565 src = simplify_replace_rtx (src,
589005ff
KH
3566 SET_DEST (PATTERN (setcc)),
3567 SET_SRC (PATTERN (setcc)));
0e3f0221
RS
3568
3569 new = simplify_replace_rtx (src, reg_used->reg_rtx,
589005ff 3570 SET_SRC (set->expr));
0e3f0221 3571
1d088dee 3572 /* Jump bypassing may have already placed instructions on
e129b3f9
RS
3573 edges of the CFG. We can't bypass an outgoing edge that
3574 has instructions associated with it, as these insns won't
3575 get executed if the incoming edge is redirected. */
3576
589005ff 3577 if (new == pc_rtx)
e129b3f9
RS
3578 {
3579 edest = FALLTHRU_EDGE (bb);
6de9cd9a 3580 dest = edest->insns.r ? NULL : edest->dest;
e129b3f9 3581 }
0e3f0221 3582 else if (GET_CODE (new) == LABEL_REF)
e129b3f9
RS
3583 {
3584 dest = BLOCK_FOR_INSN (XEXP (new, 0));
3585 /* Don't bypass edges containing instructions. */
c7d1b449
KH
3586 edest = find_edge (bb, dest);
3587 if (edest && edest->insns.r)
3588 dest = NULL;
e129b3f9 3589 }
0e3f0221
RS
3590 else
3591 dest = NULL;
3592
a544524a
JH
3593 /* Avoid unification of the edge with other edges from original
3594 branch. We would end up emitting the instruction on "both"
3595 edges. */
7b1b4aed 3596
c7d1b449
KH
3597 if (dest && setcc && !CC0_P (SET_DEST (PATTERN (setcc)))
3598 && find_edge (e->src, dest))
3599 dest = NULL;
a544524a 3600
818b6b7f 3601 old_dest = e->dest;
7821bfc7
RS
3602 if (dest != NULL
3603 && dest != old_dest
3604 && dest != EXIT_BLOCK_PTR)
3605 {
3606 redirect_edge_and_branch_force (e, dest);
3607
818b6b7f 3608 /* Copy the register setter to the redirected edge.
0e3f0221
RS
3609 Don't copy CC0 setters, as CC0 is dead after jump. */
3610 if (setcc)
3611 {
3612 rtx pat = PATTERN (setcc);
818b6b7f 3613 if (!CC0_P (SET_DEST (pat)))
0e3f0221
RS
3614 insert_insn_on_edge (copy_insn (pat), e);
3615 }
3616
3617 if (gcse_file != NULL)
3618 {
27fb79ad
SB
3619 fprintf (gcse_file, "JUMP-BYPASS: Proved reg %d "
3620 "in jump_insn %d equals constant ",
818b6b7f 3621 regno, INSN_UID (jump));
0e3f0221
RS
3622 print_rtl (gcse_file, SET_SRC (set->expr));
3623 fprintf (gcse_file, "\nBypass edge from %d->%d to %d\n",
818b6b7f 3624 e->src->index, old_dest->index, dest->index);
0e3f0221
RS
3625 }
3626 change = 1;
628f6a4e 3627 removed_p = 1;
0e3f0221
RS
3628 break;
3629 }
3630 }
628f6a4e
BE
3631 if (!removed_p)
3632 ei_next (&ei);
0e3f0221
RS
3633 }
3634 return change;
3635}
3636
3637/* Find basic blocks with more than one predecessor that only contain a
3638 single conditional jump. If the result of the comparison is known at
3639 compile-time from any incoming edge, redirect that edge to the
9a71ece1
RH
3640 appropriate target. Returns nonzero if a change was made.
3641
3642 This function is now mis-named, because we also handle indirect jumps. */
0e3f0221
RS
3643
3644static int
1d088dee 3645bypass_conditional_jumps (void)
0e3f0221
RS
3646{
3647 basic_block bb;
3648 int changed;
3649 rtx setcc;
3650 rtx insn;
3651 rtx dest;
3652
3653 /* Note we start at block 1. */
3654 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
3655 return 0;
3656
7821bfc7 3657 bypass_last_basic_block = last_basic_block;
72b8d451 3658 mark_dfs_back_edges ();
7821bfc7 3659
0e3f0221
RS
3660 changed = 0;
3661 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb,
589005ff 3662 EXIT_BLOCK_PTR, next_bb)
0e3f0221
RS
3663 {
3664 /* Check for more than one predecessor. */
628f6a4e 3665 if (EDGE_COUNT (bb->preds) > 1)
0e3f0221
RS
3666 {
3667 setcc = NULL_RTX;
a813c111
SB
3668 for (insn = BB_HEAD (bb);
3669 insn != NULL && insn != NEXT_INSN (BB_END (bb));
0e3f0221 3670 insn = NEXT_INSN (insn))
4b4bf941 3671 if (NONJUMP_INSN_P (insn))
0e3f0221 3672 {
9543a9d2 3673 if (setcc)
0e3f0221 3674 break;
ba4f7968 3675 if (GET_CODE (PATTERN (insn)) != SET)
0e3f0221
RS
3676 break;
3677
ba4f7968 3678 dest = SET_DEST (PATTERN (insn));
818b6b7f 3679 if (REG_P (dest) || CC0_P (dest))
0e3f0221 3680 setcc = insn;
0e3f0221
RS
3681 else
3682 break;
3683 }
7b1b4aed 3684 else if (JUMP_P (insn))
0e3f0221 3685 {
9a71ece1
RH
3686 if ((any_condjump_p (insn) || computed_jump_p (insn))
3687 && onlyjump_p (insn))
0e3f0221
RS
3688 changed |= bypass_block (bb, setcc, insn);
3689 break;
3690 }
3691 else if (INSN_P (insn))
3692 break;
3693 }
3694 }
3695
818b6b7f 3696 /* If we bypassed any register setting insns, we inserted a
fbe5a4a6 3697 copy on the redirected edge. These need to be committed. */
0e3f0221
RS
3698 if (changed)
3699 commit_edge_insertions();
3700
3701 return changed;
3702}
3703\f
a65f3558 3704/* Compute PRE+LCM working variables. */
7506f491
DE
3705
3706/* Local properties of expressions. */
3707/* Nonzero for expressions that are transparent in the block. */
a65f3558 3708static sbitmap *transp;
7506f491 3709
5c35539b
RH
3710/* Nonzero for expressions that are transparent at the end of the block.
3711 This is only zero for expressions killed by abnormal critical edge
3712 created by a calls. */
a65f3558 3713static sbitmap *transpout;
5c35539b 3714
a65f3558
JL
3715/* Nonzero for expressions that are computed (available) in the block. */
3716static sbitmap *comp;
7506f491 3717
a65f3558
JL
3718/* Nonzero for expressions that are locally anticipatable in the block. */
3719static sbitmap *antloc;
7506f491 3720
a65f3558
JL
3721/* Nonzero for expressions where this block is an optimal computation
3722 point. */
3723static sbitmap *pre_optimal;
5c35539b 3724
a65f3558
JL
3725/* Nonzero for expressions which are redundant in a particular block. */
3726static sbitmap *pre_redundant;
7506f491 3727
a42cd965
AM
3728/* Nonzero for expressions which should be inserted on a specific edge. */
3729static sbitmap *pre_insert_map;
3730
3731/* Nonzero for expressions which should be deleted in a specific block. */
3732static sbitmap *pre_delete_map;
3733
3734/* Contains the edge_list returned by pre_edge_lcm. */
3735static struct edge_list *edge_list;
3736
a65f3558
JL
3737/* Redundant insns. */
3738static sbitmap pre_redundant_insns;
7506f491 3739
a65f3558 3740/* Allocate vars used for PRE analysis. */
7506f491
DE
3741
3742static void
1d088dee 3743alloc_pre_mem (int n_blocks, int n_exprs)
7506f491 3744{
a65f3558
JL
3745 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
3746 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
3747 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5faf03ae 3748
a42cd965
AM
3749 pre_optimal = NULL;
3750 pre_redundant = NULL;
3751 pre_insert_map = NULL;
3752 pre_delete_map = NULL;
a42cd965 3753 ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs);
c4c81601 3754
a42cd965 3755 /* pre_insert and pre_delete are allocated later. */
7506f491
DE
3756}
3757
a65f3558 3758/* Free vars used for PRE analysis. */
7506f491
DE
3759
3760static void
1d088dee 3761free_pre_mem (void)
7506f491 3762{
5a660bff
DB
3763 sbitmap_vector_free (transp);
3764 sbitmap_vector_free (comp);
bd3675fc
JL
3765
3766 /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */
7506f491 3767
a42cd965 3768 if (pre_optimal)
5a660bff 3769 sbitmap_vector_free (pre_optimal);
a42cd965 3770 if (pre_redundant)
5a660bff 3771 sbitmap_vector_free (pre_redundant);
a42cd965 3772 if (pre_insert_map)
5a660bff 3773 sbitmap_vector_free (pre_insert_map);
a42cd965 3774 if (pre_delete_map)
5a660bff 3775 sbitmap_vector_free (pre_delete_map);
a42cd965 3776
bd3675fc 3777 transp = comp = NULL;
a42cd965 3778 pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL;
7506f491
DE
3779}
3780
3781/* Top level routine to do the dataflow analysis needed by PRE. */
3782
3783static void
1d088dee 3784compute_pre_data (void)
7506f491 3785{
b614171e 3786 sbitmap trapping_expr;
e0082a72 3787 basic_block bb;
b614171e 3788 unsigned int ui;
c66e8ae9 3789
02280659 3790 compute_local_properties (transp, comp, antloc, &expr_hash_table);
d55bc081 3791 sbitmap_vector_zero (ae_kill, last_basic_block);
c66e8ae9 3792
b614171e 3793 /* Collect expressions which might trap. */
02280659 3794 trapping_expr = sbitmap_alloc (expr_hash_table.n_elems);
b614171e 3795 sbitmap_zero (trapping_expr);
02280659 3796 for (ui = 0; ui < expr_hash_table.size; ui++)
b614171e
MM
3797 {
3798 struct expr *e;
02280659 3799 for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash)
b614171e
MM
3800 if (may_trap_p (e->expr))
3801 SET_BIT (trapping_expr, e->bitmap_index);
3802 }
3803
c66e8ae9
JL
3804 /* Compute ae_kill for each basic block using:
3805
3806 ~(TRANSP | COMP)
e83f4801 3807 */
c66e8ae9 3808
e0082a72 3809 FOR_EACH_BB (bb)
c66e8ae9 3810 {
b614171e 3811 edge e;
628f6a4e 3812 edge_iterator ei;
b614171e
MM
3813
3814 /* If the current block is the destination of an abnormal edge, we
3815 kill all trapping expressions because we won't be able to properly
3816 place the instruction on the edge. So make them neither
3817 anticipatable nor transparent. This is fairly conservative. */
628f6a4e 3818 FOR_EACH_EDGE (e, ei, bb->preds)
b614171e
MM
3819 if (e->flags & EDGE_ABNORMAL)
3820 {
e0082a72
ZD
3821 sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr);
3822 sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr);
b614171e
MM
3823 break;
3824 }
3825
e0082a72
ZD
3826 sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]);
3827 sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]);
c66e8ae9
JL
3828 }
3829
02280659 3830 edge_list = pre_edge_lcm (gcse_file, expr_hash_table.n_elems, transp, comp, antloc,
a42cd965 3831 ae_kill, &pre_insert_map, &pre_delete_map);
5a660bff 3832 sbitmap_vector_free (antloc);
bd3675fc 3833 antloc = NULL;
5a660bff 3834 sbitmap_vector_free (ae_kill);
589005ff 3835 ae_kill = NULL;
76ac938b 3836 sbitmap_free (trapping_expr);
7506f491
DE
3837}
3838\f
3839/* PRE utilities */
3840
cc2902df 3841/* Return nonzero if an occurrence of expression EXPR in OCCR_BB would reach
a65f3558 3842 block BB.
7506f491
DE
3843
3844 VISITED is a pointer to a working buffer for tracking which BB's have
3845 been visited. It is NULL for the top-level call.
3846
3847 We treat reaching expressions that go through blocks containing the same
3848 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
3849 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
3850 2 as not reaching. The intent is to improve the probability of finding
3851 only one reaching expression and to reduce register lifetimes by picking
3852 the closest such expression. */
3853
3854static int
1d088dee 3855pre_expr_reaches_here_p_work (basic_block occr_bb, struct expr *expr, basic_block bb, char *visited)
7506f491 3856{
36349f8b 3857 edge pred;
628f6a4e
BE
3858 edge_iterator ei;
3859
3860 FOR_EACH_EDGE (pred, ei, bb->preds)
7506f491 3861 {
e2d2ed72 3862 basic_block pred_bb = pred->src;
7506f491 3863
36349f8b 3864 if (pred->src == ENTRY_BLOCK_PTR
7506f491 3865 /* Has predecessor has already been visited? */
0b17ab2f 3866 || visited[pred_bb->index])
c4c81601
RK
3867 ;/* Nothing to do. */
3868
7506f491 3869 /* Does this predecessor generate this expression? */
0b17ab2f 3870 else if (TEST_BIT (comp[pred_bb->index], expr->bitmap_index))
7506f491
DE
3871 {
3872 /* Is this the occurrence we're looking for?
3873 Note that there's only one generating occurrence per block
3874 so we just need to check the block number. */
a65f3558 3875 if (occr_bb == pred_bb)
7506f491 3876 return 1;
c4c81601 3877
0b17ab2f 3878 visited[pred_bb->index] = 1;
7506f491
DE
3879 }
3880 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
3881 else if (! TEST_BIT (transp[pred_bb->index], expr->bitmap_index))
3882 visited[pred_bb->index] = 1;
c4c81601 3883
7506f491
DE
3884 /* Neither gen nor kill. */
3885 else
ac7c5af5 3886 {
0b17ab2f 3887 visited[pred_bb->index] = 1;
89e606c9 3888 if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited))
7506f491 3889 return 1;
ac7c5af5 3890 }
7506f491
DE
3891 }
3892
3893 /* All paths have been checked. */
3894 return 0;
3895}
283a2545
RL
3896
3897/* The wrapper for pre_expr_reaches_here_work that ensures that any
dc297297 3898 memory allocated for that function is returned. */
283a2545
RL
3899
3900static int
1d088dee 3901pre_expr_reaches_here_p (basic_block occr_bb, struct expr *expr, basic_block bb)
283a2545
RL
3902{
3903 int rval;
703ad42b 3904 char *visited = xcalloc (last_basic_block, 1);
283a2545 3905
8e42ace1 3906 rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited);
283a2545
RL
3907
3908 free (visited);
c4c81601 3909 return rval;
283a2545 3910}
7506f491 3911\f
a42cd965
AM
3912
3913/* Given an expr, generate RTL which we can insert at the end of a BB,
589005ff 3914 or on an edge. Set the block number of any insns generated to
a42cd965
AM
3915 the value of BB. */
3916
3917static rtx
1d088dee 3918process_insert_insn (struct expr *expr)
a42cd965
AM
3919{
3920 rtx reg = expr->reaching_reg;
fb0c0a12
RK
3921 rtx exp = copy_rtx (expr->expr);
3922 rtx pat;
a42cd965
AM
3923
3924 start_sequence ();
fb0c0a12
RK
3925
3926 /* If the expression is something that's an operand, like a constant,
3927 just copy it to a register. */
3928 if (general_operand (exp, GET_MODE (reg)))
3929 emit_move_insn (reg, exp);
3930
3931 /* Otherwise, make a new insn to compute this expression and make sure the
3932 insn will be recognized (this also adds any needed CLOBBERs). Copy the
3933 expression to make sure we don't have any sharing issues. */
282899df
NS
3934 else
3935 {
3936 rtx insn = emit_insn (gen_rtx_SET (VOIDmode, reg, exp));
3937
2f021b67
AP
3938 if (insn_invalid_p (insn))
3939 gcc_unreachable ();
282899df
NS
3940 }
3941
589005ff 3942
2f937369 3943 pat = get_insns ();
a42cd965
AM
3944 end_sequence ();
3945
3946 return pat;
3947}
589005ff 3948
a65f3558
JL
3949/* Add EXPR to the end of basic block BB.
3950
3951 This is used by both the PRE and code hoisting.
3952
3953 For PRE, we want to verify that the expr is either transparent
3954 or locally anticipatable in the target block. This check makes
3955 no sense for code hoisting. */
7506f491
DE
3956
3957static void
1d088dee 3958insert_insn_end_bb (struct expr *expr, basic_block bb, int pre)
7506f491 3959{
a813c111 3960 rtx insn = BB_END (bb);
7506f491
DE
3961 rtx new_insn;
3962 rtx reg = expr->reaching_reg;
3963 int regno = REGNO (reg);
2f937369 3964 rtx pat, pat_end;
7506f491 3965
a42cd965 3966 pat = process_insert_insn (expr);
282899df 3967 gcc_assert (pat && INSN_P (pat));
2f937369
DM
3968
3969 pat_end = pat;
3970 while (NEXT_INSN (pat_end) != NULL_RTX)
3971 pat_end = NEXT_INSN (pat_end);
7506f491
DE
3972
3973 /* If the last insn is a jump, insert EXPR in front [taking care to
4d6922ee 3974 handle cc0, etc. properly]. Similarly we need to care trapping
068473ec 3975 instructions in presence of non-call exceptions. */
7506f491 3976
7b1b4aed 3977 if (JUMP_P (insn)
4b4bf941 3978 || (NONJUMP_INSN_P (insn)
628f6a4e
BE
3979 && (EDGE_COUNT (bb->succs) > 1
3980 || EDGE_SUCC (bb, 0)->flags & EDGE_ABNORMAL)))
7506f491 3981 {
50b2596f 3982#ifdef HAVE_cc0
7506f491 3983 rtx note;
50b2596f 3984#endif
068473ec
JH
3985 /* It should always be the case that we can put these instructions
3986 anywhere in the basic block with performing PRE optimizations.
3987 Check this. */
282899df
NS
3988 gcc_assert (!NONJUMP_INSN_P (insn) || !pre
3989 || TEST_BIT (antloc[bb->index], expr->bitmap_index)
3990 || TEST_BIT (transp[bb->index], expr->bitmap_index));
7506f491
DE
3991
3992 /* If this is a jump table, then we can't insert stuff here. Since
3993 we know the previous real insn must be the tablejump, we insert
3994 the new instruction just before the tablejump. */
3995 if (GET_CODE (PATTERN (insn)) == ADDR_VEC
3996 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3997 insn = prev_real_insn (insn);
3998
3999#ifdef HAVE_cc0
4000 /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts
4001 if cc0 isn't set. */
4002 note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
4003 if (note)
4004 insn = XEXP (note, 0);
4005 else
4006 {
4007 rtx maybe_cc0_setter = prev_nonnote_insn (insn);
4008 if (maybe_cc0_setter
2c3c49de 4009 && INSN_P (maybe_cc0_setter)
7506f491
DE
4010 && sets_cc0_p (PATTERN (maybe_cc0_setter)))
4011 insn = maybe_cc0_setter;
4012 }
4013#endif
4014 /* FIXME: What if something in cc0/jump uses value set in new insn? */
a7102479 4015 new_insn = emit_insn_before_noloc (pat, insn);
3947e2f9 4016 }
c4c81601 4017
3947e2f9
RH
4018 /* Likewise if the last insn is a call, as will happen in the presence
4019 of exception handling. */
7b1b4aed 4020 else if (CALL_P (insn)
628f6a4e 4021 && (EDGE_COUNT (bb->succs) > 1 || EDGE_SUCC (bb, 0)->flags & EDGE_ABNORMAL))
3947e2f9 4022 {
3947e2f9
RH
4023 /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers,
4024 we search backward and place the instructions before the first
4025 parameter is loaded. Do this for everyone for consistency and a
fbe5a4a6 4026 presumption that we'll get better code elsewhere as well.
3947e2f9 4027
c4c81601 4028 It should always be the case that we can put these instructions
a65f3558
JL
4029 anywhere in the basic block with performing PRE optimizations.
4030 Check this. */
c4c81601 4031
282899df
NS
4032 gcc_assert (!pre
4033 || TEST_BIT (antloc[bb->index], expr->bitmap_index)
4034 || TEST_BIT (transp[bb->index], expr->bitmap_index));
3947e2f9
RH
4035
4036 /* Since different machines initialize their parameter registers
4037 in different orders, assume nothing. Collect the set of all
4038 parameter registers. */
a813c111 4039 insn = find_first_parameter_load (insn, BB_HEAD (bb));
3947e2f9 4040
b1d26727
JL
4041 /* If we found all the parameter loads, then we want to insert
4042 before the first parameter load.
4043
4044 If we did not find all the parameter loads, then we might have
4045 stopped on the head of the block, which could be a CODE_LABEL.
4046 If we inserted before the CODE_LABEL, then we would be putting
4047 the insn in the wrong basic block. In that case, put the insn
b5229628 4048 after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */
7b1b4aed 4049 while (LABEL_P (insn)
589ca5cb 4050 || NOTE_INSN_BASIC_BLOCK_P (insn))
b5229628 4051 insn = NEXT_INSN (insn);
c4c81601 4052
a7102479 4053 new_insn = emit_insn_before_noloc (pat, insn);
7506f491
DE
4054 }
4055 else
a7102479 4056 new_insn = emit_insn_after_noloc (pat, insn);
7506f491 4057
2f937369 4058 while (1)
a65f3558 4059 {
2f937369 4060 if (INSN_P (pat))
a65f3558 4061 {
2f937369
DM
4062 add_label_notes (PATTERN (pat), new_insn);
4063 note_stores (PATTERN (pat), record_set_info, pat);
a65f3558 4064 }
2f937369
DM
4065 if (pat == pat_end)
4066 break;
4067 pat = NEXT_INSN (pat);
a65f3558 4068 }
3947e2f9 4069
7506f491
DE
4070 gcse_create_count++;
4071
4072 if (gcse_file)
4073 {
c4c81601 4074 fprintf (gcse_file, "PRE/HOIST: end of bb %d, insn %d, ",
0b17ab2f 4075 bb->index, INSN_UID (new_insn));
c4c81601
RK
4076 fprintf (gcse_file, "copying expression %d to reg %d\n",
4077 expr->bitmap_index, regno);
7506f491
DE
4078 }
4079}
4080
a42cd965
AM
4081/* Insert partially redundant expressions on edges in the CFG to make
4082 the expressions fully redundant. */
7506f491 4083
a42cd965 4084static int
1d088dee 4085pre_edge_insert (struct edge_list *edge_list, struct expr **index_map)
7506f491 4086{
c4c81601 4087 int e, i, j, num_edges, set_size, did_insert = 0;
a65f3558
JL
4088 sbitmap *inserted;
4089
a42cd965
AM
4090 /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge
4091 if it reaches any of the deleted expressions. */
7506f491 4092
a42cd965
AM
4093 set_size = pre_insert_map[0]->size;
4094 num_edges = NUM_EDGES (edge_list);
02280659 4095 inserted = sbitmap_vector_alloc (num_edges, expr_hash_table.n_elems);
a42cd965 4096 sbitmap_vector_zero (inserted, num_edges);
7506f491 4097
a42cd965 4098 for (e = 0; e < num_edges; e++)
7506f491
DE
4099 {
4100 int indx;
e2d2ed72 4101 basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e);
a65f3558 4102
a65f3558 4103 for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS)
7506f491 4104 {
a42cd965 4105 SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i];
7506f491 4106
02280659 4107 for (j = indx; insert && j < (int) expr_hash_table.n_elems; j++, insert >>= 1)
c4c81601
RK
4108 if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX)
4109 {
4110 struct expr *expr = index_map[j];
4111 struct occr *occr;
a65f3558 4112
ff7cc307 4113 /* Now look at each deleted occurrence of this expression. */
c4c81601
RK
4114 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4115 {
4116 if (! occr->deleted_p)
4117 continue;
4118
3f117656 4119 /* Insert this expression on this edge if it would
ff7cc307 4120 reach the deleted occurrence in BB. */
c4c81601
RK
4121 if (!TEST_BIT (inserted[e], j))
4122 {
4123 rtx insn;
4124 edge eg = INDEX_EDGE (edge_list, e);
4125
4126 /* We can't insert anything on an abnormal and
4127 critical edge, so we insert the insn at the end of
4128 the previous block. There are several alternatives
4129 detailed in Morgans book P277 (sec 10.5) for
4130 handling this situation. This one is easiest for
4131 now. */
4132
b16aa8a5 4133 if (eg->flags & EDGE_ABNORMAL)
c4c81601
RK
4134 insert_insn_end_bb (index_map[j], bb, 0);
4135 else
4136 {
4137 insn = process_insert_insn (index_map[j]);
4138 insert_insn_on_edge (insn, eg);
4139 }
4140
4141 if (gcse_file)
4142 {
4143 fprintf (gcse_file, "PRE/HOIST: edge (%d,%d), ",
0b17ab2f
RH
4144 bb->index,
4145 INDEX_EDGE_SUCC_BB (edge_list, e)->index);
c4c81601
RK
4146 fprintf (gcse_file, "copy expression %d\n",
4147 expr->bitmap_index);
4148 }
4149
a13d4ebf 4150 update_ld_motion_stores (expr);
c4c81601
RK
4151 SET_BIT (inserted[e], j);
4152 did_insert = 1;
4153 gcse_create_count++;
4154 }
4155 }
4156 }
7506f491
DE
4157 }
4158 }
5faf03ae 4159
5a660bff 4160 sbitmap_vector_free (inserted);
a42cd965 4161 return did_insert;
7506f491
DE
4162}
4163
073089a7 4164/* Copy the result of EXPR->EXPR generated by INSN to EXPR->REACHING_REG.
b885908b
MH
4165 Given "old_reg <- expr" (INSN), instead of adding after it
4166 reaching_reg <- old_reg
4167 it's better to do the following:
4168 reaching_reg <- expr
4169 old_reg <- reaching_reg
4170 because this way copy propagation can discover additional PRE
f5f2e3cd
MH
4171 opportunities. But if this fails, we try the old way.
4172 When "expr" is a store, i.e.
4173 given "MEM <- old_reg", instead of adding after it
4174 reaching_reg <- old_reg
4175 it's better to add it before as follows:
4176 reaching_reg <- old_reg
4177 MEM <- reaching_reg. */
7506f491
DE
4178
4179static void
1d088dee 4180pre_insert_copy_insn (struct expr *expr, rtx insn)
7506f491
DE
4181{
4182 rtx reg = expr->reaching_reg;
4183 int regno = REGNO (reg);
4184 int indx = expr->bitmap_index;
073089a7
RS
4185 rtx pat = PATTERN (insn);
4186 rtx set, new_insn;
b885908b 4187 rtx old_reg;
073089a7 4188 int i;
7506f491 4189
073089a7 4190 /* This block matches the logic in hash_scan_insn. */
282899df 4191 switch (GET_CODE (pat))
073089a7 4192 {
282899df
NS
4193 case SET:
4194 set = pat;
4195 break;
4196
4197 case PARALLEL:
073089a7
RS
4198 /* Search through the parallel looking for the set whose
4199 source was the expression that we're interested in. */
4200 set = NULL_RTX;
4201 for (i = 0; i < XVECLEN (pat, 0); i++)
4202 {
4203 rtx x = XVECEXP (pat, 0, i);
4204 if (GET_CODE (x) == SET
4205 && expr_equiv_p (SET_SRC (x), expr->expr))
4206 {
4207 set = x;
4208 break;
4209 }
4210 }
282899df
NS
4211 break;
4212
4213 default:
4214 gcc_unreachable ();
073089a7 4215 }
c4c81601 4216
7b1b4aed 4217 if (REG_P (SET_DEST (set)))
073089a7 4218 {
f5f2e3cd
MH
4219 old_reg = SET_DEST (set);
4220 /* Check if we can modify the set destination in the original insn. */
4221 if (validate_change (insn, &SET_DEST (set), reg, 0))
4222 {
4223 new_insn = gen_move_insn (old_reg, reg);
4224 new_insn = emit_insn_after (new_insn, insn);
4225
4226 /* Keep register set table up to date. */
f5f2e3cd
MH
4227 record_one_set (regno, insn);
4228 }
4229 else
4230 {
4231 new_insn = gen_move_insn (reg, old_reg);
4232 new_insn = emit_insn_after (new_insn, insn);
073089a7 4233
f5f2e3cd
MH
4234 /* Keep register set table up to date. */
4235 record_one_set (regno, new_insn);
4236 }
073089a7 4237 }
f5f2e3cd 4238 else /* This is possible only in case of a store to memory. */
073089a7 4239 {
f5f2e3cd 4240 old_reg = SET_SRC (set);
073089a7 4241 new_insn = gen_move_insn (reg, old_reg);
f5f2e3cd
MH
4242
4243 /* Check if we can modify the set source in the original insn. */
4244 if (validate_change (insn, &SET_SRC (set), reg, 0))
4245 new_insn = emit_insn_before (new_insn, insn);
4246 else
4247 new_insn = emit_insn_after (new_insn, insn);
c4c81601 4248
073089a7
RS
4249 /* Keep register set table up to date. */
4250 record_one_set (regno, new_insn);
4251 }
7506f491
DE
4252
4253 gcse_create_count++;
4254
4255 if (gcse_file)
a42cd965
AM
4256 fprintf (gcse_file,
4257 "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n",
4258 BLOCK_NUM (insn), INSN_UID (new_insn), indx,
4259 INSN_UID (insn), regno);
7506f491
DE
4260}
4261
4262/* Copy available expressions that reach the redundant expression
4263 to `reaching_reg'. */
4264
4265static void
1d088dee 4266pre_insert_copies (void)
7506f491 4267{
f5f2e3cd 4268 unsigned int i, added_copy;
c4c81601
RK
4269 struct expr *expr;
4270 struct occr *occr;
4271 struct occr *avail;
a65f3558 4272
7506f491
DE
4273 /* For each available expression in the table, copy the result to
4274 `reaching_reg' if the expression reaches a deleted one.
4275
4276 ??? The current algorithm is rather brute force.
4277 Need to do some profiling. */
4278
02280659
ZD
4279 for (i = 0; i < expr_hash_table.size; i++)
4280 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
4281 {
4282 /* If the basic block isn't reachable, PPOUT will be TRUE. However,
4283 we don't want to insert a copy here because the expression may not
4284 really be redundant. So only insert an insn if the expression was
4285 deleted. This test also avoids further processing if the
4286 expression wasn't deleted anywhere. */
4287 if (expr->reaching_reg == NULL)
4288 continue;
7b1b4aed 4289
f5f2e3cd 4290 /* Set when we add a copy for that expression. */
7b1b4aed 4291 added_copy = 0;
c4c81601
RK
4292
4293 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4294 {
4295 if (! occr->deleted_p)
4296 continue;
7506f491 4297
c4c81601
RK
4298 for (avail = expr->avail_occr; avail != NULL; avail = avail->next)
4299 {
4300 rtx insn = avail->insn;
7506f491 4301
c4c81601
RK
4302 /* No need to handle this one if handled already. */
4303 if (avail->copied_p)
4304 continue;
7506f491 4305
c4c81601
RK
4306 /* Don't handle this one if it's a redundant one. */
4307 if (TEST_BIT (pre_redundant_insns, INSN_CUID (insn)))
4308 continue;
7506f491 4309
c4c81601 4310 /* Or if the expression doesn't reach the deleted one. */
589005ff 4311 if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn),
e2d2ed72
AM
4312 expr,
4313 BLOCK_FOR_INSN (occr->insn)))
c4c81601 4314 continue;
7506f491 4315
f5f2e3cd
MH
4316 added_copy = 1;
4317
c4c81601
RK
4318 /* Copy the result of avail to reaching_reg. */
4319 pre_insert_copy_insn (expr, insn);
4320 avail->copied_p = 1;
4321 }
4322 }
f5f2e3cd 4323
7b1b4aed 4324 if (added_copy)
f5f2e3cd 4325 update_ld_motion_stores (expr);
c4c81601 4326 }
7506f491
DE
4327}
4328
10d1bb36
JH
4329/* Emit move from SRC to DEST noting the equivalence with expression computed
4330 in INSN. */
4331static rtx
1d088dee 4332gcse_emit_move_after (rtx src, rtx dest, rtx insn)
10d1bb36
JH
4333{
4334 rtx new;
6bdb8dd6 4335 rtx set = single_set (insn), set2;
10d1bb36
JH
4336 rtx note;
4337 rtx eqv;
4338
4339 /* This should never fail since we're creating a reg->reg copy
4340 we've verified to be valid. */
4341
6bdb8dd6 4342 new = emit_insn_after (gen_move_insn (dest, src), insn);
285464d0 4343
10d1bb36 4344 /* Note the equivalence for local CSE pass. */
6bdb8dd6
JH
4345 set2 = single_set (new);
4346 if (!set2 || !rtx_equal_p (SET_DEST (set2), dest))
4347 return new;
10d1bb36
JH
4348 if ((note = find_reg_equal_equiv_note (insn)))
4349 eqv = XEXP (note, 0);
4350 else
4351 eqv = SET_SRC (set);
4352
a500466b 4353 set_unique_reg_note (new, REG_EQUAL, copy_insn_1 (eqv));
10d1bb36
JH
4354
4355 return new;
4356}
4357
7506f491 4358/* Delete redundant computations.
7506f491
DE
4359 Deletion is done by changing the insn to copy the `reaching_reg' of
4360 the expression into the result of the SET. It is left to later passes
4361 (cprop, cse2, flow, combine, regmove) to propagate the copy or eliminate it.
4362
cc2902df 4363 Returns nonzero if a change is made. */
7506f491
DE
4364
4365static int
1d088dee 4366pre_delete (void)
7506f491 4367{
2e653e39 4368 unsigned int i;
63bc1d05 4369 int changed;
c4c81601
RK
4370 struct expr *expr;
4371 struct occr *occr;
a65f3558 4372
7506f491 4373 changed = 0;
02280659 4374 for (i = 0; i < expr_hash_table.size; i++)
073089a7
RS
4375 for (expr = expr_hash_table.table[i];
4376 expr != NULL;
4377 expr = expr->next_same_hash)
c4c81601
RK
4378 {
4379 int indx = expr->bitmap_index;
7506f491 4380
c4c81601
RK
4381 /* We only need to search antic_occr since we require
4382 ANTLOC != 0. */
7506f491 4383
c4c81601
RK
4384 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4385 {
4386 rtx insn = occr->insn;
4387 rtx set;
e2d2ed72 4388 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491 4389
073089a7
RS
4390 /* We only delete insns that have a single_set. */
4391 if (TEST_BIT (pre_delete_map[bb->index], indx)
4392 && (set = single_set (insn)) != 0)
c4c81601 4393 {
c4c81601
RK
4394 /* Create a pseudo-reg to store the result of reaching
4395 expressions into. Get the mode for the new pseudo from
4396 the mode of the original destination pseudo. */
4397 if (expr->reaching_reg == NULL)
4398 expr->reaching_reg
4399 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
4400
9b76aa3b 4401 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
10d1bb36
JH
4402 delete_insn (insn);
4403 occr->deleted_p = 1;
4404 SET_BIT (pre_redundant_insns, INSN_CUID (insn));
4405 changed = 1;
4406 gcse_subst_count++;
7506f491 4407
c4c81601
RK
4408 if (gcse_file)
4409 {
4410 fprintf (gcse_file,
4411 "PRE: redundant insn %d (expression %d) in ",
4412 INSN_UID (insn), indx);
4413 fprintf (gcse_file, "bb %d, reaching reg is %d\n",
0b17ab2f 4414 bb->index, REGNO (expr->reaching_reg));
c4c81601
RK
4415 }
4416 }
4417 }
4418 }
7506f491
DE
4419
4420 return changed;
4421}
4422
4423/* Perform GCSE optimizations using PRE.
4424 This is called by one_pre_gcse_pass after all the dataflow analysis
4425 has been done.
4426
c4c81601
RK
4427 This is based on the original Morel-Renvoise paper Fred Chow's thesis, and
4428 lazy code motion from Knoop, Ruthing and Steffen as described in Advanced
4429 Compiler Design and Implementation.
7506f491 4430
c4c81601
RK
4431 ??? A new pseudo reg is created to hold the reaching expression. The nice
4432 thing about the classical approach is that it would try to use an existing
4433 reg. If the register can't be adequately optimized [i.e. we introduce
4434 reload problems], one could add a pass here to propagate the new register
4435 through the block.
7506f491 4436
c4c81601
RK
4437 ??? We don't handle single sets in PARALLELs because we're [currently] not
4438 able to copy the rest of the parallel when we insert copies to create full
4439 redundancies from partial redundancies. However, there's no reason why we
4440 can't handle PARALLELs in the cases where there are no partial
7506f491
DE
4441 redundancies. */
4442
4443static int
1d088dee 4444pre_gcse (void)
7506f491 4445{
2e653e39
RK
4446 unsigned int i;
4447 int did_insert, changed;
7506f491 4448 struct expr **index_map;
c4c81601 4449 struct expr *expr;
7506f491
DE
4450
4451 /* Compute a mapping from expression number (`bitmap_index') to
4452 hash table entry. */
4453
703ad42b 4454 index_map = xcalloc (expr_hash_table.n_elems, sizeof (struct expr *));
02280659
ZD
4455 for (i = 0; i < expr_hash_table.size; i++)
4456 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 4457 index_map[expr->bitmap_index] = expr;
7506f491
DE
4458
4459 /* Reset bitmap used to track which insns are redundant. */
a65f3558
JL
4460 pre_redundant_insns = sbitmap_alloc (max_cuid);
4461 sbitmap_zero (pre_redundant_insns);
7506f491
DE
4462
4463 /* Delete the redundant insns first so that
4464 - we know what register to use for the new insns and for the other
4465 ones with reaching expressions
4466 - we know which insns are redundant when we go to create copies */
c4c81601 4467
7506f491
DE
4468 changed = pre_delete ();
4469
a42cd965 4470 did_insert = pre_edge_insert (edge_list, index_map);
c4c81601 4471
7506f491 4472 /* In other places with reaching expressions, copy the expression to the
a42cd965 4473 specially allocated pseudo-reg that reaches the redundant expr. */
7506f491 4474 pre_insert_copies ();
a42cd965
AM
4475 if (did_insert)
4476 {
4477 commit_edge_insertions ();
4478 changed = 1;
4479 }
7506f491 4480
283a2545 4481 free (index_map);
76ac938b 4482 sbitmap_free (pre_redundant_insns);
7506f491
DE
4483 return changed;
4484}
4485
4486/* Top level routine to perform one PRE GCSE pass.
4487
cc2902df 4488 Return nonzero if a change was made. */
7506f491
DE
4489
4490static int
1d088dee 4491one_pre_gcse_pass (int pass)
7506f491
DE
4492{
4493 int changed = 0;
4494
4495 gcse_subst_count = 0;
4496 gcse_create_count = 0;
4497
02280659 4498 alloc_hash_table (max_cuid, &expr_hash_table, 0);
a42cd965 4499 add_noreturn_fake_exit_edges ();
a13d4ebf
AM
4500 if (flag_gcse_lm)
4501 compute_ld_motion_mems ();
4502
02280659 4503 compute_hash_table (&expr_hash_table);
a13d4ebf 4504 trim_ld_motion_mems ();
7506f491 4505 if (gcse_file)
02280659 4506 dump_hash_table (gcse_file, "Expression", &expr_hash_table);
c4c81601 4507
02280659 4508 if (expr_hash_table.n_elems > 0)
7506f491 4509 {
02280659 4510 alloc_pre_mem (last_basic_block, expr_hash_table.n_elems);
7506f491
DE
4511 compute_pre_data ();
4512 changed |= pre_gcse ();
a42cd965 4513 free_edge_list (edge_list);
7506f491
DE
4514 free_pre_mem ();
4515 }
c4c81601 4516
a13d4ebf 4517 free_ldst_mems ();
6809cbf9 4518 remove_fake_exit_edges ();
02280659 4519 free_hash_table (&expr_hash_table);
7506f491
DE
4520
4521 if (gcse_file)
4522 {
c4c81601 4523 fprintf (gcse_file, "\nPRE GCSE of %s, pass %d: %d bytes needed, ",
faed5cc3 4524 current_function_name (), pass, bytes_used);
c4c81601
RK
4525 fprintf (gcse_file, "%d substs, %d insns created\n",
4526 gcse_subst_count, gcse_create_count);
7506f491
DE
4527 }
4528
4529 return changed;
4530}
aeb2f500
JW
4531\f
4532/* If X contains any LABEL_REF's, add REG_LABEL notes for them to INSN.
5b1ef594
JDA
4533 If notes are added to an insn which references a CODE_LABEL, the
4534 LABEL_NUSES count is incremented. We have to add REG_LABEL notes,
4535 because the following loop optimization pass requires them. */
aeb2f500
JW
4536
4537/* ??? This is very similar to the loop.c add_label_notes function. We
4538 could probably share code here. */
4539
4540/* ??? If there was a jump optimization pass after gcse and before loop,
4541 then we would not need to do this here, because jump would add the
4542 necessary REG_LABEL notes. */
4543
4544static void
1d088dee 4545add_label_notes (rtx x, rtx insn)
aeb2f500
JW
4546{
4547 enum rtx_code code = GET_CODE (x);
4548 int i, j;
6f7d635c 4549 const char *fmt;
aeb2f500
JW
4550
4551 if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
4552 {
6b3603c2 4553 /* This code used to ignore labels that referred to dispatch tables to
e0bb17a8 4554 avoid flow generating (slightly) worse code.
6b3603c2 4555
ac7c5af5
JL
4556 We no longer ignore such label references (see LABEL_REF handling in
4557 mark_jump_label for additional information). */
c4c81601 4558
6b8c9327 4559 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, XEXP (x, 0),
6b3603c2 4560 REG_NOTES (insn));
5b1ef594 4561 if (LABEL_P (XEXP (x, 0)))
589005ff 4562 LABEL_NUSES (XEXP (x, 0))++;
aeb2f500
JW
4563 return;
4564 }
4565
c4c81601 4566 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
aeb2f500
JW
4567 {
4568 if (fmt[i] == 'e')
4569 add_label_notes (XEXP (x, i), insn);
4570 else if (fmt[i] == 'E')
4571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4572 add_label_notes (XVECEXP (x, i, j), insn);
4573 }
4574}
a65f3558
JL
4575
4576/* Compute transparent outgoing information for each block.
4577
4578 An expression is transparent to an edge unless it is killed by
4579 the edge itself. This can only happen with abnormal control flow,
4580 when the edge is traversed through a call. This happens with
4581 non-local labels and exceptions.
4582
4583 This would not be necessary if we split the edge. While this is
4584 normally impossible for abnormal critical edges, with some effort
4585 it should be possible with exception handling, since we still have
4586 control over which handler should be invoked. But due to increased
4587 EH table sizes, this may not be worthwhile. */
4588
4589static void
1d088dee 4590compute_transpout (void)
a65f3558 4591{
e0082a72 4592 basic_block bb;
2e653e39 4593 unsigned int i;
c4c81601 4594 struct expr *expr;
a65f3558 4595
d55bc081 4596 sbitmap_vector_ones (transpout, last_basic_block);
a65f3558 4597
e0082a72 4598 FOR_EACH_BB (bb)
a65f3558 4599 {
a65f3558
JL
4600 /* Note that flow inserted a nop a the end of basic blocks that
4601 end in call instructions for reasons other than abnormal
4602 control flow. */
7b1b4aed 4603 if (! CALL_P (BB_END (bb)))
a65f3558
JL
4604 continue;
4605
02280659
ZD
4606 for (i = 0; i < expr_hash_table.size; i++)
4607 for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash)
7b1b4aed 4608 if (MEM_P (expr->expr))
c4c81601
RK
4609 {
4610 if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF
4611 && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0)))
4612 continue;
589005ff 4613
c4c81601
RK
4614 /* ??? Optimally, we would use interprocedural alias
4615 analysis to determine if this mem is actually killed
4616 by this call. */
e0082a72 4617 RESET_BIT (transpout[bb->index], expr->bitmap_index);
c4c81601 4618 }
a65f3558
JL
4619 }
4620}
dfdb644f 4621
bb457bd9
JL
4622/* Code Hoisting variables and subroutines. */
4623
4624/* Very busy expressions. */
4625static sbitmap *hoist_vbein;
4626static sbitmap *hoist_vbeout;
4627
4628/* Hoistable expressions. */
4629static sbitmap *hoist_exprs;
4630
bb457bd9 4631/* ??? We could compute post dominators and run this algorithm in
68e82b83 4632 reverse to perform tail merging, doing so would probably be
bb457bd9
JL
4633 more effective than the tail merging code in jump.c.
4634
4635 It's unclear if tail merging could be run in parallel with
4636 code hoisting. It would be nice. */
4637
4638/* Allocate vars used for code hoisting analysis. */
4639
4640static void
1d088dee 4641alloc_code_hoist_mem (int n_blocks, int n_exprs)
bb457bd9
JL
4642{
4643 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
4644 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
4645 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
4646
4647 hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs);
4648 hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs);
4649 hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs);
4650 transpout = sbitmap_vector_alloc (n_blocks, n_exprs);
bb457bd9
JL
4651}
4652
4653/* Free vars used for code hoisting analysis. */
4654
4655static void
1d088dee 4656free_code_hoist_mem (void)
bb457bd9 4657{
5a660bff
DB
4658 sbitmap_vector_free (antloc);
4659 sbitmap_vector_free (transp);
4660 sbitmap_vector_free (comp);
bb457bd9 4661
5a660bff
DB
4662 sbitmap_vector_free (hoist_vbein);
4663 sbitmap_vector_free (hoist_vbeout);
4664 sbitmap_vector_free (hoist_exprs);
4665 sbitmap_vector_free (transpout);
bb457bd9 4666
d47cc544 4667 free_dominance_info (CDI_DOMINATORS);
bb457bd9
JL
4668}
4669
4670/* Compute the very busy expressions at entry/exit from each block.
4671
4672 An expression is very busy if all paths from a given point
4673 compute the expression. */
4674
4675static void
1d088dee 4676compute_code_hoist_vbeinout (void)
bb457bd9 4677{
e0082a72
ZD
4678 int changed, passes;
4679 basic_block bb;
bb457bd9 4680
d55bc081
ZD
4681 sbitmap_vector_zero (hoist_vbeout, last_basic_block);
4682 sbitmap_vector_zero (hoist_vbein, last_basic_block);
bb457bd9
JL
4683
4684 passes = 0;
4685 changed = 1;
c4c81601 4686
bb457bd9
JL
4687 while (changed)
4688 {
4689 changed = 0;
c4c81601 4690
bb457bd9
JL
4691 /* We scan the blocks in the reverse order to speed up
4692 the convergence. */
e0082a72 4693 FOR_EACH_BB_REVERSE (bb)
bb457bd9 4694 {
e0082a72
ZD
4695 changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index], antloc[bb->index],
4696 hoist_vbeout[bb->index], transp[bb->index]);
4697 if (bb->next_bb != EXIT_BLOCK_PTR)
4698 sbitmap_intersection_of_succs (hoist_vbeout[bb->index], hoist_vbein, bb->index);
bb457bd9 4699 }
c4c81601 4700
bb457bd9
JL
4701 passes++;
4702 }
4703
4704 if (gcse_file)
4705 fprintf (gcse_file, "hoisting vbeinout computation: %d passes\n", passes);
4706}
4707
4708/* Top level routine to do the dataflow analysis needed by code hoisting. */
4709
4710static void
1d088dee 4711compute_code_hoist_data (void)
bb457bd9 4712{
02280659 4713 compute_local_properties (transp, comp, antloc, &expr_hash_table);
bb457bd9
JL
4714 compute_transpout ();
4715 compute_code_hoist_vbeinout ();
d47cc544 4716 calculate_dominance_info (CDI_DOMINATORS);
bb457bd9
JL
4717 if (gcse_file)
4718 fprintf (gcse_file, "\n");
4719}
4720
4721/* Determine if the expression identified by EXPR_INDEX would
4722 reach BB unimpared if it was placed at the end of EXPR_BB.
4723
4724 It's unclear exactly what Muchnick meant by "unimpared". It seems
4725 to me that the expression must either be computed or transparent in
4726 *every* block in the path(s) from EXPR_BB to BB. Any other definition
4727 would allow the expression to be hoisted out of loops, even if
4728 the expression wasn't a loop invariant.
4729
4730 Contrast this to reachability for PRE where an expression is
4731 considered reachable if *any* path reaches instead of *all*
4732 paths. */
4733
4734static int
1d088dee 4735hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited)
bb457bd9
JL
4736{
4737 edge pred;
628f6a4e 4738 edge_iterator ei;
283a2545 4739 int visited_allocated_locally = 0;
589005ff 4740
bb457bd9
JL
4741
4742 if (visited == NULL)
4743 {
8e42ace1 4744 visited_allocated_locally = 1;
d55bc081 4745 visited = xcalloc (last_basic_block, 1);
bb457bd9
JL
4746 }
4747
628f6a4e 4748 FOR_EACH_EDGE (pred, ei, bb->preds)
bb457bd9 4749 {
e2d2ed72 4750 basic_block pred_bb = pred->src;
bb457bd9
JL
4751
4752 if (pred->src == ENTRY_BLOCK_PTR)
4753 break;
f305679f
JH
4754 else if (pred_bb == expr_bb)
4755 continue;
0b17ab2f 4756 else if (visited[pred_bb->index])
bb457bd9 4757 continue;
c4c81601 4758
bb457bd9 4759 /* Does this predecessor generate this expression? */
0b17ab2f 4760 else if (TEST_BIT (comp[pred_bb->index], expr_index))
bb457bd9 4761 break;
0b17ab2f 4762 else if (! TEST_BIT (transp[pred_bb->index], expr_index))
bb457bd9 4763 break;
c4c81601 4764
bb457bd9
JL
4765 /* Not killed. */
4766 else
4767 {
0b17ab2f 4768 visited[pred_bb->index] = 1;
bb457bd9
JL
4769 if (! hoist_expr_reaches_here_p (expr_bb, expr_index,
4770 pred_bb, visited))
4771 break;
4772 }
4773 }
589005ff 4774 if (visited_allocated_locally)
283a2545 4775 free (visited);
c4c81601 4776
bb457bd9
JL
4777 return (pred == NULL);
4778}
4779\f
4780/* Actually perform code hoisting. */
c4c81601 4781
bb457bd9 4782static void
1d088dee 4783hoist_code (void)
bb457bd9 4784{
e0082a72 4785 basic_block bb, dominated;
c635a1ec
DB
4786 basic_block *domby;
4787 unsigned int domby_len;
4788 unsigned int i,j;
bb457bd9 4789 struct expr **index_map;
c4c81601 4790 struct expr *expr;
bb457bd9 4791
d55bc081 4792 sbitmap_vector_zero (hoist_exprs, last_basic_block);
bb457bd9
JL
4793
4794 /* Compute a mapping from expression number (`bitmap_index') to
4795 hash table entry. */
4796
703ad42b 4797 index_map = xcalloc (expr_hash_table.n_elems, sizeof (struct expr *));
02280659
ZD
4798 for (i = 0; i < expr_hash_table.size; i++)
4799 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 4800 index_map[expr->bitmap_index] = expr;
bb457bd9
JL
4801
4802 /* Walk over each basic block looking for potentially hoistable
4803 expressions, nothing gets hoisted from the entry block. */
e0082a72 4804 FOR_EACH_BB (bb)
bb457bd9
JL
4805 {
4806 int found = 0;
4807 int insn_inserted_p;
4808
d47cc544 4809 domby_len = get_dominated_by (CDI_DOMINATORS, bb, &domby);
bb457bd9
JL
4810 /* Examine each expression that is very busy at the exit of this
4811 block. These are the potentially hoistable expressions. */
e0082a72 4812 for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++)
bb457bd9
JL
4813 {
4814 int hoistable = 0;
c4c81601 4815
c635a1ec
DB
4816 if (TEST_BIT (hoist_vbeout[bb->index], i)
4817 && TEST_BIT (transpout[bb->index], i))
bb457bd9
JL
4818 {
4819 /* We've found a potentially hoistable expression, now
4820 we look at every block BB dominates to see if it
4821 computes the expression. */
c635a1ec 4822 for (j = 0; j < domby_len; j++)
bb457bd9 4823 {
c635a1ec 4824 dominated = domby[j];
bb457bd9 4825 /* Ignore self dominance. */
c635a1ec 4826 if (bb == dominated)
bb457bd9 4827 continue;
bb457bd9
JL
4828 /* We've found a dominated block, now see if it computes
4829 the busy expression and whether or not moving that
4830 expression to the "beginning" of that block is safe. */
e0082a72 4831 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
4832 continue;
4833
4834 /* Note if the expression would reach the dominated block
589005ff 4835 unimpared if it was placed at the end of BB.
bb457bd9
JL
4836
4837 Keep track of how many times this expression is hoistable
4838 from a dominated block into BB. */
e0082a72 4839 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
4840 hoistable++;
4841 }
4842
ff7cc307 4843 /* If we found more than one hoistable occurrence of this
bb457bd9
JL
4844 expression, then note it in the bitmap of expressions to
4845 hoist. It makes no sense to hoist things which are computed
4846 in only one BB, and doing so tends to pessimize register
4847 allocation. One could increase this value to try harder
4848 to avoid any possible code expansion due to register
4849 allocation issues; however experiments have shown that
4850 the vast majority of hoistable expressions are only movable
e0bb17a8 4851 from two successors, so raising this threshold is likely
bb457bd9
JL
4852 to nullify any benefit we get from code hoisting. */
4853 if (hoistable > 1)
4854 {
e0082a72 4855 SET_BIT (hoist_exprs[bb->index], i);
bb457bd9
JL
4856 found = 1;
4857 }
4858 }
4859 }
bb457bd9
JL
4860 /* If we found nothing to hoist, then quit now. */
4861 if (! found)
c635a1ec 4862 {
1d088dee 4863 free (domby);
bb457bd9 4864 continue;
c635a1ec 4865 }
bb457bd9
JL
4866
4867 /* Loop over all the hoistable expressions. */
e0082a72 4868 for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++)
bb457bd9
JL
4869 {
4870 /* We want to insert the expression into BB only once, so
4871 note when we've inserted it. */
4872 insn_inserted_p = 0;
4873
4874 /* These tests should be the same as the tests above. */
e0082a72 4875 if (TEST_BIT (hoist_vbeout[bb->index], i))
bb457bd9
JL
4876 {
4877 /* We've found a potentially hoistable expression, now
4878 we look at every block BB dominates to see if it
4879 computes the expression. */
c635a1ec 4880 for (j = 0; j < domby_len; j++)
bb457bd9 4881 {
c635a1ec 4882 dominated = domby[j];
bb457bd9 4883 /* Ignore self dominance. */
c635a1ec 4884 if (bb == dominated)
bb457bd9
JL
4885 continue;
4886
4887 /* We've found a dominated block, now see if it computes
4888 the busy expression and whether or not moving that
4889 expression to the "beginning" of that block is safe. */
e0082a72 4890 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
4891 continue;
4892
4893 /* The expression is computed in the dominated block and
4894 it would be safe to compute it at the start of the
4895 dominated block. Now we have to determine if the
ff7cc307 4896 expression would reach the dominated block if it was
bb457bd9 4897 placed at the end of BB. */
e0082a72 4898 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
4899 {
4900 struct expr *expr = index_map[i];
4901 struct occr *occr = expr->antic_occr;
4902 rtx insn;
4903 rtx set;
4904
ff7cc307 4905 /* Find the right occurrence of this expression. */
e0082a72 4906 while (BLOCK_FOR_INSN (occr->insn) != dominated && occr)
bb457bd9
JL
4907 occr = occr->next;
4908
282899df 4909 gcc_assert (occr);
bb457bd9 4910 insn = occr->insn;
bb457bd9 4911 set = single_set (insn);
282899df 4912 gcc_assert (set);
bb457bd9
JL
4913
4914 /* Create a pseudo-reg to store the result of reaching
4915 expressions into. Get the mode for the new pseudo
4916 from the mode of the original destination pseudo. */
4917 if (expr->reaching_reg == NULL)
4918 expr->reaching_reg
4919 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
4920
10d1bb36
JH
4921 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
4922 delete_insn (insn);
4923 occr->deleted_p = 1;
4924 if (!insn_inserted_p)
bb457bd9 4925 {
10d1bb36
JH
4926 insert_insn_end_bb (index_map[i], bb, 0);
4927 insn_inserted_p = 1;
bb457bd9
JL
4928 }
4929 }
4930 }
4931 }
4932 }
c635a1ec 4933 free (domby);
bb457bd9 4934 }
c4c81601 4935
8e42ace1 4936 free (index_map);
bb457bd9
JL
4937}
4938
4939/* Top level routine to perform one code hoisting (aka unification) pass
4940
cc2902df 4941 Return nonzero if a change was made. */
bb457bd9
JL
4942
4943static int
1d088dee 4944one_code_hoisting_pass (void)
bb457bd9
JL
4945{
4946 int changed = 0;
4947
02280659
ZD
4948 alloc_hash_table (max_cuid, &expr_hash_table, 0);
4949 compute_hash_table (&expr_hash_table);
bb457bd9 4950 if (gcse_file)
02280659 4951 dump_hash_table (gcse_file, "Code Hosting Expressions", &expr_hash_table);
c4c81601 4952
02280659 4953 if (expr_hash_table.n_elems > 0)
bb457bd9 4954 {
02280659 4955 alloc_code_hoist_mem (last_basic_block, expr_hash_table.n_elems);
bb457bd9
JL
4956 compute_code_hoist_data ();
4957 hoist_code ();
4958 free_code_hoist_mem ();
4959 }
c4c81601 4960
02280659 4961 free_hash_table (&expr_hash_table);
bb457bd9
JL
4962
4963 return changed;
4964}
a13d4ebf
AM
4965\f
4966/* Here we provide the things required to do store motion towards
4967 the exit. In order for this to be effective, gcse also needed to
4968 be taught how to move a load when it is kill only by a store to itself.
4969
4970 int i;
4971 float a[10];
4972
4973 void foo(float scale)
4974 {
4975 for (i=0; i<10; i++)
4976 a[i] *= scale;
4977 }
4978
4979 'i' is both loaded and stored to in the loop. Normally, gcse cannot move
589005ff
KH
4980 the load out since its live around the loop, and stored at the bottom
4981 of the loop.
a13d4ebf 4982
589005ff 4983 The 'Load Motion' referred to and implemented in this file is
a13d4ebf
AM
4984 an enhancement to gcse which when using edge based lcm, recognizes
4985 this situation and allows gcse to move the load out of the loop.
4986
4987 Once gcse has hoisted the load, store motion can then push this
4988 load towards the exit, and we end up with no loads or stores of 'i'
4989 in the loop. */
4990
ff7cc307 4991/* This will search the ldst list for a matching expression. If it
a13d4ebf
AM
4992 doesn't find one, we create one and initialize it. */
4993
4994static struct ls_expr *
1d088dee 4995ldst_entry (rtx x)
a13d4ebf 4996{
b58b21d5 4997 int do_not_record_p = 0;
a13d4ebf 4998 struct ls_expr * ptr;
b58b21d5 4999 unsigned int hash;
a13d4ebf 5000
0516f6fe
SB
5001 hash = hash_rtx (x, GET_MODE (x), &do_not_record_p,
5002 NULL, /*have_reg_qty=*/false);
a13d4ebf 5003
b58b21d5
RS
5004 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
5005 if (ptr->hash_index == hash && expr_equiv_p (ptr->pattern, x))
5006 return ptr;
5007
5008 ptr = xmalloc (sizeof (struct ls_expr));
5009
5010 ptr->next = pre_ldst_mems;
5011 ptr->expr = NULL;
5012 ptr->pattern = x;
5013 ptr->pattern_regs = NULL_RTX;
5014 ptr->loads = NULL_RTX;
5015 ptr->stores = NULL_RTX;
5016 ptr->reaching_reg = NULL_RTX;
5017 ptr->invalid = 0;
5018 ptr->index = 0;
5019 ptr->hash_index = hash;
5020 pre_ldst_mems = ptr;
589005ff 5021
a13d4ebf
AM
5022 return ptr;
5023}
5024
5025/* Free up an individual ldst entry. */
5026
589005ff 5027static void
1d088dee 5028free_ldst_entry (struct ls_expr * ptr)
a13d4ebf 5029{
aaa4ca30
AJ
5030 free_INSN_LIST_list (& ptr->loads);
5031 free_INSN_LIST_list (& ptr->stores);
a13d4ebf
AM
5032
5033 free (ptr);
5034}
5035
5036/* Free up all memory associated with the ldst list. */
5037
5038static void
1d088dee 5039free_ldst_mems (void)
a13d4ebf 5040{
589005ff 5041 while (pre_ldst_mems)
a13d4ebf
AM
5042 {
5043 struct ls_expr * tmp = pre_ldst_mems;
5044
5045 pre_ldst_mems = pre_ldst_mems->next;
5046
5047 free_ldst_entry (tmp);
5048 }
5049
5050 pre_ldst_mems = NULL;
5051}
5052
5053/* Dump debugging info about the ldst list. */
5054
5055static void
1d088dee 5056print_ldst_list (FILE * file)
a13d4ebf
AM
5057{
5058 struct ls_expr * ptr;
5059
5060 fprintf (file, "LDST list: \n");
5061
5062 for (ptr = first_ls_expr(); ptr != NULL; ptr = next_ls_expr (ptr))
5063 {
5064 fprintf (file, " Pattern (%3d): ", ptr->index);
5065
5066 print_rtl (file, ptr->pattern);
5067
5068 fprintf (file, "\n Loads : ");
5069
5070 if (ptr->loads)
5071 print_rtl (file, ptr->loads);
5072 else
5073 fprintf (file, "(nil)");
5074
5075 fprintf (file, "\n Stores : ");
5076
5077 if (ptr->stores)
5078 print_rtl (file, ptr->stores);
5079 else
5080 fprintf (file, "(nil)");
5081
5082 fprintf (file, "\n\n");
5083 }
5084
5085 fprintf (file, "\n");
5086}
5087
5088/* Returns 1 if X is in the list of ldst only expressions. */
5089
5090static struct ls_expr *
1d088dee 5091find_rtx_in_ldst (rtx x)
a13d4ebf
AM
5092{
5093 struct ls_expr * ptr;
589005ff 5094
a13d4ebf
AM
5095 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
5096 if (expr_equiv_p (ptr->pattern, x) && ! ptr->invalid)
5097 return ptr;
5098
5099 return NULL;
5100}
5101
5102/* Assign each element of the list of mems a monotonically increasing value. */
5103
5104static int
1d088dee 5105enumerate_ldsts (void)
a13d4ebf
AM
5106{
5107 struct ls_expr * ptr;
5108 int n = 0;
5109
5110 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
5111 ptr->index = n++;
5112
5113 return n;
5114}
5115
5116/* Return first item in the list. */
5117
5118static inline struct ls_expr *
1d088dee 5119first_ls_expr (void)
a13d4ebf
AM
5120{
5121 return pre_ldst_mems;
5122}
5123
0e8a66de 5124/* Return the next item in the list after the specified one. */
a13d4ebf
AM
5125
5126static inline struct ls_expr *
1d088dee 5127next_ls_expr (struct ls_expr * ptr)
a13d4ebf
AM
5128{
5129 return ptr->next;
5130}
5131\f
5132/* Load Motion for loads which only kill themselves. */
5133
5134/* Return true if x is a simple MEM operation, with no registers or
5135 side effects. These are the types of loads we consider for the
5136 ld_motion list, otherwise we let the usual aliasing take care of it. */
5137
589005ff 5138static int
1d088dee 5139simple_mem (rtx x)
a13d4ebf 5140{
7b1b4aed 5141 if (! MEM_P (x))
a13d4ebf 5142 return 0;
589005ff 5143
a13d4ebf
AM
5144 if (MEM_VOLATILE_P (x))
5145 return 0;
589005ff 5146
a13d4ebf
AM
5147 if (GET_MODE (x) == BLKmode)
5148 return 0;
aaa4ca30 5149
47a3dae1
ZD
5150 /* If we are handling exceptions, we must be careful with memory references
5151 that may trap. If we are not, the behavior is undefined, so we may just
5152 continue. */
5153 if (flag_non_call_exceptions && may_trap_p (x))
98d3d336
RS
5154 return 0;
5155
47a3dae1
ZD
5156 if (side_effects_p (x))
5157 return 0;
589005ff 5158
47a3dae1
ZD
5159 /* Do not consider function arguments passed on stack. */
5160 if (reg_mentioned_p (stack_pointer_rtx, x))
5161 return 0;
5162
5163 if (flag_float_store && FLOAT_MODE_P (GET_MODE (x)))
5164 return 0;
5165
5166 return 1;
a13d4ebf
AM
5167}
5168
589005ff
KH
5169/* Make sure there isn't a buried reference in this pattern anywhere.
5170 If there is, invalidate the entry for it since we're not capable
5171 of fixing it up just yet.. We have to be sure we know about ALL
a13d4ebf
AM
5172 loads since the aliasing code will allow all entries in the
5173 ld_motion list to not-alias itself. If we miss a load, we will get
589005ff 5174 the wrong value since gcse might common it and we won't know to
a13d4ebf
AM
5175 fix it up. */
5176
5177static void
1d088dee 5178invalidate_any_buried_refs (rtx x)
a13d4ebf
AM
5179{
5180 const char * fmt;
8e42ace1 5181 int i, j;
a13d4ebf
AM
5182 struct ls_expr * ptr;
5183
5184 /* Invalidate it in the list. */
7b1b4aed 5185 if (MEM_P (x) && simple_mem (x))
a13d4ebf
AM
5186 {
5187 ptr = ldst_entry (x);
5188 ptr->invalid = 1;
5189 }
5190
5191 /* Recursively process the insn. */
5192 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 5193
a13d4ebf
AM
5194 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5195 {
5196 if (fmt[i] == 'e')
5197 invalidate_any_buried_refs (XEXP (x, i));
5198 else if (fmt[i] == 'E')
5199 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5200 invalidate_any_buried_refs (XVECEXP (x, i, j));
5201 }
5202}
5203
4d3eb89a
HPN
5204/* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple
5205 being defined as MEM loads and stores to symbols, with no side effects
5206 and no registers in the expression. For a MEM destination, we also
5207 check that the insn is still valid if we replace the destination with a
5208 REG, as is done in update_ld_motion_stores. If there are any uses/defs
5209 which don't match this criteria, they are invalidated and trimmed out
5210 later. */
a13d4ebf 5211
589005ff 5212static void
1d088dee 5213compute_ld_motion_mems (void)
a13d4ebf
AM
5214{
5215 struct ls_expr * ptr;
e0082a72 5216 basic_block bb;
a13d4ebf 5217 rtx insn;
589005ff 5218
a13d4ebf
AM
5219 pre_ldst_mems = NULL;
5220
e0082a72 5221 FOR_EACH_BB (bb)
a13d4ebf 5222 {
a813c111
SB
5223 for (insn = BB_HEAD (bb);
5224 insn && insn != NEXT_INSN (BB_END (bb));
a13d4ebf
AM
5225 insn = NEXT_INSN (insn))
5226 {
735e8085 5227 if (INSN_P (insn))
a13d4ebf
AM
5228 {
5229 if (GET_CODE (PATTERN (insn)) == SET)
5230 {
5231 rtx src = SET_SRC (PATTERN (insn));
5232 rtx dest = SET_DEST (PATTERN (insn));
5233
5234 /* Check for a simple LOAD... */
7b1b4aed 5235 if (MEM_P (src) && simple_mem (src))
a13d4ebf
AM
5236 {
5237 ptr = ldst_entry (src);
7b1b4aed 5238 if (REG_P (dest))
a13d4ebf
AM
5239 ptr->loads = alloc_INSN_LIST (insn, ptr->loads);
5240 else
5241 ptr->invalid = 1;
5242 }
5243 else
5244 {
5245 /* Make sure there isn't a buried load somewhere. */
5246 invalidate_any_buried_refs (src);
5247 }
589005ff 5248
a13d4ebf
AM
5249 /* Check for stores. Don't worry about aliased ones, they
5250 will block any movement we might do later. We only care
5251 about this exact pattern since those are the only
5252 circumstance that we will ignore the aliasing info. */
7b1b4aed 5253 if (MEM_P (dest) && simple_mem (dest))
a13d4ebf
AM
5254 {
5255 ptr = ldst_entry (dest);
589005ff 5256
7b1b4aed 5257 if (! MEM_P (src)
4d3eb89a
HPN
5258 && GET_CODE (src) != ASM_OPERANDS
5259 /* Check for REG manually since want_to_gcse_p
5260 returns 0 for all REGs. */
1707bafa 5261 && can_assign_to_reg_p (src))
a13d4ebf
AM
5262 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
5263 else
5264 ptr->invalid = 1;
5265 }
5266 }
5267 else
5268 invalidate_any_buried_refs (PATTERN (insn));
5269 }
5270 }
5271 }
5272}
5273
589005ff 5274/* Remove any references that have been either invalidated or are not in the
a13d4ebf
AM
5275 expression list for pre gcse. */
5276
5277static void
1d088dee 5278trim_ld_motion_mems (void)
a13d4ebf 5279{
b58b21d5
RS
5280 struct ls_expr * * last = & pre_ldst_mems;
5281 struct ls_expr * ptr = pre_ldst_mems;
a13d4ebf
AM
5282
5283 while (ptr != NULL)
5284 {
b58b21d5 5285 struct expr * expr;
589005ff 5286
a13d4ebf 5287 /* Delete if entry has been made invalid. */
b58b21d5 5288 if (! ptr->invalid)
a13d4ebf 5289 {
a13d4ebf 5290 /* Delete if we cannot find this mem in the expression list. */
b58b21d5 5291 unsigned int hash = ptr->hash_index % expr_hash_table.size;
589005ff 5292
b58b21d5
RS
5293 for (expr = expr_hash_table.table[hash];
5294 expr != NULL;
5295 expr = expr->next_same_hash)
5296 if (expr_equiv_p (expr->expr, ptr->pattern))
5297 break;
a13d4ebf
AM
5298 }
5299 else
b58b21d5
RS
5300 expr = (struct expr *) 0;
5301
5302 if (expr)
a13d4ebf
AM
5303 {
5304 /* Set the expression field if we are keeping it. */
a13d4ebf 5305 ptr->expr = expr;
b58b21d5 5306 last = & ptr->next;
a13d4ebf
AM
5307 ptr = ptr->next;
5308 }
b58b21d5
RS
5309 else
5310 {
5311 *last = ptr->next;
5312 free_ldst_entry (ptr);
5313 ptr = * last;
5314 }
a13d4ebf
AM
5315 }
5316
5317 /* Show the world what we've found. */
5318 if (gcse_file && pre_ldst_mems != NULL)
5319 print_ldst_list (gcse_file);
5320}
5321
5322/* This routine will take an expression which we are replacing with
5323 a reaching register, and update any stores that are needed if
5324 that expression is in the ld_motion list. Stores are updated by
a98ebe2e 5325 copying their SRC to the reaching register, and then storing
a13d4ebf
AM
5326 the reaching register into the store location. These keeps the
5327 correct value in the reaching register for the loads. */
5328
5329static void
1d088dee 5330update_ld_motion_stores (struct expr * expr)
a13d4ebf
AM
5331{
5332 struct ls_expr * mem_ptr;
5333
5334 if ((mem_ptr = find_rtx_in_ldst (expr->expr)))
5335 {
589005ff
KH
5336 /* We can try to find just the REACHED stores, but is shouldn't
5337 matter to set the reaching reg everywhere... some might be
a13d4ebf
AM
5338 dead and should be eliminated later. */
5339
4d3eb89a
HPN
5340 /* We replace (set mem expr) with (set reg expr) (set mem reg)
5341 where reg is the reaching reg used in the load. We checked in
5342 compute_ld_motion_mems that we can replace (set mem expr) with
5343 (set reg expr) in that insn. */
a13d4ebf 5344 rtx list = mem_ptr->stores;
589005ff 5345
a13d4ebf
AM
5346 for ( ; list != NULL_RTX; list = XEXP (list, 1))
5347 {
5348 rtx insn = XEXP (list, 0);
5349 rtx pat = PATTERN (insn);
5350 rtx src = SET_SRC (pat);
5351 rtx reg = expr->reaching_reg;
c57718d3 5352 rtx copy, new;
a13d4ebf
AM
5353
5354 /* If we've already copied it, continue. */
5355 if (expr->reaching_reg == src)
5356 continue;
589005ff 5357
a13d4ebf
AM
5358 if (gcse_file)
5359 {
5360 fprintf (gcse_file, "PRE: store updated with reaching reg ");
5361 print_rtl (gcse_file, expr->reaching_reg);
5362 fprintf (gcse_file, ":\n ");
5363 print_inline_rtx (gcse_file, insn, 8);
5364 fprintf (gcse_file, "\n");
5365 }
589005ff 5366
47a3dae1 5367 copy = gen_move_insn ( reg, copy_rtx (SET_SRC (pat)));
c57718d3
RK
5368 new = emit_insn_before (copy, insn);
5369 record_one_set (REGNO (reg), new);
a13d4ebf
AM
5370 SET_SRC (pat) = reg;
5371
5372 /* un-recognize this pattern since it's probably different now. */
5373 INSN_CODE (insn) = -1;
5374 gcse_create_count++;
5375 }
5376 }
5377}
5378\f
5379/* Store motion code. */
5380
47a3dae1
ZD
5381#define ANTIC_STORE_LIST(x) ((x)->loads)
5382#define AVAIL_STORE_LIST(x) ((x)->stores)
5383#define LAST_AVAIL_CHECK_FAILURE(x) ((x)->reaching_reg)
5384
589005ff 5385/* This is used to communicate the target bitvector we want to use in the
aaa4ca30 5386 reg_set_info routine when called via the note_stores mechanism. */
47a3dae1
ZD
5387static int * regvec;
5388
5389/* And current insn, for the same routine. */
5390static rtx compute_store_table_current_insn;
aaa4ca30 5391
a13d4ebf
AM
5392/* Used in computing the reverse edge graph bit vectors. */
5393static sbitmap * st_antloc;
5394
5395/* Global holding the number of store expressions we are dealing with. */
5396static int num_stores;
5397
01c43039
RE
5398/* Checks to set if we need to mark a register set. Called from
5399 note_stores. */
a13d4ebf 5400
aaa4ca30 5401static void
1d088dee 5402reg_set_info (rtx dest, rtx setter ATTRIBUTE_UNUSED,
01c43039 5403 void *data)
a13d4ebf 5404{
01c43039
RE
5405 sbitmap bb_reg = data;
5406
aaa4ca30
AJ
5407 if (GET_CODE (dest) == SUBREG)
5408 dest = SUBREG_REG (dest);
adfcce61 5409
7b1b4aed 5410 if (REG_P (dest))
01c43039
RE
5411 {
5412 regvec[REGNO (dest)] = INSN_UID (compute_store_table_current_insn);
5413 if (bb_reg)
5414 SET_BIT (bb_reg, REGNO (dest));
5415 }
5416}
5417
5418/* Clear any mark that says that this insn sets dest. Called from
5419 note_stores. */
5420
5421static void
5422reg_clear_last_set (rtx dest, rtx setter ATTRIBUTE_UNUSED,
5423 void *data)
5424{
5425 int *dead_vec = data;
5426
5427 if (GET_CODE (dest) == SUBREG)
5428 dest = SUBREG_REG (dest);
5429
7b1b4aed 5430 if (REG_P (dest) &&
01c43039
RE
5431 dead_vec[REGNO (dest)] == INSN_UID (compute_store_table_current_insn))
5432 dead_vec[REGNO (dest)] = 0;
a13d4ebf
AM
5433}
5434
47a3dae1
ZD
5435/* Return zero if some of the registers in list X are killed
5436 due to set of registers in bitmap REGS_SET. */
1d088dee 5437
47a3dae1 5438static bool
1d088dee 5439store_ops_ok (rtx x, int *regs_set)
47a3dae1
ZD
5440{
5441 rtx reg;
5442
5443 for (; x; x = XEXP (x, 1))
5444 {
5445 reg = XEXP (x, 0);
5446 if (regs_set[REGNO(reg)])
1d088dee 5447 return false;
47a3dae1 5448 }
a13d4ebf 5449
47a3dae1
ZD
5450 return true;
5451}
5452
5453/* Returns a list of registers mentioned in X. */
5454static rtx
1d088dee 5455extract_mentioned_regs (rtx x)
47a3dae1
ZD
5456{
5457 return extract_mentioned_regs_helper (x, NULL_RTX);
5458}
5459
5460/* Helper for extract_mentioned_regs; ACCUM is used to accumulate used
5461 registers. */
5462static rtx
1d088dee 5463extract_mentioned_regs_helper (rtx x, rtx accum)
a13d4ebf
AM
5464{
5465 int i;
5466 enum rtx_code code;
5467 const char * fmt;
5468
5469 /* Repeat is used to turn tail-recursion into iteration. */
5470 repeat:
5471
5472 if (x == 0)
47a3dae1 5473 return accum;
a13d4ebf
AM
5474
5475 code = GET_CODE (x);
5476 switch (code)
5477 {
5478 case REG:
47a3dae1 5479 return alloc_EXPR_LIST (0, x, accum);
a13d4ebf
AM
5480
5481 case MEM:
5482 x = XEXP (x, 0);
5483 goto repeat;
5484
5485 case PRE_DEC:
5486 case PRE_INC:
5487 case POST_DEC:
5488 case POST_INC:
47a3dae1 5489 /* We do not run this function with arguments having side effects. */
282899df 5490 gcc_unreachable ();
a13d4ebf
AM
5491
5492 case PC:
5493 case CC0: /*FIXME*/
5494 case CONST:
5495 case CONST_INT:
5496 case CONST_DOUBLE:
69ef87e2 5497 case CONST_VECTOR:
a13d4ebf
AM
5498 case SYMBOL_REF:
5499 case LABEL_REF:
5500 case ADDR_VEC:
5501 case ADDR_DIFF_VEC:
47a3dae1 5502 return accum;
a13d4ebf
AM
5503
5504 default:
5505 break;
5506 }
5507
5508 i = GET_RTX_LENGTH (code) - 1;
5509 fmt = GET_RTX_FORMAT (code);
589005ff 5510
a13d4ebf
AM
5511 for (; i >= 0; i--)
5512 {
5513 if (fmt[i] == 'e')
5514 {
5515 rtx tem = XEXP (x, i);
5516
5517 /* If we are about to do the last recursive call
47a3dae1 5518 needed at this level, change it into iteration. */
a13d4ebf
AM
5519 if (i == 0)
5520 {
5521 x = tem;
5522 goto repeat;
5523 }
589005ff 5524
47a3dae1 5525 accum = extract_mentioned_regs_helper (tem, accum);
a13d4ebf
AM
5526 }
5527 else if (fmt[i] == 'E')
5528 {
5529 int j;
589005ff 5530
a13d4ebf 5531 for (j = 0; j < XVECLEN (x, i); j++)
47a3dae1 5532 accum = extract_mentioned_regs_helper (XVECEXP (x, i, j), accum);
a13d4ebf
AM
5533 }
5534 }
5535
47a3dae1 5536 return accum;
a13d4ebf
AM
5537}
5538
47a3dae1
ZD
5539/* Determine whether INSN is MEM store pattern that we will consider moving.
5540 REGS_SET_BEFORE is bitmap of registers set before (and including) the
5541 current insn, REGS_SET_AFTER is bitmap of registers set after (and
5542 including) the insn in this basic block. We must be passing through BB from
5543 head to end, as we are using this fact to speed things up.
1d088dee 5544
47a3dae1
ZD
5545 The results are stored this way:
5546
5547 -- the first anticipatable expression is added into ANTIC_STORE_LIST
5548 -- if the processed expression is not anticipatable, NULL_RTX is added
5549 there instead, so that we can use it as indicator that no further
5550 expression of this type may be anticipatable
5551 -- if the expression is available, it is added as head of AVAIL_STORE_LIST;
5552 consequently, all of them but this head are dead and may be deleted.
5553 -- if the expression is not available, the insn due to that it fails to be
5554 available is stored in reaching_reg.
5555
5556 The things are complicated a bit by fact that there already may be stores
5557 to the same MEM from other blocks; also caller must take care of the
e0bb17a8 5558 necessary cleanup of the temporary markers after end of the basic block.
47a3dae1 5559 */
a13d4ebf
AM
5560
5561static void
1d088dee 5562find_moveable_store (rtx insn, int *regs_set_before, int *regs_set_after)
a13d4ebf
AM
5563{
5564 struct ls_expr * ptr;
47a3dae1
ZD
5565 rtx dest, set, tmp;
5566 int check_anticipatable, check_available;
5567 basic_block bb = BLOCK_FOR_INSN (insn);
a13d4ebf 5568
47a3dae1
ZD
5569 set = single_set (insn);
5570 if (!set)
a13d4ebf
AM
5571 return;
5572
47a3dae1 5573 dest = SET_DEST (set);
589005ff 5574
7b1b4aed 5575 if (! MEM_P (dest) || MEM_VOLATILE_P (dest)
a13d4ebf 5576 || GET_MODE (dest) == BLKmode)
aaa4ca30
AJ
5577 return;
5578
47a3dae1
ZD
5579 if (side_effects_p (dest))
5580 return;
aaa4ca30 5581
47a3dae1
ZD
5582 /* If we are handling exceptions, we must be careful with memory references
5583 that may trap. If we are not, the behavior is undefined, so we may just
5584 continue. */
94f24ddc 5585 if (flag_non_call_exceptions && may_trap_p (dest))
47a3dae1 5586 return;
1d088dee 5587
c2e2375e
UW
5588 /* Even if the destination cannot trap, the source may. In this case we'd
5589 need to handle updating the REG_EH_REGION note. */
5590 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
5591 return;
5592
a13d4ebf 5593 ptr = ldst_entry (dest);
47a3dae1
ZD
5594 if (!ptr->pattern_regs)
5595 ptr->pattern_regs = extract_mentioned_regs (dest);
5596
5597 /* Do not check for anticipatability if we either found one anticipatable
5598 store already, or tested for one and found out that it was killed. */
5599 check_anticipatable = 0;
5600 if (!ANTIC_STORE_LIST (ptr))
5601 check_anticipatable = 1;
5602 else
5603 {
5604 tmp = XEXP (ANTIC_STORE_LIST (ptr), 0);
5605 if (tmp != NULL_RTX
5606 && BLOCK_FOR_INSN (tmp) != bb)
5607 check_anticipatable = 1;
5608 }
5609 if (check_anticipatable)
5610 {
5611 if (store_killed_before (dest, ptr->pattern_regs, insn, bb, regs_set_before))
5612 tmp = NULL_RTX;
5613 else
5614 tmp = insn;
5615 ANTIC_STORE_LIST (ptr) = alloc_INSN_LIST (tmp,
5616 ANTIC_STORE_LIST (ptr));
5617 }
a13d4ebf 5618
e0bb17a8 5619 /* It is not necessary to check whether store is available if we did
47a3dae1
ZD
5620 it successfully before; if we failed before, do not bother to check
5621 until we reach the insn that caused us to fail. */
5622 check_available = 0;
5623 if (!AVAIL_STORE_LIST (ptr))
5624 check_available = 1;
5625 else
5626 {
5627 tmp = XEXP (AVAIL_STORE_LIST (ptr), 0);
5628 if (BLOCK_FOR_INSN (tmp) != bb)
5629 check_available = 1;
5630 }
5631 if (check_available)
5632 {
5633 /* Check that we have already reached the insn at that the check
5634 failed last time. */
5635 if (LAST_AVAIL_CHECK_FAILURE (ptr))
5636 {
a813c111 5637 for (tmp = BB_END (bb);
47a3dae1
ZD
5638 tmp != insn && tmp != LAST_AVAIL_CHECK_FAILURE (ptr);
5639 tmp = PREV_INSN (tmp))
5640 continue;
5641 if (tmp == insn)
5642 check_available = 0;
5643 }
5644 else
5645 check_available = store_killed_after (dest, ptr->pattern_regs, insn,
5646 bb, regs_set_after,
5647 &LAST_AVAIL_CHECK_FAILURE (ptr));
5648 }
5649 if (!check_available)
5650 AVAIL_STORE_LIST (ptr) = alloc_INSN_LIST (insn, AVAIL_STORE_LIST (ptr));
5651}
1d088dee 5652
47a3dae1 5653/* Find available and anticipatable stores. */
a13d4ebf
AM
5654
5655static int
1d088dee 5656compute_store_table (void)
a13d4ebf 5657{
e0082a72
ZD
5658 int ret;
5659 basic_block bb;
aaa4ca30 5660 unsigned regno;
47a3dae1
ZD
5661 rtx insn, pat, tmp;
5662 int *last_set_in, *already_set;
5663 struct ls_expr * ptr, **prev_next_ptr_ptr;
aaa4ca30 5664
a13d4ebf
AM
5665 max_gcse_regno = max_reg_num ();
5666
703ad42b 5667 reg_set_in_block = sbitmap_vector_alloc (last_basic_block,
aaa4ca30 5668 max_gcse_regno);
d55bc081 5669 sbitmap_vector_zero (reg_set_in_block, last_basic_block);
a13d4ebf 5670 pre_ldst_mems = 0;
01c43039 5671 last_set_in = xcalloc (max_gcse_regno, sizeof (int));
47a3dae1 5672 already_set = xmalloc (sizeof (int) * max_gcse_regno);
aaa4ca30 5673
a13d4ebf 5674 /* Find all the stores we care about. */
e0082a72 5675 FOR_EACH_BB (bb)
a13d4ebf 5676 {
47a3dae1 5677 /* First compute the registers set in this block. */
47a3dae1
ZD
5678 regvec = last_set_in;
5679
a813c111
SB
5680 for (insn = BB_HEAD (bb);
5681 insn != NEXT_INSN (BB_END (bb));
47a3dae1
ZD
5682 insn = NEXT_INSN (insn))
5683 {
5684 if (! INSN_P (insn))
5685 continue;
5686
7b1b4aed 5687 if (CALL_P (insn))
47a3dae1 5688 {
47a3dae1 5689 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6e14af16 5690 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
01c43039
RE
5691 {
5692 last_set_in[regno] = INSN_UID (insn);
5693 SET_BIT (reg_set_in_block[bb->index], regno);
5694 }
47a3dae1
ZD
5695 }
5696
5697 pat = PATTERN (insn);
5698 compute_store_table_current_insn = insn;
01c43039 5699 note_stores (pat, reg_set_info, reg_set_in_block[bb->index]);
47a3dae1
ZD
5700 }
5701
47a3dae1
ZD
5702 /* Now find the stores. */
5703 memset (already_set, 0, sizeof (int) * max_gcse_regno);
5704 regvec = already_set;
a813c111
SB
5705 for (insn = BB_HEAD (bb);
5706 insn != NEXT_INSN (BB_END (bb));
47a3dae1 5707 insn = NEXT_INSN (insn))
a13d4ebf 5708 {
19652adf 5709 if (! INSN_P (insn))
a13d4ebf
AM
5710 continue;
5711
7b1b4aed 5712 if (CALL_P (insn))
aaa4ca30
AJ
5713 {
5714 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6e14af16 5715 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
47a3dae1 5716 already_set[regno] = 1;
aaa4ca30 5717 }
589005ff 5718
a13d4ebf 5719 pat = PATTERN (insn);
aaa4ca30 5720 note_stores (pat, reg_set_info, NULL);
589005ff 5721
a13d4ebf 5722 /* Now that we've marked regs, look for stores. */
47a3dae1
ZD
5723 find_moveable_store (insn, already_set, last_set_in);
5724
5725 /* Unmark regs that are no longer set. */
01c43039
RE
5726 compute_store_table_current_insn = insn;
5727 note_stores (pat, reg_clear_last_set, last_set_in);
7b1b4aed 5728 if (CALL_P (insn))
01c43039 5729 {
01c43039 5730 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6e14af16 5731 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno)
01c43039
RE
5732 && last_set_in[regno] == INSN_UID (insn))
5733 last_set_in[regno] = 0;
5734 }
47a3dae1
ZD
5735 }
5736
01c43039
RE
5737#ifdef ENABLE_CHECKING
5738 /* last_set_in should now be all-zero. */
5739 for (regno = 0; regno < max_gcse_regno; regno++)
282899df 5740 gcc_assert (!last_set_in[regno]);
01c43039
RE
5741#endif
5742
47a3dae1
ZD
5743 /* Clear temporary marks. */
5744 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
5745 {
5746 LAST_AVAIL_CHECK_FAILURE(ptr) = NULL_RTX;
5747 if (ANTIC_STORE_LIST (ptr)
5748 && (tmp = XEXP (ANTIC_STORE_LIST (ptr), 0)) == NULL_RTX)
5749 ANTIC_STORE_LIST (ptr) = XEXP (ANTIC_STORE_LIST (ptr), 1);
5750 }
5751 }
5752
5753 /* Remove the stores that are not available anywhere, as there will
5754 be no opportunity to optimize them. */
5755 for (ptr = pre_ldst_mems, prev_next_ptr_ptr = &pre_ldst_mems;
5756 ptr != NULL;
5757 ptr = *prev_next_ptr_ptr)
5758 {
5759 if (!AVAIL_STORE_LIST (ptr))
5760 {
5761 *prev_next_ptr_ptr = ptr->next;
5762 free_ldst_entry (ptr);
a13d4ebf 5763 }
47a3dae1
ZD
5764 else
5765 prev_next_ptr_ptr = &ptr->next;
a13d4ebf
AM
5766 }
5767
5768 ret = enumerate_ldsts ();
589005ff 5769
a13d4ebf
AM
5770 if (gcse_file)
5771 {
47a3dae1 5772 fprintf (gcse_file, "ST_avail and ST_antic (shown under loads..)\n");
a13d4ebf
AM
5773 print_ldst_list (gcse_file);
5774 }
589005ff 5775
47a3dae1
ZD
5776 free (last_set_in);
5777 free (already_set);
a13d4ebf
AM
5778 return ret;
5779}
5780
3b14e3af
ZD
5781/* Check to see if the load X is aliased with STORE_PATTERN.
5782 AFTER is true if we are checking the case when STORE_PATTERN occurs
5783 after the X. */
a13d4ebf 5784
47a3dae1 5785static bool
3b14e3af 5786load_kills_store (rtx x, rtx store_pattern, int after)
a13d4ebf 5787{
3b14e3af
ZD
5788 if (after)
5789 return anti_dependence (x, store_pattern);
5790 else
5791 return true_dependence (store_pattern, GET_MODE (store_pattern), x,
5792 rtx_addr_varies_p);
a13d4ebf
AM
5793}
5794
589005ff 5795/* Go through the entire insn X, looking for any loads which might alias
3b14e3af
ZD
5796 STORE_PATTERN. Return true if found.
5797 AFTER is true if we are checking the case when STORE_PATTERN occurs
5798 after the insn X. */
a13d4ebf 5799
47a3dae1 5800static bool
3b14e3af 5801find_loads (rtx x, rtx store_pattern, int after)
a13d4ebf
AM
5802{
5803 const char * fmt;
8e42ace1 5804 int i, j;
47a3dae1 5805 int ret = false;
a13d4ebf 5806
24a28584 5807 if (!x)
47a3dae1 5808 return false;
24a28584 5809
589005ff 5810 if (GET_CODE (x) == SET)
a13d4ebf
AM
5811 x = SET_SRC (x);
5812
7b1b4aed 5813 if (MEM_P (x))
a13d4ebf 5814 {
3b14e3af 5815 if (load_kills_store (x, store_pattern, after))
47a3dae1 5816 return true;
a13d4ebf
AM
5817 }
5818
5819 /* Recursively process the insn. */
5820 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 5821
a13d4ebf
AM
5822 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0 && !ret; i--)
5823 {
5824 if (fmt[i] == 'e')
3b14e3af 5825 ret |= find_loads (XEXP (x, i), store_pattern, after);
a13d4ebf
AM
5826 else if (fmt[i] == 'E')
5827 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3b14e3af 5828 ret |= find_loads (XVECEXP (x, i, j), store_pattern, after);
a13d4ebf
AM
5829 }
5830 return ret;
5831}
5832
589005ff 5833/* Check if INSN kills the store pattern X (is aliased with it).
3b14e3af 5834 AFTER is true if we are checking the case when store X occurs
3f117656 5835 after the insn. Return true if it does. */
a13d4ebf 5836
47a3dae1 5837static bool
3b14e3af 5838store_killed_in_insn (rtx x, rtx x_regs, rtx insn, int after)
a13d4ebf 5839{
d088acea 5840 rtx reg, base, note;
94f24ddc 5841
735e8085 5842 if (!INSN_P (insn))
47a3dae1 5843 return false;
589005ff 5844
7b1b4aed 5845 if (CALL_P (insn))
a13d4ebf 5846 {
1218665b
JJ
5847 /* A normal or pure call might read from pattern,
5848 but a const call will not. */
47a3dae1
ZD
5849 if (! CONST_OR_PURE_CALL_P (insn) || pure_call_p (insn))
5850 return true;
5851
94f24ddc
ZD
5852 /* But even a const call reads its parameters. Check whether the
5853 base of some of registers used in mem is stack pointer. */
5854 for (reg = x_regs; reg; reg = XEXP (reg, 1))
5855 {
bc083e18 5856 base = find_base_term (XEXP (reg, 0));
94f24ddc
ZD
5857 if (!base
5858 || (GET_CODE (base) == ADDRESS
5859 && GET_MODE (base) == Pmode
5860 && XEXP (base, 0) == stack_pointer_rtx))
5861 return true;
5862 }
47a3dae1
ZD
5863
5864 return false;
a13d4ebf 5865 }
589005ff 5866
a13d4ebf
AM
5867 if (GET_CODE (PATTERN (insn)) == SET)
5868 {
5869 rtx pat = PATTERN (insn);
3b14e3af
ZD
5870 rtx dest = SET_DEST (pat);
5871
46d096a3 5872 if (GET_CODE (dest) == ZERO_EXTRACT)
3b14e3af
ZD
5873 dest = XEXP (dest, 0);
5874
a13d4ebf 5875 /* Check for memory stores to aliased objects. */
7b1b4aed 5876 if (MEM_P (dest)
3b14e3af
ZD
5877 && !expr_equiv_p (dest, x))
5878 {
5879 if (after)
5880 {
5881 if (output_dependence (dest, x))
5882 return true;
5883 }
5884 else
5885 {
5886 if (output_dependence (x, dest))
5887 return true;
5888 }
5889 }
d088acea
ZD
5890 if (find_loads (SET_SRC (pat), x, after))
5891 return true;
a13d4ebf 5892 }
d088acea
ZD
5893 else if (find_loads (PATTERN (insn), x, after))
5894 return true;
5895
5896 /* If this insn has a REG_EQUAL or REG_EQUIV note referencing a memory
5897 location aliased with X, then this insn kills X. */
5898 note = find_reg_equal_equiv_note (insn);
5899 if (! note)
5900 return false;
5901 note = XEXP (note, 0);
5902
5903 /* However, if the note represents a must alias rather than a may
5904 alias relationship, then it does not kill X. */
5905 if (expr_equiv_p (note, x))
5906 return false;
5907
5908 /* See if there are any aliased loads in the note. */
5909 return find_loads (note, x, after);
a13d4ebf
AM
5910}
5911
47a3dae1
ZD
5912/* Returns true if the expression X is loaded or clobbered on or after INSN
5913 within basic block BB. REGS_SET_AFTER is bitmap of registers set in
5914 or after the insn. X_REGS is list of registers mentioned in X. If the store
5915 is killed, return the last insn in that it occurs in FAIL_INSN. */
a13d4ebf 5916
47a3dae1 5917static bool
1d088dee
AJ
5918store_killed_after (rtx x, rtx x_regs, rtx insn, basic_block bb,
5919 int *regs_set_after, rtx *fail_insn)
a13d4ebf 5920{
a813c111 5921 rtx last = BB_END (bb), act;
aaa4ca30 5922
47a3dae1 5923 if (!store_ops_ok (x_regs, regs_set_after))
1d088dee 5924 {
47a3dae1
ZD
5925 /* We do not know where it will happen. */
5926 if (fail_insn)
5927 *fail_insn = NULL_RTX;
5928 return true;
5929 }
a13d4ebf 5930
47a3dae1
ZD
5931 /* Scan from the end, so that fail_insn is determined correctly. */
5932 for (act = last; act != PREV_INSN (insn); act = PREV_INSN (act))
3b14e3af 5933 if (store_killed_in_insn (x, x_regs, act, false))
47a3dae1
ZD
5934 {
5935 if (fail_insn)
5936 *fail_insn = act;
5937 return true;
5938 }
589005ff 5939
47a3dae1 5940 return false;
a13d4ebf 5941}
1d088dee 5942
47a3dae1
ZD
5943/* Returns true if the expression X is loaded or clobbered on or before INSN
5944 within basic block BB. X_REGS is list of registers mentioned in X.
5945 REGS_SET_BEFORE is bitmap of registers set before or in this insn. */
5946static bool
1d088dee
AJ
5947store_killed_before (rtx x, rtx x_regs, rtx insn, basic_block bb,
5948 int *regs_set_before)
a13d4ebf 5949{
a813c111 5950 rtx first = BB_HEAD (bb);
a13d4ebf 5951
47a3dae1
ZD
5952 if (!store_ops_ok (x_regs, regs_set_before))
5953 return true;
a13d4ebf 5954
47a3dae1 5955 for ( ; insn != PREV_INSN (first); insn = PREV_INSN (insn))
3b14e3af 5956 if (store_killed_in_insn (x, x_regs, insn, true))
47a3dae1 5957 return true;
589005ff 5958
47a3dae1 5959 return false;
a13d4ebf 5960}
1d088dee 5961
47a3dae1
ZD
5962/* Fill in available, anticipatable, transparent and kill vectors in
5963 STORE_DATA, based on lists of available and anticipatable stores. */
a13d4ebf 5964static void
1d088dee 5965build_store_vectors (void)
a13d4ebf 5966{
47a3dae1
ZD
5967 basic_block bb;
5968 int *regs_set_in_block;
a13d4ebf
AM
5969 rtx insn, st;
5970 struct ls_expr * ptr;
47a3dae1 5971 unsigned regno;
a13d4ebf
AM
5972
5973 /* Build the gen_vector. This is any store in the table which is not killed
5974 by aliasing later in its block. */
703ad42b 5975 ae_gen = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 5976 sbitmap_vector_zero (ae_gen, last_basic_block);
a13d4ebf 5977
703ad42b 5978 st_antloc = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 5979 sbitmap_vector_zero (st_antloc, last_basic_block);
aaa4ca30 5980
a13d4ebf 5981 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
589005ff 5982 {
47a3dae1 5983 for (st = AVAIL_STORE_LIST (ptr); st != NULL; st = XEXP (st, 1))
a13d4ebf
AM
5984 {
5985 insn = XEXP (st, 0);
e2d2ed72 5986 bb = BLOCK_FOR_INSN (insn);
589005ff 5987
47a3dae1
ZD
5988 /* If we've already seen an available expression in this block,
5989 we can delete this one (It occurs earlier in the block). We'll
5990 copy the SRC expression to an unused register in case there
5991 are any side effects. */
5992 if (TEST_BIT (ae_gen[bb->index], ptr->index))
a13d4ebf 5993 {
47a3dae1
ZD
5994 rtx r = gen_reg_rtx (GET_MODE (ptr->pattern));
5995 if (gcse_file)
5996 fprintf (gcse_file, "Removing redundant store:\n");
d088acea 5997 replace_store_insn (r, XEXP (st, 0), bb, ptr);
47a3dae1 5998 continue;
a13d4ebf 5999 }
47a3dae1 6000 SET_BIT (ae_gen[bb->index], ptr->index);
a13d4ebf 6001 }
589005ff 6002
47a3dae1
ZD
6003 for (st = ANTIC_STORE_LIST (ptr); st != NULL; st = XEXP (st, 1))
6004 {
6005 insn = XEXP (st, 0);
6006 bb = BLOCK_FOR_INSN (insn);
6007 SET_BIT (st_antloc[bb->index], ptr->index);
6008 }
a13d4ebf 6009 }
589005ff 6010
703ad42b 6011 ae_kill = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 6012 sbitmap_vector_zero (ae_kill, last_basic_block);
a13d4ebf 6013
703ad42b 6014 transp = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 6015 sbitmap_vector_zero (transp, last_basic_block);
47a3dae1 6016 regs_set_in_block = xmalloc (sizeof (int) * max_gcse_regno);
a13d4ebf 6017
47a3dae1
ZD
6018 FOR_EACH_BB (bb)
6019 {
6020 for (regno = 0; regno < max_gcse_regno; regno++)
6021 regs_set_in_block[regno] = TEST_BIT (reg_set_in_block[bb->index], regno);
6022
6023 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
6024 {
a813c111 6025 if (store_killed_after (ptr->pattern, ptr->pattern_regs, BB_HEAD (bb),
47a3dae1
ZD
6026 bb, regs_set_in_block, NULL))
6027 {
e0bb17a8 6028 /* It should not be necessary to consider the expression
47a3dae1
ZD
6029 killed if it is both anticipatable and available. */
6030 if (!TEST_BIT (st_antloc[bb->index], ptr->index)
6031 || !TEST_BIT (ae_gen[bb->index], ptr->index))
6032 SET_BIT (ae_kill[bb->index], ptr->index);
1d088dee
AJ
6033 }
6034 else
6035 SET_BIT (transp[bb->index], ptr->index);
6036 }
47a3dae1
ZD
6037 }
6038
6039 free (regs_set_in_block);
aaa4ca30 6040
589005ff 6041 if (gcse_file)
aaa4ca30 6042 {
d55bc081
ZD
6043 dump_sbitmap_vector (gcse_file, "st_antloc", "", st_antloc, last_basic_block);
6044 dump_sbitmap_vector (gcse_file, "st_kill", "", ae_kill, last_basic_block);
6045 dump_sbitmap_vector (gcse_file, "Transpt", "", transp, last_basic_block);
6046 dump_sbitmap_vector (gcse_file, "st_avloc", "", ae_gen, last_basic_block);
a13d4ebf
AM
6047 }
6048}
6049
fbe5a4a6 6050/* Insert an instruction at the beginning of a basic block, and update
a813c111 6051 the BB_HEAD if needed. */
a13d4ebf 6052
589005ff 6053static void
1d088dee 6054insert_insn_start_bb (rtx insn, basic_block bb)
a13d4ebf
AM
6055{
6056 /* Insert at start of successor block. */
a813c111
SB
6057 rtx prev = PREV_INSN (BB_HEAD (bb));
6058 rtx before = BB_HEAD (bb);
a13d4ebf
AM
6059 while (before != 0)
6060 {
7b1b4aed
SB
6061 if (! LABEL_P (before)
6062 && (! NOTE_P (before)
a13d4ebf
AM
6063 || NOTE_LINE_NUMBER (before) != NOTE_INSN_BASIC_BLOCK))
6064 break;
6065 prev = before;
a813c111 6066 if (prev == BB_END (bb))
a13d4ebf
AM
6067 break;
6068 before = NEXT_INSN (before);
6069 }
6070
a7102479 6071 insn = emit_insn_after_noloc (insn, prev);
a13d4ebf 6072
a13d4ebf
AM
6073 if (gcse_file)
6074 {
6075 fprintf (gcse_file, "STORE_MOTION insert store at start of BB %d:\n",
0b17ab2f 6076 bb->index);
a13d4ebf
AM
6077 print_inline_rtx (gcse_file, insn, 6);
6078 fprintf (gcse_file, "\n");
6079 }
6080}
6081
6082/* This routine will insert a store on an edge. EXPR is the ldst entry for
cc2902df 6083 the memory reference, and E is the edge to insert it on. Returns nonzero
a13d4ebf
AM
6084 if an edge insertion was performed. */
6085
6086static int
1d088dee 6087insert_store (struct ls_expr * expr, edge e)
a13d4ebf
AM
6088{
6089 rtx reg, insn;
e2d2ed72 6090 basic_block bb;
a13d4ebf 6091 edge tmp;
628f6a4e 6092 edge_iterator ei;
a13d4ebf
AM
6093
6094 /* We did all the deleted before this insert, so if we didn't delete a
6095 store, then we haven't set the reaching reg yet either. */
6096 if (expr->reaching_reg == NULL_RTX)
6097 return 0;
6098
a0c8285b
JH
6099 if (e->flags & EDGE_FAKE)
6100 return 0;
6101
a13d4ebf 6102 reg = expr->reaching_reg;
47a3dae1 6103 insn = gen_move_insn (copy_rtx (expr->pattern), reg);
589005ff 6104
a13d4ebf
AM
6105 /* If we are inserting this expression on ALL predecessor edges of a BB,
6106 insert it at the start of the BB, and reset the insert bits on the other
ff7cc307 6107 edges so we don't try to insert it on the other edges. */
e2d2ed72 6108 bb = e->dest;
628f6a4e 6109 FOR_EACH_EDGE (tmp, ei, e->dest->preds)
3f2eae23 6110 if (!(tmp->flags & EDGE_FAKE))
a0c8285b
JH
6111 {
6112 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
282899df
NS
6113
6114 gcc_assert (index != EDGE_INDEX_NO_EDGE);
a0c8285b
JH
6115 if (! TEST_BIT (pre_insert_map[index], expr->index))
6116 break;
6117 }
a13d4ebf
AM
6118
6119 /* If tmp is NULL, we found an insertion on every edge, blank the
6120 insertion vector for these edges, and insert at the start of the BB. */
e2d2ed72 6121 if (!tmp && bb != EXIT_BLOCK_PTR)
a13d4ebf 6122 {
628f6a4e 6123 FOR_EACH_EDGE (tmp, ei, e->dest->preds)
a13d4ebf
AM
6124 {
6125 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
6126 RESET_BIT (pre_insert_map[index], expr->index);
6127 }
6128 insert_insn_start_bb (insn, bb);
6129 return 0;
6130 }
589005ff 6131
b16aa8a5
RK
6132 /* We can't put stores in the front of blocks pointed to by abnormal
6133 edges since that may put a store where one didn't used to be. */
6134 gcc_assert (!(e->flags & EDGE_ABNORMAL));
a13d4ebf
AM
6135
6136 insert_insn_on_edge (insn, e);
589005ff 6137
a13d4ebf
AM
6138 if (gcse_file)
6139 {
6140 fprintf (gcse_file, "STORE_MOTION insert insn on edge (%d, %d):\n",
0b17ab2f 6141 e->src->index, e->dest->index);
a13d4ebf
AM
6142 print_inline_rtx (gcse_file, insn, 6);
6143 fprintf (gcse_file, "\n");
6144 }
589005ff 6145
a13d4ebf
AM
6146 return 1;
6147}
6148
d088acea
ZD
6149/* Remove any REG_EQUAL or REG_EQUIV notes containing a reference to the
6150 memory location in SMEXPR set in basic block BB.
6151
6152 This could be rather expensive. */
6153
6154static void
6155remove_reachable_equiv_notes (basic_block bb, struct ls_expr *smexpr)
6156{
628f6a4e
BE
6157 edge_iterator *stack, ei;
6158 int sp;
6159 edge act;
d088acea 6160 sbitmap visited = sbitmap_alloc (last_basic_block);
d088acea
ZD
6161 rtx last, insn, note;
6162 rtx mem = smexpr->pattern;
6163
628f6a4e
BE
6164 stack = xmalloc (sizeof (edge_iterator) * n_basic_blocks);
6165 sp = 0;
6166 ei = ei_start (bb->succs);
6167
d088acea 6168 sbitmap_zero (visited);
d088acea 6169
f76ccf60 6170 act = (EDGE_COUNT (ei_container (ei)) > 0 ? EDGE_I (ei_container (ei), 0) : NULL);
d088acea
ZD
6171 while (1)
6172 {
6173 if (!act)
6174 {
628f6a4e 6175 if (!sp)
d088acea
ZD
6176 {
6177 free (stack);
6178 sbitmap_free (visited);
6179 return;
6180 }
628f6a4e 6181 act = ei_edge (stack[--sp]);
d088acea
ZD
6182 }
6183 bb = act->dest;
7b1b4aed 6184
d088acea 6185 if (bb == EXIT_BLOCK_PTR
d1c6a401 6186 || TEST_BIT (visited, bb->index))
d088acea 6187 {
628f6a4e
BE
6188 if (!ei_end_p (ei))
6189 ei_next (&ei);
6190 act = (! ei_end_p (ei)) ? ei_edge (ei) : NULL;
d088acea
ZD
6191 continue;
6192 }
6193 SET_BIT (visited, bb->index);
6194
6195 if (TEST_BIT (st_antloc[bb->index], smexpr->index))
6196 {
6197 for (last = ANTIC_STORE_LIST (smexpr);
6198 BLOCK_FOR_INSN (XEXP (last, 0)) != bb;
6199 last = XEXP (last, 1))
6200 continue;
6201 last = XEXP (last, 0);
6202 }
6203 else
a813c111 6204 last = NEXT_INSN (BB_END (bb));
7b1b4aed 6205
a813c111 6206 for (insn = BB_HEAD (bb); insn != last; insn = NEXT_INSN (insn))
d088acea
ZD
6207 if (INSN_P (insn))
6208 {
6209 note = find_reg_equal_equiv_note (insn);
6210 if (!note || !expr_equiv_p (XEXP (note, 0), mem))
6211 continue;
6212
6213 if (gcse_file)
6214 fprintf (gcse_file, "STORE_MOTION drop REG_EQUAL note at insn %d:\n",
6215 INSN_UID (insn));
6216 remove_note (insn, note);
6217 }
628f6a4e
BE
6218
6219 if (!ei_end_p (ei))
6220 ei_next (&ei);
6221 act = (! ei_end_p (ei)) ? ei_edge (ei) : NULL;
6222
6223 if (EDGE_COUNT (bb->succs) > 0)
d088acea
ZD
6224 {
6225 if (act)
628f6a4e
BE
6226 stack[sp++] = ei;
6227 ei = ei_start (bb->succs);
f76ccf60 6228 act = (EDGE_COUNT (ei_container (ei)) > 0 ? EDGE_I (ei_container (ei), 0) : NULL);
d088acea
ZD
6229 }
6230 }
6231}
6232
a13d4ebf
AM
6233/* This routine will replace a store with a SET to a specified register. */
6234
6235static void
d088acea 6236replace_store_insn (rtx reg, rtx del, basic_block bb, struct ls_expr *smexpr)
a13d4ebf 6237{
d7fe1183 6238 rtx insn, mem, note, set, ptr, pair;
589005ff 6239
d088acea 6240 mem = smexpr->pattern;
9a318d30 6241 insn = gen_move_insn (reg, SET_SRC (single_set (del)));
a13d4ebf 6242 insn = emit_insn_after (insn, del);
589005ff 6243
a13d4ebf
AM
6244 if (gcse_file)
6245 {
589005ff 6246 fprintf (gcse_file,
0b17ab2f 6247 "STORE_MOTION delete insn in BB %d:\n ", bb->index);
a13d4ebf 6248 print_inline_rtx (gcse_file, del, 6);
8e42ace1 6249 fprintf (gcse_file, "\nSTORE MOTION replaced with insn:\n ");
a13d4ebf 6250 print_inline_rtx (gcse_file, insn, 6);
8e42ace1 6251 fprintf (gcse_file, "\n");
a13d4ebf 6252 }
589005ff 6253
d088acea
ZD
6254 for (ptr = ANTIC_STORE_LIST (smexpr); ptr; ptr = XEXP (ptr, 1))
6255 if (XEXP (ptr, 0) == del)
6256 {
6257 XEXP (ptr, 0) = insn;
6258 break;
6259 }
d7fe1183
ZD
6260
6261 /* Move the notes from the deleted insn to its replacement, and patch
6262 up the LIBCALL notes. */
6263 REG_NOTES (insn) = REG_NOTES (del);
6264
6265 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
6266 if (note)
6267 {
6268 pair = XEXP (note, 0);
6269 note = find_reg_note (pair, REG_LIBCALL, NULL_RTX);
6270 XEXP (note, 0) = insn;
6271 }
6272 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
6273 if (note)
6274 {
6275 pair = XEXP (note, 0);
6276 note = find_reg_note (pair, REG_RETVAL, NULL_RTX);
6277 XEXP (note, 0) = insn;
6278 }
6279
49ce134f 6280 delete_insn (del);
d088acea
ZD
6281
6282 /* Now we must handle REG_EQUAL notes whose contents is equal to the mem;
6283 they are no longer accurate provided that they are reached by this
6284 definition, so drop them. */
a813c111 6285 for (; insn != NEXT_INSN (BB_END (bb)); insn = NEXT_INSN (insn))
d088acea
ZD
6286 if (INSN_P (insn))
6287 {
6288 set = single_set (insn);
6289 if (!set)
6290 continue;
6291 if (expr_equiv_p (SET_DEST (set), mem))
6292 return;
6293 note = find_reg_equal_equiv_note (insn);
6294 if (!note || !expr_equiv_p (XEXP (note, 0), mem))
6295 continue;
6296
6297 if (gcse_file)
6298 fprintf (gcse_file, "STORE_MOTION drop REG_EQUAL note at insn %d:\n",
6299 INSN_UID (insn));
6300 remove_note (insn, note);
6301 }
6302 remove_reachable_equiv_notes (bb, smexpr);
a13d4ebf
AM
6303}
6304
6305
6306/* Delete a store, but copy the value that would have been stored into
6307 the reaching_reg for later storing. */
6308
6309static void
1d088dee 6310delete_store (struct ls_expr * expr, basic_block bb)
a13d4ebf
AM
6311{
6312 rtx reg, i, del;
6313
6314 if (expr->reaching_reg == NULL_RTX)
6315 expr->reaching_reg = gen_reg_rtx (GET_MODE (expr->pattern));
a13d4ebf 6316
a13d4ebf 6317 reg = expr->reaching_reg;
589005ff 6318
a13d4ebf
AM
6319 for (i = AVAIL_STORE_LIST (expr); i; i = XEXP (i, 1))
6320 {
6321 del = XEXP (i, 0);
e2d2ed72 6322 if (BLOCK_FOR_INSN (del) == bb)
a13d4ebf 6323 {
589005ff 6324 /* We know there is only one since we deleted redundant
a13d4ebf 6325 ones during the available computation. */
d088acea 6326 replace_store_insn (reg, del, bb, expr);
a13d4ebf
AM
6327 break;
6328 }
6329 }
6330}
6331
6332/* Free memory used by store motion. */
6333
589005ff 6334static void
1d088dee 6335free_store_memory (void)
a13d4ebf
AM
6336{
6337 free_ldst_mems ();
589005ff 6338
a13d4ebf 6339 if (ae_gen)
5a660bff 6340 sbitmap_vector_free (ae_gen);
a13d4ebf 6341 if (ae_kill)
5a660bff 6342 sbitmap_vector_free (ae_kill);
a13d4ebf 6343 if (transp)
5a660bff 6344 sbitmap_vector_free (transp);
a13d4ebf 6345 if (st_antloc)
5a660bff 6346 sbitmap_vector_free (st_antloc);
a13d4ebf 6347 if (pre_insert_map)
5a660bff 6348 sbitmap_vector_free (pre_insert_map);
a13d4ebf 6349 if (pre_delete_map)
5a660bff 6350 sbitmap_vector_free (pre_delete_map);
aaa4ca30
AJ
6351 if (reg_set_in_block)
6352 sbitmap_vector_free (reg_set_in_block);
589005ff 6353
a13d4ebf
AM
6354 ae_gen = ae_kill = transp = st_antloc = NULL;
6355 pre_insert_map = pre_delete_map = reg_set_in_block = NULL;
6356}
6357
6358/* Perform store motion. Much like gcse, except we move expressions the
6359 other way by looking at the flowgraph in reverse. */
6360
6361static void
1d088dee 6362store_motion (void)
a13d4ebf 6363{
e0082a72 6364 basic_block bb;
0b17ab2f 6365 int x;
a13d4ebf 6366 struct ls_expr * ptr;
adfcce61 6367 int update_flow = 0;
aaa4ca30 6368
a13d4ebf
AM
6369 if (gcse_file)
6370 {
6371 fprintf (gcse_file, "before store motion\n");
6372 print_rtl (gcse_file, get_insns ());
6373 }
6374
a13d4ebf 6375 init_alias_analysis ();
aaa4ca30 6376
47a3dae1 6377 /* Find all the available and anticipatable stores. */
a13d4ebf
AM
6378 num_stores = compute_store_table ();
6379 if (num_stores == 0)
6380 {
aaa4ca30 6381 sbitmap_vector_free (reg_set_in_block);
a13d4ebf
AM
6382 end_alias_analysis ();
6383 return;
6384 }
6385
47a3dae1 6386 /* Now compute kill & transp vectors. */
a13d4ebf 6387 build_store_vectors ();
47a3dae1 6388 add_noreturn_fake_exit_edges ();
2a868ea4 6389 connect_infinite_loops_to_exit ();
a13d4ebf 6390
589005ff
KH
6391 edge_list = pre_edge_rev_lcm (gcse_file, num_stores, transp, ae_gen,
6392 st_antloc, ae_kill, &pre_insert_map,
a13d4ebf
AM
6393 &pre_delete_map);
6394
6395 /* Now we want to insert the new stores which are going to be needed. */
6396 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
6397 {
b16aa8a5
RK
6398 /* If any of the edges we have above are abnormal, we can't move this
6399 store. */
6400 for (x = NUM_EDGES (edge_list) - 1; x >= 0; x--)
6401 if (TEST_BIT (pre_insert_map[x], ptr->index)
6402 && (INDEX_EDGE (edge_list, x)->flags & EDGE_ABNORMAL))
6403 break;
6404
6405 if (x >= 0)
6406 {
6407 if (gcse_file != NULL)
6408 fprintf (gcse_file,
6409 "Can't replace store %d: abnormal edge from %d to %d\n",
6410 ptr->index, INDEX_EDGE (edge_list, x)->src->index,
6411 INDEX_EDGE (edge_list, x)->dest->index);
6412 continue;
6413 }
6414
6415 /* Now we want to insert the new stores which are going to be needed. */
6416
e0082a72
ZD
6417 FOR_EACH_BB (bb)
6418 if (TEST_BIT (pre_delete_map[bb->index], ptr->index))
6419 delete_store (ptr, bb);
a13d4ebf 6420
0b17ab2f
RH
6421 for (x = 0; x < NUM_EDGES (edge_list); x++)
6422 if (TEST_BIT (pre_insert_map[x], ptr->index))
6423 update_flow |= insert_store (ptr, INDEX_EDGE (edge_list, x));
a13d4ebf
AM
6424 }
6425
6426 if (update_flow)
6427 commit_edge_insertions ();
aaa4ca30 6428
a13d4ebf
AM
6429 free_store_memory ();
6430 free_edge_list (edge_list);
6809cbf9 6431 remove_fake_exit_edges ();
a13d4ebf
AM
6432 end_alias_analysis ();
6433}
e2500fed 6434
a0134312
RS
6435\f
6436/* Entry point for jump bypassing optimization pass. */
6437
6438int
1d088dee 6439bypass_jumps (FILE *file)
a0134312
RS
6440{
6441 int changed;
6442
6443 /* We do not construct an accurate cfg in functions which call
6444 setjmp, so just punt to be safe. */
6445 if (current_function_calls_setjmp)
6446 return 0;
6447
6448 /* For calling dump_foo fns from gdb. */
6449 debug_stderr = stderr;
6450 gcse_file = file;
6451
6452 /* Identify the basic block information for this function, including
6453 successors and predecessors. */
6454 max_gcse_regno = max_reg_num ();
6455
6456 if (file)
6457 dump_flow_info (file);
6458
6614fd40 6459 /* Return if there's nothing to do, or it is too expensive. */
d128effb 6460 if (n_basic_blocks <= 1 || is_too_expensive (_ ("jump bypassing disabled")))
a0134312
RS
6461 return 0;
6462
a0134312
RS
6463 gcc_obstack_init (&gcse_obstack);
6464 bytes_used = 0;
6465
6466 /* We need alias. */
6467 init_alias_analysis ();
6468
6469 /* Record where pseudo-registers are set. This data is kept accurate
6470 during each pass. ??? We could also record hard-reg information here
6471 [since it's unchanging], however it is currently done during hash table
6472 computation.
6473
6474 It may be tempting to compute MEM set information here too, but MEM sets
6475 will be subject to code motion one day and thus we need to compute
6476 information about memory sets when we build the hash tables. */
6477
6478 alloc_reg_set_mem (max_gcse_regno);
6479 compute_sets (get_insns ());
6480
6481 max_gcse_regno = max_reg_num ();
6482 alloc_gcse_mem (get_insns ());
27fb79ad 6483 changed = one_cprop_pass (MAX_GCSE_PASSES + 2, 1, 1);
a0134312
RS
6484 free_gcse_mem ();
6485
6486 if (file)
6487 {
6488 fprintf (file, "BYPASS of %s: %d basic blocks, ",
faed5cc3 6489 current_function_name (), n_basic_blocks);
a0134312
RS
6490 fprintf (file, "%d bytes\n\n", bytes_used);
6491 }
6492
6493 obstack_free (&gcse_obstack, NULL);
6494 free_reg_set_mem ();
6495
6496 /* We are finished with alias. */
6497 end_alias_analysis ();
6498 allocate_reg_info (max_reg_num (), FALSE, FALSE);
6499
6500 return changed;
6501}
6502
d128effb
NS
6503/* Return true if the graph is too expensive to optimize. PASS is the
6504 optimization about to be performed. */
6505
6506static bool
6507is_too_expensive (const char *pass)
6508{
6509 /* Trying to perform global optimizations on flow graphs which have
6510 a high connectivity will take a long time and is unlikely to be
6511 particularly useful.
7b1b4aed 6512
d128effb
NS
6513 In normal circumstances a cfg should have about twice as many
6514 edges as blocks. But we do not want to punish small functions
6515 which have a couple switch statements. Rather than simply
6516 threshold the number of blocks, uses something with a more
6517 graceful degradation. */
6518 if (n_edges > 20000 + n_basic_blocks * 4)
6519 {
6520 if (warn_disabled_optimization)
6521 warning ("%s: %d basic blocks and %d edges/basic block",
6522 pass, n_basic_blocks, n_edges / n_basic_blocks);
7b1b4aed 6523
d128effb
NS
6524 return true;
6525 }
6526
6527 /* If allocating memory for the cprop bitmap would take up too much
6528 storage it's better just to disable the optimization. */
6529 if ((n_basic_blocks
6530 * SBITMAP_SET_SIZE (max_reg_num ())
6531 * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY)
6532 {
6533 if (warn_disabled_optimization)
6534 warning ("%s: %d basic blocks and %d registers",
6535 pass, n_basic_blocks, max_reg_num ());
6536
6537 return true;
6538 }
6539
6540 return false;
6541}
6542
e2500fed 6543#include "gt-gcse.h"