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f4e584dc 1/* Global common subexpression elimination/Partial redundancy elimination
7506f491 2 and global constant/copy propagation for GNU compiler.
8e42ace1
KH
3 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002
4 Free Software Foundation, Inc.
7506f491 5
1322177d 6This file is part of GCC.
7506f491 7
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8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2, or (at your option) any later
11version.
7506f491 12
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13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
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17
18You should have received a copy of the GNU General Public License
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19along with GCC; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
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22
23/* TODO
24 - reordering of memory allocation and freeing to be more space efficient
25 - do rough calc of how many regs are needed in each block, and a rough
26 calc of how many regs are available in each class and use that to
27 throttle back the code in cases where RTX_COST is minimal.
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28 - a store to the same address as a load does not kill the load if the
29 source of the store is also the destination of the load. Handling this
30 allows more load motion, particularly out of loops.
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31 - ability to realloc sbitmap vectors would allow one initial computation
32 of reg_set_in_block with only subsequent additions, rather than
33 recomputing it for each pass
34
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35*/
36
37/* References searched while implementing this.
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38
39 Compilers Principles, Techniques and Tools
40 Aho, Sethi, Ullman
41 Addison-Wesley, 1988
42
43 Global Optimization by Suppression of Partial Redundancies
44 E. Morel, C. Renvoise
45 communications of the acm, Vol. 22, Num. 2, Feb. 1979
46
47 A Portable Machine-Independent Global Optimizer - Design and Measurements
48 Frederick Chow
49 Stanford Ph.D. thesis, Dec. 1983
50
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51 A Fast Algorithm for Code Movement Optimization
52 D.M. Dhamdhere
53 SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988
54
55 A Solution to a Problem with Morel and Renvoise's
56 Global Optimization by Suppression of Partial Redundancies
57 K-H Drechsler, M.P. Stadel
58 ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988
59
60 Practical Adaptation of the Global Optimization
61 Algorithm of Morel and Renvoise
62 D.M. Dhamdhere
63 ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991
64
65 Efficiently Computing Static Single Assignment Form and the Control
66 Dependence Graph
67 R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck
68 ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991
69
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70 Lazy Code Motion
71 J. Knoop, O. Ruthing, B. Steffen
72 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
73
74 What's In a Region? Or Computing Control Dependence Regions in Near-Linear
75 Time for Reducible Flow Control
76 Thomas Ball
77 ACM Letters on Programming Languages and Systems,
78 Vol. 2, Num. 1-4, Mar-Dec 1993
79
80 An Efficient Representation for Sparse Sets
81 Preston Briggs, Linda Torczon
82 ACM Letters on Programming Languages and Systems,
83 Vol. 2, Num. 1-4, Mar-Dec 1993
84
85 A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion
86 K-H Drechsler, M.P. Stadel
87 ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993
88
89 Partial Dead Code Elimination
90 J. Knoop, O. Ruthing, B. Steffen
91 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
92
93 Effective Partial Redundancy Elimination
94 P. Briggs, K.D. Cooper
95 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
96
97 The Program Structure Tree: Computing Control Regions in Linear Time
98 R. Johnson, D. Pearson, K. Pingali
99 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
100
101 Optimal Code Motion: Theory and Practice
102 J. Knoop, O. Ruthing, B. Steffen
103 ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994
104
105 The power of assignment motion
106 J. Knoop, O. Ruthing, B. Steffen
107 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
108
109 Global code motion / global value numbering
110 C. Click
111 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
112
113 Value Driven Redundancy Elimination
114 L.T. Simpson
115 Rice University Ph.D. thesis, Apr. 1996
116
117 Value Numbering
118 L.T. Simpson
119 Massively Scalar Compiler Project, Rice University, Sep. 1996
120
121 High Performance Compilers for Parallel Computing
122 Michael Wolfe
123 Addison-Wesley, 1996
124
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125 Advanced Compiler Design and Implementation
126 Steven Muchnick
127 Morgan Kaufmann, 1997
128
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129 Building an Optimizing Compiler
130 Robert Morgan
131 Digital Press, 1998
132
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133 People wishing to speed up the code here should read:
134 Elimination Algorithms for Data Flow Analysis
135 B.G. Ryder, M.C. Paull
136 ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986
137
138 How to Analyze Large Programs Efficiently and Informatively
139 D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck
140 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
141
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142 People wishing to do something different can find various possibilities
143 in the above papers and elsewhere.
144*/
145
146#include "config.h"
50b2596f 147#include "system.h"
01198c2f 148#include "toplev.h"
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149
150#include "rtl.h"
6baf1cc8 151#include "tm_p.h"
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152#include "regs.h"
153#include "hard-reg-set.h"
154#include "flags.h"
155#include "real.h"
156#include "insn-config.h"
157#include "recog.h"
158#include "basic-block.h"
50b2596f 159#include "output.h"
49ad7cfa 160#include "function.h"
589005ff 161#include "expr.h"
e7d482b9 162#include "except.h"
fb0c0a12 163#include "ggc.h"
f1fa37ff 164#include "params.h"
ae860ff7 165#include "cselib.h"
aaa4ca30 166
7506f491 167#include "obstack.h"
4fa31c2a 168
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169/* Propagate flow information through back edges and thus enable PRE's
170 moving loop invariant calculations out of loops.
171
172 Originally this tended to create worse overall code, but several
173 improvements during the development of PRE seem to have made following
174 back edges generally a win.
175
176 Note much of the loop invariant code motion done here would normally
177 be done by loop.c, which has more heuristics for when to move invariants
178 out of loops. At some point we might need to move some of those
179 heuristics into gcse.c. */
7506f491 180
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181/* We support GCSE via Partial Redundancy Elimination. PRE optimizations
182 are a superset of those done by GCSE.
7506f491 183
f4e584dc 184 We perform the following steps:
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185
186 1) Compute basic block information.
187
188 2) Compute table of places where registers are set.
189
190 3) Perform copy/constant propagation.
191
192 4) Perform global cse.
193
e78d9500 194 5) Perform another pass of copy/constant propagation.
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195
196 Two passes of copy/constant propagation are done because the first one
197 enables more GCSE and the second one helps to clean up the copies that
198 GCSE creates. This is needed more for PRE than for Classic because Classic
199 GCSE will try to use an existing register containing the common
200 subexpression rather than create a new one. This is harder to do for PRE
201 because of the code motion (which Classic GCSE doesn't do).
202
203 Expressions we are interested in GCSE-ing are of the form
204 (set (pseudo-reg) (expression)).
205 Function want_to_gcse_p says what these are.
206
207 PRE handles moving invariant expressions out of loops (by treating them as
f4e584dc 208 partially redundant).
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209
210 Eventually it would be nice to replace cse.c/gcse.c with SSA (static single
211 assignment) based GVN (global value numbering). L. T. Simpson's paper
212 (Rice University) on value numbering is a useful reference for this.
213
214 **********************
215
216 We used to support multiple passes but there are diminishing returns in
217 doing so. The first pass usually makes 90% of the changes that are doable.
218 A second pass can make a few more changes made possible by the first pass.
219 Experiments show any further passes don't make enough changes to justify
220 the expense.
221
222 A study of spec92 using an unlimited number of passes:
223 [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83,
224 [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2,
225 [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1
226
227 It was found doing copy propagation between each pass enables further
228 substitutions.
229
230 PRE is quite expensive in complicated functions because the DFA can take
740f35a0 231 awhile to converge. Hence we only perform one pass. The parameter max-gcse-passes can
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232 be modified if one wants to experiment.
233
234 **********************
235
236 The steps for PRE are:
237
238 1) Build the hash table of expressions we wish to GCSE (expr_hash_table).
239
240 2) Perform the data flow analysis for PRE.
241
242 3) Delete the redundant instructions
243
244 4) Insert the required copies [if any] that make the partially
245 redundant instructions fully redundant.
246
247 5) For other reaching expressions, insert an instruction to copy the value
248 to a newly created pseudo that will reach the redundant instruction.
249
250 The deletion is done first so that when we do insertions we
251 know which pseudo reg to use.
252
253 Various papers have argued that PRE DFA is expensive (O(n^2)) and others
254 argue it is not. The number of iterations for the algorithm to converge
255 is typically 2-4 so I don't view it as that expensive (relatively speaking).
256
f4e584dc 257 PRE GCSE depends heavily on the second CSE pass to clean up the copies
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258 we create. To make an expression reach the place where it's redundant,
259 the result of the expression is copied to a new register, and the redundant
260 expression is deleted by replacing it with this new register. Classic GCSE
261 doesn't have this problem as much as it computes the reaching defs of
262 each register in each block and thus can try to use an existing register.
263
264 **********************
265
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266 A fair bit of simplicity is created by creating small functions for simple
267 tasks, even when the function is only called in one place. This may
268 measurably slow things down [or may not] by creating more function call
269 overhead than is necessary. The source is laid out so that it's trivial
270 to make the affected functions inline so that one can measure what speed
271 up, if any, can be achieved, and maybe later when things settle things can
272 be rearranged.
273
274 Help stamp out big monolithic functions! */
275\f
276/* GCSE global vars. */
277
278/* -dG dump file. */
279static FILE *gcse_file;
280
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281/* Note whether or not we should run jump optimization after gcse. We
282 want to do this for two cases.
283
284 * If we changed any jumps via cprop.
285
286 * If we added any labels via edge splitting. */
287
288static int run_jump_opt_after_gcse;
289
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290/* Bitmaps are normally not included in debugging dumps.
291 However it's useful to be able to print them from GDB.
292 We could create special functions for this, but it's simpler to
293 just allow passing stderr to the dump_foo fns. Since stderr can
294 be a macro, we store a copy here. */
295static FILE *debug_stderr;
296
297/* An obstack for our working variables. */
298static struct obstack gcse_obstack;
299
300/* Non-zero for each mode that supports (set (reg) (reg)).
301 This is trivially true for integer and floating point values.
302 It may or may not be true for condition codes. */
303static char can_copy_p[(int) NUM_MACHINE_MODES];
304
305/* Non-zero if can_copy_p has been initialized. */
306static int can_copy_init_p;
307
c4c81601 308struct reg_use {rtx reg_rtx; };
abd535b6 309
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310/* Hash table of expressions. */
311
312struct expr
313{
314 /* The expression (SET_SRC for expressions, PATTERN for assignments). */
315 rtx expr;
316 /* Index in the available expression bitmaps. */
317 int bitmap_index;
318 /* Next entry with the same hash. */
319 struct expr *next_same_hash;
320 /* List of anticipatable occurrences in basic blocks in the function.
321 An "anticipatable occurrence" is one that is the first occurrence in the
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322 basic block, the operands are not modified in the basic block prior
323 to the occurrence and the output is not used between the start of
324 the block and the occurrence. */
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325 struct occr *antic_occr;
326 /* List of available occurrence in basic blocks in the function.
327 An "available occurrence" is one that is the last occurrence in the
328 basic block and the operands are not modified by following statements in
329 the basic block [including this insn]. */
330 struct occr *avail_occr;
331 /* Non-null if the computation is PRE redundant.
332 The value is the newly created pseudo-reg to record a copy of the
333 expression in all the places that reach the redundant copy. */
334 rtx reaching_reg;
335};
336
337/* Occurrence of an expression.
338 There is one per basic block. If a pattern appears more than once the
339 last appearance is used [or first for anticipatable expressions]. */
340
341struct occr
342{
343 /* Next occurrence of this expression. */
344 struct occr *next;
345 /* The insn that computes the expression. */
346 rtx insn;
347 /* Non-zero if this [anticipatable] occurrence has been deleted. */
348 char deleted_p;
349 /* Non-zero if this [available] occurrence has been copied to
350 reaching_reg. */
351 /* ??? This is mutually exclusive with deleted_p, so they could share
352 the same byte. */
353 char copied_p;
354};
355
356/* Expression and copy propagation hash tables.
357 Each hash table is an array of buckets.
358 ??? It is known that if it were an array of entries, structure elements
359 `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is
360 not clear whether in the final analysis a sufficient amount of memory would
361 be saved as the size of the available expression bitmaps would be larger
362 [one could build a mapping table without holes afterwards though].
c4c81601 363 Someday I'll perform the computation and figure it out. */
7506f491 364
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365struct hash_table
366{
367 /* The table itself.
368 This is an array of `expr_hash_table_size' elements. */
369 struct expr **table;
370
371 /* Size of the hash table, in elements. */
372 unsigned int size;
2e653e39 373
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374 /* Number of hash table elements. */
375 unsigned int n_elems;
7506f491 376
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377 /* Whether the table is expression of copy propagation one. */
378 int set_p;
379};
c4c81601 380
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381/* Expression hash table. */
382static struct hash_table expr_hash_table;
383
384/* Copy propagation hash table. */
385static struct hash_table set_hash_table;
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386
387/* Mapping of uids to cuids.
388 Only real insns get cuids. */
389static int *uid_cuid;
390
391/* Highest UID in UID_CUID. */
392static int max_uid;
393
394/* Get the cuid of an insn. */
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395#ifdef ENABLE_CHECKING
396#define INSN_CUID(INSN) (INSN_UID (INSN) > max_uid ? (abort (), 0) : uid_cuid[INSN_UID (INSN)])
397#else
7506f491 398#define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
b86db3eb 399#endif
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400
401/* Number of cuids. */
402static int max_cuid;
403
404/* Mapping of cuids to insns. */
405static rtx *cuid_insn;
406
407/* Get insn from cuid. */
408#define CUID_INSN(CUID) (cuid_insn[CUID])
409
410/* Maximum register number in function prior to doing gcse + 1.
411 Registers created during this pass have regno >= max_gcse_regno.
412 This is named with "gcse" to not collide with global of same name. */
770ae6cc 413static unsigned int max_gcse_regno;
7506f491 414
7506f491 415/* Table of registers that are modified.
c4c81601 416
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417 For each register, each element is a list of places where the pseudo-reg
418 is set.
419
420 For simplicity, GCSE is done on sets of pseudo-regs only. PRE GCSE only
421 requires knowledge of which blocks kill which regs [and thus could use
f4e584dc 422 a bitmap instead of the lists `reg_set_table' uses].
7506f491 423
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424 `reg_set_table' and could be turned into an array of bitmaps (num-bbs x
425 num-regs) [however perhaps it may be useful to keep the data as is]. One
426 advantage of recording things this way is that `reg_set_table' is fairly
427 sparse with respect to pseudo regs but for hard regs could be fairly dense
428 [relatively speaking]. And recording sets of pseudo-regs in lists speeds
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429 up functions like compute_transp since in the case of pseudo-regs we only
430 need to iterate over the number of times a pseudo-reg is set, not over the
431 number of basic blocks [clearly there is a bit of a slow down in the cases
432 where a pseudo is set more than once in a block, however it is believed
433 that the net effect is to speed things up]. This isn't done for hard-regs
434 because recording call-clobbered hard-regs in `reg_set_table' at each
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435 function call can consume a fair bit of memory, and iterating over
436 hard-regs stored this way in compute_transp will be more expensive. */
7506f491 437
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438typedef struct reg_set
439{
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440 /* The next setting of this register. */
441 struct reg_set *next;
442 /* The insn where it was set. */
443 rtx insn;
444} reg_set;
c4c81601 445
7506f491 446static reg_set **reg_set_table;
c4c81601 447
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448/* Size of `reg_set_table'.
449 The table starts out at max_gcse_regno + slop, and is enlarged as
450 necessary. */
451static int reg_set_table_size;
c4c81601 452
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453/* Amount to grow `reg_set_table' by when it's full. */
454#define REG_SET_TABLE_SLOP 100
455
a13d4ebf 456/* This is a list of expressions which are MEMs and will be used by load
589005ff 457 or store motion.
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458 Load motion tracks MEMs which aren't killed by
459 anything except itself. (ie, loads and stores to a single location).
589005ff 460 We can then allow movement of these MEM refs with a little special
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461 allowance. (all stores copy the same value to the reaching reg used
462 for the loads). This means all values used to store into memory must have
589005ff 463 no side effects so we can re-issue the setter value.
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464 Store Motion uses this structure as an expression table to track stores
465 which look interesting, and might be moveable towards the exit block. */
466
467struct ls_expr
468{
469 struct expr * expr; /* Gcse expression reference for LM. */
470 rtx pattern; /* Pattern of this mem. */
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471 rtx loads; /* INSN list of loads seen. */
472 rtx stores; /* INSN list of stores seen. */
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473 struct ls_expr * next; /* Next in the list. */
474 int invalid; /* Invalid for some reason. */
475 int index; /* If it maps to a bitmap index. */
476 int hash_index; /* Index when in a hash table. */
477 rtx reaching_reg; /* Register to use when re-writing. */
478};
479
480/* Head of the list of load/store memory refs. */
481static struct ls_expr * pre_ldst_mems = NULL;
482
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483/* Bitmap containing one bit for each register in the program.
484 Used when performing GCSE to track which registers have been set since
485 the start of the basic block. */
73991d6a 486static regset reg_set_bitmap;
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487
488/* For each block, a bitmap of registers set in the block.
489 This is used by expr_killed_p and compute_transp.
490 It is computed during hash table computation and not by compute_sets
491 as it includes registers added since the last pass (or between cprop and
492 gcse) and it's currently not easy to realloc sbitmap vectors. */
493static sbitmap *reg_set_in_block;
494
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495/* Array, indexed by basic block number for a list of insns which modify
496 memory within that block. */
497static rtx * modify_mem_list;
73991d6a 498bitmap modify_mem_list_set;
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499
500/* This array parallels modify_mem_list, but is kept canonicalized. */
501static rtx * canon_modify_mem_list;
73991d6a 502bitmap canon_modify_mem_list_set;
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503/* Various variables for statistics gathering. */
504
505/* Memory used in a pass.
506 This isn't intended to be absolutely precise. Its intent is only
507 to keep an eye on memory usage. */
508static int bytes_used;
c4c81601 509
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510/* GCSE substitutions made. */
511static int gcse_subst_count;
512/* Number of copy instructions created. */
513static int gcse_create_count;
514/* Number of constants propagated. */
515static int const_prop_count;
516/* Number of copys propagated. */
517static int copy_prop_count;
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518\f
519/* These variables are used by classic GCSE.
520 Normally they'd be defined a bit later, but `rd_gen' needs to
521 be declared sooner. */
522
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523/* Each block has a bitmap of each type.
524 The length of each blocks bitmap is:
525
526 max_cuid - for reaching definitions
527 n_exprs - for available expressions
528
529 Thus we view the bitmaps as 2 dimensional arrays. i.e.
530 rd_kill[block_num][cuid_num]
c4c81601 531 ae_kill[block_num][expr_num] */
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532
533/* For reaching defs */
534static sbitmap *rd_kill, *rd_gen, *reaching_defs, *rd_out;
535
536/* for available exprs */
537static sbitmap *ae_kill, *ae_gen, *ae_in, *ae_out;
b5ce41ff 538
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539/* Objects of this type are passed around by the null-pointer check
540 removal routines. */
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541struct null_pointer_info
542{
0511851c 543 /* The basic block being processed. */
e0082a72 544 basic_block current_block;
0511851c 545 /* The first register to be handled in this pass. */
770ae6cc 546 unsigned int min_reg;
0511851c 547 /* One greater than the last register to be handled in this pass. */
770ae6cc 548 unsigned int max_reg;
0511851c
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549 sbitmap *nonnull_local;
550 sbitmap *nonnull_killed;
551};
7506f491 552\f
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553static void compute_can_copy PARAMS ((void));
554static char *gmalloc PARAMS ((unsigned int));
555static char *grealloc PARAMS ((char *, unsigned int));
556static char *gcse_alloc PARAMS ((unsigned long));
557static void alloc_gcse_mem PARAMS ((rtx));
558static void free_gcse_mem PARAMS ((void));
559static void alloc_reg_set_mem PARAMS ((int));
560static void free_reg_set_mem PARAMS ((void));
561static int get_bitmap_width PARAMS ((int, int, int));
562static void record_one_set PARAMS ((int, rtx));
563static void record_set_info PARAMS ((rtx, rtx, void *));
564static void compute_sets PARAMS ((rtx));
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565static void hash_scan_insn PARAMS ((rtx, struct hash_table *, int));
566static void hash_scan_set PARAMS ((rtx, rtx, struct hash_table *));
567static void hash_scan_clobber PARAMS ((rtx, rtx, struct hash_table *));
568static void hash_scan_call PARAMS ((rtx, rtx, struct hash_table *));
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569static int want_to_gcse_p PARAMS ((rtx));
570static int oprs_unchanged_p PARAMS ((rtx, rtx, int));
571static int oprs_anticipatable_p PARAMS ((rtx, rtx));
572static int oprs_available_p PARAMS ((rtx, rtx));
573static void insert_expr_in_table PARAMS ((rtx, enum machine_mode, rtx,
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574 int, int, struct hash_table *));
575static void insert_set_in_table PARAMS ((rtx, rtx, struct hash_table *));
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576static unsigned int hash_expr PARAMS ((rtx, enum machine_mode, int *, int));
577static unsigned int hash_expr_1 PARAMS ((rtx, enum machine_mode, int *));
c0712acb 578static unsigned int hash_string_1 PARAMS ((const char *));
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579static unsigned int hash_set PARAMS ((int, int));
580static int expr_equiv_p PARAMS ((rtx, rtx));
581static void record_last_reg_set_info PARAMS ((rtx, int));
582static void record_last_mem_set_info PARAMS ((rtx));
583static void record_last_set_info PARAMS ((rtx, rtx, void *));
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584static void compute_hash_table PARAMS ((struct hash_table *));
585static void alloc_hash_table PARAMS ((int, struct hash_table *, int));
586static void free_hash_table PARAMS ((struct hash_table *));
587static void compute_hash_table_work PARAMS ((struct hash_table *));
588static void dump_hash_table PARAMS ((FILE *, const char *,
589 struct hash_table *));
590static struct expr *lookup_expr PARAMS ((rtx, struct hash_table *));
591static struct expr *lookup_set PARAMS ((unsigned int, rtx, struct hash_table *));
770ae6cc 592static struct expr *next_set PARAMS ((unsigned int, struct expr *));
c4c81601
RK
593static void reset_opr_set_tables PARAMS ((void));
594static int oprs_not_set_p PARAMS ((rtx, rtx));
595static void mark_call PARAMS ((rtx));
596static void mark_set PARAMS ((rtx, rtx));
597static void mark_clobber PARAMS ((rtx, rtx));
598static void mark_oprs_set PARAMS ((rtx));
599static void alloc_cprop_mem PARAMS ((int, int));
600static void free_cprop_mem PARAMS ((void));
601static void compute_transp PARAMS ((rtx, int, sbitmap *, int));
602static void compute_transpout PARAMS ((void));
603static void compute_local_properties PARAMS ((sbitmap *, sbitmap *, sbitmap *,
02280659 604 struct hash_table *));
711d877c 605static void compute_cprop_data PARAMS ((void));
9e71c818 606static void find_used_regs PARAMS ((rtx *, void *));
c4c81601
RK
607static int try_replace_reg PARAMS ((rtx, rtx, rtx));
608static struct expr *find_avail_set PARAMS ((int, rtx));
0e3f0221 609static int cprop_jump PARAMS ((basic_block, rtx, rtx, rtx, rtx));
a13d4ebf 610static void mems_conflict_for_gcse_p PARAMS ((rtx, rtx, void *));
e2d2ed72 611static int load_killed_in_block_p PARAMS ((basic_block, int, rtx, int));
a13d4ebf 612static void canon_list_insert PARAMS ((rtx, rtx, void *));
ae860ff7 613static int cprop_insn PARAMS ((rtx, int));
c4c81601
RK
614static int cprop PARAMS ((int));
615static int one_cprop_pass PARAMS ((int, int));
ae860ff7 616static bool constprop_register PARAMS ((rtx, rtx, rtx, int));
0e3f0221
RS
617static struct expr *find_bypass_set PARAMS ((int, int));
618static int bypass_block PARAMS ((basic_block, rtx, rtx));
619static int bypass_conditional_jumps PARAMS ((void));
c4c81601
RK
620static void alloc_pre_mem PARAMS ((int, int));
621static void free_pre_mem PARAMS ((void));
622static void compute_pre_data PARAMS ((void));
589005ff 623static int pre_expr_reaches_here_p PARAMS ((basic_block, struct expr *,
e2d2ed72
AM
624 basic_block));
625static void insert_insn_end_bb PARAMS ((struct expr *, basic_block, int));
c4c81601
RK
626static void pre_insert_copy_insn PARAMS ((struct expr *, rtx));
627static void pre_insert_copies PARAMS ((void));
628static int pre_delete PARAMS ((void));
629static int pre_gcse PARAMS ((void));
630static int one_pre_gcse_pass PARAMS ((int));
631static void add_label_notes PARAMS ((rtx, rtx));
632static void alloc_code_hoist_mem PARAMS ((int, int));
633static void free_code_hoist_mem PARAMS ((void));
711d877c 634static void compute_code_hoist_vbeinout PARAMS ((void));
c4c81601 635static void compute_code_hoist_data PARAMS ((void));
589005ff 636static int hoist_expr_reaches_here_p PARAMS ((basic_block, int, basic_block,
e2d2ed72 637 char *));
c4c81601
RK
638static void hoist_code PARAMS ((void));
639static int one_code_hoisting_pass PARAMS ((void));
640static void alloc_rd_mem PARAMS ((int, int));
641static void free_rd_mem PARAMS ((void));
e2d2ed72 642static void handle_rd_kill_set PARAMS ((rtx, int, basic_block));
c4c81601 643static void compute_kill_rd PARAMS ((void));
711d877c 644static void compute_rd PARAMS ((void));
c4c81601
RK
645static void alloc_avail_expr_mem PARAMS ((int, int));
646static void free_avail_expr_mem PARAMS ((void));
02280659 647static void compute_ae_gen PARAMS ((struct hash_table *));
e2d2ed72 648static int expr_killed_p PARAMS ((rtx, basic_block));
02280659 649static void compute_ae_kill PARAMS ((sbitmap *, sbitmap *, struct hash_table *));
711d877c 650static int expr_reaches_here_p PARAMS ((struct occr *, struct expr *,
e2d2ed72 651 basic_block, int));
c4c81601
RK
652static rtx computing_insn PARAMS ((struct expr *, rtx));
653static int def_reaches_here_p PARAMS ((rtx, rtx));
654static int can_disregard_other_sets PARAMS ((struct reg_set **, rtx, int));
655static int handle_avail_expr PARAMS ((rtx, struct expr *));
656static int classic_gcse PARAMS ((void));
657static int one_classic_gcse_pass PARAMS ((int));
658static void invalidate_nonnull_info PARAMS ((rtx, rtx, void *));
99a15921 659static int delete_null_pointer_checks_1 PARAMS ((unsigned int *,
8e184d9c 660 sbitmap *, sbitmap *,
711d877c
KG
661 struct null_pointer_info *));
662static rtx process_insert_insn PARAMS ((struct expr *));
663static int pre_edge_insert PARAMS ((struct edge_list *, struct expr **));
c4c81601 664static int expr_reaches_here_p_work PARAMS ((struct occr *, struct expr *,
e2d2ed72
AM
665 basic_block, int, char *));
666static int pre_expr_reaches_here_p_work PARAMS ((basic_block, struct expr *,
667 basic_block, char *));
a13d4ebf
AM
668static struct ls_expr * ldst_entry PARAMS ((rtx));
669static void free_ldst_entry PARAMS ((struct ls_expr *));
670static void free_ldst_mems PARAMS ((void));
671static void print_ldst_list PARAMS ((FILE *));
672static struct ls_expr * find_rtx_in_ldst PARAMS ((rtx));
673static int enumerate_ldsts PARAMS ((void));
674static inline struct ls_expr * first_ls_expr PARAMS ((void));
675static inline struct ls_expr * next_ls_expr PARAMS ((struct ls_expr *));
676static int simple_mem PARAMS ((rtx));
677static void invalidate_any_buried_refs PARAMS ((rtx));
589005ff 678static void compute_ld_motion_mems PARAMS ((void));
a13d4ebf
AM
679static void trim_ld_motion_mems PARAMS ((void));
680static void update_ld_motion_stores PARAMS ((struct expr *));
aaa4ca30
AJ
681static void reg_set_info PARAMS ((rtx, rtx, void *));
682static int store_ops_ok PARAMS ((rtx, basic_block));
a13d4ebf
AM
683static void find_moveable_store PARAMS ((rtx));
684static int compute_store_table PARAMS ((void));
685static int load_kills_store PARAMS ((rtx, rtx));
686static int find_loads PARAMS ((rtx, rtx));
687static int store_killed_in_insn PARAMS ((rtx, rtx));
aaa4ca30 688static int store_killed_after PARAMS ((rtx, rtx, basic_block));
e2d2ed72 689static int store_killed_before PARAMS ((rtx, rtx, basic_block));
a13d4ebf 690static void build_store_vectors PARAMS ((void));
e2d2ed72 691static void insert_insn_start_bb PARAMS ((rtx, basic_block));
a13d4ebf 692static int insert_store PARAMS ((struct ls_expr *, edge));
e2d2ed72 693static void replace_store_insn PARAMS ((rtx, rtx, basic_block));
589005ff 694static void delete_store PARAMS ((struct ls_expr *,
e2d2ed72 695 basic_block));
a13d4ebf
AM
696static void free_store_memory PARAMS ((void));
697static void store_motion PARAMS ((void));
0fe854a7 698static void free_insn_expr_list_list PARAMS ((rtx *));
73991d6a
JH
699static void clear_modify_mem_tables PARAMS ((void));
700static void free_modify_mem_tables PARAMS ((void));
10d1bb36 701static rtx gcse_emit_move_after PARAMS ((rtx, rtx, rtx));
8ba46434
R
702static bool do_local_cprop PARAMS ((rtx, rtx, int, rtx*));
703static bool adjust_libcall_notes PARAMS ((rtx, rtx, rtx, rtx*));
ae860ff7 704static void local_cprop_pass PARAMS ((int));
7506f491
DE
705\f
706/* Entry point for global common subexpression elimination.
707 F is the first instruction in the function. */
708
e78d9500 709int
7506f491
DE
710gcse_main (f, file)
711 rtx f;
712 FILE *file;
713{
714 int changed, pass;
715 /* Bytes used at start of pass. */
716 int initial_bytes_used;
717 /* Maximum number of bytes used by a pass. */
718 int max_pass_bytes;
719 /* Point to release obstack data from for each pass. */
720 char *gcse_obstack_bottom;
721
a13d4ebf
AM
722 /* Insertion of instructions on edges can create new basic blocks; we
723 need the original basic block count so that we can properly deallocate
724 arrays sized on the number of basic blocks originally in the cfg. */
725 int orig_bb_count;
b5ce41ff
JL
726 /* We do not construct an accurate cfg in functions which call
727 setjmp, so just punt to be safe. */
7506f491 728 if (current_function_calls_setjmp)
e78d9500 729 return 0;
589005ff 730
b5ce41ff
JL
731 /* Assume that we do not need to run jump optimizations after gcse. */
732 run_jump_opt_after_gcse = 0;
733
7506f491
DE
734 /* For calling dump_foo fns from gdb. */
735 debug_stderr = stderr;
b5ce41ff 736 gcse_file = file;
7506f491 737
b5ce41ff
JL
738 /* Identify the basic block information for this function, including
739 successors and predecessors. */
7506f491 740 max_gcse_regno = max_reg_num ();
7506f491 741
a42cd965
AM
742 if (file)
743 dump_flow_info (file);
744
0b17ab2f 745 orig_bb_count = n_basic_blocks;
7506f491 746 /* Return if there's nothing to do. */
0b17ab2f 747 if (n_basic_blocks <= 1)
a18820c6 748 return 0;
7506f491 749
55f7891b
JL
750 /* Trying to perform global optimizations on flow graphs which have
751 a high connectivity will take a long time and is unlikely to be
752 particularly useful.
753
43e72072 754 In normal circumstances a cfg should have about twice as many edges
55f7891b
JL
755 as blocks. But we do not want to punish small functions which have
756 a couple switch statements. So we require a relatively large number
757 of basic blocks and the ratio of edges to blocks to be high. */
0b17ab2f 758 if (n_basic_blocks > 1000 && n_edges / n_basic_blocks >= 20)
18424ae1
BL
759 {
760 if (warn_disabled_optimization)
8e42ace1 761 warning ("GCSE disabled: %d > 1000 basic blocks and %d >= 20 edges/basic block",
0b17ab2f 762 n_basic_blocks, n_edges / n_basic_blocks);
18424ae1
BL
763 return 0;
764 }
55f7891b 765
f1fa37ff
MM
766 /* If allocating memory for the cprop bitmap would take up too much
767 storage it's better just to disable the optimization. */
589005ff 768 if ((n_basic_blocks
f1fa37ff
MM
769 * SBITMAP_SET_SIZE (max_gcse_regno)
770 * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY)
771 {
772 if (warn_disabled_optimization)
773 warning ("GCSE disabled: %d basic blocks and %d registers",
0b17ab2f 774 n_basic_blocks, max_gcse_regno);
f1fa37ff
MM
775
776 return 0;
777 }
778
7506f491
DE
779 /* See what modes support reg/reg copy operations. */
780 if (! can_copy_init_p)
781 {
782 compute_can_copy ();
783 can_copy_init_p = 1;
784 }
785
786 gcc_obstack_init (&gcse_obstack);
a42cd965 787 bytes_used = 0;
7506f491 788
a13d4ebf
AM
789 /* We need alias. */
790 init_alias_analysis ();
c4c81601
RK
791 /* Record where pseudo-registers are set. This data is kept accurate
792 during each pass. ??? We could also record hard-reg information here
793 [since it's unchanging], however it is currently done during hash table
794 computation.
b5ce41ff 795
c4c81601
RK
796 It may be tempting to compute MEM set information here too, but MEM sets
797 will be subject to code motion one day and thus we need to compute
b5ce41ff 798 information about memory sets when we build the hash tables. */
7506f491
DE
799
800 alloc_reg_set_mem (max_gcse_regno);
801 compute_sets (f);
802
803 pass = 0;
804 initial_bytes_used = bytes_used;
805 max_pass_bytes = 0;
806 gcse_obstack_bottom = gcse_alloc (1);
807 changed = 1;
740f35a0 808 while (changed && pass < MAX_GCSE_PASSES)
7506f491
DE
809 {
810 changed = 0;
811 if (file)
812 fprintf (file, "GCSE pass %d\n\n", pass + 1);
813
814 /* Initialize bytes_used to the space for the pred/succ lists,
815 and the reg_set_table data. */
816 bytes_used = initial_bytes_used;
817
818 /* Each pass may create new registers, so recalculate each time. */
819 max_gcse_regno = max_reg_num ();
820
821 alloc_gcse_mem (f);
822
b5ce41ff
JL
823 /* Don't allow constant propagation to modify jumps
824 during this pass. */
825 changed = one_cprop_pass (pass + 1, 0);
7506f491
DE
826
827 if (optimize_size)
b5ce41ff 828 changed |= one_classic_gcse_pass (pass + 1);
7506f491 829 else
589005ff 830 {
a42cd965 831 changed |= one_pre_gcse_pass (pass + 1);
a13d4ebf
AM
832 /* We may have just created new basic blocks. Release and
833 recompute various things which are sized on the number of
834 basic blocks. */
835 if (changed)
836 {
73991d6a 837 free_modify_mem_tables ();
a13d4ebf 838 modify_mem_list
d55bc081 839 = (rtx *) gmalloc (last_basic_block * sizeof (rtx));
a13d4ebf 840 canon_modify_mem_list
d55bc081
ZD
841 = (rtx *) gmalloc (last_basic_block * sizeof (rtx));
842 memset ((char *) modify_mem_list, 0, last_basic_block * sizeof (rtx));
843 memset ((char *) canon_modify_mem_list, 0, last_basic_block * sizeof (rtx));
0b17ab2f 844 orig_bb_count = n_basic_blocks;
a13d4ebf 845 }
a42cd965
AM
846 free_reg_set_mem ();
847 alloc_reg_set_mem (max_reg_num ());
848 compute_sets (f);
849 run_jump_opt_after_gcse = 1;
850 }
7506f491
DE
851
852 if (max_pass_bytes < bytes_used)
853 max_pass_bytes = bytes_used;
854
bb457bd9
JL
855 /* Free up memory, then reallocate for code hoisting. We can
856 not re-use the existing allocated memory because the tables
857 will not have info for the insns or registers created by
858 partial redundancy elimination. */
7506f491
DE
859 free_gcse_mem ();
860
bb457bd9
JL
861 /* It does not make sense to run code hoisting unless we optimizing
862 for code size -- it rarely makes programs faster, and can make
863 them bigger if we did partial redundancy elimination (when optimizing
864 for space, we use a classic gcse algorithm instead of partial
865 redundancy algorithms). */
866 if (optimize_size)
589005ff 867 {
bb457bd9
JL
868 max_gcse_regno = max_reg_num ();
869 alloc_gcse_mem (f);
870 changed |= one_code_hoisting_pass ();
871 free_gcse_mem ();
872
873 if (max_pass_bytes < bytes_used)
874 max_pass_bytes = bytes_used;
589005ff 875 }
bb457bd9 876
7506f491
DE
877 if (file)
878 {
879 fprintf (file, "\n");
880 fflush (file);
881 }
c4c81601 882
7506f491
DE
883 obstack_free (&gcse_obstack, gcse_obstack_bottom);
884 pass++;
885 }
886
b5ce41ff
JL
887 /* Do one last pass of copy propagation, including cprop into
888 conditional jumps. */
889
890 max_gcse_regno = max_reg_num ();
891 alloc_gcse_mem (f);
892 /* This time, go ahead and allow cprop to alter jumps. */
893 one_cprop_pass (pass + 1, 1);
894 free_gcse_mem ();
7506f491
DE
895
896 if (file)
897 {
898 fprintf (file, "GCSE of %s: %d basic blocks, ",
0b17ab2f 899 current_function_name, n_basic_blocks);
7506f491
DE
900 fprintf (file, "%d pass%s, %d bytes\n\n",
901 pass, pass > 1 ? "es" : "", max_pass_bytes);
902 }
903
6496a589 904 obstack_free (&gcse_obstack, NULL);
7506f491 905 free_reg_set_mem ();
a13d4ebf
AM
906 /* We are finished with alias. */
907 end_alias_analysis ();
908 allocate_reg_info (max_reg_num (), FALSE, FALSE);
909
61ad9a34
JJ
910 /* Store motion disabled until it is fixed. */
911 if (0 && !optimize_size && flag_gcse_sm)
a13d4ebf
AM
912 store_motion ();
913 /* Record where pseudo-registers are set. */
e78d9500 914 return run_jump_opt_after_gcse;
7506f491
DE
915}
916\f
917/* Misc. utilities. */
918
919/* Compute which modes support reg/reg copy operations. */
920
921static void
922compute_can_copy ()
923{
924 int i;
50b2596f 925#ifndef AVOID_CCMODE_COPIES
8e42ace1 926 rtx reg, insn;
50b2596f 927#endif
961192e1 928 memset (can_copy_p, 0, NUM_MACHINE_MODES);
7506f491
DE
929
930 start_sequence ();
931 for (i = 0; i < NUM_MACHINE_MODES; i++)
c4c81601
RK
932 if (GET_MODE_CLASS (i) == MODE_CC)
933 {
7506f491 934#ifdef AVOID_CCMODE_COPIES
c4c81601 935 can_copy_p[i] = 0;
7506f491 936#else
c4c81601
RK
937 reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1);
938 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg));
9714cf43 939 if (recog (PATTERN (insn), insn, NULL) >= 0)
c4c81601 940 can_copy_p[i] = 1;
7506f491 941#endif
c4c81601 942 }
141b5810
AO
943 else
944 can_copy_p[i] = 1;
c4c81601 945
7506f491 946 end_sequence ();
7506f491
DE
947}
948\f
949/* Cover function to xmalloc to record bytes allocated. */
950
951static char *
952gmalloc (size)
953 unsigned int size;
954{
955 bytes_used += size;
956 return xmalloc (size);
957}
958
959/* Cover function to xrealloc.
960 We don't record the additional size since we don't know it.
961 It won't affect memory usage stats much anyway. */
962
963static char *
964grealloc (ptr, size)
965 char *ptr;
966 unsigned int size;
967{
968 return xrealloc (ptr, size);
969}
970
77bbd421 971/* Cover function to obstack_alloc. */
7506f491
DE
972
973static char *
974gcse_alloc (size)
975 unsigned long size;
976{
77bbd421 977 bytes_used += size;
7506f491
DE
978 return (char *) obstack_alloc (&gcse_obstack, size);
979}
980
981/* Allocate memory for the cuid mapping array,
982 and reg/memory set tracking tables.
983
984 This is called at the start of each pass. */
985
986static void
987alloc_gcse_mem (f)
988 rtx f;
989{
8e42ace1 990 int i, n;
7506f491
DE
991 rtx insn;
992
993 /* Find the largest UID and create a mapping from UIDs to CUIDs.
994 CUIDs are like UIDs except they increase monotonically, have no gaps,
995 and only apply to real insns. */
996
997 max_uid = get_max_uid ();
998 n = (max_uid + 1) * sizeof (int);
999 uid_cuid = (int *) gmalloc (n);
961192e1 1000 memset ((char *) uid_cuid, 0, n);
7506f491
DE
1001 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
1002 {
2c3c49de 1003 if (INSN_P (insn))
b86db3eb 1004 uid_cuid[INSN_UID (insn)] = i++;
7506f491 1005 else
b86db3eb 1006 uid_cuid[INSN_UID (insn)] = i;
7506f491
DE
1007 }
1008
1009 /* Create a table mapping cuids to insns. */
1010
1011 max_cuid = i;
1012 n = (max_cuid + 1) * sizeof (rtx);
1013 cuid_insn = (rtx *) gmalloc (n);
961192e1 1014 memset ((char *) cuid_insn, 0, n);
7506f491 1015 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
2c3c49de 1016 if (INSN_P (insn))
c4c81601 1017 CUID_INSN (i++) = insn;
7506f491
DE
1018
1019 /* Allocate vars to track sets of regs. */
73991d6a 1020 reg_set_bitmap = BITMAP_XMALLOC ();
7506f491
DE
1021
1022 /* Allocate vars to track sets of regs, memory per block. */
d55bc081 1023 reg_set_in_block = (sbitmap *) sbitmap_vector_alloc (last_basic_block,
7506f491 1024 max_gcse_regno);
a13d4ebf
AM
1025 /* Allocate array to keep a list of insns which modify memory in each
1026 basic block. */
d55bc081
ZD
1027 modify_mem_list = (rtx *) gmalloc (last_basic_block * sizeof (rtx));
1028 canon_modify_mem_list = (rtx *) gmalloc (last_basic_block * sizeof (rtx));
1029 memset ((char *) modify_mem_list, 0, last_basic_block * sizeof (rtx));
1030 memset ((char *) canon_modify_mem_list, 0, last_basic_block * sizeof (rtx));
73991d6a
JH
1031 modify_mem_list_set = BITMAP_XMALLOC ();
1032 canon_modify_mem_list_set = BITMAP_XMALLOC ();
7506f491
DE
1033}
1034
1035/* Free memory allocated by alloc_gcse_mem. */
1036
1037static void
1038free_gcse_mem ()
1039{
1040 free (uid_cuid);
1041 free (cuid_insn);
1042
73991d6a 1043 BITMAP_XFREE (reg_set_bitmap);
7506f491 1044
5a660bff 1045 sbitmap_vector_free (reg_set_in_block);
73991d6a
JH
1046 free_modify_mem_tables ();
1047 BITMAP_XFREE (modify_mem_list_set);
1048 BITMAP_XFREE (canon_modify_mem_list_set);
7506f491
DE
1049}
1050
0511851c
MM
1051/* Many of the global optimization algorithms work by solving dataflow
1052 equations for various expressions. Initially, some local value is
c4c81601
RK
1053 computed for each expression in each block. Then, the values across the
1054 various blocks are combined (by following flow graph edges) to arrive at
1055 global values. Conceptually, each set of equations is independent. We
1056 may therefore solve all the equations in parallel, solve them one at a
1057 time, or pick any intermediate approach.
1058
1059 When you're going to need N two-dimensional bitmaps, each X (say, the
1060 number of blocks) by Y (say, the number of expressions), call this
1061 function. It's not important what X and Y represent; only that Y
1062 correspond to the things that can be done in parallel. This function will
1063 return an appropriate chunking factor C; you should solve C sets of
1064 equations in parallel. By going through this function, we can easily
1065 trade space against time; by solving fewer equations in parallel we use
1066 less space. */
0511851c
MM
1067
1068static int
1069get_bitmap_width (n, x, y)
1070 int n;
1071 int x;
1072 int y;
1073{
1074 /* It's not really worth figuring out *exactly* how much memory will
1075 be used by a particular choice. The important thing is to get
1076 something approximately right. */
1077 size_t max_bitmap_memory = 10 * 1024 * 1024;
1078
1079 /* The number of bytes we'd use for a single column of minimum
1080 width. */
1081 size_t column_size = n * x * sizeof (SBITMAP_ELT_TYPE);
1082
1083 /* Often, it's reasonable just to solve all the equations in
1084 parallel. */
1085 if (column_size * SBITMAP_SET_SIZE (y) <= max_bitmap_memory)
1086 return y;
1087
1088 /* Otherwise, pick the largest width we can, without going over the
1089 limit. */
1090 return SBITMAP_ELT_BITS * ((max_bitmap_memory + column_size - 1)
1091 / column_size);
1092}
b5ce41ff
JL
1093\f
1094/* Compute the local properties of each recorded expression.
c4c81601
RK
1095
1096 Local properties are those that are defined by the block, irrespective of
1097 other blocks.
b5ce41ff
JL
1098
1099 An expression is transparent in a block if its operands are not modified
1100 in the block.
1101
1102 An expression is computed (locally available) in a block if it is computed
1103 at least once and expression would contain the same value if the
1104 computation was moved to the end of the block.
1105
1106 An expression is locally anticipatable in a block if it is computed at
1107 least once and expression would contain the same value if the computation
1108 was moved to the beginning of the block.
1109
c4c81601
RK
1110 We call this routine for cprop, pre and code hoisting. They all compute
1111 basically the same information and thus can easily share this code.
7506f491 1112
c4c81601
RK
1113 TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local
1114 properties. If NULL, then it is not necessary to compute or record that
1115 particular property.
b5ce41ff 1116
02280659
ZD
1117 TABLE controls which hash table to look at. If it is set hash table,
1118 additionally, TRANSP is computed as ~TRANSP, since this is really cprop's
c4c81601 1119 ABSALTERED. */
589005ff 1120
b5ce41ff 1121static void
02280659 1122compute_local_properties (transp, comp, antloc, table)
b5ce41ff
JL
1123 sbitmap *transp;
1124 sbitmap *comp;
1125 sbitmap *antloc;
02280659 1126 struct hash_table *table;
b5ce41ff 1127{
02280659 1128 unsigned int i;
589005ff 1129
b5ce41ff
JL
1130 /* Initialize any bitmaps that were passed in. */
1131 if (transp)
695ab36a 1132 {
02280659 1133 if (table->set_p)
d55bc081 1134 sbitmap_vector_zero (transp, last_basic_block);
695ab36a 1135 else
d55bc081 1136 sbitmap_vector_ones (transp, last_basic_block);
695ab36a 1137 }
c4c81601 1138
b5ce41ff 1139 if (comp)
d55bc081 1140 sbitmap_vector_zero (comp, last_basic_block);
b5ce41ff 1141 if (antloc)
d55bc081 1142 sbitmap_vector_zero (antloc, last_basic_block);
b5ce41ff 1143
02280659 1144 for (i = 0; i < table->size; i++)
7506f491 1145 {
b5ce41ff
JL
1146 struct expr *expr;
1147
02280659 1148 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
b5ce41ff 1149 {
b5ce41ff 1150 int indx = expr->bitmap_index;
c4c81601 1151 struct occr *occr;
b5ce41ff
JL
1152
1153 /* The expression is transparent in this block if it is not killed.
1154 We start by assuming all are transparent [none are killed], and
1155 then reset the bits for those that are. */
b5ce41ff 1156 if (transp)
02280659 1157 compute_transp (expr->expr, indx, transp, table->set_p);
b5ce41ff
JL
1158
1159 /* The occurrences recorded in antic_occr are exactly those that
1160 we want to set to non-zero in ANTLOC. */
b5ce41ff 1161 if (antloc)
c4c81601
RK
1162 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
1163 {
1164 SET_BIT (antloc[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1165
c4c81601
RK
1166 /* While we're scanning the table, this is a good place to
1167 initialize this. */
1168 occr->deleted_p = 0;
1169 }
b5ce41ff
JL
1170
1171 /* The occurrences recorded in avail_occr are exactly those that
1172 we want to set to non-zero in COMP. */
1173 if (comp)
c4c81601
RK
1174 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
1175 {
1176 SET_BIT (comp[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1177
c4c81601
RK
1178 /* While we're scanning the table, this is a good place to
1179 initialize this. */
1180 occr->copied_p = 0;
1181 }
b5ce41ff
JL
1182
1183 /* While we're scanning the table, this is a good place to
1184 initialize this. */
1185 expr->reaching_reg = 0;
1186 }
7506f491 1187 }
7506f491
DE
1188}
1189\f
1190/* Register set information.
1191
1192 `reg_set_table' records where each register is set or otherwise
1193 modified. */
1194
1195static struct obstack reg_set_obstack;
1196
1197static void
1198alloc_reg_set_mem (n_regs)
1199 int n_regs;
1200{
c4c81601 1201 unsigned int n;
7506f491
DE
1202
1203 reg_set_table_size = n_regs + REG_SET_TABLE_SLOP;
1204 n = reg_set_table_size * sizeof (struct reg_set *);
1205 reg_set_table = (struct reg_set **) gmalloc (n);
961192e1 1206 memset ((char *) reg_set_table, 0, n);
7506f491
DE
1207
1208 gcc_obstack_init (&reg_set_obstack);
1209}
1210
1211static void
1212free_reg_set_mem ()
1213{
1214 free (reg_set_table);
6496a589 1215 obstack_free (&reg_set_obstack, NULL);
7506f491
DE
1216}
1217
1218/* Record REGNO in the reg_set table. */
1219
1220static void
1221record_one_set (regno, insn)
1222 int regno;
1223 rtx insn;
1224{
172890a2 1225 /* Allocate a new reg_set element and link it onto the list. */
63bc1d05 1226 struct reg_set *new_reg_info;
7506f491
DE
1227
1228 /* If the table isn't big enough, enlarge it. */
1229 if (regno >= reg_set_table_size)
1230 {
1231 int new_size = regno + REG_SET_TABLE_SLOP;
c4c81601
RK
1232
1233 reg_set_table
1234 = (struct reg_set **) grealloc ((char *) reg_set_table,
1235 new_size * sizeof (struct reg_set *));
961192e1 1236 memset ((char *) (reg_set_table + reg_set_table_size), 0,
8e42ace1 1237 (new_size - reg_set_table_size) * sizeof (struct reg_set *));
7506f491
DE
1238 reg_set_table_size = new_size;
1239 }
1240
1241 new_reg_info = (struct reg_set *) obstack_alloc (&reg_set_obstack,
1242 sizeof (struct reg_set));
1243 bytes_used += sizeof (struct reg_set);
1244 new_reg_info->insn = insn;
274969ea
MM
1245 new_reg_info->next = reg_set_table[regno];
1246 reg_set_table[regno] = new_reg_info;
7506f491
DE
1247}
1248
c4c81601
RK
1249/* Called from compute_sets via note_stores to handle one SET or CLOBBER in
1250 an insn. The DATA is really the instruction in which the SET is
1251 occurring. */
7506f491
DE
1252
1253static void
84832317 1254record_set_info (dest, setter, data)
50b2596f 1255 rtx dest, setter ATTRIBUTE_UNUSED;
84832317 1256 void *data;
7506f491 1257{
84832317
MM
1258 rtx record_set_insn = (rtx) data;
1259
c4c81601
RK
1260 if (GET_CODE (dest) == REG && REGNO (dest) >= FIRST_PSEUDO_REGISTER)
1261 record_one_set (REGNO (dest), record_set_insn);
7506f491
DE
1262}
1263
1264/* Scan the function and record each set of each pseudo-register.
1265
c4c81601
RK
1266 This is called once, at the start of the gcse pass. See the comments for
1267 `reg_set_table' for further documenation. */
7506f491
DE
1268
1269static void
1270compute_sets (f)
1271 rtx f;
1272{
c4c81601 1273 rtx insn;
7506f491 1274
c4c81601 1275 for (insn = f; insn != 0; insn = NEXT_INSN (insn))
2c3c49de 1276 if (INSN_P (insn))
c4c81601 1277 note_stores (PATTERN (insn), record_set_info, insn);
7506f491
DE
1278}
1279\f
1280/* Hash table support. */
1281
80c29cc4
RZ
1282struct reg_avail_info
1283{
e0082a72 1284 basic_block last_bb;
80c29cc4
RZ
1285 int first_set;
1286 int last_set;
1287};
1288
1289static struct reg_avail_info *reg_avail_info;
e0082a72 1290static basic_block current_bb;
7506f491 1291
7506f491 1292
fb0c0a12
RK
1293/* See whether X, the source of a set, is something we want to consider for
1294 GCSE. */
7506f491 1295
e2500fed 1296static GTY(()) rtx test_insn;
7506f491
DE
1297static int
1298want_to_gcse_p (x)
1299 rtx x;
1300{
fb0c0a12
RK
1301 int num_clobbers = 0;
1302 int icode;
1303
c4c81601 1304 switch (GET_CODE (x))
7506f491
DE
1305 {
1306 case REG:
1307 case SUBREG:
1308 case CONST_INT:
1309 case CONST_DOUBLE:
69ef87e2 1310 case CONST_VECTOR:
7506f491
DE
1311 case CALL:
1312 return 0;
1313
1314 default:
1315 break;
1316 }
1317
fb0c0a12
RK
1318 /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */
1319 if (general_operand (x, GET_MODE (x)))
1320 return 1;
1321 else if (GET_MODE (x) == VOIDmode)
1322 return 0;
1323
1324 /* Otherwise, check if we can make a valid insn from it. First initialize
1325 our test insn if we haven't already. */
1326 if (test_insn == 0)
1327 {
1328 test_insn
1329 = make_insn_raw (gen_rtx_SET (VOIDmode,
1330 gen_rtx_REG (word_mode,
1331 FIRST_PSEUDO_REGISTER * 2),
1332 const0_rtx));
1333 NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0;
fb0c0a12
RK
1334 }
1335
1336 /* Now make an insn like the one we would make when GCSE'ing and see if
1337 valid. */
1338 PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x));
1339 SET_SRC (PATTERN (test_insn)) = x;
1340 return ((icode = recog (PATTERN (test_insn), test_insn, &num_clobbers)) >= 0
1341 && (num_clobbers == 0 || ! added_clobbers_hard_reg_p (icode)));
7506f491
DE
1342}
1343
1344/* Return non-zero if the operands of expression X are unchanged from the
1345 start of INSN's basic block up to but not including INSN (if AVAIL_P == 0),
1346 or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */
1347
1348static int
1349oprs_unchanged_p (x, insn, avail_p)
1350 rtx x, insn;
1351 int avail_p;
1352{
c4c81601 1353 int i, j;
7506f491 1354 enum rtx_code code;
6f7d635c 1355 const char *fmt;
7506f491 1356
7506f491
DE
1357 if (x == 0)
1358 return 1;
1359
1360 code = GET_CODE (x);
1361 switch (code)
1362 {
1363 case REG:
80c29cc4
RZ
1364 {
1365 struct reg_avail_info *info = &reg_avail_info[REGNO (x)];
1366
1367 if (info->last_bb != current_bb)
1368 return 1;
589005ff 1369 if (avail_p)
80c29cc4
RZ
1370 return info->last_set < INSN_CUID (insn);
1371 else
1372 return info->first_set >= INSN_CUID (insn);
1373 }
7506f491
DE
1374
1375 case MEM:
e0082a72 1376 if (load_killed_in_block_p (current_bb, INSN_CUID (insn),
a13d4ebf
AM
1377 x, avail_p))
1378 return 0;
7506f491 1379 else
c4c81601 1380 return oprs_unchanged_p (XEXP (x, 0), insn, avail_p);
7506f491
DE
1381
1382 case PRE_DEC:
1383 case PRE_INC:
1384 case POST_DEC:
1385 case POST_INC:
4b983fdc
RH
1386 case PRE_MODIFY:
1387 case POST_MODIFY:
7506f491
DE
1388 return 0;
1389
1390 case PC:
1391 case CC0: /*FIXME*/
1392 case CONST:
1393 case CONST_INT:
1394 case CONST_DOUBLE:
69ef87e2 1395 case CONST_VECTOR:
7506f491
DE
1396 case SYMBOL_REF:
1397 case LABEL_REF:
1398 case ADDR_VEC:
1399 case ADDR_DIFF_VEC:
1400 return 1;
1401
1402 default:
1403 break;
1404 }
1405
c4c81601 1406 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1407 {
1408 if (fmt[i] == 'e')
1409 {
c4c81601
RK
1410 /* If we are about to do the last recursive call needed at this
1411 level, change it into iteration. This function is called enough
1412 to be worth it. */
7506f491 1413 if (i == 0)
c4c81601
RK
1414 return oprs_unchanged_p (XEXP (x, i), insn, avail_p);
1415
1416 else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p))
7506f491
DE
1417 return 0;
1418 }
1419 else if (fmt[i] == 'E')
c4c81601
RK
1420 for (j = 0; j < XVECLEN (x, i); j++)
1421 if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p))
1422 return 0;
7506f491
DE
1423 }
1424
1425 return 1;
1426}
1427
a13d4ebf
AM
1428/* Used for communication between mems_conflict_for_gcse_p and
1429 load_killed_in_block_p. Nonzero if mems_conflict_for_gcse_p finds a
1430 conflict between two memory references. */
1431static int gcse_mems_conflict_p;
1432
1433/* Used for communication between mems_conflict_for_gcse_p and
1434 load_killed_in_block_p. A memory reference for a load instruction,
1435 mems_conflict_for_gcse_p will see if a memory store conflicts with
1436 this memory load. */
1437static rtx gcse_mem_operand;
1438
1439/* DEST is the output of an instruction. If it is a memory reference, and
1440 possibly conflicts with the load found in gcse_mem_operand, then set
1441 gcse_mems_conflict_p to a nonzero value. */
1442
1443static void
1444mems_conflict_for_gcse_p (dest, setter, data)
1445 rtx dest, setter ATTRIBUTE_UNUSED;
1446 void *data ATTRIBUTE_UNUSED;
1447{
1448 while (GET_CODE (dest) == SUBREG
1449 || GET_CODE (dest) == ZERO_EXTRACT
1450 || GET_CODE (dest) == SIGN_EXTRACT
1451 || GET_CODE (dest) == STRICT_LOW_PART)
1452 dest = XEXP (dest, 0);
1453
1454 /* If DEST is not a MEM, then it will not conflict with the load. Note
1455 that function calls are assumed to clobber memory, but are handled
1456 elsewhere. */
1457 if (GET_CODE (dest) != MEM)
1458 return;
aaa4ca30 1459
a13d4ebf 1460 /* If we are setting a MEM in our list of specially recognized MEMs,
589005ff
KH
1461 don't mark as killed this time. */
1462
a13d4ebf
AM
1463 if (dest == gcse_mem_operand && pre_ldst_mems != NULL)
1464 {
1465 if (!find_rtx_in_ldst (dest))
1466 gcse_mems_conflict_p = 1;
1467 return;
1468 }
aaa4ca30 1469
a13d4ebf
AM
1470 if (true_dependence (dest, GET_MODE (dest), gcse_mem_operand,
1471 rtx_addr_varies_p))
1472 gcse_mems_conflict_p = 1;
1473}
1474
1475/* Return nonzero if the expression in X (a memory reference) is killed
1476 in block BB before or after the insn with the CUID in UID_LIMIT.
1477 AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills
1478 before UID_LIMIT.
1479
1480 To check the entire block, set UID_LIMIT to max_uid + 1 and
1481 AVAIL_P to 0. */
1482
1483static int
1484load_killed_in_block_p (bb, uid_limit, x, avail_p)
e2d2ed72 1485 basic_block bb;
a13d4ebf
AM
1486 int uid_limit;
1487 rtx x;
1488 int avail_p;
1489{
0b17ab2f 1490 rtx list_entry = modify_mem_list[bb->index];
a13d4ebf
AM
1491 while (list_entry)
1492 {
1493 rtx setter;
1494 /* Ignore entries in the list that do not apply. */
1495 if ((avail_p
1496 && INSN_CUID (XEXP (list_entry, 0)) < uid_limit)
1497 || (! avail_p
1498 && INSN_CUID (XEXP (list_entry, 0)) > uid_limit))
1499 {
1500 list_entry = XEXP (list_entry, 1);
1501 continue;
1502 }
1503
1504 setter = XEXP (list_entry, 0);
1505
1506 /* If SETTER is a call everything is clobbered. Note that calls
1507 to pure functions are never put on the list, so we need not
1508 worry about them. */
1509 if (GET_CODE (setter) == CALL_INSN)
1510 return 1;
1511
1512 /* SETTER must be an INSN of some kind that sets memory. Call
589005ff 1513 note_stores to examine each hunk of memory that is modified.
a13d4ebf
AM
1514
1515 The note_stores interface is pretty limited, so we have to
1516 communicate via global variables. Yuk. */
1517 gcse_mem_operand = x;
1518 gcse_mems_conflict_p = 0;
1519 note_stores (PATTERN (setter), mems_conflict_for_gcse_p, NULL);
1520 if (gcse_mems_conflict_p)
1521 return 1;
1522 list_entry = XEXP (list_entry, 1);
1523 }
1524 return 0;
1525}
1526
7506f491
DE
1527/* Return non-zero if the operands of expression X are unchanged from
1528 the start of INSN's basic block up to but not including INSN. */
1529
1530static int
1531oprs_anticipatable_p (x, insn)
1532 rtx x, insn;
1533{
1534 return oprs_unchanged_p (x, insn, 0);
1535}
1536
1537/* Return non-zero if the operands of expression X are unchanged from
1538 INSN to the end of INSN's basic block. */
1539
1540static int
1541oprs_available_p (x, insn)
1542 rtx x, insn;
1543{
1544 return oprs_unchanged_p (x, insn, 1);
1545}
1546
1547/* Hash expression X.
c4c81601
RK
1548
1549 MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean
1550 indicating if a volatile operand is found or if the expression contains
1551 something we don't want to insert in the table.
7506f491
DE
1552
1553 ??? One might want to merge this with canon_hash. Later. */
1554
1555static unsigned int
1556hash_expr (x, mode, do_not_record_p, hash_table_size)
1557 rtx x;
1558 enum machine_mode mode;
1559 int *do_not_record_p;
1560 int hash_table_size;
1561{
1562 unsigned int hash;
1563
1564 *do_not_record_p = 0;
1565
1566 hash = hash_expr_1 (x, mode, do_not_record_p);
1567 return hash % hash_table_size;
1568}
172890a2 1569
6462bb43 1570/* Hash a string. Just add its bytes up. */
172890a2 1571
6462bb43
AO
1572static inline unsigned
1573hash_string_1 (ps)
1574 const char *ps;
1575{
1576 unsigned hash = 0;
8e42ace1 1577 const unsigned char *p = (const unsigned char *) ps;
589005ff 1578
6462bb43
AO
1579 if (p)
1580 while (*p)
1581 hash += *p++;
1582
1583 return hash;
1584}
7506f491
DE
1585
1586/* Subroutine of hash_expr to do the actual work. */
1587
1588static unsigned int
1589hash_expr_1 (x, mode, do_not_record_p)
1590 rtx x;
1591 enum machine_mode mode;
1592 int *do_not_record_p;
1593{
1594 int i, j;
1595 unsigned hash = 0;
1596 enum rtx_code code;
6f7d635c 1597 const char *fmt;
7506f491 1598
c4c81601
RK
1599 /* Used to turn recursion into iteration. We can't rely on GCC's
1600 tail-recursion eliminatio since we need to keep accumulating values
1601 in HASH. */
7506f491
DE
1602
1603 if (x == 0)
1604 return hash;
1605
c4c81601 1606 repeat:
7506f491
DE
1607 code = GET_CODE (x);
1608 switch (code)
1609 {
1610 case REG:
c4c81601
RK
1611 hash += ((unsigned int) REG << 7) + REGNO (x);
1612 return hash;
7506f491
DE
1613
1614 case CONST_INT:
c4c81601
RK
1615 hash += (((unsigned int) CONST_INT << 7) + (unsigned int) mode
1616 + (unsigned int) INTVAL (x));
1617 return hash;
7506f491
DE
1618
1619 case CONST_DOUBLE:
1620 /* This is like the general case, except that it only counts
1621 the integers representing the constant. */
c4c81601 1622 hash += (unsigned int) code + (unsigned int) GET_MODE (x);
7506f491
DE
1623 if (GET_MODE (x) != VOIDmode)
1624 for (i = 2; i < GET_RTX_LENGTH (CONST_DOUBLE); i++)
c4c81601 1625 hash += (unsigned int) XWINT (x, i);
7506f491 1626 else
c4c81601
RK
1627 hash += ((unsigned int) CONST_DOUBLE_LOW (x)
1628 + (unsigned int) CONST_DOUBLE_HIGH (x));
7506f491
DE
1629 return hash;
1630
69ef87e2
AH
1631 case CONST_VECTOR:
1632 {
1633 int units;
1634 rtx elt;
1635
1636 units = CONST_VECTOR_NUNITS (x);
1637
1638 for (i = 0; i < units; ++i)
1639 {
1640 elt = CONST_VECTOR_ELT (x, i);
1641 hash += hash_expr_1 (elt, GET_MODE (elt), do_not_record_p);
1642 }
1643
1644 return hash;
1645 }
1646
7506f491
DE
1647 /* Assume there is only one rtx object for any given label. */
1648 case LABEL_REF:
1649 /* We don't hash on the address of the CODE_LABEL to avoid bootstrap
1650 differences and differences between each stage's debugging dumps. */
c4c81601
RK
1651 hash += (((unsigned int) LABEL_REF << 7)
1652 + CODE_LABEL_NUMBER (XEXP (x, 0)));
7506f491
DE
1653 return hash;
1654
1655 case SYMBOL_REF:
1656 {
1657 /* Don't hash on the symbol's address to avoid bootstrap differences.
1658 Different hash values may cause expressions to be recorded in
1659 different orders and thus different registers to be used in the
1660 final assembler. This also avoids differences in the dump files
1661 between various stages. */
1662 unsigned int h = 0;
3cce094d 1663 const unsigned char *p = (const unsigned char *) XSTR (x, 0);
c4c81601 1664
7506f491
DE
1665 while (*p)
1666 h += (h << 7) + *p++; /* ??? revisit */
c4c81601
RK
1667
1668 hash += ((unsigned int) SYMBOL_REF << 7) + h;
7506f491
DE
1669 return hash;
1670 }
1671
1672 case MEM:
1673 if (MEM_VOLATILE_P (x))
1674 {
1675 *do_not_record_p = 1;
1676 return 0;
1677 }
c4c81601
RK
1678
1679 hash += (unsigned int) MEM;
d51f3632
JH
1680 /* We used alias set for hashing, but this is not good, since the alias
1681 set may differ in -fprofile-arcs and -fbranch-probabilities compilation
1682 causing the profiles to fail to match. */
7506f491
DE
1683 x = XEXP (x, 0);
1684 goto repeat;
1685
1686 case PRE_DEC:
1687 case PRE_INC:
1688 case POST_DEC:
1689 case POST_INC:
1690 case PC:
1691 case CC0:
1692 case CALL:
1693 case UNSPEC_VOLATILE:
1694 *do_not_record_p = 1;
1695 return 0;
1696
1697 case ASM_OPERANDS:
1698 if (MEM_VOLATILE_P (x))
1699 {
1700 *do_not_record_p = 1;
1701 return 0;
1702 }
6462bb43
AO
1703 else
1704 {
1705 /* We don't want to take the filename and line into account. */
1706 hash += (unsigned) code + (unsigned) GET_MODE (x)
1707 + hash_string_1 (ASM_OPERANDS_TEMPLATE (x))
1708 + hash_string_1 (ASM_OPERANDS_OUTPUT_CONSTRAINT (x))
1709 + (unsigned) ASM_OPERANDS_OUTPUT_IDX (x);
1710
1711 if (ASM_OPERANDS_INPUT_LENGTH (x))
1712 {
1713 for (i = 1; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
1714 {
1715 hash += (hash_expr_1 (ASM_OPERANDS_INPUT (x, i),
1716 GET_MODE (ASM_OPERANDS_INPUT (x, i)),
1717 do_not_record_p)
1718 + hash_string_1 (ASM_OPERANDS_INPUT_CONSTRAINT
1719 (x, i)));
1720 }
1721
1722 hash += hash_string_1 (ASM_OPERANDS_INPUT_CONSTRAINT (x, 0));
1723 x = ASM_OPERANDS_INPUT (x, 0);
1724 mode = GET_MODE (x);
1725 goto repeat;
1726 }
1727 return hash;
1728 }
7506f491
DE
1729
1730 default:
1731 break;
1732 }
1733
7506f491 1734 hash += (unsigned) code + (unsigned) GET_MODE (x);
c4c81601 1735 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1736 {
1737 if (fmt[i] == 'e')
1738 {
7506f491
DE
1739 /* If we are about to do the last recursive call
1740 needed at this level, change it into iteration.
1741 This function is called enough to be worth it. */
1742 if (i == 0)
1743 {
c4c81601 1744 x = XEXP (x, i);
7506f491
DE
1745 goto repeat;
1746 }
c4c81601
RK
1747
1748 hash += hash_expr_1 (XEXP (x, i), 0, do_not_record_p);
7506f491
DE
1749 if (*do_not_record_p)
1750 return 0;
1751 }
c4c81601 1752
7506f491
DE
1753 else if (fmt[i] == 'E')
1754 for (j = 0; j < XVECLEN (x, i); j++)
1755 {
1756 hash += hash_expr_1 (XVECEXP (x, i, j), 0, do_not_record_p);
1757 if (*do_not_record_p)
1758 return 0;
1759 }
c4c81601 1760
7506f491 1761 else if (fmt[i] == 's')
6462bb43 1762 hash += hash_string_1 (XSTR (x, i));
7506f491 1763 else if (fmt[i] == 'i')
c4c81601 1764 hash += (unsigned int) XINT (x, i);
7506f491
DE
1765 else
1766 abort ();
1767 }
1768
1769 return hash;
1770}
1771
1772/* Hash a set of register REGNO.
1773
c4c81601
RK
1774 Sets are hashed on the register that is set. This simplifies the PRE copy
1775 propagation code.
7506f491
DE
1776
1777 ??? May need to make things more elaborate. Later, as necessary. */
1778
1779static unsigned int
1780hash_set (regno, hash_table_size)
1781 int regno;
1782 int hash_table_size;
1783{
1784 unsigned int hash;
1785
1786 hash = regno;
1787 return hash % hash_table_size;
1788}
1789
1790/* Return non-zero if exp1 is equivalent to exp2.
1791 ??? Borrowed from cse.c. Might want to remerge with cse.c. Later. */
1792
1793static int
1794expr_equiv_p (x, y)
1795 rtx x, y;
1796{
b3694847
SS
1797 int i, j;
1798 enum rtx_code code;
1799 const char *fmt;
7506f491
DE
1800
1801 if (x == y)
1802 return 1;
c4c81601 1803
7506f491
DE
1804 if (x == 0 || y == 0)
1805 return x == y;
1806
1807 code = GET_CODE (x);
1808 if (code != GET_CODE (y))
1809 return 0;
1810
1811 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
1812 if (GET_MODE (x) != GET_MODE (y))
1813 return 0;
1814
1815 switch (code)
1816 {
1817 case PC:
1818 case CC0:
1819 return x == y;
1820
1821 case CONST_INT:
1822 return INTVAL (x) == INTVAL (y);
1823
1824 case LABEL_REF:
1825 return XEXP (x, 0) == XEXP (y, 0);
1826
1827 case SYMBOL_REF:
1828 return XSTR (x, 0) == XSTR (y, 0);
1829
1830 case REG:
1831 return REGNO (x) == REGNO (y);
1832
297c3335
RH
1833 case MEM:
1834 /* Can't merge two expressions in different alias sets, since we can
1835 decide that the expression is transparent in a block when it isn't,
1836 due to it being set with the different alias set. */
1837 if (MEM_ALIAS_SET (x) != MEM_ALIAS_SET (y))
1838 return 0;
1839 break;
1840
7506f491
DE
1841 /* For commutative operations, check both orders. */
1842 case PLUS:
1843 case MULT:
1844 case AND:
1845 case IOR:
1846 case XOR:
1847 case NE:
1848 case EQ:
1849 return ((expr_equiv_p (XEXP (x, 0), XEXP (y, 0))
1850 && expr_equiv_p (XEXP (x, 1), XEXP (y, 1)))
1851 || (expr_equiv_p (XEXP (x, 0), XEXP (y, 1))
1852 && expr_equiv_p (XEXP (x, 1), XEXP (y, 0))));
1853
6462bb43
AO
1854 case ASM_OPERANDS:
1855 /* We don't use the generic code below because we want to
1856 disregard filename and line numbers. */
1857
1858 /* A volatile asm isn't equivalent to any other. */
1859 if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y))
1860 return 0;
1861
1862 if (GET_MODE (x) != GET_MODE (y)
1863 || strcmp (ASM_OPERANDS_TEMPLATE (x), ASM_OPERANDS_TEMPLATE (y))
1864 || strcmp (ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
1865 ASM_OPERANDS_OUTPUT_CONSTRAINT (y))
1866 || ASM_OPERANDS_OUTPUT_IDX (x) != ASM_OPERANDS_OUTPUT_IDX (y)
1867 || ASM_OPERANDS_INPUT_LENGTH (x) != ASM_OPERANDS_INPUT_LENGTH (y))
1868 return 0;
1869
1870 if (ASM_OPERANDS_INPUT_LENGTH (x))
1871 {
1872 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
1873 if (! expr_equiv_p (ASM_OPERANDS_INPUT (x, i),
1874 ASM_OPERANDS_INPUT (y, i))
1875 || strcmp (ASM_OPERANDS_INPUT_CONSTRAINT (x, i),
1876 ASM_OPERANDS_INPUT_CONSTRAINT (y, i)))
1877 return 0;
1878 }
1879
1880 return 1;
1881
7506f491
DE
1882 default:
1883 break;
1884 }
1885
1886 /* Compare the elements. If any pair of corresponding elements
1887 fail to match, return 0 for the whole thing. */
1888
1889 fmt = GET_RTX_FORMAT (code);
1890 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1891 {
1892 switch (fmt[i])
1893 {
1894 case 'e':
1895 if (! expr_equiv_p (XEXP (x, i), XEXP (y, i)))
1896 return 0;
1897 break;
1898
1899 case 'E':
1900 if (XVECLEN (x, i) != XVECLEN (y, i))
1901 return 0;
1902 for (j = 0; j < XVECLEN (x, i); j++)
1903 if (! expr_equiv_p (XVECEXP (x, i, j), XVECEXP (y, i, j)))
1904 return 0;
1905 break;
1906
1907 case 's':
1908 if (strcmp (XSTR (x, i), XSTR (y, i)))
1909 return 0;
1910 break;
1911
1912 case 'i':
1913 if (XINT (x, i) != XINT (y, i))
1914 return 0;
1915 break;
1916
1917 case 'w':
1918 if (XWINT (x, i) != XWINT (y, i))
1919 return 0;
1920 break;
1921
1922 case '0':
1923 break;
aaa4ca30 1924
7506f491
DE
1925 default:
1926 abort ();
1927 }
8e42ace1 1928 }
7506f491
DE
1929
1930 return 1;
1931}
1932
02280659 1933/* Insert expression X in INSN in the hash TABLE.
7506f491
DE
1934 If it is already present, record it as the last occurrence in INSN's
1935 basic block.
1936
1937 MODE is the mode of the value X is being stored into.
1938 It is only used if X is a CONST_INT.
1939
1940 ANTIC_P is non-zero if X is an anticipatable expression.
1941 AVAIL_P is non-zero if X is an available expression. */
1942
1943static void
02280659 1944insert_expr_in_table (x, mode, insn, antic_p, avail_p, table)
7506f491
DE
1945 rtx x;
1946 enum machine_mode mode;
1947 rtx insn;
1948 int antic_p, avail_p;
02280659 1949 struct hash_table *table;
7506f491
DE
1950{
1951 int found, do_not_record_p;
1952 unsigned int hash;
1953 struct expr *cur_expr, *last_expr = NULL;
1954 struct occr *antic_occr, *avail_occr;
1955 struct occr *last_occr = NULL;
1956
02280659 1957 hash = hash_expr (x, mode, &do_not_record_p, table->size);
7506f491
DE
1958
1959 /* Do not insert expression in table if it contains volatile operands,
1960 or if hash_expr determines the expression is something we don't want
1961 to or can't handle. */
1962 if (do_not_record_p)
1963 return;
1964
02280659 1965 cur_expr = table->table[hash];
7506f491
DE
1966 found = 0;
1967
c4c81601 1968 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1969 {
1970 /* If the expression isn't found, save a pointer to the end of
1971 the list. */
1972 last_expr = cur_expr;
1973 cur_expr = cur_expr->next_same_hash;
1974 }
1975
1976 if (! found)
1977 {
1978 cur_expr = (struct expr *) gcse_alloc (sizeof (struct expr));
1979 bytes_used += sizeof (struct expr);
02280659 1980 if (table->table[hash] == NULL)
c4c81601 1981 /* This is the first pattern that hashed to this index. */
02280659 1982 table->table[hash] = cur_expr;
7506f491 1983 else
c4c81601
RK
1984 /* Add EXPR to end of this hash chain. */
1985 last_expr->next_same_hash = cur_expr;
1986
589005ff 1987 /* Set the fields of the expr element. */
7506f491 1988 cur_expr->expr = x;
02280659 1989 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1990 cur_expr->next_same_hash = NULL;
1991 cur_expr->antic_occr = NULL;
1992 cur_expr->avail_occr = NULL;
1993 }
1994
1995 /* Now record the occurrence(s). */
7506f491
DE
1996 if (antic_p)
1997 {
1998 antic_occr = cur_expr->antic_occr;
1999
2000 /* Search for another occurrence in the same basic block. */
2001 while (antic_occr && BLOCK_NUM (antic_occr->insn) != BLOCK_NUM (insn))
2002 {
2003 /* If an occurrence isn't found, save a pointer to the end of
2004 the list. */
2005 last_occr = antic_occr;
2006 antic_occr = antic_occr->next;
2007 }
2008
2009 if (antic_occr)
c4c81601
RK
2010 /* Found another instance of the expression in the same basic block.
2011 Prefer the currently recorded one. We want the first one in the
2012 block and the block is scanned from start to end. */
2013 ; /* nothing to do */
7506f491
DE
2014 else
2015 {
2016 /* First occurrence of this expression in this basic block. */
2017 antic_occr = (struct occr *) gcse_alloc (sizeof (struct occr));
2018 bytes_used += sizeof (struct occr);
2019 /* First occurrence of this expression in any block? */
2020 if (cur_expr->antic_occr == NULL)
2021 cur_expr->antic_occr = antic_occr;
2022 else
2023 last_occr->next = antic_occr;
c4c81601 2024
7506f491
DE
2025 antic_occr->insn = insn;
2026 antic_occr->next = NULL;
2027 }
2028 }
2029
2030 if (avail_p)
2031 {
2032 avail_occr = cur_expr->avail_occr;
2033
2034 /* Search for another occurrence in the same basic block. */
2035 while (avail_occr && BLOCK_NUM (avail_occr->insn) != BLOCK_NUM (insn))
2036 {
2037 /* If an occurrence isn't found, save a pointer to the end of
2038 the list. */
2039 last_occr = avail_occr;
2040 avail_occr = avail_occr->next;
2041 }
2042
2043 if (avail_occr)
c4c81601
RK
2044 /* Found another instance of the expression in the same basic block.
2045 Prefer this occurrence to the currently recorded one. We want
2046 the last one in the block and the block is scanned from start
2047 to end. */
2048 avail_occr->insn = insn;
7506f491
DE
2049 else
2050 {
2051 /* First occurrence of this expression in this basic block. */
2052 avail_occr = (struct occr *) gcse_alloc (sizeof (struct occr));
2053 bytes_used += sizeof (struct occr);
c4c81601 2054
7506f491
DE
2055 /* First occurrence of this expression in any block? */
2056 if (cur_expr->avail_occr == NULL)
2057 cur_expr->avail_occr = avail_occr;
2058 else
2059 last_occr->next = avail_occr;
c4c81601 2060
7506f491
DE
2061 avail_occr->insn = insn;
2062 avail_occr->next = NULL;
2063 }
2064 }
2065}
2066
2067/* Insert pattern X in INSN in the hash table.
2068 X is a SET of a reg to either another reg or a constant.
2069 If it is already present, record it as the last occurrence in INSN's
2070 basic block. */
2071
2072static void
02280659 2073insert_set_in_table (x, insn, table)
7506f491
DE
2074 rtx x;
2075 rtx insn;
02280659 2076 struct hash_table *table;
7506f491
DE
2077{
2078 int found;
2079 unsigned int hash;
2080 struct expr *cur_expr, *last_expr = NULL;
2081 struct occr *cur_occr, *last_occr = NULL;
2082
2083 if (GET_CODE (x) != SET
2084 || GET_CODE (SET_DEST (x)) != REG)
2085 abort ();
2086
02280659 2087 hash = hash_set (REGNO (SET_DEST (x)), table->size);
7506f491 2088
02280659 2089 cur_expr = table->table[hash];
7506f491
DE
2090 found = 0;
2091
c4c81601 2092 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
2093 {
2094 /* If the expression isn't found, save a pointer to the end of
2095 the list. */
2096 last_expr = cur_expr;
2097 cur_expr = cur_expr->next_same_hash;
2098 }
2099
2100 if (! found)
2101 {
2102 cur_expr = (struct expr *) gcse_alloc (sizeof (struct expr));
2103 bytes_used += sizeof (struct expr);
02280659 2104 if (table->table[hash] == NULL)
c4c81601 2105 /* This is the first pattern that hashed to this index. */
02280659 2106 table->table[hash] = cur_expr;
7506f491 2107 else
c4c81601
RK
2108 /* Add EXPR to end of this hash chain. */
2109 last_expr->next_same_hash = cur_expr;
2110
7506f491
DE
2111 /* Set the fields of the expr element.
2112 We must copy X because it can be modified when copy propagation is
2113 performed on its operands. */
7506f491 2114 cur_expr->expr = copy_rtx (x);
02280659 2115 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
2116 cur_expr->next_same_hash = NULL;
2117 cur_expr->antic_occr = NULL;
2118 cur_expr->avail_occr = NULL;
2119 }
2120
2121 /* Now record the occurrence. */
7506f491
DE
2122 cur_occr = cur_expr->avail_occr;
2123
2124 /* Search for another occurrence in the same basic block. */
2125 while (cur_occr && BLOCK_NUM (cur_occr->insn) != BLOCK_NUM (insn))
2126 {
2127 /* If an occurrence isn't found, save a pointer to the end of
2128 the list. */
2129 last_occr = cur_occr;
2130 cur_occr = cur_occr->next;
2131 }
2132
2133 if (cur_occr)
c4c81601
RK
2134 /* Found another instance of the expression in the same basic block.
2135 Prefer this occurrence to the currently recorded one. We want the
2136 last one in the block and the block is scanned from start to end. */
2137 cur_occr->insn = insn;
7506f491
DE
2138 else
2139 {
2140 /* First occurrence of this expression in this basic block. */
2141 cur_occr = (struct occr *) gcse_alloc (sizeof (struct occr));
2142 bytes_used += sizeof (struct occr);
c4c81601 2143
7506f491
DE
2144 /* First occurrence of this expression in any block? */
2145 if (cur_expr->avail_occr == NULL)
2146 cur_expr->avail_occr = cur_occr;
2147 else
2148 last_occr->next = cur_occr;
c4c81601 2149
7506f491
DE
2150 cur_occr->insn = insn;
2151 cur_occr->next = NULL;
2152 }
2153}
2154
02280659
ZD
2155/* Scan pattern PAT of INSN and add an entry to the hash TABLE (set or
2156 expression one). */
7506f491
DE
2157
2158static void
02280659 2159hash_scan_set (pat, insn, table)
7506f491 2160 rtx pat, insn;
02280659 2161 struct hash_table *table;
7506f491
DE
2162{
2163 rtx src = SET_SRC (pat);
2164 rtx dest = SET_DEST (pat);
172890a2 2165 rtx note;
7506f491
DE
2166
2167 if (GET_CODE (src) == CALL)
02280659 2168 hash_scan_call (src, insn, table);
7506f491 2169
172890a2 2170 else if (GET_CODE (dest) == REG)
7506f491 2171 {
172890a2 2172 unsigned int regno = REGNO (dest);
7506f491
DE
2173 rtx tmp;
2174
172890a2
RK
2175 /* If this is a single set and we are doing constant propagation,
2176 see if a REG_NOTE shows this equivalent to a constant. */
02280659 2177 if (table->set_p && (note = find_reg_equal_equiv_note (insn)) != 0
172890a2
RK
2178 && CONSTANT_P (XEXP (note, 0)))
2179 src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src);
2180
7506f491 2181 /* Only record sets of pseudo-regs in the hash table. */
02280659 2182 if (! table->set_p
7506f491
DE
2183 && regno >= FIRST_PSEUDO_REGISTER
2184 /* Don't GCSE something if we can't do a reg/reg copy. */
2185 && can_copy_p [GET_MODE (dest)]
068473ec
JH
2186 /* GCSE commonly inserts instruction after the insn. We can't
2187 do that easily for EH_REGION notes so disable GCSE on these
2188 for now. */
2189 && !find_reg_note (insn, REG_EH_REGION, NULL_RTX)
7506f491 2190 /* Is SET_SRC something we want to gcse? */
172890a2
RK
2191 && want_to_gcse_p (src)
2192 /* Don't CSE a nop. */
43e72072
JJ
2193 && ! set_noop_p (pat)
2194 /* Don't GCSE if it has attached REG_EQUIV note.
2195 At this point this only function parameters should have
2196 REG_EQUIV notes and if the argument slot is used somewhere
a1f300c0 2197 explicitly, it means address of parameter has been taken,
43e72072
JJ
2198 so we should not extend the lifetime of the pseudo. */
2199 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
2200 || GET_CODE (XEXP (note, 0)) != MEM))
7506f491
DE
2201 {
2202 /* An expression is not anticipatable if its operands are
52d76e11
RK
2203 modified before this insn or if this is not the only SET in
2204 this insn. */
2205 int antic_p = oprs_anticipatable_p (src, insn) && single_set (insn);
7506f491 2206 /* An expression is not available if its operands are
eb296bd9
GK
2207 subsequently modified, including this insn. It's also not
2208 available if this is a branch, because we can't insert
2209 a set after the branch. */
2210 int avail_p = (oprs_available_p (src, insn)
2211 && ! JUMP_P (insn));
c4c81601 2212
02280659 2213 insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table);
7506f491 2214 }
c4c81601 2215
7506f491 2216 /* Record sets for constant/copy propagation. */
02280659 2217 else if (table->set_p
7506f491
DE
2218 && regno >= FIRST_PSEUDO_REGISTER
2219 && ((GET_CODE (src) == REG
2220 && REGNO (src) >= FIRST_PSEUDO_REGISTER
172890a2
RK
2221 && can_copy_p [GET_MODE (dest)]
2222 && REGNO (src) != regno)
b446e5a2 2223 || CONSTANT_P (src))
7506f491
DE
2224 /* A copy is not available if its src or dest is subsequently
2225 modified. Here we want to search from INSN+1 on, but
2226 oprs_available_p searches from INSN on. */
2227 && (insn == BLOCK_END (BLOCK_NUM (insn))
2228 || ((tmp = next_nonnote_insn (insn)) != NULL_RTX
2229 && oprs_available_p (pat, tmp))))
02280659 2230 insert_set_in_table (pat, insn, table);
7506f491 2231 }
7506f491
DE
2232}
2233
2234static void
02280659 2235hash_scan_clobber (x, insn, table)
50b2596f 2236 rtx x ATTRIBUTE_UNUSED, insn ATTRIBUTE_UNUSED;
02280659 2237 struct hash_table *table ATTRIBUTE_UNUSED;
7506f491
DE
2238{
2239 /* Currently nothing to do. */
2240}
2241
2242static void
02280659 2243hash_scan_call (x, insn, table)
50b2596f 2244 rtx x ATTRIBUTE_UNUSED, insn ATTRIBUTE_UNUSED;
02280659 2245 struct hash_table *table ATTRIBUTE_UNUSED;
7506f491
DE
2246{
2247 /* Currently nothing to do. */
2248}
2249
2250/* Process INSN and add hash table entries as appropriate.
2251
2252 Only available expressions that set a single pseudo-reg are recorded.
2253
2254 Single sets in a PARALLEL could be handled, but it's an extra complication
2255 that isn't dealt with right now. The trick is handling the CLOBBERs that
2256 are also in the PARALLEL. Later.
2257
2258 If SET_P is non-zero, this is for the assignment hash table,
ed79bb3d
R
2259 otherwise it is for the expression hash table.
2260 If IN_LIBCALL_BLOCK nonzero, we are in a libcall block, and should
2261 not record any expressions. */
7506f491
DE
2262
2263static void
02280659 2264hash_scan_insn (insn, table, in_libcall_block)
7506f491 2265 rtx insn;
02280659 2266 struct hash_table *table;
48e87cef 2267 int in_libcall_block;
7506f491
DE
2268{
2269 rtx pat = PATTERN (insn);
c4c81601 2270 int i;
7506f491 2271
172890a2
RK
2272 if (in_libcall_block)
2273 return;
2274
7506f491
DE
2275 /* Pick out the sets of INSN and for other forms of instructions record
2276 what's been modified. */
2277
172890a2 2278 if (GET_CODE (pat) == SET)
02280659 2279 hash_scan_set (pat, insn, table);
7506f491 2280 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
2281 for (i = 0; i < XVECLEN (pat, 0); i++)
2282 {
2283 rtx x = XVECEXP (pat, 0, i);
7506f491 2284
c4c81601 2285 if (GET_CODE (x) == SET)
02280659 2286 hash_scan_set (x, insn, table);
c4c81601 2287 else if (GET_CODE (x) == CLOBBER)
02280659 2288 hash_scan_clobber (x, insn, table);
c4c81601 2289 else if (GET_CODE (x) == CALL)
02280659 2290 hash_scan_call (x, insn, table);
c4c81601 2291 }
7506f491 2292
7506f491 2293 else if (GET_CODE (pat) == CLOBBER)
02280659 2294 hash_scan_clobber (pat, insn, table);
7506f491 2295 else if (GET_CODE (pat) == CALL)
02280659 2296 hash_scan_call (pat, insn, table);
7506f491
DE
2297}
2298
2299static void
02280659 2300dump_hash_table (file, name, table)
7506f491 2301 FILE *file;
dff01034 2302 const char *name;
02280659 2303 struct hash_table *table;
7506f491
DE
2304{
2305 int i;
2306 /* Flattened out table, so it's printed in proper order. */
4da896b2
MM
2307 struct expr **flat_table;
2308 unsigned int *hash_val;
c4c81601 2309 struct expr *expr;
4da896b2 2310
589005ff 2311 flat_table
02280659
ZD
2312 = (struct expr **) xcalloc (table->n_elems, sizeof (struct expr *));
2313 hash_val = (unsigned int *) xmalloc (table->n_elems * sizeof (unsigned int));
7506f491 2314
02280659
ZD
2315 for (i = 0; i < (int) table->size; i++)
2316 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
2317 {
2318 flat_table[expr->bitmap_index] = expr;
2319 hash_val[expr->bitmap_index] = i;
2320 }
7506f491
DE
2321
2322 fprintf (file, "%s hash table (%d buckets, %d entries)\n",
02280659 2323 name, table->size, table->n_elems);
7506f491 2324
02280659 2325 for (i = 0; i < (int) table->n_elems; i++)
21318741
RK
2326 if (flat_table[i] != 0)
2327 {
a0ac9e5a 2328 expr = flat_table[i];
21318741
RK
2329 fprintf (file, "Index %d (hash value %d)\n ",
2330 expr->bitmap_index, hash_val[i]);
a0ac9e5a 2331 print_rtl (file, expr->expr);
21318741
RK
2332 fprintf (file, "\n");
2333 }
7506f491
DE
2334
2335 fprintf (file, "\n");
4da896b2 2336
4da896b2
MM
2337 free (flat_table);
2338 free (hash_val);
7506f491
DE
2339}
2340
2341/* Record register first/last/block set information for REGNO in INSN.
c4c81601 2342
80c29cc4 2343 first_set records the first place in the block where the register
7506f491 2344 is set and is used to compute "anticipatability".
c4c81601 2345
80c29cc4 2346 last_set records the last place in the block where the register
7506f491 2347 is set and is used to compute "availability".
c4c81601 2348
80c29cc4
RZ
2349 last_bb records the block for which first_set and last_set are
2350 valid, as a quick test to invalidate them.
2351
7506f491
DE
2352 reg_set_in_block records whether the register is set in the block
2353 and is used to compute "transparency". */
2354
2355static void
2356record_last_reg_set_info (insn, regno)
2357 rtx insn;
2358 int regno;
2359{
80c29cc4
RZ
2360 struct reg_avail_info *info = &reg_avail_info[regno];
2361 int cuid = INSN_CUID (insn);
c4c81601 2362
80c29cc4
RZ
2363 info->last_set = cuid;
2364 if (info->last_bb != current_bb)
2365 {
2366 info->last_bb = current_bb;
2367 info->first_set = cuid;
e0082a72 2368 SET_BIT (reg_set_in_block[current_bb->index], regno);
80c29cc4 2369 }
7506f491
DE
2370}
2371
a13d4ebf
AM
2372
2373/* Record all of the canonicalized MEMs of record_last_mem_set_info's insn.
2374 Note we store a pair of elements in the list, so they have to be
2375 taken off pairwise. */
2376
589005ff 2377static void
a13d4ebf
AM
2378canon_list_insert (dest, unused1, v_insn)
2379 rtx dest ATTRIBUTE_UNUSED;
2380 rtx unused1 ATTRIBUTE_UNUSED;
2381 void * v_insn;
2382{
2383 rtx dest_addr, insn;
0fe854a7 2384 int bb;
a13d4ebf
AM
2385
2386 while (GET_CODE (dest) == SUBREG
2387 || GET_CODE (dest) == ZERO_EXTRACT
2388 || GET_CODE (dest) == SIGN_EXTRACT
2389 || GET_CODE (dest) == STRICT_LOW_PART)
2390 dest = XEXP (dest, 0);
2391
2392 /* If DEST is not a MEM, then it will not conflict with a load. Note
2393 that function calls are assumed to clobber memory, but are handled
2394 elsewhere. */
2395
2396 if (GET_CODE (dest) != MEM)
2397 return;
2398
2399 dest_addr = get_addr (XEXP (dest, 0));
2400 dest_addr = canon_rtx (dest_addr);
589005ff 2401 insn = (rtx) v_insn;
0fe854a7 2402 bb = BLOCK_NUM (insn);
a13d4ebf 2403
589005ff 2404 canon_modify_mem_list[bb] =
0fe854a7 2405 alloc_EXPR_LIST (VOIDmode, dest_addr, canon_modify_mem_list[bb]);
589005ff 2406 canon_modify_mem_list[bb] =
0fe854a7
RH
2407 alloc_EXPR_LIST (VOIDmode, dest, canon_modify_mem_list[bb]);
2408 bitmap_set_bit (canon_modify_mem_list_set, bb);
a13d4ebf
AM
2409}
2410
a13d4ebf
AM
2411/* Record memory modification information for INSN. We do not actually care
2412 about the memory location(s) that are set, or even how they are set (consider
2413 a CALL_INSN). We merely need to record which insns modify memory. */
7506f491
DE
2414
2415static void
2416record_last_mem_set_info (insn)
2417 rtx insn;
2418{
0fe854a7
RH
2419 int bb = BLOCK_NUM (insn);
2420
ccef9ef5 2421 /* load_killed_in_block_p will handle the case of calls clobbering
dc297297 2422 everything. */
0fe854a7
RH
2423 modify_mem_list[bb] = alloc_INSN_LIST (insn, modify_mem_list[bb]);
2424 bitmap_set_bit (modify_mem_list_set, bb);
a13d4ebf
AM
2425
2426 if (GET_CODE (insn) == CALL_INSN)
2427 {
2428 /* Note that traversals of this loop (other than for free-ing)
2429 will break after encountering a CALL_INSN. So, there's no
dc297297 2430 need to insert a pair of items, as canon_list_insert does. */
589005ff
KH
2431 canon_modify_mem_list[bb] =
2432 alloc_INSN_LIST (insn, canon_modify_mem_list[bb]);
0fe854a7 2433 bitmap_set_bit (canon_modify_mem_list_set, bb);
a13d4ebf
AM
2434 }
2435 else
0fe854a7 2436 note_stores (PATTERN (insn), canon_list_insert, (void*) insn);
7506f491
DE
2437}
2438
7506f491 2439/* Called from compute_hash_table via note_stores to handle one
84832317
MM
2440 SET or CLOBBER in an insn. DATA is really the instruction in which
2441 the SET is taking place. */
7506f491
DE
2442
2443static void
84832317 2444record_last_set_info (dest, setter, data)
50b2596f 2445 rtx dest, setter ATTRIBUTE_UNUSED;
84832317 2446 void *data;
7506f491 2447{
84832317
MM
2448 rtx last_set_insn = (rtx) data;
2449
7506f491
DE
2450 if (GET_CODE (dest) == SUBREG)
2451 dest = SUBREG_REG (dest);
2452
2453 if (GET_CODE (dest) == REG)
2454 record_last_reg_set_info (last_set_insn, REGNO (dest));
2455 else if (GET_CODE (dest) == MEM
2456 /* Ignore pushes, they clobber nothing. */
2457 && ! push_operand (dest, GET_MODE (dest)))
2458 record_last_mem_set_info (last_set_insn);
2459}
2460
2461/* Top level function to create an expression or assignment hash table.
2462
2463 Expression entries are placed in the hash table if
2464 - they are of the form (set (pseudo-reg) src),
2465 - src is something we want to perform GCSE on,
2466 - none of the operands are subsequently modified in the block
2467
2468 Assignment entries are placed in the hash table if
2469 - they are of the form (set (pseudo-reg) src),
2470 - src is something we want to perform const/copy propagation on,
2471 - none of the operands or target are subsequently modified in the block
c4c81601 2472
7506f491
DE
2473 Currently src must be a pseudo-reg or a const_int.
2474
2475 F is the first insn.
02280659 2476 TABLE is the table computed. */
7506f491
DE
2477
2478static void
02280659
ZD
2479compute_hash_table_work (table)
2480 struct hash_table *table;
7506f491 2481{
80c29cc4 2482 unsigned int i;
7506f491
DE
2483
2484 /* While we compute the hash table we also compute a bit array of which
2485 registers are set in which blocks.
7506f491
DE
2486 ??? This isn't needed during const/copy propagation, but it's cheap to
2487 compute. Later. */
d55bc081 2488 sbitmap_vector_zero (reg_set_in_block, last_basic_block);
7506f491 2489
a13d4ebf 2490 /* re-Cache any INSN_LIST nodes we have allocated. */
73991d6a 2491 clear_modify_mem_tables ();
7506f491 2492 /* Some working arrays used to track first and last set in each block. */
80c29cc4
RZ
2493 reg_avail_info = (struct reg_avail_info*)
2494 gmalloc (max_gcse_regno * sizeof (struct reg_avail_info));
2495
2496 for (i = 0; i < max_gcse_regno; ++i)
e0082a72 2497 reg_avail_info[i].last_bb = NULL;
7506f491 2498
e0082a72 2499 FOR_EACH_BB (current_bb)
7506f491
DE
2500 {
2501 rtx insn;
770ae6cc 2502 unsigned int regno;
ed79bb3d 2503 int in_libcall_block;
7506f491
DE
2504
2505 /* First pass over the instructions records information used to
2506 determine when registers and memory are first and last set.
ccef9ef5 2507 ??? hard-reg reg_set_in_block computation
7506f491
DE
2508 could be moved to compute_sets since they currently don't change. */
2509
e0082a72
ZD
2510 for (insn = current_bb->head;
2511 insn && insn != NEXT_INSN (current_bb->end);
7506f491
DE
2512 insn = NEXT_INSN (insn))
2513 {
2c3c49de 2514 if (! INSN_P (insn))
7506f491
DE
2515 continue;
2516
2517 if (GET_CODE (insn) == CALL_INSN)
2518 {
19652adf 2519 bool clobbers_all = false;
589005ff 2520#ifdef NON_SAVING_SETJMP
19652adf
ZW
2521 if (NON_SAVING_SETJMP
2522 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
2523 clobbers_all = true;
2524#endif
2525
7506f491 2526 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
19652adf
ZW
2527 if (clobbers_all
2528 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
7506f491 2529 record_last_reg_set_info (insn, regno);
c4c81601 2530
24a28584 2531 mark_call (insn);
7506f491
DE
2532 }
2533
84832317 2534 note_stores (PATTERN (insn), record_last_set_info, insn);
7506f491
DE
2535 }
2536
2537 /* The next pass builds the hash table. */
2538
e0082a72
ZD
2539 for (insn = current_bb->head, in_libcall_block = 0;
2540 insn && insn != NEXT_INSN (current_bb->end);
7506f491 2541 insn = NEXT_INSN (insn))
2c3c49de 2542 if (INSN_P (insn))
c4c81601
RK
2543 {
2544 if (find_reg_note (insn, REG_LIBCALL, NULL_RTX))
589005ff 2545 in_libcall_block = 1;
02280659 2546 else if (table->set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
589005ff 2547 in_libcall_block = 0;
02280659
ZD
2548 hash_scan_insn (insn, table, in_libcall_block);
2549 if (!table->set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
589005ff 2550 in_libcall_block = 0;
8e42ace1 2551 }
7506f491
DE
2552 }
2553
80c29cc4
RZ
2554 free (reg_avail_info);
2555 reg_avail_info = NULL;
7506f491
DE
2556}
2557
02280659 2558/* Allocate space for the set/expr hash TABLE.
7506f491 2559 N_INSNS is the number of instructions in the function.
02280659
ZD
2560 It is used to determine the number of buckets to use.
2561 SET_P determines whether set or expression table will
2562 be created. */
7506f491
DE
2563
2564static void
02280659 2565alloc_hash_table (n_insns, table, set_p)
7506f491 2566 int n_insns;
02280659
ZD
2567 struct hash_table *table;
2568 int set_p;
7506f491
DE
2569{
2570 int n;
2571
02280659
ZD
2572 table->size = n_insns / 4;
2573 if (table->size < 11)
2574 table->size = 11;
c4c81601 2575
7506f491
DE
2576 /* Attempt to maintain efficient use of hash table.
2577 Making it an odd number is simplest for now.
2578 ??? Later take some measurements. */
02280659
ZD
2579 table->size |= 1;
2580 n = table->size * sizeof (struct expr *);
2581 table->table = (struct expr **) gmalloc (n);
2582 table->set_p = set_p;
7506f491
DE
2583}
2584
02280659 2585/* Free things allocated by alloc_hash_table. */
7506f491
DE
2586
2587static void
02280659
ZD
2588free_hash_table (table)
2589 struct hash_table *table;
7506f491 2590{
02280659 2591 free (table->table);
7506f491
DE
2592}
2593
02280659
ZD
2594/* Compute the hash TABLE for doing copy/const propagation or
2595 expression hash table. */
7506f491
DE
2596
2597static void
02280659
ZD
2598compute_hash_table (table)
2599 struct hash_table *table;
7506f491
DE
2600{
2601 /* Initialize count of number of entries in hash table. */
02280659
ZD
2602 table->n_elems = 0;
2603 memset ((char *) table->table, 0,
2604 table->size * sizeof (struct expr *));
7506f491 2605
02280659 2606 compute_hash_table_work (table);
7506f491
DE
2607}
2608\f
2609/* Expression tracking support. */
2610
02280659 2611/* Lookup pattern PAT in the expression TABLE.
7506f491
DE
2612 The result is a pointer to the table entry, or NULL if not found. */
2613
2614static struct expr *
02280659 2615lookup_expr (pat, table)
7506f491 2616 rtx pat;
02280659 2617 struct hash_table *table;
7506f491
DE
2618{
2619 int do_not_record_p;
2620 unsigned int hash = hash_expr (pat, GET_MODE (pat), &do_not_record_p,
02280659 2621 table->size);
7506f491
DE
2622 struct expr *expr;
2623
2624 if (do_not_record_p)
2625 return NULL;
2626
02280659 2627 expr = table->table[hash];
7506f491
DE
2628
2629 while (expr && ! expr_equiv_p (expr->expr, pat))
2630 expr = expr->next_same_hash;
2631
2632 return expr;
2633}
2634
02280659 2635/* Lookup REGNO in the set TABLE. If PAT is non-NULL look for the entry that
c4c81601
RK
2636 matches it, otherwise return the first entry for REGNO. The result is a
2637 pointer to the table entry, or NULL if not found. */
7506f491
DE
2638
2639static struct expr *
02280659 2640lookup_set (regno, pat, table)
770ae6cc 2641 unsigned int regno;
7506f491 2642 rtx pat;
02280659 2643 struct hash_table *table;
7506f491 2644{
02280659 2645 unsigned int hash = hash_set (regno, table->size);
7506f491
DE
2646 struct expr *expr;
2647
02280659 2648 expr = table->table[hash];
7506f491
DE
2649
2650 if (pat)
2651 {
2652 while (expr && ! expr_equiv_p (expr->expr, pat))
2653 expr = expr->next_same_hash;
2654 }
2655 else
2656 {
2657 while (expr && REGNO (SET_DEST (expr->expr)) != regno)
2658 expr = expr->next_same_hash;
2659 }
2660
2661 return expr;
2662}
2663
2664/* Return the next entry for REGNO in list EXPR. */
2665
2666static struct expr *
2667next_set (regno, expr)
770ae6cc 2668 unsigned int regno;
7506f491
DE
2669 struct expr *expr;
2670{
2671 do
2672 expr = expr->next_same_hash;
2673 while (expr && REGNO (SET_DEST (expr->expr)) != regno);
c4c81601 2674
7506f491
DE
2675 return expr;
2676}
2677
0fe854a7
RH
2678/* Like free_INSN_LIST_list or free_EXPR_LIST_list, except that the node
2679 types may be mixed. */
2680
2681static void
2682free_insn_expr_list_list (listp)
2683 rtx *listp;
2684{
2685 rtx list, next;
2686
2687 for (list = *listp; list ; list = next)
2688 {
2689 next = XEXP (list, 1);
2690 if (GET_CODE (list) == EXPR_LIST)
2691 free_EXPR_LIST_node (list);
2692 else
2693 free_INSN_LIST_node (list);
2694 }
2695
2696 *listp = NULL;
2697}
2698
73991d6a
JH
2699/* Clear canon_modify_mem_list and modify_mem_list tables. */
2700static void
2701clear_modify_mem_tables ()
2702{
2703 int i;
2704
2705 EXECUTE_IF_SET_IN_BITMAP
0fe854a7
RH
2706 (modify_mem_list_set, 0, i, free_INSN_LIST_list (modify_mem_list + i));
2707 bitmap_clear (modify_mem_list_set);
73991d6a
JH
2708
2709 EXECUTE_IF_SET_IN_BITMAP
2710 (canon_modify_mem_list_set, 0, i,
0fe854a7
RH
2711 free_insn_expr_list_list (canon_modify_mem_list + i));
2712 bitmap_clear (canon_modify_mem_list_set);
73991d6a
JH
2713}
2714
2715/* Release memory used by modify_mem_list_set and canon_modify_mem_list_set. */
2716
2717static void
2718free_modify_mem_tables ()
2719{
2720 clear_modify_mem_tables ();
2721 free (modify_mem_list);
2722 free (canon_modify_mem_list);
2723 modify_mem_list = 0;
2724 canon_modify_mem_list = 0;
2725}
2726
7506f491
DE
2727/* Reset tables used to keep track of what's still available [since the
2728 start of the block]. */
2729
2730static void
2731reset_opr_set_tables ()
2732{
2733 /* Maintain a bitmap of which regs have been set since beginning of
2734 the block. */
73991d6a 2735 CLEAR_REG_SET (reg_set_bitmap);
c4c81601 2736
7506f491
DE
2737 /* Also keep a record of the last instruction to modify memory.
2738 For now this is very trivial, we only record whether any memory
2739 location has been modified. */
73991d6a 2740 clear_modify_mem_tables ();
7506f491
DE
2741}
2742
2743/* Return non-zero if the operands of X are not set before INSN in
2744 INSN's basic block. */
2745
2746static int
2747oprs_not_set_p (x, insn)
2748 rtx x, insn;
2749{
c4c81601 2750 int i, j;
7506f491 2751 enum rtx_code code;
6f7d635c 2752 const char *fmt;
7506f491 2753
7506f491
DE
2754 if (x == 0)
2755 return 1;
2756
2757 code = GET_CODE (x);
2758 switch (code)
2759 {
2760 case PC:
2761 case CC0:
2762 case CONST:
2763 case CONST_INT:
2764 case CONST_DOUBLE:
69ef87e2 2765 case CONST_VECTOR:
7506f491
DE
2766 case SYMBOL_REF:
2767 case LABEL_REF:
2768 case ADDR_VEC:
2769 case ADDR_DIFF_VEC:
2770 return 1;
2771
2772 case MEM:
589005ff 2773 if (load_killed_in_block_p (BLOCK_FOR_INSN (insn),
e2d2ed72 2774 INSN_CUID (insn), x, 0))
a13d4ebf 2775 return 0;
c4c81601
RK
2776 else
2777 return oprs_not_set_p (XEXP (x, 0), insn);
7506f491
DE
2778
2779 case REG:
73991d6a 2780 return ! REGNO_REG_SET_P (reg_set_bitmap, REGNO (x));
7506f491
DE
2781
2782 default:
2783 break;
2784 }
2785
c4c81601 2786 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2787 {
2788 if (fmt[i] == 'e')
2789 {
7506f491
DE
2790 /* If we are about to do the last recursive call
2791 needed at this level, change it into iteration.
2792 This function is called enough to be worth it. */
2793 if (i == 0)
c4c81601
RK
2794 return oprs_not_set_p (XEXP (x, i), insn);
2795
2796 if (! oprs_not_set_p (XEXP (x, i), insn))
7506f491
DE
2797 return 0;
2798 }
2799 else if (fmt[i] == 'E')
c4c81601
RK
2800 for (j = 0; j < XVECLEN (x, i); j++)
2801 if (! oprs_not_set_p (XVECEXP (x, i, j), insn))
2802 return 0;
7506f491
DE
2803 }
2804
2805 return 1;
2806}
2807
2808/* Mark things set by a CALL. */
2809
2810static void
b5ce41ff
JL
2811mark_call (insn)
2812 rtx insn;
7506f491 2813{
24a28584 2814 if (! CONST_OR_PURE_CALL_P (insn))
a13d4ebf 2815 record_last_mem_set_info (insn);
7506f491
DE
2816}
2817
2818/* Mark things set by a SET. */
2819
2820static void
2821mark_set (pat, insn)
2822 rtx pat, insn;
2823{
2824 rtx dest = SET_DEST (pat);
2825
2826 while (GET_CODE (dest) == SUBREG
2827 || GET_CODE (dest) == ZERO_EXTRACT
2828 || GET_CODE (dest) == SIGN_EXTRACT
2829 || GET_CODE (dest) == STRICT_LOW_PART)
2830 dest = XEXP (dest, 0);
2831
a13d4ebf 2832 if (GET_CODE (dest) == REG)
73991d6a 2833 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (dest));
a13d4ebf
AM
2834 else if (GET_CODE (dest) == MEM)
2835 record_last_mem_set_info (insn);
2836
7506f491 2837 if (GET_CODE (SET_SRC (pat)) == CALL)
b5ce41ff 2838 mark_call (insn);
7506f491
DE
2839}
2840
2841/* Record things set by a CLOBBER. */
2842
2843static void
2844mark_clobber (pat, insn)
2845 rtx pat, insn;
2846{
2847 rtx clob = XEXP (pat, 0);
2848
2849 while (GET_CODE (clob) == SUBREG || GET_CODE (clob) == STRICT_LOW_PART)
2850 clob = XEXP (clob, 0);
2851
a13d4ebf 2852 if (GET_CODE (clob) == REG)
73991d6a 2853 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (clob));
a13d4ebf
AM
2854 else
2855 record_last_mem_set_info (insn);
7506f491
DE
2856}
2857
2858/* Record things set by INSN.
2859 This data is used by oprs_not_set_p. */
2860
2861static void
2862mark_oprs_set (insn)
2863 rtx insn;
2864{
2865 rtx pat = PATTERN (insn);
c4c81601 2866 int i;
7506f491
DE
2867
2868 if (GET_CODE (pat) == SET)
2869 mark_set (pat, insn);
2870 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
2871 for (i = 0; i < XVECLEN (pat, 0); i++)
2872 {
2873 rtx x = XVECEXP (pat, 0, i);
2874
2875 if (GET_CODE (x) == SET)
2876 mark_set (x, insn);
2877 else if (GET_CODE (x) == CLOBBER)
2878 mark_clobber (x, insn);
2879 else if (GET_CODE (x) == CALL)
2880 mark_call (insn);
2881 }
7506f491 2882
7506f491
DE
2883 else if (GET_CODE (pat) == CLOBBER)
2884 mark_clobber (pat, insn);
2885 else if (GET_CODE (pat) == CALL)
b5ce41ff 2886 mark_call (insn);
7506f491 2887}
b5ce41ff 2888
7506f491
DE
2889\f
2890/* Classic GCSE reaching definition support. */
2891
2892/* Allocate reaching def variables. */
2893
2894static void
2895alloc_rd_mem (n_blocks, n_insns)
2896 int n_blocks, n_insns;
2897{
2898 rd_kill = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
d55bc081 2899 sbitmap_vector_zero (rd_kill, n_blocks);
7506f491
DE
2900
2901 rd_gen = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
d55bc081 2902 sbitmap_vector_zero (rd_gen, n_blocks);
7506f491
DE
2903
2904 reaching_defs = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
d55bc081 2905 sbitmap_vector_zero (reaching_defs, n_blocks);
7506f491
DE
2906
2907 rd_out = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
d55bc081 2908 sbitmap_vector_zero (rd_out, n_blocks);
7506f491
DE
2909}
2910
2911/* Free reaching def variables. */
2912
2913static void
2914free_rd_mem ()
2915{
5a660bff
DB
2916 sbitmap_vector_free (rd_kill);
2917 sbitmap_vector_free (rd_gen);
2918 sbitmap_vector_free (reaching_defs);
2919 sbitmap_vector_free (rd_out);
7506f491
DE
2920}
2921
c4c81601 2922/* Add INSN to the kills of BB. REGNO, set in BB, is killed by INSN. */
7506f491
DE
2923
2924static void
2925handle_rd_kill_set (insn, regno, bb)
2926 rtx insn;
e2d2ed72
AM
2927 int regno;
2928 basic_block bb;
7506f491 2929{
c4c81601 2930 struct reg_set *this_reg;
7506f491 2931
c4c81601
RK
2932 for (this_reg = reg_set_table[regno]; this_reg; this_reg = this_reg ->next)
2933 if (BLOCK_NUM (this_reg->insn) != BLOCK_NUM (insn))
0b17ab2f 2934 SET_BIT (rd_kill[bb->index], INSN_CUID (this_reg->insn));
7506f491
DE
2935}
2936
7506f491
DE
2937/* Compute the set of kill's for reaching definitions. */
2938
2939static void
2940compute_kill_rd ()
2941{
e0082a72 2942 int cuid;
172890a2
RK
2943 unsigned int regno;
2944 int i;
e0082a72 2945 basic_block bb;
7506f491
DE
2946
2947 /* For each block
2948 For each set bit in `gen' of the block (i.e each insn which
ac7c5af5
JL
2949 generates a definition in the block)
2950 Call the reg set by the insn corresponding to that bit regx
2951 Look at the linked list starting at reg_set_table[regx]
2952 For each setting of regx in the linked list, which is not in
2953 this block
6d2f8887 2954 Set the bit in `kill' corresponding to that insn. */
e0082a72 2955 FOR_EACH_BB (bb)
c4c81601 2956 for (cuid = 0; cuid < max_cuid; cuid++)
e0082a72 2957 if (TEST_BIT (rd_gen[bb->index], cuid))
7506f491 2958 {
c4c81601
RK
2959 rtx insn = CUID_INSN (cuid);
2960 rtx pat = PATTERN (insn);
7506f491 2961
c4c81601
RK
2962 if (GET_CODE (insn) == CALL_INSN)
2963 {
2964 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4e2db584 2965 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
e0082a72 2966 handle_rd_kill_set (insn, regno, bb);
c4c81601 2967 }
7506f491 2968
c4c81601
RK
2969 if (GET_CODE (pat) == PARALLEL)
2970 {
2971 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
7506f491 2972 {
c4c81601 2973 enum rtx_code code = GET_CODE (XVECEXP (pat, 0, i));
7506f491 2974
c4c81601
RK
2975 if ((code == SET || code == CLOBBER)
2976 && GET_CODE (XEXP (XVECEXP (pat, 0, i), 0)) == REG)
2977 handle_rd_kill_set (insn,
2978 REGNO (XEXP (XVECEXP (pat, 0, i), 0)),
e0082a72 2979 bb);
ac7c5af5 2980 }
ac7c5af5 2981 }
c4c81601
RK
2982 else if (GET_CODE (pat) == SET && GET_CODE (SET_DEST (pat)) == REG)
2983 /* Each setting of this register outside of this block
2984 must be marked in the set of kills in this block. */
e0082a72 2985 handle_rd_kill_set (insn, REGNO (SET_DEST (pat)), bb);
7506f491 2986 }
7506f491
DE
2987}
2988
589005ff 2989/* Compute the reaching definitions as in
7506f491
DE
2990 Compilers Principles, Techniques, and Tools. Aho, Sethi, Ullman,
2991 Chapter 10. It is the same algorithm as used for computing available
2992 expressions but applied to the gens and kills of reaching definitions. */
2993
2994static void
2995compute_rd ()
2996{
e0082a72
ZD
2997 int changed, passes;
2998 basic_block bb;
7506f491 2999
e0082a72
ZD
3000 FOR_EACH_BB (bb)
3001 sbitmap_copy (rd_out[bb->index] /*dst*/, rd_gen[bb->index] /*src*/);
7506f491
DE
3002
3003 passes = 0;
3004 changed = 1;
3005 while (changed)
3006 {
3007 changed = 0;
e0082a72 3008 FOR_EACH_BB (bb)
ac7c5af5 3009 {
e0082a72
ZD
3010 sbitmap_union_of_preds (reaching_defs[bb->index], rd_out, bb->index);
3011 changed |= sbitmap_union_of_diff_cg (rd_out[bb->index], rd_gen[bb->index],
3012 reaching_defs[bb->index], rd_kill[bb->index]);
ac7c5af5 3013 }
7506f491
DE
3014 passes++;
3015 }
3016
3017 if (gcse_file)
3018 fprintf (gcse_file, "reaching def computation: %d passes\n", passes);
3019}
3020\f
3021/* Classic GCSE available expression support. */
3022
3023/* Allocate memory for available expression computation. */
3024
3025static void
3026alloc_avail_expr_mem (n_blocks, n_exprs)
3027 int n_blocks, n_exprs;
3028{
3029 ae_kill = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
d55bc081 3030 sbitmap_vector_zero (ae_kill, n_blocks);
7506f491
DE
3031
3032 ae_gen = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
d55bc081 3033 sbitmap_vector_zero (ae_gen, n_blocks);
7506f491
DE
3034
3035 ae_in = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
d55bc081 3036 sbitmap_vector_zero (ae_in, n_blocks);
7506f491
DE
3037
3038 ae_out = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
d55bc081 3039 sbitmap_vector_zero (ae_out, n_blocks);
7506f491
DE
3040}
3041
3042static void
3043free_avail_expr_mem ()
3044{
5a660bff
DB
3045 sbitmap_vector_free (ae_kill);
3046 sbitmap_vector_free (ae_gen);
3047 sbitmap_vector_free (ae_in);
3048 sbitmap_vector_free (ae_out);
7506f491
DE
3049}
3050
3051/* Compute the set of available expressions generated in each basic block. */
3052
3053static void
02280659
ZD
3054compute_ae_gen (expr_hash_table)
3055 struct hash_table *expr_hash_table;
7506f491 3056{
2e653e39 3057 unsigned int i;
c4c81601
RK
3058 struct expr *expr;
3059 struct occr *occr;
7506f491
DE
3060
3061 /* For each recorded occurrence of each expression, set ae_gen[bb][expr].
3062 This is all we have to do because an expression is not recorded if it
3063 is not available, and the only expressions we want to work with are the
3064 ones that are recorded. */
02280659
ZD
3065 for (i = 0; i < expr_hash_table->size; i++)
3066 for (expr = expr_hash_table->table[i]; expr != 0; expr = expr->next_same_hash)
c4c81601
RK
3067 for (occr = expr->avail_occr; occr != 0; occr = occr->next)
3068 SET_BIT (ae_gen[BLOCK_NUM (occr->insn)], expr->bitmap_index);
7506f491
DE
3069}
3070
3071/* Return non-zero if expression X is killed in BB. */
3072
3073static int
3074expr_killed_p (x, bb)
3075 rtx x;
e2d2ed72 3076 basic_block bb;
7506f491 3077{
c4c81601 3078 int i, j;
7506f491 3079 enum rtx_code code;
6f7d635c 3080 const char *fmt;
7506f491 3081
7506f491
DE
3082 if (x == 0)
3083 return 1;
3084
3085 code = GET_CODE (x);
3086 switch (code)
3087 {
3088 case REG:
0b17ab2f 3089 return TEST_BIT (reg_set_in_block[bb->index], REGNO (x));
7506f491
DE
3090
3091 case MEM:
a13d4ebf
AM
3092 if (load_killed_in_block_p (bb, get_max_uid () + 1, x, 0))
3093 return 1;
c4c81601
RK
3094 else
3095 return expr_killed_p (XEXP (x, 0), bb);
7506f491
DE
3096
3097 case PC:
3098 case CC0: /*FIXME*/
3099 case CONST:
3100 case CONST_INT:
3101 case CONST_DOUBLE:
69ef87e2 3102 case CONST_VECTOR:
7506f491
DE
3103 case SYMBOL_REF:
3104 case LABEL_REF:
3105 case ADDR_VEC:
3106 case ADDR_DIFF_VEC:
3107 return 0;
3108
3109 default:
3110 break;
3111 }
3112
c4c81601 3113 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
3114 {
3115 if (fmt[i] == 'e')
3116 {
7506f491
DE
3117 /* If we are about to do the last recursive call
3118 needed at this level, change it into iteration.
3119 This function is called enough to be worth it. */
3120 if (i == 0)
c4c81601
RK
3121 return expr_killed_p (XEXP (x, i), bb);
3122 else if (expr_killed_p (XEXP (x, i), bb))
7506f491
DE
3123 return 1;
3124 }
3125 else if (fmt[i] == 'E')
c4c81601
RK
3126 for (j = 0; j < XVECLEN (x, i); j++)
3127 if (expr_killed_p (XVECEXP (x, i, j), bb))
3128 return 1;
7506f491
DE
3129 }
3130
3131 return 0;
3132}
3133
3134/* Compute the set of available expressions killed in each basic block. */
3135
3136static void
02280659 3137compute_ae_kill (ae_gen, ae_kill, expr_hash_table)
a42cd965 3138 sbitmap *ae_gen, *ae_kill;
02280659 3139 struct hash_table *expr_hash_table;
7506f491 3140{
e0082a72 3141 basic_block bb;
2e653e39 3142 unsigned int i;
c4c81601 3143 struct expr *expr;
7506f491 3144
e0082a72 3145 FOR_EACH_BB (bb)
02280659
ZD
3146 for (i = 0; i < expr_hash_table->size; i++)
3147 for (expr = expr_hash_table->table[i]; expr; expr = expr->next_same_hash)
7506f491 3148 {
c4c81601 3149 /* Skip EXPR if generated in this block. */
e0082a72 3150 if (TEST_BIT (ae_gen[bb->index], expr->bitmap_index))
c4c81601 3151 continue;
7506f491 3152
e0082a72
ZD
3153 if (expr_killed_p (expr->expr, bb))
3154 SET_BIT (ae_kill[bb->index], expr->bitmap_index);
7506f491 3155 }
7506f491 3156}
7506f491
DE
3157\f
3158/* Actually perform the Classic GCSE optimizations. */
3159
3160/* Return non-zero if occurrence OCCR of expression EXPR reaches block BB.
3161
3162 CHECK_SELF_LOOP is non-zero if we should consider a block reaching itself
3163 as a positive reach. We want to do this when there are two computations
3164 of the expression in the block.
3165
3166 VISITED is a pointer to a working buffer for tracking which BB's have
3167 been visited. It is NULL for the top-level call.
3168
3169 We treat reaching expressions that go through blocks containing the same
3170 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
3171 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
3172 2 as not reaching. The intent is to improve the probability of finding
3173 only one reaching expression and to reduce register lifetimes by picking
3174 the closest such expression. */
3175
3176static int
283a2545 3177expr_reaches_here_p_work (occr, expr, bb, check_self_loop, visited)
7506f491
DE
3178 struct occr *occr;
3179 struct expr *expr;
e2d2ed72 3180 basic_block bb;
7506f491
DE
3181 int check_self_loop;
3182 char *visited;
3183{
36349f8b 3184 edge pred;
7506f491 3185
e2d2ed72 3186 for (pred = bb->pred; pred != NULL; pred = pred->pred_next)
7506f491 3187 {
e2d2ed72 3188 basic_block pred_bb = pred->src;
7506f491 3189
0b17ab2f 3190 if (visited[pred_bb->index])
c4c81601 3191 /* This predecessor has already been visited. Nothing to do. */
7506f491 3192 ;
7506f491 3193 else if (pred_bb == bb)
ac7c5af5 3194 {
7506f491
DE
3195 /* BB loops on itself. */
3196 if (check_self_loop
0b17ab2f
RH
3197 && TEST_BIT (ae_gen[pred_bb->index], expr->bitmap_index)
3198 && BLOCK_NUM (occr->insn) == pred_bb->index)
7506f491 3199 return 1;
c4c81601 3200
0b17ab2f 3201 visited[pred_bb->index] = 1;
ac7c5af5 3202 }
c4c81601 3203
7506f491 3204 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
3205 else if (TEST_BIT (ae_kill[pred_bb->index], expr->bitmap_index))
3206 visited[pred_bb->index] = 1;
c4c81601 3207
7506f491 3208 /* Does this predecessor generate this expression? */
0b17ab2f 3209 else if (TEST_BIT (ae_gen[pred_bb->index], expr->bitmap_index))
7506f491
DE
3210 {
3211 /* Is this the occurrence we're looking for?
3212 Note that there's only one generating occurrence per block
3213 so we just need to check the block number. */
0b17ab2f 3214 if (BLOCK_NUM (occr->insn) == pred_bb->index)
7506f491 3215 return 1;
c4c81601 3216
0b17ab2f 3217 visited[pred_bb->index] = 1;
7506f491 3218 }
c4c81601 3219
7506f491
DE
3220 /* Neither gen nor kill. */
3221 else
ac7c5af5 3222 {
0b17ab2f 3223 visited[pred_bb->index] = 1;
589005ff 3224 if (expr_reaches_here_p_work (occr, expr, pred_bb, check_self_loop,
283a2545 3225 visited))
c4c81601 3226
7506f491 3227 return 1;
ac7c5af5 3228 }
7506f491
DE
3229 }
3230
3231 /* All paths have been checked. */
3232 return 0;
3233}
3234
283a2545 3235/* This wrapper for expr_reaches_here_p_work() is to ensure that any
dc297297 3236 memory allocated for that function is returned. */
283a2545
RL
3237
3238static int
3239expr_reaches_here_p (occr, expr, bb, check_self_loop)
3240 struct occr *occr;
3241 struct expr *expr;
e2d2ed72 3242 basic_block bb;
283a2545
RL
3243 int check_self_loop;
3244{
3245 int rval;
d55bc081 3246 char *visited = (char *) xcalloc (last_basic_block, 1);
283a2545 3247
c4c81601 3248 rval = expr_reaches_here_p_work (occr, expr, bb, check_self_loop, visited);
589005ff 3249
283a2545 3250 free (visited);
c4c81601 3251 return rval;
283a2545
RL
3252}
3253
7506f491
DE
3254/* Return the instruction that computes EXPR that reaches INSN's basic block.
3255 If there is more than one such instruction, return NULL.
3256
3257 Called only by handle_avail_expr. */
3258
3259static rtx
3260computing_insn (expr, insn)
3261 struct expr *expr;
3262 rtx insn;
3263{
e2d2ed72 3264 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491
DE
3265
3266 if (expr->avail_occr->next == NULL)
589005ff 3267 {
e2d2ed72 3268 if (BLOCK_FOR_INSN (expr->avail_occr->insn) == bb)
c4c81601
RK
3269 /* The available expression is actually itself
3270 (i.e. a loop in the flow graph) so do nothing. */
3271 return NULL;
3272
7506f491
DE
3273 /* (FIXME) Case that we found a pattern that was created by
3274 a substitution that took place. */
3275 return expr->avail_occr->insn;
3276 }
3277 else
3278 {
3279 /* Pattern is computed more than once.
589005ff 3280 Search backwards from this insn to see how many of these
7506f491
DE
3281 computations actually reach this insn. */
3282 struct occr *occr;
3283 rtx insn_computes_expr = NULL;
3284 int can_reach = 0;
3285
3286 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
3287 {
e2d2ed72 3288 if (BLOCK_FOR_INSN (occr->insn) == bb)
7506f491
DE
3289 {
3290 /* The expression is generated in this block.
3291 The only time we care about this is when the expression
3292 is generated later in the block [and thus there's a loop].
3293 We let the normal cse pass handle the other cases. */
c4c81601
RK
3294 if (INSN_CUID (insn) < INSN_CUID (occr->insn)
3295 && expr_reaches_here_p (occr, expr, bb, 1))
7506f491
DE
3296 {
3297 can_reach++;
3298 if (can_reach > 1)
3299 return NULL;
c4c81601 3300
7506f491
DE
3301 insn_computes_expr = occr->insn;
3302 }
3303 }
c4c81601
RK
3304 else if (expr_reaches_here_p (occr, expr, bb, 0))
3305 {
3306 can_reach++;
3307 if (can_reach > 1)
3308 return NULL;
3309
3310 insn_computes_expr = occr->insn;
3311 }
7506f491
DE
3312 }
3313
3314 if (insn_computes_expr == NULL)
3315 abort ();
c4c81601 3316
7506f491
DE
3317 return insn_computes_expr;
3318 }
3319}
3320
3321/* Return non-zero if the definition in DEF_INSN can reach INSN.
3322 Only called by can_disregard_other_sets. */
3323
3324static int
3325def_reaches_here_p (insn, def_insn)
3326 rtx insn, def_insn;
3327{
3328 rtx reg;
3329
3330 if (TEST_BIT (reaching_defs[BLOCK_NUM (insn)], INSN_CUID (def_insn)))
3331 return 1;
3332
3333 if (BLOCK_NUM (insn) == BLOCK_NUM (def_insn))
3334 {
3335 if (INSN_CUID (def_insn) < INSN_CUID (insn))
ac7c5af5 3336 {
7506f491
DE
3337 if (GET_CODE (PATTERN (def_insn)) == PARALLEL)
3338 return 1;
c4c81601 3339 else if (GET_CODE (PATTERN (def_insn)) == CLOBBER)
7506f491
DE
3340 reg = XEXP (PATTERN (def_insn), 0);
3341 else if (GET_CODE (PATTERN (def_insn)) == SET)
3342 reg = SET_DEST (PATTERN (def_insn));
3343 else
3344 abort ();
c4c81601 3345
7506f491
DE
3346 return ! reg_set_between_p (reg, NEXT_INSN (def_insn), insn);
3347 }
3348 else
3349 return 0;
3350 }
3351
3352 return 0;
3353}
3354
c4c81601
RK
3355/* Return non-zero if *ADDR_THIS_REG can only have one value at INSN. The
3356 value returned is the number of definitions that reach INSN. Returning a
3357 value of zero means that [maybe] more than one definition reaches INSN and
3358 the caller can't perform whatever optimization it is trying. i.e. it is
3359 always safe to return zero. */
7506f491
DE
3360
3361static int
3362can_disregard_other_sets (addr_this_reg, insn, for_combine)
3363 struct reg_set **addr_this_reg;
3364 rtx insn;
3365 int for_combine;
3366{
3367 int number_of_reaching_defs = 0;
c4c81601 3368 struct reg_set *this_reg;
7506f491 3369
c4c81601
RK
3370 for (this_reg = *addr_this_reg; this_reg != 0; this_reg = this_reg->next)
3371 if (def_reaches_here_p (insn, this_reg->insn))
3372 {
3373 number_of_reaching_defs++;
3374 /* Ignore parallels for now. */
3375 if (GET_CODE (PATTERN (this_reg->insn)) == PARALLEL)
3376 return 0;
3377
3378 if (!for_combine
3379 && (GET_CODE (PATTERN (this_reg->insn)) == CLOBBER
3380 || ! rtx_equal_p (SET_SRC (PATTERN (this_reg->insn)),
3381 SET_SRC (PATTERN (insn)))))
3382 /* A setting of the reg to a different value reaches INSN. */
3383 return 0;
3384
3385 if (number_of_reaching_defs > 1)
3386 {
3387 /* If in this setting the value the register is being set to is
3388 equal to the previous value the register was set to and this
3389 setting reaches the insn we are trying to do the substitution
3390 on then we are ok. */
3391 if (GET_CODE (PATTERN (this_reg->insn)) == CLOBBER)
7506f491 3392 return 0;
c4c81601
RK
3393 else if (! rtx_equal_p (SET_SRC (PATTERN (this_reg->insn)),
3394 SET_SRC (PATTERN (insn))))
3395 return 0;
3396 }
7506f491 3397
589005ff 3398 *addr_this_reg = this_reg;
c4c81601 3399 }
7506f491
DE
3400
3401 return number_of_reaching_defs;
3402}
3403
3404/* Expression computed by insn is available and the substitution is legal,
3405 so try to perform the substitution.
3406
3407 The result is non-zero if any changes were made. */
3408
3409static int
3410handle_avail_expr (insn, expr)
3411 rtx insn;
3412 struct expr *expr;
3413{
0631e0bf 3414 rtx pat, insn_computes_expr, expr_set;
7506f491
DE
3415 rtx to;
3416 struct reg_set *this_reg;
3417 int found_setting, use_src;
3418 int changed = 0;
3419
3420 /* We only handle the case where one computation of the expression
3421 reaches this instruction. */
3422 insn_computes_expr = computing_insn (expr, insn);
3423 if (insn_computes_expr == NULL)
3424 return 0;
0631e0bf
JH
3425 expr_set = single_set (insn_computes_expr);
3426 if (!expr_set)
3427 abort ();
7506f491
DE
3428
3429 found_setting = 0;
3430 use_src = 0;
3431
3432 /* At this point we know only one computation of EXPR outside of this
3433 block reaches this insn. Now try to find a register that the
3434 expression is computed into. */
0631e0bf 3435 if (GET_CODE (SET_SRC (expr_set)) == REG)
7506f491
DE
3436 {
3437 /* This is the case when the available expression that reaches
3438 here has already been handled as an available expression. */
770ae6cc 3439 unsigned int regnum_for_replacing
0631e0bf 3440 = REGNO (SET_SRC (expr_set));
c4c81601 3441
7506f491
DE
3442 /* If the register was created by GCSE we can't use `reg_set_table',
3443 however we know it's set only once. */
3444 if (regnum_for_replacing >= max_gcse_regno
3445 /* If the register the expression is computed into is set only once,
3446 or only one set reaches this insn, we can use it. */
3447 || (((this_reg = reg_set_table[regnum_for_replacing]),
3448 this_reg->next == NULL)
3449 || can_disregard_other_sets (&this_reg, insn, 0)))
8e42ace1
KH
3450 {
3451 use_src = 1;
3452 found_setting = 1;
3453 }
7506f491
DE
3454 }
3455
3456 if (!found_setting)
3457 {
770ae6cc 3458 unsigned int regnum_for_replacing
0631e0bf 3459 = REGNO (SET_DEST (expr_set));
c4c81601 3460
7506f491
DE
3461 /* This shouldn't happen. */
3462 if (regnum_for_replacing >= max_gcse_regno)
3463 abort ();
c4c81601 3464
7506f491 3465 this_reg = reg_set_table[regnum_for_replacing];
c4c81601 3466
7506f491
DE
3467 /* If the register the expression is computed into is set only once,
3468 or only one set reaches this insn, use it. */
3469 if (this_reg->next == NULL
3470 || can_disregard_other_sets (&this_reg, insn, 0))
3471 found_setting = 1;
3472 }
3473
3474 if (found_setting)
3475 {
3476 pat = PATTERN (insn);
3477 if (use_src)
0631e0bf 3478 to = SET_SRC (expr_set);
7506f491 3479 else
0631e0bf 3480 to = SET_DEST (expr_set);
7506f491
DE
3481 changed = validate_change (insn, &SET_SRC (pat), to, 0);
3482
3483 /* We should be able to ignore the return code from validate_change but
3484 to play it safe we check. */
3485 if (changed)
3486 {
3487 gcse_subst_count++;
3488 if (gcse_file != NULL)
3489 {
c4c81601
RK
3490 fprintf (gcse_file, "GCSE: Replacing the source in insn %d with",
3491 INSN_UID (insn));
3492 fprintf (gcse_file, " reg %d %s insn %d\n",
3493 REGNO (to), use_src ? "from" : "set in",
7506f491
DE
3494 INSN_UID (insn_computes_expr));
3495 }
7506f491
DE
3496 }
3497 }
c4c81601 3498
7506f491
DE
3499 /* The register that the expr is computed into is set more than once. */
3500 else if (1 /*expensive_op(this_pattrn->op) && do_expensive_gcse)*/)
3501 {
3502 /* Insert an insn after insnx that copies the reg set in insnx
3503 into a new pseudo register call this new register REGN.
3504 From insnb until end of basic block or until REGB is set
3505 replace all uses of REGB with REGN. */
3506 rtx new_insn;
3507
0631e0bf 3508 to = gen_reg_rtx (GET_MODE (SET_DEST (expr_set)));
7506f491
DE
3509
3510 /* Generate the new insn. */
3511 /* ??? If the change fails, we return 0, even though we created
3512 an insn. I think this is ok. */
9e6a5703
JC
3513 new_insn
3514 = emit_insn_after (gen_rtx_SET (VOIDmode, to,
0631e0bf 3515 SET_DEST (expr_set)),
c4c81601
RK
3516 insn_computes_expr);
3517
7506f491
DE
3518 /* Keep register set table up to date. */
3519 record_one_set (REGNO (to), new_insn);
3520
3521 gcse_create_count++;
3522 if (gcse_file != NULL)
ac7c5af5 3523 {
c4c81601 3524 fprintf (gcse_file, "GCSE: Creating insn %d to copy value of reg %d",
7506f491 3525 INSN_UID (NEXT_INSN (insn_computes_expr)),
c4c81601
RK
3526 REGNO (SET_SRC (PATTERN (NEXT_INSN (insn_computes_expr)))));
3527 fprintf (gcse_file, ", computed in insn %d,\n",
7506f491 3528 INSN_UID (insn_computes_expr));
c4c81601
RK
3529 fprintf (gcse_file, " into newly allocated reg %d\n",
3530 REGNO (to));
ac7c5af5 3531 }
7506f491
DE
3532
3533 pat = PATTERN (insn);
3534
3535 /* Do register replacement for INSN. */
3536 changed = validate_change (insn, &SET_SRC (pat),
c4c81601
RK
3537 SET_DEST (PATTERN
3538 (NEXT_INSN (insn_computes_expr))),
7506f491
DE
3539 0);
3540
3541 /* We should be able to ignore the return code from validate_change but
3542 to play it safe we check. */
3543 if (changed)
3544 {
3545 gcse_subst_count++;
3546 if (gcse_file != NULL)
3547 {
c4c81601
RK
3548 fprintf (gcse_file,
3549 "GCSE: Replacing the source in insn %d with reg %d ",
7506f491 3550 INSN_UID (insn),
c4c81601
RK
3551 REGNO (SET_DEST (PATTERN (NEXT_INSN
3552 (insn_computes_expr)))));
3553 fprintf (gcse_file, "set in insn %d\n",
589005ff 3554 INSN_UID (insn_computes_expr));
7506f491 3555 }
7506f491
DE
3556 }
3557 }
3558
3559 return changed;
3560}
3561
c4c81601
RK
3562/* Perform classic GCSE. This is called by one_classic_gcse_pass after all
3563 the dataflow analysis has been done.
7506f491
DE
3564
3565 The result is non-zero if a change was made. */
3566
3567static int
3568classic_gcse ()
3569{
e0082a72 3570 int changed;
7506f491 3571 rtx insn;
e0082a72 3572 basic_block bb;
7506f491
DE
3573
3574 /* Note we start at block 1. */
3575
e0082a72
ZD
3576 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
3577 return 0;
3578
7506f491 3579 changed = 0;
e0082a72 3580 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb, EXIT_BLOCK_PTR, next_bb)
7506f491
DE
3581 {
3582 /* Reset tables used to keep track of what's still valid [since the
3583 start of the block]. */
3584 reset_opr_set_tables ();
3585
e0082a72
ZD
3586 for (insn = bb->head;
3587 insn != NULL && insn != NEXT_INSN (bb->end);
7506f491
DE
3588 insn = NEXT_INSN (insn))
3589 {
3590 /* Is insn of form (set (pseudo-reg) ...)? */
7506f491
DE
3591 if (GET_CODE (insn) == INSN
3592 && GET_CODE (PATTERN (insn)) == SET
3593 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
3594 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_PSEUDO_REGISTER)
3595 {
3596 rtx pat = PATTERN (insn);
3597 rtx src = SET_SRC (pat);
3598 struct expr *expr;
3599
3600 if (want_to_gcse_p (src)
3601 /* Is the expression recorded? */
02280659 3602 && ((expr = lookup_expr (src, &expr_hash_table)) != NULL)
7506f491
DE
3603 /* Is the expression available [at the start of the
3604 block]? */
e0082a72 3605 && TEST_BIT (ae_in[bb->index], expr->bitmap_index)
7506f491
DE
3606 /* Are the operands unchanged since the start of the
3607 block? */
3608 && oprs_not_set_p (src, insn))
3609 changed |= handle_avail_expr (insn, expr);
3610 }
3611
3612 /* Keep track of everything modified by this insn. */
3613 /* ??? Need to be careful w.r.t. mods done to INSN. */
2c3c49de 3614 if (INSN_P (insn))
7506f491 3615 mark_oprs_set (insn);
ac7c5af5 3616 }
7506f491
DE
3617 }
3618
3619 return changed;
3620}
3621
3622/* Top level routine to perform one classic GCSE pass.
3623
3624 Return non-zero if a change was made. */
3625
3626static int
b5ce41ff 3627one_classic_gcse_pass (pass)
7506f491
DE
3628 int pass;
3629{
3630 int changed = 0;
3631
3632 gcse_subst_count = 0;
3633 gcse_create_count = 0;
3634
02280659 3635 alloc_hash_table (max_cuid, &expr_hash_table, 0);
d55bc081 3636 alloc_rd_mem (last_basic_block, max_cuid);
02280659 3637 compute_hash_table (&expr_hash_table);
7506f491 3638 if (gcse_file)
02280659 3639 dump_hash_table (gcse_file, "Expression", &expr_hash_table);
c4c81601 3640
02280659 3641 if (expr_hash_table.n_elems > 0)
7506f491
DE
3642 {
3643 compute_kill_rd ();
3644 compute_rd ();
02280659
ZD
3645 alloc_avail_expr_mem (last_basic_block, expr_hash_table.n_elems);
3646 compute_ae_gen (&expr_hash_table);
3647 compute_ae_kill (ae_gen, ae_kill, &expr_hash_table);
bd0eaec2 3648 compute_available (ae_gen, ae_kill, ae_out, ae_in);
7506f491
DE
3649 changed = classic_gcse ();
3650 free_avail_expr_mem ();
3651 }
c4c81601 3652
7506f491 3653 free_rd_mem ();
02280659 3654 free_hash_table (&expr_hash_table);
7506f491
DE
3655
3656 if (gcse_file)
3657 {
3658 fprintf (gcse_file, "\n");
c4c81601
RK
3659 fprintf (gcse_file, "GCSE of %s, pass %d: %d bytes needed, %d substs,",
3660 current_function_name, pass, bytes_used, gcse_subst_count);
3661 fprintf (gcse_file, "%d insns created\n", gcse_create_count);
7506f491
DE
3662 }
3663
3664 return changed;
3665}
3666\f
3667/* Compute copy/constant propagation working variables. */
3668
3669/* Local properties of assignments. */
7506f491
DE
3670static sbitmap *cprop_pavloc;
3671static sbitmap *cprop_absaltered;
3672
3673/* Global properties of assignments (computed from the local properties). */
7506f491
DE
3674static sbitmap *cprop_avin;
3675static sbitmap *cprop_avout;
3676
c4c81601
RK
3677/* Allocate vars used for copy/const propagation. N_BLOCKS is the number of
3678 basic blocks. N_SETS is the number of sets. */
7506f491
DE
3679
3680static void
3681alloc_cprop_mem (n_blocks, n_sets)
3682 int n_blocks, n_sets;
3683{
3684 cprop_pavloc = sbitmap_vector_alloc (n_blocks, n_sets);
3685 cprop_absaltered = sbitmap_vector_alloc (n_blocks, n_sets);
3686
3687 cprop_avin = sbitmap_vector_alloc (n_blocks, n_sets);
3688 cprop_avout = sbitmap_vector_alloc (n_blocks, n_sets);
3689}
3690
3691/* Free vars used by copy/const propagation. */
3692
3693static void
3694free_cprop_mem ()
3695{
5a660bff
DB
3696 sbitmap_vector_free (cprop_pavloc);
3697 sbitmap_vector_free (cprop_absaltered);
3698 sbitmap_vector_free (cprop_avin);
3699 sbitmap_vector_free (cprop_avout);
7506f491
DE
3700}
3701
c4c81601
RK
3702/* For each block, compute whether X is transparent. X is either an
3703 expression or an assignment [though we don't care which, for this context
3704 an assignment is treated as an expression]. For each block where an
3705 element of X is modified, set (SET_P == 1) or reset (SET_P == 0) the INDX
3706 bit in BMAP. */
7506f491
DE
3707
3708static void
3709compute_transp (x, indx, bmap, set_p)
3710 rtx x;
3711 int indx;
3712 sbitmap *bmap;
3713 int set_p;
3714{
e0082a72
ZD
3715 int i, j;
3716 basic_block bb;
7506f491 3717 enum rtx_code code;
c4c81601 3718 reg_set *r;
6f7d635c 3719 const char *fmt;
7506f491 3720
c4c81601
RK
3721 /* repeat is used to turn tail-recursion into iteration since GCC
3722 can't do it when there's no return value. */
7506f491
DE
3723 repeat:
3724
3725 if (x == 0)
3726 return;
3727
3728 code = GET_CODE (x);
3729 switch (code)
3730 {
3731 case REG:
c4c81601
RK
3732 if (set_p)
3733 {
3734 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
3735 {
e0082a72
ZD
3736 FOR_EACH_BB (bb)
3737 if (TEST_BIT (reg_set_in_block[bb->index], REGNO (x)))
3738 SET_BIT (bmap[bb->index], indx);
c4c81601
RK
3739 }
3740 else
3741 {
3742 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
3743 SET_BIT (bmap[BLOCK_NUM (r->insn)], indx);
3744 }
3745 }
3746 else
3747 {
3748 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
3749 {
e0082a72
ZD
3750 FOR_EACH_BB (bb)
3751 if (TEST_BIT (reg_set_in_block[bb->index], REGNO (x)))
3752 RESET_BIT (bmap[bb->index], indx);
c4c81601
RK
3753 }
3754 else
3755 {
3756 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
3757 RESET_BIT (bmap[BLOCK_NUM (r->insn)], indx);
3758 }
3759 }
7506f491 3760
c4c81601 3761 return;
7506f491
DE
3762
3763 case MEM:
e0082a72 3764 FOR_EACH_BB (bb)
a13d4ebf 3765 {
e0082a72 3766 rtx list_entry = canon_modify_mem_list[bb->index];
a13d4ebf
AM
3767
3768 while (list_entry)
3769 {
3770 rtx dest, dest_addr;
3771
3772 if (GET_CODE (XEXP (list_entry, 0)) == CALL_INSN)
3773 {
3774 if (set_p)
e0082a72 3775 SET_BIT (bmap[bb->index], indx);
a13d4ebf 3776 else
e0082a72 3777 RESET_BIT (bmap[bb->index], indx);
a13d4ebf
AM
3778 break;
3779 }
3780 /* LIST_ENTRY must be an INSN of some kind that sets memory.
3781 Examine each hunk of memory that is modified. */
3782
3783 dest = XEXP (list_entry, 0);
3784 list_entry = XEXP (list_entry, 1);
3785 dest_addr = XEXP (list_entry, 0);
589005ff 3786
a13d4ebf
AM
3787 if (canon_true_dependence (dest, GET_MODE (dest), dest_addr,
3788 x, rtx_addr_varies_p))
3789 {
3790 if (set_p)
e0082a72 3791 SET_BIT (bmap[bb->index], indx);
a13d4ebf 3792 else
e0082a72 3793 RESET_BIT (bmap[bb->index], indx);
a13d4ebf
AM
3794 break;
3795 }
3796 list_entry = XEXP (list_entry, 1);
3797 }
3798 }
c4c81601 3799
7506f491
DE
3800 x = XEXP (x, 0);
3801 goto repeat;
3802
3803 case PC:
3804 case CC0: /*FIXME*/
3805 case CONST:
3806 case CONST_INT:
3807 case CONST_DOUBLE:
69ef87e2 3808 case CONST_VECTOR:
7506f491
DE
3809 case SYMBOL_REF:
3810 case LABEL_REF:
3811 case ADDR_VEC:
3812 case ADDR_DIFF_VEC:
3813 return;
3814
3815 default:
3816 break;
3817 }
3818
c4c81601 3819 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
3820 {
3821 if (fmt[i] == 'e')
3822 {
7506f491
DE
3823 /* If we are about to do the last recursive call
3824 needed at this level, change it into iteration.
3825 This function is called enough to be worth it. */
3826 if (i == 0)
3827 {
c4c81601 3828 x = XEXP (x, i);
7506f491
DE
3829 goto repeat;
3830 }
c4c81601
RK
3831
3832 compute_transp (XEXP (x, i), indx, bmap, set_p);
7506f491
DE
3833 }
3834 else if (fmt[i] == 'E')
c4c81601
RK
3835 for (j = 0; j < XVECLEN (x, i); j++)
3836 compute_transp (XVECEXP (x, i, j), indx, bmap, set_p);
7506f491
DE
3837 }
3838}
3839
7506f491
DE
3840/* Top level routine to do the dataflow analysis needed by copy/const
3841 propagation. */
3842
3843static void
3844compute_cprop_data ()
3845{
02280659 3846 compute_local_properties (cprop_absaltered, cprop_pavloc, NULL, &set_hash_table);
ce724250
JL
3847 compute_available (cprop_pavloc, cprop_absaltered,
3848 cprop_avout, cprop_avin);
7506f491
DE
3849}
3850\f
3851/* Copy/constant propagation. */
3852
7506f491
DE
3853/* Maximum number of register uses in an insn that we handle. */
3854#define MAX_USES 8
3855
3856/* Table of uses found in an insn.
3857 Allocated statically to avoid alloc/free complexity and overhead. */
3858static struct reg_use reg_use_table[MAX_USES];
3859
3860/* Index into `reg_use_table' while building it. */
3861static int reg_use_count;
3862
c4c81601
RK
3863/* Set up a list of register numbers used in INSN. The found uses are stored
3864 in `reg_use_table'. `reg_use_count' is initialized to zero before entry,
3865 and contains the number of uses in the table upon exit.
7506f491 3866
c4c81601
RK
3867 ??? If a register appears multiple times we will record it multiple times.
3868 This doesn't hurt anything but it will slow things down. */
7506f491
DE
3869
3870static void
9e71c818
JH
3871find_used_regs (xptr, data)
3872 rtx *xptr;
3873 void *data ATTRIBUTE_UNUSED;
7506f491 3874{
c4c81601 3875 int i, j;
7506f491 3876 enum rtx_code code;
6f7d635c 3877 const char *fmt;
9e71c818 3878 rtx x = *xptr;
7506f491 3879
c4c81601
RK
3880 /* repeat is used to turn tail-recursion into iteration since GCC
3881 can't do it when there's no return value. */
7506f491 3882 repeat:
7506f491
DE
3883 if (x == 0)
3884 return;
3885
3886 code = GET_CODE (x);
9e71c818 3887 if (REG_P (x))
7506f491 3888 {
7506f491
DE
3889 if (reg_use_count == MAX_USES)
3890 return;
c4c81601 3891
7506f491
DE
3892 reg_use_table[reg_use_count].reg_rtx = x;
3893 reg_use_count++;
7506f491
DE
3894 }
3895
3896 /* Recursively scan the operands of this expression. */
3897
c4c81601 3898 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
3899 {
3900 if (fmt[i] == 'e')
3901 {
3902 /* If we are about to do the last recursive call
3903 needed at this level, change it into iteration.
3904 This function is called enough to be worth it. */
3905 if (i == 0)
3906 {
3907 x = XEXP (x, 0);
3908 goto repeat;
3909 }
c4c81601 3910
9e71c818 3911 find_used_regs (&XEXP (x, i), data);
7506f491
DE
3912 }
3913 else if (fmt[i] == 'E')
c4c81601 3914 for (j = 0; j < XVECLEN (x, i); j++)
9e71c818 3915 find_used_regs (&XVECEXP (x, i, j), data);
7506f491
DE
3916 }
3917}
3918
3919/* Try to replace all non-SET_DEST occurrences of FROM in INSN with TO.
3920 Returns non-zero is successful. */
3921
3922static int
3923try_replace_reg (from, to, insn)
3924 rtx from, to, insn;
3925{
172890a2 3926 rtx note = find_reg_equal_equiv_note (insn);
fb0c0a12 3927 rtx src = 0;
172890a2
RK
3928 int success = 0;
3929 rtx set = single_set (insn);
833fc3ad 3930
2b773ee2
JH
3931 validate_replace_src_group (from, to, insn);
3932 if (num_changes_pending () && apply_change_group ())
3933 success = 1;
9e71c818 3934
f305679f 3935 if (!success && set && reg_mentioned_p (from, SET_SRC (set)))
833fc3ad 3936 {
f305679f
JH
3937 /* If above failed and this is a single set, try to simplify the source of
3938 the set given our substitution. We could perhaps try this for multiple
3939 SETs, but it probably won't buy us anything. */
172890a2
RK
3940 src = simplify_replace_rtx (SET_SRC (set), from, to);
3941
9e71c818
JH
3942 if (!rtx_equal_p (src, SET_SRC (set))
3943 && validate_change (insn, &SET_SRC (set), src, 0))
172890a2 3944 success = 1;
833fc3ad 3945
f305679f
JH
3946 /* If we've failed to do replacement, have a single SET, and don't already
3947 have a note, add a REG_EQUAL note to not lose information. */
3948 if (!success && note == 0 && set != 0)
3949 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
3950 }
e251e2a2 3951
172890a2
RK
3952 /* If there is already a NOTE, update the expression in it with our
3953 replacement. */
3954 else if (note != 0)
3955 XEXP (note, 0) = simplify_replace_rtx (XEXP (note, 0), from, to);
833fc3ad 3956
172890a2
RK
3957 /* REG_EQUAL may get simplified into register.
3958 We don't allow that. Remove that note. This code ought
3959 not to hapen, because previous code ought to syntetize
3960 reg-reg move, but be on the safe side. */
3961 if (note && REG_P (XEXP (note, 0)))
3962 remove_note (insn, note);
833fc3ad 3963
833fc3ad
JH
3964 return success;
3965}
c4c81601
RK
3966
3967/* Find a set of REGNOs that are available on entry to INSN's block. Returns
3968 NULL no such set is found. */
7506f491
DE
3969
3970static struct expr *
3971find_avail_set (regno, insn)
3972 int regno;
3973 rtx insn;
3974{
cafba495
BS
3975 /* SET1 contains the last set found that can be returned to the caller for
3976 use in a substitution. */
3977 struct expr *set1 = 0;
589005ff 3978
cafba495
BS
3979 /* Loops are not possible here. To get a loop we would need two sets
3980 available at the start of the block containing INSN. ie we would
3981 need two sets like this available at the start of the block:
3982
3983 (set (reg X) (reg Y))
3984 (set (reg Y) (reg X))
3985
3986 This can not happen since the set of (reg Y) would have killed the
3987 set of (reg X) making it unavailable at the start of this block. */
3988 while (1)
8e42ace1 3989 {
cafba495 3990 rtx src;
02280659 3991 struct expr *set = lookup_set (regno, NULL_RTX, &set_hash_table);
cafba495
BS
3992
3993 /* Find a set that is available at the start of the block
3994 which contains INSN. */
3995 while (set)
3996 {
3997 if (TEST_BIT (cprop_avin[BLOCK_NUM (insn)], set->bitmap_index))
3998 break;
3999 set = next_set (regno, set);
4000 }
7506f491 4001
cafba495
BS
4002 /* If no available set was found we've reached the end of the
4003 (possibly empty) copy chain. */
4004 if (set == 0)
589005ff 4005 break;
cafba495
BS
4006
4007 if (GET_CODE (set->expr) != SET)
4008 abort ();
4009
4010 src = SET_SRC (set->expr);
4011
4012 /* We know the set is available.
4013 Now check that SRC is ANTLOC (i.e. none of the source operands
589005ff 4014 have changed since the start of the block).
cafba495
BS
4015
4016 If the source operand changed, we may still use it for the next
4017 iteration of this loop, but we may not use it for substitutions. */
c4c81601 4018
cafba495
BS
4019 if (CONSTANT_P (src) || oprs_not_set_p (src, insn))
4020 set1 = set;
4021
4022 /* If the source of the set is anything except a register, then
4023 we have reached the end of the copy chain. */
4024 if (GET_CODE (src) != REG)
7506f491 4025 break;
7506f491 4026
cafba495
BS
4027 /* Follow the copy chain, ie start another iteration of the loop
4028 and see if we have an available copy into SRC. */
4029 regno = REGNO (src);
8e42ace1 4030 }
cafba495
BS
4031
4032 /* SET1 holds the last set that was available and anticipatable at
4033 INSN. */
4034 return set1;
7506f491
DE
4035}
4036
abd535b6 4037/* Subroutine of cprop_insn that tries to propagate constants into
0e3f0221
RS
4038 JUMP_INSNS. JUMP must be a conditional jump. If SETCC is non-NULL
4039 it is the instruction that immediately preceeds JUMP, and must be a
818b6b7f 4040 single SET of a register. FROM is what we will try to replace,
0e3f0221 4041 SRC is the constant we will try to substitute for it. Returns nonzero
589005ff 4042 if a change was made. */
c4c81601 4043
abd535b6 4044static int
0e3f0221
RS
4045cprop_jump (bb, setcc, jump, from, src)
4046 basic_block bb;
4047 rtx setcc;
4048 rtx jump;
172890a2 4049 rtx from;
abd535b6
BS
4050 rtx src;
4051{
0e3f0221
RS
4052 rtx new, new_set;
4053 rtx set = pc_set (jump);
4054
4055 /* First substitute in the INSN condition as the SET_SRC of the JUMP,
4056 then substitute that given values in this expanded JUMP. */
4057 if (setcc != NULL)
b2f02503
RS
4058 {
4059 rtx setcc_set = single_set (setcc);
4060 new_set = simplify_replace_rtx (SET_SRC (set),
4061 SET_DEST (setcc_set),
4062 SET_SRC (setcc_set));
4063 }
0e3f0221
RS
4064 else
4065 new_set = set;
4066
4067 new = simplify_replace_rtx (new_set, from, src);
abd535b6
BS
4068
4069 /* If no simplification can be made, then try the next
4070 register. */
0e3f0221 4071 if (rtx_equal_p (new, new_set))
abd535b6 4072 return 0;
589005ff 4073
7d5ab30e 4074 /* If this is now a no-op delete it, otherwise this must be a valid insn. */
172890a2 4075 if (new == pc_rtx)
0e3f0221 4076 delete_insn (jump);
7d5ab30e 4077 else
abd535b6 4078 {
0e3f0221 4079 if (! validate_change (jump, &SET_SRC (set), new, 0))
7d5ab30e 4080 return 0;
abd535b6 4081
7d5ab30e
JH
4082 /* If this has turned into an unconditional jump,
4083 then put a barrier after it so that the unreachable
4084 code will be deleted. */
4085 if (GET_CODE (SET_SRC (set)) == LABEL_REF)
0e3f0221 4086 emit_barrier_after (jump);
7d5ab30e 4087 }
abd535b6 4088
0e3f0221
RS
4089#ifdef HAVE_cc0
4090 /* Delete the cc0 setter. */
818b6b7f 4091 if (setcc != NULL && CC0_P (SET_DEST (single_set (setcc))))
0e3f0221
RS
4092 delete_insn (setcc);
4093#endif
4094
172890a2 4095 run_jump_opt_after_gcse = 1;
c4c81601 4096
172890a2
RK
4097 const_prop_count++;
4098 if (gcse_file != NULL)
4099 {
4100 fprintf (gcse_file,
818b6b7f 4101 "CONST-PROP: Replacing reg %d in jump_insn %d with constant ",
0e3f0221 4102 REGNO (from), INSN_UID (jump));
172890a2
RK
4103 print_rtl (gcse_file, src);
4104 fprintf (gcse_file, "\n");
abd535b6 4105 }
0005550b 4106 purge_dead_edges (bb);
172890a2
RK
4107
4108 return 1;
abd535b6
BS
4109}
4110
ae860ff7
JH
4111static bool
4112constprop_register (insn, from, to, alter_jumps)
4113 rtx insn;
4114 rtx from;
4115 rtx to;
4116 int alter_jumps;
4117{
4118 rtx sset;
4119
4120 /* Check for reg or cc0 setting instructions followed by
4121 conditional branch instructions first. */
4122 if (alter_jumps
4123 && (sset = single_set (insn)) != NULL
4124 && any_condjump_p (NEXT_INSN (insn)) && onlyjump_p (NEXT_INSN (insn)))
4125 {
4126 rtx dest = SET_DEST (sset);
4127 if ((REG_P (dest) || CC0_P (dest))
4128 && cprop_jump (BLOCK_FOR_INSN (insn), insn, NEXT_INSN (insn), from, to))
4129 return 1;
4130 }
4131
4132 /* Handle normal insns next. */
4133 if (GET_CODE (insn) == INSN
4134 && try_replace_reg (from, to, insn))
4135 return 1;
4136
4137 /* Try to propagate a CONST_INT into a conditional jump.
4138 We're pretty specific about what we will handle in this
4139 code, we can extend this as necessary over time.
4140
4141 Right now the insn in question must look like
4142 (set (pc) (if_then_else ...)) */
4143 else if (alter_jumps && any_condjump_p (insn) && onlyjump_p (insn))
4144 return cprop_jump (BLOCK_FOR_INSN (insn), NULL, insn, from, to);
4145 return 0;
4146}
4147
7506f491
DE
4148/* Perform constant and copy propagation on INSN.
4149 The result is non-zero if a change was made. */
4150
4151static int
ae860ff7 4152cprop_insn (insn, alter_jumps)
7506f491 4153 rtx insn;
b5ce41ff 4154 int alter_jumps;
7506f491
DE
4155{
4156 struct reg_use *reg_used;
4157 int changed = 0;
833fc3ad 4158 rtx note;
7506f491 4159
9e71c818 4160 if (!INSN_P (insn))
7506f491
DE
4161 return 0;
4162
4163 reg_use_count = 0;
9e71c818 4164 note_uses (&PATTERN (insn), find_used_regs, NULL);
589005ff 4165
172890a2 4166 note = find_reg_equal_equiv_note (insn);
833fc3ad 4167
dc297297 4168 /* We may win even when propagating constants into notes. */
833fc3ad 4169 if (note)
9e71c818 4170 find_used_regs (&XEXP (note, 0), NULL);
7506f491 4171
c4c81601
RK
4172 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
4173 reg_used++, reg_use_count--)
7506f491 4174 {
770ae6cc 4175 unsigned int regno = REGNO (reg_used->reg_rtx);
7506f491
DE
4176 rtx pat, src;
4177 struct expr *set;
7506f491
DE
4178
4179 /* Ignore registers created by GCSE.
dc297297 4180 We do this because ... */
7506f491
DE
4181 if (regno >= max_gcse_regno)
4182 continue;
4183
4184 /* If the register has already been set in this block, there's
4185 nothing we can do. */
4186 if (! oprs_not_set_p (reg_used->reg_rtx, insn))
4187 continue;
4188
4189 /* Find an assignment that sets reg_used and is available
4190 at the start of the block. */
4191 set = find_avail_set (regno, insn);
4192 if (! set)
4193 continue;
589005ff 4194
7506f491
DE
4195 pat = set->expr;
4196 /* ??? We might be able to handle PARALLELs. Later. */
4197 if (GET_CODE (pat) != SET)
4198 abort ();
c4c81601 4199
7506f491
DE
4200 src = SET_SRC (pat);
4201
e78d9500 4202 /* Constant propagation. */
b446e5a2 4203 if (CONSTANT_P (src))
7506f491 4204 {
ae860ff7 4205 if (constprop_register (insn, reg_used->reg_rtx, src, alter_jumps))
7506f491
DE
4206 {
4207 changed = 1;
4208 const_prop_count++;
4209 if (gcse_file != NULL)
4210 {
ae860ff7
JH
4211 fprintf (gcse_file, "GLOBAL CONST-PROP: Replacing reg %d in ", regno);
4212 fprintf (gcse_file, "insn %d with constant ", INSN_UID (insn));
e78d9500 4213 print_rtl (gcse_file, src);
7506f491
DE
4214 fprintf (gcse_file, "\n");
4215 }
7506f491
DE
4216 }
4217 }
4218 else if (GET_CODE (src) == REG
4219 && REGNO (src) >= FIRST_PSEUDO_REGISTER
4220 && REGNO (src) != regno)
4221 {
cafba495 4222 if (try_replace_reg (reg_used->reg_rtx, src, insn))
7506f491 4223 {
cafba495
BS
4224 changed = 1;
4225 copy_prop_count++;
4226 if (gcse_file != NULL)
7506f491 4227 {
ae860ff7 4228 fprintf (gcse_file, "GLOBAL COPY-PROP: Replacing reg %d in insn %d",
c4c81601
RK
4229 regno, INSN_UID (insn));
4230 fprintf (gcse_file, " with reg %d\n", REGNO (src));
7506f491 4231 }
cafba495
BS
4232
4233 /* The original insn setting reg_used may or may not now be
4234 deletable. We leave the deletion to flow. */
4235 /* FIXME: If it turns out that the insn isn't deletable,
4236 then we may have unnecessarily extended register lifetimes
4237 and made things worse. */
7506f491
DE
4238 }
4239 }
4240 }
4241
4242 return changed;
4243}
4244
8ba46434
R
4245/* LIBCALL_SP is a zero-terminated array of insns at the end of a libcall;
4246 their REG_EQUAL notes need updating. */
ae860ff7 4247static bool
8ba46434 4248do_local_cprop (x, insn, alter_jumps, libcall_sp)
ae860ff7
JH
4249 rtx x;
4250 rtx insn;
4251 int alter_jumps;
8ba46434 4252 rtx *libcall_sp;
ae860ff7
JH
4253{
4254 rtx newreg = NULL, newcnst = NULL;
4255
8ba46434 4256 /* Rule out USE instructions and ASM statements as we don't want to change the hard registers mentioned. */
ae860ff7
JH
4257 if (GET_CODE (x) == REG
4258 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
4259 || (GET_CODE (PATTERN (insn)) != USE && asm_noperands (PATTERN (insn)) < 0)))
4260 {
4261 cselib_val *val = cselib_lookup (x, GET_MODE (x), 0);
4262 struct elt_loc_list *l;
4263
4264 if (!val)
4265 return false;
4266 for (l = val->locs; l; l = l->next)
4267 {
4268 rtx this_rtx = l->loc;
46690369
JH
4269 rtx note;
4270
ae860ff7
JH
4271 if (CONSTANT_P (this_rtx))
4272 newcnst = this_rtx;
46690369
JH
4273 if (REG_P (this_rtx) && REGNO (this_rtx) >= FIRST_PSEUDO_REGISTER
4274 /* Don't copy propagate if it has attached REG_EQUIV note.
4275 At this point this only function parameters should have
4276 REG_EQUIV notes and if the argument slot is used somewhere
4277 explicitly, it means address of parameter has been taken,
4278 so we should not extend the lifetime of the pseudo. */
4279 && (!(note = find_reg_note (l->setting_insn, REG_EQUIV, NULL_RTX))
4280 || GET_CODE (XEXP (note, 0)) != MEM))
ae860ff7
JH
4281 newreg = this_rtx;
4282 }
4283 if (newcnst && constprop_register (insn, x, newcnst, alter_jumps))
4284 {
8ba46434
R
4285 /* If we find a case where we can't fix the retval REG_EQUAL notes
4286 match the new register, we either have to abandom this replacement
4287 or fix delete_trivially_dead_insns to preserve the setting insn,
4288 or make it delete the REG_EUAQL note, and fix up all passes that
4289 require the REG_EQUAL note there. */
4290 if (!adjust_libcall_notes (x, newcnst, insn, libcall_sp))
4291 abort ();
ae860ff7
JH
4292 if (gcse_file != NULL)
4293 {
4294 fprintf (gcse_file, "LOCAL CONST-PROP: Replacing reg %d in ",
4295 REGNO (x));
4296 fprintf (gcse_file, "insn %d with constant ",
4297 INSN_UID (insn));
4298 print_rtl (gcse_file, newcnst);
4299 fprintf (gcse_file, "\n");
4300 }
4301 const_prop_count++;
4302 return true;
4303 }
4304 else if (newreg && newreg != x && try_replace_reg (x, newreg, insn))
4305 {
8ba46434 4306 adjust_libcall_notes (x, newreg, insn, libcall_sp);
ae860ff7
JH
4307 if (gcse_file != NULL)
4308 {
4309 fprintf (gcse_file,
4310 "LOCAL COPY-PROP: Replacing reg %d in insn %d",
4311 REGNO (x), INSN_UID (insn));
4312 fprintf (gcse_file, " with reg %d\n", REGNO (newreg));
4313 }
4314 copy_prop_count++;
4315 return true;
4316 }
4317 }
4318 return false;
4319}
4320
8ba46434
R
4321/* LIBCALL_SP is a zero-terminated array of insns at the end of a libcall;
4322 their REG_EQUAL notes need updating to reflect that OLDREG has been
4323 replaced with NEWVAL in INSN. Return true if all substitutions could
4324 be made. */
4325static bool
4326adjust_libcall_notes (oldreg, newval, insn, libcall_sp)
4327 rtx oldreg, newval, insn, *libcall_sp;
4328{
4329 rtx end;
4330
4331 while ((end = *libcall_sp++))
4332 {
4333 rtx note = find_reg_equal_equiv_note (end);
4334
4335 if (! note)
4336 continue;
4337
4338 if (REG_P (newval))
4339 {
4340 if (reg_set_between_p (newval, PREV_INSN (insn), end))
4341 {
4342 do
4343 {
4344 note = find_reg_equal_equiv_note (end);
4345 if (! note)
4346 continue;
4347 if (reg_mentioned_p (newval, XEXP (note, 0)))
4348 return false;
4349 }
4350 while ((end = *libcall_sp++));
4351 return true;
4352 }
4353 }
4354 XEXP (note, 0) = replace_rtx (XEXP (note, 0), oldreg, newval);
4355 insn = end;
4356 }
4357 return true;
4358}
4359
4360#define MAX_NESTED_LIBCALLS 9
4361
ae860ff7
JH
4362static void
4363local_cprop_pass (alter_jumps)
4364 int alter_jumps;
4365{
4366 rtx insn;
4367 struct reg_use *reg_used;
8ba46434 4368 rtx libcall_stack[MAX_NESTED_LIBCALLS + 1], *libcall_sp;
ae860ff7
JH
4369
4370 cselib_init ();
8ba46434
R
4371 libcall_sp = &libcall_stack[MAX_NESTED_LIBCALLS];
4372 *libcall_sp = 0;
ae860ff7
JH
4373 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4374 {
4375 if (INSN_P (insn))
4376 {
8ba46434 4377 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
ae860ff7 4378
8ba46434
R
4379 if (note)
4380 {
4381 if (libcall_sp == libcall_stack)
4382 abort ();
4383 *--libcall_sp = XEXP (note, 0);
4384 }
4385 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
4386 if (note)
4387 libcall_sp++;
4388 note = find_reg_equal_equiv_note (insn);
ae860ff7
JH
4389 do
4390 {
4391 reg_use_count = 0;
4392 note_uses (&PATTERN (insn), find_used_regs, NULL);
4393 if (note)
4394 find_used_regs (&XEXP (note, 0), NULL);
4395
4396 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
4397 reg_used++, reg_use_count--)
8ba46434
R
4398 if (do_local_cprop (reg_used->reg_rtx, insn, alter_jumps,
4399 libcall_sp))
ae860ff7
JH
4400 break;
4401 }
4402 while (reg_use_count);
4403 }
4404 cselib_process_insn (insn);
4405 }
4406 cselib_finish ();
4407}
4408
c4c81601
RK
4409/* Forward propagate copies. This includes copies and constants. Return
4410 non-zero if a change was made. */
7506f491
DE
4411
4412static int
b5ce41ff
JL
4413cprop (alter_jumps)
4414 int alter_jumps;
7506f491 4415{
e0082a72
ZD
4416 int changed;
4417 basic_block bb;
7506f491
DE
4418 rtx insn;
4419
4420 /* Note we start at block 1. */
e0082a72
ZD
4421 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
4422 {
4423 if (gcse_file != NULL)
4424 fprintf (gcse_file, "\n");
4425 return 0;
4426 }
7506f491
DE
4427
4428 changed = 0;
e0082a72 4429 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb, EXIT_BLOCK_PTR, next_bb)
7506f491
DE
4430 {
4431 /* Reset tables used to keep track of what's still valid [since the
4432 start of the block]. */
4433 reset_opr_set_tables ();
4434
e0082a72
ZD
4435 for (insn = bb->head;
4436 insn != NULL && insn != NEXT_INSN (bb->end);
7506f491 4437 insn = NEXT_INSN (insn))
172890a2
RK
4438 if (INSN_P (insn))
4439 {
ae860ff7 4440 changed |= cprop_insn (insn, alter_jumps);
7506f491 4441
172890a2
RK
4442 /* Keep track of everything modified by this insn. */
4443 /* ??? Need to be careful w.r.t. mods done to INSN. Don't
4444 call mark_oprs_set if we turned the insn into a NOTE. */
4445 if (GET_CODE (insn) != NOTE)
4446 mark_oprs_set (insn);
8e42ace1 4447 }
7506f491
DE
4448 }
4449
4450 if (gcse_file != NULL)
4451 fprintf (gcse_file, "\n");
4452
4453 return changed;
4454}
4455
4456/* Perform one copy/constant propagation pass.
4457 F is the first insn in the function.
4458 PASS is the pass count. */
4459
4460static int
b5ce41ff 4461one_cprop_pass (pass, alter_jumps)
7506f491 4462 int pass;
b5ce41ff 4463 int alter_jumps;
7506f491
DE
4464{
4465 int changed = 0;
4466
4467 const_prop_count = 0;
4468 copy_prop_count = 0;
4469
ae860ff7
JH
4470 local_cprop_pass (alter_jumps);
4471
02280659
ZD
4472 alloc_hash_table (max_cuid, &set_hash_table, 1);
4473 compute_hash_table (&set_hash_table);
7506f491 4474 if (gcse_file)
02280659
ZD
4475 dump_hash_table (gcse_file, "SET", &set_hash_table);
4476 if (set_hash_table.n_elems > 0)
7506f491 4477 {
02280659 4478 alloc_cprop_mem (last_basic_block, set_hash_table.n_elems);
7506f491 4479 compute_cprop_data ();
b5ce41ff 4480 changed = cprop (alter_jumps);
0e3f0221
RS
4481 if (alter_jumps)
4482 changed |= bypass_conditional_jumps ();
7506f491
DE
4483 free_cprop_mem ();
4484 }
c4c81601 4485
02280659 4486 free_hash_table (&set_hash_table);
7506f491
DE
4487
4488 if (gcse_file)
4489 {
c4c81601
RK
4490 fprintf (gcse_file, "CPROP of %s, pass %d: %d bytes needed, ",
4491 current_function_name, pass, bytes_used);
4492 fprintf (gcse_file, "%d const props, %d copy props\n\n",
4493 const_prop_count, copy_prop_count);
7506f491
DE
4494 }
4495
4496 return changed;
4497}
4498\f
0e3f0221
RS
4499/* Bypass conditional jumps. */
4500
4501/* Find a set of REGNO to a constant that is available at the end of basic
4502 block BB. Returns NULL if no such set is found. Based heavily upon
4503 find_avail_set. */
4504
4505static struct expr *
4506find_bypass_set (regno, bb)
4507 int regno;
4508 int bb;
4509{
4510 struct expr *result = 0;
4511
4512 for (;;)
4513 {
4514 rtx src;
02280659 4515 struct expr *set = lookup_set (regno, NULL_RTX, &set_hash_table);
0e3f0221
RS
4516
4517 while (set)
4518 {
4519 if (TEST_BIT (cprop_avout[bb], set->bitmap_index))
4520 break;
4521 set = next_set (regno, set);
4522 }
4523
4524 if (set == 0)
4525 break;
4526
4527 if (GET_CODE (set->expr) != SET)
4528 abort ();
4529
4530 src = SET_SRC (set->expr);
4531 if (CONSTANT_P (src))
4532 result = set;
4533
4534 if (GET_CODE (src) != REG)
4535 break;
4536
4537 regno = REGNO (src);
4538 }
4539 return result;
4540}
4541
4542
4543/* Subroutine of bypass_conditional_jumps that attempts to bypass the given
4544 basic block BB which has more than one predecessor. If not NULL, SETCC
4545 is the first instruction of BB, which is immediately followed by JUMP_INSN
4546 JUMP. Otherwise, SETCC is NULL, and JUMP is the first insn of BB.
4547 Returns nonzero if a change was made. */
4548
4549static int
4550bypass_block (bb, setcc, jump)
4551 basic_block bb;
4552 rtx setcc, jump;
4553{
4554 rtx insn, note;
4555 edge e, enext;
818b6b7f 4556 int i, change;
0e3f0221
RS
4557
4558 insn = (setcc != NULL) ? setcc : jump;
4559
4560 /* Determine set of register uses in INSN. */
4561 reg_use_count = 0;
4562 note_uses (&PATTERN (insn), find_used_regs, NULL);
4563 note = find_reg_equal_equiv_note (insn);
4564 if (note)
4565 find_used_regs (&XEXP (note, 0), NULL);
4566
4567 change = 0;
4568 for (e = bb->pred; e; e = enext)
4569 {
4570 enext = e->pred_next;
4571 for (i = 0; i < reg_use_count; i++)
4572 {
4573 struct reg_use *reg_used = &reg_use_table[i];
589005ff 4574 unsigned int regno = REGNO (reg_used->reg_rtx);
818b6b7f 4575 basic_block dest, old_dest;
589005ff
KH
4576 struct expr *set;
4577 rtx src, new;
0e3f0221 4578
589005ff
KH
4579 if (regno >= max_gcse_regno)
4580 continue;
0e3f0221 4581
589005ff 4582 set = find_bypass_set (regno, e->src->index);
0e3f0221
RS
4583
4584 if (! set)
4585 continue;
4586
589005ff 4587 src = SET_SRC (pc_set (jump));
0e3f0221
RS
4588
4589 if (setcc != NULL)
4590 src = simplify_replace_rtx (src,
589005ff
KH
4591 SET_DEST (PATTERN (setcc)),
4592 SET_SRC (PATTERN (setcc)));
0e3f0221
RS
4593
4594 new = simplify_replace_rtx (src, reg_used->reg_rtx,
589005ff 4595 SET_SRC (set->expr));
0e3f0221 4596
589005ff 4597 if (new == pc_rtx)
0e3f0221
RS
4598 dest = FALLTHRU_EDGE (bb)->dest;
4599 else if (GET_CODE (new) == LABEL_REF)
4600 dest = BRANCH_EDGE (bb)->dest;
4601 else
4602 dest = NULL;
4603
4604 /* Once basic block indices are stable, we should be able
4605 to use redirect_edge_and_branch_force instead. */
818b6b7f
RH
4606 old_dest = e->dest;
4607 if (dest != NULL && dest != old_dest
0e3f0221
RS
4608 && redirect_edge_and_branch (e, dest))
4609 {
818b6b7f 4610 /* Copy the register setter to the redirected edge.
0e3f0221
RS
4611 Don't copy CC0 setters, as CC0 is dead after jump. */
4612 if (setcc)
4613 {
4614 rtx pat = PATTERN (setcc);
818b6b7f 4615 if (!CC0_P (SET_DEST (pat)))
0e3f0221
RS
4616 insert_insn_on_edge (copy_insn (pat), e);
4617 }
4618
4619 if (gcse_file != NULL)
4620 {
818b6b7f
RH
4621 fprintf (gcse_file, "JUMP-BYPASS: Proved reg %d in jump_insn %d equals constant ",
4622 regno, INSN_UID (jump));
0e3f0221
RS
4623 print_rtl (gcse_file, SET_SRC (set->expr));
4624 fprintf (gcse_file, "\nBypass edge from %d->%d to %d\n",
818b6b7f 4625 e->src->index, old_dest->index, dest->index);
0e3f0221
RS
4626 }
4627 change = 1;
4628 break;
4629 }
4630 }
4631 }
4632 return change;
4633}
4634
4635/* Find basic blocks with more than one predecessor that only contain a
4636 single conditional jump. If the result of the comparison is known at
4637 compile-time from any incoming edge, redirect that edge to the
4638 appropriate target. Returns nonzero if a change was made. */
4639
4640static int
4641bypass_conditional_jumps ()
4642{
4643 basic_block bb;
4644 int changed;
4645 rtx setcc;
4646 rtx insn;
4647 rtx dest;
4648
4649 /* Note we start at block 1. */
4650 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
4651 return 0;
4652
4653 changed = 0;
4654 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb,
589005ff 4655 EXIT_BLOCK_PTR, next_bb)
0e3f0221
RS
4656 {
4657 /* Check for more than one predecessor. */
4658 if (bb->pred && bb->pred->pred_next)
4659 {
4660 setcc = NULL_RTX;
4661 for (insn = bb->head;
4662 insn != NULL && insn != NEXT_INSN (bb->end);
4663 insn = NEXT_INSN (insn))
4664 if (GET_CODE (insn) == INSN)
4665 {
9543a9d2 4666 if (setcc)
0e3f0221 4667 break;
ba4f7968 4668 if (GET_CODE (PATTERN (insn)) != SET)
0e3f0221
RS
4669 break;
4670
ba4f7968 4671 dest = SET_DEST (PATTERN (insn));
818b6b7f 4672 if (REG_P (dest) || CC0_P (dest))
0e3f0221 4673 setcc = insn;
0e3f0221
RS
4674 else
4675 break;
4676 }
4677 else if (GET_CODE (insn) == JUMP_INSN)
4678 {
4679 if (any_condjump_p (insn) && onlyjump_p (insn))
4680 changed |= bypass_block (bb, setcc, insn);
4681 break;
4682 }
4683 else if (INSN_P (insn))
4684 break;
4685 }
4686 }
4687
818b6b7f 4688 /* If we bypassed any register setting insns, we inserted a
0e3f0221
RS
4689 copy on the redirected edge. These need to be commited. */
4690 if (changed)
4691 commit_edge_insertions();
4692
4693 return changed;
4694}
4695\f
a65f3558 4696/* Compute PRE+LCM working variables. */
7506f491
DE
4697
4698/* Local properties of expressions. */
4699/* Nonzero for expressions that are transparent in the block. */
a65f3558 4700static sbitmap *transp;
7506f491 4701
5c35539b
RH
4702/* Nonzero for expressions that are transparent at the end of the block.
4703 This is only zero for expressions killed by abnormal critical edge
4704 created by a calls. */
a65f3558 4705static sbitmap *transpout;
5c35539b 4706
a65f3558
JL
4707/* Nonzero for expressions that are computed (available) in the block. */
4708static sbitmap *comp;
7506f491 4709
a65f3558
JL
4710/* Nonzero for expressions that are locally anticipatable in the block. */
4711static sbitmap *antloc;
7506f491 4712
a65f3558
JL
4713/* Nonzero for expressions where this block is an optimal computation
4714 point. */
4715static sbitmap *pre_optimal;
5c35539b 4716
a65f3558
JL
4717/* Nonzero for expressions which are redundant in a particular block. */
4718static sbitmap *pre_redundant;
7506f491 4719
a42cd965
AM
4720/* Nonzero for expressions which should be inserted on a specific edge. */
4721static sbitmap *pre_insert_map;
4722
4723/* Nonzero for expressions which should be deleted in a specific block. */
4724static sbitmap *pre_delete_map;
4725
4726/* Contains the edge_list returned by pre_edge_lcm. */
4727static struct edge_list *edge_list;
4728
a65f3558
JL
4729/* Redundant insns. */
4730static sbitmap pre_redundant_insns;
7506f491 4731
a65f3558 4732/* Allocate vars used for PRE analysis. */
7506f491
DE
4733
4734static void
a65f3558
JL
4735alloc_pre_mem (n_blocks, n_exprs)
4736 int n_blocks, n_exprs;
7506f491 4737{
a65f3558
JL
4738 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
4739 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
4740 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5faf03ae 4741
a42cd965
AM
4742 pre_optimal = NULL;
4743 pre_redundant = NULL;
4744 pre_insert_map = NULL;
4745 pre_delete_map = NULL;
4746 ae_in = NULL;
4747 ae_out = NULL;
a42cd965 4748 ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs);
c4c81601 4749
a42cd965 4750 /* pre_insert and pre_delete are allocated later. */
7506f491
DE
4751}
4752
a65f3558 4753/* Free vars used for PRE analysis. */
7506f491
DE
4754
4755static void
a65f3558 4756free_pre_mem ()
7506f491 4757{
5a660bff
DB
4758 sbitmap_vector_free (transp);
4759 sbitmap_vector_free (comp);
bd3675fc
JL
4760
4761 /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */
7506f491 4762
a42cd965 4763 if (pre_optimal)
5a660bff 4764 sbitmap_vector_free (pre_optimal);
a42cd965 4765 if (pre_redundant)
5a660bff 4766 sbitmap_vector_free (pre_redundant);
a42cd965 4767 if (pre_insert_map)
5a660bff 4768 sbitmap_vector_free (pre_insert_map);
a42cd965 4769 if (pre_delete_map)
5a660bff 4770 sbitmap_vector_free (pre_delete_map);
a42cd965 4771 if (ae_in)
5a660bff 4772 sbitmap_vector_free (ae_in);
a42cd965 4773 if (ae_out)
5a660bff 4774 sbitmap_vector_free (ae_out);
a42cd965 4775
bd3675fc 4776 transp = comp = NULL;
a42cd965 4777 pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL;
55d3f917 4778 ae_in = ae_out = NULL;
7506f491
DE
4779}
4780
4781/* Top level routine to do the dataflow analysis needed by PRE. */
4782
4783static void
4784compute_pre_data ()
4785{
b614171e 4786 sbitmap trapping_expr;
e0082a72 4787 basic_block bb;
b614171e 4788 unsigned int ui;
c66e8ae9 4789
02280659 4790 compute_local_properties (transp, comp, antloc, &expr_hash_table);
d55bc081 4791 sbitmap_vector_zero (ae_kill, last_basic_block);
c66e8ae9 4792
b614171e 4793 /* Collect expressions which might trap. */
02280659 4794 trapping_expr = sbitmap_alloc (expr_hash_table.n_elems);
b614171e 4795 sbitmap_zero (trapping_expr);
02280659 4796 for (ui = 0; ui < expr_hash_table.size; ui++)
b614171e
MM
4797 {
4798 struct expr *e;
02280659 4799 for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash)
b614171e
MM
4800 if (may_trap_p (e->expr))
4801 SET_BIT (trapping_expr, e->bitmap_index);
4802 }
4803
c66e8ae9
JL
4804 /* Compute ae_kill for each basic block using:
4805
4806 ~(TRANSP | COMP)
4807
a2e90653 4808 This is significantly faster than compute_ae_kill. */
c66e8ae9 4809
e0082a72 4810 FOR_EACH_BB (bb)
c66e8ae9 4811 {
b614171e
MM
4812 edge e;
4813
4814 /* If the current block is the destination of an abnormal edge, we
4815 kill all trapping expressions because we won't be able to properly
4816 place the instruction on the edge. So make them neither
4817 anticipatable nor transparent. This is fairly conservative. */
e0082a72 4818 for (e = bb->pred; e ; e = e->pred_next)
b614171e
MM
4819 if (e->flags & EDGE_ABNORMAL)
4820 {
e0082a72
ZD
4821 sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr);
4822 sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr);
b614171e
MM
4823 break;
4824 }
4825
e0082a72
ZD
4826 sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]);
4827 sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]);
c66e8ae9
JL
4828 }
4829
02280659 4830 edge_list = pre_edge_lcm (gcse_file, expr_hash_table.n_elems, transp, comp, antloc,
a42cd965 4831 ae_kill, &pre_insert_map, &pre_delete_map);
5a660bff 4832 sbitmap_vector_free (antloc);
bd3675fc 4833 antloc = NULL;
5a660bff 4834 sbitmap_vector_free (ae_kill);
589005ff 4835 ae_kill = NULL;
76ac938b 4836 sbitmap_free (trapping_expr);
7506f491
DE
4837}
4838\f
4839/* PRE utilities */
4840
a65f3558
JL
4841/* Return non-zero if an occurrence of expression EXPR in OCCR_BB would reach
4842 block BB.
7506f491
DE
4843
4844 VISITED is a pointer to a working buffer for tracking which BB's have
4845 been visited. It is NULL for the top-level call.
4846
4847 We treat reaching expressions that go through blocks containing the same
4848 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
4849 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
4850 2 as not reaching. The intent is to improve the probability of finding
4851 only one reaching expression and to reduce register lifetimes by picking
4852 the closest such expression. */
4853
4854static int
89e606c9 4855pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited)
e2d2ed72 4856 basic_block occr_bb;
7506f491 4857 struct expr *expr;
e2d2ed72 4858 basic_block bb;
7506f491
DE
4859 char *visited;
4860{
36349f8b 4861 edge pred;
7506f491 4862
e2d2ed72 4863 for (pred = bb->pred; pred != NULL; pred = pred->pred_next)
7506f491 4864 {
e2d2ed72 4865 basic_block pred_bb = pred->src;
7506f491 4866
36349f8b 4867 if (pred->src == ENTRY_BLOCK_PTR
7506f491 4868 /* Has predecessor has already been visited? */
0b17ab2f 4869 || visited[pred_bb->index])
c4c81601
RK
4870 ;/* Nothing to do. */
4871
7506f491 4872 /* Does this predecessor generate this expression? */
0b17ab2f 4873 else if (TEST_BIT (comp[pred_bb->index], expr->bitmap_index))
7506f491
DE
4874 {
4875 /* Is this the occurrence we're looking for?
4876 Note that there's only one generating occurrence per block
4877 so we just need to check the block number. */
a65f3558 4878 if (occr_bb == pred_bb)
7506f491 4879 return 1;
c4c81601 4880
0b17ab2f 4881 visited[pred_bb->index] = 1;
7506f491
DE
4882 }
4883 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
4884 else if (! TEST_BIT (transp[pred_bb->index], expr->bitmap_index))
4885 visited[pred_bb->index] = 1;
c4c81601 4886
7506f491
DE
4887 /* Neither gen nor kill. */
4888 else
ac7c5af5 4889 {
0b17ab2f 4890 visited[pred_bb->index] = 1;
89e606c9 4891 if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited))
7506f491 4892 return 1;
ac7c5af5 4893 }
7506f491
DE
4894 }
4895
4896 /* All paths have been checked. */
4897 return 0;
4898}
283a2545
RL
4899
4900/* The wrapper for pre_expr_reaches_here_work that ensures that any
dc297297 4901 memory allocated for that function is returned. */
283a2545
RL
4902
4903static int
89e606c9 4904pre_expr_reaches_here_p (occr_bb, expr, bb)
e2d2ed72 4905 basic_block occr_bb;
283a2545 4906 struct expr *expr;
e2d2ed72 4907 basic_block bb;
283a2545
RL
4908{
4909 int rval;
d55bc081 4910 char *visited = (char *) xcalloc (last_basic_block, 1);
283a2545 4911
8e42ace1 4912 rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited);
283a2545
RL
4913
4914 free (visited);
c4c81601 4915 return rval;
283a2545 4916}
7506f491 4917\f
a42cd965
AM
4918
4919/* Given an expr, generate RTL which we can insert at the end of a BB,
589005ff 4920 or on an edge. Set the block number of any insns generated to
a42cd965
AM
4921 the value of BB. */
4922
4923static rtx
4924process_insert_insn (expr)
4925 struct expr *expr;
4926{
4927 rtx reg = expr->reaching_reg;
fb0c0a12
RK
4928 rtx exp = copy_rtx (expr->expr);
4929 rtx pat;
a42cd965
AM
4930
4931 start_sequence ();
fb0c0a12
RK
4932
4933 /* If the expression is something that's an operand, like a constant,
4934 just copy it to a register. */
4935 if (general_operand (exp, GET_MODE (reg)))
4936 emit_move_insn (reg, exp);
4937
4938 /* Otherwise, make a new insn to compute this expression and make sure the
4939 insn will be recognized (this also adds any needed CLOBBERs). Copy the
4940 expression to make sure we don't have any sharing issues. */
8d444206 4941 else if (insn_invalid_p (emit_insn (gen_rtx_SET (VOIDmode, reg, exp))))
fb0c0a12 4942 abort ();
589005ff 4943
2f937369 4944 pat = get_insns ();
a42cd965
AM
4945 end_sequence ();
4946
4947 return pat;
4948}
589005ff 4949
a65f3558
JL
4950/* Add EXPR to the end of basic block BB.
4951
4952 This is used by both the PRE and code hoisting.
4953
4954 For PRE, we want to verify that the expr is either transparent
4955 or locally anticipatable in the target block. This check makes
4956 no sense for code hoisting. */
7506f491
DE
4957
4958static void
a65f3558 4959insert_insn_end_bb (expr, bb, pre)
7506f491 4960 struct expr *expr;
e2d2ed72 4961 basic_block bb;
a65f3558 4962 int pre;
7506f491 4963{
e2d2ed72 4964 rtx insn = bb->end;
7506f491
DE
4965 rtx new_insn;
4966 rtx reg = expr->reaching_reg;
4967 int regno = REGNO (reg);
2f937369 4968 rtx pat, pat_end;
7506f491 4969
a42cd965 4970 pat = process_insert_insn (expr);
2f937369
DM
4971 if (pat == NULL_RTX || ! INSN_P (pat))
4972 abort ();
4973
4974 pat_end = pat;
4975 while (NEXT_INSN (pat_end) != NULL_RTX)
4976 pat_end = NEXT_INSN (pat_end);
7506f491
DE
4977
4978 /* If the last insn is a jump, insert EXPR in front [taking care to
068473ec
JH
4979 handle cc0, etc. properly]. Similary we need to care trapping
4980 instructions in presence of non-call exceptions. */
7506f491 4981
068473ec
JH
4982 if (GET_CODE (insn) == JUMP_INSN
4983 || (GET_CODE (insn) == INSN
4984 && (bb->succ->succ_next || (bb->succ->flags & EDGE_ABNORMAL))))
7506f491 4985 {
50b2596f 4986#ifdef HAVE_cc0
7506f491 4987 rtx note;
50b2596f 4988#endif
068473ec
JH
4989 /* It should always be the case that we can put these instructions
4990 anywhere in the basic block with performing PRE optimizations.
4991 Check this. */
3b25fbfe 4992 if (GET_CODE (insn) == INSN && pre
0b17ab2f 4993 && !TEST_BIT (antloc[bb->index], expr->bitmap_index)
589005ff 4994 && !TEST_BIT (transp[bb->index], expr->bitmap_index))
068473ec 4995 abort ();
7506f491
DE
4996
4997 /* If this is a jump table, then we can't insert stuff here. Since
4998 we know the previous real insn must be the tablejump, we insert
4999 the new instruction just before the tablejump. */
5000 if (GET_CODE (PATTERN (insn)) == ADDR_VEC
5001 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
5002 insn = prev_real_insn (insn);
5003
5004#ifdef HAVE_cc0
5005 /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts
5006 if cc0 isn't set. */
5007 note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
5008 if (note)
5009 insn = XEXP (note, 0);
5010 else
5011 {
5012 rtx maybe_cc0_setter = prev_nonnote_insn (insn);
5013 if (maybe_cc0_setter
2c3c49de 5014 && INSN_P (maybe_cc0_setter)
7506f491
DE
5015 && sets_cc0_p (PATTERN (maybe_cc0_setter)))
5016 insn = maybe_cc0_setter;
5017 }
5018#endif
5019 /* FIXME: What if something in cc0/jump uses value set in new insn? */
3c030e88 5020 new_insn = emit_insn_before (pat, insn);
3947e2f9 5021 }
c4c81601 5022
3947e2f9
RH
5023 /* Likewise if the last insn is a call, as will happen in the presence
5024 of exception handling. */
068473ec
JH
5025 else if (GET_CODE (insn) == CALL_INSN
5026 && (bb->succ->succ_next || (bb->succ->flags & EDGE_ABNORMAL)))
3947e2f9 5027 {
3947e2f9
RH
5028 /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers,
5029 we search backward and place the instructions before the first
5030 parameter is loaded. Do this for everyone for consistency and a
589005ff 5031 presumtion that we'll get better code elsewhere as well.
3947e2f9 5032
c4c81601 5033 It should always be the case that we can put these instructions
a65f3558
JL
5034 anywhere in the basic block with performing PRE optimizations.
5035 Check this. */
c4c81601 5036
a65f3558 5037 if (pre
0b17ab2f 5038 && !TEST_BIT (antloc[bb->index], expr->bitmap_index)
589005ff 5039 && !TEST_BIT (transp[bb->index], expr->bitmap_index))
3947e2f9
RH
5040 abort ();
5041
5042 /* Since different machines initialize their parameter registers
5043 in different orders, assume nothing. Collect the set of all
5044 parameter registers. */
833366d6 5045 insn = find_first_parameter_load (insn, bb->head);
3947e2f9 5046
b1d26727
JL
5047 /* If we found all the parameter loads, then we want to insert
5048 before the first parameter load.
5049
5050 If we did not find all the parameter loads, then we might have
5051 stopped on the head of the block, which could be a CODE_LABEL.
5052 If we inserted before the CODE_LABEL, then we would be putting
5053 the insn in the wrong basic block. In that case, put the insn
b5229628 5054 after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */
0a377997 5055 while (GET_CODE (insn) == CODE_LABEL
589ca5cb 5056 || NOTE_INSN_BASIC_BLOCK_P (insn))
b5229628 5057 insn = NEXT_INSN (insn);
c4c81601 5058
3c030e88 5059 new_insn = emit_insn_before (pat, insn);
7506f491
DE
5060 }
5061 else
3c030e88 5062 new_insn = emit_insn_after (pat, insn);
7506f491 5063
2f937369 5064 while (1)
a65f3558 5065 {
2f937369 5066 if (INSN_P (pat))
a65f3558 5067 {
2f937369
DM
5068 add_label_notes (PATTERN (pat), new_insn);
5069 note_stores (PATTERN (pat), record_set_info, pat);
a65f3558 5070 }
2f937369
DM
5071 if (pat == pat_end)
5072 break;
5073 pat = NEXT_INSN (pat);
a65f3558 5074 }
3947e2f9 5075
7506f491
DE
5076 gcse_create_count++;
5077
5078 if (gcse_file)
5079 {
c4c81601 5080 fprintf (gcse_file, "PRE/HOIST: end of bb %d, insn %d, ",
0b17ab2f 5081 bb->index, INSN_UID (new_insn));
c4c81601
RK
5082 fprintf (gcse_file, "copying expression %d to reg %d\n",
5083 expr->bitmap_index, regno);
7506f491
DE
5084 }
5085}
5086
a42cd965
AM
5087/* Insert partially redundant expressions on edges in the CFG to make
5088 the expressions fully redundant. */
7506f491 5089
a42cd965
AM
5090static int
5091pre_edge_insert (edge_list, index_map)
5092 struct edge_list *edge_list;
7506f491
DE
5093 struct expr **index_map;
5094{
c4c81601 5095 int e, i, j, num_edges, set_size, did_insert = 0;
a65f3558
JL
5096 sbitmap *inserted;
5097
a42cd965
AM
5098 /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge
5099 if it reaches any of the deleted expressions. */
7506f491 5100
a42cd965
AM
5101 set_size = pre_insert_map[0]->size;
5102 num_edges = NUM_EDGES (edge_list);
02280659 5103 inserted = sbitmap_vector_alloc (num_edges, expr_hash_table.n_elems);
a42cd965 5104 sbitmap_vector_zero (inserted, num_edges);
7506f491 5105
a42cd965 5106 for (e = 0; e < num_edges; e++)
7506f491
DE
5107 {
5108 int indx;
e2d2ed72 5109 basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e);
a65f3558 5110
a65f3558 5111 for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS)
7506f491 5112 {
a42cd965 5113 SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i];
7506f491 5114
02280659 5115 for (j = indx; insert && j < (int) expr_hash_table.n_elems; j++, insert >>= 1)
c4c81601
RK
5116 if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX)
5117 {
5118 struct expr *expr = index_map[j];
5119 struct occr *occr;
a65f3558 5120
ff7cc307 5121 /* Now look at each deleted occurrence of this expression. */
c4c81601
RK
5122 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
5123 {
5124 if (! occr->deleted_p)
5125 continue;
5126
5127 /* Insert this expression on this edge if if it would
ff7cc307 5128 reach the deleted occurrence in BB. */
c4c81601
RK
5129 if (!TEST_BIT (inserted[e], j))
5130 {
5131 rtx insn;
5132 edge eg = INDEX_EDGE (edge_list, e);
5133
5134 /* We can't insert anything on an abnormal and
5135 critical edge, so we insert the insn at the end of
5136 the previous block. There are several alternatives
5137 detailed in Morgans book P277 (sec 10.5) for
5138 handling this situation. This one is easiest for
5139 now. */
5140
5141 if ((eg->flags & EDGE_ABNORMAL) == EDGE_ABNORMAL)
5142 insert_insn_end_bb (index_map[j], bb, 0);
5143 else
5144 {
5145 insn = process_insert_insn (index_map[j]);
5146 insert_insn_on_edge (insn, eg);
5147 }
5148
5149 if (gcse_file)
5150 {
5151 fprintf (gcse_file, "PRE/HOIST: edge (%d,%d), ",
0b17ab2f
RH
5152 bb->index,
5153 INDEX_EDGE_SUCC_BB (edge_list, e)->index);
c4c81601
RK
5154 fprintf (gcse_file, "copy expression %d\n",
5155 expr->bitmap_index);
5156 }
5157
a13d4ebf 5158 update_ld_motion_stores (expr);
c4c81601
RK
5159 SET_BIT (inserted[e], j);
5160 did_insert = 1;
5161 gcse_create_count++;
5162 }
5163 }
5164 }
7506f491
DE
5165 }
5166 }
5faf03ae 5167
5a660bff 5168 sbitmap_vector_free (inserted);
a42cd965 5169 return did_insert;
7506f491
DE
5170}
5171
c4c81601 5172/* Copy the result of INSN to REG. INDX is the expression number. */
7506f491
DE
5173
5174static void
5175pre_insert_copy_insn (expr, insn)
5176 struct expr *expr;
5177 rtx insn;
5178{
5179 rtx reg = expr->reaching_reg;
5180 int regno = REGNO (reg);
5181 int indx = expr->bitmap_index;
5182 rtx set = single_set (insn);
5183 rtx new_insn;
5184
5185 if (!set)
5186 abort ();
c4c81601 5187
cccf0ae8 5188 new_insn = emit_insn_after (gen_move_insn (reg, SET_DEST (set)), insn);
c4c81601 5189
7506f491
DE
5190 /* Keep register set table up to date. */
5191 record_one_set (regno, new_insn);
5192
5193 gcse_create_count++;
5194
5195 if (gcse_file)
a42cd965
AM
5196 fprintf (gcse_file,
5197 "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n",
5198 BLOCK_NUM (insn), INSN_UID (new_insn), indx,
5199 INSN_UID (insn), regno);
222f7ba9 5200 update_ld_motion_stores (expr);
7506f491
DE
5201}
5202
5203/* Copy available expressions that reach the redundant expression
5204 to `reaching_reg'. */
5205
5206static void
5207pre_insert_copies ()
5208{
2e653e39 5209 unsigned int i;
c4c81601
RK
5210 struct expr *expr;
5211 struct occr *occr;
5212 struct occr *avail;
a65f3558 5213
7506f491
DE
5214 /* For each available expression in the table, copy the result to
5215 `reaching_reg' if the expression reaches a deleted one.
5216
5217 ??? The current algorithm is rather brute force.
5218 Need to do some profiling. */
5219
02280659
ZD
5220 for (i = 0; i < expr_hash_table.size; i++)
5221 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
5222 {
5223 /* If the basic block isn't reachable, PPOUT will be TRUE. However,
5224 we don't want to insert a copy here because the expression may not
5225 really be redundant. So only insert an insn if the expression was
5226 deleted. This test also avoids further processing if the
5227 expression wasn't deleted anywhere. */
5228 if (expr->reaching_reg == NULL)
5229 continue;
5230
5231 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
5232 {
5233 if (! occr->deleted_p)
5234 continue;
7506f491 5235
c4c81601
RK
5236 for (avail = expr->avail_occr; avail != NULL; avail = avail->next)
5237 {
5238 rtx insn = avail->insn;
7506f491 5239
c4c81601
RK
5240 /* No need to handle this one if handled already. */
5241 if (avail->copied_p)
5242 continue;
7506f491 5243
c4c81601
RK
5244 /* Don't handle this one if it's a redundant one. */
5245 if (TEST_BIT (pre_redundant_insns, INSN_CUID (insn)))
5246 continue;
7506f491 5247
c4c81601 5248 /* Or if the expression doesn't reach the deleted one. */
589005ff 5249 if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn),
e2d2ed72
AM
5250 expr,
5251 BLOCK_FOR_INSN (occr->insn)))
c4c81601 5252 continue;
7506f491 5253
c4c81601
RK
5254 /* Copy the result of avail to reaching_reg. */
5255 pre_insert_copy_insn (expr, insn);
5256 avail->copied_p = 1;
5257 }
5258 }
5259 }
7506f491
DE
5260}
5261
10d1bb36
JH
5262/* Emit move from SRC to DEST noting the equivalence with expression computed
5263 in INSN. */
5264static rtx
5265gcse_emit_move_after (src, dest, insn)
5266 rtx src, dest, insn;
5267{
5268 rtx new;
6bdb8dd6 5269 rtx set = single_set (insn), set2;
10d1bb36
JH
5270 rtx note;
5271 rtx eqv;
5272
5273 /* This should never fail since we're creating a reg->reg copy
5274 we've verified to be valid. */
5275
6bdb8dd6 5276 new = emit_insn_after (gen_move_insn (dest, src), insn);
285464d0 5277
10d1bb36 5278 /* Note the equivalence for local CSE pass. */
6bdb8dd6
JH
5279 set2 = single_set (new);
5280 if (!set2 || !rtx_equal_p (SET_DEST (set2), dest))
5281 return new;
10d1bb36
JH
5282 if ((note = find_reg_equal_equiv_note (insn)))
5283 eqv = XEXP (note, 0);
5284 else
5285 eqv = SET_SRC (set);
5286
5287 set_unique_reg_note (new, REG_EQUAL, copy_insn_1 (src));
5288
5289 return new;
5290}
5291
7506f491 5292/* Delete redundant computations.
7506f491
DE
5293 Deletion is done by changing the insn to copy the `reaching_reg' of
5294 the expression into the result of the SET. It is left to later passes
5295 (cprop, cse2, flow, combine, regmove) to propagate the copy or eliminate it.
5296
5297 Returns non-zero if a change is made. */
5298
5299static int
5300pre_delete ()
5301{
2e653e39 5302 unsigned int i;
63bc1d05 5303 int changed;
c4c81601
RK
5304 struct expr *expr;
5305 struct occr *occr;
a65f3558 5306
7506f491 5307 changed = 0;
02280659
ZD
5308 for (i = 0; i < expr_hash_table.size; i++)
5309 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
5310 {
5311 int indx = expr->bitmap_index;
7506f491 5312
c4c81601
RK
5313 /* We only need to search antic_occr since we require
5314 ANTLOC != 0. */
7506f491 5315
c4c81601
RK
5316 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
5317 {
5318 rtx insn = occr->insn;
5319 rtx set;
e2d2ed72 5320 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491 5321
0b17ab2f 5322 if (TEST_BIT (pre_delete_map[bb->index], indx))
c4c81601
RK
5323 {
5324 set = single_set (insn);
5325 if (! set)
5326 abort ();
5327
5328 /* Create a pseudo-reg to store the result of reaching
5329 expressions into. Get the mode for the new pseudo from
5330 the mode of the original destination pseudo. */
5331 if (expr->reaching_reg == NULL)
5332 expr->reaching_reg
5333 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
5334
10d1bb36
JH
5335 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
5336 delete_insn (insn);
5337 occr->deleted_p = 1;
5338 SET_BIT (pre_redundant_insns, INSN_CUID (insn));
5339 changed = 1;
5340 gcse_subst_count++;
7506f491 5341
c4c81601
RK
5342 if (gcse_file)
5343 {
5344 fprintf (gcse_file,
5345 "PRE: redundant insn %d (expression %d) in ",
5346 INSN_UID (insn), indx);
5347 fprintf (gcse_file, "bb %d, reaching reg is %d\n",
0b17ab2f 5348 bb->index, REGNO (expr->reaching_reg));
c4c81601
RK
5349 }
5350 }
5351 }
5352 }
7506f491
DE
5353
5354 return changed;
5355}
5356
5357/* Perform GCSE optimizations using PRE.
5358 This is called by one_pre_gcse_pass after all the dataflow analysis
5359 has been done.
5360
c4c81601
RK
5361 This is based on the original Morel-Renvoise paper Fred Chow's thesis, and
5362 lazy code motion from Knoop, Ruthing and Steffen as described in Advanced
5363 Compiler Design and Implementation.
7506f491 5364
c4c81601
RK
5365 ??? A new pseudo reg is created to hold the reaching expression. The nice
5366 thing about the classical approach is that it would try to use an existing
5367 reg. If the register can't be adequately optimized [i.e. we introduce
5368 reload problems], one could add a pass here to propagate the new register
5369 through the block.
7506f491 5370
c4c81601
RK
5371 ??? We don't handle single sets in PARALLELs because we're [currently] not
5372 able to copy the rest of the parallel when we insert copies to create full
5373 redundancies from partial redundancies. However, there's no reason why we
5374 can't handle PARALLELs in the cases where there are no partial
7506f491
DE
5375 redundancies. */
5376
5377static int
5378pre_gcse ()
5379{
2e653e39
RK
5380 unsigned int i;
5381 int did_insert, changed;
7506f491 5382 struct expr **index_map;
c4c81601 5383 struct expr *expr;
7506f491
DE
5384
5385 /* Compute a mapping from expression number (`bitmap_index') to
5386 hash table entry. */
5387
02280659
ZD
5388 index_map = (struct expr **) xcalloc (expr_hash_table.n_elems, sizeof (struct expr *));
5389 for (i = 0; i < expr_hash_table.size; i++)
5390 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 5391 index_map[expr->bitmap_index] = expr;
7506f491
DE
5392
5393 /* Reset bitmap used to track which insns are redundant. */
a65f3558
JL
5394 pre_redundant_insns = sbitmap_alloc (max_cuid);
5395 sbitmap_zero (pre_redundant_insns);
7506f491
DE
5396
5397 /* Delete the redundant insns first so that
5398 - we know what register to use for the new insns and for the other
5399 ones with reaching expressions
5400 - we know which insns are redundant when we go to create copies */
c4c81601 5401
7506f491
DE
5402 changed = pre_delete ();
5403
a42cd965 5404 did_insert = pre_edge_insert (edge_list, index_map);
c4c81601 5405
7506f491 5406 /* In other places with reaching expressions, copy the expression to the
a42cd965 5407 specially allocated pseudo-reg that reaches the redundant expr. */
7506f491 5408 pre_insert_copies ();
a42cd965
AM
5409 if (did_insert)
5410 {
5411 commit_edge_insertions ();
5412 changed = 1;
5413 }
7506f491 5414
283a2545 5415 free (index_map);
76ac938b 5416 sbitmap_free (pre_redundant_insns);
7506f491
DE
5417 return changed;
5418}
5419
5420/* Top level routine to perform one PRE GCSE pass.
5421
5422 Return non-zero if a change was made. */
5423
5424static int
b5ce41ff 5425one_pre_gcse_pass (pass)
7506f491
DE
5426 int pass;
5427{
5428 int changed = 0;
5429
5430 gcse_subst_count = 0;
5431 gcse_create_count = 0;
5432
02280659 5433 alloc_hash_table (max_cuid, &expr_hash_table, 0);
a42cd965 5434 add_noreturn_fake_exit_edges ();
a13d4ebf
AM
5435 if (flag_gcse_lm)
5436 compute_ld_motion_mems ();
5437
02280659 5438 compute_hash_table (&expr_hash_table);
a13d4ebf 5439 trim_ld_motion_mems ();
7506f491 5440 if (gcse_file)
02280659 5441 dump_hash_table (gcse_file, "Expression", &expr_hash_table);
c4c81601 5442
02280659 5443 if (expr_hash_table.n_elems > 0)
7506f491 5444 {
02280659 5445 alloc_pre_mem (last_basic_block, expr_hash_table.n_elems);
7506f491
DE
5446 compute_pre_data ();
5447 changed |= pre_gcse ();
a42cd965 5448 free_edge_list (edge_list);
7506f491
DE
5449 free_pre_mem ();
5450 }
c4c81601 5451
a13d4ebf 5452 free_ldst_mems ();
a42cd965 5453 remove_fake_edges ();
02280659 5454 free_hash_table (&expr_hash_table);
7506f491
DE
5455
5456 if (gcse_file)
5457 {
c4c81601
RK
5458 fprintf (gcse_file, "\nPRE GCSE of %s, pass %d: %d bytes needed, ",
5459 current_function_name, pass, bytes_used);
5460 fprintf (gcse_file, "%d substs, %d insns created\n",
5461 gcse_subst_count, gcse_create_count);
7506f491
DE
5462 }
5463
5464 return changed;
5465}
aeb2f500
JW
5466\f
5467/* If X contains any LABEL_REF's, add REG_LABEL notes for them to INSN.
5b1ef594
JDA
5468 If notes are added to an insn which references a CODE_LABEL, the
5469 LABEL_NUSES count is incremented. We have to add REG_LABEL notes,
5470 because the following loop optimization pass requires them. */
aeb2f500
JW
5471
5472/* ??? This is very similar to the loop.c add_label_notes function. We
5473 could probably share code here. */
5474
5475/* ??? If there was a jump optimization pass after gcse and before loop,
5476 then we would not need to do this here, because jump would add the
5477 necessary REG_LABEL notes. */
5478
5479static void
5480add_label_notes (x, insn)
5481 rtx x;
5482 rtx insn;
5483{
5484 enum rtx_code code = GET_CODE (x);
5485 int i, j;
6f7d635c 5486 const char *fmt;
aeb2f500
JW
5487
5488 if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
5489 {
6b3603c2 5490 /* This code used to ignore labels that referred to dispatch tables to
ac7c5af5 5491 avoid flow generating (slighly) worse code.
6b3603c2 5492
ac7c5af5
JL
5493 We no longer ignore such label references (see LABEL_REF handling in
5494 mark_jump_label for additional information). */
c4c81601 5495
6b8c9327 5496 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, XEXP (x, 0),
6b3603c2 5497 REG_NOTES (insn));
5b1ef594 5498 if (LABEL_P (XEXP (x, 0)))
589005ff 5499 LABEL_NUSES (XEXP (x, 0))++;
aeb2f500
JW
5500 return;
5501 }
5502
c4c81601 5503 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
aeb2f500
JW
5504 {
5505 if (fmt[i] == 'e')
5506 add_label_notes (XEXP (x, i), insn);
5507 else if (fmt[i] == 'E')
5508 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5509 add_label_notes (XVECEXP (x, i, j), insn);
5510 }
5511}
a65f3558
JL
5512
5513/* Compute transparent outgoing information for each block.
5514
5515 An expression is transparent to an edge unless it is killed by
5516 the edge itself. This can only happen with abnormal control flow,
5517 when the edge is traversed through a call. This happens with
5518 non-local labels and exceptions.
5519
5520 This would not be necessary if we split the edge. While this is
5521 normally impossible for abnormal critical edges, with some effort
5522 it should be possible with exception handling, since we still have
5523 control over which handler should be invoked. But due to increased
5524 EH table sizes, this may not be worthwhile. */
5525
5526static void
5527compute_transpout ()
5528{
e0082a72 5529 basic_block bb;
2e653e39 5530 unsigned int i;
c4c81601 5531 struct expr *expr;
a65f3558 5532
d55bc081 5533 sbitmap_vector_ones (transpout, last_basic_block);
a65f3558 5534
e0082a72 5535 FOR_EACH_BB (bb)
a65f3558 5536 {
a65f3558
JL
5537 /* Note that flow inserted a nop a the end of basic blocks that
5538 end in call instructions for reasons other than abnormal
5539 control flow. */
e0082a72 5540 if (GET_CODE (bb->end) != CALL_INSN)
a65f3558
JL
5541 continue;
5542
02280659
ZD
5543 for (i = 0; i < expr_hash_table.size; i++)
5544 for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash)
c4c81601
RK
5545 if (GET_CODE (expr->expr) == MEM)
5546 {
5547 if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF
5548 && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0)))
5549 continue;
589005ff 5550
c4c81601
RK
5551 /* ??? Optimally, we would use interprocedural alias
5552 analysis to determine if this mem is actually killed
5553 by this call. */
e0082a72 5554 RESET_BIT (transpout[bb->index], expr->bitmap_index);
c4c81601 5555 }
a65f3558
JL
5556 }
5557}
dfdb644f
JL
5558
5559/* Removal of useless null pointer checks */
5560
dfdb644f 5561/* Called via note_stores. X is set by SETTER. If X is a register we must
0511851c
MM
5562 invalidate nonnull_local and set nonnull_killed. DATA is really a
5563 `null_pointer_info *'.
dfdb644f
JL
5564
5565 We ignore hard registers. */
c4c81601 5566
dfdb644f 5567static void
84832317 5568invalidate_nonnull_info (x, setter, data)
dfdb644f
JL
5569 rtx x;
5570 rtx setter ATTRIBUTE_UNUSED;
0511851c 5571 void *data;
dfdb644f 5572{
770ae6cc
RK
5573 unsigned int regno;
5574 struct null_pointer_info *npi = (struct null_pointer_info *) data;
c4c81601 5575
dfdb644f
JL
5576 while (GET_CODE (x) == SUBREG)
5577 x = SUBREG_REG (x);
5578
5579 /* Ignore anything that is not a register or is a hard register. */
5580 if (GET_CODE (x) != REG
0511851c
MM
5581 || REGNO (x) < npi->min_reg
5582 || REGNO (x) >= npi->max_reg)
dfdb644f
JL
5583 return;
5584
0511851c 5585 regno = REGNO (x) - npi->min_reg;
dfdb644f 5586
e0082a72
ZD
5587 RESET_BIT (npi->nonnull_local[npi->current_block->index], regno);
5588 SET_BIT (npi->nonnull_killed[npi->current_block->index], regno);
dfdb644f
JL
5589}
5590
0511851c
MM
5591/* Do null-pointer check elimination for the registers indicated in
5592 NPI. NONNULL_AVIN and NONNULL_AVOUT are pre-allocated sbitmaps;
5593 they are not our responsibility to free. */
dfdb644f 5594
99a15921 5595static int
9cd56be1 5596delete_null_pointer_checks_1 (block_reg, nonnull_avin,
8e184d9c 5597 nonnull_avout, npi)
770ae6cc 5598 unsigned int *block_reg;
0511851c
MM
5599 sbitmap *nonnull_avin;
5600 sbitmap *nonnull_avout;
5601 struct null_pointer_info *npi;
dfdb644f 5602{
e0082a72 5603 basic_block bb, current_block;
0511851c
MM
5604 sbitmap *nonnull_local = npi->nonnull_local;
5605 sbitmap *nonnull_killed = npi->nonnull_killed;
99a15921 5606 int something_changed = 0;
589005ff 5607
dfdb644f
JL
5608 /* Compute local properties, nonnull and killed. A register will have
5609 the nonnull property if at the end of the current block its value is
5610 known to be nonnull. The killed property indicates that somewhere in
5611 the block any information we had about the register is killed.
5612
5613 Note that a register can have both properties in a single block. That
5614 indicates that it's killed, then later in the block a new value is
5615 computed. */
d55bc081
ZD
5616 sbitmap_vector_zero (nonnull_local, last_basic_block);
5617 sbitmap_vector_zero (nonnull_killed, last_basic_block);
c4c81601 5618
e0082a72 5619 FOR_EACH_BB (current_block)
dfdb644f
JL
5620 {
5621 rtx insn, stop_insn;
5622
0511851c
MM
5623 /* Set the current block for invalidate_nonnull_info. */
5624 npi->current_block = current_block;
5625
dfdb644f
JL
5626 /* Scan each insn in the basic block looking for memory references and
5627 register sets. */
e0082a72
ZD
5628 stop_insn = NEXT_INSN (current_block->end);
5629 for (insn = current_block->head;
dfdb644f
JL
5630 insn != stop_insn;
5631 insn = NEXT_INSN (insn))
5632 {
5633 rtx set;
0511851c 5634 rtx reg;
dfdb644f
JL
5635
5636 /* Ignore anything that is not a normal insn. */
2c3c49de 5637 if (! INSN_P (insn))
dfdb644f
JL
5638 continue;
5639
5640 /* Basically ignore anything that is not a simple SET. We do have
5641 to make sure to invalidate nonnull_local and set nonnull_killed
5642 for such insns though. */
5643 set = single_set (insn);
5644 if (!set)
5645 {
0511851c 5646 note_stores (PATTERN (insn), invalidate_nonnull_info, npi);
dfdb644f
JL
5647 continue;
5648 }
5649
f63d1bf7 5650 /* See if we've got a usable memory load. We handle it first
dfdb644f
JL
5651 in case it uses its address register as a dest (which kills
5652 the nonnull property). */
5653 if (GET_CODE (SET_SRC (set)) == MEM
0511851c
MM
5654 && GET_CODE ((reg = XEXP (SET_SRC (set), 0))) == REG
5655 && REGNO (reg) >= npi->min_reg
5656 && REGNO (reg) < npi->max_reg)
e0082a72 5657 SET_BIT (nonnull_local[current_block->index],
0511851c 5658 REGNO (reg) - npi->min_reg);
dfdb644f
JL
5659
5660 /* Now invalidate stuff clobbered by this insn. */
0511851c 5661 note_stores (PATTERN (insn), invalidate_nonnull_info, npi);
dfdb644f
JL
5662
5663 /* And handle stores, we do these last since any sets in INSN can
5664 not kill the nonnull property if it is derived from a MEM
5665 appearing in a SET_DEST. */
5666 if (GET_CODE (SET_DEST (set)) == MEM
0511851c
MM
5667 && GET_CODE ((reg = XEXP (SET_DEST (set), 0))) == REG
5668 && REGNO (reg) >= npi->min_reg
5669 && REGNO (reg) < npi->max_reg)
e0082a72 5670 SET_BIT (nonnull_local[current_block->index],
0511851c 5671 REGNO (reg) - npi->min_reg);
dfdb644f
JL
5672 }
5673 }
5674
5675 /* Now compute global properties based on the local properties. This
5676 is a classic global availablity algorithm. */
ce724250
JL
5677 compute_available (nonnull_local, nonnull_killed,
5678 nonnull_avout, nonnull_avin);
dfdb644f
JL
5679
5680 /* Now look at each bb and see if it ends with a compare of a value
5681 against zero. */
e0082a72 5682 FOR_EACH_BB (bb)
dfdb644f 5683 {
e0082a72 5684 rtx last_insn = bb->end;
0511851c 5685 rtx condition, earliest;
dfdb644f
JL
5686 int compare_and_branch;
5687
0511851c
MM
5688 /* Since MIN_REG is always at least FIRST_PSEUDO_REGISTER, and
5689 since BLOCK_REG[BB] is zero if this block did not end with a
5690 comparison against zero, this condition works. */
e0082a72
ZD
5691 if (block_reg[bb->index] < npi->min_reg
5692 || block_reg[bb->index] >= npi->max_reg)
dfdb644f
JL
5693 continue;
5694
5695 /* LAST_INSN is a conditional jump. Get its condition. */
5696 condition = get_condition (last_insn, &earliest);
5697
40d7a3fe
NB
5698 /* If we can't determine the condition then skip. */
5699 if (! condition)
5700 continue;
5701
dfdb644f 5702 /* Is the register known to have a nonzero value? */
e0082a72 5703 if (!TEST_BIT (nonnull_avout[bb->index], block_reg[bb->index] - npi->min_reg))
dfdb644f
JL
5704 continue;
5705
5706 /* Try to compute whether the compare/branch at the loop end is one or
5707 two instructions. */
5708 if (earliest == last_insn)
5709 compare_and_branch = 1;
5710 else if (earliest == prev_nonnote_insn (last_insn))
5711 compare_and_branch = 2;
5712 else
5713 continue;
5714
5715 /* We know the register in this comparison is nonnull at exit from
5716 this block. We can optimize this comparison. */
5717 if (GET_CODE (condition) == NE)
5718 {
5719 rtx new_jump;
5720
38c1593d
JH
5721 new_jump = emit_jump_insn_after (gen_jump (JUMP_LABEL (last_insn)),
5722 last_insn);
dfdb644f
JL
5723 JUMP_LABEL (new_jump) = JUMP_LABEL (last_insn);
5724 LABEL_NUSES (JUMP_LABEL (new_jump))++;
5725 emit_barrier_after (new_jump);
5726 }
8e184d9c 5727
99a15921 5728 something_changed = 1;
9cd56be1 5729 delete_insn (last_insn);
dfdb644f 5730 if (compare_and_branch == 2)
589005ff 5731 delete_insn (earliest);
e0082a72 5732 purge_dead_edges (bb);
0511851c
MM
5733
5734 /* Don't check this block again. (Note that BLOCK_END is
589005ff 5735 invalid here; we deleted the last instruction in the
0511851c 5736 block.) */
e0082a72 5737 block_reg[bb->index] = 0;
0511851c 5738 }
99a15921
JL
5739
5740 return something_changed;
0511851c
MM
5741}
5742
5743/* Find EQ/NE comparisons against zero which can be (indirectly) evaluated
5744 at compile time.
5745
5746 This is conceptually similar to global constant/copy propagation and
5747 classic global CSE (it even uses the same dataflow equations as cprop).
5748
5749 If a register is used as memory address with the form (mem (reg)), then we
5750 know that REG can not be zero at that point in the program. Any instruction
5751 which sets REG "kills" this property.
5752
5753 So, if every path leading to a conditional branch has an available memory
5754 reference of that form, then we know the register can not have the value
589005ff 5755 zero at the conditional branch.
0511851c
MM
5756
5757 So we merely need to compute the local properies and propagate that data
5758 around the cfg, then optimize where possible.
5759
5760 We run this pass two times. Once before CSE, then again after CSE. This
5761 has proven to be the most profitable approach. It is rare for new
5762 optimization opportunities of this nature to appear after the first CSE
5763 pass.
5764
5765 This could probably be integrated with global cprop with a little work. */
5766
99a15921 5767int
0511851c 5768delete_null_pointer_checks (f)
2e653e39 5769 rtx f ATTRIBUTE_UNUSED;
0511851c 5770{
0511851c 5771 sbitmap *nonnull_avin, *nonnull_avout;
770ae6cc 5772 unsigned int *block_reg;
e0082a72 5773 basic_block bb;
0511851c
MM
5774 int reg;
5775 int regs_per_pass;
5776 int max_reg;
5777 struct null_pointer_info npi;
99a15921 5778 int something_changed = 0;
0511851c 5779
0511851c 5780 /* If we have only a single block, then there's nothing to do. */
0b17ab2f 5781 if (n_basic_blocks <= 1)
99a15921 5782 return 0;
0511851c
MM
5783
5784 /* Trying to perform global optimizations on flow graphs which have
5785 a high connectivity will take a long time and is unlikely to be
5786 particularly useful.
5787
43e72072 5788 In normal circumstances a cfg should have about twice as many edges
0511851c
MM
5789 as blocks. But we do not want to punish small functions which have
5790 a couple switch statements. So we require a relatively large number
5791 of basic blocks and the ratio of edges to blocks to be high. */
0b17ab2f 5792 if (n_basic_blocks > 1000 && n_edges / n_basic_blocks >= 20)
99a15921 5793 return 0;
0511851c 5794
0511851c
MM
5795 /* We need four bitmaps, each with a bit for each register in each
5796 basic block. */
5797 max_reg = max_reg_num ();
d55bc081 5798 regs_per_pass = get_bitmap_width (4, last_basic_block, max_reg);
0511851c
MM
5799
5800 /* Allocate bitmaps to hold local and global properties. */
d55bc081
ZD
5801 npi.nonnull_local = sbitmap_vector_alloc (last_basic_block, regs_per_pass);
5802 npi.nonnull_killed = sbitmap_vector_alloc (last_basic_block, regs_per_pass);
5803 nonnull_avin = sbitmap_vector_alloc (last_basic_block, regs_per_pass);
5804 nonnull_avout = sbitmap_vector_alloc (last_basic_block, regs_per_pass);
0511851c
MM
5805
5806 /* Go through the basic blocks, seeing whether or not each block
5807 ends with a conditional branch whose condition is a comparison
5808 against zero. Record the register compared in BLOCK_REG. */
d55bc081 5809 block_reg = (unsigned int *) xcalloc (last_basic_block, sizeof (int));
e0082a72 5810 FOR_EACH_BB (bb)
0511851c 5811 {
e0082a72 5812 rtx last_insn = bb->end;
0511851c
MM
5813 rtx condition, earliest, reg;
5814
5815 /* We only want conditional branches. */
5816 if (GET_CODE (last_insn) != JUMP_INSN
7f1c097d
JH
5817 || !any_condjump_p (last_insn)
5818 || !onlyjump_p (last_insn))
0511851c
MM
5819 continue;
5820
5821 /* LAST_INSN is a conditional jump. Get its condition. */
5822 condition = get_condition (last_insn, &earliest);
5823
4fe9b91c 5824 /* If we were unable to get the condition, or it is not an equality
0511851c
MM
5825 comparison against zero then there's nothing we can do. */
5826 if (!condition
5827 || (GET_CODE (condition) != NE && GET_CODE (condition) != EQ)
5828 || GET_CODE (XEXP (condition, 1)) != CONST_INT
589005ff 5829 || (XEXP (condition, 1)
0511851c
MM
5830 != CONST0_RTX (GET_MODE (XEXP (condition, 0)))))
5831 continue;
5832
5833 /* We must be checking a register against zero. */
5834 reg = XEXP (condition, 0);
5835 if (GET_CODE (reg) != REG)
5836 continue;
5837
e0082a72 5838 block_reg[bb->index] = REGNO (reg);
0511851c
MM
5839 }
5840
5841 /* Go through the algorithm for each block of registers. */
5842 for (reg = FIRST_PSEUDO_REGISTER; reg < max_reg; reg += regs_per_pass)
5843 {
5844 npi.min_reg = reg;
5845 npi.max_reg = MIN (reg + regs_per_pass, max_reg);
99a15921
JL
5846 something_changed |= delete_null_pointer_checks_1 (block_reg,
5847 nonnull_avin,
5848 nonnull_avout,
5849 &npi);
dfdb644f
JL
5850 }
5851
0511851c
MM
5852 /* Free the table of registers compared at the end of every block. */
5853 free (block_reg);
5854
dfdb644f 5855 /* Free bitmaps. */
5a660bff
DB
5856 sbitmap_vector_free (npi.nonnull_local);
5857 sbitmap_vector_free (npi.nonnull_killed);
5858 sbitmap_vector_free (nonnull_avin);
5859 sbitmap_vector_free (nonnull_avout);
99a15921
JL
5860
5861 return something_changed;
dfdb644f 5862}
bb457bd9
JL
5863
5864/* Code Hoisting variables and subroutines. */
5865
5866/* Very busy expressions. */
5867static sbitmap *hoist_vbein;
5868static sbitmap *hoist_vbeout;
5869
5870/* Hoistable expressions. */
5871static sbitmap *hoist_exprs;
5872
5873/* Dominator bitmaps. */
355be0dc 5874dominance_info dominators;
bb457bd9
JL
5875
5876/* ??? We could compute post dominators and run this algorithm in
68e82b83 5877 reverse to perform tail merging, doing so would probably be
bb457bd9
JL
5878 more effective than the tail merging code in jump.c.
5879
5880 It's unclear if tail merging could be run in parallel with
5881 code hoisting. It would be nice. */
5882
5883/* Allocate vars used for code hoisting analysis. */
5884
5885static void
5886alloc_code_hoist_mem (n_blocks, n_exprs)
5887 int n_blocks, n_exprs;
5888{
5889 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5890 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
5891 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
5892
5893 hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs);
5894 hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs);
5895 hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs);
5896 transpout = sbitmap_vector_alloc (n_blocks, n_exprs);
bb457bd9
JL
5897}
5898
5899/* Free vars used for code hoisting analysis. */
5900
5901static void
5902free_code_hoist_mem ()
5903{
5a660bff
DB
5904 sbitmap_vector_free (antloc);
5905 sbitmap_vector_free (transp);
5906 sbitmap_vector_free (comp);
bb457bd9 5907
5a660bff
DB
5908 sbitmap_vector_free (hoist_vbein);
5909 sbitmap_vector_free (hoist_vbeout);
5910 sbitmap_vector_free (hoist_exprs);
5911 sbitmap_vector_free (transpout);
bb457bd9 5912
355be0dc 5913 free_dominance_info (dominators);
bb457bd9
JL
5914}
5915
5916/* Compute the very busy expressions at entry/exit from each block.
5917
5918 An expression is very busy if all paths from a given point
5919 compute the expression. */
5920
5921static void
5922compute_code_hoist_vbeinout ()
5923{
e0082a72
ZD
5924 int changed, passes;
5925 basic_block bb;
bb457bd9 5926
d55bc081
ZD
5927 sbitmap_vector_zero (hoist_vbeout, last_basic_block);
5928 sbitmap_vector_zero (hoist_vbein, last_basic_block);
bb457bd9
JL
5929
5930 passes = 0;
5931 changed = 1;
c4c81601 5932
bb457bd9
JL
5933 while (changed)
5934 {
5935 changed = 0;
c4c81601 5936
bb457bd9
JL
5937 /* We scan the blocks in the reverse order to speed up
5938 the convergence. */
e0082a72 5939 FOR_EACH_BB_REVERSE (bb)
bb457bd9 5940 {
e0082a72
ZD
5941 changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index], antloc[bb->index],
5942 hoist_vbeout[bb->index], transp[bb->index]);
5943 if (bb->next_bb != EXIT_BLOCK_PTR)
5944 sbitmap_intersection_of_succs (hoist_vbeout[bb->index], hoist_vbein, bb->index);
bb457bd9 5945 }
c4c81601 5946
bb457bd9
JL
5947 passes++;
5948 }
5949
5950 if (gcse_file)
5951 fprintf (gcse_file, "hoisting vbeinout computation: %d passes\n", passes);
5952}
5953
5954/* Top level routine to do the dataflow analysis needed by code hoisting. */
5955
5956static void
5957compute_code_hoist_data ()
5958{
02280659 5959 compute_local_properties (transp, comp, antloc, &expr_hash_table);
bb457bd9
JL
5960 compute_transpout ();
5961 compute_code_hoist_vbeinout ();
355be0dc 5962 dominators = calculate_dominance_info (CDI_DOMINATORS);
bb457bd9
JL
5963 if (gcse_file)
5964 fprintf (gcse_file, "\n");
5965}
5966
5967/* Determine if the expression identified by EXPR_INDEX would
5968 reach BB unimpared if it was placed at the end of EXPR_BB.
5969
5970 It's unclear exactly what Muchnick meant by "unimpared". It seems
5971 to me that the expression must either be computed or transparent in
5972 *every* block in the path(s) from EXPR_BB to BB. Any other definition
5973 would allow the expression to be hoisted out of loops, even if
5974 the expression wasn't a loop invariant.
5975
5976 Contrast this to reachability for PRE where an expression is
5977 considered reachable if *any* path reaches instead of *all*
5978 paths. */
5979
5980static int
5981hoist_expr_reaches_here_p (expr_bb, expr_index, bb, visited)
e2d2ed72 5982 basic_block expr_bb;
bb457bd9 5983 int expr_index;
e2d2ed72 5984 basic_block bb;
bb457bd9
JL
5985 char *visited;
5986{
5987 edge pred;
283a2545 5988 int visited_allocated_locally = 0;
589005ff 5989
bb457bd9
JL
5990
5991 if (visited == NULL)
5992 {
8e42ace1 5993 visited_allocated_locally = 1;
d55bc081 5994 visited = xcalloc (last_basic_block, 1);
bb457bd9
JL
5995 }
5996
e2d2ed72 5997 for (pred = bb->pred; pred != NULL; pred = pred->pred_next)
bb457bd9 5998 {
e2d2ed72 5999 basic_block pred_bb = pred->src;
bb457bd9
JL
6000
6001 if (pred->src == ENTRY_BLOCK_PTR)
6002 break;
f305679f
JH
6003 else if (pred_bb == expr_bb)
6004 continue;
0b17ab2f 6005 else if (visited[pred_bb->index])
bb457bd9 6006 continue;
c4c81601 6007
bb457bd9 6008 /* Does this predecessor generate this expression? */
0b17ab2f 6009 else if (TEST_BIT (comp[pred_bb->index], expr_index))
bb457bd9 6010 break;
0b17ab2f 6011 else if (! TEST_BIT (transp[pred_bb->index], expr_index))
bb457bd9 6012 break;
c4c81601 6013
bb457bd9
JL
6014 /* Not killed. */
6015 else
6016 {
0b17ab2f 6017 visited[pred_bb->index] = 1;
bb457bd9
JL
6018 if (! hoist_expr_reaches_here_p (expr_bb, expr_index,
6019 pred_bb, visited))
6020 break;
6021 }
6022 }
589005ff 6023 if (visited_allocated_locally)
283a2545 6024 free (visited);
c4c81601 6025
bb457bd9
JL
6026 return (pred == NULL);
6027}
6028\f
6029/* Actually perform code hoisting. */
c4c81601 6030
bb457bd9
JL
6031static void
6032hoist_code ()
6033{
e0082a72 6034 basic_block bb, dominated;
c635a1ec
DB
6035 basic_block *domby;
6036 unsigned int domby_len;
6037 unsigned int i,j;
bb457bd9 6038 struct expr **index_map;
c4c81601 6039 struct expr *expr;
bb457bd9 6040
d55bc081 6041 sbitmap_vector_zero (hoist_exprs, last_basic_block);
bb457bd9
JL
6042
6043 /* Compute a mapping from expression number (`bitmap_index') to
6044 hash table entry. */
6045
02280659
ZD
6046 index_map = (struct expr **) xcalloc (expr_hash_table.n_elems, sizeof (struct expr *));
6047 for (i = 0; i < expr_hash_table.size; i++)
6048 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 6049 index_map[expr->bitmap_index] = expr;
bb457bd9
JL
6050
6051 /* Walk over each basic block looking for potentially hoistable
6052 expressions, nothing gets hoisted from the entry block. */
e0082a72 6053 FOR_EACH_BB (bb)
bb457bd9
JL
6054 {
6055 int found = 0;
6056 int insn_inserted_p;
6057
c635a1ec 6058 domby_len = get_dominated_by (dominators, bb, &domby);
bb457bd9
JL
6059 /* Examine each expression that is very busy at the exit of this
6060 block. These are the potentially hoistable expressions. */
e0082a72 6061 for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++)
bb457bd9
JL
6062 {
6063 int hoistable = 0;
c4c81601 6064
c635a1ec
DB
6065 if (TEST_BIT (hoist_vbeout[bb->index], i)
6066 && TEST_BIT (transpout[bb->index], i))
bb457bd9
JL
6067 {
6068 /* We've found a potentially hoistable expression, now
6069 we look at every block BB dominates to see if it
6070 computes the expression. */
c635a1ec 6071 for (j = 0; j < domby_len; j++)
bb457bd9 6072 {
c635a1ec 6073 dominated = domby[j];
bb457bd9 6074 /* Ignore self dominance. */
c635a1ec 6075 if (bb == dominated)
bb457bd9 6076 continue;
bb457bd9
JL
6077 /* We've found a dominated block, now see if it computes
6078 the busy expression and whether or not moving that
6079 expression to the "beginning" of that block is safe. */
e0082a72 6080 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
6081 continue;
6082
6083 /* Note if the expression would reach the dominated block
589005ff 6084 unimpared if it was placed at the end of BB.
bb457bd9
JL
6085
6086 Keep track of how many times this expression is hoistable
6087 from a dominated block into BB. */
e0082a72 6088 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
6089 hoistable++;
6090 }
6091
ff7cc307 6092 /* If we found more than one hoistable occurrence of this
bb457bd9
JL
6093 expression, then note it in the bitmap of expressions to
6094 hoist. It makes no sense to hoist things which are computed
6095 in only one BB, and doing so tends to pessimize register
6096 allocation. One could increase this value to try harder
6097 to avoid any possible code expansion due to register
6098 allocation issues; however experiments have shown that
6099 the vast majority of hoistable expressions are only movable
6100 from two successors, so raising this threshhold is likely
6101 to nullify any benefit we get from code hoisting. */
6102 if (hoistable > 1)
6103 {
e0082a72 6104 SET_BIT (hoist_exprs[bb->index], i);
bb457bd9
JL
6105 found = 1;
6106 }
6107 }
6108 }
bb457bd9
JL
6109 /* If we found nothing to hoist, then quit now. */
6110 if (! found)
c635a1ec
DB
6111 {
6112 free (domby);
bb457bd9 6113 continue;
c635a1ec 6114 }
bb457bd9
JL
6115
6116 /* Loop over all the hoistable expressions. */
e0082a72 6117 for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++)
bb457bd9
JL
6118 {
6119 /* We want to insert the expression into BB only once, so
6120 note when we've inserted it. */
6121 insn_inserted_p = 0;
6122
6123 /* These tests should be the same as the tests above. */
e0082a72 6124 if (TEST_BIT (hoist_vbeout[bb->index], i))
bb457bd9
JL
6125 {
6126 /* We've found a potentially hoistable expression, now
6127 we look at every block BB dominates to see if it
6128 computes the expression. */
c635a1ec 6129 for (j = 0; j < domby_len; j++)
bb457bd9 6130 {
c635a1ec 6131 dominated = domby[j];
bb457bd9 6132 /* Ignore self dominance. */
c635a1ec 6133 if (bb == dominated)
bb457bd9
JL
6134 continue;
6135
6136 /* We've found a dominated block, now see if it computes
6137 the busy expression and whether or not moving that
6138 expression to the "beginning" of that block is safe. */
e0082a72 6139 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
6140 continue;
6141
6142 /* The expression is computed in the dominated block and
6143 it would be safe to compute it at the start of the
6144 dominated block. Now we have to determine if the
ff7cc307 6145 expression would reach the dominated block if it was
bb457bd9 6146 placed at the end of BB. */
e0082a72 6147 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
6148 {
6149 struct expr *expr = index_map[i];
6150 struct occr *occr = expr->antic_occr;
6151 rtx insn;
6152 rtx set;
6153
ff7cc307 6154 /* Find the right occurrence of this expression. */
e0082a72 6155 while (BLOCK_FOR_INSN (occr->insn) != dominated && occr)
bb457bd9
JL
6156 occr = occr->next;
6157
6158 /* Should never happen. */
6159 if (!occr)
6160 abort ();
6161
6162 insn = occr->insn;
589005ff 6163
bb457bd9
JL
6164 set = single_set (insn);
6165 if (! set)
6166 abort ();
6167
6168 /* Create a pseudo-reg to store the result of reaching
6169 expressions into. Get the mode for the new pseudo
6170 from the mode of the original destination pseudo. */
6171 if (expr->reaching_reg == NULL)
6172 expr->reaching_reg
6173 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
6174
10d1bb36
JH
6175 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
6176 delete_insn (insn);
6177 occr->deleted_p = 1;
6178 if (!insn_inserted_p)
bb457bd9 6179 {
10d1bb36
JH
6180 insert_insn_end_bb (index_map[i], bb, 0);
6181 insn_inserted_p = 1;
bb457bd9
JL
6182 }
6183 }
6184 }
6185 }
6186 }
c635a1ec 6187 free (domby);
bb457bd9 6188 }
c4c81601 6189
8e42ace1 6190 free (index_map);
bb457bd9
JL
6191}
6192
6193/* Top level routine to perform one code hoisting (aka unification) pass
6194
6195 Return non-zero if a change was made. */
6196
6197static int
6198one_code_hoisting_pass ()
6199{
6200 int changed = 0;
6201
02280659
ZD
6202 alloc_hash_table (max_cuid, &expr_hash_table, 0);
6203 compute_hash_table (&expr_hash_table);
bb457bd9 6204 if (gcse_file)
02280659 6205 dump_hash_table (gcse_file, "Code Hosting Expressions", &expr_hash_table);
c4c81601 6206
02280659 6207 if (expr_hash_table.n_elems > 0)
bb457bd9 6208 {
02280659 6209 alloc_code_hoist_mem (last_basic_block, expr_hash_table.n_elems);
bb457bd9
JL
6210 compute_code_hoist_data ();
6211 hoist_code ();
6212 free_code_hoist_mem ();
6213 }
c4c81601 6214
02280659 6215 free_hash_table (&expr_hash_table);
bb457bd9
JL
6216
6217 return changed;
6218}
a13d4ebf
AM
6219\f
6220/* Here we provide the things required to do store motion towards
6221 the exit. In order for this to be effective, gcse also needed to
6222 be taught how to move a load when it is kill only by a store to itself.
6223
6224 int i;
6225 float a[10];
6226
6227 void foo(float scale)
6228 {
6229 for (i=0; i<10; i++)
6230 a[i] *= scale;
6231 }
6232
6233 'i' is both loaded and stored to in the loop. Normally, gcse cannot move
589005ff
KH
6234 the load out since its live around the loop, and stored at the bottom
6235 of the loop.
a13d4ebf 6236
589005ff 6237 The 'Load Motion' referred to and implemented in this file is
a13d4ebf
AM
6238 an enhancement to gcse which when using edge based lcm, recognizes
6239 this situation and allows gcse to move the load out of the loop.
6240
6241 Once gcse has hoisted the load, store motion can then push this
6242 load towards the exit, and we end up with no loads or stores of 'i'
6243 in the loop. */
6244
ff7cc307 6245/* This will search the ldst list for a matching expression. If it
a13d4ebf
AM
6246 doesn't find one, we create one and initialize it. */
6247
6248static struct ls_expr *
6249ldst_entry (x)
6250 rtx x;
6251{
6252 struct ls_expr * ptr;
6253
6254 for (ptr = first_ls_expr(); ptr != NULL; ptr = next_ls_expr (ptr))
6255 if (expr_equiv_p (ptr->pattern, x))
6256 break;
6257
6258 if (!ptr)
6259 {
6260 ptr = (struct ls_expr *) xmalloc (sizeof (struct ls_expr));
6261
6262 ptr->next = pre_ldst_mems;
6263 ptr->expr = NULL;
6264 ptr->pattern = x;
6265 ptr->loads = NULL_RTX;
6266 ptr->stores = NULL_RTX;
6267 ptr->reaching_reg = NULL_RTX;
6268 ptr->invalid = 0;
6269 ptr->index = 0;
6270 ptr->hash_index = 0;
6271 pre_ldst_mems = ptr;
6272 }
589005ff 6273
a13d4ebf
AM
6274 return ptr;
6275}
6276
6277/* Free up an individual ldst entry. */
6278
589005ff 6279static void
a13d4ebf
AM
6280free_ldst_entry (ptr)
6281 struct ls_expr * ptr;
6282{
aaa4ca30
AJ
6283 free_INSN_LIST_list (& ptr->loads);
6284 free_INSN_LIST_list (& ptr->stores);
a13d4ebf
AM
6285
6286 free (ptr);
6287}
6288
6289/* Free up all memory associated with the ldst list. */
6290
6291static void
6292free_ldst_mems ()
6293{
589005ff 6294 while (pre_ldst_mems)
a13d4ebf
AM
6295 {
6296 struct ls_expr * tmp = pre_ldst_mems;
6297
6298 pre_ldst_mems = pre_ldst_mems->next;
6299
6300 free_ldst_entry (tmp);
6301 }
6302
6303 pre_ldst_mems = NULL;
6304}
6305
6306/* Dump debugging info about the ldst list. */
6307
6308static void
6309print_ldst_list (file)
6310 FILE * file;
6311{
6312 struct ls_expr * ptr;
6313
6314 fprintf (file, "LDST list: \n");
6315
6316 for (ptr = first_ls_expr(); ptr != NULL; ptr = next_ls_expr (ptr))
6317 {
6318 fprintf (file, " Pattern (%3d): ", ptr->index);
6319
6320 print_rtl (file, ptr->pattern);
6321
6322 fprintf (file, "\n Loads : ");
6323
6324 if (ptr->loads)
6325 print_rtl (file, ptr->loads);
6326 else
6327 fprintf (file, "(nil)");
6328
6329 fprintf (file, "\n Stores : ");
6330
6331 if (ptr->stores)
6332 print_rtl (file, ptr->stores);
6333 else
6334 fprintf (file, "(nil)");
6335
6336 fprintf (file, "\n\n");
6337 }
6338
6339 fprintf (file, "\n");
6340}
6341
6342/* Returns 1 if X is in the list of ldst only expressions. */
6343
6344static struct ls_expr *
6345find_rtx_in_ldst (x)
6346 rtx x;
6347{
6348 struct ls_expr * ptr;
589005ff 6349
a13d4ebf
AM
6350 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
6351 if (expr_equiv_p (ptr->pattern, x) && ! ptr->invalid)
6352 return ptr;
6353
6354 return NULL;
6355}
6356
6357/* Assign each element of the list of mems a monotonically increasing value. */
6358
6359static int
6360enumerate_ldsts ()
6361{
6362 struct ls_expr * ptr;
6363 int n = 0;
6364
6365 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
6366 ptr->index = n++;
6367
6368 return n;
6369}
6370
6371/* Return first item in the list. */
6372
6373static inline struct ls_expr *
6374first_ls_expr ()
6375{
6376 return pre_ldst_mems;
6377}
6378
6379/* Return the next item in ther list after the specified one. */
6380
6381static inline struct ls_expr *
6382next_ls_expr (ptr)
6383 struct ls_expr * ptr;
6384{
6385 return ptr->next;
6386}
6387\f
6388/* Load Motion for loads which only kill themselves. */
6389
6390/* Return true if x is a simple MEM operation, with no registers or
6391 side effects. These are the types of loads we consider for the
6392 ld_motion list, otherwise we let the usual aliasing take care of it. */
6393
589005ff 6394static int
a13d4ebf
AM
6395simple_mem (x)
6396 rtx x;
6397{
6398 if (GET_CODE (x) != MEM)
6399 return 0;
589005ff 6400
a13d4ebf
AM
6401 if (MEM_VOLATILE_P (x))
6402 return 0;
589005ff 6403
a13d4ebf
AM
6404 if (GET_MODE (x) == BLKmode)
6405 return 0;
aaa4ca30
AJ
6406
6407 if (!rtx_varies_p (XEXP (x, 0), 0))
a13d4ebf 6408 return 1;
589005ff 6409
a13d4ebf
AM
6410 return 0;
6411}
6412
589005ff
KH
6413/* Make sure there isn't a buried reference in this pattern anywhere.
6414 If there is, invalidate the entry for it since we're not capable
6415 of fixing it up just yet.. We have to be sure we know about ALL
a13d4ebf
AM
6416 loads since the aliasing code will allow all entries in the
6417 ld_motion list to not-alias itself. If we miss a load, we will get
589005ff 6418 the wrong value since gcse might common it and we won't know to
a13d4ebf
AM
6419 fix it up. */
6420
6421static void
6422invalidate_any_buried_refs (x)
6423 rtx x;
6424{
6425 const char * fmt;
8e42ace1 6426 int i, j;
a13d4ebf
AM
6427 struct ls_expr * ptr;
6428
6429 /* Invalidate it in the list. */
6430 if (GET_CODE (x) == MEM && simple_mem (x))
6431 {
6432 ptr = ldst_entry (x);
6433 ptr->invalid = 1;
6434 }
6435
6436 /* Recursively process the insn. */
6437 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 6438
a13d4ebf
AM
6439 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6440 {
6441 if (fmt[i] == 'e')
6442 invalidate_any_buried_refs (XEXP (x, i));
6443 else if (fmt[i] == 'E')
6444 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6445 invalidate_any_buried_refs (XVECEXP (x, i, j));
6446 }
6447}
6448
6449/* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple
6450 being defined as MEM loads and stores to symbols, with no
589005ff 6451 side effects and no registers in the expression. If there are any
f63d1bf7 6452 uses/defs which don't match this criteria, it is invalidated and
a13d4ebf
AM
6453 trimmed out later. */
6454
589005ff 6455static void
a13d4ebf
AM
6456compute_ld_motion_mems ()
6457{
6458 struct ls_expr * ptr;
e0082a72 6459 basic_block bb;
a13d4ebf 6460 rtx insn;
589005ff 6461
a13d4ebf
AM
6462 pre_ldst_mems = NULL;
6463
e0082a72 6464 FOR_EACH_BB (bb)
a13d4ebf 6465 {
e0082a72
ZD
6466 for (insn = bb->head;
6467 insn && insn != NEXT_INSN (bb->end);
a13d4ebf
AM
6468 insn = NEXT_INSN (insn))
6469 {
6470 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
6471 {
6472 if (GET_CODE (PATTERN (insn)) == SET)
6473 {
6474 rtx src = SET_SRC (PATTERN (insn));
6475 rtx dest = SET_DEST (PATTERN (insn));
6476
6477 /* Check for a simple LOAD... */
6478 if (GET_CODE (src) == MEM && simple_mem (src))
6479 {
6480 ptr = ldst_entry (src);
6481 if (GET_CODE (dest) == REG)
6482 ptr->loads = alloc_INSN_LIST (insn, ptr->loads);
6483 else
6484 ptr->invalid = 1;
6485 }
6486 else
6487 {
6488 /* Make sure there isn't a buried load somewhere. */
6489 invalidate_any_buried_refs (src);
6490 }
589005ff 6491
a13d4ebf
AM
6492 /* Check for stores. Don't worry about aliased ones, they
6493 will block any movement we might do later. We only care
6494 about this exact pattern since those are the only
6495 circumstance that we will ignore the aliasing info. */
6496 if (GET_CODE (dest) == MEM && simple_mem (dest))
6497 {
6498 ptr = ldst_entry (dest);
589005ff 6499
f54104df
AO
6500 if (GET_CODE (src) != MEM
6501 && GET_CODE (src) != ASM_OPERANDS)
a13d4ebf
AM
6502 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
6503 else
6504 ptr->invalid = 1;
6505 }
6506 }
6507 else
6508 invalidate_any_buried_refs (PATTERN (insn));
6509 }
6510 }
6511 }
6512}
6513
589005ff 6514/* Remove any references that have been either invalidated or are not in the
a13d4ebf
AM
6515 expression list for pre gcse. */
6516
6517static void
6518trim_ld_motion_mems ()
6519{
6520 struct ls_expr * last = NULL;
6521 struct ls_expr * ptr = first_ls_expr ();
6522
6523 while (ptr != NULL)
6524 {
6525 int del = ptr->invalid;
6526 struct expr * expr = NULL;
589005ff 6527
a13d4ebf 6528 /* Delete if entry has been made invalid. */
589005ff 6529 if (!del)
a13d4ebf
AM
6530 {
6531 unsigned int i;
589005ff 6532
a13d4ebf
AM
6533 del = 1;
6534 /* Delete if we cannot find this mem in the expression list. */
02280659 6535 for (i = 0; i < expr_hash_table.size && del; i++)
a13d4ebf 6536 {
02280659 6537 for (expr = expr_hash_table.table[i];
589005ff 6538 expr != NULL;
a13d4ebf
AM
6539 expr = expr->next_same_hash)
6540 if (expr_equiv_p (expr->expr, ptr->pattern))
6541 {
6542 del = 0;
6543 break;
6544 }
6545 }
6546 }
589005ff 6547
a13d4ebf
AM
6548 if (del)
6549 {
6550 if (last != NULL)
6551 {
6552 last->next = ptr->next;
6553 free_ldst_entry (ptr);
6554 ptr = last->next;
6555 }
6556 else
6557 {
6558 pre_ldst_mems = pre_ldst_mems->next;
6559 free_ldst_entry (ptr);
6560 ptr = pre_ldst_mems;
6561 }
6562 }
6563 else
6564 {
6565 /* Set the expression field if we are keeping it. */
6566 last = ptr;
6567 ptr->expr = expr;
6568 ptr = ptr->next;
6569 }
6570 }
6571
6572 /* Show the world what we've found. */
6573 if (gcse_file && pre_ldst_mems != NULL)
6574 print_ldst_list (gcse_file);
6575}
6576
6577/* This routine will take an expression which we are replacing with
6578 a reaching register, and update any stores that are needed if
6579 that expression is in the ld_motion list. Stores are updated by
6580 copying their SRC to the reaching register, and then storeing
6581 the reaching register into the store location. These keeps the
6582 correct value in the reaching register for the loads. */
6583
6584static void
6585update_ld_motion_stores (expr)
6586 struct expr * expr;
6587{
6588 struct ls_expr * mem_ptr;
6589
6590 if ((mem_ptr = find_rtx_in_ldst (expr->expr)))
6591 {
589005ff
KH
6592 /* We can try to find just the REACHED stores, but is shouldn't
6593 matter to set the reaching reg everywhere... some might be
a13d4ebf
AM
6594 dead and should be eliminated later. */
6595
6596 /* We replace SET mem = expr with
6597 SET reg = expr
589005ff 6598 SET mem = reg , where reg is the
a13d4ebf
AM
6599 reaching reg used in the load. */
6600 rtx list = mem_ptr->stores;
589005ff 6601
a13d4ebf
AM
6602 for ( ; list != NULL_RTX; list = XEXP (list, 1))
6603 {
6604 rtx insn = XEXP (list, 0);
6605 rtx pat = PATTERN (insn);
6606 rtx src = SET_SRC (pat);
6607 rtx reg = expr->reaching_reg;
c57718d3 6608 rtx copy, new;
a13d4ebf
AM
6609
6610 /* If we've already copied it, continue. */
6611 if (expr->reaching_reg == src)
6612 continue;
589005ff 6613
a13d4ebf
AM
6614 if (gcse_file)
6615 {
6616 fprintf (gcse_file, "PRE: store updated with reaching reg ");
6617 print_rtl (gcse_file, expr->reaching_reg);
6618 fprintf (gcse_file, ":\n ");
6619 print_inline_rtx (gcse_file, insn, 8);
6620 fprintf (gcse_file, "\n");
6621 }
589005ff 6622
a13d4ebf 6623 copy = gen_move_insn ( reg, SET_SRC (pat));
c57718d3
RK
6624 new = emit_insn_before (copy, insn);
6625 record_one_set (REGNO (reg), new);
a13d4ebf
AM
6626 SET_SRC (pat) = reg;
6627
6628 /* un-recognize this pattern since it's probably different now. */
6629 INSN_CODE (insn) = -1;
6630 gcse_create_count++;
6631 }
6632 }
6633}
6634\f
6635/* Store motion code. */
6636
589005ff 6637/* This is used to communicate the target bitvector we want to use in the
aaa4ca30
AJ
6638 reg_set_info routine when called via the note_stores mechanism. */
6639static sbitmap * regvec;
6640
a13d4ebf
AM
6641/* Used in computing the reverse edge graph bit vectors. */
6642static sbitmap * st_antloc;
6643
6644/* Global holding the number of store expressions we are dealing with. */
6645static int num_stores;
6646
aaa4ca30 6647/* Checks to set if we need to mark a register set. Called from note_stores. */
a13d4ebf 6648
aaa4ca30
AJ
6649static void
6650reg_set_info (dest, setter, data)
6651 rtx dest, setter ATTRIBUTE_UNUSED;
6652 void * data ATTRIBUTE_UNUSED;
a13d4ebf 6653{
aaa4ca30
AJ
6654 if (GET_CODE (dest) == SUBREG)
6655 dest = SUBREG_REG (dest);
adfcce61 6656
aaa4ca30
AJ
6657 if (GET_CODE (dest) == REG)
6658 SET_BIT (*regvec, REGNO (dest));
a13d4ebf
AM
6659}
6660
589005ff 6661/* Return non-zero if the register operands of expression X are killed
aaa4ca30 6662 anywhere in basic block BB. */
a13d4ebf
AM
6663
6664static int
aaa4ca30 6665store_ops_ok (x, bb)
a13d4ebf 6666 rtx x;
e2d2ed72 6667 basic_block bb;
a13d4ebf
AM
6668{
6669 int i;
6670 enum rtx_code code;
6671 const char * fmt;
6672
6673 /* Repeat is used to turn tail-recursion into iteration. */
6674 repeat:
6675
6676 if (x == 0)
6677 return 1;
6678
6679 code = GET_CODE (x);
6680 switch (code)
6681 {
6682 case REG:
aaa4ca30
AJ
6683 /* If a reg has changed after us in this
6684 block, the operand has been killed. */
0b17ab2f 6685 return TEST_BIT (reg_set_in_block[bb->index], REGNO (x));
a13d4ebf
AM
6686
6687 case MEM:
6688 x = XEXP (x, 0);
6689 goto repeat;
6690
6691 case PRE_DEC:
6692 case PRE_INC:
6693 case POST_DEC:
6694 case POST_INC:
6695 return 0;
6696
6697 case PC:
6698 case CC0: /*FIXME*/
6699 case CONST:
6700 case CONST_INT:
6701 case CONST_DOUBLE:
69ef87e2 6702 case CONST_VECTOR:
a13d4ebf
AM
6703 case SYMBOL_REF:
6704 case LABEL_REF:
6705 case ADDR_VEC:
6706 case ADDR_DIFF_VEC:
6707 return 1;
6708
6709 default:
6710 break;
6711 }
6712
6713 i = GET_RTX_LENGTH (code) - 1;
6714 fmt = GET_RTX_FORMAT (code);
589005ff 6715
a13d4ebf
AM
6716 for (; i >= 0; i--)
6717 {
6718 if (fmt[i] == 'e')
6719 {
6720 rtx tem = XEXP (x, i);
6721
6722 /* If we are about to do the last recursive call
6723 needed at this level, change it into iteration.
6724 This function is called enough to be worth it. */
6725 if (i == 0)
6726 {
6727 x = tem;
6728 goto repeat;
6729 }
589005ff 6730
aaa4ca30 6731 if (! store_ops_ok (tem, bb))
a13d4ebf
AM
6732 return 0;
6733 }
6734 else if (fmt[i] == 'E')
6735 {
6736 int j;
589005ff 6737
a13d4ebf
AM
6738 for (j = 0; j < XVECLEN (x, i); j++)
6739 {
aaa4ca30 6740 if (! store_ops_ok (XVECEXP (x, i, j), bb))
a13d4ebf
AM
6741 return 0;
6742 }
6743 }
6744 }
6745
6746 return 1;
6747}
6748
aaa4ca30 6749/* Determine whether insn is MEM store pattern that we will consider moving. */
a13d4ebf
AM
6750
6751static void
6752find_moveable_store (insn)
6753 rtx insn;
6754{
6755 struct ls_expr * ptr;
6756 rtx dest = PATTERN (insn);
6757
f54104df
AO
6758 if (GET_CODE (dest) != SET
6759 || GET_CODE (SET_SRC (dest)) == ASM_OPERANDS)
a13d4ebf
AM
6760 return;
6761
6762 dest = SET_DEST (dest);
589005ff 6763
a13d4ebf
AM
6764 if (GET_CODE (dest) != MEM || MEM_VOLATILE_P (dest)
6765 || GET_MODE (dest) == BLKmode)
aaa4ca30
AJ
6766 return;
6767
6768 if (GET_CODE (XEXP (dest, 0)) != SYMBOL_REF)
a13d4ebf 6769 return;
aaa4ca30
AJ
6770
6771 if (rtx_varies_p (XEXP (dest, 0), 0))
a13d4ebf 6772 return;
aaa4ca30 6773
a13d4ebf
AM
6774 ptr = ldst_entry (dest);
6775 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
6776}
6777
aaa4ca30
AJ
6778/* Perform store motion. Much like gcse, except we move expressions the
6779 other way by looking at the flowgraph in reverse. */
a13d4ebf
AM
6780
6781static int
6782compute_store_table ()
6783{
e0082a72
ZD
6784 int ret;
6785 basic_block bb;
aaa4ca30 6786 unsigned regno;
a13d4ebf 6787 rtx insn, pat;
aaa4ca30 6788
a13d4ebf
AM
6789 max_gcse_regno = max_reg_num ();
6790
d55bc081 6791 reg_set_in_block = (sbitmap *) sbitmap_vector_alloc (last_basic_block,
aaa4ca30 6792 max_gcse_regno);
d55bc081 6793 sbitmap_vector_zero (reg_set_in_block, last_basic_block);
a13d4ebf 6794 pre_ldst_mems = 0;
aaa4ca30 6795
a13d4ebf 6796 /* Find all the stores we care about. */
e0082a72 6797 FOR_EACH_BB (bb)
a13d4ebf 6798 {
e0082a72
ZD
6799 regvec = & (reg_set_in_block[bb->index]);
6800 for (insn = bb->end;
6801 insn && insn != PREV_INSN (bb->end);
a13d4ebf
AM
6802 insn = PREV_INSN (insn))
6803 {
19652adf
ZW
6804 /* Ignore anything that is not a normal insn. */
6805 if (! INSN_P (insn))
a13d4ebf
AM
6806 continue;
6807
aaa4ca30
AJ
6808 if (GET_CODE (insn) == CALL_INSN)
6809 {
19652adf 6810 bool clobbers_all = false;
589005ff 6811#ifdef NON_SAVING_SETJMP
19652adf
ZW
6812 if (NON_SAVING_SETJMP
6813 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
6814 clobbers_all = true;
6815#endif
6816
aaa4ca30 6817 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
19652adf
ZW
6818 if (clobbers_all
6819 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
e0082a72 6820 SET_BIT (reg_set_in_block[bb->index], regno);
aaa4ca30 6821 }
589005ff 6822
a13d4ebf 6823 pat = PATTERN (insn);
aaa4ca30 6824 note_stores (pat, reg_set_info, NULL);
589005ff 6825
a13d4ebf
AM
6826 /* Now that we've marked regs, look for stores. */
6827 if (GET_CODE (pat) == SET)
6828 find_moveable_store (insn);
6829 }
6830 }
6831
6832 ret = enumerate_ldsts ();
589005ff 6833
a13d4ebf
AM
6834 if (gcse_file)
6835 {
6836 fprintf (gcse_file, "Store Motion Expressions.\n");
6837 print_ldst_list (gcse_file);
6838 }
589005ff 6839
a13d4ebf
AM
6840 return ret;
6841}
6842
aaa4ca30 6843/* Check to see if the load X is aliased with STORE_PATTERN. */
a13d4ebf
AM
6844
6845static int
6846load_kills_store (x, store_pattern)
6847 rtx x, store_pattern;
6848{
6849 if (true_dependence (x, GET_MODE (x), store_pattern, rtx_addr_varies_p))
6850 return 1;
6851 return 0;
6852}
6853
589005ff 6854/* Go through the entire insn X, looking for any loads which might alias
aaa4ca30 6855 STORE_PATTERN. Return 1 if found. */
a13d4ebf
AM
6856
6857static int
6858find_loads (x, store_pattern)
6859 rtx x, store_pattern;
6860{
6861 const char * fmt;
8e42ace1 6862 int i, j;
a13d4ebf
AM
6863 int ret = 0;
6864
24a28584
JH
6865 if (!x)
6866 return 0;
6867
589005ff 6868 if (GET_CODE (x) == SET)
a13d4ebf
AM
6869 x = SET_SRC (x);
6870
6871 if (GET_CODE (x) == MEM)
6872 {
6873 if (load_kills_store (x, store_pattern))
6874 return 1;
6875 }
6876
6877 /* Recursively process the insn. */
6878 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 6879
a13d4ebf
AM
6880 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0 && !ret; i--)
6881 {
6882 if (fmt[i] == 'e')
6883 ret |= find_loads (XEXP (x, i), store_pattern);
6884 else if (fmt[i] == 'E')
6885 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6886 ret |= find_loads (XVECEXP (x, i, j), store_pattern);
6887 }
6888 return ret;
6889}
6890
589005ff 6891/* Check if INSN kills the store pattern X (is aliased with it).
a13d4ebf
AM
6892 Return 1 if it it does. */
6893
589005ff 6894static int
a13d4ebf
AM
6895store_killed_in_insn (x, insn)
6896 rtx x, insn;
6897{
6898 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6899 return 0;
589005ff 6900
a13d4ebf
AM
6901 if (GET_CODE (insn) == CALL_INSN)
6902 {
1218665b
JJ
6903 /* A normal or pure call might read from pattern,
6904 but a const call will not. */
a6a063b8 6905 return ! CONST_OR_PURE_CALL_P (insn) || pure_call_p (insn);
a13d4ebf 6906 }
589005ff 6907
a13d4ebf
AM
6908 if (GET_CODE (PATTERN (insn)) == SET)
6909 {
6910 rtx pat = PATTERN (insn);
6911 /* Check for memory stores to aliased objects. */
6912 if (GET_CODE (SET_DEST (pat)) == MEM && !expr_equiv_p (SET_DEST (pat), x))
aaa4ca30 6913 /* pretend its a load and check for aliasing. */
a13d4ebf
AM
6914 if (find_loads (SET_DEST (pat), x))
6915 return 1;
6916 return find_loads (SET_SRC (pat), x);
6917 }
6918 else
6919 return find_loads (PATTERN (insn), x);
6920}
6921
6922/* Returns 1 if the expression X is loaded or clobbered on or after INSN
6923 within basic block BB. */
6924
589005ff 6925static int
aaa4ca30 6926store_killed_after (x, insn, bb)
a13d4ebf 6927 rtx x, insn;
e2d2ed72 6928 basic_block bb;
a13d4ebf 6929{
8e42ace1 6930 rtx last = bb->end;
589005ff 6931
8e42ace1
KH
6932 if (insn == last)
6933 return 0;
aaa4ca30
AJ
6934
6935 /* Check if the register operands of the store are OK in this block.
589005ff
KH
6936 Note that if registers are changed ANYWHERE in the block, we'll
6937 decide we can't move it, regardless of whether it changed above
aaa4ca30
AJ
6938 or below the store. This could be improved by checking the register
6939 operands while lookinng for aliasing in each insn. */
6940 if (!store_ops_ok (XEXP (x, 0), bb))
a13d4ebf
AM
6941 return 1;
6942
8e42ace1
KH
6943 for ( ; insn && insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
6944 if (store_killed_in_insn (x, insn))
6945 return 1;
589005ff 6946
a13d4ebf
AM
6947 return 0;
6948}
6949
aaa4ca30 6950/* Returns 1 if the expression X is loaded or clobbered on or before INSN
a13d4ebf 6951 within basic block BB. */
589005ff 6952static int
a13d4ebf
AM
6953store_killed_before (x, insn, bb)
6954 rtx x, insn;
e2d2ed72 6955 basic_block bb;
a13d4ebf 6956{
8e42ace1 6957 rtx first = bb->head;
a13d4ebf 6958
8e42ace1
KH
6959 if (insn == first)
6960 return store_killed_in_insn (x, insn);
589005ff 6961
aaa4ca30 6962 /* Check if the register operands of the store are OK in this block.
589005ff
KH
6963 Note that if registers are changed ANYWHERE in the block, we'll
6964 decide we can't move it, regardless of whether it changed above
aaa4ca30
AJ
6965 or below the store. This could be improved by checking the register
6966 operands while lookinng for aliasing in each insn. */
6967 if (!store_ops_ok (XEXP (x, 0), bb))
a13d4ebf
AM
6968 return 1;
6969
8e42ace1
KH
6970 for ( ; insn && insn != PREV_INSN (first); insn = PREV_INSN (insn))
6971 if (store_killed_in_insn (x, insn))
6972 return 1;
589005ff 6973
8e42ace1 6974 return 0;
a13d4ebf
AM
6975}
6976
6977#define ANTIC_STORE_LIST(x) ((x)->loads)
6978#define AVAIL_STORE_LIST(x) ((x)->stores)
6979
6980/* Given the table of available store insns at the end of blocks,
6981 determine which ones are not killed by aliasing, and generate
6982 the appropriate vectors for gen and killed. */
6983static void
589005ff 6984build_store_vectors ()
a13d4ebf 6985{
e0082a72 6986 basic_block bb, b;
a13d4ebf
AM
6987 rtx insn, st;
6988 struct ls_expr * ptr;
6989
6990 /* Build the gen_vector. This is any store in the table which is not killed
6991 by aliasing later in its block. */
d55bc081
ZD
6992 ae_gen = (sbitmap *) sbitmap_vector_alloc (last_basic_block, num_stores);
6993 sbitmap_vector_zero (ae_gen, last_basic_block);
a13d4ebf 6994
d55bc081
ZD
6995 st_antloc = (sbitmap *) sbitmap_vector_alloc (last_basic_block, num_stores);
6996 sbitmap_vector_zero (st_antloc, last_basic_block);
aaa4ca30 6997
a13d4ebf 6998 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
589005ff 6999 {
a13d4ebf
AM
7000 /* Put all the stores into either the antic list, or the avail list,
7001 or both. */
7002 rtx store_list = ptr->stores;
7003 ptr->stores = NULL_RTX;
7004
7005 for (st = store_list; st != NULL; st = XEXP (st, 1))
7006 {
7007 insn = XEXP (st, 0);
e2d2ed72 7008 bb = BLOCK_FOR_INSN (insn);
589005ff 7009
aaa4ca30 7010 if (!store_killed_after (ptr->pattern, insn, bb))
a13d4ebf
AM
7011 {
7012 /* If we've already seen an availale expression in this block,
7013 we can delete the one we saw already (It occurs earlier in
7014 the block), and replace it with this one). We'll copy the
7015 old SRC expression to an unused register in case there
7016 are any side effects. */
0b17ab2f 7017 if (TEST_BIT (ae_gen[bb->index], ptr->index))
a13d4ebf
AM
7018 {
7019 /* Find previous store. */
7020 rtx st;
7021 for (st = AVAIL_STORE_LIST (ptr); st ; st = XEXP (st, 1))
e2d2ed72 7022 if (BLOCK_FOR_INSN (XEXP (st, 0)) == bb)
a13d4ebf
AM
7023 break;
7024 if (st)
7025 {
7026 rtx r = gen_reg_rtx (GET_MODE (ptr->pattern));
7027 if (gcse_file)
8e42ace1 7028 fprintf (gcse_file, "Removing redundant store:\n");
a13d4ebf
AM
7029 replace_store_insn (r, XEXP (st, 0), bb);
7030 XEXP (st, 0) = insn;
7031 continue;
7032 }
7033 }
0b17ab2f 7034 SET_BIT (ae_gen[bb->index], ptr->index);
a13d4ebf
AM
7035 AVAIL_STORE_LIST (ptr) = alloc_INSN_LIST (insn,
7036 AVAIL_STORE_LIST (ptr));
7037 }
589005ff 7038
a13d4ebf
AM
7039 if (!store_killed_before (ptr->pattern, insn, bb))
7040 {
7041 SET_BIT (st_antloc[BLOCK_NUM (insn)], ptr->index);
7042 ANTIC_STORE_LIST (ptr) = alloc_INSN_LIST (insn,
7043 ANTIC_STORE_LIST (ptr));
7044 }
7045 }
589005ff 7046
a13d4ebf
AM
7047 /* Free the original list of store insns. */
7048 free_INSN_LIST_list (&store_list);
7049 }
589005ff 7050
d55bc081
ZD
7051 ae_kill = (sbitmap *) sbitmap_vector_alloc (last_basic_block, num_stores);
7052 sbitmap_vector_zero (ae_kill, last_basic_block);
a13d4ebf 7053
d55bc081
ZD
7054 transp = (sbitmap *) sbitmap_vector_alloc (last_basic_block, num_stores);
7055 sbitmap_vector_zero (transp, last_basic_block);
a13d4ebf
AM
7056
7057 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
e0082a72 7058 FOR_EACH_BB (b)
a13d4ebf 7059 {
e0082a72 7060 if (store_killed_after (ptr->pattern, b->head, b))
a13d4ebf 7061 {
dc297297 7062 /* The anticipatable expression is not killed if it's gen'd. */
aaa4ca30 7063 /*
589005ff 7064 We leave this check out for now. If we have a code sequence
aaa4ca30
AJ
7065 in a block which looks like:
7066 ST MEMa = x
7067 L y = MEMa
7068 ST MEMa = z
7069 We should flag this as having an ANTIC expression, NOT
7070 transparent, NOT killed, and AVAIL.
7071 Unfortunately, since we haven't re-written all loads to
589005ff 7072 use the reaching reg, we'll end up doing an incorrect
aaa4ca30
AJ
7073 Load in the middle here if we push the store down. It happens in
7074 gcc.c-torture/execute/960311-1.c with -O3
7075 If we always kill it in this case, we'll sometimes do
7076 uneccessary work, but it shouldn't actually hurt anything.
7077 if (!TEST_BIT (ae_gen[b], ptr->index)). */
e0082a72 7078 SET_BIT (ae_kill[b->index], ptr->index);
aaa4ca30
AJ
7079 }
7080 else
e0082a72 7081 SET_BIT (transp[b->index], ptr->index);
aaa4ca30
AJ
7082 }
7083
7084 /* Any block with no exits calls some non-returning function, so
7085 we better mark the store killed here, or we might not store to
7086 it at all. If we knew it was abort, we wouldn't have to store,
7087 but we don't know that for sure. */
589005ff 7088 if (gcse_file)
aaa4ca30
AJ
7089 {
7090 fprintf (gcse_file, "ST_avail and ST_antic (shown under loads..)\n");
7091 print_ldst_list (gcse_file);
d55bc081
ZD
7092 dump_sbitmap_vector (gcse_file, "st_antloc", "", st_antloc, last_basic_block);
7093 dump_sbitmap_vector (gcse_file, "st_kill", "", ae_kill, last_basic_block);
7094 dump_sbitmap_vector (gcse_file, "Transpt", "", transp, last_basic_block);
7095 dump_sbitmap_vector (gcse_file, "st_avloc", "", ae_gen, last_basic_block);
a13d4ebf
AM
7096 }
7097}
7098
589005ff 7099/* Insert an instruction at the begining of a basic block, and update
a13d4ebf
AM
7100 the BLOCK_HEAD if needed. */
7101
589005ff 7102static void
a13d4ebf
AM
7103insert_insn_start_bb (insn, bb)
7104 rtx insn;
e2d2ed72 7105 basic_block bb;
a13d4ebf
AM
7106{
7107 /* Insert at start of successor block. */
e2d2ed72
AM
7108 rtx prev = PREV_INSN (bb->head);
7109 rtx before = bb->head;
a13d4ebf
AM
7110 while (before != 0)
7111 {
7112 if (GET_CODE (before) != CODE_LABEL
7113 && (GET_CODE (before) != NOTE
7114 || NOTE_LINE_NUMBER (before) != NOTE_INSN_BASIC_BLOCK))
7115 break;
7116 prev = before;
e2d2ed72 7117 if (prev == bb->end)
a13d4ebf
AM
7118 break;
7119 before = NEXT_INSN (before);
7120 }
7121
7122 insn = emit_insn_after (insn, prev);
7123
a13d4ebf
AM
7124 if (gcse_file)
7125 {
7126 fprintf (gcse_file, "STORE_MOTION insert store at start of BB %d:\n",
0b17ab2f 7127 bb->index);
a13d4ebf
AM
7128 print_inline_rtx (gcse_file, insn, 6);
7129 fprintf (gcse_file, "\n");
7130 }
7131}
7132
7133/* This routine will insert a store on an edge. EXPR is the ldst entry for
7134 the memory reference, and E is the edge to insert it on. Returns non-zero
7135 if an edge insertion was performed. */
7136
7137static int
7138insert_store (expr, e)
7139 struct ls_expr * expr;
7140 edge e;
7141{
7142 rtx reg, insn;
e2d2ed72 7143 basic_block bb;
a13d4ebf
AM
7144 edge tmp;
7145
7146 /* We did all the deleted before this insert, so if we didn't delete a
7147 store, then we haven't set the reaching reg yet either. */
7148 if (expr->reaching_reg == NULL_RTX)
7149 return 0;
7150
7151 reg = expr->reaching_reg;
7152 insn = gen_move_insn (expr->pattern, reg);
589005ff 7153
a13d4ebf
AM
7154 /* If we are inserting this expression on ALL predecessor edges of a BB,
7155 insert it at the start of the BB, and reset the insert bits on the other
ff7cc307 7156 edges so we don't try to insert it on the other edges. */
e2d2ed72 7157 bb = e->dest;
a13d4ebf
AM
7158 for (tmp = e->dest->pred; tmp ; tmp = tmp->pred_next)
7159 {
7160 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
7161 if (index == EDGE_INDEX_NO_EDGE)
7162 abort ();
7163 if (! TEST_BIT (pre_insert_map[index], expr->index))
7164 break;
7165 }
7166
7167 /* If tmp is NULL, we found an insertion on every edge, blank the
7168 insertion vector for these edges, and insert at the start of the BB. */
e2d2ed72 7169 if (!tmp && bb != EXIT_BLOCK_PTR)
a13d4ebf
AM
7170 {
7171 for (tmp = e->dest->pred; tmp ; tmp = tmp->pred_next)
7172 {
7173 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
7174 RESET_BIT (pre_insert_map[index], expr->index);
7175 }
7176 insert_insn_start_bb (insn, bb);
7177 return 0;
7178 }
589005ff 7179
a13d4ebf
AM
7180 /* We can't insert on this edge, so we'll insert at the head of the
7181 successors block. See Morgan, sec 10.5. */
7182 if ((e->flags & EDGE_ABNORMAL) == EDGE_ABNORMAL)
7183 {
7184 insert_insn_start_bb (insn, bb);
7185 return 0;
7186 }
7187
7188 insert_insn_on_edge (insn, e);
589005ff 7189
a13d4ebf
AM
7190 if (gcse_file)
7191 {
7192 fprintf (gcse_file, "STORE_MOTION insert insn on edge (%d, %d):\n",
0b17ab2f 7193 e->src->index, e->dest->index);
a13d4ebf
AM
7194 print_inline_rtx (gcse_file, insn, 6);
7195 fprintf (gcse_file, "\n");
7196 }
589005ff 7197
a13d4ebf
AM
7198 return 1;
7199}
7200
7201/* This routine will replace a store with a SET to a specified register. */
7202
7203static void
7204replace_store_insn (reg, del, bb)
7205 rtx reg, del;
e2d2ed72 7206 basic_block bb;
a13d4ebf
AM
7207{
7208 rtx insn;
589005ff 7209
a13d4ebf
AM
7210 insn = gen_move_insn (reg, SET_SRC (PATTERN (del)));
7211 insn = emit_insn_after (insn, del);
589005ff 7212
a13d4ebf
AM
7213 if (gcse_file)
7214 {
589005ff 7215 fprintf (gcse_file,
0b17ab2f 7216 "STORE_MOTION delete insn in BB %d:\n ", bb->index);
a13d4ebf 7217 print_inline_rtx (gcse_file, del, 6);
8e42ace1 7218 fprintf (gcse_file, "\nSTORE MOTION replaced with insn:\n ");
a13d4ebf 7219 print_inline_rtx (gcse_file, insn, 6);
8e42ace1 7220 fprintf (gcse_file, "\n");
a13d4ebf 7221 }
589005ff 7222
49ce134f 7223 delete_insn (del);
a13d4ebf
AM
7224}
7225
7226
7227/* Delete a store, but copy the value that would have been stored into
7228 the reaching_reg for later storing. */
7229
7230static void
7231delete_store (expr, bb)
7232 struct ls_expr * expr;
e2d2ed72 7233 basic_block bb;
a13d4ebf
AM
7234{
7235 rtx reg, i, del;
7236
7237 if (expr->reaching_reg == NULL_RTX)
7238 expr->reaching_reg = gen_reg_rtx (GET_MODE (expr->pattern));
a13d4ebf 7239
589005ff
KH
7240
7241 /* If there is more than 1 store, the earlier ones will be dead,
7242 but it doesn't hurt to replace them here. */
a13d4ebf 7243 reg = expr->reaching_reg;
589005ff 7244
a13d4ebf
AM
7245 for (i = AVAIL_STORE_LIST (expr); i; i = XEXP (i, 1))
7246 {
7247 del = XEXP (i, 0);
e2d2ed72 7248 if (BLOCK_FOR_INSN (del) == bb)
a13d4ebf 7249 {
589005ff 7250 /* We know there is only one since we deleted redundant
a13d4ebf
AM
7251 ones during the available computation. */
7252 replace_store_insn (reg, del, bb);
7253 break;
7254 }
7255 }
7256}
7257
7258/* Free memory used by store motion. */
7259
589005ff 7260static void
a13d4ebf
AM
7261free_store_memory ()
7262{
7263 free_ldst_mems ();
589005ff 7264
a13d4ebf 7265 if (ae_gen)
5a660bff 7266 sbitmap_vector_free (ae_gen);
a13d4ebf 7267 if (ae_kill)
5a660bff 7268 sbitmap_vector_free (ae_kill);
a13d4ebf 7269 if (transp)
5a660bff 7270 sbitmap_vector_free (transp);
a13d4ebf 7271 if (st_antloc)
5a660bff 7272 sbitmap_vector_free (st_antloc);
a13d4ebf 7273 if (pre_insert_map)
5a660bff 7274 sbitmap_vector_free (pre_insert_map);
a13d4ebf 7275 if (pre_delete_map)
5a660bff 7276 sbitmap_vector_free (pre_delete_map);
aaa4ca30
AJ
7277 if (reg_set_in_block)
7278 sbitmap_vector_free (reg_set_in_block);
589005ff 7279
a13d4ebf
AM
7280 ae_gen = ae_kill = transp = st_antloc = NULL;
7281 pre_insert_map = pre_delete_map = reg_set_in_block = NULL;
7282}
7283
7284/* Perform store motion. Much like gcse, except we move expressions the
7285 other way by looking at the flowgraph in reverse. */
7286
7287static void
7288store_motion ()
7289{
e0082a72 7290 basic_block bb;
0b17ab2f 7291 int x;
a13d4ebf 7292 struct ls_expr * ptr;
adfcce61 7293 int update_flow = 0;
aaa4ca30 7294
a13d4ebf
AM
7295 if (gcse_file)
7296 {
7297 fprintf (gcse_file, "before store motion\n");
7298 print_rtl (gcse_file, get_insns ());
7299 }
7300
7301
7302 init_alias_analysis ();
aaa4ca30 7303
a13d4ebf
AM
7304 /* Find all the stores that are live to the end of their block. */
7305 num_stores = compute_store_table ();
7306 if (num_stores == 0)
7307 {
aaa4ca30 7308 sbitmap_vector_free (reg_set_in_block);
a13d4ebf
AM
7309 end_alias_analysis ();
7310 return;
7311 }
7312
7313 /* Now compute whats actually available to move. */
7314 add_noreturn_fake_exit_edges ();
7315 build_store_vectors ();
7316
589005ff
KH
7317 edge_list = pre_edge_rev_lcm (gcse_file, num_stores, transp, ae_gen,
7318 st_antloc, ae_kill, &pre_insert_map,
a13d4ebf
AM
7319 &pre_delete_map);
7320
7321 /* Now we want to insert the new stores which are going to be needed. */
7322 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
7323 {
e0082a72
ZD
7324 FOR_EACH_BB (bb)
7325 if (TEST_BIT (pre_delete_map[bb->index], ptr->index))
7326 delete_store (ptr, bb);
a13d4ebf 7327
0b17ab2f
RH
7328 for (x = 0; x < NUM_EDGES (edge_list); x++)
7329 if (TEST_BIT (pre_insert_map[x], ptr->index))
7330 update_flow |= insert_store (ptr, INDEX_EDGE (edge_list, x));
a13d4ebf
AM
7331 }
7332
7333 if (update_flow)
7334 commit_edge_insertions ();
aaa4ca30 7335
a13d4ebf
AM
7336 free_store_memory ();
7337 free_edge_list (edge_list);
7338 remove_fake_edges ();
7339 end_alias_analysis ();
7340}
e2500fed
GK
7341
7342#include "gt-gcse.h"