]>
Commit | Line | Data |
---|---|---|
07abdb66 | 1 | /* Partial redundancy elimination / Hoisting for RTL. |
711789cc | 2 | Copyright (C) 1997-2013 Free Software Foundation, Inc. |
18aa2adf | 3 | |
f12b58b3 | 4 | This file is part of GCC. |
18aa2adf | 5 | |
f12b58b3 | 6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
8c4c00c1 | 8 | Software Foundation; either version 3, or (at your option) any later |
f12b58b3 | 9 | version. |
18aa2adf | 10 | |
f12b58b3 | 11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
18aa2adf | 15 | |
16 | You should have received a copy of the GNU General Public License | |
8c4c00c1 | 17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
18aa2adf | 19 | |
20 | /* TODO | |
21 | - reordering of memory allocation and freeing to be more space efficient | |
1ec78e16 | 22 | - calc rough register pressure information and use the info to drive all |
23 | kinds of code motion (including code hoisting) in a unified way. | |
18aa2adf | 24 | */ |
25 | ||
26 | /* References searched while implementing this. | |
18aa2adf | 27 | |
28 | Compilers Principles, Techniques and Tools | |
29 | Aho, Sethi, Ullman | |
30 | Addison-Wesley, 1988 | |
31 | ||
32 | Global Optimization by Suppression of Partial Redundancies | |
33 | E. Morel, C. Renvoise | |
34 | communications of the acm, Vol. 22, Num. 2, Feb. 1979 | |
35 | ||
36 | A Portable Machine-Independent Global Optimizer - Design and Measurements | |
37 | Frederick Chow | |
38 | Stanford Ph.D. thesis, Dec. 1983 | |
39 | ||
18aa2adf | 40 | A Fast Algorithm for Code Movement Optimization |
41 | D.M. Dhamdhere | |
42 | SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988 | |
43 | ||
44 | A Solution to a Problem with Morel and Renvoise's | |
45 | Global Optimization by Suppression of Partial Redundancies | |
46 | K-H Drechsler, M.P. Stadel | |
47 | ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988 | |
48 | ||
49 | Practical Adaptation of the Global Optimization | |
50 | Algorithm of Morel and Renvoise | |
51 | D.M. Dhamdhere | |
52 | ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991 | |
53 | ||
54 | Efficiently Computing Static Single Assignment Form and the Control | |
55 | Dependence Graph | |
56 | R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck | |
57 | ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991 | |
58 | ||
18aa2adf | 59 | Lazy Code Motion |
60 | J. Knoop, O. Ruthing, B. Steffen | |
61 | ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI | |
62 | ||
63 | What's In a Region? Or Computing Control Dependence Regions in Near-Linear | |
64 | Time for Reducible Flow Control | |
65 | Thomas Ball | |
66 | ACM Letters on Programming Languages and Systems, | |
67 | Vol. 2, Num. 1-4, Mar-Dec 1993 | |
68 | ||
69 | An Efficient Representation for Sparse Sets | |
70 | Preston Briggs, Linda Torczon | |
71 | ACM Letters on Programming Languages and Systems, | |
72 | Vol. 2, Num. 1-4, Mar-Dec 1993 | |
73 | ||
74 | A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion | |
75 | K-H Drechsler, M.P. Stadel | |
76 | ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993 | |
77 | ||
78 | Partial Dead Code Elimination | |
79 | J. Knoop, O. Ruthing, B. Steffen | |
80 | ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994 | |
81 | ||
82 | Effective Partial Redundancy Elimination | |
83 | P. Briggs, K.D. Cooper | |
84 | ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994 | |
85 | ||
86 | The Program Structure Tree: Computing Control Regions in Linear Time | |
87 | R. Johnson, D. Pearson, K. Pingali | |
88 | ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994 | |
89 | ||
90 | Optimal Code Motion: Theory and Practice | |
91 | J. Knoop, O. Ruthing, B. Steffen | |
92 | ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994 | |
93 | ||
94 | The power of assignment motion | |
95 | J. Knoop, O. Ruthing, B. Steffen | |
96 | ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI | |
97 | ||
98 | Global code motion / global value numbering | |
99 | C. Click | |
100 | ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI | |
101 | ||
102 | Value Driven Redundancy Elimination | |
103 | L.T. Simpson | |
104 | Rice University Ph.D. thesis, Apr. 1996 | |
105 | ||
106 | Value Numbering | |
107 | L.T. Simpson | |
108 | Massively Scalar Compiler Project, Rice University, Sep. 1996 | |
109 | ||
110 | High Performance Compilers for Parallel Computing | |
111 | Michael Wolfe | |
112 | Addison-Wesley, 1996 | |
113 | ||
ef0d57a0 | 114 | Advanced Compiler Design and Implementation |
115 | Steven Muchnick | |
116 | Morgan Kaufmann, 1997 | |
117 | ||
7bcd381b | 118 | Building an Optimizing Compiler |
119 | Robert Morgan | |
120 | Digital Press, 1998 | |
121 | ||
ef0d57a0 | 122 | People wishing to speed up the code here should read: |
123 | Elimination Algorithms for Data Flow Analysis | |
124 | B.G. Ryder, M.C. Paull | |
125 | ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986 | |
126 | ||
127 | How to Analyze Large Programs Efficiently and Informatively | |
128 | D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck | |
129 | ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI | |
130 | ||
18aa2adf | 131 | People wishing to do something different can find various possibilities |
132 | in the above papers and elsewhere. | |
133 | */ | |
134 | ||
135 | #include "config.h" | |
ebd9163c | 136 | #include "system.h" |
805e22b2 | 137 | #include "coretypes.h" |
138 | #include "tm.h" | |
0b205f4c | 139 | #include "diagnostic-core.h" |
d3b64f2d | 140 | #include "toplev.h" |
18aa2adf | 141 | |
1ec78e16 | 142 | #include "hard-reg-set.h" |
18aa2adf | 143 | #include "rtl.h" |
95b49b1d | 144 | #include "tree.h" |
7953c610 | 145 | #include "tm_p.h" |
18aa2adf | 146 | #include "regs.h" |
1ec78e16 | 147 | #include "ira.h" |
18aa2adf | 148 | #include "flags.h" |
18aa2adf | 149 | #include "insn-config.h" |
150 | #include "recog.h" | |
151 | #include "basic-block.h" | |
0a893c29 | 152 | #include "function.h" |
3cfec666 | 153 | #include "expr.h" |
a17466fa | 154 | #include "except.h" |
06e2144a | 155 | #include "ggc.h" |
9159979b | 156 | #include "params.h" |
09a762be | 157 | #include "cselib.h" |
c8a8ab0f | 158 | #include "intl.h" |
18aa2adf | 159 | #include "obstack.h" |
77fce4cd | 160 | #include "tree-pass.h" |
d9dd21a8 | 161 | #include "hash-table.h" |
3072d30e | 162 | #include "df.h" |
163 | #include "dbgcnt.h" | |
2b86a75a | 164 | #include "target.h" |
049d15fc | 165 | #include "gcse.h" |
4059f3f0 | 166 | |
ef0d57a0 | 167 | /* We support GCSE via Partial Redundancy Elimination. PRE optimizations |
05476866 | 168 | are a superset of those done by classic GCSE. |
18aa2adf | 169 | |
07abdb66 | 170 | Two passes of copy/constant propagation are done around PRE or hoisting |
171 | because the first one enables more GCSE and the second one helps to clean | |
172 | up the copies that PRE and HOIST create. This is needed more for PRE than | |
173 | for HOIST because code hoisting will try to use an existing register | |
174 | containing the common subexpression rather than create a new one. This is | |
175 | harder to do for PRE because of the code motion (which HOIST doesn't do). | |
18aa2adf | 176 | |
177 | Expressions we are interested in GCSE-ing are of the form | |
178 | (set (pseudo-reg) (expression)). | |
179 | Function want_to_gcse_p says what these are. | |
180 | ||
05476866 | 181 | In addition, expressions in REG_EQUAL notes are candidates for GCSE-ing. |
d45a307d | 182 | This allows PRE to hoist expressions that are expressed in multiple insns, |
05476866 | 183 | such as complex address calculations (e.g. for PIC code, or loads with a |
184 | high part and a low part). | |
d45a307d | 185 | |
18aa2adf | 186 | PRE handles moving invariant expressions out of loops (by treating them as |
ef0d57a0 | 187 | partially redundant). |
18aa2adf | 188 | |
18aa2adf | 189 | ********************** |
190 | ||
191 | We used to support multiple passes but there are diminishing returns in | |
192 | doing so. The first pass usually makes 90% of the changes that are doable. | |
193 | A second pass can make a few more changes made possible by the first pass. | |
194 | Experiments show any further passes don't make enough changes to justify | |
195 | the expense. | |
196 | ||
197 | A study of spec92 using an unlimited number of passes: | |
198 | [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83, | |
199 | [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2, | |
200 | [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1 | |
201 | ||
202 | It was found doing copy propagation between each pass enables further | |
203 | substitutions. | |
204 | ||
d45a307d | 205 | This study was done before expressions in REG_EQUAL notes were added as |
206 | candidate expressions for optimization, and before the GIMPLE optimizers | |
207 | were added. Probably, multiple passes is even less efficient now than | |
208 | at the time when the study was conducted. | |
209 | ||
18aa2adf | 210 | PRE is quite expensive in complicated functions because the DFA can take |
d45a307d | 211 | a while to converge. Hence we only perform one pass. |
18aa2adf | 212 | |
213 | ********************** | |
214 | ||
215 | The steps for PRE are: | |
216 | ||
217 | 1) Build the hash table of expressions we wish to GCSE (expr_hash_table). | |
218 | ||
219 | 2) Perform the data flow analysis for PRE. | |
220 | ||
221 | 3) Delete the redundant instructions | |
222 | ||
223 | 4) Insert the required copies [if any] that make the partially | |
224 | redundant instructions fully redundant. | |
225 | ||
226 | 5) For other reaching expressions, insert an instruction to copy the value | |
227 | to a newly created pseudo that will reach the redundant instruction. | |
228 | ||
229 | The deletion is done first so that when we do insertions we | |
230 | know which pseudo reg to use. | |
231 | ||
232 | Various papers have argued that PRE DFA is expensive (O(n^2)) and others | |
233 | argue it is not. The number of iterations for the algorithm to converge | |
234 | is typically 2-4 so I don't view it as that expensive (relatively speaking). | |
235 | ||
05476866 | 236 | PRE GCSE depends heavily on the second CPROP pass to clean up the copies |
18aa2adf | 237 | we create. To make an expression reach the place where it's redundant, |
238 | the result of the expression is copied to a new register, and the redundant | |
239 | expression is deleted by replacing it with this new register. Classic GCSE | |
240 | doesn't have this problem as much as it computes the reaching defs of | |
04a40f24 | 241 | each register in each block and thus can try to use an existing |
242 | register. */ | |
18aa2adf | 243 | \f |
244 | /* GCSE global vars. */ | |
245 | ||
049d15fc | 246 | struct target_gcse default_target_gcse; |
247 | #if SWITCHABLE_TARGET | |
248 | struct target_gcse *this_target_gcse = &default_target_gcse; | |
249 | #endif | |
250 | ||
d743aba2 | 251 | /* Set to non-zero if CSE should run after all GCSE optimizations are done. */ |
252 | int flag_rerun_cse_after_global_opts; | |
ef0d57a0 | 253 | |
18aa2adf | 254 | /* An obstack for our working variables. */ |
255 | static struct obstack gcse_obstack; | |
256 | ||
18aa2adf | 257 | /* Hash table of expressions. */ |
258 | ||
259 | struct expr | |
260 | { | |
bc8197c0 | 261 | /* The expression. */ |
18aa2adf | 262 | rtx expr; |
263 | /* Index in the available expression bitmaps. */ | |
264 | int bitmap_index; | |
265 | /* Next entry with the same hash. */ | |
266 | struct expr *next_same_hash; | |
267 | /* List of anticipatable occurrences in basic blocks in the function. | |
268 | An "anticipatable occurrence" is one that is the first occurrence in the | |
ef0d57a0 | 269 | basic block, the operands are not modified in the basic block prior |
270 | to the occurrence and the output is not used between the start of | |
271 | the block and the occurrence. */ | |
18aa2adf | 272 | struct occr *antic_occr; |
273 | /* List of available occurrence in basic blocks in the function. | |
274 | An "available occurrence" is one that is the last occurrence in the | |
275 | basic block and the operands are not modified by following statements in | |
276 | the basic block [including this insn]. */ | |
277 | struct occr *avail_occr; | |
278 | /* Non-null if the computation is PRE redundant. | |
279 | The value is the newly created pseudo-reg to record a copy of the | |
280 | expression in all the places that reach the redundant copy. */ | |
281 | rtx reaching_reg; | |
8b38b150 | 282 | /* Maximum distance in instructions this expression can travel. |
283 | We avoid moving simple expressions for more than a few instructions | |
284 | to keep register pressure under control. | |
285 | A value of "0" removes restrictions on how far the expression can | |
286 | travel. */ | |
287 | int max_distance; | |
18aa2adf | 288 | }; |
289 | ||
290 | /* Occurrence of an expression. | |
291 | There is one per basic block. If a pattern appears more than once the | |
292 | last appearance is used [or first for anticipatable expressions]. */ | |
293 | ||
294 | struct occr | |
295 | { | |
296 | /* Next occurrence of this expression. */ | |
297 | struct occr *next; | |
298 | /* The insn that computes the expression. */ | |
299 | rtx insn; | |
6ef828f9 | 300 | /* Nonzero if this [anticipatable] occurrence has been deleted. */ |
18aa2adf | 301 | char deleted_p; |
6ef828f9 | 302 | /* Nonzero if this [available] occurrence has been copied to |
18aa2adf | 303 | reaching_reg. */ |
304 | /* ??? This is mutually exclusive with deleted_p, so they could share | |
305 | the same byte. */ | |
306 | char copied_p; | |
307 | }; | |
308 | ||
c0939130 | 309 | typedef struct occr *occr_t; |
c0939130 | 310 | |
07abdb66 | 311 | /* Expression hash tables. |
18aa2adf | 312 | Each hash table is an array of buckets. |
313 | ??? It is known that if it were an array of entries, structure elements | |
314 | `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is | |
315 | not clear whether in the final analysis a sufficient amount of memory would | |
316 | be saved as the size of the available expression bitmaps would be larger | |
317 | [one could build a mapping table without holes afterwards though]. | |
2c084240 | 318 | Someday I'll perform the computation and figure it out. */ |
18aa2adf | 319 | |
26dbec0a | 320 | struct hash_table_d |
27cfe3f1 | 321 | { |
322 | /* The table itself. | |
323 | This is an array of `expr_hash_table_size' elements. */ | |
324 | struct expr **table; | |
325 | ||
326 | /* Size of the hash table, in elements. */ | |
327 | unsigned int size; | |
a08b57af | 328 | |
27cfe3f1 | 329 | /* Number of hash table elements. */ |
330 | unsigned int n_elems; | |
27cfe3f1 | 331 | }; |
2c084240 | 332 | |
27cfe3f1 | 333 | /* Expression hash table. */ |
26dbec0a | 334 | static struct hash_table_d expr_hash_table; |
27cfe3f1 | 335 | |
8e802be9 | 336 | /* This is a list of expressions which are MEMs and will be used by load |
3cfec666 | 337 | or store motion. |
bc8197c0 | 338 | Load motion tracks MEMs which aren't killed by anything except itself, |
339 | i.e. loads and stores to a single location. | |
3cfec666 | 340 | We can then allow movement of these MEM refs with a little special |
8e802be9 | 341 | allowance. (all stores copy the same value to the reaching reg used |
342 | for the loads). This means all values used to store into memory must have | |
bc8197c0 | 343 | no side effects so we can re-issue the setter value. */ |
8e802be9 | 344 | |
345 | struct ls_expr | |
346 | { | |
347 | struct expr * expr; /* Gcse expression reference for LM. */ | |
348 | rtx pattern; /* Pattern of this mem. */ | |
64928ee5 | 349 | rtx pattern_regs; /* List of registers mentioned by the mem. */ |
7a676a9f | 350 | rtx loads; /* INSN list of loads seen. */ |
351 | rtx stores; /* INSN list of stores seen. */ | |
8e802be9 | 352 | struct ls_expr * next; /* Next in the list. */ |
353 | int invalid; /* Invalid for some reason. */ | |
354 | int index; /* If it maps to a bitmap index. */ | |
69333952 | 355 | unsigned int hash_index; /* Index when in a hash table. */ |
8e802be9 | 356 | rtx reaching_reg; /* Register to use when re-writing. */ |
357 | }; | |
358 | ||
359 | /* Head of the list of load/store memory refs. */ | |
360 | static struct ls_expr * pre_ldst_mems = NULL; | |
361 | ||
d9dd21a8 | 362 | struct pre_ldst_expr_hasher : typed_noop_remove <ls_expr> |
363 | { | |
364 | typedef ls_expr value_type; | |
365 | typedef value_type compare_type; | |
366 | static inline hashval_t hash (const value_type *); | |
367 | static inline bool equal (const value_type *, const compare_type *); | |
368 | }; | |
369 | ||
370 | /* Hashtable helpers. */ | |
371 | inline hashval_t | |
372 | pre_ldst_expr_hasher::hash (const value_type *x) | |
373 | { | |
374 | int do_not_record_p = 0; | |
375 | return | |
376 | hash_rtx (x->pattern, GET_MODE (x->pattern), &do_not_record_p, NULL, false); | |
377 | } | |
378 | ||
379 | static int expr_equiv_p (const_rtx, const_rtx); | |
380 | ||
381 | inline bool | |
382 | pre_ldst_expr_hasher::equal (const value_type *ptr1, | |
383 | const compare_type *ptr2) | |
384 | { | |
385 | return expr_equiv_p (ptr1->pattern, ptr2->pattern); | |
386 | } | |
387 | ||
0d707271 | 388 | /* Hashtable for the load/store memory refs. */ |
d9dd21a8 | 389 | static hash_table <pre_ldst_expr_hasher> pre_ldst_table; |
0d707271 | 390 | |
18aa2adf | 391 | /* Bitmap containing one bit for each register in the program. |
392 | Used when performing GCSE to track which registers have been set since | |
393 | the start of the basic block. */ | |
7fb47f9f | 394 | static regset reg_set_bitmap; |
18aa2adf | 395 | |
8e802be9 | 396 | /* Array, indexed by basic block number for a list of insns which modify |
397 | memory within that block. */ | |
f1f41a6c | 398 | static vec<rtx> *modify_mem_list; |
78d140c9 | 399 | static bitmap modify_mem_list_set; |
8e802be9 | 400 | |
57c8e46c | 401 | typedef struct modify_pair_s |
402 | { | |
403 | rtx dest; /* A MEM. */ | |
404 | rtx dest_addr; /* The canonical address of `dest'. */ | |
405 | } modify_pair; | |
406 | ||
57c8e46c | 407 | |
408 | /* This array parallels modify_mem_list, except that it stores MEMs | |
409 | being set and their canonicalized memory addresses. */ | |
f1f41a6c | 410 | static vec<modify_pair> *canon_modify_mem_list; |
78d140c9 | 411 | |
f55d2721 | 412 | /* Bitmap indexed by block numbers to record which blocks contain |
413 | function calls. */ | |
414 | static bitmap blocks_with_calls; | |
415 | ||
18aa2adf | 416 | /* Various variables for statistics gathering. */ |
417 | ||
418 | /* Memory used in a pass. | |
419 | This isn't intended to be absolutely precise. Its intent is only | |
420 | to keep an eye on memory usage. */ | |
421 | static int bytes_used; | |
2c084240 | 422 | |
18aa2adf | 423 | /* GCSE substitutions made. */ |
424 | static int gcse_subst_count; | |
425 | /* Number of copy instructions created. */ | |
426 | static int gcse_create_count; | |
18aa2adf | 427 | \f |
8b38b150 | 428 | /* Doing code hoisting. */ |
429 | static bool doing_code_hoisting_p = false; | |
430 | \f | |
0ca684f3 | 431 | /* For available exprs */ |
4b673aa1 | 432 | static sbitmap *ae_kill; |
18aa2adf | 433 | \f |
1ec78e16 | 434 | /* Data stored for each basic block. */ |
435 | struct bb_data | |
436 | { | |
437 | /* Maximal register pressure inside basic block for given register class | |
438 | (defined only for the pressure classes). */ | |
439 | int max_reg_pressure[N_REG_CLASSES]; | |
ded17066 | 440 | /* Recorded register pressure of basic block before trying to hoist |
441 | an expression. Will be used to restore the register pressure | |
442 | if the expression should not be hoisted. */ | |
443 | int old_pressure; | |
444 | /* Recorded register live_in info of basic block during code hoisting | |
445 | process. BACKUP is used to record live_in info before trying to | |
446 | hoist an expression, and will be used to restore LIVE_IN if the | |
447 | expression should not be hoisted. */ | |
448 | bitmap live_in, backup; | |
1ec78e16 | 449 | }; |
450 | ||
451 | #define BB_DATA(bb) ((struct bb_data *) (bb)->aux) | |
452 | ||
453 | static basic_block curr_bb; | |
454 | ||
455 | /* Current register pressure for each pressure class. */ | |
456 | static int curr_reg_pressure[N_REG_CLASSES]; | |
457 | \f | |
458 | ||
952f0048 | 459 | static void compute_can_copy (void); |
2f800191 | 460 | static void *gmalloc (size_t) ATTRIBUTE_MALLOC; |
461 | static void *gcalloc (size_t, size_t) ATTRIBUTE_MALLOC; | |
f0af5a88 | 462 | static void *gcse_alloc (unsigned long); |
defc8016 | 463 | static void alloc_gcse_mem (void); |
952f0048 | 464 | static void free_gcse_mem (void); |
26dbec0a | 465 | static void hash_scan_insn (rtx, struct hash_table_d *); |
466 | static void hash_scan_set (rtx, rtx, struct hash_table_d *); | |
467 | static void hash_scan_clobber (rtx, rtx, struct hash_table_d *); | |
468 | static void hash_scan_call (rtx, rtx, struct hash_table_d *); | |
8b38b150 | 469 | static int want_to_gcse_p (rtx, int *); |
7ecb5bb2 | 470 | static int oprs_unchanged_p (const_rtx, const_rtx, int); |
471 | static int oprs_anticipatable_p (const_rtx, const_rtx); | |
472 | static int oprs_available_p (const_rtx, const_rtx); | |
8b38b150 | 473 | static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, int, |
26dbec0a | 474 | struct hash_table_d *); |
7ecb5bb2 | 475 | static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int); |
952f0048 | 476 | static void record_last_reg_set_info (rtx, int); |
477 | static void record_last_mem_set_info (rtx); | |
81a410b1 | 478 | static void record_last_set_info (rtx, const_rtx, void *); |
26dbec0a | 479 | static void compute_hash_table (struct hash_table_d *); |
07abdb66 | 480 | static void alloc_hash_table (struct hash_table_d *); |
26dbec0a | 481 | static void free_hash_table (struct hash_table_d *); |
482 | static void compute_hash_table_work (struct hash_table_d *); | |
483 | static void dump_hash_table (FILE *, const char *, struct hash_table_d *); | |
07abdb66 | 484 | static void compute_transp (const_rtx, int, sbitmap *); |
952f0048 | 485 | static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *, |
26dbec0a | 486 | struct hash_table_d *); |
81a410b1 | 487 | static void mems_conflict_for_gcse_p (rtx, const_rtx, void *); |
7ecb5bb2 | 488 | static int load_killed_in_block_p (const_basic_block, int, const_rtx, int); |
81a410b1 | 489 | static void canon_list_insert (rtx, const_rtx, void *); |
952f0048 | 490 | static void alloc_pre_mem (int, int); |
491 | static void free_pre_mem (void); | |
bc8197c0 | 492 | static struct edge_list *compute_pre_data (void); |
952f0048 | 493 | static int pre_expr_reaches_here_p (basic_block, struct expr *, |
494 | basic_block); | |
36f52b0d | 495 | static void insert_insn_end_basic_block (struct expr *, basic_block); |
952f0048 | 496 | static void pre_insert_copy_insn (struct expr *, rtx); |
497 | static void pre_insert_copies (void); | |
498 | static int pre_delete (void); | |
bc8197c0 | 499 | static int pre_gcse (struct edge_list *); |
d743aba2 | 500 | static int one_pre_gcse_pass (void); |
952f0048 | 501 | static void add_label_notes (rtx, rtx); |
502 | static void alloc_code_hoist_mem (int, int); | |
503 | static void free_code_hoist_mem (void); | |
504 | static void compute_code_hoist_vbeinout (void); | |
505 | static void compute_code_hoist_data (void); | |
1ec78e16 | 506 | static int should_hoist_expr_to_dom (basic_block, struct expr *, basic_block, |
507 | sbitmap, int, int *, enum reg_class, | |
ded17066 | 508 | int *, bitmap, rtx); |
d743aba2 | 509 | static int hoist_code (void); |
ded17066 | 510 | static enum reg_class get_regno_pressure_class (int regno, int *nregs); |
1ec78e16 | 511 | static enum reg_class get_pressure_class_and_nregs (rtx insn, int *nregs); |
952f0048 | 512 | static int one_code_hoisting_pass (void); |
952f0048 | 513 | static rtx process_insert_insn (struct expr *); |
514 | static int pre_edge_insert (struct edge_list *, struct expr **); | |
952f0048 | 515 | static int pre_expr_reaches_here_p_work (basic_block, struct expr *, |
516 | basic_block, char *); | |
517 | static struct ls_expr * ldst_entry (rtx); | |
518 | static void free_ldst_entry (struct ls_expr *); | |
bc8197c0 | 519 | static void free_ld_motion_mems (void); |
952f0048 | 520 | static void print_ldst_list (FILE *); |
521 | static struct ls_expr * find_rtx_in_ldst (rtx); | |
7ecb5bb2 | 522 | static int simple_mem (const_rtx); |
952f0048 | 523 | static void invalidate_any_buried_refs (rtx); |
524 | static void compute_ld_motion_mems (void); | |
525 | static void trim_ld_motion_mems (void); | |
526 | static void update_ld_motion_stores (struct expr *); | |
952f0048 | 527 | static void clear_modify_mem_tables (void); |
528 | static void free_modify_mem_tables (void); | |
529 | static rtx gcse_emit_move_after (rtx, rtx, rtx); | |
c8a8ab0f | 530 | static bool is_too_expensive (const char *); |
2457c754 | 531 | |
532 | #define GNEW(T) ((T *) gmalloc (sizeof (T))) | |
533 | #define GCNEW(T) ((T *) gcalloc (1, sizeof (T))) | |
534 | ||
535 | #define GNEWVEC(T, N) ((T *) gmalloc (sizeof (T) * (N))) | |
536 | #define GCNEWVEC(T, N) ((T *) gcalloc ((N), sizeof (T))) | |
2457c754 | 537 | |
538 | #define GNEWVAR(T, S) ((T *) gmalloc ((S))) | |
539 | #define GCNEWVAR(T, S) ((T *) gcalloc (1, (S))) | |
2457c754 | 540 | |
541 | #define GOBNEW(T) ((T *) gcse_alloc (sizeof (T))) | |
542 | #define GOBNEWVAR(T, S) ((T *) gcse_alloc ((S))) | |
18aa2adf | 543 | \f |
18aa2adf | 544 | /* Misc. utilities. */ |
545 | ||
049d15fc | 546 | #define can_copy \ |
547 | (this_target_gcse->x_can_copy) | |
548 | #define can_copy_init_p \ | |
549 | (this_target_gcse->x_can_copy_init_p) | |
3d055936 | 550 | |
18aa2adf | 551 | /* Compute which modes support reg/reg copy operations. */ |
552 | ||
553 | static void | |
952f0048 | 554 | compute_can_copy (void) |
18aa2adf | 555 | { |
556 | int i; | |
ebd9163c | 557 | #ifndef AVOID_CCMODE_COPIES |
387732c1 | 558 | rtx reg, insn; |
ebd9163c | 559 | #endif |
3d055936 | 560 | memset (can_copy, 0, NUM_MACHINE_MODES); |
18aa2adf | 561 | |
562 | start_sequence (); | |
563 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
2c084240 | 564 | if (GET_MODE_CLASS (i) == MODE_CC) |
565 | { | |
18aa2adf | 566 | #ifdef AVOID_CCMODE_COPIES |
3d055936 | 567 | can_copy[i] = 0; |
18aa2adf | 568 | #else |
2c084240 | 569 | reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1); |
570 | insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg)); | |
4679ade3 | 571 | if (recog (PATTERN (insn), insn, NULL) >= 0) |
3d055936 | 572 | can_copy[i] = 1; |
18aa2adf | 573 | #endif |
2c084240 | 574 | } |
72f3466e | 575 | else |
3d055936 | 576 | can_copy[i] = 1; |
2c084240 | 577 | |
18aa2adf | 578 | end_sequence (); |
18aa2adf | 579 | } |
3d055936 | 580 | |
581 | /* Returns whether the mode supports reg/reg copy operations. */ | |
582 | ||
583 | bool | |
952f0048 | 584 | can_copy_p (enum machine_mode mode) |
3d055936 | 585 | { |
3d055936 | 586 | if (! can_copy_init_p) |
587 | { | |
588 | compute_can_copy (); | |
589 | can_copy_init_p = true; | |
590 | } | |
591 | ||
592 | return can_copy[mode] != 0; | |
593 | } | |
18aa2adf | 594 | \f |
595 | /* Cover function to xmalloc to record bytes allocated. */ | |
596 | ||
f0af5a88 | 597 | static void * |
a41493eb | 598 | gmalloc (size_t size) |
18aa2adf | 599 | { |
600 | bytes_used += size; | |
601 | return xmalloc (size); | |
602 | } | |
603 | ||
2f800191 | 604 | /* Cover function to xcalloc to record bytes allocated. */ |
605 | ||
606 | static void * | |
607 | gcalloc (size_t nelem, size_t elsize) | |
608 | { | |
609 | bytes_used += nelem * elsize; | |
610 | return xcalloc (nelem, elsize); | |
611 | } | |
612 | ||
7cdd3716 | 613 | /* Cover function to obstack_alloc. */ |
18aa2adf | 614 | |
f0af5a88 | 615 | static void * |
952f0048 | 616 | gcse_alloc (unsigned long size) |
18aa2adf | 617 | { |
7cdd3716 | 618 | bytes_used += size; |
f0af5a88 | 619 | return obstack_alloc (&gcse_obstack, size); |
18aa2adf | 620 | } |
621 | ||
2e81afe5 | 622 | /* Allocate memory for the reg/memory set tracking tables. |
18aa2adf | 623 | This is called at the start of each pass. */ |
624 | ||
625 | static void | |
defc8016 | 626 | alloc_gcse_mem (void) |
18aa2adf | 627 | { |
18aa2adf | 628 | /* Allocate vars to track sets of regs. */ |
0f71a633 | 629 | reg_set_bitmap = ALLOC_REG_SET (NULL); |
18aa2adf | 630 | |
8e802be9 | 631 | /* Allocate array to keep a list of insns which modify memory in each |
f1f41a6c | 632 | basic block. The two typedefs are needed to work around the |
633 | pre-processor limitation with template types in macro arguments. */ | |
634 | typedef vec<rtx> vec_rtx_heap; | |
635 | typedef vec<modify_pair> vec_modify_pair_heap; | |
fe672ac0 | 636 | modify_mem_list = GCNEWVEC (vec_rtx_heap, last_basic_block_for_fn (cfun)); |
637 | canon_modify_mem_list = GCNEWVEC (vec_modify_pair_heap, | |
638 | last_basic_block_for_fn (cfun)); | |
27335ffd | 639 | modify_mem_list_set = BITMAP_ALLOC (NULL); |
640 | blocks_with_calls = BITMAP_ALLOC (NULL); | |
18aa2adf | 641 | } |
642 | ||
643 | /* Free memory allocated by alloc_gcse_mem. */ | |
644 | ||
645 | static void | |
952f0048 | 646 | free_gcse_mem (void) |
18aa2adf | 647 | { |
98076867 | 648 | FREE_REG_SET (reg_set_bitmap); |
649 | ||
7fb47f9f | 650 | free_modify_mem_tables (); |
27335ffd | 651 | BITMAP_FREE (modify_mem_list_set); |
652 | BITMAP_FREE (blocks_with_calls); | |
18aa2adf | 653 | } |
c7a3eccf | 654 | \f |
655 | /* Compute the local properties of each recorded expression. | |
2c084240 | 656 | |
657 | Local properties are those that are defined by the block, irrespective of | |
658 | other blocks. | |
c7a3eccf | 659 | |
660 | An expression is transparent in a block if its operands are not modified | |
661 | in the block. | |
662 | ||
663 | An expression is computed (locally available) in a block if it is computed | |
664 | at least once and expression would contain the same value if the | |
665 | computation was moved to the end of the block. | |
666 | ||
667 | An expression is locally anticipatable in a block if it is computed at | |
668 | least once and expression would contain the same value if the computation | |
669 | was moved to the beginning of the block. | |
670 | ||
07abdb66 | 671 | We call this routine for pre and code hoisting. They all compute |
2c084240 | 672 | basically the same information and thus can easily share this code. |
18aa2adf | 673 | |
2c084240 | 674 | TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local |
675 | properties. If NULL, then it is not necessary to compute or record that | |
676 | particular property. | |
c7a3eccf | 677 | |
07abdb66 | 678 | TABLE controls which hash table to look at. */ |
3cfec666 | 679 | |
c7a3eccf | 680 | static void |
b9f02dbb | 681 | compute_local_properties (sbitmap *transp, sbitmap *comp, sbitmap *antloc, |
26dbec0a | 682 | struct hash_table_d *table) |
c7a3eccf | 683 | { |
27cfe3f1 | 684 | unsigned int i; |
3cfec666 | 685 | |
c7a3eccf | 686 | /* Initialize any bitmaps that were passed in. */ |
687 | if (transp) | |
3d5c627e | 688 | { |
fe672ac0 | 689 | bitmap_vector_ones (transp, last_basic_block_for_fn (cfun)); |
3d5c627e | 690 | } |
2c084240 | 691 | |
c7a3eccf | 692 | if (comp) |
fe672ac0 | 693 | bitmap_vector_clear (comp, last_basic_block_for_fn (cfun)); |
c7a3eccf | 694 | if (antloc) |
fe672ac0 | 695 | bitmap_vector_clear (antloc, last_basic_block_for_fn (cfun)); |
c7a3eccf | 696 | |
27cfe3f1 | 697 | for (i = 0; i < table->size; i++) |
18aa2adf | 698 | { |
c7a3eccf | 699 | struct expr *expr; |
700 | ||
27cfe3f1 | 701 | for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash) |
c7a3eccf | 702 | { |
c7a3eccf | 703 | int indx = expr->bitmap_index; |
2c084240 | 704 | struct occr *occr; |
c7a3eccf | 705 | |
706 | /* The expression is transparent in this block if it is not killed. | |
707 | We start by assuming all are transparent [none are killed], and | |
708 | then reset the bits for those that are. */ | |
c7a3eccf | 709 | if (transp) |
07abdb66 | 710 | compute_transp (expr->expr, indx, transp); |
c7a3eccf | 711 | |
712 | /* The occurrences recorded in antic_occr are exactly those that | |
6ef828f9 | 713 | we want to set to nonzero in ANTLOC. */ |
c7a3eccf | 714 | if (antloc) |
2c084240 | 715 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) |
716 | { | |
08b7917c | 717 | bitmap_set_bit (antloc[BLOCK_FOR_INSN (occr->insn)->index], indx); |
c7a3eccf | 718 | |
2c084240 | 719 | /* While we're scanning the table, this is a good place to |
720 | initialize this. */ | |
721 | occr->deleted_p = 0; | |
722 | } | |
c7a3eccf | 723 | |
724 | /* The occurrences recorded in avail_occr are exactly those that | |
6ef828f9 | 725 | we want to set to nonzero in COMP. */ |
c7a3eccf | 726 | if (comp) |
2c084240 | 727 | for (occr = expr->avail_occr; occr != NULL; occr = occr->next) |
728 | { | |
08b7917c | 729 | bitmap_set_bit (comp[BLOCK_FOR_INSN (occr->insn)->index], indx); |
c7a3eccf | 730 | |
2c084240 | 731 | /* While we're scanning the table, this is a good place to |
732 | initialize this. */ | |
733 | occr->copied_p = 0; | |
734 | } | |
c7a3eccf | 735 | |
736 | /* While we're scanning the table, this is a good place to | |
737 | initialize this. */ | |
738 | expr->reaching_reg = 0; | |
739 | } | |
18aa2adf | 740 | } |
18aa2adf | 741 | } |
742 | \f | |
18aa2adf | 743 | /* Hash table support. */ |
744 | ||
eac13465 | 745 | struct reg_avail_info |
746 | { | |
4c26117a | 747 | basic_block last_bb; |
eac13465 | 748 | int first_set; |
749 | int last_set; | |
750 | }; | |
751 | ||
752 | static struct reg_avail_info *reg_avail_info; | |
4c26117a | 753 | static basic_block current_bb; |
18aa2adf | 754 | |
06e2144a | 755 | /* See whether X, the source of a set, is something we want to consider for |
756 | GCSE. */ | |
18aa2adf | 757 | |
758 | static int | |
8b38b150 | 759 | want_to_gcse_p (rtx x, int *max_distance_ptr) |
18aa2adf | 760 | { |
e207fd7a | 761 | #ifdef STACK_REGS |
762 | /* On register stack architectures, don't GCSE constants from the | |
763 | constant pool, as the benefits are often swamped by the overhead | |
764 | of shuffling the register stack between basic blocks. */ | |
765 | if (IS_STACK_MODE (GET_MODE (x))) | |
766 | x = avoid_constant_pool_reference (x); | |
767 | #endif | |
768 | ||
8b38b150 | 769 | /* GCSE'ing constants: |
770 | ||
771 | We do not specifically distinguish between constant and non-constant | |
7013e87c | 772 | expressions in PRE and Hoist. We use set_src_cost below to limit |
8b38b150 | 773 | the maximum distance simple expressions can travel. |
774 | ||
775 | Nevertheless, constants are much easier to GCSE, and, hence, | |
776 | it is easy to overdo the optimizations. Usually, excessive PRE and | |
777 | Hoisting of constant leads to increased register pressure. | |
778 | ||
779 | RA can deal with this by rematerialing some of the constants. | |
780 | Therefore, it is important that the back-end generates sets of constants | |
781 | in a way that allows reload rematerialize them under high register | |
782 | pressure, i.e., a pseudo register with REG_EQUAL to constant | |
783 | is set only once. Failing to do so will result in IRA/reload | |
784 | spilling such constants under high register pressure instead of | |
785 | rematerializing them. */ | |
786 | ||
2c084240 | 787 | switch (GET_CODE (x)) |
18aa2adf | 788 | { |
789 | case REG: | |
790 | case SUBREG: | |
8b38b150 | 791 | case CALL: |
792 | return 0; | |
793 | ||
0349edce | 794 | CASE_CONST_ANY: |
8b38b150 | 795 | if (!doing_code_hoisting_p) |
796 | /* Do not PRE constants. */ | |
797 | return 0; | |
798 | ||
799 | /* FALLTHRU */ | |
18aa2adf | 800 | |
801 | default: | |
8b38b150 | 802 | if (doing_code_hoisting_p) |
803 | /* PRE doesn't implement max_distance restriction. */ | |
804 | { | |
805 | int cost; | |
806 | int max_distance; | |
807 | ||
808 | gcc_assert (!optimize_function_for_speed_p (cfun) | |
809 | && optimize_function_for_size_p (cfun)); | |
7013e87c | 810 | cost = set_src_cost (x, 0); |
8b38b150 | 811 | |
812 | if (cost < COSTS_N_INSNS (GCSE_UNRESTRICTED_COST)) | |
813 | { | |
814 | max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10; | |
815 | if (max_distance == 0) | |
816 | return 0; | |
817 | ||
818 | gcc_assert (max_distance > 0); | |
819 | } | |
820 | else | |
821 | max_distance = 0; | |
822 | ||
823 | if (max_distance_ptr) | |
824 | *max_distance_ptr = max_distance; | |
825 | } | |
826 | ||
4b673aa1 | 827 | return can_assign_to_reg_without_clobbers_p (x); |
18aa2adf | 828 | } |
69dbb666 | 829 | } |
830 | ||
4b673aa1 | 831 | /* Used internally by can_assign_to_reg_without_clobbers_p. */ |
69dbb666 | 832 | |
833 | static GTY(()) rtx test_insn; | |
834 | ||
4b673aa1 | 835 | /* Return true if we can assign X to a pseudo register such that the |
836 | resulting insn does not result in clobbering a hard register as a | |
837 | side-effect. | |
2b86a75a | 838 | |
839 | Additionally, if the target requires it, check that the resulting insn | |
840 | can be copied. If it cannot, this means that X is special and probably | |
841 | has hidden side-effects we don't want to mess with. | |
842 | ||
4b673aa1 | 843 | This function is typically used by code motion passes, to verify |
844 | that it is safe to insert an insn without worrying about clobbering | |
845 | maybe live hard regs. */ | |
69dbb666 | 846 | |
4b673aa1 | 847 | bool |
848 | can_assign_to_reg_without_clobbers_p (rtx x) | |
69dbb666 | 849 | { |
850 | int num_clobbers = 0; | |
851 | int icode; | |
18aa2adf | 852 | |
06e2144a | 853 | /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */ |
854 | if (general_operand (x, GET_MODE (x))) | |
855 | return 1; | |
856 | else if (GET_MODE (x) == VOIDmode) | |
857 | return 0; | |
858 | ||
859 | /* Otherwise, check if we can make a valid insn from it. First initialize | |
860 | our test insn if we haven't already. */ | |
861 | if (test_insn == 0) | |
862 | { | |
863 | test_insn | |
864 | = make_insn_raw (gen_rtx_SET (VOIDmode, | |
865 | gen_rtx_REG (word_mode, | |
866 | FIRST_PSEUDO_REGISTER * 2), | |
867 | const0_rtx)); | |
868 | NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0; | |
06e2144a | 869 | } |
870 | ||
871 | /* Now make an insn like the one we would make when GCSE'ing and see if | |
872 | valid. */ | |
873 | PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x)); | |
874 | SET_SRC (PATTERN (test_insn)) = x; | |
48e1416a | 875 | |
2b86a75a | 876 | icode = recog (PATTERN (test_insn), test_insn, &num_clobbers); |
877 | if (icode < 0) | |
878 | return false; | |
48e1416a | 879 | |
2b86a75a | 880 | if (num_clobbers > 0 && added_clobbers_hard_reg_p (icode)) |
881 | return false; | |
48e1416a | 882 | |
2b86a75a | 883 | if (targetm.cannot_copy_insn_p && targetm.cannot_copy_insn_p (test_insn)) |
884 | return false; | |
48e1416a | 885 | |
2b86a75a | 886 | return true; |
18aa2adf | 887 | } |
888 | ||
6ef828f9 | 889 | /* Return nonzero if the operands of expression X are unchanged from the |
18aa2adf | 890 | start of INSN's basic block up to but not including INSN (if AVAIL_P == 0), |
891 | or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */ | |
892 | ||
893 | static int | |
7ecb5bb2 | 894 | oprs_unchanged_p (const_rtx x, const_rtx insn, int avail_p) |
18aa2adf | 895 | { |
2c084240 | 896 | int i, j; |
18aa2adf | 897 | enum rtx_code code; |
d2ca078f | 898 | const char *fmt; |
18aa2adf | 899 | |
18aa2adf | 900 | if (x == 0) |
901 | return 1; | |
902 | ||
903 | code = GET_CODE (x); | |
904 | switch (code) | |
905 | { | |
906 | case REG: | |
eac13465 | 907 | { |
908 | struct reg_avail_info *info = ®_avail_info[REGNO (x)]; | |
909 | ||
910 | if (info->last_bb != current_bb) | |
911 | return 1; | |
3cfec666 | 912 | if (avail_p) |
2e81afe5 | 913 | return info->last_set < DF_INSN_LUID (insn); |
eac13465 | 914 | else |
2e81afe5 | 915 | return info->first_set >= DF_INSN_LUID (insn); |
eac13465 | 916 | } |
18aa2adf | 917 | |
918 | case MEM: | |
37495d69 | 919 | if (! flag_gcse_lm |
920 | || load_killed_in_block_p (current_bb, DF_INSN_LUID (insn), | |
921 | x, avail_p)) | |
8e802be9 | 922 | return 0; |
18aa2adf | 923 | else |
2c084240 | 924 | return oprs_unchanged_p (XEXP (x, 0), insn, avail_p); |
18aa2adf | 925 | |
926 | case PRE_DEC: | |
927 | case PRE_INC: | |
928 | case POST_DEC: | |
929 | case POST_INC: | |
40988080 | 930 | case PRE_MODIFY: |
931 | case POST_MODIFY: | |
18aa2adf | 932 | return 0; |
933 | ||
934 | case PC: | |
935 | case CC0: /*FIXME*/ | |
936 | case CONST: | |
0349edce | 937 | CASE_CONST_ANY: |
18aa2adf | 938 | case SYMBOL_REF: |
939 | case LABEL_REF: | |
940 | case ADDR_VEC: | |
941 | case ADDR_DIFF_VEC: | |
942 | return 1; | |
943 | ||
944 | default: | |
945 | break; | |
946 | } | |
947 | ||
2c084240 | 948 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--) |
18aa2adf | 949 | { |
950 | if (fmt[i] == 'e') | |
951 | { | |
2c084240 | 952 | /* If we are about to do the last recursive call needed at this |
953 | level, change it into iteration. This function is called enough | |
954 | to be worth it. */ | |
18aa2adf | 955 | if (i == 0) |
2c084240 | 956 | return oprs_unchanged_p (XEXP (x, i), insn, avail_p); |
957 | ||
958 | else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p)) | |
18aa2adf | 959 | return 0; |
960 | } | |
961 | else if (fmt[i] == 'E') | |
2c084240 | 962 | for (j = 0; j < XVECLEN (x, i); j++) |
963 | if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p)) | |
964 | return 0; | |
18aa2adf | 965 | } |
966 | ||
967 | return 1; | |
968 | } | |
969 | ||
bc8197c0 | 970 | /* Info passed from load_killed_in_block_p to mems_conflict_for_gcse_p. */ |
8e802be9 | 971 | |
bc8197c0 | 972 | struct mem_conflict_info |
973 | { | |
974 | /* A memory reference for a load instruction, mems_conflict_for_gcse_p will | |
975 | see if a memory store conflicts with this memory load. */ | |
976 | const_rtx mem; | |
8e802be9 | 977 | |
bc8197c0 | 978 | /* True if mems_conflict_for_gcse_p finds a conflict between two memory |
979 | references. */ | |
980 | bool conflict; | |
981 | }; | |
982 | ||
983 | /* DEST is the output of an instruction. If it is a memory reference and | |
984 | possibly conflicts with the load found in DATA, then communicate this | |
985 | information back through DATA. */ | |
8e802be9 | 986 | |
987 | static void | |
81a410b1 | 988 | mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, |
bc8197c0 | 989 | void *data) |
8e802be9 | 990 | { |
bc8197c0 | 991 | struct mem_conflict_info *mci = (struct mem_conflict_info *) data; |
992 | ||
8e802be9 | 993 | while (GET_CODE (dest) == SUBREG |
994 | || GET_CODE (dest) == ZERO_EXTRACT | |
8e802be9 | 995 | || GET_CODE (dest) == STRICT_LOW_PART) |
996 | dest = XEXP (dest, 0); | |
997 | ||
998 | /* If DEST is not a MEM, then it will not conflict with the load. Note | |
999 | that function calls are assumed to clobber memory, but are handled | |
1000 | elsewhere. */ | |
b9f02dbb | 1001 | if (! MEM_P (dest)) |
8e802be9 | 1002 | return; |
7a676a9f | 1003 | |
8e802be9 | 1004 | /* If we are setting a MEM in our list of specially recognized MEMs, |
3cfec666 | 1005 | don't mark as killed this time. */ |
bc8197c0 | 1006 | if (pre_ldst_mems != NULL && expr_equiv_p (dest, mci->mem)) |
8e802be9 | 1007 | { |
1008 | if (!find_rtx_in_ldst (dest)) | |
bc8197c0 | 1009 | mci->conflict = true; |
8e802be9 | 1010 | return; |
1011 | } | |
7a676a9f | 1012 | |
376a287d | 1013 | if (true_dependence (dest, GET_MODE (dest), mci->mem)) |
bc8197c0 | 1014 | mci->conflict = true; |
8e802be9 | 1015 | } |
1016 | ||
1017 | /* Return nonzero if the expression in X (a memory reference) is killed | |
2e81afe5 | 1018 | in block BB before or after the insn with the LUID in UID_LIMIT. |
8e802be9 | 1019 | AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills |
1020 | before UID_LIMIT. | |
1021 | ||
1022 | To check the entire block, set UID_LIMIT to max_uid + 1 and | |
1023 | AVAIL_P to 0. */ | |
1024 | ||
1025 | static int | |
bc8197c0 | 1026 | load_killed_in_block_p (const_basic_block bb, int uid_limit, const_rtx x, |
1027 | int avail_p) | |
8e802be9 | 1028 | { |
f1f41a6c | 1029 | vec<rtx> list = modify_mem_list[bb->index]; |
577cca34 | 1030 | rtx setter; |
1031 | unsigned ix; | |
a2658f4a | 1032 | |
1033 | /* If this is a readonly then we aren't going to be changing it. */ | |
1034 | if (MEM_READONLY_P (x)) | |
1035 | return 0; | |
1036 | ||
f1f41a6c | 1037 | FOR_EACH_VEC_ELT_REVERSE (list, ix, setter) |
8e802be9 | 1038 | { |
bc8197c0 | 1039 | struct mem_conflict_info mci; |
1040 | ||
8e802be9 | 1041 | /* Ignore entries in the list that do not apply. */ |
1042 | if ((avail_p | |
577cca34 | 1043 | && DF_INSN_LUID (setter) < uid_limit) |
8e802be9 | 1044 | || (! avail_p |
577cca34 | 1045 | && DF_INSN_LUID (setter) > uid_limit)) |
1046 | continue; | |
8e802be9 | 1047 | |
1048 | /* If SETTER is a call everything is clobbered. Note that calls | |
1049 | to pure functions are never put on the list, so we need not | |
1050 | worry about them. */ | |
b9f02dbb | 1051 | if (CALL_P (setter)) |
8e802be9 | 1052 | return 1; |
1053 | ||
1054 | /* SETTER must be an INSN of some kind that sets memory. Call | |
bc8197c0 | 1055 | note_stores to examine each hunk of memory that is modified. */ |
1056 | mci.mem = x; | |
1057 | mci.conflict = false; | |
1058 | note_stores (PATTERN (setter), mems_conflict_for_gcse_p, &mci); | |
1059 | if (mci.conflict) | |
8e802be9 | 1060 | return 1; |
8e802be9 | 1061 | } |
1062 | return 0; | |
1063 | } | |
1064 | ||
6ef828f9 | 1065 | /* Return nonzero if the operands of expression X are unchanged from |
18aa2adf | 1066 | the start of INSN's basic block up to but not including INSN. */ |
1067 | ||
1068 | static int | |
7ecb5bb2 | 1069 | oprs_anticipatable_p (const_rtx x, const_rtx insn) |
18aa2adf | 1070 | { |
1071 | return oprs_unchanged_p (x, insn, 0); | |
1072 | } | |
1073 | ||
6ef828f9 | 1074 | /* Return nonzero if the operands of expression X are unchanged from |
18aa2adf | 1075 | INSN to the end of INSN's basic block. */ |
1076 | ||
1077 | static int | |
7ecb5bb2 | 1078 | oprs_available_p (const_rtx x, const_rtx insn) |
18aa2adf | 1079 | { |
1080 | return oprs_unchanged_p (x, insn, 1); | |
1081 | } | |
1082 | ||
1083 | /* Hash expression X. | |
2c084240 | 1084 | |
1085 | MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean | |
1086 | indicating if a volatile operand is found or if the expression contains | |
69333952 | 1087 | something we don't want to insert in the table. HASH_TABLE_SIZE is |
78d140c9 | 1088 | the current size of the hash table to be probed. */ |
18aa2adf | 1089 | |
1090 | static unsigned int | |
7ecb5bb2 | 1091 | hash_expr (const_rtx x, enum machine_mode mode, int *do_not_record_p, |
69333952 | 1092 | int hash_table_size) |
18aa2adf | 1093 | { |
1094 | unsigned int hash; | |
1095 | ||
1096 | *do_not_record_p = 0; | |
1097 | ||
bc8197c0 | 1098 | hash = hash_rtx (x, mode, do_not_record_p, NULL, /*have_reg_qty=*/false); |
18aa2adf | 1099 | return hash % hash_table_size; |
1100 | } | |
1b80ba05 | 1101 | |
78d140c9 | 1102 | /* Return nonzero if exp1 is equivalent to exp2. */ |
18aa2adf | 1103 | |
1104 | static int | |
7ecb5bb2 | 1105 | expr_equiv_p (const_rtx x, const_rtx y) |
18aa2adf | 1106 | { |
78d140c9 | 1107 | return exp_equiv_p (x, y, 0, true); |
18aa2adf | 1108 | } |
1109 | ||
27cfe3f1 | 1110 | /* Insert expression X in INSN in the hash TABLE. |
18aa2adf | 1111 | If it is already present, record it as the last occurrence in INSN's |
1112 | basic block. | |
1113 | ||
1114 | MODE is the mode of the value X is being stored into. | |
1115 | It is only used if X is a CONST_INT. | |
1116 | ||
6ef828f9 | 1117 | ANTIC_P is nonzero if X is an anticipatable expression. |
8b38b150 | 1118 | AVAIL_P is nonzero if X is an available expression. |
1119 | ||
1120 | MAX_DISTANCE is the maximum distance in instructions this expression can | |
1121 | be moved. */ | |
18aa2adf | 1122 | |
1123 | static void | |
952f0048 | 1124 | insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p, |
8b38b150 | 1125 | int avail_p, int max_distance, struct hash_table_d *table) |
18aa2adf | 1126 | { |
1127 | int found, do_not_record_p; | |
1128 | unsigned int hash; | |
1129 | struct expr *cur_expr, *last_expr = NULL; | |
1130 | struct occr *antic_occr, *avail_occr; | |
18aa2adf | 1131 | |
27cfe3f1 | 1132 | hash = hash_expr (x, mode, &do_not_record_p, table->size); |
18aa2adf | 1133 | |
1134 | /* Do not insert expression in table if it contains volatile operands, | |
1135 | or if hash_expr determines the expression is something we don't want | |
1136 | to or can't handle. */ | |
1137 | if (do_not_record_p) | |
1138 | return; | |
1139 | ||
27cfe3f1 | 1140 | cur_expr = table->table[hash]; |
18aa2adf | 1141 | found = 0; |
1142 | ||
2c084240 | 1143 | while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x))) |
18aa2adf | 1144 | { |
1145 | /* If the expression isn't found, save a pointer to the end of | |
1146 | the list. */ | |
1147 | last_expr = cur_expr; | |
1148 | cur_expr = cur_expr->next_same_hash; | |
1149 | } | |
1150 | ||
1151 | if (! found) | |
1152 | { | |
2457c754 | 1153 | cur_expr = GOBNEW (struct expr); |
18aa2adf | 1154 | bytes_used += sizeof (struct expr); |
27cfe3f1 | 1155 | if (table->table[hash] == NULL) |
2c084240 | 1156 | /* This is the first pattern that hashed to this index. */ |
27cfe3f1 | 1157 | table->table[hash] = cur_expr; |
18aa2adf | 1158 | else |
2c084240 | 1159 | /* Add EXPR to end of this hash chain. */ |
1160 | last_expr->next_same_hash = cur_expr; | |
1161 | ||
3cfec666 | 1162 | /* Set the fields of the expr element. */ |
18aa2adf | 1163 | cur_expr->expr = x; |
27cfe3f1 | 1164 | cur_expr->bitmap_index = table->n_elems++; |
18aa2adf | 1165 | cur_expr->next_same_hash = NULL; |
1166 | cur_expr->antic_occr = NULL; | |
1167 | cur_expr->avail_occr = NULL; | |
8b38b150 | 1168 | gcc_assert (max_distance >= 0); |
1169 | cur_expr->max_distance = max_distance; | |
18aa2adf | 1170 | } |
8b38b150 | 1171 | else |
1172 | gcc_assert (cur_expr->max_distance == max_distance); | |
18aa2adf | 1173 | |
1174 | /* Now record the occurrence(s). */ | |
18aa2adf | 1175 | if (antic_p) |
1176 | { | |
1177 | antic_occr = cur_expr->antic_occr; | |
1178 | ||
90bd219d | 1179 | if (antic_occr |
1180 | && BLOCK_FOR_INSN (antic_occr->insn) != BLOCK_FOR_INSN (insn)) | |
77780ba6 | 1181 | antic_occr = NULL; |
18aa2adf | 1182 | |
1183 | if (antic_occr) | |
2c084240 | 1184 | /* Found another instance of the expression in the same basic block. |
1185 | Prefer the currently recorded one. We want the first one in the | |
1186 | block and the block is scanned from start to end. */ | |
1187 | ; /* nothing to do */ | |
18aa2adf | 1188 | else |
1189 | { | |
1190 | /* First occurrence of this expression in this basic block. */ | |
2457c754 | 1191 | antic_occr = GOBNEW (struct occr); |
18aa2adf | 1192 | bytes_used += sizeof (struct occr); |
18aa2adf | 1193 | antic_occr->insn = insn; |
77780ba6 | 1194 | antic_occr->next = cur_expr->antic_occr; |
839f8415 | 1195 | antic_occr->deleted_p = 0; |
77780ba6 | 1196 | cur_expr->antic_occr = antic_occr; |
18aa2adf | 1197 | } |
1198 | } | |
1199 | ||
1200 | if (avail_p) | |
1201 | { | |
1202 | avail_occr = cur_expr->avail_occr; | |
1203 | ||
90bd219d | 1204 | if (avail_occr |
1205 | && BLOCK_FOR_INSN (avail_occr->insn) == BLOCK_FOR_INSN (insn)) | |
18aa2adf | 1206 | { |
77780ba6 | 1207 | /* Found another instance of the expression in the same basic block. |
1208 | Prefer this occurrence to the currently recorded one. We want | |
1209 | the last one in the block and the block is scanned from start | |
1210 | to end. */ | |
1211 | avail_occr->insn = insn; | |
18aa2adf | 1212 | } |
18aa2adf | 1213 | else |
1214 | { | |
1215 | /* First occurrence of this expression in this basic block. */ | |
2457c754 | 1216 | avail_occr = GOBNEW (struct occr); |
18aa2adf | 1217 | bytes_used += sizeof (struct occr); |
18aa2adf | 1218 | avail_occr->insn = insn; |
77780ba6 | 1219 | avail_occr->next = cur_expr->avail_occr; |
839f8415 | 1220 | avail_occr->deleted_p = 0; |
77780ba6 | 1221 | cur_expr->avail_occr = avail_occr; |
18aa2adf | 1222 | } |
1223 | } | |
1224 | } | |
1225 | ||
bc8197c0 | 1226 | /* Scan SET present in INSN and add an entry to the hash TABLE. */ |
18aa2adf | 1227 | |
1228 | static void | |
bc8197c0 | 1229 | hash_scan_set (rtx set, rtx insn, struct hash_table_d *table) |
18aa2adf | 1230 | { |
bc8197c0 | 1231 | rtx src = SET_SRC (set); |
1232 | rtx dest = SET_DEST (set); | |
1b80ba05 | 1233 | rtx note; |
18aa2adf | 1234 | |
19595145 | 1235 | if (GET_CODE (src) == CALL) |
27cfe3f1 | 1236 | hash_scan_call (src, insn, table); |
18aa2adf | 1237 | |
b9f02dbb | 1238 | else if (REG_P (dest)) |
18aa2adf | 1239 | { |
1b80ba05 | 1240 | unsigned int regno = REGNO (dest); |
8b38b150 | 1241 | int max_distance = 0; |
18aa2adf | 1242 | |
ad6cd748 | 1243 | /* See if a REG_EQUAL note shows this equivalent to a simpler expression. |
1244 | ||
59254d98 | 1245 | This allows us to do a single GCSE pass and still eliminate |
1246 | redundant constants, addresses or other expressions that are | |
ad6cd748 | 1247 | constructed with multiple instructions. |
1248 | ||
07abdb66 | 1249 | However, keep the original SRC if INSN is a simple reg-reg move. |
ad6cd748 | 1250 | In this case, there will almost always be a REG_EQUAL note on the |
1251 | insn that sets SRC. By recording the REG_EQUAL value here as SRC | |
1252 | for INSN, we miss copy propagation opportunities and we perform the | |
1253 | same PRE GCSE operation repeatedly on the same REG_EQUAL value if we | |
1254 | do more than one PRE GCSE pass. | |
1255 | ||
f0b5f617 | 1256 | Note that this does not impede profitable constant propagations. We |
ad6cd748 | 1257 | "look through" reg-reg sets in lookup_avail_set. */ |
59254d98 | 1258 | note = find_reg_equal_equiv_note (insn); |
1259 | if (note != 0 | |
ad6cd748 | 1260 | && REG_NOTE_KIND (note) == REG_EQUAL |
1261 | && !REG_P (src) | |
07abdb66 | 1262 | && want_to_gcse_p (XEXP (note, 0), NULL)) |
bc8197c0 | 1263 | src = XEXP (note, 0), set = gen_rtx_SET (VOIDmode, dest, src); |
1b80ba05 | 1264 | |
18aa2adf | 1265 | /* Only record sets of pseudo-regs in the hash table. */ |
07abdb66 | 1266 | if (regno >= FIRST_PSEUDO_REGISTER |
18aa2adf | 1267 | /* Don't GCSE something if we can't do a reg/reg copy. */ |
3d055936 | 1268 | && can_copy_p (GET_MODE (dest)) |
17a54dac | 1269 | /* GCSE commonly inserts instruction after the insn. We can't |
e38def9c | 1270 | do that easily for EH edges so disable GCSE on these for now. */ |
1271 | /* ??? We can now easily create new EH landing pads at the | |
1272 | gimple level, for splitting edges; there's no reason we | |
1273 | can't do the same thing at the rtl level. */ | |
1274 | && !can_throw_internal (insn) | |
18aa2adf | 1275 | /* Is SET_SRC something we want to gcse? */ |
8b38b150 | 1276 | && want_to_gcse_p (src, &max_distance) |
1b80ba05 | 1277 | /* Don't CSE a nop. */ |
bc8197c0 | 1278 | && ! set_noop_p (set) |
75f84104 | 1279 | /* Don't GCSE if it has attached REG_EQUIV note. |
1280 | At this point this only function parameters should have | |
1281 | REG_EQUIV notes and if the argument slot is used somewhere | |
3fb1e43b | 1282 | explicitly, it means address of parameter has been taken, |
75f84104 | 1283 | so we should not extend the lifetime of the pseudo. */ |
59254d98 | 1284 | && (note == NULL_RTX || ! MEM_P (XEXP (note, 0)))) |
18aa2adf | 1285 | { |
1286 | /* An expression is not anticipatable if its operands are | |
232bbfff | 1287 | modified before this insn or if this is not the only SET in |
3072d30e | 1288 | this insn. The latter condition does not have to mean that |
1289 | SRC itself is not anticipatable, but we just will not be | |
1290 | able to handle code motion of insns with multiple sets. */ | |
1291 | int antic_p = oprs_anticipatable_p (src, insn) | |
1292 | && !multiple_sets (insn); | |
18aa2adf | 1293 | /* An expression is not available if its operands are |
f441a382 | 1294 | subsequently modified, including this insn. It's also not |
1295 | available if this is a branch, because we can't insert | |
1296 | a set after the branch. */ | |
1297 | int avail_p = (oprs_available_p (src, insn) | |
1298 | && ! JUMP_P (insn)); | |
2c084240 | 1299 | |
8b38b150 | 1300 | insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, |
1301 | max_distance, table); | |
18aa2adf | 1302 | } |
18aa2adf | 1303 | } |
40e55fbb | 1304 | /* In case of store we want to consider the memory value as available in |
5c47e414 | 1305 | the REG stored in that memory. This makes it possible to remove |
1306 | redundant loads from due to stores to the same location. */ | |
b9f02dbb | 1307 | else if (flag_gcse_las && REG_P (src) && MEM_P (dest)) |
5c47e414 | 1308 | { |
1309 | unsigned int regno = REGNO (src); | |
02540644 | 1310 | int max_distance = 0; |
5c47e414 | 1311 | |
07abdb66 | 1312 | /* Only record sets of pseudo-regs in the hash table. */ |
1313 | if (regno >= FIRST_PSEUDO_REGISTER | |
5c47e414 | 1314 | /* Don't GCSE something if we can't do a reg/reg copy. */ |
1315 | && can_copy_p (GET_MODE (src)) | |
1316 | /* GCSE commonly inserts instruction after the insn. We can't | |
e38def9c | 1317 | do that easily for EH edges so disable GCSE on these for now. */ |
1318 | && !can_throw_internal (insn) | |
5c47e414 | 1319 | /* Is SET_DEST something we want to gcse? */ |
02540644 | 1320 | && want_to_gcse_p (dest, &max_distance) |
5c47e414 | 1321 | /* Don't CSE a nop. */ |
bc8197c0 | 1322 | && ! set_noop_p (set) |
5c47e414 | 1323 | /* Don't GCSE if it has attached REG_EQUIV note. |
1324 | At this point this only function parameters should have | |
1325 | REG_EQUIV notes and if the argument slot is used somewhere | |
1326 | explicitly, it means address of parameter has been taken, | |
1327 | so we should not extend the lifetime of the pseudo. */ | |
1328 | && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0 | |
b9f02dbb | 1329 | || ! MEM_P (XEXP (note, 0)))) |
5c47e414 | 1330 | { |
1331 | /* Stores are never anticipatable. */ | |
1332 | int antic_p = 0; | |
1333 | /* An expression is not available if its operands are | |
1334 | subsequently modified, including this insn. It's also not | |
1335 | available if this is a branch, because we can't insert | |
1336 | a set after the branch. */ | |
1337 | int avail_p = oprs_available_p (dest, insn) | |
1338 | && ! JUMP_P (insn); | |
1339 | ||
1340 | /* Record the memory expression (DEST) in the hash table. */ | |
716ad11c | 1341 | insert_expr_in_table (dest, GET_MODE (dest), insn, |
02540644 | 1342 | antic_p, avail_p, max_distance, table); |
5c47e414 | 1343 | } |
1344 | } | |
18aa2adf | 1345 | } |
1346 | ||
1347 | static void | |
952f0048 | 1348 | hash_scan_clobber (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED, |
26dbec0a | 1349 | struct hash_table_d *table ATTRIBUTE_UNUSED) |
18aa2adf | 1350 | { |
1351 | /* Currently nothing to do. */ | |
1352 | } | |
1353 | ||
1354 | static void | |
952f0048 | 1355 | hash_scan_call (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED, |
26dbec0a | 1356 | struct hash_table_d *table ATTRIBUTE_UNUSED) |
18aa2adf | 1357 | { |
1358 | /* Currently nothing to do. */ | |
1359 | } | |
1360 | ||
bc8197c0 | 1361 | /* Process INSN and add hash table entries as appropriate. */ |
18aa2adf | 1362 | |
1363 | static void | |
26dbec0a | 1364 | hash_scan_insn (rtx insn, struct hash_table_d *table) |
18aa2adf | 1365 | { |
1366 | rtx pat = PATTERN (insn); | |
2c084240 | 1367 | int i; |
18aa2adf | 1368 | |
1369 | /* Pick out the sets of INSN and for other forms of instructions record | |
1370 | what's been modified. */ | |
1371 | ||
1b80ba05 | 1372 | if (GET_CODE (pat) == SET) |
27cfe3f1 | 1373 | hash_scan_set (pat, insn, table); |
bc8197c0 | 1374 | |
1375 | else if (GET_CODE (pat) == CLOBBER) | |
1376 | hash_scan_clobber (pat, insn, table); | |
1377 | ||
1378 | else if (GET_CODE (pat) == CALL) | |
1379 | hash_scan_call (pat, insn, table); | |
1380 | ||
18aa2adf | 1381 | else if (GET_CODE (pat) == PARALLEL) |
2c084240 | 1382 | for (i = 0; i < XVECLEN (pat, 0); i++) |
1383 | { | |
1384 | rtx x = XVECEXP (pat, 0, i); | |
18aa2adf | 1385 | |
2c084240 | 1386 | if (GET_CODE (x) == SET) |
27cfe3f1 | 1387 | hash_scan_set (x, insn, table); |
2c084240 | 1388 | else if (GET_CODE (x) == CLOBBER) |
27cfe3f1 | 1389 | hash_scan_clobber (x, insn, table); |
19595145 | 1390 | else if (GET_CODE (x) == CALL) |
27cfe3f1 | 1391 | hash_scan_call (x, insn, table); |
2c084240 | 1392 | } |
18aa2adf | 1393 | } |
1394 | ||
bc8197c0 | 1395 | /* Dump the hash table TABLE to file FILE under the name NAME. */ |
1396 | ||
18aa2adf | 1397 | static void |
26dbec0a | 1398 | dump_hash_table (FILE *file, const char *name, struct hash_table_d *table) |
18aa2adf | 1399 | { |
1400 | int i; | |
1401 | /* Flattened out table, so it's printed in proper order. */ | |
b9cf3f63 | 1402 | struct expr **flat_table; |
1403 | unsigned int *hash_val; | |
2c084240 | 1404 | struct expr *expr; |
b9cf3f63 | 1405 | |
2457c754 | 1406 | flat_table = XCNEWVEC (struct expr *, table->n_elems); |
1407 | hash_val = XNEWVEC (unsigned int, table->n_elems); | |
18aa2adf | 1408 | |
27cfe3f1 | 1409 | for (i = 0; i < (int) table->size; i++) |
1410 | for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash) | |
2c084240 | 1411 | { |
1412 | flat_table[expr->bitmap_index] = expr; | |
1413 | hash_val[expr->bitmap_index] = i; | |
1414 | } | |
18aa2adf | 1415 | |
1416 | fprintf (file, "%s hash table (%d buckets, %d entries)\n", | |
27cfe3f1 | 1417 | name, table->size, table->n_elems); |
18aa2adf | 1418 | |
27cfe3f1 | 1419 | for (i = 0; i < (int) table->n_elems; i++) |
46fd7177 | 1420 | if (flat_table[i] != 0) |
1421 | { | |
b16f1e6c | 1422 | expr = flat_table[i]; |
8b38b150 | 1423 | fprintf (file, "Index %d (hash value %d; max distance %d)\n ", |
1424 | expr->bitmap_index, hash_val[i], expr->max_distance); | |
b16f1e6c | 1425 | print_rtl (file, expr->expr); |
46fd7177 | 1426 | fprintf (file, "\n"); |
1427 | } | |
18aa2adf | 1428 | |
1429 | fprintf (file, "\n"); | |
b9cf3f63 | 1430 | |
b9cf3f63 | 1431 | free (flat_table); |
1432 | free (hash_val); | |
18aa2adf | 1433 | } |
1434 | ||
1435 | /* Record register first/last/block set information for REGNO in INSN. | |
2c084240 | 1436 | |
eac13465 | 1437 | first_set records the first place in the block where the register |
18aa2adf | 1438 | is set and is used to compute "anticipatability". |
2c084240 | 1439 | |
eac13465 | 1440 | last_set records the last place in the block where the register |
18aa2adf | 1441 | is set and is used to compute "availability". |
2c084240 | 1442 | |
eac13465 | 1443 | last_bb records the block for which first_set and last_set are |
2e81afe5 | 1444 | valid, as a quick test to invalidate them. */ |
18aa2adf | 1445 | |
1446 | static void | |
952f0048 | 1447 | record_last_reg_set_info (rtx insn, int regno) |
18aa2adf | 1448 | { |
eac13465 | 1449 | struct reg_avail_info *info = ®_avail_info[regno]; |
2e81afe5 | 1450 | int luid = DF_INSN_LUID (insn); |
2c084240 | 1451 | |
2e81afe5 | 1452 | info->last_set = luid; |
eac13465 | 1453 | if (info->last_bb != current_bb) |
1454 | { | |
1455 | info->last_bb = current_bb; | |
2e81afe5 | 1456 | info->first_set = luid; |
eac13465 | 1457 | } |
18aa2adf | 1458 | } |
1459 | ||
8e802be9 | 1460 | /* Record all of the canonicalized MEMs of record_last_mem_set_info's insn. |
1461 | Note we store a pair of elements in the list, so they have to be | |
1462 | taken off pairwise. */ | |
1463 | ||
3cfec666 | 1464 | static void |
bc8197c0 | 1465 | canon_list_insert (rtx dest ATTRIBUTE_UNUSED, const_rtx x ATTRIBUTE_UNUSED, |
952f0048 | 1466 | void * v_insn) |
8e802be9 | 1467 | { |
1468 | rtx dest_addr, insn; | |
d7b592b0 | 1469 | int bb; |
e82e4eb5 | 1470 | modify_pair pair; |
8e802be9 | 1471 | |
1472 | while (GET_CODE (dest) == SUBREG | |
1473 | || GET_CODE (dest) == ZERO_EXTRACT | |
8e802be9 | 1474 | || GET_CODE (dest) == STRICT_LOW_PART) |
1475 | dest = XEXP (dest, 0); | |
1476 | ||
1477 | /* If DEST is not a MEM, then it will not conflict with a load. Note | |
1478 | that function calls are assumed to clobber memory, but are handled | |
1479 | elsewhere. */ | |
1480 | ||
b9f02dbb | 1481 | if (! MEM_P (dest)) |
8e802be9 | 1482 | return; |
1483 | ||
1484 | dest_addr = get_addr (XEXP (dest, 0)); | |
1485 | dest_addr = canon_rtx (dest_addr); | |
3cfec666 | 1486 | insn = (rtx) v_insn; |
90bd219d | 1487 | bb = BLOCK_FOR_INSN (insn)->index; |
8e802be9 | 1488 | |
e82e4eb5 | 1489 | pair.dest = dest; |
1490 | pair.dest_addr = dest_addr; | |
f1f41a6c | 1491 | canon_modify_mem_list[bb].safe_push (pair); |
8e802be9 | 1492 | } |
1493 | ||
8e802be9 | 1494 | /* Record memory modification information for INSN. We do not actually care |
1495 | about the memory location(s) that are set, or even how they are set (consider | |
1496 | a CALL_INSN). We merely need to record which insns modify memory. */ | |
18aa2adf | 1497 | |
1498 | static void | |
952f0048 | 1499 | record_last_mem_set_info (rtx insn) |
18aa2adf | 1500 | { |
37495d69 | 1501 | int bb; |
1502 | ||
1503 | if (! flag_gcse_lm) | |
1504 | return; | |
d7b592b0 | 1505 | |
45b51429 | 1506 | /* load_killed_in_block_p will handle the case of calls clobbering |
aa40f561 | 1507 | everything. */ |
37495d69 | 1508 | bb = BLOCK_FOR_INSN (insn)->index; |
f1f41a6c | 1509 | modify_mem_list[bb].safe_push (insn); |
d7b592b0 | 1510 | bitmap_set_bit (modify_mem_list_set, bb); |
8e802be9 | 1511 | |
b9f02dbb | 1512 | if (CALL_P (insn)) |
57c8e46c | 1513 | bitmap_set_bit (blocks_with_calls, bb); |
8e802be9 | 1514 | else |
d7b592b0 | 1515 | note_stores (PATTERN (insn), canon_list_insert, (void*) insn); |
18aa2adf | 1516 | } |
1517 | ||
18aa2adf | 1518 | /* Called from compute_hash_table via note_stores to handle one |
ec8895d7 | 1519 | SET or CLOBBER in an insn. DATA is really the instruction in which |
1520 | the SET is taking place. */ | |
18aa2adf | 1521 | |
1522 | static void | |
81a410b1 | 1523 | record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data) |
18aa2adf | 1524 | { |
ec8895d7 | 1525 | rtx last_set_insn = (rtx) data; |
1526 | ||
18aa2adf | 1527 | if (GET_CODE (dest) == SUBREG) |
1528 | dest = SUBREG_REG (dest); | |
1529 | ||
b9f02dbb | 1530 | if (REG_P (dest)) |
18aa2adf | 1531 | record_last_reg_set_info (last_set_insn, REGNO (dest)); |
b9f02dbb | 1532 | else if (MEM_P (dest) |
18aa2adf | 1533 | /* Ignore pushes, they clobber nothing. */ |
1534 | && ! push_operand (dest, GET_MODE (dest))) | |
1535 | record_last_mem_set_info (last_set_insn); | |
1536 | } | |
1537 | ||
07abdb66 | 1538 | /* Top level function to create an expression hash table. |
18aa2adf | 1539 | |
1540 | Expression entries are placed in the hash table if | |
1541 | - they are of the form (set (pseudo-reg) src), | |
1542 | - src is something we want to perform GCSE on, | |
1543 | - none of the operands are subsequently modified in the block | |
1544 | ||
18aa2adf | 1545 | Currently src must be a pseudo-reg or a const_int. |
1546 | ||
27cfe3f1 | 1547 | TABLE is the table computed. */ |
18aa2adf | 1548 | |
1549 | static void | |
26dbec0a | 1550 | compute_hash_table_work (struct hash_table_d *table) |
18aa2adf | 1551 | { |
d743aba2 | 1552 | int i; |
18aa2adf | 1553 | |
8e802be9 | 1554 | /* re-Cache any INSN_LIST nodes we have allocated. */ |
7fb47f9f | 1555 | clear_modify_mem_tables (); |
18aa2adf | 1556 | /* Some working arrays used to track first and last set in each block. */ |
d743aba2 | 1557 | reg_avail_info = GNEWVEC (struct reg_avail_info, max_reg_num ()); |
eac13465 | 1558 | |
d743aba2 | 1559 | for (i = 0; i < max_reg_num (); ++i) |
4c26117a | 1560 | reg_avail_info[i].last_bb = NULL; |
18aa2adf | 1561 | |
fc00614f | 1562 | FOR_EACH_BB_FN (current_bb, cfun) |
18aa2adf | 1563 | { |
1564 | rtx insn; | |
02e7a332 | 1565 | unsigned int regno; |
18aa2adf | 1566 | |
1567 | /* First pass over the instructions records information used to | |
2e81afe5 | 1568 | determine when registers and memory are first and last set. */ |
defc8016 | 1569 | FOR_BB_INSNS (current_bb, insn) |
18aa2adf | 1570 | { |
da6f6776 | 1571 | if (!NONDEBUG_INSN_P (insn)) |
18aa2adf | 1572 | continue; |
1573 | ||
b9f02dbb | 1574 | if (CALL_P (insn)) |
18aa2adf | 1575 | { |
24ec6636 | 1576 | hard_reg_set_iterator hrsi; |
1577 | EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, | |
1578 | 0, regno, hrsi) | |
1579 | record_last_reg_set_info (insn, regno); | |
2c084240 | 1580 | |
07abdb66 | 1581 | if (! RTL_CONST_OR_PURE_CALL_P (insn)) |
1582 | record_last_mem_set_info (insn); | |
18aa2adf | 1583 | } |
1584 | ||
ec8895d7 | 1585 | note_stores (PATTERN (insn), record_last_set_info, insn); |
18aa2adf | 1586 | } |
1587 | ||
1588 | /* The next pass builds the hash table. */ | |
defc8016 | 1589 | FOR_BB_INSNS (current_bb, insn) |
da6f6776 | 1590 | if (NONDEBUG_INSN_P (insn)) |
1e5b92fa | 1591 | hash_scan_insn (insn, table); |
18aa2adf | 1592 | } |
1593 | ||
eac13465 | 1594 | free (reg_avail_info); |
1595 | reg_avail_info = NULL; | |
18aa2adf | 1596 | } |
1597 | ||
27cfe3f1 | 1598 | /* Allocate space for the set/expr hash TABLE. |
07abdb66 | 1599 | It is used to determine the number of buckets to use. */ |
18aa2adf | 1600 | |
1601 | static void | |
07abdb66 | 1602 | alloc_hash_table (struct hash_table_d *table) |
18aa2adf | 1603 | { |
1604 | int n; | |
1605 | ||
9845d120 | 1606 | n = get_max_insn_count (); |
1607 | ||
1608 | table->size = n / 4; | |
27cfe3f1 | 1609 | if (table->size < 11) |
1610 | table->size = 11; | |
2c084240 | 1611 | |
18aa2adf | 1612 | /* Attempt to maintain efficient use of hash table. |
1613 | Making it an odd number is simplest for now. | |
1614 | ??? Later take some measurements. */ | |
27cfe3f1 | 1615 | table->size |= 1; |
1616 | n = table->size * sizeof (struct expr *); | |
2457c754 | 1617 | table->table = GNEWVAR (struct expr *, n); |
18aa2adf | 1618 | } |
1619 | ||
27cfe3f1 | 1620 | /* Free things allocated by alloc_hash_table. */ |
18aa2adf | 1621 | |
1622 | static void | |
26dbec0a | 1623 | free_hash_table (struct hash_table_d *table) |
18aa2adf | 1624 | { |
27cfe3f1 | 1625 | free (table->table); |
18aa2adf | 1626 | } |
1627 | ||
07abdb66 | 1628 | /* Compute the expression hash table TABLE. */ |
18aa2adf | 1629 | |
1630 | static void | |
26dbec0a | 1631 | compute_hash_table (struct hash_table_d *table) |
18aa2adf | 1632 | { |
1633 | /* Initialize count of number of entries in hash table. */ | |
27cfe3f1 | 1634 | table->n_elems = 0; |
f0af5a88 | 1635 | memset (table->table, 0, table->size * sizeof (struct expr *)); |
18aa2adf | 1636 | |
27cfe3f1 | 1637 | compute_hash_table_work (table); |
18aa2adf | 1638 | } |
1639 | \f | |
1640 | /* Expression tracking support. */ | |
1641 | ||
07abdb66 | 1642 | /* Clear canon_modify_mem_list and modify_mem_list tables. */ |
1643 | static void | |
1644 | clear_modify_mem_tables (void) | |
23e5207c | 1645 | { |
07abdb66 | 1646 | unsigned i; |
1647 | bitmap_iterator bi; | |
23e5207c | 1648 | |
07abdb66 | 1649 | EXECUTE_IF_SET_IN_BITMAP (modify_mem_list_set, 0, i, bi) |
23e5207c | 1650 | { |
f1f41a6c | 1651 | modify_mem_list[i].release (); |
1652 | canon_modify_mem_list[i].release (); | |
23e5207c | 1653 | } |
07abdb66 | 1654 | bitmap_clear (modify_mem_list_set); |
1655 | bitmap_clear (blocks_with_calls); | |
23e5207c | 1656 | } |
1657 | ||
07abdb66 | 1658 | /* Release memory used by modify_mem_list_set. */ |
23e5207c | 1659 | |
07abdb66 | 1660 | static void |
1661 | free_modify_mem_tables (void) | |
375b98af | 1662 | { |
07abdb66 | 1663 | clear_modify_mem_tables (); |
1664 | free (modify_mem_list); | |
1665 | free (canon_modify_mem_list); | |
1666 | modify_mem_list = 0; | |
1667 | canon_modify_mem_list = 0; | |
375b98af | 1668 | } |
07abdb66 | 1669 | \f |
1670 | /* For each block, compute whether X is transparent. X is either an | |
1671 | expression or an assignment [though we don't care which, for this context | |
1672 | an assignment is treated as an expression]. For each block where an | |
1673 | element of X is modified, reset the INDX bit in BMAP. */ | |
23e5207c | 1674 | |
07abdb66 | 1675 | static void |
1676 | compute_transp (const_rtx x, int indx, sbitmap *bmap) | |
23e5207c | 1677 | { |
07abdb66 | 1678 | int i, j; |
1679 | enum rtx_code code; | |
1680 | const char *fmt; | |
23e5207c | 1681 | |
07abdb66 | 1682 | /* repeat is used to turn tail-recursion into iteration since GCC |
1683 | can't do it when there's no return value. */ | |
1684 | repeat: | |
23e5207c | 1685 | |
07abdb66 | 1686 | if (x == 0) |
1687 | return; | |
a964683a | 1688 | |
07abdb66 | 1689 | code = GET_CODE (x); |
1690 | switch (code) | |
23e5207c | 1691 | { |
07abdb66 | 1692 | case REG: |
cd665a06 | 1693 | { |
07abdb66 | 1694 | df_ref def; |
1695 | for (def = DF_REG_DEF_CHAIN (REGNO (x)); | |
1696 | def; | |
1697 | def = DF_REF_NEXT_REG (def)) | |
08b7917c | 1698 | bitmap_clear_bit (bmap[DF_REF_BB (def)->index], indx); |
cd665a06 | 1699 | } |
8724a717 | 1700 | |
07abdb66 | 1701 | return; |
a964683a | 1702 | |
07abdb66 | 1703 | case MEM: |
1704 | if (! MEM_READONLY_P (x)) | |
23e5207c | 1705 | { |
07abdb66 | 1706 | bitmap_iterator bi; |
1707 | unsigned bb_index; | |
5d3b0682 | 1708 | rtx x_addr; |
1709 | ||
1710 | x_addr = get_addr (XEXP (x, 0)); | |
1711 | x_addr = canon_rtx (x_addr); | |
375b98af | 1712 | |
07abdb66 | 1713 | /* First handle all the blocks with calls. We don't need to |
1714 | do any list walking for them. */ | |
1715 | EXECUTE_IF_SET_IN_BITMAP (blocks_with_calls, 0, bb_index, bi) | |
1716 | { | |
08b7917c | 1717 | bitmap_clear_bit (bmap[bb_index], indx); |
07abdb66 | 1718 | } |
23e5207c | 1719 | |
5d3b0682 | 1720 | /* Now iterate over the blocks which have memory modifications |
1721 | but which do not have any calls. */ | |
1722 | EXECUTE_IF_AND_COMPL_IN_BITMAP (modify_mem_list_set, | |
1723 | blocks_with_calls, | |
1724 | 0, bb_index, bi) | |
1725 | { | |
1726 | vec<modify_pair> list | |
1727 | = canon_modify_mem_list[bb_index]; | |
1728 | modify_pair *pair; | |
1729 | unsigned ix; | |
1730 | ||
1731 | FOR_EACH_VEC_ELT_REVERSE (list, ix, pair) | |
1732 | { | |
1733 | rtx dest = pair->dest; | |
1734 | rtx dest_addr = pair->dest_addr; | |
1735 | ||
1736 | if (canon_true_dependence (dest, GET_MODE (dest), | |
1737 | dest_addr, x, x_addr)) | |
1738 | bitmap_clear_bit (bmap[bb_index], indx); | |
1739 | } | |
1740 | } | |
23e5207c | 1741 | } |
23e5207c | 1742 | |
07abdb66 | 1743 | x = XEXP (x, 0); |
1744 | goto repeat; | |
23e5207c | 1745 | |
07abdb66 | 1746 | case PC: |
1747 | case CC0: /*FIXME*/ | |
1748 | case CONST: | |
0349edce | 1749 | CASE_CONST_ANY: |
07abdb66 | 1750 | case SYMBOL_REF: |
1751 | case LABEL_REF: | |
1752 | case ADDR_VEC: | |
1753 | case ADDR_DIFF_VEC: | |
1754 | return; | |
23e5207c | 1755 | |
07abdb66 | 1756 | default: |
1757 | break; | |
1758 | } | |
8724a717 | 1759 | |
07abdb66 | 1760 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--) |
23e5207c | 1761 | { |
07abdb66 | 1762 | if (fmt[i] == 'e') |
23e5207c | 1763 | { |
07abdb66 | 1764 | /* If we are about to do the last recursive call |
1765 | needed at this level, change it into iteration. | |
1766 | This function is called enough to be worth it. */ | |
1767 | if (i == 0) | |
1768 | { | |
1769 | x = XEXP (x, i); | |
1770 | goto repeat; | |
1771 | } | |
1772 | ||
1773 | compute_transp (XEXP (x, i), indx, bmap); | |
23e5207c | 1774 | } |
07abdb66 | 1775 | else if (fmt[i] == 'E') |
1776 | for (j = 0; j < XVECLEN (x, i); j++) | |
1777 | compute_transp (XVECEXP (x, i, j), indx, bmap); | |
23e5207c | 1778 | } |
23e5207c | 1779 | } |
1780 | \f | |
b3f3796c | 1781 | /* Compute PRE+LCM working variables. */ |
18aa2adf | 1782 | |
1783 | /* Local properties of expressions. */ | |
bc8197c0 | 1784 | |
18aa2adf | 1785 | /* Nonzero for expressions that are transparent in the block. */ |
b3f3796c | 1786 | static sbitmap *transp; |
18aa2adf | 1787 | |
b3f3796c | 1788 | /* Nonzero for expressions that are computed (available) in the block. */ |
1789 | static sbitmap *comp; | |
18aa2adf | 1790 | |
b3f3796c | 1791 | /* Nonzero for expressions that are locally anticipatable in the block. */ |
1792 | static sbitmap *antloc; | |
18aa2adf | 1793 | |
b3f3796c | 1794 | /* Nonzero for expressions where this block is an optimal computation |
1795 | point. */ | |
1796 | static sbitmap *pre_optimal; | |
7bdba5dd | 1797 | |
b3f3796c | 1798 | /* Nonzero for expressions which are redundant in a particular block. */ |
1799 | static sbitmap *pre_redundant; | |
18aa2adf | 1800 | |
7bcd381b | 1801 | /* Nonzero for expressions which should be inserted on a specific edge. */ |
1802 | static sbitmap *pre_insert_map; | |
1803 | ||
1804 | /* Nonzero for expressions which should be deleted in a specific block. */ | |
1805 | static sbitmap *pre_delete_map; | |
1806 | ||
b3f3796c | 1807 | /* Allocate vars used for PRE analysis. */ |
18aa2adf | 1808 | |
1809 | static void | |
952f0048 | 1810 | alloc_pre_mem (int n_blocks, int n_exprs) |
18aa2adf | 1811 | { |
b3f3796c | 1812 | transp = sbitmap_vector_alloc (n_blocks, n_exprs); |
1813 | comp = sbitmap_vector_alloc (n_blocks, n_exprs); | |
1814 | antloc = sbitmap_vector_alloc (n_blocks, n_exprs); | |
0388e90f | 1815 | |
7bcd381b | 1816 | pre_optimal = NULL; |
1817 | pre_redundant = NULL; | |
1818 | pre_insert_map = NULL; | |
1819 | pre_delete_map = NULL; | |
7bcd381b | 1820 | ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs); |
2c084240 | 1821 | |
7bcd381b | 1822 | /* pre_insert and pre_delete are allocated later. */ |
18aa2adf | 1823 | } |
1824 | ||
b3f3796c | 1825 | /* Free vars used for PRE analysis. */ |
18aa2adf | 1826 | |
1827 | static void | |
952f0048 | 1828 | free_pre_mem (void) |
18aa2adf | 1829 | { |
cca23eb2 | 1830 | sbitmap_vector_free (transp); |
1831 | sbitmap_vector_free (comp); | |
8123d49b | 1832 | |
1833 | /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */ | |
18aa2adf | 1834 | |
7bcd381b | 1835 | if (pre_optimal) |
cca23eb2 | 1836 | sbitmap_vector_free (pre_optimal); |
7bcd381b | 1837 | if (pre_redundant) |
cca23eb2 | 1838 | sbitmap_vector_free (pre_redundant); |
7bcd381b | 1839 | if (pre_insert_map) |
cca23eb2 | 1840 | sbitmap_vector_free (pre_insert_map); |
7bcd381b | 1841 | if (pre_delete_map) |
cca23eb2 | 1842 | sbitmap_vector_free (pre_delete_map); |
7bcd381b | 1843 | |
8123d49b | 1844 | transp = comp = NULL; |
7bcd381b | 1845 | pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL; |
18aa2adf | 1846 | } |
1847 | ||
f151d0c6 | 1848 | /* Remove certain expressions from anticipatable and transparent |
1849 | sets of basic blocks that have incoming abnormal edge. | |
1850 | For PRE remove potentially trapping expressions to avoid placing | |
1851 | them on abnormal edges. For hoisting remove memory references that | |
1852 | can be clobbered by calls. */ | |
18aa2adf | 1853 | |
1854 | static void | |
f151d0c6 | 1855 | prune_expressions (bool pre_p) |
18aa2adf | 1856 | { |
f151d0c6 | 1857 | sbitmap prune_exprs; |
bc8197c0 | 1858 | struct expr *expr; |
e531b5f0 | 1859 | unsigned int ui; |
f151d0c6 | 1860 | basic_block bb; |
bafa5ac7 | 1861 | |
f151d0c6 | 1862 | prune_exprs = sbitmap_alloc (expr_hash_table.n_elems); |
53c5d9d4 | 1863 | bitmap_clear (prune_exprs); |
27cfe3f1 | 1864 | for (ui = 0; ui < expr_hash_table.size; ui++) |
e531b5f0 | 1865 | { |
bc8197c0 | 1866 | for (expr = expr_hash_table.table[ui]; expr; expr = expr->next_same_hash) |
f151d0c6 | 1867 | { |
1868 | /* Note potentially trapping expressions. */ | |
bc8197c0 | 1869 | if (may_trap_p (expr->expr)) |
f151d0c6 | 1870 | { |
08b7917c | 1871 | bitmap_set_bit (prune_exprs, expr->bitmap_index); |
f151d0c6 | 1872 | continue; |
1873 | } | |
e531b5f0 | 1874 | |
bc8197c0 | 1875 | if (!pre_p && MEM_P (expr->expr)) |
f151d0c6 | 1876 | /* Note memory references that can be clobbered by a call. |
1877 | We do not split abnormal edges in hoisting, so would | |
1878 | a memory reference get hoisted along an abnormal edge, | |
1879 | it would be placed /before/ the call. Therefore, only | |
1880 | constant memory references can be hoisted along abnormal | |
1881 | edges. */ | |
1882 | { | |
bc8197c0 | 1883 | if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF |
1884 | && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0))) | |
f151d0c6 | 1885 | continue; |
bafa5ac7 | 1886 | |
bc8197c0 | 1887 | if (MEM_READONLY_P (expr->expr) |
1888 | && !MEM_VOLATILE_P (expr->expr) | |
1889 | && MEM_NOTRAP_P (expr->expr)) | |
f151d0c6 | 1890 | /* Constant memory reference, e.g., a PIC address. */ |
1891 | continue; | |
1892 | ||
1893 | /* ??? Optimally, we would use interprocedural alias | |
1894 | analysis to determine if this mem is actually killed | |
1895 | by this call. */ | |
1896 | ||
08b7917c | 1897 | bitmap_set_bit (prune_exprs, expr->bitmap_index); |
f151d0c6 | 1898 | } |
1899 | } | |
1900 | } | |
bafa5ac7 | 1901 | |
fc00614f | 1902 | FOR_EACH_BB_FN (bb, cfun) |
bafa5ac7 | 1903 | { |
e531b5f0 | 1904 | edge e; |
cd665a06 | 1905 | edge_iterator ei; |
e531b5f0 | 1906 | |
1907 | /* If the current block is the destination of an abnormal edge, we | |
f151d0c6 | 1908 | kill all trapping (for PRE) and memory (for hoist) expressions |
1909 | because we won't be able to properly place the instruction on | |
1910 | the edge. So make them neither anticipatable nor transparent. | |
1911 | This is fairly conservative. | |
1912 | ||
1913 | ??? For hoisting it may be necessary to check for set-and-jump | |
1914 | instructions here, not just for abnormal edges. The general problem | |
1915 | is that when an expression cannot not be placed right at the end of | |
1916 | a basic block we should account for any side-effects of a subsequent | |
1917 | jump instructions that could clobber the expression. It would | |
1918 | be best to implement this check along the lines of | |
1ec78e16 | 1919 | should_hoist_expr_to_dom where the target block is already known |
f151d0c6 | 1920 | and, hence, there's no need to conservatively prune expressions on |
1921 | "intermediate" set-and-jump instructions. */ | |
cd665a06 | 1922 | FOR_EACH_EDGE (e, ei, bb->preds) |
f151d0c6 | 1923 | if ((e->flags & EDGE_ABNORMAL) |
1924 | && (pre_p || CALL_P (BB_END (e->src)))) | |
e531b5f0 | 1925 | { |
53c5d9d4 | 1926 | bitmap_and_compl (antloc[bb->index], |
f151d0c6 | 1927 | antloc[bb->index], prune_exprs); |
53c5d9d4 | 1928 | bitmap_and_compl (transp[bb->index], |
f151d0c6 | 1929 | transp[bb->index], prune_exprs); |
e531b5f0 | 1930 | break; |
1931 | } | |
f151d0c6 | 1932 | } |
1933 | ||
1934 | sbitmap_free (prune_exprs); | |
1935 | } | |
1936 | ||
b89c219c | 1937 | /* It may be necessary to insert a large number of insns on edges to |
1938 | make the existing occurrences of expressions fully redundant. This | |
1939 | routine examines the set of insertions and deletions and if the ratio | |
1940 | of insertions to deletions is too high for a particular expression, then | |
1941 | the expression is removed from the insertion/deletion sets. | |
1942 | ||
1943 | N_ELEMS is the number of elements in the hash table. */ | |
1944 | ||
1945 | static void | |
1946 | prune_insertions_deletions (int n_elems) | |
1947 | { | |
1948 | sbitmap_iterator sbi; | |
1949 | sbitmap prune_exprs; | |
1950 | ||
1951 | /* We always use I to iterate over blocks/edges and J to iterate over | |
1952 | expressions. */ | |
1953 | unsigned int i, j; | |
1954 | ||
1955 | /* Counts for the number of times an expression needs to be inserted and | |
1956 | number of times an expression can be removed as a result. */ | |
1957 | int *insertions = GCNEWVEC (int, n_elems); | |
1958 | int *deletions = GCNEWVEC (int, n_elems); | |
1959 | ||
1960 | /* Set of expressions which require too many insertions relative to | |
1961 | the number of deletions achieved. We will prune these out of the | |
1962 | insertion/deletion sets. */ | |
1963 | prune_exprs = sbitmap_alloc (n_elems); | |
53c5d9d4 | 1964 | bitmap_clear (prune_exprs); |
b89c219c | 1965 | |
1966 | /* Iterate over the edges counting the number of times each expression | |
1967 | needs to be inserted. */ | |
f1955b22 | 1968 | for (i = 0; i < (unsigned) n_edges_for_fn (cfun); i++) |
b89c219c | 1969 | { |
0d211963 | 1970 | EXECUTE_IF_SET_IN_BITMAP (pre_insert_map[i], 0, j, sbi) |
b89c219c | 1971 | insertions[j]++; |
1972 | } | |
1973 | ||
1974 | /* Similarly for deletions, but those occur in blocks rather than on | |
1975 | edges. */ | |
fe672ac0 | 1976 | for (i = 0; i < (unsigned) last_basic_block_for_fn (cfun); i++) |
b89c219c | 1977 | { |
0d211963 | 1978 | EXECUTE_IF_SET_IN_BITMAP (pre_delete_map[i], 0, j, sbi) |
b89c219c | 1979 | deletions[j]++; |
1980 | } | |
1981 | ||
1982 | /* Now that we have accurate counts, iterate over the elements in the | |
1983 | hash table and see if any need too many insertions relative to the | |
1984 | number of evaluations that can be removed. If so, mark them in | |
1985 | PRUNE_EXPRS. */ | |
1986 | for (j = 0; j < (unsigned) n_elems; j++) | |
1987 | if (deletions[j] | |
1988 | && ((unsigned) insertions[j] / deletions[j]) > MAX_GCSE_INSERTION_RATIO) | |
08b7917c | 1989 | bitmap_set_bit (prune_exprs, j); |
b89c219c | 1990 | |
1991 | /* Now prune PRE_INSERT_MAP and PRE_DELETE_MAP based on PRUNE_EXPRS. */ | |
0d211963 | 1992 | EXECUTE_IF_SET_IN_BITMAP (prune_exprs, 0, j, sbi) |
b89c219c | 1993 | { |
f1955b22 | 1994 | for (i = 0; i < (unsigned) n_edges_for_fn (cfun); i++) |
08b7917c | 1995 | bitmap_clear_bit (pre_insert_map[i], j); |
b89c219c | 1996 | |
fe672ac0 | 1997 | for (i = 0; i < (unsigned) last_basic_block_for_fn (cfun); i++) |
08b7917c | 1998 | bitmap_clear_bit (pre_delete_map[i], j); |
b89c219c | 1999 | } |
2000 | ||
2001 | sbitmap_free (prune_exprs); | |
2002 | free (insertions); | |
2003 | free (deletions); | |
2004 | } | |
2005 | ||
f151d0c6 | 2006 | /* Top level routine to do the dataflow analysis needed by PRE. */ |
e531b5f0 | 2007 | |
bc8197c0 | 2008 | static struct edge_list * |
f151d0c6 | 2009 | compute_pre_data (void) |
2010 | { | |
bc8197c0 | 2011 | struct edge_list *edge_list; |
f151d0c6 | 2012 | basic_block bb; |
2013 | ||
2014 | compute_local_properties (transp, comp, antloc, &expr_hash_table); | |
2015 | prune_expressions (true); | |
fe672ac0 | 2016 | bitmap_vector_clear (ae_kill, last_basic_block_for_fn (cfun)); |
f151d0c6 | 2017 | |
2018 | /* Compute ae_kill for each basic block using: | |
2019 | ||
2020 | ~(TRANSP | COMP) | |
2021 | */ | |
2022 | ||
fc00614f | 2023 | FOR_EACH_BB_FN (bb, cfun) |
f151d0c6 | 2024 | { |
53c5d9d4 | 2025 | bitmap_ior (ae_kill[bb->index], transp[bb->index], comp[bb->index]); |
2026 | bitmap_not (ae_kill[bb->index], ae_kill[bb->index]); | |
bafa5ac7 | 2027 | } |
2028 | ||
3f5be5f4 | 2029 | edge_list = pre_edge_lcm (expr_hash_table.n_elems, transp, comp, antloc, |
7bcd381b | 2030 | ae_kill, &pre_insert_map, &pre_delete_map); |
cca23eb2 | 2031 | sbitmap_vector_free (antloc); |
8123d49b | 2032 | antloc = NULL; |
cca23eb2 | 2033 | sbitmap_vector_free (ae_kill); |
3cfec666 | 2034 | ae_kill = NULL; |
b89c219c | 2035 | |
2036 | prune_insertions_deletions (expr_hash_table.n_elems); | |
bc8197c0 | 2037 | |
2038 | return edge_list; | |
18aa2adf | 2039 | } |
2040 | \f | |
2041 | /* PRE utilities */ | |
2042 | ||
6ef828f9 | 2043 | /* Return nonzero if an occurrence of expression EXPR in OCCR_BB would reach |
b3f3796c | 2044 | block BB. |
18aa2adf | 2045 | |
2046 | VISITED is a pointer to a working buffer for tracking which BB's have | |
2047 | been visited. It is NULL for the top-level call. | |
2048 | ||
2049 | We treat reaching expressions that go through blocks containing the same | |
2050 | reaching expression as "not reaching". E.g. if EXPR is generated in blocks | |
2051 | 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block | |
2052 | 2 as not reaching. The intent is to improve the probability of finding | |
2053 | only one reaching expression and to reduce register lifetimes by picking | |
2054 | the closest such expression. */ | |
2055 | ||
2056 | static int | |
bc8197c0 | 2057 | pre_expr_reaches_here_p_work (basic_block occr_bb, struct expr *expr, |
2058 | basic_block bb, char *visited) | |
18aa2adf | 2059 | { |
cb7e28c3 | 2060 | edge pred; |
cd665a06 | 2061 | edge_iterator ei; |
48e1416a | 2062 | |
cd665a06 | 2063 | FOR_EACH_EDGE (pred, ei, bb->preds) |
18aa2adf | 2064 | { |
8d4a53c7 | 2065 | basic_block pred_bb = pred->src; |
18aa2adf | 2066 | |
34154e27 | 2067 | if (pred->src == ENTRY_BLOCK_PTR_FOR_FN (cfun) |
18aa2adf | 2068 | /* Has predecessor has already been visited? */ |
b3d6de89 | 2069 | || visited[pred_bb->index]) |
2c084240 | 2070 | ;/* Nothing to do. */ |
2071 | ||
18aa2adf | 2072 | /* Does this predecessor generate this expression? */ |
08b7917c | 2073 | else if (bitmap_bit_p (comp[pred_bb->index], expr->bitmap_index)) |
18aa2adf | 2074 | { |
2075 | /* Is this the occurrence we're looking for? | |
2076 | Note that there's only one generating occurrence per block | |
2077 | so we just need to check the block number. */ | |
b3f3796c | 2078 | if (occr_bb == pred_bb) |
18aa2adf | 2079 | return 1; |
2c084240 | 2080 | |
b3d6de89 | 2081 | visited[pred_bb->index] = 1; |
18aa2adf | 2082 | } |
2083 | /* Ignore this predecessor if it kills the expression. */ | |
08b7917c | 2084 | else if (! bitmap_bit_p (transp[pred_bb->index], expr->bitmap_index)) |
b3d6de89 | 2085 | visited[pred_bb->index] = 1; |
2c084240 | 2086 | |
18aa2adf | 2087 | /* Neither gen nor kill. */ |
2088 | else | |
b65b4f63 | 2089 | { |
b3d6de89 | 2090 | visited[pred_bb->index] = 1; |
048599b9 | 2091 | if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited)) |
18aa2adf | 2092 | return 1; |
b65b4f63 | 2093 | } |
18aa2adf | 2094 | } |
2095 | ||
2096 | /* All paths have been checked. */ | |
2097 | return 0; | |
2098 | } | |
cd55d9d6 | 2099 | |
2100 | /* The wrapper for pre_expr_reaches_here_work that ensures that any | |
aa40f561 | 2101 | memory allocated for that function is returned. */ |
cd55d9d6 | 2102 | |
2103 | static int | |
952f0048 | 2104 | pre_expr_reaches_here_p (basic_block occr_bb, struct expr *expr, basic_block bb) |
cd55d9d6 | 2105 | { |
2106 | int rval; | |
fe672ac0 | 2107 | char *visited = XCNEWVEC (char, last_basic_block_for_fn (cfun)); |
cd55d9d6 | 2108 | |
387732c1 | 2109 | rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited); |
cd55d9d6 | 2110 | |
2111 | free (visited); | |
2c084240 | 2112 | return rval; |
cd55d9d6 | 2113 | } |
18aa2adf | 2114 | \f |
bc8197c0 | 2115 | /* Generate RTL to copy an EXPR to its `reaching_reg' and return it. */ |
7bcd381b | 2116 | |
2117 | static rtx | |
952f0048 | 2118 | process_insert_insn (struct expr *expr) |
7bcd381b | 2119 | { |
2120 | rtx reg = expr->reaching_reg; | |
bc8197c0 | 2121 | /* Copy the expression to make sure we don't have any sharing issues. */ |
06e2144a | 2122 | rtx exp = copy_rtx (expr->expr); |
2123 | rtx pat; | |
7bcd381b | 2124 | |
2125 | start_sequence (); | |
06e2144a | 2126 | |
2127 | /* If the expression is something that's an operand, like a constant, | |
2128 | just copy it to a register. */ | |
2129 | if (general_operand (exp, GET_MODE (reg))) | |
2130 | emit_move_insn (reg, exp); | |
2131 | ||
2132 | /* Otherwise, make a new insn to compute this expression and make sure the | |
bc8197c0 | 2133 | insn will be recognized (this also adds any needed CLOBBERs). */ |
0d59b19d | 2134 | else |
2135 | { | |
2136 | rtx insn = emit_insn (gen_rtx_SET (VOIDmode, reg, exp)); | |
2137 | ||
dae9d0e7 | 2138 | if (insn_invalid_p (insn, false)) |
0fa137b8 | 2139 | gcc_unreachable (); |
0d59b19d | 2140 | } |
48e1416a | 2141 | |
31d3e01c | 2142 | pat = get_insns (); |
7bcd381b | 2143 | end_sequence (); |
2144 | ||
2145 | return pat; | |
2146 | } | |
3cfec666 | 2147 | |
b3f3796c | 2148 | /* Add EXPR to the end of basic block BB. |
2149 | ||
36f52b0d | 2150 | This is used by both the PRE and code hoisting. */ |
18aa2adf | 2151 | |
2152 | static void | |
36f52b0d | 2153 | insert_insn_end_basic_block (struct expr *expr, basic_block bb) |
18aa2adf | 2154 | { |
5496dbfc | 2155 | rtx insn = BB_END (bb); |
18aa2adf | 2156 | rtx new_insn; |
2157 | rtx reg = expr->reaching_reg; | |
2158 | int regno = REGNO (reg); | |
31d3e01c | 2159 | rtx pat, pat_end; |
18aa2adf | 2160 | |
7bcd381b | 2161 | pat = process_insert_insn (expr); |
0d59b19d | 2162 | gcc_assert (pat && INSN_P (pat)); |
31d3e01c | 2163 | |
2164 | pat_end = pat; | |
2165 | while (NEXT_INSN (pat_end) != NULL_RTX) | |
2166 | pat_end = NEXT_INSN (pat_end); | |
18aa2adf | 2167 | |
2168 | /* If the last insn is a jump, insert EXPR in front [taking care to | |
917bbcab | 2169 | handle cc0, etc. properly]. Similarly we need to care trapping |
17a54dac | 2170 | instructions in presence of non-call exceptions. */ |
18aa2adf | 2171 | |
b9f02dbb | 2172 | if (JUMP_P (insn) |
6d7dc5b9 | 2173 | || (NONJUMP_INSN_P (insn) |
ea091dfd | 2174 | && (!single_succ_p (bb) |
2175 | || single_succ_edge (bb)->flags & EDGE_ABNORMAL))) | |
18aa2adf | 2176 | { |
18aa2adf | 2177 | #ifdef HAVE_cc0 |
2178 | /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts | |
2179 | if cc0 isn't set. */ | |
91f71fa3 | 2180 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
18aa2adf | 2181 | if (note) |
2182 | insn = XEXP (note, 0); | |
2183 | else | |
2184 | { | |
2185 | rtx maybe_cc0_setter = prev_nonnote_insn (insn); | |
2186 | if (maybe_cc0_setter | |
9204e736 | 2187 | && INSN_P (maybe_cc0_setter) |
18aa2adf | 2188 | && sets_cc0_p (PATTERN (maybe_cc0_setter))) |
2189 | insn = maybe_cc0_setter; | |
2190 | } | |
2191 | #endif | |
2192 | /* FIXME: What if something in cc0/jump uses value set in new insn? */ | |
3072d30e | 2193 | new_insn = emit_insn_before_noloc (pat, insn, bb); |
170e5c6c | 2194 | } |
2c084240 | 2195 | |
170e5c6c | 2196 | /* Likewise if the last insn is a call, as will happen in the presence |
2197 | of exception handling. */ | |
b9f02dbb | 2198 | else if (CALL_P (insn) |
ea091dfd | 2199 | && (!single_succ_p (bb) |
2200 | || single_succ_edge (bb)->flags & EDGE_ABNORMAL)) | |
170e5c6c | 2201 | { |
ed5527ca | 2202 | /* Keeping in mind targets with small register classes and parameters |
2203 | in registers, we search backward and place the instructions before | |
2204 | the first parameter is loaded. Do this for everyone for consistency | |
36f52b0d | 2205 | and a presumption that we'll get better code elsewhere as well. */ |
170e5c6c | 2206 | |
2207 | /* Since different machines initialize their parameter registers | |
2208 | in different orders, assume nothing. Collect the set of all | |
2209 | parameter registers. */ | |
5496dbfc | 2210 | insn = find_first_parameter_load (insn, BB_HEAD (bb)); |
170e5c6c | 2211 | |
9fc37e9d | 2212 | /* If we found all the parameter loads, then we want to insert |
2213 | before the first parameter load. | |
2214 | ||
2215 | If we did not find all the parameter loads, then we might have | |
2216 | stopped on the head of the block, which could be a CODE_LABEL. | |
2217 | If we inserted before the CODE_LABEL, then we would be putting | |
2218 | the insn in the wrong basic block. In that case, put the insn | |
8b3dea0b | 2219 | after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */ |
b9f02dbb | 2220 | while (LABEL_P (insn) |
83458610 | 2221 | || NOTE_INSN_BASIC_BLOCK_P (insn)) |
8b3dea0b | 2222 | insn = NEXT_INSN (insn); |
2c084240 | 2223 | |
3072d30e | 2224 | new_insn = emit_insn_before_noloc (pat, insn, bb); |
18aa2adf | 2225 | } |
2226 | else | |
3072d30e | 2227 | new_insn = emit_insn_after_noloc (pat, insn, bb); |
18aa2adf | 2228 | |
31d3e01c | 2229 | while (1) |
b3f3796c | 2230 | { |
31d3e01c | 2231 | if (INSN_P (pat)) |
2e81afe5 | 2232 | add_label_notes (PATTERN (pat), new_insn); |
31d3e01c | 2233 | if (pat == pat_end) |
2234 | break; | |
2235 | pat = NEXT_INSN (pat); | |
b3f3796c | 2236 | } |
170e5c6c | 2237 | |
18aa2adf | 2238 | gcse_create_count++; |
2239 | ||
3f5be5f4 | 2240 | if (dump_file) |
18aa2adf | 2241 | { |
3f5be5f4 | 2242 | fprintf (dump_file, "PRE/HOIST: end of bb %d, insn %d, ", |
b3d6de89 | 2243 | bb->index, INSN_UID (new_insn)); |
3f5be5f4 | 2244 | fprintf (dump_file, "copying expression %d to reg %d\n", |
2c084240 | 2245 | expr->bitmap_index, regno); |
18aa2adf | 2246 | } |
2247 | } | |
2248 | ||
7bcd381b | 2249 | /* Insert partially redundant expressions on edges in the CFG to make |
2250 | the expressions fully redundant. */ | |
18aa2adf | 2251 | |
7bcd381b | 2252 | static int |
952f0048 | 2253 | pre_edge_insert (struct edge_list *edge_list, struct expr **index_map) |
18aa2adf | 2254 | { |
2c084240 | 2255 | int e, i, j, num_edges, set_size, did_insert = 0; |
b3f3796c | 2256 | sbitmap *inserted; |
2257 | ||
7bcd381b | 2258 | /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge |
2259 | if it reaches any of the deleted expressions. */ | |
18aa2adf | 2260 | |
7bcd381b | 2261 | set_size = pre_insert_map[0]->size; |
2262 | num_edges = NUM_EDGES (edge_list); | |
27cfe3f1 | 2263 | inserted = sbitmap_vector_alloc (num_edges, expr_hash_table.n_elems); |
53c5d9d4 | 2264 | bitmap_vector_clear (inserted, num_edges); |
18aa2adf | 2265 | |
7bcd381b | 2266 | for (e = 0; e < num_edges; e++) |
18aa2adf | 2267 | { |
2268 | int indx; | |
8d4a53c7 | 2269 | basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e); |
b3f3796c | 2270 | |
b3f3796c | 2271 | for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS) |
18aa2adf | 2272 | { |
7bcd381b | 2273 | SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i]; |
18aa2adf | 2274 | |
bc8197c0 | 2275 | for (j = indx; |
2276 | insert && j < (int) expr_hash_table.n_elems; | |
2277 | j++, insert >>= 1) | |
2c084240 | 2278 | if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX) |
2279 | { | |
2280 | struct expr *expr = index_map[j]; | |
2281 | struct occr *occr; | |
b3f3796c | 2282 | |
424da949 | 2283 | /* Now look at each deleted occurrence of this expression. */ |
2c084240 | 2284 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) |
2285 | { | |
2286 | if (! occr->deleted_p) | |
2287 | continue; | |
2288 | ||
822e391f | 2289 | /* Insert this expression on this edge if it would |
424da949 | 2290 | reach the deleted occurrence in BB. */ |
08b7917c | 2291 | if (!bitmap_bit_p (inserted[e], j)) |
2c084240 | 2292 | { |
2293 | rtx insn; | |
2294 | edge eg = INDEX_EDGE (edge_list, e); | |
2295 | ||
2296 | /* We can't insert anything on an abnormal and | |
2297 | critical edge, so we insert the insn at the end of | |
2298 | the previous block. There are several alternatives | |
2299 | detailed in Morgans book P277 (sec 10.5) for | |
2300 | handling this situation. This one is easiest for | |
2301 | now. */ | |
2302 | ||
164aece4 | 2303 | if (eg->flags & EDGE_ABNORMAL) |
36f52b0d | 2304 | insert_insn_end_basic_block (index_map[j], bb); |
2c084240 | 2305 | else |
2306 | { | |
2307 | insn = process_insert_insn (index_map[j]); | |
2308 | insert_insn_on_edge (insn, eg); | |
2309 | } | |
2310 | ||
3f5be5f4 | 2311 | if (dump_file) |
2c084240 | 2312 | { |
d743aba2 | 2313 | fprintf (dump_file, "PRE: edge (%d,%d), ", |
b3d6de89 | 2314 | bb->index, |
2315 | INDEX_EDGE_SUCC_BB (edge_list, e)->index); | |
3f5be5f4 | 2316 | fprintf (dump_file, "copy expression %d\n", |
2c084240 | 2317 | expr->bitmap_index); |
2318 | } | |
2319 | ||
8e802be9 | 2320 | update_ld_motion_stores (expr); |
08b7917c | 2321 | bitmap_set_bit (inserted[e], j); |
2c084240 | 2322 | did_insert = 1; |
2323 | gcse_create_count++; | |
2324 | } | |
2325 | } | |
2326 | } | |
18aa2adf | 2327 | } |
2328 | } | |
0388e90f | 2329 | |
cca23eb2 | 2330 | sbitmap_vector_free (inserted); |
7bcd381b | 2331 | return did_insert; |
18aa2adf | 2332 | } |
2333 | ||
53ee16e4 | 2334 | /* Copy the result of EXPR->EXPR generated by INSN to EXPR->REACHING_REG. |
9d344979 | 2335 | Given "old_reg <- expr" (INSN), instead of adding after it |
2336 | reaching_reg <- old_reg | |
2337 | it's better to do the following: | |
2338 | reaching_reg <- expr | |
2339 | old_reg <- reaching_reg | |
2340 | because this way copy propagation can discover additional PRE | |
5c47e414 | 2341 | opportunities. But if this fails, we try the old way. |
2342 | When "expr" is a store, i.e. | |
2343 | given "MEM <- old_reg", instead of adding after it | |
2344 | reaching_reg <- old_reg | |
2345 | it's better to add it before as follows: | |
2346 | reaching_reg <- old_reg | |
2347 | MEM <- reaching_reg. */ | |
18aa2adf | 2348 | |
2349 | static void | |
952f0048 | 2350 | pre_insert_copy_insn (struct expr *expr, rtx insn) |
18aa2adf | 2351 | { |
2352 | rtx reg = expr->reaching_reg; | |
2353 | int regno = REGNO (reg); | |
2354 | int indx = expr->bitmap_index; | |
53ee16e4 | 2355 | rtx pat = PATTERN (insn); |
00ce82e3 | 2356 | rtx set, first_set, new_insn; |
9d344979 | 2357 | rtx old_reg; |
53ee16e4 | 2358 | int i; |
18aa2adf | 2359 | |
53ee16e4 | 2360 | /* This block matches the logic in hash_scan_insn. */ |
0d59b19d | 2361 | switch (GET_CODE (pat)) |
53ee16e4 | 2362 | { |
0d59b19d | 2363 | case SET: |
2364 | set = pat; | |
2365 | break; | |
2366 | ||
2367 | case PARALLEL: | |
53ee16e4 | 2368 | /* Search through the parallel looking for the set whose |
2369 | source was the expression that we're interested in. */ | |
00ce82e3 | 2370 | first_set = NULL_RTX; |
53ee16e4 | 2371 | set = NULL_RTX; |
2372 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
2373 | { | |
2374 | rtx x = XVECEXP (pat, 0, i); | |
00ce82e3 | 2375 | if (GET_CODE (x) == SET) |
53ee16e4 | 2376 | { |
00ce82e3 | 2377 | /* If the source was a REG_EQUAL or REG_EQUIV note, we |
2378 | may not find an equivalent expression, but in this | |
2379 | case the PARALLEL will have a single set. */ | |
2380 | if (first_set == NULL_RTX) | |
2381 | first_set = x; | |
2382 | if (expr_equiv_p (SET_SRC (x), expr->expr)) | |
2383 | { | |
2384 | set = x; | |
2385 | break; | |
2386 | } | |
53ee16e4 | 2387 | } |
2388 | } | |
00ce82e3 | 2389 | |
2390 | gcc_assert (first_set); | |
2391 | if (set == NULL_RTX) | |
2392 | set = first_set; | |
0d59b19d | 2393 | break; |
2394 | ||
2395 | default: | |
2396 | gcc_unreachable (); | |
53ee16e4 | 2397 | } |
2c084240 | 2398 | |
b9f02dbb | 2399 | if (REG_P (SET_DEST (set))) |
53ee16e4 | 2400 | { |
5c47e414 | 2401 | old_reg = SET_DEST (set); |
2402 | /* Check if we can modify the set destination in the original insn. */ | |
2403 | if (validate_change (insn, &SET_DEST (set), reg, 0)) | |
2404 | { | |
2405 | new_insn = gen_move_insn (old_reg, reg); | |
2406 | new_insn = emit_insn_after (new_insn, insn); | |
5c47e414 | 2407 | } |
2408 | else | |
2409 | { | |
2410 | new_insn = gen_move_insn (reg, old_reg); | |
2411 | new_insn = emit_insn_after (new_insn, insn); | |
5c47e414 | 2412 | } |
53ee16e4 | 2413 | } |
5c47e414 | 2414 | else /* This is possible only in case of a store to memory. */ |
53ee16e4 | 2415 | { |
5c47e414 | 2416 | old_reg = SET_SRC (set); |
53ee16e4 | 2417 | new_insn = gen_move_insn (reg, old_reg); |
5c47e414 | 2418 | |
2419 | /* Check if we can modify the set source in the original insn. */ | |
2420 | if (validate_change (insn, &SET_SRC (set), reg, 0)) | |
2421 | new_insn = emit_insn_before (new_insn, insn); | |
2422 | else | |
2423 | new_insn = emit_insn_after (new_insn, insn); | |
53ee16e4 | 2424 | } |
18aa2adf | 2425 | |
2426 | gcse_create_count++; | |
2427 | ||
3f5be5f4 | 2428 | if (dump_file) |
2429 | fprintf (dump_file, | |
7bcd381b | 2430 | "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n", |
90bd219d | 2431 | BLOCK_FOR_INSN (insn)->index, INSN_UID (new_insn), indx, |
7bcd381b | 2432 | INSN_UID (insn), regno); |
18aa2adf | 2433 | } |
2434 | ||
2435 | /* Copy available expressions that reach the redundant expression | |
2436 | to `reaching_reg'. */ | |
2437 | ||
2438 | static void | |
952f0048 | 2439 | pre_insert_copies (void) |
18aa2adf | 2440 | { |
5c47e414 | 2441 | unsigned int i, added_copy; |
2c084240 | 2442 | struct expr *expr; |
2443 | struct occr *occr; | |
2444 | struct occr *avail; | |
b3f3796c | 2445 | |
18aa2adf | 2446 | /* For each available expression in the table, copy the result to |
2447 | `reaching_reg' if the expression reaches a deleted one. | |
2448 | ||
2449 | ??? The current algorithm is rather brute force. | |
2450 | Need to do some profiling. */ | |
2451 | ||
27cfe3f1 | 2452 | for (i = 0; i < expr_hash_table.size; i++) |
bc8197c0 | 2453 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
2c084240 | 2454 | { |
2455 | /* If the basic block isn't reachable, PPOUT will be TRUE. However, | |
2456 | we don't want to insert a copy here because the expression may not | |
2457 | really be redundant. So only insert an insn if the expression was | |
2458 | deleted. This test also avoids further processing if the | |
2459 | expression wasn't deleted anywhere. */ | |
2460 | if (expr->reaching_reg == NULL) | |
2461 | continue; | |
b9f02dbb | 2462 | |
5c47e414 | 2463 | /* Set when we add a copy for that expression. */ |
b9f02dbb | 2464 | added_copy = 0; |
2c084240 | 2465 | |
2466 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) | |
2467 | { | |
2468 | if (! occr->deleted_p) | |
2469 | continue; | |
18aa2adf | 2470 | |
2c084240 | 2471 | for (avail = expr->avail_occr; avail != NULL; avail = avail->next) |
2472 | { | |
2473 | rtx insn = avail->insn; | |
18aa2adf | 2474 | |
2c084240 | 2475 | /* No need to handle this one if handled already. */ |
2476 | if (avail->copied_p) | |
2477 | continue; | |
18aa2adf | 2478 | |
2c084240 | 2479 | /* Don't handle this one if it's a redundant one. */ |
2e81afe5 | 2480 | if (INSN_DELETED_P (insn)) |
2c084240 | 2481 | continue; |
18aa2adf | 2482 | |
2c084240 | 2483 | /* Or if the expression doesn't reach the deleted one. */ |
3cfec666 | 2484 | if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn), |
8d4a53c7 | 2485 | expr, |
2486 | BLOCK_FOR_INSN (occr->insn))) | |
2c084240 | 2487 | continue; |
18aa2adf | 2488 | |
5c47e414 | 2489 | added_copy = 1; |
2490 | ||
2c084240 | 2491 | /* Copy the result of avail to reaching_reg. */ |
2492 | pre_insert_copy_insn (expr, insn); | |
2493 | avail->copied_p = 1; | |
2494 | } | |
2495 | } | |
5c47e414 | 2496 | |
b9f02dbb | 2497 | if (added_copy) |
5c47e414 | 2498 | update_ld_motion_stores (expr); |
2c084240 | 2499 | } |
18aa2adf | 2500 | } |
2501 | ||
51f6e244 | 2502 | /* Emit move from SRC to DEST noting the equivalence with expression computed |
2503 | in INSN. */ | |
bc8197c0 | 2504 | |
51f6e244 | 2505 | static rtx |
bc8197c0 | 2506 | gcse_emit_move_after (rtx dest, rtx src, rtx insn) |
51f6e244 | 2507 | { |
9ce37fa7 | 2508 | rtx new_rtx; |
65e78aeb | 2509 | rtx set = single_set (insn), set2; |
51f6e244 | 2510 | rtx note; |
264adf90 | 2511 | rtx eqv = NULL_RTX; |
51f6e244 | 2512 | |
2513 | /* This should never fail since we're creating a reg->reg copy | |
2514 | we've verified to be valid. */ | |
2515 | ||
9ce37fa7 | 2516 | new_rtx = emit_insn_after (gen_move_insn (dest, src), insn); |
27442180 | 2517 | |
264adf90 | 2518 | /* Note the equivalence for local CSE pass. Take the note from the old |
2519 | set if there was one. Otherwise record the SET_SRC from the old set | |
2520 | unless DEST is also an operand of the SET_SRC. */ | |
9ce37fa7 | 2521 | set2 = single_set (new_rtx); |
65e78aeb | 2522 | if (!set2 || !rtx_equal_p (SET_DEST (set2), dest)) |
9ce37fa7 | 2523 | return new_rtx; |
51f6e244 | 2524 | if ((note = find_reg_equal_equiv_note (insn))) |
2525 | eqv = XEXP (note, 0); | |
264adf90 | 2526 | else if (! REG_P (dest) |
2527 | || ! reg_mentioned_p (dest, SET_SRC (set))) | |
51f6e244 | 2528 | eqv = SET_SRC (set); |
2529 | ||
264adf90 | 2530 | if (eqv != NULL_RTX) |
2531 | set_unique_reg_note (new_rtx, REG_EQUAL, copy_insn_1 (eqv)); | |
51f6e244 | 2532 | |
9ce37fa7 | 2533 | return new_rtx; |
51f6e244 | 2534 | } |
2535 | ||
18aa2adf | 2536 | /* Delete redundant computations. |
18aa2adf | 2537 | Deletion is done by changing the insn to copy the `reaching_reg' of |
2538 | the expression into the result of the SET. It is left to later passes | |
67d57e27 | 2539 | to propagate the copy or eliminate it. |
18aa2adf | 2540 | |
bc8197c0 | 2541 | Return nonzero if a change is made. */ |
18aa2adf | 2542 | |
2543 | static int | |
952f0048 | 2544 | pre_delete (void) |
18aa2adf | 2545 | { |
a08b57af | 2546 | unsigned int i; |
256d47d0 | 2547 | int changed; |
2c084240 | 2548 | struct expr *expr; |
2549 | struct occr *occr; | |
b3f3796c | 2550 | |
18aa2adf | 2551 | changed = 0; |
27cfe3f1 | 2552 | for (i = 0; i < expr_hash_table.size; i++) |
bc8197c0 | 2553 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
2c084240 | 2554 | { |
2555 | int indx = expr->bitmap_index; | |
18aa2adf | 2556 | |
bc8197c0 | 2557 | /* We only need to search antic_occr since we require ANTLOC != 0. */ |
2c084240 | 2558 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) |
2559 | { | |
2560 | rtx insn = occr->insn; | |
2561 | rtx set; | |
8d4a53c7 | 2562 | basic_block bb = BLOCK_FOR_INSN (insn); |
18aa2adf | 2563 | |
53ee16e4 | 2564 | /* We only delete insns that have a single_set. */ |
08b7917c | 2565 | if (bitmap_bit_p (pre_delete_map[bb->index], indx) |
3072d30e | 2566 | && (set = single_set (insn)) != 0 |
2567 | && dbg_cnt (pre_insn)) | |
2c084240 | 2568 | { |
2c084240 | 2569 | /* Create a pseudo-reg to store the result of reaching |
2570 | expressions into. Get the mode for the new pseudo from | |
2571 | the mode of the original destination pseudo. */ | |
2572 | if (expr->reaching_reg == NULL) | |
ae12ddda | 2573 | expr->reaching_reg = gen_reg_rtx_and_attrs (SET_DEST (set)); |
2c084240 | 2574 | |
bc8197c0 | 2575 | gcse_emit_move_after (SET_DEST (set), expr->reaching_reg, insn); |
51f6e244 | 2576 | delete_insn (insn); |
2577 | occr->deleted_p = 1; | |
51f6e244 | 2578 | changed = 1; |
2579 | gcse_subst_count++; | |
18aa2adf | 2580 | |
3f5be5f4 | 2581 | if (dump_file) |
2c084240 | 2582 | { |
3f5be5f4 | 2583 | fprintf (dump_file, |
2c084240 | 2584 | "PRE: redundant insn %d (expression %d) in ", |
2585 | INSN_UID (insn), indx); | |
3f5be5f4 | 2586 | fprintf (dump_file, "bb %d, reaching reg is %d\n", |
b3d6de89 | 2587 | bb->index, REGNO (expr->reaching_reg)); |
2c084240 | 2588 | } |
2589 | } | |
2590 | } | |
2591 | } | |
18aa2adf | 2592 | |
2593 | return changed; | |
2594 | } | |
2595 | ||
2596 | /* Perform GCSE optimizations using PRE. | |
2597 | This is called by one_pre_gcse_pass after all the dataflow analysis | |
2598 | has been done. | |
2599 | ||
2c084240 | 2600 | This is based on the original Morel-Renvoise paper Fred Chow's thesis, and |
2601 | lazy code motion from Knoop, Ruthing and Steffen as described in Advanced | |
2602 | Compiler Design and Implementation. | |
18aa2adf | 2603 | |
2c084240 | 2604 | ??? A new pseudo reg is created to hold the reaching expression. The nice |
2605 | thing about the classical approach is that it would try to use an existing | |
2606 | reg. If the register can't be adequately optimized [i.e. we introduce | |
2607 | reload problems], one could add a pass here to propagate the new register | |
2608 | through the block. | |
18aa2adf | 2609 | |
2c084240 | 2610 | ??? We don't handle single sets in PARALLELs because we're [currently] not |
2611 | able to copy the rest of the parallel when we insert copies to create full | |
2612 | redundancies from partial redundancies. However, there's no reason why we | |
2613 | can't handle PARALLELs in the cases where there are no partial | |
18aa2adf | 2614 | redundancies. */ |
2615 | ||
2616 | static int | |
bc8197c0 | 2617 | pre_gcse (struct edge_list *edge_list) |
18aa2adf | 2618 | { |
a08b57af | 2619 | unsigned int i; |
2620 | int did_insert, changed; | |
18aa2adf | 2621 | struct expr **index_map; |
2c084240 | 2622 | struct expr *expr; |
18aa2adf | 2623 | |
2624 | /* Compute a mapping from expression number (`bitmap_index') to | |
2625 | hash table entry. */ | |
2626 | ||
4c36ffe6 | 2627 | index_map = XCNEWVEC (struct expr *, expr_hash_table.n_elems); |
27cfe3f1 | 2628 | for (i = 0; i < expr_hash_table.size; i++) |
bc8197c0 | 2629 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
2c084240 | 2630 | index_map[expr->bitmap_index] = expr; |
18aa2adf | 2631 | |
18aa2adf | 2632 | /* Delete the redundant insns first so that |
2633 | - we know what register to use for the new insns and for the other | |
2634 | ones with reaching expressions | |
2635 | - we know which insns are redundant when we go to create copies */ | |
2c084240 | 2636 | |
18aa2adf | 2637 | changed = pre_delete (); |
7bcd381b | 2638 | did_insert = pre_edge_insert (edge_list, index_map); |
2c084240 | 2639 | |
18aa2adf | 2640 | /* In other places with reaching expressions, copy the expression to the |
7bcd381b | 2641 | specially allocated pseudo-reg that reaches the redundant expr. */ |
18aa2adf | 2642 | pre_insert_copies (); |
7bcd381b | 2643 | if (did_insert) |
2644 | { | |
2645 | commit_edge_insertions (); | |
2646 | changed = 1; | |
2647 | } | |
18aa2adf | 2648 | |
cd55d9d6 | 2649 | free (index_map); |
18aa2adf | 2650 | return changed; |
2651 | } | |
2652 | ||
2653 | /* Top level routine to perform one PRE GCSE pass. | |
2654 | ||
6ef828f9 | 2655 | Return nonzero if a change was made. */ |
18aa2adf | 2656 | |
2657 | static int | |
d743aba2 | 2658 | one_pre_gcse_pass (void) |
18aa2adf | 2659 | { |
2660 | int changed = 0; | |
2661 | ||
2662 | gcse_subst_count = 0; | |
2663 | gcse_create_count = 0; | |
2664 | ||
d743aba2 | 2665 | /* Return if there's nothing to do, or it is too expensive. */ |
a28770e1 | 2666 | if (n_basic_blocks_for_fn (cfun) <= NUM_FIXED_BLOCKS + 1 |
d743aba2 | 2667 | || is_too_expensive (_("PRE disabled"))) |
2668 | return 0; | |
2669 | ||
2670 | /* We need alias. */ | |
2671 | init_alias_analysis (); | |
2672 | ||
2673 | bytes_used = 0; | |
2674 | gcc_obstack_init (&gcse_obstack); | |
2675 | alloc_gcse_mem (); | |
2676 | ||
07abdb66 | 2677 | alloc_hash_table (&expr_hash_table); |
7bcd381b | 2678 | add_noreturn_fake_exit_edges (); |
8e802be9 | 2679 | if (flag_gcse_lm) |
2680 | compute_ld_motion_mems (); | |
2681 | ||
27cfe3f1 | 2682 | compute_hash_table (&expr_hash_table); |
bc8197c0 | 2683 | if (flag_gcse_lm) |
2684 | trim_ld_motion_mems (); | |
3f5be5f4 | 2685 | if (dump_file) |
2686 | dump_hash_table (dump_file, "Expression", &expr_hash_table); | |
2c084240 | 2687 | |
27cfe3f1 | 2688 | if (expr_hash_table.n_elems > 0) |
18aa2adf | 2689 | { |
bc8197c0 | 2690 | struct edge_list *edge_list; |
fe672ac0 | 2691 | alloc_pre_mem (last_basic_block_for_fn (cfun), expr_hash_table.n_elems); |
bc8197c0 | 2692 | edge_list = compute_pre_data (); |
2693 | changed |= pre_gcse (edge_list); | |
7bcd381b | 2694 | free_edge_list (edge_list); |
18aa2adf | 2695 | free_pre_mem (); |
2696 | } | |
2c084240 | 2697 | |
bc8197c0 | 2698 | if (flag_gcse_lm) |
2699 | free_ld_motion_mems (); | |
41d24834 | 2700 | remove_fake_exit_edges (); |
27cfe3f1 | 2701 | free_hash_table (&expr_hash_table); |
18aa2adf | 2702 | |
d743aba2 | 2703 | free_gcse_mem (); |
2704 | obstack_free (&gcse_obstack, NULL); | |
2705 | ||
2706 | /* We are finished with alias. */ | |
2707 | end_alias_analysis (); | |
2708 | ||
3f5be5f4 | 2709 | if (dump_file) |
18aa2adf | 2710 | { |
d743aba2 | 2711 | fprintf (dump_file, "PRE GCSE of %s, %d basic blocks, %d bytes needed, ", |
a28770e1 | 2712 | current_function_name (), n_basic_blocks_for_fn (cfun), |
2713 | bytes_used); | |
3f5be5f4 | 2714 | fprintf (dump_file, "%d substs, %d insns created\n", |
2c084240 | 2715 | gcse_subst_count, gcse_create_count); |
18aa2adf | 2716 | } |
2717 | ||
2718 | return changed; | |
2719 | } | |
322b2436 | 2720 | \f |
19d2fe05 | 2721 | /* If X contains any LABEL_REF's, add REG_LABEL_OPERAND notes for them |
2722 | to INSN. If such notes are added to an insn which references a | |
2723 | CODE_LABEL, the LABEL_NUSES count is incremented. We have to add | |
2724 | that note, because the following loop optimization pass requires | |
2725 | them. */ | |
322b2436 | 2726 | |
322b2436 | 2727 | /* ??? If there was a jump optimization pass after gcse and before loop, |
2728 | then we would not need to do this here, because jump would add the | |
19d2fe05 | 2729 | necessary REG_LABEL_OPERAND and REG_LABEL_TARGET notes. */ |
322b2436 | 2730 | |
2731 | static void | |
952f0048 | 2732 | add_label_notes (rtx x, rtx insn) |
322b2436 | 2733 | { |
2734 | enum rtx_code code = GET_CODE (x); | |
2735 | int i, j; | |
d2ca078f | 2736 | const char *fmt; |
322b2436 | 2737 | |
2738 | if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x)) | |
2739 | { | |
e72f55f8 | 2740 | /* This code used to ignore labels that referred to dispatch tables to |
d01481af | 2741 | avoid flow generating (slightly) worse code. |
e72f55f8 | 2742 | |
b65b4f63 | 2743 | We no longer ignore such label references (see LABEL_REF handling in |
2744 | mark_jump_label for additional information). */ | |
2c084240 | 2745 | |
a8d1dae0 | 2746 | /* There's no reason for current users to emit jump-insns with |
2747 | such a LABEL_REF, so we don't have to handle REG_LABEL_TARGET | |
2748 | notes. */ | |
2749 | gcc_assert (!JUMP_P (insn)); | |
a1ddb869 | 2750 | add_reg_note (insn, REG_LABEL_OPERAND, XEXP (x, 0)); |
2751 | ||
a8d1dae0 | 2752 | if (LABEL_P (XEXP (x, 0))) |
2753 | LABEL_NUSES (XEXP (x, 0))++; | |
2754 | ||
322b2436 | 2755 | return; |
2756 | } | |
2757 | ||
2c084240 | 2758 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--) |
322b2436 | 2759 | { |
2760 | if (fmt[i] == 'e') | |
2761 | add_label_notes (XEXP (x, i), insn); | |
2762 | else if (fmt[i] == 'E') | |
2763 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2764 | add_label_notes (XVECEXP (x, i, j), insn); | |
2765 | } | |
2766 | } | |
b3f3796c | 2767 | |
6627f3ed | 2768 | /* Code Hoisting variables and subroutines. */ |
2769 | ||
2770 | /* Very busy expressions. */ | |
2771 | static sbitmap *hoist_vbein; | |
2772 | static sbitmap *hoist_vbeout; | |
2773 | ||
6627f3ed | 2774 | /* ??? We could compute post dominators and run this algorithm in |
95cc2547 | 2775 | reverse to perform tail merging, doing so would probably be |
6627f3ed | 2776 | more effective than the tail merging code in jump.c. |
2777 | ||
2778 | It's unclear if tail merging could be run in parallel with | |
2779 | code hoisting. It would be nice. */ | |
2780 | ||
2781 | /* Allocate vars used for code hoisting analysis. */ | |
2782 | ||
2783 | static void | |
952f0048 | 2784 | alloc_code_hoist_mem (int n_blocks, int n_exprs) |
6627f3ed | 2785 | { |
2786 | antloc = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2787 | transp = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2788 | comp = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2789 | ||
2790 | hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2791 | hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs); | |
6627f3ed | 2792 | } |
2793 | ||
2794 | /* Free vars used for code hoisting analysis. */ | |
2795 | ||
2796 | static void | |
952f0048 | 2797 | free_code_hoist_mem (void) |
6627f3ed | 2798 | { |
cca23eb2 | 2799 | sbitmap_vector_free (antloc); |
2800 | sbitmap_vector_free (transp); | |
2801 | sbitmap_vector_free (comp); | |
6627f3ed | 2802 | |
cca23eb2 | 2803 | sbitmap_vector_free (hoist_vbein); |
2804 | sbitmap_vector_free (hoist_vbeout); | |
6627f3ed | 2805 | |
0051c76a | 2806 | free_dominance_info (CDI_DOMINATORS); |
6627f3ed | 2807 | } |
2808 | ||
2809 | /* Compute the very busy expressions at entry/exit from each block. | |
2810 | ||
2811 | An expression is very busy if all paths from a given point | |
2812 | compute the expression. */ | |
2813 | ||
2814 | static void | |
952f0048 | 2815 | compute_code_hoist_vbeinout (void) |
6627f3ed | 2816 | { |
4c26117a | 2817 | int changed, passes; |
2818 | basic_block bb; | |
6627f3ed | 2819 | |
fe672ac0 | 2820 | bitmap_vector_clear (hoist_vbeout, last_basic_block_for_fn (cfun)); |
2821 | bitmap_vector_clear (hoist_vbein, last_basic_block_for_fn (cfun)); | |
6627f3ed | 2822 | |
2823 | passes = 0; | |
2824 | changed = 1; | |
2c084240 | 2825 | |
6627f3ed | 2826 | while (changed) |
2827 | { | |
2828 | changed = 0; | |
2c084240 | 2829 | |
6627f3ed | 2830 | /* We scan the blocks in the reverse order to speed up |
2831 | the convergence. */ | |
4c26117a | 2832 | FOR_EACH_BB_REVERSE (bb) |
6627f3ed | 2833 | { |
34154e27 | 2834 | if (bb->next_bb != EXIT_BLOCK_PTR_FOR_FN (cfun)) |
33ff724a | 2835 | { |
08b7917c | 2836 | bitmap_intersection_of_succs (hoist_vbeout[bb->index], |
2837 | hoist_vbein, bb); | |
33ff724a | 2838 | |
2839 | /* Include expressions in VBEout that are calculated | |
2840 | in BB and available at its end. */ | |
53c5d9d4 | 2841 | bitmap_ior (hoist_vbeout[bb->index], |
33ff724a | 2842 | hoist_vbeout[bb->index], comp[bb->index]); |
2843 | } | |
0f11b6b5 | 2844 | |
53c5d9d4 | 2845 | changed |= bitmap_or_and (hoist_vbein[bb->index], |
0f11b6b5 | 2846 | antloc[bb->index], |
2847 | hoist_vbeout[bb->index], | |
2848 | transp[bb->index]); | |
6627f3ed | 2849 | } |
2c084240 | 2850 | |
6627f3ed | 2851 | passes++; |
2852 | } | |
2853 | ||
3f5be5f4 | 2854 | if (dump_file) |
c0939130 | 2855 | { |
2856 | fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); | |
2857 | ||
fc00614f | 2858 | FOR_EACH_BB_FN (bb, cfun) |
c0939130 | 2859 | { |
2860 | fprintf (dump_file, "vbein (%d): ", bb->index); | |
53c5d9d4 | 2861 | dump_bitmap_file (dump_file, hoist_vbein[bb->index]); |
c0939130 | 2862 | fprintf (dump_file, "vbeout(%d): ", bb->index); |
53c5d9d4 | 2863 | dump_bitmap_file (dump_file, hoist_vbeout[bb->index]); |
c0939130 | 2864 | } |
2865 | } | |
6627f3ed | 2866 | } |
2867 | ||
2868 | /* Top level routine to do the dataflow analysis needed by code hoisting. */ | |
2869 | ||
2870 | static void | |
952f0048 | 2871 | compute_code_hoist_data (void) |
6627f3ed | 2872 | { |
27cfe3f1 | 2873 | compute_local_properties (transp, comp, antloc, &expr_hash_table); |
f151d0c6 | 2874 | prune_expressions (false); |
6627f3ed | 2875 | compute_code_hoist_vbeinout (); |
0051c76a | 2876 | calculate_dominance_info (CDI_DOMINATORS); |
3f5be5f4 | 2877 | if (dump_file) |
2878 | fprintf (dump_file, "\n"); | |
6627f3ed | 2879 | } |
2880 | ||
ded17066 | 2881 | /* Update register pressure for BB when hoisting an expression from |
2882 | instruction FROM, if live ranges of inputs are shrunk. Also | |
2883 | maintain live_in information if live range of register referred | |
2884 | in FROM is shrunk. | |
2885 | ||
2886 | Return 0 if register pressure doesn't change, otherwise return | |
2887 | the number by which register pressure is decreased. | |
2888 | ||
2889 | NOTE: Register pressure won't be increased in this function. */ | |
2890 | ||
2891 | static int | |
2892 | update_bb_reg_pressure (basic_block bb, rtx from) | |
2893 | { | |
2894 | rtx dreg, insn; | |
2895 | basic_block succ_bb; | |
2896 | df_ref *op, op_ref; | |
2897 | edge succ; | |
2898 | edge_iterator ei; | |
2899 | int decreased_pressure = 0; | |
2900 | int nregs; | |
2901 | enum reg_class pressure_class; | |
2902 | ||
2903 | for (op = DF_INSN_USES (from); *op; op++) | |
2904 | { | |
2905 | dreg = DF_REF_REAL_REG (*op); | |
2906 | /* The live range of register is shrunk only if it isn't: | |
2907 | 1. referred on any path from the end of this block to EXIT, or | |
2908 | 2. referred by insns other than FROM in this block. */ | |
2909 | FOR_EACH_EDGE (succ, ei, bb->succs) | |
2910 | { | |
2911 | succ_bb = succ->dest; | |
34154e27 | 2912 | if (succ_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)) |
ded17066 | 2913 | continue; |
2914 | ||
2915 | if (bitmap_bit_p (BB_DATA (succ_bb)->live_in, REGNO (dreg))) | |
2916 | break; | |
2917 | } | |
2918 | if (succ != NULL) | |
2919 | continue; | |
2920 | ||
2921 | op_ref = DF_REG_USE_CHAIN (REGNO (dreg)); | |
2922 | for (; op_ref; op_ref = DF_REF_NEXT_REG (op_ref)) | |
2923 | { | |
2924 | if (!DF_REF_INSN_INFO (op_ref)) | |
2925 | continue; | |
2926 | ||
2927 | insn = DF_REF_INSN (op_ref); | |
2928 | if (BLOCK_FOR_INSN (insn) == bb | |
2929 | && NONDEBUG_INSN_P (insn) && insn != from) | |
2930 | break; | |
2931 | } | |
2932 | ||
2933 | pressure_class = get_regno_pressure_class (REGNO (dreg), &nregs); | |
2934 | /* Decrease register pressure and update live_in information for | |
2935 | this block. */ | |
2936 | if (!op_ref && pressure_class != NO_REGS) | |
2937 | { | |
2938 | decreased_pressure += nregs; | |
2939 | BB_DATA (bb)->max_reg_pressure[pressure_class] -= nregs; | |
2940 | bitmap_clear_bit (BB_DATA (bb)->live_in, REGNO (dreg)); | |
2941 | } | |
2942 | } | |
2943 | return decreased_pressure; | |
2944 | } | |
2945 | ||
1ec78e16 | 2946 | /* Determine if the expression EXPR should be hoisted to EXPR_BB up in |
2947 | flow graph, if it can reach BB unimpared. Stop the search if the | |
2948 | expression would need to be moved more than DISTANCE instructions. | |
2949 | ||
2950 | DISTANCE is the number of instructions through which EXPR can be | |
2951 | hoisted up in flow graph. | |
2952 | ||
2953 | BB_SIZE points to an array which contains the number of instructions | |
2954 | for each basic block. | |
2955 | ||
2956 | PRESSURE_CLASS and NREGS are register class and number of hard registers | |
2957 | for storing EXPR. | |
2958 | ||
2959 | HOISTED_BBS points to a bitmap indicating basic blocks through which | |
2960 | EXPR is hoisted. | |
6627f3ed | 2961 | |
ded17066 | 2962 | FROM is the instruction from which EXPR is hoisted. |
2963 | ||
6627f3ed | 2964 | It's unclear exactly what Muchnick meant by "unimpared". It seems |
2965 | to me that the expression must either be computed or transparent in | |
2966 | *every* block in the path(s) from EXPR_BB to BB. Any other definition | |
2967 | would allow the expression to be hoisted out of loops, even if | |
2968 | the expression wasn't a loop invariant. | |
2969 | ||
2970 | Contrast this to reachability for PRE where an expression is | |
2971 | considered reachable if *any* path reaches instead of *all* | |
2972 | paths. */ | |
2973 | ||
2974 | static int | |
1ec78e16 | 2975 | should_hoist_expr_to_dom (basic_block expr_bb, struct expr *expr, |
2976 | basic_block bb, sbitmap visited, int distance, | |
2977 | int *bb_size, enum reg_class pressure_class, | |
ded17066 | 2978 | int *nregs, bitmap hoisted_bbs, rtx from) |
6627f3ed | 2979 | { |
1ec78e16 | 2980 | unsigned int i; |
6627f3ed | 2981 | edge pred; |
cd665a06 | 2982 | edge_iterator ei; |
1ec78e16 | 2983 | sbitmap_iterator sbi; |
cd55d9d6 | 2984 | int visited_allocated_locally = 0; |
ded17066 | 2985 | int decreased_pressure = 0; |
3cfec666 | 2986 | |
ded17066 | 2987 | if (flag_ira_hoist_pressure) |
2988 | { | |
2989 | /* Record old information of basic block BB when it is visited | |
2990 | at the first time. */ | |
2991 | if (!bitmap_bit_p (hoisted_bbs, bb->index)) | |
2992 | { | |
2993 | struct bb_data *data = BB_DATA (bb); | |
2994 | bitmap_copy (data->backup, data->live_in); | |
2995 | data->old_pressure = data->max_reg_pressure[pressure_class]; | |
2996 | } | |
2997 | decreased_pressure = update_bb_reg_pressure (bb, from); | |
2998 | } | |
8b38b150 | 2999 | /* Terminate the search if distance, for which EXPR is allowed to move, |
3000 | is exhausted. */ | |
3001 | if (distance > 0) | |
3002 | { | |
ded17066 | 3003 | if (flag_ira_hoist_pressure) |
3004 | { | |
3005 | /* Prefer to hoist EXPR if register pressure is decreased. */ | |
3006 | if (decreased_pressure > *nregs) | |
3007 | distance += bb_size[bb->index]; | |
3008 | /* Let EXPR be hoisted through basic block at no cost if one | |
3009 | of following conditions is satisfied: | |
3010 | ||
3011 | 1. The basic block has low register pressure. | |
3012 | 2. Register pressure won't be increases after hoisting EXPR. | |
3013 | ||
3014 | Constant expressions is handled conservatively, because | |
3015 | hoisting constant expression aggressively results in worse | |
3016 | code. This decision is made by the observation of CSiBE | |
3017 | on ARM target, while it has no obvious effect on other | |
3018 | targets like x86, x86_64, mips and powerpc. */ | |
3019 | else if (CONST_INT_P (expr->expr) | |
3020 | || (BB_DATA (bb)->max_reg_pressure[pressure_class] | |
3021 | >= ira_class_hard_regs_num[pressure_class] | |
3022 | && decreased_pressure < *nregs)) | |
3023 | distance -= bb_size[bb->index]; | |
3024 | } | |
3025 | else | |
1ec78e16 | 3026 | distance -= bb_size[bb->index]; |
8b38b150 | 3027 | |
3028 | if (distance <= 0) | |
3029 | return 0; | |
3030 | } | |
3031 | else | |
3032 | gcc_assert (distance == 0); | |
6627f3ed | 3033 | |
3034 | if (visited == NULL) | |
3035 | { | |
387732c1 | 3036 | visited_allocated_locally = 1; |
fe672ac0 | 3037 | visited = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
53c5d9d4 | 3038 | bitmap_clear (visited); |
6627f3ed | 3039 | } |
3040 | ||
cd665a06 | 3041 | FOR_EACH_EDGE (pred, ei, bb->preds) |
6627f3ed | 3042 | { |
8d4a53c7 | 3043 | basic_block pred_bb = pred->src; |
6627f3ed | 3044 | |
34154e27 | 3045 | if (pred->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)) |
6627f3ed | 3046 | break; |
2e281af0 | 3047 | else if (pred_bb == expr_bb) |
3048 | continue; | |
08b7917c | 3049 | else if (bitmap_bit_p (visited, pred_bb->index)) |
6627f3ed | 3050 | continue; |
08b7917c | 3051 | else if (! bitmap_bit_p (transp[pred_bb->index], expr->bitmap_index)) |
6627f3ed | 3052 | break; |
3053 | /* Not killed. */ | |
3054 | else | |
3055 | { | |
08b7917c | 3056 | bitmap_set_bit (visited, pred_bb->index); |
1ec78e16 | 3057 | if (! should_hoist_expr_to_dom (expr_bb, expr, pred_bb, |
3058 | visited, distance, bb_size, | |
ded17066 | 3059 | pressure_class, nregs, |
3060 | hoisted_bbs, from)) | |
6627f3ed | 3061 | break; |
3062 | } | |
3063 | } | |
3cfec666 | 3064 | if (visited_allocated_locally) |
1ec78e16 | 3065 | { |
3066 | /* If EXPR can be hoisted to expr_bb, record basic blocks through | |
ded17066 | 3067 | which EXPR is hoisted in hoisted_bbs. */ |
1ec78e16 | 3068 | if (flag_ira_hoist_pressure && !pred) |
3069 | { | |
ded17066 | 3070 | /* Record the basic block from which EXPR is hoisted. */ |
3071 | bitmap_set_bit (visited, bb->index); | |
0d211963 | 3072 | EXECUTE_IF_SET_IN_BITMAP (visited, 0, i, sbi) |
ded17066 | 3073 | bitmap_set_bit (hoisted_bbs, i); |
1ec78e16 | 3074 | } |
3075 | sbitmap_free (visited); | |
3076 | } | |
2c084240 | 3077 | |
6627f3ed | 3078 | return (pred == NULL); |
3079 | } | |
3080 | \f | |
9d75589a | 3081 | /* Find occurrence in BB. */ |
bc8197c0 | 3082 | |
8b38b150 | 3083 | static struct occr * |
3084 | find_occr_in_bb (struct occr *occr, basic_block bb) | |
3085 | { | |
3086 | /* Find the right occurrence of this expression. */ | |
3087 | while (occr && BLOCK_FOR_INSN (occr->insn) != bb) | |
3088 | occr = occr->next; | |
3089 | ||
3090 | return occr; | |
3091 | } | |
3092 | ||
1ec78e16 | 3093 | /* Actually perform code hoisting. |
3094 | ||
3095 | The code hoisting pass can hoist multiple computations of the same | |
3096 | expression along dominated path to a dominating basic block, like | |
3097 | from b2/b3 to b1 as depicted below: | |
3098 | ||
3099 | b1 ------ | |
3100 | /\ | | |
3101 | / \ | | |
3102 | bx by distance | |
3103 | / \ | | |
3104 | / \ | | |
3105 | b2 b3 ------ | |
3106 | ||
3107 | Unfortunately code hoisting generally extends the live range of an | |
3108 | output pseudo register, which increases register pressure and hurts | |
3109 | register allocation. To address this issue, an attribute MAX_DISTANCE | |
3110 | is computed and attached to each expression. The attribute is computed | |
3111 | from rtx cost of the corresponding expression and it's used to control | |
3112 | how long the expression can be hoisted up in flow graph. As the | |
3113 | expression is hoisted up in flow graph, GCC decreases its DISTANCE | |
ded17066 | 3114 | and stops the hoist if DISTANCE reaches 0. Code hoisting can decrease |
3115 | register pressure if live ranges of inputs are shrunk. | |
1ec78e16 | 3116 | |
3117 | Option "-fira-hoist-pressure" implements register pressure directed | |
3118 | hoist based on upper method. The rationale is: | |
3119 | 1. Calculate register pressure for each basic block by reusing IRA | |
3120 | facility. | |
3121 | 2. When expression is hoisted through one basic block, GCC checks | |
ded17066 | 3122 | the change of live ranges for inputs/output. The basic block's |
3123 | register pressure will be increased because of extended live | |
3124 | range of output. However, register pressure will be decreased | |
3125 | if the live ranges of inputs are shrunk. | |
3126 | 3. After knowing how hoisting affects register pressure, GCC prefers | |
3127 | to hoist the expression if it can decrease register pressure, by | |
3128 | increasing DISTANCE of the corresponding expression. | |
3129 | 4. If hoisting the expression increases register pressure, GCC checks | |
3130 | register pressure of the basic block and decrease DISTANCE only if | |
3131 | the register pressure is high. In other words, expression will be | |
3132 | hoisted through at no cost if the basic block has low register | |
3133 | pressure. | |
3134 | 5. Update register pressure information for basic blocks through | |
3135 | which expression is hoisted. */ | |
2c084240 | 3136 | |
d743aba2 | 3137 | static int |
952f0048 | 3138 | hoist_code (void) |
6627f3ed | 3139 | { |
4c26117a | 3140 | basic_block bb, dominated; |
f1f41a6c | 3141 | vec<basic_block> dom_tree_walk; |
c0939130 | 3142 | unsigned int dom_tree_walk_index; |
f1f41a6c | 3143 | vec<basic_block> domby; |
1ec78e16 | 3144 | unsigned int i, j, k; |
6627f3ed | 3145 | struct expr **index_map; |
2c084240 | 3146 | struct expr *expr; |
8b38b150 | 3147 | int *to_bb_head; |
3148 | int *bb_size; | |
d743aba2 | 3149 | int changed = 0; |
1ec78e16 | 3150 | struct bb_data *data; |
3151 | /* Basic blocks that have occurrences reachable from BB. */ | |
3152 | bitmap from_bbs; | |
3153 | /* Basic blocks through which expr is hoisted. */ | |
3154 | bitmap hoisted_bbs = NULL; | |
3155 | bitmap_iterator bi; | |
6627f3ed | 3156 | |
6627f3ed | 3157 | /* Compute a mapping from expression number (`bitmap_index') to |
3158 | hash table entry. */ | |
3159 | ||
4c36ffe6 | 3160 | index_map = XCNEWVEC (struct expr *, expr_hash_table.n_elems); |
27cfe3f1 | 3161 | for (i = 0; i < expr_hash_table.size; i++) |
bc8197c0 | 3162 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
2c084240 | 3163 | index_map[expr->bitmap_index] = expr; |
6627f3ed | 3164 | |
8b38b150 | 3165 | /* Calculate sizes of basic blocks and note how far |
3166 | each instruction is from the start of its block. We then use this | |
3167 | data to restrict distance an expression can travel. */ | |
3168 | ||
3169 | to_bb_head = XCNEWVEC (int, get_max_uid ()); | |
fe672ac0 | 3170 | bb_size = XCNEWVEC (int, last_basic_block_for_fn (cfun)); |
8b38b150 | 3171 | |
fc00614f | 3172 | FOR_EACH_BB_FN (bb, cfun) |
8b38b150 | 3173 | { |
3174 | rtx insn; | |
8b38b150 | 3175 | int to_head; |
3176 | ||
8b38b150 | 3177 | to_head = 0; |
2241e3a7 | 3178 | FOR_BB_INSNS (bb, insn) |
8b38b150 | 3179 | { |
3180 | /* Don't count debug instructions to avoid them affecting | |
3181 | decision choices. */ | |
3182 | if (NONDEBUG_INSN_P (insn)) | |
3183 | to_bb_head[INSN_UID (insn)] = to_head++; | |
8b38b150 | 3184 | } |
3185 | ||
3186 | bb_size[bb->index] = to_head; | |
3187 | } | |
3188 | ||
34154e27 | 3189 | gcc_assert (EDGE_COUNT (ENTRY_BLOCK_PTR_FOR_FN (cfun)->succs) == 1 |
3190 | && (EDGE_SUCC (ENTRY_BLOCK_PTR_FOR_FN (cfun), 0)->dest | |
3191 | == ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb)); | |
c0939130 | 3192 | |
1ec78e16 | 3193 | from_bbs = BITMAP_ALLOC (NULL); |
3194 | if (flag_ira_hoist_pressure) | |
3195 | hoisted_bbs = BITMAP_ALLOC (NULL); | |
3196 | ||
c0939130 | 3197 | dom_tree_walk = get_all_dominated_blocks (CDI_DOMINATORS, |
34154e27 | 3198 | ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb); |
c0939130 | 3199 | |
6627f3ed | 3200 | /* Walk over each basic block looking for potentially hoistable |
3201 | expressions, nothing gets hoisted from the entry block. */ | |
f1f41a6c | 3202 | FOR_EACH_VEC_ELT (dom_tree_walk, dom_tree_walk_index, bb) |
6627f3ed | 3203 | { |
c0939130 | 3204 | domby = get_dominated_to_depth (CDI_DOMINATORS, bb, MAX_HOIST_DEPTH); |
3205 | ||
f1f41a6c | 3206 | if (domby.length () == 0) |
c0939130 | 3207 | continue; |
6627f3ed | 3208 | |
3209 | /* Examine each expression that is very busy at the exit of this | |
3210 | block. These are the potentially hoistable expressions. */ | |
156093aa | 3211 | for (i = 0; i < SBITMAP_SIZE (hoist_vbeout[bb->index]); i++) |
6627f3ed | 3212 | { |
08b7917c | 3213 | if (bitmap_bit_p (hoist_vbeout[bb->index], i)) |
6627f3ed | 3214 | { |
1ec78e16 | 3215 | int nregs = 0; |
3216 | enum reg_class pressure_class = NO_REGS; | |
c0939130 | 3217 | /* Current expression. */ |
3218 | struct expr *expr = index_map[i]; | |
9d75589a | 3219 | /* Number of occurrences of EXPR that can be hoisted to BB. */ |
c0939130 | 3220 | int hoistable = 0; |
9d75589a | 3221 | /* Occurrences reachable from BB. */ |
1e094109 | 3222 | vec<occr_t> occrs_to_hoist = vNULL; |
c0939130 | 3223 | /* We want to insert the expression into BB only once, so |
3224 | note when we've inserted it. */ | |
3225 | int insn_inserted_p; | |
3226 | occr_t occr; | |
3227 | ||
33ff724a | 3228 | /* If an expression is computed in BB and is available at end of |
9d75589a | 3229 | BB, hoist all occurrences dominated by BB to BB. */ |
08b7917c | 3230 | if (bitmap_bit_p (comp[bb->index], i)) |
c0939130 | 3231 | { |
3232 | occr = find_occr_in_bb (expr->antic_occr, bb); | |
3233 | ||
3234 | if (occr) | |
3235 | { | |
9d75589a | 3236 | /* An occurrence might've been already deleted |
c0939130 | 3237 | while processing a dominator of BB. */ |
c96e0a0a | 3238 | if (!occr->deleted_p) |
c0939130 | 3239 | { |
3240 | gcc_assert (NONDEBUG_INSN_P (occr->insn)); | |
3241 | hoistable++; | |
3242 | } | |
3243 | } | |
3244 | else | |
3245 | hoistable++; | |
3246 | } | |
33ff724a | 3247 | |
6627f3ed | 3248 | /* We've found a potentially hoistable expression, now |
3249 | we look at every block BB dominates to see if it | |
3250 | computes the expression. */ | |
f1f41a6c | 3251 | FOR_EACH_VEC_ELT (domby, j, dominated) |
6627f3ed | 3252 | { |
8b38b150 | 3253 | int max_distance; |
3254 | ||
6627f3ed | 3255 | /* Ignore self dominance. */ |
8c4bd339 | 3256 | if (bb == dominated) |
6627f3ed | 3257 | continue; |
6627f3ed | 3258 | /* We've found a dominated block, now see if it computes |
3259 | the busy expression and whether or not moving that | |
3260 | expression to the "beginning" of that block is safe. */ | |
08b7917c | 3261 | if (!bitmap_bit_p (antloc[dominated->index], i)) |
6627f3ed | 3262 | continue; |
3263 | ||
c0939130 | 3264 | occr = find_occr_in_bb (expr->antic_occr, dominated); |
3265 | gcc_assert (occr); | |
8b38b150 | 3266 | |
9d75589a | 3267 | /* An occurrence might've been already deleted |
c0939130 | 3268 | while processing a dominator of BB. */ |
3269 | if (occr->deleted_p) | |
c96e0a0a | 3270 | continue; |
c0939130 | 3271 | gcc_assert (NONDEBUG_INSN_P (occr->insn)); |
3272 | ||
3273 | max_distance = expr->max_distance; | |
3274 | if (max_distance > 0) | |
3275 | /* Adjust MAX_DISTANCE to account for the fact that | |
3276 | OCCR won't have to travel all of DOMINATED, but | |
3277 | only part of it. */ | |
3278 | max_distance += (bb_size[dominated->index] | |
3279 | - to_bb_head[INSN_UID (occr->insn)]); | |
8b38b150 | 3280 | |
1ec78e16 | 3281 | pressure_class = get_pressure_class_and_nregs (occr->insn, |
3282 | &nregs); | |
3283 | ||
3284 | /* Note if the expression should be hoisted from the dominated | |
3285 | block to BB if it can reach DOMINATED unimpared. | |
6627f3ed | 3286 | |
3287 | Keep track of how many times this expression is hoistable | |
3288 | from a dominated block into BB. */ | |
1ec78e16 | 3289 | if (should_hoist_expr_to_dom (bb, expr, dominated, NULL, |
3290 | max_distance, bb_size, | |
3291 | pressure_class, &nregs, | |
ded17066 | 3292 | hoisted_bbs, occr->insn)) |
c0939130 | 3293 | { |
3294 | hoistable++; | |
f1f41a6c | 3295 | occrs_to_hoist.safe_push (occr); |
c0939130 | 3296 | bitmap_set_bit (from_bbs, dominated->index); |
3297 | } | |
6627f3ed | 3298 | } |
3299 | ||
424da949 | 3300 | /* If we found more than one hoistable occurrence of this |
c0939130 | 3301 | expression, then note it in the vector of expressions to |
6627f3ed | 3302 | hoist. It makes no sense to hoist things which are computed |
3303 | in only one BB, and doing so tends to pessimize register | |
3304 | allocation. One could increase this value to try harder | |
3305 | to avoid any possible code expansion due to register | |
3306 | allocation issues; however experiments have shown that | |
3307 | the vast majority of hoistable expressions are only movable | |
d01481af | 3308 | from two successors, so raising this threshold is likely |
6627f3ed | 3309 | to nullify any benefit we get from code hoisting. */ |
da54886a | 3310 | if (hoistable > 1 && dbg_cnt (hoist_insn)) |
6627f3ed | 3311 | { |
f1f41a6c | 3312 | /* If (hoistable != vec::length), then there is |
9d75589a | 3313 | an occurrence of EXPR in BB itself. Don't waste |
c0939130 | 3314 | time looking for LCA in this case. */ |
f1f41a6c | 3315 | if ((unsigned) hoistable == occrs_to_hoist.length ()) |
c0939130 | 3316 | { |
3317 | basic_block lca; | |
3318 | ||
3319 | lca = nearest_common_dominator_for_set (CDI_DOMINATORS, | |
3320 | from_bbs); | |
3321 | if (lca != bb) | |
9d75589a | 3322 | /* Punt, it's better to hoist these occurrences to |
c0939130 | 3323 | LCA. */ |
f1f41a6c | 3324 | occrs_to_hoist.release (); |
c0939130 | 3325 | } |
6627f3ed | 3326 | } |
c0939130 | 3327 | else |
a04e8d62 | 3328 | /* Punt, no point hoisting a single occurrence. */ |
f1f41a6c | 3329 | occrs_to_hoist.release (); |
6627f3ed | 3330 | |
1ec78e16 | 3331 | if (flag_ira_hoist_pressure |
f1f41a6c | 3332 | && !occrs_to_hoist.is_empty ()) |
1ec78e16 | 3333 | { |
ded17066 | 3334 | /* Increase register pressure of basic blocks to which |
3335 | expr is hoisted because of extended live range of | |
3336 | output. */ | |
1ec78e16 | 3337 | data = BB_DATA (bb); |
3338 | data->max_reg_pressure[pressure_class] += nregs; | |
ded17066 | 3339 | EXECUTE_IF_SET_IN_BITMAP (hoisted_bbs, 0, k, bi) |
3340 | { | |
f5a6b05f | 3341 | data = BB_DATA (BASIC_BLOCK_FOR_FN (cfun, k)); |
ded17066 | 3342 | data->max_reg_pressure[pressure_class] += nregs; |
3343 | } | |
1ec78e16 | 3344 | } |
3345 | else if (flag_ira_hoist_pressure) | |
3346 | { | |
ded17066 | 3347 | /* Restore register pressure and live_in info for basic |
3348 | blocks recorded in hoisted_bbs when expr will not be | |
3349 | hoisted. */ | |
1ec78e16 | 3350 | EXECUTE_IF_SET_IN_BITMAP (hoisted_bbs, 0, k, bi) |
3351 | { | |
f5a6b05f | 3352 | data = BB_DATA (BASIC_BLOCK_FOR_FN (cfun, k)); |
ded17066 | 3353 | bitmap_copy (data->live_in, data->backup); |
3354 | data->max_reg_pressure[pressure_class] | |
3355 | = data->old_pressure; | |
1ec78e16 | 3356 | } |
3357 | } | |
3358 | ||
3359 | if (flag_ira_hoist_pressure) | |
3360 | bitmap_clear (hoisted_bbs); | |
3361 | ||
c0939130 | 3362 | insn_inserted_p = 0; |
6627f3ed | 3363 | |
9d75589a | 3364 | /* Walk through occurrences of I'th expressions we want |
c0939130 | 3365 | to hoist to BB and make the transformations. */ |
f1f41a6c | 3366 | FOR_EACH_VEC_ELT (occrs_to_hoist, j, occr) |
6627f3ed | 3367 | { |
c0939130 | 3368 | rtx insn; |
3369 | rtx set; | |
3370 | ||
3371 | gcc_assert (!occr->deleted_p); | |
3372 | ||
3373 | insn = occr->insn; | |
3374 | set = single_set (insn); | |
3375 | gcc_assert (set); | |
3376 | ||
3377 | /* Create a pseudo-reg to store the result of reaching | |
3378 | expressions into. Get the mode for the new pseudo | |
3379 | from the mode of the original destination pseudo. | |
3380 | ||
3381 | It is important to use new pseudos whenever we | |
3382 | emit a set. This will allow reload to use | |
3383 | rematerialization for such registers. */ | |
3384 | if (!insn_inserted_p) | |
3385 | expr->reaching_reg | |
3386 | = gen_reg_rtx_and_attrs (SET_DEST (set)); | |
3387 | ||
bc8197c0 | 3388 | gcse_emit_move_after (SET_DEST (set), expr->reaching_reg, |
c0939130 | 3389 | insn); |
3390 | delete_insn (insn); | |
3391 | occr->deleted_p = 1; | |
3392 | changed = 1; | |
3393 | gcse_subst_count++; | |
3394 | ||
3395 | if (!insn_inserted_p) | |
6627f3ed | 3396 | { |
c0939130 | 3397 | insert_insn_end_basic_block (expr, bb); |
3398 | insn_inserted_p = 1; | |
6627f3ed | 3399 | } |
3400 | } | |
c0939130 | 3401 | |
f1f41a6c | 3402 | occrs_to_hoist.release (); |
c0939130 | 3403 | bitmap_clear (from_bbs); |
6627f3ed | 3404 | } |
3405 | } | |
f1f41a6c | 3406 | domby.release (); |
6627f3ed | 3407 | } |
2c084240 | 3408 | |
f1f41a6c | 3409 | dom_tree_walk.release (); |
1ec78e16 | 3410 | BITMAP_FREE (from_bbs); |
3411 | if (flag_ira_hoist_pressure) | |
3412 | BITMAP_FREE (hoisted_bbs); | |
3413 | ||
8b38b150 | 3414 | free (bb_size); |
3415 | free (to_bb_head); | |
387732c1 | 3416 | free (index_map); |
d743aba2 | 3417 | |
3418 | return changed; | |
6627f3ed | 3419 | } |
3420 | ||
1ec78e16 | 3421 | /* Return pressure class and number of needed hard registers (through |
3422 | *NREGS) of register REGNO. */ | |
3423 | static enum reg_class | |
3424 | get_regno_pressure_class (int regno, int *nregs) | |
3425 | { | |
3426 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3427 | { | |
3428 | enum reg_class pressure_class; | |
3429 | ||
3430 | pressure_class = reg_allocno_class (regno); | |
3431 | pressure_class = ira_pressure_class_translate[pressure_class]; | |
3432 | *nregs | |
3433 | = ira_reg_class_max_nregs[pressure_class][PSEUDO_REGNO_MODE (regno)]; | |
3434 | return pressure_class; | |
3435 | } | |
3436 | else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno) | |
3437 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
3438 | { | |
3439 | *nregs = 1; | |
3440 | return ira_pressure_class_translate[REGNO_REG_CLASS (regno)]; | |
3441 | } | |
3442 | else | |
3443 | { | |
3444 | *nregs = 0; | |
3445 | return NO_REGS; | |
3446 | } | |
3447 | } | |
3448 | ||
3449 | /* Return pressure class and number of hard registers (through *NREGS) | |
3450 | for destination of INSN. */ | |
3451 | static enum reg_class | |
3452 | get_pressure_class_and_nregs (rtx insn, int *nregs) | |
3453 | { | |
3454 | rtx reg; | |
3455 | enum reg_class pressure_class; | |
3456 | rtx set = single_set (insn); | |
3457 | ||
3458 | /* Considered invariant insns have only one set. */ | |
3459 | gcc_assert (set != NULL_RTX); | |
3460 | reg = SET_DEST (set); | |
3461 | if (GET_CODE (reg) == SUBREG) | |
3462 | reg = SUBREG_REG (reg); | |
3463 | if (MEM_P (reg)) | |
3464 | { | |
3465 | *nregs = 0; | |
3466 | pressure_class = NO_REGS; | |
3467 | } | |
3468 | else | |
3469 | { | |
3470 | gcc_assert (REG_P (reg)); | |
3471 | pressure_class = reg_allocno_class (REGNO (reg)); | |
3472 | pressure_class = ira_pressure_class_translate[pressure_class]; | |
3473 | *nregs | |
3474 | = ira_reg_class_max_nregs[pressure_class][GET_MODE (SET_SRC (set))]; | |
3475 | } | |
3476 | return pressure_class; | |
3477 | } | |
3478 | ||
3479 | /* Increase (if INCR_P) or decrease current register pressure for | |
3480 | register REGNO. */ | |
3481 | static void | |
3482 | change_pressure (int regno, bool incr_p) | |
3483 | { | |
3484 | int nregs; | |
3485 | enum reg_class pressure_class; | |
3486 | ||
3487 | pressure_class = get_regno_pressure_class (regno, &nregs); | |
3488 | if (! incr_p) | |
3489 | curr_reg_pressure[pressure_class] -= nregs; | |
3490 | else | |
3491 | { | |
3492 | curr_reg_pressure[pressure_class] += nregs; | |
3493 | if (BB_DATA (curr_bb)->max_reg_pressure[pressure_class] | |
3494 | < curr_reg_pressure[pressure_class]) | |
3495 | BB_DATA (curr_bb)->max_reg_pressure[pressure_class] | |
3496 | = curr_reg_pressure[pressure_class]; | |
3497 | } | |
3498 | } | |
3499 | ||
3500 | /* Calculate register pressure for each basic block by walking insns | |
3501 | from last to first. */ | |
3502 | static void | |
3503 | calculate_bb_reg_pressure (void) | |
3504 | { | |
3505 | int i; | |
3506 | unsigned int j; | |
3507 | rtx insn; | |
3508 | basic_block bb; | |
3509 | bitmap curr_regs_live; | |
3510 | bitmap_iterator bi; | |
3511 | ||
3512 | ||
3b3a5e5f | 3513 | ira_setup_eliminable_regset (); |
1ec78e16 | 3514 | curr_regs_live = BITMAP_ALLOC (®_obstack); |
fc00614f | 3515 | FOR_EACH_BB_FN (bb, cfun) |
1ec78e16 | 3516 | { |
3517 | curr_bb = bb; | |
ded17066 | 3518 | BB_DATA (bb)->live_in = BITMAP_ALLOC (NULL); |
3519 | BB_DATA (bb)->backup = BITMAP_ALLOC (NULL); | |
3520 | bitmap_copy (BB_DATA (bb)->live_in, df_get_live_in (bb)); | |
3521 | bitmap_copy (curr_regs_live, df_get_live_out (bb)); | |
1ec78e16 | 3522 | for (i = 0; i < ira_pressure_classes_num; i++) |
3523 | curr_reg_pressure[ira_pressure_classes[i]] = 0; | |
3524 | EXECUTE_IF_SET_IN_BITMAP (curr_regs_live, 0, j, bi) | |
3525 | change_pressure (j, true); | |
3526 | ||
3527 | FOR_BB_INSNS_REVERSE (bb, insn) | |
3528 | { | |
3529 | rtx dreg; | |
3530 | int regno; | |
3531 | df_ref *def_rec, *use_rec; | |
3532 | ||
3533 | if (! NONDEBUG_INSN_P (insn)) | |
3534 | continue; | |
3535 | ||
3536 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
3537 | { | |
3538 | dreg = DF_REF_REAL_REG (*def_rec); | |
3539 | gcc_assert (REG_P (dreg)); | |
3540 | regno = REGNO (dreg); | |
3541 | if (!(DF_REF_FLAGS (*def_rec) | |
3542 | & (DF_REF_PARTIAL | DF_REF_CONDITIONAL))) | |
3543 | { | |
3544 | if (bitmap_clear_bit (curr_regs_live, regno)) | |
3545 | change_pressure (regno, false); | |
3546 | } | |
3547 | } | |
3548 | ||
3549 | for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
3550 | { | |
3551 | dreg = DF_REF_REAL_REG (*use_rec); | |
3552 | gcc_assert (REG_P (dreg)); | |
3553 | regno = REGNO (dreg); | |
3554 | if (bitmap_set_bit (curr_regs_live, regno)) | |
3555 | change_pressure (regno, true); | |
3556 | } | |
3557 | } | |
3558 | } | |
3559 | BITMAP_FREE (curr_regs_live); | |
3560 | ||
3561 | if (dump_file == NULL) | |
3562 | return; | |
3563 | ||
3564 | fprintf (dump_file, "\nRegister Pressure: \n"); | |
fc00614f | 3565 | FOR_EACH_BB_FN (bb, cfun) |
1ec78e16 | 3566 | { |
3567 | fprintf (dump_file, " Basic block %d: \n", bb->index); | |
3568 | for (i = 0; (int) i < ira_pressure_classes_num; i++) | |
3569 | { | |
3570 | enum reg_class pressure_class; | |
3571 | ||
3572 | pressure_class = ira_pressure_classes[i]; | |
3573 | if (BB_DATA (bb)->max_reg_pressure[pressure_class] == 0) | |
3574 | continue; | |
3575 | ||
3576 | fprintf (dump_file, " %s=%d\n", reg_class_names[pressure_class], | |
3577 | BB_DATA (bb)->max_reg_pressure[pressure_class]); | |
3578 | } | |
3579 | } | |
3580 | fprintf (dump_file, "\n"); | |
3581 | } | |
3582 | ||
6627f3ed | 3583 | /* Top level routine to perform one code hoisting (aka unification) pass |
3584 | ||
6ef828f9 | 3585 | Return nonzero if a change was made. */ |
6627f3ed | 3586 | |
3587 | static int | |
952f0048 | 3588 | one_code_hoisting_pass (void) |
6627f3ed | 3589 | { |
3590 | int changed = 0; | |
3591 | ||
d743aba2 | 3592 | gcse_subst_count = 0; |
3593 | gcse_create_count = 0; | |
3594 | ||
3595 | /* Return if there's nothing to do, or it is too expensive. */ | |
a28770e1 | 3596 | if (n_basic_blocks_for_fn (cfun) <= NUM_FIXED_BLOCKS + 1 |
d743aba2 | 3597 | || is_too_expensive (_("GCSE disabled"))) |
3598 | return 0; | |
3599 | ||
8b38b150 | 3600 | doing_code_hoisting_p = true; |
3601 | ||
1ec78e16 | 3602 | /* Calculate register pressure for each basic block. */ |
3603 | if (flag_ira_hoist_pressure) | |
3604 | { | |
3605 | regstat_init_n_sets_and_refs (); | |
3606 | ira_set_pseudo_classes (false, dump_file); | |
3607 | alloc_aux_for_blocks (sizeof (struct bb_data)); | |
3608 | calculate_bb_reg_pressure (); | |
3609 | regstat_free_n_sets_and_refs (); | |
3610 | } | |
3611 | ||
d743aba2 | 3612 | /* We need alias. */ |
3613 | init_alias_analysis (); | |
3614 | ||
3615 | bytes_used = 0; | |
3616 | gcc_obstack_init (&gcse_obstack); | |
3617 | alloc_gcse_mem (); | |
3618 | ||
07abdb66 | 3619 | alloc_hash_table (&expr_hash_table); |
27cfe3f1 | 3620 | compute_hash_table (&expr_hash_table); |
3f5be5f4 | 3621 | if (dump_file) |
3622 | dump_hash_table (dump_file, "Code Hosting Expressions", &expr_hash_table); | |
2c084240 | 3623 | |
27cfe3f1 | 3624 | if (expr_hash_table.n_elems > 0) |
6627f3ed | 3625 | { |
fe672ac0 | 3626 | alloc_code_hoist_mem (last_basic_block_for_fn (cfun), |
3627 | expr_hash_table.n_elems); | |
6627f3ed | 3628 | compute_code_hoist_data (); |
d743aba2 | 3629 | changed = hoist_code (); |
6627f3ed | 3630 | free_code_hoist_mem (); |
3631 | } | |
2c084240 | 3632 | |
1ec78e16 | 3633 | if (flag_ira_hoist_pressure) |
3634 | { | |
3635 | free_aux_for_blocks (); | |
3636 | free_reg_info (); | |
3637 | } | |
27cfe3f1 | 3638 | free_hash_table (&expr_hash_table); |
d743aba2 | 3639 | free_gcse_mem (); |
3640 | obstack_free (&gcse_obstack, NULL); | |
3641 | ||
3642 | /* We are finished with alias. */ | |
3643 | end_alias_analysis (); | |
3644 | ||
3645 | if (dump_file) | |
3646 | { | |
3647 | fprintf (dump_file, "HOIST of %s, %d basic blocks, %d bytes needed, ", | |
a28770e1 | 3648 | current_function_name (), n_basic_blocks_for_fn (cfun), |
3649 | bytes_used); | |
d743aba2 | 3650 | fprintf (dump_file, "%d substs, %d insns created\n", |
3651 | gcse_subst_count, gcse_create_count); | |
3652 | } | |
6627f3ed | 3653 | |
8b38b150 | 3654 | doing_code_hoisting_p = false; |
3655 | ||
6627f3ed | 3656 | return changed; |
3657 | } | |
8e802be9 | 3658 | \f |
bc8197c0 | 3659 | /* Here we provide the things required to do store motion towards the exit. |
3660 | In order for this to be effective, gcse also needed to be taught how to | |
3661 | move a load when it is killed only by a store to itself. | |
8e802be9 | 3662 | |
3663 | int i; | |
3664 | float a[10]; | |
3665 | ||
3666 | void foo(float scale) | |
3667 | { | |
3668 | for (i=0; i<10; i++) | |
3669 | a[i] *= scale; | |
3670 | } | |
3671 | ||
3672 | 'i' is both loaded and stored to in the loop. Normally, gcse cannot move | |
3cfec666 | 3673 | the load out since its live around the loop, and stored at the bottom |
3674 | of the loop. | |
8e802be9 | 3675 | |
3cfec666 | 3676 | The 'Load Motion' referred to and implemented in this file is |
bc8197c0 | 3677 | an enhancement to gcse which when using edge based LCM, recognizes |
8e802be9 | 3678 | this situation and allows gcse to move the load out of the loop. |
3679 | ||
3680 | Once gcse has hoisted the load, store motion can then push this | |
3681 | load towards the exit, and we end up with no loads or stores of 'i' | |
3682 | in the loop. */ | |
3683 | ||
424da949 | 3684 | /* This will search the ldst list for a matching expression. If it |
8e802be9 | 3685 | doesn't find one, we create one and initialize it. */ |
3686 | ||
3687 | static struct ls_expr * | |
952f0048 | 3688 | ldst_entry (rtx x) |
8e802be9 | 3689 | { |
69333952 | 3690 | int do_not_record_p = 0; |
8e802be9 | 3691 | struct ls_expr * ptr; |
69333952 | 3692 | unsigned int hash; |
d9dd21a8 | 3693 | ls_expr **slot; |
0d707271 | 3694 | struct ls_expr e; |
8e802be9 | 3695 | |
78d140c9 | 3696 | hash = hash_rtx (x, GET_MODE (x), &do_not_record_p, |
3697 | NULL, /*have_reg_qty=*/false); | |
8e802be9 | 3698 | |
0d707271 | 3699 | e.pattern = x; |
d9dd21a8 | 3700 | slot = pre_ldst_table.find_slot_with_hash (&e, hash, INSERT); |
0d707271 | 3701 | if (*slot) |
d9dd21a8 | 3702 | return *slot; |
69333952 | 3703 | |
4c36ffe6 | 3704 | ptr = XNEW (struct ls_expr); |
69333952 | 3705 | |
3706 | ptr->next = pre_ldst_mems; | |
3707 | ptr->expr = NULL; | |
3708 | ptr->pattern = x; | |
3709 | ptr->pattern_regs = NULL_RTX; | |
3710 | ptr->loads = NULL_RTX; | |
3711 | ptr->stores = NULL_RTX; | |
3712 | ptr->reaching_reg = NULL_RTX; | |
3713 | ptr->invalid = 0; | |
3714 | ptr->index = 0; | |
3715 | ptr->hash_index = hash; | |
3716 | pre_ldst_mems = ptr; | |
0d707271 | 3717 | *slot = ptr; |
3cfec666 | 3718 | |
8e802be9 | 3719 | return ptr; |
3720 | } | |
3721 | ||
3722 | /* Free up an individual ldst entry. */ | |
3723 | ||
3cfec666 | 3724 | static void |
952f0048 | 3725 | free_ldst_entry (struct ls_expr * ptr) |
8e802be9 | 3726 | { |
7a676a9f | 3727 | free_INSN_LIST_list (& ptr->loads); |
3728 | free_INSN_LIST_list (& ptr->stores); | |
8e802be9 | 3729 | |
3730 | free (ptr); | |
3731 | } | |
3732 | ||
3733 | /* Free up all memory associated with the ldst list. */ | |
3734 | ||
3735 | static void | |
bc8197c0 | 3736 | free_ld_motion_mems (void) |
8e802be9 | 3737 | { |
d9dd21a8 | 3738 | if (pre_ldst_table.is_created ()) |
3739 | pre_ldst_table.dispose (); | |
0d707271 | 3740 | |
3cfec666 | 3741 | while (pre_ldst_mems) |
8e802be9 | 3742 | { |
3743 | struct ls_expr * tmp = pre_ldst_mems; | |
3744 | ||
3745 | pre_ldst_mems = pre_ldst_mems->next; | |
3746 | ||
3747 | free_ldst_entry (tmp); | |
3748 | } | |
3749 | ||
3750 | pre_ldst_mems = NULL; | |
3751 | } | |
3752 | ||
3753 | /* Dump debugging info about the ldst list. */ | |
3754 | ||
3755 | static void | |
952f0048 | 3756 | print_ldst_list (FILE * file) |
8e802be9 | 3757 | { |
3758 | struct ls_expr * ptr; | |
3759 | ||
3760 | fprintf (file, "LDST list: \n"); | |
3761 | ||
bc8197c0 | 3762 | for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next) |
8e802be9 | 3763 | { |
3764 | fprintf (file, " Pattern (%3d): ", ptr->index); | |
3765 | ||
3766 | print_rtl (file, ptr->pattern); | |
3767 | ||
3768 | fprintf (file, "\n Loads : "); | |
3769 | ||
3770 | if (ptr->loads) | |
3771 | print_rtl (file, ptr->loads); | |
3772 | else | |
3773 | fprintf (file, "(nil)"); | |
3774 | ||
3775 | fprintf (file, "\n Stores : "); | |
3776 | ||
3777 | if (ptr->stores) | |
3778 | print_rtl (file, ptr->stores); | |
3779 | else | |
3780 | fprintf (file, "(nil)"); | |
3781 | ||
3782 | fprintf (file, "\n\n"); | |
3783 | } | |
3784 | ||
3785 | fprintf (file, "\n"); | |
3786 | } | |
3787 | ||
3788 | /* Returns 1 if X is in the list of ldst only expressions. */ | |
3789 | ||
3790 | static struct ls_expr * | |
952f0048 | 3791 | find_rtx_in_ldst (rtx x) |
8e802be9 | 3792 | { |
0d707271 | 3793 | struct ls_expr e; |
d9dd21a8 | 3794 | ls_expr **slot; |
3795 | if (!pre_ldst_table.is_created ()) | |
00784725 | 3796 | return NULL; |
0d707271 | 3797 | e.pattern = x; |
d9dd21a8 | 3798 | slot = pre_ldst_table.find_slot (&e, NO_INSERT); |
3799 | if (!slot || (*slot)->invalid) | |
0d707271 | 3800 | return NULL; |
d9dd21a8 | 3801 | return *slot; |
8e802be9 | 3802 | } |
8e802be9 | 3803 | \f |
3804 | /* Load Motion for loads which only kill themselves. */ | |
3805 | ||
bc8197c0 | 3806 | /* Return true if x, a MEM, is a simple access with no side effects. |
3807 | These are the types of loads we consider for the ld_motion list, | |
3808 | otherwise we let the usual aliasing take care of it. */ | |
8e802be9 | 3809 | |
3cfec666 | 3810 | static int |
7ecb5bb2 | 3811 | simple_mem (const_rtx x) |
8e802be9 | 3812 | { |
8e802be9 | 3813 | if (MEM_VOLATILE_P (x)) |
3814 | return 0; | |
3cfec666 | 3815 | |
8e802be9 | 3816 | if (GET_MODE (x) == BLKmode) |
3817 | return 0; | |
7a676a9f | 3818 | |
64928ee5 | 3819 | /* If we are handling exceptions, we must be careful with memory references |
cbeb677e | 3820 | that may trap. If we are not, the behavior is undefined, so we may just |
64928ee5 | 3821 | continue. */ |
cbeb677e | 3822 | if (cfun->can_throw_non_call_exceptions && may_trap_p (x)) |
43f5be72 | 3823 | return 0; |
3824 | ||
64928ee5 | 3825 | if (side_effects_p (x)) |
3826 | return 0; | |
3cfec666 | 3827 | |
64928ee5 | 3828 | /* Do not consider function arguments passed on stack. */ |
3829 | if (reg_mentioned_p (stack_pointer_rtx, x)) | |
3830 | return 0; | |
3831 | ||
3832 | if (flag_float_store && FLOAT_MODE_P (GET_MODE (x))) | |
3833 | return 0; | |
3834 | ||
3835 | return 1; | |
8e802be9 | 3836 | } |
3837 | ||
3cfec666 | 3838 | /* Make sure there isn't a buried reference in this pattern anywhere. |
3839 | If there is, invalidate the entry for it since we're not capable | |
3840 | of fixing it up just yet.. We have to be sure we know about ALL | |
8e802be9 | 3841 | loads since the aliasing code will allow all entries in the |
3842 | ld_motion list to not-alias itself. If we miss a load, we will get | |
3cfec666 | 3843 | the wrong value since gcse might common it and we won't know to |
8e802be9 | 3844 | fix it up. */ |
3845 | ||
3846 | static void | |
952f0048 | 3847 | invalidate_any_buried_refs (rtx x) |
8e802be9 | 3848 | { |
3849 | const char * fmt; | |
387732c1 | 3850 | int i, j; |
8e802be9 | 3851 | struct ls_expr * ptr; |
3852 | ||
3853 | /* Invalidate it in the list. */ | |
b9f02dbb | 3854 | if (MEM_P (x) && simple_mem (x)) |
8e802be9 | 3855 | { |
3856 | ptr = ldst_entry (x); | |
3857 | ptr->invalid = 1; | |
3858 | } | |
3859 | ||
3860 | /* Recursively process the insn. */ | |
3861 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
3cfec666 | 3862 | |
8e802be9 | 3863 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
3864 | { | |
3865 | if (fmt[i] == 'e') | |
3866 | invalidate_any_buried_refs (XEXP (x, i)); | |
3867 | else if (fmt[i] == 'E') | |
3868 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3869 | invalidate_any_buried_refs (XVECEXP (x, i, j)); | |
3870 | } | |
3871 | } | |
3872 | ||
c5d8ca43 | 3873 | /* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple |
3874 | being defined as MEM loads and stores to symbols, with no side effects | |
3875 | and no registers in the expression. For a MEM destination, we also | |
3876 | check that the insn is still valid if we replace the destination with a | |
3877 | REG, as is done in update_ld_motion_stores. If there are any uses/defs | |
3878 | which don't match this criteria, they are invalidated and trimmed out | |
3879 | later. */ | |
8e802be9 | 3880 | |
3cfec666 | 3881 | static void |
952f0048 | 3882 | compute_ld_motion_mems (void) |
8e802be9 | 3883 | { |
3884 | struct ls_expr * ptr; | |
4c26117a | 3885 | basic_block bb; |
8e802be9 | 3886 | rtx insn; |
3cfec666 | 3887 | |
8e802be9 | 3888 | pre_ldst_mems = NULL; |
d9dd21a8 | 3889 | pre_ldst_table.create (13); |
8e802be9 | 3890 | |
fc00614f | 3891 | FOR_EACH_BB_FN (bb, cfun) |
8e802be9 | 3892 | { |
defc8016 | 3893 | FOR_BB_INSNS (bb, insn) |
8e802be9 | 3894 | { |
9845d120 | 3895 | if (NONDEBUG_INSN_P (insn)) |
8e802be9 | 3896 | { |
3897 | if (GET_CODE (PATTERN (insn)) == SET) | |
3898 | { | |
3899 | rtx src = SET_SRC (PATTERN (insn)); | |
3900 | rtx dest = SET_DEST (PATTERN (insn)); | |
f473eb72 | 3901 | rtx note = find_reg_equal_equiv_note (insn); |
3902 | rtx src_eq; | |
8e802be9 | 3903 | |
3904 | /* Check for a simple LOAD... */ | |
b9f02dbb | 3905 | if (MEM_P (src) && simple_mem (src)) |
8e802be9 | 3906 | { |
3907 | ptr = ldst_entry (src); | |
b9f02dbb | 3908 | if (REG_P (dest)) |
8e802be9 | 3909 | ptr->loads = alloc_INSN_LIST (insn, ptr->loads); |
3910 | else | |
3911 | ptr->invalid = 1; | |
3912 | } | |
3913 | else | |
3914 | { | |
3915 | /* Make sure there isn't a buried load somewhere. */ | |
3916 | invalidate_any_buried_refs (src); | |
3917 | } | |
3cfec666 | 3918 | |
f473eb72 | 3919 | if (note != 0 && REG_NOTE_KIND (note) == REG_EQUAL) |
3920 | src_eq = XEXP (note, 0); | |
3921 | else | |
3922 | src_eq = NULL_RTX; | |
3923 | ||
3924 | if (src_eq != NULL_RTX | |
3925 | && !(MEM_P (src_eq) && simple_mem (src_eq))) | |
3926 | invalidate_any_buried_refs (src_eq); | |
3927 | ||
8e802be9 | 3928 | /* Check for stores. Don't worry about aliased ones, they |
3929 | will block any movement we might do later. We only care | |
3930 | about this exact pattern since those are the only | |
3931 | circumstance that we will ignore the aliasing info. */ | |
b9f02dbb | 3932 | if (MEM_P (dest) && simple_mem (dest)) |
8e802be9 | 3933 | { |
3934 | ptr = ldst_entry (dest); | |
3cfec666 | 3935 | |
b9f02dbb | 3936 | if (! MEM_P (src) |
c5d8ca43 | 3937 | && GET_CODE (src) != ASM_OPERANDS |
3938 | /* Check for REG manually since want_to_gcse_p | |
3939 | returns 0 for all REGs. */ | |
4b673aa1 | 3940 | && can_assign_to_reg_without_clobbers_p (src)) |
8e802be9 | 3941 | ptr->stores = alloc_INSN_LIST (insn, ptr->stores); |
3942 | else | |
3943 | ptr->invalid = 1; | |
3944 | } | |
3945 | } | |
3946 | else | |
3947 | invalidate_any_buried_refs (PATTERN (insn)); | |
3948 | } | |
3949 | } | |
3950 | } | |
3951 | } | |
3952 | ||
3cfec666 | 3953 | /* Remove any references that have been either invalidated or are not in the |
8e802be9 | 3954 | expression list for pre gcse. */ |
3955 | ||
3956 | static void | |
952f0048 | 3957 | trim_ld_motion_mems (void) |
8e802be9 | 3958 | { |
69333952 | 3959 | struct ls_expr * * last = & pre_ldst_mems; |
3960 | struct ls_expr * ptr = pre_ldst_mems; | |
8e802be9 | 3961 | |
3962 | while (ptr != NULL) | |
3963 | { | |
69333952 | 3964 | struct expr * expr; |
3cfec666 | 3965 | |
8e802be9 | 3966 | /* Delete if entry has been made invalid. */ |
69333952 | 3967 | if (! ptr->invalid) |
8e802be9 | 3968 | { |
8e802be9 | 3969 | /* Delete if we cannot find this mem in the expression list. */ |
69333952 | 3970 | unsigned int hash = ptr->hash_index % expr_hash_table.size; |
3cfec666 | 3971 | |
69333952 | 3972 | for (expr = expr_hash_table.table[hash]; |
3973 | expr != NULL; | |
3974 | expr = expr->next_same_hash) | |
3975 | if (expr_equiv_p (expr->expr, ptr->pattern)) | |
3976 | break; | |
8e802be9 | 3977 | } |
3978 | else | |
69333952 | 3979 | expr = (struct expr *) 0; |
3980 | ||
3981 | if (expr) | |
8e802be9 | 3982 | { |
3983 | /* Set the expression field if we are keeping it. */ | |
8e802be9 | 3984 | ptr->expr = expr; |
69333952 | 3985 | last = & ptr->next; |
8e802be9 | 3986 | ptr = ptr->next; |
3987 | } | |
69333952 | 3988 | else |
3989 | { | |
3990 | *last = ptr->next; | |
d9dd21a8 | 3991 | pre_ldst_table.remove_elt_with_hash (ptr, ptr->hash_index); |
69333952 | 3992 | free_ldst_entry (ptr); |
3993 | ptr = * last; | |
3994 | } | |
8e802be9 | 3995 | } |
3996 | ||
3997 | /* Show the world what we've found. */ | |
3f5be5f4 | 3998 | if (dump_file && pre_ldst_mems != NULL) |
3999 | print_ldst_list (dump_file); | |
8e802be9 | 4000 | } |
4001 | ||
4002 | /* This routine will take an expression which we are replacing with | |
4003 | a reaching register, and update any stores that are needed if | |
4004 | that expression is in the ld_motion list. Stores are updated by | |
91c82c20 | 4005 | copying their SRC to the reaching register, and then storing |
8e802be9 | 4006 | the reaching register into the store location. These keeps the |
4007 | correct value in the reaching register for the loads. */ | |
4008 | ||
4009 | static void | |
952f0048 | 4010 | update_ld_motion_stores (struct expr * expr) |
8e802be9 | 4011 | { |
4012 | struct ls_expr * mem_ptr; | |
4013 | ||
4014 | if ((mem_ptr = find_rtx_in_ldst (expr->expr))) | |
4015 | { | |
3cfec666 | 4016 | /* We can try to find just the REACHED stores, but is shouldn't |
4017 | matter to set the reaching reg everywhere... some might be | |
8e802be9 | 4018 | dead and should be eliminated later. */ |
4019 | ||
c5d8ca43 | 4020 | /* We replace (set mem expr) with (set reg expr) (set mem reg) |
4021 | where reg is the reaching reg used in the load. We checked in | |
4022 | compute_ld_motion_mems that we can replace (set mem expr) with | |
4023 | (set reg expr) in that insn. */ | |
8e802be9 | 4024 | rtx list = mem_ptr->stores; |
3cfec666 | 4025 | |
8e802be9 | 4026 | for ( ; list != NULL_RTX; list = XEXP (list, 1)) |
4027 | { | |
4028 | rtx insn = XEXP (list, 0); | |
4029 | rtx pat = PATTERN (insn); | |
4030 | rtx src = SET_SRC (pat); | |
4031 | rtx reg = expr->reaching_reg; | |
d52d7a3a | 4032 | rtx copy; |
8e802be9 | 4033 | |
4034 | /* If we've already copied it, continue. */ | |
4035 | if (expr->reaching_reg == src) | |
4036 | continue; | |
3cfec666 | 4037 | |
3f5be5f4 | 4038 | if (dump_file) |
8e802be9 | 4039 | { |
3f5be5f4 | 4040 | fprintf (dump_file, "PRE: store updated with reaching reg "); |
bc8197c0 | 4041 | print_rtl (dump_file, reg); |
3f5be5f4 | 4042 | fprintf (dump_file, ":\n "); |
4043 | print_inline_rtx (dump_file, insn, 8); | |
4044 | fprintf (dump_file, "\n"); | |
8e802be9 | 4045 | } |
3cfec666 | 4046 | |
2e81afe5 | 4047 | copy = gen_move_insn (reg, copy_rtx (SET_SRC (pat))); |
d52d7a3a | 4048 | emit_insn_before (copy, insn); |
8e802be9 | 4049 | SET_SRC (pat) = reg; |
3072d30e | 4050 | df_insn_rescan (insn); |
8e802be9 | 4051 | |
4052 | /* un-recognize this pattern since it's probably different now. */ | |
4053 | INSN_CODE (insn) = -1; | |
4054 | gcse_create_count++; | |
4055 | } | |
4056 | } | |
4057 | } | |
4058 | \f | |
4b673aa1 | 4059 | /* Return true if the graph is too expensive to optimize. PASS is the |
4060 | optimization about to be performed. */ | |
64928ee5 | 4061 | |
4b673aa1 | 4062 | static bool |
4063 | is_too_expensive (const char *pass) | |
4064 | { | |
4065 | /* Trying to perform global optimizations on flow graphs which have | |
4066 | a high connectivity will take a long time and is unlikely to be | |
4067 | particularly useful. | |
7a676a9f | 4068 | |
4b673aa1 | 4069 | In normal circumstances a cfg should have about twice as many |
4070 | edges as blocks. But we do not want to punish small functions | |
4071 | which have a couple switch statements. Rather than simply | |
4072 | threshold the number of blocks, uses something with a more | |
4073 | graceful degradation. */ | |
f1955b22 | 4074 | if (n_edges_for_fn (cfun) > 20000 + n_basic_blocks_for_fn (cfun) * 4) |
4b673aa1 | 4075 | { |
4076 | warning (OPT_Wdisabled_optimization, | |
4077 | "%s: %d basic blocks and %d edges/basic block", | |
a28770e1 | 4078 | pass, n_basic_blocks_for_fn (cfun), |
f1955b22 | 4079 | n_edges_for_fn (cfun) / n_basic_blocks_for_fn (cfun)); |
8e802be9 | 4080 | |
4b673aa1 | 4081 | return true; |
4082 | } | |
8e802be9 | 4083 | |
07abdb66 | 4084 | /* If allocating memory for the dataflow bitmaps would take up too much |
4b673aa1 | 4085 | storage it's better just to disable the optimization. */ |
a28770e1 | 4086 | if ((n_basic_blocks_for_fn (cfun) |
4b673aa1 | 4087 | * SBITMAP_SET_SIZE (max_reg_num ()) |
4088 | * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY) | |
4089 | { | |
4090 | warning (OPT_Wdisabled_optimization, | |
4091 | "%s: %d basic blocks and %d registers", | |
a28770e1 | 4092 | pass, n_basic_blocks_for_fn (cfun), max_reg_num ()); |
8e802be9 | 4093 | |
4b673aa1 | 4094 | return true; |
4095 | } | |
42334a67 | 4096 | |
4b673aa1 | 4097 | return false; |
9e4a9ceb | 4098 | } |
4b673aa1 | 4099 | \f |
4100 | /* All the passes implemented in this file. Each pass has its | |
4101 | own gate and execute function, and at the end of the file a | |
4102 | pass definition for passes.c. | |
64928ee5 | 4103 | |
4b673aa1 | 4104 | We do not construct an accurate cfg in functions which call |
4105 | setjmp, so none of these passes runs if the function calls | |
4106 | setjmp. | |
4107 | FIXME: Should just handle setjmp via REG_SETJMP notes. */ | |
8e802be9 | 4108 | |
4b673aa1 | 4109 | static bool |
4110 | gate_rtl_pre (void) | |
4111 | { | |
4112 | return optimize > 0 && flag_gcse | |
de2ca00d | 4113 | && !cfun->calls_setjmp |
4114 | && optimize_function_for_speed_p (cfun) | |
4115 | && dbg_cnt (pre); | |
4b673aa1 | 4116 | } |
3cfec666 | 4117 | |
4b673aa1 | 4118 | static unsigned int |
4119 | execute_rtl_pre (void) | |
4120 | { | |
805e3e15 | 4121 | int changed; |
4b673aa1 | 4122 | delete_unreachable_blocks (); |
4b673aa1 | 4123 | df_analyze (); |
805e3e15 | 4124 | changed = one_pre_gcse_pass (); |
4125 | flag_rerun_cse_after_global_opts |= changed; | |
4126 | if (changed) | |
4127 | cleanup_cfg (0); | |
4b673aa1 | 4128 | return 0; |
4129 | } | |
7a676a9f | 4130 | |
4b673aa1 | 4131 | static bool |
4132 | gate_rtl_hoist (void) | |
4133 | { | |
4134 | return optimize > 0 && flag_gcse | |
de2ca00d | 4135 | && !cfun->calls_setjmp |
4136 | /* It does not make sense to run code hoisting unless we are optimizing | |
4137 | for code size -- it rarely makes programs faster, and can make then | |
4138 | bigger if we did PRE (when optimizing for space, we don't run PRE). */ | |
4139 | && optimize_function_for_size_p (cfun) | |
4140 | && dbg_cnt (hoist); | |
4b673aa1 | 4141 | } |
7a676a9f | 4142 | |
4b673aa1 | 4143 | static unsigned int |
4144 | execute_rtl_hoist (void) | |
4145 | { | |
805e3e15 | 4146 | int changed; |
4b673aa1 | 4147 | delete_unreachable_blocks (); |
4b673aa1 | 4148 | df_analyze (); |
805e3e15 | 4149 | changed = one_code_hoisting_pass (); |
4150 | flag_rerun_cse_after_global_opts |= changed; | |
4151 | if (changed) | |
4152 | cleanup_cfg (0); | |
4b673aa1 | 4153 | return 0; |
4154 | } | |
77fce4cd | 4155 | |
cbe8bda8 | 4156 | namespace { |
4157 | ||
4158 | const pass_data pass_data_rtl_pre = | |
77fce4cd | 4159 | { |
cbe8bda8 | 4160 | RTL_PASS, /* type */ |
4161 | "rtl pre", /* name */ | |
4162 | OPTGROUP_NONE, /* optinfo_flags */ | |
4163 | true, /* has_gate */ | |
4164 | true, /* has_execute */ | |
4165 | TV_PRE, /* tv_id */ | |
4166 | PROP_cfglayout, /* properties_required */ | |
4167 | 0, /* properties_provided */ | |
4168 | 0, /* properties_destroyed */ | |
4169 | 0, /* todo_flags_start */ | |
4170 | ( TODO_df_finish | TODO_verify_rtl_sharing | |
4171 | | TODO_verify_flow ), /* todo_flags_finish */ | |
d743aba2 | 4172 | }; |
77fce4cd | 4173 | |
cbe8bda8 | 4174 | class pass_rtl_pre : public rtl_opt_pass |
4175 | { | |
4176 | public: | |
9af5ce0c | 4177 | pass_rtl_pre (gcc::context *ctxt) |
4178 | : rtl_opt_pass (pass_data_rtl_pre, ctxt) | |
cbe8bda8 | 4179 | {} |
4180 | ||
4181 | /* opt_pass methods: */ | |
4182 | bool gate () { return gate_rtl_pre (); } | |
4183 | unsigned int execute () { return execute_rtl_pre (); } | |
4184 | ||
4185 | }; // class pass_rtl_pre | |
4186 | ||
4187 | } // anon namespace | |
4188 | ||
4189 | rtl_opt_pass * | |
4190 | make_pass_rtl_pre (gcc::context *ctxt) | |
4191 | { | |
4192 | return new pass_rtl_pre (ctxt); | |
4193 | } | |
4194 | ||
4195 | namespace { | |
4196 | ||
4197 | const pass_data pass_data_rtl_hoist = | |
77fce4cd | 4198 | { |
cbe8bda8 | 4199 | RTL_PASS, /* type */ |
4200 | "hoist", /* name */ | |
4201 | OPTGROUP_NONE, /* optinfo_flags */ | |
4202 | true, /* has_gate */ | |
4203 | true, /* has_execute */ | |
4204 | TV_HOIST, /* tv_id */ | |
4205 | PROP_cfglayout, /* properties_required */ | |
4206 | 0, /* properties_provided */ | |
4207 | 0, /* properties_destroyed */ | |
4208 | 0, /* todo_flags_start */ | |
4209 | ( TODO_df_finish | TODO_verify_rtl_sharing | |
4210 | | TODO_verify_flow ), /* todo_flags_finish */ | |
77fce4cd | 4211 | }; |
4212 | ||
cbe8bda8 | 4213 | class pass_rtl_hoist : public rtl_opt_pass |
4214 | { | |
4215 | public: | |
9af5ce0c | 4216 | pass_rtl_hoist (gcc::context *ctxt) |
4217 | : rtl_opt_pass (pass_data_rtl_hoist, ctxt) | |
cbe8bda8 | 4218 | {} |
4219 | ||
4220 | /* opt_pass methods: */ | |
4221 | bool gate () { return gate_rtl_hoist (); } | |
4222 | unsigned int execute () { return execute_rtl_hoist (); } | |
4223 | ||
4224 | }; // class pass_rtl_hoist | |
4225 | ||
4226 | } // anon namespace | |
4227 | ||
4228 | rtl_opt_pass * | |
4229 | make_pass_rtl_hoist (gcc::context *ctxt) | |
4230 | { | |
4231 | return new pass_rtl_hoist (ctxt); | |
4232 | } | |
4233 | ||
1f3233d1 | 4234 | #include "gt-gcse.h" |