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ffbd18cc 1/* Allocate registers for pseudo-registers that span basic blocks.
2f791da8 2 Copyright (C) 1987, 1988, 1991, 1994, 1996, 1997, 1998,
dfe09cce 3 1999, 2000, 2002 Free Software Foundation, Inc.
ffbd18cc 4
f12b58b3 5This file is part of GCC.
ffbd18cc 6
f12b58b3 7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
ffbd18cc 11
f12b58b3 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
ffbd18cc 16
17You should have received a copy of the GNU General Public License
f12b58b3 18along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
ffbd18cc 21
22
ffbd18cc 23#include "config.h"
405711de 24#include "system.h"
3ef9782d 25
f41a3237 26#include "machmode.h"
27#include "hard-reg-set.h"
ffbd18cc 28#include "rtl.h"
7953c610 29#include "tm_p.h"
ffbd18cc 30#include "flags.h"
31#include "basic-block.h"
ffbd18cc 32#include "regs.h"
0a893c29 33#include "function.h"
ffbd18cc 34#include "insn-config.h"
e94a59c6 35#include "reload.h"
ffbd18cc 36#include "output.h"
ce1fd7fc 37#include "toplev.h"
ffbd18cc 38
39/* This pass of the compiler performs global register allocation.
40 It assigns hard register numbers to all the pseudo registers
41 that were not handled in local_alloc. Assignments are recorded
42 in the vector reg_renumber, not by changing the rtl code.
43 (Such changes are made by final). The entry point is
44 the function global_alloc.
45
46 After allocation is complete, the reload pass is run as a subroutine
47 of this pass, so that when a pseudo reg loses its hard reg due to
48 spilling it is possible to make a second attempt to find a hard
49 reg for it. The reload pass is independent in other respects
50 and it is run even when stupid register allocation is in use.
51
0b6b86e7 52 1. Assign allocation-numbers (allocnos) to the pseudo-registers
53 still needing allocations and to the pseudo-registers currently
54 allocated by local-alloc which may be spilled by reload.
3cfec666 55 Set up tables reg_allocno and allocno_reg to map
ffbd18cc 56 reg numbers to allocnos and vice versa.
57 max_allocno gets the number of allocnos in use.
58
59 2. Allocate a max_allocno by max_allocno conflict bit matrix and clear it.
60 Allocate a max_allocno by FIRST_PSEUDO_REGISTER conflict matrix
61 for conflicts between allocnos and explicit hard register use
62 (which includes use of pseudo-registers allocated by local_alloc).
63
0b6b86e7 64 3. For each basic block
ffbd18cc 65 walk forward through the block, recording which
0b6b86e7 66 pseudo-registers and which hardware registers are live.
67 Build the conflict matrix between the pseudo-registers
68 and another of pseudo-registers versus hardware registers.
ffbd18cc 69 Also record the preferred hardware registers
0b6b86e7 70 for each pseudo-register.
ffbd18cc 71
72 4. Sort a table of the allocnos into order of
73 desirability of the variables.
74
75 5. Allocate the variables in that order; each if possible into
76 a preferred register, else into another register. */
77\f
aa40f561 78/* Number of pseudo-registers which are candidates for allocation. */
ffbd18cc 79
80static int max_allocno;
81
82/* Indexed by (pseudo) reg number, gives the allocno, or -1
0b6b86e7 83 for pseudo registers which are not to be allocated. */
ffbd18cc 84
64ab4a7b 85static int *reg_allocno;
ffbd18cc 86
71b77236 87struct allocno
88{
89 int reg;
90 /* Gives the number of consecutive hard registers needed by that
91 pseudo reg. */
92 int size;
93
94 /* Number of calls crossed by each allocno. */
95 int calls_crossed;
96
63f23608 97 /* Number of refs to each allocno. */
71b77236 98 int n_refs;
99
63f23608 100 /* Frequency of uses of each allocno. */
101 int freq;
102
71b77236 103 /* Guess at live length of each allocno.
104 This is actually the max of the live lengths of the regs. */
105 int live_length;
106
107 /* Set of hard regs conflicting with allocno N. */
108
109 HARD_REG_SET hard_reg_conflicts;
110
111 /* Set of hard regs preferred by allocno N.
112 This is used to make allocnos go into regs that are copied to or from them,
113 when possible, to reduce register shuffling. */
114
115 HARD_REG_SET hard_reg_preferences;
116
117 /* Similar, but just counts register preferences made in simple copy
118 operations, rather than arithmetic. These are given priority because
119 we can always eliminate an insn by using these, but using a register
120 in the above list won't always eliminate an insn. */
ffbd18cc 121
71b77236 122 HARD_REG_SET hard_reg_copy_preferences;
123
124 /* Similar to hard_reg_preferences, but includes bits for subsequent
125 registers when an allocno is multi-word. The above variable is used for
126 allocation while this is used to build reg_someone_prefers, below. */
127
128 HARD_REG_SET hard_reg_full_preferences;
129
130 /* Set of hard registers that some later allocno has a preference for. */
131
132 HARD_REG_SET regs_someone_prefers;
133};
134
135static struct allocno *allocno;
ffbd18cc 136
137/* A vector of the integers from 0 to max_allocno-1,
138 sorted in the order of first-to-be-allocated first. */
139
140static int *allocno_order;
141
ffbd18cc 142/* Indexed by (pseudo) reg number, gives the number of another
4bbea254 143 lower-numbered pseudo reg which can share a hard reg with this pseudo
ffbd18cc 144 *even if the two pseudos would otherwise appear to conflict*. */
145
146static int *reg_may_share;
147
50b0c9ee 148/* Define the number of bits in each element of `conflicts' and what
149 type that element has. We use the largest integer format on the
150 host machine. */
151
152#define INT_BITS HOST_BITS_PER_WIDE_INT
153#define INT_TYPE HOST_WIDE_INT
154
ffbd18cc 155/* max_allocno by max_allocno array of bits,
156 recording whether two allocno's conflict (can't go in the same
157 hardware register).
158
51bc0ccc 159 `conflicts' is symmetric after the call to mirror_conflicts. */
ffbd18cc 160
50b0c9ee 161static INT_TYPE *conflicts;
ffbd18cc 162
163/* Number of ints require to hold max_allocno bits.
164 This is the length of a row in `conflicts'. */
165
166static int allocno_row_words;
167
168/* Two macros to test or store 1 in an element of `conflicts'. */
169
170#define CONFLICTP(I, J) \
dfe09cce 171 (conflicts[(I) * allocno_row_words + (unsigned) (J) / INT_BITS] \
172 & ((INT_TYPE) 1 << ((unsigned) (J) % INT_BITS)))
ffbd18cc 173
174#define SET_CONFLICT(I, J) \
dfe09cce 175 (conflicts[(I) * allocno_row_words + (unsigned) (J) / INT_BITS] \
176 |= ((INT_TYPE) 1 << ((unsigned) (J) % INT_BITS)))
51bc0ccc 177
1f45e4d5 178/* For any allocno set in ALLOCNO_SET, set ALLOCNO to that allocno,
179 and execute CODE. */
180#define EXECUTE_IF_SET_IN_ALLOCNO_SET(ALLOCNO_SET, ALLOCNO, CODE) \
181do { \
182 int i_; \
183 int allocno_; \
71b77236 184 INT_TYPE *p_ = (ALLOCNO_SET); \
1f45e4d5 185 \
186 for (i_ = allocno_row_words - 1, allocno_ = 0; i_ >= 0; \
187 i_--, allocno_ += INT_BITS) \
188 { \
189 unsigned INT_TYPE word_ = (unsigned INT_TYPE) *p_++; \
190 \
191 for ((ALLOCNO) = allocno_; word_; word_ >>= 1, (ALLOCNO)++) \
192 { \
193 if (word_ & 1) \
c74159a4 194 {CODE;} \
1f45e4d5 195 } \
196 } \
197} while (0)
198
8c278a57 199/* This doesn't work for non-GNU C due to the way CODE is macro expanded. */
200#if 0
1f45e4d5 201/* For any allocno that conflicts with IN_ALLOCNO, set OUT_ALLOCNO to
202 the conflicting allocno, and execute CODE. This macro assumes that
203 mirror_conflicts has been run. */
204#define EXECUTE_IF_CONFLICT(IN_ALLOCNO, OUT_ALLOCNO, CODE)\
205 EXECUTE_IF_SET_IN_ALLOCNO_SET (conflicts + (IN_ALLOCNO) * allocno_row_words,\
c74159a4 206 OUT_ALLOCNO, (CODE))
8c278a57 207#endif
1f45e4d5 208
ffbd18cc 209/* Set of hard regs currently live (during scan of all insns). */
210
211static HARD_REG_SET hard_regs_live;
212
ffbd18cc 213/* Set of registers that global-alloc isn't supposed to use. */
214
215static HARD_REG_SET no_global_alloc_regs;
216
217/* Set of registers used so far. */
218
219static HARD_REG_SET regs_used_so_far;
220
63f23608 221/* Number of refs to each hard reg, as used by local alloc.
05f2333b 222 It is zero for a reg that contains global pseudos or is explicitly used. */
223
224static int local_reg_n_refs[FIRST_PSEUDO_REGISTER];
225
63f23608 226/* Frequency of uses of given hard reg. */
227static int local_reg_freq[FIRST_PSEUDO_REGISTER];
228
05f2333b 229/* Guess at live length of each hard reg, as used by local alloc.
230 This is actually the sum of the live lengths of the specific regs. */
231
232static int local_reg_live_length[FIRST_PSEUDO_REGISTER];
233
ffbd18cc 234/* Test a bit in TABLE, a vector of HARD_REG_SETs,
235 for vector element I, and hard register number J. */
236
71b77236 237#define REGBITP(TABLE, I, J) TEST_HARD_REG_BIT (allocno[I].TABLE, J)
ffbd18cc 238
239/* Set to 1 a bit in a vector of HARD_REG_SETs. Works like REGBITP. */
240
71b77236 241#define SET_REGBIT(TABLE, I, J) SET_HARD_REG_BIT (allocno[I].TABLE, J)
ffbd18cc 242
243/* Bit mask for allocnos live at current point in the scan. */
244
50b0c9ee 245static INT_TYPE *allocnos_live;
ffbd18cc 246
247/* Test, set or clear bit number I in allocnos_live,
248 a bit vector indexed by allocno. */
249
1f45e4d5 250#define ALLOCNO_LIVE_P(I) \
dfe09cce 251 (allocnos_live[(unsigned) (I) / INT_BITS] \
252 & ((INT_TYPE) 1 << ((unsigned) (I) % INT_BITS)))
ffbd18cc 253
1f45e4d5 254#define SET_ALLOCNO_LIVE(I) \
dfe09cce 255 (allocnos_live[(unsigned) (I) / INT_BITS] \
256 |= ((INT_TYPE) 1 << ((unsigned) (I) % INT_BITS)))
ffbd18cc 257
1f45e4d5 258#define CLEAR_ALLOCNO_LIVE(I) \
dfe09cce 259 (allocnos_live[(unsigned) (I) / INT_BITS] \
260 &= ~((INT_TYPE) 1 << ((unsigned) (I) % INT_BITS)))
ffbd18cc 261
262/* This is turned off because it doesn't work right for DImode.
263 (And it is only used for DImode, so the other cases are worthless.)
264 The problem is that it isn't true that there is NO possibility of conflict;
265 only that there is no conflict if the two pseudos get the exact same regs.
266 If they were allocated with a partial overlap, there would be a conflict.
267 We can't safely turn off the conflict unless we have another way to
268 prevent the partial overlap.
269
270 Idea: change hard_reg_conflicts so that instead of recording which
271 hard regs the allocno may not overlap, it records where the allocno
272 may not start. Change both where it is used and where it is updated.
273 Then there is a way to record that (reg:DI 108) may start at 10
274 but not at 9 or 11. There is still the question of how to record
275 this semi-conflict between two pseudos. */
276#if 0
277/* Reg pairs for which conflict after the current insn
278 is inhibited by a REG_NO_CONFLICT note.
279 If the table gets full, we ignore any other notes--that is conservative. */
280#define NUM_NO_CONFLICT_PAIRS 4
281/* Number of pairs in use in this insn. */
282int n_no_conflict_pairs;
283static struct { int allocno1, allocno2;}
284 no_conflict_pairs[NUM_NO_CONFLICT_PAIRS];
285#endif /* 0 */
286
287/* Record all regs that are set in any one insn.
288 Communication from mark_reg_{store,clobber} and global_conflicts. */
289
290static rtx *regs_set;
291static int n_regs_set;
292
d55c71c6 293/* All registers that can be eliminated. */
ffbd18cc 294
295static HARD_REG_SET eliminable_regset;
296
38b9004f 297static int allocno_compare PARAMS ((const PTR, const PTR));
298static void global_conflicts PARAMS ((void));
299static void mirror_conflicts PARAMS ((void));
300static void expand_preferences PARAMS ((void));
301static void prune_preferences PARAMS ((void));
302static void find_reg PARAMS ((int, HARD_REG_SET, int, int, int));
303static void record_one_conflict PARAMS ((int));
304static void record_conflicts PARAMS ((int *, int));
305static void mark_reg_store PARAMS ((rtx, rtx, void *));
306static void mark_reg_clobber PARAMS ((rtx, rtx, void *));
307static void mark_reg_conflicts PARAMS ((rtx));
308static void mark_reg_death PARAMS ((rtx));
309static void mark_reg_live_nc PARAMS ((int, enum machine_mode));
310static void set_preference PARAMS ((rtx, rtx));
311static void dump_conflicts PARAMS ((FILE *));
312static void reg_becomes_live PARAMS ((rtx, rtx, void *));
313static void reg_dies PARAMS ((int, enum machine_mode,
a570a59f 314 struct insn_chain *));
ffbd18cc 315\f
316/* Perform allocation of pseudo-registers not allocated by local_alloc.
317 FILE is a file to output debugging information on,
5aaac310 318 or zero if such output is not desired.
ffbd18cc 319
5aaac310 320 Return value is nonzero if reload failed
321 and we must not do any more for this function. */
322
323int
ffbd18cc 324global_alloc (file)
325 FILE *file;
326{
d561366f 327 int retval;
ffbd18cc 328#ifdef ELIMINABLE_REGS
e99c3a1d 329 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
ffbd18cc 330#endif
d55c71c6 331 int need_fp
332 = (! flag_omit_frame_pointer
333#ifdef EXIT_IGNORE_STACK
334 || (current_function_calls_alloca && EXIT_IGNORE_STACK)
335#endif
336 || FRAME_POINTER_REQUIRED);
337
19cb6b50 338 size_t i;
ffbd18cc 339 rtx x;
340
341 max_allocno = 0;
342
343 /* A machine may have certain hard registers that
344 are safe to use only within a basic block. */
345
346 CLEAR_HARD_REG_SET (no_global_alloc_regs);
ffbd18cc 347
348 /* Build the regset of all eliminable registers and show we can't use those
349 that we already know won't be eliminated. */
350#ifdef ELIMINABLE_REGS
3098b2d3 351 for (i = 0; i < ARRAY_SIZE (eliminables); i++)
ffbd18cc 352 {
353 SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from);
354
355 if (! CAN_ELIMINATE (eliminables[i].from, eliminables[i].to)
d55c71c6 356 || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp))
ffbd18cc 357 SET_HARD_REG_BIT (no_global_alloc_regs, eliminables[i].from);
358 }
60718504 359#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
d55c71c6 360 SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM);
361 if (need_fp)
60718504 362 SET_HARD_REG_BIT (no_global_alloc_regs, HARD_FRAME_POINTER_REGNUM);
363#endif
d55c71c6 364
ffbd18cc 365#else
366 SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM);
d55c71c6 367 if (need_fp)
ffbd18cc 368 SET_HARD_REG_BIT (no_global_alloc_regs, FRAME_POINTER_REGNUM);
369#endif
370
371 /* Track which registers have already been used. Start with registers
372 explicitly in the rtl, then registers allocated by local register
9ebcdd59 373 allocation. */
ffbd18cc 374
375 CLEAR_HARD_REG_SET (regs_used_so_far);
9ebcdd59 376#ifdef LEAF_REGISTERS
377 /* If we are doing the leaf function optimization, and this is a leaf
378 function, it means that the registers that take work to save are those
379 that need a register window. So prefer the ones that can be used in
380 a leaf function. */
381 {
382 char *cheap_regs;
7a8d641b 383 char *leaf_regs = LEAF_REGISTERS;
9ebcdd59 384
385 if (only_leaf_regs_used () && leaf_function_p ())
386 cheap_regs = leaf_regs;
387 else
388 cheap_regs = call_used_regs;
389 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
390 if (regs_ever_live[i] || cheap_regs[i])
391 SET_HARD_REG_BIT (regs_used_so_far, i);
392 }
393#else
394 /* We consider registers that do not have to be saved over calls as if
395 they were already used since there is no cost in using them. */
ffbd18cc 396 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
397 if (regs_ever_live[i] || call_used_regs[i])
398 SET_HARD_REG_BIT (regs_used_so_far, i);
9ebcdd59 399#endif
ffbd18cc 400
274c11d8 401 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
ffbd18cc 402 if (reg_renumber[i] >= 0)
403 SET_HARD_REG_BIT (regs_used_so_far, reg_renumber[i]);
404
405 /* Establish mappings from register number to allocation number
406 and vice versa. In the process, count the allocnos. */
407
8b861be4 408 reg_allocno = (int *) xmalloc (max_regno * sizeof (int));
ffbd18cc 409
410 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
411 reg_allocno[i] = -1;
412
413 /* Initialize the shared-hard-reg mapping
414 from the list of pairs that may share. */
8b861be4 415 reg_may_share = (int *) xcalloc (max_regno, sizeof (int));
ffbd18cc 416 for (x = regs_may_share; x; x = XEXP (XEXP (x, 1), 1))
417 {
418 int r1 = REGNO (XEXP (x, 0));
419 int r2 = REGNO (XEXP (XEXP (x, 1), 0));
420 if (r1 > r2)
421 reg_may_share[r1] = r2;
422 else
423 reg_may_share[r2] = r1;
424 }
425
274c11d8 426 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
ffbd18cc 427 /* Note that reg_live_length[i] < 0 indicates a "constant" reg
428 that we are supposed to refrain from putting in a hard reg.
429 -2 means do make an allocno but don't allocate it. */
0b6b86e7 430 if (REG_N_REFS (i) != 0 && REG_LIVE_LENGTH (i) != -1
ffbd18cc 431 /* Don't allocate pseudos that cross calls,
432 if this function receives a nonlocal goto. */
433 && (! current_function_has_nonlocal_label
394685a4 434 || REG_N_CALLS_CROSSED (i) == 0))
ffbd18cc 435 {
0b6b86e7 436 if (reg_renumber[i] < 0 && reg_may_share[i] && reg_allocno[reg_may_share[i]] >= 0)
ffbd18cc 437 reg_allocno[i] = reg_allocno[reg_may_share[i]];
438 else
439 reg_allocno[i] = max_allocno++;
394685a4 440 if (REG_LIVE_LENGTH (i) == 0)
ffbd18cc 441 abort ();
442 }
443 else
444 reg_allocno[i] = -1;
445
71b77236 446 allocno = (struct allocno *) xcalloc (max_allocno, sizeof (struct allocno));
ffbd18cc 447
274c11d8 448 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
ffbd18cc 449 if (reg_allocno[i] >= 0)
450 {
71b77236 451 int num = reg_allocno[i];
452 allocno[num].reg = i;
453 allocno[num].size = PSEUDO_REGNO_SIZE (i);
454 allocno[num].calls_crossed += REG_N_CALLS_CROSSED (i);
455 allocno[num].n_refs += REG_N_REFS (i);
63f23608 456 allocno[num].freq += REG_FREQ (i);
71b77236 457 if (allocno[num].live_length < REG_LIVE_LENGTH (i))
458 allocno[num].live_length = REG_LIVE_LENGTH (i);
ffbd18cc 459 }
460
05f2333b 461 /* Calculate amount of usage of each hard reg by pseudos
462 allocated by local-alloc. This is to see if we want to
463 override it. */
93d3b7de 464 memset ((char *) local_reg_live_length, 0, sizeof local_reg_live_length);
465 memset ((char *) local_reg_n_refs, 0, sizeof local_reg_n_refs);
63f23608 466 memset ((char *) local_reg_freq, 0, sizeof local_reg_freq);
274c11d8 467 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
0b6b86e7 468 if (reg_renumber[i] >= 0)
05f2333b 469 {
3b1a9578 470 int regno = reg_renumber[i];
471 int endregno = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
472 int j;
473
474 for (j = regno; j < endregno; j++)
475 {
394685a4 476 local_reg_n_refs[j] += REG_N_REFS (i);
63f23608 477 local_reg_freq[j] += REG_FREQ (i);
394685a4 478 local_reg_live_length[j] += REG_LIVE_LENGTH (i);
3b1a9578 479 }
05f2333b 480 }
3b1a9578 481
05f2333b 482 /* We can't override local-alloc for a reg used not just by local-alloc. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 if (regs_ever_live[i])
63f23608 485 local_reg_n_refs[i] = 0, local_reg_freq[i] = 0;
3cfec666 486
ffbd18cc 487 allocno_row_words = (max_allocno + INT_BITS - 1) / INT_BITS;
488
46142c2d 489 /* We used to use alloca here, but the size of what it would try to
490 allocate would occasionally cause it to exceed the stack limit and
491 cause unpredictable core dumps. Some examples were > 2Mb in size. */
a559f7c8 492 conflicts = (INT_TYPE *) xcalloc (max_allocno * allocno_row_words,
493 sizeof (INT_TYPE));
ffbd18cc 494
8b861be4 495 allocnos_live = (INT_TYPE *) xmalloc (allocno_row_words * sizeof (INT_TYPE));
ffbd18cc 496
497 /* If there is work to be done (at least one reg to allocate),
498 perform global conflict analysis and allocate the regs. */
499
500 if (max_allocno > 0)
501 {
502 /* Scan all the insns and compute the conflicts among allocnos
503 and between allocnos and hard regs. */
504
505 global_conflicts ();
506
51bc0ccc 507 mirror_conflicts ();
508
ffbd18cc 509 /* Eliminate conflicts between pseudos and eliminable registers. If
510 the register is not eliminated, the pseudo won't really be able to
511 live in the eliminable register, so the conflict doesn't matter.
512 If we do eliminate the register, the conflict will no longer exist.
05f2333b 513 So in either case, we can ignore the conflict. Likewise for
514 preferences. */
ffbd18cc 515
274c11d8 516 for (i = 0; i < (size_t) max_allocno; i++)
05f2333b 517 {
71b77236 518 AND_COMPL_HARD_REG_SET (allocno[i].hard_reg_conflicts,
519 eliminable_regset);
520 AND_COMPL_HARD_REG_SET (allocno[i].hard_reg_copy_preferences,
521 eliminable_regset);
522 AND_COMPL_HARD_REG_SET (allocno[i].hard_reg_preferences,
05f2333b 523 eliminable_regset);
05f2333b 524 }
ffbd18cc 525
526 /* Try to expand the preferences by merging them between allocnos. */
527
528 expand_preferences ();
529
530 /* Determine the order to allocate the remaining pseudo registers. */
531
8b861be4 532 allocno_order = (int *) xmalloc (max_allocno * sizeof (int));
274c11d8 533 for (i = 0; i < (size_t) max_allocno; i++)
ffbd18cc 534 allocno_order[i] = i;
535
536 /* Default the size to 1, since allocno_compare uses it to divide by.
537 Also convert allocno_live_length of zero to -1. A length of zero
538 can occur when all the registers for that allocno have reg_live_length
539 equal to -2. In this case, we want to make an allocno, but not
540 allocate it. So avoid the divide-by-zero and set it to a low
541 priority. */
542
274c11d8 543 for (i = 0; i < (size_t) max_allocno; i++)
ffbd18cc 544 {
71b77236 545 if (allocno[i].size == 0)
546 allocno[i].size = 1;
547 if (allocno[i].live_length == 0)
548 allocno[i].live_length = -1;
ffbd18cc 549 }
550
551 qsort (allocno_order, max_allocno, sizeof (int), allocno_compare);
3cfec666 552
ffbd18cc 553 prune_preferences ();
554
555 if (file)
556 dump_conflicts (file);
557
558 /* Try allocating them, one by one, in that order,
559 except for parameters marked with reg_live_length[regno] == -2. */
560
274c11d8 561 for (i = 0; i < (size_t) max_allocno; i++)
71b77236 562 if (reg_renumber[allocno[allocno_order[i]].reg] < 0
563 && REG_LIVE_LENGTH (allocno[allocno_order[i]].reg) >= 0)
ffbd18cc 564 {
565 /* If we have more than one register class,
566 first try allocating in the class that is cheapest
567 for this pseudo-reg. If that fails, try any reg. */
568 if (N_REG_CLASSES > 1)
569 {
bd09ab5d 570 find_reg (allocno_order[i], 0, 0, 0, 0);
71b77236 571 if (reg_renumber[allocno[allocno_order[i]].reg] >= 0)
ffbd18cc 572 continue;
573 }
71b77236 574 if (reg_alternate_class (allocno[allocno_order[i]].reg) != NO_REGS)
bd09ab5d 575 find_reg (allocno_order[i], 0, 1, 0, 0);
ffbd18cc 576 }
8b861be4 577
578 free (allocno_order);
ffbd18cc 579 }
580
581 /* Do the reloads now while the allocno data still exist, so that we can
582 try to assign new hard regs to any pseudo regs that are spilled. */
583
a6ce2572 584#if 0 /* We need to eliminate regs even if there is no rtl code,
585 for the sake of debugging information. */
b3d6de89 586 if (n_basic_blocks > 0)
a6ce2572 587#endif
e94a59c6 588 {
6f5c3acb 589 build_insn_chain (get_insns ());
bfd0ee98 590 retval = reload (get_insns (), 1);
e94a59c6 591 }
d561366f 592
8b861be4 593 /* Clean up. */
594 free (reg_allocno);
595 free (reg_may_share);
71b77236 596 free (allocno);
d561366f 597 free (conflicts);
8b861be4 598 free (allocnos_live);
599
d561366f 600 return retval;
ffbd18cc 601}
602
603/* Sort predicate for ordering the allocnos.
604 Returns -1 (1) if *v1 should be allocated before (after) *v2. */
605
606static int
de27a084 607allocno_compare (v1p, v2p)
9520c8bb 608 const PTR v1p;
609 const PTR v2p;
ffbd18cc 610{
20f0a040 611 int v1 = *(const int *)v1p, v2 = *(const int *)v2p;
ffbd18cc 612 /* Note that the quotient will never be bigger than
613 the value of floor_log2 times the maximum number of
eefdec48 614 times a register can occur in one insn (surely less than 100)
615 weighted by the frequency (maximally REG_FREQ_MAX).
616 Multiplying this by 10000/REG_FREQ_MAX can't overflow. */
19cb6b50 617 int pri1
63f23608 618 = (((double) (floor_log2 (allocno[v1].n_refs) * allocno[v1].freq)
71b77236 619 / allocno[v1].live_length)
eefdec48 620 * (10000 / REG_FREQ_MAX) * allocno[v1].size);
19cb6b50 621 int pri2
63f23608 622 = (((double) (floor_log2 (allocno[v2].n_refs) * allocno[v2].freq)
71b77236 623 / allocno[v2].live_length)
eefdec48 624 * (10000 / REG_FREQ_MAX) * allocno[v2].size);
ffbd18cc 625 if (pri2 - pri1)
626 return pri2 - pri1;
627
628 /* If regs are equally good, sort by allocno,
629 so that the results of qsort leave nothing to chance. */
de27a084 630 return v1 - v2;
ffbd18cc 631}
632\f
633/* Scan the rtl code and record all conflicts and register preferences in the
634 conflict matrices and preference tables. */
635
636static void
637global_conflicts ()
638{
4c26117a 639 int i;
640 basic_block b;
19cb6b50 641 rtx insn;
75fa5dae 642 int *block_start_allocnos;
ffbd18cc 643
644 /* Make a vector that mark_reg_{store,clobber} will store in. */
8b861be4 645 regs_set = (rtx *) xmalloc (max_parallel * sizeof (rtx) * 2);
ffbd18cc 646
8b861be4 647 block_start_allocnos = (int *) xmalloc (max_allocno * sizeof (int));
ffbd18cc 648
4c26117a 649 FOR_EACH_BB (b)
ffbd18cc 650 {
93d3b7de 651 memset ((char *) allocnos_live, 0, allocno_row_words * sizeof (INT_TYPE));
ffbd18cc 652
653 /* Initialize table of registers currently live
654 to the state at the beginning of this basic block.
60f19080 655 This also marks the conflicts among hard registers
656 and any allocnos that are live.
ffbd18cc 657
658 For pseudo-regs, there is only one bit for each one
659 no matter how many hard regs it occupies.
660 This is ok; we know the size from PSEUDO_REGNO_SIZE.
661 For explicit hard regs, we cannot know the size that way
662 since one hard reg can be used with various sizes.
663 Therefore, we must require that all the hard regs
664 implicitly live as part of a multi-word hard reg
665 are explicitly marked in basic_block_live_at_start. */
666
667 {
4c26117a 668 regset old = b->global_live_at_start;
ffbd18cc 669 int ax = 0;
670
74666a14 671 REG_SET_TO_HARD_REG_SET (hard_regs_live, old);
31df18a3 672 EXECUTE_IF_SET_IN_REG_SET (old, FIRST_PSEUDO_REGISTER, i,
74666a14 673 {
19cb6b50 674 int a = reg_allocno[i];
74666a14 675 if (a >= 0)
676 {
677 SET_ALLOCNO_LIVE (a);
678 block_start_allocnos[ax++] = a;
679 }
680 else if ((a = reg_renumber[i]) >= 0)
31df18a3 681 mark_reg_live_nc
682 (a, PSEUDO_REGNO_MODE (i));
74666a14 683 });
ffbd18cc 684
60f19080 685 /* Record that each allocno now live conflicts with each hard reg
686 now live.
ffbd18cc 687
60f19080 688 It is not necessary to mark any conflicts between pseudos as
689 this point, even for pseudos which are live at the start of
690 the basic block.
691
692 Given two pseudos X and Y and any point in the CFG P.
693
694 On any path to point P where X and Y are live one of the
695 following conditions must be true:
696
697 1. X is live at some instruction on the path that
698 evaluates Y.
699
700 2. Y is live at some instruction on the path that
701 evaluates X.
702
703 3. Either X or Y is not evaluted on the path to P
704 (ie it is used uninitialized) and thus the
705 conflict can be ignored.
706
707 In cases #1 and #2 the conflict will be recorded when we
708 scan the instruction that makes either X or Y become live. */
ffbd18cc 709 record_conflicts (block_start_allocnos, ax);
f24e9d92 710
711#ifdef STACK_REGS
71caadc0 712 {
713 /* Pseudos can't go in stack regs at the start of a basic block
f3d96a58 714 that is reached by an abnormal edge. */
71caadc0 715
716 edge e;
4c26117a 717 for (e = b->pred; e ; e = e->pred_next)
71caadc0 718 if (e->flags & EDGE_ABNORMAL)
719 break;
71caadc0 720 if (e != NULL)
721 for (ax = FIRST_STACK_REG; ax <= LAST_STACK_REG; ax++)
722 record_one_conflict (ax);
723 }
f24e9d92 724#endif
ffbd18cc 725 }
726
4c26117a 727 insn = b->head;
ffbd18cc 728
729 /* Scan the code of this basic block, noting which allocnos
730 and hard regs are born or die. When one is born,
731 record a conflict with all others currently live. */
732
733 while (1)
734 {
19cb6b50 735 RTX_CODE code = GET_CODE (insn);
736 rtx link;
ffbd18cc 737
738 /* Make regs_set an empty set. */
739
740 n_regs_set = 0;
741
742 if (code == INSN || code == CALL_INSN || code == JUMP_INSN)
743 {
ffbd18cc 744
745#if 0
ab9d0fcb 746 int i = 0;
ffbd18cc 747 for (link = REG_NOTES (insn);
748 link && i < NUM_NO_CONFLICT_PAIRS;
749 link = XEXP (link, 1))
750 if (REG_NOTE_KIND (link) == REG_NO_CONFLICT)
751 {
752 no_conflict_pairs[i].allocno1
753 = reg_allocno[REGNO (SET_DEST (PATTERN (insn)))];
754 no_conflict_pairs[i].allocno2
755 = reg_allocno[REGNO (XEXP (link, 0))];
756 i++;
757 }
758#endif /* 0 */
759
760 /* Mark any registers clobbered by INSN as live,
761 so they conflict with the inputs. */
762
ec8895d7 763 note_stores (PATTERN (insn), mark_reg_clobber, NULL);
ffbd18cc 764
765 /* Mark any registers dead after INSN as dead now. */
766
767 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
768 if (REG_NOTE_KIND (link) == REG_DEAD)
769 mark_reg_death (XEXP (link, 0));
770
771 /* Mark any registers set in INSN as live,
772 and mark them as conflicting with all other live regs.
773 Clobbers are processed again, so they conflict with
774 the registers that are set. */
775
ec8895d7 776 note_stores (PATTERN (insn), mark_reg_store, NULL);
ffbd18cc 777
778#ifdef AUTO_INC_DEC
779 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
780 if (REG_NOTE_KIND (link) == REG_INC)
ec8895d7 781 mark_reg_store (XEXP (link, 0), NULL_RTX, NULL);
ffbd18cc 782#endif
783
eea407a7 784 /* If INSN has multiple outputs, then any reg that dies here
785 and is used inside of an output
e6cae665 786 must conflict with the other outputs.
787
788 It is unsafe to use !single_set here since it will ignore an
789 unused output. Just because an output is unused does not mean
790 the compiler can assume the side effect will not occur.
791 Consider if REG appears in the address of an output and we
792 reload the output. If we allocate REG to the same hard
793 register as an unused output we could set the hard register
794 before the output reload insn. */
795 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
eea407a7 796 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
797 if (REG_NOTE_KIND (link) == REG_DEAD)
798 {
799 int used_in_output = 0;
800 int i;
801 rtx reg = XEXP (link, 0);
802
803 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
804 {
805 rtx set = XVECEXP (PATTERN (insn), 0, i);
806 if (GET_CODE (set) == SET
807 && GET_CODE (SET_DEST (set)) != REG
808 && !rtx_equal_p (reg, SET_DEST (set))
809 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
810 used_in_output = 1;
811 }
812 if (used_in_output)
813 mark_reg_conflicts (reg);
814 }
815
ffbd18cc 816 /* Mark any registers set in INSN and then never used. */
817
34c8a8c1 818 while (n_regs_set-- > 0)
819 {
820 rtx note = find_regno_note (insn, REG_UNUSED,
821 REGNO (regs_set[n_regs_set]));
822 if (note)
823 mark_reg_death (XEXP (note, 0));
824 }
ffbd18cc 825 }
826
4c26117a 827 if (insn == b->end)
ffbd18cc 828 break;
829 insn = NEXT_INSN (insn);
830 }
831 }
8b861be4 832
833 /* Clean up. */
834 free (block_start_allocnos);
835 free (regs_set);
ffbd18cc 836}
837/* Expand the preference information by looking for cases where one allocno
838 dies in an insn that sets an allocno. If those two allocnos don't conflict,
839 merge any preferences between those allocnos. */
840
841static void
842expand_preferences ()
843{
844 rtx insn;
845 rtx link;
846 rtx set;
847
848 /* We only try to handle the most common cases here. Most of the cases
849 where this wins are reg-reg copies. */
850
851 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9204e736 852 if (INSN_P (insn)
ffbd18cc 853 && (set = single_set (insn)) != 0
854 && GET_CODE (SET_DEST (set)) == REG
855 && reg_allocno[REGNO (SET_DEST (set))] >= 0)
856 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
857 if (REG_NOTE_KIND (link) == REG_DEAD
858 && GET_CODE (XEXP (link, 0)) == REG
859 && reg_allocno[REGNO (XEXP (link, 0))] >= 0
860 && ! CONFLICTP (reg_allocno[REGNO (SET_DEST (set))],
51bc0ccc 861 reg_allocno[REGNO (XEXP (link, 0))]))
ffbd18cc 862 {
863 int a1 = reg_allocno[REGNO (SET_DEST (set))];
864 int a2 = reg_allocno[REGNO (XEXP (link, 0))];
865
866 if (XEXP (link, 0) == SET_SRC (set))
867 {
71b77236 868 IOR_HARD_REG_SET (allocno[a1].hard_reg_copy_preferences,
869 allocno[a2].hard_reg_copy_preferences);
870 IOR_HARD_REG_SET (allocno[a2].hard_reg_copy_preferences,
871 allocno[a1].hard_reg_copy_preferences);
ffbd18cc 872 }
873
71b77236 874 IOR_HARD_REG_SET (allocno[a1].hard_reg_preferences,
875 allocno[a2].hard_reg_preferences);
876 IOR_HARD_REG_SET (allocno[a2].hard_reg_preferences,
877 allocno[a1].hard_reg_preferences);
878 IOR_HARD_REG_SET (allocno[a1].hard_reg_full_preferences,
879 allocno[a2].hard_reg_full_preferences);
880 IOR_HARD_REG_SET (allocno[a2].hard_reg_full_preferences,
881 allocno[a1].hard_reg_full_preferences);
ffbd18cc 882 }
883}
884\f
885/* Prune the preferences for global registers to exclude registers that cannot
886 be used.
3cfec666 887
ffbd18cc 888 Compute `regs_someone_prefers', which is a bitmask of the hard registers
889 that are preferred by conflicting registers of lower priority. If possible,
890 we will avoid using these registers. */
3cfec666 891
ffbd18cc 892static void
893prune_preferences ()
894{
1f45e4d5 895 int i;
71b77236 896 int num;
51bc0ccc 897 int *allocno_to_order = (int *) xmalloc (max_allocno * sizeof (int));
3cfec666 898
ffbd18cc 899 /* Scan least most important to most important.
900 For each allocno, remove from preferences registers that cannot be used,
901 either because of conflicts or register type. Then compute all registers
f9e15121 902 preferred by each lower-priority register that conflicts. */
ffbd18cc 903
904 for (i = max_allocno - 1; i >= 0; i--)
905 {
51bc0ccc 906 HARD_REG_SET temp;
ffbd18cc 907
71b77236 908 num = allocno_order[i];
909 allocno_to_order[num] = i;
910 COPY_HARD_REG_SET (temp, allocno[num].hard_reg_conflicts);
ffbd18cc 911
71b77236 912 if (allocno[num].calls_crossed == 0)
ffbd18cc 913 IOR_HARD_REG_SET (temp, fixed_reg_set);
914 else
915 IOR_HARD_REG_SET (temp, call_used_reg_set);
916
917 IOR_COMPL_HARD_REG_SET
918 (temp,
71b77236 919 reg_class_contents[(int) reg_preferred_class (allocno[num].reg)]);
ffbd18cc 920
71b77236 921 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_preferences, temp);
922 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_copy_preferences, temp);
923 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_full_preferences, temp);
51bc0ccc 924 }
ffbd18cc 925
51bc0ccc 926 for (i = max_allocno - 1; i >= 0; i--)
927 {
ffbd18cc 928 /* Merge in the preferences of lower-priority registers (they have
929 already been pruned). If we also prefer some of those registers,
930 don't exclude them unless we are of a smaller size (in which case
931 we want to give the lower-priority allocno the first chance for
932 these registers). */
51bc0ccc 933 HARD_REG_SET temp, temp2;
1f45e4d5 934 int allocno2;
51bc0ccc 935
71b77236 936 num = allocno_order[i];
51bc0ccc 937
15065cea 938 CLEAR_HARD_REG_SET (temp);
939 CLEAR_HARD_REG_SET (temp2);
51bc0ccc 940
71b77236 941 EXECUTE_IF_SET_IN_ALLOCNO_SET (conflicts + num * allocno_row_words,
8c278a57 942 allocno2,
51bc0ccc 943 {
1f45e4d5 944 if (allocno_to_order[allocno2] > i)
51bc0ccc 945 {
71b77236 946 if (allocno[allocno2].size <= allocno[num].size)
947 IOR_HARD_REG_SET (temp,
948 allocno[allocno2].hard_reg_full_preferences);
1f45e4d5 949 else
71b77236 950 IOR_HARD_REG_SET (temp2,
951 allocno[allocno2].hard_reg_full_preferences);
51bc0ccc 952 }
1f45e4d5 953 });
51bc0ccc 954
71b77236 955 AND_COMPL_HARD_REG_SET (temp, allocno[num].hard_reg_full_preferences);
15065cea 956 IOR_HARD_REG_SET (temp, temp2);
71b77236 957 COPY_HARD_REG_SET (allocno[num].regs_someone_prefers, temp);
ffbd18cc 958 }
51bc0ccc 959 free (allocno_to_order);
ffbd18cc 960}
961\f
71b77236 962/* Assign a hard register to allocno NUM; look for one that is the beginning
ffbd18cc 963 of a long enough stretch of hard regs none of which conflicts with ALLOCNO.
964 The registers marked in PREFREGS are tried first.
965
966 LOSERS, if non-zero, is a HARD_REG_SET indicating registers that cannot
967 be used for this allocation.
968
50b0c9ee 969 If ALT_REGS_P is zero, consider only the preferred class of ALLOCNO's reg.
970 Otherwise ignore that preferred class and use the alternate class.
ffbd18cc 971
972 If ACCEPT_CALL_CLOBBERED is nonzero, accept a call-clobbered hard reg that
973 will have to be saved and restored at calls.
974
05f2333b 975 RETRYING is nonzero if this is called from retry_global_alloc.
976
ffbd18cc 977 If we find one, record it in reg_renumber.
978 If not, do nothing. */
979
980static void
71b77236 981find_reg (num, losers, alt_regs_p, accept_call_clobbered, retrying)
982 int num;
ffbd18cc 983 HARD_REG_SET losers;
50b0c9ee 984 int alt_regs_p;
ffbd18cc 985 int accept_call_clobbered;
05f2333b 986 int retrying;
ffbd18cc 987{
19cb6b50 988 int i, best_reg, pass;
ffbd18cc 989#ifdef HARD_REG_SET
990 register /* Declare it register if it's a scalar. */
991#endif
05f2333b 992 HARD_REG_SET used, used1, used2;
ffbd18cc 993
50b0c9ee 994 enum reg_class class = (alt_regs_p
71b77236 995 ? reg_alternate_class (allocno[num].reg)
996 : reg_preferred_class (allocno[num].reg));
997 enum machine_mode mode = PSEUDO_REGNO_MODE (allocno[num].reg);
ffbd18cc 998
999 if (accept_call_clobbered)
1000 COPY_HARD_REG_SET (used1, call_fixed_reg_set);
71b77236 1001 else if (allocno[num].calls_crossed == 0)
ffbd18cc 1002 COPY_HARD_REG_SET (used1, fixed_reg_set);
1003 else
1004 COPY_HARD_REG_SET (used1, call_used_reg_set);
1005
1006 /* Some registers should not be allocated in global-alloc. */
1007 IOR_HARD_REG_SET (used1, no_global_alloc_regs);
1008 if (losers)
1009 IOR_HARD_REG_SET (used1, losers);
1010
1011 IOR_COMPL_HARD_REG_SET (used1, reg_class_contents[(int) class]);
05f2333b 1012 COPY_HARD_REG_SET (used2, used1);
1013
71b77236 1014 IOR_HARD_REG_SET (used1, allocno[num].hard_reg_conflicts);
ffbd18cc 1015
c5af420e 1016#ifdef CLASS_CANNOT_CHANGE_MODE
1017 if (REG_CHANGES_MODE (allocno[num].reg))
7fbbfd4a 1018 IOR_HARD_REG_SET (used1,
c5af420e 1019 reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
7fbbfd4a 1020#endif
1021
ffbd18cc 1022 /* Try each hard reg to see if it fits. Do this in two passes.
f9e15121 1023 In the first pass, skip registers that are preferred by some other pseudo
ffbd18cc 1024 to give it a better chance of getting one of those registers. Only if
1025 we can't get a register when excluding those do we take one of them.
1026 However, we never allocate a register for the first time in pass 0. */
1027
1028 COPY_HARD_REG_SET (used, used1);
1029 IOR_COMPL_HARD_REG_SET (used, regs_used_so_far);
71b77236 1030 IOR_HARD_REG_SET (used, allocno[num].regs_someone_prefers);
3cfec666 1031
ffbd18cc 1032 best_reg = -1;
1033 for (i = FIRST_PSEUDO_REGISTER, pass = 0;
1034 pass <= 1 && i >= FIRST_PSEUDO_REGISTER;
1035 pass++)
1036 {
1037 if (pass == 1)
1038 COPY_HARD_REG_SET (used, used1);
1039 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1040 {
1041#ifdef REG_ALLOC_ORDER
1042 int regno = reg_alloc_order[i];
1043#else
1044 int regno = i;
1045#endif
1046 if (! TEST_HARD_REG_BIT (used, regno)
fc51ca3b 1047 && HARD_REGNO_MODE_OK (regno, mode)
71b77236 1048 && (allocno[num].calls_crossed == 0
fc51ca3b 1049 || accept_call_clobbered
1050 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
ffbd18cc 1051 {
19cb6b50 1052 int j;
1053 int lim = regno + HARD_REGNO_NREGS (regno, mode);
ffbd18cc 1054 for (j = regno + 1;
1055 (j < lim
1056 && ! TEST_HARD_REG_BIT (used, j));
1057 j++);
1058 if (j == lim)
1059 {
1060 best_reg = regno;
1061 break;
1062 }
1063#ifndef REG_ALLOC_ORDER
1064 i = j; /* Skip starting points we know will lose */
1065#endif
1066 }
1067 }
1068 }
1069
1070 /* See if there is a preferred register with the same class as the register
1071 we allocated above. Making this restriction prevents register
1072 preferencing from creating worse register allocation.
1073
1074 Remove from the preferred registers and conflicting registers. Note that
1075 additional conflicts may have been added after `prune_preferences' was
3cfec666 1076 called.
ffbd18cc 1077
1078 First do this for those register with copy preferences, then all
1079 preferred registers. */
1080
71b77236 1081 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_copy_preferences, used);
1082 GO_IF_HARD_REG_SUBSET (allocno[num].hard_reg_copy_preferences,
ffbd18cc 1083 reg_class_contents[(int) NO_REGS], no_copy_prefs);
1084
1085 if (best_reg >= 0)
1086 {
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
71b77236 1088 if (TEST_HARD_REG_BIT (allocno[num].hard_reg_copy_preferences, i)
ffbd18cc 1089 && HARD_REGNO_MODE_OK (i, mode)
ddaaa5fd 1090 && (allocno[num].calls_crossed == 0
1091 || accept_call_clobbered
1092 || ! HARD_REGNO_CALL_PART_CLOBBERED (i, mode))
ffbd18cc 1093 && (REGNO_REG_CLASS (i) == REGNO_REG_CLASS (best_reg)
1094 || reg_class_subset_p (REGNO_REG_CLASS (i),
1095 REGNO_REG_CLASS (best_reg))
1096 || reg_class_subset_p (REGNO_REG_CLASS (best_reg),
1097 REGNO_REG_CLASS (i))))
1098 {
19cb6b50 1099 int j;
1100 int lim = i + HARD_REGNO_NREGS (i, mode);
ffbd18cc 1101 for (j = i + 1;
1102 (j < lim
1103 && ! TEST_HARD_REG_BIT (used, j)
1104 && (REGNO_REG_CLASS (j)
1105 == REGNO_REG_CLASS (best_reg + (j - i))
1106 || reg_class_subset_p (REGNO_REG_CLASS (j),
1107 REGNO_REG_CLASS (best_reg + (j - i)))
1108 || reg_class_subset_p (REGNO_REG_CLASS (best_reg + (j - i)),
1109 REGNO_REG_CLASS (j))));
1110 j++);
1111 if (j == lim)
1112 {
1113 best_reg = i;
1114 goto no_prefs;
1115 }
1116 }
1117 }
1118 no_copy_prefs:
1119
71b77236 1120 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_preferences, used);
1121 GO_IF_HARD_REG_SUBSET (allocno[num].hard_reg_preferences,
ffbd18cc 1122 reg_class_contents[(int) NO_REGS], no_prefs);
1123
1124 if (best_reg >= 0)
1125 {
1126 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
71b77236 1127 if (TEST_HARD_REG_BIT (allocno[num].hard_reg_preferences, i)
ffbd18cc 1128 && HARD_REGNO_MODE_OK (i, mode)
ddaaa5fd 1129 && (allocno[num].calls_crossed == 0
1130 || accept_call_clobbered
1131 || ! HARD_REGNO_CALL_PART_CLOBBERED (i, mode))
ffbd18cc 1132 && (REGNO_REG_CLASS (i) == REGNO_REG_CLASS (best_reg)
1133 || reg_class_subset_p (REGNO_REG_CLASS (i),
1134 REGNO_REG_CLASS (best_reg))
1135 || reg_class_subset_p (REGNO_REG_CLASS (best_reg),
1136 REGNO_REG_CLASS (i))))
1137 {
19cb6b50 1138 int j;
1139 int lim = i + HARD_REGNO_NREGS (i, mode);
ffbd18cc 1140 for (j = i + 1;
1141 (j < lim
1142 && ! TEST_HARD_REG_BIT (used, j)
1143 && (REGNO_REG_CLASS (j)
1144 == REGNO_REG_CLASS (best_reg + (j - i))
1145 || reg_class_subset_p (REGNO_REG_CLASS (j),
1146 REGNO_REG_CLASS (best_reg + (j - i)))
1147 || reg_class_subset_p (REGNO_REG_CLASS (best_reg + (j - i)),
1148 REGNO_REG_CLASS (j))));
1149 j++);
1150 if (j == lim)
1151 {
1152 best_reg = i;
1153 break;
1154 }
1155 }
1156 }
1157 no_prefs:
1158
3cfec666 1159 /* If we haven't succeeded yet, try with caller-saves.
e65e050b 1160 We need not check to see if the current function has nonlocal
1161 labels because we don't put any pseudos that are live over calls in
1162 registers in that case. */
1163
05f2333b 1164 if (flag_caller_saves && best_reg < 0)
1165 {
1166 /* Did not find a register. If it would be profitable to
1167 allocate a call-clobbered register and save and restore it
1168 around calls, do that. */
1169 if (! accept_call_clobbered
71b77236 1170 && allocno[num].calls_crossed != 0
1171 && CALLER_SAVE_PROFITABLE (allocno[num].n_refs,
1172 allocno[num].calls_crossed))
05f2333b 1173 {
2836f006 1174 HARD_REG_SET new_losers;
1175 if (! losers)
1176 CLEAR_HARD_REG_SET (new_losers);
1177 else
1178 COPY_HARD_REG_SET (new_losers, losers);
3cfec666 1179
2836f006 1180 IOR_HARD_REG_SET(new_losers, losing_caller_save_reg_set);
71b77236 1181 find_reg (num, new_losers, alt_regs_p, 1, retrying);
1182 if (reg_renumber[allocno[num].reg] >= 0)
05f2333b 1183 {
1184 caller_save_needed = 1;
1185 return;
1186 }
1187 }
1188 }
1189
1190 /* If we haven't succeeded yet,
1191 see if some hard reg that conflicts with us
1192 was utilized poorly by local-alloc.
1193 If so, kick out the regs that were put there by local-alloc
1194 so we can use it instead. */
1195 if (best_reg < 0 && !retrying
1196 /* Let's not bother with multi-reg allocnos. */
71b77236 1197 && allocno[num].size == 1)
05f2333b 1198 {
1199 /* Count from the end, to find the least-used ones first. */
1200 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
0c8c7dbf 1201 {
1202#ifdef REG_ALLOC_ORDER
1203 int regno = reg_alloc_order[i];
1204#else
1205 int regno = i;
1206#endif
3b1a9578 1207
0c8c7dbf 1208 if (local_reg_n_refs[regno] != 0
1209 /* Don't use a reg no good for this pseudo. */
1210 && ! TEST_HARD_REG_BIT (used2, regno)
7fbbfd4a 1211 && HARD_REGNO_MODE_OK (regno, mode)
ddaaa5fd 1212 && (allocno[num].calls_crossed == 0
1213 || accept_call_clobbered
1214 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
c5af420e 1215#ifdef CLASS_CANNOT_CHANGE_MODE
1216 && ! (REG_CHANGES_MODE (allocno[num].reg)
7fbbfd4a 1217 && (TEST_HARD_REG_BIT
c5af420e 1218 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
7fbbfd4a 1219 regno)))
1220#endif
1221 )
0c8c7dbf 1222 {
d9893de9 1223 /* We explicitly evaluate the divide results into temporary
1224 variables so as to avoid excess precision problems that occur
20dd417a 1225 on an i386-unknown-sysv4.2 (unixware) host. */
3cfec666 1226
63f23608 1227 double tmp1 = ((double) local_reg_freq[regno]
d9893de9 1228 / local_reg_live_length[regno]);
63f23608 1229 double tmp2 = ((double) allocno[num].freq
71b77236 1230 / allocno[num].live_length);
d9893de9 1231
1232 if (tmp1 < tmp2)
1233 {
1234 /* Hard reg REGNO was used less in total by local regs
1235 than it would be used by this one allocno! */
1236 int k;
1237 for (k = 0; k < max_regno; k++)
1238 if (reg_renumber[k] >= 0)
1239 {
1240 int r = reg_renumber[k];
1241 int endregno
1242 = r + HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (k));
3b1a9578 1243
d9893de9 1244 if (regno >= r && regno < endregno)
1245 reg_renumber[k] = -1;
1246 }
0c8c7dbf 1247
d9893de9 1248 best_reg = regno;
1249 break;
1250 }
0c8c7dbf 1251 }
1252 }
05f2333b 1253 }
1254
ffbd18cc 1255 /* Did we find a register? */
1256
1257 if (best_reg >= 0)
1258 {
19cb6b50 1259 int lim, j;
ffbd18cc 1260 HARD_REG_SET this_reg;
1261
1262 /* Yes. Record it as the hard register of this pseudo-reg. */
71b77236 1263 reg_renumber[allocno[num].reg] = best_reg;
ffbd18cc 1264 /* Also of any pseudo-regs that share with it. */
71b77236 1265 if (reg_may_share[allocno[num].reg])
ffbd18cc 1266 for (j = FIRST_PSEUDO_REGISTER; j < max_regno; j++)
71b77236 1267 if (reg_allocno[j] == num)
ffbd18cc 1268 reg_renumber[j] = best_reg;
1269
1270 /* Make a set of the hard regs being allocated. */
1271 CLEAR_HARD_REG_SET (this_reg);
1272 lim = best_reg + HARD_REGNO_NREGS (best_reg, mode);
1273 for (j = best_reg; j < lim; j++)
1274 {
1275 SET_HARD_REG_BIT (this_reg, j);
1276 SET_HARD_REG_BIT (regs_used_so_far, j);
05f2333b 1277 /* This is no longer a reg used just by local regs. */
1278 local_reg_n_refs[j] = 0;
63f23608 1279 local_reg_freq[j] = 0;
ffbd18cc 1280 }
1281 /* For each other pseudo-reg conflicting with this one,
1282 mark it as conflicting with the hard regs this one occupies. */
71b77236 1283 lim = num;
8c278a57 1284 EXECUTE_IF_SET_IN_ALLOCNO_SET (conflicts + lim * allocno_row_words, j,
1f45e4d5 1285 {
71b77236 1286 IOR_HARD_REG_SET (allocno[j].hard_reg_conflicts, this_reg);
1f45e4d5 1287 });
ffbd18cc 1288 }
ffbd18cc 1289}
1290\f
1291/* Called from `reload' to look for a hard reg to put pseudo reg REGNO in.
1292 Perhaps it had previously seemed not worth a hard reg,
1293 or perhaps its old hard reg has been commandeered for reloads.
1294 FORBIDDEN_REGS indicates certain hard regs that may not be used, even if
1295 they do not appear to be allocated.
1296 If FORBIDDEN_REGS is zero, no regs are forbidden. */
1297
1298void
1299retry_global_alloc (regno, forbidden_regs)
1300 int regno;
1301 HARD_REG_SET forbidden_regs;
1302{
e1a0b211 1303 int alloc_no = reg_allocno[regno];
1304 if (alloc_no >= 0)
ffbd18cc 1305 {
1306 /* If we have more than one register class,
1307 first try allocating in the class that is cheapest
1308 for this pseudo-reg. If that fails, try any reg. */
1309 if (N_REG_CLASSES > 1)
e1a0b211 1310 find_reg (alloc_no, forbidden_regs, 0, 0, 1);
ffbd18cc 1311 if (reg_renumber[regno] < 0
50b0c9ee 1312 && reg_alternate_class (regno) != NO_REGS)
e1a0b211 1313 find_reg (alloc_no, forbidden_regs, 1, 0, 1);
ffbd18cc 1314
1315 /* If we found a register, modify the RTL for the register to
1316 show the hard register, and mark that register live. */
1317 if (reg_renumber[regno] >= 0)
1318 {
1319 REGNO (regno_reg_rtx[regno]) = reg_renumber[regno];
1320 mark_home_live (regno);
1321 }
1322 }
1323}
1324\f
1325/* Record a conflict between register REGNO
1326 and everything currently live.
1327 REGNO must not be a pseudo reg that was allocated
1328 by local_alloc; such numbers must be translated through
1329 reg_renumber before calling here. */
1330
1331static void
1332record_one_conflict (regno)
1333 int regno;
1334{
19cb6b50 1335 int j;
ffbd18cc 1336
1337 if (regno < FIRST_PSEUDO_REGISTER)
1338 /* When a hard register becomes live,
1339 record conflicts with live pseudo regs. */
1f45e4d5 1340 EXECUTE_IF_SET_IN_ALLOCNO_SET (allocnos_live, j,
ffbd18cc 1341 {
71b77236 1342 SET_HARD_REG_BIT (allocno[j].hard_reg_conflicts, regno);
1f45e4d5 1343 });
ffbd18cc 1344 else
1345 /* When a pseudo-register becomes live,
1346 record conflicts first with hard regs,
1347 then with other pseudo regs. */
1348 {
19cb6b50 1349 int ialloc = reg_allocno[regno];
1350 int ialloc_prod = ialloc * allocno_row_words;
1351
71b77236 1352 IOR_HARD_REG_SET (allocno[ialloc].hard_reg_conflicts, hard_regs_live);
ffbd18cc 1353 for (j = allocno_row_words - 1; j >= 0; j--)
1354 {
1355#if 0
1356 int k;
1357 for (k = 0; k < n_no_conflict_pairs; k++)
1358 if (! ((j == no_conflict_pairs[k].allocno1
1359 && ialloc == no_conflict_pairs[k].allocno2)
1360 ||
1361 (j == no_conflict_pairs[k].allocno2
1362 && ialloc == no_conflict_pairs[k].allocno1)))
1363#endif /* 0 */
1364 conflicts[ialloc_prod + j] |= allocnos_live[j];
1365 }
1366 }
1367}
1368
1369/* Record all allocnos currently live as conflicting
60f19080 1370 with all hard regs currently live.
1371
ffbd18cc 1372 ALLOCNO_VEC is a vector of LEN allocnos, all allocnos that
1373 are currently live. Their bits are also flagged in allocnos_live. */
1374
1375static void
1376record_conflicts (allocno_vec, len)
19cb6b50 1377 int *allocno_vec;
1378 int len;
ffbd18cc 1379{
19cb6b50 1380 int num;
1381 int ialloc_prod;
ffbd18cc 1382
1383 while (--len >= 0)
1384 {
71b77236 1385 num = allocno_vec[len];
1386 ialloc_prod = num * allocno_row_words;
1387 IOR_HARD_REG_SET (allocno[num].hard_reg_conflicts, hard_regs_live);
ffbd18cc 1388 }
1389}
51bc0ccc 1390
1391/* If CONFLICTP (i, j) is true, make sure CONFLICTP (j, i) is also true. */
1392static void
1393mirror_conflicts ()
1394{
19cb6b50 1395 int i, j;
51bc0ccc 1396 int rw = allocno_row_words;
1397 int rwb = rw * INT_BITS;
1398 INT_TYPE *p = conflicts;
1399 INT_TYPE *q0 = conflicts, *q1, *q2;
1400 unsigned INT_TYPE mask;
1401
1402 for (i = max_allocno - 1, mask = 1; i >= 0; i--, mask <<= 1)
1403 {
1404 if (! mask)
1405 {
1406 mask = 1;
1407 q0++;
1408 }
1409 for (j = allocno_row_words - 1, q1 = q0; j >= 0; j--, q1 += rwb)
1410 {
1411 unsigned INT_TYPE word;
1412
1413 for (word = (unsigned INT_TYPE) *p++, q2 = q1; word;
1414 word >>= 1, q2 += rw)
1415 {
1416 if (word & 1)
1417 *q2 |= mask;
1418 }
1419 }
1420 }
1421}
ffbd18cc 1422\f
1423/* Handle the case where REG is set by the insn being scanned,
1424 during the forward scan to accumulate conflicts.
1425 Store a 1 in regs_live or allocnos_live for this register, record how many
1426 consecutive hardware registers it actually needs,
1427 and record a conflict with all other registers already live.
1428
1429 Note that even if REG does not remain alive after this insn,
1430 we must mark it here as live, to ensure a conflict between
1431 REG and any other regs set in this insn that really do live.
1432 This is because those other regs could be considered after this.
1433
1434 REG might actually be something other than a register;
1435 if so, we do nothing.
1436
1437 SETTER is 0 if this register was modified by an auto-increment (i.e.,
0fa3405d 1438 a REG_INC note was found for it). */
ffbd18cc 1439
1440static void
ec8895d7 1441mark_reg_store (reg, setter, data)
0fa3405d 1442 rtx reg, setter;
ec8895d7 1443 void *data ATTRIBUTE_UNUSED;
ffbd18cc 1444{
19cb6b50 1445 int regno;
ffbd18cc 1446
ffbd18cc 1447 if (GET_CODE (reg) == SUBREG)
701e46d0 1448 reg = SUBREG_REG (reg);
ffbd18cc 1449
1450 if (GET_CODE (reg) != REG)
1451 return;
1452
ffbd18cc 1453 regs_set[n_regs_set++] = reg;
1454
0fa3405d 1455 if (setter && GET_CODE (setter) != CLOBBER)
ffbd18cc 1456 set_preference (reg, SET_SRC (setter));
1457
1458 regno = REGNO (reg);
1459
ffbd18cc 1460 /* Either this is one of the max_allocno pseudo regs not allocated,
1461 or it is or has a hardware reg. First handle the pseudo-regs. */
1462 if (regno >= FIRST_PSEUDO_REGISTER)
1463 {
1464 if (reg_allocno[regno] >= 0)
1465 {
1466 SET_ALLOCNO_LIVE (reg_allocno[regno]);
1467 record_one_conflict (regno);
1468 }
1469 }
0b6b86e7 1470
1471 if (reg_renumber[regno] >= 0)
701e46d0 1472 regno = reg_renumber[regno];
0b6b86e7 1473
ffbd18cc 1474 /* Handle hardware regs (and pseudos allocated to hard regs). */
0b6b86e7 1475 if (regno < FIRST_PSEUDO_REGISTER && ! fixed_regs[regno])
ffbd18cc 1476 {
19cb6b50 1477 int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
ffbd18cc 1478 while (regno < last)
1479 {
1480 record_one_conflict (regno);
1481 SET_HARD_REG_BIT (hard_regs_live, regno);
1482 regno++;
1483 }
1484 }
1485}
1486\f
1487/* Like mark_reg_set except notice just CLOBBERs; ignore SETs. */
1488
1489static void
ec8895d7 1490mark_reg_clobber (reg, setter, data)
ffbd18cc 1491 rtx reg, setter;
ec8895d7 1492 void *data ATTRIBUTE_UNUSED;
ffbd18cc 1493{
0fa3405d 1494 if (GET_CODE (setter) == CLOBBER)
ec8895d7 1495 mark_reg_store (reg, setter, data);
eea407a7 1496}
1497
1498/* Record that REG has conflicts with all the regs currently live.
1499 Do not mark REG itself as live. */
1500
1501static void
1502mark_reg_conflicts (reg)
1503 rtx reg;
1504{
19cb6b50 1505 int regno;
eea407a7 1506
1507 if (GET_CODE (reg) == SUBREG)
1508 reg = SUBREG_REG (reg);
1509
1510 if (GET_CODE (reg) != REG)
1511 return;
1512
1513 regno = REGNO (reg);
1514
eea407a7 1515 /* Either this is one of the max_allocno pseudo regs not allocated,
1516 or it is or has a hardware reg. First handle the pseudo-regs. */
1517 if (regno >= FIRST_PSEUDO_REGISTER)
1518 {
1519 if (reg_allocno[regno] >= 0)
1520 record_one_conflict (regno);
1521 }
0b6b86e7 1522
1523 if (reg_renumber[regno] >= 0)
1524 regno = reg_renumber[regno];
1525
eea407a7 1526 /* Handle hardware regs (and pseudos allocated to hard regs). */
0b6b86e7 1527 if (regno < FIRST_PSEUDO_REGISTER && ! fixed_regs[regno])
eea407a7 1528 {
19cb6b50 1529 int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
eea407a7 1530 while (regno < last)
1531 {
1532 record_one_conflict (regno);
1533 regno++;
1534 }
1535 }
ffbd18cc 1536}
1537\f
1538/* Mark REG as being dead (following the insn being scanned now).
1539 Store a 0 in regs_live or allocnos_live for this register. */
1540
1541static void
1542mark_reg_death (reg)
1543 rtx reg;
1544{
19cb6b50 1545 int regno = REGNO (reg);
ffbd18cc 1546
ffbd18cc 1547 /* Either this is one of the max_allocno pseudo regs not allocated,
1548 or it is a hardware reg. First handle the pseudo-regs. */
1549 if (regno >= FIRST_PSEUDO_REGISTER)
1550 {
1551 if (reg_allocno[regno] >= 0)
1552 CLEAR_ALLOCNO_LIVE (reg_allocno[regno]);
1553 }
0b6b86e7 1554
1555 /* For pseudo reg, see if it has been assigned a hardware reg. */
1556 if (reg_renumber[regno] >= 0)
1557 regno = reg_renumber[regno];
1558
ffbd18cc 1559 /* Handle hardware regs (and pseudos allocated to hard regs). */
0b6b86e7 1560 if (regno < FIRST_PSEUDO_REGISTER && ! fixed_regs[regno])
ffbd18cc 1561 {
1562 /* Pseudo regs already assigned hardware regs are treated
1563 almost the same as explicit hardware regs. */
19cb6b50 1564 int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
ffbd18cc 1565 while (regno < last)
1566 {
1567 CLEAR_HARD_REG_BIT (hard_regs_live, regno);
1568 regno++;
1569 }
1570 }
1571}
1572
1573/* Mark hard reg REGNO as currently live, assuming machine mode MODE
1574 for the value stored in it. MODE determines how many consecutive
1575 registers are actually in use. Do not record conflicts;
1576 it is assumed that the caller will do that. */
1577
1578static void
1579mark_reg_live_nc (regno, mode)
19cb6b50 1580 int regno;
ffbd18cc 1581 enum machine_mode mode;
1582{
19cb6b50 1583 int last = regno + HARD_REGNO_NREGS (regno, mode);
ffbd18cc 1584 while (regno < last)
1585 {
1586 SET_HARD_REG_BIT (hard_regs_live, regno);
1587 regno++;
1588 }
1589}
1590\f
1591/* Try to set a preference for an allocno to a hard register.
1592 We are passed DEST and SRC which are the operands of a SET. It is known
1593 that SRC is a register. If SRC or the first operand of SRC is a register,
1594 try to set a preference. If one of the two is a hard register and the other
1595 is a pseudo-register, mark the preference.
3cfec666 1596
4bbea254 1597 Note that we are not as aggressive as local-alloc in trying to tie a
ffbd18cc 1598 pseudo-register to a hard register. */
1599
1600static void
1601set_preference (dest, src)
1602 rtx dest, src;
1603{
02e7a332 1604 unsigned int src_regno, dest_regno;
ffbd18cc 1605 /* Amount to add to the hard regno for SRC, or subtract from that for DEST,
1606 to compensate for subregs in SRC or DEST. */
1607 int offset = 0;
02e7a332 1608 unsigned int i;
ffbd18cc 1609 int copy = 1;
1610
1611 if (GET_RTX_FORMAT (GET_CODE (src))[0] == 'e')
1612 src = XEXP (src, 0), copy = 0;
1613
1614 /* Get the reg number for both SRC and DEST.
1615 If neither is a reg, give up. */
1616
1617 if (GET_CODE (src) == REG)
1618 src_regno = REGNO (src);
1619 else if (GET_CODE (src) == SUBREG && GET_CODE (SUBREG_REG (src)) == REG)
1620 {
1621 src_regno = REGNO (SUBREG_REG (src));
701e46d0 1622
1623 if (REGNO (SUBREG_REG (src)) < FIRST_PSEUDO_REGISTER)
1624 offset += subreg_regno_offset (REGNO (SUBREG_REG (src)),
1625 GET_MODE (SUBREG_REG (src)),
1626 SUBREG_BYTE (src),
1627 GET_MODE (src));
1628 else
1629 offset += (SUBREG_BYTE (src)
1630 / REGMODE_NATURAL_SIZE (GET_MODE (src)));
ffbd18cc 1631 }
1632 else
1633 return;
1634
1635 if (GET_CODE (dest) == REG)
1636 dest_regno = REGNO (dest);
1637 else if (GET_CODE (dest) == SUBREG && GET_CODE (SUBREG_REG (dest)) == REG)
1638 {
1639 dest_regno = REGNO (SUBREG_REG (dest));
701e46d0 1640
1641 if (REGNO (SUBREG_REG (dest)) < FIRST_PSEUDO_REGISTER)
1642 offset -= subreg_regno_offset (REGNO (SUBREG_REG (dest)),
1643 GET_MODE (SUBREG_REG (dest)),
1644 SUBREG_BYTE (dest),
1645 GET_MODE (dest));
1646 else
1647 offset -= (SUBREG_BYTE (dest)
1648 / REGMODE_NATURAL_SIZE (GET_MODE (dest)));
ffbd18cc 1649 }
1650 else
1651 return;
1652
1653 /* Convert either or both to hard reg numbers. */
1654
1655 if (reg_renumber[src_regno] >= 0)
1656 src_regno = reg_renumber[src_regno];
1657
1658 if (reg_renumber[dest_regno] >= 0)
1659 dest_regno = reg_renumber[dest_regno];
1660
1661 /* Now if one is a hard reg and the other is a global pseudo
1662 then give the other a preference. */
1663
1664 if (dest_regno < FIRST_PSEUDO_REGISTER && src_regno >= FIRST_PSEUDO_REGISTER
1665 && reg_allocno[src_regno] >= 0)
1666 {
1667 dest_regno -= offset;
02e7a332 1668 if (dest_regno < FIRST_PSEUDO_REGISTER)
ffbd18cc 1669 {
1670 if (copy)
1671 SET_REGBIT (hard_reg_copy_preferences,
1672 reg_allocno[src_regno], dest_regno);
1673
1674 SET_REGBIT (hard_reg_preferences,
1675 reg_allocno[src_regno], dest_regno);
1676 for (i = dest_regno;
1677 i < dest_regno + HARD_REGNO_NREGS (dest_regno, GET_MODE (dest));
1678 i++)
1679 SET_REGBIT (hard_reg_full_preferences, reg_allocno[src_regno], i);
1680 }
1681 }
1682
1683 if (src_regno < FIRST_PSEUDO_REGISTER && dest_regno >= FIRST_PSEUDO_REGISTER
1684 && reg_allocno[dest_regno] >= 0)
1685 {
1686 src_regno += offset;
02e7a332 1687 if (src_regno < FIRST_PSEUDO_REGISTER)
ffbd18cc 1688 {
1689 if (copy)
1690 SET_REGBIT (hard_reg_copy_preferences,
1691 reg_allocno[dest_regno], src_regno);
1692
1693 SET_REGBIT (hard_reg_preferences,
1694 reg_allocno[dest_regno], src_regno);
1695 for (i = src_regno;
1696 i < src_regno + HARD_REGNO_NREGS (src_regno, GET_MODE (src));
1697 i++)
1698 SET_REGBIT (hard_reg_full_preferences, reg_allocno[dest_regno], i);
1699 }
1700 }
1701}
1702\f
1703/* Indicate that hard register number FROM was eliminated and replaced with
1704 an offset from hard register number TO. The status of hard registers live
1705 at the start of a basic block is updated by replacing a use of FROM with
1706 a use of TO. */
1707
1708void
1709mark_elimination (from, to)
1710 int from, to;
1711{
4c26117a 1712 basic_block bb;
ffbd18cc 1713
4c26117a 1714 FOR_EACH_BB (bb)
71caadc0 1715 {
3cfec666 1716 regset r = bb->global_live_at_start;
71caadc0 1717 if (REGNO_REG_SET_P (r, from))
1718 {
1719 CLEAR_REGNO_REG_SET (r, from);
1720 SET_REGNO_REG_SET (r, to);
1721 }
1722 }
ffbd18cc 1723}
1724\f
e94a59c6 1725/* Used for communication between the following functions. Holds the
1726 current life information. */
1727static regset live_relevant_regs;
1728
a570a59f 1729/* Record in live_relevant_regs and REGS_SET that register REG became live.
1730 This is called via note_stores. */
e94a59c6 1731static void
a570a59f 1732reg_becomes_live (reg, setter, regs_set)
e94a59c6 1733 rtx reg;
1734 rtx setter ATTRIBUTE_UNUSED;
a570a59f 1735 void *regs_set;
e94a59c6 1736{
1737 int regno;
1738
1739 if (GET_CODE (reg) == SUBREG)
1740 reg = SUBREG_REG (reg);
1741
1742 if (GET_CODE (reg) != REG)
1743 return;
3cfec666 1744
e94a59c6 1745 regno = REGNO (reg);
1746 if (regno < FIRST_PSEUDO_REGISTER)
1747 {
1748 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
1749 while (nregs-- > 0)
a570a59f 1750 {
1751 SET_REGNO_REG_SET (live_relevant_regs, regno);
1752 if (! fixed_regs[regno])
1753 SET_REGNO_REG_SET ((regset) regs_set, regno);
1754 regno++;
1755 }
e94a59c6 1756 }
1757 else if (reg_renumber[regno] >= 0)
a570a59f 1758 {
1759 SET_REGNO_REG_SET (live_relevant_regs, regno);
1760 SET_REGNO_REG_SET ((regset) regs_set, regno);
1761 }
e94a59c6 1762}
1763
1764/* Record in live_relevant_regs that register REGNO died. */
1765static void
a570a59f 1766reg_dies (regno, mode, chain)
e94a59c6 1767 int regno;
1768 enum machine_mode mode;
a570a59f 1769 struct insn_chain *chain;
e94a59c6 1770{
1771 if (regno < FIRST_PSEUDO_REGISTER)
1772 {
1773 int nregs = HARD_REGNO_NREGS (regno, mode);
1774 while (nregs-- > 0)
a570a59f 1775 {
1776 CLEAR_REGNO_REG_SET (live_relevant_regs, regno);
1777 if (! fixed_regs[regno])
f62c22a7 1778 SET_REGNO_REG_SET (&chain->dead_or_set, regno);
a570a59f 1779 regno++;
1780 }
e94a59c6 1781 }
1782 else
a570a59f 1783 {
1784 CLEAR_REGNO_REG_SET (live_relevant_regs, regno);
1785 if (reg_renumber[regno] >= 0)
f62c22a7 1786 SET_REGNO_REG_SET (&chain->dead_or_set, regno);
a570a59f 1787 }
e94a59c6 1788}
1789
1790/* Walk the insns of the current function and build reload_insn_chain,
1791 and record register life information. */
dd2acd83 1792void
6f5c3acb 1793build_insn_chain (first)
1794 rtx first;
e94a59c6 1795{
1796 struct insn_chain **p = &reload_insn_chain;
1797 struct insn_chain *prev = 0;
345ac34a 1798 basic_block b = ENTRY_BLOCK_PTR->next_bb;
3367fbd0 1799 regset_head live_relevant_regs_head;
e94a59c6 1800
3367fbd0 1801 live_relevant_regs = INITIALIZE_REG_SET (live_relevant_regs_head);
e94a59c6 1802
6f5c3acb 1803 for (; first; first = NEXT_INSN (first))
e94a59c6 1804 {
6f5c3acb 1805 struct insn_chain *c;
e94a59c6 1806
345ac34a 1807 if (first == b->head)
e94a59c6 1808 {
6f5c3acb 1809 int i;
51bc0ccc 1810
6f5c3acb 1811 CLEAR_REG_SET (live_relevant_regs);
51bc0ccc 1812
1813 EXECUTE_IF_SET_IN_BITMAP
345ac34a 1814 (b->global_live_at_start, 0, i,
51bc0ccc 1815 {
1816 if (i < FIRST_PSEUDO_REGISTER
1817 ? ! TEST_HARD_REG_BIT (eliminable_regset, i)
1818 : reg_renumber[i] >= 0)
1819 SET_REGNO_REG_SET (live_relevant_regs, i);
1820 });
3cfec666 1821 }
6f5c3acb 1822
1823 if (GET_CODE (first) != NOTE && GET_CODE (first) != BARRIER)
b104a6a7 1824 {
6f5c3acb 1825 c = new_insn_chain ();
1826 c->prev = prev;
1827 prev = c;
1828 *p = c;
1829 p = &c->next;
1830 c->insn = first;
345ac34a 1831 c->block = b->index;
6f5c3acb 1832
9204e736 1833 if (INSN_P (first))
e94a59c6 1834 {
6f5c3acb 1835 rtx link;
e94a59c6 1836
6f5c3acb 1837 /* Mark the death of everything that dies in this instruction. */
e94a59c6 1838
6f5c3acb 1839 for (link = REG_NOTES (first); link; link = XEXP (link, 1))
1840 if (REG_NOTE_KIND (link) == REG_DEAD
1841 && GET_CODE (XEXP (link, 0)) == REG)
a570a59f 1842 reg_dies (REGNO (XEXP (link, 0)), GET_MODE (XEXP (link, 0)),
1843 c);
1844
f62c22a7 1845 COPY_REG_SET (&c->live_throughout, live_relevant_regs);
e94a59c6 1846
6f5c3acb 1847 /* Mark everything born in this instruction as live. */
e94a59c6 1848
a570a59f 1849 note_stores (PATTERN (first), reg_becomes_live,
f62c22a7 1850 &c->dead_or_set);
e94a59c6 1851 }
a570a59f 1852 else
f62c22a7 1853 COPY_REG_SET (&c->live_throughout, live_relevant_regs);
6f5c3acb 1854
9204e736 1855 if (INSN_P (first))
6f5c3acb 1856 {
1857 rtx link;
1858
1859 /* Mark anything that is set in this insn and then unused as dying. */
1860
1861 for (link = REG_NOTES (first); link; link = XEXP (link, 1))
1862 if (REG_NOTE_KIND (link) == REG_UNUSED
1863 && GET_CODE (XEXP (link, 0)) == REG)
a570a59f 1864 reg_dies (REGNO (XEXP (link, 0)), GET_MODE (XEXP (link, 0)),
1865 c);
6f5c3acb 1866 }
3cf7d3b9 1867 }
b104a6a7 1868
345ac34a 1869 if (first == b->end)
1870 b = b->next_bb;
6f5c3acb 1871
1872 /* Stop after we pass the end of the last basic block. Verify that
1873 no real insns are after the end of the last basic block.
1874
1875 We may want to reorganize the loop somewhat since this test should
954b85b0 1876 always be the right exit test. Allow an ADDR_VEC or ADDR_DIF_VEC if
1877 the previous real insn is a JUMP_INSN. */
345ac34a 1878 if (b == EXIT_BLOCK_PTR)
6f5c3acb 1879 {
1880 for (first = NEXT_INSN (first) ; first; first = NEXT_INSN (first))
954b85b0 1881 if (INSN_P (first)
1882 && GET_CODE (PATTERN (first)) != USE
1883 && ! ((GET_CODE (PATTERN (first)) == ADDR_VEC
1884 || GET_CODE (PATTERN (first)) == ADDR_DIFF_VEC)
1885 && prev_real_insn (first) != 0
1886 && GET_CODE (prev_real_insn (first)) == JUMP_INSN))
6f5c3acb 1887 abort ();
1888 break;
1889 }
1890 }
e94a59c6 1891 FREE_REG_SET (live_relevant_regs);
1892 *p = 0;
1893}
1894\f
86c5656a 1895/* Print debugging trace information if -dg switch is given,
ffbd18cc 1896 showing the information on which the allocation decisions are based. */
1897
1898static void
1899dump_conflicts (file)
1900 FILE *file;
1901{
19cb6b50 1902 int i;
1903 int has_preferences;
1904 int nregs;
0b6b86e7 1905 nregs = 0;
1906 for (i = 0; i < max_allocno; i++)
1907 {
71b77236 1908 if (reg_renumber[allocno[allocno_order[i]].reg] >= 0)
3cfec666 1909 continue;
0b6b86e7 1910 nregs++;
1911 }
1912 fprintf (file, ";; %d regs to allocate:", nregs);
ffbd18cc 1913 for (i = 0; i < max_allocno; i++)
1914 {
1915 int j;
71b77236 1916 if (reg_renumber[allocno[allocno_order[i]].reg] >= 0)
0b6b86e7 1917 continue;
71b77236 1918 fprintf (file, " %d", allocno[allocno_order[i]].reg);
ffbd18cc 1919 for (j = 0; j < max_regno; j++)
1920 if (reg_allocno[j] == allocno_order[i]
71b77236 1921 && j != allocno[allocno_order[i]].reg)
ffbd18cc 1922 fprintf (file, "+%d", j);
71b77236 1923 if (allocno[allocno_order[i]].size != 1)
1924 fprintf (file, " (%d)", allocno[allocno_order[i]].size);
ffbd18cc 1925 }
1926 fprintf (file, "\n");
1927
1928 for (i = 0; i < max_allocno; i++)
1929 {
19cb6b50 1930 int j;
71b77236 1931 fprintf (file, ";; %d conflicts:", allocno[i].reg);
ffbd18cc 1932 for (j = 0; j < max_allocno; j++)
51bc0ccc 1933 if (CONFLICTP (j, i))
71b77236 1934 fprintf (file, " %d", allocno[j].reg);
ffbd18cc 1935 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
71b77236 1936 if (TEST_HARD_REG_BIT (allocno[i].hard_reg_conflicts, j))
ffbd18cc 1937 fprintf (file, " %d", j);
1938 fprintf (file, "\n");
1939
1940 has_preferences = 0;
1941 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
71b77236 1942 if (TEST_HARD_REG_BIT (allocno[i].hard_reg_preferences, j))
ffbd18cc 1943 has_preferences = 1;
1944
1945 if (! has_preferences)
1946 continue;
71b77236 1947 fprintf (file, ";; %d preferences:", allocno[i].reg);
ffbd18cc 1948 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
71b77236 1949 if (TEST_HARD_REG_BIT (allocno[i].hard_reg_preferences, j))
ffbd18cc 1950 fprintf (file, " %d", j);
1951 fprintf (file, "\n");
1952 }
1953 fprintf (file, "\n");
1954}
1955
1956void
1957dump_global_regs (file)
1958 FILE *file;
1959{
19cb6b50 1960 int i, j;
3cfec666 1961
ffbd18cc 1962 fprintf (file, ";; Register dispositions:\n");
1963 for (i = FIRST_PSEUDO_REGISTER, j = 0; i < max_regno; i++)
1964 if (reg_renumber[i] >= 0)
1965 {
1966 fprintf (file, "%d in %d ", i, reg_renumber[i]);
3cfec666 1967 if (++j % 6 == 0)
ffbd18cc 1968 fprintf (file, "\n");
1969 }
1970
1971 fprintf (file, "\n\n;; Hard regs used: ");
1972 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1973 if (regs_ever_live[i])
1974 fprintf (file, " %d", i);
1975 fprintf (file, "\n\n");
1976}