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ffbd18cc 1/* Allocate registers for pseudo-registers that span basic blocks.
2f791da8 2 Copyright (C) 1987, 1988, 1991, 1994, 1996, 1997, 1998,
dfe09cce 3 1999, 2000, 2002 Free Software Foundation, Inc.
ffbd18cc 4
f12b58b3 5This file is part of GCC.
ffbd18cc 6
f12b58b3 7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
ffbd18cc 11
f12b58b3 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
ffbd18cc 16
17You should have received a copy of the GNU General Public License
f12b58b3 18along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
ffbd18cc 21
22
ffbd18cc 23#include "config.h"
405711de 24#include "system.h"
3ef9782d 25
f41a3237 26#include "machmode.h"
27#include "hard-reg-set.h"
ffbd18cc 28#include "rtl.h"
7953c610 29#include "tm_p.h"
ffbd18cc 30#include "flags.h"
31#include "basic-block.h"
ffbd18cc 32#include "regs.h"
0a893c29 33#include "function.h"
ffbd18cc 34#include "insn-config.h"
e94a59c6 35#include "reload.h"
ffbd18cc 36#include "output.h"
ce1fd7fc 37#include "toplev.h"
ffbd18cc 38
39/* This pass of the compiler performs global register allocation.
40 It assigns hard register numbers to all the pseudo registers
41 that were not handled in local_alloc. Assignments are recorded
42 in the vector reg_renumber, not by changing the rtl code.
43 (Such changes are made by final). The entry point is
44 the function global_alloc.
45
46 After allocation is complete, the reload pass is run as a subroutine
47 of this pass, so that when a pseudo reg loses its hard reg due to
48 spilling it is possible to make a second attempt to find a hard
49 reg for it. The reload pass is independent in other respects
50 and it is run even when stupid register allocation is in use.
51
0b6b86e7 52 1. Assign allocation-numbers (allocnos) to the pseudo-registers
53 still needing allocations and to the pseudo-registers currently
54 allocated by local-alloc which may be spilled by reload.
ffbd18cc 55 Set up tables reg_allocno and allocno_reg to map
56 reg numbers to allocnos and vice versa.
57 max_allocno gets the number of allocnos in use.
58
59 2. Allocate a max_allocno by max_allocno conflict bit matrix and clear it.
60 Allocate a max_allocno by FIRST_PSEUDO_REGISTER conflict matrix
61 for conflicts between allocnos and explicit hard register use
62 (which includes use of pseudo-registers allocated by local_alloc).
63
0b6b86e7 64 3. For each basic block
ffbd18cc 65 walk forward through the block, recording which
0b6b86e7 66 pseudo-registers and which hardware registers are live.
67 Build the conflict matrix between the pseudo-registers
68 and another of pseudo-registers versus hardware registers.
ffbd18cc 69 Also record the preferred hardware registers
0b6b86e7 70 for each pseudo-register.
ffbd18cc 71
72 4. Sort a table of the allocnos into order of
73 desirability of the variables.
74
75 5. Allocate the variables in that order; each if possible into
76 a preferred register, else into another register. */
77\f
aa40f561 78/* Number of pseudo-registers which are candidates for allocation. */
ffbd18cc 79
80static int max_allocno;
81
82/* Indexed by (pseudo) reg number, gives the allocno, or -1
0b6b86e7 83 for pseudo registers which are not to be allocated. */
ffbd18cc 84
64ab4a7b 85static int *reg_allocno;
ffbd18cc 86
71b77236 87struct allocno
88{
89 int reg;
90 /* Gives the number of consecutive hard registers needed by that
91 pseudo reg. */
92 int size;
93
94 /* Number of calls crossed by each allocno. */
95 int calls_crossed;
96
63f23608 97 /* Number of refs to each allocno. */
71b77236 98 int n_refs;
99
63f23608 100 /* Frequency of uses of each allocno. */
101 int freq;
102
71b77236 103 /* Guess at live length of each allocno.
104 This is actually the max of the live lengths of the regs. */
105 int live_length;
106
107 /* Set of hard regs conflicting with allocno N. */
108
109 HARD_REG_SET hard_reg_conflicts;
110
111 /* Set of hard regs preferred by allocno N.
112 This is used to make allocnos go into regs that are copied to or from them,
113 when possible, to reduce register shuffling. */
114
115 HARD_REG_SET hard_reg_preferences;
116
117 /* Similar, but just counts register preferences made in simple copy
118 operations, rather than arithmetic. These are given priority because
119 we can always eliminate an insn by using these, but using a register
120 in the above list won't always eliminate an insn. */
ffbd18cc 121
71b77236 122 HARD_REG_SET hard_reg_copy_preferences;
123
124 /* Similar to hard_reg_preferences, but includes bits for subsequent
125 registers when an allocno is multi-word. The above variable is used for
126 allocation while this is used to build reg_someone_prefers, below. */
127
128 HARD_REG_SET hard_reg_full_preferences;
129
130 /* Set of hard registers that some later allocno has a preference for. */
131
132 HARD_REG_SET regs_someone_prefers;
133};
134
135static struct allocno *allocno;
ffbd18cc 136
137/* A vector of the integers from 0 to max_allocno-1,
138 sorted in the order of first-to-be-allocated first. */
139
140static int *allocno_order;
141
ffbd18cc 142/* Indexed by (pseudo) reg number, gives the number of another
4bbea254 143 lower-numbered pseudo reg which can share a hard reg with this pseudo
ffbd18cc 144 *even if the two pseudos would otherwise appear to conflict*. */
145
146static int *reg_may_share;
147
50b0c9ee 148/* Define the number of bits in each element of `conflicts' and what
149 type that element has. We use the largest integer format on the
150 host machine. */
151
152#define INT_BITS HOST_BITS_PER_WIDE_INT
153#define INT_TYPE HOST_WIDE_INT
154
ffbd18cc 155/* max_allocno by max_allocno array of bits,
156 recording whether two allocno's conflict (can't go in the same
157 hardware register).
158
51bc0ccc 159 `conflicts' is symmetric after the call to mirror_conflicts. */
ffbd18cc 160
50b0c9ee 161static INT_TYPE *conflicts;
ffbd18cc 162
163/* Number of ints require to hold max_allocno bits.
164 This is the length of a row in `conflicts'. */
165
166static int allocno_row_words;
167
168/* Two macros to test or store 1 in an element of `conflicts'. */
169
170#define CONFLICTP(I, J) \
dfe09cce 171 (conflicts[(I) * allocno_row_words + (unsigned) (J) / INT_BITS] \
172 & ((INT_TYPE) 1 << ((unsigned) (J) % INT_BITS)))
ffbd18cc 173
174#define SET_CONFLICT(I, J) \
dfe09cce 175 (conflicts[(I) * allocno_row_words + (unsigned) (J) / INT_BITS] \
176 |= ((INT_TYPE) 1 << ((unsigned) (J) % INT_BITS)))
51bc0ccc 177
1f45e4d5 178/* For any allocno set in ALLOCNO_SET, set ALLOCNO to that allocno,
179 and execute CODE. */
180#define EXECUTE_IF_SET_IN_ALLOCNO_SET(ALLOCNO_SET, ALLOCNO, CODE) \
181do { \
182 int i_; \
183 int allocno_; \
71b77236 184 INT_TYPE *p_ = (ALLOCNO_SET); \
1f45e4d5 185 \
186 for (i_ = allocno_row_words - 1, allocno_ = 0; i_ >= 0; \
187 i_--, allocno_ += INT_BITS) \
188 { \
189 unsigned INT_TYPE word_ = (unsigned INT_TYPE) *p_++; \
190 \
191 for ((ALLOCNO) = allocno_; word_; word_ >>= 1, (ALLOCNO)++) \
192 { \
193 if (word_ & 1) \
c74159a4 194 {CODE;} \
1f45e4d5 195 } \
196 } \
197} while (0)
198
8c278a57 199/* This doesn't work for non-GNU C due to the way CODE is macro expanded. */
200#if 0
1f45e4d5 201/* For any allocno that conflicts with IN_ALLOCNO, set OUT_ALLOCNO to
202 the conflicting allocno, and execute CODE. This macro assumes that
203 mirror_conflicts has been run. */
204#define EXECUTE_IF_CONFLICT(IN_ALLOCNO, OUT_ALLOCNO, CODE)\
205 EXECUTE_IF_SET_IN_ALLOCNO_SET (conflicts + (IN_ALLOCNO) * allocno_row_words,\
c74159a4 206 OUT_ALLOCNO, (CODE))
8c278a57 207#endif
1f45e4d5 208
ffbd18cc 209/* Set of hard regs currently live (during scan of all insns). */
210
211static HARD_REG_SET hard_regs_live;
212
ffbd18cc 213/* Set of registers that global-alloc isn't supposed to use. */
214
215static HARD_REG_SET no_global_alloc_regs;
216
217/* Set of registers used so far. */
218
219static HARD_REG_SET regs_used_so_far;
220
63f23608 221/* Number of refs to each hard reg, as used by local alloc.
05f2333b 222 It is zero for a reg that contains global pseudos or is explicitly used. */
223
224static int local_reg_n_refs[FIRST_PSEUDO_REGISTER];
225
63f23608 226/* Frequency of uses of given hard reg. */
227static int local_reg_freq[FIRST_PSEUDO_REGISTER];
228
05f2333b 229/* Guess at live length of each hard reg, as used by local alloc.
230 This is actually the sum of the live lengths of the specific regs. */
231
232static int local_reg_live_length[FIRST_PSEUDO_REGISTER];
233
ffbd18cc 234/* Test a bit in TABLE, a vector of HARD_REG_SETs,
235 for vector element I, and hard register number J. */
236
71b77236 237#define REGBITP(TABLE, I, J) TEST_HARD_REG_BIT (allocno[I].TABLE, J)
ffbd18cc 238
239/* Set to 1 a bit in a vector of HARD_REG_SETs. Works like REGBITP. */
240
71b77236 241#define SET_REGBIT(TABLE, I, J) SET_HARD_REG_BIT (allocno[I].TABLE, J)
ffbd18cc 242
243/* Bit mask for allocnos live at current point in the scan. */
244
50b0c9ee 245static INT_TYPE *allocnos_live;
ffbd18cc 246
247/* Test, set or clear bit number I in allocnos_live,
248 a bit vector indexed by allocno. */
249
1f45e4d5 250#define ALLOCNO_LIVE_P(I) \
dfe09cce 251 (allocnos_live[(unsigned) (I) / INT_BITS] \
252 & ((INT_TYPE) 1 << ((unsigned) (I) % INT_BITS)))
ffbd18cc 253
1f45e4d5 254#define SET_ALLOCNO_LIVE(I) \
dfe09cce 255 (allocnos_live[(unsigned) (I) / INT_BITS] \
256 |= ((INT_TYPE) 1 << ((unsigned) (I) % INT_BITS)))
ffbd18cc 257
1f45e4d5 258#define CLEAR_ALLOCNO_LIVE(I) \
dfe09cce 259 (allocnos_live[(unsigned) (I) / INT_BITS] \
260 &= ~((INT_TYPE) 1 << ((unsigned) (I) % INT_BITS)))
ffbd18cc 261
262/* This is turned off because it doesn't work right for DImode.
263 (And it is only used for DImode, so the other cases are worthless.)
264 The problem is that it isn't true that there is NO possibility of conflict;
265 only that there is no conflict if the two pseudos get the exact same regs.
266 If they were allocated with a partial overlap, there would be a conflict.
267 We can't safely turn off the conflict unless we have another way to
268 prevent the partial overlap.
269
270 Idea: change hard_reg_conflicts so that instead of recording which
271 hard regs the allocno may not overlap, it records where the allocno
272 may not start. Change both where it is used and where it is updated.
273 Then there is a way to record that (reg:DI 108) may start at 10
274 but not at 9 or 11. There is still the question of how to record
275 this semi-conflict between two pseudos. */
276#if 0
277/* Reg pairs for which conflict after the current insn
278 is inhibited by a REG_NO_CONFLICT note.
279 If the table gets full, we ignore any other notes--that is conservative. */
280#define NUM_NO_CONFLICT_PAIRS 4
281/* Number of pairs in use in this insn. */
282int n_no_conflict_pairs;
283static struct { int allocno1, allocno2;}
284 no_conflict_pairs[NUM_NO_CONFLICT_PAIRS];
285#endif /* 0 */
286
287/* Record all regs that are set in any one insn.
288 Communication from mark_reg_{store,clobber} and global_conflicts. */
289
290static rtx *regs_set;
291static int n_regs_set;
292
d55c71c6 293/* All registers that can be eliminated. */
ffbd18cc 294
295static HARD_REG_SET eliminable_regset;
296
38b9004f 297static int allocno_compare PARAMS ((const PTR, const PTR));
298static void global_conflicts PARAMS ((void));
299static void mirror_conflicts PARAMS ((void));
300static void expand_preferences PARAMS ((void));
301static void prune_preferences PARAMS ((void));
302static void find_reg PARAMS ((int, HARD_REG_SET, int, int, int));
303static void record_one_conflict PARAMS ((int));
304static void record_conflicts PARAMS ((int *, int));
305static void mark_reg_store PARAMS ((rtx, rtx, void *));
306static void mark_reg_clobber PARAMS ((rtx, rtx, void *));
307static void mark_reg_conflicts PARAMS ((rtx));
308static void mark_reg_death PARAMS ((rtx));
309static void mark_reg_live_nc PARAMS ((int, enum machine_mode));
310static void set_preference PARAMS ((rtx, rtx));
311static void dump_conflicts PARAMS ((FILE *));
312static void reg_becomes_live PARAMS ((rtx, rtx, void *));
313static void reg_dies PARAMS ((int, enum machine_mode,
a570a59f 314 struct insn_chain *));
ffbd18cc 315\f
316/* Perform allocation of pseudo-registers not allocated by local_alloc.
317 FILE is a file to output debugging information on,
5aaac310 318 or zero if such output is not desired.
ffbd18cc 319
5aaac310 320 Return value is nonzero if reload failed
321 and we must not do any more for this function. */
322
323int
ffbd18cc 324global_alloc (file)
325 FILE *file;
326{
d561366f 327 int retval;
ffbd18cc 328#ifdef ELIMINABLE_REGS
e99c3a1d 329 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
ffbd18cc 330#endif
d55c71c6 331 int need_fp
332 = (! flag_omit_frame_pointer
333#ifdef EXIT_IGNORE_STACK
334 || (current_function_calls_alloca && EXIT_IGNORE_STACK)
335#endif
336 || FRAME_POINTER_REQUIRED);
337
19cb6b50 338 size_t i;
ffbd18cc 339 rtx x;
340
341 max_allocno = 0;
342
343 /* A machine may have certain hard registers that
344 are safe to use only within a basic block. */
345
346 CLEAR_HARD_REG_SET (no_global_alloc_regs);
ffbd18cc 347
348 /* Build the regset of all eliminable registers and show we can't use those
349 that we already know won't be eliminated. */
350#ifdef ELIMINABLE_REGS
3098b2d3 351 for (i = 0; i < ARRAY_SIZE (eliminables); i++)
ffbd18cc 352 {
353 SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from);
354
355 if (! CAN_ELIMINATE (eliminables[i].from, eliminables[i].to)
d55c71c6 356 || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp))
ffbd18cc 357 SET_HARD_REG_BIT (no_global_alloc_regs, eliminables[i].from);
358 }
60718504 359#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
d55c71c6 360 SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM);
361 if (need_fp)
60718504 362 SET_HARD_REG_BIT (no_global_alloc_regs, HARD_FRAME_POINTER_REGNUM);
363#endif
d55c71c6 364
ffbd18cc 365#else
366 SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM);
d55c71c6 367 if (need_fp)
ffbd18cc 368 SET_HARD_REG_BIT (no_global_alloc_regs, FRAME_POINTER_REGNUM);
369#endif
370
371 /* Track which registers have already been used. Start with registers
372 explicitly in the rtl, then registers allocated by local register
9ebcdd59 373 allocation. */
ffbd18cc 374
375 CLEAR_HARD_REG_SET (regs_used_so_far);
9ebcdd59 376#ifdef LEAF_REGISTERS
377 /* If we are doing the leaf function optimization, and this is a leaf
378 function, it means that the registers that take work to save are those
379 that need a register window. So prefer the ones that can be used in
380 a leaf function. */
381 {
382 char *cheap_regs;
7a8d641b 383 char *leaf_regs = LEAF_REGISTERS;
9ebcdd59 384
385 if (only_leaf_regs_used () && leaf_function_p ())
386 cheap_regs = leaf_regs;
387 else
388 cheap_regs = call_used_regs;
389 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
390 if (regs_ever_live[i] || cheap_regs[i])
391 SET_HARD_REG_BIT (regs_used_so_far, i);
392 }
393#else
394 /* We consider registers that do not have to be saved over calls as if
395 they were already used since there is no cost in using them. */
ffbd18cc 396 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
397 if (regs_ever_live[i] || call_used_regs[i])
398 SET_HARD_REG_BIT (regs_used_so_far, i);
9ebcdd59 399#endif
ffbd18cc 400
274c11d8 401 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
ffbd18cc 402 if (reg_renumber[i] >= 0)
403 SET_HARD_REG_BIT (regs_used_so_far, reg_renumber[i]);
404
405 /* Establish mappings from register number to allocation number
406 and vice versa. In the process, count the allocnos. */
407
8b861be4 408 reg_allocno = (int *) xmalloc (max_regno * sizeof (int));
ffbd18cc 409
410 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
411 reg_allocno[i] = -1;
412
413 /* Initialize the shared-hard-reg mapping
414 from the list of pairs that may share. */
8b861be4 415 reg_may_share = (int *) xcalloc (max_regno, sizeof (int));
ffbd18cc 416 for (x = regs_may_share; x; x = XEXP (XEXP (x, 1), 1))
417 {
418 int r1 = REGNO (XEXP (x, 0));
419 int r2 = REGNO (XEXP (XEXP (x, 1), 0));
420 if (r1 > r2)
421 reg_may_share[r1] = r2;
422 else
423 reg_may_share[r2] = r1;
424 }
425
274c11d8 426 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
ffbd18cc 427 /* Note that reg_live_length[i] < 0 indicates a "constant" reg
428 that we are supposed to refrain from putting in a hard reg.
429 -2 means do make an allocno but don't allocate it. */
0b6b86e7 430 if (REG_N_REFS (i) != 0 && REG_LIVE_LENGTH (i) != -1
ffbd18cc 431 /* Don't allocate pseudos that cross calls,
432 if this function receives a nonlocal goto. */
433 && (! current_function_has_nonlocal_label
394685a4 434 || REG_N_CALLS_CROSSED (i) == 0))
ffbd18cc 435 {
0b6b86e7 436 if (reg_renumber[i] < 0 && reg_may_share[i] && reg_allocno[reg_may_share[i]] >= 0)
ffbd18cc 437 reg_allocno[i] = reg_allocno[reg_may_share[i]];
438 else
439 reg_allocno[i] = max_allocno++;
394685a4 440 if (REG_LIVE_LENGTH (i) == 0)
ffbd18cc 441 abort ();
442 }
443 else
444 reg_allocno[i] = -1;
445
71b77236 446 allocno = (struct allocno *) xcalloc (max_allocno, sizeof (struct allocno));
ffbd18cc 447
274c11d8 448 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
ffbd18cc 449 if (reg_allocno[i] >= 0)
450 {
71b77236 451 int num = reg_allocno[i];
452 allocno[num].reg = i;
453 allocno[num].size = PSEUDO_REGNO_SIZE (i);
454 allocno[num].calls_crossed += REG_N_CALLS_CROSSED (i);
455 allocno[num].n_refs += REG_N_REFS (i);
63f23608 456 allocno[num].freq += REG_FREQ (i);
71b77236 457 if (allocno[num].live_length < REG_LIVE_LENGTH (i))
458 allocno[num].live_length = REG_LIVE_LENGTH (i);
ffbd18cc 459 }
460
05f2333b 461 /* Calculate amount of usage of each hard reg by pseudos
462 allocated by local-alloc. This is to see if we want to
463 override it. */
93d3b7de 464 memset ((char *) local_reg_live_length, 0, sizeof local_reg_live_length);
465 memset ((char *) local_reg_n_refs, 0, sizeof local_reg_n_refs);
63f23608 466 memset ((char *) local_reg_freq, 0, sizeof local_reg_freq);
274c11d8 467 for (i = FIRST_PSEUDO_REGISTER; i < (size_t) max_regno; i++)
0b6b86e7 468 if (reg_renumber[i] >= 0)
05f2333b 469 {
3b1a9578 470 int regno = reg_renumber[i];
471 int endregno = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
472 int j;
473
474 for (j = regno; j < endregno; j++)
475 {
394685a4 476 local_reg_n_refs[j] += REG_N_REFS (i);
63f23608 477 local_reg_freq[j] += REG_FREQ (i);
394685a4 478 local_reg_live_length[j] += REG_LIVE_LENGTH (i);
3b1a9578 479 }
05f2333b 480 }
3b1a9578 481
05f2333b 482 /* We can't override local-alloc for a reg used not just by local-alloc. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 if (regs_ever_live[i])
63f23608 485 local_reg_n_refs[i] = 0, local_reg_freq[i] = 0;
9e682813 486
ffbd18cc 487 allocno_row_words = (max_allocno + INT_BITS - 1) / INT_BITS;
488
46142c2d 489 /* We used to use alloca here, but the size of what it would try to
490 allocate would occasionally cause it to exceed the stack limit and
491 cause unpredictable core dumps. Some examples were > 2Mb in size. */
a559f7c8 492 conflicts = (INT_TYPE *) xcalloc (max_allocno * allocno_row_words,
493 sizeof (INT_TYPE));
ffbd18cc 494
8b861be4 495 allocnos_live = (INT_TYPE *) xmalloc (allocno_row_words * sizeof (INT_TYPE));
ffbd18cc 496
497 /* If there is work to be done (at least one reg to allocate),
498 perform global conflict analysis and allocate the regs. */
499
500 if (max_allocno > 0)
501 {
502 /* Scan all the insns and compute the conflicts among allocnos
503 and between allocnos and hard regs. */
504
505 global_conflicts ();
506
51bc0ccc 507 mirror_conflicts ();
508
ffbd18cc 509 /* Eliminate conflicts between pseudos and eliminable registers. If
510 the register is not eliminated, the pseudo won't really be able to
511 live in the eliminable register, so the conflict doesn't matter.
512 If we do eliminate the register, the conflict will no longer exist.
05f2333b 513 So in either case, we can ignore the conflict. Likewise for
514 preferences. */
ffbd18cc 515
274c11d8 516 for (i = 0; i < (size_t) max_allocno; i++)
05f2333b 517 {
71b77236 518 AND_COMPL_HARD_REG_SET (allocno[i].hard_reg_conflicts,
519 eliminable_regset);
520 AND_COMPL_HARD_REG_SET (allocno[i].hard_reg_copy_preferences,
521 eliminable_regset);
522 AND_COMPL_HARD_REG_SET (allocno[i].hard_reg_preferences,
05f2333b 523 eliminable_regset);
05f2333b 524 }
ffbd18cc 525
526 /* Try to expand the preferences by merging them between allocnos. */
527
528 expand_preferences ();
529
530 /* Determine the order to allocate the remaining pseudo registers. */
531
8b861be4 532 allocno_order = (int *) xmalloc (max_allocno * sizeof (int));
274c11d8 533 for (i = 0; i < (size_t) max_allocno; i++)
ffbd18cc 534 allocno_order[i] = i;
535
536 /* Default the size to 1, since allocno_compare uses it to divide by.
537 Also convert allocno_live_length of zero to -1. A length of zero
538 can occur when all the registers for that allocno have reg_live_length
539 equal to -2. In this case, we want to make an allocno, but not
540 allocate it. So avoid the divide-by-zero and set it to a low
541 priority. */
542
274c11d8 543 for (i = 0; i < (size_t) max_allocno; i++)
ffbd18cc 544 {
71b77236 545 if (allocno[i].size == 0)
546 allocno[i].size = 1;
547 if (allocno[i].live_length == 0)
548 allocno[i].live_length = -1;
ffbd18cc 549 }
550
551 qsort (allocno_order, max_allocno, sizeof (int), allocno_compare);
552
553 prune_preferences ();
554
555 if (file)
556 dump_conflicts (file);
557
558 /* Try allocating them, one by one, in that order,
559 except for parameters marked with reg_live_length[regno] == -2. */
560
274c11d8 561 for (i = 0; i < (size_t) max_allocno; i++)
71b77236 562 if (reg_renumber[allocno[allocno_order[i]].reg] < 0
563 && REG_LIVE_LENGTH (allocno[allocno_order[i]].reg) >= 0)
ffbd18cc 564 {
565 /* If we have more than one register class,
566 first try allocating in the class that is cheapest
567 for this pseudo-reg. If that fails, try any reg. */
568 if (N_REG_CLASSES > 1)
569 {
bd09ab5d 570 find_reg (allocno_order[i], 0, 0, 0, 0);
71b77236 571 if (reg_renumber[allocno[allocno_order[i]].reg] >= 0)
ffbd18cc 572 continue;
573 }
71b77236 574 if (reg_alternate_class (allocno[allocno_order[i]].reg) != NO_REGS)
bd09ab5d 575 find_reg (allocno_order[i], 0, 1, 0, 0);
ffbd18cc 576 }
8b861be4 577
578 free (allocno_order);
ffbd18cc 579 }
580
581 /* Do the reloads now while the allocno data still exist, so that we can
582 try to assign new hard regs to any pseudo regs that are spilled. */
583
a6ce2572 584#if 0 /* We need to eliminate regs even if there is no rtl code,
585 for the sake of debugging information. */
ffbd18cc 586 if (n_basic_blocks > 0)
a6ce2572 587#endif
e94a59c6 588 {
6f5c3acb 589 build_insn_chain (get_insns ());
bfd0ee98 590 retval = reload (get_insns (), 1);
e94a59c6 591 }
d561366f 592
8b861be4 593 /* Clean up. */
594 free (reg_allocno);
595 free (reg_may_share);
71b77236 596 free (allocno);
d561366f 597 free (conflicts);
8b861be4 598 free (allocnos_live);
599
d561366f 600 return retval;
ffbd18cc 601}
602
603/* Sort predicate for ordering the allocnos.
604 Returns -1 (1) if *v1 should be allocated before (after) *v2. */
605
606static int
de27a084 607allocno_compare (v1p, v2p)
9520c8bb 608 const PTR v1p;
609 const PTR v2p;
ffbd18cc 610{
20f0a040 611 int v1 = *(const int *)v1p, v2 = *(const int *)v2p;
ffbd18cc 612 /* Note that the quotient will never be bigger than
613 the value of floor_log2 times the maximum number of
eefdec48 614 times a register can occur in one insn (surely less than 100)
615 weighted by the frequency (maximally REG_FREQ_MAX).
616 Multiplying this by 10000/REG_FREQ_MAX can't overflow. */
19cb6b50 617 int pri1
63f23608 618 = (((double) (floor_log2 (allocno[v1].n_refs) * allocno[v1].freq)
71b77236 619 / allocno[v1].live_length)
eefdec48 620 * (10000 / REG_FREQ_MAX) * allocno[v1].size);
19cb6b50 621 int pri2
63f23608 622 = (((double) (floor_log2 (allocno[v2].n_refs) * allocno[v2].freq)
71b77236 623 / allocno[v2].live_length)
eefdec48 624 * (10000 / REG_FREQ_MAX) * allocno[v2].size);
ffbd18cc 625 if (pri2 - pri1)
626 return pri2 - pri1;
627
628 /* If regs are equally good, sort by allocno,
629 so that the results of qsort leave nothing to chance. */
de27a084 630 return v1 - v2;
ffbd18cc 631}
632\f
633/* Scan the rtl code and record all conflicts and register preferences in the
634 conflict matrices and preference tables. */
635
636static void
637global_conflicts ()
638{
19cb6b50 639 int b, i;
640 rtx insn;
75fa5dae 641 int *block_start_allocnos;
ffbd18cc 642
643 /* Make a vector that mark_reg_{store,clobber} will store in. */
8b861be4 644 regs_set = (rtx *) xmalloc (max_parallel * sizeof (rtx) * 2);
ffbd18cc 645
8b861be4 646 block_start_allocnos = (int *) xmalloc (max_allocno * sizeof (int));
ffbd18cc 647
648 for (b = 0; b < n_basic_blocks; b++)
649 {
93d3b7de 650 memset ((char *) allocnos_live, 0, allocno_row_words * sizeof (INT_TYPE));
ffbd18cc 651
652 /* Initialize table of registers currently live
653 to the state at the beginning of this basic block.
60f19080 654 This also marks the conflicts among hard registers
655 and any allocnos that are live.
ffbd18cc 656
657 For pseudo-regs, there is only one bit for each one
658 no matter how many hard regs it occupies.
659 This is ok; we know the size from PSEUDO_REGNO_SIZE.
660 For explicit hard regs, we cannot know the size that way
661 since one hard reg can be used with various sizes.
662 Therefore, we must require that all the hard regs
663 implicitly live as part of a multi-word hard reg
664 are explicitly marked in basic_block_live_at_start. */
665
666 {
19cb6b50 667 regset old = BASIC_BLOCK (b)->global_live_at_start;
ffbd18cc 668 int ax = 0;
669
74666a14 670 REG_SET_TO_HARD_REG_SET (hard_regs_live, old);
31df18a3 671 EXECUTE_IF_SET_IN_REG_SET (old, FIRST_PSEUDO_REGISTER, i,
74666a14 672 {
19cb6b50 673 int a = reg_allocno[i];
74666a14 674 if (a >= 0)
675 {
676 SET_ALLOCNO_LIVE (a);
677 block_start_allocnos[ax++] = a;
678 }
679 else if ((a = reg_renumber[i]) >= 0)
31df18a3 680 mark_reg_live_nc
681 (a, PSEUDO_REGNO_MODE (i));
74666a14 682 });
ffbd18cc 683
60f19080 684 /* Record that each allocno now live conflicts with each hard reg
685 now live.
ffbd18cc 686
60f19080 687 It is not necessary to mark any conflicts between pseudos as
688 this point, even for pseudos which are live at the start of
689 the basic block.
690
691 Given two pseudos X and Y and any point in the CFG P.
692
693 On any path to point P where X and Y are live one of the
694 following conditions must be true:
695
696 1. X is live at some instruction on the path that
697 evaluates Y.
698
699 2. Y is live at some instruction on the path that
700 evaluates X.
701
702 3. Either X or Y is not evaluted on the path to P
703 (ie it is used uninitialized) and thus the
704 conflict can be ignored.
705
706 In cases #1 and #2 the conflict will be recorded when we
707 scan the instruction that makes either X or Y become live. */
ffbd18cc 708 record_conflicts (block_start_allocnos, ax);
f24e9d92 709
710#ifdef STACK_REGS
71caadc0 711 {
712 /* Pseudos can't go in stack regs at the start of a basic block
f3d96a58 713 that is reached by an abnormal edge. */
71caadc0 714
715 edge e;
716 for (e = BASIC_BLOCK (b)->pred; e ; e = e->pred_next)
717 if (e->flags & EDGE_ABNORMAL)
718 break;
71caadc0 719 if (e != NULL)
720 for (ax = FIRST_STACK_REG; ax <= LAST_STACK_REG; ax++)
721 record_one_conflict (ax);
722 }
f24e9d92 723#endif
ffbd18cc 724 }
725
68676d00 726 insn = BLOCK_HEAD (b);
ffbd18cc 727
728 /* Scan the code of this basic block, noting which allocnos
729 and hard regs are born or die. When one is born,
730 record a conflict with all others currently live. */
731
732 while (1)
733 {
19cb6b50 734 RTX_CODE code = GET_CODE (insn);
735 rtx link;
ffbd18cc 736
737 /* Make regs_set an empty set. */
738
739 n_regs_set = 0;
740
741 if (code == INSN || code == CALL_INSN || code == JUMP_INSN)
742 {
ffbd18cc 743
744#if 0
ab9d0fcb 745 int i = 0;
ffbd18cc 746 for (link = REG_NOTES (insn);
747 link && i < NUM_NO_CONFLICT_PAIRS;
748 link = XEXP (link, 1))
749 if (REG_NOTE_KIND (link) == REG_NO_CONFLICT)
750 {
751 no_conflict_pairs[i].allocno1
752 = reg_allocno[REGNO (SET_DEST (PATTERN (insn)))];
753 no_conflict_pairs[i].allocno2
754 = reg_allocno[REGNO (XEXP (link, 0))];
755 i++;
756 }
757#endif /* 0 */
758
759 /* Mark any registers clobbered by INSN as live,
760 so they conflict with the inputs. */
761
ec8895d7 762 note_stores (PATTERN (insn), mark_reg_clobber, NULL);
ffbd18cc 763
764 /* Mark any registers dead after INSN as dead now. */
765
766 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
767 if (REG_NOTE_KIND (link) == REG_DEAD)
768 mark_reg_death (XEXP (link, 0));
769
770 /* Mark any registers set in INSN as live,
771 and mark them as conflicting with all other live regs.
772 Clobbers are processed again, so they conflict with
773 the registers that are set. */
774
ec8895d7 775 note_stores (PATTERN (insn), mark_reg_store, NULL);
ffbd18cc 776
777#ifdef AUTO_INC_DEC
778 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
779 if (REG_NOTE_KIND (link) == REG_INC)
ec8895d7 780 mark_reg_store (XEXP (link, 0), NULL_RTX, NULL);
ffbd18cc 781#endif
782
eea407a7 783 /* If INSN has multiple outputs, then any reg that dies here
784 and is used inside of an output
e6cae665 785 must conflict with the other outputs.
786
787 It is unsafe to use !single_set here since it will ignore an
788 unused output. Just because an output is unused does not mean
789 the compiler can assume the side effect will not occur.
790 Consider if REG appears in the address of an output and we
791 reload the output. If we allocate REG to the same hard
792 register as an unused output we could set the hard register
793 before the output reload insn. */
794 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
eea407a7 795 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
796 if (REG_NOTE_KIND (link) == REG_DEAD)
797 {
798 int used_in_output = 0;
799 int i;
800 rtx reg = XEXP (link, 0);
801
802 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
803 {
804 rtx set = XVECEXP (PATTERN (insn), 0, i);
805 if (GET_CODE (set) == SET
806 && GET_CODE (SET_DEST (set)) != REG
807 && !rtx_equal_p (reg, SET_DEST (set))
808 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
809 used_in_output = 1;
810 }
811 if (used_in_output)
812 mark_reg_conflicts (reg);
813 }
814
ffbd18cc 815 /* Mark any registers set in INSN and then never used. */
816
34c8a8c1 817 while (n_regs_set-- > 0)
818 {
819 rtx note = find_regno_note (insn, REG_UNUSED,
820 REGNO (regs_set[n_regs_set]));
821 if (note)
822 mark_reg_death (XEXP (note, 0));
823 }
ffbd18cc 824 }
825
68676d00 826 if (insn == BLOCK_END (b))
ffbd18cc 827 break;
828 insn = NEXT_INSN (insn);
829 }
830 }
8b861be4 831
832 /* Clean up. */
833 free (block_start_allocnos);
834 free (regs_set);
ffbd18cc 835}
836/* Expand the preference information by looking for cases where one allocno
837 dies in an insn that sets an allocno. If those two allocnos don't conflict,
838 merge any preferences between those allocnos. */
839
840static void
841expand_preferences ()
842{
843 rtx insn;
844 rtx link;
845 rtx set;
846
847 /* We only try to handle the most common cases here. Most of the cases
848 where this wins are reg-reg copies. */
849
850 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9204e736 851 if (INSN_P (insn)
ffbd18cc 852 && (set = single_set (insn)) != 0
853 && GET_CODE (SET_DEST (set)) == REG
854 && reg_allocno[REGNO (SET_DEST (set))] >= 0)
855 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
856 if (REG_NOTE_KIND (link) == REG_DEAD
857 && GET_CODE (XEXP (link, 0)) == REG
858 && reg_allocno[REGNO (XEXP (link, 0))] >= 0
859 && ! CONFLICTP (reg_allocno[REGNO (SET_DEST (set))],
51bc0ccc 860 reg_allocno[REGNO (XEXP (link, 0))]))
ffbd18cc 861 {
862 int a1 = reg_allocno[REGNO (SET_DEST (set))];
863 int a2 = reg_allocno[REGNO (XEXP (link, 0))];
864
865 if (XEXP (link, 0) == SET_SRC (set))
866 {
71b77236 867 IOR_HARD_REG_SET (allocno[a1].hard_reg_copy_preferences,
868 allocno[a2].hard_reg_copy_preferences);
869 IOR_HARD_REG_SET (allocno[a2].hard_reg_copy_preferences,
870 allocno[a1].hard_reg_copy_preferences);
ffbd18cc 871 }
872
71b77236 873 IOR_HARD_REG_SET (allocno[a1].hard_reg_preferences,
874 allocno[a2].hard_reg_preferences);
875 IOR_HARD_REG_SET (allocno[a2].hard_reg_preferences,
876 allocno[a1].hard_reg_preferences);
877 IOR_HARD_REG_SET (allocno[a1].hard_reg_full_preferences,
878 allocno[a2].hard_reg_full_preferences);
879 IOR_HARD_REG_SET (allocno[a2].hard_reg_full_preferences,
880 allocno[a1].hard_reg_full_preferences);
ffbd18cc 881 }
882}
883\f
884/* Prune the preferences for global registers to exclude registers that cannot
885 be used.
886
887 Compute `regs_someone_prefers', which is a bitmask of the hard registers
888 that are preferred by conflicting registers of lower priority. If possible,
889 we will avoid using these registers. */
890
891static void
892prune_preferences ()
893{
1f45e4d5 894 int i;
71b77236 895 int num;
51bc0ccc 896 int *allocno_to_order = (int *) xmalloc (max_allocno * sizeof (int));
ffbd18cc 897
898 /* Scan least most important to most important.
899 For each allocno, remove from preferences registers that cannot be used,
900 either because of conflicts or register type. Then compute all registers
f9e15121 901 preferred by each lower-priority register that conflicts. */
ffbd18cc 902
903 for (i = max_allocno - 1; i >= 0; i--)
904 {
51bc0ccc 905 HARD_REG_SET temp;
ffbd18cc 906
71b77236 907 num = allocno_order[i];
908 allocno_to_order[num] = i;
909 COPY_HARD_REG_SET (temp, allocno[num].hard_reg_conflicts);
ffbd18cc 910
71b77236 911 if (allocno[num].calls_crossed == 0)
ffbd18cc 912 IOR_HARD_REG_SET (temp, fixed_reg_set);
913 else
914 IOR_HARD_REG_SET (temp, call_used_reg_set);
915
916 IOR_COMPL_HARD_REG_SET
917 (temp,
71b77236 918 reg_class_contents[(int) reg_preferred_class (allocno[num].reg)]);
ffbd18cc 919
71b77236 920 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_preferences, temp);
921 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_copy_preferences, temp);
922 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_full_preferences, temp);
51bc0ccc 923 }
ffbd18cc 924
51bc0ccc 925 for (i = max_allocno - 1; i >= 0; i--)
926 {
ffbd18cc 927 /* Merge in the preferences of lower-priority registers (they have
928 already been pruned). If we also prefer some of those registers,
929 don't exclude them unless we are of a smaller size (in which case
930 we want to give the lower-priority allocno the first chance for
931 these registers). */
51bc0ccc 932 HARD_REG_SET temp, temp2;
1f45e4d5 933 int allocno2;
51bc0ccc 934
71b77236 935 num = allocno_order[i];
51bc0ccc 936
15065cea 937 CLEAR_HARD_REG_SET (temp);
938 CLEAR_HARD_REG_SET (temp2);
51bc0ccc 939
71b77236 940 EXECUTE_IF_SET_IN_ALLOCNO_SET (conflicts + num * allocno_row_words,
8c278a57 941 allocno2,
51bc0ccc 942 {
1f45e4d5 943 if (allocno_to_order[allocno2] > i)
51bc0ccc 944 {
71b77236 945 if (allocno[allocno2].size <= allocno[num].size)
946 IOR_HARD_REG_SET (temp,
947 allocno[allocno2].hard_reg_full_preferences);
1f45e4d5 948 else
71b77236 949 IOR_HARD_REG_SET (temp2,
950 allocno[allocno2].hard_reg_full_preferences);
51bc0ccc 951 }
1f45e4d5 952 });
51bc0ccc 953
71b77236 954 AND_COMPL_HARD_REG_SET (temp, allocno[num].hard_reg_full_preferences);
15065cea 955 IOR_HARD_REG_SET (temp, temp2);
71b77236 956 COPY_HARD_REG_SET (allocno[num].regs_someone_prefers, temp);
ffbd18cc 957 }
51bc0ccc 958 free (allocno_to_order);
ffbd18cc 959}
960\f
71b77236 961/* Assign a hard register to allocno NUM; look for one that is the beginning
ffbd18cc 962 of a long enough stretch of hard regs none of which conflicts with ALLOCNO.
963 The registers marked in PREFREGS are tried first.
964
965 LOSERS, if non-zero, is a HARD_REG_SET indicating registers that cannot
966 be used for this allocation.
967
50b0c9ee 968 If ALT_REGS_P is zero, consider only the preferred class of ALLOCNO's reg.
969 Otherwise ignore that preferred class and use the alternate class.
ffbd18cc 970
971 If ACCEPT_CALL_CLOBBERED is nonzero, accept a call-clobbered hard reg that
972 will have to be saved and restored at calls.
973
05f2333b 974 RETRYING is nonzero if this is called from retry_global_alloc.
975
ffbd18cc 976 If we find one, record it in reg_renumber.
977 If not, do nothing. */
978
979static void
71b77236 980find_reg (num, losers, alt_regs_p, accept_call_clobbered, retrying)
981 int num;
ffbd18cc 982 HARD_REG_SET losers;
50b0c9ee 983 int alt_regs_p;
ffbd18cc 984 int accept_call_clobbered;
05f2333b 985 int retrying;
ffbd18cc 986{
19cb6b50 987 int i, best_reg, pass;
ffbd18cc 988#ifdef HARD_REG_SET
989 register /* Declare it register if it's a scalar. */
990#endif
05f2333b 991 HARD_REG_SET used, used1, used2;
ffbd18cc 992
50b0c9ee 993 enum reg_class class = (alt_regs_p
71b77236 994 ? reg_alternate_class (allocno[num].reg)
995 : reg_preferred_class (allocno[num].reg));
996 enum machine_mode mode = PSEUDO_REGNO_MODE (allocno[num].reg);
ffbd18cc 997
998 if (accept_call_clobbered)
999 COPY_HARD_REG_SET (used1, call_fixed_reg_set);
71b77236 1000 else if (allocno[num].calls_crossed == 0)
ffbd18cc 1001 COPY_HARD_REG_SET (used1, fixed_reg_set);
1002 else
1003 COPY_HARD_REG_SET (used1, call_used_reg_set);
1004
1005 /* Some registers should not be allocated in global-alloc. */
1006 IOR_HARD_REG_SET (used1, no_global_alloc_regs);
1007 if (losers)
1008 IOR_HARD_REG_SET (used1, losers);
1009
1010 IOR_COMPL_HARD_REG_SET (used1, reg_class_contents[(int) class]);
05f2333b 1011 COPY_HARD_REG_SET (used2, used1);
1012
71b77236 1013 IOR_HARD_REG_SET (used1, allocno[num].hard_reg_conflicts);
ffbd18cc 1014
c5af420e 1015#ifdef CLASS_CANNOT_CHANGE_MODE
1016 if (REG_CHANGES_MODE (allocno[num].reg))
7fbbfd4a 1017 IOR_HARD_REG_SET (used1,
c5af420e 1018 reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
7fbbfd4a 1019#endif
1020
ffbd18cc 1021 /* Try each hard reg to see if it fits. Do this in two passes.
f9e15121 1022 In the first pass, skip registers that are preferred by some other pseudo
ffbd18cc 1023 to give it a better chance of getting one of those registers. Only if
1024 we can't get a register when excluding those do we take one of them.
1025 However, we never allocate a register for the first time in pass 0. */
1026
1027 COPY_HARD_REG_SET (used, used1);
1028 IOR_COMPL_HARD_REG_SET (used, regs_used_so_far);
71b77236 1029 IOR_HARD_REG_SET (used, allocno[num].regs_someone_prefers);
ffbd18cc 1030
1031 best_reg = -1;
1032 for (i = FIRST_PSEUDO_REGISTER, pass = 0;
1033 pass <= 1 && i >= FIRST_PSEUDO_REGISTER;
1034 pass++)
1035 {
1036 if (pass == 1)
1037 COPY_HARD_REG_SET (used, used1);
1038 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1039 {
1040#ifdef REG_ALLOC_ORDER
1041 int regno = reg_alloc_order[i];
1042#else
1043 int regno = i;
1044#endif
1045 if (! TEST_HARD_REG_BIT (used, regno)
fc51ca3b 1046 && HARD_REGNO_MODE_OK (regno, mode)
71b77236 1047 && (allocno[num].calls_crossed == 0
fc51ca3b 1048 || accept_call_clobbered
1049 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
ffbd18cc 1050 {
19cb6b50 1051 int j;
1052 int lim = regno + HARD_REGNO_NREGS (regno, mode);
ffbd18cc 1053 for (j = regno + 1;
1054 (j < lim
1055 && ! TEST_HARD_REG_BIT (used, j));
1056 j++);
1057 if (j == lim)
1058 {
1059 best_reg = regno;
1060 break;
1061 }
1062#ifndef REG_ALLOC_ORDER
1063 i = j; /* Skip starting points we know will lose */
1064#endif
1065 }
1066 }
1067 }
1068
1069 /* See if there is a preferred register with the same class as the register
1070 we allocated above. Making this restriction prevents register
1071 preferencing from creating worse register allocation.
1072
1073 Remove from the preferred registers and conflicting registers. Note that
1074 additional conflicts may have been added after `prune_preferences' was
1075 called.
1076
1077 First do this for those register with copy preferences, then all
1078 preferred registers. */
1079
71b77236 1080 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_copy_preferences, used);
1081 GO_IF_HARD_REG_SUBSET (allocno[num].hard_reg_copy_preferences,
ffbd18cc 1082 reg_class_contents[(int) NO_REGS], no_copy_prefs);
1083
1084 if (best_reg >= 0)
1085 {
1086 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
71b77236 1087 if (TEST_HARD_REG_BIT (allocno[num].hard_reg_copy_preferences, i)
ffbd18cc 1088 && HARD_REGNO_MODE_OK (i, mode)
1089 && (REGNO_REG_CLASS (i) == REGNO_REG_CLASS (best_reg)
1090 || reg_class_subset_p (REGNO_REG_CLASS (i),
1091 REGNO_REG_CLASS (best_reg))
1092 || reg_class_subset_p (REGNO_REG_CLASS (best_reg),
1093 REGNO_REG_CLASS (i))))
1094 {
19cb6b50 1095 int j;
1096 int lim = i + HARD_REGNO_NREGS (i, mode);
ffbd18cc 1097 for (j = i + 1;
1098 (j < lim
1099 && ! TEST_HARD_REG_BIT (used, j)
1100 && (REGNO_REG_CLASS (j)
1101 == REGNO_REG_CLASS (best_reg + (j - i))
1102 || reg_class_subset_p (REGNO_REG_CLASS (j),
1103 REGNO_REG_CLASS (best_reg + (j - i)))
1104 || reg_class_subset_p (REGNO_REG_CLASS (best_reg + (j - i)),
1105 REGNO_REG_CLASS (j))));
1106 j++);
1107 if (j == lim)
1108 {
1109 best_reg = i;
1110 goto no_prefs;
1111 }
1112 }
1113 }
1114 no_copy_prefs:
1115
71b77236 1116 AND_COMPL_HARD_REG_SET (allocno[num].hard_reg_preferences, used);
1117 GO_IF_HARD_REG_SUBSET (allocno[num].hard_reg_preferences,
ffbd18cc 1118 reg_class_contents[(int) NO_REGS], no_prefs);
1119
1120 if (best_reg >= 0)
1121 {
1122 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
71b77236 1123 if (TEST_HARD_REG_BIT (allocno[num].hard_reg_preferences, i)
ffbd18cc 1124 && HARD_REGNO_MODE_OK (i, mode)
1125 && (REGNO_REG_CLASS (i) == REGNO_REG_CLASS (best_reg)
1126 || reg_class_subset_p (REGNO_REG_CLASS (i),
1127 REGNO_REG_CLASS (best_reg))
1128 || reg_class_subset_p (REGNO_REG_CLASS (best_reg),
1129 REGNO_REG_CLASS (i))))
1130 {
19cb6b50 1131 int j;
1132 int lim = i + HARD_REGNO_NREGS (i, mode);
ffbd18cc 1133 for (j = i + 1;
1134 (j < lim
1135 && ! TEST_HARD_REG_BIT (used, j)
1136 && (REGNO_REG_CLASS (j)
1137 == REGNO_REG_CLASS (best_reg + (j - i))
1138 || reg_class_subset_p (REGNO_REG_CLASS (j),
1139 REGNO_REG_CLASS (best_reg + (j - i)))
1140 || reg_class_subset_p (REGNO_REG_CLASS (best_reg + (j - i)),
1141 REGNO_REG_CLASS (j))));
1142 j++);
1143 if (j == lim)
1144 {
1145 best_reg = i;
1146 break;
1147 }
1148 }
1149 }
1150 no_prefs:
1151
e65e050b 1152 /* If we haven't succeeded yet, try with caller-saves.
1153 We need not check to see if the current function has nonlocal
1154 labels because we don't put any pseudos that are live over calls in
1155 registers in that case. */
1156
05f2333b 1157 if (flag_caller_saves && best_reg < 0)
1158 {
1159 /* Did not find a register. If it would be profitable to
1160 allocate a call-clobbered register and save and restore it
1161 around calls, do that. */
1162 if (! accept_call_clobbered
71b77236 1163 && allocno[num].calls_crossed != 0
1164 && CALLER_SAVE_PROFITABLE (allocno[num].n_refs,
1165 allocno[num].calls_crossed))
05f2333b 1166 {
2836f006 1167 HARD_REG_SET new_losers;
1168 if (! losers)
1169 CLEAR_HARD_REG_SET (new_losers);
1170 else
1171 COPY_HARD_REG_SET (new_losers, losers);
1172
1173 IOR_HARD_REG_SET(new_losers, losing_caller_save_reg_set);
71b77236 1174 find_reg (num, new_losers, alt_regs_p, 1, retrying);
1175 if (reg_renumber[allocno[num].reg] >= 0)
05f2333b 1176 {
1177 caller_save_needed = 1;
1178 return;
1179 }
1180 }
1181 }
1182
1183 /* If we haven't succeeded yet,
1184 see if some hard reg that conflicts with us
1185 was utilized poorly by local-alloc.
1186 If so, kick out the regs that were put there by local-alloc
1187 so we can use it instead. */
1188 if (best_reg < 0 && !retrying
1189 /* Let's not bother with multi-reg allocnos. */
71b77236 1190 && allocno[num].size == 1)
05f2333b 1191 {
1192 /* Count from the end, to find the least-used ones first. */
1193 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
0c8c7dbf 1194 {
1195#ifdef REG_ALLOC_ORDER
1196 int regno = reg_alloc_order[i];
1197#else
1198 int regno = i;
1199#endif
3b1a9578 1200
0c8c7dbf 1201 if (local_reg_n_refs[regno] != 0
1202 /* Don't use a reg no good for this pseudo. */
1203 && ! TEST_HARD_REG_BIT (used2, regno)
7fbbfd4a 1204 && HARD_REGNO_MODE_OK (regno, mode)
c5af420e 1205#ifdef CLASS_CANNOT_CHANGE_MODE
1206 && ! (REG_CHANGES_MODE (allocno[num].reg)
7fbbfd4a 1207 && (TEST_HARD_REG_BIT
c5af420e 1208 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
7fbbfd4a 1209 regno)))
1210#endif
1211 )
0c8c7dbf 1212 {
d9893de9 1213 /* We explicitly evaluate the divide results into temporary
1214 variables so as to avoid excess precision problems that occur
20dd417a 1215 on an i386-unknown-sysv4.2 (unixware) host. */
d9893de9 1216
63f23608 1217 double tmp1 = ((double) local_reg_freq[regno]
d9893de9 1218 / local_reg_live_length[regno]);
63f23608 1219 double tmp2 = ((double) allocno[num].freq
71b77236 1220 / allocno[num].live_length);
d9893de9 1221
1222 if (tmp1 < tmp2)
1223 {
1224 /* Hard reg REGNO was used less in total by local regs
1225 than it would be used by this one allocno! */
1226 int k;
1227 for (k = 0; k < max_regno; k++)
1228 if (reg_renumber[k] >= 0)
1229 {
1230 int r = reg_renumber[k];
1231 int endregno
1232 = r + HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (k));
3b1a9578 1233
d9893de9 1234 if (regno >= r && regno < endregno)
1235 reg_renumber[k] = -1;
1236 }
0c8c7dbf 1237
d9893de9 1238 best_reg = regno;
1239 break;
1240 }
0c8c7dbf 1241 }
1242 }
05f2333b 1243 }
1244
ffbd18cc 1245 /* Did we find a register? */
1246
1247 if (best_reg >= 0)
1248 {
19cb6b50 1249 int lim, j;
ffbd18cc 1250 HARD_REG_SET this_reg;
1251
1252 /* Yes. Record it as the hard register of this pseudo-reg. */
71b77236 1253 reg_renumber[allocno[num].reg] = best_reg;
ffbd18cc 1254 /* Also of any pseudo-regs that share with it. */
71b77236 1255 if (reg_may_share[allocno[num].reg])
ffbd18cc 1256 for (j = FIRST_PSEUDO_REGISTER; j < max_regno; j++)
71b77236 1257 if (reg_allocno[j] == num)
ffbd18cc 1258 reg_renumber[j] = best_reg;
1259
1260 /* Make a set of the hard regs being allocated. */
1261 CLEAR_HARD_REG_SET (this_reg);
1262 lim = best_reg + HARD_REGNO_NREGS (best_reg, mode);
1263 for (j = best_reg; j < lim; j++)
1264 {
1265 SET_HARD_REG_BIT (this_reg, j);
1266 SET_HARD_REG_BIT (regs_used_so_far, j);
05f2333b 1267 /* This is no longer a reg used just by local regs. */
1268 local_reg_n_refs[j] = 0;
63f23608 1269 local_reg_freq[j] = 0;
ffbd18cc 1270 }
1271 /* For each other pseudo-reg conflicting with this one,
1272 mark it as conflicting with the hard regs this one occupies. */
71b77236 1273 lim = num;
8c278a57 1274 EXECUTE_IF_SET_IN_ALLOCNO_SET (conflicts + lim * allocno_row_words, j,
1f45e4d5 1275 {
71b77236 1276 IOR_HARD_REG_SET (allocno[j].hard_reg_conflicts, this_reg);
1f45e4d5 1277 });
ffbd18cc 1278 }
ffbd18cc 1279}
1280\f
1281/* Called from `reload' to look for a hard reg to put pseudo reg REGNO in.
1282 Perhaps it had previously seemed not worth a hard reg,
1283 or perhaps its old hard reg has been commandeered for reloads.
1284 FORBIDDEN_REGS indicates certain hard regs that may not be used, even if
1285 they do not appear to be allocated.
1286 If FORBIDDEN_REGS is zero, no regs are forbidden. */
1287
1288void
1289retry_global_alloc (regno, forbidden_regs)
1290 int regno;
1291 HARD_REG_SET forbidden_regs;
1292{
e1a0b211 1293 int alloc_no = reg_allocno[regno];
1294 if (alloc_no >= 0)
ffbd18cc 1295 {
1296 /* If we have more than one register class,
1297 first try allocating in the class that is cheapest
1298 for this pseudo-reg. If that fails, try any reg. */
1299 if (N_REG_CLASSES > 1)
e1a0b211 1300 find_reg (alloc_no, forbidden_regs, 0, 0, 1);
ffbd18cc 1301 if (reg_renumber[regno] < 0
50b0c9ee 1302 && reg_alternate_class (regno) != NO_REGS)
e1a0b211 1303 find_reg (alloc_no, forbidden_regs, 1, 0, 1);
ffbd18cc 1304
1305 /* If we found a register, modify the RTL for the register to
1306 show the hard register, and mark that register live. */
1307 if (reg_renumber[regno] >= 0)
1308 {
1309 REGNO (regno_reg_rtx[regno]) = reg_renumber[regno];
1310 mark_home_live (regno);
1311 }
1312 }
1313}
1314\f
1315/* Record a conflict between register REGNO
1316 and everything currently live.
1317 REGNO must not be a pseudo reg that was allocated
1318 by local_alloc; such numbers must be translated through
1319 reg_renumber before calling here. */
1320
1321static void
1322record_one_conflict (regno)
1323 int regno;
1324{
19cb6b50 1325 int j;
ffbd18cc 1326
1327 if (regno < FIRST_PSEUDO_REGISTER)
1328 /* When a hard register becomes live,
1329 record conflicts with live pseudo regs. */
1f45e4d5 1330 EXECUTE_IF_SET_IN_ALLOCNO_SET (allocnos_live, j,
ffbd18cc 1331 {
71b77236 1332 SET_HARD_REG_BIT (allocno[j].hard_reg_conflicts, regno);
1f45e4d5 1333 });
ffbd18cc 1334 else
1335 /* When a pseudo-register becomes live,
1336 record conflicts first with hard regs,
1337 then with other pseudo regs. */
1338 {
19cb6b50 1339 int ialloc = reg_allocno[regno];
1340 int ialloc_prod = ialloc * allocno_row_words;
1341
71b77236 1342 IOR_HARD_REG_SET (allocno[ialloc].hard_reg_conflicts, hard_regs_live);
ffbd18cc 1343 for (j = allocno_row_words - 1; j >= 0; j--)
1344 {
1345#if 0
1346 int k;
1347 for (k = 0; k < n_no_conflict_pairs; k++)
1348 if (! ((j == no_conflict_pairs[k].allocno1
1349 && ialloc == no_conflict_pairs[k].allocno2)
1350 ||
1351 (j == no_conflict_pairs[k].allocno2
1352 && ialloc == no_conflict_pairs[k].allocno1)))
1353#endif /* 0 */
1354 conflicts[ialloc_prod + j] |= allocnos_live[j];
1355 }
1356 }
1357}
1358
1359/* Record all allocnos currently live as conflicting
60f19080 1360 with all hard regs currently live.
1361
ffbd18cc 1362 ALLOCNO_VEC is a vector of LEN allocnos, all allocnos that
1363 are currently live. Their bits are also flagged in allocnos_live. */
1364
1365static void
1366record_conflicts (allocno_vec, len)
19cb6b50 1367 int *allocno_vec;
1368 int len;
ffbd18cc 1369{
19cb6b50 1370 int num;
1371 int ialloc_prod;
ffbd18cc 1372
1373 while (--len >= 0)
1374 {
71b77236 1375 num = allocno_vec[len];
1376 ialloc_prod = num * allocno_row_words;
1377 IOR_HARD_REG_SET (allocno[num].hard_reg_conflicts, hard_regs_live);
ffbd18cc 1378 }
1379}
51bc0ccc 1380
1381/* If CONFLICTP (i, j) is true, make sure CONFLICTP (j, i) is also true. */
1382static void
1383mirror_conflicts ()
1384{
19cb6b50 1385 int i, j;
51bc0ccc 1386 int rw = allocno_row_words;
1387 int rwb = rw * INT_BITS;
1388 INT_TYPE *p = conflicts;
1389 INT_TYPE *q0 = conflicts, *q1, *q2;
1390 unsigned INT_TYPE mask;
1391
1392 for (i = max_allocno - 1, mask = 1; i >= 0; i--, mask <<= 1)
1393 {
1394 if (! mask)
1395 {
1396 mask = 1;
1397 q0++;
1398 }
1399 for (j = allocno_row_words - 1, q1 = q0; j >= 0; j--, q1 += rwb)
1400 {
1401 unsigned INT_TYPE word;
1402
1403 for (word = (unsigned INT_TYPE) *p++, q2 = q1; word;
1404 word >>= 1, q2 += rw)
1405 {
1406 if (word & 1)
1407 *q2 |= mask;
1408 }
1409 }
1410 }
1411}
ffbd18cc 1412\f
1413/* Handle the case where REG is set by the insn being scanned,
1414 during the forward scan to accumulate conflicts.
1415 Store a 1 in regs_live or allocnos_live for this register, record how many
1416 consecutive hardware registers it actually needs,
1417 and record a conflict with all other registers already live.
1418
1419 Note that even if REG does not remain alive after this insn,
1420 we must mark it here as live, to ensure a conflict between
1421 REG and any other regs set in this insn that really do live.
1422 This is because those other regs could be considered after this.
1423
1424 REG might actually be something other than a register;
1425 if so, we do nothing.
1426
1427 SETTER is 0 if this register was modified by an auto-increment (i.e.,
0fa3405d 1428 a REG_INC note was found for it). */
ffbd18cc 1429
1430static void
ec8895d7 1431mark_reg_store (reg, setter, data)
0fa3405d 1432 rtx reg, setter;
ec8895d7 1433 void *data ATTRIBUTE_UNUSED;
ffbd18cc 1434{
19cb6b50 1435 int regno;
ffbd18cc 1436
ffbd18cc 1437 if (GET_CODE (reg) == SUBREG)
701e46d0 1438 reg = SUBREG_REG (reg);
ffbd18cc 1439
1440 if (GET_CODE (reg) != REG)
1441 return;
1442
ffbd18cc 1443 regs_set[n_regs_set++] = reg;
1444
0fa3405d 1445 if (setter && GET_CODE (setter) != CLOBBER)
ffbd18cc 1446 set_preference (reg, SET_SRC (setter));
1447
1448 regno = REGNO (reg);
1449
ffbd18cc 1450 /* Either this is one of the max_allocno pseudo regs not allocated,
1451 or it is or has a hardware reg. First handle the pseudo-regs. */
1452 if (regno >= FIRST_PSEUDO_REGISTER)
1453 {
1454 if (reg_allocno[regno] >= 0)
1455 {
1456 SET_ALLOCNO_LIVE (reg_allocno[regno]);
1457 record_one_conflict (regno);
1458 }
1459 }
0b6b86e7 1460
1461 if (reg_renumber[regno] >= 0)
701e46d0 1462 regno = reg_renumber[regno];
0b6b86e7 1463
ffbd18cc 1464 /* Handle hardware regs (and pseudos allocated to hard regs). */
0b6b86e7 1465 if (regno < FIRST_PSEUDO_REGISTER && ! fixed_regs[regno])
ffbd18cc 1466 {
19cb6b50 1467 int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
ffbd18cc 1468 while (regno < last)
1469 {
1470 record_one_conflict (regno);
1471 SET_HARD_REG_BIT (hard_regs_live, regno);
1472 regno++;
1473 }
1474 }
1475}
1476\f
1477/* Like mark_reg_set except notice just CLOBBERs; ignore SETs. */
1478
1479static void
ec8895d7 1480mark_reg_clobber (reg, setter, data)
ffbd18cc 1481 rtx reg, setter;
ec8895d7 1482 void *data ATTRIBUTE_UNUSED;
ffbd18cc 1483{
0fa3405d 1484 if (GET_CODE (setter) == CLOBBER)
ec8895d7 1485 mark_reg_store (reg, setter, data);
eea407a7 1486}
1487
1488/* Record that REG has conflicts with all the regs currently live.
1489 Do not mark REG itself as live. */
1490
1491static void
1492mark_reg_conflicts (reg)
1493 rtx reg;
1494{
19cb6b50 1495 int regno;
eea407a7 1496
1497 if (GET_CODE (reg) == SUBREG)
1498 reg = SUBREG_REG (reg);
1499
1500 if (GET_CODE (reg) != REG)
1501 return;
1502
1503 regno = REGNO (reg);
1504
eea407a7 1505 /* Either this is one of the max_allocno pseudo regs not allocated,
1506 or it is or has a hardware reg. First handle the pseudo-regs. */
1507 if (regno >= FIRST_PSEUDO_REGISTER)
1508 {
1509 if (reg_allocno[regno] >= 0)
1510 record_one_conflict (regno);
1511 }
0b6b86e7 1512
1513 if (reg_renumber[regno] >= 0)
1514 regno = reg_renumber[regno];
1515
eea407a7 1516 /* Handle hardware regs (and pseudos allocated to hard regs). */
0b6b86e7 1517 if (regno < FIRST_PSEUDO_REGISTER && ! fixed_regs[regno])
eea407a7 1518 {
19cb6b50 1519 int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
eea407a7 1520 while (regno < last)
1521 {
1522 record_one_conflict (regno);
1523 regno++;
1524 }
1525 }
ffbd18cc 1526}
1527\f
1528/* Mark REG as being dead (following the insn being scanned now).
1529 Store a 0 in regs_live or allocnos_live for this register. */
1530
1531static void
1532mark_reg_death (reg)
1533 rtx reg;
1534{
19cb6b50 1535 int regno = REGNO (reg);
ffbd18cc 1536
ffbd18cc 1537 /* Either this is one of the max_allocno pseudo regs not allocated,
1538 or it is a hardware reg. First handle the pseudo-regs. */
1539 if (regno >= FIRST_PSEUDO_REGISTER)
1540 {
1541 if (reg_allocno[regno] >= 0)
1542 CLEAR_ALLOCNO_LIVE (reg_allocno[regno]);
1543 }
0b6b86e7 1544
1545 /* For pseudo reg, see if it has been assigned a hardware reg. */
1546 if (reg_renumber[regno] >= 0)
1547 regno = reg_renumber[regno];
1548
ffbd18cc 1549 /* Handle hardware regs (and pseudos allocated to hard regs). */
0b6b86e7 1550 if (regno < FIRST_PSEUDO_REGISTER && ! fixed_regs[regno])
ffbd18cc 1551 {
1552 /* Pseudo regs already assigned hardware regs are treated
1553 almost the same as explicit hardware regs. */
19cb6b50 1554 int last = regno + HARD_REGNO_NREGS (regno, GET_MODE (reg));
ffbd18cc 1555 while (regno < last)
1556 {
1557 CLEAR_HARD_REG_BIT (hard_regs_live, regno);
1558 regno++;
1559 }
1560 }
1561}
1562
1563/* Mark hard reg REGNO as currently live, assuming machine mode MODE
1564 for the value stored in it. MODE determines how many consecutive
1565 registers are actually in use. Do not record conflicts;
1566 it is assumed that the caller will do that. */
1567
1568static void
1569mark_reg_live_nc (regno, mode)
19cb6b50 1570 int regno;
ffbd18cc 1571 enum machine_mode mode;
1572{
19cb6b50 1573 int last = regno + HARD_REGNO_NREGS (regno, mode);
ffbd18cc 1574 while (regno < last)
1575 {
1576 SET_HARD_REG_BIT (hard_regs_live, regno);
1577 regno++;
1578 }
1579}
1580\f
1581/* Try to set a preference for an allocno to a hard register.
1582 We are passed DEST and SRC which are the operands of a SET. It is known
1583 that SRC is a register. If SRC or the first operand of SRC is a register,
1584 try to set a preference. If one of the two is a hard register and the other
1585 is a pseudo-register, mark the preference.
1586
4bbea254 1587 Note that we are not as aggressive as local-alloc in trying to tie a
ffbd18cc 1588 pseudo-register to a hard register. */
1589
1590static void
1591set_preference (dest, src)
1592 rtx dest, src;
1593{
02e7a332 1594 unsigned int src_regno, dest_regno;
ffbd18cc 1595 /* Amount to add to the hard regno for SRC, or subtract from that for DEST,
1596 to compensate for subregs in SRC or DEST. */
1597 int offset = 0;
02e7a332 1598 unsigned int i;
ffbd18cc 1599 int copy = 1;
1600
1601 if (GET_RTX_FORMAT (GET_CODE (src))[0] == 'e')
1602 src = XEXP (src, 0), copy = 0;
1603
1604 /* Get the reg number for both SRC and DEST.
1605 If neither is a reg, give up. */
1606
1607 if (GET_CODE (src) == REG)
1608 src_regno = REGNO (src);
1609 else if (GET_CODE (src) == SUBREG && GET_CODE (SUBREG_REG (src)) == REG)
1610 {
1611 src_regno = REGNO (SUBREG_REG (src));
701e46d0 1612
1613 if (REGNO (SUBREG_REG (src)) < FIRST_PSEUDO_REGISTER)
1614 offset += subreg_regno_offset (REGNO (SUBREG_REG (src)),
1615 GET_MODE (SUBREG_REG (src)),
1616 SUBREG_BYTE (src),
1617 GET_MODE (src));
1618 else
1619 offset += (SUBREG_BYTE (src)
1620 / REGMODE_NATURAL_SIZE (GET_MODE (src)));
ffbd18cc 1621 }
1622 else
1623 return;
1624
1625 if (GET_CODE (dest) == REG)
1626 dest_regno = REGNO (dest);
1627 else if (GET_CODE (dest) == SUBREG && GET_CODE (SUBREG_REG (dest)) == REG)
1628 {
1629 dest_regno = REGNO (SUBREG_REG (dest));
701e46d0 1630
1631 if (REGNO (SUBREG_REG (dest)) < FIRST_PSEUDO_REGISTER)
1632 offset -= subreg_regno_offset (REGNO (SUBREG_REG (dest)),
1633 GET_MODE (SUBREG_REG (dest)),
1634 SUBREG_BYTE (dest),
1635 GET_MODE (dest));
1636 else
1637 offset -= (SUBREG_BYTE (dest)
1638 / REGMODE_NATURAL_SIZE (GET_MODE (dest)));
ffbd18cc 1639 }
1640 else
1641 return;
1642
1643 /* Convert either or both to hard reg numbers. */
1644
1645 if (reg_renumber[src_regno] >= 0)
1646 src_regno = reg_renumber[src_regno];
1647
1648 if (reg_renumber[dest_regno] >= 0)
1649 dest_regno = reg_renumber[dest_regno];
1650
1651 /* Now if one is a hard reg and the other is a global pseudo
1652 then give the other a preference. */
1653
1654 if (dest_regno < FIRST_PSEUDO_REGISTER && src_regno >= FIRST_PSEUDO_REGISTER
1655 && reg_allocno[src_regno] >= 0)
1656 {
1657 dest_regno -= offset;
02e7a332 1658 if (dest_regno < FIRST_PSEUDO_REGISTER)
ffbd18cc 1659 {
1660 if (copy)
1661 SET_REGBIT (hard_reg_copy_preferences,
1662 reg_allocno[src_regno], dest_regno);
1663
1664 SET_REGBIT (hard_reg_preferences,
1665 reg_allocno[src_regno], dest_regno);
1666 for (i = dest_regno;
1667 i < dest_regno + HARD_REGNO_NREGS (dest_regno, GET_MODE (dest));
1668 i++)
1669 SET_REGBIT (hard_reg_full_preferences, reg_allocno[src_regno], i);
1670 }
1671 }
1672
1673 if (src_regno < FIRST_PSEUDO_REGISTER && dest_regno >= FIRST_PSEUDO_REGISTER
1674 && reg_allocno[dest_regno] >= 0)
1675 {
1676 src_regno += offset;
02e7a332 1677 if (src_regno < FIRST_PSEUDO_REGISTER)
ffbd18cc 1678 {
1679 if (copy)
1680 SET_REGBIT (hard_reg_copy_preferences,
1681 reg_allocno[dest_regno], src_regno);
1682
1683 SET_REGBIT (hard_reg_preferences,
1684 reg_allocno[dest_regno], src_regno);
1685 for (i = src_regno;
1686 i < src_regno + HARD_REGNO_NREGS (src_regno, GET_MODE (src));
1687 i++)
1688 SET_REGBIT (hard_reg_full_preferences, reg_allocno[dest_regno], i);
1689 }
1690 }
1691}
1692\f
1693/* Indicate that hard register number FROM was eliminated and replaced with
1694 an offset from hard register number TO. The status of hard registers live
1695 at the start of a basic block is updated by replacing a use of FROM with
1696 a use of TO. */
1697
1698void
1699mark_elimination (from, to)
1700 int from, to;
1701{
1702 int i;
1703
1704 for (i = 0; i < n_basic_blocks; i++)
71caadc0 1705 {
19cb6b50 1706 regset r = BASIC_BLOCK (i)->global_live_at_start;
71caadc0 1707 if (REGNO_REG_SET_P (r, from))
1708 {
1709 CLEAR_REGNO_REG_SET (r, from);
1710 SET_REGNO_REG_SET (r, to);
1711 }
1712 }
ffbd18cc 1713}
1714\f
e94a59c6 1715/* Used for communication between the following functions. Holds the
1716 current life information. */
1717static regset live_relevant_regs;
1718
a570a59f 1719/* Record in live_relevant_regs and REGS_SET that register REG became live.
1720 This is called via note_stores. */
e94a59c6 1721static void
a570a59f 1722reg_becomes_live (reg, setter, regs_set)
e94a59c6 1723 rtx reg;
1724 rtx setter ATTRIBUTE_UNUSED;
a570a59f 1725 void *regs_set;
e94a59c6 1726{
1727 int regno;
1728
1729 if (GET_CODE (reg) == SUBREG)
1730 reg = SUBREG_REG (reg);
1731
1732 if (GET_CODE (reg) != REG)
1733 return;
1734
1735 regno = REGNO (reg);
1736 if (regno < FIRST_PSEUDO_REGISTER)
1737 {
1738 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
1739 while (nregs-- > 0)
a570a59f 1740 {
1741 SET_REGNO_REG_SET (live_relevant_regs, regno);
1742 if (! fixed_regs[regno])
1743 SET_REGNO_REG_SET ((regset) regs_set, regno);
1744 regno++;
1745 }
e94a59c6 1746 }
1747 else if (reg_renumber[regno] >= 0)
a570a59f 1748 {
1749 SET_REGNO_REG_SET (live_relevant_regs, regno);
1750 SET_REGNO_REG_SET ((regset) regs_set, regno);
1751 }
e94a59c6 1752}
1753
1754/* Record in live_relevant_regs that register REGNO died. */
1755static void
a570a59f 1756reg_dies (regno, mode, chain)
e94a59c6 1757 int regno;
1758 enum machine_mode mode;
a570a59f 1759 struct insn_chain *chain;
e94a59c6 1760{
1761 if (regno < FIRST_PSEUDO_REGISTER)
1762 {
1763 int nregs = HARD_REGNO_NREGS (regno, mode);
1764 while (nregs-- > 0)
a570a59f 1765 {
1766 CLEAR_REGNO_REG_SET (live_relevant_regs, regno);
1767 if (! fixed_regs[regno])
f62c22a7 1768 SET_REGNO_REG_SET (&chain->dead_or_set, regno);
a570a59f 1769 regno++;
1770 }
e94a59c6 1771 }
1772 else
a570a59f 1773 {
1774 CLEAR_REGNO_REG_SET (live_relevant_regs, regno);
1775 if (reg_renumber[regno] >= 0)
f62c22a7 1776 SET_REGNO_REG_SET (&chain->dead_or_set, regno);
a570a59f 1777 }
e94a59c6 1778}
1779
1780/* Walk the insns of the current function and build reload_insn_chain,
1781 and record register life information. */
dd2acd83 1782void
6f5c3acb 1783build_insn_chain (first)
1784 rtx first;
e94a59c6 1785{
1786 struct insn_chain **p = &reload_insn_chain;
1787 struct insn_chain *prev = 0;
6f5c3acb 1788 int b = 0;
3367fbd0 1789 regset_head live_relevant_regs_head;
e94a59c6 1790
3367fbd0 1791 live_relevant_regs = INITIALIZE_REG_SET (live_relevant_regs_head);
e94a59c6 1792
6f5c3acb 1793 for (; first; first = NEXT_INSN (first))
e94a59c6 1794 {
6f5c3acb 1795 struct insn_chain *c;
e94a59c6 1796
6f5c3acb 1797 if (first == BLOCK_HEAD (b))
e94a59c6 1798 {
6f5c3acb 1799 int i;
51bc0ccc 1800
6f5c3acb 1801 CLEAR_REG_SET (live_relevant_regs);
51bc0ccc 1802
1803 EXECUTE_IF_SET_IN_BITMAP
1804 (BASIC_BLOCK (b)->global_live_at_start, 0, i,
1805 {
1806 if (i < FIRST_PSEUDO_REGISTER
1807 ? ! TEST_HARD_REG_BIT (eliminable_regset, i)
1808 : reg_renumber[i] >= 0)
1809 SET_REGNO_REG_SET (live_relevant_regs, i);
1810 });
1811 }
6f5c3acb 1812
1813 if (GET_CODE (first) != NOTE && GET_CODE (first) != BARRIER)
b104a6a7 1814 {
6f5c3acb 1815 c = new_insn_chain ();
1816 c->prev = prev;
1817 prev = c;
1818 *p = c;
1819 p = &c->next;
1820 c->insn = first;
1821 c->block = b;
1822
9204e736 1823 if (INSN_P (first))
e94a59c6 1824 {
6f5c3acb 1825 rtx link;
e94a59c6 1826
6f5c3acb 1827 /* Mark the death of everything that dies in this instruction. */
e94a59c6 1828
6f5c3acb 1829 for (link = REG_NOTES (first); link; link = XEXP (link, 1))
1830 if (REG_NOTE_KIND (link) == REG_DEAD
1831 && GET_CODE (XEXP (link, 0)) == REG)
a570a59f 1832 reg_dies (REGNO (XEXP (link, 0)), GET_MODE (XEXP (link, 0)),
1833 c);
1834
f62c22a7 1835 COPY_REG_SET (&c->live_throughout, live_relevant_regs);
e94a59c6 1836
6f5c3acb 1837 /* Mark everything born in this instruction as live. */
e94a59c6 1838
a570a59f 1839 note_stores (PATTERN (first), reg_becomes_live,
f62c22a7 1840 &c->dead_or_set);
e94a59c6 1841 }
a570a59f 1842 else
f62c22a7 1843 COPY_REG_SET (&c->live_throughout, live_relevant_regs);
6f5c3acb 1844
9204e736 1845 if (INSN_P (first))
6f5c3acb 1846 {
1847 rtx link;
1848
1849 /* Mark anything that is set in this insn and then unused as dying. */
1850
1851 for (link = REG_NOTES (first); link; link = XEXP (link, 1))
1852 if (REG_NOTE_KIND (link) == REG_UNUSED
1853 && GET_CODE (XEXP (link, 0)) == REG)
a570a59f 1854 reg_dies (REGNO (XEXP (link, 0)), GET_MODE (XEXP (link, 0)),
1855 c);
6f5c3acb 1856 }
3cf7d3b9 1857 }
b104a6a7 1858
6f5c3acb 1859 if (first == BLOCK_END (b))
1860 b++;
1861
1862 /* Stop after we pass the end of the last basic block. Verify that
1863 no real insns are after the end of the last basic block.
1864
1865 We may want to reorganize the loop somewhat since this test should
954b85b0 1866 always be the right exit test. Allow an ADDR_VEC or ADDR_DIF_VEC if
1867 the previous real insn is a JUMP_INSN. */
6f5c3acb 1868 if (b == n_basic_blocks)
1869 {
1870 for (first = NEXT_INSN (first) ; first; first = NEXT_INSN (first))
954b85b0 1871 if (INSN_P (first)
1872 && GET_CODE (PATTERN (first)) != USE
1873 && ! ((GET_CODE (PATTERN (first)) == ADDR_VEC
1874 || GET_CODE (PATTERN (first)) == ADDR_DIFF_VEC)
1875 && prev_real_insn (first) != 0
1876 && GET_CODE (prev_real_insn (first)) == JUMP_INSN))
6f5c3acb 1877 abort ();
1878 break;
1879 }
1880 }
e94a59c6 1881 FREE_REG_SET (live_relevant_regs);
1882 *p = 0;
1883}
1884\f
86c5656a 1885/* Print debugging trace information if -dg switch is given,
ffbd18cc 1886 showing the information on which the allocation decisions are based. */
1887
1888static void
1889dump_conflicts (file)
1890 FILE *file;
1891{
19cb6b50 1892 int i;
1893 int has_preferences;
1894 int nregs;
0b6b86e7 1895 nregs = 0;
1896 for (i = 0; i < max_allocno; i++)
1897 {
71b77236 1898 if (reg_renumber[allocno[allocno_order[i]].reg] >= 0)
0b6b86e7 1899 continue;
1900 nregs++;
1901 }
1902 fprintf (file, ";; %d regs to allocate:", nregs);
ffbd18cc 1903 for (i = 0; i < max_allocno; i++)
1904 {
1905 int j;
71b77236 1906 if (reg_renumber[allocno[allocno_order[i]].reg] >= 0)
0b6b86e7 1907 continue;
71b77236 1908 fprintf (file, " %d", allocno[allocno_order[i]].reg);
ffbd18cc 1909 for (j = 0; j < max_regno; j++)
1910 if (reg_allocno[j] == allocno_order[i]
71b77236 1911 && j != allocno[allocno_order[i]].reg)
ffbd18cc 1912 fprintf (file, "+%d", j);
71b77236 1913 if (allocno[allocno_order[i]].size != 1)
1914 fprintf (file, " (%d)", allocno[allocno_order[i]].size);
ffbd18cc 1915 }
1916 fprintf (file, "\n");
1917
1918 for (i = 0; i < max_allocno; i++)
1919 {
19cb6b50 1920 int j;
71b77236 1921 fprintf (file, ";; %d conflicts:", allocno[i].reg);
ffbd18cc 1922 for (j = 0; j < max_allocno; j++)
51bc0ccc 1923 if (CONFLICTP (j, i))
71b77236 1924 fprintf (file, " %d", allocno[j].reg);
ffbd18cc 1925 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
71b77236 1926 if (TEST_HARD_REG_BIT (allocno[i].hard_reg_conflicts, j))
ffbd18cc 1927 fprintf (file, " %d", j);
1928 fprintf (file, "\n");
1929
1930 has_preferences = 0;
1931 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
71b77236 1932 if (TEST_HARD_REG_BIT (allocno[i].hard_reg_preferences, j))
ffbd18cc 1933 has_preferences = 1;
1934
1935 if (! has_preferences)
1936 continue;
71b77236 1937 fprintf (file, ";; %d preferences:", allocno[i].reg);
ffbd18cc 1938 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
71b77236 1939 if (TEST_HARD_REG_BIT (allocno[i].hard_reg_preferences, j))
ffbd18cc 1940 fprintf (file, " %d", j);
1941 fprintf (file, "\n");
1942 }
1943 fprintf (file, "\n");
1944}
1945
1946void
1947dump_global_regs (file)
1948 FILE *file;
1949{
19cb6b50 1950 int i, j;
ffbd18cc 1951
1952 fprintf (file, ";; Register dispositions:\n");
1953 for (i = FIRST_PSEUDO_REGISTER, j = 0; i < max_regno; i++)
1954 if (reg_renumber[i] >= 0)
1955 {
1956 fprintf (file, "%d in %d ", i, reg_renumber[i]);
1957 if (++j % 6 == 0)
1958 fprintf (file, "\n");
1959 }
1960
1961 fprintf (file, "\n\n;; Hard regs used: ");
1962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1963 if (regs_ever_live[i])
1964 fprintf (file, " %d", i);
1965 fprintf (file, "\n\n");
1966}