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3245eea0 1/* Sets (bit vectors) of hard registers, and operations on them.
7adcbafe 2 Copyright (C) 1987-2022 Free Software Foundation, Inc.
3245eea0 3
1322177d 4This file is part of GCC
3245eea0 5
1322177d
LB
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
9dcd6f09 8Software Foundation; either version 3, or (at your option) any later
1322177d 9version.
3245eea0 10
1322177d
LB
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
3245eea0
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15
16You should have received a copy of the GNU General Public License
9dcd6f09
NC
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
3245eea0 19
88657302 20#ifndef GCC_HARD_REG_SET_H
b8698a0f 21#define GCC_HARD_REG_SET_H
3245eea0 22
148909bc
RS
23#include "array-traits.h"
24
3245eea0
CH
25/* Define the type of a set of hard registers. */
26
328d0797
RS
27/* HARD_REG_ELT_TYPE is a typedef of the unsigned integral type which
28 will be used for hard reg sets, either alone or in an array.
29
30 If HARD_REG_SET is a macro, its definition is HARD_REG_ELT_TYPE,
31 and it has enough bits to represent all the target machine's hard
32 registers. Otherwise, it is a typedef for a suitably sized array
33 of HARD_REG_ELT_TYPEs. HARD_REG_SET_LONGS is defined as how many.
3245eea0
CH
34
35 Note that lots of code assumes that the first part of a regset is
36 the same format as a HARD_REG_SET. To help make sure this is true,
99fa8911
AP
37 we only try the widest fast integer mode (HOST_WIDEST_FAST_INT)
38 instead of all the smaller types. This approach loses only if
2a7e31df 39 there are very few registers and then only in the few cases where
99fa8911
AP
40 we have an array of HARD_REG_SETs, so it needn't be as complex as
41 it used to be. */
328d0797 42
99fa8911 43typedef unsigned HOST_WIDEST_FAST_INT HARD_REG_ELT_TYPE;
3245eea0 44
99fa8911 45#if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDEST_FAST_INT
328d0797 46
504279ae
RS
47typedef HARD_REG_ELT_TYPE HARD_REG_SET;
48typedef const HARD_REG_SET const_hard_reg_set;
3245eea0
CH
49
50#else
51
52#define HARD_REG_SET_LONGS \
99fa8911
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53 ((FIRST_PSEUDO_REGISTER + HOST_BITS_PER_WIDEST_FAST_INT - 1) \
54 / HOST_BITS_PER_WIDEST_FAST_INT)
504279ae
RS
55
56struct HARD_REG_SET
57{
50b3f54d
RS
58 HARD_REG_SET
59 operator~ () const
60 {
61 HARD_REG_SET res;
62 for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
63 res.elts[i] = ~elts[i];
64 return res;
65 }
66
dc333d8f
RS
67 HARD_REG_SET
68 operator& (const HARD_REG_SET &other) const
69 {
70 HARD_REG_SET res;
71 for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
72 res.elts[i] = elts[i] & other.elts[i];
73 return res;
74 }
75
76 HARD_REG_SET &
77 operator&= (const HARD_REG_SET &other)
78 {
79 for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
80 elts[i] &= other.elts[i];
81 return *this;
82 }
83
44942965
RS
84 HARD_REG_SET
85 operator| (const HARD_REG_SET &other) const
86 {
87 HARD_REG_SET res;
88 for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
89 res.elts[i] = elts[i] | other.elts[i];
90 return res;
91 }
92
93 HARD_REG_SET &
94 operator|= (const HARD_REG_SET &other)
95 {
96 for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
97 elts[i] |= other.elts[i];
98 return *this;
99 }
100
a8579651
RS
101 bool
102 operator== (const HARD_REG_SET &other) const
103 {
104 HARD_REG_ELT_TYPE bad = 0;
105 for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
106 bad |= (elts[i] ^ other.elts[i]);
107 return bad == 0;
108 }
109
110 bool
111 operator!= (const HARD_REG_SET &other) const
112 {
113 return !operator== (other);
114 }
115
504279ae
RS
116 HARD_REG_ELT_TYPE elts[HARD_REG_SET_LONGS];
117};
118typedef const HARD_REG_SET &const_hard_reg_set;
3245eea0 119
148909bc
RS
120template<>
121struct array_traits<HARD_REG_SET>
122{
123 typedef HARD_REG_ELT_TYPE element_type;
124 static const bool has_constant_size = true;
125 static const size_t constant_size = HARD_REG_SET_LONGS;
126 static const element_type *base (const HARD_REG_SET &x) { return x.elts; }
127 static size_t size (const HARD_REG_SET &) { return HARD_REG_SET_LONGS; }
128};
129
3245eea0
CH
130#endif
131
ee3d2ecd
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132/* HARD_REG_SET wrapped into a structure, to make it possible to
133 use HARD_REG_SET even in APIs that should not include
134 hard-reg-set.h. */
135struct hard_reg_set_container
136{
137 HARD_REG_SET set;
138};
139
328d0797
RS
140/* HARD_CONST is used to cast a constant to the appropriate type
141 for use with a HARD_REG_SET. */
3245eea0 142
328d0797 143#define HARD_CONST(X) ((HARD_REG_ELT_TYPE) (X))
3245eea0
CH
144
145/* Define macros SET_HARD_REG_BIT, CLEAR_HARD_REG_BIT and TEST_HARD_REG_BIT
146 to set, clear or test one bit in a hard reg set of type HARD_REG_SET.
147 All three take two arguments: the set and the register number.
148
149 In the case where sets are arrays of longs, the first argument
150 is actually a pointer to a long.
151
152 Define two macros for initializing a set:
153 CLEAR_HARD_REG_SET and SET_HARD_REG_SET.
154 These take just one argument.
155
56b138ae
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156 Also define:
157
158 hard_reg_set_subset_p (X, Y), which returns true if X is a subset of Y.
56b138ae
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159 hard_reg_set_intersect_p (X, Y), which returns true if X and Y intersect.
160 hard_reg_set_empty_p (X), which returns true if X is empty. */
3245eea0 161
e855c69d
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162#define UHOST_BITS_PER_WIDE_INT ((unsigned) HOST_BITS_PER_WIDEST_FAST_INT)
163
504279ae 164#if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDEST_FAST_INT
3245eea0
CH
165
166#define SET_HARD_REG_BIT(SET, BIT) \
167 ((SET) |= HARD_CONST (1) << (BIT))
168#define CLEAR_HARD_REG_BIT(SET, BIT) \
169 ((SET) &= ~(HARD_CONST (1) << (BIT)))
170#define TEST_HARD_REG_BIT(SET, BIT) \
ae32926b 171 (!!((SET) & (HARD_CONST (1) << (BIT))))
3245eea0
CH
172
173#define CLEAR_HARD_REG_SET(TO) ((TO) = HARD_CONST (0))
328d0797 174#define SET_HARD_REG_SET(TO) ((TO) = ~ HARD_CONST (0))
3245eea0 175
56b138ae 176static inline bool
504279ae 177hard_reg_set_subset_p (const_hard_reg_set x, const_hard_reg_set y)
56b138ae
RS
178{
179 return (x & ~y) == HARD_CONST (0);
180}
181
56b138ae 182static inline bool
504279ae 183hard_reg_set_intersect_p (const_hard_reg_set x, const_hard_reg_set y)
56b138ae
RS
184{
185 return (x & y) != HARD_CONST (0);
186}
187
188static inline bool
504279ae 189hard_reg_set_empty_p (const_hard_reg_set x)
56b138ae
RS
190{
191 return x == HARD_CONST (0);
192}
328d0797 193
3245eea0
CH
194#else
195
504279ae
RS
196inline void
197SET_HARD_REG_BIT (HARD_REG_SET &set, unsigned int bit)
56b138ae 198{
504279ae
RS
199 set.elts[bit / UHOST_BITS_PER_WIDE_INT]
200 |= HARD_CONST (1) << (bit % UHOST_BITS_PER_WIDE_INT);
56b138ae
RS
201}
202
504279ae
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203inline void
204CLEAR_HARD_REG_BIT (HARD_REG_SET &set, unsigned int bit)
56b138ae 205{
504279ae
RS
206 set.elts[bit / UHOST_BITS_PER_WIDE_INT]
207 &= ~(HARD_CONST (1) << (bit % UHOST_BITS_PER_WIDE_INT));
56b138ae
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208}
209
504279ae
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210inline bool
211TEST_HARD_REG_BIT (const_hard_reg_set set, unsigned int bit)
56b138ae 212{
504279ae
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213 return (set.elts[bit / UHOST_BITS_PER_WIDE_INT]
214 & (HARD_CONST (1) << (bit % UHOST_BITS_PER_WIDE_INT)));
56b138ae
RS
215}
216
504279ae
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217inline void
218CLEAR_HARD_REG_SET (HARD_REG_SET &set)
56b138ae 219{
504279ae
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220 for (unsigned int i = 0; i < ARRAY_SIZE (set.elts); ++i)
221 set.elts[i] = 0;
56b138ae 222}
ea78578f 223
504279ae
RS
224inline void
225SET_HARD_REG_SET (HARD_REG_SET &set)
56b138ae 226{
504279ae
RS
227 for (unsigned int i = 0; i < ARRAY_SIZE (set.elts); ++i)
228 set.elts[i] = -1;
56b138ae
RS
229}
230
56b138ae 231static inline bool
504279ae 232hard_reg_set_subset_p (const_hard_reg_set x, const_hard_reg_set y)
56b138ae 233{
504279ae
RS
234 HARD_REG_ELT_TYPE bad = 0;
235 for (unsigned int i = 0; i < ARRAY_SIZE (x.elts); ++i)
236 bad |= (x.elts[i] & ~y.elts[i]);
237 return bad == 0;
56b138ae
RS
238}
239
56b138ae 240static inline bool
504279ae 241hard_reg_set_intersect_p (const_hard_reg_set x, const_hard_reg_set y)
56b138ae 242{
504279ae
RS
243 HARD_REG_ELT_TYPE good = 0;
244 for (unsigned int i = 0; i < ARRAY_SIZE (x.elts); ++i)
245 good |= (x.elts[i] & y.elts[i]);
246 return good != 0;
56b138ae
RS
247}
248
249static inline bool
504279ae 250hard_reg_set_empty_p (const_hard_reg_set x)
56b138ae 251{
504279ae
RS
252 HARD_REG_ELT_TYPE bad = 0;
253 for (unsigned int i = 0; i < ARRAY_SIZE (x.elts); ++i)
254 bad |= x.elts[i];
255 return bad == 0;
56b138ae 256}
ea78578f 257#endif
3245eea0 258
e855c69d
AB
259/* Iterator for hard register sets. */
260
84562394 261struct hard_reg_set_iterator
e855c69d
AB
262{
263 /* Pointer to the current element. */
504279ae 264 const HARD_REG_ELT_TYPE *pelt;
e855c69d
AB
265
266 /* The length of the set. */
267 unsigned short length;
268
269 /* Word within the current element. */
270 unsigned short word_no;
271
272 /* Contents of the actually processed word. When finding next bit
273 it is shifted right, so that the actual bit is always the least
274 significant bit of ACTUAL. */
275 HARD_REG_ELT_TYPE bits;
84562394 276};
e855c69d
AB
277
278#define HARD_REG_ELT_BITS UHOST_BITS_PER_WIDE_INT
279
b8698a0f 280/* The implementation of the iterator functions is fully analogous to
e855c69d
AB
281 the bitmap iterators. */
282static inline void
504279ae 283hard_reg_set_iter_init (hard_reg_set_iterator *iter, const_hard_reg_set set,
e855c69d
AB
284 unsigned min, unsigned *regno)
285{
286#ifdef HARD_REG_SET_LONGS
504279ae 287 iter->pelt = set.elts;
e855c69d
AB
288 iter->length = HARD_REG_SET_LONGS;
289#else
290 iter->pelt = &set;
291 iter->length = 1;
292#endif
293 iter->word_no = min / HARD_REG_ELT_BITS;
294 if (iter->word_no < iter->length)
295 {
296 iter->bits = iter->pelt[iter->word_no];
297 iter->bits >>= min % HARD_REG_ELT_BITS;
298
299 /* This is required for correct search of the next bit. */
300 min += !iter->bits;
301 }
302 *regno = min;
303}
304
b8698a0f 305static inline bool
e855c69d
AB
306hard_reg_set_iter_set (hard_reg_set_iterator *iter, unsigned *regno)
307{
308 while (1)
309 {
310 /* Return false when we're advanced past the end of the set. */
311 if (iter->word_no >= iter->length)
312 return false;
313
314 if (iter->bits)
315 {
316 /* Find the correct bit and return it. */
317 while (!(iter->bits & 1))
318 {
319 iter->bits >>= 1;
320 *regno += 1;
321 }
322 return (*regno < FIRST_PSEUDO_REGISTER);
323 }
b8698a0f 324
e855c69d
AB
325 /* Round to the beginning of the next word. */
326 *regno = (*regno + HARD_REG_ELT_BITS - 1);
327 *regno -= *regno % HARD_REG_ELT_BITS;
328
329 /* Find the next non-zero word. */
330 while (++iter->word_no < iter->length)
331 {
332 iter->bits = iter->pelt[iter->word_no];
333 if (iter->bits)
334 break;
335 *regno += HARD_REG_ELT_BITS;
336 }
337 }
338}
339
340static inline void
341hard_reg_set_iter_next (hard_reg_set_iterator *iter, unsigned *regno)
342{
343 iter->bits >>= 1;
344 *regno += 1;
345}
346
347#define EXECUTE_IF_SET_IN_HARD_REG_SET(SET, MIN, REGNUM, ITER) \
348 for (hard_reg_set_iter_init (&(ITER), (SET), (MIN), &(REGNUM)); \
349 hard_reg_set_iter_set (&(ITER), &(REGNUM)); \
350 hard_reg_set_iter_next (&(ITER), &(REGNUM)))
351
352
3245eea0
CH
353/* Define some standard sets of registers. */
354
3245eea0
CH
355/* Indexed by hard register number, contains 1 for registers
356 that are being used for global register decls.
357 These must be exempt from ordinary flow analysis
358 and are also considered fixed. */
359
360extern char global_regs[FIRST_PSEUDO_REGISTER];
361
900846cd
RS
362extern HARD_REG_SET global_reg_set;
363
99b1c316
MS
364class simplifiable_subreg;
365class subreg_shape;
67f58944 366
8d67ee55 367struct simplifiable_subregs_hasher : nofree_ptr_hash <simplifiable_subreg>
67f58944 368{
67f58944
TS
369 typedef const subreg_shape *compare_type;
370
371 static inline hashval_t hash (const simplifiable_subreg *);
372 static inline bool equal (const simplifiable_subreg *, const subreg_shape *);
373};
6969eb0d 374
6642445b 375struct target_hard_regs {
6969eb0d
RS
376 void finalize ();
377
006b72bf
RS
378 /* The set of registers that actually exist on the current target. */
379 HARD_REG_SET x_accessible_reg_set;
380
381 /* The set of registers that should be considered to be register
382 operands. It is a subset of x_accessible_reg_set. */
383 HARD_REG_SET x_operand_reg_set;
384
6642445b
RS
385 /* Indexed by hard register number, contains 1 for registers
386 that are fixed use (stack pointer, pc, frame pointer, etc.;.
387 These are the registers that cannot be used to allocate
388 a pseudo reg whose life does not cross calls. */
389 char x_fixed_regs[FIRST_PSEUDO_REGISTER];
3245eea0 390
6642445b
RS
391 /* The same info as a HARD_REG_SET. */
392 HARD_REG_SET x_fixed_reg_set;
f5d8c9f4 393
6642445b
RS
394 /* Indexed by hard register number, contains 1 for registers
395 that are fixed use or are clobbered by function calls.
396 These are the registers that cannot be used to allocate
397 a pseudo reg whose life crosses calls. */
398 char x_call_used_regs[FIRST_PSEUDO_REGISTER];
f5d8c9f4 399
df1f0eef
RS
400 /* For targets that use reload rather than LRA, this is the set
401 of registers that we are able to save and restore around calls
402 (i.e. those for which we know a suitable mode and set of
403 load/store instructions exist). For LRA targets it contains
404 all registers.
405
406 This is legacy information and should be removed if all targets
407 switch to LRA. */
408 HARD_REG_SET x_savable_regs;
3245eea0 409
f80041ef
BS
410 /* Contains registers that are fixed use -- i.e. in fixed_reg_set -- but
411 only if they are not merely part of that set because they are global
412 regs. Global regs that are not otherwise fixed can still take part
413 in register allocation. */
414 HARD_REG_SET x_fixed_nonglobal_reg_set;
415
6642445b
RS
416 /* Contains 1 for registers that are set or clobbered by calls. */
417 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
418 for someone's bright idea to have call_used_regs strictly include
419 fixed_regs. Which leaves us guessing as to the set of fixed_regs
420 that are actually preserved. We know for sure that those associated
421 with the local stack frame are safe, but scant others. */
422 HARD_REG_SET x_regs_invalidated_by_call;
3245eea0 423
6642445b
RS
424 /* Table of register numbers in the order in which to try to use them. */
425 int x_reg_alloc_order[FIRST_PSEUDO_REGISTER];
c033690d 426
6642445b
RS
427 /* The inverse of reg_alloc_order. */
428 int x_inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
3245eea0 429
6642445b
RS
430 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
431 HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
3245eea0 432
6642445b
RS
433 /* For each reg class, a boolean saying whether the class contains only
434 fixed registers. */
435 bool x_class_only_fixed_regs[N_REG_CLASSES];
058e97ec 436
6642445b
RS
437 /* For each reg class, number of regs it contains. */
438 unsigned int x_reg_class_size[N_REG_CLASSES];
058e97ec 439
6642445b
RS
440 /* For each reg class, table listing all the classes contained in it. */
441 enum reg_class x_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
3245eea0 442
6642445b
RS
443 /* For each pair of reg classes,
444 a largest reg class contained in their union. */
445 enum reg_class x_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
3245eea0 446
6642445b
RS
447 /* For each pair of reg classes,
448 the smallest reg class that contains their union. */
449 enum reg_class x_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
3245eea0 450
6642445b
RS
451 /* Vector indexed by hardware reg giving its name. */
452 const char *x_reg_names[FIRST_PSEUDO_REGISTER];
6969eb0d
RS
453
454 /* Records which registers can form a particular subreg, with the subreg
455 being identified by its outer mode, inner mode and offset. */
456 hash_table <simplifiable_subregs_hasher> *x_simplifiable_subregs;
6642445b 457};
3245eea0 458
6642445b
RS
459extern struct target_hard_regs default_target_hard_regs;
460#if SWITCHABLE_TARGET
461extern struct target_hard_regs *this_target_hard_regs;
462#else
463#define this_target_hard_regs (&default_target_hard_regs)
464#endif
3245eea0 465
006b72bf
RS
466#define accessible_reg_set \
467 (this_target_hard_regs->x_accessible_reg_set)
468#define operand_reg_set \
469 (this_target_hard_regs->x_operand_reg_set)
6642445b
RS
470#define fixed_regs \
471 (this_target_hard_regs->x_fixed_regs)
472#define fixed_reg_set \
473 (this_target_hard_regs->x_fixed_reg_set)
f80041ef
BS
474#define fixed_nonglobal_reg_set \
475 (this_target_hard_regs->x_fixed_nonglobal_reg_set)
53bee79c 476#ifdef IN_TARGET_CODE
6642445b
RS
477#define call_used_regs \
478 (this_target_hard_regs->x_call_used_regs)
53bee79c 479#endif
df1f0eef
RS
480#define savable_regs \
481 (this_target_hard_regs->x_savable_regs)
7c395881 482#ifdef IN_TARGET_CODE
6642445b
RS
483#define regs_invalidated_by_call \
484 (this_target_hard_regs->x_regs_invalidated_by_call)
a5647ae8
RS
485#define call_used_or_fixed_regs \
486 (regs_invalidated_by_call | fixed_reg_set)
7c395881 487#endif
6642445b
RS
488#define reg_alloc_order \
489 (this_target_hard_regs->x_reg_alloc_order)
490#define inv_reg_alloc_order \
491 (this_target_hard_regs->x_inv_reg_alloc_order)
492#define reg_class_contents \
493 (this_target_hard_regs->x_reg_class_contents)
494#define class_only_fixed_regs \
495 (this_target_hard_regs->x_class_only_fixed_regs)
496#define reg_class_size \
497 (this_target_hard_regs->x_reg_class_size)
498#define reg_class_subclasses \
499 (this_target_hard_regs->x_reg_class_subclasses)
500#define reg_class_subunion \
501 (this_target_hard_regs->x_reg_class_subunion)
502#define reg_class_superunion \
503 (this_target_hard_regs->x_reg_class_superunion)
504#define reg_names \
505 (this_target_hard_regs->x_reg_names)
96a45535 506
778f72f2
RS
507/* Vector indexed by reg class giving its name. */
508
509extern const char * reg_class_names[];
510
0d803030
RS
511/* Given a hard REGN a FROM mode and a TO mode, return true if
512 REGN can change from mode FROM to mode TO. */
513#define REG_CAN_CHANGE_MODE_P(REGN, FROM, TO) \
514 (targetm.can_change_mode_class (FROM, TO, REGNO_REG_CLASS (REGN)))
cff9f8d5 515
7c395881 516#ifdef IN_TARGET_CODE
a365fa06
RS
517/* Return true if register REGNO is either fixed or call-used
518 (aka call-clobbered). */
519
520inline bool
521call_used_or_fixed_reg_p (unsigned int regno)
522{
53bee79c 523 return fixed_regs[regno] || this_target_hard_regs->x_call_used_regs[regno];
a365fa06 524}
7c395881 525#endif
a365fa06 526
88657302 527#endif /* ! GCC_HARD_REG_SET_H */