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ce18efcb | 1 | /* IRA hard register and memory cost calculation for allocnos or pseudos. |
8d9254fc | 2 | Copyright (C) 2006-2020 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
c7131fb2 | 24 | #include "backend.h" |
957060b5 | 25 | #include "target.h" |
058e97ec | 26 | #include "rtl.h" |
c7131fb2 | 27 | #include "tree.h" |
957060b5 | 28 | #include "predict.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
957060b5 | 30 | #include "tm_p.h" |
957060b5 AM |
31 | #include "insn-config.h" |
32 | #include "regs.h" | |
33 | #include "ira.h" | |
34 | #include "ira-int.h" | |
058e97ec | 35 | #include "addresses.h" |
8ff49c29 | 36 | #include "reload.h" |
058e97ec | 37 | |
ce18efcb VM |
38 | /* The flags is set up every time when we calculate pseudo register |
39 | classes through function ira_set_pseudo_classes. */ | |
40 | static bool pseudo_classes_defined_p = false; | |
41 | ||
42 | /* TRUE if we work with allocnos. Otherwise we work with pseudos. */ | |
43 | static bool allocno_p; | |
44 | ||
9aaa7e47 | 45 | /* Number of elements in array `costs'. */ |
ce18efcb | 46 | static int cost_elements_num; |
058e97ec | 47 | |
058e97ec VM |
48 | /* The `costs' struct records the cost of using hard registers of each |
49 | class considered for the calculation and of using memory for each | |
ce18efcb | 50 | allocno or pseudo. */ |
058e97ec VM |
51 | struct costs |
52 | { | |
53 | int mem_cost; | |
54 | /* Costs for register classes start here. We process only some | |
1756cb66 | 55 | allocno classes. */ |
058e97ec VM |
56 | int cost[1]; |
57 | }; | |
58 | ||
aa1c5d72 RS |
59 | #define max_struct_costs_size \ |
60 | (this_target_ira_int->x_max_struct_costs_size) | |
61 | #define init_cost \ | |
62 | (this_target_ira_int->x_init_cost) | |
63 | #define temp_costs \ | |
64 | (this_target_ira_int->x_temp_costs) | |
65 | #define op_costs \ | |
66 | (this_target_ira_int->x_op_costs) | |
67 | #define this_op_costs \ | |
68 | (this_target_ira_int->x_this_op_costs) | |
058e97ec | 69 | |
ce18efcb VM |
70 | /* Costs of each class for each allocno or pseudo. */ |
71 | static struct costs *costs; | |
72 | ||
73 | /* Accumulated costs of each class for each allocno. */ | |
74 | static struct costs *total_allocno_costs; | |
058e97ec | 75 | |
058e97ec | 76 | /* It is the current size of struct costs. */ |
ff304c01 | 77 | static size_t struct_costs_size; |
058e97ec | 78 | |
ce18efcb VM |
79 | /* Return pointer to structure containing costs of allocno or pseudo |
80 | with given NUM in array ARR. */ | |
81 | #define COSTS(arr, num) \ | |
058e97ec VM |
82 | ((struct costs *) ((char *) (arr) + (num) * struct_costs_size)) |
83 | ||
ce18efcb | 84 | /* Return index in COSTS when processing reg with REGNO. */ |
1756cb66 VM |
85 | #define COST_INDEX(regno) (allocno_p \ |
86 | ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \ | |
ce18efcb | 87 | : (int) regno) |
058e97ec | 88 | |
ce18efcb VM |
89 | /* Record register class preferences of each allocno or pseudo. Null |
90 | value means no preferences. It happens on the 1st iteration of the | |
91 | cost calculation. */ | |
92 | static enum reg_class *pref; | |
058e97ec | 93 | |
ce18efcb VM |
94 | /* Allocated buffers for pref. */ |
95 | static enum reg_class *pref_buffer; | |
96 | ||
1756cb66 VM |
97 | /* Record allocno class of each allocno with the same regno. */ |
98 | static enum reg_class *regno_aclass; | |
7db7ed3c | 99 | |
8ff49c29 BS |
100 | /* Record cost gains for not allocating a register with an invariant |
101 | equivalence. */ | |
102 | static int *regno_equiv_gains; | |
103 | ||
058e97ec VM |
104 | /* Execution frequency of the current insn. */ |
105 | static int frequency; | |
106 | ||
107 | \f | |
108 | ||
1756cb66 VM |
109 | /* Info about reg classes whose costs are calculated for a pseudo. */ |
110 | struct cost_classes | |
111 | { | |
112 | /* Number of the cost classes in the subsequent array. */ | |
113 | int num; | |
114 | /* Container of the cost classes. */ | |
115 | enum reg_class classes[N_REG_CLASSES]; | |
116 | /* Map reg class -> index of the reg class in the previous array. | |
df3e3493 | 117 | -1 if it is not a cost class. */ |
1756cb66 VM |
118 | int index[N_REG_CLASSES]; |
119 | /* Map hard regno index of first class in array CLASSES containing | |
120 | the hard regno, -1 otherwise. */ | |
121 | int hard_regno_index[FIRST_PSEUDO_REGISTER]; | |
122 | }; | |
123 | ||
124 | /* Types of pointers to the structure above. */ | |
125 | typedef struct cost_classes *cost_classes_t; | |
126 | typedef const struct cost_classes *const_cost_classes_t; | |
127 | ||
128 | /* Info about cost classes for each pseudo. */ | |
129 | static cost_classes_t *regno_cost_classes; | |
130 | ||
4a8fb1a1 LC |
131 | /* Helper for cost_classes hashing. */ |
132 | ||
7edd9b15 | 133 | struct cost_classes_hasher : pointer_hash <cost_classes> |
1756cb66 | 134 | { |
67f58944 TS |
135 | static inline hashval_t hash (const cost_classes *); |
136 | static inline bool equal (const cost_classes *, const cost_classes *); | |
137 | static inline void remove (cost_classes *); | |
4a8fb1a1 | 138 | }; |
1756cb66 | 139 | |
4a8fb1a1 LC |
140 | /* Returns hash value for cost classes info HV. */ |
141 | inline hashval_t | |
67f58944 | 142 | cost_classes_hasher::hash (const cost_classes *hv) |
4a8fb1a1 | 143 | { |
1756cb66 VM |
144 | return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0); |
145 | } | |
146 | ||
4a8fb1a1 LC |
147 | /* Compares cost classes info HV1 and HV2. */ |
148 | inline bool | |
67f58944 | 149 | cost_classes_hasher::equal (const cost_classes *hv1, const cost_classes *hv2) |
1756cb66 | 150 | { |
c99ebd4d FY |
151 | return (hv1->num == hv2->num |
152 | && memcmp (hv1->classes, hv2->classes, | |
153 | sizeof (enum reg_class) * hv1->num) == 0); | |
1756cb66 VM |
154 | } |
155 | ||
156 | /* Delete cost classes info V from the hash table. */ | |
4a8fb1a1 | 157 | inline void |
67f58944 | 158 | cost_classes_hasher::remove (cost_classes *v) |
1756cb66 VM |
159 | { |
160 | ira_free (v); | |
161 | } | |
162 | ||
163 | /* Hash table of unique cost classes. */ | |
c203e8a7 | 164 | static hash_table<cost_classes_hasher> *cost_classes_htab; |
1756cb66 VM |
165 | |
166 | /* Map allocno class -> cost classes for pseudo of given allocno | |
167 | class. */ | |
168 | static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES]; | |
169 | ||
170 | /* Map mode -> cost classes for pseudo of give mode. */ | |
171 | static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE]; | |
172 | ||
cbfb1548 RS |
173 | /* Cost classes that include all classes in ira_important_classes. */ |
174 | static cost_classes all_cost_classes; | |
175 | ||
176 | /* Use the array of classes in CLASSES_PTR to fill out the rest of | |
177 | the structure. */ | |
178 | static void | |
179 | complete_cost_classes (cost_classes_t classes_ptr) | |
180 | { | |
181 | for (int i = 0; i < N_REG_CLASSES; i++) | |
182 | classes_ptr->index[i] = -1; | |
183 | for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
184 | classes_ptr->hard_regno_index[i] = -1; | |
185 | for (int i = 0; i < classes_ptr->num; i++) | |
186 | { | |
187 | enum reg_class cl = classes_ptr->classes[i]; | |
188 | classes_ptr->index[cl] = i; | |
189 | for (int j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--) | |
190 | { | |
191 | unsigned int hard_regno = ira_class_hard_regs[cl][j]; | |
192 | if (classes_ptr->hard_regno_index[hard_regno] < 0) | |
193 | classes_ptr->hard_regno_index[hard_regno] = i; | |
194 | } | |
195 | } | |
196 | } | |
197 | ||
1756cb66 VM |
198 | /* Initialize info about the cost classes for each pseudo. */ |
199 | static void | |
200 | initiate_regno_cost_classes (void) | |
201 | { | |
202 | int size = sizeof (cost_classes_t) * max_reg_num (); | |
203 | ||
204 | regno_cost_classes = (cost_classes_t *) ira_allocate (size); | |
205 | memset (regno_cost_classes, 0, size); | |
206 | memset (cost_classes_aclass_cache, 0, | |
207 | sizeof (cost_classes_t) * N_REG_CLASSES); | |
208 | memset (cost_classes_mode_cache, 0, | |
209 | sizeof (cost_classes_t) * MAX_MACHINE_MODE); | |
c203e8a7 | 210 | cost_classes_htab = new hash_table<cost_classes_hasher> (200); |
cbfb1548 RS |
211 | all_cost_classes.num = ira_important_classes_num; |
212 | for (int i = 0; i < ira_important_classes_num; i++) | |
213 | all_cost_classes.classes[i] = ira_important_classes[i]; | |
214 | complete_cost_classes (&all_cost_classes); | |
1756cb66 VM |
215 | } |
216 | ||
217 | /* Create new cost classes from cost classes FROM and set up members | |
218 | index and hard_regno_index. Return the new classes. The function | |
219 | implements some common code of two functions | |
220 | setup_regno_cost_classes_by_aclass and | |
221 | setup_regno_cost_classes_by_mode. */ | |
222 | static cost_classes_t | |
223 | setup_cost_classes (cost_classes_t from) | |
224 | { | |
225 | cost_classes_t classes_ptr; | |
1756cb66 VM |
226 | |
227 | classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes)); | |
228 | classes_ptr->num = from->num; | |
cbfb1548 RS |
229 | for (int i = 0; i < from->num; i++) |
230 | classes_ptr->classes[i] = from->classes[i]; | |
231 | complete_cost_classes (classes_ptr); | |
232 | return classes_ptr; | |
233 | } | |
234 | ||
235 | /* Return a version of FULL that only considers registers in REGS that are | |
236 | valid for mode MODE. Both FULL and the returned class are globally | |
237 | allocated. */ | |
238 | static cost_classes_t | |
ef4bddc2 | 239 | restrict_cost_classes (cost_classes_t full, machine_mode mode, |
504279ae | 240 | const_hard_reg_set regs) |
cbfb1548 RS |
241 | { |
242 | static struct cost_classes narrow; | |
243 | int map[N_REG_CLASSES]; | |
244 | narrow.num = 0; | |
245 | for (int i = 0; i < full->num; i++) | |
1756cb66 | 246 | { |
cbfb1548 RS |
247 | /* Assume that we'll drop the class. */ |
248 | map[i] = -1; | |
249 | ||
250 | /* Ignore classes that are too small for the mode. */ | |
251 | enum reg_class cl = full->classes[i]; | |
252 | if (!contains_reg_of_mode[cl][mode]) | |
253 | continue; | |
254 | ||
255 | /* Calculate the set of registers in CL that belong to REGS and | |
256 | are valid for MODE. */ | |
dc333d8f | 257 | HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs; |
d15e5131 RS |
258 | valid_for_cl &= ~(ira_prohibited_class_mode_regs[cl][mode] |
259 | | ira_no_alloc_regs); | |
cbfb1548 RS |
260 | if (hard_reg_set_empty_p (valid_for_cl)) |
261 | continue; | |
262 | ||
263 | /* Don't use this class if the set of valid registers is a subset | |
264 | of an existing class. For example, suppose we have two classes | |
265 | GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose | |
266 | that the mode changes allowed by FR_REGS are not as general as | |
267 | the mode changes allowed by GR_REGS. | |
268 | ||
269 | In this situation, the mode changes for GR_AND_FR_REGS could | |
270 | either be seen as the union or the intersection of the mode | |
271 | changes allowed by the two subclasses. The justification for | |
272 | the union-based definition would be that, if you want a mode | |
273 | change that's only allowed by GR_REGS, you can pick a register | |
274 | from the GR_REGS subclass. The justification for the | |
275 | intersection-based definition would be that every register | |
276 | from the class would allow the mode change. | |
277 | ||
278 | However, if we have a register that needs to be in GR_REGS, | |
279 | using GR_AND_FR_REGS with the intersection-based definition | |
280 | would be too pessimistic, since it would bring in restrictions | |
281 | that only apply to FR_REGS. Conversely, if we have a register | |
282 | that needs to be in FR_REGS, using GR_AND_FR_REGS with the | |
283 | union-based definition would lose the extra restrictions | |
284 | placed on FR_REGS. GR_AND_FR_REGS is therefore only useful | |
285 | for cases where GR_REGS and FP_REGS are both valid. */ | |
286 | int pos; | |
287 | for (pos = 0; pos < narrow.num; ++pos) | |
1756cb66 | 288 | { |
cbfb1548 RS |
289 | enum reg_class cl2 = narrow.classes[pos]; |
290 | if (hard_reg_set_subset_p (valid_for_cl, reg_class_contents[cl2])) | |
291 | break; | |
292 | } | |
293 | map[i] = pos; | |
294 | if (pos == narrow.num) | |
295 | { | |
296 | /* If several classes are equivalent, prefer to use the one | |
297 | that was chosen as the allocno class. */ | |
298 | enum reg_class cl2 = ira_allocno_class_translate[cl]; | |
299 | if (ira_class_hard_regs_num[cl] == ira_class_hard_regs_num[cl2]) | |
300 | cl = cl2; | |
301 | narrow.classes[narrow.num++] = cl; | |
1756cb66 VM |
302 | } |
303 | } | |
cbfb1548 RS |
304 | if (narrow.num == full->num) |
305 | return full; | |
306 | ||
307 | cost_classes **slot = cost_classes_htab->find_slot (&narrow, INSERT); | |
308 | if (*slot == NULL) | |
309 | { | |
310 | cost_classes_t classes = setup_cost_classes (&narrow); | |
311 | /* Map equivalent classes to the representative that we chose above. */ | |
312 | for (int i = 0; i < ira_important_classes_num; i++) | |
313 | { | |
314 | enum reg_class cl = ira_important_classes[i]; | |
315 | int index = full->index[cl]; | |
316 | if (index >= 0) | |
317 | classes->index[cl] = map[index]; | |
318 | } | |
319 | *slot = classes; | |
320 | } | |
321 | return *slot; | |
1756cb66 VM |
322 | } |
323 | ||
324 | /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS. | |
325 | This function is used when we know an initial approximation of | |
326 | allocno class of the pseudo already, e.g. on the second iteration | |
327 | of class cost calculation or after class cost calculation in | |
328 | register-pressure sensitive insn scheduling or register-pressure | |
329 | sensitive loop-invariant motion. */ | |
330 | static void | |
331 | setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass) | |
332 | { | |
333 | static struct cost_classes classes; | |
334 | cost_classes_t classes_ptr; | |
335 | enum reg_class cl; | |
336 | int i; | |
4a8fb1a1 | 337 | cost_classes **slot; |
1756cb66 | 338 | HARD_REG_SET temp, temp2; |
6277a710 | 339 | bool exclude_p; |
1756cb66 VM |
340 | |
341 | if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL) | |
342 | { | |
d15e5131 | 343 | temp = reg_class_contents[aclass] & ~ira_no_alloc_regs; |
6277a710 | 344 | /* We exclude classes from consideration which are subsets of |
165f639c VM |
345 | ACLASS only if ACLASS is an uniform class. */ |
346 | exclude_p = ira_uniform_class_p[aclass]; | |
1756cb66 VM |
347 | classes.num = 0; |
348 | for (i = 0; i < ira_important_classes_num; i++) | |
349 | { | |
350 | cl = ira_important_classes[i]; | |
6277a710 VM |
351 | if (exclude_p) |
352 | { | |
165f639c | 353 | /* Exclude non-uniform classes which are subsets of |
6277a710 | 354 | ACLASS. */ |
d15e5131 | 355 | temp2 = reg_class_contents[cl] & ~ira_no_alloc_regs; |
165f639c | 356 | if (hard_reg_set_subset_p (temp2, temp) && cl != aclass) |
6277a710 VM |
357 | continue; |
358 | } | |
1756cb66 VM |
359 | classes.classes[classes.num++] = cl; |
360 | } | |
c203e8a7 | 361 | slot = cost_classes_htab->find_slot (&classes, INSERT); |
1756cb66 VM |
362 | if (*slot == NULL) |
363 | { | |
364 | classes_ptr = setup_cost_classes (&classes); | |
365 | *slot = classes_ptr; | |
366 | } | |
367 | classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot; | |
368 | } | |
cbfb1548 | 369 | if (regno_reg_rtx[regno] != NULL_RTX) |
dab67d2c RS |
370 | { |
371 | /* Restrict the classes to those that are valid for REGNO's mode | |
372 | (which might for example exclude singleton classes if the mode | |
373 | requires two registers). Also restrict the classes to those that | |
374 | are valid for subregs of REGNO. */ | |
375 | const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno); | |
376 | if (!valid_regs) | |
377 | valid_regs = ®_class_contents[ALL_REGS]; | |
378 | classes_ptr = restrict_cost_classes (classes_ptr, | |
379 | PSEUDO_REGNO_MODE (regno), | |
380 | *valid_regs); | |
381 | } | |
1756cb66 VM |
382 | regno_cost_classes[regno] = classes_ptr; |
383 | } | |
384 | ||
385 | /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can | |
386 | decrease number of cost classes for the pseudo, if hard registers | |
67914693 SL |
387 | of some important classes cannot hold a value of MODE. So the |
388 | pseudo cannot get hard register of some important classes and cost | |
df3e3493 | 389 | calculation for such important classes is only wasting CPU |
1756cb66 VM |
390 | time. */ |
391 | static void | |
ef4bddc2 | 392 | setup_regno_cost_classes_by_mode (int regno, machine_mode mode) |
1756cb66 | 393 | { |
dab67d2c RS |
394 | if (const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno)) |
395 | regno_cost_classes[regno] = restrict_cost_classes (&all_cost_classes, | |
396 | mode, *valid_regs); | |
397 | else | |
398 | { | |
399 | if (cost_classes_mode_cache[mode] == NULL) | |
400 | cost_classes_mode_cache[mode] | |
401 | = restrict_cost_classes (&all_cost_classes, mode, | |
402 | reg_class_contents[ALL_REGS]); | |
403 | regno_cost_classes[regno] = cost_classes_mode_cache[mode]; | |
404 | } | |
1756cb66 VM |
405 | } |
406 | ||
df3e3493 | 407 | /* Finalize info about the cost classes for each pseudo. */ |
1756cb66 VM |
408 | static void |
409 | finish_regno_cost_classes (void) | |
410 | { | |
411 | ira_free (regno_cost_classes); | |
c203e8a7 TS |
412 | delete cost_classes_htab; |
413 | cost_classes_htab = NULL; | |
1756cb66 VM |
414 | } |
415 | ||
416 | \f | |
417 | ||
058e97ec VM |
418 | /* Compute the cost of loading X into (if TO_P is TRUE) or from (if |
419 | TO_P is FALSE) a register of class RCLASS in mode MODE. X must not | |
420 | be a pseudo register. */ | |
421 | static int | |
ef4bddc2 | 422 | copy_cost (rtx x, machine_mode mode, reg_class_t rclass, bool to_p, |
058e97ec VM |
423 | secondary_reload_info *prev_sri) |
424 | { | |
425 | secondary_reload_info sri; | |
fba42e24 | 426 | reg_class_t secondary_class = NO_REGS; |
058e97ec VM |
427 | |
428 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
429 | assuming optimal allocation. */ | |
430 | if (GET_CODE (x) == SCRATCH) | |
431 | return 0; | |
432 | ||
433 | /* Get the class we will actually use for a reload. */ | |
fba42e24 | 434 | rclass = targetm.preferred_reload_class (x, rclass); |
058e97ec VM |
435 | |
436 | /* If we need a secondary reload for an intermediate, the cost is | |
437 | that to load the input into the intermediate register, then to | |
438 | copy it. */ | |
439 | sri.prev_sri = prev_sri; | |
440 | sri.extra_cost = 0; | |
a2faef8e NC |
441 | /* PR 68770: Secondary reload might examine the t_icode field. */ |
442 | sri.t_icode = CODE_FOR_nothing; | |
443 | ||
fba42e24 | 444 | secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri); |
058e97ec | 445 | |
058e97ec | 446 | if (secondary_class != NO_REGS) |
20377b47 | 447 | { |
bac1c6a4 RS |
448 | ira_init_register_move_cost_if_necessary (mode); |
449 | return (ira_register_move_cost[mode][(int) secondary_class][(int) rclass] | |
fba42e24 | 450 | + sri.extra_cost |
20377b47 JH |
451 | + copy_cost (x, mode, secondary_class, to_p, &sri)); |
452 | } | |
058e97ec VM |
453 | |
454 | /* For memory, use the memory move cost, for (hard) registers, use | |
455 | the cost to move between the register classes, and use 2 for | |
456 | everything else (constants). */ | |
457 | if (MEM_P (x) || rclass == NO_REGS) | |
fba42e24 AS |
458 | return sri.extra_cost |
459 | + ira_memory_move_cost[mode][(int) rclass][to_p != 0]; | |
058e97ec | 460 | else if (REG_P (x)) |
20377b47 | 461 | { |
bac1c6a4 RS |
462 | reg_class_t x_class = REGNO_REG_CLASS (REGNO (x)); |
463 | ||
464 | ira_init_register_move_cost_if_necessary (mode); | |
fba42e24 | 465 | return (sri.extra_cost |
bac1c6a4 | 466 | + ira_register_move_cost[mode][(int) x_class][(int) rclass]); |
20377b47 | 467 | } |
058e97ec VM |
468 | else |
469 | /* If this is a constant, we may eventually want to call rtx_cost | |
470 | here. */ | |
471 | return sri.extra_cost + COSTS_N_INSNS (1); | |
472 | } | |
473 | ||
474 | \f | |
475 | ||
476 | /* Record the cost of using memory or hard registers of various | |
477 | classes for the operands in INSN. | |
478 | ||
479 | N_ALTS is the number of alternatives. | |
480 | N_OPS is the number of operands. | |
481 | OPS is an array of the operands. | |
482 | MODES are the modes of the operands, in case any are VOIDmode. | |
483 | CONSTRAINTS are the constraints to use for the operands. This array | |
484 | is modified by this procedure. | |
485 | ||
486 | This procedure works alternative by alternative. For each | |
487 | alternative we assume that we will be able to allocate all allocnos | |
488 | to their ideal register class and calculate the cost of using that | |
489 | alternative. Then we compute, for each operand that is a | |
490 | pseudo-register, the cost of having the allocno allocated to each | |
491 | register class and using it in that alternative. To this cost is | |
492 | added the cost of the alternative. | |
493 | ||
494 | The cost of each class for this insn is its lowest cost among all | |
495 | the alternatives. */ | |
496 | static void | |
497 | record_reg_classes (int n_alts, int n_ops, rtx *ops, | |
ef4bddc2 | 498 | machine_mode *modes, const char **constraints, |
070a1983 | 499 | rtx_insn *insn, enum reg_class *pref) |
058e97ec VM |
500 | { |
501 | int alt; | |
502 | int i, j, k; | |
927425df | 503 | int insn_allows_mem[MAX_RECOG_OPERANDS]; |
0a1eb350 VM |
504 | move_table *move_in_cost, *move_out_cost; |
505 | short (*mem_cost)[2]; | |
927425df VM |
506 | |
507 | for (i = 0; i < n_ops; i++) | |
508 | insn_allows_mem[i] = 0; | |
058e97ec VM |
509 | |
510 | /* Process each alternative, each time minimizing an operand's cost | |
511 | with the cost for each operand in that alternative. */ | |
9840b2fa | 512 | alternative_mask preferred = get_preferred_alternatives (insn); |
058e97ec VM |
513 | for (alt = 0; alt < n_alts; alt++) |
514 | { | |
515 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
516 | int allows_mem[MAX_RECOG_OPERANDS]; | |
bbbbb16a | 517 | enum reg_class rclass; |
058e97ec VM |
518 | int alt_fail = 0; |
519 | int alt_cost = 0, op_cost_add; | |
520 | ||
9840b2fa | 521 | if (!TEST_BIT (preferred, alt)) |
979740a0 BS |
522 | { |
523 | for (i = 0; i < recog_data.n_operands; i++) | |
524 | constraints[i] = skip_alternative (constraints[i]); | |
525 | ||
526 | continue; | |
527 | } | |
528 | ||
058e97ec VM |
529 | for (i = 0; i < n_ops; i++) |
530 | { | |
531 | unsigned char c; | |
532 | const char *p = constraints[i]; | |
533 | rtx op = ops[i]; | |
ef4bddc2 | 534 | machine_mode mode = modes[i]; |
058e97ec VM |
535 | int allows_addr = 0; |
536 | int win = 0; | |
537 | ||
538 | /* Initially show we know nothing about the register class. */ | |
539 | classes[i] = NO_REGS; | |
540 | allows_mem[i] = 0; | |
541 | ||
542 | /* If this operand has no constraints at all, we can | |
543 | conclude nothing about it since anything is valid. */ | |
544 | if (*p == 0) | |
545 | { | |
546 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
547 | memset (this_op_costs[i], 0, struct_costs_size); | |
548 | continue; | |
549 | } | |
550 | ||
551 | /* If this alternative is only relevant when this operand | |
552 | matches a previous operand, we do different things | |
553 | depending on whether this operand is a allocno-reg or not. | |
554 | We must process any modifiers for the operand before we | |
555 | can make this test. */ | |
556 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') | |
557 | p++; | |
558 | ||
d81c5030 | 559 | if (p[0] >= '0' && p[0] <= '0' + i) |
058e97ec VM |
560 | { |
561 | /* Copy class and whether memory is allowed from the | |
562 | matching alternative. Then perform any needed cost | |
563 | computations and/or adjustments. */ | |
564 | j = p[0] - '0'; | |
565 | classes[i] = classes[j]; | |
566 | allows_mem[i] = allows_mem[j]; | |
927425df VM |
567 | if (allows_mem[i]) |
568 | insn_allows_mem[i] = 1; | |
058e97ec VM |
569 | |
570 | if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
571 | { | |
572 | /* If this matches the other operand, we have no | |
573 | added cost and we win. */ | |
574 | if (rtx_equal_p (ops[j], op)) | |
575 | win = 1; | |
576 | /* If we can put the other operand into a register, | |
577 | add to the cost of this alternative the cost to | |
578 | copy this operand to the register used for the | |
579 | other operand. */ | |
580 | else if (classes[j] != NO_REGS) | |
581 | { | |
582 | alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
583 | win = 1; | |
584 | } | |
585 | } | |
586 | else if (! REG_P (ops[j]) | |
587 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
588 | { | |
589 | /* This op is an allocno but the one it matches is | |
590 | not. */ | |
591 | ||
592 | /* If we can't put the other operand into a | |
593 | register, this alternative can't be used. */ | |
594 | ||
595 | if (classes[j] == NO_REGS) | |
596 | alt_fail = 1; | |
597 | /* Otherwise, add to the cost of this alternative | |
598 | the cost to copy the other operand to the hard | |
599 | register used for this operand. */ | |
600 | else | |
601 | alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); | |
602 | } | |
603 | else | |
604 | { | |
605 | /* The costs of this operand are not the same as the | |
606 | other operand since move costs are not symmetric. | |
607 | Moreover, if we cannot tie them, this alternative | |
608 | needs to do a copy, which is one insn. */ | |
609 | struct costs *pp = this_op_costs[i]; | |
1756cb66 VM |
610 | int *pp_costs = pp->cost; |
611 | cost_classes_t cost_classes_ptr | |
612 | = regno_cost_classes[REGNO (op)]; | |
613 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
614 | bool in_p = recog_data.operand_type[i] != OP_OUT; | |
615 | bool out_p = recog_data.operand_type[i] != OP_IN; | |
616 | enum reg_class op_class = classes[i]; | |
1756cb66 VM |
617 | |
618 | ira_init_register_move_cost_if_necessary (mode); | |
619 | if (! in_p) | |
fe82cdfb | 620 | { |
1756cb66 | 621 | ira_assert (out_p); |
0a1eb350 | 622 | if (op_class == NO_REGS) |
1756cb66 | 623 | { |
0a1eb350 VM |
624 | mem_cost = ira_memory_move_cost[mode]; |
625 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
626 | { | |
627 | rclass = cost_classes[k]; | |
628 | pp_costs[k] = mem_cost[rclass][0] * frequency; | |
629 | } | |
630 | } | |
631 | else | |
632 | { | |
633 | move_out_cost = ira_may_move_out_cost[mode]; | |
634 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
635 | { | |
636 | rclass = cost_classes[k]; | |
637 | pp_costs[k] | |
638 | = move_out_cost[op_class][rclass] * frequency; | |
639 | } | |
1756cb66 VM |
640 | } |
641 | } | |
642 | else if (! out_p) | |
643 | { | |
644 | ira_assert (in_p); | |
0a1eb350 | 645 | if (op_class == NO_REGS) |
1756cb66 | 646 | { |
0a1eb350 VM |
647 | mem_cost = ira_memory_move_cost[mode]; |
648 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
649 | { | |
650 | rclass = cost_classes[k]; | |
651 | pp_costs[k] = mem_cost[rclass][1] * frequency; | |
652 | } | |
653 | } | |
654 | else | |
655 | { | |
656 | move_in_cost = ira_may_move_in_cost[mode]; | |
657 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
658 | { | |
659 | rclass = cost_classes[k]; | |
660 | pp_costs[k] | |
661 | = move_in_cost[rclass][op_class] * frequency; | |
662 | } | |
1756cb66 VM |
663 | } |
664 | } | |
665 | else | |
666 | { | |
0a1eb350 | 667 | if (op_class == NO_REGS) |
1756cb66 | 668 | { |
0a1eb350 VM |
669 | mem_cost = ira_memory_move_cost[mode]; |
670 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
671 | { | |
672 | rclass = cost_classes[k]; | |
673 | pp_costs[k] = ((mem_cost[rclass][0] | |
674 | + mem_cost[rclass][1]) | |
675 | * frequency); | |
676 | } | |
677 | } | |
678 | else | |
679 | { | |
680 | move_in_cost = ira_may_move_in_cost[mode]; | |
681 | move_out_cost = ira_may_move_out_cost[mode]; | |
682 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
683 | { | |
684 | rclass = cost_classes[k]; | |
685 | pp_costs[k] = ((move_in_cost[rclass][op_class] | |
686 | + move_out_cost[op_class][rclass]) | |
687 | * frequency); | |
688 | } | |
1756cb66 | 689 | } |
058e97ec VM |
690 | } |
691 | ||
692 | /* If the alternative actually allows memory, make | |
693 | things a bit cheaper since we won't need an extra | |
694 | insn to load it. */ | |
695 | pp->mem_cost | |
1756cb66 VM |
696 | = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0) |
697 | + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0) | |
058e97ec | 698 | - allows_mem[i]) * frequency; |
927425df | 699 | |
1756cb66 VM |
700 | /* If we have assigned a class to this allocno in |
701 | our first pass, add a cost to this alternative | |
702 | corresponding to what we would add if this | |
703 | allocno were not in the appropriate class. */ | |
ce18efcb | 704 | if (pref) |
058e97ec | 705 | { |
ce18efcb | 706 | enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
058e97ec VM |
707 | |
708 | if (pref_class == NO_REGS) | |
709 | alt_cost | |
1756cb66 VM |
710 | += ((out_p |
711 | ? ira_memory_move_cost[mode][op_class][0] : 0) | |
712 | + (in_p | |
713 | ? ira_memory_move_cost[mode][op_class][1] | |
058e97ec VM |
714 | : 0)); |
715 | else if (ira_reg_class_intersect | |
1756cb66 VM |
716 | [pref_class][op_class] == NO_REGS) |
717 | alt_cost | |
718 | += ira_register_move_cost[mode][pref_class][op_class]; | |
058e97ec VM |
719 | } |
720 | if (REGNO (ops[i]) != REGNO (ops[j]) | |
721 | && ! find_reg_note (insn, REG_DEAD, op)) | |
722 | alt_cost += 2; | |
723 | ||
d81c5030 | 724 | p++; |
058e97ec VM |
725 | } |
726 | } | |
b8698a0f | 727 | |
058e97ec VM |
728 | /* Scan all the constraint letters. See if the operand |
729 | matches any of the constraints. Collect the valid | |
730 | register classes and see if this operand accepts | |
731 | memory. */ | |
732 | while ((c = *p)) | |
733 | { | |
734 | switch (c) | |
735 | { | |
058e97ec VM |
736 | case '*': |
737 | /* Ignore the next letter for this pass. */ | |
738 | c = *++p; | |
739 | break; | |
740 | ||
d1457701 VM |
741 | case '^': |
742 | alt_cost += 2; | |
743 | break; | |
744 | ||
058e97ec VM |
745 | case '?': |
746 | alt_cost += 2; | |
058e97ec VM |
747 | break; |
748 | ||
749 | case 'g': | |
750 | if (MEM_P (op) | |
751 | || (CONSTANT_P (op) | |
752 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) | |
753 | win = 1; | |
927425df | 754 | insn_allows_mem[i] = allows_mem[i] = 1; |
1756cb66 | 755 | classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; |
058e97ec VM |
756 | break; |
757 | ||
758 | default: | |
777e635f RS |
759 | enum constraint_num cn = lookup_constraint (p); |
760 | enum reg_class cl; | |
761 | switch (get_constraint_type (cn)) | |
058e97ec | 762 | { |
777e635f RS |
763 | case CT_REGISTER: |
764 | cl = reg_class_for_constraint (cn); | |
765 | if (cl != NO_REGS) | |
766 | classes[i] = ira_reg_class_subunion[classes[i]][cl]; | |
767 | break; | |
768 | ||
d9c35eee RS |
769 | case CT_CONST_INT: |
770 | if (CONST_INT_P (op) | |
771 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
772 | win = 1; | |
773 | break; | |
774 | ||
777e635f | 775 | case CT_MEMORY: |
058e97ec | 776 | /* Every MEM can be reloaded to fit. */ |
927425df | 777 | insn_allows_mem[i] = allows_mem[i] = 1; |
058e97ec VM |
778 | if (MEM_P (op)) |
779 | win = 1; | |
777e635f RS |
780 | break; |
781 | ||
9eb1ca69 VM |
782 | case CT_SPECIAL_MEMORY: |
783 | insn_allows_mem[i] = allows_mem[i] = 1; | |
784 | if (MEM_P (op) && constraint_satisfied_p (op, cn)) | |
785 | win = 1; | |
786 | break; | |
787 | ||
777e635f | 788 | case CT_ADDRESS: |
058e97ec VM |
789 | /* Every address can be reloaded to fit. */ |
790 | allows_addr = 1; | |
777e635f RS |
791 | if (address_operand (op, GET_MODE (op)) |
792 | || constraint_satisfied_p (op, cn)) | |
058e97ec VM |
793 | win = 1; |
794 | /* We know this operand is an address, so we | |
795 | want it to be allocated to a hard register | |
796 | that can be the base of an address, | |
797 | i.e. BASE_REG_CLASS. */ | |
798 | classes[i] | |
1756cb66 | 799 | = ira_reg_class_subunion[classes[i]] |
86fc3d06 UW |
800 | [base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, |
801 | ADDRESS, SCRATCH)]; | |
777e635f RS |
802 | break; |
803 | ||
804 | case CT_FIXED_FORM: | |
805 | if (constraint_satisfied_p (op, cn)) | |
806 | win = 1; | |
807 | break; | |
058e97ec | 808 | } |
058e97ec VM |
809 | break; |
810 | } | |
811 | p += CONSTRAINT_LEN (c, p); | |
812 | if (c == ',') | |
813 | break; | |
814 | } | |
815 | ||
816 | constraints[i] = p; | |
817 | ||
3d8e4920 RS |
818 | if (alt_fail) |
819 | break; | |
820 | ||
058e97ec VM |
821 | /* How we account for this operand now depends on whether it |
822 | is a pseudo register or not. If it is, we first check if | |
823 | any register classes are valid. If not, we ignore this | |
824 | alternative, since we want to assume that all allocnos get | |
825 | allocated for register preferencing. If some register | |
826 | class is valid, compute the costs of moving the allocno | |
827 | into that class. */ | |
828 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
829 | { | |
f4e075e7 | 830 | if (classes[i] == NO_REGS && ! allows_mem[i]) |
058e97ec VM |
831 | { |
832 | /* We must always fail if the operand is a REG, but | |
f4e075e7 VM |
833 | we did not find a suitable class and memory is |
834 | not allowed. | |
058e97ec VM |
835 | |
836 | Otherwise we may perform an uninitialized read | |
837 | from this_op_costs after the `continue' statement | |
838 | below. */ | |
839 | alt_fail = 1; | |
840 | } | |
841 | else | |
842 | { | |
1756cb66 | 843 | unsigned int regno = REGNO (op); |
058e97ec | 844 | struct costs *pp = this_op_costs[i]; |
1756cb66 VM |
845 | int *pp_costs = pp->cost; |
846 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
847 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
848 | bool in_p = recog_data.operand_type[i] != OP_OUT; | |
849 | bool out_p = recog_data.operand_type[i] != OP_IN; | |
850 | enum reg_class op_class = classes[i]; | |
1756cb66 VM |
851 | |
852 | ira_init_register_move_cost_if_necessary (mode); | |
853 | if (! in_p) | |
fe82cdfb | 854 | { |
1756cb66 | 855 | ira_assert (out_p); |
f4e075e7 | 856 | if (op_class == NO_REGS) |
1756cb66 | 857 | { |
f4e075e7 VM |
858 | mem_cost = ira_memory_move_cost[mode]; |
859 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
860 | { | |
861 | rclass = cost_classes[k]; | |
862 | pp_costs[k] = mem_cost[rclass][0] * frequency; | |
863 | } | |
864 | } | |
865 | else | |
866 | { | |
867 | move_out_cost = ira_may_move_out_cost[mode]; | |
868 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
869 | { | |
870 | rclass = cost_classes[k]; | |
871 | pp_costs[k] | |
872 | = move_out_cost[op_class][rclass] * frequency; | |
873 | } | |
1756cb66 VM |
874 | } |
875 | } | |
876 | else if (! out_p) | |
877 | { | |
878 | ira_assert (in_p); | |
f4e075e7 | 879 | if (op_class == NO_REGS) |
1756cb66 | 880 | { |
f4e075e7 VM |
881 | mem_cost = ira_memory_move_cost[mode]; |
882 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
883 | { | |
884 | rclass = cost_classes[k]; | |
885 | pp_costs[k] = mem_cost[rclass][1] * frequency; | |
886 | } | |
887 | } | |
888 | else | |
889 | { | |
890 | move_in_cost = ira_may_move_in_cost[mode]; | |
891 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
892 | { | |
893 | rclass = cost_classes[k]; | |
894 | pp_costs[k] | |
895 | = move_in_cost[rclass][op_class] * frequency; | |
896 | } | |
1756cb66 VM |
897 | } |
898 | } | |
899 | else | |
900 | { | |
f4e075e7 | 901 | if (op_class == NO_REGS) |
1756cb66 | 902 | { |
f4e075e7 VM |
903 | mem_cost = ira_memory_move_cost[mode]; |
904 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
905 | { | |
906 | rclass = cost_classes[k]; | |
907 | pp_costs[k] = ((mem_cost[rclass][0] | |
908 | + mem_cost[rclass][1]) | |
909 | * frequency); | |
910 | } | |
911 | } | |
912 | else | |
913 | { | |
914 | move_in_cost = ira_may_move_in_cost[mode]; | |
915 | move_out_cost = ira_may_move_out_cost[mode]; | |
916 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
917 | { | |
918 | rclass = cost_classes[k]; | |
919 | pp_costs[k] = ((move_in_cost[rclass][op_class] | |
920 | + move_out_cost[op_class][rclass]) | |
921 | * frequency); | |
922 | } | |
1756cb66 | 923 | } |
058e97ec VM |
924 | } |
925 | ||
0a1eb350 VM |
926 | if (op_class == NO_REGS) |
927 | /* Although we don't need insn to reload from | |
928 | memory, still accessing memory is usually more | |
929 | expensive than a register. */ | |
930 | pp->mem_cost = frequency; | |
931 | else | |
932 | /* If the alternative actually allows memory, make | |
933 | things a bit cheaper since we won't need an | |
934 | extra insn to load it. */ | |
f4e075e7 VM |
935 | pp->mem_cost |
936 | = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0) | |
937 | + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0) | |
938 | - allows_mem[i]) * frequency; | |
1756cb66 VM |
939 | /* If we have assigned a class to this allocno in |
940 | our first pass, add a cost to this alternative | |
941 | corresponding to what we would add if this | |
942 | allocno were not in the appropriate class. */ | |
ce18efcb | 943 | if (pref) |
058e97ec | 944 | { |
ce18efcb | 945 | enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
058e97ec VM |
946 | |
947 | if (pref_class == NO_REGS) | |
f4e075e7 VM |
948 | { |
949 | if (op_class != NO_REGS) | |
950 | alt_cost | |
951 | += ((out_p | |
952 | ? ira_memory_move_cost[mode][op_class][0] | |
953 | : 0) | |
954 | + (in_p | |
955 | ? ira_memory_move_cost[mode][op_class][1] | |
956 | : 0)); | |
957 | } | |
958 | else if (op_class == NO_REGS) | |
058e97ec | 959 | alt_cost |
1756cb66 | 960 | += ((out_p |
f4e075e7 VM |
961 | ? ira_memory_move_cost[mode][pref_class][1] |
962 | : 0) | |
1756cb66 | 963 | + (in_p |
f4e075e7 | 964 | ? ira_memory_move_cost[mode][pref_class][0] |
058e97ec | 965 | : 0)); |
1756cb66 | 966 | else if (ira_reg_class_intersect[pref_class][op_class] |
058e97ec | 967 | == NO_REGS) |
f4e075e7 VM |
968 | alt_cost += (ira_register_move_cost |
969 | [mode][pref_class][op_class]); | |
058e97ec VM |
970 | } |
971 | } | |
972 | } | |
973 | ||
974 | /* Otherwise, if this alternative wins, either because we | |
975 | have already determined that or if we have a hard | |
976 | register of the proper class, there is no cost for this | |
977 | alternative. */ | |
978 | else if (win || (REG_P (op) | |
979 | && reg_fits_class_p (op, classes[i], | |
980 | 0, GET_MODE (op)))) | |
981 | ; | |
982 | ||
983 | /* If registers are valid, the cost of this alternative | |
984 | includes copying the object to and/or from a | |
985 | register. */ | |
986 | else if (classes[i] != NO_REGS) | |
987 | { | |
988 | if (recog_data.operand_type[i] != OP_OUT) | |
989 | alt_cost += copy_cost (op, mode, classes[i], 1, NULL); | |
990 | ||
991 | if (recog_data.operand_type[i] != OP_IN) | |
992 | alt_cost += copy_cost (op, mode, classes[i], 0, NULL); | |
993 | } | |
994 | /* The only other way this alternative can be used is if | |
995 | this is a constant that could be placed into memory. */ | |
996 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) | |
997 | alt_cost += ira_memory_move_cost[mode][classes[i]][1]; | |
998 | else | |
999 | alt_fail = 1; | |
3d8e4920 RS |
1000 | |
1001 | if (alt_fail) | |
1002 | break; | |
058e97ec VM |
1003 | } |
1004 | ||
1005 | if (alt_fail) | |
3d8e4920 RS |
1006 | { |
1007 | /* The loop above might have exited early once the failure | |
1008 | was seen. Skip over the constraints for the remaining | |
1009 | operands. */ | |
1010 | i += 1; | |
1011 | for (; i < n_ops; ++i) | |
1012 | constraints[i] = skip_alternative (constraints[i]); | |
1013 | continue; | |
1014 | } | |
058e97ec VM |
1015 | |
1016 | op_cost_add = alt_cost * frequency; | |
1017 | /* Finally, update the costs with the information we've | |
1018 | calculated about this alternative. */ | |
1019 | for (i = 0; i < n_ops; i++) | |
1020 | if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1021 | { | |
1022 | struct costs *pp = op_costs[i], *qq = this_op_costs[i]; | |
1756cb66 | 1023 | int *pp_costs = pp->cost, *qq_costs = qq->cost; |
058e97ec | 1024 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
1756cb66 VM |
1025 | cost_classes_t cost_classes_ptr |
1026 | = regno_cost_classes[REGNO (ops[i])]; | |
058e97ec VM |
1027 | |
1028 | pp->mem_cost = MIN (pp->mem_cost, | |
1029 | (qq->mem_cost + op_cost_add) * scale); | |
1030 | ||
1756cb66 VM |
1031 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) |
1032 | pp_costs[k] | |
1033 | = MIN (pp_costs[k], (qq_costs[k] + op_cost_add) * scale); | |
058e97ec VM |
1034 | } |
1035 | } | |
1036 | ||
ce18efcb VM |
1037 | if (allocno_p) |
1038 | for (i = 0; i < n_ops; i++) | |
1039 | { | |
1040 | ira_allocno_t a; | |
1041 | rtx op = ops[i]; | |
b8698a0f | 1042 | |
ce18efcb VM |
1043 | if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
1044 | continue; | |
1045 | a = ira_curr_regno_allocno_map [REGNO (op)]; | |
1046 | if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0) | |
1047 | ALLOCNO_BAD_SPILL_P (a) = true; | |
1048 | } | |
927425df | 1049 | |
058e97ec VM |
1050 | } |
1051 | ||
1052 | \f | |
1053 | ||
1054 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ | |
1055 | static inline bool | |
1056 | ok_for_index_p_nonstrict (rtx reg) | |
1057 | { | |
1058 | unsigned regno = REGNO (reg); | |
1059 | ||
1060 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
1061 | } | |
1062 | ||
1063 | /* A version of regno_ok_for_base_p for use here, when all | |
1064 | pseudo-registers should count as OK. Arguments as for | |
1065 | regno_ok_for_base_p. */ | |
1066 | static inline bool | |
ef4bddc2 | 1067 | ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as, |
058e97ec VM |
1068 | enum rtx_code outer_code, enum rtx_code index_code) |
1069 | { | |
1070 | unsigned regno = REGNO (reg); | |
1071 | ||
1072 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1073 | return true; | |
86fc3d06 | 1074 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); |
058e97ec VM |
1075 | } |
1076 | ||
1077 | /* Record the pseudo registers we must reload into hard registers in a | |
1078 | subexpression of a memory address, X. | |
1079 | ||
1080 | If CONTEXT is 0, we are looking at the base part of an address, | |
1081 | otherwise we are looking at the index part. | |
1082 | ||
86fc3d06 UW |
1083 | MODE and AS are the mode and address space of the memory reference; |
1084 | OUTER_CODE and INDEX_CODE give the context that the rtx appears in. | |
1085 | These four arguments are passed down to base_reg_class. | |
058e97ec VM |
1086 | |
1087 | SCALE is twice the amount to multiply the cost by (it is twice so | |
1088 | we can represent half-cost adjustments). */ | |
1089 | static void | |
ef4bddc2 | 1090 | record_address_regs (machine_mode mode, addr_space_t as, rtx x, |
86fc3d06 UW |
1091 | int context, enum rtx_code outer_code, |
1092 | enum rtx_code index_code, int scale) | |
058e97ec VM |
1093 | { |
1094 | enum rtx_code code = GET_CODE (x); | |
1095 | enum reg_class rclass; | |
1096 | ||
1097 | if (context == 1) | |
1098 | rclass = INDEX_REG_CLASS; | |
1099 | else | |
86fc3d06 | 1100 | rclass = base_reg_class (mode, as, outer_code, index_code); |
058e97ec VM |
1101 | |
1102 | switch (code) | |
1103 | { | |
1104 | case CONST_INT: | |
1105 | case CONST: | |
1106 | case CC0: | |
1107 | case PC: | |
1108 | case SYMBOL_REF: | |
1109 | case LABEL_REF: | |
1110 | return; | |
1111 | ||
1112 | case PLUS: | |
1113 | /* When we have an address that is a sum, we must determine | |
1114 | whether registers are "base" or "index" regs. If there is a | |
1115 | sum of two registers, we must choose one to be the "base". | |
1116 | Luckily, we can use the REG_POINTER to make a good choice | |
1117 | most of the time. We only need to do this on machines that | |
1118 | can have two registers in an address and where the base and | |
1119 | index register classes are different. | |
1120 | ||
1121 | ??? This code used to set REGNO_POINTER_FLAG in some cases, | |
1122 | but that seems bogus since it should only be set when we are | |
1123 | sure the register is being used as a pointer. */ | |
1124 | { | |
1125 | rtx arg0 = XEXP (x, 0); | |
1126 | rtx arg1 = XEXP (x, 1); | |
1127 | enum rtx_code code0 = GET_CODE (arg0); | |
1128 | enum rtx_code code1 = GET_CODE (arg1); | |
1129 | ||
1130 | /* Look inside subregs. */ | |
1131 | if (code0 == SUBREG) | |
1132 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
1133 | if (code1 == SUBREG) | |
1134 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
1135 | ||
9f1c93df | 1136 | /* If index registers do not appear, or coincide with base registers, |
058e97ec VM |
1137 | just record registers in any non-constant operands. We |
1138 | assume here, as well as in the tests below, that all | |
1139 | addresses are in canonical form. */ | |
9f1c93df AM |
1140 | if (MAX_REGS_PER_ADDRESS == 1 |
1141 | || INDEX_REG_CLASS == base_reg_class (VOIDmode, as, PLUS, SCRATCH)) | |
058e97ec | 1142 | { |
86fc3d06 | 1143 | record_address_regs (mode, as, arg0, context, PLUS, code1, scale); |
058e97ec | 1144 | if (! CONSTANT_P (arg1)) |
86fc3d06 | 1145 | record_address_regs (mode, as, arg1, context, PLUS, code0, scale); |
058e97ec VM |
1146 | } |
1147 | ||
1148 | /* If the second operand is a constant integer, it doesn't | |
1149 | change what class the first operand must be. */ | |
33ffb5c5 | 1150 | else if (CONST_SCALAR_INT_P (arg1)) |
86fc3d06 | 1151 | record_address_regs (mode, as, arg0, context, PLUS, code1, scale); |
058e97ec VM |
1152 | /* If the second operand is a symbolic constant, the first |
1153 | operand must be an index register. */ | |
1154 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
86fc3d06 | 1155 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale); |
058e97ec VM |
1156 | /* If both operands are registers but one is already a hard |
1157 | register of index or reg-base class, give the other the | |
1158 | class that the hard register is not. */ | |
1159 | else if (code0 == REG && code1 == REG | |
1160 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
86fc3d06 | 1161 | && (ok_for_base_p_nonstrict (arg0, mode, as, PLUS, REG) |
058e97ec | 1162 | || ok_for_index_p_nonstrict (arg0))) |
86fc3d06 UW |
1163 | record_address_regs (mode, as, arg1, |
1164 | ok_for_base_p_nonstrict (arg0, mode, as, | |
1165 | PLUS, REG) ? 1 : 0, | |
058e97ec VM |
1166 | PLUS, REG, scale); |
1167 | else if (code0 == REG && code1 == REG | |
1168 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
86fc3d06 | 1169 | && (ok_for_base_p_nonstrict (arg1, mode, as, PLUS, REG) |
058e97ec | 1170 | || ok_for_index_p_nonstrict (arg1))) |
86fc3d06 UW |
1171 | record_address_regs (mode, as, arg0, |
1172 | ok_for_base_p_nonstrict (arg1, mode, as, | |
1173 | PLUS, REG) ? 1 : 0, | |
058e97ec VM |
1174 | PLUS, REG, scale); |
1175 | /* If one operand is known to be a pointer, it must be the | |
1176 | base with the other operand the index. Likewise if the | |
1177 | other operand is a MULT. */ | |
1178 | else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT) | |
1179 | { | |
86fc3d06 UW |
1180 | record_address_regs (mode, as, arg0, 0, PLUS, code1, scale); |
1181 | record_address_regs (mode, as, arg1, 1, PLUS, code0, scale); | |
058e97ec VM |
1182 | } |
1183 | else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT) | |
1184 | { | |
86fc3d06 UW |
1185 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale); |
1186 | record_address_regs (mode, as, arg1, 0, PLUS, code0, scale); | |
058e97ec VM |
1187 | } |
1188 | /* Otherwise, count equal chances that each might be a base or | |
1189 | index register. This case should be rare. */ | |
1190 | else | |
1191 | { | |
86fc3d06 UW |
1192 | record_address_regs (mode, as, arg0, 0, PLUS, code1, scale / 2); |
1193 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale / 2); | |
1194 | record_address_regs (mode, as, arg1, 0, PLUS, code0, scale / 2); | |
1195 | record_address_regs (mode, as, arg1, 1, PLUS, code0, scale / 2); | |
058e97ec VM |
1196 | } |
1197 | } | |
1198 | break; | |
1199 | ||
1200 | /* Double the importance of an allocno that is incremented or | |
1201 | decremented, since it would take two extra insns if it ends | |
1202 | up in the wrong place. */ | |
1203 | case POST_MODIFY: | |
1204 | case PRE_MODIFY: | |
86fc3d06 | 1205 | record_address_regs (mode, as, XEXP (x, 0), 0, code, |
058e97ec VM |
1206 | GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); |
1207 | if (REG_P (XEXP (XEXP (x, 1), 1))) | |
86fc3d06 | 1208 | record_address_regs (mode, as, XEXP (XEXP (x, 1), 1), 1, code, REG, |
058e97ec VM |
1209 | 2 * scale); |
1210 | break; | |
1211 | ||
1212 | case POST_INC: | |
1213 | case PRE_INC: | |
1214 | case POST_DEC: | |
1215 | case PRE_DEC: | |
1216 | /* Double the importance of an allocno that is incremented or | |
1217 | decremented, since it would take two extra insns if it ends | |
9aaa7e47 | 1218 | up in the wrong place. */ |
86fc3d06 | 1219 | record_address_regs (mode, as, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); |
058e97ec VM |
1220 | break; |
1221 | ||
1222 | case REG: | |
1223 | { | |
1224 | struct costs *pp; | |
1756cb66 | 1225 | int *pp_costs; |
bbbbb16a | 1226 | enum reg_class i; |
1756cb66 VM |
1227 | int k, regno, add_cost; |
1228 | cost_classes_t cost_classes_ptr; | |
1229 | enum reg_class *cost_classes; | |
1230 | move_table *move_in_cost; | |
058e97ec VM |
1231 | |
1232 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1233 | break; | |
1234 | ||
1756cb66 | 1235 | regno = REGNO (x); |
ce18efcb | 1236 | if (allocno_p) |
1756cb66 VM |
1237 | ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) = true; |
1238 | pp = COSTS (costs, COST_INDEX (regno)); | |
1239 | add_cost = (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; | |
1240 | if (INT_MAX - add_cost < pp->mem_cost) | |
1241 | pp->mem_cost = INT_MAX; | |
1242 | else | |
1243 | pp->mem_cost += add_cost; | |
1244 | cost_classes_ptr = regno_cost_classes[regno]; | |
1245 | cost_classes = cost_classes_ptr->classes; | |
1246 | pp_costs = pp->cost; | |
1247 | ira_init_register_move_cost_if_necessary (Pmode); | |
1248 | move_in_cost = ira_may_move_in_cost[Pmode]; | |
1249 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
058e97ec VM |
1250 | { |
1251 | i = cost_classes[k]; | |
1756cb66 VM |
1252 | add_cost = (move_in_cost[i][rclass] * scale) / 2; |
1253 | if (INT_MAX - add_cost < pp_costs[k]) | |
1254 | pp_costs[k] = INT_MAX; | |
eeae9314 | 1255 | else |
1756cb66 | 1256 | pp_costs[k] += add_cost; |
058e97ec VM |
1257 | } |
1258 | } | |
1259 | break; | |
1260 | ||
1261 | default: | |
1262 | { | |
1263 | const char *fmt = GET_RTX_FORMAT (code); | |
1264 | int i; | |
1265 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1266 | if (fmt[i] == 'e') | |
86fc3d06 | 1267 | record_address_regs (mode, as, XEXP (x, i), context, code, SCRATCH, |
058e97ec VM |
1268 | scale); |
1269 | } | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | \f | |
1274 | ||
1275 | /* Calculate the costs of insn operands. */ | |
1276 | static void | |
070a1983 | 1277 | record_operand_costs (rtx_insn *insn, enum reg_class *pref) |
058e97ec VM |
1278 | { |
1279 | const char *constraints[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 1280 | machine_mode modes[MAX_RECOG_OPERANDS]; |
3b6d1699 | 1281 | rtx set; |
058e97ec VM |
1282 | int i; |
1283 | ||
eeae9314 VM |
1284 | if ((set = single_set (insn)) != NULL_RTX |
1285 | /* In rare cases the single set insn might have less 2 operands | |
1286 | as the source can be a fixed special reg. */ | |
1287 | && recog_data.n_operands > 1 | |
1288 | && recog_data.operand[0] == SET_DEST (set) | |
1289 | && recog_data.operand[1] == SET_SRC (set)) | |
1290 | { | |
1291 | int regno, other_regno; | |
1292 | rtx dest = SET_DEST (set); | |
1293 | rtx src = SET_SRC (set); | |
1294 | ||
1295 | if (GET_CODE (dest) == SUBREG | |
1296 | && known_eq (GET_MODE_SIZE (GET_MODE (dest)), | |
1297 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))))) | |
1298 | dest = SUBREG_REG (dest); | |
1299 | if (GET_CODE (src) == SUBREG | |
1300 | && known_eq (GET_MODE_SIZE (GET_MODE (src)), | |
1301 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) | |
1302 | src = SUBREG_REG (src); | |
1303 | if (REG_P (src) && REG_P (dest) | |
1304 | && (((regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
1305 | && (other_regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER) | |
1306 | || ((regno = REGNO (dest)) >= FIRST_PSEUDO_REGISTER | |
1307 | && (other_regno = REGNO (src)) < FIRST_PSEUDO_REGISTER))) | |
1308 | { | |
1309 | machine_mode mode = GET_MODE (SET_SRC (set)); | |
1310 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
1311 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
36d070a7 | 1312 | reg_class_t rclass, hard_reg_class, pref_class, bigger_hard_reg_class; |
eeae9314 | 1313 | int cost, k; |
36d070a7 | 1314 | move_table *move_costs; |
eeae9314 VM |
1315 | bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src)); |
1316 | ||
12422bc8 | 1317 | ira_init_register_move_cost_if_necessary (mode); |
36d070a7 | 1318 | move_costs = ira_register_move_cost[mode]; |
eeae9314 | 1319 | hard_reg_class = REGNO_REG_CLASS (other_regno); |
36d070a7 | 1320 | bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class]; |
795a6c67 | 1321 | /* Target code may return any cost for mode which does not |
700d4cb0 | 1322 | fit the hard reg class (e.g. DImode for AREG on |
795a6c67 VM |
1323 | i386). Check this and use a bigger class to get the |
1324 | right cost. */ | |
66a0970a VM |
1325 | if (bigger_hard_reg_class != NO_REGS |
1326 | && ! ira_hard_reg_in_set_p (other_regno, mode, | |
1327 | reg_class_contents[hard_reg_class])) | |
36d070a7 | 1328 | hard_reg_class = bigger_hard_reg_class; |
eeae9314 VM |
1329 | i = regno == (int) REGNO (src) ? 1 : 0; |
1330 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1331 | { | |
1332 | rclass = cost_classes[k]; | |
36d070a7 VM |
1333 | cost = (i == 0 |
1334 | ? move_costs[hard_reg_class][rclass] | |
1335 | : move_costs[rclass][hard_reg_class]); | |
36d070a7 VM |
1336 | |
1337 | op_costs[i]->cost[k] = cost * frequency; | |
eeae9314 VM |
1338 | /* If we have assigned a class to this allocno in our |
1339 | first pass, add a cost to this alternative | |
1340 | corresponding to what we would add if this allocno | |
1341 | were not in the appropriate class. */ | |
1342 | if (pref) | |
1343 | { | |
1344 | if ((pref_class = pref[COST_INDEX (regno)]) == NO_REGS) | |
1345 | op_costs[i]->cost[k] | |
1346 | += ((i == 0 ? ira_memory_move_cost[mode][rclass][0] : 0) | |
1347 | + (i == 1 ? ira_memory_move_cost[mode][rclass][1] : 0) | |
1348 | * frequency); | |
1349 | else if (ira_reg_class_intersect[pref_class][rclass] | |
1350 | == NO_REGS) | |
1351 | op_costs[i]->cost[k] | |
36d070a7 | 1352 | += (move_costs[pref_class][rclass] |
eeae9314 VM |
1353 | * frequency); |
1354 | } | |
1355 | /* If this insn is a single set copying operand 1 to | |
1356 | operand 0 and one operand is an allocno with the | |
1357 | other a hard reg or an allocno that prefers a hard | |
1358 | register that is in its own register class then we | |
1359 | may want to adjust the cost of that register class to | |
1360 | -1. | |
1361 | ||
1362 | Avoid the adjustment if the source does not die to | |
1363 | avoid stressing of register allocator by preferencing | |
1364 | two colliding registers into single class. */ | |
1365 | if (dead_p | |
1366 | && TEST_HARD_REG_BIT (reg_class_contents[rclass], other_regno) | |
1367 | && (reg_class_size[(int) rclass] | |
1368 | == (ira_reg_class_max_nregs | |
1369 | [(int) rclass][(int) GET_MODE(src)]))) | |
1370 | { | |
1371 | if (reg_class_size[rclass] == 1) | |
1372 | op_costs[i]->cost[k] = -frequency; | |
1373 | else if (in_hard_reg_set_p (reg_class_contents[rclass], | |
1374 | GET_MODE(src), other_regno)) | |
1375 | op_costs[i]->cost[k] = -frequency; | |
1376 | } | |
1377 | } | |
1378 | op_costs[i]->mem_cost | |
1379 | = ira_memory_move_cost[mode][hard_reg_class][i] * frequency; | |
1380 | if (pref && (pref_class = pref[COST_INDEX (regno)]) != NO_REGS) | |
1381 | op_costs[i]->mem_cost | |
1382 | += ira_memory_move_cost[mode][pref_class][i] * frequency; | |
1383 | return; | |
1384 | } | |
1385 | } | |
1386 | ||
058e97ec VM |
1387 | for (i = 0; i < recog_data.n_operands; i++) |
1388 | { | |
1389 | constraints[i] = recog_data.constraints[i]; | |
1390 | modes[i] = recog_data.operand_mode[i]; | |
1391 | } | |
1392 | ||
1393 | /* If we get here, we are set up to record the costs of all the | |
1394 | operands for this insn. Start by initializing the costs. Then | |
1395 | handle any address registers. Finally record the desired classes | |
1396 | for any allocnos, doing it twice if some pair of operands are | |
1397 | commutative. */ | |
1398 | for (i = 0; i < recog_data.n_operands; i++) | |
1399 | { | |
1400 | memcpy (op_costs[i], init_cost, struct_costs_size); | |
1401 | ||
1402 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
1403 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
1404 | ||
1405 | if (MEM_P (recog_data.operand[i])) | |
1406 | record_address_regs (GET_MODE (recog_data.operand[i]), | |
86fc3d06 | 1407 | MEM_ADDR_SPACE (recog_data.operand[i]), |
058e97ec VM |
1408 | XEXP (recog_data.operand[i], 0), |
1409 | 0, MEM, SCRATCH, frequency * 2); | |
1410 | else if (constraints[i][0] == 'p' | |
777e635f RS |
1411 | || (insn_extra_address_constraint |
1412 | (lookup_constraint (constraints[i])))) | |
86fc3d06 UW |
1413 | record_address_regs (VOIDmode, ADDR_SPACE_GENERIC, |
1414 | recog_data.operand[i], 0, ADDRESS, SCRATCH, | |
1415 | frequency * 2); | |
058e97ec | 1416 | } |
eeae9314 | 1417 | |
058e97ec VM |
1418 | /* Check for commutative in a separate loop so everything will have |
1419 | been initialized. We must do this even if one operand is a | |
1420 | constant--see addsi3 in m68k.md. */ | |
1421 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1422 | if (constraints[i][0] == '%') | |
1423 | { | |
1424 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1425 | int j; | |
1426 | ||
eeae9314 VM |
1427 | /* Handle commutative operands by swapping the |
1428 | constraints. We assume the modes are the same. */ | |
058e97ec VM |
1429 | for (j = 0; j < recog_data.n_operands; j++) |
1430 | xconstraints[j] = constraints[j]; | |
1431 | ||
1432 | xconstraints[i] = constraints[i+1]; | |
1433 | xconstraints[i+1] = constraints[i]; | |
1434 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
1435 | recog_data.operand, modes, | |
aa1c5d72 | 1436 | xconstraints, insn, pref); |
058e97ec VM |
1437 | } |
1438 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
1439 | recog_data.operand, modes, | |
aa1c5d72 | 1440 | constraints, insn, pref); |
058e97ec VM |
1441 | } |
1442 | ||
1443 | \f | |
1444 | ||
1445 | /* Process one insn INSN. Scan it and record each time it would save | |
1446 | code to put a certain allocnos in a certain class. Return the last | |
1447 | insn processed, so that the scan can be continued from there. */ | |
070a1983 DM |
1448 | static rtx_insn * |
1449 | scan_one_insn (rtx_insn *insn) | |
058e97ec VM |
1450 | { |
1451 | enum rtx_code pat_code; | |
1452 | rtx set, note; | |
1453 | int i, k; | |
82ce305c | 1454 | bool counted_mem; |
058e97ec | 1455 | |
39718607 | 1456 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec VM |
1457 | return insn; |
1458 | ||
1459 | pat_code = GET_CODE (PATTERN (insn)); | |
355930ab | 1460 | if (pat_code == ASM_INPUT) |
058e97ec VM |
1461 | return insn; |
1462 | ||
355930ab JL |
1463 | /* If INSN is a USE/CLOBBER of a pseudo in a mode M then go ahead |
1464 | and initialize the register move costs of mode M. | |
1465 | ||
1466 | The pseudo may be related to another pseudo via a copy (implicit or | |
1467 | explicit) and if there are no mode M uses/sets of the original | |
1468 | pseudo, then we may leave the register move costs uninitialized for | |
1469 | mode M. */ | |
1470 | if (pat_code == USE || pat_code == CLOBBER) | |
1471 | { | |
1472 | rtx x = XEXP (PATTERN (insn), 0); | |
1473 | if (GET_CODE (x) == REG | |
2c2d5d00 JL |
1474 | && REGNO (x) >= FIRST_PSEUDO_REGISTER |
1475 | && have_regs_of_mode[GET_MODE (x)]) | |
355930ab JL |
1476 | ira_init_register_move_cost_if_necessary (GET_MODE (x)); |
1477 | return insn; | |
1478 | } | |
1479 | ||
82ce305c | 1480 | counted_mem = false; |
058e97ec VM |
1481 | set = single_set (insn); |
1482 | extract_insn (insn); | |
1483 | ||
1484 | /* If this insn loads a parameter from its stack slot, then it | |
1485 | represents a savings, rather than a cost, if the parameter is | |
eeae9314 | 1486 | stored in memory. Record this fact. |
82ce305c JL |
1487 | |
1488 | Similarly if we're loading other constants from memory (constant | |
1489 | pool, TOC references, small data areas, etc) and this is the only | |
3db93c89 JJ |
1490 | assignment to the destination pseudo. |
1491 | ||
1492 | Don't do this if SET_SRC (set) isn't a general operand, if it is | |
1493 | a memory requiring special instructions to load it, decreasing | |
1494 | mem_cost might result in it being loaded using the specialized | |
1495 | instruction into a register, then stored into stack and loaded | |
b8578ff7 | 1496 | again from the stack. See PR52208. |
eeae9314 | 1497 | |
b8578ff7 | 1498 | Don't do this if SET_SRC (set) has side effect. See PR56124. */ |
058e97ec VM |
1499 | if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set)) |
1500 | && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX | |
b8578ff7 BC |
1501 | && ((MEM_P (XEXP (note, 0)) |
1502 | && !side_effects_p (SET_SRC (set))) | |
82ce305c | 1503 | || (CONSTANT_P (XEXP (note, 0)) |
cca81ac8 L |
1504 | && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)), |
1505 | XEXP (note, 0)) | |
3db93c89 | 1506 | && REG_N_SETS (REGNO (SET_DEST (set))) == 1)) |
9129a561 VM |
1507 | && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set))) |
1508 | /* LRA does not use equiv with a symbol for PIC code. */ | |
1509 | && (! ira_use_lra_p || ! pic_offset_table_rtx | |
1510 | || ! contains_symbol_ref_p (XEXP (note, 0)))) | |
058e97ec | 1511 | { |
cca81ac8 | 1512 | enum reg_class cl = GENERAL_REGS; |
548a6322 | 1513 | rtx reg = SET_DEST (set); |
ce18efcb | 1514 | int num = COST_INDEX (REGNO (reg)); |
548a6322 | 1515 | |
ce18efcb | 1516 | COSTS (costs, num)->mem_cost |
548a6322 | 1517 | -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency; |
86fc3d06 UW |
1518 | record_address_regs (GET_MODE (SET_SRC (set)), |
1519 | MEM_ADDR_SPACE (SET_SRC (set)), | |
1520 | XEXP (SET_SRC (set), 0), 0, MEM, SCRATCH, | |
1521 | frequency * 2); | |
82ce305c | 1522 | counted_mem = true; |
058e97ec VM |
1523 | } |
1524 | ||
aa1c5d72 | 1525 | record_operand_costs (insn, pref); |
058e97ec VM |
1526 | |
1527 | /* Now add the cost for each operand to the total costs for its | |
1528 | allocno. */ | |
1529 | for (i = 0; i < recog_data.n_operands; i++) | |
6d078c9a VM |
1530 | { |
1531 | rtx op = recog_data.operand[i]; | |
1532 | ||
1533 | if (GET_CODE (op) == SUBREG) | |
1534 | op = SUBREG_REG (op); | |
1535 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1536 | { | |
1537 | int regno = REGNO (op); | |
1538 | struct costs *p = COSTS (costs, COST_INDEX (regno)); | |
1539 | struct costs *q = op_costs[i]; | |
1540 | int *p_costs = p->cost, *q_costs = q->cost; | |
1541 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
1542 | int add_cost; | |
1543 | ||
1544 | /* If the already accounted for the memory "cost" above, don't | |
1545 | do so again. */ | |
1546 | if (!counted_mem) | |
1547 | { | |
1548 | add_cost = q->mem_cost; | |
1549 | if (add_cost > 0 && INT_MAX - add_cost < p->mem_cost) | |
1550 | p->mem_cost = INT_MAX; | |
1551 | else | |
1552 | p->mem_cost += add_cost; | |
1553 | } | |
1554 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1555 | { | |
1556 | add_cost = q_costs[k]; | |
1557 | if (add_cost > 0 && INT_MAX - add_cost < p_costs[k]) | |
1558 | p_costs[k] = INT_MAX; | |
1559 | else | |
1560 | p_costs[k] += add_cost; | |
1561 | } | |
1562 | } | |
1563 | } | |
058e97ec VM |
1564 | return insn; |
1565 | } | |
1566 | ||
1567 | \f | |
1568 | ||
1569 | /* Print allocnos costs to file F. */ | |
1570 | static void | |
ce18efcb | 1571 | print_allocno_costs (FILE *f) |
058e97ec VM |
1572 | { |
1573 | int k; | |
1574 | ira_allocno_t a; | |
1575 | ira_allocno_iterator ai; | |
1576 | ||
ce18efcb | 1577 | ira_assert (allocno_p); |
058e97ec VM |
1578 | fprintf (f, "\n"); |
1579 | FOR_EACH_ALLOCNO (a, ai) | |
1580 | { | |
1581 | int i, rclass; | |
1582 | basic_block bb; | |
1583 | int regno = ALLOCNO_REGNO (a); | |
1756cb66 VM |
1584 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; |
1585 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
058e97ec VM |
1586 | |
1587 | i = ALLOCNO_NUM (a); | |
1588 | fprintf (f, " a%d(r%d,", i, regno); | |
1589 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
1590 | fprintf (f, "b%d", bb->index); | |
1591 | else | |
2608d841 | 1592 | fprintf (f, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec | 1593 | fprintf (f, ") costs:"); |
1756cb66 | 1594 | for (k = 0; k < cost_classes_ptr->num; k++) |
058e97ec VM |
1595 | { |
1596 | rclass = cost_classes[k]; | |
dab67d2c RS |
1597 | fprintf (f, " %s:%d", reg_class_names[rclass], |
1598 | COSTS (costs, i)->cost[k]); | |
1599 | if (flag_ira_region == IRA_REGION_ALL | |
1600 | || flag_ira_region == IRA_REGION_MIXED) | |
1601 | fprintf (f, ",%d", COSTS (total_allocno_costs, i)->cost[k]); | |
058e97ec | 1602 | } |
1756cb66 VM |
1603 | fprintf (f, " MEM:%i", COSTS (costs, i)->mem_cost); |
1604 | if (flag_ira_region == IRA_REGION_ALL | |
1605 | || flag_ira_region == IRA_REGION_MIXED) | |
1606 | fprintf (f, ",%d", COSTS (total_allocno_costs, i)->mem_cost); | |
1607 | fprintf (f, "\n"); | |
ce18efcb VM |
1608 | } |
1609 | } | |
1610 | ||
1611 | /* Print pseudo costs to file F. */ | |
1612 | static void | |
1613 | print_pseudo_costs (FILE *f) | |
1614 | { | |
1615 | int regno, k; | |
1616 | int rclass; | |
1756cb66 VM |
1617 | cost_classes_t cost_classes_ptr; |
1618 | enum reg_class *cost_classes; | |
ce18efcb VM |
1619 | |
1620 | ira_assert (! allocno_p); | |
1621 | fprintf (f, "\n"); | |
1622 | for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--) | |
1623 | { | |
1756cb66 | 1624 | if (REG_N_REFS (regno) <= 0) |
ce18efcb | 1625 | continue; |
1756cb66 VM |
1626 | cost_classes_ptr = regno_cost_classes[regno]; |
1627 | cost_classes = cost_classes_ptr->classes; | |
ce18efcb | 1628 | fprintf (f, " r%d costs:", regno); |
1756cb66 | 1629 | for (k = 0; k < cost_classes_ptr->num; k++) |
ce18efcb VM |
1630 | { |
1631 | rclass = cost_classes[k]; | |
dab67d2c RS |
1632 | fprintf (f, " %s:%d", reg_class_names[rclass], |
1633 | COSTS (costs, regno)->cost[k]); | |
ce18efcb VM |
1634 | } |
1635 | fprintf (f, " MEM:%i\n", COSTS (costs, regno)->mem_cost); | |
058e97ec VM |
1636 | } |
1637 | } | |
1638 | ||
1639 | /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno | |
1640 | costs. */ | |
1641 | static void | |
ce18efcb | 1642 | process_bb_for_costs (basic_block bb) |
058e97ec | 1643 | { |
070a1983 | 1644 | rtx_insn *insn; |
058e97ec | 1645 | |
058e97ec VM |
1646 | frequency = REG_FREQ_FROM_BB (bb); |
1647 | if (frequency == 0) | |
1648 | frequency = 1; | |
1649 | FOR_BB_INSNS (bb, insn) | |
1650 | insn = scan_one_insn (insn); | |
1651 | } | |
1652 | ||
ce18efcb VM |
1653 | /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
1654 | costs. */ | |
058e97ec | 1655 | static void |
ce18efcb | 1656 | process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node) |
058e97ec | 1657 | { |
ce18efcb VM |
1658 | basic_block bb; |
1659 | ||
1660 | bb = loop_tree_node->bb; | |
1661 | if (bb != NULL) | |
1662 | process_bb_for_costs (bb); | |
1663 | } | |
1664 | ||
1665 | /* Find costs of register classes and memory for allocnos or pseudos | |
1756cb66 | 1666 | and their best costs. Set up preferred, alternative and allocno |
ce18efcb VM |
1667 | classes for pseudos. */ |
1668 | static void | |
1669 | find_costs_and_classes (FILE *dump_file) | |
1670 | { | |
1756cb66 | 1671 | int i, k, start, max_cost_classes_num; |
058e97ec VM |
1672 | int pass; |
1673 | basic_block bb; | |
5074a1f8 | 1674 | enum reg_class *regno_best_class, new_class; |
058e97ec VM |
1675 | |
1676 | init_recog (); | |
1756cb66 VM |
1677 | regno_best_class |
1678 | = (enum reg_class *) ira_allocate (max_reg_num () | |
1679 | * sizeof (enum reg_class)); | |
1680 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1681 | regno_best_class[i] = NO_REGS; | |
1682 | if (!resize_reg_info () && allocno_p | |
1683 | && pseudo_classes_defined_p && flag_expensive_optimizations) | |
ce18efcb VM |
1684 | { |
1685 | ira_allocno_t a; | |
1686 | ira_allocno_iterator ai; | |
b8698a0f | 1687 | |
ce18efcb | 1688 | pref = pref_buffer; |
1756cb66 | 1689 | max_cost_classes_num = 1; |
ce18efcb | 1690 | FOR_EACH_ALLOCNO (a, ai) |
1756cb66 VM |
1691 | { |
1692 | pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a)); | |
1693 | setup_regno_cost_classes_by_aclass | |
1694 | (ALLOCNO_REGNO (a), pref[ALLOCNO_NUM (a)]); | |
1695 | max_cost_classes_num | |
1696 | = MAX (max_cost_classes_num, | |
1697 | regno_cost_classes[ALLOCNO_REGNO (a)]->num); | |
1698 | } | |
1699 | start = 1; | |
1700 | } | |
1701 | else | |
1702 | { | |
1703 | pref = NULL; | |
1704 | max_cost_classes_num = ira_important_classes_num; | |
1705 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1706 | if (regno_reg_rtx[i] != NULL_RTX) | |
1707 | setup_regno_cost_classes_by_mode (i, PSEUDO_REGNO_MODE (i)); | |
1708 | else | |
1709 | setup_regno_cost_classes_by_aclass (i, ALL_REGS); | |
1710 | start = 0; | |
ce18efcb VM |
1711 | } |
1712 | if (allocno_p) | |
1713 | /* Clear the flag for the next compiled function. */ | |
1714 | pseudo_classes_defined_p = false; | |
058e97ec VM |
1715 | /* Normally we scan the insns once and determine the best class to |
1716 | use for each allocno. However, if -fexpensive-optimizations are | |
1717 | on, we do so twice, the second time using the tentative best | |
1718 | classes to guide the selection. */ | |
ce18efcb | 1719 | for (pass = start; pass <= flag_expensive_optimizations; pass++) |
058e97ec | 1720 | { |
ce18efcb VM |
1721 | if ((!allocno_p || internal_flag_ira_verbose > 0) && dump_file) |
1722 | fprintf (dump_file, | |
1723 | "\nPass %i for finding pseudo/allocno costs\n\n", pass); | |
1756cb66 VM |
1724 | |
1725 | if (pass != start) | |
058e97ec | 1726 | { |
1756cb66 VM |
1727 | max_cost_classes_num = 1; |
1728 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1729 | { | |
1730 | setup_regno_cost_classes_by_aclass (i, regno_best_class[i]); | |
1731 | max_cost_classes_num | |
1732 | = MAX (max_cost_classes_num, regno_cost_classes[i]->num); | |
1733 | } | |
058e97ec | 1734 | } |
1756cb66 | 1735 | |
058e97ec | 1736 | struct_costs_size |
1756cb66 | 1737 | = sizeof (struct costs) + sizeof (int) * (max_cost_classes_num - 1); |
058e97ec VM |
1738 | /* Zero out our accumulation of the cost of each class for each |
1739 | allocno. */ | |
ce18efcb | 1740 | memset (costs, 0, cost_elements_num * struct_costs_size); |
058e97ec | 1741 | |
ce18efcb VM |
1742 | if (allocno_p) |
1743 | { | |
1744 | /* Scan the instructions and record each time it would save code | |
1745 | to put a certain allocno in a certain class. */ | |
1746 | ira_traverse_loop_tree (true, ira_loop_tree_root, | |
1747 | process_bb_node_for_costs, NULL); | |
1748 | ||
1749 | memcpy (total_allocno_costs, costs, | |
1750 | max_struct_costs_size * ira_allocnos_num); | |
1751 | } | |
1752 | else | |
1753 | { | |
1754 | basic_block bb; | |
1755 | ||
11cd3bed | 1756 | FOR_EACH_BB_FN (bb, cfun) |
ce18efcb VM |
1757 | process_bb_for_costs (bb); |
1758 | } | |
058e97ec | 1759 | |
058e97ec | 1760 | if (pass == 0) |
ce18efcb | 1761 | pref = pref_buffer; |
058e97ec VM |
1762 | |
1763 | /* Now for each allocno look at how desirable each class is and | |
1764 | find which class is preferred. */ | |
1765 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1766 | { | |
1767 | ira_allocno_t a, parent_a; | |
1756cb66 | 1768 | int rclass, a_num, parent_a_num, add_cost; |
058e97ec | 1769 | ira_loop_tree_node_t parent; |
61ad6db1 | 1770 | int best_cost, allocno_cost; |
7db7ed3c | 1771 | enum reg_class best, alt_class; |
1756cb66 | 1772 | cost_classes_t cost_classes_ptr = regno_cost_classes[i]; |
0dc7d7cc | 1773 | enum reg_class *cost_classes; |
1756cb66 VM |
1774 | int *i_costs = temp_costs->cost; |
1775 | int i_mem_cost; | |
8ff49c29 | 1776 | int equiv_savings = regno_equiv_gains[i]; |
058e97ec | 1777 | |
ce18efcb | 1778 | if (! allocno_p) |
058e97ec | 1779 | { |
ce18efcb VM |
1780 | if (regno_reg_rtx[i] == NULL_RTX) |
1781 | continue; | |
ce18efcb | 1782 | memcpy (temp_costs, COSTS (costs, i), struct_costs_size); |
1756cb66 | 1783 | i_mem_cost = temp_costs->mem_cost; |
0dc7d7cc | 1784 | cost_classes = cost_classes_ptr->classes; |
ce18efcb VM |
1785 | } |
1786 | else | |
1787 | { | |
1788 | if (ira_regno_allocno_map[i] == NULL) | |
1789 | continue; | |
1790 | memset (temp_costs, 0, struct_costs_size); | |
1756cb66 | 1791 | i_mem_cost = 0; |
0dc7d7cc | 1792 | cost_classes = cost_classes_ptr->classes; |
ce18efcb VM |
1793 | /* Find cost of all allocnos with the same regno. */ |
1794 | for (a = ira_regno_allocno_map[i]; | |
1795 | a != NULL; | |
1796 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
058e97ec | 1797 | { |
1756cb66 | 1798 | int *a_costs, *p_costs; |
eeae9314 | 1799 | |
ce18efcb VM |
1800 | a_num = ALLOCNO_NUM (a); |
1801 | if ((flag_ira_region == IRA_REGION_ALL | |
1802 | || flag_ira_region == IRA_REGION_MIXED) | |
1803 | && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL | |
1804 | && (parent_a = parent->regno_allocno_map[i]) != NULL | |
1805 | /* There are no caps yet. */ | |
1806 | && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE | |
1807 | (a)->border_allocnos, | |
1808 | ALLOCNO_NUM (a))) | |
1809 | { | |
1810 | /* Propagate costs to upper levels in the region | |
1811 | tree. */ | |
1812 | parent_a_num = ALLOCNO_NUM (parent_a); | |
1756cb66 VM |
1813 | a_costs = COSTS (total_allocno_costs, a_num)->cost; |
1814 | p_costs = COSTS (total_allocno_costs, parent_a_num)->cost; | |
1815 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1816 | { | |
1817 | add_cost = a_costs[k]; | |
1818 | if (add_cost > 0 && INT_MAX - add_cost < p_costs[k]) | |
1819 | p_costs[k] = INT_MAX; | |
1820 | else | |
1821 | p_costs[k] += add_cost; | |
1822 | } | |
1823 | add_cost = COSTS (total_allocno_costs, a_num)->mem_cost; | |
1824 | if (add_cost > 0 | |
1825 | && (INT_MAX - add_cost | |
1826 | < COSTS (total_allocno_costs, | |
1827 | parent_a_num)->mem_cost)) | |
1828 | COSTS (total_allocno_costs, parent_a_num)->mem_cost | |
1829 | = INT_MAX; | |
1830 | else | |
1831 | COSTS (total_allocno_costs, parent_a_num)->mem_cost | |
1832 | += add_cost; | |
1833 | ||
acf41a74 BS |
1834 | if (i >= first_moveable_pseudo && i < last_moveable_pseudo) |
1835 | COSTS (total_allocno_costs, parent_a_num)->mem_cost = 0; | |
ce18efcb | 1836 | } |
1756cb66 VM |
1837 | a_costs = COSTS (costs, a_num)->cost; |
1838 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1839 | { | |
1840 | add_cost = a_costs[k]; | |
1841 | if (add_cost > 0 && INT_MAX - add_cost < i_costs[k]) | |
1842 | i_costs[k] = INT_MAX; | |
1843 | else | |
1844 | i_costs[k] += add_cost; | |
1845 | } | |
1846 | add_cost = COSTS (costs, a_num)->mem_cost; | |
bddc98e1 | 1847 | if (add_cost > 0 && INT_MAX - add_cost < i_mem_cost) |
1756cb66 VM |
1848 | i_mem_cost = INT_MAX; |
1849 | else | |
1850 | i_mem_cost += add_cost; | |
ce18efcb | 1851 | } |
058e97ec | 1852 | } |
acf41a74 BS |
1853 | if (i >= first_moveable_pseudo && i < last_moveable_pseudo) |
1854 | i_mem_cost = 0; | |
1855 | else if (equiv_savings < 0) | |
89fa552a | 1856 | i_mem_cost = -equiv_savings; |
8ff49c29 BS |
1857 | else if (equiv_savings > 0) |
1858 | { | |
89fa552a | 1859 | i_mem_cost = 0; |
1756cb66 VM |
1860 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) |
1861 | i_costs[k] += equiv_savings; | |
8ff49c29 BS |
1862 | } |
1863 | ||
058e97ec VM |
1864 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
1865 | best = ALL_REGS; | |
1866 | alt_class = NO_REGS; | |
1867 | /* Find best common class for all allocnos with the same | |
1868 | regno. */ | |
1756cb66 | 1869 | for (k = 0; k < cost_classes_ptr->num; k++) |
058e97ec VM |
1870 | { |
1871 | rclass = cost_classes[k]; | |
1756cb66 | 1872 | if (i_costs[k] < best_cost) |
058e97ec | 1873 | { |
1756cb66 | 1874 | best_cost = i_costs[k]; |
058e97ec VM |
1875 | best = (enum reg_class) rclass; |
1876 | } | |
1756cb66 VM |
1877 | else if (i_costs[k] == best_cost) |
1878 | best = ira_reg_class_subunion[best][rclass]; | |
058e97ec | 1879 | if (pass == flag_expensive_optimizations |
9d19c732 VM |
1880 | /* We still prefer registers to memory even at this |
1881 | stage if their costs are the same. We will make | |
1882 | a final decision during assigning hard registers | |
1883 | when we have all info including more accurate | |
1884 | costs which might be affected by assigning hard | |
1885 | registers to other pseudos because the pseudos | |
1886 | involved in moves can be coalesced. */ | |
1887 | && i_costs[k] <= i_mem_cost | |
058e97ec VM |
1888 | && (reg_class_size[reg_class_subunion[alt_class][rclass]] |
1889 | > reg_class_size[alt_class])) | |
1890 | alt_class = reg_class_subunion[alt_class][rclass]; | |
1891 | } | |
1756cb66 | 1892 | alt_class = ira_allocno_class_translate[alt_class]; |
b81a2f0d VM |
1893 | if (best_cost > i_mem_cost |
1894 | && ! non_spilled_static_chain_regno_p (i)) | |
1756cb66 | 1895 | regno_aclass[i] = NO_REGS; |
2da068d5 RS |
1896 | else if (!optimize && !targetm.class_likely_spilled_p (best)) |
1897 | /* Registers in the alternative class are likely to need | |
1898 | longer or slower sequences than registers in the best class. | |
1899 | When optimizing we make some effort to use the best class | |
1900 | over the alternative class where possible, but at -O0 we | |
1901 | effectively give the alternative class equal weight. | |
1902 | We then run the risk of using slower alternative registers | |
1903 | when plenty of registers from the best class are still free. | |
1904 | This is especially true because live ranges tend to be very | |
1905 | short in -O0 code and so register pressure tends to be low. | |
1906 | ||
1907 | Avoid that by ignoring the alternative class if the best | |
bc13623e VM |
1908 | class has plenty of registers. |
1909 | ||
1910 | The union class arrays give important classes and only | |
1911 | part of it are allocno classes. So translate them into | |
1912 | allocno classes. */ | |
1913 | regno_aclass[i] = ira_allocno_class_translate[best]; | |
058e97ec | 1914 | else |
1756cb66 VM |
1915 | { |
1916 | /* Make the common class the biggest class of best and | |
bc13623e VM |
1917 | alt_class. Translate the common class into an |
1918 | allocno class too. */ | |
1919 | regno_aclass[i] = (ira_allocno_class_translate | |
1920 | [ira_reg_class_superunion[best][alt_class]]); | |
1756cb66 VM |
1921 | ira_assert (regno_aclass[i] != NO_REGS |
1922 | && ira_reg_allocno_class_p[regno_aclass[i]]); | |
1923 | } | |
5074a1f8 VM |
1924 | if ((new_class |
1925 | = (reg_class) (targetm.ira_change_pseudo_allocno_class | |
31e2b5a3 | 1926 | (i, regno_aclass[i], best))) != regno_aclass[i]) |
5074a1f8 VM |
1927 | { |
1928 | regno_aclass[i] = new_class; | |
1929 | if (hard_reg_set_subset_p (reg_class_contents[new_class], | |
1930 | reg_class_contents[best])) | |
1931 | best = new_class; | |
1932 | if (hard_reg_set_subset_p (reg_class_contents[new_class], | |
1933 | reg_class_contents[alt_class])) | |
1934 | alt_class = new_class; | |
1935 | } | |
ce18efcb VM |
1936 | if (pass == flag_expensive_optimizations) |
1937 | { | |
b81a2f0d VM |
1938 | if (best_cost > i_mem_cost |
1939 | /* Do not assign NO_REGS to static chain pointer | |
1940 | pseudo when non-local goto is used. */ | |
1941 | && ! non_spilled_static_chain_regno_p (i)) | |
ce18efcb VM |
1942 | best = alt_class = NO_REGS; |
1943 | else if (best == alt_class) | |
1944 | alt_class = NO_REGS; | |
1756cb66 | 1945 | setup_reg_classes (i, best, alt_class, regno_aclass[i]); |
ce18efcb VM |
1946 | if ((!allocno_p || internal_flag_ira_verbose > 2) |
1947 | && dump_file != NULL) | |
1948 | fprintf (dump_file, | |
1756cb66 | 1949 | " r%d: preferred %s, alternative %s, allocno %s\n", |
ce18efcb | 1950 | i, reg_class_names[best], reg_class_names[alt_class], |
1756cb66 | 1951 | reg_class_names[regno_aclass[i]]); |
ce18efcb | 1952 | } |
1756cb66 | 1953 | regno_best_class[i] = best; |
ce18efcb VM |
1954 | if (! allocno_p) |
1955 | { | |
b81a2f0d VM |
1956 | pref[i] = (best_cost > i_mem_cost |
1957 | && ! non_spilled_static_chain_regno_p (i) | |
1958 | ? NO_REGS : best); | |
ce18efcb VM |
1959 | continue; |
1960 | } | |
058e97ec VM |
1961 | for (a = ira_regno_allocno_map[i]; |
1962 | a != NULL; | |
1963 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
1964 | { | |
3b6d1699 VM |
1965 | enum reg_class aclass = regno_aclass[i]; |
1966 | int a_num = ALLOCNO_NUM (a); | |
1967 | int *total_a_costs = COSTS (total_allocno_costs, a_num)->cost; | |
1968 | int *a_costs = COSTS (costs, a_num)->cost; | |
eeae9314 | 1969 | |
3b6d1699 | 1970 | if (aclass == NO_REGS) |
058e97ec VM |
1971 | best = NO_REGS; |
1972 | else | |
b8698a0f | 1973 | { |
058e97ec VM |
1974 | /* Finding best class which is subset of the common |
1975 | class. */ | |
1976 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
61ad6db1 | 1977 | allocno_cost = best_cost; |
058e97ec | 1978 | best = ALL_REGS; |
1756cb66 | 1979 | for (k = 0; k < cost_classes_ptr->num; k++) |
058e97ec VM |
1980 | { |
1981 | rclass = cost_classes[k]; | |
3b6d1699 | 1982 | if (! ira_class_subset_p[rclass][aclass]) |
058e97ec | 1983 | continue; |
dab67d2c | 1984 | if (total_a_costs[k] < best_cost) |
058e97ec | 1985 | { |
1756cb66 VM |
1986 | best_cost = total_a_costs[k]; |
1987 | allocno_cost = a_costs[k]; | |
058e97ec VM |
1988 | best = (enum reg_class) rclass; |
1989 | } | |
1756cb66 | 1990 | else if (total_a_costs[k] == best_cost) |
61ad6db1 | 1991 | { |
1756cb66 VM |
1992 | best = ira_reg_class_subunion[best][rclass]; |
1993 | allocno_cost = MAX (allocno_cost, a_costs[k]); | |
61ad6db1 | 1994 | } |
058e97ec | 1995 | } |
1756cb66 | 1996 | ALLOCNO_CLASS_COST (a) = allocno_cost; |
058e97ec | 1997 | } |
ce18efcb VM |
1998 | if (internal_flag_ira_verbose > 2 && dump_file != NULL |
1999 | && (pass == 0 || pref[a_num] != best)) | |
058e97ec | 2000 | { |
ce18efcb | 2001 | fprintf (dump_file, " a%d (r%d,", a_num, i); |
058e97ec | 2002 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) |
ce18efcb | 2003 | fprintf (dump_file, "b%d", bb->index); |
058e97ec | 2004 | else |
ce18efcb | 2005 | fprintf (dump_file, "l%d", |
2608d841 | 2006 | ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
1756cb66 | 2007 | fprintf (dump_file, ") best %s, allocno %s\n", |
058e97ec | 2008 | reg_class_names[best], |
3b6d1699 | 2009 | reg_class_names[aclass]); |
058e97ec | 2010 | } |
ce18efcb | 2011 | pref[a_num] = best; |
3b6d1699 VM |
2012 | if (pass == flag_expensive_optimizations && best != aclass |
2013 | && ira_class_hard_regs_num[best] > 0 | |
2014 | && (ira_reg_class_max_nregs[best][ALLOCNO_MODE (a)] | |
2015 | >= ira_class_hard_regs_num[best])) | |
2016 | { | |
2017 | int ind = cost_classes_ptr->index[aclass]; | |
2018 | ||
2019 | ira_assert (ind >= 0); | |
dc687582 | 2020 | ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a)); |
3b6d1699 VM |
2021 | ira_add_allocno_pref (a, ira_class_hard_regs[best][0], |
2022 | (a_costs[ind] - ALLOCNO_CLASS_COST (a)) | |
2023 | / (ira_register_move_cost | |
2024 | [ALLOCNO_MODE (a)][best][aclass])); | |
2025 | for (k = 0; k < cost_classes_ptr->num; k++) | |
2026 | if (ira_class_subset_p[cost_classes[k]][best]) | |
2027 | a_costs[k] = a_costs[ind]; | |
2028 | } | |
058e97ec VM |
2029 | } |
2030 | } | |
eeae9314 | 2031 | |
ce18efcb | 2032 | if (internal_flag_ira_verbose > 4 && dump_file) |
058e97ec | 2033 | { |
ce18efcb VM |
2034 | if (allocno_p) |
2035 | print_allocno_costs (dump_file); | |
2036 | else | |
2037 | print_pseudo_costs (dump_file); | |
2038 | fprintf (dump_file,"\n"); | |
058e97ec VM |
2039 | } |
2040 | } | |
1756cb66 | 2041 | ira_free (regno_best_class); |
058e97ec VM |
2042 | } |
2043 | ||
2044 | \f | |
2045 | ||
2046 | /* Process moves involving hard regs to modify allocno hard register | |
1756cb66 | 2047 | costs. We can do this only after determining allocno class. If a |
420ab54b | 2048 | hard register forms a register class, then moves with the hard |
058e97ec VM |
2049 | register are already taken into account in class costs for the |
2050 | allocno. */ | |
2051 | static void | |
2052 | process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node) | |
2053 | { | |
3b6d1699 | 2054 | int i, freq, src_regno, dst_regno, hard_regno, a_regno; |
058e97ec | 2055 | bool to_p; |
3b6d1699 VM |
2056 | ira_allocno_t a, curr_a; |
2057 | ira_loop_tree_node_t curr_loop_tree_node; | |
2058 | enum reg_class rclass; | |
058e97ec | 2059 | basic_block bb; |
070a1983 DM |
2060 | rtx_insn *insn; |
2061 | rtx set, src, dst; | |
058e97ec VM |
2062 | |
2063 | bb = loop_tree_node->bb; | |
2064 | if (bb == NULL) | |
2065 | return; | |
2066 | freq = REG_FREQ_FROM_BB (bb); | |
2067 | if (freq == 0) | |
2068 | freq = 1; | |
2069 | FOR_BB_INSNS (bb, insn) | |
2070 | { | |
b5b8b0ac | 2071 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec VM |
2072 | continue; |
2073 | set = single_set (insn); | |
2074 | if (set == NULL_RTX) | |
2075 | continue; | |
2076 | dst = SET_DEST (set); | |
2077 | src = SET_SRC (set); | |
2078 | if (! REG_P (dst) || ! REG_P (src)) | |
2079 | continue; | |
2080 | dst_regno = REGNO (dst); | |
2081 | src_regno = REGNO (src); | |
2082 | if (dst_regno >= FIRST_PSEUDO_REGISTER | |
2083 | && src_regno < FIRST_PSEUDO_REGISTER) | |
2084 | { | |
2085 | hard_regno = src_regno; | |
058e97ec | 2086 | a = ira_curr_regno_allocno_map[dst_regno]; |
3b6d1699 | 2087 | to_p = true; |
058e97ec VM |
2088 | } |
2089 | else if (src_regno >= FIRST_PSEUDO_REGISTER | |
2090 | && dst_regno < FIRST_PSEUDO_REGISTER) | |
2091 | { | |
2092 | hard_regno = dst_regno; | |
058e97ec | 2093 | a = ira_curr_regno_allocno_map[src_regno]; |
3b6d1699 | 2094 | to_p = false; |
058e97ec VM |
2095 | } |
2096 | else | |
2097 | continue; | |
0d2a576a VM |
2098 | if (reg_class_size[(int) REGNO_REG_CLASS (hard_regno)] |
2099 | == (ira_reg_class_max_nregs | |
2100 | [REGNO_REG_CLASS (hard_regno)][(int) ALLOCNO_MODE(a)])) | |
2101 | /* If the class can provide only one hard reg to the allocno, | |
2102 | we processed the insn record_operand_costs already and we | |
2103 | actually updated the hard reg cost there. */ | |
2104 | continue; | |
1756cb66 | 2105 | rclass = ALLOCNO_CLASS (a); |
058e97ec VM |
2106 | if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno)) |
2107 | continue; | |
2108 | i = ira_class_hard_reg_index[rclass][hard_regno]; | |
2109 | if (i < 0) | |
2110 | continue; | |
3b6d1699 VM |
2111 | a_regno = ALLOCNO_REGNO (a); |
2112 | for (curr_loop_tree_node = ALLOCNO_LOOP_TREE_NODE (a); | |
2113 | curr_loop_tree_node != NULL; | |
2114 | curr_loop_tree_node = curr_loop_tree_node->parent) | |
2115 | if ((curr_a = curr_loop_tree_node->regno_allocno_map[a_regno]) != NULL) | |
2116 | ira_add_allocno_pref (curr_a, hard_regno, freq); | |
2117 | { | |
2118 | int cost; | |
2119 | enum reg_class hard_reg_class; | |
ef4bddc2 | 2120 | machine_mode mode; |
eeae9314 | 2121 | |
3b6d1699 VM |
2122 | mode = ALLOCNO_MODE (a); |
2123 | hard_reg_class = REGNO_REG_CLASS (hard_regno); | |
2124 | ira_init_register_move_cost_if_necessary (mode); | |
2125 | cost = (to_p ? ira_register_move_cost[mode][hard_reg_class][rclass] | |
2126 | : ira_register_move_cost[mode][rclass][hard_reg_class]) * freq; | |
2127 | ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass, | |
2128 | ALLOCNO_CLASS_COST (a)); | |
2129 | ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a), | |
2130 | rclass, 0); | |
2131 | ALLOCNO_HARD_REG_COSTS (a)[i] -= cost; | |
2132 | ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost; | |
2133 | ALLOCNO_CLASS_COST (a) = MIN (ALLOCNO_CLASS_COST (a), | |
2134 | ALLOCNO_HARD_REG_COSTS (a)[i]); | |
2135 | } | |
058e97ec VM |
2136 | } |
2137 | } | |
2138 | ||
2139 | /* After we find hard register and memory costs for allocnos, define | |
1756cb66 | 2140 | its class and modify hard register cost because insns moving |
058e97ec VM |
2141 | allocno to/from hard registers. */ |
2142 | static void | |
1756cb66 | 2143 | setup_allocno_class_and_costs (void) |
058e97ec | 2144 | { |
1756cb66 | 2145 | int i, j, n, regno, hard_regno, num; |
058e97ec | 2146 | int *reg_costs; |
1756cb66 | 2147 | enum reg_class aclass, rclass; |
058e97ec VM |
2148 | ira_allocno_t a; |
2149 | ira_allocno_iterator ai; | |
1756cb66 | 2150 | cost_classes_t cost_classes_ptr; |
058e97ec | 2151 | |
ce18efcb | 2152 | ira_assert (allocno_p); |
058e97ec VM |
2153 | FOR_EACH_ALLOCNO (a, ai) |
2154 | { | |
2155 | i = ALLOCNO_NUM (a); | |
1756cb66 VM |
2156 | regno = ALLOCNO_REGNO (a); |
2157 | aclass = regno_aclass[regno]; | |
2158 | cost_classes_ptr = regno_cost_classes[regno]; | |
2159 | ira_assert (pref[i] == NO_REGS || aclass != NO_REGS); | |
ce18efcb | 2160 | ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost; |
1756cb66 VM |
2161 | ira_set_allocno_class (a, aclass); |
2162 | if (aclass == NO_REGS) | |
058e97ec | 2163 | continue; |
1756cb66 | 2164 | if (optimize && ALLOCNO_CLASS (a) != pref[i]) |
058e97ec | 2165 | { |
1756cb66 | 2166 | n = ira_class_hard_regs_num[aclass]; |
058e97ec | 2167 | ALLOCNO_HARD_REG_COSTS (a) |
1756cb66 | 2168 | = reg_costs = ira_allocate_cost_vector (aclass); |
058e97ec VM |
2169 | for (j = n - 1; j >= 0; j--) |
2170 | { | |
1756cb66 VM |
2171 | hard_regno = ira_class_hard_regs[aclass][j]; |
2172 | if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], hard_regno)) | |
2173 | reg_costs[j] = ALLOCNO_CLASS_COST (a); | |
61ad6db1 | 2174 | else |
c0683a82 | 2175 | { |
1756cb66 VM |
2176 | rclass = REGNO_REG_CLASS (hard_regno); |
2177 | num = cost_classes_ptr->index[rclass]; | |
61ad6db1 RS |
2178 | if (num < 0) |
2179 | { | |
1756cb66 VM |
2180 | num = cost_classes_ptr->hard_regno_index[hard_regno]; |
2181 | ira_assert (num >= 0); | |
61ad6db1 | 2182 | } |
ce18efcb | 2183 | reg_costs[j] = COSTS (costs, i)->cost[num]; |
c0683a82 | 2184 | } |
058e97ec VM |
2185 | } |
2186 | } | |
2187 | } | |
2188 | if (optimize) | |
2189 | ira_traverse_loop_tree (true, ira_loop_tree_root, | |
2190 | process_bb_node_for_hard_reg_moves, NULL); | |
2191 | } | |
2192 | ||
2193 | \f | |
2194 | ||
2195 | /* Function called once during compiler work. */ | |
2196 | void | |
2197 | ira_init_costs_once (void) | |
2198 | { | |
2199 | int i; | |
2200 | ||
2201 | init_cost = NULL; | |
2202 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
2203 | { | |
2204 | op_costs[i] = NULL; | |
2205 | this_op_costs[i] = NULL; | |
2206 | } | |
2207 | temp_costs = NULL; | |
058e97ec VM |
2208 | } |
2209 | ||
2210 | /* Free allocated temporary cost vectors. */ | |
19c708dc RS |
2211 | void |
2212 | target_ira_int::free_ira_costs () | |
058e97ec VM |
2213 | { |
2214 | int i; | |
2215 | ||
19c708dc RS |
2216 | free (x_init_cost); |
2217 | x_init_cost = NULL; | |
058e97ec VM |
2218 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) |
2219 | { | |
19c708dc RS |
2220 | free (x_op_costs[i]); |
2221 | free (x_this_op_costs[i]); | |
2222 | x_op_costs[i] = x_this_op_costs[i] = NULL; | |
058e97ec | 2223 | } |
19c708dc RS |
2224 | free (x_temp_costs); |
2225 | x_temp_costs = NULL; | |
058e97ec VM |
2226 | } |
2227 | ||
2228 | /* This is called each time register related information is | |
2229 | changed. */ | |
2230 | void | |
2231 | ira_init_costs (void) | |
2232 | { | |
2233 | int i; | |
2234 | ||
19c708dc | 2235 | this_target_ira_int->free_ira_costs (); |
058e97ec VM |
2236 | max_struct_costs_size |
2237 | = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1); | |
1756cb66 VM |
2238 | /* Don't use ira_allocate because vectors live through several IRA |
2239 | calls. */ | |
058e97ec VM |
2240 | init_cost = (struct costs *) xmalloc (max_struct_costs_size); |
2241 | init_cost->mem_cost = 1000000; | |
2242 | for (i = 0; i < ira_important_classes_num; i++) | |
2243 | init_cost->cost[i] = 1000000; | |
2244 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
2245 | { | |
2246 | op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
2247 | this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
2248 | } | |
2249 | temp_costs = (struct costs *) xmalloc (max_struct_costs_size); | |
058e97ec VM |
2250 | } |
2251 | ||
058e97ec VM |
2252 | \f |
2253 | ||
ce18efcb VM |
2254 | /* Common initialization function for ira_costs and |
2255 | ira_set_pseudo_classes. */ | |
2256 | static void | |
2257 | init_costs (void) | |
2258 | { | |
1833192f | 2259 | init_subregs_of_mode (); |
ce18efcb VM |
2260 | costs = (struct costs *) ira_allocate (max_struct_costs_size |
2261 | * cost_elements_num); | |
1756cb66 VM |
2262 | pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
2263 | * cost_elements_num); | |
2264 | regno_aclass = (enum reg_class *) ira_allocate (sizeof (enum reg_class) | |
2265 | * max_reg_num ()); | |
8ff49c29 BS |
2266 | regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); |
2267 | memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); | |
ce18efcb VM |
2268 | } |
2269 | ||
2270 | /* Common finalization function for ira_costs and | |
2271 | ira_set_pseudo_classes. */ | |
2272 | static void | |
2273 | finish_costs (void) | |
2274 | { | |
fa1fabcb | 2275 | finish_subregs_of_mode (); |
8ff49c29 | 2276 | ira_free (regno_equiv_gains); |
1756cb66 | 2277 | ira_free (regno_aclass); |
ce18efcb VM |
2278 | ira_free (pref_buffer); |
2279 | ira_free (costs); | |
2280 | } | |
2281 | ||
1756cb66 VM |
2282 | /* Entry function which defines register class, memory and hard |
2283 | register costs for each allocno. */ | |
058e97ec VM |
2284 | void |
2285 | ira_costs (void) | |
2286 | { | |
ce18efcb VM |
2287 | allocno_p = true; |
2288 | cost_elements_num = ira_allocnos_num; | |
2289 | init_costs (); | |
2290 | total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size | |
2291 | * ira_allocnos_num); | |
1756cb66 | 2292 | initiate_regno_cost_classes (); |
8ff49c29 | 2293 | calculate_elim_costs_all_insns (); |
ce18efcb | 2294 | find_costs_and_classes (ira_dump_file); |
1756cb66 VM |
2295 | setup_allocno_class_and_costs (); |
2296 | finish_regno_cost_classes (); | |
ce18efcb VM |
2297 | finish_costs (); |
2298 | ira_free (total_allocno_costs); | |
2299 | } | |
2300 | ||
b11f0116 BC |
2301 | /* Entry function which defines classes for pseudos. |
2302 | Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */ | |
ce18efcb | 2303 | void |
b11f0116 | 2304 | ira_set_pseudo_classes (bool define_pseudo_classes, FILE *dump_file) |
ce18efcb VM |
2305 | { |
2306 | allocno_p = false; | |
2307 | internal_flag_ira_verbose = flag_ira_verbose; | |
2308 | cost_elements_num = max_reg_num (); | |
2309 | init_costs (); | |
1756cb66 | 2310 | initiate_regno_cost_classes (); |
ce18efcb | 2311 | find_costs_and_classes (dump_file); |
1756cb66 | 2312 | finish_regno_cost_classes (); |
b11f0116 BC |
2313 | if (define_pseudo_classes) |
2314 | pseudo_classes_defined_p = true; | |
2315 | ||
ce18efcb | 2316 | finish_costs (); |
058e97ec VM |
2317 | } |
2318 | ||
2319 | \f | |
2320 | ||
2321 | /* Change hard register costs for allocnos which lives through | |
2322 | function calls. This is called only when we found all intersected | |
2323 | calls during building allocno live ranges. */ | |
2324 | void | |
1756cb66 | 2325 | ira_tune_allocno_costs (void) |
058e97ec VM |
2326 | { |
2327 | int j, n, regno; | |
2328 | int cost, min_cost, *reg_costs; | |
1756cb66 | 2329 | enum reg_class aclass, rclass; |
ef4bddc2 | 2330 | machine_mode mode; |
058e97ec VM |
2331 | ira_allocno_t a; |
2332 | ira_allocno_iterator ai; | |
1756cb66 VM |
2333 | ira_allocno_object_iterator oi; |
2334 | ira_object_t obj; | |
2335 | bool skip_p; | |
058e97ec VM |
2336 | |
2337 | FOR_EACH_ALLOCNO (a, ai) | |
2338 | { | |
1756cb66 VM |
2339 | aclass = ALLOCNO_CLASS (a); |
2340 | if (aclass == NO_REGS) | |
058e97ec VM |
2341 | continue; |
2342 | mode = ALLOCNO_MODE (a); | |
1756cb66 | 2343 | n = ira_class_hard_regs_num[aclass]; |
058e97ec | 2344 | min_cost = INT_MAX; |
e384e6b5 BS |
2345 | if (ALLOCNO_CALLS_CROSSED_NUM (a) |
2346 | != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
058e97ec VM |
2347 | { |
2348 | ira_allocate_and_set_costs | |
1756cb66 VM |
2349 | (&ALLOCNO_HARD_REG_COSTS (a), aclass, |
2350 | ALLOCNO_CLASS_COST (a)); | |
058e97ec VM |
2351 | reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
2352 | for (j = n - 1; j >= 0; j--) | |
2353 | { | |
1756cb66 VM |
2354 | regno = ira_class_hard_regs[aclass][j]; |
2355 | skip_p = false; | |
2356 | FOR_EACH_ALLOCNO_OBJECT (a, obj, oi) | |
2357 | { | |
9181a6e5 VM |
2358 | if (ira_hard_reg_set_intersection_p (regno, mode, |
2359 | OBJECT_CONFLICT_HARD_REGS | |
2360 | (obj))) | |
1756cb66 VM |
2361 | { |
2362 | skip_p = true; | |
2363 | break; | |
2364 | } | |
2365 | } | |
2366 | if (skip_p) | |
2367 | continue; | |
058e97ec VM |
2368 | rclass = REGNO_REG_CLASS (regno); |
2369 | cost = 0; | |
6c476222 | 2370 | if (ira_need_caller_save_p (a, regno)) |
811e4f15 TV |
2371 | cost += (ALLOCNO_CALL_FREQ (a) |
2372 | * (ira_memory_move_cost[mode][rclass][0] | |
2373 | + ira_memory_move_cost[mode][rclass][1])); | |
058e97ec | 2374 | #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER |
811e4f15 TV |
2375 | cost += ((ira_memory_move_cost[mode][rclass][0] |
2376 | + ira_memory_move_cost[mode][rclass][1]) | |
2377 | * ALLOCNO_FREQ (a) | |
2378 | * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2); | |
058e97ec | 2379 | #endif |
1756cb66 VM |
2380 | if (INT_MAX - cost < reg_costs[j]) |
2381 | reg_costs[j] = INT_MAX; | |
2382 | else | |
2383 | reg_costs[j] += cost; | |
058e97ec VM |
2384 | if (min_cost > reg_costs[j]) |
2385 | min_cost = reg_costs[j]; | |
2386 | } | |
2387 | } | |
2388 | if (min_cost != INT_MAX) | |
1756cb66 | 2389 | ALLOCNO_CLASS_COST (a) = min_cost; |
0583835c | 2390 | |
8908df28 EB |
2391 | /* Some targets allow pseudos to be allocated to unaligned sequences |
2392 | of hard registers. However, selecting an unaligned sequence can | |
2393 | unnecessarily restrict later allocations. So increase the cost of | |
2394 | unaligned hard regs to encourage the use of aligned hard regs. */ | |
0583835c | 2395 | { |
1756cb66 | 2396 | const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)]; |
0583835c | 2397 | |
8908df28 | 2398 | if (nregs > 1) |
0583835c VM |
2399 | { |
2400 | ira_allocate_and_set_costs | |
1756cb66 | 2401 | (&ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a)); |
0583835c VM |
2402 | reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
2403 | for (j = n - 1; j >= 0; j--) | |
2404 | { | |
1756cb66 | 2405 | regno = ira_non_ordered_class_hard_regs[aclass][j]; |
8908df28 | 2406 | if ((regno % nregs) != 0) |
0583835c | 2407 | { |
1756cb66 | 2408 | int index = ira_class_hard_reg_index[aclass][regno]; |
c6d0f11a | 2409 | ira_assert (index != -1); |
0583835c VM |
2410 | reg_costs[index] += ALLOCNO_FREQ (a); |
2411 | } | |
2412 | } | |
2413 | } | |
2414 | } | |
058e97ec VM |
2415 | } |
2416 | } | |
8ff49c29 BS |
2417 | |
2418 | /* Add COST to the estimated gain for eliminating REGNO with its | |
2419 | equivalence. If COST is zero, record that no such elimination is | |
2420 | possible. */ | |
2421 | ||
2422 | void | |
2423 | ira_adjust_equiv_reg_cost (unsigned regno, int cost) | |
2424 | { | |
2425 | if (cost == 0) | |
2426 | regno_equiv_gains[regno] = 0; | |
2427 | else | |
2428 | regno_equiv_gains[regno] += cost; | |
2429 | } | |
eec42458 DM |
2430 | |
2431 | void | |
2432 | ira_costs_c_finalize (void) | |
2433 | { | |
2434 | this_target_ira_int->free_ira_costs (); | |
2435 | } |