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a7dcf969 | 1 | /* IRA hard register and memory cost calculation for allocnos or pseudos. |
fbd26352 | 2 | Copyright (C) 2006-2019 Free Software Foundation, Inc. |
47dd2e78 | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
9ef16211 | 24 | #include "backend.h" |
7c29e30e | 25 | #include "target.h" |
47dd2e78 | 26 | #include "rtl.h" |
9ef16211 | 27 | #include "tree.h" |
7c29e30e | 28 | #include "predict.h" |
ad7b10a2 | 29 | #include "memmodel.h" |
7c29e30e | 30 | #include "tm_p.h" |
7c29e30e | 31 | #include "insn-config.h" |
32 | #include "regs.h" | |
33 | #include "ira.h" | |
34 | #include "ira-int.h" | |
47dd2e78 | 35 | #include "addresses.h" |
4164ad58 | 36 | #include "reload.h" |
47dd2e78 | 37 | |
a7dcf969 | 38 | /* The flags is set up every time when we calculate pseudo register |
39 | classes through function ira_set_pseudo_classes. */ | |
40 | static bool pseudo_classes_defined_p = false; | |
41 | ||
42 | /* TRUE if we work with allocnos. Otherwise we work with pseudos. */ | |
43 | static bool allocno_p; | |
44 | ||
d12ecbda | 45 | /* Number of elements in array `costs'. */ |
a7dcf969 | 46 | static int cost_elements_num; |
47dd2e78 | 47 | |
47dd2e78 | 48 | /* The `costs' struct records the cost of using hard registers of each |
49 | class considered for the calculation and of using memory for each | |
a7dcf969 | 50 | allocno or pseudo. */ |
47dd2e78 | 51 | struct costs |
52 | { | |
53 | int mem_cost; | |
54 | /* Costs for register classes start here. We process only some | |
66d9a7b9 | 55 | allocno classes. */ |
47dd2e78 | 56 | int cost[1]; |
57 | }; | |
58 | ||
74b4a59f | 59 | #define max_struct_costs_size \ |
60 | (this_target_ira_int->x_max_struct_costs_size) | |
61 | #define init_cost \ | |
62 | (this_target_ira_int->x_init_cost) | |
63 | #define temp_costs \ | |
64 | (this_target_ira_int->x_temp_costs) | |
65 | #define op_costs \ | |
66 | (this_target_ira_int->x_op_costs) | |
67 | #define this_op_costs \ | |
68 | (this_target_ira_int->x_this_op_costs) | |
47dd2e78 | 69 | |
a7dcf969 | 70 | /* Costs of each class for each allocno or pseudo. */ |
71 | static struct costs *costs; | |
72 | ||
73 | /* Accumulated costs of each class for each allocno. */ | |
74 | static struct costs *total_allocno_costs; | |
47dd2e78 | 75 | |
47dd2e78 | 76 | /* It is the current size of struct costs. */ |
7cadd19a | 77 | static size_t struct_costs_size; |
47dd2e78 | 78 | |
a7dcf969 | 79 | /* Return pointer to structure containing costs of allocno or pseudo |
80 | with given NUM in array ARR. */ | |
81 | #define COSTS(arr, num) \ | |
47dd2e78 | 82 | ((struct costs *) ((char *) (arr) + (num) * struct_costs_size)) |
83 | ||
a7dcf969 | 84 | /* Return index in COSTS when processing reg with REGNO. */ |
66d9a7b9 | 85 | #define COST_INDEX(regno) (allocno_p \ |
86 | ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \ | |
a7dcf969 | 87 | : (int) regno) |
47dd2e78 | 88 | |
a7dcf969 | 89 | /* Record register class preferences of each allocno or pseudo. Null |
90 | value means no preferences. It happens on the 1st iteration of the | |
91 | cost calculation. */ | |
92 | static enum reg_class *pref; | |
47dd2e78 | 93 | |
a7dcf969 | 94 | /* Allocated buffers for pref. */ |
95 | static enum reg_class *pref_buffer; | |
96 | ||
66d9a7b9 | 97 | /* Record allocno class of each allocno with the same regno. */ |
98 | static enum reg_class *regno_aclass; | |
14792f4e | 99 | |
4164ad58 | 100 | /* Record cost gains for not allocating a register with an invariant |
101 | equivalence. */ | |
102 | static int *regno_equiv_gains; | |
103 | ||
47dd2e78 | 104 | /* Execution frequency of the current insn. */ |
105 | static int frequency; | |
106 | ||
107 | \f | |
108 | ||
66d9a7b9 | 109 | /* Info about reg classes whose costs are calculated for a pseudo. */ |
110 | struct cost_classes | |
111 | { | |
112 | /* Number of the cost classes in the subsequent array. */ | |
113 | int num; | |
114 | /* Container of the cost classes. */ | |
115 | enum reg_class classes[N_REG_CLASSES]; | |
116 | /* Map reg class -> index of the reg class in the previous array. | |
b59bd98f | 117 | -1 if it is not a cost class. */ |
66d9a7b9 | 118 | int index[N_REG_CLASSES]; |
119 | /* Map hard regno index of first class in array CLASSES containing | |
120 | the hard regno, -1 otherwise. */ | |
121 | int hard_regno_index[FIRST_PSEUDO_REGISTER]; | |
122 | }; | |
123 | ||
124 | /* Types of pointers to the structure above. */ | |
125 | typedef struct cost_classes *cost_classes_t; | |
126 | typedef const struct cost_classes *const_cost_classes_t; | |
127 | ||
128 | /* Info about cost classes for each pseudo. */ | |
129 | static cost_classes_t *regno_cost_classes; | |
130 | ||
d9dd21a8 | 131 | /* Helper for cost_classes hashing. */ |
132 | ||
576d4555 | 133 | struct cost_classes_hasher : pointer_hash <cost_classes> |
66d9a7b9 | 134 | { |
9969c043 | 135 | static inline hashval_t hash (const cost_classes *); |
136 | static inline bool equal (const cost_classes *, const cost_classes *); | |
137 | static inline void remove (cost_classes *); | |
d9dd21a8 | 138 | }; |
66d9a7b9 | 139 | |
d9dd21a8 | 140 | /* Returns hash value for cost classes info HV. */ |
141 | inline hashval_t | |
9969c043 | 142 | cost_classes_hasher::hash (const cost_classes *hv) |
d9dd21a8 | 143 | { |
66d9a7b9 | 144 | return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0); |
145 | } | |
146 | ||
d9dd21a8 | 147 | /* Compares cost classes info HV1 and HV2. */ |
148 | inline bool | |
9969c043 | 149 | cost_classes_hasher::equal (const cost_classes *hv1, const cost_classes *hv2) |
66d9a7b9 | 150 | { |
4433d0ad | 151 | return (hv1->num == hv2->num |
152 | && memcmp (hv1->classes, hv2->classes, | |
153 | sizeof (enum reg_class) * hv1->num) == 0); | |
66d9a7b9 | 154 | } |
155 | ||
156 | /* Delete cost classes info V from the hash table. */ | |
d9dd21a8 | 157 | inline void |
9969c043 | 158 | cost_classes_hasher::remove (cost_classes *v) |
66d9a7b9 | 159 | { |
160 | ira_free (v); | |
161 | } | |
162 | ||
163 | /* Hash table of unique cost classes. */ | |
c1f445d2 | 164 | static hash_table<cost_classes_hasher> *cost_classes_htab; |
66d9a7b9 | 165 | |
166 | /* Map allocno class -> cost classes for pseudo of given allocno | |
167 | class. */ | |
168 | static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES]; | |
169 | ||
170 | /* Map mode -> cost classes for pseudo of give mode. */ | |
171 | static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE]; | |
172 | ||
4aafe239 | 173 | /* Cost classes that include all classes in ira_important_classes. */ |
174 | static cost_classes all_cost_classes; | |
175 | ||
176 | /* Use the array of classes in CLASSES_PTR to fill out the rest of | |
177 | the structure. */ | |
178 | static void | |
179 | complete_cost_classes (cost_classes_t classes_ptr) | |
180 | { | |
181 | for (int i = 0; i < N_REG_CLASSES; i++) | |
182 | classes_ptr->index[i] = -1; | |
183 | for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
184 | classes_ptr->hard_regno_index[i] = -1; | |
185 | for (int i = 0; i < classes_ptr->num; i++) | |
186 | { | |
187 | enum reg_class cl = classes_ptr->classes[i]; | |
188 | classes_ptr->index[cl] = i; | |
189 | for (int j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--) | |
190 | { | |
191 | unsigned int hard_regno = ira_class_hard_regs[cl][j]; | |
192 | if (classes_ptr->hard_regno_index[hard_regno] < 0) | |
193 | classes_ptr->hard_regno_index[hard_regno] = i; | |
194 | } | |
195 | } | |
196 | } | |
197 | ||
66d9a7b9 | 198 | /* Initialize info about the cost classes for each pseudo. */ |
199 | static void | |
200 | initiate_regno_cost_classes (void) | |
201 | { | |
202 | int size = sizeof (cost_classes_t) * max_reg_num (); | |
203 | ||
204 | regno_cost_classes = (cost_classes_t *) ira_allocate (size); | |
205 | memset (regno_cost_classes, 0, size); | |
206 | memset (cost_classes_aclass_cache, 0, | |
207 | sizeof (cost_classes_t) * N_REG_CLASSES); | |
208 | memset (cost_classes_mode_cache, 0, | |
209 | sizeof (cost_classes_t) * MAX_MACHINE_MODE); | |
c1f445d2 | 210 | cost_classes_htab = new hash_table<cost_classes_hasher> (200); |
4aafe239 | 211 | all_cost_classes.num = ira_important_classes_num; |
212 | for (int i = 0; i < ira_important_classes_num; i++) | |
213 | all_cost_classes.classes[i] = ira_important_classes[i]; | |
214 | complete_cost_classes (&all_cost_classes); | |
66d9a7b9 | 215 | } |
216 | ||
217 | /* Create new cost classes from cost classes FROM and set up members | |
218 | index and hard_regno_index. Return the new classes. The function | |
219 | implements some common code of two functions | |
220 | setup_regno_cost_classes_by_aclass and | |
221 | setup_regno_cost_classes_by_mode. */ | |
222 | static cost_classes_t | |
223 | setup_cost_classes (cost_classes_t from) | |
224 | { | |
225 | cost_classes_t classes_ptr; | |
66d9a7b9 | 226 | |
227 | classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes)); | |
228 | classes_ptr->num = from->num; | |
4aafe239 | 229 | for (int i = 0; i < from->num; i++) |
230 | classes_ptr->classes[i] = from->classes[i]; | |
231 | complete_cost_classes (classes_ptr); | |
232 | return classes_ptr; | |
233 | } | |
234 | ||
235 | /* Return a version of FULL that only considers registers in REGS that are | |
236 | valid for mode MODE. Both FULL and the returned class are globally | |
237 | allocated. */ | |
238 | static cost_classes_t | |
3754d046 | 239 | restrict_cost_classes (cost_classes_t full, machine_mode mode, |
4aafe239 | 240 | const HARD_REG_SET ®s) |
241 | { | |
242 | static struct cost_classes narrow; | |
243 | int map[N_REG_CLASSES]; | |
244 | narrow.num = 0; | |
245 | for (int i = 0; i < full->num; i++) | |
66d9a7b9 | 246 | { |
4aafe239 | 247 | /* Assume that we'll drop the class. */ |
248 | map[i] = -1; | |
249 | ||
250 | /* Ignore classes that are too small for the mode. */ | |
251 | enum reg_class cl = full->classes[i]; | |
252 | if (!contains_reg_of_mode[cl][mode]) | |
253 | continue; | |
254 | ||
255 | /* Calculate the set of registers in CL that belong to REGS and | |
256 | are valid for MODE. */ | |
257 | HARD_REG_SET valid_for_cl; | |
258 | COPY_HARD_REG_SET (valid_for_cl, reg_class_contents[cl]); | |
259 | AND_HARD_REG_SET (valid_for_cl, regs); | |
260 | AND_COMPL_HARD_REG_SET (valid_for_cl, | |
261 | ira_prohibited_class_mode_regs[cl][mode]); | |
262 | AND_COMPL_HARD_REG_SET (valid_for_cl, ira_no_alloc_regs); | |
263 | if (hard_reg_set_empty_p (valid_for_cl)) | |
264 | continue; | |
265 | ||
266 | /* Don't use this class if the set of valid registers is a subset | |
267 | of an existing class. For example, suppose we have two classes | |
268 | GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose | |
269 | that the mode changes allowed by FR_REGS are not as general as | |
270 | the mode changes allowed by GR_REGS. | |
271 | ||
272 | In this situation, the mode changes for GR_AND_FR_REGS could | |
273 | either be seen as the union or the intersection of the mode | |
274 | changes allowed by the two subclasses. The justification for | |
275 | the union-based definition would be that, if you want a mode | |
276 | change that's only allowed by GR_REGS, you can pick a register | |
277 | from the GR_REGS subclass. The justification for the | |
278 | intersection-based definition would be that every register | |
279 | from the class would allow the mode change. | |
280 | ||
281 | However, if we have a register that needs to be in GR_REGS, | |
282 | using GR_AND_FR_REGS with the intersection-based definition | |
283 | would be too pessimistic, since it would bring in restrictions | |
284 | that only apply to FR_REGS. Conversely, if we have a register | |
285 | that needs to be in FR_REGS, using GR_AND_FR_REGS with the | |
286 | union-based definition would lose the extra restrictions | |
287 | placed on FR_REGS. GR_AND_FR_REGS is therefore only useful | |
288 | for cases where GR_REGS and FP_REGS are both valid. */ | |
289 | int pos; | |
290 | for (pos = 0; pos < narrow.num; ++pos) | |
66d9a7b9 | 291 | { |
4aafe239 | 292 | enum reg_class cl2 = narrow.classes[pos]; |
293 | if (hard_reg_set_subset_p (valid_for_cl, reg_class_contents[cl2])) | |
294 | break; | |
295 | } | |
296 | map[i] = pos; | |
297 | if (pos == narrow.num) | |
298 | { | |
299 | /* If several classes are equivalent, prefer to use the one | |
300 | that was chosen as the allocno class. */ | |
301 | enum reg_class cl2 = ira_allocno_class_translate[cl]; | |
302 | if (ira_class_hard_regs_num[cl] == ira_class_hard_regs_num[cl2]) | |
303 | cl = cl2; | |
304 | narrow.classes[narrow.num++] = cl; | |
66d9a7b9 | 305 | } |
306 | } | |
4aafe239 | 307 | if (narrow.num == full->num) |
308 | return full; | |
309 | ||
310 | cost_classes **slot = cost_classes_htab->find_slot (&narrow, INSERT); | |
311 | if (*slot == NULL) | |
312 | { | |
313 | cost_classes_t classes = setup_cost_classes (&narrow); | |
314 | /* Map equivalent classes to the representative that we chose above. */ | |
315 | for (int i = 0; i < ira_important_classes_num; i++) | |
316 | { | |
317 | enum reg_class cl = ira_important_classes[i]; | |
318 | int index = full->index[cl]; | |
319 | if (index >= 0) | |
320 | classes->index[cl] = map[index]; | |
321 | } | |
322 | *slot = classes; | |
323 | } | |
324 | return *slot; | |
66d9a7b9 | 325 | } |
326 | ||
327 | /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS. | |
328 | This function is used when we know an initial approximation of | |
329 | allocno class of the pseudo already, e.g. on the second iteration | |
330 | of class cost calculation or after class cost calculation in | |
331 | register-pressure sensitive insn scheduling or register-pressure | |
332 | sensitive loop-invariant motion. */ | |
333 | static void | |
334 | setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass) | |
335 | { | |
336 | static struct cost_classes classes; | |
337 | cost_classes_t classes_ptr; | |
338 | enum reg_class cl; | |
339 | int i; | |
d9dd21a8 | 340 | cost_classes **slot; |
66d9a7b9 | 341 | HARD_REG_SET temp, temp2; |
42f875c3 | 342 | bool exclude_p; |
66d9a7b9 | 343 | |
344 | if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL) | |
345 | { | |
346 | COPY_HARD_REG_SET (temp, reg_class_contents[aclass]); | |
347 | AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs); | |
42f875c3 | 348 | /* We exclude classes from consideration which are subsets of |
b48acad0 | 349 | ACLASS only if ACLASS is an uniform class. */ |
350 | exclude_p = ira_uniform_class_p[aclass]; | |
66d9a7b9 | 351 | classes.num = 0; |
352 | for (i = 0; i < ira_important_classes_num; i++) | |
353 | { | |
354 | cl = ira_important_classes[i]; | |
42f875c3 | 355 | if (exclude_p) |
356 | { | |
b48acad0 | 357 | /* Exclude non-uniform classes which are subsets of |
42f875c3 | 358 | ACLASS. */ |
359 | COPY_HARD_REG_SET (temp2, reg_class_contents[cl]); | |
360 | AND_COMPL_HARD_REG_SET (temp2, ira_no_alloc_regs); | |
b48acad0 | 361 | if (hard_reg_set_subset_p (temp2, temp) && cl != aclass) |
42f875c3 | 362 | continue; |
363 | } | |
66d9a7b9 | 364 | classes.classes[classes.num++] = cl; |
365 | } | |
c1f445d2 | 366 | slot = cost_classes_htab->find_slot (&classes, INSERT); |
66d9a7b9 | 367 | if (*slot == NULL) |
368 | { | |
369 | classes_ptr = setup_cost_classes (&classes); | |
370 | *slot = classes_ptr; | |
371 | } | |
372 | classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot; | |
373 | } | |
4aafe239 | 374 | if (regno_reg_rtx[regno] != NULL_RTX) |
511b66fb | 375 | { |
376 | /* Restrict the classes to those that are valid for REGNO's mode | |
377 | (which might for example exclude singleton classes if the mode | |
378 | requires two registers). Also restrict the classes to those that | |
379 | are valid for subregs of REGNO. */ | |
380 | const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno); | |
381 | if (!valid_regs) | |
382 | valid_regs = ®_class_contents[ALL_REGS]; | |
383 | classes_ptr = restrict_cost_classes (classes_ptr, | |
384 | PSEUDO_REGNO_MODE (regno), | |
385 | *valid_regs); | |
386 | } | |
66d9a7b9 | 387 | regno_cost_classes[regno] = classes_ptr; |
388 | } | |
389 | ||
390 | /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can | |
391 | decrease number of cost classes for the pseudo, if hard registers | |
392 | of some important classes can not hold a value of MODE. So the | |
393 | pseudo can not get hard register of some important classes and cost | |
b59bd98f | 394 | calculation for such important classes is only wasting CPU |
66d9a7b9 | 395 | time. */ |
396 | static void | |
3754d046 | 397 | setup_regno_cost_classes_by_mode (int regno, machine_mode mode) |
66d9a7b9 | 398 | { |
511b66fb | 399 | if (const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno)) |
400 | regno_cost_classes[regno] = restrict_cost_classes (&all_cost_classes, | |
401 | mode, *valid_regs); | |
402 | else | |
403 | { | |
404 | if (cost_classes_mode_cache[mode] == NULL) | |
405 | cost_classes_mode_cache[mode] | |
406 | = restrict_cost_classes (&all_cost_classes, mode, | |
407 | reg_class_contents[ALL_REGS]); | |
408 | regno_cost_classes[regno] = cost_classes_mode_cache[mode]; | |
409 | } | |
66d9a7b9 | 410 | } |
411 | ||
b59bd98f | 412 | /* Finalize info about the cost classes for each pseudo. */ |
66d9a7b9 | 413 | static void |
414 | finish_regno_cost_classes (void) | |
415 | { | |
416 | ira_free (regno_cost_classes); | |
c1f445d2 | 417 | delete cost_classes_htab; |
418 | cost_classes_htab = NULL; | |
66d9a7b9 | 419 | } |
420 | ||
421 | \f | |
422 | ||
47dd2e78 | 423 | /* Compute the cost of loading X into (if TO_P is TRUE) or from (if |
424 | TO_P is FALSE) a register of class RCLASS in mode MODE. X must not | |
425 | be a pseudo register. */ | |
426 | static int | |
3754d046 | 427 | copy_cost (rtx x, machine_mode mode, reg_class_t rclass, bool to_p, |
47dd2e78 | 428 | secondary_reload_info *prev_sri) |
429 | { | |
430 | secondary_reload_info sri; | |
09a17585 | 431 | reg_class_t secondary_class = NO_REGS; |
47dd2e78 | 432 | |
433 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
434 | assuming optimal allocation. */ | |
435 | if (GET_CODE (x) == SCRATCH) | |
436 | return 0; | |
437 | ||
438 | /* Get the class we will actually use for a reload. */ | |
09a17585 | 439 | rclass = targetm.preferred_reload_class (x, rclass); |
47dd2e78 | 440 | |
441 | /* If we need a secondary reload for an intermediate, the cost is | |
442 | that to load the input into the intermediate register, then to | |
443 | copy it. */ | |
444 | sri.prev_sri = prev_sri; | |
445 | sri.extra_cost = 0; | |
5beb12c0 | 446 | /* PR 68770: Secondary reload might examine the t_icode field. */ |
447 | sri.t_icode = CODE_FOR_nothing; | |
448 | ||
09a17585 | 449 | secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri); |
47dd2e78 | 450 | |
47dd2e78 | 451 | if (secondary_class != NO_REGS) |
3f9f9860 | 452 | { |
ad8d4dca | 453 | ira_init_register_move_cost_if_necessary (mode); |
454 | return (ira_register_move_cost[mode][(int) secondary_class][(int) rclass] | |
09a17585 | 455 | + sri.extra_cost |
3f9f9860 | 456 | + copy_cost (x, mode, secondary_class, to_p, &sri)); |
457 | } | |
47dd2e78 | 458 | |
459 | /* For memory, use the memory move cost, for (hard) registers, use | |
460 | the cost to move between the register classes, and use 2 for | |
461 | everything else (constants). */ | |
462 | if (MEM_P (x) || rclass == NO_REGS) | |
09a17585 | 463 | return sri.extra_cost |
464 | + ira_memory_move_cost[mode][(int) rclass][to_p != 0]; | |
47dd2e78 | 465 | else if (REG_P (x)) |
3f9f9860 | 466 | { |
ad8d4dca | 467 | reg_class_t x_class = REGNO_REG_CLASS (REGNO (x)); |
468 | ||
469 | ira_init_register_move_cost_if_necessary (mode); | |
09a17585 | 470 | return (sri.extra_cost |
ad8d4dca | 471 | + ira_register_move_cost[mode][(int) x_class][(int) rclass]); |
3f9f9860 | 472 | } |
47dd2e78 | 473 | else |
474 | /* If this is a constant, we may eventually want to call rtx_cost | |
475 | here. */ | |
476 | return sri.extra_cost + COSTS_N_INSNS (1); | |
477 | } | |
478 | ||
479 | \f | |
480 | ||
481 | /* Record the cost of using memory or hard registers of various | |
482 | classes for the operands in INSN. | |
483 | ||
484 | N_ALTS is the number of alternatives. | |
485 | N_OPS is the number of operands. | |
486 | OPS is an array of the operands. | |
487 | MODES are the modes of the operands, in case any are VOIDmode. | |
488 | CONSTRAINTS are the constraints to use for the operands. This array | |
489 | is modified by this procedure. | |
490 | ||
491 | This procedure works alternative by alternative. For each | |
492 | alternative we assume that we will be able to allocate all allocnos | |
493 | to their ideal register class and calculate the cost of using that | |
494 | alternative. Then we compute, for each operand that is a | |
495 | pseudo-register, the cost of having the allocno allocated to each | |
496 | register class and using it in that alternative. To this cost is | |
497 | added the cost of the alternative. | |
498 | ||
499 | The cost of each class for this insn is its lowest cost among all | |
500 | the alternatives. */ | |
501 | static void | |
502 | record_reg_classes (int n_alts, int n_ops, rtx *ops, | |
3754d046 | 503 | machine_mode *modes, const char **constraints, |
56067879 | 504 | rtx_insn *insn, enum reg_class *pref) |
47dd2e78 | 505 | { |
506 | int alt; | |
507 | int i, j, k; | |
68d4bdfb | 508 | int insn_allows_mem[MAX_RECOG_OPERANDS]; |
c5d7f2f6 | 509 | move_table *move_in_cost, *move_out_cost; |
510 | short (*mem_cost)[2]; | |
68d4bdfb | 511 | |
512 | for (i = 0; i < n_ops; i++) | |
513 | insn_allows_mem[i] = 0; | |
47dd2e78 | 514 | |
515 | /* Process each alternative, each time minimizing an operand's cost | |
516 | with the cost for each operand in that alternative. */ | |
e1a797ad | 517 | alternative_mask preferred = get_preferred_alternatives (insn); |
47dd2e78 | 518 | for (alt = 0; alt < n_alts; alt++) |
519 | { | |
520 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
521 | int allows_mem[MAX_RECOG_OPERANDS]; | |
b9c74b4d | 522 | enum reg_class rclass; |
47dd2e78 | 523 | int alt_fail = 0; |
524 | int alt_cost = 0, op_cost_add; | |
525 | ||
e1a797ad | 526 | if (!TEST_BIT (preferred, alt)) |
26f5b5dd | 527 | { |
528 | for (i = 0; i < recog_data.n_operands; i++) | |
529 | constraints[i] = skip_alternative (constraints[i]); | |
530 | ||
531 | continue; | |
532 | } | |
533 | ||
47dd2e78 | 534 | for (i = 0; i < n_ops; i++) |
535 | { | |
536 | unsigned char c; | |
537 | const char *p = constraints[i]; | |
538 | rtx op = ops[i]; | |
3754d046 | 539 | machine_mode mode = modes[i]; |
47dd2e78 | 540 | int allows_addr = 0; |
541 | int win = 0; | |
542 | ||
543 | /* Initially show we know nothing about the register class. */ | |
544 | classes[i] = NO_REGS; | |
545 | allows_mem[i] = 0; | |
546 | ||
547 | /* If this operand has no constraints at all, we can | |
548 | conclude nothing about it since anything is valid. */ | |
549 | if (*p == 0) | |
550 | { | |
551 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
552 | memset (this_op_costs[i], 0, struct_costs_size); | |
553 | continue; | |
554 | } | |
555 | ||
556 | /* If this alternative is only relevant when this operand | |
557 | matches a previous operand, we do different things | |
558 | depending on whether this operand is a allocno-reg or not. | |
559 | We must process any modifiers for the operand before we | |
560 | can make this test. */ | |
561 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') | |
562 | p++; | |
563 | ||
ec44a0da | 564 | if (p[0] >= '0' && p[0] <= '0' + i) |
47dd2e78 | 565 | { |
566 | /* Copy class and whether memory is allowed from the | |
567 | matching alternative. Then perform any needed cost | |
568 | computations and/or adjustments. */ | |
569 | j = p[0] - '0'; | |
570 | classes[i] = classes[j]; | |
571 | allows_mem[i] = allows_mem[j]; | |
68d4bdfb | 572 | if (allows_mem[i]) |
573 | insn_allows_mem[i] = 1; | |
47dd2e78 | 574 | |
575 | if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
576 | { | |
577 | /* If this matches the other operand, we have no | |
578 | added cost and we win. */ | |
579 | if (rtx_equal_p (ops[j], op)) | |
580 | win = 1; | |
581 | /* If we can put the other operand into a register, | |
582 | add to the cost of this alternative the cost to | |
583 | copy this operand to the register used for the | |
584 | other operand. */ | |
585 | else if (classes[j] != NO_REGS) | |
586 | { | |
587 | alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
588 | win = 1; | |
589 | } | |
590 | } | |
591 | else if (! REG_P (ops[j]) | |
592 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
593 | { | |
594 | /* This op is an allocno but the one it matches is | |
595 | not. */ | |
596 | ||
597 | /* If we can't put the other operand into a | |
598 | register, this alternative can't be used. */ | |
599 | ||
600 | if (classes[j] == NO_REGS) | |
601 | alt_fail = 1; | |
602 | /* Otherwise, add to the cost of this alternative | |
603 | the cost to copy the other operand to the hard | |
604 | register used for this operand. */ | |
605 | else | |
606 | alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); | |
607 | } | |
608 | else | |
609 | { | |
610 | /* The costs of this operand are not the same as the | |
611 | other operand since move costs are not symmetric. | |
612 | Moreover, if we cannot tie them, this alternative | |
613 | needs to do a copy, which is one insn. */ | |
614 | struct costs *pp = this_op_costs[i]; | |
66d9a7b9 | 615 | int *pp_costs = pp->cost; |
616 | cost_classes_t cost_classes_ptr | |
617 | = regno_cost_classes[REGNO (op)]; | |
618 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
619 | bool in_p = recog_data.operand_type[i] != OP_OUT; | |
620 | bool out_p = recog_data.operand_type[i] != OP_IN; | |
621 | enum reg_class op_class = classes[i]; | |
66d9a7b9 | 622 | |
623 | ira_init_register_move_cost_if_necessary (mode); | |
624 | if (! in_p) | |
28491485 | 625 | { |
66d9a7b9 | 626 | ira_assert (out_p); |
c5d7f2f6 | 627 | if (op_class == NO_REGS) |
66d9a7b9 | 628 | { |
c5d7f2f6 | 629 | mem_cost = ira_memory_move_cost[mode]; |
630 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
631 | { | |
632 | rclass = cost_classes[k]; | |
633 | pp_costs[k] = mem_cost[rclass][0] * frequency; | |
634 | } | |
635 | } | |
636 | else | |
637 | { | |
638 | move_out_cost = ira_may_move_out_cost[mode]; | |
639 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
640 | { | |
641 | rclass = cost_classes[k]; | |
642 | pp_costs[k] | |
643 | = move_out_cost[op_class][rclass] * frequency; | |
644 | } | |
66d9a7b9 | 645 | } |
646 | } | |
647 | else if (! out_p) | |
648 | { | |
649 | ira_assert (in_p); | |
c5d7f2f6 | 650 | if (op_class == NO_REGS) |
66d9a7b9 | 651 | { |
c5d7f2f6 | 652 | mem_cost = ira_memory_move_cost[mode]; |
653 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
654 | { | |
655 | rclass = cost_classes[k]; | |
656 | pp_costs[k] = mem_cost[rclass][1] * frequency; | |
657 | } | |
658 | } | |
659 | else | |
660 | { | |
661 | move_in_cost = ira_may_move_in_cost[mode]; | |
662 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
663 | { | |
664 | rclass = cost_classes[k]; | |
665 | pp_costs[k] | |
666 | = move_in_cost[rclass][op_class] * frequency; | |
667 | } | |
66d9a7b9 | 668 | } |
669 | } | |
670 | else | |
671 | { | |
c5d7f2f6 | 672 | if (op_class == NO_REGS) |
66d9a7b9 | 673 | { |
c5d7f2f6 | 674 | mem_cost = ira_memory_move_cost[mode]; |
675 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
676 | { | |
677 | rclass = cost_classes[k]; | |
678 | pp_costs[k] = ((mem_cost[rclass][0] | |
679 | + mem_cost[rclass][1]) | |
680 | * frequency); | |
681 | } | |
682 | } | |
683 | else | |
684 | { | |
685 | move_in_cost = ira_may_move_in_cost[mode]; | |
686 | move_out_cost = ira_may_move_out_cost[mode]; | |
687 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
688 | { | |
689 | rclass = cost_classes[k]; | |
690 | pp_costs[k] = ((move_in_cost[rclass][op_class] | |
691 | + move_out_cost[op_class][rclass]) | |
692 | * frequency); | |
693 | } | |
66d9a7b9 | 694 | } |
47dd2e78 | 695 | } |
696 | ||
697 | /* If the alternative actually allows memory, make | |
698 | things a bit cheaper since we won't need an extra | |
699 | insn to load it. */ | |
700 | pp->mem_cost | |
66d9a7b9 | 701 | = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0) |
702 | + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0) | |
47dd2e78 | 703 | - allows_mem[i]) * frequency; |
68d4bdfb | 704 | |
66d9a7b9 | 705 | /* If we have assigned a class to this allocno in |
706 | our first pass, add a cost to this alternative | |
707 | corresponding to what we would add if this | |
708 | allocno were not in the appropriate class. */ | |
a7dcf969 | 709 | if (pref) |
47dd2e78 | 710 | { |
a7dcf969 | 711 | enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
47dd2e78 | 712 | |
713 | if (pref_class == NO_REGS) | |
714 | alt_cost | |
66d9a7b9 | 715 | += ((out_p |
716 | ? ira_memory_move_cost[mode][op_class][0] : 0) | |
717 | + (in_p | |
718 | ? ira_memory_move_cost[mode][op_class][1] | |
47dd2e78 | 719 | : 0)); |
720 | else if (ira_reg_class_intersect | |
66d9a7b9 | 721 | [pref_class][op_class] == NO_REGS) |
722 | alt_cost | |
723 | += ira_register_move_cost[mode][pref_class][op_class]; | |
47dd2e78 | 724 | } |
725 | if (REGNO (ops[i]) != REGNO (ops[j]) | |
726 | && ! find_reg_note (insn, REG_DEAD, op)) | |
727 | alt_cost += 2; | |
728 | ||
ec44a0da | 729 | p++; |
47dd2e78 | 730 | } |
731 | } | |
48e1416a | 732 | |
47dd2e78 | 733 | /* Scan all the constraint letters. See if the operand |
734 | matches any of the constraints. Collect the valid | |
735 | register classes and see if this operand accepts | |
736 | memory. */ | |
737 | while ((c = *p)) | |
738 | { | |
739 | switch (c) | |
740 | { | |
47dd2e78 | 741 | case '*': |
742 | /* Ignore the next letter for this pass. */ | |
743 | c = *++p; | |
744 | break; | |
745 | ||
ed6272f7 | 746 | case '^': |
747 | alt_cost += 2; | |
748 | break; | |
749 | ||
47dd2e78 | 750 | case '?': |
751 | alt_cost += 2; | |
47dd2e78 | 752 | break; |
753 | ||
754 | case 'g': | |
755 | if (MEM_P (op) | |
756 | || (CONSTANT_P (op) | |
757 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) | |
758 | win = 1; | |
68d4bdfb | 759 | insn_allows_mem[i] = allows_mem[i] = 1; |
66d9a7b9 | 760 | classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; |
47dd2e78 | 761 | break; |
762 | ||
763 | default: | |
79bc09fb | 764 | enum constraint_num cn = lookup_constraint (p); |
765 | enum reg_class cl; | |
766 | switch (get_constraint_type (cn)) | |
47dd2e78 | 767 | { |
79bc09fb | 768 | case CT_REGISTER: |
769 | cl = reg_class_for_constraint (cn); | |
770 | if (cl != NO_REGS) | |
771 | classes[i] = ira_reg_class_subunion[classes[i]][cl]; | |
772 | break; | |
773 | ||
4e67d0bf | 774 | case CT_CONST_INT: |
775 | if (CONST_INT_P (op) | |
776 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
777 | win = 1; | |
778 | break; | |
779 | ||
79bc09fb | 780 | case CT_MEMORY: |
47dd2e78 | 781 | /* Every MEM can be reloaded to fit. */ |
68d4bdfb | 782 | insn_allows_mem[i] = allows_mem[i] = 1; |
47dd2e78 | 783 | if (MEM_P (op)) |
784 | win = 1; | |
79bc09fb | 785 | break; |
786 | ||
6b3b345a | 787 | case CT_SPECIAL_MEMORY: |
788 | insn_allows_mem[i] = allows_mem[i] = 1; | |
789 | if (MEM_P (op) && constraint_satisfied_p (op, cn)) | |
790 | win = 1; | |
791 | break; | |
792 | ||
79bc09fb | 793 | case CT_ADDRESS: |
47dd2e78 | 794 | /* Every address can be reloaded to fit. */ |
795 | allows_addr = 1; | |
79bc09fb | 796 | if (address_operand (op, GET_MODE (op)) |
797 | || constraint_satisfied_p (op, cn)) | |
47dd2e78 | 798 | win = 1; |
799 | /* We know this operand is an address, so we | |
800 | want it to be allocated to a hard register | |
801 | that can be the base of an address, | |
802 | i.e. BASE_REG_CLASS. */ | |
803 | classes[i] | |
66d9a7b9 | 804 | = ira_reg_class_subunion[classes[i]] |
f8a8fc7b | 805 | [base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, |
806 | ADDRESS, SCRATCH)]; | |
79bc09fb | 807 | break; |
808 | ||
809 | case CT_FIXED_FORM: | |
810 | if (constraint_satisfied_p (op, cn)) | |
811 | win = 1; | |
812 | break; | |
47dd2e78 | 813 | } |
47dd2e78 | 814 | break; |
815 | } | |
816 | p += CONSTRAINT_LEN (c, p); | |
817 | if (c == ',') | |
818 | break; | |
819 | } | |
820 | ||
821 | constraints[i] = p; | |
822 | ||
eb87bcd9 | 823 | if (alt_fail) |
824 | break; | |
825 | ||
47dd2e78 | 826 | /* How we account for this operand now depends on whether it |
827 | is a pseudo register or not. If it is, we first check if | |
828 | any register classes are valid. If not, we ignore this | |
829 | alternative, since we want to assume that all allocnos get | |
830 | allocated for register preferencing. If some register | |
831 | class is valid, compute the costs of moving the allocno | |
832 | into that class. */ | |
833 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
834 | { | |
1e5911a9 | 835 | if (classes[i] == NO_REGS && ! allows_mem[i]) |
47dd2e78 | 836 | { |
837 | /* We must always fail if the operand is a REG, but | |
1e5911a9 | 838 | we did not find a suitable class and memory is |
839 | not allowed. | |
47dd2e78 | 840 | |
841 | Otherwise we may perform an uninitialized read | |
842 | from this_op_costs after the `continue' statement | |
843 | below. */ | |
844 | alt_fail = 1; | |
845 | } | |
846 | else | |
847 | { | |
66d9a7b9 | 848 | unsigned int regno = REGNO (op); |
47dd2e78 | 849 | struct costs *pp = this_op_costs[i]; |
66d9a7b9 | 850 | int *pp_costs = pp->cost; |
851 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
852 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
853 | bool in_p = recog_data.operand_type[i] != OP_OUT; | |
854 | bool out_p = recog_data.operand_type[i] != OP_IN; | |
855 | enum reg_class op_class = classes[i]; | |
66d9a7b9 | 856 | |
857 | ira_init_register_move_cost_if_necessary (mode); | |
858 | if (! in_p) | |
28491485 | 859 | { |
66d9a7b9 | 860 | ira_assert (out_p); |
1e5911a9 | 861 | if (op_class == NO_REGS) |
66d9a7b9 | 862 | { |
1e5911a9 | 863 | mem_cost = ira_memory_move_cost[mode]; |
864 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
865 | { | |
866 | rclass = cost_classes[k]; | |
867 | pp_costs[k] = mem_cost[rclass][0] * frequency; | |
868 | } | |
869 | } | |
870 | else | |
871 | { | |
872 | move_out_cost = ira_may_move_out_cost[mode]; | |
873 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
874 | { | |
875 | rclass = cost_classes[k]; | |
876 | pp_costs[k] | |
877 | = move_out_cost[op_class][rclass] * frequency; | |
878 | } | |
66d9a7b9 | 879 | } |
880 | } | |
881 | else if (! out_p) | |
882 | { | |
883 | ira_assert (in_p); | |
1e5911a9 | 884 | if (op_class == NO_REGS) |
66d9a7b9 | 885 | { |
1e5911a9 | 886 | mem_cost = ira_memory_move_cost[mode]; |
887 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
888 | { | |
889 | rclass = cost_classes[k]; | |
890 | pp_costs[k] = mem_cost[rclass][1] * frequency; | |
891 | } | |
892 | } | |
893 | else | |
894 | { | |
895 | move_in_cost = ira_may_move_in_cost[mode]; | |
896 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
897 | { | |
898 | rclass = cost_classes[k]; | |
899 | pp_costs[k] | |
900 | = move_in_cost[rclass][op_class] * frequency; | |
901 | } | |
66d9a7b9 | 902 | } |
903 | } | |
904 | else | |
905 | { | |
1e5911a9 | 906 | if (op_class == NO_REGS) |
66d9a7b9 | 907 | { |
1e5911a9 | 908 | mem_cost = ira_memory_move_cost[mode]; |
909 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
910 | { | |
911 | rclass = cost_classes[k]; | |
912 | pp_costs[k] = ((mem_cost[rclass][0] | |
913 | + mem_cost[rclass][1]) | |
914 | * frequency); | |
915 | } | |
916 | } | |
917 | else | |
918 | { | |
919 | move_in_cost = ira_may_move_in_cost[mode]; | |
920 | move_out_cost = ira_may_move_out_cost[mode]; | |
921 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
922 | { | |
923 | rclass = cost_classes[k]; | |
924 | pp_costs[k] = ((move_in_cost[rclass][op_class] | |
925 | + move_out_cost[op_class][rclass]) | |
926 | * frequency); | |
927 | } | |
66d9a7b9 | 928 | } |
47dd2e78 | 929 | } |
930 | ||
c5d7f2f6 | 931 | if (op_class == NO_REGS) |
932 | /* Although we don't need insn to reload from | |
933 | memory, still accessing memory is usually more | |
934 | expensive than a register. */ | |
935 | pp->mem_cost = frequency; | |
936 | else | |
937 | /* If the alternative actually allows memory, make | |
938 | things a bit cheaper since we won't need an | |
939 | extra insn to load it. */ | |
1e5911a9 | 940 | pp->mem_cost |
941 | = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0) | |
942 | + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0) | |
943 | - allows_mem[i]) * frequency; | |
66d9a7b9 | 944 | /* If we have assigned a class to this allocno in |
945 | our first pass, add a cost to this alternative | |
946 | corresponding to what we would add if this | |
947 | allocno were not in the appropriate class. */ | |
a7dcf969 | 948 | if (pref) |
47dd2e78 | 949 | { |
a7dcf969 | 950 | enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
47dd2e78 | 951 | |
952 | if (pref_class == NO_REGS) | |
1e5911a9 | 953 | { |
954 | if (op_class != NO_REGS) | |
955 | alt_cost | |
956 | += ((out_p | |
957 | ? ira_memory_move_cost[mode][op_class][0] | |
958 | : 0) | |
959 | + (in_p | |
960 | ? ira_memory_move_cost[mode][op_class][1] | |
961 | : 0)); | |
962 | } | |
963 | else if (op_class == NO_REGS) | |
47dd2e78 | 964 | alt_cost |
66d9a7b9 | 965 | += ((out_p |
1e5911a9 | 966 | ? ira_memory_move_cost[mode][pref_class][1] |
967 | : 0) | |
66d9a7b9 | 968 | + (in_p |
1e5911a9 | 969 | ? ira_memory_move_cost[mode][pref_class][0] |
47dd2e78 | 970 | : 0)); |
66d9a7b9 | 971 | else if (ira_reg_class_intersect[pref_class][op_class] |
47dd2e78 | 972 | == NO_REGS) |
1e5911a9 | 973 | alt_cost += (ira_register_move_cost |
974 | [mode][pref_class][op_class]); | |
47dd2e78 | 975 | } |
976 | } | |
977 | } | |
978 | ||
979 | /* Otherwise, if this alternative wins, either because we | |
980 | have already determined that or if we have a hard | |
981 | register of the proper class, there is no cost for this | |
982 | alternative. */ | |
983 | else if (win || (REG_P (op) | |
984 | && reg_fits_class_p (op, classes[i], | |
985 | 0, GET_MODE (op)))) | |
986 | ; | |
987 | ||
988 | /* If registers are valid, the cost of this alternative | |
989 | includes copying the object to and/or from a | |
990 | register. */ | |
991 | else if (classes[i] != NO_REGS) | |
992 | { | |
993 | if (recog_data.operand_type[i] != OP_OUT) | |
994 | alt_cost += copy_cost (op, mode, classes[i], 1, NULL); | |
995 | ||
996 | if (recog_data.operand_type[i] != OP_IN) | |
997 | alt_cost += copy_cost (op, mode, classes[i], 0, NULL); | |
998 | } | |
999 | /* The only other way this alternative can be used is if | |
1000 | this is a constant that could be placed into memory. */ | |
1001 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) | |
1002 | alt_cost += ira_memory_move_cost[mode][classes[i]][1]; | |
1003 | else | |
1004 | alt_fail = 1; | |
eb87bcd9 | 1005 | |
1006 | if (alt_fail) | |
1007 | break; | |
47dd2e78 | 1008 | } |
1009 | ||
1010 | if (alt_fail) | |
eb87bcd9 | 1011 | { |
1012 | /* The loop above might have exited early once the failure | |
1013 | was seen. Skip over the constraints for the remaining | |
1014 | operands. */ | |
1015 | i += 1; | |
1016 | for (; i < n_ops; ++i) | |
1017 | constraints[i] = skip_alternative (constraints[i]); | |
1018 | continue; | |
1019 | } | |
47dd2e78 | 1020 | |
1021 | op_cost_add = alt_cost * frequency; | |
1022 | /* Finally, update the costs with the information we've | |
1023 | calculated about this alternative. */ | |
1024 | for (i = 0; i < n_ops; i++) | |
1025 | if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1026 | { | |
1027 | struct costs *pp = op_costs[i], *qq = this_op_costs[i]; | |
66d9a7b9 | 1028 | int *pp_costs = pp->cost, *qq_costs = qq->cost; |
47dd2e78 | 1029 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
66d9a7b9 | 1030 | cost_classes_t cost_classes_ptr |
1031 | = regno_cost_classes[REGNO (ops[i])]; | |
47dd2e78 | 1032 | |
1033 | pp->mem_cost = MIN (pp->mem_cost, | |
1034 | (qq->mem_cost + op_cost_add) * scale); | |
1035 | ||
66d9a7b9 | 1036 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) |
1037 | pp_costs[k] | |
1038 | = MIN (pp_costs[k], (qq_costs[k] + op_cost_add) * scale); | |
47dd2e78 | 1039 | } |
1040 | } | |
1041 | ||
a7dcf969 | 1042 | if (allocno_p) |
1043 | for (i = 0; i < n_ops; i++) | |
1044 | { | |
1045 | ira_allocno_t a; | |
1046 | rtx op = ops[i]; | |
48e1416a | 1047 | |
a7dcf969 | 1048 | if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
1049 | continue; | |
1050 | a = ira_curr_regno_allocno_map [REGNO (op)]; | |
1051 | if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0) | |
1052 | ALLOCNO_BAD_SPILL_P (a) = true; | |
1053 | } | |
68d4bdfb | 1054 | |
47dd2e78 | 1055 | } |
1056 | ||
1057 | \f | |
1058 | ||
1059 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ | |
1060 | static inline bool | |
1061 | ok_for_index_p_nonstrict (rtx reg) | |
1062 | { | |
1063 | unsigned regno = REGNO (reg); | |
1064 | ||
1065 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
1066 | } | |
1067 | ||
1068 | /* A version of regno_ok_for_base_p for use here, when all | |
1069 | pseudo-registers should count as OK. Arguments as for | |
1070 | regno_ok_for_base_p. */ | |
1071 | static inline bool | |
3754d046 | 1072 | ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as, |
47dd2e78 | 1073 | enum rtx_code outer_code, enum rtx_code index_code) |
1074 | { | |
1075 | unsigned regno = REGNO (reg); | |
1076 | ||
1077 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1078 | return true; | |
f8a8fc7b | 1079 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); |
47dd2e78 | 1080 | } |
1081 | ||
1082 | /* Record the pseudo registers we must reload into hard registers in a | |
1083 | subexpression of a memory address, X. | |
1084 | ||
1085 | If CONTEXT is 0, we are looking at the base part of an address, | |
1086 | otherwise we are looking at the index part. | |
1087 | ||
f8a8fc7b | 1088 | MODE and AS are the mode and address space of the memory reference; |
1089 | OUTER_CODE and INDEX_CODE give the context that the rtx appears in. | |
1090 | These four arguments are passed down to base_reg_class. | |
47dd2e78 | 1091 | |
1092 | SCALE is twice the amount to multiply the cost by (it is twice so | |
1093 | we can represent half-cost adjustments). */ | |
1094 | static void | |
3754d046 | 1095 | record_address_regs (machine_mode mode, addr_space_t as, rtx x, |
f8a8fc7b | 1096 | int context, enum rtx_code outer_code, |
1097 | enum rtx_code index_code, int scale) | |
47dd2e78 | 1098 | { |
1099 | enum rtx_code code = GET_CODE (x); | |
1100 | enum reg_class rclass; | |
1101 | ||
1102 | if (context == 1) | |
1103 | rclass = INDEX_REG_CLASS; | |
1104 | else | |
f8a8fc7b | 1105 | rclass = base_reg_class (mode, as, outer_code, index_code); |
47dd2e78 | 1106 | |
1107 | switch (code) | |
1108 | { | |
1109 | case CONST_INT: | |
1110 | case CONST: | |
1111 | case CC0: | |
1112 | case PC: | |
1113 | case SYMBOL_REF: | |
1114 | case LABEL_REF: | |
1115 | return; | |
1116 | ||
1117 | case PLUS: | |
1118 | /* When we have an address that is a sum, we must determine | |
1119 | whether registers are "base" or "index" regs. If there is a | |
1120 | sum of two registers, we must choose one to be the "base". | |
1121 | Luckily, we can use the REG_POINTER to make a good choice | |
1122 | most of the time. We only need to do this on machines that | |
1123 | can have two registers in an address and where the base and | |
1124 | index register classes are different. | |
1125 | ||
1126 | ??? This code used to set REGNO_POINTER_FLAG in some cases, | |
1127 | but that seems bogus since it should only be set when we are | |
1128 | sure the register is being used as a pointer. */ | |
1129 | { | |
1130 | rtx arg0 = XEXP (x, 0); | |
1131 | rtx arg1 = XEXP (x, 1); | |
1132 | enum rtx_code code0 = GET_CODE (arg0); | |
1133 | enum rtx_code code1 = GET_CODE (arg1); | |
1134 | ||
1135 | /* Look inside subregs. */ | |
1136 | if (code0 == SUBREG) | |
1137 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
1138 | if (code1 == SUBREG) | |
1139 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
1140 | ||
b0c5722b | 1141 | /* If index registers do not appear, or coincide with base registers, |
47dd2e78 | 1142 | just record registers in any non-constant operands. We |
1143 | assume here, as well as in the tests below, that all | |
1144 | addresses are in canonical form. */ | |
b0c5722b | 1145 | if (MAX_REGS_PER_ADDRESS == 1 |
1146 | || INDEX_REG_CLASS == base_reg_class (VOIDmode, as, PLUS, SCRATCH)) | |
47dd2e78 | 1147 | { |
f8a8fc7b | 1148 | record_address_regs (mode, as, arg0, context, PLUS, code1, scale); |
47dd2e78 | 1149 | if (! CONSTANT_P (arg1)) |
f8a8fc7b | 1150 | record_address_regs (mode, as, arg1, context, PLUS, code0, scale); |
47dd2e78 | 1151 | } |
1152 | ||
1153 | /* If the second operand is a constant integer, it doesn't | |
1154 | change what class the first operand must be. */ | |
efa08fc2 | 1155 | else if (CONST_SCALAR_INT_P (arg1)) |
f8a8fc7b | 1156 | record_address_regs (mode, as, arg0, context, PLUS, code1, scale); |
47dd2e78 | 1157 | /* If the second operand is a symbolic constant, the first |
1158 | operand must be an index register. */ | |
1159 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
f8a8fc7b | 1160 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale); |
47dd2e78 | 1161 | /* If both operands are registers but one is already a hard |
1162 | register of index or reg-base class, give the other the | |
1163 | class that the hard register is not. */ | |
1164 | else if (code0 == REG && code1 == REG | |
1165 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
f8a8fc7b | 1166 | && (ok_for_base_p_nonstrict (arg0, mode, as, PLUS, REG) |
47dd2e78 | 1167 | || ok_for_index_p_nonstrict (arg0))) |
f8a8fc7b | 1168 | record_address_regs (mode, as, arg1, |
1169 | ok_for_base_p_nonstrict (arg0, mode, as, | |
1170 | PLUS, REG) ? 1 : 0, | |
47dd2e78 | 1171 | PLUS, REG, scale); |
1172 | else if (code0 == REG && code1 == REG | |
1173 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
f8a8fc7b | 1174 | && (ok_for_base_p_nonstrict (arg1, mode, as, PLUS, REG) |
47dd2e78 | 1175 | || ok_for_index_p_nonstrict (arg1))) |
f8a8fc7b | 1176 | record_address_regs (mode, as, arg0, |
1177 | ok_for_base_p_nonstrict (arg1, mode, as, | |
1178 | PLUS, REG) ? 1 : 0, | |
47dd2e78 | 1179 | PLUS, REG, scale); |
1180 | /* If one operand is known to be a pointer, it must be the | |
1181 | base with the other operand the index. Likewise if the | |
1182 | other operand is a MULT. */ | |
1183 | else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT) | |
1184 | { | |
f8a8fc7b | 1185 | record_address_regs (mode, as, arg0, 0, PLUS, code1, scale); |
1186 | record_address_regs (mode, as, arg1, 1, PLUS, code0, scale); | |
47dd2e78 | 1187 | } |
1188 | else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT) | |
1189 | { | |
f8a8fc7b | 1190 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale); |
1191 | record_address_regs (mode, as, arg1, 0, PLUS, code0, scale); | |
47dd2e78 | 1192 | } |
1193 | /* Otherwise, count equal chances that each might be a base or | |
1194 | index register. This case should be rare. */ | |
1195 | else | |
1196 | { | |
f8a8fc7b | 1197 | record_address_regs (mode, as, arg0, 0, PLUS, code1, scale / 2); |
1198 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale / 2); | |
1199 | record_address_regs (mode, as, arg1, 0, PLUS, code0, scale / 2); | |
1200 | record_address_regs (mode, as, arg1, 1, PLUS, code0, scale / 2); | |
47dd2e78 | 1201 | } |
1202 | } | |
1203 | break; | |
1204 | ||
1205 | /* Double the importance of an allocno that is incremented or | |
1206 | decremented, since it would take two extra insns if it ends | |
1207 | up in the wrong place. */ | |
1208 | case POST_MODIFY: | |
1209 | case PRE_MODIFY: | |
f8a8fc7b | 1210 | record_address_regs (mode, as, XEXP (x, 0), 0, code, |
47dd2e78 | 1211 | GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); |
1212 | if (REG_P (XEXP (XEXP (x, 1), 1))) | |
f8a8fc7b | 1213 | record_address_regs (mode, as, XEXP (XEXP (x, 1), 1), 1, code, REG, |
47dd2e78 | 1214 | 2 * scale); |
1215 | break; | |
1216 | ||
1217 | case POST_INC: | |
1218 | case PRE_INC: | |
1219 | case POST_DEC: | |
1220 | case PRE_DEC: | |
1221 | /* Double the importance of an allocno that is incremented or | |
1222 | decremented, since it would take two extra insns if it ends | |
d12ecbda | 1223 | up in the wrong place. */ |
f8a8fc7b | 1224 | record_address_regs (mode, as, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); |
47dd2e78 | 1225 | break; |
1226 | ||
1227 | case REG: | |
1228 | { | |
1229 | struct costs *pp; | |
66d9a7b9 | 1230 | int *pp_costs; |
b9c74b4d | 1231 | enum reg_class i; |
66d9a7b9 | 1232 | int k, regno, add_cost; |
1233 | cost_classes_t cost_classes_ptr; | |
1234 | enum reg_class *cost_classes; | |
1235 | move_table *move_in_cost; | |
47dd2e78 | 1236 | |
1237 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1238 | break; | |
1239 | ||
66d9a7b9 | 1240 | regno = REGNO (x); |
a7dcf969 | 1241 | if (allocno_p) |
66d9a7b9 | 1242 | ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) = true; |
1243 | pp = COSTS (costs, COST_INDEX (regno)); | |
1244 | add_cost = (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; | |
1245 | if (INT_MAX - add_cost < pp->mem_cost) | |
1246 | pp->mem_cost = INT_MAX; | |
1247 | else | |
1248 | pp->mem_cost += add_cost; | |
1249 | cost_classes_ptr = regno_cost_classes[regno]; | |
1250 | cost_classes = cost_classes_ptr->classes; | |
1251 | pp_costs = pp->cost; | |
1252 | ira_init_register_move_cost_if_necessary (Pmode); | |
1253 | move_in_cost = ira_may_move_in_cost[Pmode]; | |
1254 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
47dd2e78 | 1255 | { |
1256 | i = cost_classes[k]; | |
66d9a7b9 | 1257 | add_cost = (move_in_cost[i][rclass] * scale) / 2; |
1258 | if (INT_MAX - add_cost < pp_costs[k]) | |
1259 | pp_costs[k] = INT_MAX; | |
8fc3599d | 1260 | else |
66d9a7b9 | 1261 | pp_costs[k] += add_cost; |
47dd2e78 | 1262 | } |
1263 | } | |
1264 | break; | |
1265 | ||
1266 | default: | |
1267 | { | |
1268 | const char *fmt = GET_RTX_FORMAT (code); | |
1269 | int i; | |
1270 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1271 | if (fmt[i] == 'e') | |
f8a8fc7b | 1272 | record_address_regs (mode, as, XEXP (x, i), context, code, SCRATCH, |
47dd2e78 | 1273 | scale); |
1274 | } | |
1275 | } | |
1276 | } | |
1277 | ||
1278 | \f | |
1279 | ||
1280 | /* Calculate the costs of insn operands. */ | |
1281 | static void | |
56067879 | 1282 | record_operand_costs (rtx_insn *insn, enum reg_class *pref) |
47dd2e78 | 1283 | { |
1284 | const char *constraints[MAX_RECOG_OPERANDS]; | |
3754d046 | 1285 | machine_mode modes[MAX_RECOG_OPERANDS]; |
284f0696 | 1286 | rtx set; |
47dd2e78 | 1287 | int i; |
1288 | ||
8fc3599d | 1289 | if ((set = single_set (insn)) != NULL_RTX |
1290 | /* In rare cases the single set insn might have less 2 operands | |
1291 | as the source can be a fixed special reg. */ | |
1292 | && recog_data.n_operands > 1 | |
1293 | && recog_data.operand[0] == SET_DEST (set) | |
1294 | && recog_data.operand[1] == SET_SRC (set)) | |
1295 | { | |
1296 | int regno, other_regno; | |
1297 | rtx dest = SET_DEST (set); | |
1298 | rtx src = SET_SRC (set); | |
1299 | ||
1300 | if (GET_CODE (dest) == SUBREG | |
1301 | && known_eq (GET_MODE_SIZE (GET_MODE (dest)), | |
1302 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))))) | |
1303 | dest = SUBREG_REG (dest); | |
1304 | if (GET_CODE (src) == SUBREG | |
1305 | && known_eq (GET_MODE_SIZE (GET_MODE (src)), | |
1306 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) | |
1307 | src = SUBREG_REG (src); | |
1308 | if (REG_P (src) && REG_P (dest) | |
1309 | && (((regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
1310 | && (other_regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER) | |
1311 | || ((regno = REGNO (dest)) >= FIRST_PSEUDO_REGISTER | |
1312 | && (other_regno = REGNO (src)) < FIRST_PSEUDO_REGISTER))) | |
1313 | { | |
1314 | machine_mode mode = GET_MODE (SET_SRC (set)); | |
1315 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
1316 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
445aa576 | 1317 | reg_class_t rclass, hard_reg_class, pref_class, bigger_hard_reg_class; |
8fc3599d | 1318 | int cost, k; |
445aa576 | 1319 | move_table *move_costs; |
8fc3599d | 1320 | bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src)); |
1321 | ||
21fcb11b | 1322 | ira_init_register_move_cost_if_necessary (mode); |
445aa576 | 1323 | move_costs = ira_register_move_cost[mode]; |
8fc3599d | 1324 | hard_reg_class = REGNO_REG_CLASS (other_regno); |
445aa576 | 1325 | bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class]; |
91132079 | 1326 | /* Target code may return any cost for mode which does not |
1327 | fit the the hard reg class (e.g. DImode for AREG on | |
1328 | i386). Check this and use a bigger class to get the | |
1329 | right cost. */ | |
31e5af84 | 1330 | if (bigger_hard_reg_class != NO_REGS |
1331 | && ! ira_hard_reg_in_set_p (other_regno, mode, | |
1332 | reg_class_contents[hard_reg_class])) | |
445aa576 | 1333 | hard_reg_class = bigger_hard_reg_class; |
8fc3599d | 1334 | i = regno == (int) REGNO (src) ? 1 : 0; |
1335 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1336 | { | |
1337 | rclass = cost_classes[k]; | |
445aa576 | 1338 | cost = (i == 0 |
1339 | ? move_costs[hard_reg_class][rclass] | |
1340 | : move_costs[rclass][hard_reg_class]); | |
445aa576 | 1341 | |
1342 | op_costs[i]->cost[k] = cost * frequency; | |
8fc3599d | 1343 | /* If we have assigned a class to this allocno in our |
1344 | first pass, add a cost to this alternative | |
1345 | corresponding to what we would add if this allocno | |
1346 | were not in the appropriate class. */ | |
1347 | if (pref) | |
1348 | { | |
1349 | if ((pref_class = pref[COST_INDEX (regno)]) == NO_REGS) | |
1350 | op_costs[i]->cost[k] | |
1351 | += ((i == 0 ? ira_memory_move_cost[mode][rclass][0] : 0) | |
1352 | + (i == 1 ? ira_memory_move_cost[mode][rclass][1] : 0) | |
1353 | * frequency); | |
1354 | else if (ira_reg_class_intersect[pref_class][rclass] | |
1355 | == NO_REGS) | |
1356 | op_costs[i]->cost[k] | |
445aa576 | 1357 | += (move_costs[pref_class][rclass] |
8fc3599d | 1358 | * frequency); |
1359 | } | |
1360 | /* If this insn is a single set copying operand 1 to | |
1361 | operand 0 and one operand is an allocno with the | |
1362 | other a hard reg or an allocno that prefers a hard | |
1363 | register that is in its own register class then we | |
1364 | may want to adjust the cost of that register class to | |
1365 | -1. | |
1366 | ||
1367 | Avoid the adjustment if the source does not die to | |
1368 | avoid stressing of register allocator by preferencing | |
1369 | two colliding registers into single class. */ | |
1370 | if (dead_p | |
1371 | && TEST_HARD_REG_BIT (reg_class_contents[rclass], other_regno) | |
1372 | && (reg_class_size[(int) rclass] | |
1373 | == (ira_reg_class_max_nregs | |
1374 | [(int) rclass][(int) GET_MODE(src)]))) | |
1375 | { | |
1376 | if (reg_class_size[rclass] == 1) | |
1377 | op_costs[i]->cost[k] = -frequency; | |
1378 | else if (in_hard_reg_set_p (reg_class_contents[rclass], | |
1379 | GET_MODE(src), other_regno)) | |
1380 | op_costs[i]->cost[k] = -frequency; | |
1381 | } | |
1382 | } | |
1383 | op_costs[i]->mem_cost | |
1384 | = ira_memory_move_cost[mode][hard_reg_class][i] * frequency; | |
1385 | if (pref && (pref_class = pref[COST_INDEX (regno)]) != NO_REGS) | |
1386 | op_costs[i]->mem_cost | |
1387 | += ira_memory_move_cost[mode][pref_class][i] * frequency; | |
1388 | return; | |
1389 | } | |
1390 | } | |
1391 | ||
47dd2e78 | 1392 | for (i = 0; i < recog_data.n_operands; i++) |
1393 | { | |
1394 | constraints[i] = recog_data.constraints[i]; | |
1395 | modes[i] = recog_data.operand_mode[i]; | |
1396 | } | |
1397 | ||
1398 | /* If we get here, we are set up to record the costs of all the | |
1399 | operands for this insn. Start by initializing the costs. Then | |
1400 | handle any address registers. Finally record the desired classes | |
1401 | for any allocnos, doing it twice if some pair of operands are | |
1402 | commutative. */ | |
1403 | for (i = 0; i < recog_data.n_operands; i++) | |
1404 | { | |
1405 | memcpy (op_costs[i], init_cost, struct_costs_size); | |
1406 | ||
1407 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
1408 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
1409 | ||
1410 | if (MEM_P (recog_data.operand[i])) | |
1411 | record_address_regs (GET_MODE (recog_data.operand[i]), | |
f8a8fc7b | 1412 | MEM_ADDR_SPACE (recog_data.operand[i]), |
47dd2e78 | 1413 | XEXP (recog_data.operand[i], 0), |
1414 | 0, MEM, SCRATCH, frequency * 2); | |
1415 | else if (constraints[i][0] == 'p' | |
79bc09fb | 1416 | || (insn_extra_address_constraint |
1417 | (lookup_constraint (constraints[i])))) | |
f8a8fc7b | 1418 | record_address_regs (VOIDmode, ADDR_SPACE_GENERIC, |
1419 | recog_data.operand[i], 0, ADDRESS, SCRATCH, | |
1420 | frequency * 2); | |
47dd2e78 | 1421 | } |
8fc3599d | 1422 | |
47dd2e78 | 1423 | /* Check for commutative in a separate loop so everything will have |
1424 | been initialized. We must do this even if one operand is a | |
1425 | constant--see addsi3 in m68k.md. */ | |
1426 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1427 | if (constraints[i][0] == '%') | |
1428 | { | |
1429 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1430 | int j; | |
1431 | ||
8fc3599d | 1432 | /* Handle commutative operands by swapping the |
1433 | constraints. We assume the modes are the same. */ | |
47dd2e78 | 1434 | for (j = 0; j < recog_data.n_operands; j++) |
1435 | xconstraints[j] = constraints[j]; | |
1436 | ||
1437 | xconstraints[i] = constraints[i+1]; | |
1438 | xconstraints[i+1] = constraints[i]; | |
1439 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
1440 | recog_data.operand, modes, | |
74b4a59f | 1441 | xconstraints, insn, pref); |
47dd2e78 | 1442 | } |
1443 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
1444 | recog_data.operand, modes, | |
74b4a59f | 1445 | constraints, insn, pref); |
47dd2e78 | 1446 | } |
1447 | ||
1448 | \f | |
1449 | ||
1450 | /* Process one insn INSN. Scan it and record each time it would save | |
1451 | code to put a certain allocnos in a certain class. Return the last | |
1452 | insn processed, so that the scan can be continued from there. */ | |
56067879 | 1453 | static rtx_insn * |
1454 | scan_one_insn (rtx_insn *insn) | |
47dd2e78 | 1455 | { |
1456 | enum rtx_code pat_code; | |
1457 | rtx set, note; | |
1458 | int i, k; | |
be03890a | 1459 | bool counted_mem; |
47dd2e78 | 1460 | |
91f71fa3 | 1461 | if (!NONDEBUG_INSN_P (insn)) |
47dd2e78 | 1462 | return insn; |
1463 | ||
1464 | pat_code = GET_CODE (PATTERN (insn)); | |
b3038ce5 | 1465 | if (pat_code == ASM_INPUT) |
47dd2e78 | 1466 | return insn; |
1467 | ||
b3038ce5 | 1468 | /* If INSN is a USE/CLOBBER of a pseudo in a mode M then go ahead |
1469 | and initialize the register move costs of mode M. | |
1470 | ||
1471 | The pseudo may be related to another pseudo via a copy (implicit or | |
1472 | explicit) and if there are no mode M uses/sets of the original | |
1473 | pseudo, then we may leave the register move costs uninitialized for | |
1474 | mode M. */ | |
1475 | if (pat_code == USE || pat_code == CLOBBER) | |
1476 | { | |
1477 | rtx x = XEXP (PATTERN (insn), 0); | |
1478 | if (GET_CODE (x) == REG | |
b066c8cd | 1479 | && REGNO (x) >= FIRST_PSEUDO_REGISTER |
1480 | && have_regs_of_mode[GET_MODE (x)]) | |
b3038ce5 | 1481 | ira_init_register_move_cost_if_necessary (GET_MODE (x)); |
1482 | return insn; | |
1483 | } | |
1484 | ||
70bdfe23 | 1485 | if (pat_code == CLOBBER_HIGH) |
1486 | { | |
1487 | gcc_assert (REG_P (XEXP (PATTERN (insn), 0)) | |
1488 | && HARD_REGISTER_P (XEXP (PATTERN (insn), 0))); | |
1489 | return insn; | |
1490 | } | |
1491 | ||
be03890a | 1492 | counted_mem = false; |
47dd2e78 | 1493 | set = single_set (insn); |
1494 | extract_insn (insn); | |
1495 | ||
1496 | /* If this insn loads a parameter from its stack slot, then it | |
1497 | represents a savings, rather than a cost, if the parameter is | |
8fc3599d | 1498 | stored in memory. Record this fact. |
be03890a | 1499 | |
1500 | Similarly if we're loading other constants from memory (constant | |
1501 | pool, TOC references, small data areas, etc) and this is the only | |
72e3d363 | 1502 | assignment to the destination pseudo. |
1503 | ||
1504 | Don't do this if SET_SRC (set) isn't a general operand, if it is | |
1505 | a memory requiring special instructions to load it, decreasing | |
1506 | mem_cost might result in it being loaded using the specialized | |
1507 | instruction into a register, then stored into stack and loaded | |
a0ca7f3d | 1508 | again from the stack. See PR52208. |
8fc3599d | 1509 | |
a0ca7f3d | 1510 | Don't do this if SET_SRC (set) has side effect. See PR56124. */ |
47dd2e78 | 1511 | if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set)) |
1512 | && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX | |
a0ca7f3d | 1513 | && ((MEM_P (XEXP (note, 0)) |
1514 | && !side_effects_p (SET_SRC (set))) | |
be03890a | 1515 | || (CONSTANT_P (XEXP (note, 0)) |
4468904c | 1516 | && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)), |
1517 | XEXP (note, 0)) | |
72e3d363 | 1518 | && REG_N_SETS (REGNO (SET_DEST (set))) == 1)) |
d5952b7c | 1519 | && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set))) |
1520 | /* LRA does not use equiv with a symbol for PIC code. */ | |
1521 | && (! ira_use_lra_p || ! pic_offset_table_rtx | |
1522 | || ! contains_symbol_ref_p (XEXP (note, 0)))) | |
47dd2e78 | 1523 | { |
4468904c | 1524 | enum reg_class cl = GENERAL_REGS; |
b7c06809 | 1525 | rtx reg = SET_DEST (set); |
a7dcf969 | 1526 | int num = COST_INDEX (REGNO (reg)); |
b7c06809 | 1527 | |
a7dcf969 | 1528 | COSTS (costs, num)->mem_cost |
b7c06809 | 1529 | -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency; |
f8a8fc7b | 1530 | record_address_regs (GET_MODE (SET_SRC (set)), |
1531 | MEM_ADDR_SPACE (SET_SRC (set)), | |
1532 | XEXP (SET_SRC (set), 0), 0, MEM, SCRATCH, | |
1533 | frequency * 2); | |
be03890a | 1534 | counted_mem = true; |
47dd2e78 | 1535 | } |
1536 | ||
74b4a59f | 1537 | record_operand_costs (insn, pref); |
47dd2e78 | 1538 | |
1539 | /* Now add the cost for each operand to the total costs for its | |
1540 | allocno. */ | |
1541 | for (i = 0; i < recog_data.n_operands; i++) | |
4da42d4f | 1542 | { |
1543 | rtx op = recog_data.operand[i]; | |
1544 | ||
1545 | if (GET_CODE (op) == SUBREG) | |
1546 | op = SUBREG_REG (op); | |
1547 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1548 | { | |
1549 | int regno = REGNO (op); | |
1550 | struct costs *p = COSTS (costs, COST_INDEX (regno)); | |
1551 | struct costs *q = op_costs[i]; | |
1552 | int *p_costs = p->cost, *q_costs = q->cost; | |
1553 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
1554 | int add_cost; | |
1555 | ||
1556 | /* If the already accounted for the memory "cost" above, don't | |
1557 | do so again. */ | |
1558 | if (!counted_mem) | |
1559 | { | |
1560 | add_cost = q->mem_cost; | |
1561 | if (add_cost > 0 && INT_MAX - add_cost < p->mem_cost) | |
1562 | p->mem_cost = INT_MAX; | |
1563 | else | |
1564 | p->mem_cost += add_cost; | |
1565 | } | |
1566 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1567 | { | |
1568 | add_cost = q_costs[k]; | |
1569 | if (add_cost > 0 && INT_MAX - add_cost < p_costs[k]) | |
1570 | p_costs[k] = INT_MAX; | |
1571 | else | |
1572 | p_costs[k] += add_cost; | |
1573 | } | |
1574 | } | |
1575 | } | |
47dd2e78 | 1576 | return insn; |
1577 | } | |
1578 | ||
1579 | \f | |
1580 | ||
1581 | /* Print allocnos costs to file F. */ | |
1582 | static void | |
a7dcf969 | 1583 | print_allocno_costs (FILE *f) |
47dd2e78 | 1584 | { |
1585 | int k; | |
1586 | ira_allocno_t a; | |
1587 | ira_allocno_iterator ai; | |
1588 | ||
a7dcf969 | 1589 | ira_assert (allocno_p); |
47dd2e78 | 1590 | fprintf (f, "\n"); |
1591 | FOR_EACH_ALLOCNO (a, ai) | |
1592 | { | |
1593 | int i, rclass; | |
1594 | basic_block bb; | |
1595 | int regno = ALLOCNO_REGNO (a); | |
66d9a7b9 | 1596 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; |
1597 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
47dd2e78 | 1598 | |
1599 | i = ALLOCNO_NUM (a); | |
1600 | fprintf (f, " a%d(r%d,", i, regno); | |
1601 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
1602 | fprintf (f, "b%d", bb->index); | |
1603 | else | |
9f8ac546 | 1604 | fprintf (f, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
47dd2e78 | 1605 | fprintf (f, ") costs:"); |
66d9a7b9 | 1606 | for (k = 0; k < cost_classes_ptr->num; k++) |
47dd2e78 | 1607 | { |
1608 | rclass = cost_classes[k]; | |
511b66fb | 1609 | fprintf (f, " %s:%d", reg_class_names[rclass], |
1610 | COSTS (costs, i)->cost[k]); | |
1611 | if (flag_ira_region == IRA_REGION_ALL | |
1612 | || flag_ira_region == IRA_REGION_MIXED) | |
1613 | fprintf (f, ",%d", COSTS (total_allocno_costs, i)->cost[k]); | |
47dd2e78 | 1614 | } |
66d9a7b9 | 1615 | fprintf (f, " MEM:%i", COSTS (costs, i)->mem_cost); |
1616 | if (flag_ira_region == IRA_REGION_ALL | |
1617 | || flag_ira_region == IRA_REGION_MIXED) | |
1618 | fprintf (f, ",%d", COSTS (total_allocno_costs, i)->mem_cost); | |
1619 | fprintf (f, "\n"); | |
a7dcf969 | 1620 | } |
1621 | } | |
1622 | ||
1623 | /* Print pseudo costs to file F. */ | |
1624 | static void | |
1625 | print_pseudo_costs (FILE *f) | |
1626 | { | |
1627 | int regno, k; | |
1628 | int rclass; | |
66d9a7b9 | 1629 | cost_classes_t cost_classes_ptr; |
1630 | enum reg_class *cost_classes; | |
a7dcf969 | 1631 | |
1632 | ira_assert (! allocno_p); | |
1633 | fprintf (f, "\n"); | |
1634 | for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--) | |
1635 | { | |
66d9a7b9 | 1636 | if (REG_N_REFS (regno) <= 0) |
a7dcf969 | 1637 | continue; |
66d9a7b9 | 1638 | cost_classes_ptr = regno_cost_classes[regno]; |
1639 | cost_classes = cost_classes_ptr->classes; | |
a7dcf969 | 1640 | fprintf (f, " r%d costs:", regno); |
66d9a7b9 | 1641 | for (k = 0; k < cost_classes_ptr->num; k++) |
a7dcf969 | 1642 | { |
1643 | rclass = cost_classes[k]; | |
511b66fb | 1644 | fprintf (f, " %s:%d", reg_class_names[rclass], |
1645 | COSTS (costs, regno)->cost[k]); | |
a7dcf969 | 1646 | } |
1647 | fprintf (f, " MEM:%i\n", COSTS (costs, regno)->mem_cost); | |
47dd2e78 | 1648 | } |
1649 | } | |
1650 | ||
1651 | /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno | |
1652 | costs. */ | |
1653 | static void | |
a7dcf969 | 1654 | process_bb_for_costs (basic_block bb) |
47dd2e78 | 1655 | { |
56067879 | 1656 | rtx_insn *insn; |
47dd2e78 | 1657 | |
47dd2e78 | 1658 | frequency = REG_FREQ_FROM_BB (bb); |
1659 | if (frequency == 0) | |
1660 | frequency = 1; | |
1661 | FOR_BB_INSNS (bb, insn) | |
1662 | insn = scan_one_insn (insn); | |
1663 | } | |
1664 | ||
a7dcf969 | 1665 | /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
1666 | costs. */ | |
47dd2e78 | 1667 | static void |
a7dcf969 | 1668 | process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node) |
47dd2e78 | 1669 | { |
a7dcf969 | 1670 | basic_block bb; |
1671 | ||
1672 | bb = loop_tree_node->bb; | |
1673 | if (bb != NULL) | |
1674 | process_bb_for_costs (bb); | |
1675 | } | |
1676 | ||
1677 | /* Find costs of register classes and memory for allocnos or pseudos | |
66d9a7b9 | 1678 | and their best costs. Set up preferred, alternative and allocno |
a7dcf969 | 1679 | classes for pseudos. */ |
1680 | static void | |
1681 | find_costs_and_classes (FILE *dump_file) | |
1682 | { | |
66d9a7b9 | 1683 | int i, k, start, max_cost_classes_num; |
47dd2e78 | 1684 | int pass; |
1685 | basic_block bb; | |
20c3c7fc | 1686 | enum reg_class *regno_best_class, new_class; |
47dd2e78 | 1687 | |
1688 | init_recog (); | |
66d9a7b9 | 1689 | regno_best_class |
1690 | = (enum reg_class *) ira_allocate (max_reg_num () | |
1691 | * sizeof (enum reg_class)); | |
1692 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1693 | regno_best_class[i] = NO_REGS; | |
1694 | if (!resize_reg_info () && allocno_p | |
1695 | && pseudo_classes_defined_p && flag_expensive_optimizations) | |
a7dcf969 | 1696 | { |
1697 | ira_allocno_t a; | |
1698 | ira_allocno_iterator ai; | |
48e1416a | 1699 | |
a7dcf969 | 1700 | pref = pref_buffer; |
66d9a7b9 | 1701 | max_cost_classes_num = 1; |
a7dcf969 | 1702 | FOR_EACH_ALLOCNO (a, ai) |
66d9a7b9 | 1703 | { |
1704 | pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a)); | |
1705 | setup_regno_cost_classes_by_aclass | |
1706 | (ALLOCNO_REGNO (a), pref[ALLOCNO_NUM (a)]); | |
1707 | max_cost_classes_num | |
1708 | = MAX (max_cost_classes_num, | |
1709 | regno_cost_classes[ALLOCNO_REGNO (a)]->num); | |
1710 | } | |
1711 | start = 1; | |
1712 | } | |
1713 | else | |
1714 | { | |
1715 | pref = NULL; | |
1716 | max_cost_classes_num = ira_important_classes_num; | |
1717 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1718 | if (regno_reg_rtx[i] != NULL_RTX) | |
1719 | setup_regno_cost_classes_by_mode (i, PSEUDO_REGNO_MODE (i)); | |
1720 | else | |
1721 | setup_regno_cost_classes_by_aclass (i, ALL_REGS); | |
1722 | start = 0; | |
a7dcf969 | 1723 | } |
1724 | if (allocno_p) | |
1725 | /* Clear the flag for the next compiled function. */ | |
1726 | pseudo_classes_defined_p = false; | |
47dd2e78 | 1727 | /* Normally we scan the insns once and determine the best class to |
1728 | use for each allocno. However, if -fexpensive-optimizations are | |
1729 | on, we do so twice, the second time using the tentative best | |
1730 | classes to guide the selection. */ | |
a7dcf969 | 1731 | for (pass = start; pass <= flag_expensive_optimizations; pass++) |
47dd2e78 | 1732 | { |
a7dcf969 | 1733 | if ((!allocno_p || internal_flag_ira_verbose > 0) && dump_file) |
1734 | fprintf (dump_file, | |
1735 | "\nPass %i for finding pseudo/allocno costs\n\n", pass); | |
66d9a7b9 | 1736 | |
1737 | if (pass != start) | |
47dd2e78 | 1738 | { |
66d9a7b9 | 1739 | max_cost_classes_num = 1; |
1740 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1741 | { | |
1742 | setup_regno_cost_classes_by_aclass (i, regno_best_class[i]); | |
1743 | max_cost_classes_num | |
1744 | = MAX (max_cost_classes_num, regno_cost_classes[i]->num); | |
1745 | } | |
47dd2e78 | 1746 | } |
66d9a7b9 | 1747 | |
47dd2e78 | 1748 | struct_costs_size |
66d9a7b9 | 1749 | = sizeof (struct costs) + sizeof (int) * (max_cost_classes_num - 1); |
47dd2e78 | 1750 | /* Zero out our accumulation of the cost of each class for each |
1751 | allocno. */ | |
a7dcf969 | 1752 | memset (costs, 0, cost_elements_num * struct_costs_size); |
47dd2e78 | 1753 | |
a7dcf969 | 1754 | if (allocno_p) |
1755 | { | |
1756 | /* Scan the instructions and record each time it would save code | |
1757 | to put a certain allocno in a certain class. */ | |
1758 | ira_traverse_loop_tree (true, ira_loop_tree_root, | |
1759 | process_bb_node_for_costs, NULL); | |
1760 | ||
1761 | memcpy (total_allocno_costs, costs, | |
1762 | max_struct_costs_size * ira_allocnos_num); | |
1763 | } | |
1764 | else | |
1765 | { | |
1766 | basic_block bb; | |
1767 | ||
fc00614f | 1768 | FOR_EACH_BB_FN (bb, cfun) |
a7dcf969 | 1769 | process_bb_for_costs (bb); |
1770 | } | |
47dd2e78 | 1771 | |
47dd2e78 | 1772 | if (pass == 0) |
a7dcf969 | 1773 | pref = pref_buffer; |
47dd2e78 | 1774 | |
1775 | /* Now for each allocno look at how desirable each class is and | |
1776 | find which class is preferred. */ | |
1777 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1778 | { | |
1779 | ira_allocno_t a, parent_a; | |
66d9a7b9 | 1780 | int rclass, a_num, parent_a_num, add_cost; |
47dd2e78 | 1781 | ira_loop_tree_node_t parent; |
4352d38e | 1782 | int best_cost, allocno_cost; |
14792f4e | 1783 | enum reg_class best, alt_class; |
66d9a7b9 | 1784 | cost_classes_t cost_classes_ptr = regno_cost_classes[i]; |
60f78312 | 1785 | enum reg_class *cost_classes; |
66d9a7b9 | 1786 | int *i_costs = temp_costs->cost; |
1787 | int i_mem_cost; | |
4164ad58 | 1788 | int equiv_savings = regno_equiv_gains[i]; |
47dd2e78 | 1789 | |
a7dcf969 | 1790 | if (! allocno_p) |
47dd2e78 | 1791 | { |
a7dcf969 | 1792 | if (regno_reg_rtx[i] == NULL_RTX) |
1793 | continue; | |
a7dcf969 | 1794 | memcpy (temp_costs, COSTS (costs, i), struct_costs_size); |
66d9a7b9 | 1795 | i_mem_cost = temp_costs->mem_cost; |
60f78312 | 1796 | cost_classes = cost_classes_ptr->classes; |
a7dcf969 | 1797 | } |
1798 | else | |
1799 | { | |
1800 | if (ira_regno_allocno_map[i] == NULL) | |
1801 | continue; | |
1802 | memset (temp_costs, 0, struct_costs_size); | |
66d9a7b9 | 1803 | i_mem_cost = 0; |
60f78312 | 1804 | cost_classes = cost_classes_ptr->classes; |
a7dcf969 | 1805 | /* Find cost of all allocnos with the same regno. */ |
1806 | for (a = ira_regno_allocno_map[i]; | |
1807 | a != NULL; | |
1808 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
47dd2e78 | 1809 | { |
66d9a7b9 | 1810 | int *a_costs, *p_costs; |
8fc3599d | 1811 | |
a7dcf969 | 1812 | a_num = ALLOCNO_NUM (a); |
1813 | if ((flag_ira_region == IRA_REGION_ALL | |
1814 | || flag_ira_region == IRA_REGION_MIXED) | |
1815 | && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL | |
1816 | && (parent_a = parent->regno_allocno_map[i]) != NULL | |
1817 | /* There are no caps yet. */ | |
1818 | && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE | |
1819 | (a)->border_allocnos, | |
1820 | ALLOCNO_NUM (a))) | |
1821 | { | |
1822 | /* Propagate costs to upper levels in the region | |
1823 | tree. */ | |
1824 | parent_a_num = ALLOCNO_NUM (parent_a); | |
66d9a7b9 | 1825 | a_costs = COSTS (total_allocno_costs, a_num)->cost; |
1826 | p_costs = COSTS (total_allocno_costs, parent_a_num)->cost; | |
1827 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1828 | { | |
1829 | add_cost = a_costs[k]; | |
1830 | if (add_cost > 0 && INT_MAX - add_cost < p_costs[k]) | |
1831 | p_costs[k] = INT_MAX; | |
1832 | else | |
1833 | p_costs[k] += add_cost; | |
1834 | } | |
1835 | add_cost = COSTS (total_allocno_costs, a_num)->mem_cost; | |
1836 | if (add_cost > 0 | |
1837 | && (INT_MAX - add_cost | |
1838 | < COSTS (total_allocno_costs, | |
1839 | parent_a_num)->mem_cost)) | |
1840 | COSTS (total_allocno_costs, parent_a_num)->mem_cost | |
1841 | = INT_MAX; | |
1842 | else | |
1843 | COSTS (total_allocno_costs, parent_a_num)->mem_cost | |
1844 | += add_cost; | |
1845 | ||
fe9cf48d | 1846 | if (i >= first_moveable_pseudo && i < last_moveable_pseudo) |
1847 | COSTS (total_allocno_costs, parent_a_num)->mem_cost = 0; | |
a7dcf969 | 1848 | } |
66d9a7b9 | 1849 | a_costs = COSTS (costs, a_num)->cost; |
1850 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1851 | { | |
1852 | add_cost = a_costs[k]; | |
1853 | if (add_cost > 0 && INT_MAX - add_cost < i_costs[k]) | |
1854 | i_costs[k] = INT_MAX; | |
1855 | else | |
1856 | i_costs[k] += add_cost; | |
1857 | } | |
1858 | add_cost = COSTS (costs, a_num)->mem_cost; | |
13cf233a | 1859 | if (add_cost > 0 && INT_MAX - add_cost < i_mem_cost) |
66d9a7b9 | 1860 | i_mem_cost = INT_MAX; |
1861 | else | |
1862 | i_mem_cost += add_cost; | |
a7dcf969 | 1863 | } |
47dd2e78 | 1864 | } |
fe9cf48d | 1865 | if (i >= first_moveable_pseudo && i < last_moveable_pseudo) |
1866 | i_mem_cost = 0; | |
1867 | else if (equiv_savings < 0) | |
ca8cd143 | 1868 | i_mem_cost = -equiv_savings; |
4164ad58 | 1869 | else if (equiv_savings > 0) |
1870 | { | |
ca8cd143 | 1871 | i_mem_cost = 0; |
66d9a7b9 | 1872 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) |
1873 | i_costs[k] += equiv_savings; | |
4164ad58 | 1874 | } |
1875 | ||
47dd2e78 | 1876 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
1877 | best = ALL_REGS; | |
1878 | alt_class = NO_REGS; | |
1879 | /* Find best common class for all allocnos with the same | |
1880 | regno. */ | |
66d9a7b9 | 1881 | for (k = 0; k < cost_classes_ptr->num; k++) |
47dd2e78 | 1882 | { |
1883 | rclass = cost_classes[k]; | |
66d9a7b9 | 1884 | if (i_costs[k] < best_cost) |
47dd2e78 | 1885 | { |
66d9a7b9 | 1886 | best_cost = i_costs[k]; |
47dd2e78 | 1887 | best = (enum reg_class) rclass; |
1888 | } | |
66d9a7b9 | 1889 | else if (i_costs[k] == best_cost) |
1890 | best = ira_reg_class_subunion[best][rclass]; | |
47dd2e78 | 1891 | if (pass == flag_expensive_optimizations |
99d809ea | 1892 | /* We still prefer registers to memory even at this |
1893 | stage if their costs are the same. We will make | |
1894 | a final decision during assigning hard registers | |
1895 | when we have all info including more accurate | |
1896 | costs which might be affected by assigning hard | |
1897 | registers to other pseudos because the pseudos | |
1898 | involved in moves can be coalesced. */ | |
1899 | && i_costs[k] <= i_mem_cost | |
47dd2e78 | 1900 | && (reg_class_size[reg_class_subunion[alt_class][rclass]] |
1901 | > reg_class_size[alt_class])) | |
1902 | alt_class = reg_class_subunion[alt_class][rclass]; | |
1903 | } | |
66d9a7b9 | 1904 | alt_class = ira_allocno_class_translate[alt_class]; |
bf9df576 | 1905 | if (best_cost > i_mem_cost |
1906 | && ! non_spilled_static_chain_regno_p (i)) | |
66d9a7b9 | 1907 | regno_aclass[i] = NO_REGS; |
f9edeb70 | 1908 | else if (!optimize && !targetm.class_likely_spilled_p (best)) |
1909 | /* Registers in the alternative class are likely to need | |
1910 | longer or slower sequences than registers in the best class. | |
1911 | When optimizing we make some effort to use the best class | |
1912 | over the alternative class where possible, but at -O0 we | |
1913 | effectively give the alternative class equal weight. | |
1914 | We then run the risk of using slower alternative registers | |
1915 | when plenty of registers from the best class are still free. | |
1916 | This is especially true because live ranges tend to be very | |
1917 | short in -O0 code and so register pressure tends to be low. | |
1918 | ||
1919 | Avoid that by ignoring the alternative class if the best | |
db591c64 | 1920 | class has plenty of registers. |
1921 | ||
1922 | The union class arrays give important classes and only | |
1923 | part of it are allocno classes. So translate them into | |
1924 | allocno classes. */ | |
1925 | regno_aclass[i] = ira_allocno_class_translate[best]; | |
47dd2e78 | 1926 | else |
66d9a7b9 | 1927 | { |
1928 | /* Make the common class the biggest class of best and | |
db591c64 | 1929 | alt_class. Translate the common class into an |
1930 | allocno class too. */ | |
1931 | regno_aclass[i] = (ira_allocno_class_translate | |
1932 | [ira_reg_class_superunion[best][alt_class]]); | |
66d9a7b9 | 1933 | ira_assert (regno_aclass[i] != NO_REGS |
1934 | && ira_reg_allocno_class_p[regno_aclass[i]]); | |
1935 | } | |
20c3c7fc | 1936 | if ((new_class |
1937 | = (reg_class) (targetm.ira_change_pseudo_allocno_class | |
ef704984 | 1938 | (i, regno_aclass[i], best))) != regno_aclass[i]) |
20c3c7fc | 1939 | { |
1940 | regno_aclass[i] = new_class; | |
1941 | if (hard_reg_set_subset_p (reg_class_contents[new_class], | |
1942 | reg_class_contents[best])) | |
1943 | best = new_class; | |
1944 | if (hard_reg_set_subset_p (reg_class_contents[new_class], | |
1945 | reg_class_contents[alt_class])) | |
1946 | alt_class = new_class; | |
1947 | } | |
a7dcf969 | 1948 | if (pass == flag_expensive_optimizations) |
1949 | { | |
bf9df576 | 1950 | if (best_cost > i_mem_cost |
1951 | /* Do not assign NO_REGS to static chain pointer | |
1952 | pseudo when non-local goto is used. */ | |
1953 | && ! non_spilled_static_chain_regno_p (i)) | |
a7dcf969 | 1954 | best = alt_class = NO_REGS; |
1955 | else if (best == alt_class) | |
1956 | alt_class = NO_REGS; | |
66d9a7b9 | 1957 | setup_reg_classes (i, best, alt_class, regno_aclass[i]); |
a7dcf969 | 1958 | if ((!allocno_p || internal_flag_ira_verbose > 2) |
1959 | && dump_file != NULL) | |
1960 | fprintf (dump_file, | |
66d9a7b9 | 1961 | " r%d: preferred %s, alternative %s, allocno %s\n", |
a7dcf969 | 1962 | i, reg_class_names[best], reg_class_names[alt_class], |
66d9a7b9 | 1963 | reg_class_names[regno_aclass[i]]); |
a7dcf969 | 1964 | } |
66d9a7b9 | 1965 | regno_best_class[i] = best; |
a7dcf969 | 1966 | if (! allocno_p) |
1967 | { | |
bf9df576 | 1968 | pref[i] = (best_cost > i_mem_cost |
1969 | && ! non_spilled_static_chain_regno_p (i) | |
1970 | ? NO_REGS : best); | |
a7dcf969 | 1971 | continue; |
1972 | } | |
47dd2e78 | 1973 | for (a = ira_regno_allocno_map[i]; |
1974 | a != NULL; | |
1975 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
1976 | { | |
284f0696 | 1977 | enum reg_class aclass = regno_aclass[i]; |
1978 | int a_num = ALLOCNO_NUM (a); | |
1979 | int *total_a_costs = COSTS (total_allocno_costs, a_num)->cost; | |
1980 | int *a_costs = COSTS (costs, a_num)->cost; | |
8fc3599d | 1981 | |
284f0696 | 1982 | if (aclass == NO_REGS) |
47dd2e78 | 1983 | best = NO_REGS; |
1984 | else | |
48e1416a | 1985 | { |
47dd2e78 | 1986 | /* Finding best class which is subset of the common |
1987 | class. */ | |
1988 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
4352d38e | 1989 | allocno_cost = best_cost; |
47dd2e78 | 1990 | best = ALL_REGS; |
66d9a7b9 | 1991 | for (k = 0; k < cost_classes_ptr->num; k++) |
47dd2e78 | 1992 | { |
1993 | rclass = cost_classes[k]; | |
284f0696 | 1994 | if (! ira_class_subset_p[rclass][aclass]) |
47dd2e78 | 1995 | continue; |
511b66fb | 1996 | if (total_a_costs[k] < best_cost) |
47dd2e78 | 1997 | { |
66d9a7b9 | 1998 | best_cost = total_a_costs[k]; |
1999 | allocno_cost = a_costs[k]; | |
47dd2e78 | 2000 | best = (enum reg_class) rclass; |
2001 | } | |
66d9a7b9 | 2002 | else if (total_a_costs[k] == best_cost) |
4352d38e | 2003 | { |
66d9a7b9 | 2004 | best = ira_reg_class_subunion[best][rclass]; |
2005 | allocno_cost = MAX (allocno_cost, a_costs[k]); | |
4352d38e | 2006 | } |
47dd2e78 | 2007 | } |
66d9a7b9 | 2008 | ALLOCNO_CLASS_COST (a) = allocno_cost; |
47dd2e78 | 2009 | } |
a7dcf969 | 2010 | if (internal_flag_ira_verbose > 2 && dump_file != NULL |
2011 | && (pass == 0 || pref[a_num] != best)) | |
47dd2e78 | 2012 | { |
a7dcf969 | 2013 | fprintf (dump_file, " a%d (r%d,", a_num, i); |
47dd2e78 | 2014 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) |
a7dcf969 | 2015 | fprintf (dump_file, "b%d", bb->index); |
47dd2e78 | 2016 | else |
a7dcf969 | 2017 | fprintf (dump_file, "l%d", |
9f8ac546 | 2018 | ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
66d9a7b9 | 2019 | fprintf (dump_file, ") best %s, allocno %s\n", |
47dd2e78 | 2020 | reg_class_names[best], |
284f0696 | 2021 | reg_class_names[aclass]); |
47dd2e78 | 2022 | } |
a7dcf969 | 2023 | pref[a_num] = best; |
284f0696 | 2024 | if (pass == flag_expensive_optimizations && best != aclass |
2025 | && ira_class_hard_regs_num[best] > 0 | |
2026 | && (ira_reg_class_max_nregs[best][ALLOCNO_MODE (a)] | |
2027 | >= ira_class_hard_regs_num[best])) | |
2028 | { | |
2029 | int ind = cost_classes_ptr->index[aclass]; | |
2030 | ||
2031 | ira_assert (ind >= 0); | |
afcc0d26 | 2032 | ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a)); |
284f0696 | 2033 | ira_add_allocno_pref (a, ira_class_hard_regs[best][0], |
2034 | (a_costs[ind] - ALLOCNO_CLASS_COST (a)) | |
2035 | / (ira_register_move_cost | |
2036 | [ALLOCNO_MODE (a)][best][aclass])); | |
2037 | for (k = 0; k < cost_classes_ptr->num; k++) | |
2038 | if (ira_class_subset_p[cost_classes[k]][best]) | |
2039 | a_costs[k] = a_costs[ind]; | |
2040 | } | |
47dd2e78 | 2041 | } |
2042 | } | |
8fc3599d | 2043 | |
a7dcf969 | 2044 | if (internal_flag_ira_verbose > 4 && dump_file) |
47dd2e78 | 2045 | { |
a7dcf969 | 2046 | if (allocno_p) |
2047 | print_allocno_costs (dump_file); | |
2048 | else | |
2049 | print_pseudo_costs (dump_file); | |
2050 | fprintf (dump_file,"\n"); | |
47dd2e78 | 2051 | } |
2052 | } | |
66d9a7b9 | 2053 | ira_free (regno_best_class); |
47dd2e78 | 2054 | } |
2055 | ||
2056 | \f | |
2057 | ||
2058 | /* Process moves involving hard regs to modify allocno hard register | |
66d9a7b9 | 2059 | costs. We can do this only after determining allocno class. If a |
2628e0e8 | 2060 | hard register forms a register class, then moves with the hard |
47dd2e78 | 2061 | register are already taken into account in class costs for the |
2062 | allocno. */ | |
2063 | static void | |
2064 | process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node) | |
2065 | { | |
284f0696 | 2066 | int i, freq, src_regno, dst_regno, hard_regno, a_regno; |
47dd2e78 | 2067 | bool to_p; |
284f0696 | 2068 | ira_allocno_t a, curr_a; |
2069 | ira_loop_tree_node_t curr_loop_tree_node; | |
2070 | enum reg_class rclass; | |
47dd2e78 | 2071 | basic_block bb; |
56067879 | 2072 | rtx_insn *insn; |
2073 | rtx set, src, dst; | |
47dd2e78 | 2074 | |
2075 | bb = loop_tree_node->bb; | |
2076 | if (bb == NULL) | |
2077 | return; | |
2078 | freq = REG_FREQ_FROM_BB (bb); | |
2079 | if (freq == 0) | |
2080 | freq = 1; | |
2081 | FOR_BB_INSNS (bb, insn) | |
2082 | { | |
9845d120 | 2083 | if (!NONDEBUG_INSN_P (insn)) |
47dd2e78 | 2084 | continue; |
2085 | set = single_set (insn); | |
2086 | if (set == NULL_RTX) | |
2087 | continue; | |
2088 | dst = SET_DEST (set); | |
2089 | src = SET_SRC (set); | |
2090 | if (! REG_P (dst) || ! REG_P (src)) | |
2091 | continue; | |
2092 | dst_regno = REGNO (dst); | |
2093 | src_regno = REGNO (src); | |
2094 | if (dst_regno >= FIRST_PSEUDO_REGISTER | |
2095 | && src_regno < FIRST_PSEUDO_REGISTER) | |
2096 | { | |
2097 | hard_regno = src_regno; | |
47dd2e78 | 2098 | a = ira_curr_regno_allocno_map[dst_regno]; |
284f0696 | 2099 | to_p = true; |
47dd2e78 | 2100 | } |
2101 | else if (src_regno >= FIRST_PSEUDO_REGISTER | |
2102 | && dst_regno < FIRST_PSEUDO_REGISTER) | |
2103 | { | |
2104 | hard_regno = dst_regno; | |
47dd2e78 | 2105 | a = ira_curr_regno_allocno_map[src_regno]; |
284f0696 | 2106 | to_p = false; |
47dd2e78 | 2107 | } |
2108 | else | |
2109 | continue; | |
66d9a7b9 | 2110 | rclass = ALLOCNO_CLASS (a); |
47dd2e78 | 2111 | if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno)) |
2112 | continue; | |
2113 | i = ira_class_hard_reg_index[rclass][hard_regno]; | |
2114 | if (i < 0) | |
2115 | continue; | |
284f0696 | 2116 | a_regno = ALLOCNO_REGNO (a); |
2117 | for (curr_loop_tree_node = ALLOCNO_LOOP_TREE_NODE (a); | |
2118 | curr_loop_tree_node != NULL; | |
2119 | curr_loop_tree_node = curr_loop_tree_node->parent) | |
2120 | if ((curr_a = curr_loop_tree_node->regno_allocno_map[a_regno]) != NULL) | |
2121 | ira_add_allocno_pref (curr_a, hard_regno, freq); | |
2122 | { | |
2123 | int cost; | |
2124 | enum reg_class hard_reg_class; | |
3754d046 | 2125 | machine_mode mode; |
8fc3599d | 2126 | |
284f0696 | 2127 | mode = ALLOCNO_MODE (a); |
2128 | hard_reg_class = REGNO_REG_CLASS (hard_regno); | |
2129 | ira_init_register_move_cost_if_necessary (mode); | |
2130 | cost = (to_p ? ira_register_move_cost[mode][hard_reg_class][rclass] | |
2131 | : ira_register_move_cost[mode][rclass][hard_reg_class]) * freq; | |
2132 | ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass, | |
2133 | ALLOCNO_CLASS_COST (a)); | |
2134 | ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a), | |
2135 | rclass, 0); | |
2136 | ALLOCNO_HARD_REG_COSTS (a)[i] -= cost; | |
2137 | ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost; | |
2138 | ALLOCNO_CLASS_COST (a) = MIN (ALLOCNO_CLASS_COST (a), | |
2139 | ALLOCNO_HARD_REG_COSTS (a)[i]); | |
2140 | } | |
47dd2e78 | 2141 | } |
2142 | } | |
2143 | ||
2144 | /* After we find hard register and memory costs for allocnos, define | |
66d9a7b9 | 2145 | its class and modify hard register cost because insns moving |
47dd2e78 | 2146 | allocno to/from hard registers. */ |
2147 | static void | |
66d9a7b9 | 2148 | setup_allocno_class_and_costs (void) |
47dd2e78 | 2149 | { |
66d9a7b9 | 2150 | int i, j, n, regno, hard_regno, num; |
47dd2e78 | 2151 | int *reg_costs; |
66d9a7b9 | 2152 | enum reg_class aclass, rclass; |
47dd2e78 | 2153 | ira_allocno_t a; |
2154 | ira_allocno_iterator ai; | |
66d9a7b9 | 2155 | cost_classes_t cost_classes_ptr; |
47dd2e78 | 2156 | |
a7dcf969 | 2157 | ira_assert (allocno_p); |
47dd2e78 | 2158 | FOR_EACH_ALLOCNO (a, ai) |
2159 | { | |
2160 | i = ALLOCNO_NUM (a); | |
66d9a7b9 | 2161 | regno = ALLOCNO_REGNO (a); |
2162 | aclass = regno_aclass[regno]; | |
2163 | cost_classes_ptr = regno_cost_classes[regno]; | |
2164 | ira_assert (pref[i] == NO_REGS || aclass != NO_REGS); | |
a7dcf969 | 2165 | ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost; |
66d9a7b9 | 2166 | ira_set_allocno_class (a, aclass); |
2167 | if (aclass == NO_REGS) | |
47dd2e78 | 2168 | continue; |
66d9a7b9 | 2169 | if (optimize && ALLOCNO_CLASS (a) != pref[i]) |
47dd2e78 | 2170 | { |
66d9a7b9 | 2171 | n = ira_class_hard_regs_num[aclass]; |
47dd2e78 | 2172 | ALLOCNO_HARD_REG_COSTS (a) |
66d9a7b9 | 2173 | = reg_costs = ira_allocate_cost_vector (aclass); |
47dd2e78 | 2174 | for (j = n - 1; j >= 0; j--) |
2175 | { | |
66d9a7b9 | 2176 | hard_regno = ira_class_hard_regs[aclass][j]; |
2177 | if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], hard_regno)) | |
2178 | reg_costs[j] = ALLOCNO_CLASS_COST (a); | |
4352d38e | 2179 | else |
1e204c74 | 2180 | { |
66d9a7b9 | 2181 | rclass = REGNO_REG_CLASS (hard_regno); |
2182 | num = cost_classes_ptr->index[rclass]; | |
4352d38e | 2183 | if (num < 0) |
2184 | { | |
66d9a7b9 | 2185 | num = cost_classes_ptr->hard_regno_index[hard_regno]; |
2186 | ira_assert (num >= 0); | |
4352d38e | 2187 | } |
a7dcf969 | 2188 | reg_costs[j] = COSTS (costs, i)->cost[num]; |
1e204c74 | 2189 | } |
47dd2e78 | 2190 | } |
2191 | } | |
2192 | } | |
2193 | if (optimize) | |
2194 | ira_traverse_loop_tree (true, ira_loop_tree_root, | |
2195 | process_bb_node_for_hard_reg_moves, NULL); | |
2196 | } | |
2197 | ||
2198 | \f | |
2199 | ||
2200 | /* Function called once during compiler work. */ | |
2201 | void | |
2202 | ira_init_costs_once (void) | |
2203 | { | |
2204 | int i; | |
2205 | ||
2206 | init_cost = NULL; | |
2207 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
2208 | { | |
2209 | op_costs[i] = NULL; | |
2210 | this_op_costs[i] = NULL; | |
2211 | } | |
2212 | temp_costs = NULL; | |
47dd2e78 | 2213 | } |
2214 | ||
2215 | /* Free allocated temporary cost vectors. */ | |
0c61fbed | 2216 | void |
2217 | target_ira_int::free_ira_costs () | |
47dd2e78 | 2218 | { |
2219 | int i; | |
2220 | ||
0c61fbed | 2221 | free (x_init_cost); |
2222 | x_init_cost = NULL; | |
47dd2e78 | 2223 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) |
2224 | { | |
0c61fbed | 2225 | free (x_op_costs[i]); |
2226 | free (x_this_op_costs[i]); | |
2227 | x_op_costs[i] = x_this_op_costs[i] = NULL; | |
47dd2e78 | 2228 | } |
0c61fbed | 2229 | free (x_temp_costs); |
2230 | x_temp_costs = NULL; | |
47dd2e78 | 2231 | } |
2232 | ||
2233 | /* This is called each time register related information is | |
2234 | changed. */ | |
2235 | void | |
2236 | ira_init_costs (void) | |
2237 | { | |
2238 | int i; | |
2239 | ||
0c61fbed | 2240 | this_target_ira_int->free_ira_costs (); |
47dd2e78 | 2241 | max_struct_costs_size |
2242 | = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1); | |
66d9a7b9 | 2243 | /* Don't use ira_allocate because vectors live through several IRA |
2244 | calls. */ | |
47dd2e78 | 2245 | init_cost = (struct costs *) xmalloc (max_struct_costs_size); |
2246 | init_cost->mem_cost = 1000000; | |
2247 | for (i = 0; i < ira_important_classes_num; i++) | |
2248 | init_cost->cost[i] = 1000000; | |
2249 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
2250 | { | |
2251 | op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
2252 | this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
2253 | } | |
2254 | temp_costs = (struct costs *) xmalloc (max_struct_costs_size); | |
47dd2e78 | 2255 | } |
2256 | ||
47dd2e78 | 2257 | \f |
2258 | ||
a7dcf969 | 2259 | /* Common initialization function for ira_costs and |
2260 | ira_set_pseudo_classes. */ | |
2261 | static void | |
2262 | init_costs (void) | |
2263 | { | |
e8eed2f8 | 2264 | init_subregs_of_mode (); |
a7dcf969 | 2265 | costs = (struct costs *) ira_allocate (max_struct_costs_size |
2266 | * cost_elements_num); | |
66d9a7b9 | 2267 | pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
2268 | * cost_elements_num); | |
2269 | regno_aclass = (enum reg_class *) ira_allocate (sizeof (enum reg_class) | |
2270 | * max_reg_num ()); | |
4164ad58 | 2271 | regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); |
2272 | memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); | |
a7dcf969 | 2273 | } |
2274 | ||
2275 | /* Common finalization function for ira_costs and | |
2276 | ira_set_pseudo_classes. */ | |
2277 | static void | |
2278 | finish_costs (void) | |
2279 | { | |
63dae96b | 2280 | finish_subregs_of_mode (); |
4164ad58 | 2281 | ira_free (regno_equiv_gains); |
66d9a7b9 | 2282 | ira_free (regno_aclass); |
a7dcf969 | 2283 | ira_free (pref_buffer); |
2284 | ira_free (costs); | |
2285 | } | |
2286 | ||
66d9a7b9 | 2287 | /* Entry function which defines register class, memory and hard |
2288 | register costs for each allocno. */ | |
47dd2e78 | 2289 | void |
2290 | ira_costs (void) | |
2291 | { | |
a7dcf969 | 2292 | allocno_p = true; |
2293 | cost_elements_num = ira_allocnos_num; | |
2294 | init_costs (); | |
2295 | total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size | |
2296 | * ira_allocnos_num); | |
66d9a7b9 | 2297 | initiate_regno_cost_classes (); |
4164ad58 | 2298 | calculate_elim_costs_all_insns (); |
a7dcf969 | 2299 | find_costs_and_classes (ira_dump_file); |
66d9a7b9 | 2300 | setup_allocno_class_and_costs (); |
2301 | finish_regno_cost_classes (); | |
a7dcf969 | 2302 | finish_costs (); |
2303 | ira_free (total_allocno_costs); | |
2304 | } | |
2305 | ||
1ec78e16 | 2306 | /* Entry function which defines classes for pseudos. |
2307 | Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */ | |
a7dcf969 | 2308 | void |
1ec78e16 | 2309 | ira_set_pseudo_classes (bool define_pseudo_classes, FILE *dump_file) |
a7dcf969 | 2310 | { |
2311 | allocno_p = false; | |
2312 | internal_flag_ira_verbose = flag_ira_verbose; | |
2313 | cost_elements_num = max_reg_num (); | |
2314 | init_costs (); | |
66d9a7b9 | 2315 | initiate_regno_cost_classes (); |
a7dcf969 | 2316 | find_costs_and_classes (dump_file); |
66d9a7b9 | 2317 | finish_regno_cost_classes (); |
1ec78e16 | 2318 | if (define_pseudo_classes) |
2319 | pseudo_classes_defined_p = true; | |
2320 | ||
a7dcf969 | 2321 | finish_costs (); |
47dd2e78 | 2322 | } |
2323 | ||
2324 | \f | |
2325 | ||
2326 | /* Change hard register costs for allocnos which lives through | |
2327 | function calls. This is called only when we found all intersected | |
2328 | calls during building allocno live ranges. */ | |
2329 | void | |
66d9a7b9 | 2330 | ira_tune_allocno_costs (void) |
47dd2e78 | 2331 | { |
2332 | int j, n, regno; | |
2333 | int cost, min_cost, *reg_costs; | |
66d9a7b9 | 2334 | enum reg_class aclass, rclass; |
3754d046 | 2335 | machine_mode mode; |
47dd2e78 | 2336 | ira_allocno_t a; |
2337 | ira_allocno_iterator ai; | |
66d9a7b9 | 2338 | ira_allocno_object_iterator oi; |
2339 | ira_object_t obj; | |
2340 | bool skip_p; | |
754158d9 | 2341 | HARD_REG_SET *crossed_calls_clobber_regs; |
47dd2e78 | 2342 | |
2343 | FOR_EACH_ALLOCNO (a, ai) | |
2344 | { | |
66d9a7b9 | 2345 | aclass = ALLOCNO_CLASS (a); |
2346 | if (aclass == NO_REGS) | |
47dd2e78 | 2347 | continue; |
2348 | mode = ALLOCNO_MODE (a); | |
66d9a7b9 | 2349 | n = ira_class_hard_regs_num[aclass]; |
47dd2e78 | 2350 | min_cost = INT_MAX; |
c8010b80 | 2351 | if (ALLOCNO_CALLS_CROSSED_NUM (a) |
2352 | != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
47dd2e78 | 2353 | { |
2354 | ira_allocate_and_set_costs | |
66d9a7b9 | 2355 | (&ALLOCNO_HARD_REG_COSTS (a), aclass, |
2356 | ALLOCNO_CLASS_COST (a)); | |
47dd2e78 | 2357 | reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
2358 | for (j = n - 1; j >= 0; j--) | |
2359 | { | |
66d9a7b9 | 2360 | regno = ira_class_hard_regs[aclass][j]; |
2361 | skip_p = false; | |
2362 | FOR_EACH_ALLOCNO_OBJECT (a, obj, oi) | |
2363 | { | |
4682ca16 | 2364 | if (ira_hard_reg_set_intersection_p (regno, mode, |
2365 | OBJECT_CONFLICT_HARD_REGS | |
2366 | (obj))) | |
66d9a7b9 | 2367 | { |
2368 | skip_p = true; | |
2369 | break; | |
2370 | } | |
2371 | } | |
2372 | if (skip_p) | |
2373 | continue; | |
47dd2e78 | 2374 | rclass = REGNO_REG_CLASS (regno); |
2375 | cost = 0; | |
754158d9 | 2376 | crossed_calls_clobber_regs |
2377 | = &(ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)); | |
2378 | if (ira_hard_reg_set_intersection_p (regno, mode, | |
3ed2e52f | 2379 | *crossed_calls_clobber_regs) |
2380 | && (ira_hard_reg_set_intersection_p (regno, mode, | |
754158d9 | 2381 | call_used_reg_set) |
5da94e60 | 2382 | || targetm.hard_regno_call_part_clobbered (regno, |
2383 | mode))) | |
3ed2e52f | 2384 | cost += (ALLOCNO_CALL_FREQ (a) |
2385 | * (ira_memory_move_cost[mode][rclass][0] | |
2386 | + ira_memory_move_cost[mode][rclass][1])); | |
47dd2e78 | 2387 | #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER |
3ed2e52f | 2388 | cost += ((ira_memory_move_cost[mode][rclass][0] |
2389 | + ira_memory_move_cost[mode][rclass][1]) | |
2390 | * ALLOCNO_FREQ (a) | |
2391 | * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2); | |
47dd2e78 | 2392 | #endif |
66d9a7b9 | 2393 | if (INT_MAX - cost < reg_costs[j]) |
2394 | reg_costs[j] = INT_MAX; | |
2395 | else | |
2396 | reg_costs[j] += cost; | |
47dd2e78 | 2397 | if (min_cost > reg_costs[j]) |
2398 | min_cost = reg_costs[j]; | |
2399 | } | |
2400 | } | |
2401 | if (min_cost != INT_MAX) | |
66d9a7b9 | 2402 | ALLOCNO_CLASS_COST (a) = min_cost; |
f7ace4bc | 2403 | |
58611ff1 | 2404 | /* Some targets allow pseudos to be allocated to unaligned sequences |
2405 | of hard registers. However, selecting an unaligned sequence can | |
2406 | unnecessarily restrict later allocations. So increase the cost of | |
2407 | unaligned hard regs to encourage the use of aligned hard regs. */ | |
f7ace4bc | 2408 | { |
66d9a7b9 | 2409 | const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)]; |
f7ace4bc | 2410 | |
58611ff1 | 2411 | if (nregs > 1) |
f7ace4bc | 2412 | { |
2413 | ira_allocate_and_set_costs | |
66d9a7b9 | 2414 | (&ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a)); |
f7ace4bc | 2415 | reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
2416 | for (j = n - 1; j >= 0; j--) | |
2417 | { | |
66d9a7b9 | 2418 | regno = ira_non_ordered_class_hard_regs[aclass][j]; |
58611ff1 | 2419 | if ((regno % nregs) != 0) |
f7ace4bc | 2420 | { |
66d9a7b9 | 2421 | int index = ira_class_hard_reg_index[aclass][regno]; |
1feb164a | 2422 | ira_assert (index != -1); |
f7ace4bc | 2423 | reg_costs[index] += ALLOCNO_FREQ (a); |
2424 | } | |
2425 | } | |
2426 | } | |
2427 | } | |
47dd2e78 | 2428 | } |
2429 | } | |
4164ad58 | 2430 | |
2431 | /* Add COST to the estimated gain for eliminating REGNO with its | |
2432 | equivalence. If COST is zero, record that no such elimination is | |
2433 | possible. */ | |
2434 | ||
2435 | void | |
2436 | ira_adjust_equiv_reg_cost (unsigned regno, int cost) | |
2437 | { | |
2438 | if (cost == 0) | |
2439 | regno_equiv_gains[regno] = 0; | |
2440 | else | |
2441 | regno_equiv_gains[regno] += cost; | |
2442 | } | |
6015ec52 | 2443 | |
2444 | void | |
2445 | ira_costs_c_finalize (void) | |
2446 | { | |
2447 | this_target_ira_int->free_ira_costs (); | |
2448 | } |