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ce18efcb | 1 | /* IRA hard register and memory cost calculation for allocnos or pseudos. |
a945c346 | 2 | Copyright (C) 2006-2024 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
c7131fb2 | 24 | #include "backend.h" |
957060b5 | 25 | #include "target.h" |
058e97ec | 26 | #include "rtl.h" |
c7131fb2 | 27 | #include "tree.h" |
957060b5 | 28 | #include "predict.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
957060b5 | 30 | #include "tm_p.h" |
957060b5 AM |
31 | #include "insn-config.h" |
32 | #include "regs.h" | |
f55cdce3 | 33 | #include "regset.h" |
957060b5 AM |
34 | #include "ira.h" |
35 | #include "ira-int.h" | |
058e97ec | 36 | #include "addresses.h" |
8ff49c29 | 37 | #include "reload.h" |
2639f9d2 | 38 | #include "print-rtl.h" |
058e97ec | 39 | |
ce18efcb VM |
40 | /* The flags is set up every time when we calculate pseudo register |
41 | classes through function ira_set_pseudo_classes. */ | |
42 | static bool pseudo_classes_defined_p = false; | |
43 | ||
44 | /* TRUE if we work with allocnos. Otherwise we work with pseudos. */ | |
45 | static bool allocno_p; | |
46 | ||
9aaa7e47 | 47 | /* Number of elements in array `costs'. */ |
ce18efcb | 48 | static int cost_elements_num; |
058e97ec | 49 | |
058e97ec VM |
50 | /* The `costs' struct records the cost of using hard registers of each |
51 | class considered for the calculation and of using memory for each | |
ce18efcb | 52 | allocno or pseudo. */ |
058e97ec VM |
53 | struct costs |
54 | { | |
55 | int mem_cost; | |
56 | /* Costs for register classes start here. We process only some | |
1756cb66 | 57 | allocno classes. */ |
058e97ec VM |
58 | int cost[1]; |
59 | }; | |
60 | ||
aa1c5d72 RS |
61 | #define max_struct_costs_size \ |
62 | (this_target_ira_int->x_max_struct_costs_size) | |
63 | #define init_cost \ | |
64 | (this_target_ira_int->x_init_cost) | |
65 | #define temp_costs \ | |
66 | (this_target_ira_int->x_temp_costs) | |
67 | #define op_costs \ | |
68 | (this_target_ira_int->x_op_costs) | |
69 | #define this_op_costs \ | |
70 | (this_target_ira_int->x_this_op_costs) | |
058e97ec | 71 | |
ce18efcb VM |
72 | /* Costs of each class for each allocno or pseudo. */ |
73 | static struct costs *costs; | |
74 | ||
75 | /* Accumulated costs of each class for each allocno. */ | |
76 | static struct costs *total_allocno_costs; | |
058e97ec | 77 | |
058e97ec | 78 | /* It is the current size of struct costs. */ |
ff304c01 | 79 | static size_t struct_costs_size; |
058e97ec | 80 | |
ce18efcb VM |
81 | /* Return pointer to structure containing costs of allocno or pseudo |
82 | with given NUM in array ARR. */ | |
83 | #define COSTS(arr, num) \ | |
058e97ec VM |
84 | ((struct costs *) ((char *) (arr) + (num) * struct_costs_size)) |
85 | ||
ce18efcb | 86 | /* Return index in COSTS when processing reg with REGNO. */ |
1756cb66 VM |
87 | #define COST_INDEX(regno) (allocno_p \ |
88 | ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \ | |
ce18efcb | 89 | : (int) regno) |
058e97ec | 90 | |
ce18efcb VM |
91 | /* Record register class preferences of each allocno or pseudo. Null |
92 | value means no preferences. It happens on the 1st iteration of the | |
93 | cost calculation. */ | |
94 | static enum reg_class *pref; | |
058e97ec | 95 | |
ce18efcb VM |
96 | /* Allocated buffers for pref. */ |
97 | static enum reg_class *pref_buffer; | |
98 | ||
1756cb66 VM |
99 | /* Record allocno class of each allocno with the same regno. */ |
100 | static enum reg_class *regno_aclass; | |
7db7ed3c | 101 | |
8ff49c29 BS |
102 | /* Record cost gains for not allocating a register with an invariant |
103 | equivalence. */ | |
104 | static int *regno_equiv_gains; | |
105 | ||
058e97ec VM |
106 | /* Execution frequency of the current insn. */ |
107 | static int frequency; | |
108 | ||
109 | \f | |
110 | ||
1756cb66 VM |
111 | /* Info about reg classes whose costs are calculated for a pseudo. */ |
112 | struct cost_classes | |
113 | { | |
114 | /* Number of the cost classes in the subsequent array. */ | |
115 | int num; | |
116 | /* Container of the cost classes. */ | |
117 | enum reg_class classes[N_REG_CLASSES]; | |
118 | /* Map reg class -> index of the reg class in the previous array. | |
df3e3493 | 119 | -1 if it is not a cost class. */ |
1756cb66 VM |
120 | int index[N_REG_CLASSES]; |
121 | /* Map hard regno index of first class in array CLASSES containing | |
122 | the hard regno, -1 otherwise. */ | |
123 | int hard_regno_index[FIRST_PSEUDO_REGISTER]; | |
124 | }; | |
125 | ||
126 | /* Types of pointers to the structure above. */ | |
127 | typedef struct cost_classes *cost_classes_t; | |
128 | typedef const struct cost_classes *const_cost_classes_t; | |
129 | ||
130 | /* Info about cost classes for each pseudo. */ | |
131 | static cost_classes_t *regno_cost_classes; | |
132 | ||
4a8fb1a1 LC |
133 | /* Helper for cost_classes hashing. */ |
134 | ||
7edd9b15 | 135 | struct cost_classes_hasher : pointer_hash <cost_classes> |
1756cb66 | 136 | { |
67f58944 TS |
137 | static inline hashval_t hash (const cost_classes *); |
138 | static inline bool equal (const cost_classes *, const cost_classes *); | |
139 | static inline void remove (cost_classes *); | |
4a8fb1a1 | 140 | }; |
1756cb66 | 141 | |
4a8fb1a1 LC |
142 | /* Returns hash value for cost classes info HV. */ |
143 | inline hashval_t | |
67f58944 | 144 | cost_classes_hasher::hash (const cost_classes *hv) |
4a8fb1a1 | 145 | { |
1756cb66 VM |
146 | return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0); |
147 | } | |
148 | ||
4a8fb1a1 LC |
149 | /* Compares cost classes info HV1 and HV2. */ |
150 | inline bool | |
67f58944 | 151 | cost_classes_hasher::equal (const cost_classes *hv1, const cost_classes *hv2) |
1756cb66 | 152 | { |
c99ebd4d FY |
153 | return (hv1->num == hv2->num |
154 | && memcmp (hv1->classes, hv2->classes, | |
155 | sizeof (enum reg_class) * hv1->num) == 0); | |
1756cb66 VM |
156 | } |
157 | ||
158 | /* Delete cost classes info V from the hash table. */ | |
4a8fb1a1 | 159 | inline void |
67f58944 | 160 | cost_classes_hasher::remove (cost_classes *v) |
1756cb66 VM |
161 | { |
162 | ira_free (v); | |
163 | } | |
164 | ||
165 | /* Hash table of unique cost classes. */ | |
c203e8a7 | 166 | static hash_table<cost_classes_hasher> *cost_classes_htab; |
1756cb66 VM |
167 | |
168 | /* Map allocno class -> cost classes for pseudo of given allocno | |
169 | class. */ | |
170 | static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES]; | |
171 | ||
172 | /* Map mode -> cost classes for pseudo of give mode. */ | |
173 | static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE]; | |
174 | ||
cbfb1548 RS |
175 | /* Cost classes that include all classes in ira_important_classes. */ |
176 | static cost_classes all_cost_classes; | |
177 | ||
178 | /* Use the array of classes in CLASSES_PTR to fill out the rest of | |
179 | the structure. */ | |
180 | static void | |
181 | complete_cost_classes (cost_classes_t classes_ptr) | |
182 | { | |
183 | for (int i = 0; i < N_REG_CLASSES; i++) | |
184 | classes_ptr->index[i] = -1; | |
185 | for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
186 | classes_ptr->hard_regno_index[i] = -1; | |
187 | for (int i = 0; i < classes_ptr->num; i++) | |
188 | { | |
189 | enum reg_class cl = classes_ptr->classes[i]; | |
190 | classes_ptr->index[cl] = i; | |
191 | for (int j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--) | |
192 | { | |
193 | unsigned int hard_regno = ira_class_hard_regs[cl][j]; | |
194 | if (classes_ptr->hard_regno_index[hard_regno] < 0) | |
195 | classes_ptr->hard_regno_index[hard_regno] = i; | |
196 | } | |
197 | } | |
198 | } | |
199 | ||
1756cb66 VM |
200 | /* Initialize info about the cost classes for each pseudo. */ |
201 | static void | |
202 | initiate_regno_cost_classes (void) | |
203 | { | |
204 | int size = sizeof (cost_classes_t) * max_reg_num (); | |
205 | ||
206 | regno_cost_classes = (cost_classes_t *) ira_allocate (size); | |
207 | memset (regno_cost_classes, 0, size); | |
208 | memset (cost_classes_aclass_cache, 0, | |
209 | sizeof (cost_classes_t) * N_REG_CLASSES); | |
210 | memset (cost_classes_mode_cache, 0, | |
211 | sizeof (cost_classes_t) * MAX_MACHINE_MODE); | |
c203e8a7 | 212 | cost_classes_htab = new hash_table<cost_classes_hasher> (200); |
cbfb1548 RS |
213 | all_cost_classes.num = ira_important_classes_num; |
214 | for (int i = 0; i < ira_important_classes_num; i++) | |
215 | all_cost_classes.classes[i] = ira_important_classes[i]; | |
216 | complete_cost_classes (&all_cost_classes); | |
1756cb66 VM |
217 | } |
218 | ||
219 | /* Create new cost classes from cost classes FROM and set up members | |
220 | index and hard_regno_index. Return the new classes. The function | |
221 | implements some common code of two functions | |
222 | setup_regno_cost_classes_by_aclass and | |
223 | setup_regno_cost_classes_by_mode. */ | |
224 | static cost_classes_t | |
225 | setup_cost_classes (cost_classes_t from) | |
226 | { | |
227 | cost_classes_t classes_ptr; | |
1756cb66 VM |
228 | |
229 | classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes)); | |
230 | classes_ptr->num = from->num; | |
cbfb1548 RS |
231 | for (int i = 0; i < from->num; i++) |
232 | classes_ptr->classes[i] = from->classes[i]; | |
233 | complete_cost_classes (classes_ptr); | |
234 | return classes_ptr; | |
235 | } | |
236 | ||
237 | /* Return a version of FULL that only considers registers in REGS that are | |
238 | valid for mode MODE. Both FULL and the returned class are globally | |
239 | allocated. */ | |
240 | static cost_classes_t | |
ef4bddc2 | 241 | restrict_cost_classes (cost_classes_t full, machine_mode mode, |
504279ae | 242 | const_hard_reg_set regs) |
cbfb1548 RS |
243 | { |
244 | static struct cost_classes narrow; | |
245 | int map[N_REG_CLASSES]; | |
246 | narrow.num = 0; | |
247 | for (int i = 0; i < full->num; i++) | |
1756cb66 | 248 | { |
cbfb1548 RS |
249 | /* Assume that we'll drop the class. */ |
250 | map[i] = -1; | |
251 | ||
252 | /* Ignore classes that are too small for the mode. */ | |
253 | enum reg_class cl = full->classes[i]; | |
254 | if (!contains_reg_of_mode[cl][mode]) | |
255 | continue; | |
256 | ||
257 | /* Calculate the set of registers in CL that belong to REGS and | |
258 | are valid for MODE. */ | |
dc333d8f | 259 | HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs; |
d15e5131 RS |
260 | valid_for_cl &= ~(ira_prohibited_class_mode_regs[cl][mode] |
261 | | ira_no_alloc_regs); | |
cbfb1548 RS |
262 | if (hard_reg_set_empty_p (valid_for_cl)) |
263 | continue; | |
264 | ||
265 | /* Don't use this class if the set of valid registers is a subset | |
266 | of an existing class. For example, suppose we have two classes | |
267 | GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose | |
268 | that the mode changes allowed by FR_REGS are not as general as | |
269 | the mode changes allowed by GR_REGS. | |
270 | ||
271 | In this situation, the mode changes for GR_AND_FR_REGS could | |
272 | either be seen as the union or the intersection of the mode | |
273 | changes allowed by the two subclasses. The justification for | |
274 | the union-based definition would be that, if you want a mode | |
275 | change that's only allowed by GR_REGS, you can pick a register | |
276 | from the GR_REGS subclass. The justification for the | |
277 | intersection-based definition would be that every register | |
278 | from the class would allow the mode change. | |
279 | ||
280 | However, if we have a register that needs to be in GR_REGS, | |
281 | using GR_AND_FR_REGS with the intersection-based definition | |
282 | would be too pessimistic, since it would bring in restrictions | |
283 | that only apply to FR_REGS. Conversely, if we have a register | |
284 | that needs to be in FR_REGS, using GR_AND_FR_REGS with the | |
285 | union-based definition would lose the extra restrictions | |
286 | placed on FR_REGS. GR_AND_FR_REGS is therefore only useful | |
287 | for cases where GR_REGS and FP_REGS are both valid. */ | |
288 | int pos; | |
289 | for (pos = 0; pos < narrow.num; ++pos) | |
1756cb66 | 290 | { |
cbfb1548 RS |
291 | enum reg_class cl2 = narrow.classes[pos]; |
292 | if (hard_reg_set_subset_p (valid_for_cl, reg_class_contents[cl2])) | |
293 | break; | |
294 | } | |
295 | map[i] = pos; | |
296 | if (pos == narrow.num) | |
297 | { | |
298 | /* If several classes are equivalent, prefer to use the one | |
299 | that was chosen as the allocno class. */ | |
300 | enum reg_class cl2 = ira_allocno_class_translate[cl]; | |
301 | if (ira_class_hard_regs_num[cl] == ira_class_hard_regs_num[cl2]) | |
302 | cl = cl2; | |
303 | narrow.classes[narrow.num++] = cl; | |
1756cb66 VM |
304 | } |
305 | } | |
cbfb1548 RS |
306 | if (narrow.num == full->num) |
307 | return full; | |
308 | ||
309 | cost_classes **slot = cost_classes_htab->find_slot (&narrow, INSERT); | |
310 | if (*slot == NULL) | |
311 | { | |
312 | cost_classes_t classes = setup_cost_classes (&narrow); | |
313 | /* Map equivalent classes to the representative that we chose above. */ | |
314 | for (int i = 0; i < ira_important_classes_num; i++) | |
315 | { | |
316 | enum reg_class cl = ira_important_classes[i]; | |
317 | int index = full->index[cl]; | |
318 | if (index >= 0) | |
319 | classes->index[cl] = map[index]; | |
320 | } | |
321 | *slot = classes; | |
322 | } | |
323 | return *slot; | |
1756cb66 VM |
324 | } |
325 | ||
326 | /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS. | |
327 | This function is used when we know an initial approximation of | |
328 | allocno class of the pseudo already, e.g. on the second iteration | |
329 | of class cost calculation or after class cost calculation in | |
330 | register-pressure sensitive insn scheduling or register-pressure | |
331 | sensitive loop-invariant motion. */ | |
332 | static void | |
333 | setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass) | |
334 | { | |
335 | static struct cost_classes classes; | |
336 | cost_classes_t classes_ptr; | |
337 | enum reg_class cl; | |
338 | int i; | |
4a8fb1a1 | 339 | cost_classes **slot; |
1756cb66 | 340 | HARD_REG_SET temp, temp2; |
6277a710 | 341 | bool exclude_p; |
1756cb66 VM |
342 | |
343 | if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL) | |
344 | { | |
d15e5131 | 345 | temp = reg_class_contents[aclass] & ~ira_no_alloc_regs; |
6277a710 | 346 | /* We exclude classes from consideration which are subsets of |
165f639c VM |
347 | ACLASS only if ACLASS is an uniform class. */ |
348 | exclude_p = ira_uniform_class_p[aclass]; | |
1756cb66 VM |
349 | classes.num = 0; |
350 | for (i = 0; i < ira_important_classes_num; i++) | |
351 | { | |
352 | cl = ira_important_classes[i]; | |
6277a710 VM |
353 | if (exclude_p) |
354 | { | |
165f639c | 355 | /* Exclude non-uniform classes which are subsets of |
6277a710 | 356 | ACLASS. */ |
d15e5131 | 357 | temp2 = reg_class_contents[cl] & ~ira_no_alloc_regs; |
165f639c | 358 | if (hard_reg_set_subset_p (temp2, temp) && cl != aclass) |
6277a710 VM |
359 | continue; |
360 | } | |
1756cb66 VM |
361 | classes.classes[classes.num++] = cl; |
362 | } | |
c203e8a7 | 363 | slot = cost_classes_htab->find_slot (&classes, INSERT); |
1756cb66 VM |
364 | if (*slot == NULL) |
365 | { | |
366 | classes_ptr = setup_cost_classes (&classes); | |
367 | *slot = classes_ptr; | |
368 | } | |
369 | classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot; | |
370 | } | |
cbfb1548 | 371 | if (regno_reg_rtx[regno] != NULL_RTX) |
dab67d2c RS |
372 | { |
373 | /* Restrict the classes to those that are valid for REGNO's mode | |
374 | (which might for example exclude singleton classes if the mode | |
375 | requires two registers). Also restrict the classes to those that | |
376 | are valid for subregs of REGNO. */ | |
377 | const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno); | |
378 | if (!valid_regs) | |
379 | valid_regs = ®_class_contents[ALL_REGS]; | |
380 | classes_ptr = restrict_cost_classes (classes_ptr, | |
381 | PSEUDO_REGNO_MODE (regno), | |
382 | *valid_regs); | |
383 | } | |
1756cb66 VM |
384 | regno_cost_classes[regno] = classes_ptr; |
385 | } | |
386 | ||
387 | /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can | |
388 | decrease number of cost classes for the pseudo, if hard registers | |
67914693 SL |
389 | of some important classes cannot hold a value of MODE. So the |
390 | pseudo cannot get hard register of some important classes and cost | |
df3e3493 | 391 | calculation for such important classes is only wasting CPU |
1756cb66 VM |
392 | time. */ |
393 | static void | |
ef4bddc2 | 394 | setup_regno_cost_classes_by_mode (int regno, machine_mode mode) |
1756cb66 | 395 | { |
dab67d2c RS |
396 | if (const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno)) |
397 | regno_cost_classes[regno] = restrict_cost_classes (&all_cost_classes, | |
398 | mode, *valid_regs); | |
399 | else | |
400 | { | |
401 | if (cost_classes_mode_cache[mode] == NULL) | |
402 | cost_classes_mode_cache[mode] | |
403 | = restrict_cost_classes (&all_cost_classes, mode, | |
404 | reg_class_contents[ALL_REGS]); | |
405 | regno_cost_classes[regno] = cost_classes_mode_cache[mode]; | |
406 | } | |
1756cb66 VM |
407 | } |
408 | ||
df3e3493 | 409 | /* Finalize info about the cost classes for each pseudo. */ |
1756cb66 VM |
410 | static void |
411 | finish_regno_cost_classes (void) | |
412 | { | |
413 | ira_free (regno_cost_classes); | |
c203e8a7 TS |
414 | delete cost_classes_htab; |
415 | cost_classes_htab = NULL; | |
1756cb66 VM |
416 | } |
417 | ||
418 | \f | |
419 | ||
058e97ec VM |
420 | /* Compute the cost of loading X into (if TO_P is TRUE) or from (if |
421 | TO_P is FALSE) a register of class RCLASS in mode MODE. X must not | |
422 | be a pseudo register. */ | |
423 | static int | |
ef4bddc2 | 424 | copy_cost (rtx x, machine_mode mode, reg_class_t rclass, bool to_p, |
058e97ec VM |
425 | secondary_reload_info *prev_sri) |
426 | { | |
427 | secondary_reload_info sri; | |
fba42e24 | 428 | reg_class_t secondary_class = NO_REGS; |
058e97ec VM |
429 | |
430 | /* If X is a SCRATCH, there is actually nothing to move since we are | |
431 | assuming optimal allocation. */ | |
432 | if (GET_CODE (x) == SCRATCH) | |
433 | return 0; | |
434 | ||
435 | /* Get the class we will actually use for a reload. */ | |
fba42e24 | 436 | rclass = targetm.preferred_reload_class (x, rclass); |
058e97ec VM |
437 | |
438 | /* If we need a secondary reload for an intermediate, the cost is | |
439 | that to load the input into the intermediate register, then to | |
440 | copy it. */ | |
441 | sri.prev_sri = prev_sri; | |
442 | sri.extra_cost = 0; | |
a2faef8e NC |
443 | /* PR 68770: Secondary reload might examine the t_icode field. */ |
444 | sri.t_icode = CODE_FOR_nothing; | |
445 | ||
fba42e24 | 446 | secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri); |
058e97ec | 447 | |
058e97ec | 448 | if (secondary_class != NO_REGS) |
20377b47 | 449 | { |
bac1c6a4 RS |
450 | ira_init_register_move_cost_if_necessary (mode); |
451 | return (ira_register_move_cost[mode][(int) secondary_class][(int) rclass] | |
fba42e24 | 452 | + sri.extra_cost |
20377b47 JH |
453 | + copy_cost (x, mode, secondary_class, to_p, &sri)); |
454 | } | |
058e97ec VM |
455 | |
456 | /* For memory, use the memory move cost, for (hard) registers, use | |
457 | the cost to move between the register classes, and use 2 for | |
458 | everything else (constants). */ | |
459 | if (MEM_P (x) || rclass == NO_REGS) | |
fba42e24 AS |
460 | return sri.extra_cost |
461 | + ira_memory_move_cost[mode][(int) rclass][to_p != 0]; | |
058e97ec | 462 | else if (REG_P (x)) |
20377b47 | 463 | { |
bac1c6a4 RS |
464 | reg_class_t x_class = REGNO_REG_CLASS (REGNO (x)); |
465 | ||
466 | ira_init_register_move_cost_if_necessary (mode); | |
fba42e24 | 467 | return (sri.extra_cost |
bac1c6a4 | 468 | + ira_register_move_cost[mode][(int) x_class][(int) rclass]); |
20377b47 | 469 | } |
058e97ec VM |
470 | else |
471 | /* If this is a constant, we may eventually want to call rtx_cost | |
472 | here. */ | |
473 | return sri.extra_cost + COSTS_N_INSNS (1); | |
474 | } | |
475 | ||
476 | \f | |
477 | ||
478 | /* Record the cost of using memory or hard registers of various | |
479 | classes for the operands in INSN. | |
480 | ||
481 | N_ALTS is the number of alternatives. | |
482 | N_OPS is the number of operands. | |
483 | OPS is an array of the operands. | |
484 | MODES are the modes of the operands, in case any are VOIDmode. | |
485 | CONSTRAINTS are the constraints to use for the operands. This array | |
486 | is modified by this procedure. | |
487 | ||
488 | This procedure works alternative by alternative. For each | |
489 | alternative we assume that we will be able to allocate all allocnos | |
490 | to their ideal register class and calculate the cost of using that | |
491 | alternative. Then we compute, for each operand that is a | |
492 | pseudo-register, the cost of having the allocno allocated to each | |
493 | register class and using it in that alternative. To this cost is | |
494 | added the cost of the alternative. | |
495 | ||
496 | The cost of each class for this insn is its lowest cost among all | |
497 | the alternatives. */ | |
498 | static void | |
499 | record_reg_classes (int n_alts, int n_ops, rtx *ops, | |
ef4bddc2 | 500 | machine_mode *modes, const char **constraints, |
070a1983 | 501 | rtx_insn *insn, enum reg_class *pref) |
058e97ec VM |
502 | { |
503 | int alt; | |
504 | int i, j, k; | |
927425df | 505 | int insn_allows_mem[MAX_RECOG_OPERANDS]; |
0a1eb350 VM |
506 | move_table *move_in_cost, *move_out_cost; |
507 | short (*mem_cost)[2]; | |
2639f9d2 VM |
508 | const char *p; |
509 | ||
510 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) | |
511 | { | |
512 | fprintf (ira_dump_file, " Processing insn %u", INSN_UID (insn)); | |
513 | if (INSN_CODE (insn) >= 0 | |
514 | && (p = get_insn_name (INSN_CODE (insn))) != NULL) | |
515 | fprintf (ira_dump_file, " {%s}", p); | |
516 | fprintf (ira_dump_file, " (freq=%d)\n", | |
517 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn))); | |
518 | dump_insn_slim (ira_dump_file, insn); | |
519 | } | |
927425df VM |
520 | |
521 | for (i = 0; i < n_ops; i++) | |
522 | insn_allows_mem[i] = 0; | |
058e97ec VM |
523 | |
524 | /* Process each alternative, each time minimizing an operand's cost | |
525 | with the cost for each operand in that alternative. */ | |
9840b2fa | 526 | alternative_mask preferred = get_preferred_alternatives (insn); |
058e97ec VM |
527 | for (alt = 0; alt < n_alts; alt++) |
528 | { | |
529 | enum reg_class classes[MAX_RECOG_OPERANDS]; | |
530 | int allows_mem[MAX_RECOG_OPERANDS]; | |
bbbbb16a | 531 | enum reg_class rclass; |
058e97ec VM |
532 | int alt_fail = 0; |
533 | int alt_cost = 0, op_cost_add; | |
534 | ||
9840b2fa | 535 | if (!TEST_BIT (preferred, alt)) |
979740a0 BS |
536 | { |
537 | for (i = 0; i < recog_data.n_operands; i++) | |
538 | constraints[i] = skip_alternative (constraints[i]); | |
539 | ||
540 | continue; | |
541 | } | |
542 | ||
2639f9d2 VM |
543 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) |
544 | { | |
545 | fprintf (ira_dump_file, " Alt %d:", alt); | |
546 | for (i = 0; i < n_ops; i++) | |
547 | { | |
548 | p = constraints[i]; | |
549 | if (*p == '\0') | |
550 | continue; | |
551 | fprintf (ira_dump_file, " (%d) ", i); | |
552 | for (; *p != '\0' && *p != ',' && *p != '#'; p++) | |
553 | fputc (*p, ira_dump_file); | |
554 | } | |
555 | fprintf (ira_dump_file, "\n"); | |
556 | } | |
557 | ||
058e97ec VM |
558 | for (i = 0; i < n_ops; i++) |
559 | { | |
560 | unsigned char c; | |
561 | const char *p = constraints[i]; | |
562 | rtx op = ops[i]; | |
ef4bddc2 | 563 | machine_mode mode = modes[i]; |
058e97ec VM |
564 | int allows_addr = 0; |
565 | int win = 0; | |
566 | ||
567 | /* Initially show we know nothing about the register class. */ | |
568 | classes[i] = NO_REGS; | |
569 | allows_mem[i] = 0; | |
570 | ||
571 | /* If this operand has no constraints at all, we can | |
572 | conclude nothing about it since anything is valid. */ | |
573 | if (*p == 0) | |
574 | { | |
575 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
576 | memset (this_op_costs[i], 0, struct_costs_size); | |
577 | continue; | |
578 | } | |
579 | ||
580 | /* If this alternative is only relevant when this operand | |
581 | matches a previous operand, we do different things | |
582 | depending on whether this operand is a allocno-reg or not. | |
583 | We must process any modifiers for the operand before we | |
584 | can make this test. */ | |
585 | while (*p == '%' || *p == '=' || *p == '+' || *p == '&') | |
586 | p++; | |
587 | ||
d81c5030 | 588 | if (p[0] >= '0' && p[0] <= '0' + i) |
058e97ec VM |
589 | { |
590 | /* Copy class and whether memory is allowed from the | |
591 | matching alternative. Then perform any needed cost | |
592 | computations and/or adjustments. */ | |
593 | j = p[0] - '0'; | |
594 | classes[i] = classes[j]; | |
595 | allows_mem[i] = allows_mem[j]; | |
927425df VM |
596 | if (allows_mem[i]) |
597 | insn_allows_mem[i] = 1; | |
058e97ec VM |
598 | |
599 | if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
600 | { | |
601 | /* If this matches the other operand, we have no | |
602 | added cost and we win. */ | |
603 | if (rtx_equal_p (ops[j], op)) | |
604 | win = 1; | |
605 | /* If we can put the other operand into a register, | |
606 | add to the cost of this alternative the cost to | |
607 | copy this operand to the register used for the | |
608 | other operand. */ | |
609 | else if (classes[j] != NO_REGS) | |
610 | { | |
611 | alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
612 | win = 1; | |
613 | } | |
614 | } | |
615 | else if (! REG_P (ops[j]) | |
616 | || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
617 | { | |
618 | /* This op is an allocno but the one it matches is | |
619 | not. */ | |
620 | ||
621 | /* If we can't put the other operand into a | |
622 | register, this alternative can't be used. */ | |
623 | ||
624 | if (classes[j] == NO_REGS) | |
2639f9d2 VM |
625 | { |
626 | alt_fail = 1; | |
627 | } | |
058e97ec | 628 | else |
2639f9d2 VM |
629 | /* Otherwise, add to the cost of this alternative the cost |
630 | to copy the other operand to the hard register used for | |
631 | this operand. */ | |
632 | { | |
633 | alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); | |
634 | } | |
058e97ec VM |
635 | } |
636 | else | |
637 | { | |
638 | /* The costs of this operand are not the same as the | |
639 | other operand since move costs are not symmetric. | |
640 | Moreover, if we cannot tie them, this alternative | |
641 | needs to do a copy, which is one insn. */ | |
642 | struct costs *pp = this_op_costs[i]; | |
1756cb66 VM |
643 | int *pp_costs = pp->cost; |
644 | cost_classes_t cost_classes_ptr | |
645 | = regno_cost_classes[REGNO (op)]; | |
646 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
647 | bool in_p = recog_data.operand_type[i] != OP_OUT; | |
648 | bool out_p = recog_data.operand_type[i] != OP_IN; | |
649 | enum reg_class op_class = classes[i]; | |
1756cb66 VM |
650 | |
651 | ira_init_register_move_cost_if_necessary (mode); | |
652 | if (! in_p) | |
fe82cdfb | 653 | { |
1756cb66 | 654 | ira_assert (out_p); |
0a1eb350 | 655 | if (op_class == NO_REGS) |
1756cb66 | 656 | { |
0a1eb350 VM |
657 | mem_cost = ira_memory_move_cost[mode]; |
658 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
659 | { | |
660 | rclass = cost_classes[k]; | |
661 | pp_costs[k] = mem_cost[rclass][0] * frequency; | |
662 | } | |
663 | } | |
664 | else | |
665 | { | |
666 | move_out_cost = ira_may_move_out_cost[mode]; | |
667 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
668 | { | |
669 | rclass = cost_classes[k]; | |
670 | pp_costs[k] | |
671 | = move_out_cost[op_class][rclass] * frequency; | |
672 | } | |
1756cb66 VM |
673 | } |
674 | } | |
675 | else if (! out_p) | |
676 | { | |
677 | ira_assert (in_p); | |
0a1eb350 | 678 | if (op_class == NO_REGS) |
1756cb66 | 679 | { |
0a1eb350 VM |
680 | mem_cost = ira_memory_move_cost[mode]; |
681 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
682 | { | |
683 | rclass = cost_classes[k]; | |
684 | pp_costs[k] = mem_cost[rclass][1] * frequency; | |
685 | } | |
686 | } | |
687 | else | |
688 | { | |
689 | move_in_cost = ira_may_move_in_cost[mode]; | |
690 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
691 | { | |
692 | rclass = cost_classes[k]; | |
693 | pp_costs[k] | |
694 | = move_in_cost[rclass][op_class] * frequency; | |
695 | } | |
1756cb66 VM |
696 | } |
697 | } | |
698 | else | |
699 | { | |
0a1eb350 | 700 | if (op_class == NO_REGS) |
1756cb66 | 701 | { |
0a1eb350 VM |
702 | mem_cost = ira_memory_move_cost[mode]; |
703 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
704 | { | |
705 | rclass = cost_classes[k]; | |
706 | pp_costs[k] = ((mem_cost[rclass][0] | |
707 | + mem_cost[rclass][1]) | |
708 | * frequency); | |
709 | } | |
710 | } | |
711 | else | |
712 | { | |
713 | move_in_cost = ira_may_move_in_cost[mode]; | |
714 | move_out_cost = ira_may_move_out_cost[mode]; | |
715 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
716 | { | |
717 | rclass = cost_classes[k]; | |
718 | pp_costs[k] = ((move_in_cost[rclass][op_class] | |
719 | + move_out_cost[op_class][rclass]) | |
720 | * frequency); | |
721 | } | |
1756cb66 | 722 | } |
058e97ec VM |
723 | } |
724 | ||
725 | /* If the alternative actually allows memory, make | |
726 | things a bit cheaper since we won't need an extra | |
727 | insn to load it. */ | |
728 | pp->mem_cost | |
1756cb66 VM |
729 | = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0) |
730 | + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0) | |
058e97ec | 731 | - allows_mem[i]) * frequency; |
927425df | 732 | |
1756cb66 VM |
733 | /* If we have assigned a class to this allocno in |
734 | our first pass, add a cost to this alternative | |
735 | corresponding to what we would add if this | |
736 | allocno were not in the appropriate class. */ | |
ce18efcb | 737 | if (pref) |
058e97ec | 738 | { |
ce18efcb | 739 | enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
058e97ec VM |
740 | |
741 | if (pref_class == NO_REGS) | |
742 | alt_cost | |
1756cb66 VM |
743 | += ((out_p |
744 | ? ira_memory_move_cost[mode][op_class][0] : 0) | |
745 | + (in_p | |
746 | ? ira_memory_move_cost[mode][op_class][1] | |
058e97ec VM |
747 | : 0)); |
748 | else if (ira_reg_class_intersect | |
1756cb66 VM |
749 | [pref_class][op_class] == NO_REGS) |
750 | alt_cost | |
751 | += ira_register_move_cost[mode][pref_class][op_class]; | |
058e97ec VM |
752 | } |
753 | if (REGNO (ops[i]) != REGNO (ops[j]) | |
754 | && ! find_reg_note (insn, REG_DEAD, op)) | |
755 | alt_cost += 2; | |
756 | ||
d81c5030 | 757 | p++; |
058e97ec VM |
758 | } |
759 | } | |
b8698a0f | 760 | |
058e97ec VM |
761 | /* Scan all the constraint letters. See if the operand |
762 | matches any of the constraints. Collect the valid | |
763 | register classes and see if this operand accepts | |
764 | memory. */ | |
765 | while ((c = *p)) | |
766 | { | |
767 | switch (c) | |
768 | { | |
058e97ec VM |
769 | case '*': |
770 | /* Ignore the next letter for this pass. */ | |
771 | c = *++p; | |
772 | break; | |
773 | ||
d1457701 VM |
774 | case '^': |
775 | alt_cost += 2; | |
776 | break; | |
777 | ||
058e97ec VM |
778 | case '?': |
779 | alt_cost += 2; | |
058e97ec VM |
780 | break; |
781 | ||
782 | case 'g': | |
783 | if (MEM_P (op) | |
784 | || (CONSTANT_P (op) | |
785 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) | |
786 | win = 1; | |
927425df | 787 | insn_allows_mem[i] = allows_mem[i] = 1; |
1756cb66 | 788 | classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS]; |
058e97ec VM |
789 | break; |
790 | ||
791 | default: | |
777e635f RS |
792 | enum constraint_num cn = lookup_constraint (p); |
793 | enum reg_class cl; | |
794 | switch (get_constraint_type (cn)) | |
058e97ec | 795 | { |
777e635f RS |
796 | case CT_REGISTER: |
797 | cl = reg_class_for_constraint (cn); | |
798 | if (cl != NO_REGS) | |
799 | classes[i] = ira_reg_class_subunion[classes[i]][cl]; | |
800 | break; | |
801 | ||
d9c35eee RS |
802 | case CT_CONST_INT: |
803 | if (CONST_INT_P (op) | |
804 | && insn_const_int_ok_for_constraint (INTVAL (op), cn)) | |
805 | win = 1; | |
806 | break; | |
807 | ||
777e635f | 808 | case CT_MEMORY: |
0d37e2d3 | 809 | case CT_RELAXED_MEMORY: |
058e97ec | 810 | /* Every MEM can be reloaded to fit. */ |
927425df | 811 | insn_allows_mem[i] = allows_mem[i] = 1; |
058e97ec VM |
812 | if (MEM_P (op)) |
813 | win = 1; | |
777e635f RS |
814 | break; |
815 | ||
9eb1ca69 VM |
816 | case CT_SPECIAL_MEMORY: |
817 | insn_allows_mem[i] = allows_mem[i] = 1; | |
4de7b010 | 818 | if (MEM_P (extract_mem_from_operand (op)) |
819 | && constraint_satisfied_p (op, cn)) | |
9eb1ca69 VM |
820 | win = 1; |
821 | break; | |
822 | ||
777e635f | 823 | case CT_ADDRESS: |
058e97ec VM |
824 | /* Every address can be reloaded to fit. */ |
825 | allows_addr = 1; | |
777e635f RS |
826 | if (address_operand (op, GET_MODE (op)) |
827 | || constraint_satisfied_p (op, cn)) | |
058e97ec VM |
828 | win = 1; |
829 | /* We know this operand is an address, so we | |
830 | want it to be allocated to a hard register | |
831 | that can be the base of an address, | |
832 | i.e. BASE_REG_CLASS. */ | |
833 | classes[i] | |
1756cb66 | 834 | = ira_reg_class_subunion[classes[i]] |
86fc3d06 UW |
835 | [base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, |
836 | ADDRESS, SCRATCH)]; | |
777e635f RS |
837 | break; |
838 | ||
839 | case CT_FIXED_FORM: | |
840 | if (constraint_satisfied_p (op, cn)) | |
841 | win = 1; | |
842 | break; | |
058e97ec | 843 | } |
058e97ec VM |
844 | break; |
845 | } | |
846 | p += CONSTRAINT_LEN (c, p); | |
847 | if (c == ',') | |
848 | break; | |
849 | } | |
850 | ||
851 | constraints[i] = p; | |
852 | ||
3d8e4920 RS |
853 | if (alt_fail) |
854 | break; | |
855 | ||
058e97ec VM |
856 | /* How we account for this operand now depends on whether it |
857 | is a pseudo register or not. If it is, we first check if | |
858 | any register classes are valid. If not, we ignore this | |
859 | alternative, since we want to assume that all allocnos get | |
860 | allocated for register preferencing. If some register | |
861 | class is valid, compute the costs of moving the allocno | |
862 | into that class. */ | |
863 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
864 | { | |
f4e075e7 | 865 | if (classes[i] == NO_REGS && ! allows_mem[i]) |
058e97ec VM |
866 | { |
867 | /* We must always fail if the operand is a REG, but | |
f4e075e7 VM |
868 | we did not find a suitable class and memory is |
869 | not allowed. | |
058e97ec VM |
870 | |
871 | Otherwise we may perform an uninitialized read | |
872 | from this_op_costs after the `continue' statement | |
873 | below. */ | |
874 | alt_fail = 1; | |
875 | } | |
876 | else | |
877 | { | |
1756cb66 | 878 | unsigned int regno = REGNO (op); |
058e97ec | 879 | struct costs *pp = this_op_costs[i]; |
1756cb66 VM |
880 | int *pp_costs = pp->cost; |
881 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
882 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
883 | bool in_p = recog_data.operand_type[i] != OP_OUT; | |
884 | bool out_p = recog_data.operand_type[i] != OP_IN; | |
885 | enum reg_class op_class = classes[i]; | |
1756cb66 VM |
886 | |
887 | ira_init_register_move_cost_if_necessary (mode); | |
888 | if (! in_p) | |
fe82cdfb | 889 | { |
1756cb66 | 890 | ira_assert (out_p); |
f4e075e7 | 891 | if (op_class == NO_REGS) |
1756cb66 | 892 | { |
f4e075e7 VM |
893 | mem_cost = ira_memory_move_cost[mode]; |
894 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
895 | { | |
896 | rclass = cost_classes[k]; | |
897 | pp_costs[k] = mem_cost[rclass][0] * frequency; | |
898 | } | |
899 | } | |
900 | else | |
901 | { | |
902 | move_out_cost = ira_may_move_out_cost[mode]; | |
903 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
904 | { | |
905 | rclass = cost_classes[k]; | |
906 | pp_costs[k] | |
907 | = move_out_cost[op_class][rclass] * frequency; | |
908 | } | |
1756cb66 VM |
909 | } |
910 | } | |
911 | else if (! out_p) | |
912 | { | |
913 | ira_assert (in_p); | |
f4e075e7 | 914 | if (op_class == NO_REGS) |
1756cb66 | 915 | { |
f4e075e7 VM |
916 | mem_cost = ira_memory_move_cost[mode]; |
917 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
918 | { | |
919 | rclass = cost_classes[k]; | |
920 | pp_costs[k] = mem_cost[rclass][1] * frequency; | |
921 | } | |
922 | } | |
923 | else | |
924 | { | |
925 | move_in_cost = ira_may_move_in_cost[mode]; | |
926 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
927 | { | |
928 | rclass = cost_classes[k]; | |
929 | pp_costs[k] | |
930 | = move_in_cost[rclass][op_class] * frequency; | |
931 | } | |
1756cb66 VM |
932 | } |
933 | } | |
934 | else | |
935 | { | |
f4e075e7 | 936 | if (op_class == NO_REGS) |
1756cb66 | 937 | { |
f4e075e7 VM |
938 | mem_cost = ira_memory_move_cost[mode]; |
939 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
940 | { | |
941 | rclass = cost_classes[k]; | |
942 | pp_costs[k] = ((mem_cost[rclass][0] | |
943 | + mem_cost[rclass][1]) | |
944 | * frequency); | |
945 | } | |
946 | } | |
947 | else | |
948 | { | |
949 | move_in_cost = ira_may_move_in_cost[mode]; | |
950 | move_out_cost = ira_may_move_out_cost[mode]; | |
951 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
952 | { | |
953 | rclass = cost_classes[k]; | |
954 | pp_costs[k] = ((move_in_cost[rclass][op_class] | |
955 | + move_out_cost[op_class][rclass]) | |
956 | * frequency); | |
957 | } | |
1756cb66 | 958 | } |
058e97ec VM |
959 | } |
960 | ||
0a1eb350 VM |
961 | if (op_class == NO_REGS) |
962 | /* Although we don't need insn to reload from | |
963 | memory, still accessing memory is usually more | |
964 | expensive than a register. */ | |
965 | pp->mem_cost = frequency; | |
966 | else | |
967 | /* If the alternative actually allows memory, make | |
968 | things a bit cheaper since we won't need an | |
969 | extra insn to load it. */ | |
f4e075e7 VM |
970 | pp->mem_cost |
971 | = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0) | |
972 | + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0) | |
973 | - allows_mem[i]) * frequency; | |
1756cb66 VM |
974 | /* If we have assigned a class to this allocno in |
975 | our first pass, add a cost to this alternative | |
976 | corresponding to what we would add if this | |
977 | allocno were not in the appropriate class. */ | |
ce18efcb | 978 | if (pref) |
058e97ec | 979 | { |
ce18efcb | 980 | enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
058e97ec VM |
981 | |
982 | if (pref_class == NO_REGS) | |
f4e075e7 VM |
983 | { |
984 | if (op_class != NO_REGS) | |
985 | alt_cost | |
986 | += ((out_p | |
987 | ? ira_memory_move_cost[mode][op_class][0] | |
988 | : 0) | |
989 | + (in_p | |
990 | ? ira_memory_move_cost[mode][op_class][1] | |
991 | : 0)); | |
992 | } | |
993 | else if (op_class == NO_REGS) | |
058e97ec | 994 | alt_cost |
1756cb66 | 995 | += ((out_p |
f4e075e7 VM |
996 | ? ira_memory_move_cost[mode][pref_class][1] |
997 | : 0) | |
1756cb66 | 998 | + (in_p |
f4e075e7 | 999 | ? ira_memory_move_cost[mode][pref_class][0] |
058e97ec | 1000 | : 0)); |
1756cb66 | 1001 | else if (ira_reg_class_intersect[pref_class][op_class] |
058e97ec | 1002 | == NO_REGS) |
f4e075e7 VM |
1003 | alt_cost += (ira_register_move_cost |
1004 | [mode][pref_class][op_class]); | |
058e97ec VM |
1005 | } |
1006 | } | |
1007 | } | |
1008 | ||
1009 | /* Otherwise, if this alternative wins, either because we | |
1010 | have already determined that or if we have a hard | |
1011 | register of the proper class, there is no cost for this | |
1012 | alternative. */ | |
1013 | else if (win || (REG_P (op) | |
1014 | && reg_fits_class_p (op, classes[i], | |
1015 | 0, GET_MODE (op)))) | |
1016 | ; | |
1017 | ||
1018 | /* If registers are valid, the cost of this alternative | |
1019 | includes copying the object to and/or from a | |
1020 | register. */ | |
1021 | else if (classes[i] != NO_REGS) | |
1022 | { | |
1023 | if (recog_data.operand_type[i] != OP_OUT) | |
1024 | alt_cost += copy_cost (op, mode, classes[i], 1, NULL); | |
1025 | ||
1026 | if (recog_data.operand_type[i] != OP_IN) | |
1027 | alt_cost += copy_cost (op, mode, classes[i], 0, NULL); | |
1028 | } | |
1029 | /* The only other way this alternative can be used is if | |
1030 | this is a constant that could be placed into memory. */ | |
1031 | else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) | |
1032 | alt_cost += ira_memory_move_cost[mode][classes[i]][1]; | |
1033 | else | |
1034 | alt_fail = 1; | |
3d8e4920 RS |
1035 | |
1036 | if (alt_fail) | |
1037 | break; | |
058e97ec VM |
1038 | } |
1039 | ||
1040 | if (alt_fail) | |
3d8e4920 RS |
1041 | { |
1042 | /* The loop above might have exited early once the failure | |
1043 | was seen. Skip over the constraints for the remaining | |
1044 | operands. */ | |
1045 | i += 1; | |
1046 | for (; i < n_ops; ++i) | |
1047 | constraints[i] = skip_alternative (constraints[i]); | |
1048 | continue; | |
1049 | } | |
058e97ec VM |
1050 | |
1051 | op_cost_add = alt_cost * frequency; | |
1052 | /* Finally, update the costs with the information we've | |
1053 | calculated about this alternative. */ | |
1054 | for (i = 0; i < n_ops; i++) | |
1055 | if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
1056 | { | |
2639f9d2 VM |
1057 | int old_cost; |
1058 | bool cost_change_p = false; | |
058e97ec | 1059 | struct costs *pp = op_costs[i], *qq = this_op_costs[i]; |
1756cb66 | 1060 | int *pp_costs = pp->cost, *qq_costs = qq->cost; |
058e97ec | 1061 | int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); |
1756cb66 VM |
1062 | cost_classes_t cost_classes_ptr |
1063 | = regno_cost_classes[REGNO (ops[i])]; | |
058e97ec | 1064 | |
2639f9d2 VM |
1065 | old_cost = pp->mem_cost; |
1066 | pp->mem_cost = MIN (old_cost, | |
058e97ec VM |
1067 | (qq->mem_cost + op_cost_add) * scale); |
1068 | ||
2639f9d2 VM |
1069 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5 |
1070 | && pp->mem_cost < old_cost) | |
1071 | { | |
1072 | cost_change_p = true; | |
1073 | fprintf (ira_dump_file, " op %d(r=%u) new costs MEM:%d", | |
1074 | i, REGNO(ops[i]), pp->mem_cost); | |
1075 | } | |
1756cb66 | 1076 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) |
2639f9d2 VM |
1077 | { |
1078 | old_cost = pp_costs[k]; | |
1079 | pp_costs[k] | |
1080 | = MIN (old_cost, (qq_costs[k] + op_cost_add) * scale); | |
1081 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5 | |
1082 | && pp_costs[k] < old_cost) | |
1083 | { | |
1084 | if (!cost_change_p) | |
1085 | fprintf (ira_dump_file, " op %d(r=%u) new costs", | |
1086 | i, REGNO(ops[i])); | |
1087 | cost_change_p = true; | |
1088 | fprintf (ira_dump_file, " %s:%d", | |
1089 | reg_class_names[cost_classes_ptr->classes[k]], | |
1090 | pp_costs[k]); | |
1091 | } | |
1092 | } | |
1093 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5 | |
1094 | && cost_change_p) | |
1095 | fprintf (ira_dump_file, "\n"); | |
058e97ec VM |
1096 | } |
1097 | } | |
1098 | ||
ce18efcb VM |
1099 | if (allocno_p) |
1100 | for (i = 0; i < n_ops; i++) | |
1101 | { | |
1102 | ira_allocno_t a; | |
1103 | rtx op = ops[i]; | |
b8698a0f | 1104 | |
ce18efcb VM |
1105 | if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
1106 | continue; | |
1107 | a = ira_curr_regno_allocno_map [REGNO (op)]; | |
1108 | if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0) | |
1109 | ALLOCNO_BAD_SPILL_P (a) = true; | |
1110 | } | |
927425df | 1111 | |
058e97ec VM |
1112 | } |
1113 | ||
1114 | \f | |
1115 | ||
1116 | /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ | |
1117 | static inline bool | |
1118 | ok_for_index_p_nonstrict (rtx reg) | |
1119 | { | |
1120 | unsigned regno = REGNO (reg); | |
1121 | ||
1122 | return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
1123 | } | |
1124 | ||
1125 | /* A version of regno_ok_for_base_p for use here, when all | |
1126 | pseudo-registers should count as OK. Arguments as for | |
1127 | regno_ok_for_base_p. */ | |
1128 | static inline bool | |
ef4bddc2 | 1129 | ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as, |
058e97ec VM |
1130 | enum rtx_code outer_code, enum rtx_code index_code) |
1131 | { | |
1132 | unsigned regno = REGNO (reg); | |
1133 | ||
1134 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1135 | return true; | |
86fc3d06 | 1136 | return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); |
058e97ec VM |
1137 | } |
1138 | ||
1139 | /* Record the pseudo registers we must reload into hard registers in a | |
1140 | subexpression of a memory address, X. | |
1141 | ||
1142 | If CONTEXT is 0, we are looking at the base part of an address, | |
1143 | otherwise we are looking at the index part. | |
1144 | ||
86fc3d06 UW |
1145 | MODE and AS are the mode and address space of the memory reference; |
1146 | OUTER_CODE and INDEX_CODE give the context that the rtx appears in. | |
1147 | These four arguments are passed down to base_reg_class. | |
058e97ec VM |
1148 | |
1149 | SCALE is twice the amount to multiply the cost by (it is twice so | |
1150 | we can represent half-cost adjustments). */ | |
1151 | static void | |
ef4bddc2 | 1152 | record_address_regs (machine_mode mode, addr_space_t as, rtx x, |
86fc3d06 UW |
1153 | int context, enum rtx_code outer_code, |
1154 | enum rtx_code index_code, int scale) | |
058e97ec VM |
1155 | { |
1156 | enum rtx_code code = GET_CODE (x); | |
1157 | enum reg_class rclass; | |
1158 | ||
1159 | if (context == 1) | |
1160 | rclass = INDEX_REG_CLASS; | |
1161 | else | |
86fc3d06 | 1162 | rclass = base_reg_class (mode, as, outer_code, index_code); |
058e97ec VM |
1163 | |
1164 | switch (code) | |
1165 | { | |
1166 | case CONST_INT: | |
1167 | case CONST: | |
058e97ec VM |
1168 | case PC: |
1169 | case SYMBOL_REF: | |
1170 | case LABEL_REF: | |
1171 | return; | |
1172 | ||
1173 | case PLUS: | |
1174 | /* When we have an address that is a sum, we must determine | |
1175 | whether registers are "base" or "index" regs. If there is a | |
1176 | sum of two registers, we must choose one to be the "base". | |
1177 | Luckily, we can use the REG_POINTER to make a good choice | |
1178 | most of the time. We only need to do this on machines that | |
1179 | can have two registers in an address and where the base and | |
1180 | index register classes are different. | |
1181 | ||
1182 | ??? This code used to set REGNO_POINTER_FLAG in some cases, | |
1183 | but that seems bogus since it should only be set when we are | |
1184 | sure the register is being used as a pointer. */ | |
1185 | { | |
1186 | rtx arg0 = XEXP (x, 0); | |
1187 | rtx arg1 = XEXP (x, 1); | |
1188 | enum rtx_code code0 = GET_CODE (arg0); | |
1189 | enum rtx_code code1 = GET_CODE (arg1); | |
1190 | ||
1191 | /* Look inside subregs. */ | |
1192 | if (code0 == SUBREG) | |
1193 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
1194 | if (code1 == SUBREG) | |
1195 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
1196 | ||
9f1c93df | 1197 | /* If index registers do not appear, or coincide with base registers, |
058e97ec VM |
1198 | just record registers in any non-constant operands. We |
1199 | assume here, as well as in the tests below, that all | |
1200 | addresses are in canonical form. */ | |
9f1c93df AM |
1201 | if (MAX_REGS_PER_ADDRESS == 1 |
1202 | || INDEX_REG_CLASS == base_reg_class (VOIDmode, as, PLUS, SCRATCH)) | |
058e97ec | 1203 | { |
86fc3d06 | 1204 | record_address_regs (mode, as, arg0, context, PLUS, code1, scale); |
058e97ec | 1205 | if (! CONSTANT_P (arg1)) |
86fc3d06 | 1206 | record_address_regs (mode, as, arg1, context, PLUS, code0, scale); |
058e97ec VM |
1207 | } |
1208 | ||
1209 | /* If the second operand is a constant integer, it doesn't | |
1210 | change what class the first operand must be. */ | |
33ffb5c5 | 1211 | else if (CONST_SCALAR_INT_P (arg1)) |
86fc3d06 | 1212 | record_address_regs (mode, as, arg0, context, PLUS, code1, scale); |
058e97ec VM |
1213 | /* If the second operand is a symbolic constant, the first |
1214 | operand must be an index register. */ | |
1215 | else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
86fc3d06 | 1216 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale); |
058e97ec VM |
1217 | /* If both operands are registers but one is already a hard |
1218 | register of index or reg-base class, give the other the | |
1219 | class that the hard register is not. */ | |
1220 | else if (code0 == REG && code1 == REG | |
1221 | && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
86fc3d06 | 1222 | && (ok_for_base_p_nonstrict (arg0, mode, as, PLUS, REG) |
058e97ec | 1223 | || ok_for_index_p_nonstrict (arg0))) |
86fc3d06 UW |
1224 | record_address_regs (mode, as, arg1, |
1225 | ok_for_base_p_nonstrict (arg0, mode, as, | |
1226 | PLUS, REG) ? 1 : 0, | |
058e97ec VM |
1227 | PLUS, REG, scale); |
1228 | else if (code0 == REG && code1 == REG | |
1229 | && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
86fc3d06 | 1230 | && (ok_for_base_p_nonstrict (arg1, mode, as, PLUS, REG) |
058e97ec | 1231 | || ok_for_index_p_nonstrict (arg1))) |
86fc3d06 UW |
1232 | record_address_regs (mode, as, arg0, |
1233 | ok_for_base_p_nonstrict (arg1, mode, as, | |
1234 | PLUS, REG) ? 1 : 0, | |
058e97ec VM |
1235 | PLUS, REG, scale); |
1236 | /* If one operand is known to be a pointer, it must be the | |
1237 | base with the other operand the index. Likewise if the | |
1238 | other operand is a MULT. */ | |
1239 | else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT) | |
1240 | { | |
86fc3d06 UW |
1241 | record_address_regs (mode, as, arg0, 0, PLUS, code1, scale); |
1242 | record_address_regs (mode, as, arg1, 1, PLUS, code0, scale); | |
058e97ec VM |
1243 | } |
1244 | else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT) | |
1245 | { | |
86fc3d06 UW |
1246 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale); |
1247 | record_address_regs (mode, as, arg1, 0, PLUS, code0, scale); | |
058e97ec VM |
1248 | } |
1249 | /* Otherwise, count equal chances that each might be a base or | |
1250 | index register. This case should be rare. */ | |
1251 | else | |
1252 | { | |
86fc3d06 UW |
1253 | record_address_regs (mode, as, arg0, 0, PLUS, code1, scale / 2); |
1254 | record_address_regs (mode, as, arg0, 1, PLUS, code1, scale / 2); | |
1255 | record_address_regs (mode, as, arg1, 0, PLUS, code0, scale / 2); | |
1256 | record_address_regs (mode, as, arg1, 1, PLUS, code0, scale / 2); | |
058e97ec VM |
1257 | } |
1258 | } | |
1259 | break; | |
1260 | ||
1261 | /* Double the importance of an allocno that is incremented or | |
1262 | decremented, since it would take two extra insns if it ends | |
1263 | up in the wrong place. */ | |
1264 | case POST_MODIFY: | |
1265 | case PRE_MODIFY: | |
86fc3d06 | 1266 | record_address_regs (mode, as, XEXP (x, 0), 0, code, |
058e97ec VM |
1267 | GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); |
1268 | if (REG_P (XEXP (XEXP (x, 1), 1))) | |
86fc3d06 | 1269 | record_address_regs (mode, as, XEXP (XEXP (x, 1), 1), 1, code, REG, |
058e97ec VM |
1270 | 2 * scale); |
1271 | break; | |
1272 | ||
1273 | case POST_INC: | |
1274 | case PRE_INC: | |
1275 | case POST_DEC: | |
1276 | case PRE_DEC: | |
1277 | /* Double the importance of an allocno that is incremented or | |
1278 | decremented, since it would take two extra insns if it ends | |
9aaa7e47 | 1279 | up in the wrong place. */ |
86fc3d06 | 1280 | record_address_regs (mode, as, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); |
058e97ec VM |
1281 | break; |
1282 | ||
1283 | case REG: | |
1284 | { | |
1285 | struct costs *pp; | |
1756cb66 | 1286 | int *pp_costs; |
bbbbb16a | 1287 | enum reg_class i; |
1756cb66 VM |
1288 | int k, regno, add_cost; |
1289 | cost_classes_t cost_classes_ptr; | |
1290 | enum reg_class *cost_classes; | |
1291 | move_table *move_in_cost; | |
058e97ec VM |
1292 | |
1293 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
1294 | break; | |
1295 | ||
1756cb66 | 1296 | regno = REGNO (x); |
ce18efcb | 1297 | if (allocno_p) |
1756cb66 VM |
1298 | ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) = true; |
1299 | pp = COSTS (costs, COST_INDEX (regno)); | |
1300 | add_cost = (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; | |
1301 | if (INT_MAX - add_cost < pp->mem_cost) | |
1302 | pp->mem_cost = INT_MAX; | |
1303 | else | |
1304 | pp->mem_cost += add_cost; | |
1305 | cost_classes_ptr = regno_cost_classes[regno]; | |
1306 | cost_classes = cost_classes_ptr->classes; | |
1307 | pp_costs = pp->cost; | |
1308 | ira_init_register_move_cost_if_necessary (Pmode); | |
1309 | move_in_cost = ira_may_move_in_cost[Pmode]; | |
1310 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
058e97ec VM |
1311 | { |
1312 | i = cost_classes[k]; | |
1756cb66 VM |
1313 | add_cost = (move_in_cost[i][rclass] * scale) / 2; |
1314 | if (INT_MAX - add_cost < pp_costs[k]) | |
1315 | pp_costs[k] = INT_MAX; | |
eeae9314 | 1316 | else |
1756cb66 | 1317 | pp_costs[k] += add_cost; |
058e97ec VM |
1318 | } |
1319 | } | |
1320 | break; | |
1321 | ||
1322 | default: | |
1323 | { | |
1324 | const char *fmt = GET_RTX_FORMAT (code); | |
1325 | int i; | |
1326 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1327 | if (fmt[i] == 'e') | |
86fc3d06 | 1328 | record_address_regs (mode, as, XEXP (x, i), context, code, SCRATCH, |
058e97ec VM |
1329 | scale); |
1330 | } | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | \f | |
1335 | ||
1336 | /* Calculate the costs of insn operands. */ | |
1337 | static void | |
070a1983 | 1338 | record_operand_costs (rtx_insn *insn, enum reg_class *pref) |
058e97ec VM |
1339 | { |
1340 | const char *constraints[MAX_RECOG_OPERANDS]; | |
ef4bddc2 | 1341 | machine_mode modes[MAX_RECOG_OPERANDS]; |
3b6d1699 | 1342 | rtx set; |
058e97ec VM |
1343 | int i; |
1344 | ||
eeae9314 VM |
1345 | if ((set = single_set (insn)) != NULL_RTX |
1346 | /* In rare cases the single set insn might have less 2 operands | |
1347 | as the source can be a fixed special reg. */ | |
1348 | && recog_data.n_operands > 1 | |
1349 | && recog_data.operand[0] == SET_DEST (set) | |
1350 | && recog_data.operand[1] == SET_SRC (set)) | |
1351 | { | |
1352 | int regno, other_regno; | |
1353 | rtx dest = SET_DEST (set); | |
1354 | rtx src = SET_SRC (set); | |
1355 | ||
1356 | if (GET_CODE (dest) == SUBREG | |
1357 | && known_eq (GET_MODE_SIZE (GET_MODE (dest)), | |
1358 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))))) | |
1359 | dest = SUBREG_REG (dest); | |
1360 | if (GET_CODE (src) == SUBREG | |
1361 | && known_eq (GET_MODE_SIZE (GET_MODE (src)), | |
1362 | GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))) | |
1363 | src = SUBREG_REG (src); | |
1364 | if (REG_P (src) && REG_P (dest) | |
1365 | && (((regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
1366 | && (other_regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER) | |
1367 | || ((regno = REGNO (dest)) >= FIRST_PSEUDO_REGISTER | |
1368 | && (other_regno = REGNO (src)) < FIRST_PSEUDO_REGISTER))) | |
1369 | { | |
2639f9d2 VM |
1370 | machine_mode mode = GET_MODE (SET_SRC (set)), cost_mode = mode; |
1371 | machine_mode hard_reg_mode = GET_MODE(regno_reg_rtx[other_regno]); | |
1372 | poly_int64 pmode_size = GET_MODE_SIZE (mode); | |
1373 | poly_int64 phard_reg_mode_size = GET_MODE_SIZE (hard_reg_mode); | |
1374 | HOST_WIDE_INT mode_size, hard_reg_mode_size; | |
eeae9314 VM |
1375 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; |
1376 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
a7acb6dc | 1377 | reg_class_t rclass, hard_reg_class, bigger_hard_reg_class; |
2639f9d2 | 1378 | int cost_factor = 1, cost, k; |
36d070a7 | 1379 | move_table *move_costs; |
eeae9314 VM |
1380 | bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src)); |
1381 | ||
1382 | hard_reg_class = REGNO_REG_CLASS (other_regno); | |
2639f9d2 VM |
1383 | bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class]; |
1384 | /* Target code may return any cost for mode which does not fit the | |
1385 | hard reg class (e.g. DImode for AREG on i386). Check this and use | |
1386 | a bigger class to get the right cost. */ | |
1387 | if (bigger_hard_reg_class != NO_REGS | |
1388 | && ! ira_hard_reg_in_set_p (other_regno, mode, | |
1389 | reg_class_contents[hard_reg_class])) | |
1390 | hard_reg_class = bigger_hard_reg_class; | |
1391 | ira_init_register_move_cost_if_necessary (mode); | |
1392 | ira_init_register_move_cost_if_necessary (hard_reg_mode); | |
1393 | /* Use smaller movement cost for natural hard reg mode or its mode as | |
1394 | operand. */ | |
1395 | if (pmode_size.is_constant (&mode_size) | |
1396 | && phard_reg_mode_size.is_constant (&hard_reg_mode_size)) | |
1397 | { | |
1398 | /* Assume we are moving in the natural modes: */ | |
1399 | cost_factor = mode_size / hard_reg_mode_size; | |
1400 | if (mode_size % hard_reg_mode_size != 0) | |
1401 | cost_factor++; | |
1402 | if (cost_factor | |
1403 | * (ira_register_move_cost | |
1404 | [hard_reg_mode][hard_reg_class][hard_reg_class]) | |
1405 | < (ira_register_move_cost | |
1406 | [mode][hard_reg_class][hard_reg_class])) | |
1407 | cost_mode = hard_reg_mode; | |
1408 | else | |
1409 | cost_factor = 1; | |
1410 | } | |
1411 | move_costs = ira_register_move_cost[cost_mode]; | |
eeae9314 VM |
1412 | i = regno == (int) REGNO (src) ? 1 : 0; |
1413 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
1414 | { | |
1415 | rclass = cost_classes[k]; | |
36d070a7 VM |
1416 | cost = (i == 0 |
1417 | ? move_costs[hard_reg_class][rclass] | |
1418 | : move_costs[rclass][hard_reg_class]); | |
2639f9d2 | 1419 | cost *= cost_factor; |
36d070a7 | 1420 | op_costs[i]->cost[k] = cost * frequency; |
eeae9314 VM |
1421 | /* If this insn is a single set copying operand 1 to |
1422 | operand 0 and one operand is an allocno with the | |
1423 | other a hard reg or an allocno that prefers a hard | |
1424 | register that is in its own register class then we | |
1425 | may want to adjust the cost of that register class to | |
1426 | -1. | |
1427 | ||
1428 | Avoid the adjustment if the source does not die to | |
1429 | avoid stressing of register allocator by preferencing | |
1430 | two colliding registers into single class. */ | |
1431 | if (dead_p | |
1432 | && TEST_HARD_REG_BIT (reg_class_contents[rclass], other_regno) | |
1433 | && (reg_class_size[(int) rclass] | |
1434 | == (ira_reg_class_max_nregs | |
1435 | [(int) rclass][(int) GET_MODE(src)]))) | |
1436 | { | |
1437 | if (reg_class_size[rclass] == 1) | |
1438 | op_costs[i]->cost[k] = -frequency; | |
1439 | else if (in_hard_reg_set_p (reg_class_contents[rclass], | |
1440 | GET_MODE(src), other_regno)) | |
1441 | op_costs[i]->cost[k] = -frequency; | |
1442 | } | |
1443 | } | |
1444 | op_costs[i]->mem_cost | |
1445 | = ira_memory_move_cost[mode][hard_reg_class][i] * frequency; | |
eeae9314 VM |
1446 | return; |
1447 | } | |
1448 | } | |
1449 | ||
058e97ec VM |
1450 | for (i = 0; i < recog_data.n_operands; i++) |
1451 | { | |
1452 | constraints[i] = recog_data.constraints[i]; | |
1453 | modes[i] = recog_data.operand_mode[i]; | |
1454 | } | |
1455 | ||
1456 | /* If we get here, we are set up to record the costs of all the | |
1457 | operands for this insn. Start by initializing the costs. Then | |
1458 | handle any address registers. Finally record the desired classes | |
1459 | for any allocnos, doing it twice if some pair of operands are | |
1460 | commutative. */ | |
1461 | for (i = 0; i < recog_data.n_operands; i++) | |
1462 | { | |
4de7b010 | 1463 | rtx op_mem = extract_mem_from_operand (recog_data.operand[i]); |
058e97ec VM |
1464 | memcpy (op_costs[i], init_cost, struct_costs_size); |
1465 | ||
1466 | if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
1467 | recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
1468 | ||
4de7b010 | 1469 | if (MEM_P (op_mem)) |
1470 | record_address_regs (GET_MODE (op_mem), | |
1471 | MEM_ADDR_SPACE (op_mem), | |
1472 | XEXP (op_mem, 0), | |
058e97ec VM |
1473 | 0, MEM, SCRATCH, frequency * 2); |
1474 | else if (constraints[i][0] == 'p' | |
777e635f RS |
1475 | || (insn_extra_address_constraint |
1476 | (lookup_constraint (constraints[i])))) | |
86fc3d06 UW |
1477 | record_address_regs (VOIDmode, ADDR_SPACE_GENERIC, |
1478 | recog_data.operand[i], 0, ADDRESS, SCRATCH, | |
1479 | frequency * 2); | |
058e97ec | 1480 | } |
eeae9314 | 1481 | |
058e97ec VM |
1482 | /* Check for commutative in a separate loop so everything will have |
1483 | been initialized. We must do this even if one operand is a | |
1484 | constant--see addsi3 in m68k.md. */ | |
1485 | for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
1486 | if (constraints[i][0] == '%') | |
1487 | { | |
1488 | const char *xconstraints[MAX_RECOG_OPERANDS]; | |
1489 | int j; | |
1490 | ||
eeae9314 VM |
1491 | /* Handle commutative operands by swapping the |
1492 | constraints. We assume the modes are the same. */ | |
058e97ec VM |
1493 | for (j = 0; j < recog_data.n_operands; j++) |
1494 | xconstraints[j] = constraints[j]; | |
1495 | ||
1496 | xconstraints[i] = constraints[i+1]; | |
1497 | xconstraints[i+1] = constraints[i]; | |
1498 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
1499 | recog_data.operand, modes, | |
aa1c5d72 | 1500 | xconstraints, insn, pref); |
058e97ec VM |
1501 | } |
1502 | record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
1503 | recog_data.operand, modes, | |
aa1c5d72 | 1504 | constraints, insn, pref); |
058e97ec VM |
1505 | } |
1506 | ||
1507 | \f | |
1508 | ||
1509 | /* Process one insn INSN. Scan it and record each time it would save | |
1510 | code to put a certain allocnos in a certain class. Return the last | |
1511 | insn processed, so that the scan can be continued from there. */ | |
070a1983 DM |
1512 | static rtx_insn * |
1513 | scan_one_insn (rtx_insn *insn) | |
058e97ec VM |
1514 | { |
1515 | enum rtx_code pat_code; | |
1516 | rtx set, note; | |
1517 | int i, k; | |
82ce305c | 1518 | bool counted_mem; |
058e97ec | 1519 | |
39718607 | 1520 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec VM |
1521 | return insn; |
1522 | ||
1523 | pat_code = GET_CODE (PATTERN (insn)); | |
355930ab | 1524 | if (pat_code == ASM_INPUT) |
058e97ec VM |
1525 | return insn; |
1526 | ||
355930ab JL |
1527 | /* If INSN is a USE/CLOBBER of a pseudo in a mode M then go ahead |
1528 | and initialize the register move costs of mode M. | |
1529 | ||
1530 | The pseudo may be related to another pseudo via a copy (implicit or | |
1531 | explicit) and if there are no mode M uses/sets of the original | |
1532 | pseudo, then we may leave the register move costs uninitialized for | |
1533 | mode M. */ | |
1534 | if (pat_code == USE || pat_code == CLOBBER) | |
1535 | { | |
1536 | rtx x = XEXP (PATTERN (insn), 0); | |
1537 | if (GET_CODE (x) == REG | |
2c2d5d00 JL |
1538 | && REGNO (x) >= FIRST_PSEUDO_REGISTER |
1539 | && have_regs_of_mode[GET_MODE (x)]) | |
355930ab JL |
1540 | ira_init_register_move_cost_if_necessary (GET_MODE (x)); |
1541 | return insn; | |
1542 | } | |
1543 | ||
82ce305c | 1544 | counted_mem = false; |
058e97ec VM |
1545 | set = single_set (insn); |
1546 | extract_insn (insn); | |
1547 | ||
1548 | /* If this insn loads a parameter from its stack slot, then it | |
1549 | represents a savings, rather than a cost, if the parameter is | |
eeae9314 | 1550 | stored in memory. Record this fact. |
82ce305c JL |
1551 | |
1552 | Similarly if we're loading other constants from memory (constant | |
1553 | pool, TOC references, small data areas, etc) and this is the only | |
3db93c89 JJ |
1554 | assignment to the destination pseudo. |
1555 | ||
1556 | Don't do this if SET_SRC (set) isn't a general operand, if it is | |
1557 | a memory requiring special instructions to load it, decreasing | |
1558 | mem_cost might result in it being loaded using the specialized | |
1559 | instruction into a register, then stored into stack and loaded | |
b8578ff7 | 1560 | again from the stack. See PR52208. |
eeae9314 | 1561 | |
b8578ff7 | 1562 | Don't do this if SET_SRC (set) has side effect. See PR56124. */ |
058e97ec VM |
1563 | if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set)) |
1564 | && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX | |
b8578ff7 BC |
1565 | && ((MEM_P (XEXP (note, 0)) |
1566 | && !side_effects_p (SET_SRC (set))) | |
82ce305c | 1567 | || (CONSTANT_P (XEXP (note, 0)) |
cca81ac8 L |
1568 | && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)), |
1569 | XEXP (note, 0)) | |
3db93c89 | 1570 | && REG_N_SETS (REGNO (SET_DEST (set))) == 1)) |
9129a561 VM |
1571 | && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set))) |
1572 | /* LRA does not use equiv with a symbol for PIC code. */ | |
1573 | && (! ira_use_lra_p || ! pic_offset_table_rtx | |
1574 | || ! contains_symbol_ref_p (XEXP (note, 0)))) | |
058e97ec | 1575 | { |
4fb66b23 | 1576 | enum reg_class cl = GENERAL_REGS; |
548a6322 | 1577 | rtx reg = SET_DEST (set); |
ce18efcb | 1578 | int num = COST_INDEX (REGNO (reg)); |
4fb66b23 | 1579 | /* Costs for NO_REGS are used in cost calculation on the |
1580 | 1st pass when the preferred register classes are not | |
1581 | known yet. In this case we take the best scenario when | |
1582 | mode can't be put into GENERAL_REGS. */ | |
1583 | if (!targetm.hard_regno_mode_ok (ira_class_hard_regs[cl][0], | |
1584 | GET_MODE (reg))) | |
1585 | cl = NO_REGS; | |
548a6322 | 1586 | |
ce18efcb | 1587 | COSTS (costs, num)->mem_cost |
548a6322 | 1588 | -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency; |
86fc3d06 UW |
1589 | record_address_regs (GET_MODE (SET_SRC (set)), |
1590 | MEM_ADDR_SPACE (SET_SRC (set)), | |
1591 | XEXP (SET_SRC (set), 0), 0, MEM, SCRATCH, | |
1592 | frequency * 2); | |
82ce305c | 1593 | counted_mem = true; |
058e97ec VM |
1594 | } |
1595 | ||
aa1c5d72 | 1596 | record_operand_costs (insn, pref); |
058e97ec | 1597 | |
2639f9d2 VM |
1598 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) |
1599 | { | |
1600 | const char *p; | |
1601 | fprintf (ira_dump_file, " Final costs after insn %u", INSN_UID (insn)); | |
1602 | if (INSN_CODE (insn) >= 0 | |
1603 | && (p = get_insn_name (INSN_CODE (insn))) != NULL) | |
1604 | fprintf (ira_dump_file, " {%s}", p); | |
1605 | fprintf (ira_dump_file, " (freq=%d)\n", | |
1606 | REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn))); | |
1607 | dump_insn_slim (ira_dump_file, insn); | |
1608 | } | |
1609 | ||
058e97ec VM |
1610 | /* Now add the cost for each operand to the total costs for its |
1611 | allocno. */ | |
1612 | for (i = 0; i < recog_data.n_operands; i++) | |
6d078c9a VM |
1613 | { |
1614 | rtx op = recog_data.operand[i]; | |
2639f9d2 | 1615 | |
6d078c9a VM |
1616 | if (GET_CODE (op) == SUBREG) |
1617 | op = SUBREG_REG (op); | |
1618 | if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
1619 | { | |
1620 | int regno = REGNO (op); | |
1621 | struct costs *p = COSTS (costs, COST_INDEX (regno)); | |
1622 | struct costs *q = op_costs[i]; | |
1623 | int *p_costs = p->cost, *q_costs = q->cost; | |
1624 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; | |
2639f9d2 VM |
1625 | int add_cost = 0; |
1626 | ||
6d078c9a VM |
1627 | /* If the already accounted for the memory "cost" above, don't |
1628 | do so again. */ | |
1629 | if (!counted_mem) | |
1630 | { | |
1631 | add_cost = q->mem_cost; | |
1632 | if (add_cost > 0 && INT_MAX - add_cost < p->mem_cost) | |
1633 | p->mem_cost = INT_MAX; | |
1634 | else | |
1635 | p->mem_cost += add_cost; | |
1636 | } | |
2639f9d2 VM |
1637 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) |
1638 | { | |
1639 | fprintf (ira_dump_file, " op %d(r=%u) MEM:%d(+%d)", | |
1640 | i, REGNO(op), p->mem_cost, add_cost); | |
1641 | } | |
6d078c9a VM |
1642 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) |
1643 | { | |
1644 | add_cost = q_costs[k]; | |
1645 | if (add_cost > 0 && INT_MAX - add_cost < p_costs[k]) | |
1646 | p_costs[k] = INT_MAX; | |
1647 | else | |
1648 | p_costs[k] += add_cost; | |
2639f9d2 VM |
1649 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) |
1650 | { | |
1651 | fprintf (ira_dump_file, " %s:%d(+%d)", | |
1652 | reg_class_names[cost_classes_ptr->classes[k]], | |
1653 | p_costs[k], add_cost); | |
1654 | } | |
6d078c9a | 1655 | } |
2639f9d2 VM |
1656 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) |
1657 | fprintf (ira_dump_file, "\n"); | |
6d078c9a VM |
1658 | } |
1659 | } | |
058e97ec VM |
1660 | return insn; |
1661 | } | |
1662 | ||
1663 | \f | |
1664 | ||
95f61de9 | 1665 | /* Print allocnos costs to the dump file. */ |
058e97ec | 1666 | static void |
95f61de9 | 1667 | print_allocno_costs (void) |
058e97ec VM |
1668 | { |
1669 | int k; | |
1670 | ira_allocno_t a; | |
1671 | ira_allocno_iterator ai; | |
1672 | ||
ce18efcb | 1673 | ira_assert (allocno_p); |
95f61de9 | 1674 | fprintf (ira_dump_file, "\n"); |
058e97ec VM |
1675 | FOR_EACH_ALLOCNO (a, ai) |
1676 | { | |
1677 | int i, rclass; | |
1678 | basic_block bb; | |
1679 | int regno = ALLOCNO_REGNO (a); | |
1756cb66 VM |
1680 | cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; |
1681 | enum reg_class *cost_classes = cost_classes_ptr->classes; | |
058e97ec VM |
1682 | |
1683 | i = ALLOCNO_NUM (a); | |
95f61de9 | 1684 | fprintf (ira_dump_file, " a%d(r%d,", i, regno); |
058e97ec | 1685 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) |
95f61de9 | 1686 | fprintf (ira_dump_file, "b%d", bb->index); |
058e97ec | 1687 | else |
95f61de9 VM |
1688 | fprintf (ira_dump_file, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
1689 | fprintf (ira_dump_file, ") costs:"); | |
1756cb66 | 1690 | for (k = 0; k < cost_classes_ptr->num; k++) |
058e97ec VM |
1691 | { |
1692 | rclass = cost_classes[k]; | |
95f61de9 | 1693 | fprintf (ira_dump_file, " %s:%d", reg_class_names[rclass], |
dab67d2c RS |
1694 | COSTS (costs, i)->cost[k]); |
1695 | if (flag_ira_region == IRA_REGION_ALL | |
1696 | || flag_ira_region == IRA_REGION_MIXED) | |
95f61de9 VM |
1697 | fprintf (ira_dump_file, ",%d", |
1698 | COSTS (total_allocno_costs, i)->cost[k]); | |
058e97ec | 1699 | } |
95f61de9 | 1700 | fprintf (ira_dump_file, " MEM:%i", COSTS (costs, i)->mem_cost); |
1756cb66 VM |
1701 | if (flag_ira_region == IRA_REGION_ALL |
1702 | || flag_ira_region == IRA_REGION_MIXED) | |
95f61de9 VM |
1703 | fprintf (ira_dump_file, ",%d", |
1704 | COSTS (total_allocno_costs, i)->mem_cost); | |
1705 | fprintf (ira_dump_file, "\n"); | |
ce18efcb VM |
1706 | } |
1707 | } | |
1708 | ||
95f61de9 | 1709 | /* Print pseudo costs to the dump file. */ |
ce18efcb | 1710 | static void |
95f61de9 | 1711 | print_pseudo_costs (void) |
ce18efcb VM |
1712 | { |
1713 | int regno, k; | |
1714 | int rclass; | |
1756cb66 VM |
1715 | cost_classes_t cost_classes_ptr; |
1716 | enum reg_class *cost_classes; | |
ce18efcb VM |
1717 | |
1718 | ira_assert (! allocno_p); | |
95f61de9 | 1719 | fprintf (ira_dump_file, "\n"); |
ce18efcb VM |
1720 | for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--) |
1721 | { | |
1756cb66 | 1722 | if (REG_N_REFS (regno) <= 0) |
ce18efcb | 1723 | continue; |
1756cb66 VM |
1724 | cost_classes_ptr = regno_cost_classes[regno]; |
1725 | cost_classes = cost_classes_ptr->classes; | |
95f61de9 | 1726 | fprintf (ira_dump_file, " r%d costs:", regno); |
1756cb66 | 1727 | for (k = 0; k < cost_classes_ptr->num; k++) |
ce18efcb VM |
1728 | { |
1729 | rclass = cost_classes[k]; | |
95f61de9 | 1730 | fprintf (ira_dump_file, " %s:%d", reg_class_names[rclass], |
dab67d2c | 1731 | COSTS (costs, regno)->cost[k]); |
ce18efcb | 1732 | } |
95f61de9 | 1733 | fprintf (ira_dump_file, " MEM:%i\n", COSTS (costs, regno)->mem_cost); |
058e97ec VM |
1734 | } |
1735 | } | |
1736 | ||
1737 | /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno | |
1738 | costs. */ | |
1739 | static void | |
ce18efcb | 1740 | process_bb_for_costs (basic_block bb) |
058e97ec | 1741 | { |
070a1983 | 1742 | rtx_insn *insn; |
058e97ec | 1743 | |
058e97ec VM |
1744 | frequency = REG_FREQ_FROM_BB (bb); |
1745 | if (frequency == 0) | |
1746 | frequency = 1; | |
1747 | FOR_BB_INSNS (bb, insn) | |
1748 | insn = scan_one_insn (insn); | |
1749 | } | |
1750 | ||
ce18efcb VM |
1751 | /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
1752 | costs. */ | |
058e97ec | 1753 | static void |
ce18efcb | 1754 | process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node) |
058e97ec | 1755 | { |
ce18efcb VM |
1756 | basic_block bb; |
1757 | ||
1758 | bb = loop_tree_node->bb; | |
1759 | if (bb != NULL) | |
1760 | process_bb_for_costs (bb); | |
1761 | } | |
1762 | ||
df66fa08 VM |
1763 | /* Return true if all autoinc rtx in X change only a register and memory is |
1764 | valid. */ | |
1765 | static bool | |
1766 | validate_autoinc_and_mem_addr_p (rtx x) | |
1767 | { | |
1768 | enum rtx_code code = GET_CODE (x); | |
1769 | if (GET_RTX_CLASS (code) == RTX_AUTOINC) | |
1770 | return REG_P (XEXP (x, 0)); | |
1771 | const char *fmt = GET_RTX_FORMAT (code); | |
1772 | for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1773 | if (fmt[i] == 'e') | |
1774 | { | |
1775 | if (!validate_autoinc_and_mem_addr_p (XEXP (x, i))) | |
1776 | return false; | |
1777 | } | |
1778 | else if (fmt[i] == 'E') | |
1779 | { | |
1780 | for (int j = 0; j < XVECLEN (x, i); j++) | |
1781 | if (!validate_autoinc_and_mem_addr_p (XVECEXP (x, i, j))) | |
1782 | return false; | |
1783 | } | |
1784 | /* Check memory after checking autoinc to guarantee that autoinc is already | |
1785 | valid for machine-dependent code checking memory address. */ | |
1786 | return (!MEM_P (x) | |
1787 | || memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0), | |
1788 | MEM_ADDR_SPACE (x))); | |
1789 | } | |
1790 | ||
f55cdce3 VM |
1791 | /* Check that reg REGNO can be changed by TO in INSN. Return true in case the |
1792 | result insn would be valid one. */ | |
1793 | static bool | |
1794 | equiv_can_be_consumed_p (int regno, rtx to, rtx_insn *insn) | |
1795 | { | |
1796 | validate_replace_src_group (regno_reg_rtx[regno], to, insn); | |
df66fa08 VM |
1797 | /* We can change register to equivalent memory in autoinc rtl. Some code |
1798 | including verify_changes assumes that autoinc contains only a register. | |
1799 | So check this first. */ | |
1800 | bool res = validate_autoinc_and_mem_addr_p (PATTERN (insn)); | |
1801 | if (res) | |
1802 | res = verify_changes (0); | |
f55cdce3 VM |
1803 | cancel_changes (0); |
1804 | return res; | |
1805 | } | |
1806 | ||
1807 | /* Return true if X contains a pseudo with equivalence. In this case also | |
1808 | return the pseudo through parameter REG. If the pseudo is a part of subreg, | |
1809 | return the subreg through parameter SUBREG. */ | |
1810 | ||
1811 | static bool | |
1812 | get_equiv_regno (rtx x, int ®no, rtx &subreg) | |
1813 | { | |
1814 | subreg = NULL_RTX; | |
1815 | if (GET_CODE (x) == SUBREG) | |
1816 | { | |
1817 | subreg = x; | |
1818 | x = SUBREG_REG (x); | |
1819 | } | |
1820 | if (REG_P (x) | |
1821 | && (ira_reg_equiv[REGNO (x)].memory != NULL | |
8aa47713 | 1822 | || ira_reg_equiv[REGNO (x)].invariant != NULL |
f55cdce3 VM |
1823 | || ira_reg_equiv[REGNO (x)].constant != NULL)) |
1824 | { | |
1825 | regno = REGNO (x); | |
1826 | return true; | |
1827 | } | |
1828 | RTX_CODE code = GET_CODE (x); | |
1829 | const char *fmt = GET_RTX_FORMAT (code); | |
1830 | ||
1831 | for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1832 | if (fmt[i] == 'e') | |
1833 | { | |
1834 | if (get_equiv_regno (XEXP (x, i), regno, subreg)) | |
1835 | return true; | |
1836 | } | |
1837 | else if (fmt[i] == 'E') | |
1838 | { | |
1839 | for (int j = 0; j < XVECLEN (x, i); j++) | |
1840 | if (get_equiv_regno (XVECEXP (x, i, j), regno, subreg)) | |
1841 | return true; | |
1842 | } | |
1843 | return false; | |
1844 | } | |
1845 | ||
1846 | /* A pass through the current function insns. Calculate costs of using | |
1847 | equivalences for pseudos and store them in regno_equiv_gains. */ | |
1848 | ||
1849 | static void | |
1850 | calculate_equiv_gains (void) | |
1851 | { | |
1852 | basic_block bb; | |
1853 | int regno, freq, cost; | |
1854 | rtx subreg; | |
1855 | rtx_insn *insn; | |
1856 | machine_mode mode; | |
1857 | enum reg_class rclass; | |
1858 | bitmap_head equiv_pseudos; | |
1859 | ||
1860 | ira_assert (allocno_p); | |
1861 | bitmap_initialize (&equiv_pseudos, ®_obstack); | |
1862 | for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--) | |
1863 | if (ira_reg_equiv[regno].init_insns != NULL | |
1864 | && (ira_reg_equiv[regno].memory != NULL | |
8aa47713 | 1865 | || ira_reg_equiv[regno].invariant != NULL |
f55cdce3 VM |
1866 | || (ira_reg_equiv[regno].constant != NULL |
1867 | /* Ignore complicated constants which probably will be placed | |
1868 | in memory: */ | |
1869 | && GET_CODE (ira_reg_equiv[regno].constant) != CONST_DOUBLE | |
1870 | && GET_CODE (ira_reg_equiv[regno].constant) != CONST_VECTOR | |
1871 | && GET_CODE (ira_reg_equiv[regno].constant) != LABEL_REF))) | |
1872 | { | |
1873 | rtx_insn_list *x; | |
1874 | for (x = ira_reg_equiv[regno].init_insns; x != NULL; x = x->next ()) | |
1875 | { | |
1876 | insn = x->insn (); | |
1877 | rtx set = single_set (insn); | |
1878 | ||
1879 | if (set == NULL_RTX || SET_DEST (set) != regno_reg_rtx[regno]) | |
1880 | break; | |
1881 | bb = BLOCK_FOR_INSN (insn); | |
1882 | ira_curr_regno_allocno_map | |
1883 | = ira_bb_nodes[bb->index].parent->regno_allocno_map; | |
1884 | mode = PSEUDO_REGNO_MODE (regno); | |
1885 | rclass = pref[COST_INDEX (regno)]; | |
1886 | ira_init_register_move_cost_if_necessary (mode); | |
1887 | if (ira_reg_equiv[regno].memory != NULL) | |
1888 | cost = ira_memory_move_cost[mode][rclass][1]; | |
1889 | else | |
1890 | cost = ira_register_move_cost[mode][rclass][rclass]; | |
1891 | freq = REG_FREQ_FROM_BB (bb); | |
1892 | regno_equiv_gains[regno] += cost * freq; | |
1893 | } | |
1894 | if (x != NULL) | |
1895 | /* We found complicated equiv or reverse equiv mem=reg. Ignore | |
1896 | them. */ | |
1897 | regno_equiv_gains[regno] = 0; | |
1898 | else | |
1899 | bitmap_set_bit (&equiv_pseudos, regno); | |
1900 | } | |
1901 | ||
1902 | FOR_EACH_BB_FN (bb, cfun) | |
1903 | { | |
1904 | freq = REG_FREQ_FROM_BB (bb); | |
1905 | ira_curr_regno_allocno_map | |
1906 | = ira_bb_nodes[bb->index].parent->regno_allocno_map; | |
1907 | FOR_BB_INSNS (bb, insn) | |
1908 | { | |
4d3d2cdb VM |
1909 | if (!NONDEBUG_INSN_P (insn) |
1910 | || !get_equiv_regno (PATTERN (insn), regno, subreg) | |
f55cdce3 VM |
1911 | || !bitmap_bit_p (&equiv_pseudos, regno)) |
1912 | continue; | |
1913 | rtx subst = ira_reg_equiv[regno].memory; | |
1914 | ||
1915 | if (subst == NULL) | |
1916 | subst = ira_reg_equiv[regno].constant; | |
8aa47713 VM |
1917 | if (subst == NULL) |
1918 | subst = ira_reg_equiv[regno].invariant; | |
f55cdce3 VM |
1919 | ira_assert (subst != NULL); |
1920 | mode = PSEUDO_REGNO_MODE (regno); | |
1921 | ira_init_register_move_cost_if_necessary (mode); | |
1922 | bool consumed_p = equiv_can_be_consumed_p (regno, subst, insn); | |
1923 | ||
1924 | rclass = pref[COST_INDEX (regno)]; | |
1925 | if (MEM_P (subst) | |
1926 | /* If it is a change of constant into double for example, the | |
1927 | result constant probably will be placed in memory. */ | |
1928 | || (subreg != NULL_RTX && !INTEGRAL_MODE_P (GET_MODE (subreg)))) | |
1929 | cost = ira_memory_move_cost[mode][rclass][1] + (consumed_p ? 0 : 1); | |
1930 | else if (consumed_p) | |
1931 | continue; | |
1932 | else | |
1933 | cost = ira_register_move_cost[mode][rclass][rclass]; | |
1934 | regno_equiv_gains[regno] -= cost * freq; | |
1935 | } | |
1936 | } | |
1937 | bitmap_clear (&equiv_pseudos); | |
1938 | } | |
1939 | ||
ce18efcb | 1940 | /* Find costs of register classes and memory for allocnos or pseudos |
1756cb66 | 1941 | and their best costs. Set up preferred, alternative and allocno |
ce18efcb VM |
1942 | classes for pseudos. */ |
1943 | static void | |
95f61de9 | 1944 | find_costs_and_classes (void) |
ce18efcb | 1945 | { |
1756cb66 | 1946 | int i, k, start, max_cost_classes_num; |
058e97ec VM |
1947 | int pass; |
1948 | basic_block bb; | |
5074a1f8 | 1949 | enum reg_class *regno_best_class, new_class; |
058e97ec VM |
1950 | |
1951 | init_recog (); | |
1756cb66 VM |
1952 | regno_best_class |
1953 | = (enum reg_class *) ira_allocate (max_reg_num () | |
1954 | * sizeof (enum reg_class)); | |
1955 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1956 | regno_best_class[i] = NO_REGS; | |
1957 | if (!resize_reg_info () && allocno_p | |
1958 | && pseudo_classes_defined_p && flag_expensive_optimizations) | |
ce18efcb VM |
1959 | { |
1960 | ira_allocno_t a; | |
1961 | ira_allocno_iterator ai; | |
b8698a0f | 1962 | |
ce18efcb | 1963 | pref = pref_buffer; |
1756cb66 | 1964 | max_cost_classes_num = 1; |
ce18efcb | 1965 | FOR_EACH_ALLOCNO (a, ai) |
1756cb66 VM |
1966 | { |
1967 | pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a)); | |
1968 | setup_regno_cost_classes_by_aclass | |
1969 | (ALLOCNO_REGNO (a), pref[ALLOCNO_NUM (a)]); | |
1970 | max_cost_classes_num | |
1971 | = MAX (max_cost_classes_num, | |
1972 | regno_cost_classes[ALLOCNO_REGNO (a)]->num); | |
1973 | } | |
1974 | start = 1; | |
1975 | } | |
1976 | else | |
1977 | { | |
1978 | pref = NULL; | |
1979 | max_cost_classes_num = ira_important_classes_num; | |
1980 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
1981 | if (regno_reg_rtx[i] != NULL_RTX) | |
1982 | setup_regno_cost_classes_by_mode (i, PSEUDO_REGNO_MODE (i)); | |
1983 | else | |
1984 | setup_regno_cost_classes_by_aclass (i, ALL_REGS); | |
1985 | start = 0; | |
ce18efcb VM |
1986 | } |
1987 | if (allocno_p) | |
1988 | /* Clear the flag for the next compiled function. */ | |
1989 | pseudo_classes_defined_p = false; | |
058e97ec VM |
1990 | /* Normally we scan the insns once and determine the best class to |
1991 | use for each allocno. However, if -fexpensive-optimizations are | |
1992 | on, we do so twice, the second time using the tentative best | |
1993 | classes to guide the selection. */ | |
ce18efcb | 1994 | for (pass = start; pass <= flag_expensive_optimizations; pass++) |
058e97ec | 1995 | { |
95f61de9 VM |
1996 | if ((!allocno_p || internal_flag_ira_verbose > 0) && ira_dump_file) |
1997 | fprintf (ira_dump_file, | |
ce18efcb | 1998 | "\nPass %i for finding pseudo/allocno costs\n\n", pass); |
1756cb66 VM |
1999 | |
2000 | if (pass != start) | |
058e97ec | 2001 | { |
1756cb66 VM |
2002 | max_cost_classes_num = 1; |
2003 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
2004 | { | |
2005 | setup_regno_cost_classes_by_aclass (i, regno_best_class[i]); | |
2006 | max_cost_classes_num | |
2007 | = MAX (max_cost_classes_num, regno_cost_classes[i]->num); | |
2008 | } | |
058e97ec | 2009 | } |
1756cb66 | 2010 | |
058e97ec | 2011 | struct_costs_size |
1756cb66 | 2012 | = sizeof (struct costs) + sizeof (int) * (max_cost_classes_num - 1); |
058e97ec VM |
2013 | /* Zero out our accumulation of the cost of each class for each |
2014 | allocno. */ | |
ce18efcb | 2015 | memset (costs, 0, cost_elements_num * struct_costs_size); |
058e97ec | 2016 | |
ce18efcb VM |
2017 | if (allocno_p) |
2018 | { | |
2019 | /* Scan the instructions and record each time it would save code | |
2020 | to put a certain allocno in a certain class. */ | |
2021 | ira_traverse_loop_tree (true, ira_loop_tree_root, | |
2022 | process_bb_node_for_costs, NULL); | |
2023 | ||
2024 | memcpy (total_allocno_costs, costs, | |
2025 | max_struct_costs_size * ira_allocnos_num); | |
2026 | } | |
2027 | else | |
2028 | { | |
2029 | basic_block bb; | |
2030 | ||
11cd3bed | 2031 | FOR_EACH_BB_FN (bb, cfun) |
ce18efcb VM |
2032 | process_bb_for_costs (bb); |
2033 | } | |
058e97ec | 2034 | |
058e97ec | 2035 | if (pass == 0) |
ce18efcb | 2036 | pref = pref_buffer; |
058e97ec | 2037 | |
f55cdce3 VM |
2038 | if (ira_use_lra_p && allocno_p && pass == 1) |
2039 | /* It is a pass through all insns. So do it once and only for RA (not | |
2040 | for insn scheduler) when we already found preferable pseudo register | |
2041 | classes on the previous pass. */ | |
2042 | calculate_equiv_gains (); | |
2043 | ||
058e97ec VM |
2044 | /* Now for each allocno look at how desirable each class is and |
2045 | find which class is preferred. */ | |
2046 | for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
2047 | { | |
2048 | ira_allocno_t a, parent_a; | |
1756cb66 | 2049 | int rclass, a_num, parent_a_num, add_cost; |
058e97ec | 2050 | ira_loop_tree_node_t parent; |
61ad6db1 | 2051 | int best_cost, allocno_cost; |
7db7ed3c | 2052 | enum reg_class best, alt_class; |
1756cb66 | 2053 | cost_classes_t cost_classes_ptr = regno_cost_classes[i]; |
0dc7d7cc | 2054 | enum reg_class *cost_classes; |
1756cb66 VM |
2055 | int *i_costs = temp_costs->cost; |
2056 | int i_mem_cost; | |
8ff49c29 | 2057 | int equiv_savings = regno_equiv_gains[i]; |
058e97ec | 2058 | |
ce18efcb | 2059 | if (! allocno_p) |
058e97ec | 2060 | { |
ce18efcb VM |
2061 | if (regno_reg_rtx[i] == NULL_RTX) |
2062 | continue; | |
ce18efcb | 2063 | memcpy (temp_costs, COSTS (costs, i), struct_costs_size); |
1756cb66 | 2064 | i_mem_cost = temp_costs->mem_cost; |
0dc7d7cc | 2065 | cost_classes = cost_classes_ptr->classes; |
ce18efcb VM |
2066 | } |
2067 | else | |
2068 | { | |
2069 | if (ira_regno_allocno_map[i] == NULL) | |
2070 | continue; | |
2071 | memset (temp_costs, 0, struct_costs_size); | |
1756cb66 | 2072 | i_mem_cost = 0; |
0dc7d7cc | 2073 | cost_classes = cost_classes_ptr->classes; |
ce18efcb VM |
2074 | /* Find cost of all allocnos with the same regno. */ |
2075 | for (a = ira_regno_allocno_map[i]; | |
2076 | a != NULL; | |
2077 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
058e97ec | 2078 | { |
1756cb66 | 2079 | int *a_costs, *p_costs; |
eeae9314 | 2080 | |
ce18efcb VM |
2081 | a_num = ALLOCNO_NUM (a); |
2082 | if ((flag_ira_region == IRA_REGION_ALL | |
2083 | || flag_ira_region == IRA_REGION_MIXED) | |
2084 | && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL | |
2085 | && (parent_a = parent->regno_allocno_map[i]) != NULL | |
2086 | /* There are no caps yet. */ | |
2087 | && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE | |
2088 | (a)->border_allocnos, | |
2089 | ALLOCNO_NUM (a))) | |
2090 | { | |
2091 | /* Propagate costs to upper levels in the region | |
2092 | tree. */ | |
2093 | parent_a_num = ALLOCNO_NUM (parent_a); | |
1756cb66 VM |
2094 | a_costs = COSTS (total_allocno_costs, a_num)->cost; |
2095 | p_costs = COSTS (total_allocno_costs, parent_a_num)->cost; | |
2096 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
2097 | { | |
2098 | add_cost = a_costs[k]; | |
2099 | if (add_cost > 0 && INT_MAX - add_cost < p_costs[k]) | |
2100 | p_costs[k] = INT_MAX; | |
2101 | else | |
2102 | p_costs[k] += add_cost; | |
2103 | } | |
2104 | add_cost = COSTS (total_allocno_costs, a_num)->mem_cost; | |
2105 | if (add_cost > 0 | |
2106 | && (INT_MAX - add_cost | |
2107 | < COSTS (total_allocno_costs, | |
2108 | parent_a_num)->mem_cost)) | |
2109 | COSTS (total_allocno_costs, parent_a_num)->mem_cost | |
2110 | = INT_MAX; | |
2111 | else | |
2112 | COSTS (total_allocno_costs, parent_a_num)->mem_cost | |
2113 | += add_cost; | |
2114 | ||
acf41a74 BS |
2115 | if (i >= first_moveable_pseudo && i < last_moveable_pseudo) |
2116 | COSTS (total_allocno_costs, parent_a_num)->mem_cost = 0; | |
ce18efcb | 2117 | } |
1756cb66 VM |
2118 | a_costs = COSTS (costs, a_num)->cost; |
2119 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
2120 | { | |
2121 | add_cost = a_costs[k]; | |
2122 | if (add_cost > 0 && INT_MAX - add_cost < i_costs[k]) | |
2123 | i_costs[k] = INT_MAX; | |
2124 | else | |
2125 | i_costs[k] += add_cost; | |
2126 | } | |
2127 | add_cost = COSTS (costs, a_num)->mem_cost; | |
bddc98e1 | 2128 | if (add_cost > 0 && INT_MAX - add_cost < i_mem_cost) |
1756cb66 VM |
2129 | i_mem_cost = INT_MAX; |
2130 | else | |
2131 | i_mem_cost += add_cost; | |
ce18efcb | 2132 | } |
058e97ec | 2133 | } |
acf41a74 BS |
2134 | if (i >= first_moveable_pseudo && i < last_moveable_pseudo) |
2135 | i_mem_cost = 0; | |
f55cdce3 VM |
2136 | else if (ira_use_lra_p) |
2137 | { | |
2138 | if (equiv_savings > 0) | |
2139 | { | |
2140 | i_mem_cost = 0; | |
2141 | if (ira_dump_file != NULL && internal_flag_ira_verbose > 5) | |
2142 | fprintf (ira_dump_file, | |
2143 | " Use MEM for r%d as the equiv savings is %d\n", | |
2144 | i, equiv_savings); | |
2145 | } | |
2146 | } | |
8552dcd8 VM |
2147 | else if (equiv_savings < 0) |
2148 | i_mem_cost = -equiv_savings; | |
2149 | else if (equiv_savings > 0) | |
2150 | { | |
2151 | i_mem_cost = 0; | |
2152 | for (k = cost_classes_ptr->num - 1; k >= 0; k--) | |
2153 | i_costs[k] += equiv_savings; | |
2154 | } | |
2155 | ||
058e97ec VM |
2156 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; |
2157 | best = ALL_REGS; | |
2158 | alt_class = NO_REGS; | |
2159 | /* Find best common class for all allocnos with the same | |
2160 | regno. */ | |
1756cb66 | 2161 | for (k = 0; k < cost_classes_ptr->num; k++) |
058e97ec VM |
2162 | { |
2163 | rclass = cost_classes[k]; | |
1756cb66 | 2164 | if (i_costs[k] < best_cost) |
058e97ec | 2165 | { |
1756cb66 | 2166 | best_cost = i_costs[k]; |
058e97ec VM |
2167 | best = (enum reg_class) rclass; |
2168 | } | |
1756cb66 VM |
2169 | else if (i_costs[k] == best_cost) |
2170 | best = ira_reg_class_subunion[best][rclass]; | |
058e97ec | 2171 | if (pass == flag_expensive_optimizations |
9d19c732 VM |
2172 | /* We still prefer registers to memory even at this |
2173 | stage if their costs are the same. We will make | |
2174 | a final decision during assigning hard registers | |
2175 | when we have all info including more accurate | |
2176 | costs which might be affected by assigning hard | |
2177 | registers to other pseudos because the pseudos | |
2178 | involved in moves can be coalesced. */ | |
2179 | && i_costs[k] <= i_mem_cost | |
058e97ec VM |
2180 | && (reg_class_size[reg_class_subunion[alt_class][rclass]] |
2181 | > reg_class_size[alt_class])) | |
2182 | alt_class = reg_class_subunion[alt_class][rclass]; | |
2183 | } | |
1756cb66 | 2184 | alt_class = ira_allocno_class_translate[alt_class]; |
b81a2f0d VM |
2185 | if (best_cost > i_mem_cost |
2186 | && ! non_spilled_static_chain_regno_p (i)) | |
1756cb66 | 2187 | regno_aclass[i] = NO_REGS; |
2da068d5 RS |
2188 | else if (!optimize && !targetm.class_likely_spilled_p (best)) |
2189 | /* Registers in the alternative class are likely to need | |
2190 | longer or slower sequences than registers in the best class. | |
2191 | When optimizing we make some effort to use the best class | |
2192 | over the alternative class where possible, but at -O0 we | |
2193 | effectively give the alternative class equal weight. | |
2194 | We then run the risk of using slower alternative registers | |
2195 | when plenty of registers from the best class are still free. | |
2196 | This is especially true because live ranges tend to be very | |
2197 | short in -O0 code and so register pressure tends to be low. | |
2198 | ||
2199 | Avoid that by ignoring the alternative class if the best | |
bc13623e VM |
2200 | class has plenty of registers. |
2201 | ||
2202 | The union class arrays give important classes and only | |
2203 | part of it are allocno classes. So translate them into | |
2204 | allocno classes. */ | |
2205 | regno_aclass[i] = ira_allocno_class_translate[best]; | |
058e97ec | 2206 | else |
1756cb66 VM |
2207 | { |
2208 | /* Make the common class the biggest class of best and | |
bc13623e VM |
2209 | alt_class. Translate the common class into an |
2210 | allocno class too. */ | |
2211 | regno_aclass[i] = (ira_allocno_class_translate | |
2212 | [ira_reg_class_superunion[best][alt_class]]); | |
1756cb66 VM |
2213 | ira_assert (regno_aclass[i] != NO_REGS |
2214 | && ira_reg_allocno_class_p[regno_aclass[i]]); | |
2215 | } | |
8cc87074 VM |
2216 | if (pic_offset_table_rtx != NULL |
2217 | && i == (int) REGNO (pic_offset_table_rtx)) | |
2218 | { | |
2219 | /* For some targets, integer pseudos can be assigned to fp | |
2220 | regs. As we don't want reload pic offset table pseudo, we | |
2221 | should avoid using non-integer regs. */ | |
2222 | regno_aclass[i] | |
2223 | = ira_reg_class_intersect[regno_aclass[i]][GENERAL_REGS]; | |
2224 | alt_class = ira_reg_class_intersect[alt_class][GENERAL_REGS]; | |
2225 | } | |
5074a1f8 VM |
2226 | if ((new_class |
2227 | = (reg_class) (targetm.ira_change_pseudo_allocno_class | |
31e2b5a3 | 2228 | (i, regno_aclass[i], best))) != regno_aclass[i]) |
5074a1f8 VM |
2229 | { |
2230 | regno_aclass[i] = new_class; | |
2231 | if (hard_reg_set_subset_p (reg_class_contents[new_class], | |
2232 | reg_class_contents[best])) | |
2233 | best = new_class; | |
2234 | if (hard_reg_set_subset_p (reg_class_contents[new_class], | |
2235 | reg_class_contents[alt_class])) | |
2236 | alt_class = new_class; | |
2237 | } | |
ce18efcb VM |
2238 | if (pass == flag_expensive_optimizations) |
2239 | { | |
b81a2f0d VM |
2240 | if (best_cost > i_mem_cost |
2241 | /* Do not assign NO_REGS to static chain pointer | |
2242 | pseudo when non-local goto is used. */ | |
2243 | && ! non_spilled_static_chain_regno_p (i)) | |
ce18efcb VM |
2244 | best = alt_class = NO_REGS; |
2245 | else if (best == alt_class) | |
2246 | alt_class = NO_REGS; | |
1756cb66 | 2247 | setup_reg_classes (i, best, alt_class, regno_aclass[i]); |
ce18efcb | 2248 | if ((!allocno_p || internal_flag_ira_verbose > 2) |
95f61de9 VM |
2249 | && ira_dump_file != NULL) |
2250 | fprintf (ira_dump_file, | |
1756cb66 | 2251 | " r%d: preferred %s, alternative %s, allocno %s\n", |
ce18efcb | 2252 | i, reg_class_names[best], reg_class_names[alt_class], |
1756cb66 | 2253 | reg_class_names[regno_aclass[i]]); |
ce18efcb | 2254 | } |
1756cb66 | 2255 | regno_best_class[i] = best; |
ce18efcb VM |
2256 | if (! allocno_p) |
2257 | { | |
b81a2f0d VM |
2258 | pref[i] = (best_cost > i_mem_cost |
2259 | && ! non_spilled_static_chain_regno_p (i) | |
2260 | ? NO_REGS : best); | |
ce18efcb VM |
2261 | continue; |
2262 | } | |
058e97ec VM |
2263 | for (a = ira_regno_allocno_map[i]; |
2264 | a != NULL; | |
2265 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
2266 | { | |
3b6d1699 VM |
2267 | enum reg_class aclass = regno_aclass[i]; |
2268 | int a_num = ALLOCNO_NUM (a); | |
2269 | int *total_a_costs = COSTS (total_allocno_costs, a_num)->cost; | |
2270 | int *a_costs = COSTS (costs, a_num)->cost; | |
eeae9314 | 2271 | |
3b6d1699 | 2272 | if (aclass == NO_REGS) |
058e97ec VM |
2273 | best = NO_REGS; |
2274 | else | |
b8698a0f | 2275 | { |
058e97ec VM |
2276 | /* Finding best class which is subset of the common |
2277 | class. */ | |
2278 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
61ad6db1 | 2279 | allocno_cost = best_cost; |
058e97ec | 2280 | best = ALL_REGS; |
1756cb66 | 2281 | for (k = 0; k < cost_classes_ptr->num; k++) |
058e97ec VM |
2282 | { |
2283 | rclass = cost_classes[k]; | |
3b6d1699 | 2284 | if (! ira_class_subset_p[rclass][aclass]) |
058e97ec | 2285 | continue; |
dab67d2c | 2286 | if (total_a_costs[k] < best_cost) |
058e97ec | 2287 | { |
1756cb66 VM |
2288 | best_cost = total_a_costs[k]; |
2289 | allocno_cost = a_costs[k]; | |
058e97ec VM |
2290 | best = (enum reg_class) rclass; |
2291 | } | |
1756cb66 | 2292 | else if (total_a_costs[k] == best_cost) |
61ad6db1 | 2293 | { |
1756cb66 VM |
2294 | best = ira_reg_class_subunion[best][rclass]; |
2295 | allocno_cost = MAX (allocno_cost, a_costs[k]); | |
61ad6db1 | 2296 | } |
058e97ec | 2297 | } |
1756cb66 | 2298 | ALLOCNO_CLASS_COST (a) = allocno_cost; |
058e97ec | 2299 | } |
95f61de9 | 2300 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL |
ce18efcb | 2301 | && (pass == 0 || pref[a_num] != best)) |
058e97ec | 2302 | { |
95f61de9 | 2303 | fprintf (ira_dump_file, " a%d (r%d,", a_num, i); |
058e97ec | 2304 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) |
95f61de9 | 2305 | fprintf (ira_dump_file, "b%d", bb->index); |
058e97ec | 2306 | else |
95f61de9 | 2307 | fprintf (ira_dump_file, "l%d", |
2608d841 | 2308 | ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
95f61de9 | 2309 | fprintf (ira_dump_file, ") best %s, allocno %s\n", |
058e97ec | 2310 | reg_class_names[best], |
3b6d1699 | 2311 | reg_class_names[aclass]); |
058e97ec | 2312 | } |
ce18efcb | 2313 | pref[a_num] = best; |
3b6d1699 VM |
2314 | if (pass == flag_expensive_optimizations && best != aclass |
2315 | && ira_class_hard_regs_num[best] > 0 | |
2316 | && (ira_reg_class_max_nregs[best][ALLOCNO_MODE (a)] | |
2317 | >= ira_class_hard_regs_num[best])) | |
2318 | { | |
2319 | int ind = cost_classes_ptr->index[aclass]; | |
2320 | ||
2321 | ira_assert (ind >= 0); | |
dc687582 | 2322 | ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a)); |
3b6d1699 VM |
2323 | ira_add_allocno_pref (a, ira_class_hard_regs[best][0], |
2324 | (a_costs[ind] - ALLOCNO_CLASS_COST (a)) | |
2325 | / (ira_register_move_cost | |
2326 | [ALLOCNO_MODE (a)][best][aclass])); | |
2327 | for (k = 0; k < cost_classes_ptr->num; k++) | |
2328 | if (ira_class_subset_p[cost_classes[k]][best]) | |
2329 | a_costs[k] = a_costs[ind]; | |
2330 | } | |
058e97ec VM |
2331 | } |
2332 | } | |
eeae9314 | 2333 | |
95f61de9 | 2334 | if (internal_flag_ira_verbose > 4 && ira_dump_file) |
058e97ec | 2335 | { |
ce18efcb | 2336 | if (allocno_p) |
95f61de9 | 2337 | print_allocno_costs (); |
ce18efcb | 2338 | else |
95f61de9 VM |
2339 | print_pseudo_costs (); |
2340 | fprintf (ira_dump_file,"\n"); | |
058e97ec VM |
2341 | } |
2342 | } | |
1756cb66 | 2343 | ira_free (regno_best_class); |
058e97ec VM |
2344 | } |
2345 | ||
2346 | \f | |
2347 | ||
2348 | /* Process moves involving hard regs to modify allocno hard register | |
1756cb66 | 2349 | costs. We can do this only after determining allocno class. If a |
420ab54b | 2350 | hard register forms a register class, then moves with the hard |
058e97ec VM |
2351 | register are already taken into account in class costs for the |
2352 | allocno. */ | |
2353 | static void | |
2354 | process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node) | |
2355 | { | |
3b6d1699 | 2356 | int i, freq, src_regno, dst_regno, hard_regno, a_regno; |
058e97ec | 2357 | bool to_p; |
3b6d1699 VM |
2358 | ira_allocno_t a, curr_a; |
2359 | ira_loop_tree_node_t curr_loop_tree_node; | |
2360 | enum reg_class rclass; | |
058e97ec | 2361 | basic_block bb; |
070a1983 DM |
2362 | rtx_insn *insn; |
2363 | rtx set, src, dst; | |
058e97ec VM |
2364 | |
2365 | bb = loop_tree_node->bb; | |
2366 | if (bb == NULL) | |
2367 | return; | |
2368 | freq = REG_FREQ_FROM_BB (bb); | |
2369 | if (freq == 0) | |
2370 | freq = 1; | |
2371 | FOR_BB_INSNS (bb, insn) | |
2372 | { | |
b5b8b0ac | 2373 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec VM |
2374 | continue; |
2375 | set = single_set (insn); | |
2376 | if (set == NULL_RTX) | |
2377 | continue; | |
2378 | dst = SET_DEST (set); | |
2379 | src = SET_SRC (set); | |
2380 | if (! REG_P (dst) || ! REG_P (src)) | |
2381 | continue; | |
2382 | dst_regno = REGNO (dst); | |
2383 | src_regno = REGNO (src); | |
2384 | if (dst_regno >= FIRST_PSEUDO_REGISTER | |
2385 | && src_regno < FIRST_PSEUDO_REGISTER) | |
2386 | { | |
2387 | hard_regno = src_regno; | |
058e97ec | 2388 | a = ira_curr_regno_allocno_map[dst_regno]; |
3b6d1699 | 2389 | to_p = true; |
058e97ec VM |
2390 | } |
2391 | else if (src_regno >= FIRST_PSEUDO_REGISTER | |
2392 | && dst_regno < FIRST_PSEUDO_REGISTER) | |
2393 | { | |
2394 | hard_regno = dst_regno; | |
058e97ec | 2395 | a = ira_curr_regno_allocno_map[src_regno]; |
3b6d1699 | 2396 | to_p = false; |
058e97ec VM |
2397 | } |
2398 | else | |
2399 | continue; | |
0d2a576a VM |
2400 | if (reg_class_size[(int) REGNO_REG_CLASS (hard_regno)] |
2401 | == (ira_reg_class_max_nregs | |
2402 | [REGNO_REG_CLASS (hard_regno)][(int) ALLOCNO_MODE(a)])) | |
2403 | /* If the class can provide only one hard reg to the allocno, | |
2404 | we processed the insn record_operand_costs already and we | |
2405 | actually updated the hard reg cost there. */ | |
2406 | continue; | |
1756cb66 | 2407 | rclass = ALLOCNO_CLASS (a); |
058e97ec VM |
2408 | if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno)) |
2409 | continue; | |
2410 | i = ira_class_hard_reg_index[rclass][hard_regno]; | |
2411 | if (i < 0) | |
2412 | continue; | |
3b6d1699 VM |
2413 | a_regno = ALLOCNO_REGNO (a); |
2414 | for (curr_loop_tree_node = ALLOCNO_LOOP_TREE_NODE (a); | |
2415 | curr_loop_tree_node != NULL; | |
2416 | curr_loop_tree_node = curr_loop_tree_node->parent) | |
2417 | if ((curr_a = curr_loop_tree_node->regno_allocno_map[a_regno]) != NULL) | |
2418 | ira_add_allocno_pref (curr_a, hard_regno, freq); | |
2419 | { | |
2420 | int cost; | |
2421 | enum reg_class hard_reg_class; | |
ef4bddc2 | 2422 | machine_mode mode; |
eeae9314 | 2423 | |
3b6d1699 VM |
2424 | mode = ALLOCNO_MODE (a); |
2425 | hard_reg_class = REGNO_REG_CLASS (hard_regno); | |
2426 | ira_init_register_move_cost_if_necessary (mode); | |
2427 | cost = (to_p ? ira_register_move_cost[mode][hard_reg_class][rclass] | |
2428 | : ira_register_move_cost[mode][rclass][hard_reg_class]) * freq; | |
2429 | ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass, | |
2430 | ALLOCNO_CLASS_COST (a)); | |
2431 | ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a), | |
2432 | rclass, 0); | |
2433 | ALLOCNO_HARD_REG_COSTS (a)[i] -= cost; | |
2434 | ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost; | |
2435 | ALLOCNO_CLASS_COST (a) = MIN (ALLOCNO_CLASS_COST (a), | |
2436 | ALLOCNO_HARD_REG_COSTS (a)[i]); | |
2437 | } | |
058e97ec VM |
2438 | } |
2439 | } | |
2440 | ||
2441 | /* After we find hard register and memory costs for allocnos, define | |
1756cb66 | 2442 | its class and modify hard register cost because insns moving |
058e97ec VM |
2443 | allocno to/from hard registers. */ |
2444 | static void | |
1756cb66 | 2445 | setup_allocno_class_and_costs (void) |
058e97ec | 2446 | { |
1756cb66 | 2447 | int i, j, n, regno, hard_regno, num; |
058e97ec | 2448 | int *reg_costs; |
1756cb66 | 2449 | enum reg_class aclass, rclass; |
058e97ec VM |
2450 | ira_allocno_t a; |
2451 | ira_allocno_iterator ai; | |
1756cb66 | 2452 | cost_classes_t cost_classes_ptr; |
058e97ec | 2453 | |
ce18efcb | 2454 | ira_assert (allocno_p); |
058e97ec VM |
2455 | FOR_EACH_ALLOCNO (a, ai) |
2456 | { | |
2457 | i = ALLOCNO_NUM (a); | |
1756cb66 VM |
2458 | regno = ALLOCNO_REGNO (a); |
2459 | aclass = regno_aclass[regno]; | |
2460 | cost_classes_ptr = regno_cost_classes[regno]; | |
2461 | ira_assert (pref[i] == NO_REGS || aclass != NO_REGS); | |
ce18efcb | 2462 | ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost; |
1756cb66 VM |
2463 | ira_set_allocno_class (a, aclass); |
2464 | if (aclass == NO_REGS) | |
058e97ec | 2465 | continue; |
1756cb66 | 2466 | if (optimize && ALLOCNO_CLASS (a) != pref[i]) |
058e97ec | 2467 | { |
1756cb66 | 2468 | n = ira_class_hard_regs_num[aclass]; |
058e97ec | 2469 | ALLOCNO_HARD_REG_COSTS (a) |
1756cb66 | 2470 | = reg_costs = ira_allocate_cost_vector (aclass); |
058e97ec VM |
2471 | for (j = n - 1; j >= 0; j--) |
2472 | { | |
1756cb66 VM |
2473 | hard_regno = ira_class_hard_regs[aclass][j]; |
2474 | if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], hard_regno)) | |
2475 | reg_costs[j] = ALLOCNO_CLASS_COST (a); | |
61ad6db1 | 2476 | else |
c0683a82 | 2477 | { |
1756cb66 VM |
2478 | rclass = REGNO_REG_CLASS (hard_regno); |
2479 | num = cost_classes_ptr->index[rclass]; | |
61ad6db1 RS |
2480 | if (num < 0) |
2481 | { | |
1756cb66 VM |
2482 | num = cost_classes_ptr->hard_regno_index[hard_regno]; |
2483 | ira_assert (num >= 0); | |
61ad6db1 | 2484 | } |
ce18efcb | 2485 | reg_costs[j] = COSTS (costs, i)->cost[num]; |
c0683a82 | 2486 | } |
058e97ec VM |
2487 | } |
2488 | } | |
2489 | } | |
2490 | if (optimize) | |
2491 | ira_traverse_loop_tree (true, ira_loop_tree_root, | |
2492 | process_bb_node_for_hard_reg_moves, NULL); | |
2493 | } | |
2494 | ||
2495 | \f | |
2496 | ||
2497 | /* Function called once during compiler work. */ | |
2498 | void | |
2499 | ira_init_costs_once (void) | |
2500 | { | |
2501 | int i; | |
2502 | ||
2503 | init_cost = NULL; | |
2504 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
2505 | { | |
2506 | op_costs[i] = NULL; | |
2507 | this_op_costs[i] = NULL; | |
2508 | } | |
2509 | temp_costs = NULL; | |
058e97ec VM |
2510 | } |
2511 | ||
2512 | /* Free allocated temporary cost vectors. */ | |
19c708dc RS |
2513 | void |
2514 | target_ira_int::free_ira_costs () | |
058e97ec VM |
2515 | { |
2516 | int i; | |
2517 | ||
19c708dc RS |
2518 | free (x_init_cost); |
2519 | x_init_cost = NULL; | |
058e97ec VM |
2520 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) |
2521 | { | |
19c708dc RS |
2522 | free (x_op_costs[i]); |
2523 | free (x_this_op_costs[i]); | |
2524 | x_op_costs[i] = x_this_op_costs[i] = NULL; | |
058e97ec | 2525 | } |
19c708dc RS |
2526 | free (x_temp_costs); |
2527 | x_temp_costs = NULL; | |
058e97ec VM |
2528 | } |
2529 | ||
2530 | /* This is called each time register related information is | |
2531 | changed. */ | |
2532 | void | |
2533 | ira_init_costs (void) | |
2534 | { | |
2535 | int i; | |
2536 | ||
19c708dc | 2537 | this_target_ira_int->free_ira_costs (); |
058e97ec VM |
2538 | max_struct_costs_size |
2539 | = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1); | |
1756cb66 VM |
2540 | /* Don't use ira_allocate because vectors live through several IRA |
2541 | calls. */ | |
058e97ec VM |
2542 | init_cost = (struct costs *) xmalloc (max_struct_costs_size); |
2543 | init_cost->mem_cost = 1000000; | |
2544 | for (i = 0; i < ira_important_classes_num; i++) | |
2545 | init_cost->cost[i] = 1000000; | |
2546 | for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
2547 | { | |
2548 | op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
2549 | this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
2550 | } | |
2551 | temp_costs = (struct costs *) xmalloc (max_struct_costs_size); | |
058e97ec VM |
2552 | } |
2553 | ||
058e97ec VM |
2554 | \f |
2555 | ||
ce18efcb VM |
2556 | /* Common initialization function for ira_costs and |
2557 | ira_set_pseudo_classes. */ | |
2558 | static void | |
2559 | init_costs (void) | |
2560 | { | |
1833192f | 2561 | init_subregs_of_mode (); |
ce18efcb VM |
2562 | costs = (struct costs *) ira_allocate (max_struct_costs_size |
2563 | * cost_elements_num); | |
1756cb66 VM |
2564 | pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
2565 | * cost_elements_num); | |
2566 | regno_aclass = (enum reg_class *) ira_allocate (sizeof (enum reg_class) | |
2567 | * max_reg_num ()); | |
8ff49c29 BS |
2568 | regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); |
2569 | memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); | |
ce18efcb VM |
2570 | } |
2571 | ||
2572 | /* Common finalization function for ira_costs and | |
2573 | ira_set_pseudo_classes. */ | |
2574 | static void | |
2575 | finish_costs (void) | |
2576 | { | |
fa1fabcb | 2577 | finish_subregs_of_mode (); |
8ff49c29 | 2578 | ira_free (regno_equiv_gains); |
1756cb66 | 2579 | ira_free (regno_aclass); |
ce18efcb VM |
2580 | ira_free (pref_buffer); |
2581 | ira_free (costs); | |
2582 | } | |
2583 | ||
1756cb66 VM |
2584 | /* Entry function which defines register class, memory and hard |
2585 | register costs for each allocno. */ | |
058e97ec VM |
2586 | void |
2587 | ira_costs (void) | |
2588 | { | |
ce18efcb VM |
2589 | allocno_p = true; |
2590 | cost_elements_num = ira_allocnos_num; | |
2591 | init_costs (); | |
2592 | total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size | |
2593 | * ira_allocnos_num); | |
1756cb66 | 2594 | initiate_regno_cost_classes (); |
f55cdce3 VM |
2595 | if (!ira_use_lra_p) |
2596 | /* Process equivs in reload to update costs through hook | |
2597 | ira_adjust_equiv_reg_cost. */ | |
2598 | calculate_elim_costs_all_insns (); | |
95f61de9 | 2599 | find_costs_and_classes (); |
1756cb66 VM |
2600 | setup_allocno_class_and_costs (); |
2601 | finish_regno_cost_classes (); | |
ce18efcb VM |
2602 | finish_costs (); |
2603 | ira_free (total_allocno_costs); | |
2604 | } | |
2605 | ||
b11f0116 BC |
2606 | /* Entry function which defines classes for pseudos. |
2607 | Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */ | |
ce18efcb | 2608 | void |
b11f0116 | 2609 | ira_set_pseudo_classes (bool define_pseudo_classes, FILE *dump_file) |
ce18efcb | 2610 | { |
95f61de9 | 2611 | FILE *saved_file = ira_dump_file; |
ce18efcb VM |
2612 | allocno_p = false; |
2613 | internal_flag_ira_verbose = flag_ira_verbose; | |
95f61de9 | 2614 | ira_dump_file = dump_file; |
ce18efcb VM |
2615 | cost_elements_num = max_reg_num (); |
2616 | init_costs (); | |
1756cb66 | 2617 | initiate_regno_cost_classes (); |
95f61de9 | 2618 | find_costs_and_classes (); |
1756cb66 | 2619 | finish_regno_cost_classes (); |
b11f0116 BC |
2620 | if (define_pseudo_classes) |
2621 | pseudo_classes_defined_p = true; | |
2622 | ||
ce18efcb | 2623 | finish_costs (); |
95f61de9 | 2624 | ira_dump_file = saved_file; |
058e97ec VM |
2625 | } |
2626 | ||
2627 | \f | |
2628 | ||
2629 | /* Change hard register costs for allocnos which lives through | |
2630 | function calls. This is called only when we found all intersected | |
2631 | calls during building allocno live ranges. */ | |
2632 | void | |
1756cb66 | 2633 | ira_tune_allocno_costs (void) |
058e97ec VM |
2634 | { |
2635 | int j, n, regno; | |
2636 | int cost, min_cost, *reg_costs; | |
01f3e6a4 | 2637 | enum reg_class aclass; |
ef4bddc2 | 2638 | machine_mode mode; |
058e97ec VM |
2639 | ira_allocno_t a; |
2640 | ira_allocno_iterator ai; | |
1756cb66 VM |
2641 | ira_allocno_object_iterator oi; |
2642 | ira_object_t obj; | |
2643 | bool skip_p; | |
058e97ec VM |
2644 | |
2645 | FOR_EACH_ALLOCNO (a, ai) | |
2646 | { | |
1756cb66 VM |
2647 | aclass = ALLOCNO_CLASS (a); |
2648 | if (aclass == NO_REGS) | |
058e97ec VM |
2649 | continue; |
2650 | mode = ALLOCNO_MODE (a); | |
1756cb66 | 2651 | n = ira_class_hard_regs_num[aclass]; |
058e97ec | 2652 | min_cost = INT_MAX; |
e384e6b5 BS |
2653 | if (ALLOCNO_CALLS_CROSSED_NUM (a) |
2654 | != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
058e97ec VM |
2655 | { |
2656 | ira_allocate_and_set_costs | |
1756cb66 VM |
2657 | (&ALLOCNO_HARD_REG_COSTS (a), aclass, |
2658 | ALLOCNO_CLASS_COST (a)); | |
058e97ec VM |
2659 | reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
2660 | for (j = n - 1; j >= 0; j--) | |
2661 | { | |
1756cb66 VM |
2662 | regno = ira_class_hard_regs[aclass][j]; |
2663 | skip_p = false; | |
2664 | FOR_EACH_ALLOCNO_OBJECT (a, obj, oi) | |
2665 | { | |
9181a6e5 VM |
2666 | if (ira_hard_reg_set_intersection_p (regno, mode, |
2667 | OBJECT_CONFLICT_HARD_REGS | |
2668 | (obj))) | |
1756cb66 VM |
2669 | { |
2670 | skip_p = true; | |
2671 | break; | |
2672 | } | |
2673 | } | |
2674 | if (skip_p) | |
2675 | continue; | |
058e97ec | 2676 | cost = 0; |
6c476222 | 2677 | if (ira_need_caller_save_p (a, regno)) |
01f3e6a4 | 2678 | cost += ira_caller_save_cost (a); |
058e97ec | 2679 | #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER |
a923fa6d RS |
2680 | { |
2681 | auto rclass = REGNO_REG_CLASS (regno); | |
2682 | cost += ((ira_memory_move_cost[mode][rclass][0] | |
2683 | + ira_memory_move_cost[mode][rclass][1]) | |
2684 | * ALLOCNO_FREQ (a) | |
2685 | * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2); | |
2686 | } | |
058e97ec | 2687 | #endif |
1756cb66 VM |
2688 | if (INT_MAX - cost < reg_costs[j]) |
2689 | reg_costs[j] = INT_MAX; | |
2690 | else | |
2691 | reg_costs[j] += cost; | |
058e97ec VM |
2692 | if (min_cost > reg_costs[j]) |
2693 | min_cost = reg_costs[j]; | |
2694 | } | |
2695 | } | |
2696 | if (min_cost != INT_MAX) | |
1756cb66 | 2697 | ALLOCNO_CLASS_COST (a) = min_cost; |
0583835c | 2698 | |
8908df28 EB |
2699 | /* Some targets allow pseudos to be allocated to unaligned sequences |
2700 | of hard registers. However, selecting an unaligned sequence can | |
2701 | unnecessarily restrict later allocations. So increase the cost of | |
2702 | unaligned hard regs to encourage the use of aligned hard regs. */ | |
0583835c | 2703 | { |
1756cb66 | 2704 | const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)]; |
0583835c | 2705 | |
8908df28 | 2706 | if (nregs > 1) |
0583835c VM |
2707 | { |
2708 | ira_allocate_and_set_costs | |
1756cb66 | 2709 | (&ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a)); |
0583835c VM |
2710 | reg_costs = ALLOCNO_HARD_REG_COSTS (a); |
2711 | for (j = n - 1; j >= 0; j--) | |
2712 | { | |
1756cb66 | 2713 | regno = ira_non_ordered_class_hard_regs[aclass][j]; |
8908df28 | 2714 | if ((regno % nregs) != 0) |
0583835c | 2715 | { |
1756cb66 | 2716 | int index = ira_class_hard_reg_index[aclass][regno]; |
c6d0f11a | 2717 | ira_assert (index != -1); |
0583835c VM |
2718 | reg_costs[index] += ALLOCNO_FREQ (a); |
2719 | } | |
2720 | } | |
2721 | } | |
2722 | } | |
058e97ec VM |
2723 | } |
2724 | } | |
8ff49c29 | 2725 | |
f55cdce3 VM |
2726 | /* A hook from the reload pass. Add COST to the estimated gain for eliminating |
2727 | REGNO with its equivalence. If COST is zero, record that no such | |
2728 | elimination is possible. */ | |
8ff49c29 BS |
2729 | |
2730 | void | |
2731 | ira_adjust_equiv_reg_cost (unsigned regno, int cost) | |
2732 | { | |
f55cdce3 | 2733 | ira_assert (!ira_use_lra_p); |
8ff49c29 BS |
2734 | if (cost == 0) |
2735 | regno_equiv_gains[regno] = 0; | |
2736 | else | |
2737 | regno_equiv_gains[regno] += cost; | |
2738 | } | |
eec42458 DM |
2739 | |
2740 | void | |
d5148d4f | 2741 | ira_costs_cc_finalize (void) |
eec42458 DM |
2742 | { |
2743 | this_target_ira_int->free_ira_costs (); | |
2744 | } |