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058e97ec | 1 | /* Integrated Register Allocator (IRA) intercommunication header file. |
a945c346 | 2 | Copyright (C) 2006-2024 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
f1717f8d KC |
21 | #ifndef GCC_IRA_INT_H |
22 | #define GCC_IRA_INT_H | |
23 | ||
68c6cacb | 24 | #include "recog.h" |
6c476222 | 25 | #include "function-abi.h" |
68c6cacb | 26 | |
058e97ec VM |
27 | /* To provide consistency in naming, all IRA external variables, |
28 | functions, common typedefs start with prefix ira_. */ | |
29 | ||
b2b29377 | 30 | #if CHECKING_P |
058e97ec VM |
31 | #define ENABLE_IRA_CHECKING |
32 | #endif | |
33 | ||
34 | #ifdef ENABLE_IRA_CHECKING | |
35 | #define ira_assert(c) gcc_assert (c) | |
36 | #else | |
f7556aae | 37 | /* Always define and include C, so that warnings for empty body in an |
7b3b6ae4 | 38 | 'if' statement and unused variable do not occur. */ |
f7556aae | 39 | #define ira_assert(c) ((void)(0 && (c))) |
058e97ec VM |
40 | #endif |
41 | ||
42 | /* Compute register frequency from edge frequency FREQ. It is | |
43 | analogous to REG_FREQ_FROM_BB. When optimizing for size, or | |
44 | profile driven feedback is available and the function is never | |
45 | executed, frequency is always equivalent. Otherwise rescale the | |
46 | edge frequency. */ | |
cf40f973 DC |
47 | #define REG_FREQ_FROM_EDGE_FREQ(freq) \ |
48 | (optimize_function_for_size_p (cfun) \ | |
fefa31b5 | 49 | ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \ |
058e97ec VM |
50 | ? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1) |
51 | ||
058e97ec VM |
52 | /* A modified value of flag `-fira-verbose' used internally. */ |
53 | extern int internal_flag_ira_verbose; | |
54 | ||
55 | /* Dump file of the allocator if it is not NULL. */ | |
56 | extern FILE *ira_dump_file; | |
57 | ||
58 | /* Typedefs for pointers to allocno live range, allocno, and copy of | |
59 | allocnos. */ | |
b14151b5 | 60 | typedef struct live_range *live_range_t; |
058e97ec | 61 | typedef struct ira_allocno *ira_allocno_t; |
3b6d1699 | 62 | typedef struct ira_allocno_pref *ira_pref_t; |
058e97ec | 63 | typedef struct ira_allocno_copy *ira_copy_t; |
a49ae217 | 64 | typedef struct ira_object *ira_object_t; |
058e97ec VM |
65 | |
66 | /* Definition of vector of allocnos and copies. */ | |
058e97ec VM |
67 | |
68 | /* Typedef for pointer to the subsequent structure. */ | |
69 | typedef struct ira_loop_tree_node *ira_loop_tree_node_t; | |
70 | ||
e80ccebc RS |
71 | typedef unsigned short move_table[N_REG_CLASSES]; |
72 | ||
058e97ec VM |
73 | /* In general case, IRA is a regional allocator. The regions are |
74 | nested and form a tree. Currently regions are natural loops. The | |
75 | following structure describes loop tree node (representing basic | |
76 | block or loop). We need such tree because the loop tree from | |
77 | cfgloop.h is not convenient for the optimization: basic blocks are | |
78 | not a part of the tree from cfgloop.h. We also use the nodes for | |
79 | storing additional information about basic blocks/loops for the | |
80 | register allocation purposes. */ | |
81 | struct ira_loop_tree_node | |
82 | { | |
83 | /* The node represents basic block if children == NULL. */ | |
84 | basic_block bb; /* NULL for loop. */ | |
2608d841 | 85 | /* NULL for BB or for loop tree root if we did not build CFG loop tree. */ |
99b1c316 | 86 | class loop *loop; |
af51c885 AN |
87 | /* NEXT/SUBLOOP_NEXT is the next node/loop-node of the same parent. |
88 | SUBLOOP_NEXT is always NULL for BBs. */ | |
058e97ec | 89 | ira_loop_tree_node_t subloop_next, next; |
af51c885 AN |
90 | /* CHILDREN/SUBLOOPS is the first node/loop-node immediately inside |
91 | the node. They are NULL for BBs. */ | |
058e97ec VM |
92 | ira_loop_tree_node_t subloops, children; |
93 | /* The node immediately containing given node. */ | |
94 | ira_loop_tree_node_t parent; | |
95 | ||
96 | /* Loop level in range [0, ira_loop_tree_height). */ | |
97 | int level; | |
98 | ||
99 | /* All the following members are defined only for nodes representing | |
100 | loops. */ | |
101 | ||
2608d841 VM |
102 | /* The loop number from CFG loop tree. The root number is 0. */ |
103 | int loop_num; | |
104 | ||
30ea859e VM |
105 | /* True if the loop was marked for removal from the register |
106 | allocation. */ | |
107 | bool to_remove_p; | |
108 | ||
058e97ec VM |
109 | /* Allocnos in the loop corresponding to their regnos. If it is |
110 | NULL the loop does not form a separate register allocation region | |
67914693 | 111 | (e.g. because it has abnormal enter/exit edges and we cannot put |
058e97ec VM |
112 | code for register shuffling on the edges if a different |
113 | allocation is used for a pseudo-register on different sides of | |
114 | the edges). Caps are not in the map (remember we can have more | |
115 | one cap with the same regno in a region). */ | |
116 | ira_allocno_t *regno_allocno_map; | |
117 | ||
ea1c67e6 VM |
118 | /* True if there is an entry to given loop not from its parent (or |
119 | grandparent) basic block. For example, it is possible for two | |
120 | adjacent loops inside another loop. */ | |
121 | bool entered_from_non_parent_p; | |
122 | ||
058e97ec | 123 | /* Maximal register pressure inside loop for given register class |
1756cb66 | 124 | (defined only for the pressure classes). */ |
058e97ec VM |
125 | int reg_pressure[N_REG_CLASSES]; |
126 | ||
49d988e7 VM |
127 | /* Numbers of allocnos referred or living in the loop node (except |
128 | for its subloops). */ | |
129 | bitmap all_allocnos; | |
130 | ||
131 | /* Numbers of allocnos living at the loop borders. */ | |
132 | bitmap border_allocnos; | |
058e97ec VM |
133 | |
134 | /* Regnos of pseudos modified in the loop node (including its | |
135 | subloops). */ | |
136 | bitmap modified_regnos; | |
137 | ||
058e97ec VM |
138 | /* Numbers of copies referred in the corresponding loop. */ |
139 | bitmap local_copies; | |
140 | }; | |
141 | ||
142 | /* The root of the loop tree corresponding to the all function. */ | |
143 | extern ira_loop_tree_node_t ira_loop_tree_root; | |
144 | ||
145 | /* Height of the loop tree. */ | |
146 | extern int ira_loop_tree_height; | |
147 | ||
148 | /* All nodes representing basic blocks are referred through the | |
67914693 | 149 | following array. We cannot use basic block member `aux' for this |
058e97ec VM |
150 | because it is used for insertion of insns on edges. */ |
151 | extern ira_loop_tree_node_t ira_bb_nodes; | |
152 | ||
153 | /* Two access macros to the nodes representing basic blocks. */ | |
154 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
155 | #define IRA_BB_NODE_BY_INDEX(index) __extension__ \ | |
2608d841 | 156 | (({ ira_loop_tree_node_t _node = (&ira_bb_nodes[index]); \ |
058e97ec VM |
157 | if (_node->children != NULL || _node->loop != NULL || _node->bb == NULL)\ |
158 | { \ | |
159 | fprintf (stderr, \ | |
160 | "\n%s: %d: error in %s: it is not a block node\n", \ | |
161 | __FILE__, __LINE__, __FUNCTION__); \ | |
162 | gcc_unreachable (); \ | |
163 | } \ | |
164 | _node; })) | |
165 | #else | |
166 | #define IRA_BB_NODE_BY_INDEX(index) (&ira_bb_nodes[index]) | |
167 | #endif | |
168 | ||
169 | #define IRA_BB_NODE(bb) IRA_BB_NODE_BY_INDEX ((bb)->index) | |
170 | ||
171 | /* All nodes representing loops are referred through the following | |
172 | array. */ | |
173 | extern ira_loop_tree_node_t ira_loop_nodes; | |
174 | ||
175 | /* Two access macros to the nodes representing loops. */ | |
176 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
177 | #define IRA_LOOP_NODE_BY_INDEX(index) __extension__ \ | |
2608d841 VM |
178 | (({ ira_loop_tree_node_t const _node = (&ira_loop_nodes[index]); \ |
179 | if (_node->children == NULL || _node->bb != NULL \ | |
180 | || (_node->loop == NULL && current_loops != NULL)) \ | |
058e97ec VM |
181 | { \ |
182 | fprintf (stderr, \ | |
183 | "\n%s: %d: error in %s: it is not a loop node\n", \ | |
184 | __FILE__, __LINE__, __FUNCTION__); \ | |
185 | gcc_unreachable (); \ | |
186 | } \ | |
187 | _node; })) | |
188 | #else | |
189 | #define IRA_LOOP_NODE_BY_INDEX(index) (&ira_loop_nodes[index]) | |
190 | #endif | |
191 | ||
192 | #define IRA_LOOP_NODE(loop) IRA_LOOP_NODE_BY_INDEX ((loop)->num) | |
193 | ||
194 | \f | |
058e97ec | 195 | /* The structure describes program points where a given allocno lives. |
1756cb66 VM |
196 | If the live ranges of two allocnos are intersected, the allocnos |
197 | are in conflict. */ | |
b14151b5 | 198 | struct live_range |
058e97ec | 199 | { |
ac0ab4f7 | 200 | /* Object whose live range is described by given structure. */ |
9140d27b | 201 | ira_object_t object; |
058e97ec VM |
202 | /* Program point range. */ |
203 | int start, finish; | |
204 | /* Next structure describing program points where the allocno | |
205 | lives. */ | |
b14151b5 | 206 | live_range_t next; |
058e97ec | 207 | /* Pointer to structures with the same start/finish. */ |
b14151b5 | 208 | live_range_t start_next, finish_next; |
058e97ec VM |
209 | }; |
210 | ||
211 | /* Program points are enumerated by numbers from range | |
212 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
213 | points than insns. Program points are places in the program where | |
214 | liveness info can be changed. In most general case (there are more | |
215 | complicated cases too) some program points correspond to places | |
216 | where input operand dies and other ones correspond to places where | |
217 | output operands are born. */ | |
218 | extern int ira_max_point; | |
219 | ||
220 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
221 | live ranges with given start/finish point. */ | |
b14151b5 | 222 | extern live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec | 223 | |
a49ae217 BS |
224 | /* A structure representing conflict information for an allocno |
225 | (or one of its subwords). */ | |
226 | struct ira_object | |
227 | { | |
228 | /* The allocno associated with this record. */ | |
229 | ira_allocno_t allocno; | |
230 | /* Vector of accumulated conflicting conflict_redords with NULL end | |
231 | marker (if OBJECT_CONFLICT_VEC_P is true) or conflict bit vector | |
1756cb66 | 232 | otherwise. */ |
a49ae217 | 233 | void *conflicts_array; |
9140d27b BS |
234 | /* Pointer to structures describing at what program point the |
235 | object lives. We always maintain the list in such way that *the | |
236 | ranges in the list are not intersected and ordered by decreasing | |
237 | their program points*. */ | |
238 | live_range_t live_ranges; | |
ac0ab4f7 BS |
239 | /* The subword within ALLOCNO which is represented by this object. |
240 | Zero means the lowest-order subword (or the entire allocno in case | |
241 | it is not being tracked in subwords). */ | |
242 | int subword; | |
9140d27b | 243 | /* Allocated size of the conflicts array. */ |
a49ae217 | 244 | unsigned int conflicts_array_size; |
ac0ab4f7 | 245 | /* A unique number for every instance of this structure, which is used |
a49ae217 BS |
246 | to represent it in conflict bit vectors. */ |
247 | int id; | |
248 | /* Before building conflicts, MIN and MAX are initialized to | |
249 | correspondingly minimal and maximal points of the accumulated | |
ac0ab4f7 BS |
250 | live ranges. Afterwards, they hold the minimal and maximal ids |
251 | of other ira_objects that this one can conflict with. */ | |
a49ae217 BS |
252 | int min, max; |
253 | /* Initial and accumulated hard registers conflicting with this | |
67914693 | 254 | object and as a consequences cannot be assigned to the allocno. |
1756cb66 | 255 | All non-allocatable hard regs and hard regs of register classes |
ac0ab4f7 | 256 | different from given allocno one are included in the sets. */ |
a49ae217 BS |
257 | HARD_REG_SET conflict_hard_regs, total_conflict_hard_regs; |
258 | /* Number of accumulated conflicts in the vector of conflicting | |
ac0ab4f7 | 259 | objects. */ |
a49ae217 BS |
260 | int num_accumulated_conflicts; |
261 | /* TRUE if conflicts are represented by a vector of pointers to | |
262 | ira_object structures. Otherwise, we use a bit vector indexed | |
263 | by conflict ID numbers. */ | |
264 | unsigned int conflict_vec_p : 1; | |
265 | }; | |
266 | ||
058e97ec VM |
267 | /* A structure representing an allocno (allocation entity). Allocno |
268 | represents a pseudo-register in an allocation region. If | |
269 | pseudo-register does not live in a region but it lives in the | |
270 | nested regions, it is represented in the region by special allocno | |
271 | called *cap*. There may be more one cap representing the same | |
272 | pseudo-register in region. It means that the corresponding | |
273 | pseudo-register lives in more one non-intersected subregion. */ | |
274 | struct ira_allocno | |
275 | { | |
276 | /* The allocno order number starting with 0. Each allocno has an | |
277 | unique number and the number is never changed for the | |
278 | allocno. */ | |
279 | int num; | |
280 | /* Regno for allocno or cap. */ | |
281 | int regno; | |
282 | /* Mode of the allocno which is the mode of the corresponding | |
283 | pseudo-register. */ | |
b14af304 | 284 | ENUM_BITFIELD (machine_mode) mode : MACHINE_MODE_BITSIZE; |
d1bb282e DS |
285 | /* Widest mode of the allocno which in at least one case could be |
286 | for paradoxical subregs where wmode > mode. */ | |
b14af304 | 287 | ENUM_BITFIELD (machine_mode) wmode : MACHINE_MODE_BITSIZE; |
1756cb66 VM |
288 | /* Register class which should be used for allocation for given |
289 | allocno. NO_REGS means that we should use memory. */ | |
290 | ENUM_BITFIELD (reg_class) aclass : 16; | |
b14af304 PL |
291 | /* Hard register assigned to given allocno. Negative value means |
292 | that memory was allocated to the allocno. During the reload, | |
293 | spilled allocno has value equal to the corresponding stack slot | |
294 | number (0, ...) - 2. Value -1 is used for allocnos spilled by the | |
295 | reload (at this point pseudo-register has only one allocno) which | |
296 | did not get stack slot yet. */ | |
297 | signed int hard_regno : 16; | |
6c476222 RS |
298 | /* A bitmask of the ABIs used by calls that occur while the allocno |
299 | is live. */ | |
300 | unsigned int crossed_calls_abis : NUM_ABI_IDS; | |
1756cb66 VM |
301 | /* During the reload, value TRUE means that we should not reassign a |
302 | hard register to the allocno got memory earlier. It is set up | |
303 | when we removed memory-memory move insn before each iteration of | |
304 | the reload. */ | |
305 | unsigned int dont_reassign_p : 1; | |
306 | #ifdef STACK_REGS | |
307 | /* Set to TRUE if allocno can't be assigned to the stack hard | |
308 | register correspondingly in this region and area including the | |
309 | region and all its subregions recursively. */ | |
310 | unsigned int no_stack_reg_p : 1, total_no_stack_reg_p : 1; | |
311 | #endif | |
312 | /* TRUE value means that there is no sense to spill the allocno | |
313 | during coloring because the spill will result in additional | |
314 | reloads in reload pass. */ | |
315 | unsigned int bad_spill_p : 1; | |
316 | /* TRUE if a hard register or memory has been assigned to the | |
317 | allocno. */ | |
318 | unsigned int assigned_p : 1; | |
319 | /* TRUE if conflicts for given allocno are represented by vector of | |
320 | pointers to the conflicting allocnos. Otherwise, we use a bit | |
321 | vector where a bit with given index represents allocno with the | |
322 | same number. */ | |
323 | unsigned int conflict_vec_p : 1; | |
8e7a2372 RS |
324 | /* True if the parent loop has an allocno for the same register and |
325 | if the parent allocno's assignment might not be valid in this loop. | |
326 | This means that we cannot merge this allocno and the parent allocno | |
327 | together. | |
328 | ||
329 | This is only ever true for non-cap allocnos. */ | |
330 | unsigned int might_conflict_with_parent_p : 1; | |
ef4e6e2c RS |
331 | #ifndef NUM_REGISTER_FILTERS |
332 | #error "insn-config.h not included" | |
333 | #elif NUM_REGISTER_FILTERS | |
334 | /* The set of register filters applied to the allocno by operand | |
335 | alternatives that accept class ACLASS. */ | |
336 | unsigned int register_filters : NUM_REGISTER_FILTERS; | |
337 | #endif | |
058e97ec VM |
338 | /* Accumulated usage references of the allocno. Here and below, |
339 | word 'accumulated' means info for given region and all nested | |
340 | subregions. In this case, 'accumulated' means sum of references | |
341 | of the corresponding pseudo-register in this region and in all | |
342 | nested subregions recursively. */ | |
343 | int nrefs; | |
344 | /* Accumulated frequency of usage of the allocno. */ | |
345 | int freq; | |
cb1ca6ac | 346 | /* Minimal accumulated and updated costs of usage register of the |
1756cb66 VM |
347 | allocno class. */ |
348 | int class_cost, updated_class_cost; | |
058e97ec VM |
349 | /* Minimal accumulated, and updated costs of memory for the allocno. |
350 | At the allocation start, the original and updated costs are | |
351 | equal. The updated cost may be changed after finishing | |
352 | allocation in a region and starting allocation in a subregion. | |
353 | The change reflects the cost of spill/restore code on the | |
354 | subregion border if we assign memory to the pseudo in the | |
355 | subregion. */ | |
356 | int memory_cost, updated_memory_cost; | |
357 | /* Accumulated number of points where the allocno lives and there is | |
358 | excess pressure for its class. Excess pressure for a register | |
359 | class at some point means that there are more allocnos of given | |
360 | register class living at the point than number of hard-registers | |
361 | of the class available for the allocation. */ | |
362 | int excess_pressure_points_num; | |
b14af304 PL |
363 | /* The number of objects tracked in the following array. */ |
364 | int num_objects; | |
365 | /* Accumulated frequency of calls which given allocno | |
366 | intersects. */ | |
367 | int call_freq; | |
368 | /* Accumulated number of the intersected calls. */ | |
369 | int calls_crossed_num; | |
370 | /* The number of calls across which it is live, but which should not | |
371 | affect register preferences. */ | |
372 | int cheap_calls_crossed_num; | |
373 | /* Allocnos with the same regno are linked by the following member. | |
374 | Allocnos corresponding to inner loops are first in the list (it | |
375 | corresponds to depth-first traverse of the loops). */ | |
376 | ira_allocno_t next_regno_allocno; | |
377 | /* There may be different allocnos with the same regno in different | |
378 | regions. Allocnos are bound to the corresponding loop tree node. | |
379 | Pseudo-register may have only one regular allocno with given loop | |
380 | tree node but more than one cap (see comments above). */ | |
381 | ira_loop_tree_node_t loop_tree_node; | |
3b6d1699 VM |
382 | /* Allocno hard reg preferences. */ |
383 | ira_pref_t allocno_prefs; | |
058e97ec VM |
384 | /* Copies to other non-conflicting allocnos. The copies can |
385 | represent move insn or potential move insn usually because of two | |
386 | operand insn constraints. */ | |
387 | ira_copy_t allocno_copies; | |
388 | /* It is a allocno (cap) representing given allocno on upper loop tree | |
389 | level. */ | |
390 | ira_allocno_t cap; | |
391 | /* It is a link to allocno (cap) on lower loop level represented by | |
392 | given cap. Null if given allocno is not a cap. */ | |
393 | ira_allocno_t cap_member; | |
ac0ab4f7 BS |
394 | /* An array of structures describing conflict information and live |
395 | ranges for each object associated with the allocno. There may be | |
396 | more than one such object in cases where the allocno represents a | |
397 | multi-word register. */ | |
398 | ira_object_t objects[2]; | |
c2ba7e7a RO |
399 | /* Registers clobbered by intersected calls. */ |
400 | HARD_REG_SET crossed_calls_clobbered_regs; | |
058e97ec | 401 | /* Array of usage costs (accumulated and the one updated during |
1756cb66 | 402 | coloring) for each hard register of the allocno class. The |
058e97ec | 403 | member value can be NULL if all costs are the same and equal to |
1756cb66 | 404 | CLASS_COST. For example, the costs of two different hard |
058e97ec VM |
405 | registers can be different if one hard register is callee-saved |
406 | and another one is callee-used and the allocno lives through | |
407 | calls. Another example can be case when for some insn the | |
408 | corresponding pseudo-register value should be put in specific | |
409 | register class (e.g. AREG for x86) which is a strict subset of | |
1756cb66 VM |
410 | the allocno class (GENERAL_REGS for x86). We have updated costs |
411 | to reflect the situation when the usage cost of a hard register | |
412 | is decreased because the allocno is connected to another allocno | |
413 | by a copy and the another allocno has been assigned to the hard | |
414 | register. */ | |
058e97ec VM |
415 | int *hard_reg_costs, *updated_hard_reg_costs; |
416 | /* Array of decreasing costs (accumulated and the one updated during | |
417 | coloring) for allocnos conflicting with given allocno for hard | |
1756cb66 VM |
418 | regno of the allocno class. The member value can be NULL if all |
419 | costs are the same. These costs are used to reflect preferences | |
420 | of other allocnos not assigned yet during assigning to given | |
421 | allocno. */ | |
058e97ec | 422 | int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs; |
1756cb66 VM |
423 | /* Different additional data. It is used to decrease size of |
424 | allocno data footprint. */ | |
425 | void *add_data; | |
058e97ec VM |
426 | }; |
427 | ||
1756cb66 | 428 | |
058e97ec VM |
429 | /* All members of the allocno structures should be accessed only |
430 | through the following macros. */ | |
431 | #define ALLOCNO_NUM(A) ((A)->num) | |
432 | #define ALLOCNO_REGNO(A) ((A)->regno) | |
433 | #define ALLOCNO_REG(A) ((A)->reg) | |
434 | #define ALLOCNO_NEXT_REGNO_ALLOCNO(A) ((A)->next_regno_allocno) | |
435 | #define ALLOCNO_LOOP_TREE_NODE(A) ((A)->loop_tree_node) | |
436 | #define ALLOCNO_CAP(A) ((A)->cap) | |
437 | #define ALLOCNO_CAP_MEMBER(A) ((A)->cap_member) | |
058e97ec VM |
438 | #define ALLOCNO_NREFS(A) ((A)->nrefs) |
439 | #define ALLOCNO_FREQ(A) ((A)->freq) | |
8e7a2372 RS |
440 | #define ALLOCNO_MIGHT_CONFLICT_WITH_PARENT_P(A) \ |
441 | ((A)->might_conflict_with_parent_p) | |
ef4e6e2c RS |
442 | #if NUM_REGISTER_FILTERS |
443 | #define ALLOCNO_REGISTER_FILTERS(A) (A)->register_filters | |
444 | #define ALLOCNO_SET_REGISTER_FILTERS(A, X) ((A)->register_filters = (X)) | |
445 | #else | |
446 | #define ALLOCNO_REGISTER_FILTERS(A) 0 | |
447 | #define ALLOCNO_SET_REGISTER_FILTERS(A, X) ((void) (A), gcc_assert ((X) == 0)) | |
448 | #endif | |
058e97ec VM |
449 | #define ALLOCNO_HARD_REGNO(A) ((A)->hard_regno) |
450 | #define ALLOCNO_CALL_FREQ(A) ((A)->call_freq) | |
451 | #define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num) | |
e384e6b5 | 452 | #define ALLOCNO_CHEAP_CALLS_CROSSED_NUM(A) ((A)->cheap_calls_crossed_num) |
6c476222 | 453 | #define ALLOCNO_CROSSED_CALLS_ABIS(A) ((A)->crossed_calls_abis) |
c2ba7e7a RO |
454 | #define ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS(A) \ |
455 | ((A)->crossed_calls_clobbered_regs) | |
058e97ec VM |
456 | #define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest) |
457 | #define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p) | |
458 | #define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p) | |
459 | #define ALLOCNO_CHILD_RENAMED_P(A) ((A)->child_renamed_p) | |
460 | #define ALLOCNO_DONT_REASSIGN_P(A) ((A)->dont_reassign_p) | |
461 | #ifdef STACK_REGS | |
462 | #define ALLOCNO_NO_STACK_REG_P(A) ((A)->no_stack_reg_p) | |
463 | #define ALLOCNO_TOTAL_NO_STACK_REG_P(A) ((A)->total_no_stack_reg_p) | |
464 | #endif | |
927425df | 465 | #define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p) |
058e97ec | 466 | #define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p) |
058e97ec | 467 | #define ALLOCNO_MODE(A) ((A)->mode) |
d1bb282e | 468 | #define ALLOCNO_WMODE(A) ((A)->wmode) |
3b6d1699 | 469 | #define ALLOCNO_PREFS(A) ((A)->allocno_prefs) |
058e97ec VM |
470 | #define ALLOCNO_COPIES(A) ((A)->allocno_copies) |
471 | #define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs) | |
472 | #define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs) | |
473 | #define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \ | |
474 | ((A)->conflict_hard_reg_costs) | |
475 | #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \ | |
476 | ((A)->updated_conflict_hard_reg_costs) | |
1756cb66 VM |
477 | #define ALLOCNO_CLASS(A) ((A)->aclass) |
478 | #define ALLOCNO_CLASS_COST(A) ((A)->class_cost) | |
479 | #define ALLOCNO_UPDATED_CLASS_COST(A) ((A)->updated_class_cost) | |
058e97ec VM |
480 | #define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost) |
481 | #define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost) | |
1756cb66 VM |
482 | #define ALLOCNO_EXCESS_PRESSURE_POINTS_NUM(A) \ |
483 | ((A)->excess_pressure_points_num) | |
ac0ab4f7 BS |
484 | #define ALLOCNO_OBJECT(A,N) ((A)->objects[N]) |
485 | #define ALLOCNO_NUM_OBJECTS(A) ((A)->num_objects) | |
1756cb66 | 486 | #define ALLOCNO_ADD_DATA(A) ((A)->add_data) |
a49ae217 | 487 | |
1756cb66 VM |
488 | /* Typedef for pointer to the subsequent structure. */ |
489 | typedef struct ira_emit_data *ira_emit_data_t; | |
490 | ||
491 | /* Allocno bound data used for emit pseudo live range split insns and | |
492 | to flattening IR. */ | |
493 | struct ira_emit_data | |
494 | { | |
495 | /* TRUE if the allocno assigned to memory was a destination of | |
e53b6e56 | 496 | removed move (see ira-emit.cc) at loop exit because the value of |
1756cb66 VM |
497 | the corresponding pseudo-register is not changed inside the |
498 | loop. */ | |
499 | unsigned int mem_optimized_dest_p : 1; | |
500 | /* TRUE if the corresponding pseudo-register has disjoint live | |
501 | ranges and the other allocnos of the pseudo-register except this | |
502 | one changed REG. */ | |
503 | unsigned int somewhere_renamed_p : 1; | |
504 | /* TRUE if allocno with the same REGNO in a subregion has been | |
505 | renamed, in other words, got a new pseudo-register. */ | |
506 | unsigned int child_renamed_p : 1; | |
507 | /* Final rtx representation of the allocno. */ | |
508 | rtx reg; | |
509 | /* Non NULL if we remove restoring value from given allocno to | |
e53b6e56 | 510 | MEM_OPTIMIZED_DEST at loop exit (see ira-emit.cc) because the |
1756cb66 VM |
511 | allocno value is not changed inside the loop. */ |
512 | ira_allocno_t mem_optimized_dest; | |
513 | }; | |
514 | ||
515 | #define ALLOCNO_EMIT_DATA(a) ((ira_emit_data_t) ALLOCNO_ADD_DATA (a)) | |
516 | ||
517 | /* Data used to emit live range split insns and to flattening IR. */ | |
518 | extern ira_emit_data_t ira_allocno_emit_data; | |
519 | ||
520 | /* Abbreviation for frequent emit data access. */ | |
cb3e0eac | 521 | inline rtx |
1756cb66 VM |
522 | allocno_emit_reg (ira_allocno_t a) |
523 | { | |
524 | return ALLOCNO_EMIT_DATA (a)->reg; | |
525 | } | |
526 | ||
527 | #define OBJECT_ALLOCNO(O) ((O)->allocno) | |
528 | #define OBJECT_SUBWORD(O) ((O)->subword) | |
529 | #define OBJECT_CONFLICT_ARRAY(O) ((O)->conflicts_array) | |
530 | #define OBJECT_CONFLICT_VEC(O) ((ira_object_t *)(O)->conflicts_array) | |
531 | #define OBJECT_CONFLICT_BITVEC(O) ((IRA_INT_TYPE *)(O)->conflicts_array) | |
532 | #define OBJECT_CONFLICT_ARRAY_SIZE(O) ((O)->conflicts_array_size) | |
533 | #define OBJECT_CONFLICT_VEC_P(O) ((O)->conflict_vec_p) | |
534 | #define OBJECT_NUM_CONFLICTS(O) ((O)->num_accumulated_conflicts) | |
535 | #define OBJECT_CONFLICT_HARD_REGS(O) ((O)->conflict_hard_regs) | |
536 | #define OBJECT_TOTAL_CONFLICT_HARD_REGS(O) ((O)->total_conflict_hard_regs) | |
537 | #define OBJECT_MIN(O) ((O)->min) | |
538 | #define OBJECT_MAX(O) ((O)->max) | |
539 | #define OBJECT_CONFLICT_ID(O) ((O)->id) | |
540 | #define OBJECT_LIVE_RANGES(O) ((O)->live_ranges) | |
058e97ec | 541 | |
b8698a0f | 542 | /* Map regno -> allocnos with given regno (see comments for |
058e97ec VM |
543 | allocno member `next_regno_allocno'). */ |
544 | extern ira_allocno_t *ira_regno_allocno_map; | |
545 | ||
546 | /* Array of references to all allocnos. The order number of the | |
547 | allocno corresponds to the index in the array. Removed allocnos | |
548 | have NULL element value. */ | |
549 | extern ira_allocno_t *ira_allocnos; | |
550 | ||
a49ae217 | 551 | /* The size of the previous array. */ |
058e97ec VM |
552 | extern int ira_allocnos_num; |
553 | ||
a49ae217 BS |
554 | /* Map a conflict id to its corresponding ira_object structure. */ |
555 | extern ira_object_t *ira_object_id_map; | |
556 | ||
557 | /* The size of the previous array. */ | |
558 | extern int ira_objects_num; | |
058e97ec | 559 | |
df3e3493 | 560 | /* The following structure represents a hard register preference of |
3b6d1699 VM |
561 | allocno. The preference represent move insns or potential move |
562 | insns usually because of two operand insn constraints. One move | |
563 | operand is a hard register. */ | |
564 | struct ira_allocno_pref | |
565 | { | |
566 | /* The unique order number of the preference node starting with 0. */ | |
567 | int num; | |
568 | /* Preferred hard register. */ | |
569 | int hard_regno; | |
570 | /* Accumulated execution frequency of insns from which the | |
571 | preference created. */ | |
572 | int freq; | |
573 | /* Given allocno. */ | |
574 | ira_allocno_t allocno; | |
df3e3493 | 575 | /* All preferences with the same allocno are linked by the following |
3b6d1699 VM |
576 | member. */ |
577 | ira_pref_t next_pref; | |
578 | }; | |
579 | ||
580 | /* Array of references to all allocno preferences. The order number | |
581 | of the preference corresponds to the index in the array. */ | |
582 | extern ira_pref_t *ira_prefs; | |
583 | ||
584 | /* Size of the previous array. */ | |
585 | extern int ira_prefs_num; | |
586 | ||
058e97ec VM |
587 | /* The following structure represents a copy of two allocnos. The |
588 | copies represent move insns or potential move insns usually because | |
589 | of two operand insn constraints. To remove register shuffle, we | |
590 | also create copies between allocno which is output of an insn and | |
591 | allocno becoming dead in the insn. */ | |
592 | struct ira_allocno_copy | |
593 | { | |
594 | /* The unique order number of the copy node starting with 0. */ | |
595 | int num; | |
596 | /* Allocnos connected by the copy. The first allocno should have | |
597 | smaller order number than the second one. */ | |
598 | ira_allocno_t first, second; | |
599 | /* Execution frequency of the copy. */ | |
600 | int freq; | |
548a6322 | 601 | bool constraint_p; |
058e97ec VM |
602 | /* It is a move insn which is an origin of the copy. The member |
603 | value for the copy representing two operand insn constraints or | |
604 | for the copy created to remove register shuffle is NULL. In last | |
605 | case the copy frequency is smaller than the corresponding insn | |
606 | execution frequency. */ | |
070a1983 | 607 | rtx_insn *insn; |
058e97ec VM |
608 | /* All copies with the same allocno as FIRST are linked by the two |
609 | following members. */ | |
610 | ira_copy_t prev_first_allocno_copy, next_first_allocno_copy; | |
611 | /* All copies with the same allocno as SECOND are linked by the two | |
612 | following members. */ | |
613 | ira_copy_t prev_second_allocno_copy, next_second_allocno_copy; | |
614 | /* Region from which given copy is originated. */ | |
615 | ira_loop_tree_node_t loop_tree_node; | |
616 | }; | |
617 | ||
618 | /* Array of references to all copies. The order number of the copy | |
619 | corresponds to the index in the array. Removed copies have NULL | |
620 | element value. */ | |
621 | extern ira_copy_t *ira_copies; | |
622 | ||
623 | /* Size of the previous array. */ | |
624 | extern int ira_copies_num; | |
625 | ||
626 | /* The following structure describes a stack slot used for spilled | |
627 | pseudo-registers. */ | |
6c1dae73 | 628 | class ira_spilled_reg_stack_slot |
058e97ec | 629 | { |
6c1dae73 | 630 | public: |
058e97ec | 631 | /* pseudo-registers assigned to the stack slot. */ |
7a8cba34 | 632 | bitmap_head spilled_regs; |
058e97ec VM |
633 | /* RTL representation of the stack slot. */ |
634 | rtx mem; | |
635 | /* Size of the stack slot. */ | |
eaa41a6d | 636 | poly_uint64 width; |
058e97ec VM |
637 | }; |
638 | ||
639 | /* The number of elements in the following array. */ | |
640 | extern int ira_spilled_reg_stack_slots_num; | |
641 | ||
642 | /* The following array contains info about spilled pseudo-registers | |
643 | stack slots used in current function so far. */ | |
99b1c316 | 644 | extern class ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; |
058e97ec VM |
645 | |
646 | /* Correspondingly overall cost of the allocation, cost of the | |
647 | allocnos assigned to hard-registers, cost of the allocnos assigned | |
648 | to memory, cost of loads, stores and register move insns generated | |
e53b6e56 | 649 | for pseudo-register live range splitting (see ira-emit.cc). */ |
2bf7560b VM |
650 | extern int64_t ira_overall_cost; |
651 | extern int64_t ira_reg_cost, ira_mem_cost; | |
652 | extern int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
058e97ec | 653 | extern int ira_move_loops_num, ira_additional_jumps_num; |
1756cb66 | 654 | |
42ce1cc4 BS |
655 | \f |
656 | /* This page contains a bitset implementation called 'min/max sets' used to | |
657 | record conflicts in IRA. | |
658 | They are named min/maxs set since we keep track of a minimum and a maximum | |
659 | bit number for each set representing the bounds of valid elements. Otherwise, | |
660 | the implementation resembles sbitmaps in that we store an array of integers | |
661 | whose bits directly represent the members of the set. */ | |
662 | ||
663 | /* The type used as elements in the array, and the number of bits in | |
664 | this type. */ | |
ac0ab4f7 | 665 | |
058e97ec VM |
666 | #define IRA_INT_BITS HOST_BITS_PER_WIDE_INT |
667 | #define IRA_INT_TYPE HOST_WIDE_INT | |
668 | ||
669 | /* Set, clear or test bit number I in R, a bit vector of elements with | |
670 | minimal index and maximal index equal correspondingly to MIN and | |
671 | MAX. */ | |
672 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
673 | ||
42ce1cc4 | 674 | #define SET_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
675 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
676 | if (_i < _min || _i > _max) \ | |
677 | { \ | |
678 | fprintf (stderr, \ | |
679 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
680 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
681 | gcc_unreachable (); \ | |
682 | } \ | |
683 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
684 | |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
b8698a0f | 685 | |
058e97ec | 686 | |
42ce1cc4 | 687 | #define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
688 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
689 | if (_i < _min || _i > _max) \ | |
690 | { \ | |
691 | fprintf (stderr, \ | |
692 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
693 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
694 | gcc_unreachable (); \ | |
695 | } \ | |
696 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
697 | &= ~((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
698 | ||
42ce1cc4 | 699 | #define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
700 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
701 | if (_i < _min || _i > _max) \ | |
702 | { \ | |
703 | fprintf (stderr, \ | |
704 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
705 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
706 | gcc_unreachable (); \ | |
707 | } \ | |
708 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
709 | & ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
710 | ||
711 | #else | |
712 | ||
42ce1cc4 | 713 | #define SET_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
714 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
715 | |= ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
716 | ||
42ce1cc4 | 717 | #define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
718 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
719 | &= ~((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
720 | ||
42ce1cc4 | 721 | #define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
722 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
723 | & ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
724 | ||
725 | #endif | |
726 | ||
42ce1cc4 | 727 | /* The iterator for min/max sets. */ |
84562394 | 728 | struct minmax_set_iterator { |
058e97ec | 729 | |
42ce1cc4 | 730 | /* Array containing the bit vector. */ |
058e97ec VM |
731 | IRA_INT_TYPE *vec; |
732 | ||
733 | /* The number of the current element in the vector. */ | |
734 | unsigned int word_num; | |
735 | ||
736 | /* The number of bits in the bit vector. */ | |
737 | unsigned int nel; | |
738 | ||
739 | /* The current bit index of the bit vector. */ | |
740 | unsigned int bit_num; | |
741 | ||
742 | /* Index corresponding to the 1st bit of the bit vector. */ | |
743 | int start_val; | |
744 | ||
745 | /* The word of the bit vector currently visited. */ | |
746 | unsigned IRA_INT_TYPE word; | |
84562394 | 747 | }; |
058e97ec | 748 | |
42ce1cc4 BS |
749 | /* Initialize the iterator I for bit vector VEC containing minimal and |
750 | maximal values MIN and MAX. */ | |
cb3e0eac | 751 | inline void |
42ce1cc4 BS |
752 | minmax_set_iter_init (minmax_set_iterator *i, IRA_INT_TYPE *vec, int min, |
753 | int max) | |
058e97ec VM |
754 | { |
755 | i->vec = vec; | |
756 | i->word_num = 0; | |
757 | i->nel = max < min ? 0 : max - min + 1; | |
758 | i->start_val = min; | |
759 | i->bit_num = 0; | |
760 | i->word = i->nel == 0 ? 0 : vec[0]; | |
761 | } | |
762 | ||
ac0ab4f7 | 763 | /* Return TRUE if we have more allocnos to visit, in which case *N is |
42ce1cc4 | 764 | set to the number of the element to be visited. Otherwise, return |
058e97ec | 765 | FALSE. */ |
cb3e0eac | 766 | inline bool |
42ce1cc4 | 767 | minmax_set_iter_cond (minmax_set_iterator *i, int *n) |
058e97ec VM |
768 | { |
769 | /* Skip words that are zeros. */ | |
770 | for (; i->word == 0; i->word = i->vec[i->word_num]) | |
771 | { | |
772 | i->word_num++; | |
773 | i->bit_num = i->word_num * IRA_INT_BITS; | |
b8698a0f | 774 | |
058e97ec VM |
775 | /* If we have reached the end, break. */ |
776 | if (i->bit_num >= i->nel) | |
777 | return false; | |
778 | } | |
b8698a0f | 779 | |
058e97ec | 780 | /* Skip bits that are zero. */ |
a8250bba RB |
781 | int off = ctz_hwi (i->word); |
782 | i->bit_num += off; | |
783 | i->word >>= off; | |
b8698a0f | 784 | |
058e97ec | 785 | *n = (int) i->bit_num + i->start_val; |
b8698a0f | 786 | |
058e97ec VM |
787 | return true; |
788 | } | |
789 | ||
42ce1cc4 | 790 | /* Advance to the next element in the set. */ |
cb3e0eac | 791 | inline void |
42ce1cc4 | 792 | minmax_set_iter_next (minmax_set_iterator *i) |
058e97ec VM |
793 | { |
794 | i->word >>= 1; | |
795 | i->bit_num++; | |
796 | } | |
797 | ||
42ce1cc4 | 798 | /* Loop over all elements of a min/max set given by bit vector VEC and |
058e97ec VM |
799 | their minimal and maximal values MIN and MAX. In each iteration, N |
800 | is set to the number of next allocno. ITER is an instance of | |
42ce1cc4 BS |
801 | minmax_set_iterator used to iterate over the set. */ |
802 | #define FOR_EACH_BIT_IN_MINMAX_SET(VEC, MIN, MAX, N, ITER) \ | |
803 | for (minmax_set_iter_init (&(ITER), (VEC), (MIN), (MAX)); \ | |
804 | minmax_set_iter_cond (&(ITER), &(N)); \ | |
805 | minmax_set_iter_next (&(ITER))) | |
806 | \f | |
6c1dae73 MS |
807 | class target_ira_int { |
808 | public: | |
19c708dc RS |
809 | ~target_ira_int (); |
810 | ||
811 | void free_ira_costs (); | |
812 | void free_register_move_costs (); | |
813 | ||
aa1c5d72 RS |
814 | /* Initialized once. It is a maximal possible size of the allocated |
815 | struct costs. */ | |
ff304c01 | 816 | size_t x_max_struct_costs_size; |
aa1c5d72 RS |
817 | |
818 | /* Allocated and initialized once, and used to initialize cost values | |
819 | for each insn. */ | |
820 | struct costs *x_init_cost; | |
821 | ||
822 | /* Allocated once, and used for temporary purposes. */ | |
823 | struct costs *x_temp_costs; | |
824 | ||
825 | /* Allocated once, and used for the cost calculation. */ | |
826 | struct costs *x_op_costs[MAX_RECOG_OPERANDS]; | |
827 | struct costs *x_this_op_costs[MAX_RECOG_OPERANDS]; | |
828 | ||
67914693 | 829 | /* Hard registers that cannot be used for the register allocator for |
afcc66c4 RS |
830 | all functions of the current compilation unit. */ |
831 | HARD_REG_SET x_no_unit_alloc_regs; | |
832 | ||
833 | /* Map: hard regs X modes -> set of hard registers for storing value | |
834 | of given mode starting with given hard register. */ | |
835 | HARD_REG_SET (x_ira_reg_mode_hard_regset | |
836 | [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]); | |
837 | ||
e80ccebc RS |
838 | /* Maximum cost of moving from a register in one class to a register |
839 | in another class. Based on TARGET_REGISTER_MOVE_COST. */ | |
7cc61ee4 | 840 | move_table *x_ira_register_move_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
841 | |
842 | /* Similar, but here we don't have to move if the first index is a | |
843 | subset of the second so in that case the cost is zero. */ | |
7cc61ee4 | 844 | move_table *x_ira_may_move_in_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
845 | |
846 | /* Similar, but here we don't have to move if the first index is a | |
847 | superset of the second so in that case the cost is zero. */ | |
7cc61ee4 | 848 | move_table *x_ira_may_move_out_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
849 | |
850 | /* Keep track of the last mode we initialized move costs for. */ | |
851 | int x_last_mode_for_init_move_cost; | |
852 | ||
7cc61ee4 RS |
853 | /* Array analog of the macro MEMORY_MOVE_COST but they contain maximal |
854 | cost not minimal. */ | |
1756cb66 | 855 | short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; |
1756cb66 VM |
856 | |
857 | /* Map class->true if class is a possible allocno class, false | |
858 | otherwise. */ | |
859 | bool x_ira_reg_allocno_class_p[N_REG_CLASSES]; | |
860 | ||
861 | /* Map class->true if class is a pressure class, false otherwise. */ | |
862 | bool x_ira_reg_pressure_class_p[N_REG_CLASSES]; | |
863 | ||
afcc66c4 | 864 | /* Array of the number of hard registers of given class which are |
dd5a833e | 865 | available for allocation. The order is defined by the hard |
afcc66c4 RS |
866 | register numbers. */ |
867 | short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
868 | ||
869 | /* Index (in ira_class_hard_regs; for given register class and hard | |
870 | register (in general case a hard register can belong to several | |
871 | register classes;. The index is negative for hard registers | |
872 | unavailable for the allocation. */ | |
873 | short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
874 | ||
a2c19e93 RS |
875 | /* Index [CL][M] contains R if R appears somewhere in a register of the form: |
876 | ||
877 | (reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M] | |
878 | ||
879 | For example, if: | |
880 | ||
881 | - (reg:M 2) is valid and occupies two registers; | |
882 | - register 2 belongs to CL; and | |
883 | - register 3 belongs to the same pressure class as CL | |
884 | ||
885 | then (reg:M 2) contributes to [CL][M] and registers 2 and 3 will be | |
886 | in the set. */ | |
887 | HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; | |
888 | ||
afcc66c4 RS |
889 | /* The value is number of elements in the subsequent array. */ |
890 | int x_ira_important_classes_num; | |
891 | ||
1756cb66 | 892 | /* The array containing all non-empty classes. Such classes is |
afcc66c4 RS |
893 | important for calculation of the hard register usage costs. */ |
894 | enum reg_class x_ira_important_classes[N_REG_CLASSES]; | |
895 | ||
1756cb66 VM |
896 | /* The array containing indexes of important classes in the previous |
897 | array. The array elements are defined only for important | |
898 | classes. */ | |
899 | int x_ira_important_class_nums[N_REG_CLASSES]; | |
900 | ||
165f639c VM |
901 | /* Map class->true if class is an uniform class, false otherwise. */ |
902 | bool x_ira_uniform_class_p[N_REG_CLASSES]; | |
903 | ||
afcc66c4 RS |
904 | /* The biggest important class inside of intersection of the two |
905 | classes (that is calculated taking only hard registers available | |
906 | for allocation into account;. If the both classes contain no hard | |
907 | registers available for allocation, the value is calculated with | |
908 | taking all hard-registers including fixed ones into account. */ | |
909 | enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES]; | |
910 | ||
afcc66c4 | 911 | /* Classes with end marker LIM_REG_CLASSES which are intersected with |
55a2c322 | 912 | given class (the first index). That includes given class itself. |
afcc66c4 RS |
913 | This is calculated taking only hard registers available for |
914 | allocation into account. */ | |
915 | enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES]; | |
916 | ||
1756cb66 VM |
917 | /* The biggest (smallest) important class inside of (covering) union |
918 | of the two classes (that is calculated taking only hard registers | |
919 | available for allocation into account). If the both classes | |
920 | contain no hard registers available for allocation, the value is | |
921 | calculated with taking all hard-registers including fixed ones | |
922 | into account. In other words, the value is the corresponding | |
923 | reg_class_subunion (reg_class_superunion) value. */ | |
924 | enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
925 | enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
afcc66c4 RS |
926 | |
927 | /* For each reg class, table listing all the classes contained in it | |
928 | (excluding the class itself. Non-allocatable registers are | |
55a2c322 | 929 | excluded from the consideration). */ |
afcc66c4 | 930 | enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
15e7b94f RS |
931 | |
932 | /* Array whose values are hard regset of hard registers for which | |
933 | move of the hard register in given mode into itself is | |
934 | prohibited. */ | |
935 | HARD_REG_SET x_ira_prohibited_mode_move_regs[NUM_MACHINE_MODES]; | |
936 | ||
937 | /* Flag of that the above array has been initialized. */ | |
938 | bool x_ira_prohibited_mode_move_regs_initialized_p; | |
afcc66c4 RS |
939 | }; |
940 | ||
99b1c316 | 941 | extern class target_ira_int default_target_ira_int; |
afcc66c4 | 942 | #if SWITCHABLE_TARGET |
99b1c316 | 943 | extern class target_ira_int *this_target_ira_int; |
afcc66c4 RS |
944 | #else |
945 | #define this_target_ira_int (&default_target_ira_int) | |
946 | #endif | |
058e97ec | 947 | |
afcc66c4 RS |
948 | #define ira_reg_mode_hard_regset \ |
949 | (this_target_ira_int->x_ira_reg_mode_hard_regset) | |
950 | #define ira_register_move_cost \ | |
951 | (this_target_ira_int->x_ira_register_move_cost) | |
1756cb66 VM |
952 | #define ira_max_memory_move_cost \ |
953 | (this_target_ira_int->x_ira_max_memory_move_cost) | |
afcc66c4 RS |
954 | #define ira_may_move_in_cost \ |
955 | (this_target_ira_int->x_ira_may_move_in_cost) | |
956 | #define ira_may_move_out_cost \ | |
957 | (this_target_ira_int->x_ira_may_move_out_cost) | |
1756cb66 VM |
958 | #define ira_reg_allocno_class_p \ |
959 | (this_target_ira_int->x_ira_reg_allocno_class_p) | |
960 | #define ira_reg_pressure_class_p \ | |
961 | (this_target_ira_int->x_ira_reg_pressure_class_p) | |
afcc66c4 RS |
962 | #define ira_non_ordered_class_hard_regs \ |
963 | (this_target_ira_int->x_ira_non_ordered_class_hard_regs) | |
964 | #define ira_class_hard_reg_index \ | |
965 | (this_target_ira_int->x_ira_class_hard_reg_index) | |
a2c19e93 RS |
966 | #define ira_useful_class_mode_regs \ |
967 | (this_target_ira_int->x_ira_useful_class_mode_regs) | |
afcc66c4 RS |
968 | #define ira_important_classes_num \ |
969 | (this_target_ira_int->x_ira_important_classes_num) | |
970 | #define ira_important_classes \ | |
971 | (this_target_ira_int->x_ira_important_classes) | |
1756cb66 VM |
972 | #define ira_important_class_nums \ |
973 | (this_target_ira_int->x_ira_important_class_nums) | |
165f639c VM |
974 | #define ira_uniform_class_p \ |
975 | (this_target_ira_int->x_ira_uniform_class_p) | |
afcc66c4 RS |
976 | #define ira_reg_class_intersect \ |
977 | (this_target_ira_int->x_ira_reg_class_intersect) | |
afcc66c4 RS |
978 | #define ira_reg_class_super_classes \ |
979 | (this_target_ira_int->x_ira_reg_class_super_classes) | |
1756cb66 VM |
980 | #define ira_reg_class_subunion \ |
981 | (this_target_ira_int->x_ira_reg_class_subunion) | |
982 | #define ira_reg_class_superunion \ | |
983 | (this_target_ira_int->x_ira_reg_class_superunion) | |
15e7b94f RS |
984 | #define ira_prohibited_mode_move_regs \ |
985 | (this_target_ira_int->x_ira_prohibited_mode_move_regs) | |
afcc66c4 | 986 | \f |
e53b6e56 | 987 | /* ira.cc: */ |
058e97ec | 988 | |
058e97ec | 989 | extern void *ira_allocate (size_t); |
058e97ec VM |
990 | extern void ira_free (void *addr); |
991 | extern bitmap ira_allocate_bitmap (void); | |
992 | extern void ira_free_bitmap (bitmap); | |
993 | extern void ira_print_disposition (FILE *); | |
994 | extern void ira_debug_disposition (void); | |
1756cb66 | 995 | extern void ira_debug_allocno_classes (void); |
ef4bddc2 | 996 | extern void ira_init_register_move_cost (machine_mode); |
73bb8fe9 | 997 | extern alternative_mask ira_setup_alts (rtx_insn *); |
8ffe25ee | 998 | extern int ira_get_dup_out_num (int, alternative_mask, bool &); |
058e97ec | 999 | |
e53b6e56 | 1000 | /* ira-build.cc */ |
058e97ec VM |
1001 | |
1002 | /* The current loop tree node and its regno allocno map. */ | |
1003 | extern ira_loop_tree_node_t ira_curr_loop_tree_node; | |
1004 | extern ira_allocno_t *ira_curr_regno_allocno_map; | |
1005 | ||
3b6d1699 VM |
1006 | extern void ira_debug_pref (ira_pref_t); |
1007 | extern void ira_debug_prefs (void); | |
1008 | extern void ira_debug_allocno_prefs (ira_allocno_t); | |
1009 | ||
4cda38d5 | 1010 | extern void ira_debug_copy (ira_copy_t); |
7b3b6ae4 LC |
1011 | extern void debug (ira_allocno_copy &ref); |
1012 | extern void debug (ira_allocno_copy *ptr); | |
1013 | ||
4cda38d5 | 1014 | extern void ira_debug_copies (void); |
058e97ec | 1015 | extern void ira_debug_allocno_copies (ira_allocno_t); |
7b3b6ae4 LC |
1016 | extern void debug (ira_allocno &ref); |
1017 | extern void debug (ira_allocno *ptr); | |
058e97ec VM |
1018 | |
1019 | extern void ira_traverse_loop_tree (bool, ira_loop_tree_node_t, | |
1020 | void (*) (ira_loop_tree_node_t), | |
1021 | void (*) (ira_loop_tree_node_t)); | |
029da7d4 BS |
1022 | extern ira_allocno_t ira_parent_allocno (ira_allocno_t); |
1023 | extern ira_allocno_t ira_parent_or_cap_allocno (ira_allocno_t); | |
058e97ec | 1024 | extern ira_allocno_t ira_create_allocno (int, bool, ira_loop_tree_node_t); |
ac0ab4f7 | 1025 | extern void ira_create_allocno_objects (ira_allocno_t); |
1756cb66 | 1026 | extern void ira_set_allocno_class (ira_allocno_t, enum reg_class); |
a49ae217 BS |
1027 | extern bool ira_conflict_vector_profitable_p (ira_object_t, int); |
1028 | extern void ira_allocate_conflict_vec (ira_object_t, int); | |
1029 | extern void ira_allocate_object_conflicts (ira_object_t, int); | |
75f4e3a1 | 1030 | extern void ior_hard_reg_conflicts (ira_allocno_t, const_hard_reg_set); |
058e97ec | 1031 | extern void ira_print_expanded_allocno (ira_allocno_t); |
ac0ab4f7 | 1032 | extern void ira_add_live_range_to_object (ira_object_t, int, int); |
9140d27b BS |
1033 | extern live_range_t ira_create_live_range (ira_object_t, int, int, |
1034 | live_range_t); | |
1035 | extern live_range_t ira_copy_live_range_list (live_range_t); | |
1036 | extern live_range_t ira_merge_live_ranges (live_range_t, live_range_t); | |
1037 | extern bool ira_live_ranges_intersect_p (live_range_t, live_range_t); | |
1038 | extern void ira_finish_live_range (live_range_t); | |
1039 | extern void ira_finish_live_range_list (live_range_t); | |
058e97ec | 1040 | extern void ira_free_allocno_updated_costs (ira_allocno_t); |
3b6d1699 VM |
1041 | extern ira_pref_t ira_create_pref (ira_allocno_t, int, int); |
1042 | extern void ira_add_allocno_pref (ira_allocno_t, int, int); | |
1043 | extern void ira_remove_pref (ira_pref_t); | |
1044 | extern void ira_remove_allocno_prefs (ira_allocno_t); | |
058e97ec | 1045 | extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t, |
070a1983 DM |
1046 | int, bool, rtx_insn *, |
1047 | ira_loop_tree_node_t); | |
548a6322 | 1048 | extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int, |
070a1983 DM |
1049 | bool, rtx_insn *, |
1050 | ira_loop_tree_node_t); | |
058e97ec | 1051 | |
6f76a878 AS |
1052 | extern int *ira_allocate_cost_vector (reg_class_t); |
1053 | extern void ira_free_cost_vector (int *, reg_class_t); | |
058e97ec VM |
1054 | |
1055 | extern void ira_flattening (int, int); | |
2608d841 | 1056 | extern bool ira_build (void); |
058e97ec VM |
1057 | extern void ira_destroy (void); |
1058 | ||
e53b6e56 | 1059 | /* ira-costs.cc */ |
058e97ec VM |
1060 | extern void ira_init_costs_once (void); |
1061 | extern void ira_init_costs (void); | |
058e97ec | 1062 | extern void ira_costs (void); |
1756cb66 | 1063 | extern void ira_tune_allocno_costs (void); |
058e97ec | 1064 | |
e53b6e56 | 1065 | /* ira-lives.cc */ |
058e97ec VM |
1066 | |
1067 | extern void ira_rebuild_start_finish_chains (void); | |
b14151b5 | 1068 | extern void ira_print_live_range_list (FILE *, live_range_t); |
7b3b6ae4 LC |
1069 | extern void debug (live_range &ref); |
1070 | extern void debug (live_range *ptr); | |
b14151b5 | 1071 | extern void ira_debug_live_range_list (live_range_t); |
058e97ec VM |
1072 | extern void ira_debug_allocno_live_ranges (ira_allocno_t); |
1073 | extern void ira_debug_live_ranges (void); | |
1074 | extern void ira_create_allocno_live_ranges (void); | |
b15a7ae6 | 1075 | extern void ira_compress_allocno_live_ranges (void); |
058e97ec | 1076 | extern void ira_finish_allocno_live_ranges (void); |
8f3f5ac0 L |
1077 | extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *, |
1078 | alternative_mask); | |
058e97ec | 1079 | |
e53b6e56 | 1080 | /* ira-conflicts.cc */ |
058e97ec VM |
1081 | extern void ira_debug_conflicts (bool); |
1082 | extern void ira_build_conflicts (void); | |
1083 | ||
e53b6e56 | 1084 | /* ira-color.cc */ |
037cc0b4 | 1085 | extern ira_allocno_t ira_soft_conflict (ira_allocno_t, ira_allocno_t); |
1756cb66 | 1086 | extern void ira_debug_hard_regs_forest (void); |
058e97ec VM |
1087 | extern int ira_loop_edge_freq (ira_loop_tree_node_t, int, bool); |
1088 | extern void ira_reassign_conflict_allocnos (int); | |
1089 | extern void ira_initiate_assign (void); | |
1090 | extern void ira_finish_assign (void); | |
1091 | extern void ira_color (void); | |
058e97ec | 1092 | |
e53b6e56 | 1093 | /* ira-emit.cc */ |
1756cb66 VM |
1094 | extern void ira_initiate_emit_data (void); |
1095 | extern void ira_finish_emit_data (void); | |
058e97ec VM |
1096 | extern void ira_emit (bool); |
1097 | ||
1098 | \f | |
1099 | ||
55a2c322 | 1100 | /* Return true if equivalence of pseudo REGNO is not a lvalue. */ |
cb3e0eac | 1101 | inline bool |
55a2c322 VM |
1102 | ira_equiv_no_lvalue_p (int regno) |
1103 | { | |
1104 | if (regno >= ira_reg_equiv_len) | |
1105 | return false; | |
1106 | return (ira_reg_equiv[regno].constant != NULL_RTX | |
1107 | || ira_reg_equiv[regno].invariant != NULL_RTX | |
1108 | || (ira_reg_equiv[regno].memory != NULL_RTX | |
1109 | && MEM_READONLY_P (ira_reg_equiv[regno].memory))); | |
1110 | } | |
1111 | ||
1112 | \f | |
1113 | ||
1756cb66 | 1114 | /* Initialize register costs for MODE if necessary. */ |
cb3e0eac | 1115 | inline void |
ef4bddc2 | 1116 | ira_init_register_move_cost_if_necessary (machine_mode mode) |
6080348f VM |
1117 | { |
1118 | if (ira_register_move_cost[mode] == NULL) | |
1119 | ira_init_register_move_cost (mode); | |
6080348f VM |
1120 | } |
1121 | ||
1122 | \f | |
1123 | ||
058e97ec | 1124 | /* The iterator for all allocnos. */ |
84562394 | 1125 | struct ira_allocno_iterator { |
058e97ec VM |
1126 | /* The number of the current element in IRA_ALLOCNOS. */ |
1127 | int n; | |
84562394 | 1128 | }; |
058e97ec VM |
1129 | |
1130 | /* Initialize the iterator I. */ | |
cb3e0eac | 1131 | inline void |
058e97ec VM |
1132 | ira_allocno_iter_init (ira_allocno_iterator *i) |
1133 | { | |
1134 | i->n = 0; | |
1135 | } | |
1136 | ||
1137 | /* Return TRUE if we have more allocnos to visit, in which case *A is | |
1138 | set to the allocno to be visited. Otherwise, return FALSE. */ | |
cb3e0eac | 1139 | inline bool |
058e97ec VM |
1140 | ira_allocno_iter_cond (ira_allocno_iterator *i, ira_allocno_t *a) |
1141 | { | |
1142 | int n; | |
1143 | ||
1144 | for (n = i->n; n < ira_allocnos_num; n++) | |
1145 | if (ira_allocnos[n] != NULL) | |
1146 | { | |
1147 | *a = ira_allocnos[n]; | |
1148 | i->n = n + 1; | |
1149 | return true; | |
1150 | } | |
1151 | return false; | |
1152 | } | |
1153 | ||
1154 | /* Loop over all allocnos. In each iteration, A is set to the next | |
1155 | allocno. ITER is an instance of ira_allocno_iterator used to iterate | |
1156 | the allocnos. */ | |
1157 | #define FOR_EACH_ALLOCNO(A, ITER) \ | |
1158 | for (ira_allocno_iter_init (&(ITER)); \ | |
1159 | ira_allocno_iter_cond (&(ITER), &(A));) | |
a49ae217 BS |
1160 | \f |
1161 | /* The iterator for all objects. */ | |
84562394 | 1162 | struct ira_object_iterator { |
ac0ab4f7 | 1163 | /* The number of the current element in ira_object_id_map. */ |
a49ae217 | 1164 | int n; |
84562394 | 1165 | }; |
058e97ec | 1166 | |
a49ae217 | 1167 | /* Initialize the iterator I. */ |
cb3e0eac | 1168 | inline void |
a49ae217 BS |
1169 | ira_object_iter_init (ira_object_iterator *i) |
1170 | { | |
1171 | i->n = 0; | |
1172 | } | |
1173 | ||
1174 | /* Return TRUE if we have more objects to visit, in which case *OBJ is | |
1175 | set to the object to be visited. Otherwise, return FALSE. */ | |
cb3e0eac | 1176 | inline bool |
a49ae217 BS |
1177 | ira_object_iter_cond (ira_object_iterator *i, ira_object_t *obj) |
1178 | { | |
1179 | int n; | |
058e97ec | 1180 | |
a49ae217 BS |
1181 | for (n = i->n; n < ira_objects_num; n++) |
1182 | if (ira_object_id_map[n] != NULL) | |
1183 | { | |
1184 | *obj = ira_object_id_map[n]; | |
1185 | i->n = n + 1; | |
1186 | return true; | |
1187 | } | |
1188 | return false; | |
1189 | } | |
1190 | ||
ac0ab4f7 BS |
1191 | /* Loop over all objects. In each iteration, OBJ is set to the next |
1192 | object. ITER is an instance of ira_object_iterator used to iterate | |
a49ae217 BS |
1193 | the objects. */ |
1194 | #define FOR_EACH_OBJECT(OBJ, ITER) \ | |
1195 | for (ira_object_iter_init (&(ITER)); \ | |
1196 | ira_object_iter_cond (&(ITER), &(OBJ));) | |
058e97ec | 1197 | \f |
ac0ab4f7 | 1198 | /* The iterator for objects associated with an allocno. */ |
84562394 | 1199 | struct ira_allocno_object_iterator { |
ac0ab4f7 BS |
1200 | /* The number of the element the allocno's object array. */ |
1201 | int n; | |
84562394 | 1202 | }; |
ac0ab4f7 BS |
1203 | |
1204 | /* Initialize the iterator I. */ | |
cb3e0eac | 1205 | inline void |
ac0ab4f7 BS |
1206 | ira_allocno_object_iter_init (ira_allocno_object_iterator *i) |
1207 | { | |
1208 | i->n = 0; | |
1209 | } | |
1210 | ||
1211 | /* Return TRUE if we have more objects to visit in allocno A, in which | |
1212 | case *O is set to the object to be visited. Otherwise, return | |
1213 | FALSE. */ | |
cb3e0eac | 1214 | inline bool |
ac0ab4f7 BS |
1215 | ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a, |
1216 | ira_object_t *o) | |
1217 | { | |
d0a854af RG |
1218 | int n = i->n++; |
1219 | if (n < ALLOCNO_NUM_OBJECTS (a)) | |
1220 | { | |
1221 | *o = ALLOCNO_OBJECT (a, n); | |
1222 | return true; | |
1223 | } | |
1224 | return false; | |
ac0ab4f7 BS |
1225 | } |
1226 | ||
1227 | /* Loop over all objects associated with allocno A. In each | |
1228 | iteration, O is set to the next object. ITER is an instance of | |
1229 | ira_allocno_object_iterator used to iterate the conflicts. */ | |
1230 | #define FOR_EACH_ALLOCNO_OBJECT(A, O, ITER) \ | |
1231 | for (ira_allocno_object_iter_init (&(ITER)); \ | |
1232 | ira_allocno_object_iter_cond (&(ITER), (A), &(O));) | |
1233 | \f | |
058e97ec | 1234 | |
3b6d1699 | 1235 | /* The iterator for prefs. */ |
84562394 | 1236 | struct ira_pref_iterator { |
3b6d1699 VM |
1237 | /* The number of the current element in IRA_PREFS. */ |
1238 | int n; | |
84562394 | 1239 | }; |
3b6d1699 VM |
1240 | |
1241 | /* Initialize the iterator I. */ | |
cb3e0eac | 1242 | inline void |
3b6d1699 VM |
1243 | ira_pref_iter_init (ira_pref_iterator *i) |
1244 | { | |
1245 | i->n = 0; | |
1246 | } | |
1247 | ||
1248 | /* Return TRUE if we have more prefs to visit, in which case *PREF is | |
1249 | set to the pref to be visited. Otherwise, return FALSE. */ | |
cb3e0eac | 1250 | inline bool |
3b6d1699 VM |
1251 | ira_pref_iter_cond (ira_pref_iterator *i, ira_pref_t *pref) |
1252 | { | |
1253 | int n; | |
1254 | ||
1255 | for (n = i->n; n < ira_prefs_num; n++) | |
1256 | if (ira_prefs[n] != NULL) | |
1257 | { | |
1258 | *pref = ira_prefs[n]; | |
1259 | i->n = n + 1; | |
1260 | return true; | |
1261 | } | |
1262 | return false; | |
1263 | } | |
1264 | ||
1265 | /* Loop over all prefs. In each iteration, P is set to the next | |
1266 | pref. ITER is an instance of ira_pref_iterator used to iterate | |
1267 | the prefs. */ | |
1268 | #define FOR_EACH_PREF(P, ITER) \ | |
1269 | for (ira_pref_iter_init (&(ITER)); \ | |
1270 | ira_pref_iter_cond (&(ITER), &(P));) | |
1271 | \f | |
1272 | ||
058e97ec | 1273 | /* The iterator for copies. */ |
84562394 | 1274 | struct ira_copy_iterator { |
058e97ec VM |
1275 | /* The number of the current element in IRA_COPIES. */ |
1276 | int n; | |
84562394 | 1277 | }; |
058e97ec VM |
1278 | |
1279 | /* Initialize the iterator I. */ | |
cb3e0eac | 1280 | inline void |
058e97ec VM |
1281 | ira_copy_iter_init (ira_copy_iterator *i) |
1282 | { | |
1283 | i->n = 0; | |
1284 | } | |
1285 | ||
1286 | /* Return TRUE if we have more copies to visit, in which case *CP is | |
1287 | set to the copy to be visited. Otherwise, return FALSE. */ | |
cb3e0eac | 1288 | inline bool |
058e97ec VM |
1289 | ira_copy_iter_cond (ira_copy_iterator *i, ira_copy_t *cp) |
1290 | { | |
1291 | int n; | |
1292 | ||
1293 | for (n = i->n; n < ira_copies_num; n++) | |
1294 | if (ira_copies[n] != NULL) | |
1295 | { | |
1296 | *cp = ira_copies[n]; | |
1297 | i->n = n + 1; | |
1298 | return true; | |
1299 | } | |
1300 | return false; | |
1301 | } | |
1302 | ||
1303 | /* Loop over all copies. In each iteration, C is set to the next | |
1304 | copy. ITER is an instance of ira_copy_iterator used to iterate | |
1305 | the copies. */ | |
1306 | #define FOR_EACH_COPY(C, ITER) \ | |
1307 | for (ira_copy_iter_init (&(ITER)); \ | |
1308 | ira_copy_iter_cond (&(ITER), &(C));) | |
058e97ec | 1309 | \f |
ac0ab4f7 | 1310 | /* The iterator for object conflicts. */ |
84562394 | 1311 | struct ira_object_conflict_iterator { |
ac0ab4f7 BS |
1312 | |
1313 | /* TRUE if the conflicts are represented by vector of allocnos. */ | |
a49ae217 | 1314 | bool conflict_vec_p; |
058e97ec VM |
1315 | |
1316 | /* The conflict vector or conflict bit vector. */ | |
1317 | void *vec; | |
1318 | ||
1319 | /* The number of the current element in the vector (of type | |
a49ae217 | 1320 | ira_object_t or IRA_INT_TYPE). */ |
058e97ec VM |
1321 | unsigned int word_num; |
1322 | ||
1323 | /* The bit vector size. It is defined only if | |
a49ae217 | 1324 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec VM |
1325 | unsigned int size; |
1326 | ||
1327 | /* The current bit index of bit vector. It is defined only if | |
a49ae217 | 1328 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec VM |
1329 | unsigned int bit_num; |
1330 | ||
a49ae217 BS |
1331 | /* The object id corresponding to the 1st bit of the bit vector. It |
1332 | is defined only if OBJECT_CONFLICT_VEC_P is FALSE. */ | |
058e97ec VM |
1333 | int base_conflict_id; |
1334 | ||
1335 | /* The word of bit vector currently visited. It is defined only if | |
a49ae217 | 1336 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec | 1337 | unsigned IRA_INT_TYPE word; |
84562394 | 1338 | }; |
058e97ec VM |
1339 | |
1340 | /* Initialize the iterator I with ALLOCNO conflicts. */ | |
cb3e0eac | 1341 | inline void |
fa86d337 BS |
1342 | ira_object_conflict_iter_init (ira_object_conflict_iterator *i, |
1343 | ira_object_t obj) | |
058e97ec | 1344 | { |
a49ae217 BS |
1345 | i->conflict_vec_p = OBJECT_CONFLICT_VEC_P (obj); |
1346 | i->vec = OBJECT_CONFLICT_ARRAY (obj); | |
058e97ec | 1347 | i->word_num = 0; |
a49ae217 | 1348 | if (i->conflict_vec_p) |
058e97ec VM |
1349 | i->size = i->bit_num = i->base_conflict_id = i->word = 0; |
1350 | else | |
1351 | { | |
a49ae217 | 1352 | if (OBJECT_MIN (obj) > OBJECT_MAX (obj)) |
058e97ec VM |
1353 | i->size = 0; |
1354 | else | |
a49ae217 | 1355 | i->size = ((OBJECT_MAX (obj) - OBJECT_MIN (obj) |
058e97ec VM |
1356 | + IRA_INT_BITS) |
1357 | / IRA_INT_BITS) * sizeof (IRA_INT_TYPE); | |
1358 | i->bit_num = 0; | |
a49ae217 | 1359 | i->base_conflict_id = OBJECT_MIN (obj); |
058e97ec VM |
1360 | i->word = (i->size == 0 ? 0 : ((IRA_INT_TYPE *) i->vec)[0]); |
1361 | } | |
1362 | } | |
1363 | ||
1364 | /* Return TRUE if we have more conflicting allocnos to visit, in which | |
1365 | case *A is set to the allocno to be visited. Otherwise, return | |
1366 | FALSE. */ | |
cb3e0eac | 1367 | inline bool |
fa86d337 BS |
1368 | ira_object_conflict_iter_cond (ira_object_conflict_iterator *i, |
1369 | ira_object_t *pobj) | |
058e97ec | 1370 | { |
a49ae217 | 1371 | ira_object_t obj; |
058e97ec | 1372 | |
a49ae217 | 1373 | if (i->conflict_vec_p) |
058e97ec | 1374 | { |
1756cb66 | 1375 | obj = ((ira_object_t *) i->vec)[i->word_num++]; |
a49ae217 | 1376 | if (obj == NULL) |
058e97ec | 1377 | return false; |
058e97ec VM |
1378 | } |
1379 | else | |
1380 | { | |
1756cb66 VM |
1381 | unsigned IRA_INT_TYPE word = i->word; |
1382 | unsigned int bit_num = i->bit_num; | |
1383 | ||
058e97ec | 1384 | /* Skip words that are zeros. */ |
1756cb66 | 1385 | for (; word == 0; word = ((IRA_INT_TYPE *) i->vec)[i->word_num]) |
058e97ec VM |
1386 | { |
1387 | i->word_num++; | |
b8698a0f | 1388 | |
058e97ec VM |
1389 | /* If we have reached the end, break. */ |
1390 | if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size) | |
1391 | return false; | |
b8698a0f | 1392 | |
1756cb66 | 1393 | bit_num = i->word_num * IRA_INT_BITS; |
058e97ec | 1394 | } |
b8698a0f | 1395 | |
058e97ec | 1396 | /* Skip bits that are zero. */ |
a8250bba RB |
1397 | int off = ctz_hwi (word); |
1398 | bit_num += off; | |
1399 | word >>= off; | |
b8698a0f | 1400 | |
1756cb66 VM |
1401 | obj = ira_object_id_map[bit_num + i->base_conflict_id]; |
1402 | i->bit_num = bit_num + 1; | |
1403 | i->word = word >> 1; | |
058e97ec | 1404 | } |
a49ae217 | 1405 | |
fa86d337 | 1406 | *pobj = obj; |
a49ae217 | 1407 | return true; |
058e97ec VM |
1408 | } |
1409 | ||
fa86d337 BS |
1410 | /* Loop over all objects conflicting with OBJ. In each iteration, |
1411 | CONF is set to the next conflicting object. ITER is an instance | |
1412 | of ira_object_conflict_iterator used to iterate the conflicts. */ | |
1413 | #define FOR_EACH_OBJECT_CONFLICT(OBJ, CONF, ITER) \ | |
1414 | for (ira_object_conflict_iter_init (&(ITER), (OBJ)); \ | |
1756cb66 | 1415 | ira_object_conflict_iter_cond (&(ITER), &(CONF));) |
058e97ec VM |
1416 | |
1417 | \f | |
1418 | ||
1756cb66 VM |
1419 | /* The function returns TRUE if at least one hard register from ones |
1420 | starting with HARD_REGNO and containing value of MODE are in set | |
1421 | HARD_REGSET. */ | |
cb3e0eac | 1422 | inline bool |
ef4bddc2 | 1423 | ira_hard_reg_set_intersection_p (int hard_regno, machine_mode mode, |
1756cb66 VM |
1424 | HARD_REG_SET hard_regset) |
1425 | { | |
1426 | int i; | |
1427 | ||
1428 | gcc_assert (hard_regno >= 0); | |
ad474626 | 1429 | for (i = hard_regno_nregs (hard_regno, mode) - 1; i >= 0; i--) |
1756cb66 VM |
1430 | if (TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) |
1431 | return true; | |
1432 | return false; | |
1433 | } | |
1434 | ||
1435 | /* Return number of hard registers in hard register SET. */ | |
cb3e0eac | 1436 | inline int |
1756cb66 VM |
1437 | hard_reg_set_size (HARD_REG_SET set) |
1438 | { | |
1439 | int i, size; | |
1440 | ||
1441 | for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1442 | if (TEST_HARD_REG_BIT (set, i)) | |
1443 | size++; | |
1444 | return size; | |
1445 | } | |
1446 | ||
058e97ec | 1447 | /* The function returns TRUE if hard registers starting with |
9181a6e5 | 1448 | HARD_REGNO and containing value of MODE are fully in set |
058e97ec | 1449 | HARD_REGSET. */ |
cb3e0eac | 1450 | inline bool |
ef4bddc2 | 1451 | ira_hard_reg_in_set_p (int hard_regno, machine_mode mode, |
9181a6e5 | 1452 | HARD_REG_SET hard_regset) |
058e97ec VM |
1453 | { |
1454 | int i; | |
1455 | ||
1456 | ira_assert (hard_regno >= 0); | |
ad474626 | 1457 | for (i = hard_regno_nregs (hard_regno, mode) - 1; i >= 0; i--) |
9181a6e5 | 1458 | if (!TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) |
058e97ec VM |
1459 | return false; |
1460 | return true; | |
1461 | } | |
1462 | ||
1463 | \f | |
1464 | ||
1465 | /* To save memory we use a lazy approach for allocation and | |
1466 | initialization of the cost vectors. We do this only when it is | |
1467 | really necessary. */ | |
1468 | ||
1756cb66 | 1469 | /* Allocate cost vector *VEC for hard registers of ACLASS and |
058e97ec | 1470 | initialize the elements by VAL if it is necessary */ |
cb3e0eac | 1471 | inline void |
6f76a878 | 1472 | ira_allocate_and_set_costs (int **vec, reg_class_t aclass, int val) |
058e97ec VM |
1473 | { |
1474 | int i, *reg_costs; | |
1475 | int len; | |
1476 | ||
1477 | if (*vec != NULL) | |
1478 | return; | |
1756cb66 | 1479 | *vec = reg_costs = ira_allocate_cost_vector (aclass); |
6f76a878 | 1480 | len = ira_class_hard_regs_num[(int) aclass]; |
058e97ec VM |
1481 | for (i = 0; i < len; i++) |
1482 | reg_costs[i] = val; | |
1483 | } | |
1484 | ||
1756cb66 VM |
1485 | /* Allocate cost vector *VEC for hard registers of ACLASS and copy |
1486 | values of vector SRC into the vector if it is necessary */ | |
cb3e0eac | 1487 | inline void |
1756cb66 | 1488 | ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src) |
058e97ec VM |
1489 | { |
1490 | int len; | |
1491 | ||
1492 | if (*vec != NULL || src == NULL) | |
1493 | return; | |
1756cb66 VM |
1494 | *vec = ira_allocate_cost_vector (aclass); |
1495 | len = ira_class_hard_regs_num[aclass]; | |
058e97ec VM |
1496 | memcpy (*vec, src, sizeof (int) * len); |
1497 | } | |
1498 | ||
1756cb66 VM |
1499 | /* Allocate cost vector *VEC for hard registers of ACLASS and add |
1500 | values of vector SRC into the vector if it is necessary */ | |
cb3e0eac | 1501 | inline void |
1756cb66 | 1502 | ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src) |
058e97ec VM |
1503 | { |
1504 | int i, len; | |
1505 | ||
1506 | if (src == NULL) | |
1507 | return; | |
1756cb66 | 1508 | len = ira_class_hard_regs_num[aclass]; |
058e97ec VM |
1509 | if (*vec == NULL) |
1510 | { | |
1756cb66 | 1511 | *vec = ira_allocate_cost_vector (aclass); |
058e97ec VM |
1512 | memset (*vec, 0, sizeof (int) * len); |
1513 | } | |
1514 | for (i = 0; i < len; i++) | |
1515 | (*vec)[i] += src[i]; | |
1516 | } | |
1517 | ||
1756cb66 VM |
1518 | /* Allocate cost vector *VEC for hard registers of ACLASS and copy |
1519 | values of vector SRC into the vector or initialize it by VAL (if | |
1520 | SRC is null). */ | |
cb3e0eac | 1521 | inline void |
1756cb66 | 1522 | ira_allocate_and_set_or_copy_costs (int **vec, enum reg_class aclass, |
058e97ec VM |
1523 | int val, int *src) |
1524 | { | |
1525 | int i, *reg_costs; | |
1526 | int len; | |
1527 | ||
1528 | if (*vec != NULL) | |
1529 | return; | |
1756cb66 VM |
1530 | *vec = reg_costs = ira_allocate_cost_vector (aclass); |
1531 | len = ira_class_hard_regs_num[aclass]; | |
058e97ec VM |
1532 | if (src != NULL) |
1533 | memcpy (reg_costs, src, sizeof (int) * len); | |
1534 | else | |
1535 | { | |
1536 | for (i = 0; i < len; i++) | |
1537 | reg_costs[i] = val; | |
1538 | } | |
1539 | } | |
acf41a74 BS |
1540 | |
1541 | extern rtx ira_create_new_reg (rtx); | |
1542 | extern int first_moveable_pseudo, last_moveable_pseudo; | |
f1717f8d | 1543 | |
6c476222 RS |
1544 | /* Return the set of registers that would need a caller save if allocno A |
1545 | overlapped them. */ | |
1546 | ||
1547 | inline HARD_REG_SET | |
1548 | ira_need_caller_save_regs (ira_allocno_t a) | |
1549 | { | |
1550 | return call_clobbers_in_region (ALLOCNO_CROSSED_CALLS_ABIS (a), | |
1551 | ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), | |
1552 | ALLOCNO_MODE (a)); | |
1553 | } | |
1554 | ||
1555 | /* Return true if we would need to save allocno A around a call if we | |
1556 | assigned hard register REGNO. */ | |
1557 | ||
1558 | inline bool | |
1559 | ira_need_caller_save_p (ira_allocno_t a, unsigned int regno) | |
1560 | { | |
1561 | if (ALLOCNO_CALLS_CROSSED_NUM (a) == 0) | |
1562 | return false; | |
1563 | return call_clobbered_in_region_p (ALLOCNO_CROSSED_CALLS_ABIS (a), | |
1564 | ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), | |
1565 | ALLOCNO_MODE (a), regno); | |
1566 | } | |
1567 | ||
bf37fd35 RS |
1568 | /* Represents the boundary between an allocno in one loop and its parent |
1569 | allocno in the enclosing loop. It is usually possible to change a | |
1570 | register's allocation on this boundary; the class provides routines | |
1571 | for calculating the cost of such changes. */ | |
1572 | class ira_loop_border_costs | |
1573 | { | |
1574 | public: | |
1575 | ira_loop_border_costs (ira_allocno_t); | |
1576 | ||
1577 | int move_between_loops_cost () const; | |
1578 | int spill_outside_loop_cost () const; | |
1579 | int spill_inside_loop_cost () const; | |
1580 | ||
1581 | private: | |
1582 | /* The mode and class of the child allocno. */ | |
1583 | machine_mode m_mode; | |
1584 | reg_class m_class; | |
1585 | ||
1586 | /* Sums the frequencies of the entry edges and the exit edges. */ | |
1587 | int m_entry_freq, m_exit_freq; | |
1588 | }; | |
1589 | ||
1590 | /* Return the cost of storing the register on entry to the loop and | |
1591 | loading it back on exit from the loop. This is the cost to use if | |
1592 | the register is spilled within the loop but is successfully allocated | |
1593 | in the parent loop. */ | |
1594 | inline int | |
1595 | ira_loop_border_costs::spill_inside_loop_cost () const | |
1596 | { | |
1597 | return (m_entry_freq * ira_memory_move_cost[m_mode][m_class][0] | |
1598 | + m_exit_freq * ira_memory_move_cost[m_mode][m_class][1]); | |
1599 | } | |
1600 | ||
1601 | /* Return the cost of loading the register on entry to the loop and | |
1602 | storing it back on exit from the loop. This is the cost to use if | |
1603 | the register is successfully allocated within the loop but is spilled | |
1604 | in the parent loop. */ | |
1605 | inline int | |
1606 | ira_loop_border_costs::spill_outside_loop_cost () const | |
1607 | { | |
1608 | return (m_entry_freq * ira_memory_move_cost[m_mode][m_class][1] | |
1609 | + m_exit_freq * ira_memory_move_cost[m_mode][m_class][0]); | |
1610 | } | |
1611 | ||
1612 | /* Return the cost of moving the pseudo register between different hard | |
1613 | registers on entry and exit from the loop. This is the cost to use | |
1614 | if the register is successfully allocated within both this loop and | |
1615 | the parent loop, but the allocations for the loops differ. */ | |
1616 | inline int | |
1617 | ira_loop_border_costs::move_between_loops_cost () const | |
1618 | { | |
1619 | ira_init_register_move_cost_if_necessary (m_mode); | |
1620 | auto move_cost = ira_register_move_cost[m_mode][m_class][m_class]; | |
1621 | return move_cost * (m_entry_freq + m_exit_freq); | |
1622 | } | |
1623 | ||
d54565d8 RS |
1624 | /* Return true if subloops that contain allocnos for A's register can |
1625 | use a different assignment from A. ALLOCATED_P is true for the case | |
db8d94a0 RS |
1626 | in which allocation succeeded for A. EXCLUDE_OLD_RELOAD is true if |
1627 | we should always return false for non-LRA targets. (This is a hack | |
1628 | and should be removed along with old reload.) */ | |
d54565d8 | 1629 | inline bool |
db8d94a0 RS |
1630 | ira_subloop_allocnos_can_differ_p (ira_allocno_t a, bool allocated_p = true, |
1631 | bool exclude_old_reload = true) | |
d54565d8 | 1632 | { |
db8d94a0 RS |
1633 | if (exclude_old_reload && !ira_use_lra_p) |
1634 | return false; | |
1635 | ||
d54565d8 RS |
1636 | auto regno = ALLOCNO_REGNO (a); |
1637 | ||
1638 | if (pic_offset_table_rtx != NULL | |
1639 | && regno == (int) REGNO (pic_offset_table_rtx)) | |
1640 | return false; | |
1641 | ||
1642 | ira_assert (regno < ira_reg_equiv_len); | |
1643 | if (ira_equiv_no_lvalue_p (regno)) | |
1644 | return false; | |
1645 | ||
1646 | /* Avoid overlapping multi-registers. Moves between them might result | |
1647 | in wrong code generation. */ | |
1648 | if (allocated_p) | |
1649 | { | |
1650 | auto pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; | |
1651 | if (ira_reg_class_max_nregs[pclass][ALLOCNO_MODE (a)] > 1) | |
1652 | return false; | |
1653 | } | |
1654 | ||
1655 | return true; | |
1656 | } | |
1657 | ||
8e7a2372 RS |
1658 | /* Return true if we should treat A and SUBLOOP_A as belonging to a |
1659 | single region. */ | |
1660 | inline bool | |
1661 | ira_single_region_allocno_p (ira_allocno_t a, ira_allocno_t subloop_a) | |
1662 | { | |
1663 | if (flag_ira_region != IRA_REGION_MIXED) | |
1664 | return false; | |
1665 | ||
1666 | if (ALLOCNO_MIGHT_CONFLICT_WITH_PARENT_P (subloop_a)) | |
1667 | return false; | |
1668 | ||
1669 | auto rclass = ALLOCNO_CLASS (a); | |
1670 | auto pclass = ira_pressure_class_translate[rclass]; | |
1671 | auto loop_used_regs = ALLOCNO_LOOP_TREE_NODE (a)->reg_pressure[pclass]; | |
1672 | return loop_used_regs <= ira_class_hard_regs_num[pclass]; | |
1673 | } | |
1674 | ||
1675 | /* Return the set of all hard registers that conflict with A. */ | |
1676 | inline HARD_REG_SET | |
1677 | ira_total_conflict_hard_regs (ira_allocno_t a) | |
1678 | { | |
1679 | auto obj_0 = ALLOCNO_OBJECT (a, 0); | |
1680 | HARD_REG_SET conflicts = OBJECT_TOTAL_CONFLICT_HARD_REGS (obj_0); | |
1681 | for (int i = 1; i < ALLOCNO_NUM_OBJECTS (a); i++) | |
1682 | conflicts |= OBJECT_TOTAL_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a, i)); | |
1683 | return conflicts; | |
1684 | } | |
1685 | ||
01f3e6a4 RS |
1686 | /* Return the cost of saving a caller-saved register before each call |
1687 | in A's live range and restoring the same register after each call. */ | |
1688 | inline int | |
1689 | ira_caller_save_cost (ira_allocno_t a) | |
1690 | { | |
1691 | auto mode = ALLOCNO_MODE (a); | |
1692 | auto rclass = ALLOCNO_CLASS (a); | |
1693 | return (ALLOCNO_CALL_FREQ (a) | |
1694 | * (ira_memory_move_cost[mode][rclass][0] | |
1695 | + ira_memory_move_cost[mode][rclass][1])); | |
1696 | } | |
1697 | ||
1698 | /* A and SUBLOOP_A are allocnos for the same pseudo register, with A's | |
1699 | loop immediately enclosing SUBLOOP_A's loop. If we allocate to A a | |
1700 | hard register R that is clobbered by a call in SUBLOOP_A, decide | |
1701 | which of the following approaches should be used for handling the | |
1702 | conflict: | |
1703 | ||
1704 | (1) Spill R on entry to SUBLOOP_A's loop, assign memory to SUBLOOP_A, | |
1705 | and restore R on exit from SUBLOOP_A's loop. | |
1706 | ||
1707 | (2) Spill R before each necessary call in SUBLOOP_A's live range and | |
1708 | restore R after each such call. | |
1709 | ||
1710 | Return true if (1) is better than (2). SPILL_COST is the cost of | |
1711 | doing (1). */ | |
1712 | inline bool | |
1713 | ira_caller_save_loop_spill_p (ira_allocno_t a, ira_allocno_t subloop_a, | |
1714 | int spill_cost) | |
1715 | { | |
1716 | if (!ira_subloop_allocnos_can_differ_p (a)) | |
1717 | return false; | |
1718 | ||
1719 | /* Calculate the cost of saving a call-clobbered register | |
1720 | before each call and restoring it afterwards. */ | |
1721 | int call_cost = ira_caller_save_cost (subloop_a); | |
1722 | return call_cost && call_cost >= spill_cost; | |
1723 | } | |
1724 | ||
f1717f8d | 1725 | #endif /* GCC_IRA_INT_H */ |