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058e97ec | 1 | /* Integrated Register Allocator (IRA) intercommunication header file. |
23a5b65a | 2 | Copyright (C) 2006-2014 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
f1717f8d KC |
21 | #ifndef GCC_IRA_INT_H |
22 | #define GCC_IRA_INT_H | |
23 | ||
058e97ec VM |
24 | #include "cfgloop.h" |
25 | #include "ira.h" | |
26 | #include "alloc-pool.h" | |
27 | ||
28 | /* To provide consistency in naming, all IRA external variables, | |
29 | functions, common typedefs start with prefix ira_. */ | |
30 | ||
31 | #ifdef ENABLE_CHECKING | |
32 | #define ENABLE_IRA_CHECKING | |
33 | #endif | |
34 | ||
35 | #ifdef ENABLE_IRA_CHECKING | |
36 | #define ira_assert(c) gcc_assert (c) | |
37 | #else | |
f7556aae | 38 | /* Always define and include C, so that warnings for empty body in an |
7b3b6ae4 | 39 | 'if' statement and unused variable do not occur. */ |
f7556aae | 40 | #define ira_assert(c) ((void)(0 && (c))) |
058e97ec VM |
41 | #endif |
42 | ||
43 | /* Compute register frequency from edge frequency FREQ. It is | |
44 | analogous to REG_FREQ_FROM_BB. When optimizing for size, or | |
45 | profile driven feedback is available and the function is never | |
46 | executed, frequency is always equivalent. Otherwise rescale the | |
47 | edge frequency. */ | |
cf40f973 DC |
48 | #define REG_FREQ_FROM_EDGE_FREQ(freq) \ |
49 | (optimize_function_for_size_p (cfun) \ | |
fefa31b5 | 50 | ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \ |
058e97ec VM |
51 | ? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1) |
52 | ||
058e97ec VM |
53 | /* A modified value of flag `-fira-verbose' used internally. */ |
54 | extern int internal_flag_ira_verbose; | |
55 | ||
56 | /* Dump file of the allocator if it is not NULL. */ | |
57 | extern FILE *ira_dump_file; | |
58 | ||
59 | /* Typedefs for pointers to allocno live range, allocno, and copy of | |
60 | allocnos. */ | |
b14151b5 | 61 | typedef struct live_range *live_range_t; |
058e97ec | 62 | typedef struct ira_allocno *ira_allocno_t; |
3b6d1699 | 63 | typedef struct ira_allocno_pref *ira_pref_t; |
058e97ec | 64 | typedef struct ira_allocno_copy *ira_copy_t; |
a49ae217 | 65 | typedef struct ira_object *ira_object_t; |
058e97ec VM |
66 | |
67 | /* Definition of vector of allocnos and copies. */ | |
058e97ec VM |
68 | |
69 | /* Typedef for pointer to the subsequent structure. */ | |
70 | typedef struct ira_loop_tree_node *ira_loop_tree_node_t; | |
71 | ||
e80ccebc RS |
72 | typedef unsigned short move_table[N_REG_CLASSES]; |
73 | ||
058e97ec VM |
74 | /* In general case, IRA is a regional allocator. The regions are |
75 | nested and form a tree. Currently regions are natural loops. The | |
76 | following structure describes loop tree node (representing basic | |
77 | block or loop). We need such tree because the loop tree from | |
78 | cfgloop.h is not convenient for the optimization: basic blocks are | |
79 | not a part of the tree from cfgloop.h. We also use the nodes for | |
80 | storing additional information about basic blocks/loops for the | |
81 | register allocation purposes. */ | |
82 | struct ira_loop_tree_node | |
83 | { | |
84 | /* The node represents basic block if children == NULL. */ | |
85 | basic_block bb; /* NULL for loop. */ | |
2608d841 VM |
86 | /* NULL for BB or for loop tree root if we did not build CFG loop tree. */ |
87 | struct loop *loop; | |
af51c885 AN |
88 | /* NEXT/SUBLOOP_NEXT is the next node/loop-node of the same parent. |
89 | SUBLOOP_NEXT is always NULL for BBs. */ | |
058e97ec | 90 | ira_loop_tree_node_t subloop_next, next; |
af51c885 AN |
91 | /* CHILDREN/SUBLOOPS is the first node/loop-node immediately inside |
92 | the node. They are NULL for BBs. */ | |
058e97ec VM |
93 | ira_loop_tree_node_t subloops, children; |
94 | /* The node immediately containing given node. */ | |
95 | ira_loop_tree_node_t parent; | |
96 | ||
97 | /* Loop level in range [0, ira_loop_tree_height). */ | |
98 | int level; | |
99 | ||
100 | /* All the following members are defined only for nodes representing | |
101 | loops. */ | |
102 | ||
2608d841 VM |
103 | /* The loop number from CFG loop tree. The root number is 0. */ |
104 | int loop_num; | |
105 | ||
30ea859e VM |
106 | /* True if the loop was marked for removal from the register |
107 | allocation. */ | |
108 | bool to_remove_p; | |
109 | ||
058e97ec VM |
110 | /* Allocnos in the loop corresponding to their regnos. If it is |
111 | NULL the loop does not form a separate register allocation region | |
112 | (e.g. because it has abnormal enter/exit edges and we can not put | |
113 | code for register shuffling on the edges if a different | |
114 | allocation is used for a pseudo-register on different sides of | |
115 | the edges). Caps are not in the map (remember we can have more | |
116 | one cap with the same regno in a region). */ | |
117 | ira_allocno_t *regno_allocno_map; | |
118 | ||
ea1c67e6 VM |
119 | /* True if there is an entry to given loop not from its parent (or |
120 | grandparent) basic block. For example, it is possible for two | |
121 | adjacent loops inside another loop. */ | |
122 | bool entered_from_non_parent_p; | |
123 | ||
058e97ec | 124 | /* Maximal register pressure inside loop for given register class |
1756cb66 | 125 | (defined only for the pressure classes). */ |
058e97ec VM |
126 | int reg_pressure[N_REG_CLASSES]; |
127 | ||
49d988e7 VM |
128 | /* Numbers of allocnos referred or living in the loop node (except |
129 | for its subloops). */ | |
130 | bitmap all_allocnos; | |
131 | ||
132 | /* Numbers of allocnos living at the loop borders. */ | |
133 | bitmap border_allocnos; | |
058e97ec VM |
134 | |
135 | /* Regnos of pseudos modified in the loop node (including its | |
136 | subloops). */ | |
137 | bitmap modified_regnos; | |
138 | ||
058e97ec VM |
139 | /* Numbers of copies referred in the corresponding loop. */ |
140 | bitmap local_copies; | |
141 | }; | |
142 | ||
143 | /* The root of the loop tree corresponding to the all function. */ | |
144 | extern ira_loop_tree_node_t ira_loop_tree_root; | |
145 | ||
146 | /* Height of the loop tree. */ | |
147 | extern int ira_loop_tree_height; | |
148 | ||
149 | /* All nodes representing basic blocks are referred through the | |
150 | following array. We can not use basic block member `aux' for this | |
151 | because it is used for insertion of insns on edges. */ | |
152 | extern ira_loop_tree_node_t ira_bb_nodes; | |
153 | ||
154 | /* Two access macros to the nodes representing basic blocks. */ | |
155 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
156 | #define IRA_BB_NODE_BY_INDEX(index) __extension__ \ | |
2608d841 | 157 | (({ ira_loop_tree_node_t _node = (&ira_bb_nodes[index]); \ |
058e97ec VM |
158 | if (_node->children != NULL || _node->loop != NULL || _node->bb == NULL)\ |
159 | { \ | |
160 | fprintf (stderr, \ | |
161 | "\n%s: %d: error in %s: it is not a block node\n", \ | |
162 | __FILE__, __LINE__, __FUNCTION__); \ | |
163 | gcc_unreachable (); \ | |
164 | } \ | |
165 | _node; })) | |
166 | #else | |
167 | #define IRA_BB_NODE_BY_INDEX(index) (&ira_bb_nodes[index]) | |
168 | #endif | |
169 | ||
170 | #define IRA_BB_NODE(bb) IRA_BB_NODE_BY_INDEX ((bb)->index) | |
171 | ||
172 | /* All nodes representing loops are referred through the following | |
173 | array. */ | |
174 | extern ira_loop_tree_node_t ira_loop_nodes; | |
175 | ||
176 | /* Two access macros to the nodes representing loops. */ | |
177 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
178 | #define IRA_LOOP_NODE_BY_INDEX(index) __extension__ \ | |
2608d841 VM |
179 | (({ ira_loop_tree_node_t const _node = (&ira_loop_nodes[index]); \ |
180 | if (_node->children == NULL || _node->bb != NULL \ | |
181 | || (_node->loop == NULL && current_loops != NULL)) \ | |
058e97ec VM |
182 | { \ |
183 | fprintf (stderr, \ | |
184 | "\n%s: %d: error in %s: it is not a loop node\n", \ | |
185 | __FILE__, __LINE__, __FUNCTION__); \ | |
186 | gcc_unreachable (); \ | |
187 | } \ | |
188 | _node; })) | |
189 | #else | |
190 | #define IRA_LOOP_NODE_BY_INDEX(index) (&ira_loop_nodes[index]) | |
191 | #endif | |
192 | ||
193 | #define IRA_LOOP_NODE(loop) IRA_LOOP_NODE_BY_INDEX ((loop)->num) | |
194 | ||
195 | \f | |
058e97ec | 196 | /* The structure describes program points where a given allocno lives. |
1756cb66 VM |
197 | If the live ranges of two allocnos are intersected, the allocnos |
198 | are in conflict. */ | |
b14151b5 | 199 | struct live_range |
058e97ec | 200 | { |
ac0ab4f7 | 201 | /* Object whose live range is described by given structure. */ |
9140d27b | 202 | ira_object_t object; |
058e97ec VM |
203 | /* Program point range. */ |
204 | int start, finish; | |
205 | /* Next structure describing program points where the allocno | |
206 | lives. */ | |
b14151b5 | 207 | live_range_t next; |
058e97ec | 208 | /* Pointer to structures with the same start/finish. */ |
b14151b5 | 209 | live_range_t start_next, finish_next; |
058e97ec VM |
210 | }; |
211 | ||
212 | /* Program points are enumerated by numbers from range | |
213 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
214 | points than insns. Program points are places in the program where | |
215 | liveness info can be changed. In most general case (there are more | |
216 | complicated cases too) some program points correspond to places | |
217 | where input operand dies and other ones correspond to places where | |
218 | output operands are born. */ | |
219 | extern int ira_max_point; | |
220 | ||
221 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
222 | live ranges with given start/finish point. */ | |
b14151b5 | 223 | extern live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec | 224 | |
a49ae217 BS |
225 | /* A structure representing conflict information for an allocno |
226 | (or one of its subwords). */ | |
227 | struct ira_object | |
228 | { | |
229 | /* The allocno associated with this record. */ | |
230 | ira_allocno_t allocno; | |
231 | /* Vector of accumulated conflicting conflict_redords with NULL end | |
232 | marker (if OBJECT_CONFLICT_VEC_P is true) or conflict bit vector | |
1756cb66 | 233 | otherwise. */ |
a49ae217 | 234 | void *conflicts_array; |
9140d27b BS |
235 | /* Pointer to structures describing at what program point the |
236 | object lives. We always maintain the list in such way that *the | |
237 | ranges in the list are not intersected and ordered by decreasing | |
238 | their program points*. */ | |
239 | live_range_t live_ranges; | |
ac0ab4f7 BS |
240 | /* The subword within ALLOCNO which is represented by this object. |
241 | Zero means the lowest-order subword (or the entire allocno in case | |
242 | it is not being tracked in subwords). */ | |
243 | int subword; | |
9140d27b | 244 | /* Allocated size of the conflicts array. */ |
a49ae217 | 245 | unsigned int conflicts_array_size; |
ac0ab4f7 | 246 | /* A unique number for every instance of this structure, which is used |
a49ae217 BS |
247 | to represent it in conflict bit vectors. */ |
248 | int id; | |
249 | /* Before building conflicts, MIN and MAX are initialized to | |
250 | correspondingly minimal and maximal points of the accumulated | |
ac0ab4f7 BS |
251 | live ranges. Afterwards, they hold the minimal and maximal ids |
252 | of other ira_objects that this one can conflict with. */ | |
a49ae217 BS |
253 | int min, max; |
254 | /* Initial and accumulated hard registers conflicting with this | |
ac0ab4f7 | 255 | object and as a consequences can not be assigned to the allocno. |
1756cb66 | 256 | All non-allocatable hard regs and hard regs of register classes |
ac0ab4f7 | 257 | different from given allocno one are included in the sets. */ |
a49ae217 BS |
258 | HARD_REG_SET conflict_hard_regs, total_conflict_hard_regs; |
259 | /* Number of accumulated conflicts in the vector of conflicting | |
ac0ab4f7 | 260 | objects. */ |
a49ae217 BS |
261 | int num_accumulated_conflicts; |
262 | /* TRUE if conflicts are represented by a vector of pointers to | |
263 | ira_object structures. Otherwise, we use a bit vector indexed | |
264 | by conflict ID numbers. */ | |
265 | unsigned int conflict_vec_p : 1; | |
266 | }; | |
267 | ||
058e97ec VM |
268 | /* A structure representing an allocno (allocation entity). Allocno |
269 | represents a pseudo-register in an allocation region. If | |
270 | pseudo-register does not live in a region but it lives in the | |
271 | nested regions, it is represented in the region by special allocno | |
272 | called *cap*. There may be more one cap representing the same | |
273 | pseudo-register in region. It means that the corresponding | |
274 | pseudo-register lives in more one non-intersected subregion. */ | |
275 | struct ira_allocno | |
276 | { | |
277 | /* The allocno order number starting with 0. Each allocno has an | |
278 | unique number and the number is never changed for the | |
279 | allocno. */ | |
280 | int num; | |
281 | /* Regno for allocno or cap. */ | |
282 | int regno; | |
283 | /* Mode of the allocno which is the mode of the corresponding | |
284 | pseudo-register. */ | |
1756cb66 | 285 | ENUM_BITFIELD (machine_mode) mode : 8; |
d1bb282e DS |
286 | /* Widest mode of the allocno which in at least one case could be |
287 | for paradoxical subregs where wmode > mode. */ | |
288 | ENUM_BITFIELD (machine_mode) wmode : 8; | |
1756cb66 VM |
289 | /* Register class which should be used for allocation for given |
290 | allocno. NO_REGS means that we should use memory. */ | |
291 | ENUM_BITFIELD (reg_class) aclass : 16; | |
292 | /* During the reload, value TRUE means that we should not reassign a | |
293 | hard register to the allocno got memory earlier. It is set up | |
294 | when we removed memory-memory move insn before each iteration of | |
295 | the reload. */ | |
296 | unsigned int dont_reassign_p : 1; | |
297 | #ifdef STACK_REGS | |
298 | /* Set to TRUE if allocno can't be assigned to the stack hard | |
299 | register correspondingly in this region and area including the | |
300 | region and all its subregions recursively. */ | |
301 | unsigned int no_stack_reg_p : 1, total_no_stack_reg_p : 1; | |
302 | #endif | |
303 | /* TRUE value means that there is no sense to spill the allocno | |
304 | during coloring because the spill will result in additional | |
305 | reloads in reload pass. */ | |
306 | unsigned int bad_spill_p : 1; | |
307 | /* TRUE if a hard register or memory has been assigned to the | |
308 | allocno. */ | |
309 | unsigned int assigned_p : 1; | |
310 | /* TRUE if conflicts for given allocno are represented by vector of | |
311 | pointers to the conflicting allocnos. Otherwise, we use a bit | |
312 | vector where a bit with given index represents allocno with the | |
313 | same number. */ | |
314 | unsigned int conflict_vec_p : 1; | |
058e97ec VM |
315 | /* Hard register assigned to given allocno. Negative value means |
316 | that memory was allocated to the allocno. During the reload, | |
317 | spilled allocno has value equal to the corresponding stack slot | |
318 | number (0, ...) - 2. Value -1 is used for allocnos spilled by the | |
319 | reload (at this point pseudo-register has only one allocno) which | |
320 | did not get stack slot yet. */ | |
8684302d | 321 | signed int hard_regno : 16; |
058e97ec VM |
322 | /* Allocnos with the same regno are linked by the following member. |
323 | Allocnos corresponding to inner loops are first in the list (it | |
324 | corresponds to depth-first traverse of the loops). */ | |
325 | ira_allocno_t next_regno_allocno; | |
326 | /* There may be different allocnos with the same regno in different | |
327 | regions. Allocnos are bound to the corresponding loop tree node. | |
328 | Pseudo-register may have only one regular allocno with given loop | |
329 | tree node but more than one cap (see comments above). */ | |
330 | ira_loop_tree_node_t loop_tree_node; | |
331 | /* Accumulated usage references of the allocno. Here and below, | |
332 | word 'accumulated' means info for given region and all nested | |
333 | subregions. In this case, 'accumulated' means sum of references | |
334 | of the corresponding pseudo-register in this region and in all | |
335 | nested subregions recursively. */ | |
336 | int nrefs; | |
337 | /* Accumulated frequency of usage of the allocno. */ | |
338 | int freq; | |
cb1ca6ac | 339 | /* Minimal accumulated and updated costs of usage register of the |
1756cb66 VM |
340 | allocno class. */ |
341 | int class_cost, updated_class_cost; | |
058e97ec VM |
342 | /* Minimal accumulated, and updated costs of memory for the allocno. |
343 | At the allocation start, the original and updated costs are | |
344 | equal. The updated cost may be changed after finishing | |
345 | allocation in a region and starting allocation in a subregion. | |
346 | The change reflects the cost of spill/restore code on the | |
347 | subregion border if we assign memory to the pseudo in the | |
348 | subregion. */ | |
349 | int memory_cost, updated_memory_cost; | |
350 | /* Accumulated number of points where the allocno lives and there is | |
351 | excess pressure for its class. Excess pressure for a register | |
352 | class at some point means that there are more allocnos of given | |
353 | register class living at the point than number of hard-registers | |
354 | of the class available for the allocation. */ | |
355 | int excess_pressure_points_num; | |
3b6d1699 VM |
356 | /* Allocno hard reg preferences. */ |
357 | ira_pref_t allocno_prefs; | |
058e97ec VM |
358 | /* Copies to other non-conflicting allocnos. The copies can |
359 | represent move insn or potential move insn usually because of two | |
360 | operand insn constraints. */ | |
361 | ira_copy_t allocno_copies; | |
362 | /* It is a allocno (cap) representing given allocno on upper loop tree | |
363 | level. */ | |
364 | ira_allocno_t cap; | |
365 | /* It is a link to allocno (cap) on lower loop level represented by | |
366 | given cap. Null if given allocno is not a cap. */ | |
367 | ira_allocno_t cap_member; | |
ac0ab4f7 BS |
368 | /* The number of objects tracked in the following array. */ |
369 | int num_objects; | |
370 | /* An array of structures describing conflict information and live | |
371 | ranges for each object associated with the allocno. There may be | |
372 | more than one such object in cases where the allocno represents a | |
373 | multi-word register. */ | |
374 | ira_object_t objects[2]; | |
058e97ec VM |
375 | /* Accumulated frequency of calls which given allocno |
376 | intersects. */ | |
377 | int call_freq; | |
a812fb07 | 378 | /* Accumulated number of the intersected calls. */ |
058e97ec | 379 | int calls_crossed_num; |
e384e6b5 BS |
380 | /* The number of calls across which it is live, but which should not |
381 | affect register preferences. */ | |
382 | int cheap_calls_crossed_num; | |
c2ba7e7a RO |
383 | /* Registers clobbered by intersected calls. */ |
384 | HARD_REG_SET crossed_calls_clobbered_regs; | |
058e97ec | 385 | /* Array of usage costs (accumulated and the one updated during |
1756cb66 | 386 | coloring) for each hard register of the allocno class. The |
058e97ec | 387 | member value can be NULL if all costs are the same and equal to |
1756cb66 | 388 | CLASS_COST. For example, the costs of two different hard |
058e97ec VM |
389 | registers can be different if one hard register is callee-saved |
390 | and another one is callee-used and the allocno lives through | |
391 | calls. Another example can be case when for some insn the | |
392 | corresponding pseudo-register value should be put in specific | |
393 | register class (e.g. AREG for x86) which is a strict subset of | |
1756cb66 VM |
394 | the allocno class (GENERAL_REGS for x86). We have updated costs |
395 | to reflect the situation when the usage cost of a hard register | |
396 | is decreased because the allocno is connected to another allocno | |
397 | by a copy and the another allocno has been assigned to the hard | |
398 | register. */ | |
058e97ec VM |
399 | int *hard_reg_costs, *updated_hard_reg_costs; |
400 | /* Array of decreasing costs (accumulated and the one updated during | |
401 | coloring) for allocnos conflicting with given allocno for hard | |
1756cb66 VM |
402 | regno of the allocno class. The member value can be NULL if all |
403 | costs are the same. These costs are used to reflect preferences | |
404 | of other allocnos not assigned yet during assigning to given | |
405 | allocno. */ | |
058e97ec | 406 | int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs; |
1756cb66 VM |
407 | /* Different additional data. It is used to decrease size of |
408 | allocno data footprint. */ | |
409 | void *add_data; | |
058e97ec VM |
410 | }; |
411 | ||
1756cb66 | 412 | |
058e97ec VM |
413 | /* All members of the allocno structures should be accessed only |
414 | through the following macros. */ | |
415 | #define ALLOCNO_NUM(A) ((A)->num) | |
416 | #define ALLOCNO_REGNO(A) ((A)->regno) | |
417 | #define ALLOCNO_REG(A) ((A)->reg) | |
418 | #define ALLOCNO_NEXT_REGNO_ALLOCNO(A) ((A)->next_regno_allocno) | |
419 | #define ALLOCNO_LOOP_TREE_NODE(A) ((A)->loop_tree_node) | |
420 | #define ALLOCNO_CAP(A) ((A)->cap) | |
421 | #define ALLOCNO_CAP_MEMBER(A) ((A)->cap_member) | |
058e97ec VM |
422 | #define ALLOCNO_NREFS(A) ((A)->nrefs) |
423 | #define ALLOCNO_FREQ(A) ((A)->freq) | |
424 | #define ALLOCNO_HARD_REGNO(A) ((A)->hard_regno) | |
425 | #define ALLOCNO_CALL_FREQ(A) ((A)->call_freq) | |
426 | #define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num) | |
e384e6b5 | 427 | #define ALLOCNO_CHEAP_CALLS_CROSSED_NUM(A) ((A)->cheap_calls_crossed_num) |
c2ba7e7a RO |
428 | #define ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS(A) \ |
429 | ((A)->crossed_calls_clobbered_regs) | |
058e97ec VM |
430 | #define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest) |
431 | #define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p) | |
432 | #define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p) | |
433 | #define ALLOCNO_CHILD_RENAMED_P(A) ((A)->child_renamed_p) | |
434 | #define ALLOCNO_DONT_REASSIGN_P(A) ((A)->dont_reassign_p) | |
435 | #ifdef STACK_REGS | |
436 | #define ALLOCNO_NO_STACK_REG_P(A) ((A)->no_stack_reg_p) | |
437 | #define ALLOCNO_TOTAL_NO_STACK_REG_P(A) ((A)->total_no_stack_reg_p) | |
438 | #endif | |
927425df | 439 | #define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p) |
058e97ec | 440 | #define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p) |
058e97ec | 441 | #define ALLOCNO_MODE(A) ((A)->mode) |
d1bb282e | 442 | #define ALLOCNO_WMODE(A) ((A)->wmode) |
3b6d1699 | 443 | #define ALLOCNO_PREFS(A) ((A)->allocno_prefs) |
058e97ec VM |
444 | #define ALLOCNO_COPIES(A) ((A)->allocno_copies) |
445 | #define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs) | |
446 | #define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs) | |
447 | #define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \ | |
448 | ((A)->conflict_hard_reg_costs) | |
449 | #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \ | |
450 | ((A)->updated_conflict_hard_reg_costs) | |
1756cb66 VM |
451 | #define ALLOCNO_CLASS(A) ((A)->aclass) |
452 | #define ALLOCNO_CLASS_COST(A) ((A)->class_cost) | |
453 | #define ALLOCNO_UPDATED_CLASS_COST(A) ((A)->updated_class_cost) | |
058e97ec VM |
454 | #define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost) |
455 | #define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost) | |
1756cb66 VM |
456 | #define ALLOCNO_EXCESS_PRESSURE_POINTS_NUM(A) \ |
457 | ((A)->excess_pressure_points_num) | |
ac0ab4f7 BS |
458 | #define ALLOCNO_OBJECT(A,N) ((A)->objects[N]) |
459 | #define ALLOCNO_NUM_OBJECTS(A) ((A)->num_objects) | |
1756cb66 | 460 | #define ALLOCNO_ADD_DATA(A) ((A)->add_data) |
a49ae217 | 461 | |
1756cb66 VM |
462 | /* Typedef for pointer to the subsequent structure. */ |
463 | typedef struct ira_emit_data *ira_emit_data_t; | |
464 | ||
465 | /* Allocno bound data used for emit pseudo live range split insns and | |
466 | to flattening IR. */ | |
467 | struct ira_emit_data | |
468 | { | |
469 | /* TRUE if the allocno assigned to memory was a destination of | |
470 | removed move (see ira-emit.c) at loop exit because the value of | |
471 | the corresponding pseudo-register is not changed inside the | |
472 | loop. */ | |
473 | unsigned int mem_optimized_dest_p : 1; | |
474 | /* TRUE if the corresponding pseudo-register has disjoint live | |
475 | ranges and the other allocnos of the pseudo-register except this | |
476 | one changed REG. */ | |
477 | unsigned int somewhere_renamed_p : 1; | |
478 | /* TRUE if allocno with the same REGNO in a subregion has been | |
479 | renamed, in other words, got a new pseudo-register. */ | |
480 | unsigned int child_renamed_p : 1; | |
481 | /* Final rtx representation of the allocno. */ | |
482 | rtx reg; | |
483 | /* Non NULL if we remove restoring value from given allocno to | |
484 | MEM_OPTIMIZED_DEST at loop exit (see ira-emit.c) because the | |
485 | allocno value is not changed inside the loop. */ | |
486 | ira_allocno_t mem_optimized_dest; | |
487 | }; | |
488 | ||
489 | #define ALLOCNO_EMIT_DATA(a) ((ira_emit_data_t) ALLOCNO_ADD_DATA (a)) | |
490 | ||
491 | /* Data used to emit live range split insns and to flattening IR. */ | |
492 | extern ira_emit_data_t ira_allocno_emit_data; | |
493 | ||
494 | /* Abbreviation for frequent emit data access. */ | |
495 | static inline rtx | |
496 | allocno_emit_reg (ira_allocno_t a) | |
497 | { | |
498 | return ALLOCNO_EMIT_DATA (a)->reg; | |
499 | } | |
500 | ||
501 | #define OBJECT_ALLOCNO(O) ((O)->allocno) | |
502 | #define OBJECT_SUBWORD(O) ((O)->subword) | |
503 | #define OBJECT_CONFLICT_ARRAY(O) ((O)->conflicts_array) | |
504 | #define OBJECT_CONFLICT_VEC(O) ((ira_object_t *)(O)->conflicts_array) | |
505 | #define OBJECT_CONFLICT_BITVEC(O) ((IRA_INT_TYPE *)(O)->conflicts_array) | |
506 | #define OBJECT_CONFLICT_ARRAY_SIZE(O) ((O)->conflicts_array_size) | |
507 | #define OBJECT_CONFLICT_VEC_P(O) ((O)->conflict_vec_p) | |
508 | #define OBJECT_NUM_CONFLICTS(O) ((O)->num_accumulated_conflicts) | |
509 | #define OBJECT_CONFLICT_HARD_REGS(O) ((O)->conflict_hard_regs) | |
510 | #define OBJECT_TOTAL_CONFLICT_HARD_REGS(O) ((O)->total_conflict_hard_regs) | |
511 | #define OBJECT_MIN(O) ((O)->min) | |
512 | #define OBJECT_MAX(O) ((O)->max) | |
513 | #define OBJECT_CONFLICT_ID(O) ((O)->id) | |
514 | #define OBJECT_LIVE_RANGES(O) ((O)->live_ranges) | |
058e97ec | 515 | |
b8698a0f | 516 | /* Map regno -> allocnos with given regno (see comments for |
058e97ec VM |
517 | allocno member `next_regno_allocno'). */ |
518 | extern ira_allocno_t *ira_regno_allocno_map; | |
519 | ||
520 | /* Array of references to all allocnos. The order number of the | |
521 | allocno corresponds to the index in the array. Removed allocnos | |
522 | have NULL element value. */ | |
523 | extern ira_allocno_t *ira_allocnos; | |
524 | ||
a49ae217 | 525 | /* The size of the previous array. */ |
058e97ec VM |
526 | extern int ira_allocnos_num; |
527 | ||
a49ae217 BS |
528 | /* Map a conflict id to its corresponding ira_object structure. */ |
529 | extern ira_object_t *ira_object_id_map; | |
530 | ||
531 | /* The size of the previous array. */ | |
532 | extern int ira_objects_num; | |
058e97ec | 533 | |
3b6d1699 VM |
534 | /* The following structure represents a hard register prefererence of |
535 | allocno. The preference represent move insns or potential move | |
536 | insns usually because of two operand insn constraints. One move | |
537 | operand is a hard register. */ | |
538 | struct ira_allocno_pref | |
539 | { | |
540 | /* The unique order number of the preference node starting with 0. */ | |
541 | int num; | |
542 | /* Preferred hard register. */ | |
543 | int hard_regno; | |
544 | /* Accumulated execution frequency of insns from which the | |
545 | preference created. */ | |
546 | int freq; | |
547 | /* Given allocno. */ | |
548 | ira_allocno_t allocno; | |
549 | /* All prefernces with the same allocno are linked by the following | |
550 | member. */ | |
551 | ira_pref_t next_pref; | |
552 | }; | |
553 | ||
554 | /* Array of references to all allocno preferences. The order number | |
555 | of the preference corresponds to the index in the array. */ | |
556 | extern ira_pref_t *ira_prefs; | |
557 | ||
558 | /* Size of the previous array. */ | |
559 | extern int ira_prefs_num; | |
560 | ||
058e97ec VM |
561 | /* The following structure represents a copy of two allocnos. The |
562 | copies represent move insns or potential move insns usually because | |
563 | of two operand insn constraints. To remove register shuffle, we | |
564 | also create copies between allocno which is output of an insn and | |
565 | allocno becoming dead in the insn. */ | |
566 | struct ira_allocno_copy | |
567 | { | |
568 | /* The unique order number of the copy node starting with 0. */ | |
569 | int num; | |
570 | /* Allocnos connected by the copy. The first allocno should have | |
571 | smaller order number than the second one. */ | |
572 | ira_allocno_t first, second; | |
573 | /* Execution frequency of the copy. */ | |
574 | int freq; | |
548a6322 | 575 | bool constraint_p; |
058e97ec VM |
576 | /* It is a move insn which is an origin of the copy. The member |
577 | value for the copy representing two operand insn constraints or | |
578 | for the copy created to remove register shuffle is NULL. In last | |
579 | case the copy frequency is smaller than the corresponding insn | |
580 | execution frequency. */ | |
070a1983 | 581 | rtx_insn *insn; |
058e97ec VM |
582 | /* All copies with the same allocno as FIRST are linked by the two |
583 | following members. */ | |
584 | ira_copy_t prev_first_allocno_copy, next_first_allocno_copy; | |
585 | /* All copies with the same allocno as SECOND are linked by the two | |
586 | following members. */ | |
587 | ira_copy_t prev_second_allocno_copy, next_second_allocno_copy; | |
588 | /* Region from which given copy is originated. */ | |
589 | ira_loop_tree_node_t loop_tree_node; | |
590 | }; | |
591 | ||
592 | /* Array of references to all copies. The order number of the copy | |
593 | corresponds to the index in the array. Removed copies have NULL | |
594 | element value. */ | |
595 | extern ira_copy_t *ira_copies; | |
596 | ||
597 | /* Size of the previous array. */ | |
598 | extern int ira_copies_num; | |
599 | ||
600 | /* The following structure describes a stack slot used for spilled | |
601 | pseudo-registers. */ | |
602 | struct ira_spilled_reg_stack_slot | |
603 | { | |
604 | /* pseudo-registers assigned to the stack slot. */ | |
7a8cba34 | 605 | bitmap_head spilled_regs; |
058e97ec VM |
606 | /* RTL representation of the stack slot. */ |
607 | rtx mem; | |
608 | /* Size of the stack slot. */ | |
609 | unsigned int width; | |
610 | }; | |
611 | ||
612 | /* The number of elements in the following array. */ | |
613 | extern int ira_spilled_reg_stack_slots_num; | |
614 | ||
615 | /* The following array contains info about spilled pseudo-registers | |
616 | stack slots used in current function so far. */ | |
617 | extern struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
618 | ||
619 | /* Correspondingly overall cost of the allocation, cost of the | |
620 | allocnos assigned to hard-registers, cost of the allocnos assigned | |
621 | to memory, cost of loads, stores and register move insns generated | |
622 | for pseudo-register live range splitting (see ira-emit.c). */ | |
623 | extern int ira_overall_cost; | |
624 | extern int ira_reg_cost, ira_mem_cost; | |
625 | extern int ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
626 | extern int ira_move_loops_num, ira_additional_jumps_num; | |
1756cb66 | 627 | |
42ce1cc4 BS |
628 | \f |
629 | /* This page contains a bitset implementation called 'min/max sets' used to | |
630 | record conflicts in IRA. | |
631 | They are named min/maxs set since we keep track of a minimum and a maximum | |
632 | bit number for each set representing the bounds of valid elements. Otherwise, | |
633 | the implementation resembles sbitmaps in that we store an array of integers | |
634 | whose bits directly represent the members of the set. */ | |
635 | ||
636 | /* The type used as elements in the array, and the number of bits in | |
637 | this type. */ | |
ac0ab4f7 | 638 | |
058e97ec VM |
639 | #define IRA_INT_BITS HOST_BITS_PER_WIDE_INT |
640 | #define IRA_INT_TYPE HOST_WIDE_INT | |
641 | ||
642 | /* Set, clear or test bit number I in R, a bit vector of elements with | |
643 | minimal index and maximal index equal correspondingly to MIN and | |
644 | MAX. */ | |
645 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
646 | ||
42ce1cc4 | 647 | #define SET_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
648 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
649 | if (_i < _min || _i > _max) \ | |
650 | { \ | |
651 | fprintf (stderr, \ | |
652 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
653 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
654 | gcc_unreachable (); \ | |
655 | } \ | |
656 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
657 | |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
b8698a0f | 658 | |
058e97ec | 659 | |
42ce1cc4 | 660 | #define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
661 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
662 | if (_i < _min || _i > _max) \ | |
663 | { \ | |
664 | fprintf (stderr, \ | |
665 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
666 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
667 | gcc_unreachable (); \ | |
668 | } \ | |
669 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
670 | &= ~((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
671 | ||
42ce1cc4 | 672 | #define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
673 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
674 | if (_i < _min || _i > _max) \ | |
675 | { \ | |
676 | fprintf (stderr, \ | |
677 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
678 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
679 | gcc_unreachable (); \ | |
680 | } \ | |
681 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
682 | & ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
683 | ||
684 | #else | |
685 | ||
42ce1cc4 | 686 | #define SET_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
687 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
688 | |= ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
689 | ||
42ce1cc4 | 690 | #define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
691 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
692 | &= ~((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
693 | ||
42ce1cc4 | 694 | #define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
695 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
696 | & ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
697 | ||
698 | #endif | |
699 | ||
42ce1cc4 | 700 | /* The iterator for min/max sets. */ |
84562394 | 701 | struct minmax_set_iterator { |
058e97ec | 702 | |
42ce1cc4 | 703 | /* Array containing the bit vector. */ |
058e97ec VM |
704 | IRA_INT_TYPE *vec; |
705 | ||
706 | /* The number of the current element in the vector. */ | |
707 | unsigned int word_num; | |
708 | ||
709 | /* The number of bits in the bit vector. */ | |
710 | unsigned int nel; | |
711 | ||
712 | /* The current bit index of the bit vector. */ | |
713 | unsigned int bit_num; | |
714 | ||
715 | /* Index corresponding to the 1st bit of the bit vector. */ | |
716 | int start_val; | |
717 | ||
718 | /* The word of the bit vector currently visited. */ | |
719 | unsigned IRA_INT_TYPE word; | |
84562394 | 720 | }; |
058e97ec | 721 | |
42ce1cc4 BS |
722 | /* Initialize the iterator I for bit vector VEC containing minimal and |
723 | maximal values MIN and MAX. */ | |
058e97ec | 724 | static inline void |
42ce1cc4 BS |
725 | minmax_set_iter_init (minmax_set_iterator *i, IRA_INT_TYPE *vec, int min, |
726 | int max) | |
058e97ec VM |
727 | { |
728 | i->vec = vec; | |
729 | i->word_num = 0; | |
730 | i->nel = max < min ? 0 : max - min + 1; | |
731 | i->start_val = min; | |
732 | i->bit_num = 0; | |
733 | i->word = i->nel == 0 ? 0 : vec[0]; | |
734 | } | |
735 | ||
ac0ab4f7 | 736 | /* Return TRUE if we have more allocnos to visit, in which case *N is |
42ce1cc4 | 737 | set to the number of the element to be visited. Otherwise, return |
058e97ec VM |
738 | FALSE. */ |
739 | static inline bool | |
42ce1cc4 | 740 | minmax_set_iter_cond (minmax_set_iterator *i, int *n) |
058e97ec VM |
741 | { |
742 | /* Skip words that are zeros. */ | |
743 | for (; i->word == 0; i->word = i->vec[i->word_num]) | |
744 | { | |
745 | i->word_num++; | |
746 | i->bit_num = i->word_num * IRA_INT_BITS; | |
b8698a0f | 747 | |
058e97ec VM |
748 | /* If we have reached the end, break. */ |
749 | if (i->bit_num >= i->nel) | |
750 | return false; | |
751 | } | |
b8698a0f | 752 | |
058e97ec VM |
753 | /* Skip bits that are zero. */ |
754 | for (; (i->word & 1) == 0; i->word >>= 1) | |
755 | i->bit_num++; | |
b8698a0f | 756 | |
058e97ec | 757 | *n = (int) i->bit_num + i->start_val; |
b8698a0f | 758 | |
058e97ec VM |
759 | return true; |
760 | } | |
761 | ||
42ce1cc4 | 762 | /* Advance to the next element in the set. */ |
058e97ec | 763 | static inline void |
42ce1cc4 | 764 | minmax_set_iter_next (minmax_set_iterator *i) |
058e97ec VM |
765 | { |
766 | i->word >>= 1; | |
767 | i->bit_num++; | |
768 | } | |
769 | ||
42ce1cc4 | 770 | /* Loop over all elements of a min/max set given by bit vector VEC and |
058e97ec VM |
771 | their minimal and maximal values MIN and MAX. In each iteration, N |
772 | is set to the number of next allocno. ITER is an instance of | |
42ce1cc4 BS |
773 | minmax_set_iterator used to iterate over the set. */ |
774 | #define FOR_EACH_BIT_IN_MINMAX_SET(VEC, MIN, MAX, N, ITER) \ | |
775 | for (minmax_set_iter_init (&(ITER), (VEC), (MIN), (MAX)); \ | |
776 | minmax_set_iter_cond (&(ITER), &(N)); \ | |
777 | minmax_set_iter_next (&(ITER))) | |
778 | \f | |
afcc66c4 | 779 | struct target_ira_int { |
19c708dc RS |
780 | ~target_ira_int (); |
781 | ||
782 | void free_ira_costs (); | |
783 | void free_register_move_costs (); | |
784 | ||
aa1c5d72 RS |
785 | /* Initialized once. It is a maximal possible size of the allocated |
786 | struct costs. */ | |
787 | int x_max_struct_costs_size; | |
788 | ||
789 | /* Allocated and initialized once, and used to initialize cost values | |
790 | for each insn. */ | |
791 | struct costs *x_init_cost; | |
792 | ||
793 | /* Allocated once, and used for temporary purposes. */ | |
794 | struct costs *x_temp_costs; | |
795 | ||
796 | /* Allocated once, and used for the cost calculation. */ | |
797 | struct costs *x_op_costs[MAX_RECOG_OPERANDS]; | |
798 | struct costs *x_this_op_costs[MAX_RECOG_OPERANDS]; | |
799 | ||
afcc66c4 RS |
800 | /* Hard registers that can not be used for the register allocator for |
801 | all functions of the current compilation unit. */ | |
802 | HARD_REG_SET x_no_unit_alloc_regs; | |
803 | ||
804 | /* Map: hard regs X modes -> set of hard registers for storing value | |
805 | of given mode starting with given hard register. */ | |
806 | HARD_REG_SET (x_ira_reg_mode_hard_regset | |
807 | [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]); | |
808 | ||
e80ccebc RS |
809 | /* Maximum cost of moving from a register in one class to a register |
810 | in another class. Based on TARGET_REGISTER_MOVE_COST. */ | |
7cc61ee4 | 811 | move_table *x_ira_register_move_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
812 | |
813 | /* Similar, but here we don't have to move if the first index is a | |
814 | subset of the second so in that case the cost is zero. */ | |
7cc61ee4 | 815 | move_table *x_ira_may_move_in_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
816 | |
817 | /* Similar, but here we don't have to move if the first index is a | |
818 | superset of the second so in that case the cost is zero. */ | |
7cc61ee4 | 819 | move_table *x_ira_may_move_out_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
820 | |
821 | /* Keep track of the last mode we initialized move costs for. */ | |
822 | int x_last_mode_for_init_move_cost; | |
823 | ||
7cc61ee4 RS |
824 | /* Array analog of the macro MEMORY_MOVE_COST but they contain maximal |
825 | cost not minimal. */ | |
1756cb66 | 826 | short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; |
1756cb66 VM |
827 | |
828 | /* Map class->true if class is a possible allocno class, false | |
829 | otherwise. */ | |
830 | bool x_ira_reg_allocno_class_p[N_REG_CLASSES]; | |
831 | ||
832 | /* Map class->true if class is a pressure class, false otherwise. */ | |
833 | bool x_ira_reg_pressure_class_p[N_REG_CLASSES]; | |
834 | ||
afcc66c4 | 835 | /* Array of the number of hard registers of given class which are |
dd5a833e | 836 | available for allocation. The order is defined by the hard |
afcc66c4 RS |
837 | register numbers. */ |
838 | short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
839 | ||
840 | /* Index (in ira_class_hard_regs; for given register class and hard | |
841 | register (in general case a hard register can belong to several | |
842 | register classes;. The index is negative for hard registers | |
843 | unavailable for the allocation. */ | |
844 | short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
845 | ||
846 | /* Array whose values are hard regset of hard registers available for | |
847 | the allocation of given register class whose HARD_REGNO_MODE_OK | |
848 | values for given mode are zero. */ | |
1756cb66 | 849 | HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; |
afcc66c4 | 850 | |
a2c19e93 RS |
851 | /* Index [CL][M] contains R if R appears somewhere in a register of the form: |
852 | ||
853 | (reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M] | |
854 | ||
855 | For example, if: | |
856 | ||
857 | - (reg:M 2) is valid and occupies two registers; | |
858 | - register 2 belongs to CL; and | |
859 | - register 3 belongs to the same pressure class as CL | |
860 | ||
861 | then (reg:M 2) contributes to [CL][M] and registers 2 and 3 will be | |
862 | in the set. */ | |
863 | HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; | |
864 | ||
afcc66c4 RS |
865 | /* The value is number of elements in the subsequent array. */ |
866 | int x_ira_important_classes_num; | |
867 | ||
1756cb66 | 868 | /* The array containing all non-empty classes. Such classes is |
afcc66c4 RS |
869 | important for calculation of the hard register usage costs. */ |
870 | enum reg_class x_ira_important_classes[N_REG_CLASSES]; | |
871 | ||
1756cb66 VM |
872 | /* The array containing indexes of important classes in the previous |
873 | array. The array elements are defined only for important | |
874 | classes. */ | |
875 | int x_ira_important_class_nums[N_REG_CLASSES]; | |
876 | ||
165f639c VM |
877 | /* Map class->true if class is an uniform class, false otherwise. */ |
878 | bool x_ira_uniform_class_p[N_REG_CLASSES]; | |
879 | ||
afcc66c4 RS |
880 | /* The biggest important class inside of intersection of the two |
881 | classes (that is calculated taking only hard registers available | |
882 | for allocation into account;. If the both classes contain no hard | |
883 | registers available for allocation, the value is calculated with | |
884 | taking all hard-registers including fixed ones into account. */ | |
885 | enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES]; | |
886 | ||
afcc66c4 | 887 | /* Classes with end marker LIM_REG_CLASSES which are intersected with |
55a2c322 | 888 | given class (the first index). That includes given class itself. |
afcc66c4 RS |
889 | This is calculated taking only hard registers available for |
890 | allocation into account. */ | |
891 | enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES]; | |
892 | ||
1756cb66 VM |
893 | /* The biggest (smallest) important class inside of (covering) union |
894 | of the two classes (that is calculated taking only hard registers | |
895 | available for allocation into account). If the both classes | |
896 | contain no hard registers available for allocation, the value is | |
897 | calculated with taking all hard-registers including fixed ones | |
898 | into account. In other words, the value is the corresponding | |
899 | reg_class_subunion (reg_class_superunion) value. */ | |
900 | enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
901 | enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
afcc66c4 RS |
902 | |
903 | /* For each reg class, table listing all the classes contained in it | |
904 | (excluding the class itself. Non-allocatable registers are | |
55a2c322 | 905 | excluded from the consideration). */ |
afcc66c4 | 906 | enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; |
15e7b94f RS |
907 | |
908 | /* Array whose values are hard regset of hard registers for which | |
909 | move of the hard register in given mode into itself is | |
910 | prohibited. */ | |
911 | HARD_REG_SET x_ira_prohibited_mode_move_regs[NUM_MACHINE_MODES]; | |
912 | ||
913 | /* Flag of that the above array has been initialized. */ | |
914 | bool x_ira_prohibited_mode_move_regs_initialized_p; | |
afcc66c4 RS |
915 | }; |
916 | ||
917 | extern struct target_ira_int default_target_ira_int; | |
918 | #if SWITCHABLE_TARGET | |
919 | extern struct target_ira_int *this_target_ira_int; | |
920 | #else | |
921 | #define this_target_ira_int (&default_target_ira_int) | |
922 | #endif | |
058e97ec | 923 | |
afcc66c4 RS |
924 | #define ira_reg_mode_hard_regset \ |
925 | (this_target_ira_int->x_ira_reg_mode_hard_regset) | |
926 | #define ira_register_move_cost \ | |
927 | (this_target_ira_int->x_ira_register_move_cost) | |
1756cb66 VM |
928 | #define ira_max_memory_move_cost \ |
929 | (this_target_ira_int->x_ira_max_memory_move_cost) | |
afcc66c4 RS |
930 | #define ira_may_move_in_cost \ |
931 | (this_target_ira_int->x_ira_may_move_in_cost) | |
932 | #define ira_may_move_out_cost \ | |
933 | (this_target_ira_int->x_ira_may_move_out_cost) | |
1756cb66 VM |
934 | #define ira_reg_allocno_class_p \ |
935 | (this_target_ira_int->x_ira_reg_allocno_class_p) | |
936 | #define ira_reg_pressure_class_p \ | |
937 | (this_target_ira_int->x_ira_reg_pressure_class_p) | |
afcc66c4 RS |
938 | #define ira_non_ordered_class_hard_regs \ |
939 | (this_target_ira_int->x_ira_non_ordered_class_hard_regs) | |
940 | #define ira_class_hard_reg_index \ | |
941 | (this_target_ira_int->x_ira_class_hard_reg_index) | |
1756cb66 VM |
942 | #define ira_prohibited_class_mode_regs \ |
943 | (this_target_ira_int->x_ira_prohibited_class_mode_regs) | |
a2c19e93 RS |
944 | #define ira_useful_class_mode_regs \ |
945 | (this_target_ira_int->x_ira_useful_class_mode_regs) | |
afcc66c4 RS |
946 | #define ira_important_classes_num \ |
947 | (this_target_ira_int->x_ira_important_classes_num) | |
948 | #define ira_important_classes \ | |
949 | (this_target_ira_int->x_ira_important_classes) | |
1756cb66 VM |
950 | #define ira_important_class_nums \ |
951 | (this_target_ira_int->x_ira_important_class_nums) | |
165f639c VM |
952 | #define ira_uniform_class_p \ |
953 | (this_target_ira_int->x_ira_uniform_class_p) | |
afcc66c4 RS |
954 | #define ira_reg_class_intersect \ |
955 | (this_target_ira_int->x_ira_reg_class_intersect) | |
afcc66c4 RS |
956 | #define ira_reg_class_super_classes \ |
957 | (this_target_ira_int->x_ira_reg_class_super_classes) | |
1756cb66 VM |
958 | #define ira_reg_class_subunion \ |
959 | (this_target_ira_int->x_ira_reg_class_subunion) | |
960 | #define ira_reg_class_superunion \ | |
961 | (this_target_ira_int->x_ira_reg_class_superunion) | |
15e7b94f RS |
962 | #define ira_prohibited_mode_move_regs \ |
963 | (this_target_ira_int->x_ira_prohibited_mode_move_regs) | |
afcc66c4 RS |
964 | \f |
965 | /* ira.c: */ | |
058e97ec | 966 | |
058e97ec | 967 | extern void *ira_allocate (size_t); |
058e97ec VM |
968 | extern void ira_free (void *addr); |
969 | extern bitmap ira_allocate_bitmap (void); | |
970 | extern void ira_free_bitmap (bitmap); | |
971 | extern void ira_print_disposition (FILE *); | |
972 | extern void ira_debug_disposition (void); | |
1756cb66 | 973 | extern void ira_debug_allocno_classes (void); |
058e97ec | 974 | extern void ira_init_register_move_cost (enum machine_mode); |
647d790d | 975 | extern void ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts); |
3b6d1699 | 976 | extern int ira_get_dup_out_num (int op_num, HARD_REG_SET &alts); |
058e97ec | 977 | |
058e97ec VM |
978 | /* ira-build.c */ |
979 | ||
980 | /* The current loop tree node and its regno allocno map. */ | |
981 | extern ira_loop_tree_node_t ira_curr_loop_tree_node; | |
982 | extern ira_allocno_t *ira_curr_regno_allocno_map; | |
983 | ||
3b6d1699 VM |
984 | extern void ira_debug_pref (ira_pref_t); |
985 | extern void ira_debug_prefs (void); | |
986 | extern void ira_debug_allocno_prefs (ira_allocno_t); | |
987 | ||
4cda38d5 | 988 | extern void ira_debug_copy (ira_copy_t); |
7b3b6ae4 LC |
989 | extern void debug (ira_allocno_copy &ref); |
990 | extern void debug (ira_allocno_copy *ptr); | |
991 | ||
4cda38d5 | 992 | extern void ira_debug_copies (void); |
058e97ec | 993 | extern void ira_debug_allocno_copies (ira_allocno_t); |
7b3b6ae4 LC |
994 | extern void debug (ira_allocno &ref); |
995 | extern void debug (ira_allocno *ptr); | |
058e97ec VM |
996 | |
997 | extern void ira_traverse_loop_tree (bool, ira_loop_tree_node_t, | |
998 | void (*) (ira_loop_tree_node_t), | |
999 | void (*) (ira_loop_tree_node_t)); | |
029da7d4 BS |
1000 | extern ira_allocno_t ira_parent_allocno (ira_allocno_t); |
1001 | extern ira_allocno_t ira_parent_or_cap_allocno (ira_allocno_t); | |
058e97ec | 1002 | extern ira_allocno_t ira_create_allocno (int, bool, ira_loop_tree_node_t); |
ac0ab4f7 | 1003 | extern void ira_create_allocno_objects (ira_allocno_t); |
1756cb66 | 1004 | extern void ira_set_allocno_class (ira_allocno_t, enum reg_class); |
a49ae217 BS |
1005 | extern bool ira_conflict_vector_profitable_p (ira_object_t, int); |
1006 | extern void ira_allocate_conflict_vec (ira_object_t, int); | |
1007 | extern void ira_allocate_object_conflicts (ira_object_t, int); | |
ac0ab4f7 | 1008 | extern void ior_hard_reg_conflicts (ira_allocno_t, HARD_REG_SET *); |
058e97ec | 1009 | extern void ira_print_expanded_allocno (ira_allocno_t); |
ac0ab4f7 | 1010 | extern void ira_add_live_range_to_object (ira_object_t, int, int); |
9140d27b BS |
1011 | extern live_range_t ira_create_live_range (ira_object_t, int, int, |
1012 | live_range_t); | |
1013 | extern live_range_t ira_copy_live_range_list (live_range_t); | |
1014 | extern live_range_t ira_merge_live_ranges (live_range_t, live_range_t); | |
1015 | extern bool ira_live_ranges_intersect_p (live_range_t, live_range_t); | |
1016 | extern void ira_finish_live_range (live_range_t); | |
1017 | extern void ira_finish_live_range_list (live_range_t); | |
058e97ec | 1018 | extern void ira_free_allocno_updated_costs (ira_allocno_t); |
3b6d1699 VM |
1019 | extern ira_pref_t ira_create_pref (ira_allocno_t, int, int); |
1020 | extern void ira_add_allocno_pref (ira_allocno_t, int, int); | |
1021 | extern void ira_remove_pref (ira_pref_t); | |
1022 | extern void ira_remove_allocno_prefs (ira_allocno_t); | |
058e97ec | 1023 | extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t, |
070a1983 DM |
1024 | int, bool, rtx_insn *, |
1025 | ira_loop_tree_node_t); | |
548a6322 | 1026 | extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int, |
070a1983 DM |
1027 | bool, rtx_insn *, |
1028 | ira_loop_tree_node_t); | |
058e97ec | 1029 | |
6f76a878 AS |
1030 | extern int *ira_allocate_cost_vector (reg_class_t); |
1031 | extern void ira_free_cost_vector (int *, reg_class_t); | |
058e97ec VM |
1032 | |
1033 | extern void ira_flattening (int, int); | |
2608d841 | 1034 | extern bool ira_build (void); |
058e97ec VM |
1035 | extern void ira_destroy (void); |
1036 | ||
1037 | /* ira-costs.c */ | |
1038 | extern void ira_init_costs_once (void); | |
1039 | extern void ira_init_costs (void); | |
058e97ec | 1040 | extern void ira_costs (void); |
1756cb66 | 1041 | extern void ira_tune_allocno_costs (void); |
058e97ec VM |
1042 | |
1043 | /* ira-lives.c */ | |
1044 | ||
1045 | extern void ira_rebuild_start_finish_chains (void); | |
b14151b5 | 1046 | extern void ira_print_live_range_list (FILE *, live_range_t); |
7b3b6ae4 LC |
1047 | extern void debug (live_range &ref); |
1048 | extern void debug (live_range *ptr); | |
b14151b5 | 1049 | extern void ira_debug_live_range_list (live_range_t); |
058e97ec VM |
1050 | extern void ira_debug_allocno_live_ranges (ira_allocno_t); |
1051 | extern void ira_debug_live_ranges (void); | |
1052 | extern void ira_create_allocno_live_ranges (void); | |
b15a7ae6 | 1053 | extern void ira_compress_allocno_live_ranges (void); |
058e97ec VM |
1054 | extern void ira_finish_allocno_live_ranges (void); |
1055 | ||
1056 | /* ira-conflicts.c */ | |
058e97ec VM |
1057 | extern void ira_debug_conflicts (bool); |
1058 | extern void ira_build_conflicts (void); | |
1059 | ||
1060 | /* ira-color.c */ | |
1756cb66 | 1061 | extern void ira_debug_hard_regs_forest (void); |
058e97ec VM |
1062 | extern int ira_loop_edge_freq (ira_loop_tree_node_t, int, bool); |
1063 | extern void ira_reassign_conflict_allocnos (int); | |
1064 | extern void ira_initiate_assign (void); | |
1065 | extern void ira_finish_assign (void); | |
1066 | extern void ira_color (void); | |
058e97ec VM |
1067 | |
1068 | /* ira-emit.c */ | |
1756cb66 VM |
1069 | extern void ira_initiate_emit_data (void); |
1070 | extern void ira_finish_emit_data (void); | |
058e97ec VM |
1071 | extern void ira_emit (bool); |
1072 | ||
1073 | \f | |
1074 | ||
55a2c322 VM |
1075 | /* Return true if equivalence of pseudo REGNO is not a lvalue. */ |
1076 | static inline bool | |
1077 | ira_equiv_no_lvalue_p (int regno) | |
1078 | { | |
1079 | if (regno >= ira_reg_equiv_len) | |
1080 | return false; | |
1081 | return (ira_reg_equiv[regno].constant != NULL_RTX | |
1082 | || ira_reg_equiv[regno].invariant != NULL_RTX | |
1083 | || (ira_reg_equiv[regno].memory != NULL_RTX | |
1084 | && MEM_READONLY_P (ira_reg_equiv[regno].memory))); | |
1085 | } | |
1086 | ||
1087 | \f | |
1088 | ||
1756cb66 VM |
1089 | /* Initialize register costs for MODE if necessary. */ |
1090 | static inline void | |
1091 | ira_init_register_move_cost_if_necessary (enum machine_mode mode) | |
6080348f VM |
1092 | { |
1093 | if (ira_register_move_cost[mode] == NULL) | |
1094 | ira_init_register_move_cost (mode); | |
6080348f VM |
1095 | } |
1096 | ||
1097 | \f | |
1098 | ||
058e97ec | 1099 | /* The iterator for all allocnos. */ |
84562394 | 1100 | struct ira_allocno_iterator { |
058e97ec VM |
1101 | /* The number of the current element in IRA_ALLOCNOS. */ |
1102 | int n; | |
84562394 | 1103 | }; |
058e97ec VM |
1104 | |
1105 | /* Initialize the iterator I. */ | |
1106 | static inline void | |
1107 | ira_allocno_iter_init (ira_allocno_iterator *i) | |
1108 | { | |
1109 | i->n = 0; | |
1110 | } | |
1111 | ||
1112 | /* Return TRUE if we have more allocnos to visit, in which case *A is | |
1113 | set to the allocno to be visited. Otherwise, return FALSE. */ | |
1114 | static inline bool | |
1115 | ira_allocno_iter_cond (ira_allocno_iterator *i, ira_allocno_t *a) | |
1116 | { | |
1117 | int n; | |
1118 | ||
1119 | for (n = i->n; n < ira_allocnos_num; n++) | |
1120 | if (ira_allocnos[n] != NULL) | |
1121 | { | |
1122 | *a = ira_allocnos[n]; | |
1123 | i->n = n + 1; | |
1124 | return true; | |
1125 | } | |
1126 | return false; | |
1127 | } | |
1128 | ||
1129 | /* Loop over all allocnos. In each iteration, A is set to the next | |
1130 | allocno. ITER is an instance of ira_allocno_iterator used to iterate | |
1131 | the allocnos. */ | |
1132 | #define FOR_EACH_ALLOCNO(A, ITER) \ | |
1133 | for (ira_allocno_iter_init (&(ITER)); \ | |
1134 | ira_allocno_iter_cond (&(ITER), &(A));) | |
a49ae217 BS |
1135 | \f |
1136 | /* The iterator for all objects. */ | |
84562394 | 1137 | struct ira_object_iterator { |
ac0ab4f7 | 1138 | /* The number of the current element in ira_object_id_map. */ |
a49ae217 | 1139 | int n; |
84562394 | 1140 | }; |
058e97ec | 1141 | |
a49ae217 BS |
1142 | /* Initialize the iterator I. */ |
1143 | static inline void | |
1144 | ira_object_iter_init (ira_object_iterator *i) | |
1145 | { | |
1146 | i->n = 0; | |
1147 | } | |
1148 | ||
1149 | /* Return TRUE if we have more objects to visit, in which case *OBJ is | |
1150 | set to the object to be visited. Otherwise, return FALSE. */ | |
1151 | static inline bool | |
1152 | ira_object_iter_cond (ira_object_iterator *i, ira_object_t *obj) | |
1153 | { | |
1154 | int n; | |
058e97ec | 1155 | |
a49ae217 BS |
1156 | for (n = i->n; n < ira_objects_num; n++) |
1157 | if (ira_object_id_map[n] != NULL) | |
1158 | { | |
1159 | *obj = ira_object_id_map[n]; | |
1160 | i->n = n + 1; | |
1161 | return true; | |
1162 | } | |
1163 | return false; | |
1164 | } | |
1165 | ||
ac0ab4f7 BS |
1166 | /* Loop over all objects. In each iteration, OBJ is set to the next |
1167 | object. ITER is an instance of ira_object_iterator used to iterate | |
a49ae217 BS |
1168 | the objects. */ |
1169 | #define FOR_EACH_OBJECT(OBJ, ITER) \ | |
1170 | for (ira_object_iter_init (&(ITER)); \ | |
1171 | ira_object_iter_cond (&(ITER), &(OBJ));) | |
058e97ec | 1172 | \f |
ac0ab4f7 | 1173 | /* The iterator for objects associated with an allocno. */ |
84562394 | 1174 | struct ira_allocno_object_iterator { |
ac0ab4f7 BS |
1175 | /* The number of the element the allocno's object array. */ |
1176 | int n; | |
84562394 | 1177 | }; |
ac0ab4f7 BS |
1178 | |
1179 | /* Initialize the iterator I. */ | |
1180 | static inline void | |
1181 | ira_allocno_object_iter_init (ira_allocno_object_iterator *i) | |
1182 | { | |
1183 | i->n = 0; | |
1184 | } | |
1185 | ||
1186 | /* Return TRUE if we have more objects to visit in allocno A, in which | |
1187 | case *O is set to the object to be visited. Otherwise, return | |
1188 | FALSE. */ | |
1189 | static inline bool | |
1190 | ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a, | |
1191 | ira_object_t *o) | |
1192 | { | |
d0a854af RG |
1193 | int n = i->n++; |
1194 | if (n < ALLOCNO_NUM_OBJECTS (a)) | |
1195 | { | |
1196 | *o = ALLOCNO_OBJECT (a, n); | |
1197 | return true; | |
1198 | } | |
1199 | return false; | |
ac0ab4f7 BS |
1200 | } |
1201 | ||
1202 | /* Loop over all objects associated with allocno A. In each | |
1203 | iteration, O is set to the next object. ITER is an instance of | |
1204 | ira_allocno_object_iterator used to iterate the conflicts. */ | |
1205 | #define FOR_EACH_ALLOCNO_OBJECT(A, O, ITER) \ | |
1206 | for (ira_allocno_object_iter_init (&(ITER)); \ | |
1207 | ira_allocno_object_iter_cond (&(ITER), (A), &(O));) | |
1208 | \f | |
058e97ec | 1209 | |
3b6d1699 | 1210 | /* The iterator for prefs. */ |
84562394 | 1211 | struct ira_pref_iterator { |
3b6d1699 VM |
1212 | /* The number of the current element in IRA_PREFS. */ |
1213 | int n; | |
84562394 | 1214 | }; |
3b6d1699 VM |
1215 | |
1216 | /* Initialize the iterator I. */ | |
1217 | static inline void | |
1218 | ira_pref_iter_init (ira_pref_iterator *i) | |
1219 | { | |
1220 | i->n = 0; | |
1221 | } | |
1222 | ||
1223 | /* Return TRUE if we have more prefs to visit, in which case *PREF is | |
1224 | set to the pref to be visited. Otherwise, return FALSE. */ | |
1225 | static inline bool | |
1226 | ira_pref_iter_cond (ira_pref_iterator *i, ira_pref_t *pref) | |
1227 | { | |
1228 | int n; | |
1229 | ||
1230 | for (n = i->n; n < ira_prefs_num; n++) | |
1231 | if (ira_prefs[n] != NULL) | |
1232 | { | |
1233 | *pref = ira_prefs[n]; | |
1234 | i->n = n + 1; | |
1235 | return true; | |
1236 | } | |
1237 | return false; | |
1238 | } | |
1239 | ||
1240 | /* Loop over all prefs. In each iteration, P is set to the next | |
1241 | pref. ITER is an instance of ira_pref_iterator used to iterate | |
1242 | the prefs. */ | |
1243 | #define FOR_EACH_PREF(P, ITER) \ | |
1244 | for (ira_pref_iter_init (&(ITER)); \ | |
1245 | ira_pref_iter_cond (&(ITER), &(P));) | |
1246 | \f | |
1247 | ||
058e97ec | 1248 | /* The iterator for copies. */ |
84562394 | 1249 | struct ira_copy_iterator { |
058e97ec VM |
1250 | /* The number of the current element in IRA_COPIES. */ |
1251 | int n; | |
84562394 | 1252 | }; |
058e97ec VM |
1253 | |
1254 | /* Initialize the iterator I. */ | |
1255 | static inline void | |
1256 | ira_copy_iter_init (ira_copy_iterator *i) | |
1257 | { | |
1258 | i->n = 0; | |
1259 | } | |
1260 | ||
1261 | /* Return TRUE if we have more copies to visit, in which case *CP is | |
1262 | set to the copy to be visited. Otherwise, return FALSE. */ | |
1263 | static inline bool | |
1264 | ira_copy_iter_cond (ira_copy_iterator *i, ira_copy_t *cp) | |
1265 | { | |
1266 | int n; | |
1267 | ||
1268 | for (n = i->n; n < ira_copies_num; n++) | |
1269 | if (ira_copies[n] != NULL) | |
1270 | { | |
1271 | *cp = ira_copies[n]; | |
1272 | i->n = n + 1; | |
1273 | return true; | |
1274 | } | |
1275 | return false; | |
1276 | } | |
1277 | ||
1278 | /* Loop over all copies. In each iteration, C is set to the next | |
1279 | copy. ITER is an instance of ira_copy_iterator used to iterate | |
1280 | the copies. */ | |
1281 | #define FOR_EACH_COPY(C, ITER) \ | |
1282 | for (ira_copy_iter_init (&(ITER)); \ | |
1283 | ira_copy_iter_cond (&(ITER), &(C));) | |
058e97ec | 1284 | \f |
ac0ab4f7 | 1285 | /* The iterator for object conflicts. */ |
84562394 | 1286 | struct ira_object_conflict_iterator { |
ac0ab4f7 BS |
1287 | |
1288 | /* TRUE if the conflicts are represented by vector of allocnos. */ | |
a49ae217 | 1289 | bool conflict_vec_p; |
058e97ec VM |
1290 | |
1291 | /* The conflict vector or conflict bit vector. */ | |
1292 | void *vec; | |
1293 | ||
1294 | /* The number of the current element in the vector (of type | |
a49ae217 | 1295 | ira_object_t or IRA_INT_TYPE). */ |
058e97ec VM |
1296 | unsigned int word_num; |
1297 | ||
1298 | /* The bit vector size. It is defined only if | |
a49ae217 | 1299 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec VM |
1300 | unsigned int size; |
1301 | ||
1302 | /* The current bit index of bit vector. It is defined only if | |
a49ae217 | 1303 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec VM |
1304 | unsigned int bit_num; |
1305 | ||
a49ae217 BS |
1306 | /* The object id corresponding to the 1st bit of the bit vector. It |
1307 | is defined only if OBJECT_CONFLICT_VEC_P is FALSE. */ | |
058e97ec VM |
1308 | int base_conflict_id; |
1309 | ||
1310 | /* The word of bit vector currently visited. It is defined only if | |
a49ae217 | 1311 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec | 1312 | unsigned IRA_INT_TYPE word; |
84562394 | 1313 | }; |
058e97ec VM |
1314 | |
1315 | /* Initialize the iterator I with ALLOCNO conflicts. */ | |
1316 | static inline void | |
fa86d337 BS |
1317 | ira_object_conflict_iter_init (ira_object_conflict_iterator *i, |
1318 | ira_object_t obj) | |
058e97ec | 1319 | { |
a49ae217 BS |
1320 | i->conflict_vec_p = OBJECT_CONFLICT_VEC_P (obj); |
1321 | i->vec = OBJECT_CONFLICT_ARRAY (obj); | |
058e97ec | 1322 | i->word_num = 0; |
a49ae217 | 1323 | if (i->conflict_vec_p) |
058e97ec VM |
1324 | i->size = i->bit_num = i->base_conflict_id = i->word = 0; |
1325 | else | |
1326 | { | |
a49ae217 | 1327 | if (OBJECT_MIN (obj) > OBJECT_MAX (obj)) |
058e97ec VM |
1328 | i->size = 0; |
1329 | else | |
a49ae217 | 1330 | i->size = ((OBJECT_MAX (obj) - OBJECT_MIN (obj) |
058e97ec VM |
1331 | + IRA_INT_BITS) |
1332 | / IRA_INT_BITS) * sizeof (IRA_INT_TYPE); | |
1333 | i->bit_num = 0; | |
a49ae217 | 1334 | i->base_conflict_id = OBJECT_MIN (obj); |
058e97ec VM |
1335 | i->word = (i->size == 0 ? 0 : ((IRA_INT_TYPE *) i->vec)[0]); |
1336 | } | |
1337 | } | |
1338 | ||
1339 | /* Return TRUE if we have more conflicting allocnos to visit, in which | |
1340 | case *A is set to the allocno to be visited. Otherwise, return | |
1341 | FALSE. */ | |
1342 | static inline bool | |
fa86d337 BS |
1343 | ira_object_conflict_iter_cond (ira_object_conflict_iterator *i, |
1344 | ira_object_t *pobj) | |
058e97ec | 1345 | { |
a49ae217 | 1346 | ira_object_t obj; |
058e97ec | 1347 | |
a49ae217 | 1348 | if (i->conflict_vec_p) |
058e97ec | 1349 | { |
1756cb66 | 1350 | obj = ((ira_object_t *) i->vec)[i->word_num++]; |
a49ae217 | 1351 | if (obj == NULL) |
058e97ec | 1352 | return false; |
058e97ec VM |
1353 | } |
1354 | else | |
1355 | { | |
1756cb66 VM |
1356 | unsigned IRA_INT_TYPE word = i->word; |
1357 | unsigned int bit_num = i->bit_num; | |
1358 | ||
058e97ec | 1359 | /* Skip words that are zeros. */ |
1756cb66 | 1360 | for (; word == 0; word = ((IRA_INT_TYPE *) i->vec)[i->word_num]) |
058e97ec VM |
1361 | { |
1362 | i->word_num++; | |
b8698a0f | 1363 | |
058e97ec VM |
1364 | /* If we have reached the end, break. */ |
1365 | if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size) | |
1366 | return false; | |
b8698a0f | 1367 | |
1756cb66 | 1368 | bit_num = i->word_num * IRA_INT_BITS; |
058e97ec | 1369 | } |
b8698a0f | 1370 | |
058e97ec | 1371 | /* Skip bits that are zero. */ |
1756cb66 VM |
1372 | for (; (word & 1) == 0; word >>= 1) |
1373 | bit_num++; | |
b8698a0f | 1374 | |
1756cb66 VM |
1375 | obj = ira_object_id_map[bit_num + i->base_conflict_id]; |
1376 | i->bit_num = bit_num + 1; | |
1377 | i->word = word >> 1; | |
058e97ec | 1378 | } |
a49ae217 | 1379 | |
fa86d337 | 1380 | *pobj = obj; |
a49ae217 | 1381 | return true; |
058e97ec VM |
1382 | } |
1383 | ||
fa86d337 BS |
1384 | /* Loop over all objects conflicting with OBJ. In each iteration, |
1385 | CONF is set to the next conflicting object. ITER is an instance | |
1386 | of ira_object_conflict_iterator used to iterate the conflicts. */ | |
1387 | #define FOR_EACH_OBJECT_CONFLICT(OBJ, CONF, ITER) \ | |
1388 | for (ira_object_conflict_iter_init (&(ITER), (OBJ)); \ | |
1756cb66 | 1389 | ira_object_conflict_iter_cond (&(ITER), &(CONF));) |
058e97ec VM |
1390 | |
1391 | \f | |
1392 | ||
1756cb66 VM |
1393 | /* The function returns TRUE if at least one hard register from ones |
1394 | starting with HARD_REGNO and containing value of MODE are in set | |
1395 | HARD_REGSET. */ | |
1396 | static inline bool | |
1397 | ira_hard_reg_set_intersection_p (int hard_regno, enum machine_mode mode, | |
1398 | HARD_REG_SET hard_regset) | |
1399 | { | |
1400 | int i; | |
1401 | ||
1402 | gcc_assert (hard_regno >= 0); | |
1403 | for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--) | |
1404 | if (TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) | |
1405 | return true; | |
1406 | return false; | |
1407 | } | |
1408 | ||
1409 | /* Return number of hard registers in hard register SET. */ | |
1410 | static inline int | |
1411 | hard_reg_set_size (HARD_REG_SET set) | |
1412 | { | |
1413 | int i, size; | |
1414 | ||
1415 | for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1416 | if (TEST_HARD_REG_BIT (set, i)) | |
1417 | size++; | |
1418 | return size; | |
1419 | } | |
1420 | ||
058e97ec | 1421 | /* The function returns TRUE if hard registers starting with |
9181a6e5 | 1422 | HARD_REGNO and containing value of MODE are fully in set |
058e97ec VM |
1423 | HARD_REGSET. */ |
1424 | static inline bool | |
9181a6e5 VM |
1425 | ira_hard_reg_in_set_p (int hard_regno, enum machine_mode mode, |
1426 | HARD_REG_SET hard_regset) | |
058e97ec VM |
1427 | { |
1428 | int i; | |
1429 | ||
1430 | ira_assert (hard_regno >= 0); | |
1431 | for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--) | |
9181a6e5 | 1432 | if (!TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) |
058e97ec VM |
1433 | return false; |
1434 | return true; | |
1435 | } | |
1436 | ||
1437 | \f | |
1438 | ||
1439 | /* To save memory we use a lazy approach for allocation and | |
1440 | initialization of the cost vectors. We do this only when it is | |
1441 | really necessary. */ | |
1442 | ||
1756cb66 | 1443 | /* Allocate cost vector *VEC for hard registers of ACLASS and |
058e97ec VM |
1444 | initialize the elements by VAL if it is necessary */ |
1445 | static inline void | |
6f76a878 | 1446 | ira_allocate_and_set_costs (int **vec, reg_class_t aclass, int val) |
058e97ec VM |
1447 | { |
1448 | int i, *reg_costs; | |
1449 | int len; | |
1450 | ||
1451 | if (*vec != NULL) | |
1452 | return; | |
1756cb66 | 1453 | *vec = reg_costs = ira_allocate_cost_vector (aclass); |
6f76a878 | 1454 | len = ira_class_hard_regs_num[(int) aclass]; |
058e97ec VM |
1455 | for (i = 0; i < len; i++) |
1456 | reg_costs[i] = val; | |
1457 | } | |
1458 | ||
1756cb66 VM |
1459 | /* Allocate cost vector *VEC for hard registers of ACLASS and copy |
1460 | values of vector SRC into the vector if it is necessary */ | |
058e97ec | 1461 | static inline void |
1756cb66 | 1462 | ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src) |
058e97ec VM |
1463 | { |
1464 | int len; | |
1465 | ||
1466 | if (*vec != NULL || src == NULL) | |
1467 | return; | |
1756cb66 VM |
1468 | *vec = ira_allocate_cost_vector (aclass); |
1469 | len = ira_class_hard_regs_num[aclass]; | |
058e97ec VM |
1470 | memcpy (*vec, src, sizeof (int) * len); |
1471 | } | |
1472 | ||
1756cb66 VM |
1473 | /* Allocate cost vector *VEC for hard registers of ACLASS and add |
1474 | values of vector SRC into the vector if it is necessary */ | |
058e97ec | 1475 | static inline void |
1756cb66 | 1476 | ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src) |
058e97ec VM |
1477 | { |
1478 | int i, len; | |
1479 | ||
1480 | if (src == NULL) | |
1481 | return; | |
1756cb66 | 1482 | len = ira_class_hard_regs_num[aclass]; |
058e97ec VM |
1483 | if (*vec == NULL) |
1484 | { | |
1756cb66 | 1485 | *vec = ira_allocate_cost_vector (aclass); |
058e97ec VM |
1486 | memset (*vec, 0, sizeof (int) * len); |
1487 | } | |
1488 | for (i = 0; i < len; i++) | |
1489 | (*vec)[i] += src[i]; | |
1490 | } | |
1491 | ||
1756cb66 VM |
1492 | /* Allocate cost vector *VEC for hard registers of ACLASS and copy |
1493 | values of vector SRC into the vector or initialize it by VAL (if | |
1494 | SRC is null). */ | |
058e97ec | 1495 | static inline void |
1756cb66 | 1496 | ira_allocate_and_set_or_copy_costs (int **vec, enum reg_class aclass, |
058e97ec VM |
1497 | int val, int *src) |
1498 | { | |
1499 | int i, *reg_costs; | |
1500 | int len; | |
1501 | ||
1502 | if (*vec != NULL) | |
1503 | return; | |
1756cb66 VM |
1504 | *vec = reg_costs = ira_allocate_cost_vector (aclass); |
1505 | len = ira_class_hard_regs_num[aclass]; | |
058e97ec VM |
1506 | if (src != NULL) |
1507 | memcpy (reg_costs, src, sizeof (int) * len); | |
1508 | else | |
1509 | { | |
1510 | for (i = 0; i < len; i++) | |
1511 | reg_costs[i] = val; | |
1512 | } | |
1513 | } | |
acf41a74 BS |
1514 | |
1515 | extern rtx ira_create_new_reg (rtx); | |
1516 | extern int first_moveable_pseudo, last_moveable_pseudo; | |
f1717f8d KC |
1517 | |
1518 | #endif /* GCC_IRA_INT_H */ |