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058e97ec | 1 | /* Integrated Register Allocator (IRA) intercommunication header file. |
d652f226 | 2 | Copyright (C) 2006, 2007, 2008, 2009, 2010 |
058e97ec VM |
3 | Free Software Foundation, Inc. |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "cfgloop.h" | |
23 | #include "ira.h" | |
24 | #include "alloc-pool.h" | |
25 | ||
26 | /* To provide consistency in naming, all IRA external variables, | |
27 | functions, common typedefs start with prefix ira_. */ | |
28 | ||
29 | #ifdef ENABLE_CHECKING | |
30 | #define ENABLE_IRA_CHECKING | |
31 | #endif | |
32 | ||
33 | #ifdef ENABLE_IRA_CHECKING | |
34 | #define ira_assert(c) gcc_assert (c) | |
35 | #else | |
f7556aae L |
36 | /* Always define and include C, so that warnings for empty body in an |
37 | ‘if’ statement and unused variable do not occur. */ | |
38 | #define ira_assert(c) ((void)(0 && (c))) | |
058e97ec VM |
39 | #endif |
40 | ||
41 | /* Compute register frequency from edge frequency FREQ. It is | |
42 | analogous to REG_FREQ_FROM_BB. When optimizing for size, or | |
43 | profile driven feedback is available and the function is never | |
44 | executed, frequency is always equivalent. Otherwise rescale the | |
45 | edge frequency. */ | |
1756cb66 VM |
46 | #define REG_FREQ_FROM_EDGE_FREQ(freq) \ |
47 | (optimize_size || (flag_branch_probabilities && !ENTRY_BLOCK_PTR->count) \ | |
48 | ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \ | |
058e97ec VM |
49 | ? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1) |
50 | ||
51 | /* All natural loops. */ | |
52 | extern struct loops ira_loops; | |
53 | ||
54 | /* A modified value of flag `-fira-verbose' used internally. */ | |
55 | extern int internal_flag_ira_verbose; | |
56 | ||
57 | /* Dump file of the allocator if it is not NULL. */ | |
58 | extern FILE *ira_dump_file; | |
59 | ||
60 | /* Typedefs for pointers to allocno live range, allocno, and copy of | |
61 | allocnos. */ | |
b14151b5 | 62 | typedef struct live_range *live_range_t; |
058e97ec VM |
63 | typedef struct ira_allocno *ira_allocno_t; |
64 | typedef struct ira_allocno_copy *ira_copy_t; | |
a49ae217 | 65 | typedef struct ira_object *ira_object_t; |
058e97ec VM |
66 | |
67 | /* Definition of vector of allocnos and copies. */ | |
68 | DEF_VEC_P(ira_allocno_t); | |
69 | DEF_VEC_ALLOC_P(ira_allocno_t, heap); | |
a49ae217 BS |
70 | DEF_VEC_P(ira_object_t); |
71 | DEF_VEC_ALLOC_P(ira_object_t, heap); | |
058e97ec VM |
72 | DEF_VEC_P(ira_copy_t); |
73 | DEF_VEC_ALLOC_P(ira_copy_t, heap); | |
74 | ||
75 | /* Typedef for pointer to the subsequent structure. */ | |
76 | typedef struct ira_loop_tree_node *ira_loop_tree_node_t; | |
77 | ||
e80ccebc RS |
78 | typedef unsigned short move_table[N_REG_CLASSES]; |
79 | ||
058e97ec VM |
80 | /* In general case, IRA is a regional allocator. The regions are |
81 | nested and form a tree. Currently regions are natural loops. The | |
82 | following structure describes loop tree node (representing basic | |
83 | block or loop). We need such tree because the loop tree from | |
84 | cfgloop.h is not convenient for the optimization: basic blocks are | |
85 | not a part of the tree from cfgloop.h. We also use the nodes for | |
86 | storing additional information about basic blocks/loops for the | |
87 | register allocation purposes. */ | |
88 | struct ira_loop_tree_node | |
89 | { | |
90 | /* The node represents basic block if children == NULL. */ | |
91 | basic_block bb; /* NULL for loop. */ | |
2608d841 VM |
92 | /* NULL for BB or for loop tree root if we did not build CFG loop tree. */ |
93 | struct loop *loop; | |
af51c885 AN |
94 | /* NEXT/SUBLOOP_NEXT is the next node/loop-node of the same parent. |
95 | SUBLOOP_NEXT is always NULL for BBs. */ | |
058e97ec | 96 | ira_loop_tree_node_t subloop_next, next; |
af51c885 AN |
97 | /* CHILDREN/SUBLOOPS is the first node/loop-node immediately inside |
98 | the node. They are NULL for BBs. */ | |
058e97ec VM |
99 | ira_loop_tree_node_t subloops, children; |
100 | /* The node immediately containing given node. */ | |
101 | ira_loop_tree_node_t parent; | |
102 | ||
103 | /* Loop level in range [0, ira_loop_tree_height). */ | |
104 | int level; | |
105 | ||
106 | /* All the following members are defined only for nodes representing | |
107 | loops. */ | |
108 | ||
2608d841 VM |
109 | /* The loop number from CFG loop tree. The root number is 0. */ |
110 | int loop_num; | |
111 | ||
30ea859e VM |
112 | /* True if the loop was marked for removal from the register |
113 | allocation. */ | |
114 | bool to_remove_p; | |
115 | ||
058e97ec VM |
116 | /* Allocnos in the loop corresponding to their regnos. If it is |
117 | NULL the loop does not form a separate register allocation region | |
118 | (e.g. because it has abnormal enter/exit edges and we can not put | |
119 | code for register shuffling on the edges if a different | |
120 | allocation is used for a pseudo-register on different sides of | |
121 | the edges). Caps are not in the map (remember we can have more | |
122 | one cap with the same regno in a region). */ | |
123 | ira_allocno_t *regno_allocno_map; | |
124 | ||
ea1c67e6 VM |
125 | /* True if there is an entry to given loop not from its parent (or |
126 | grandparent) basic block. For example, it is possible for two | |
127 | adjacent loops inside another loop. */ | |
128 | bool entered_from_non_parent_p; | |
129 | ||
058e97ec | 130 | /* Maximal register pressure inside loop for given register class |
1756cb66 | 131 | (defined only for the pressure classes). */ |
058e97ec VM |
132 | int reg_pressure[N_REG_CLASSES]; |
133 | ||
49d988e7 VM |
134 | /* Numbers of allocnos referred or living in the loop node (except |
135 | for its subloops). */ | |
136 | bitmap all_allocnos; | |
137 | ||
138 | /* Numbers of allocnos living at the loop borders. */ | |
139 | bitmap border_allocnos; | |
058e97ec VM |
140 | |
141 | /* Regnos of pseudos modified in the loop node (including its | |
142 | subloops). */ | |
143 | bitmap modified_regnos; | |
144 | ||
058e97ec VM |
145 | /* Numbers of copies referred in the corresponding loop. */ |
146 | bitmap local_copies; | |
147 | }; | |
148 | ||
149 | /* The root of the loop tree corresponding to the all function. */ | |
150 | extern ira_loop_tree_node_t ira_loop_tree_root; | |
151 | ||
152 | /* Height of the loop tree. */ | |
153 | extern int ira_loop_tree_height; | |
154 | ||
155 | /* All nodes representing basic blocks are referred through the | |
156 | following array. We can not use basic block member `aux' for this | |
157 | because it is used for insertion of insns on edges. */ | |
158 | extern ira_loop_tree_node_t ira_bb_nodes; | |
159 | ||
160 | /* Two access macros to the nodes representing basic blocks. */ | |
161 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
162 | #define IRA_BB_NODE_BY_INDEX(index) __extension__ \ | |
2608d841 | 163 | (({ ira_loop_tree_node_t _node = (&ira_bb_nodes[index]); \ |
058e97ec VM |
164 | if (_node->children != NULL || _node->loop != NULL || _node->bb == NULL)\ |
165 | { \ | |
166 | fprintf (stderr, \ | |
167 | "\n%s: %d: error in %s: it is not a block node\n", \ | |
168 | __FILE__, __LINE__, __FUNCTION__); \ | |
169 | gcc_unreachable (); \ | |
170 | } \ | |
171 | _node; })) | |
172 | #else | |
173 | #define IRA_BB_NODE_BY_INDEX(index) (&ira_bb_nodes[index]) | |
174 | #endif | |
175 | ||
176 | #define IRA_BB_NODE(bb) IRA_BB_NODE_BY_INDEX ((bb)->index) | |
177 | ||
178 | /* All nodes representing loops are referred through the following | |
179 | array. */ | |
180 | extern ira_loop_tree_node_t ira_loop_nodes; | |
181 | ||
182 | /* Two access macros to the nodes representing loops. */ | |
183 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
184 | #define IRA_LOOP_NODE_BY_INDEX(index) __extension__ \ | |
2608d841 VM |
185 | (({ ira_loop_tree_node_t const _node = (&ira_loop_nodes[index]); \ |
186 | if (_node->children == NULL || _node->bb != NULL \ | |
187 | || (_node->loop == NULL && current_loops != NULL)) \ | |
058e97ec VM |
188 | { \ |
189 | fprintf (stderr, \ | |
190 | "\n%s: %d: error in %s: it is not a loop node\n", \ | |
191 | __FILE__, __LINE__, __FUNCTION__); \ | |
192 | gcc_unreachable (); \ | |
193 | } \ | |
194 | _node; })) | |
195 | #else | |
196 | #define IRA_LOOP_NODE_BY_INDEX(index) (&ira_loop_nodes[index]) | |
197 | #endif | |
198 | ||
199 | #define IRA_LOOP_NODE(loop) IRA_LOOP_NODE_BY_INDEX ((loop)->num) | |
200 | ||
201 | \f | |
058e97ec | 202 | /* The structure describes program points where a given allocno lives. |
1756cb66 VM |
203 | If the live ranges of two allocnos are intersected, the allocnos |
204 | are in conflict. */ | |
b14151b5 | 205 | struct live_range |
058e97ec | 206 | { |
ac0ab4f7 | 207 | /* Object whose live range is described by given structure. */ |
9140d27b | 208 | ira_object_t object; |
058e97ec VM |
209 | /* Program point range. */ |
210 | int start, finish; | |
211 | /* Next structure describing program points where the allocno | |
212 | lives. */ | |
b14151b5 | 213 | live_range_t next; |
058e97ec | 214 | /* Pointer to structures with the same start/finish. */ |
b14151b5 | 215 | live_range_t start_next, finish_next; |
058e97ec VM |
216 | }; |
217 | ||
218 | /* Program points are enumerated by numbers from range | |
219 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
220 | points than insns. Program points are places in the program where | |
221 | liveness info can be changed. In most general case (there are more | |
222 | complicated cases too) some program points correspond to places | |
223 | where input operand dies and other ones correspond to places where | |
224 | output operands are born. */ | |
225 | extern int ira_max_point; | |
226 | ||
227 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
228 | live ranges with given start/finish point. */ | |
b14151b5 | 229 | extern live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec | 230 | |
a49ae217 BS |
231 | /* A structure representing conflict information for an allocno |
232 | (or one of its subwords). */ | |
233 | struct ira_object | |
234 | { | |
235 | /* The allocno associated with this record. */ | |
236 | ira_allocno_t allocno; | |
237 | /* Vector of accumulated conflicting conflict_redords with NULL end | |
238 | marker (if OBJECT_CONFLICT_VEC_P is true) or conflict bit vector | |
1756cb66 | 239 | otherwise. */ |
a49ae217 | 240 | void *conflicts_array; |
9140d27b BS |
241 | /* Pointer to structures describing at what program point the |
242 | object lives. We always maintain the list in such way that *the | |
243 | ranges in the list are not intersected and ordered by decreasing | |
244 | their program points*. */ | |
245 | live_range_t live_ranges; | |
ac0ab4f7 BS |
246 | /* The subword within ALLOCNO which is represented by this object. |
247 | Zero means the lowest-order subword (or the entire allocno in case | |
248 | it is not being tracked in subwords). */ | |
249 | int subword; | |
9140d27b | 250 | /* Allocated size of the conflicts array. */ |
a49ae217 | 251 | unsigned int conflicts_array_size; |
ac0ab4f7 | 252 | /* A unique number for every instance of this structure, which is used |
a49ae217 BS |
253 | to represent it in conflict bit vectors. */ |
254 | int id; | |
255 | /* Before building conflicts, MIN and MAX are initialized to | |
256 | correspondingly minimal and maximal points of the accumulated | |
ac0ab4f7 BS |
257 | live ranges. Afterwards, they hold the minimal and maximal ids |
258 | of other ira_objects that this one can conflict with. */ | |
a49ae217 BS |
259 | int min, max; |
260 | /* Initial and accumulated hard registers conflicting with this | |
ac0ab4f7 | 261 | object and as a consequences can not be assigned to the allocno. |
1756cb66 | 262 | All non-allocatable hard regs and hard regs of register classes |
ac0ab4f7 | 263 | different from given allocno one are included in the sets. */ |
a49ae217 BS |
264 | HARD_REG_SET conflict_hard_regs, total_conflict_hard_regs; |
265 | /* Number of accumulated conflicts in the vector of conflicting | |
ac0ab4f7 | 266 | objects. */ |
a49ae217 BS |
267 | int num_accumulated_conflicts; |
268 | /* TRUE if conflicts are represented by a vector of pointers to | |
269 | ira_object structures. Otherwise, we use a bit vector indexed | |
270 | by conflict ID numbers. */ | |
271 | unsigned int conflict_vec_p : 1; | |
272 | }; | |
273 | ||
058e97ec VM |
274 | /* A structure representing an allocno (allocation entity). Allocno |
275 | represents a pseudo-register in an allocation region. If | |
276 | pseudo-register does not live in a region but it lives in the | |
277 | nested regions, it is represented in the region by special allocno | |
278 | called *cap*. There may be more one cap representing the same | |
279 | pseudo-register in region. It means that the corresponding | |
280 | pseudo-register lives in more one non-intersected subregion. */ | |
281 | struct ira_allocno | |
282 | { | |
283 | /* The allocno order number starting with 0. Each allocno has an | |
284 | unique number and the number is never changed for the | |
285 | allocno. */ | |
286 | int num; | |
287 | /* Regno for allocno or cap. */ | |
288 | int regno; | |
289 | /* Mode of the allocno which is the mode of the corresponding | |
290 | pseudo-register. */ | |
1756cb66 VM |
291 | ENUM_BITFIELD (machine_mode) mode : 8; |
292 | /* Register class which should be used for allocation for given | |
293 | allocno. NO_REGS means that we should use memory. */ | |
294 | ENUM_BITFIELD (reg_class) aclass : 16; | |
295 | /* During the reload, value TRUE means that we should not reassign a | |
296 | hard register to the allocno got memory earlier. It is set up | |
297 | when we removed memory-memory move insn before each iteration of | |
298 | the reload. */ | |
299 | unsigned int dont_reassign_p : 1; | |
300 | #ifdef STACK_REGS | |
301 | /* Set to TRUE if allocno can't be assigned to the stack hard | |
302 | register correspondingly in this region and area including the | |
303 | region and all its subregions recursively. */ | |
304 | unsigned int no_stack_reg_p : 1, total_no_stack_reg_p : 1; | |
305 | #endif | |
306 | /* TRUE value means that there is no sense to spill the allocno | |
307 | during coloring because the spill will result in additional | |
308 | reloads in reload pass. */ | |
309 | unsigned int bad_spill_p : 1; | |
310 | /* TRUE if a hard register or memory has been assigned to the | |
311 | allocno. */ | |
312 | unsigned int assigned_p : 1; | |
313 | /* TRUE if conflicts for given allocno are represented by vector of | |
314 | pointers to the conflicting allocnos. Otherwise, we use a bit | |
315 | vector where a bit with given index represents allocno with the | |
316 | same number. */ | |
317 | unsigned int conflict_vec_p : 1; | |
058e97ec VM |
318 | /* Hard register assigned to given allocno. Negative value means |
319 | that memory was allocated to the allocno. During the reload, | |
320 | spilled allocno has value equal to the corresponding stack slot | |
321 | number (0, ...) - 2. Value -1 is used for allocnos spilled by the | |
322 | reload (at this point pseudo-register has only one allocno) which | |
323 | did not get stack slot yet. */ | |
1756cb66 | 324 | short int hard_regno; |
058e97ec VM |
325 | /* Allocnos with the same regno are linked by the following member. |
326 | Allocnos corresponding to inner loops are first in the list (it | |
327 | corresponds to depth-first traverse of the loops). */ | |
328 | ira_allocno_t next_regno_allocno; | |
329 | /* There may be different allocnos with the same regno in different | |
330 | regions. Allocnos are bound to the corresponding loop tree node. | |
331 | Pseudo-register may have only one regular allocno with given loop | |
332 | tree node but more than one cap (see comments above). */ | |
333 | ira_loop_tree_node_t loop_tree_node; | |
334 | /* Accumulated usage references of the allocno. Here and below, | |
335 | word 'accumulated' means info for given region and all nested | |
336 | subregions. In this case, 'accumulated' means sum of references | |
337 | of the corresponding pseudo-register in this region and in all | |
338 | nested subregions recursively. */ | |
339 | int nrefs; | |
340 | /* Accumulated frequency of usage of the allocno. */ | |
341 | int freq; | |
cb1ca6ac | 342 | /* Minimal accumulated and updated costs of usage register of the |
1756cb66 VM |
343 | allocno class. */ |
344 | int class_cost, updated_class_cost; | |
058e97ec VM |
345 | /* Minimal accumulated, and updated costs of memory for the allocno. |
346 | At the allocation start, the original and updated costs are | |
347 | equal. The updated cost may be changed after finishing | |
348 | allocation in a region and starting allocation in a subregion. | |
349 | The change reflects the cost of spill/restore code on the | |
350 | subregion border if we assign memory to the pseudo in the | |
351 | subregion. */ | |
352 | int memory_cost, updated_memory_cost; | |
353 | /* Accumulated number of points where the allocno lives and there is | |
354 | excess pressure for its class. Excess pressure for a register | |
355 | class at some point means that there are more allocnos of given | |
356 | register class living at the point than number of hard-registers | |
357 | of the class available for the allocation. */ | |
358 | int excess_pressure_points_num; | |
359 | /* Copies to other non-conflicting allocnos. The copies can | |
360 | represent move insn or potential move insn usually because of two | |
361 | operand insn constraints. */ | |
362 | ira_copy_t allocno_copies; | |
363 | /* It is a allocno (cap) representing given allocno on upper loop tree | |
364 | level. */ | |
365 | ira_allocno_t cap; | |
366 | /* It is a link to allocno (cap) on lower loop level represented by | |
367 | given cap. Null if given allocno is not a cap. */ | |
368 | ira_allocno_t cap_member; | |
ac0ab4f7 BS |
369 | /* The number of objects tracked in the following array. */ |
370 | int num_objects; | |
371 | /* An array of structures describing conflict information and live | |
372 | ranges for each object associated with the allocno. There may be | |
373 | more than one such object in cases where the allocno represents a | |
374 | multi-word register. */ | |
375 | ira_object_t objects[2]; | |
058e97ec VM |
376 | /* Accumulated frequency of calls which given allocno |
377 | intersects. */ | |
378 | int call_freq; | |
a812fb07 | 379 | /* Accumulated number of the intersected calls. */ |
058e97ec | 380 | int calls_crossed_num; |
e384e6b5 BS |
381 | /* The number of calls across which it is live, but which should not |
382 | affect register preferences. */ | |
383 | int cheap_calls_crossed_num; | |
058e97ec | 384 | /* Array of usage costs (accumulated and the one updated during |
1756cb66 | 385 | coloring) for each hard register of the allocno class. The |
058e97ec | 386 | member value can be NULL if all costs are the same and equal to |
1756cb66 | 387 | CLASS_COST. For example, the costs of two different hard |
058e97ec VM |
388 | registers can be different if one hard register is callee-saved |
389 | and another one is callee-used and the allocno lives through | |
390 | calls. Another example can be case when for some insn the | |
391 | corresponding pseudo-register value should be put in specific | |
392 | register class (e.g. AREG for x86) which is a strict subset of | |
1756cb66 VM |
393 | the allocno class (GENERAL_REGS for x86). We have updated costs |
394 | to reflect the situation when the usage cost of a hard register | |
395 | is decreased because the allocno is connected to another allocno | |
396 | by a copy and the another allocno has been assigned to the hard | |
397 | register. */ | |
058e97ec VM |
398 | int *hard_reg_costs, *updated_hard_reg_costs; |
399 | /* Array of decreasing costs (accumulated and the one updated during | |
400 | coloring) for allocnos conflicting with given allocno for hard | |
1756cb66 VM |
401 | regno of the allocno class. The member value can be NULL if all |
402 | costs are the same. These costs are used to reflect preferences | |
403 | of other allocnos not assigned yet during assigning to given | |
404 | allocno. */ | |
058e97ec | 405 | int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs; |
1756cb66 VM |
406 | /* Different additional data. It is used to decrease size of |
407 | allocno data footprint. */ | |
408 | void *add_data; | |
058e97ec VM |
409 | }; |
410 | ||
1756cb66 | 411 | |
058e97ec VM |
412 | /* All members of the allocno structures should be accessed only |
413 | through the following macros. */ | |
414 | #define ALLOCNO_NUM(A) ((A)->num) | |
415 | #define ALLOCNO_REGNO(A) ((A)->regno) | |
416 | #define ALLOCNO_REG(A) ((A)->reg) | |
417 | #define ALLOCNO_NEXT_REGNO_ALLOCNO(A) ((A)->next_regno_allocno) | |
418 | #define ALLOCNO_LOOP_TREE_NODE(A) ((A)->loop_tree_node) | |
419 | #define ALLOCNO_CAP(A) ((A)->cap) | |
420 | #define ALLOCNO_CAP_MEMBER(A) ((A)->cap_member) | |
058e97ec VM |
421 | #define ALLOCNO_NREFS(A) ((A)->nrefs) |
422 | #define ALLOCNO_FREQ(A) ((A)->freq) | |
423 | #define ALLOCNO_HARD_REGNO(A) ((A)->hard_regno) | |
424 | #define ALLOCNO_CALL_FREQ(A) ((A)->call_freq) | |
425 | #define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num) | |
e384e6b5 | 426 | #define ALLOCNO_CHEAP_CALLS_CROSSED_NUM(A) ((A)->cheap_calls_crossed_num) |
058e97ec VM |
427 | #define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest) |
428 | #define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p) | |
429 | #define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p) | |
430 | #define ALLOCNO_CHILD_RENAMED_P(A) ((A)->child_renamed_p) | |
431 | #define ALLOCNO_DONT_REASSIGN_P(A) ((A)->dont_reassign_p) | |
432 | #ifdef STACK_REGS | |
433 | #define ALLOCNO_NO_STACK_REG_P(A) ((A)->no_stack_reg_p) | |
434 | #define ALLOCNO_TOTAL_NO_STACK_REG_P(A) ((A)->total_no_stack_reg_p) | |
435 | #endif | |
927425df | 436 | #define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p) |
058e97ec | 437 | #define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p) |
058e97ec VM |
438 | #define ALLOCNO_MODE(A) ((A)->mode) |
439 | #define ALLOCNO_COPIES(A) ((A)->allocno_copies) | |
440 | #define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs) | |
441 | #define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs) | |
442 | #define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \ | |
443 | ((A)->conflict_hard_reg_costs) | |
444 | #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \ | |
445 | ((A)->updated_conflict_hard_reg_costs) | |
1756cb66 VM |
446 | #define ALLOCNO_CLASS(A) ((A)->aclass) |
447 | #define ALLOCNO_CLASS_COST(A) ((A)->class_cost) | |
448 | #define ALLOCNO_UPDATED_CLASS_COST(A) ((A)->updated_class_cost) | |
058e97ec VM |
449 | #define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost) |
450 | #define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost) | |
1756cb66 VM |
451 | #define ALLOCNO_EXCESS_PRESSURE_POINTS_NUM(A) \ |
452 | ((A)->excess_pressure_points_num) | |
ac0ab4f7 BS |
453 | #define ALLOCNO_OBJECT(A,N) ((A)->objects[N]) |
454 | #define ALLOCNO_NUM_OBJECTS(A) ((A)->num_objects) | |
1756cb66 | 455 | #define ALLOCNO_ADD_DATA(A) ((A)->add_data) |
a49ae217 | 456 | |
1756cb66 VM |
457 | /* Typedef for pointer to the subsequent structure. */ |
458 | typedef struct ira_emit_data *ira_emit_data_t; | |
459 | ||
460 | /* Allocno bound data used for emit pseudo live range split insns and | |
461 | to flattening IR. */ | |
462 | struct ira_emit_data | |
463 | { | |
464 | /* TRUE if the allocno assigned to memory was a destination of | |
465 | removed move (see ira-emit.c) at loop exit because the value of | |
466 | the corresponding pseudo-register is not changed inside the | |
467 | loop. */ | |
468 | unsigned int mem_optimized_dest_p : 1; | |
469 | /* TRUE if the corresponding pseudo-register has disjoint live | |
470 | ranges and the other allocnos of the pseudo-register except this | |
471 | one changed REG. */ | |
472 | unsigned int somewhere_renamed_p : 1; | |
473 | /* TRUE if allocno with the same REGNO in a subregion has been | |
474 | renamed, in other words, got a new pseudo-register. */ | |
475 | unsigned int child_renamed_p : 1; | |
476 | /* Final rtx representation of the allocno. */ | |
477 | rtx reg; | |
478 | /* Non NULL if we remove restoring value from given allocno to | |
479 | MEM_OPTIMIZED_DEST at loop exit (see ira-emit.c) because the | |
480 | allocno value is not changed inside the loop. */ | |
481 | ira_allocno_t mem_optimized_dest; | |
482 | }; | |
483 | ||
484 | #define ALLOCNO_EMIT_DATA(a) ((ira_emit_data_t) ALLOCNO_ADD_DATA (a)) | |
485 | ||
486 | /* Data used to emit live range split insns and to flattening IR. */ | |
487 | extern ira_emit_data_t ira_allocno_emit_data; | |
488 | ||
489 | /* Abbreviation for frequent emit data access. */ | |
490 | static inline rtx | |
491 | allocno_emit_reg (ira_allocno_t a) | |
492 | { | |
493 | return ALLOCNO_EMIT_DATA (a)->reg; | |
494 | } | |
495 | ||
496 | #define OBJECT_ALLOCNO(O) ((O)->allocno) | |
497 | #define OBJECT_SUBWORD(O) ((O)->subword) | |
498 | #define OBJECT_CONFLICT_ARRAY(O) ((O)->conflicts_array) | |
499 | #define OBJECT_CONFLICT_VEC(O) ((ira_object_t *)(O)->conflicts_array) | |
500 | #define OBJECT_CONFLICT_BITVEC(O) ((IRA_INT_TYPE *)(O)->conflicts_array) | |
501 | #define OBJECT_CONFLICT_ARRAY_SIZE(O) ((O)->conflicts_array_size) | |
502 | #define OBJECT_CONFLICT_VEC_P(O) ((O)->conflict_vec_p) | |
503 | #define OBJECT_NUM_CONFLICTS(O) ((O)->num_accumulated_conflicts) | |
504 | #define OBJECT_CONFLICT_HARD_REGS(O) ((O)->conflict_hard_regs) | |
505 | #define OBJECT_TOTAL_CONFLICT_HARD_REGS(O) ((O)->total_conflict_hard_regs) | |
506 | #define OBJECT_MIN(O) ((O)->min) | |
507 | #define OBJECT_MAX(O) ((O)->max) | |
508 | #define OBJECT_CONFLICT_ID(O) ((O)->id) | |
509 | #define OBJECT_LIVE_RANGES(O) ((O)->live_ranges) | |
058e97ec | 510 | |
b8698a0f | 511 | /* Map regno -> allocnos with given regno (see comments for |
058e97ec VM |
512 | allocno member `next_regno_allocno'). */ |
513 | extern ira_allocno_t *ira_regno_allocno_map; | |
514 | ||
515 | /* Array of references to all allocnos. The order number of the | |
516 | allocno corresponds to the index in the array. Removed allocnos | |
517 | have NULL element value. */ | |
518 | extern ira_allocno_t *ira_allocnos; | |
519 | ||
a49ae217 | 520 | /* The size of the previous array. */ |
058e97ec VM |
521 | extern int ira_allocnos_num; |
522 | ||
a49ae217 BS |
523 | /* Map a conflict id to its corresponding ira_object structure. */ |
524 | extern ira_object_t *ira_object_id_map; | |
525 | ||
526 | /* The size of the previous array. */ | |
527 | extern int ira_objects_num; | |
058e97ec VM |
528 | |
529 | /* The following structure represents a copy of two allocnos. The | |
530 | copies represent move insns or potential move insns usually because | |
531 | of two operand insn constraints. To remove register shuffle, we | |
532 | also create copies between allocno which is output of an insn and | |
533 | allocno becoming dead in the insn. */ | |
534 | struct ira_allocno_copy | |
535 | { | |
536 | /* The unique order number of the copy node starting with 0. */ | |
537 | int num; | |
538 | /* Allocnos connected by the copy. The first allocno should have | |
539 | smaller order number than the second one. */ | |
540 | ira_allocno_t first, second; | |
541 | /* Execution frequency of the copy. */ | |
542 | int freq; | |
548a6322 | 543 | bool constraint_p; |
058e97ec VM |
544 | /* It is a move insn which is an origin of the copy. The member |
545 | value for the copy representing two operand insn constraints or | |
546 | for the copy created to remove register shuffle is NULL. In last | |
547 | case the copy frequency is smaller than the corresponding insn | |
548 | execution frequency. */ | |
549 | rtx insn; | |
550 | /* All copies with the same allocno as FIRST are linked by the two | |
551 | following members. */ | |
552 | ira_copy_t prev_first_allocno_copy, next_first_allocno_copy; | |
553 | /* All copies with the same allocno as SECOND are linked by the two | |
554 | following members. */ | |
555 | ira_copy_t prev_second_allocno_copy, next_second_allocno_copy; | |
556 | /* Region from which given copy is originated. */ | |
557 | ira_loop_tree_node_t loop_tree_node; | |
558 | }; | |
559 | ||
560 | /* Array of references to all copies. The order number of the copy | |
561 | corresponds to the index in the array. Removed copies have NULL | |
562 | element value. */ | |
563 | extern ira_copy_t *ira_copies; | |
564 | ||
565 | /* Size of the previous array. */ | |
566 | extern int ira_copies_num; | |
567 | ||
568 | /* The following structure describes a stack slot used for spilled | |
569 | pseudo-registers. */ | |
570 | struct ira_spilled_reg_stack_slot | |
571 | { | |
572 | /* pseudo-registers assigned to the stack slot. */ | |
7a8cba34 | 573 | bitmap_head spilled_regs; |
058e97ec VM |
574 | /* RTL representation of the stack slot. */ |
575 | rtx mem; | |
576 | /* Size of the stack slot. */ | |
577 | unsigned int width; | |
578 | }; | |
579 | ||
580 | /* The number of elements in the following array. */ | |
581 | extern int ira_spilled_reg_stack_slots_num; | |
582 | ||
583 | /* The following array contains info about spilled pseudo-registers | |
584 | stack slots used in current function so far. */ | |
585 | extern struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
586 | ||
587 | /* Correspondingly overall cost of the allocation, cost of the | |
588 | allocnos assigned to hard-registers, cost of the allocnos assigned | |
589 | to memory, cost of loads, stores and register move insns generated | |
590 | for pseudo-register live range splitting (see ira-emit.c). */ | |
591 | extern int ira_overall_cost; | |
592 | extern int ira_reg_cost, ira_mem_cost; | |
593 | extern int ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
594 | extern int ira_move_loops_num, ira_additional_jumps_num; | |
1756cb66 | 595 | |
42ce1cc4 BS |
596 | \f |
597 | /* This page contains a bitset implementation called 'min/max sets' used to | |
598 | record conflicts in IRA. | |
599 | They are named min/maxs set since we keep track of a minimum and a maximum | |
600 | bit number for each set representing the bounds of valid elements. Otherwise, | |
601 | the implementation resembles sbitmaps in that we store an array of integers | |
602 | whose bits directly represent the members of the set. */ | |
603 | ||
604 | /* The type used as elements in the array, and the number of bits in | |
605 | this type. */ | |
ac0ab4f7 | 606 | |
058e97ec VM |
607 | #define IRA_INT_BITS HOST_BITS_PER_WIDE_INT |
608 | #define IRA_INT_TYPE HOST_WIDE_INT | |
609 | ||
610 | /* Set, clear or test bit number I in R, a bit vector of elements with | |
611 | minimal index and maximal index equal correspondingly to MIN and | |
612 | MAX. */ | |
613 | #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007) | |
614 | ||
42ce1cc4 | 615 | #define SET_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
616 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
617 | if (_i < _min || _i > _max) \ | |
618 | { \ | |
619 | fprintf (stderr, \ | |
620 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
621 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
622 | gcc_unreachable (); \ | |
623 | } \ | |
624 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
625 | |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
b8698a0f | 626 | |
058e97ec | 627 | |
42ce1cc4 | 628 | #define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
629 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
630 | if (_i < _min || _i > _max) \ | |
631 | { \ | |
632 | fprintf (stderr, \ | |
633 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
634 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
635 | gcc_unreachable (); \ | |
636 | } \ | |
637 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
638 | &= ~((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
639 | ||
42ce1cc4 | 640 | #define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \ |
058e97ec VM |
641 | (({ int _min = (MIN), _max = (MAX), _i = (I); \ |
642 | if (_i < _min || _i > _max) \ | |
643 | { \ | |
644 | fprintf (stderr, \ | |
645 | "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \ | |
646 | __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \ | |
647 | gcc_unreachable (); \ | |
648 | } \ | |
649 | ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \ | |
650 | & ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); })) | |
651 | ||
652 | #else | |
653 | ||
42ce1cc4 | 654 | #define SET_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
655 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
656 | |= ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
657 | ||
42ce1cc4 | 658 | #define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
659 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
660 | &= ~((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
661 | ||
42ce1cc4 | 662 | #define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) \ |
058e97ec VM |
663 | ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \ |
664 | & ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS))) | |
665 | ||
666 | #endif | |
667 | ||
42ce1cc4 | 668 | /* The iterator for min/max sets. */ |
058e97ec VM |
669 | typedef struct { |
670 | ||
42ce1cc4 | 671 | /* Array containing the bit vector. */ |
058e97ec VM |
672 | IRA_INT_TYPE *vec; |
673 | ||
674 | /* The number of the current element in the vector. */ | |
675 | unsigned int word_num; | |
676 | ||
677 | /* The number of bits in the bit vector. */ | |
678 | unsigned int nel; | |
679 | ||
680 | /* The current bit index of the bit vector. */ | |
681 | unsigned int bit_num; | |
682 | ||
683 | /* Index corresponding to the 1st bit of the bit vector. */ | |
684 | int start_val; | |
685 | ||
686 | /* The word of the bit vector currently visited. */ | |
687 | unsigned IRA_INT_TYPE word; | |
42ce1cc4 | 688 | } minmax_set_iterator; |
058e97ec | 689 | |
42ce1cc4 BS |
690 | /* Initialize the iterator I for bit vector VEC containing minimal and |
691 | maximal values MIN and MAX. */ | |
058e97ec | 692 | static inline void |
42ce1cc4 BS |
693 | minmax_set_iter_init (minmax_set_iterator *i, IRA_INT_TYPE *vec, int min, |
694 | int max) | |
058e97ec VM |
695 | { |
696 | i->vec = vec; | |
697 | i->word_num = 0; | |
698 | i->nel = max < min ? 0 : max - min + 1; | |
699 | i->start_val = min; | |
700 | i->bit_num = 0; | |
701 | i->word = i->nel == 0 ? 0 : vec[0]; | |
702 | } | |
703 | ||
ac0ab4f7 | 704 | /* Return TRUE if we have more allocnos to visit, in which case *N is |
42ce1cc4 | 705 | set to the number of the element to be visited. Otherwise, return |
058e97ec VM |
706 | FALSE. */ |
707 | static inline bool | |
42ce1cc4 | 708 | minmax_set_iter_cond (minmax_set_iterator *i, int *n) |
058e97ec VM |
709 | { |
710 | /* Skip words that are zeros. */ | |
711 | for (; i->word == 0; i->word = i->vec[i->word_num]) | |
712 | { | |
713 | i->word_num++; | |
714 | i->bit_num = i->word_num * IRA_INT_BITS; | |
b8698a0f | 715 | |
058e97ec VM |
716 | /* If we have reached the end, break. */ |
717 | if (i->bit_num >= i->nel) | |
718 | return false; | |
719 | } | |
b8698a0f | 720 | |
058e97ec VM |
721 | /* Skip bits that are zero. */ |
722 | for (; (i->word & 1) == 0; i->word >>= 1) | |
723 | i->bit_num++; | |
b8698a0f | 724 | |
058e97ec | 725 | *n = (int) i->bit_num + i->start_val; |
b8698a0f | 726 | |
058e97ec VM |
727 | return true; |
728 | } | |
729 | ||
42ce1cc4 | 730 | /* Advance to the next element in the set. */ |
058e97ec | 731 | static inline void |
42ce1cc4 | 732 | minmax_set_iter_next (minmax_set_iterator *i) |
058e97ec VM |
733 | { |
734 | i->word >>= 1; | |
735 | i->bit_num++; | |
736 | } | |
737 | ||
42ce1cc4 | 738 | /* Loop over all elements of a min/max set given by bit vector VEC and |
058e97ec VM |
739 | their minimal and maximal values MIN and MAX. In each iteration, N |
740 | is set to the number of next allocno. ITER is an instance of | |
42ce1cc4 BS |
741 | minmax_set_iterator used to iterate over the set. */ |
742 | #define FOR_EACH_BIT_IN_MINMAX_SET(VEC, MIN, MAX, N, ITER) \ | |
743 | for (minmax_set_iter_init (&(ITER), (VEC), (MIN), (MAX)); \ | |
744 | minmax_set_iter_cond (&(ITER), &(N)); \ | |
745 | minmax_set_iter_next (&(ITER))) | |
746 | \f | |
afcc66c4 | 747 | struct target_ira_int { |
aa1c5d72 RS |
748 | /* Initialized once. It is a maximal possible size of the allocated |
749 | struct costs. */ | |
750 | int x_max_struct_costs_size; | |
751 | ||
752 | /* Allocated and initialized once, and used to initialize cost values | |
753 | for each insn. */ | |
754 | struct costs *x_init_cost; | |
755 | ||
756 | /* Allocated once, and used for temporary purposes. */ | |
757 | struct costs *x_temp_costs; | |
758 | ||
759 | /* Allocated once, and used for the cost calculation. */ | |
760 | struct costs *x_op_costs[MAX_RECOG_OPERANDS]; | |
761 | struct costs *x_this_op_costs[MAX_RECOG_OPERANDS]; | |
762 | ||
afcc66c4 RS |
763 | /* Hard registers that can not be used for the register allocator for |
764 | all functions of the current compilation unit. */ | |
765 | HARD_REG_SET x_no_unit_alloc_regs; | |
766 | ||
767 | /* Map: hard regs X modes -> set of hard registers for storing value | |
768 | of given mode starting with given hard register. */ | |
769 | HARD_REG_SET (x_ira_reg_mode_hard_regset | |
770 | [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]); | |
771 | ||
e80ccebc RS |
772 | /* Maximum cost of moving from a register in one class to a register |
773 | in another class. Based on TARGET_REGISTER_MOVE_COST. */ | |
7cc61ee4 | 774 | move_table *x_ira_register_move_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
775 | |
776 | /* Similar, but here we don't have to move if the first index is a | |
777 | subset of the second so in that case the cost is zero. */ | |
7cc61ee4 | 778 | move_table *x_ira_may_move_in_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
779 | |
780 | /* Similar, but here we don't have to move if the first index is a | |
781 | superset of the second so in that case the cost is zero. */ | |
7cc61ee4 | 782 | move_table *x_ira_may_move_out_cost[MAX_MACHINE_MODE]; |
e80ccebc RS |
783 | |
784 | /* Keep track of the last mode we initialized move costs for. */ | |
785 | int x_last_mode_for_init_move_cost; | |
786 | ||
7cc61ee4 RS |
787 | /* Array analog of the macro MEMORY_MOVE_COST but they contain maximal |
788 | cost not minimal. */ | |
1756cb66 | 789 | short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; |
1756cb66 VM |
790 | |
791 | /* Map class->true if class is a possible allocno class, false | |
792 | otherwise. */ | |
793 | bool x_ira_reg_allocno_class_p[N_REG_CLASSES]; | |
794 | ||
795 | /* Map class->true if class is a pressure class, false otherwise. */ | |
796 | bool x_ira_reg_pressure_class_p[N_REG_CLASSES]; | |
797 | ||
afcc66c4 RS |
798 | /* Register class subset relation: TRUE if the first class is a subset |
799 | of the second one considering only hard registers available for the | |
800 | allocation. */ | |
801 | int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES]; | |
802 | ||
803 | /* Array of the number of hard registers of given class which are | |
dd5a833e | 804 | available for allocation. The order is defined by the hard |
afcc66c4 RS |
805 | register numbers. */ |
806 | short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
807 | ||
808 | /* Index (in ira_class_hard_regs; for given register class and hard | |
809 | register (in general case a hard register can belong to several | |
810 | register classes;. The index is negative for hard registers | |
811 | unavailable for the allocation. */ | |
812 | short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; | |
813 | ||
814 | /* Array whose values are hard regset of hard registers available for | |
815 | the allocation of given register class whose HARD_REGNO_MODE_OK | |
816 | values for given mode are zero. */ | |
1756cb66 | 817 | HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]; |
afcc66c4 RS |
818 | |
819 | /* The value is number of elements in the subsequent array. */ | |
820 | int x_ira_important_classes_num; | |
821 | ||
1756cb66 | 822 | /* The array containing all non-empty classes. Such classes is |
afcc66c4 RS |
823 | important for calculation of the hard register usage costs. */ |
824 | enum reg_class x_ira_important_classes[N_REG_CLASSES]; | |
825 | ||
1756cb66 VM |
826 | /* The array containing indexes of important classes in the previous |
827 | array. The array elements are defined only for important | |
828 | classes. */ | |
829 | int x_ira_important_class_nums[N_REG_CLASSES]; | |
830 | ||
afcc66c4 RS |
831 | /* The biggest important class inside of intersection of the two |
832 | classes (that is calculated taking only hard registers available | |
833 | for allocation into account;. If the both classes contain no hard | |
834 | registers available for allocation, the value is calculated with | |
835 | taking all hard-registers including fixed ones into account. */ | |
836 | enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES]; | |
837 | ||
838 | /* True if the two classes (that is calculated taking only hard | |
839 | registers available for allocation into account; are | |
840 | intersected. */ | |
841 | bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES]; | |
842 | ||
843 | /* Classes with end marker LIM_REG_CLASSES which are intersected with | |
844 | given class (the first index;. That includes given class itself. | |
845 | This is calculated taking only hard registers available for | |
846 | allocation into account. */ | |
847 | enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES]; | |
848 | ||
1756cb66 VM |
849 | /* The biggest (smallest) important class inside of (covering) union |
850 | of the two classes (that is calculated taking only hard registers | |
851 | available for allocation into account). If the both classes | |
852 | contain no hard registers available for allocation, the value is | |
853 | calculated with taking all hard-registers including fixed ones | |
854 | into account. In other words, the value is the corresponding | |
855 | reg_class_subunion (reg_class_superunion) value. */ | |
856 | enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
857 | enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; | |
afcc66c4 RS |
858 | |
859 | /* For each reg class, table listing all the classes contained in it | |
860 | (excluding the class itself. Non-allocatable registers are | |
861 | excluded from the consideration;. */ | |
862 | enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
15e7b94f RS |
863 | |
864 | /* Array whose values are hard regset of hard registers for which | |
865 | move of the hard register in given mode into itself is | |
866 | prohibited. */ | |
867 | HARD_REG_SET x_ira_prohibited_mode_move_regs[NUM_MACHINE_MODES]; | |
868 | ||
869 | /* Flag of that the above array has been initialized. */ | |
870 | bool x_ira_prohibited_mode_move_regs_initialized_p; | |
afcc66c4 RS |
871 | }; |
872 | ||
873 | extern struct target_ira_int default_target_ira_int; | |
874 | #if SWITCHABLE_TARGET | |
875 | extern struct target_ira_int *this_target_ira_int; | |
876 | #else | |
877 | #define this_target_ira_int (&default_target_ira_int) | |
878 | #endif | |
058e97ec | 879 | |
afcc66c4 RS |
880 | #define ira_reg_mode_hard_regset \ |
881 | (this_target_ira_int->x_ira_reg_mode_hard_regset) | |
882 | #define ira_register_move_cost \ | |
883 | (this_target_ira_int->x_ira_register_move_cost) | |
1756cb66 VM |
884 | #define ira_max_memory_move_cost \ |
885 | (this_target_ira_int->x_ira_max_memory_move_cost) | |
afcc66c4 RS |
886 | #define ira_may_move_in_cost \ |
887 | (this_target_ira_int->x_ira_may_move_in_cost) | |
888 | #define ira_may_move_out_cost \ | |
889 | (this_target_ira_int->x_ira_may_move_out_cost) | |
1756cb66 VM |
890 | #define ira_reg_allocno_class_p \ |
891 | (this_target_ira_int->x_ira_reg_allocno_class_p) | |
892 | #define ira_reg_pressure_class_p \ | |
893 | (this_target_ira_int->x_ira_reg_pressure_class_p) | |
afcc66c4 RS |
894 | #define ira_class_subset_p \ |
895 | (this_target_ira_int->x_ira_class_subset_p) | |
896 | #define ira_non_ordered_class_hard_regs \ | |
897 | (this_target_ira_int->x_ira_non_ordered_class_hard_regs) | |
898 | #define ira_class_hard_reg_index \ | |
899 | (this_target_ira_int->x_ira_class_hard_reg_index) | |
1756cb66 VM |
900 | #define ira_prohibited_class_mode_regs \ |
901 | (this_target_ira_int->x_ira_prohibited_class_mode_regs) | |
afcc66c4 RS |
902 | #define ira_important_classes_num \ |
903 | (this_target_ira_int->x_ira_important_classes_num) | |
904 | #define ira_important_classes \ | |
905 | (this_target_ira_int->x_ira_important_classes) | |
1756cb66 VM |
906 | #define ira_important_class_nums \ |
907 | (this_target_ira_int->x_ira_important_class_nums) | |
afcc66c4 RS |
908 | #define ira_reg_class_intersect \ |
909 | (this_target_ira_int->x_ira_reg_class_intersect) | |
910 | #define ira_reg_classes_intersect_p \ | |
911 | (this_target_ira_int->x_ira_reg_classes_intersect_p) | |
912 | #define ira_reg_class_super_classes \ | |
913 | (this_target_ira_int->x_ira_reg_class_super_classes) | |
1756cb66 VM |
914 | #define ira_reg_class_subunion \ |
915 | (this_target_ira_int->x_ira_reg_class_subunion) | |
916 | #define ira_reg_class_superunion \ | |
917 | (this_target_ira_int->x_ira_reg_class_superunion) | |
15e7b94f RS |
918 | #define ira_prohibited_mode_move_regs \ |
919 | (this_target_ira_int->x_ira_prohibited_mode_move_regs) | |
afcc66c4 RS |
920 | \f |
921 | /* ira.c: */ | |
058e97ec | 922 | |
058e97ec | 923 | extern void *ira_allocate (size_t); |
058e97ec VM |
924 | extern void ira_free (void *addr); |
925 | extern bitmap ira_allocate_bitmap (void); | |
926 | extern void ira_free_bitmap (bitmap); | |
927 | extern void ira_print_disposition (FILE *); | |
928 | extern void ira_debug_disposition (void); | |
1756cb66 | 929 | extern void ira_debug_allocno_classes (void); |
058e97ec VM |
930 | extern void ira_init_register_move_cost (enum machine_mode); |
931 | ||
932 | /* The length of the two following arrays. */ | |
933 | extern int ira_reg_equiv_len; | |
934 | ||
935 | /* The element value is TRUE if the corresponding regno value is | |
936 | invariant. */ | |
937 | extern bool *ira_reg_equiv_invariant_p; | |
938 | ||
939 | /* The element value is equiv constant of given pseudo-register or | |
940 | NULL_RTX. */ | |
941 | extern rtx *ira_reg_equiv_const; | |
942 | ||
943 | /* ira-build.c */ | |
944 | ||
945 | /* The current loop tree node and its regno allocno map. */ | |
946 | extern ira_loop_tree_node_t ira_curr_loop_tree_node; | |
947 | extern ira_allocno_t *ira_curr_regno_allocno_map; | |
948 | ||
4cda38d5 VM |
949 | extern void ira_debug_copy (ira_copy_t); |
950 | extern void ira_debug_copies (void); | |
058e97ec VM |
951 | extern void ira_debug_allocno_copies (ira_allocno_t); |
952 | ||
953 | extern void ira_traverse_loop_tree (bool, ira_loop_tree_node_t, | |
954 | void (*) (ira_loop_tree_node_t), | |
955 | void (*) (ira_loop_tree_node_t)); | |
029da7d4 BS |
956 | extern ira_allocno_t ira_parent_allocno (ira_allocno_t); |
957 | extern ira_allocno_t ira_parent_or_cap_allocno (ira_allocno_t); | |
058e97ec | 958 | extern ira_allocno_t ira_create_allocno (int, bool, ira_loop_tree_node_t); |
ac0ab4f7 | 959 | extern void ira_create_allocno_objects (ira_allocno_t); |
1756cb66 | 960 | extern void ira_set_allocno_class (ira_allocno_t, enum reg_class); |
a49ae217 BS |
961 | extern bool ira_conflict_vector_profitable_p (ira_object_t, int); |
962 | extern void ira_allocate_conflict_vec (ira_object_t, int); | |
963 | extern void ira_allocate_object_conflicts (ira_object_t, int); | |
ac0ab4f7 | 964 | extern void ior_hard_reg_conflicts (ira_allocno_t, HARD_REG_SET *); |
058e97ec | 965 | extern void ira_print_expanded_allocno (ira_allocno_t); |
ac0ab4f7 | 966 | extern void ira_add_live_range_to_object (ira_object_t, int, int); |
9140d27b BS |
967 | extern live_range_t ira_create_live_range (ira_object_t, int, int, |
968 | live_range_t); | |
969 | extern live_range_t ira_copy_live_range_list (live_range_t); | |
970 | extern live_range_t ira_merge_live_ranges (live_range_t, live_range_t); | |
971 | extern bool ira_live_ranges_intersect_p (live_range_t, live_range_t); | |
972 | extern void ira_finish_live_range (live_range_t); | |
973 | extern void ira_finish_live_range_list (live_range_t); | |
058e97ec VM |
974 | extern void ira_free_allocno_updated_costs (ira_allocno_t); |
975 | extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t, | |
548a6322 | 976 | int, bool, rtx, ira_loop_tree_node_t); |
058e97ec VM |
977 | extern void ira_add_allocno_copy_to_list (ira_copy_t); |
978 | extern void ira_swap_allocno_copy_ends_if_necessary (ira_copy_t); | |
548a6322 VM |
979 | extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int, |
980 | bool, rtx, ira_loop_tree_node_t); | |
058e97ec | 981 | |
6f76a878 AS |
982 | extern int *ira_allocate_cost_vector (reg_class_t); |
983 | extern void ira_free_cost_vector (int *, reg_class_t); | |
058e97ec VM |
984 | |
985 | extern void ira_flattening (int, int); | |
2608d841 | 986 | extern bool ira_build (void); |
058e97ec VM |
987 | extern void ira_destroy (void); |
988 | ||
989 | /* ira-costs.c */ | |
990 | extern void ira_init_costs_once (void); | |
991 | extern void ira_init_costs (void); | |
992 | extern void ira_finish_costs_once (void); | |
993 | extern void ira_costs (void); | |
1756cb66 | 994 | extern void ira_tune_allocno_costs (void); |
058e97ec VM |
995 | |
996 | /* ira-lives.c */ | |
997 | ||
998 | extern void ira_rebuild_start_finish_chains (void); | |
b14151b5 BS |
999 | extern void ira_print_live_range_list (FILE *, live_range_t); |
1000 | extern void ira_debug_live_range_list (live_range_t); | |
058e97ec VM |
1001 | extern void ira_debug_allocno_live_ranges (ira_allocno_t); |
1002 | extern void ira_debug_live_ranges (void); | |
1003 | extern void ira_create_allocno_live_ranges (void); | |
b15a7ae6 | 1004 | extern void ira_compress_allocno_live_ranges (void); |
058e97ec VM |
1005 | extern void ira_finish_allocno_live_ranges (void); |
1006 | ||
1007 | /* ira-conflicts.c */ | |
058e97ec VM |
1008 | extern void ira_debug_conflicts (bool); |
1009 | extern void ira_build_conflicts (void); | |
1010 | ||
1011 | /* ira-color.c */ | |
1756cb66 | 1012 | extern void ira_debug_hard_regs_forest (void); |
058e97ec VM |
1013 | extern int ira_loop_edge_freq (ira_loop_tree_node_t, int, bool); |
1014 | extern void ira_reassign_conflict_allocnos (int); | |
1015 | extern void ira_initiate_assign (void); | |
1016 | extern void ira_finish_assign (void); | |
1017 | extern void ira_color (void); | |
058e97ec VM |
1018 | |
1019 | /* ira-emit.c */ | |
1756cb66 VM |
1020 | extern void ira_initiate_emit_data (void); |
1021 | extern void ira_finish_emit_data (void); | |
058e97ec VM |
1022 | extern void ira_emit (bool); |
1023 | ||
1024 | \f | |
1025 | ||
1756cb66 VM |
1026 | /* Initialize register costs for MODE if necessary. */ |
1027 | static inline void | |
1028 | ira_init_register_move_cost_if_necessary (enum machine_mode mode) | |
6080348f VM |
1029 | { |
1030 | if (ira_register_move_cost[mode] == NULL) | |
1031 | ira_init_register_move_cost (mode); | |
6080348f VM |
1032 | } |
1033 | ||
1034 | \f | |
1035 | ||
058e97ec VM |
1036 | /* The iterator for all allocnos. */ |
1037 | typedef struct { | |
1038 | /* The number of the current element in IRA_ALLOCNOS. */ | |
1039 | int n; | |
1040 | } ira_allocno_iterator; | |
1041 | ||
1042 | /* Initialize the iterator I. */ | |
1043 | static inline void | |
1044 | ira_allocno_iter_init (ira_allocno_iterator *i) | |
1045 | { | |
1046 | i->n = 0; | |
1047 | } | |
1048 | ||
1049 | /* Return TRUE if we have more allocnos to visit, in which case *A is | |
1050 | set to the allocno to be visited. Otherwise, return FALSE. */ | |
1051 | static inline bool | |
1052 | ira_allocno_iter_cond (ira_allocno_iterator *i, ira_allocno_t *a) | |
1053 | { | |
1054 | int n; | |
1055 | ||
1056 | for (n = i->n; n < ira_allocnos_num; n++) | |
1057 | if (ira_allocnos[n] != NULL) | |
1058 | { | |
1059 | *a = ira_allocnos[n]; | |
1060 | i->n = n + 1; | |
1061 | return true; | |
1062 | } | |
1063 | return false; | |
1064 | } | |
1065 | ||
1066 | /* Loop over all allocnos. In each iteration, A is set to the next | |
1067 | allocno. ITER is an instance of ira_allocno_iterator used to iterate | |
1068 | the allocnos. */ | |
1069 | #define FOR_EACH_ALLOCNO(A, ITER) \ | |
1070 | for (ira_allocno_iter_init (&(ITER)); \ | |
1071 | ira_allocno_iter_cond (&(ITER), &(A));) | |
a49ae217 BS |
1072 | \f |
1073 | /* The iterator for all objects. */ | |
1074 | typedef struct { | |
ac0ab4f7 | 1075 | /* The number of the current element in ira_object_id_map. */ |
a49ae217 BS |
1076 | int n; |
1077 | } ira_object_iterator; | |
058e97ec | 1078 | |
a49ae217 BS |
1079 | /* Initialize the iterator I. */ |
1080 | static inline void | |
1081 | ira_object_iter_init (ira_object_iterator *i) | |
1082 | { | |
1083 | i->n = 0; | |
1084 | } | |
1085 | ||
1086 | /* Return TRUE if we have more objects to visit, in which case *OBJ is | |
1087 | set to the object to be visited. Otherwise, return FALSE. */ | |
1088 | static inline bool | |
1089 | ira_object_iter_cond (ira_object_iterator *i, ira_object_t *obj) | |
1090 | { | |
1091 | int n; | |
058e97ec | 1092 | |
a49ae217 BS |
1093 | for (n = i->n; n < ira_objects_num; n++) |
1094 | if (ira_object_id_map[n] != NULL) | |
1095 | { | |
1096 | *obj = ira_object_id_map[n]; | |
1097 | i->n = n + 1; | |
1098 | return true; | |
1099 | } | |
1100 | return false; | |
1101 | } | |
1102 | ||
ac0ab4f7 BS |
1103 | /* Loop over all objects. In each iteration, OBJ is set to the next |
1104 | object. ITER is an instance of ira_object_iterator used to iterate | |
a49ae217 BS |
1105 | the objects. */ |
1106 | #define FOR_EACH_OBJECT(OBJ, ITER) \ | |
1107 | for (ira_object_iter_init (&(ITER)); \ | |
1108 | ira_object_iter_cond (&(ITER), &(OBJ));) | |
058e97ec | 1109 | \f |
ac0ab4f7 BS |
1110 | /* The iterator for objects associated with an allocno. */ |
1111 | typedef struct { | |
1112 | /* The number of the element the allocno's object array. */ | |
1113 | int n; | |
1114 | } ira_allocno_object_iterator; | |
1115 | ||
1116 | /* Initialize the iterator I. */ | |
1117 | static inline void | |
1118 | ira_allocno_object_iter_init (ira_allocno_object_iterator *i) | |
1119 | { | |
1120 | i->n = 0; | |
1121 | } | |
1122 | ||
1123 | /* Return TRUE if we have more objects to visit in allocno A, in which | |
1124 | case *O is set to the object to be visited. Otherwise, return | |
1125 | FALSE. */ | |
1126 | static inline bool | |
1127 | ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a, | |
1128 | ira_object_t *o) | |
1129 | { | |
d0a854af RG |
1130 | int n = i->n++; |
1131 | if (n < ALLOCNO_NUM_OBJECTS (a)) | |
1132 | { | |
1133 | *o = ALLOCNO_OBJECT (a, n); | |
1134 | return true; | |
1135 | } | |
1136 | return false; | |
ac0ab4f7 BS |
1137 | } |
1138 | ||
1139 | /* Loop over all objects associated with allocno A. In each | |
1140 | iteration, O is set to the next object. ITER is an instance of | |
1141 | ira_allocno_object_iterator used to iterate the conflicts. */ | |
1142 | #define FOR_EACH_ALLOCNO_OBJECT(A, O, ITER) \ | |
1143 | for (ira_allocno_object_iter_init (&(ITER)); \ | |
1144 | ira_allocno_object_iter_cond (&(ITER), (A), &(O));) | |
1145 | \f | |
058e97ec VM |
1146 | |
1147 | /* The iterator for copies. */ | |
1148 | typedef struct { | |
1149 | /* The number of the current element in IRA_COPIES. */ | |
1150 | int n; | |
1151 | } ira_copy_iterator; | |
1152 | ||
1153 | /* Initialize the iterator I. */ | |
1154 | static inline void | |
1155 | ira_copy_iter_init (ira_copy_iterator *i) | |
1156 | { | |
1157 | i->n = 0; | |
1158 | } | |
1159 | ||
1160 | /* Return TRUE if we have more copies to visit, in which case *CP is | |
1161 | set to the copy to be visited. Otherwise, return FALSE. */ | |
1162 | static inline bool | |
1163 | ira_copy_iter_cond (ira_copy_iterator *i, ira_copy_t *cp) | |
1164 | { | |
1165 | int n; | |
1166 | ||
1167 | for (n = i->n; n < ira_copies_num; n++) | |
1168 | if (ira_copies[n] != NULL) | |
1169 | { | |
1170 | *cp = ira_copies[n]; | |
1171 | i->n = n + 1; | |
1172 | return true; | |
1173 | } | |
1174 | return false; | |
1175 | } | |
1176 | ||
1177 | /* Loop over all copies. In each iteration, C is set to the next | |
1178 | copy. ITER is an instance of ira_copy_iterator used to iterate | |
1179 | the copies. */ | |
1180 | #define FOR_EACH_COPY(C, ITER) \ | |
1181 | for (ira_copy_iter_init (&(ITER)); \ | |
1182 | ira_copy_iter_cond (&(ITER), &(C));) | |
058e97ec | 1183 | \f |
ac0ab4f7 | 1184 | /* The iterator for object conflicts. */ |
058e97ec | 1185 | typedef struct { |
ac0ab4f7 BS |
1186 | |
1187 | /* TRUE if the conflicts are represented by vector of allocnos. */ | |
a49ae217 | 1188 | bool conflict_vec_p; |
058e97ec VM |
1189 | |
1190 | /* The conflict vector or conflict bit vector. */ | |
1191 | void *vec; | |
1192 | ||
1193 | /* The number of the current element in the vector (of type | |
a49ae217 | 1194 | ira_object_t or IRA_INT_TYPE). */ |
058e97ec VM |
1195 | unsigned int word_num; |
1196 | ||
1197 | /* The bit vector size. It is defined only if | |
a49ae217 | 1198 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec VM |
1199 | unsigned int size; |
1200 | ||
1201 | /* The current bit index of bit vector. It is defined only if | |
a49ae217 | 1202 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec VM |
1203 | unsigned int bit_num; |
1204 | ||
a49ae217 BS |
1205 | /* The object id corresponding to the 1st bit of the bit vector. It |
1206 | is defined only if OBJECT_CONFLICT_VEC_P is FALSE. */ | |
058e97ec VM |
1207 | int base_conflict_id; |
1208 | ||
1209 | /* The word of bit vector currently visited. It is defined only if | |
a49ae217 | 1210 | OBJECT_CONFLICT_VEC_P is FALSE. */ |
058e97ec | 1211 | unsigned IRA_INT_TYPE word; |
fa86d337 | 1212 | } ira_object_conflict_iterator; |
058e97ec VM |
1213 | |
1214 | /* Initialize the iterator I with ALLOCNO conflicts. */ | |
1215 | static inline void | |
fa86d337 BS |
1216 | ira_object_conflict_iter_init (ira_object_conflict_iterator *i, |
1217 | ira_object_t obj) | |
058e97ec | 1218 | { |
a49ae217 BS |
1219 | i->conflict_vec_p = OBJECT_CONFLICT_VEC_P (obj); |
1220 | i->vec = OBJECT_CONFLICT_ARRAY (obj); | |
058e97ec | 1221 | i->word_num = 0; |
a49ae217 | 1222 | if (i->conflict_vec_p) |
058e97ec VM |
1223 | i->size = i->bit_num = i->base_conflict_id = i->word = 0; |
1224 | else | |
1225 | { | |
a49ae217 | 1226 | if (OBJECT_MIN (obj) > OBJECT_MAX (obj)) |
058e97ec VM |
1227 | i->size = 0; |
1228 | else | |
a49ae217 | 1229 | i->size = ((OBJECT_MAX (obj) - OBJECT_MIN (obj) |
058e97ec VM |
1230 | + IRA_INT_BITS) |
1231 | / IRA_INT_BITS) * sizeof (IRA_INT_TYPE); | |
1232 | i->bit_num = 0; | |
a49ae217 | 1233 | i->base_conflict_id = OBJECT_MIN (obj); |
058e97ec VM |
1234 | i->word = (i->size == 0 ? 0 : ((IRA_INT_TYPE *) i->vec)[0]); |
1235 | } | |
1236 | } | |
1237 | ||
1238 | /* Return TRUE if we have more conflicting allocnos to visit, in which | |
1239 | case *A is set to the allocno to be visited. Otherwise, return | |
1240 | FALSE. */ | |
1241 | static inline bool | |
fa86d337 BS |
1242 | ira_object_conflict_iter_cond (ira_object_conflict_iterator *i, |
1243 | ira_object_t *pobj) | |
058e97ec | 1244 | { |
a49ae217 | 1245 | ira_object_t obj; |
058e97ec | 1246 | |
a49ae217 | 1247 | if (i->conflict_vec_p) |
058e97ec | 1248 | { |
1756cb66 | 1249 | obj = ((ira_object_t *) i->vec)[i->word_num++]; |
a49ae217 | 1250 | if (obj == NULL) |
058e97ec | 1251 | return false; |
058e97ec VM |
1252 | } |
1253 | else | |
1254 | { | |
1756cb66 VM |
1255 | unsigned IRA_INT_TYPE word = i->word; |
1256 | unsigned int bit_num = i->bit_num; | |
1257 | ||
058e97ec | 1258 | /* Skip words that are zeros. */ |
1756cb66 | 1259 | for (; word == 0; word = ((IRA_INT_TYPE *) i->vec)[i->word_num]) |
058e97ec VM |
1260 | { |
1261 | i->word_num++; | |
b8698a0f | 1262 | |
058e97ec VM |
1263 | /* If we have reached the end, break. */ |
1264 | if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size) | |
1265 | return false; | |
b8698a0f | 1266 | |
1756cb66 | 1267 | bit_num = i->word_num * IRA_INT_BITS; |
058e97ec | 1268 | } |
b8698a0f | 1269 | |
058e97ec | 1270 | /* Skip bits that are zero. */ |
1756cb66 VM |
1271 | for (; (word & 1) == 0; word >>= 1) |
1272 | bit_num++; | |
b8698a0f | 1273 | |
1756cb66 VM |
1274 | obj = ira_object_id_map[bit_num + i->base_conflict_id]; |
1275 | i->bit_num = bit_num + 1; | |
1276 | i->word = word >> 1; | |
058e97ec | 1277 | } |
a49ae217 | 1278 | |
fa86d337 | 1279 | *pobj = obj; |
a49ae217 | 1280 | return true; |
058e97ec VM |
1281 | } |
1282 | ||
fa86d337 BS |
1283 | /* Loop over all objects conflicting with OBJ. In each iteration, |
1284 | CONF is set to the next conflicting object. ITER is an instance | |
1285 | of ira_object_conflict_iterator used to iterate the conflicts. */ | |
1286 | #define FOR_EACH_OBJECT_CONFLICT(OBJ, CONF, ITER) \ | |
1287 | for (ira_object_conflict_iter_init (&(ITER), (OBJ)); \ | |
1756cb66 | 1288 | ira_object_conflict_iter_cond (&(ITER), &(CONF));) |
058e97ec VM |
1289 | |
1290 | \f | |
1291 | ||
1756cb66 VM |
1292 | /* The function returns TRUE if at least one hard register from ones |
1293 | starting with HARD_REGNO and containing value of MODE are in set | |
1294 | HARD_REGSET. */ | |
1295 | static inline bool | |
1296 | ira_hard_reg_set_intersection_p (int hard_regno, enum machine_mode mode, | |
1297 | HARD_REG_SET hard_regset) | |
1298 | { | |
1299 | int i; | |
1300 | ||
1301 | gcc_assert (hard_regno >= 0); | |
1302 | for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--) | |
1303 | if (TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) | |
1304 | return true; | |
1305 | return false; | |
1306 | } | |
1307 | ||
1308 | /* Return number of hard registers in hard register SET. */ | |
1309 | static inline int | |
1310 | hard_reg_set_size (HARD_REG_SET set) | |
1311 | { | |
1312 | int i, size; | |
1313 | ||
1314 | for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1315 | if (TEST_HARD_REG_BIT (set, i)) | |
1316 | size++; | |
1317 | return size; | |
1318 | } | |
1319 | ||
058e97ec | 1320 | /* The function returns TRUE if hard registers starting with |
9181a6e5 | 1321 | HARD_REGNO and containing value of MODE are fully in set |
058e97ec VM |
1322 | HARD_REGSET. */ |
1323 | static inline bool | |
9181a6e5 VM |
1324 | ira_hard_reg_in_set_p (int hard_regno, enum machine_mode mode, |
1325 | HARD_REG_SET hard_regset) | |
058e97ec VM |
1326 | { |
1327 | int i; | |
1328 | ||
1329 | ira_assert (hard_regno >= 0); | |
1330 | for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--) | |
9181a6e5 | 1331 | if (!TEST_HARD_REG_BIT (hard_regset, hard_regno + i)) |
058e97ec VM |
1332 | return false; |
1333 | return true; | |
1334 | } | |
1335 | ||
1336 | \f | |
1337 | ||
1338 | /* To save memory we use a lazy approach for allocation and | |
1339 | initialization of the cost vectors. We do this only when it is | |
1340 | really necessary. */ | |
1341 | ||
1756cb66 | 1342 | /* Allocate cost vector *VEC for hard registers of ACLASS and |
058e97ec VM |
1343 | initialize the elements by VAL if it is necessary */ |
1344 | static inline void | |
6f76a878 | 1345 | ira_allocate_and_set_costs (int **vec, reg_class_t aclass, int val) |
058e97ec VM |
1346 | { |
1347 | int i, *reg_costs; | |
1348 | int len; | |
1349 | ||
1350 | if (*vec != NULL) | |
1351 | return; | |
1756cb66 | 1352 | *vec = reg_costs = ira_allocate_cost_vector (aclass); |
6f76a878 | 1353 | len = ira_class_hard_regs_num[(int) aclass]; |
058e97ec VM |
1354 | for (i = 0; i < len; i++) |
1355 | reg_costs[i] = val; | |
1356 | } | |
1357 | ||
1756cb66 VM |
1358 | /* Allocate cost vector *VEC for hard registers of ACLASS and copy |
1359 | values of vector SRC into the vector if it is necessary */ | |
058e97ec | 1360 | static inline void |
1756cb66 | 1361 | ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src) |
058e97ec VM |
1362 | { |
1363 | int len; | |
1364 | ||
1365 | if (*vec != NULL || src == NULL) | |
1366 | return; | |
1756cb66 VM |
1367 | *vec = ira_allocate_cost_vector (aclass); |
1368 | len = ira_class_hard_regs_num[aclass]; | |
058e97ec VM |
1369 | memcpy (*vec, src, sizeof (int) * len); |
1370 | } | |
1371 | ||
1756cb66 VM |
1372 | /* Allocate cost vector *VEC for hard registers of ACLASS and add |
1373 | values of vector SRC into the vector if it is necessary */ | |
058e97ec | 1374 | static inline void |
1756cb66 | 1375 | ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src) |
058e97ec VM |
1376 | { |
1377 | int i, len; | |
1378 | ||
1379 | if (src == NULL) | |
1380 | return; | |
1756cb66 | 1381 | len = ira_class_hard_regs_num[aclass]; |
058e97ec VM |
1382 | if (*vec == NULL) |
1383 | { | |
1756cb66 | 1384 | *vec = ira_allocate_cost_vector (aclass); |
058e97ec VM |
1385 | memset (*vec, 0, sizeof (int) * len); |
1386 | } | |
1387 | for (i = 0; i < len; i++) | |
1388 | (*vec)[i] += src[i]; | |
1389 | } | |
1390 | ||
1756cb66 VM |
1391 | /* Allocate cost vector *VEC for hard registers of ACLASS and copy |
1392 | values of vector SRC into the vector or initialize it by VAL (if | |
1393 | SRC is null). */ | |
058e97ec | 1394 | static inline void |
1756cb66 | 1395 | ira_allocate_and_set_or_copy_costs (int **vec, enum reg_class aclass, |
058e97ec VM |
1396 | int val, int *src) |
1397 | { | |
1398 | int i, *reg_costs; | |
1399 | int len; | |
1400 | ||
1401 | if (*vec != NULL) | |
1402 | return; | |
1756cb66 VM |
1403 | *vec = reg_costs = ira_allocate_cost_vector (aclass); |
1404 | len = ira_class_hard_regs_num[aclass]; | |
058e97ec VM |
1405 | if (src != NULL) |
1406 | memcpy (reg_costs, src, sizeof (int) * len); | |
1407 | else | |
1408 | { | |
1409 | for (i = 0; i < len; i++) | |
1410 | reg_costs[i] = val; | |
1411 | } | |
1412 | } | |
acf41a74 BS |
1413 | |
1414 | extern rtx ira_create_new_reg (rtx); | |
1415 | extern int first_moveable_pseudo, last_moveable_pseudo; |