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058e97ec | 1 | /* IRA processing allocno lives to build allocno live ranges. |
8d9254fc | 2 | Copyright (C) 2006-2020 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
c7131fb2 | 24 | #include "backend.h" |
957060b5 | 25 | #include "target.h" |
058e97ec | 26 | #include "rtl.h" |
957060b5 | 27 | #include "predict.h" |
c7131fb2 | 28 | #include "df.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
058e97ec | 30 | #include "tm_p.h" |
058e97ec | 31 | #include "insn-config.h" |
957060b5 AM |
32 | #include "regs.h" |
33 | #include "ira.h" | |
34 | #include "ira-int.h" | |
058e97ec | 35 | #include "sparseset.h" |
5a5a3bc5 | 36 | #include "function-abi.h" |
058e97ec VM |
37 | |
38 | /* The code in this file is similar to one in global but the code | |
39 | works on the allocno basis and creates live ranges instead of | |
40 | pseudo-register conflicts. */ | |
41 | ||
42 | /* Program points are enumerated by numbers from range | |
43 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
44 | points than insns. Program points are places in the program where | |
45 | liveness info can be changed. In most general case (there are more | |
46 | complicated cases too) some program points correspond to places | |
47 | where input operand dies and other ones correspond to places where | |
48 | output operands are born. */ | |
49 | int ira_max_point; | |
50 | ||
51 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
52 | live ranges with given start/finish point. */ | |
b14151b5 | 53 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec VM |
54 | |
55 | /* Number of the current program point. */ | |
56 | static int curr_point; | |
57 | ||
58 | /* Point where register pressure excess started or -1 if there is no | |
59 | register pressure excess. Excess pressure for a register class at | |
60 | some point means that there are more allocnos of given register | |
61 | class living at the point than number of hard-registers of the | |
1756cb66 VM |
62 | class available for the allocation. It is defined only for |
63 | pressure classes. */ | |
058e97ec VM |
64 | static int high_pressure_start_point[N_REG_CLASSES]; |
65 | ||
ac0ab4f7 BS |
66 | /* Objects live at current point in the scan. */ |
67 | static sparseset objects_live; | |
68 | ||
69 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
70 | multiple times. */ | |
71 | static sparseset allocnos_processed; | |
058e97ec VM |
72 | |
73 | /* Set of hard regs (except eliminable ones) currently live. */ | |
74 | static HARD_REG_SET hard_regs_live; | |
75 | ||
76 | /* The loop tree node corresponding to the current basic block. */ | |
77 | static ira_loop_tree_node_t curr_bb_node; | |
78 | ||
cb1ca6ac VM |
79 | /* The number of the last processed call. */ |
80 | static int last_call_num; | |
81 | /* The number of last call at which given allocno was saved. */ | |
82 | static int *allocno_saved_at_call; | |
83 | ||
6de20b9d RS |
84 | /* The value returned by ira_setup_alts for the current instruction; |
85 | i.e. the set of alternatives that we should consider to be likely | |
86 | candidates during reloading. */ | |
9840b2fa RS |
87 | static alternative_mask preferred_alternatives; |
88 | ||
a141f2d8 PB |
89 | /* If non-NULL, the source operand of a register to register copy for which |
90 | we should not add a conflict with the copy's destination operand. */ | |
91 | static rtx ignore_reg_for_conflicts; | |
92 | ||
0df92803 | 93 | /* Record hard register REGNO as now being live. */ |
058e97ec | 94 | static void |
0df92803 | 95 | make_hard_regno_live (int regno) |
058e97ec | 96 | { |
3c55880a | 97 | SET_HARD_REG_BIT (hard_regs_live, regno); |
0df92803 PB |
98 | } |
99 | ||
100 | /* Process the definition of hard register REGNO. This updates | |
101 | hard_regs_live and hard reg conflict information for living allocnos. */ | |
102 | static void | |
103 | make_hard_regno_dead (int regno) | |
104 | { | |
105 | unsigned int i; | |
ac0ab4f7 | 106 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 107 | { |
ac0ab4f7 | 108 | ira_object_t obj = ira_object_id_map[i]; |
1756cb66 | 109 | |
a141f2d8 PB |
110 | if (ignore_reg_for_conflicts != NULL_RTX |
111 | && REGNO (ignore_reg_for_conflicts) | |
112 | == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj))) | |
113 | continue; | |
114 | ||
a49ae217 BS |
115 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
116 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
058e97ec | 117 | } |
3c55880a BS |
118 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); |
119 | } | |
120 | ||
0df92803 PB |
121 | /* Record object OBJ as now being live. Set a bit for it in objects_live, |
122 | and start a new live range for it if necessary. */ | |
3c55880a | 123 | static void |
0df92803 | 124 | make_object_live (ira_object_t obj) |
3c55880a | 125 | { |
ac0ab4f7 | 126 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
3c55880a | 127 | |
0df92803 | 128 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
ac0ab4f7 BS |
129 | if (lr == NULL |
130 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
131 | ira_add_live_range_to_object (obj, curr_point, -1); | |
058e97ec VM |
132 | } |
133 | ||
ac0ab4f7 BS |
134 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
135 | associated with object OBJ. */ | |
058e97ec | 136 | static void |
ac0ab4f7 | 137 | update_allocno_pressure_excess_length (ira_object_t obj) |
058e97ec | 138 | { |
ac0ab4f7 | 139 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
7db7ed3c | 140 | int start, i; |
1756cb66 | 141 | enum reg_class aclass, pclass, cl; |
b14151b5 | 142 | live_range_t p; |
058e97ec | 143 | |
1756cb66 VM |
144 | aclass = ALLOCNO_CLASS (a); |
145 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 146 | for (i = 0; |
1756cb66 | 147 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
148 | i++) |
149 | { | |
1756cb66 VM |
150 | if (! ira_reg_pressure_class_p[cl]) |
151 | continue; | |
7db7ed3c VM |
152 | if (high_pressure_start_point[cl] < 0) |
153 | continue; | |
9140d27b | 154 | p = OBJECT_LIVE_RANGES (obj); |
7db7ed3c VM |
155 | ira_assert (p != NULL); |
156 | start = (high_pressure_start_point[cl] > p->start | |
157 | ? high_pressure_start_point[cl] : p->start); | |
158 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
159 | } | |
058e97ec VM |
160 | } |
161 | ||
0df92803 PB |
162 | /* Process the definition of object OBJ, which is associated with allocno A. |
163 | This finishes the current live range for it. */ | |
058e97ec | 164 | static void |
ac0ab4f7 | 165 | make_object_dead (ira_object_t obj) |
058e97ec | 166 | { |
ac0ab4f7 | 167 | live_range_t lr; |
8503f963 | 168 | int regno; |
a141f2d8 | 169 | int ignore_regno = -1; |
8503f963 | 170 | int ignore_total_regno = -1; |
a141f2d8 | 171 | int end_regno = -1; |
058e97ec | 172 | |
ac0ab4f7 | 173 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
0df92803 | 174 | |
a141f2d8 PB |
175 | /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts |
176 | with OBJ. */ | |
177 | if (ignore_reg_for_conflicts != NULL_RTX | |
178 | && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER) | |
179 | { | |
180 | end_regno = END_REGNO (ignore_reg_for_conflicts); | |
8503f963 | 181 | ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts); |
a141f2d8 | 182 | |
8503f963 | 183 | for (regno = ignore_regno; regno < end_regno; regno++) |
a141f2d8 | 184 | { |
8503f963 PB |
185 | if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno)) |
186 | ignore_regno = end_regno; | |
187 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
188 | ignore_total_regno = end_regno; | |
a141f2d8 PB |
189 | } |
190 | } | |
191 | ||
44942965 RS |
192 | OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live; |
193 | OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live; | |
0df92803 | 194 | |
a141f2d8 PB |
195 | /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make |
196 | sure it still doesn't. */ | |
8503f963 PB |
197 | for (regno = ignore_regno; regno < end_regno; regno++) |
198 | CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); | |
199 | for (regno = ignore_total_regno; regno < end_regno; regno++) | |
200 | CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
a141f2d8 | 201 | |
ac0ab4f7 BS |
202 | lr = OBJECT_LIVE_RANGES (obj); |
203 | ira_assert (lr != NULL); | |
204 | lr->finish = curr_point; | |
205 | update_allocno_pressure_excess_length (obj); | |
058e97ec VM |
206 | } |
207 | ||
1756cb66 | 208 | /* The current register pressures for each pressure class for the current |
058e97ec VM |
209 | basic block. */ |
210 | static int curr_reg_pressure[N_REG_CLASSES]; | |
211 | ||
1756cb66 VM |
212 | /* Record that register pressure for PCLASS increased by N registers. |
213 | Update the current register pressure, maximal register pressure for | |
214 | the current BB and the start point of the register pressure | |
215 | excess. */ | |
058e97ec | 216 | static void |
1756cb66 | 217 | inc_register_pressure (enum reg_class pclass, int n) |
058e97ec | 218 | { |
7db7ed3c | 219 | int i; |
3c55880a | 220 | enum reg_class cl; |
058e97ec | 221 | |
7db7ed3c | 222 | for (i = 0; |
1756cb66 | 223 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
224 | i++) |
225 | { | |
1756cb66 VM |
226 | if (! ira_reg_pressure_class_p[cl]) |
227 | continue; | |
3c55880a | 228 | curr_reg_pressure[cl] += n; |
7db7ed3c | 229 | if (high_pressure_start_point[cl] < 0 |
f508f827 | 230 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
7db7ed3c VM |
231 | high_pressure_start_point[cl] = curr_point; |
232 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
233 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
234 | } | |
058e97ec VM |
235 | } |
236 | ||
1756cb66 VM |
237 | /* Record that register pressure for PCLASS has decreased by NREGS |
238 | registers; update current register pressure, start point of the | |
239 | register pressure excess, and register pressure excess length for | |
240 | living allocnos. */ | |
3c55880a | 241 | |
058e97ec | 242 | static void |
1756cb66 | 243 | dec_register_pressure (enum reg_class pclass, int nregs) |
058e97ec | 244 | { |
7db7ed3c VM |
245 | int i; |
246 | unsigned int j; | |
3c55880a BS |
247 | enum reg_class cl; |
248 | bool set_p = false; | |
058e97ec | 249 | |
3c55880a | 250 | for (i = 0; |
1756cb66 | 251 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
3c55880a | 252 | i++) |
058e97ec | 253 | { |
1756cb66 VM |
254 | if (! ira_reg_pressure_class_p[cl]) |
255 | continue; | |
3c55880a BS |
256 | curr_reg_pressure[cl] -= nregs; |
257 | ira_assert (curr_reg_pressure[cl] >= 0); | |
258 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 259 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
3c55880a BS |
260 | set_p = true; |
261 | } | |
262 | if (set_p) | |
263 | { | |
ac0ab4f7 BS |
264 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
265 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
7db7ed3c | 266 | for (i = 0; |
1756cb66 | 267 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c | 268 | i++) |
1756cb66 VM |
269 | { |
270 | if (! ira_reg_pressure_class_p[cl]) | |
271 | continue; | |
272 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 273 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
1756cb66 VM |
274 | high_pressure_start_point[cl] = -1; |
275 | } | |
058e97ec | 276 | } |
058e97ec VM |
277 | } |
278 | ||
e384e6b5 BS |
279 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
280 | and occupies only one object. Return false if we have no information. */ | |
281 | static bool | |
282 | pseudo_regno_single_word_and_live_p (int regno) | |
283 | { | |
284 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
285 | ira_object_t obj; | |
286 | ||
287 | if (a == NULL) | |
288 | return false; | |
289 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
290 | return false; | |
291 | ||
292 | obj = ALLOCNO_OBJECT (a, 0); | |
293 | ||
294 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
295 | } | |
296 | ||
3c55880a BS |
297 | /* Mark the pseudo register REGNO as live. Update all information about |
298 | live ranges and register pressure. */ | |
058e97ec | 299 | static void |
3c55880a | 300 | mark_pseudo_regno_live (int regno) |
058e97ec | 301 | { |
3c55880a | 302 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
1756cb66 | 303 | enum reg_class pclass; |
ac0ab4f7 | 304 | int i, n, nregs; |
058e97ec | 305 | |
3c55880a BS |
306 | if (a == NULL) |
307 | return; | |
058e97ec | 308 | |
3c55880a BS |
309 | /* Invalidate because it is referenced. */ |
310 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 311 | |
ac0ab4f7 | 312 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
313 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
314 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
315 | if (n > 1) |
316 | { | |
317 | /* We track every subobject separately. */ | |
318 | gcc_assert (nregs == n); | |
319 | nregs = 1; | |
320 | } | |
321 | ||
322 | for (i = 0; i < n; i++) | |
323 | { | |
324 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1756cb66 | 325 | |
ac0ab4f7 BS |
326 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
327 | continue; | |
328 | ||
1756cb66 | 329 | inc_register_pressure (pclass, nregs); |
0df92803 | 330 | make_object_live (obj); |
ac0ab4f7 BS |
331 | } |
332 | } | |
333 | ||
334 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
335 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
336 | indicates the low part. */ | |
337 | static void | |
338 | mark_pseudo_regno_subword_live (int regno, int subword) | |
339 | { | |
340 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 341 | int n; |
1756cb66 | 342 | enum reg_class pclass; |
ac0ab4f7 BS |
343 | ira_object_t obj; |
344 | ||
345 | if (a == NULL) | |
3c55880a BS |
346 | return; |
347 | ||
ac0ab4f7 BS |
348 | /* Invalidate because it is referenced. */ |
349 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
350 | ||
351 | n = ALLOCNO_NUM_OBJECTS (a); | |
352 | if (n == 1) | |
353 | { | |
354 | mark_pseudo_regno_live (regno); | |
355 | return; | |
356 | } | |
357 | ||
1756cb66 | 358 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
359 | gcc_assert |
360 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
361 | obj = ALLOCNO_OBJECT (a, subword); |
362 | ||
363 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
364 | return; | |
365 | ||
51935358 | 366 | inc_register_pressure (pclass, 1); |
0df92803 | 367 | make_object_live (obj); |
3c55880a BS |
368 | } |
369 | ||
ac0ab4f7 BS |
370 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
371 | this register, record how many consecutive hardware registers it | |
372 | actually needs. */ | |
3c55880a BS |
373 | static void |
374 | mark_hard_reg_live (rtx reg) | |
375 | { | |
376 | int regno = REGNO (reg); | |
377 | ||
378 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec | 379 | { |
dc8afb70 | 380 | int last = END_REGNO (reg); |
1756cb66 | 381 | enum reg_class aclass, pclass; |
058e97ec VM |
382 | |
383 | while (regno < last) | |
384 | { | |
385 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
386 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
387 | { | |
1756cb66 VM |
388 | aclass = ira_hard_regno_allocno_class[regno]; |
389 | pclass = ira_pressure_class_translate[aclass]; | |
390 | inc_register_pressure (pclass, 1); | |
0df92803 | 391 | make_hard_regno_live (regno); |
058e97ec VM |
392 | } |
393 | regno++; | |
394 | } | |
395 | } | |
396 | } | |
397 | ||
579c1bf3 BS |
398 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
399 | register number; ORIG_REG is the access in the insn, which may be a | |
400 | subreg. */ | |
401 | static void | |
402 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
403 | { | |
33845ca9 | 404 | if (read_modify_subreg_p (orig_reg)) |
579c1bf3 BS |
405 | { |
406 | mark_pseudo_regno_subword_live (regno, | |
407 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
408 | } | |
409 | else | |
410 | mark_pseudo_regno_live (regno); | |
411 | } | |
412 | ||
3517d3a0 VM |
413 | /* Mark the register referenced by use or def REF as live. */ |
414 | static void | |
57512f53 | 415 | mark_ref_live (df_ref ref) |
058e97ec | 416 | { |
ac0ab4f7 BS |
417 | rtx reg = DF_REF_REG (ref); |
418 | rtx orig_reg = reg; | |
3517d3a0 | 419 | |
3517d3a0 VM |
420 | if (GET_CODE (reg) == SUBREG) |
421 | reg = SUBREG_REG (reg); | |
ac0ab4f7 | 422 | |
3c55880a | 423 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 424 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
3c55880a BS |
425 | else |
426 | mark_hard_reg_live (reg); | |
058e97ec VM |
427 | } |
428 | ||
3c55880a BS |
429 | /* Mark the pseudo register REGNO as dead. Update all information about |
430 | live ranges and register pressure. */ | |
058e97ec | 431 | static void |
3c55880a | 432 | mark_pseudo_regno_dead (int regno) |
058e97ec | 433 | { |
3c55880a | 434 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
ac0ab4f7 | 435 | int n, i, nregs; |
3c55880a | 436 | enum reg_class cl; |
058e97ec | 437 | |
3c55880a BS |
438 | if (a == NULL) |
439 | return; | |
058e97ec | 440 | |
3c55880a BS |
441 | /* Invalidate because it is referenced. */ |
442 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 443 | |
ac0ab4f7 | 444 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
445 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
446 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
447 | if (n > 1) |
448 | { | |
449 | /* We track every subobject separately. */ | |
450 | gcc_assert (nregs == n); | |
451 | nregs = 1; | |
452 | } | |
453 | for (i = 0; i < n; i++) | |
454 | { | |
455 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
456 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
457 | continue; | |
458 | ||
459 | dec_register_pressure (cl, nregs); | |
460 | make_object_dead (obj); | |
461 | } | |
462 | } | |
463 | ||
464 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
465 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
466 | static void | |
467 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
468 | { | |
469 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 470 | int n; |
ac0ab4f7 BS |
471 | enum reg_class cl; |
472 | ira_object_t obj; | |
473 | ||
474 | if (a == NULL) | |
475 | return; | |
476 | ||
477 | /* Invalidate because it is referenced. */ | |
478 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
479 | ||
480 | n = ALLOCNO_NUM_OBJECTS (a); | |
481 | if (n == 1) | |
482 | /* The allocno as a whole doesn't die in this case. */ | |
3c55880a BS |
483 | return; |
484 | ||
1756cb66 | 485 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
486 | gcc_assert |
487 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
488 | |
489 | obj = ALLOCNO_OBJECT (a, subword); | |
490 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
491 | return; | |
3c55880a | 492 | |
ac0ab4f7 BS |
493 | dec_register_pressure (cl, 1); |
494 | make_object_dead (obj); | |
3c55880a BS |
495 | } |
496 | ||
0df92803 PB |
497 | /* Process the definition of hard register REG. This updates hard_regs_live |
498 | and hard reg conflict information for living allocnos. */ | |
3c55880a BS |
499 | static void |
500 | mark_hard_reg_dead (rtx reg) | |
501 | { | |
502 | int regno = REGNO (reg); | |
503 | ||
504 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec | 505 | { |
53d1bae9 | 506 | int last = END_REGNO (reg); |
1756cb66 | 507 | enum reg_class aclass, pclass; |
058e97ec VM |
508 | |
509 | while (regno < last) | |
510 | { | |
511 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
512 | { | |
1756cb66 VM |
513 | aclass = ira_hard_regno_allocno_class[regno]; |
514 | pclass = ira_pressure_class_translate[aclass]; | |
515 | dec_register_pressure (pclass, 1); | |
3c55880a | 516 | make_hard_regno_dead (regno); |
058e97ec VM |
517 | } |
518 | regno++; | |
519 | } | |
520 | } | |
521 | } | |
522 | ||
579c1bf3 BS |
523 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
524 | register number; ORIG_REG is the access in the insn, which may be a | |
525 | subreg. */ | |
526 | static void | |
527 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
528 | { | |
33845ca9 | 529 | if (read_modify_subreg_p (orig_reg)) |
579c1bf3 BS |
530 | { |
531 | mark_pseudo_regno_subword_dead (regno, | |
532 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
533 | } | |
534 | else | |
535 | mark_pseudo_regno_dead (regno); | |
536 | } | |
537 | ||
3517d3a0 VM |
538 | /* Mark the register referenced by definition DEF as dead, if the |
539 | definition is a total one. */ | |
540 | static void | |
57512f53 | 541 | mark_ref_dead (df_ref def) |
3517d3a0 | 542 | { |
ac0ab4f7 BS |
543 | rtx reg = DF_REF_REG (def); |
544 | rtx orig_reg = reg; | |
3517d3a0 | 545 | |
ac0ab4f7 | 546 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
3517d3a0 VM |
547 | return; |
548 | ||
3517d3a0 VM |
549 | if (GET_CODE (reg) == SUBREG) |
550 | reg = SUBREG_REG (reg); | |
ac0ab4f7 BS |
551 | |
552 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
553 | && (GET_CODE (orig_reg) != SUBREG | |
554 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
33845ca9 | 555 | || !read_modify_subreg_p (orig_reg))) |
ac0ab4f7 BS |
556 | return; |
557 | ||
3c55880a | 558 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 559 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
3c55880a BS |
560 | else |
561 | mark_hard_reg_dead (reg); | |
3517d3a0 VM |
562 | } |
563 | ||
579c1bf3 BS |
564 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
565 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
073a8998 | 566 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
579c1bf3 BS |
567 | Advance the current program point before making the conflict if |
568 | ADVANCE_P. Return TRUE if we will need to advance the current | |
569 | program point. */ | |
3517d3a0 | 570 | static bool |
579c1bf3 BS |
571 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
572 | bool advance_p) | |
3517d3a0 | 573 | { |
579c1bf3 | 574 | rtx orig_reg = reg; |
22c02455 | 575 | ira_allocno_t a; |
3517d3a0 | 576 | |
22c02455 VM |
577 | if (GET_CODE (reg) == SUBREG) |
578 | reg = SUBREG_REG (reg); | |
b8698a0f | 579 | |
22c02455 VM |
580 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
581 | return advance_p; | |
b8698a0f | 582 | |
22c02455 | 583 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
1756cb66 | 584 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
22c02455 | 585 | return advance_p; |
3517d3a0 | 586 | |
22c02455 VM |
587 | if (advance_p) |
588 | curr_point++; | |
3517d3a0 | 589 | |
579c1bf3 BS |
590 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
591 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
592 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
593 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
22c02455 VM |
594 | |
595 | return false; | |
596 | } | |
3517d3a0 | 597 | |
22c02455 VM |
598 | /* Check and make if necessary conflicts for pseudo DREG of class |
599 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
073a8998 | 600 | ORIG_DREG is the rtx actually accessed, it may be identical to |
579c1bf3 BS |
601 | DREG or a subreg of it. Advance the current program point before |
602 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
603 | advance the current program point. */ | |
22c02455 | 604 | static bool |
579c1bf3 BS |
605 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
606 | enum reg_class def_cl, int use, | |
607 | enum reg_class use_cl, bool advance_p) | |
22c02455 VM |
608 | { |
609 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
610 | return advance_p; | |
b8698a0f | 611 | |
22c02455 | 612 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
579c1bf3 BS |
613 | use_cl, dreg, orig_dreg, advance_p); |
614 | ||
22c02455 VM |
615 | /* Reload may end up swapping commutative operands, so you |
616 | have to take both orderings into account. The | |
617 | constraints for the two operands can be completely | |
618 | different. (Indeed, if the constraints for the two | |
619 | operands are the same for all alternatives, there's no | |
620 | point marking them as commutative.) */ | |
dc344e87 | 621 | if (use < recog_data.n_operands - 1 |
22c02455 VM |
622 | && recog_data.constraints[use][0] == '%') |
623 | advance_p | |
624 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
579c1bf3 | 625 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
626 | if (use >= 1 |
627 | && recog_data.constraints[use - 1][0] == '%') | |
628 | advance_p | |
629 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
579c1bf3 | 630 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
631 | return advance_p; |
632 | } | |
633 | ||
634 | /* Check and make if necessary conflicts for definition DEF of class | |
635 | DEF_CL of the current insn with input operands. Process only | |
9b036587 RS |
636 | constraints of alternative ALT. |
637 | ||
638 | One of three things is true when this function is called: | |
639 | ||
640 | (1) DEF is an earlyclobber for alternative ALT. Input operands then | |
641 | conflict with DEF in ALT unless they explicitly match DEF via 0-9 | |
642 | constraints. | |
643 | ||
644 | (2) DEF matches (via 0-9 constraints) an operand that is an | |
645 | earlyclobber for alternative ALT. Other input operands then | |
646 | conflict with DEF in ALT. | |
647 | ||
648 | (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT. | |
649 | Input operands with a different value from X then conflict with | |
650 | DEF in ALT. | |
651 | ||
652 | However, there's still a judgement call to make when deciding | |
653 | whether a conflict in ALT is important enough to be reflected | |
654 | in the pan-alternative allocno conflict set. */ | |
22c02455 | 655 | static void |
9b036587 RS |
656 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl, |
657 | bool for_tie_p) | |
22c02455 VM |
658 | { |
659 | int use, use_match; | |
660 | ira_allocno_t a; | |
661 | enum reg_class use_cl, acl; | |
662 | bool advance_p; | |
663 | rtx dreg = recog_data.operand[def]; | |
579c1bf3 | 664 | rtx orig_dreg = dreg; |
b8698a0f | 665 | |
22c02455 VM |
666 | if (def_cl == NO_REGS) |
667 | return; | |
b8698a0f | 668 | |
22c02455 VM |
669 | if (GET_CODE (dreg) == SUBREG) |
670 | dreg = SUBREG_REG (dreg); | |
b8698a0f | 671 | |
22c02455 VM |
672 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
673 | return; | |
b8698a0f | 674 | |
22c02455 | 675 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
1756cb66 | 676 | acl = ALLOCNO_CLASS (a); |
22c02455 VM |
677 | if (! reg_classes_intersect_p (acl, def_cl)) |
678 | return; | |
b8698a0f | 679 | |
22c02455 | 680 | advance_p = true; |
b8698a0f | 681 | |
29d70a0f | 682 | int n_operands = recog_data.n_operands; |
1145837d | 683 | const operand_alternative *op_alt = &recog_op_alt[alt * n_operands]; |
29d70a0f | 684 | for (use = 0; use < n_operands; use++) |
22c02455 | 685 | { |
002b2dee BS |
686 | int alt1; |
687 | ||
22c02455 | 688 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
7ba06dee | 689 | continue; |
b8698a0f | 690 | |
9b036587 RS |
691 | /* An earlyclobber on DEF doesn't apply to an input operand X if X |
692 | explicitly matches DEF, but it applies to other input operands | |
693 | even if they happen to be the same value as X. | |
694 | ||
695 | In contrast, if an input operand X is tied to a non-earlyclobber | |
696 | DEF, there's no conflict with other input operands that have the | |
697 | same value as X. */ | |
698 | if (op_alt[use].matches == def | |
699 | || (for_tie_p | |
700 | && rtx_equal_p (recog_data.operand[use], | |
701 | recog_data.operand[op_alt[def].matched]))) | |
702 | continue; | |
703 | ||
29d70a0f | 704 | if (op_alt[use].anything_ok) |
22c02455 | 705 | use_cl = ALL_REGS; |
3517d3a0 | 706 | else |
29d70a0f | 707 | use_cl = op_alt[use].cl; |
9b036587 RS |
708 | if (use_cl == NO_REGS) |
709 | continue; | |
710 | ||
711 | /* If DEF is simply a tied operand, ignore cases in which this | |
712 | alternative requires USE to have a likely-spilled class. | |
713 | Adding a conflict would just constrain USE further if DEF | |
714 | happens to be allocated first. */ | |
715 | if (for_tie_p && targetm.class_likely_spilled_p (use_cl)) | |
716 | continue; | |
b8698a0f | 717 | |
002b2dee BS |
718 | /* If there's any alternative that allows USE to match DEF, do not |
719 | record a conflict. If that causes us to create an invalid | |
9b036587 RS |
720 | instruction due to the earlyclobber, reload must fix it up. |
721 | ||
722 | Likewise, if we're treating a tied DEF like a partial earlyclobber, | |
723 | do not record a conflict if there's another alternative in which | |
724 | DEF is neither tied nor earlyclobber. */ | |
002b2dee | 725 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
29d70a0f | 726 | { |
9840b2fa | 727 | if (!TEST_BIT (preferred_alternatives, alt1)) |
5f2e0797 | 728 | continue; |
1145837d RS |
729 | const operand_alternative *op_alt1 |
730 | = &recog_op_alt[alt1 * n_operands]; | |
29d70a0f RS |
731 | if (op_alt1[use].matches == def |
732 | || (use < n_operands - 1 | |
733 | && recog_data.constraints[use][0] == '%' | |
734 | && op_alt1[use + 1].matches == def) | |
735 | || (use >= 1 | |
736 | && recog_data.constraints[use - 1][0] == '%' | |
737 | && op_alt1[use - 1].matches == def)) | |
738 | break; | |
9b036587 RS |
739 | if (for_tie_p |
740 | && !op_alt1[def].earlyclobber | |
741 | && op_alt1[def].matched < 0 | |
742 | && alternative_class (op_alt1, def) != NO_REGS | |
743 | && alternative_class (op_alt1, use) != NO_REGS) | |
744 | break; | |
29d70a0f | 745 | } |
002b2dee BS |
746 | |
747 | if (alt1 < recog_data.n_alternatives) | |
748 | continue; | |
749 | ||
579c1bf3 BS |
750 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
751 | use, use_cl, advance_p); | |
b8698a0f | 752 | |
29d70a0f | 753 | if ((use_match = op_alt[use].matches) >= 0) |
22c02455 | 754 | { |
9b036587 | 755 | gcc_checking_assert (use_match != def); |
b8698a0f | 756 | |
29d70a0f | 757 | if (op_alt[use_match].anything_ok) |
22c02455 VM |
758 | use_cl = ALL_REGS; |
759 | else | |
29d70a0f | 760 | use_cl = op_alt[use_match].cl; |
579c1bf3 BS |
761 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
762 | use, use_cl, advance_p); | |
22c02455 | 763 | } |
3517d3a0 | 764 | } |
22c02455 VM |
765 | } |
766 | ||
767 | /* Make conflicts of early clobber pseudo registers of the current | |
768 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
769 | checking classes of the constraints and pseudos because otherwise | |
9b036587 RS |
770 | significant code degradation is possible for some targets. |
771 | ||
772 | For these purposes, tying an input to an output makes that output act | |
773 | like an earlyclobber for inputs with a different value, since the output | |
774 | register then has a predetermined purpose on input to the instruction. */ | |
22c02455 VM |
775 | static void |
776 | make_early_clobber_and_input_conflicts (void) | |
777 | { | |
778 | int alt; | |
779 | int def, def_match; | |
780 | enum reg_class def_cl; | |
781 | ||
29d70a0f RS |
782 | int n_alternatives = recog_data.n_alternatives; |
783 | int n_operands = recog_data.n_operands; | |
1145837d | 784 | const operand_alternative *op_alt = recog_op_alt; |
29d70a0f | 785 | for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands) |
9840b2fa | 786 | if (TEST_BIT (preferred_alternatives, alt)) |
5f2e0797 RS |
787 | for (def = 0; def < n_operands; def++) |
788 | { | |
9b036587 RS |
789 | if (op_alt[def].anything_ok) |
790 | def_cl = ALL_REGS; | |
791 | else | |
792 | def_cl = op_alt[def].cl; | |
793 | if (def_cl != NO_REGS) | |
5f2e0797 | 794 | { |
9b036587 RS |
795 | if (op_alt[def].earlyclobber) |
796 | check_and_make_def_conflict (alt, def, def_cl, false); | |
797 | else if (op_alt[def].matched >= 0 | |
798 | && !targetm.class_likely_spilled_p (def_cl)) | |
799 | check_and_make_def_conflict (alt, def, def_cl, true); | |
5f2e0797 | 800 | } |
9b036587 | 801 | |
5f2e0797 RS |
802 | if ((def_match = op_alt[def].matches) >= 0 |
803 | && (op_alt[def_match].earlyclobber | |
804 | || op_alt[def].earlyclobber)) | |
805 | { | |
806 | if (op_alt[def_match].anything_ok) | |
807 | def_cl = ALL_REGS; | |
808 | else | |
809 | def_cl = op_alt[def_match].cl; | |
9b036587 | 810 | check_and_make_def_conflict (alt, def, def_cl, false); |
5f2e0797 RS |
811 | } |
812 | } | |
22c02455 VM |
813 | } |
814 | ||
815 | /* Mark early clobber hard registers of the current INSN as live (if | |
816 | LIVE_P) or dead. Return true if there are such registers. */ | |
817 | static bool | |
070a1983 | 818 | mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p) |
22c02455 | 819 | { |
bfac633a | 820 | df_ref def; |
22c02455 | 821 | bool set_p = false; |
3517d3a0 | 822 | |
bfac633a RS |
823 | FOR_EACH_INSN_DEF (def, insn) |
824 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)) | |
3517d3a0 | 825 | { |
bfac633a | 826 | rtx dreg = DF_REF_REG (def); |
b8698a0f | 827 | |
3517d3a0 VM |
828 | if (GET_CODE (dreg) == SUBREG) |
829 | dreg = SUBREG_REG (dreg); | |
830 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
831 | continue; | |
832 | ||
833 | /* Hard register clobbers are believed to be early clobber | |
834 | because there is no way to say that non-operand hard | |
b8698a0f | 835 | register clobbers are not early ones. */ |
3517d3a0 | 836 | if (live_p) |
bfac633a | 837 | mark_ref_live (def); |
3517d3a0 | 838 | else |
bfac633a | 839 | mark_ref_dead (def); |
3517d3a0 VM |
840 | set_p = true; |
841 | } | |
842 | ||
843 | return set_p; | |
844 | } | |
845 | ||
058e97ec VM |
846 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
847 | it is so, the function returns the class of the hard register. | |
848 | Otherwise it returns NO_REGS. */ | |
849 | static enum reg_class | |
850 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
851 | { | |
4cc8d9d2 | 852 | int c; |
058e97ec | 853 | enum reg_class cl, next_cl; |
777e635f | 854 | enum constraint_num cn; |
058e97ec VM |
855 | |
856 | cl = NO_REGS; | |
9840b2fa | 857 | alternative_mask preferred = preferred_alternatives; |
4cc8d9d2 RS |
858 | for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)) |
859 | if (c == '#') | |
9840b2fa | 860 | preferred &= ~ALTERNATIVE_BIT (0); |
058e97ec | 861 | else if (c == ',') |
9840b2fa RS |
862 | preferred >>= 1; |
863 | else if (preferred & 1) | |
058e97ec VM |
864 | switch (c) |
865 | { | |
8677664e RS |
866 | case 'g': |
867 | return NO_REGS; | |
b8698a0f | 868 | |
8677664e | 869 | default: |
b58923e2 | 870 | /* ??? Is this the best way to handle memory constraints? */ |
777e635f RS |
871 | cn = lookup_constraint (constraints); |
872 | if (insn_extra_memory_constraint (cn) | |
9eb1ca69 | 873 | || insn_extra_special_memory_constraint (cn) |
777e635f | 874 | || insn_extra_address_constraint (cn)) |
b58923e2 | 875 | return NO_REGS; |
777e635f | 876 | if (constraint_satisfied_p (op, cn) |
b58923e2 RS |
877 | || (equiv_const != NULL_RTX |
878 | && CONSTANT_P (equiv_const) | |
777e635f | 879 | && constraint_satisfied_p (equiv_const, cn))) |
b58923e2 | 880 | return NO_REGS; |
8677664e | 881 | next_cl = reg_class_for_constraint (cn); |
b58923e2 RS |
882 | if (next_cl == NO_REGS) |
883 | break; | |
c9d74da6 RS |
884 | if (cl == NO_REGS |
885 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
886 | : (ira_class_singleton[cl][GET_MODE (op)] | |
887 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
888 | return NO_REGS; |
889 | cl = next_cl; | |
890 | break; | |
b8698a0f | 891 | |
058e97ec VM |
892 | case '0': case '1': case '2': case '3': case '4': |
893 | case '5': case '6': case '7': case '8': case '9': | |
894 | next_cl | |
895 | = single_reg_class (recog_data.constraints[c - '0'], | |
896 | recog_data.operand[c - '0'], NULL_RTX); | |
c9d74da6 RS |
897 | if (cl == NO_REGS |
898 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
899 | : (ira_class_singleton[cl][GET_MODE (op)] | |
900 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
901 | return NO_REGS; |
902 | cl = next_cl; | |
903 | break; | |
058e97ec VM |
904 | } |
905 | return cl; | |
906 | } | |
907 | ||
908 | /* The function checks that operand OP_NUM of the current insn can use | |
909 | only one hard register. If it is so, the function returns the | |
910 | class of the hard register. Otherwise it returns NO_REGS. */ | |
911 | static enum reg_class | |
912 | single_reg_operand_class (int op_num) | |
913 | { | |
914 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
915 | return NO_REGS; | |
916 | return single_reg_class (recog_data.constraints[op_num], | |
917 | recog_data.operand[op_num], NULL_RTX); | |
918 | } | |
919 | ||
ce18efcb VM |
920 | /* The function sets up hard register set *SET to hard registers which |
921 | might be used by insn reloads because the constraints are too | |
922 | strict. */ | |
923 | void | |
8f3f5ac0 L |
924 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set, |
925 | alternative_mask preferred) | |
ce18efcb | 926 | { |
4cc8d9d2 | 927 | int i, c, regno = 0; |
ce18efcb VM |
928 | enum reg_class cl; |
929 | rtx op; | |
ef4bddc2 | 930 | machine_mode mode; |
ce18efcb VM |
931 | |
932 | CLEAR_HARD_REG_SET (*set); | |
933 | for (i = 0; i < recog_data.n_operands; i++) | |
934 | { | |
935 | op = recog_data.operand[i]; | |
936 | ||
937 | if (GET_CODE (op) == SUBREG) | |
938 | op = SUBREG_REG (op); | |
b8698a0f | 939 | |
ce18efcb VM |
940 | if (GET_CODE (op) == SCRATCH |
941 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
942 | { | |
943 | const char *p = recog_data.constraints[i]; | |
944 | ||
945 | mode = (GET_CODE (op) == SCRATCH | |
946 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
947 | cl = NO_REGS; | |
4cc8d9d2 RS |
948 | for (; (c = *p); p += CONSTRAINT_LEN (c, p)) |
949 | if (c == '#') | |
9840b2fa | 950 | preferred &= ~ALTERNATIVE_BIT (0); |
ce18efcb | 951 | else if (c == ',') |
9840b2fa RS |
952 | preferred >>= 1; |
953 | else if (preferred & 1) | |
8677664e RS |
954 | { |
955 | cl = reg_class_for_constraint (lookup_constraint (p)); | |
956 | if (cl != NO_REGS) | |
957 | { | |
958 | /* There is no register pressure problem if all of the | |
959 | regs in this class are fixed. */ | |
960 | int regno = ira_class_singleton[cl][mode]; | |
961 | if (regno >= 0) | |
962 | add_to_hard_reg_set (set, mode, regno); | |
963 | } | |
964 | } | |
ce18efcb VM |
965 | } |
966 | } | |
967 | } | |
058e97ec VM |
968 | /* Processes input operands, if IN_P, or output operands otherwise of |
969 | the current insn with FREQ to find allocno which can use only one | |
970 | hard register and makes other currently living allocnos conflicting | |
971 | with the hard register. */ | |
972 | static void | |
973 | process_single_reg_class_operands (bool in_p, int freq) | |
974 | { | |
6d1e1a26 | 975 | int i, regno; |
058e97ec | 976 | unsigned int px; |
11895e28 | 977 | enum reg_class cl; |
058e97ec VM |
978 | rtx operand; |
979 | ira_allocno_t operand_a, a; | |
980 | ||
981 | for (i = 0; i < recog_data.n_operands; i++) | |
982 | { | |
983 | operand = recog_data.operand[i]; | |
984 | if (in_p && recog_data.operand_type[i] != OP_IN | |
985 | && recog_data.operand_type[i] != OP_INOUT) | |
986 | continue; | |
987 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
988 | && recog_data.operand_type[i] != OP_INOUT) | |
989 | continue; | |
990 | cl = single_reg_operand_class (i); | |
991 | if (cl == NO_REGS) | |
992 | continue; | |
993 | ||
994 | operand_a = NULL; | |
995 | ||
996 | if (GET_CODE (operand) == SUBREG) | |
997 | operand = SUBREG_REG (operand); | |
b8698a0f | 998 | |
058e97ec VM |
999 | if (REG_P (operand) |
1000 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
1001 | { | |
1756cb66 | 1002 | enum reg_class aclass; |
058e97ec VM |
1003 | |
1004 | operand_a = ira_curr_regno_allocno_map[regno]; | |
1756cb66 | 1005 | aclass = ALLOCNO_CLASS (operand_a); |
c9d74da6 | 1006 | if (ira_class_subset_p[cl][aclass]) |
058e97ec | 1007 | { |
6d1e1a26 RS |
1008 | /* View the desired allocation of OPERAND as: |
1009 | ||
1010 | (REG:YMODE YREGNO), | |
1011 | ||
1012 | a simplification of: | |
1013 | ||
1014 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
ef4bddc2 | 1015 | machine_mode ymode, xmode; |
6d1e1a26 | 1016 | int xregno, yregno; |
91914e56 | 1017 | poly_int64 offset; |
6d1e1a26 RS |
1018 | |
1019 | xmode = recog_data.operand_mode[i]; | |
c9d74da6 RS |
1020 | xregno = ira_class_singleton[cl][xmode]; |
1021 | gcc_assert (xregno >= 0); | |
6d1e1a26 RS |
1022 | ymode = ALLOCNO_MODE (operand_a); |
1023 | offset = subreg_lowpart_offset (ymode, xmode); | |
1024 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
1025 | if (yregno >= 0 | |
1756cb66 | 1026 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
6d1e1a26 RS |
1027 | { |
1028 | int cost; | |
1029 | ||
1030 | ira_allocate_and_set_costs | |
1031 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
1756cb66 VM |
1032 | aclass, 0); |
1033 | ira_init_register_move_cost_if_necessary (xmode); | |
1034 | cost = freq * (in_p | |
1035 | ? ira_register_move_cost[xmode][aclass][cl] | |
1036 | : ira_register_move_cost[xmode][cl][aclass]); | |
6d1e1a26 | 1037 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
1756cb66 | 1038 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
6d1e1a26 | 1039 | } |
058e97ec VM |
1040 | } |
1041 | } | |
1042 | ||
ac0ab4f7 | 1043 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
058e97ec | 1044 | { |
ac0ab4f7 BS |
1045 | ira_object_t obj = ira_object_id_map[px]; |
1046 | a = OBJECT_ALLOCNO (obj); | |
058e97ec VM |
1047 | if (a != operand_a) |
1048 | { | |
1049 | /* We could increase costs of A instead of making it | |
1050 | conflicting with the hard register. But it works worse | |
1051 | because it will be spilled in reload in anyway. */ | |
44942965 RS |
1052 | OBJECT_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl]; |
1053 | OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl]; | |
058e97ec VM |
1054 | } |
1055 | } | |
1056 | } | |
1057 | } | |
1058 | ||
e384e6b5 BS |
1059 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
1060 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
1061 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
1062 | static rtx | |
070a1983 | 1063 | find_call_crossed_cheap_reg (rtx_insn *insn) |
e384e6b5 BS |
1064 | { |
1065 | rtx cheap_reg = NULL_RTX; | |
1066 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
1067 | ||
1068 | while (exp != NULL) | |
1069 | { | |
1070 | rtx x = XEXP (exp, 0); | |
1071 | if (GET_CODE (x) == SET) | |
1072 | { | |
1073 | exp = x; | |
1074 | break; | |
1075 | } | |
1076 | exp = XEXP (exp, 1); | |
1077 | } | |
1078 | if (exp != NULL) | |
1079 | { | |
1080 | basic_block bb = BLOCK_FOR_INSN (insn); | |
1081 | rtx reg = SET_SRC (exp); | |
c74ef30d | 1082 | rtx_insn *prev = PREV_INSN (insn); |
e384e6b5 BS |
1083 | while (prev && !(INSN_P (prev) |
1084 | && BLOCK_FOR_INSN (prev) != bb)) | |
1085 | { | |
1086 | if (NONDEBUG_INSN_P (prev)) | |
1087 | { | |
1088 | rtx set = single_set (prev); | |
1089 | ||
1090 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
1091 | { | |
1092 | rtx src = SET_SRC (set); | |
1093 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
1094 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1095 | break; | |
1096 | if (!modified_between_p (src, prev, insn)) | |
1097 | cheap_reg = src; | |
1098 | break; | |
1099 | } | |
1100 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1101 | { | |
1102 | rtx dest = SET_DEST (set); | |
1103 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1104 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1105 | break; | |
1106 | if (!modified_between_p (dest, prev, insn)) | |
1107 | cheap_reg = dest; | |
1108 | break; | |
1109 | } | |
1110 | ||
55dcc361 | 1111 | if (reg_set_p (reg, prev)) |
e384e6b5 BS |
1112 | break; |
1113 | } | |
1114 | prev = PREV_INSN (prev); | |
1115 | } | |
1116 | } | |
1117 | return cheap_reg; | |
1118 | } | |
1119 | ||
a141f2d8 PB |
1120 | /* Determine whether INSN is a register to register copy of the type where |
1121 | we do not need to make the source and destiniation registers conflict. | |
1122 | If this is a copy instruction, then return the source reg. Otherwise, | |
1123 | return NULL_RTX. */ | |
1124 | rtx | |
1125 | non_conflicting_reg_copy_p (rtx_insn *insn) | |
1126 | { | |
d8d3cc09 PB |
1127 | /* Reload has issues with overlapping pseudos being assigned to the |
1128 | same hard register, so don't allow it. See PR87600 for details. */ | |
1129 | if (!targetm.lra_p ()) | |
1130 | return NULL_RTX; | |
1131 | ||
a141f2d8 PB |
1132 | rtx set = single_set (insn); |
1133 | ||
1134 | /* Disallow anything other than a simple register to register copy | |
1135 | that has no side effects. */ | |
1136 | if (set == NULL_RTX | |
1137 | || !REG_P (SET_DEST (set)) | |
1138 | || !REG_P (SET_SRC (set)) | |
1139 | || side_effects_p (set)) | |
1140 | return NULL_RTX; | |
1141 | ||
1142 | int dst_regno = REGNO (SET_DEST (set)); | |
1143 | int src_regno = REGNO (SET_SRC (set)); | |
1144 | machine_mode mode = GET_MODE (SET_DEST (set)); | |
1145 | ||
4b0f04fb PB |
1146 | /* By definition, a register does not conflict with itself, therefore we |
1147 | do not have to handle it specially. Returning NULL_RTX now, helps | |
1148 | simplify the callers of this function. */ | |
1149 | if (dst_regno == src_regno) | |
1150 | return NULL_RTX; | |
1151 | ||
a141f2d8 PB |
1152 | /* Computing conflicts for register pairs is difficult to get right, so |
1153 | for now, disallow it. */ | |
4b0f04fb | 1154 | if ((HARD_REGISTER_NUM_P (dst_regno) |
a141f2d8 | 1155 | && hard_regno_nregs (dst_regno, mode) != 1) |
4b0f04fb | 1156 | || (HARD_REGISTER_NUM_P (src_regno) |
a141f2d8 PB |
1157 | && hard_regno_nregs (src_regno, mode) != 1)) |
1158 | return NULL_RTX; | |
1159 | ||
1160 | return SET_SRC (set); | |
1161 | } | |
1162 | ||
5c8a1211 VM |
1163 | #ifdef EH_RETURN_DATA_REGNO |
1164 | ||
1165 | /* Add EH return hard registers as conflict hard registers to allocnos | |
1166 | living at end of BB. For most allocnos it is already done in | |
1167 | process_bb_node_lives when we processing input edges but it does | |
1168 | not work when and EH edge is edge out of the current region. This | |
1169 | function covers such out of region edges. */ | |
1170 | static void | |
1171 | process_out_of_region_eh_regs (basic_block bb) | |
1172 | { | |
1173 | edge e; | |
1174 | edge_iterator ei; | |
1175 | unsigned int i; | |
1176 | bitmap_iterator bi; | |
1177 | bool eh_p = false; | |
1178 | ||
1179 | FOR_EACH_EDGE (e, ei, bb->succs) | |
1180 | if ((e->flags & EDGE_EH) | |
1181 | && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent) | |
1182 | eh_p = true; | |
1183 | ||
1184 | if (! eh_p) | |
1185 | return; | |
1186 | ||
1187 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi) | |
1188 | { | |
1189 | ira_allocno_t a = ira_curr_regno_allocno_map[i]; | |
1190 | for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--) | |
1191 | { | |
1192 | ira_object_t obj = ALLOCNO_OBJECT (a, n); | |
1193 | for (int k = 0; ; k++) | |
1194 | { | |
1195 | unsigned int regno = EH_RETURN_DATA_REGNO (k); | |
1196 | if (regno == INVALID_REGNUM) | |
1197 | break; | |
1198 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); | |
1199 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
1200 | } | |
1201 | } | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | #endif | |
1206 | ||
058e97ec VM |
1207 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1208 | update allocno live ranges, allocno hard register conflicts, | |
1209 | intersected calls, and register pressure info for allocnos for the | |
1210 | basic block for and regions containing the basic block. */ | |
1211 | static void | |
1212 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1213 | { | |
acb37d29 | 1214 | int i, freq; |
058e97ec VM |
1215 | unsigned int j; |
1216 | basic_block bb; | |
070a1983 | 1217 | rtx_insn *insn; |
058e97ec | 1218 | bitmap_iterator bi; |
acb37d29 | 1219 | bitmap reg_live_out; |
058e97ec | 1220 | unsigned int px; |
3517d3a0 | 1221 | bool set_p; |
058e97ec VM |
1222 | |
1223 | bb = loop_tree_node->bb; | |
1224 | if (bb != NULL) | |
1225 | { | |
1756cb66 | 1226 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1227 | { |
1756cb66 VM |
1228 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1229 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
058e97ec VM |
1230 | } |
1231 | curr_bb_node = loop_tree_node; | |
bf744527 | 1232 | reg_live_out = df_get_live_out (bb); |
ac0ab4f7 | 1233 | sparseset_clear (objects_live); |
acb37d29 | 1234 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
d15e5131 | 1235 | hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs); |
058e97ec VM |
1236 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1237 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1238 | { | |
1756cb66 | 1239 | enum reg_class aclass, pclass, cl; |
b8698a0f | 1240 | |
1756cb66 VM |
1241 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1242 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 1243 | for (j = 0; |
1756cb66 | 1244 | (cl = ira_reg_class_super_classes[pclass][j]) |
7db7ed3c VM |
1245 | != LIM_REG_CLASSES; |
1246 | j++) | |
1247 | { | |
1756cb66 VM |
1248 | if (! ira_reg_pressure_class_p[cl]) |
1249 | continue; | |
7db7ed3c VM |
1250 | curr_reg_pressure[cl]++; |
1251 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1252 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1253 | ira_assert (curr_reg_pressure[cl] | |
f508f827 | 1254 | <= ira_class_hard_regs_num[cl]); |
7db7ed3c | 1255 | } |
058e97ec | 1256 | } |
acb37d29 | 1257 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
3c55880a | 1258 | mark_pseudo_regno_live (j); |
b8698a0f | 1259 | |
5c8a1211 VM |
1260 | #ifdef EH_RETURN_DATA_REGNO |
1261 | process_out_of_region_eh_regs (bb); | |
1262 | #endif | |
1263 | ||
acb37d29 RS |
1264 | freq = REG_FREQ_FROM_BB (bb); |
1265 | if (freq == 0) | |
1266 | freq = 1; | |
1267 | ||
cb1ca6ac VM |
1268 | /* Invalidate all allocno_saved_at_call entries. */ |
1269 | last_call_num++; | |
1270 | ||
058e97ec | 1271 | /* Scan the code of this basic block, noting which allocnos and |
acb37d29 RS |
1272 | hard regs are born or die. |
1273 | ||
1274 | Note that this loop treats uninitialized values as live until | |
1275 | the beginning of the block. For example, if an instruction | |
1276 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1277 | set, FOO will remain live until the beginning of the block. | |
1278 | Likewise if FOO is not set at all. This is unnecessarily | |
1279 | pessimistic, but it probably doesn't matter much in practice. */ | |
1280 | FOR_BB_INSNS_REVERSE (bb, insn) | |
058e97ec | 1281 | { |
21c6c24f | 1282 | ira_allocno_t a; |
bfac633a | 1283 | df_ref def, use; |
61001a35 | 1284 | bool call_p; |
b8698a0f | 1285 | |
b5b8b0ac | 1286 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec | 1287 | continue; |
b8698a0f | 1288 | |
058e97ec VM |
1289 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1290 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
2608d841 | 1291 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
058e97ec VM |
1292 | curr_point); |
1293 | ||
21c6c24f | 1294 | call_p = CALL_P (insn); |
a141f2d8 | 1295 | ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn); |
21c6c24f | 1296 | |
acb37d29 RS |
1297 | /* Mark each defined value as live. We need to do this for |
1298 | unused values because they still conflict with quantities | |
1299 | that are live at the time of the definition. | |
1300 | ||
1301 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1302 | references represent the effect of the called function | |
1303 | on a call-clobbered register. Marking the register as | |
1304 | live would stop us from allocating it to a call-crossing | |
1305 | allocno. */ | |
bfac633a RS |
1306 | FOR_EACH_INSN_DEF (def, insn) |
1307 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1308 | mark_ref_live (def); | |
acb37d29 RS |
1309 | |
1310 | /* If INSN has multiple outputs, then any value used in one | |
1311 | of the outputs conflicts with the other outputs. Model this | |
1312 | by making the used value live during the output phase. | |
1313 | ||
1314 | It is unsafe to use !single_set here since it will ignore | |
1315 | an unused output. Just because an output is unused does | |
1316 | not mean the compiler can assume the side effect will not | |
1317 | occur. Consider if ALLOCNO appears in the address of an | |
1318 | output and we reload the output. If we allocate ALLOCNO | |
1319 | to the same hard register as an unused output we could | |
1320 | set the hard register before the output reload insn. */ | |
1321 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
bfac633a | 1322 | FOR_EACH_INSN_USE (use, insn) |
acb37d29 RS |
1323 | { |
1324 | int i; | |
1325 | rtx reg; | |
1326 | ||
bfac633a | 1327 | reg = DF_REF_REG (use); |
acb37d29 RS |
1328 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
1329 | { | |
1330 | rtx set; | |
1331 | ||
1332 | set = XVECEXP (PATTERN (insn), 0, i); | |
1333 | if (GET_CODE (set) == SET | |
1334 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1335 | { | |
1336 | /* After the previous loop, this is a no-op if | |
1337 | REG is contained within SET_DEST (SET). */ | |
bfac633a | 1338 | mark_ref_live (use); |
acb37d29 RS |
1339 | break; |
1340 | } | |
1341 | } | |
1342 | } | |
b8698a0f | 1343 | |
6de20b9d | 1344 | preferred_alternatives = ira_setup_alts (insn); |
acb37d29 | 1345 | process_single_reg_class_operands (false, freq); |
b8698a0f | 1346 | |
acb37d29 | 1347 | if (call_p) |
058e97ec | 1348 | { |
e384e6b5 BS |
1349 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1350 | there, try to find a pseudo that is live across the call but | |
1351 | can be cheaply reconstructed from the return value. */ | |
1352 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1353 | if (cheap_reg != NULL_RTX) | |
1354 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1355 | ||
cb1ca6ac | 1356 | last_call_num++; |
ac0ab4f7 | 1357 | sparseset_clear (allocnos_processed); |
acb37d29 | 1358 | /* The current set of live allocnos are live across the call. */ |
ac0ab4f7 | 1359 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 1360 | { |
ac0ab4f7 | 1361 | ira_object_t obj = ira_object_id_map[i]; |
21c6c24f | 1362 | a = OBJECT_ALLOCNO (obj); |
ac0ab4f7 | 1363 | int num = ALLOCNO_NUM (a); |
6c476222 | 1364 | function_abi callee_abi = insn_callee_abi (insn); |
b8698a0f | 1365 | |
5feec5c1 VM |
1366 | /* Don't allocate allocnos that cross setjmps or any |
1367 | call, if this function receives a nonlocal | |
1368 | goto. */ | |
1369 | if (cfun->has_nonlocal_label | |
82957a73 PB |
1370 | || (!targetm.setjmp_preserves_nonvolatile_regs_p () |
1371 | && (find_reg_note (insn, REG_SETJMP, NULL_RTX) | |
1372 | != NULL_RTX))) | |
058e97ec | 1373 | { |
a49ae217 BS |
1374 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1375 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
058e97ec | 1376 | } |
cf0c2a60 VM |
1377 | if (can_throw_internal (insn)) |
1378 | { | |
44942965 | 1379 | OBJECT_CONFLICT_HARD_REGS (obj) |
6c476222 | 1380 | |= callee_abi.mode_clobbers (ALLOCNO_MODE (a)); |
44942965 | 1381 | OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |
6c476222 | 1382 | |= callee_abi.mode_clobbers (ALLOCNO_MODE (a)); |
cf0c2a60 | 1383 | } |
ac0ab4f7 BS |
1384 | |
1385 | if (sparseset_bit_p (allocnos_processed, num)) | |
1386 | continue; | |
1387 | sparseset_set_bit (allocnos_processed, num); | |
1388 | ||
1389 | if (allocno_saved_at_call[num] != last_call_num) | |
df3e3493 | 1390 | /* Here we are mimicking caller-save.c behavior |
ac0ab4f7 BS |
1391 | which does not save hard register at a call if |
1392 | it was saved on previous call in the same basic | |
1393 | block and the hard register was not mentioned | |
1394 | between the two calls. */ | |
1395 | ALLOCNO_CALL_FREQ (a) += freq; | |
1396 | /* Mark it as saved at the next call. */ | |
1397 | allocno_saved_at_call[num] = last_call_num + 1; | |
1398 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
6c476222 | 1399 | ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id (); |
44942965 | 1400 | ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a) |
6c476222 | 1401 | |= callee_abi.full_and_partial_reg_clobbers (); |
e384e6b5 BS |
1402 | if (cheap_reg != NULL_RTX |
1403 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1404 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
058e97ec VM |
1405 | } |
1406 | } | |
b8698a0f | 1407 | |
5e21e8e7 HPN |
1408 | /* See which defined values die here. Note that we include |
1409 | the call insn in the lifetimes of these values, so we don't | |
1410 | mistakenly consider, for e.g. an addressing mode with a | |
1411 | side-effect like a post-increment fetching the address, | |
1412 | that the use happens before the call, and the def to happen | |
1413 | after the call: we believe both to happen before the actual | |
1414 | call. (We don't handle return-values here.) */ | |
1415 | FOR_EACH_INSN_DEF (def, insn) | |
1416 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1417 | mark_ref_dead (def); | |
1418 | ||
22c02455 VM |
1419 | make_early_clobber_and_input_conflicts (); |
1420 | ||
acb37d29 | 1421 | curr_point++; |
21c6c24f | 1422 | |
acb37d29 | 1423 | /* Mark each used value as live. */ |
bfac633a RS |
1424 | FOR_EACH_INSN_USE (use, insn) |
1425 | mark_ref_live (use); | |
acb37d29 | 1426 | |
acb37d29 | 1427 | process_single_reg_class_operands (true, freq); |
b8698a0f | 1428 | |
22c02455 VM |
1429 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1430 | ||
3517d3a0 VM |
1431 | if (set_p) |
1432 | { | |
22c02455 | 1433 | mark_hard_reg_early_clobbers (insn, false); |
3517d3a0 | 1434 | |
22c02455 | 1435 | /* Mark each hard reg as live again. For example, a |
3517d3a0 VM |
1436 | hard register can be in clobber and in an insn |
1437 | input. */ | |
bfac633a | 1438 | FOR_EACH_INSN_USE (use, insn) |
22c02455 | 1439 | { |
bfac633a | 1440 | rtx ureg = DF_REF_REG (use); |
b8698a0f | 1441 | |
22c02455 VM |
1442 | if (GET_CODE (ureg) == SUBREG) |
1443 | ureg = SUBREG_REG (ureg); | |
1444 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1445 | continue; | |
b8698a0f | 1446 | |
bfac633a | 1447 | mark_ref_live (use); |
22c02455 | 1448 | } |
3517d3a0 | 1449 | } |
058e97ec | 1450 | |
058e97ec VM |
1451 | curr_point++; |
1452 | } | |
a141f2d8 | 1453 | ignore_reg_for_conflicts = NULL_RTX; |
acb37d29 | 1454 | |
5dbd125c EB |
1455 | if (bb_has_eh_pred (bb)) |
1456 | for (j = 0; ; ++j) | |
1457 | { | |
1458 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1459 | if (regno == INVALID_REGNUM) | |
1460 | break; | |
0df92803 | 1461 | make_hard_regno_live (regno); |
5dbd125c | 1462 | } |
5dbd125c | 1463 | |
acb37d29 | 1464 | /* Allocnos can't go in stack regs at the start of a basic block |
6c476222 RS |
1465 | that is reached by an abnormal edge. Likewise for registers |
1466 | that are at least partly call clobbered, because caller-save, | |
1467 | fixup_abnormal_edges and possibly the table driven EH machinery | |
1468 | are not quite ready to handle such allocnos live across such | |
1469 | edges. */ | |
5dbd125c | 1470 | if (bb_has_abnormal_pred (bb)) |
acb37d29 RS |
1471 | { |
1472 | #ifdef STACK_REGS | |
ac0ab4f7 | 1473 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
acb37d29 | 1474 | { |
ac0ab4f7 | 1475 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
1756cb66 | 1476 | |
ac0ab4f7 BS |
1477 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1478 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
acb37d29 RS |
1479 | } |
1480 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
0df92803 | 1481 | make_hard_regno_live (px); |
acb37d29 RS |
1482 | #endif |
1483 | /* No need to record conflicts for call clobbered regs if we | |
1484 | have nonlocal labels around, as we don't ever try to | |
1485 | allocate such regs in this case. */ | |
f1544089 MP |
1486 | if (!cfun->has_nonlocal_label |
1487 | && has_abnormal_call_or_eh_pred_edge_p (bb)) | |
acb37d29 | 1488 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
6c476222 | 1489 | if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px) |
1d6cc2e4 VM |
1490 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
1491 | /* We should create a conflict of PIC pseudo with | |
1492 | PIC hard reg as PIC hard reg can have a wrong | |
1493 | value after jump described by the abnormal edge. | |
67914693 | 1494 | In this case we cannot allocate PIC hard reg to |
1d6cc2e4 VM |
1495 | PIC pseudo as PIC pseudo will also have a wrong |
1496 | value. This code is not critical as LRA can fix | |
1497 | it but it is better to have the right allocation | |
1498 | earlier. */ | |
1499 | || (px == REAL_PIC_OFFSET_TABLE_REGNUM | |
1500 | && pic_offset_table_rtx != NULL_RTX | |
1501 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
1502 | #endif | |
1503 | ) | |
0df92803 | 1504 | make_hard_regno_live (px); |
acb37d29 RS |
1505 | } |
1506 | ||
ac0ab4f7 BS |
1507 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1508 | make_object_dead (ira_object_id_map[i]); | |
058e97ec VM |
1509 | |
1510 | curr_point++; | |
1511 | ||
1512 | } | |
2b9c63a2 | 1513 | /* Propagate register pressure to upper loop tree nodes. */ |
058e97ec | 1514 | if (loop_tree_node != ira_loop_tree_root) |
1756cb66 | 1515 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1516 | { |
1756cb66 | 1517 | enum reg_class pclass; |
058e97ec | 1518 | |
1756cb66 VM |
1519 | pclass = ira_pressure_classes[i]; |
1520 | if (loop_tree_node->reg_pressure[pclass] | |
1521 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1522 | loop_tree_node->parent->reg_pressure[pclass] | |
1523 | = loop_tree_node->reg_pressure[pclass]; | |
058e97ec VM |
1524 | } |
1525 | } | |
1526 | ||
1527 | /* Create and set up IRA_START_POINT_RANGES and | |
1528 | IRA_FINISH_POINT_RANGES. */ | |
1529 | static void | |
1530 | create_start_finish_chains (void) | |
1531 | { | |
ac0ab4f7 BS |
1532 | ira_object_t obj; |
1533 | ira_object_iterator oi; | |
b14151b5 | 1534 | live_range_t r; |
058e97ec VM |
1535 | |
1536 | ira_start_point_ranges | |
ac0ab4f7 BS |
1537 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1538 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
058e97ec | 1539 | ira_finish_point_ranges |
ac0ab4f7 BS |
1540 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1541 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1542 | FOR_EACH_OBJECT (obj, oi) | |
1543 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1544 | { | |
1545 | r->start_next = ira_start_point_ranges[r->start]; | |
1546 | ira_start_point_ranges[r->start] = r; | |
1547 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
058e97ec | 1548 | ira_finish_point_ranges[r->finish] = r; |
ac0ab4f7 | 1549 | } |
058e97ec VM |
1550 | } |
1551 | ||
1552 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1553 | new live ranges and program points were added as a result if new | |
1554 | insn generation. */ | |
1555 | void | |
1556 | ira_rebuild_start_finish_chains (void) | |
1557 | { | |
1558 | ira_free (ira_finish_point_ranges); | |
1559 | ira_free (ira_start_point_ranges); | |
1560 | create_start_finish_chains (); | |
1561 | } | |
1562 | ||
b15a7ae6 VM |
1563 | /* Compress allocno live ranges by removing program points where |
1564 | nothing happens. */ | |
1565 | static void | |
1566 | remove_some_program_points_and_update_live_ranges (void) | |
1567 | { | |
1568 | unsigned i; | |
1569 | int n; | |
1570 | int *map; | |
9140d27b BS |
1571 | ira_object_t obj; |
1572 | ira_object_iterator oi; | |
e6a7da82 | 1573 | live_range_t r, prev_r, next_r; |
9995f209 VM |
1574 | sbitmap_iterator sbi; |
1575 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1576 | ||
7ba9e72d TS |
1577 | auto_sbitmap born (ira_max_point); |
1578 | auto_sbitmap dead (ira_max_point); | |
f61e445a LC |
1579 | bitmap_clear (born); |
1580 | bitmap_clear (dead); | |
9140d27b BS |
1581 | FOR_EACH_OBJECT (obj, oi) |
1582 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1583 | { | |
1584 | ira_assert (r->start <= r->finish); | |
d7c028c0 LC |
1585 | bitmap_set_bit (born, r->start); |
1586 | bitmap_set_bit (dead, r->finish); | |
9140d27b BS |
1587 | } |
1588 | ||
7ba9e72d | 1589 | auto_sbitmap born_or_dead (ira_max_point); |
f61e445a | 1590 | bitmap_ior (born_or_dead, born, dead); |
b15a7ae6 | 1591 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
9995f209 VM |
1592 | n = -1; |
1593 | prev_born_p = prev_dead_p = false; | |
d4ac4ce2 | 1594 | EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi) |
b15a7ae6 | 1595 | { |
d7c028c0 LC |
1596 | born_p = bitmap_bit_p (born, i); |
1597 | dead_p = bitmap_bit_p (dead, i); | |
9995f209 VM |
1598 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
1599 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1600 | map[i] = n; | |
1601 | else | |
1602 | map[i] = ++n; | |
1603 | prev_born_p = born_p; | |
1604 | prev_dead_p = dead_p; | |
b15a7ae6 | 1605 | } |
7ba9e72d | 1606 | |
9995f209 | 1607 | n++; |
b15a7ae6 VM |
1608 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1609 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1610 | ira_max_point, n, 100 * n / ira_max_point); | |
1611 | ira_max_point = n; | |
9140d27b BS |
1612 | |
1613 | FOR_EACH_OBJECT (obj, oi) | |
e6a7da82 | 1614 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9140d27b | 1615 | { |
e6a7da82 | 1616 | next_r = r->next; |
9140d27b BS |
1617 | r->start = map[r->start]; |
1618 | r->finish = map[r->finish]; | |
e6a7da82 SB |
1619 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1620 | { | |
1621 | prev_r = r; | |
1622 | continue; | |
1623 | } | |
1624 | prev_r->start = r->start; | |
1625 | prev_r->next = next_r; | |
1626 | ira_finish_live_range (r); | |
9140d27b | 1627 | } |
ac0ab4f7 | 1628 | |
b15a7ae6 VM |
1629 | ira_free (map); |
1630 | } | |
1631 | ||
058e97ec VM |
1632 | /* Print live ranges R to file F. */ |
1633 | void | |
b14151b5 | 1634 | ira_print_live_range_list (FILE *f, live_range_t r) |
058e97ec VM |
1635 | { |
1636 | for (; r != NULL; r = r->next) | |
1637 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1638 | fprintf (f, "\n"); | |
1639 | } | |
1640 | ||
7b3b6ae4 LC |
1641 | DEBUG_FUNCTION void |
1642 | debug (live_range &ref) | |
1643 | { | |
1644 | ira_print_live_range_list (stderr, &ref); | |
1645 | } | |
1646 | ||
1647 | DEBUG_FUNCTION void | |
1648 | debug (live_range *ptr) | |
1649 | { | |
1650 | if (ptr) | |
1651 | debug (*ptr); | |
1652 | else | |
1653 | fprintf (stderr, "<nil>\n"); | |
1654 | } | |
1655 | ||
058e97ec VM |
1656 | /* Print live ranges R to stderr. */ |
1657 | void | |
b14151b5 | 1658 | ira_debug_live_range_list (live_range_t r) |
058e97ec VM |
1659 | { |
1660 | ira_print_live_range_list (stderr, r); | |
1661 | } | |
1662 | ||
ac0ab4f7 BS |
1663 | /* Print live ranges of object OBJ to file F. */ |
1664 | static void | |
1665 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1666 | { | |
1667 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1668 | } | |
1669 | ||
058e97ec VM |
1670 | /* Print live ranges of allocno A to file F. */ |
1671 | static void | |
1672 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1673 | { | |
ac0ab4f7 BS |
1674 | int n = ALLOCNO_NUM_OBJECTS (a); |
1675 | int i; | |
1756cb66 | 1676 | |
ac0ab4f7 BS |
1677 | for (i = 0; i < n; i++) |
1678 | { | |
1679 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1680 | if (n > 1) | |
1681 | fprintf (f, " [%d]", i); | |
1682 | fprintf (f, "):"); | |
1683 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1684 | } | |
058e97ec VM |
1685 | } |
1686 | ||
1687 | /* Print live ranges of allocno A to stderr. */ | |
1688 | void | |
1689 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1690 | { | |
1691 | print_allocno_live_ranges (stderr, a); | |
1692 | } | |
1693 | ||
1694 | /* Print live ranges of all allocnos to file F. */ | |
1695 | static void | |
1696 | print_live_ranges (FILE *f) | |
1697 | { | |
1698 | ira_allocno_t a; | |
1699 | ira_allocno_iterator ai; | |
1700 | ||
1701 | FOR_EACH_ALLOCNO (a, ai) | |
1702 | print_allocno_live_ranges (f, a); | |
1703 | } | |
1704 | ||
1705 | /* Print live ranges of all allocnos to stderr. */ | |
1706 | void | |
1707 | ira_debug_live_ranges (void) | |
1708 | { | |
1709 | print_live_ranges (stderr); | |
1710 | } | |
1711 | ||
1712 | /* The main entry function creates live ranges, set up | |
ac0ab4f7 | 1713 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
058e97ec VM |
1714 | calculate register pressure info. */ |
1715 | void | |
1716 | ira_create_allocno_live_ranges (void) | |
1717 | { | |
ac0ab4f7 BS |
1718 | objects_live = sparseset_alloc (ira_objects_num); |
1719 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
058e97ec | 1720 | curr_point = 0; |
cb1ca6ac VM |
1721 | last_call_num = 0; |
1722 | allocno_saved_at_call | |
1723 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1724 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
058e97ec VM |
1725 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1726 | process_bb_node_lives); | |
1727 | ira_max_point = curr_point; | |
1728 | create_start_finish_chains (); | |
1729 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1730 | print_live_ranges (ira_dump_file); | |
1731 | /* Clean up. */ | |
cb1ca6ac | 1732 | ira_free (allocno_saved_at_call); |
ac0ab4f7 BS |
1733 | sparseset_free (objects_live); |
1734 | sparseset_free (allocnos_processed); | |
058e97ec VM |
1735 | } |
1736 | ||
b15a7ae6 VM |
1737 | /* Compress allocno live ranges. */ |
1738 | void | |
1739 | ira_compress_allocno_live_ranges (void) | |
1740 | { | |
1741 | remove_some_program_points_and_update_live_ranges (); | |
1742 | ira_rebuild_start_finish_chains (); | |
1743 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1744 | { | |
1745 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1746 | print_live_ranges (ira_dump_file); | |
1747 | } | |
1748 | } | |
1749 | ||
058e97ec VM |
1750 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1751 | void | |
1752 | ira_finish_allocno_live_ranges (void) | |
1753 | { | |
1754 | ira_free (ira_finish_point_ranges); | |
1755 | ira_free (ira_start_point_ranges); | |
1756 | } |