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47dd2e78 | 1 | /* IRA processing allocno lives to build allocno live ranges. |
3aea1f79 | 2 | Copyright (C) 2006-2014 Free Software Foundation, Inc. |
47dd2e78 | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
25 | #include "regs.h" | |
26 | #include "rtl.h" | |
27 | #include "tm_p.h" | |
28 | #include "target.h" | |
29 | #include "flags.h" | |
cab55469 | 30 | #include "except.h" |
47dd2e78 | 31 | #include "hard-reg-set.h" |
32 | #include "basic-block.h" | |
33 | #include "insn-config.h" | |
34 | #include "recog.h" | |
0b205f4c | 35 | #include "diagnostic-core.h" |
47dd2e78 | 36 | #include "params.h" |
37 | #include "df.h" | |
82cc92bf | 38 | #include "sbitmap.h" |
47dd2e78 | 39 | #include "sparseset.h" |
40 | #include "ira-int.h" | |
41 | ||
42 | /* The code in this file is similar to one in global but the code | |
43 | works on the allocno basis and creates live ranges instead of | |
44 | pseudo-register conflicts. */ | |
45 | ||
46 | /* Program points are enumerated by numbers from range | |
47 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
48 | points than insns. Program points are places in the program where | |
49 | liveness info can be changed. In most general case (there are more | |
50 | complicated cases too) some program points correspond to places | |
51 | where input operand dies and other ones correspond to places where | |
52 | output operands are born. */ | |
53 | int ira_max_point; | |
54 | ||
55 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
56 | live ranges with given start/finish point. */ | |
fbff82f4 | 57 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
47dd2e78 | 58 | |
59 | /* Number of the current program point. */ | |
60 | static int curr_point; | |
61 | ||
62 | /* Point where register pressure excess started or -1 if there is no | |
63 | register pressure excess. Excess pressure for a register class at | |
64 | some point means that there are more allocnos of given register | |
65 | class living at the point than number of hard-registers of the | |
66d9a7b9 | 66 | class available for the allocation. It is defined only for |
67 | pressure classes. */ | |
47dd2e78 | 68 | static int high_pressure_start_point[N_REG_CLASSES]; |
69 | ||
be18556f | 70 | /* Objects live at current point in the scan. */ |
71 | static sparseset objects_live; | |
72 | ||
73 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
74 | multiple times. */ | |
75 | static sparseset allocnos_processed; | |
47dd2e78 | 76 | |
77 | /* Set of hard regs (except eliminable ones) currently live. */ | |
78 | static HARD_REG_SET hard_regs_live; | |
79 | ||
80 | /* The loop tree node corresponding to the current basic block. */ | |
81 | static ira_loop_tree_node_t curr_bb_node; | |
82 | ||
df07a54c | 83 | /* The number of the last processed call. */ |
84 | static int last_call_num; | |
85 | /* The number of last call at which given allocno was saved. */ | |
86 | static int *allocno_saved_at_call; | |
87 | ||
be18556f | 88 | /* Record the birth of hard register REGNO, updating hard_regs_live and |
89 | hard reg conflict information for living allocnos. */ | |
47dd2e78 | 90 | static void |
b4f5e198 | 91 | make_hard_regno_born (int regno) |
47dd2e78 | 92 | { |
93 | unsigned int i; | |
47dd2e78 | 94 | |
b4f5e198 | 95 | SET_HARD_REG_BIT (hard_regs_live, regno); |
be18556f | 96 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
47dd2e78 | 97 | { |
be18556f | 98 | ira_object_t obj = ira_object_id_map[i]; |
66d9a7b9 | 99 | |
ae9587ed | 100 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
101 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
47dd2e78 | 102 | } |
b4f5e198 | 103 | } |
104 | ||
105 | /* Process the death of hard register REGNO. This updates | |
106 | hard_regs_live. */ | |
107 | static void | |
108 | make_hard_regno_dead (int regno) | |
109 | { | |
110 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); | |
111 | } | |
112 | ||
be18556f | 113 | /* Record the birth of object OBJ. Set a bit for it in objects_live, |
114 | start a new live range for it if necessary and update hard register | |
115 | conflicts. */ | |
b4f5e198 | 116 | static void |
be18556f | 117 | make_object_born (ira_object_t obj) |
b4f5e198 | 118 | { |
be18556f | 119 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
b4f5e198 | 120 | |
be18556f | 121 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
ae9587ed | 122 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
123 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); | |
b4f5e198 | 124 | |
be18556f | 125 | if (lr == NULL |
126 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
127 | ira_add_live_range_to_object (obj, curr_point, -1); | |
47dd2e78 | 128 | } |
129 | ||
be18556f | 130 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
131 | associated with object OBJ. */ | |
47dd2e78 | 132 | static void |
be18556f | 133 | update_allocno_pressure_excess_length (ira_object_t obj) |
47dd2e78 | 134 | { |
be18556f | 135 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
14792f4e | 136 | int start, i; |
66d9a7b9 | 137 | enum reg_class aclass, pclass, cl; |
fbff82f4 | 138 | live_range_t p; |
47dd2e78 | 139 | |
66d9a7b9 | 140 | aclass = ALLOCNO_CLASS (a); |
141 | pclass = ira_pressure_class_translate[aclass]; | |
14792f4e | 142 | for (i = 0; |
66d9a7b9 | 143 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 144 | i++) |
145 | { | |
66d9a7b9 | 146 | if (! ira_reg_pressure_class_p[cl]) |
147 | continue; | |
14792f4e | 148 | if (high_pressure_start_point[cl] < 0) |
149 | continue; | |
9d53e372 | 150 | p = OBJECT_LIVE_RANGES (obj); |
14792f4e | 151 | ira_assert (p != NULL); |
152 | start = (high_pressure_start_point[cl] > p->start | |
153 | ? high_pressure_start_point[cl] : p->start); | |
154 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
155 | } | |
47dd2e78 | 156 | } |
157 | ||
be18556f | 158 | /* Process the death of object OBJ, which is associated with allocno |
159 | A. This finishes the current live range for it. */ | |
47dd2e78 | 160 | static void |
be18556f | 161 | make_object_dead (ira_object_t obj) |
47dd2e78 | 162 | { |
be18556f | 163 | live_range_t lr; |
47dd2e78 | 164 | |
be18556f | 165 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
166 | lr = OBJECT_LIVE_RANGES (obj); | |
167 | ira_assert (lr != NULL); | |
168 | lr->finish = curr_point; | |
169 | update_allocno_pressure_excess_length (obj); | |
47dd2e78 | 170 | } |
171 | ||
66d9a7b9 | 172 | /* The current register pressures for each pressure class for the current |
47dd2e78 | 173 | basic block. */ |
174 | static int curr_reg_pressure[N_REG_CLASSES]; | |
175 | ||
66d9a7b9 | 176 | /* Record that register pressure for PCLASS increased by N registers. |
177 | Update the current register pressure, maximal register pressure for | |
178 | the current BB and the start point of the register pressure | |
179 | excess. */ | |
47dd2e78 | 180 | static void |
66d9a7b9 | 181 | inc_register_pressure (enum reg_class pclass, int n) |
47dd2e78 | 182 | { |
14792f4e | 183 | int i; |
b4f5e198 | 184 | enum reg_class cl; |
47dd2e78 | 185 | |
14792f4e | 186 | for (i = 0; |
66d9a7b9 | 187 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 188 | i++) |
189 | { | |
66d9a7b9 | 190 | if (! ira_reg_pressure_class_p[cl]) |
191 | continue; | |
b4f5e198 | 192 | curr_reg_pressure[cl] += n; |
14792f4e | 193 | if (high_pressure_start_point[cl] < 0 |
1072fecf | 194 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
14792f4e | 195 | high_pressure_start_point[cl] = curr_point; |
196 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
197 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
198 | } | |
47dd2e78 | 199 | } |
200 | ||
66d9a7b9 | 201 | /* Record that register pressure for PCLASS has decreased by NREGS |
202 | registers; update current register pressure, start point of the | |
203 | register pressure excess, and register pressure excess length for | |
204 | living allocnos. */ | |
b4f5e198 | 205 | |
47dd2e78 | 206 | static void |
66d9a7b9 | 207 | dec_register_pressure (enum reg_class pclass, int nregs) |
47dd2e78 | 208 | { |
14792f4e | 209 | int i; |
210 | unsigned int j; | |
b4f5e198 | 211 | enum reg_class cl; |
212 | bool set_p = false; | |
47dd2e78 | 213 | |
b4f5e198 | 214 | for (i = 0; |
66d9a7b9 | 215 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
b4f5e198 | 216 | i++) |
47dd2e78 | 217 | { |
66d9a7b9 | 218 | if (! ira_reg_pressure_class_p[cl]) |
219 | continue; | |
b4f5e198 | 220 | curr_reg_pressure[cl] -= nregs; |
221 | ira_assert (curr_reg_pressure[cl] >= 0); | |
222 | if (high_pressure_start_point[cl] >= 0 | |
1072fecf | 223 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
b4f5e198 | 224 | set_p = true; |
225 | } | |
226 | if (set_p) | |
227 | { | |
be18556f | 228 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
229 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
14792f4e | 230 | for (i = 0; |
66d9a7b9 | 231 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 232 | i++) |
66d9a7b9 | 233 | { |
234 | if (! ira_reg_pressure_class_p[cl]) | |
235 | continue; | |
236 | if (high_pressure_start_point[cl] >= 0 | |
1072fecf | 237 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
66d9a7b9 | 238 | high_pressure_start_point[cl] = -1; |
239 | } | |
47dd2e78 | 240 | } |
47dd2e78 | 241 | } |
242 | ||
c8010b80 | 243 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
244 | and occupies only one object. Return false if we have no information. */ | |
245 | static bool | |
246 | pseudo_regno_single_word_and_live_p (int regno) | |
247 | { | |
248 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
249 | ira_object_t obj; | |
250 | ||
251 | if (a == NULL) | |
252 | return false; | |
253 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
254 | return false; | |
255 | ||
256 | obj = ALLOCNO_OBJECT (a, 0); | |
257 | ||
258 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
259 | } | |
260 | ||
b4f5e198 | 261 | /* Mark the pseudo register REGNO as live. Update all information about |
262 | live ranges and register pressure. */ | |
47dd2e78 | 263 | static void |
b4f5e198 | 264 | mark_pseudo_regno_live (int regno) |
47dd2e78 | 265 | { |
b4f5e198 | 266 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
66d9a7b9 | 267 | enum reg_class pclass; |
be18556f | 268 | int i, n, nregs; |
47dd2e78 | 269 | |
b4f5e198 | 270 | if (a == NULL) |
271 | return; | |
47dd2e78 | 272 | |
b4f5e198 | 273 | /* Invalidate because it is referenced. */ |
274 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
47dd2e78 | 275 | |
be18556f | 276 | n = ALLOCNO_NUM_OBJECTS (a); |
66d9a7b9 | 277 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
278 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
be18556f | 279 | if (n > 1) |
280 | { | |
281 | /* We track every subobject separately. */ | |
282 | gcc_assert (nregs == n); | |
283 | nregs = 1; | |
284 | } | |
285 | ||
286 | for (i = 0; i < n; i++) | |
287 | { | |
288 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
66d9a7b9 | 289 | |
be18556f | 290 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
291 | continue; | |
292 | ||
66d9a7b9 | 293 | inc_register_pressure (pclass, nregs); |
be18556f | 294 | make_object_born (obj); |
295 | } | |
296 | } | |
297 | ||
298 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
299 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
300 | indicates the low part. */ | |
301 | static void | |
302 | mark_pseudo_regno_subword_live (int regno, int subword) | |
303 | { | |
304 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
342f23d2 | 305 | int n; |
66d9a7b9 | 306 | enum reg_class pclass; |
be18556f | 307 | ira_object_t obj; |
308 | ||
309 | if (a == NULL) | |
b4f5e198 | 310 | return; |
311 | ||
be18556f | 312 | /* Invalidate because it is referenced. */ |
313 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
314 | ||
315 | n = ALLOCNO_NUM_OBJECTS (a); | |
316 | if (n == 1) | |
317 | { | |
318 | mark_pseudo_regno_live (regno); | |
319 | return; | |
320 | } | |
321 | ||
66d9a7b9 | 322 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
342f23d2 | 323 | gcc_assert |
324 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
be18556f | 325 | obj = ALLOCNO_OBJECT (a, subword); |
326 | ||
327 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
328 | return; | |
329 | ||
342f23d2 | 330 | inc_register_pressure (pclass, 1); |
be18556f | 331 | make_object_born (obj); |
b4f5e198 | 332 | } |
333 | ||
be18556f | 334 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
335 | this register, record how many consecutive hardware registers it | |
336 | actually needs. */ | |
b4f5e198 | 337 | static void |
338 | mark_hard_reg_live (rtx reg) | |
339 | { | |
340 | int regno = REGNO (reg); | |
341 | ||
342 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
47dd2e78 | 343 | { |
344 | int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
66d9a7b9 | 345 | enum reg_class aclass, pclass; |
47dd2e78 | 346 | |
347 | while (regno < last) | |
348 | { | |
349 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
350 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
351 | { | |
66d9a7b9 | 352 | aclass = ira_hard_regno_allocno_class[regno]; |
353 | pclass = ira_pressure_class_translate[aclass]; | |
354 | inc_register_pressure (pclass, 1); | |
b4f5e198 | 355 | make_hard_regno_born (regno); |
47dd2e78 | 356 | } |
357 | regno++; | |
358 | } | |
359 | } | |
360 | } | |
361 | ||
044621b2 | 362 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
363 | register number; ORIG_REG is the access in the insn, which may be a | |
364 | subreg. */ | |
365 | static void | |
366 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
367 | { | |
368 | if (df_read_modify_subreg_p (orig_reg)) | |
369 | { | |
370 | mark_pseudo_regno_subword_live (regno, | |
371 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
372 | } | |
373 | else | |
374 | mark_pseudo_regno_live (regno); | |
375 | } | |
376 | ||
793e7497 | 377 | /* Mark the register referenced by use or def REF as live. */ |
378 | static void | |
ed6e85ae | 379 | mark_ref_live (df_ref ref) |
47dd2e78 | 380 | { |
be18556f | 381 | rtx reg = DF_REF_REG (ref); |
382 | rtx orig_reg = reg; | |
793e7497 | 383 | |
793e7497 | 384 | if (GET_CODE (reg) == SUBREG) |
385 | reg = SUBREG_REG (reg); | |
be18556f | 386 | |
b4f5e198 | 387 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
044621b2 | 388 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
b4f5e198 | 389 | else |
390 | mark_hard_reg_live (reg); | |
47dd2e78 | 391 | } |
392 | ||
b4f5e198 | 393 | /* Mark the pseudo register REGNO as dead. Update all information about |
394 | live ranges and register pressure. */ | |
47dd2e78 | 395 | static void |
b4f5e198 | 396 | mark_pseudo_regno_dead (int regno) |
47dd2e78 | 397 | { |
b4f5e198 | 398 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
be18556f | 399 | int n, i, nregs; |
b4f5e198 | 400 | enum reg_class cl; |
47dd2e78 | 401 | |
b4f5e198 | 402 | if (a == NULL) |
403 | return; | |
47dd2e78 | 404 | |
b4f5e198 | 405 | /* Invalidate because it is referenced. */ |
406 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
47dd2e78 | 407 | |
be18556f | 408 | n = ALLOCNO_NUM_OBJECTS (a); |
66d9a7b9 | 409 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
410 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
be18556f | 411 | if (n > 1) |
412 | { | |
413 | /* We track every subobject separately. */ | |
414 | gcc_assert (nregs == n); | |
415 | nregs = 1; | |
416 | } | |
417 | for (i = 0; i < n; i++) | |
418 | { | |
419 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
420 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
421 | continue; | |
422 | ||
423 | dec_register_pressure (cl, nregs); | |
424 | make_object_dead (obj); | |
425 | } | |
426 | } | |
427 | ||
428 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
429 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
430 | static void | |
431 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
432 | { | |
433 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
342f23d2 | 434 | int n; |
be18556f | 435 | enum reg_class cl; |
436 | ira_object_t obj; | |
437 | ||
438 | if (a == NULL) | |
439 | return; | |
440 | ||
441 | /* Invalidate because it is referenced. */ | |
442 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
443 | ||
444 | n = ALLOCNO_NUM_OBJECTS (a); | |
445 | if (n == 1) | |
446 | /* The allocno as a whole doesn't die in this case. */ | |
b4f5e198 | 447 | return; |
448 | ||
66d9a7b9 | 449 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
342f23d2 | 450 | gcc_assert |
451 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
be18556f | 452 | |
453 | obj = ALLOCNO_OBJECT (a, subword); | |
454 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
455 | return; | |
b4f5e198 | 456 | |
be18556f | 457 | dec_register_pressure (cl, 1); |
458 | make_object_dead (obj); | |
b4f5e198 | 459 | } |
460 | ||
be18556f | 461 | /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
462 | register. */ | |
b4f5e198 | 463 | static void |
464 | mark_hard_reg_dead (rtx reg) | |
465 | { | |
466 | int regno = REGNO (reg); | |
467 | ||
468 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
47dd2e78 | 469 | { |
470 | int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
66d9a7b9 | 471 | enum reg_class aclass, pclass; |
47dd2e78 | 472 | |
473 | while (regno < last) | |
474 | { | |
475 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
476 | { | |
66d9a7b9 | 477 | aclass = ira_hard_regno_allocno_class[regno]; |
478 | pclass = ira_pressure_class_translate[aclass]; | |
479 | dec_register_pressure (pclass, 1); | |
b4f5e198 | 480 | make_hard_regno_dead (regno); |
47dd2e78 | 481 | } |
482 | regno++; | |
483 | } | |
484 | } | |
485 | } | |
486 | ||
044621b2 | 487 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
488 | register number; ORIG_REG is the access in the insn, which may be a | |
489 | subreg. */ | |
490 | static void | |
491 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
492 | { | |
493 | if (df_read_modify_subreg_p (orig_reg)) | |
494 | { | |
495 | mark_pseudo_regno_subword_dead (regno, | |
496 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
497 | } | |
498 | else | |
499 | mark_pseudo_regno_dead (regno); | |
500 | } | |
501 | ||
793e7497 | 502 | /* Mark the register referenced by definition DEF as dead, if the |
503 | definition is a total one. */ | |
504 | static void | |
ed6e85ae | 505 | mark_ref_dead (df_ref def) |
793e7497 | 506 | { |
be18556f | 507 | rtx reg = DF_REF_REG (def); |
508 | rtx orig_reg = reg; | |
793e7497 | 509 | |
be18556f | 510 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
793e7497 | 511 | return; |
512 | ||
793e7497 | 513 | if (GET_CODE (reg) == SUBREG) |
514 | reg = SUBREG_REG (reg); | |
be18556f | 515 | |
516 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
517 | && (GET_CODE (orig_reg) != SUBREG | |
518 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
519 | || !df_read_modify_subreg_p (orig_reg))) | |
520 | return; | |
521 | ||
b4f5e198 | 522 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
044621b2 | 523 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
b4f5e198 | 524 | else |
525 | mark_hard_reg_dead (reg); | |
793e7497 | 526 | } |
527 | ||
044621b2 | 528 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
529 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
9d75589a | 530 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
044621b2 | 531 | Advance the current program point before making the conflict if |
532 | ADVANCE_P. Return TRUE if we will need to advance the current | |
533 | program point. */ | |
793e7497 | 534 | static bool |
044621b2 | 535 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
536 | bool advance_p) | |
793e7497 | 537 | { |
044621b2 | 538 | rtx orig_reg = reg; |
7173d4d0 | 539 | ira_allocno_t a; |
793e7497 | 540 | |
7173d4d0 | 541 | if (GET_CODE (reg) == SUBREG) |
542 | reg = SUBREG_REG (reg); | |
48e1416a | 543 | |
7173d4d0 | 544 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
545 | return advance_p; | |
48e1416a | 546 | |
7173d4d0 | 547 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
66d9a7b9 | 548 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
7173d4d0 | 549 | return advance_p; |
793e7497 | 550 | |
7173d4d0 | 551 | if (advance_p) |
552 | curr_point++; | |
793e7497 | 553 | |
044621b2 | 554 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
555 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
556 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
557 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
7173d4d0 | 558 | |
559 | return false; | |
560 | } | |
793e7497 | 561 | |
7173d4d0 | 562 | /* Check and make if necessary conflicts for pseudo DREG of class |
563 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
9d75589a | 564 | ORIG_DREG is the rtx actually accessed, it may be identical to |
044621b2 | 565 | DREG or a subreg of it. Advance the current program point before |
566 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
567 | advance the current program point. */ | |
7173d4d0 | 568 | static bool |
044621b2 | 569 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
570 | enum reg_class def_cl, int use, | |
571 | enum reg_class use_cl, bool advance_p) | |
7173d4d0 | 572 | { |
573 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
574 | return advance_p; | |
48e1416a | 575 | |
7173d4d0 | 576 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
044621b2 | 577 | use_cl, dreg, orig_dreg, advance_p); |
578 | ||
7173d4d0 | 579 | /* Reload may end up swapping commutative operands, so you |
580 | have to take both orderings into account. The | |
581 | constraints for the two operands can be completely | |
582 | different. (Indeed, if the constraints for the two | |
583 | operands are the same for all alternatives, there's no | |
584 | point marking them as commutative.) */ | |
e91a9c3f | 585 | if (use < recog_data.n_operands - 1 |
7173d4d0 | 586 | && recog_data.constraints[use][0] == '%') |
587 | advance_p | |
588 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
044621b2 | 589 | use_cl, dreg, orig_dreg, advance_p); |
7173d4d0 | 590 | if (use >= 1 |
591 | && recog_data.constraints[use - 1][0] == '%') | |
592 | advance_p | |
593 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
044621b2 | 594 | use_cl, dreg, orig_dreg, advance_p); |
7173d4d0 | 595 | return advance_p; |
596 | } | |
597 | ||
598 | /* Check and make if necessary conflicts for definition DEF of class | |
599 | DEF_CL of the current insn with input operands. Process only | |
600 | constraints of alternative ALT. */ | |
601 | static void | |
602 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
603 | { | |
604 | int use, use_match; | |
605 | ira_allocno_t a; | |
606 | enum reg_class use_cl, acl; | |
607 | bool advance_p; | |
608 | rtx dreg = recog_data.operand[def]; | |
044621b2 | 609 | rtx orig_dreg = dreg; |
48e1416a | 610 | |
7173d4d0 | 611 | if (def_cl == NO_REGS) |
612 | return; | |
48e1416a | 613 | |
7173d4d0 | 614 | if (GET_CODE (dreg) == SUBREG) |
615 | dreg = SUBREG_REG (dreg); | |
48e1416a | 616 | |
7173d4d0 | 617 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
618 | return; | |
48e1416a | 619 | |
7173d4d0 | 620 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
66d9a7b9 | 621 | acl = ALLOCNO_CLASS (a); |
7173d4d0 | 622 | if (! reg_classes_intersect_p (acl, def_cl)) |
623 | return; | |
48e1416a | 624 | |
7173d4d0 | 625 | advance_p = true; |
48e1416a | 626 | |
757fefec | 627 | int n_operands = recog_data.n_operands; |
8eaaac4d | 628 | const operand_alternative *op_alt = &recog_op_alt[alt * n_operands]; |
757fefec | 629 | for (use = 0; use < n_operands; use++) |
7173d4d0 | 630 | { |
d09294c0 | 631 | int alt1; |
632 | ||
7173d4d0 | 633 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
c2b66149 | 634 | continue; |
48e1416a | 635 | |
757fefec | 636 | if (op_alt[use].anything_ok) |
7173d4d0 | 637 | use_cl = ALL_REGS; |
793e7497 | 638 | else |
757fefec | 639 | use_cl = op_alt[use].cl; |
48e1416a | 640 | |
d09294c0 | 641 | /* If there's any alternative that allows USE to match DEF, do not |
642 | record a conflict. If that causes us to create an invalid | |
be18556f | 643 | instruction due to the earlyclobber, reload must fix it up. */ |
b5b87913 | 644 | alternative_mask enabled = recog_data.enabled_alternatives; |
d09294c0 | 645 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
757fefec | 646 | { |
b5b87913 | 647 | if (!TEST_BIT (enabled, alt1)) |
648 | continue; | |
8eaaac4d | 649 | const operand_alternative *op_alt1 |
650 | = &recog_op_alt[alt1 * n_operands]; | |
757fefec | 651 | if (op_alt1[use].matches == def |
652 | || (use < n_operands - 1 | |
653 | && recog_data.constraints[use][0] == '%' | |
654 | && op_alt1[use + 1].matches == def) | |
655 | || (use >= 1 | |
656 | && recog_data.constraints[use - 1][0] == '%' | |
657 | && op_alt1[use - 1].matches == def)) | |
658 | break; | |
659 | } | |
d09294c0 | 660 | |
661 | if (alt1 < recog_data.n_alternatives) | |
662 | continue; | |
663 | ||
044621b2 | 664 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
665 | use, use_cl, advance_p); | |
48e1416a | 666 | |
757fefec | 667 | if ((use_match = op_alt[use].matches) >= 0) |
7173d4d0 | 668 | { |
669 | if (use_match == def) | |
c2b66149 | 670 | continue; |
48e1416a | 671 | |
757fefec | 672 | if (op_alt[use_match].anything_ok) |
7173d4d0 | 673 | use_cl = ALL_REGS; |
674 | else | |
757fefec | 675 | use_cl = op_alt[use_match].cl; |
044621b2 | 676 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
677 | use, use_cl, advance_p); | |
7173d4d0 | 678 | } |
793e7497 | 679 | } |
7173d4d0 | 680 | } |
681 | ||
682 | /* Make conflicts of early clobber pseudo registers of the current | |
683 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
684 | checking classes of the constraints and pseudos because otherwise | |
685 | significant code degradation is possible for some targets. */ | |
686 | static void | |
687 | make_early_clobber_and_input_conflicts (void) | |
688 | { | |
689 | int alt; | |
690 | int def, def_match; | |
691 | enum reg_class def_cl; | |
692 | ||
757fefec | 693 | int n_alternatives = recog_data.n_alternatives; |
694 | int n_operands = recog_data.n_operands; | |
b5b87913 | 695 | alternative_mask enabled = recog_data.enabled_alternatives; |
8eaaac4d | 696 | const operand_alternative *op_alt = recog_op_alt; |
757fefec | 697 | for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands) |
b5b87913 | 698 | if (TEST_BIT (enabled, alt)) |
699 | for (def = 0; def < n_operands; def++) | |
700 | { | |
701 | def_cl = NO_REGS; | |
702 | if (op_alt[def].earlyclobber) | |
703 | { | |
704 | if (op_alt[def].anything_ok) | |
705 | def_cl = ALL_REGS; | |
706 | else | |
707 | def_cl = op_alt[def].cl; | |
708 | check_and_make_def_conflict (alt, def, def_cl); | |
709 | } | |
710 | if ((def_match = op_alt[def].matches) >= 0 | |
711 | && (op_alt[def_match].earlyclobber | |
712 | || op_alt[def].earlyclobber)) | |
713 | { | |
714 | if (op_alt[def_match].anything_ok) | |
715 | def_cl = ALL_REGS; | |
716 | else | |
717 | def_cl = op_alt[def_match].cl; | |
718 | check_and_make_def_conflict (alt, def, def_cl); | |
719 | } | |
720 | } | |
7173d4d0 | 721 | } |
722 | ||
723 | /* Mark early clobber hard registers of the current INSN as live (if | |
724 | LIVE_P) or dead. Return true if there are such registers. */ | |
725 | static bool | |
56067879 | 726 | mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p) |
7173d4d0 | 727 | { |
be10bb5a | 728 | df_ref def; |
7173d4d0 | 729 | bool set_p = false; |
793e7497 | 730 | |
be10bb5a | 731 | FOR_EACH_INSN_DEF (def, insn) |
732 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)) | |
793e7497 | 733 | { |
be10bb5a | 734 | rtx dreg = DF_REF_REG (def); |
48e1416a | 735 | |
793e7497 | 736 | if (GET_CODE (dreg) == SUBREG) |
737 | dreg = SUBREG_REG (dreg); | |
738 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
739 | continue; | |
740 | ||
741 | /* Hard register clobbers are believed to be early clobber | |
742 | because there is no way to say that non-operand hard | |
48e1416a | 743 | register clobbers are not early ones. */ |
793e7497 | 744 | if (live_p) |
be10bb5a | 745 | mark_ref_live (def); |
793e7497 | 746 | else |
be10bb5a | 747 | mark_ref_dead (def); |
793e7497 | 748 | set_p = true; |
749 | } | |
750 | ||
751 | return set_p; | |
752 | } | |
753 | ||
47dd2e78 | 754 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
755 | it is so, the function returns the class of the hard register. | |
756 | Otherwise it returns NO_REGS. */ | |
757 | static enum reg_class | |
758 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
759 | { | |
d2b854bc | 760 | int c; |
47dd2e78 | 761 | enum reg_class cl, next_cl; |
79bc09fb | 762 | enum constraint_num cn; |
47dd2e78 | 763 | |
764 | cl = NO_REGS; | |
d2b854bc | 765 | alternative_mask enabled = recog_data.enabled_alternatives; |
766 | for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)) | |
767 | if (c == '#') | |
768 | enabled &= ~ALTERNATIVE_BIT (0); | |
47dd2e78 | 769 | else if (c == ',') |
d2b854bc | 770 | enabled >>= 1; |
771 | else if (enabled & 1) | |
47dd2e78 | 772 | switch (c) |
773 | { | |
69449463 | 774 | case 'g': |
775 | return NO_REGS; | |
48e1416a | 776 | |
69449463 | 777 | default: |
c91b6d86 | 778 | /* ??? Is this the best way to handle memory constraints? */ |
79bc09fb | 779 | cn = lookup_constraint (constraints); |
780 | if (insn_extra_memory_constraint (cn) | |
781 | || insn_extra_address_constraint (cn)) | |
c91b6d86 | 782 | return NO_REGS; |
79bc09fb | 783 | if (constraint_satisfied_p (op, cn) |
c91b6d86 | 784 | || (equiv_const != NULL_RTX |
785 | && CONSTANT_P (equiv_const) | |
79bc09fb | 786 | && constraint_satisfied_p (equiv_const, cn))) |
c91b6d86 | 787 | return NO_REGS; |
69449463 | 788 | next_cl = reg_class_for_constraint (cn); |
c91b6d86 | 789 | if (next_cl == NO_REGS) |
790 | break; | |
c259678f | 791 | if (cl == NO_REGS |
792 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
793 | : (ira_class_singleton[cl][GET_MODE (op)] | |
794 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
47dd2e78 | 795 | return NO_REGS; |
796 | cl = next_cl; | |
797 | break; | |
48e1416a | 798 | |
47dd2e78 | 799 | case '0': case '1': case '2': case '3': case '4': |
800 | case '5': case '6': case '7': case '8': case '9': | |
801 | next_cl | |
802 | = single_reg_class (recog_data.constraints[c - '0'], | |
803 | recog_data.operand[c - '0'], NULL_RTX); | |
c259678f | 804 | if (cl == NO_REGS |
805 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
806 | : (ira_class_singleton[cl][GET_MODE (op)] | |
807 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
47dd2e78 | 808 | return NO_REGS; |
809 | cl = next_cl; | |
810 | break; | |
47dd2e78 | 811 | } |
812 | return cl; | |
813 | } | |
814 | ||
815 | /* The function checks that operand OP_NUM of the current insn can use | |
816 | only one hard register. If it is so, the function returns the | |
817 | class of the hard register. Otherwise it returns NO_REGS. */ | |
818 | static enum reg_class | |
819 | single_reg_operand_class (int op_num) | |
820 | { | |
821 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
822 | return NO_REGS; | |
823 | return single_reg_class (recog_data.constraints[op_num], | |
824 | recog_data.operand[op_num], NULL_RTX); | |
825 | } | |
826 | ||
a7dcf969 | 827 | /* The function sets up hard register set *SET to hard registers which |
828 | might be used by insn reloads because the constraints are too | |
829 | strict. */ | |
830 | void | |
831 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set) | |
832 | { | |
d2b854bc | 833 | int i, c, regno = 0; |
a7dcf969 | 834 | enum reg_class cl; |
835 | rtx op; | |
836 | enum machine_mode mode; | |
837 | ||
838 | CLEAR_HARD_REG_SET (*set); | |
839 | for (i = 0; i < recog_data.n_operands; i++) | |
840 | { | |
841 | op = recog_data.operand[i]; | |
842 | ||
843 | if (GET_CODE (op) == SUBREG) | |
844 | op = SUBREG_REG (op); | |
48e1416a | 845 | |
a7dcf969 | 846 | if (GET_CODE (op) == SCRATCH |
847 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
848 | { | |
849 | const char *p = recog_data.constraints[i]; | |
850 | ||
851 | mode = (GET_CODE (op) == SCRATCH | |
852 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
853 | cl = NO_REGS; | |
d2b854bc | 854 | alternative_mask enabled = recog_data.enabled_alternatives; |
855 | for (; (c = *p); p += CONSTRAINT_LEN (c, p)) | |
856 | if (c == '#') | |
857 | enabled &= ~ALTERNATIVE_BIT (0); | |
a7dcf969 | 858 | else if (c == ',') |
d2b854bc | 859 | enabled >>= 1; |
860 | else if (enabled & 1) | |
69449463 | 861 | { |
862 | cl = reg_class_for_constraint (lookup_constraint (p)); | |
863 | if (cl != NO_REGS) | |
864 | { | |
865 | /* There is no register pressure problem if all of the | |
866 | regs in this class are fixed. */ | |
867 | int regno = ira_class_singleton[cl][mode]; | |
868 | if (regno >= 0) | |
869 | add_to_hard_reg_set (set, mode, regno); | |
870 | } | |
871 | } | |
a7dcf969 | 872 | } |
873 | } | |
874 | } | |
47dd2e78 | 875 | /* Processes input operands, if IN_P, or output operands otherwise of |
876 | the current insn with FREQ to find allocno which can use only one | |
877 | hard register and makes other currently living allocnos conflicting | |
878 | with the hard register. */ | |
879 | static void | |
880 | process_single_reg_class_operands (bool in_p, int freq) | |
881 | { | |
744d7848 | 882 | int i, regno; |
47dd2e78 | 883 | unsigned int px; |
da7a04f1 | 884 | enum reg_class cl; |
47dd2e78 | 885 | rtx operand; |
886 | ira_allocno_t operand_a, a; | |
887 | ||
888 | for (i = 0; i < recog_data.n_operands; i++) | |
889 | { | |
890 | operand = recog_data.operand[i]; | |
891 | if (in_p && recog_data.operand_type[i] != OP_IN | |
892 | && recog_data.operand_type[i] != OP_INOUT) | |
893 | continue; | |
894 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
895 | && recog_data.operand_type[i] != OP_INOUT) | |
896 | continue; | |
897 | cl = single_reg_operand_class (i); | |
898 | if (cl == NO_REGS) | |
899 | continue; | |
900 | ||
901 | operand_a = NULL; | |
902 | ||
903 | if (GET_CODE (operand) == SUBREG) | |
904 | operand = SUBREG_REG (operand); | |
48e1416a | 905 | |
47dd2e78 | 906 | if (REG_P (operand) |
907 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
908 | { | |
66d9a7b9 | 909 | enum reg_class aclass; |
47dd2e78 | 910 | |
911 | operand_a = ira_curr_regno_allocno_map[regno]; | |
66d9a7b9 | 912 | aclass = ALLOCNO_CLASS (operand_a); |
c259678f | 913 | if (ira_class_subset_p[cl][aclass]) |
47dd2e78 | 914 | { |
744d7848 | 915 | /* View the desired allocation of OPERAND as: |
916 | ||
917 | (REG:YMODE YREGNO), | |
918 | ||
919 | a simplification of: | |
920 | ||
921 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
922 | enum machine_mode ymode, xmode; | |
923 | int xregno, yregno; | |
924 | HOST_WIDE_INT offset; | |
925 | ||
926 | xmode = recog_data.operand_mode[i]; | |
c259678f | 927 | xregno = ira_class_singleton[cl][xmode]; |
928 | gcc_assert (xregno >= 0); | |
744d7848 | 929 | ymode = ALLOCNO_MODE (operand_a); |
930 | offset = subreg_lowpart_offset (ymode, xmode); | |
931 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
932 | if (yregno >= 0 | |
66d9a7b9 | 933 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
744d7848 | 934 | { |
935 | int cost; | |
936 | ||
937 | ira_allocate_and_set_costs | |
938 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
66d9a7b9 | 939 | aclass, 0); |
940 | ira_init_register_move_cost_if_necessary (xmode); | |
941 | cost = freq * (in_p | |
942 | ? ira_register_move_cost[xmode][aclass][cl] | |
943 | : ira_register_move_cost[xmode][cl][aclass]); | |
744d7848 | 944 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
66d9a7b9 | 945 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
744d7848 | 946 | } |
47dd2e78 | 947 | } |
948 | } | |
949 | ||
be18556f | 950 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
47dd2e78 | 951 | { |
be18556f | 952 | ira_object_t obj = ira_object_id_map[px]; |
953 | a = OBJECT_ALLOCNO (obj); | |
47dd2e78 | 954 | if (a != operand_a) |
955 | { | |
956 | /* We could increase costs of A instead of making it | |
957 | conflicting with the hard register. But it works worse | |
958 | because it will be spilled in reload in anyway. */ | |
ae9587ed | 959 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
47dd2e78 | 960 | reg_class_contents[cl]); |
ae9587ed | 961 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
47dd2e78 | 962 | reg_class_contents[cl]); |
963 | } | |
964 | } | |
965 | } | |
966 | } | |
967 | ||
9f724a58 | 968 | /* Return true when one of the predecessor edges of BB is marked with |
969 | EDGE_ABNORMAL_CALL or EDGE_EH. */ | |
970 | static bool | |
971 | bb_has_abnormal_call_pred (basic_block bb) | |
972 | { | |
973 | edge e; | |
974 | edge_iterator ei; | |
48e1416a | 975 | |
9f724a58 | 976 | FOR_EACH_EDGE (e, ei, bb->preds) |
977 | { | |
978 | if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH)) | |
979 | return true; | |
980 | } | |
981 | return false; | |
982 | } | |
983 | ||
c8010b80 | 984 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
985 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
986 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
987 | static rtx | |
56067879 | 988 | find_call_crossed_cheap_reg (rtx_insn *insn) |
c8010b80 | 989 | { |
990 | rtx cheap_reg = NULL_RTX; | |
991 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
992 | ||
993 | while (exp != NULL) | |
994 | { | |
995 | rtx x = XEXP (exp, 0); | |
996 | if (GET_CODE (x) == SET) | |
997 | { | |
998 | exp = x; | |
999 | break; | |
1000 | } | |
1001 | exp = XEXP (exp, 1); | |
1002 | } | |
1003 | if (exp != NULL) | |
1004 | { | |
1005 | basic_block bb = BLOCK_FOR_INSN (insn); | |
1006 | rtx reg = SET_SRC (exp); | |
fde37bf5 | 1007 | rtx_insn *prev = PREV_INSN (insn); |
c8010b80 | 1008 | while (prev && !(INSN_P (prev) |
1009 | && BLOCK_FOR_INSN (prev) != bb)) | |
1010 | { | |
1011 | if (NONDEBUG_INSN_P (prev)) | |
1012 | { | |
1013 | rtx set = single_set (prev); | |
1014 | ||
1015 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
1016 | { | |
1017 | rtx src = SET_SRC (set); | |
1018 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
1019 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1020 | break; | |
1021 | if (!modified_between_p (src, prev, insn)) | |
1022 | cheap_reg = src; | |
1023 | break; | |
1024 | } | |
1025 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1026 | { | |
1027 | rtx dest = SET_DEST (set); | |
1028 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1029 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1030 | break; | |
1031 | if (!modified_between_p (dest, prev, insn)) | |
1032 | cheap_reg = dest; | |
1033 | break; | |
1034 | } | |
1035 | ||
1036 | if (reg_overlap_mentioned_p (reg, PATTERN (prev))) | |
1037 | break; | |
1038 | } | |
1039 | prev = PREV_INSN (prev); | |
1040 | } | |
1041 | } | |
1042 | return cheap_reg; | |
1043 | } | |
1044 | ||
47dd2e78 | 1045 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1046 | update allocno live ranges, allocno hard register conflicts, | |
1047 | intersected calls, and register pressure info for allocnos for the | |
1048 | basic block for and regions containing the basic block. */ | |
1049 | static void | |
1050 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1051 | { | |
7e03a244 | 1052 | int i, freq; |
47dd2e78 | 1053 | unsigned int j; |
1054 | basic_block bb; | |
56067879 | 1055 | rtx_insn *insn; |
47dd2e78 | 1056 | bitmap_iterator bi; |
7e03a244 | 1057 | bitmap reg_live_out; |
47dd2e78 | 1058 | unsigned int px; |
793e7497 | 1059 | bool set_p; |
47dd2e78 | 1060 | |
1061 | bb = loop_tree_node->bb; | |
1062 | if (bb != NULL) | |
1063 | { | |
66d9a7b9 | 1064 | for (i = 0; i < ira_pressure_classes_num; i++) |
47dd2e78 | 1065 | { |
66d9a7b9 | 1066 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1067 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
47dd2e78 | 1068 | } |
1069 | curr_bb_node = loop_tree_node; | |
0841d295 | 1070 | reg_live_out = df_get_live_out (bb); |
be18556f | 1071 | sparseset_clear (objects_live); |
7e03a244 | 1072 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
47dd2e78 | 1073 | AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); |
1074 | AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
1075 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1076 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1077 | { | |
66d9a7b9 | 1078 | enum reg_class aclass, pclass, cl; |
48e1416a | 1079 | |
66d9a7b9 | 1080 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1081 | pclass = ira_pressure_class_translate[aclass]; | |
14792f4e | 1082 | for (j = 0; |
66d9a7b9 | 1083 | (cl = ira_reg_class_super_classes[pclass][j]) |
14792f4e | 1084 | != LIM_REG_CLASSES; |
1085 | j++) | |
1086 | { | |
66d9a7b9 | 1087 | if (! ira_reg_pressure_class_p[cl]) |
1088 | continue; | |
14792f4e | 1089 | curr_reg_pressure[cl]++; |
1090 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1091 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1092 | ira_assert (curr_reg_pressure[cl] | |
1072fecf | 1093 | <= ira_class_hard_regs_num[cl]); |
14792f4e | 1094 | } |
47dd2e78 | 1095 | } |
7e03a244 | 1096 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
b4f5e198 | 1097 | mark_pseudo_regno_live (j); |
48e1416a | 1098 | |
7e03a244 | 1099 | freq = REG_FREQ_FROM_BB (bb); |
1100 | if (freq == 0) | |
1101 | freq = 1; | |
1102 | ||
df07a54c | 1103 | /* Invalidate all allocno_saved_at_call entries. */ |
1104 | last_call_num++; | |
1105 | ||
47dd2e78 | 1106 | /* Scan the code of this basic block, noting which allocnos and |
7e03a244 | 1107 | hard regs are born or die. |
1108 | ||
1109 | Note that this loop treats uninitialized values as live until | |
1110 | the beginning of the block. For example, if an instruction | |
1111 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1112 | set, FOO will remain live until the beginning of the block. | |
1113 | Likewise if FOO is not set at all. This is unnecessarily | |
1114 | pessimistic, but it probably doesn't matter much in practice. */ | |
1115 | FOR_BB_INSNS_REVERSE (bb, insn) | |
47dd2e78 | 1116 | { |
be10bb5a | 1117 | df_ref def, use; |
7e03a244 | 1118 | bool call_p; |
48e1416a | 1119 | |
9845d120 | 1120 | if (!NONDEBUG_INSN_P (insn)) |
47dd2e78 | 1121 | continue; |
48e1416a | 1122 | |
47dd2e78 | 1123 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1124 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
9f8ac546 | 1125 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
47dd2e78 | 1126 | curr_point); |
1127 | ||
7e03a244 | 1128 | /* Mark each defined value as live. We need to do this for |
1129 | unused values because they still conflict with quantities | |
1130 | that are live at the time of the definition. | |
1131 | ||
1132 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1133 | references represent the effect of the called function | |
1134 | on a call-clobbered register. Marking the register as | |
1135 | live would stop us from allocating it to a call-crossing | |
1136 | allocno. */ | |
1137 | call_p = CALL_P (insn); | |
be10bb5a | 1138 | FOR_EACH_INSN_DEF (def, insn) |
1139 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1140 | mark_ref_live (def); | |
7e03a244 | 1141 | |
1142 | /* If INSN has multiple outputs, then any value used in one | |
1143 | of the outputs conflicts with the other outputs. Model this | |
1144 | by making the used value live during the output phase. | |
1145 | ||
1146 | It is unsafe to use !single_set here since it will ignore | |
1147 | an unused output. Just because an output is unused does | |
1148 | not mean the compiler can assume the side effect will not | |
1149 | occur. Consider if ALLOCNO appears in the address of an | |
1150 | output and we reload the output. If we allocate ALLOCNO | |
1151 | to the same hard register as an unused output we could | |
1152 | set the hard register before the output reload insn. */ | |
1153 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
be10bb5a | 1154 | FOR_EACH_INSN_USE (use, insn) |
7e03a244 | 1155 | { |
1156 | int i; | |
1157 | rtx reg; | |
1158 | ||
be10bb5a | 1159 | reg = DF_REF_REG (use); |
7e03a244 | 1160 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
1161 | { | |
1162 | rtx set; | |
1163 | ||
1164 | set = XVECEXP (PATTERN (insn), 0, i); | |
1165 | if (GET_CODE (set) == SET | |
1166 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1167 | { | |
1168 | /* After the previous loop, this is a no-op if | |
1169 | REG is contained within SET_DEST (SET). */ | |
be10bb5a | 1170 | mark_ref_live (use); |
7e03a244 | 1171 | break; |
1172 | } | |
1173 | } | |
1174 | } | |
48e1416a | 1175 | |
47dd2e78 | 1176 | extract_insn (insn); |
8eaaac4d | 1177 | preprocess_constraints (insn); |
7e03a244 | 1178 | process_single_reg_class_operands (false, freq); |
48e1416a | 1179 | |
7e03a244 | 1180 | /* See which defined values die here. */ |
be10bb5a | 1181 | FOR_EACH_INSN_DEF (def, insn) |
1182 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1183 | mark_ref_dead (def); | |
47dd2e78 | 1184 | |
7e03a244 | 1185 | if (call_p) |
47dd2e78 | 1186 | { |
c8010b80 | 1187 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1188 | there, try to find a pseudo that is live across the call but | |
1189 | can be cheaply reconstructed from the return value. */ | |
1190 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1191 | if (cheap_reg != NULL_RTX) | |
1192 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1193 | ||
df07a54c | 1194 | last_call_num++; |
be18556f | 1195 | sparseset_clear (allocnos_processed); |
7e03a244 | 1196 | /* The current set of live allocnos are live across the call. */ |
be18556f | 1197 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
47dd2e78 | 1198 | { |
be18556f | 1199 | ira_object_t obj = ira_object_id_map[i]; |
1200 | ira_allocno_t a = OBJECT_ALLOCNO (obj); | |
1201 | int num = ALLOCNO_NUM (a); | |
754158d9 | 1202 | HARD_REG_SET this_call_used_reg_set; |
1203 | ||
1204 | get_call_reg_set_usage (insn, &this_call_used_reg_set, | |
1205 | call_used_reg_set); | |
48e1416a | 1206 | |
d6a421d5 | 1207 | /* Don't allocate allocnos that cross setjmps or any |
1208 | call, if this function receives a nonlocal | |
1209 | goto. */ | |
1210 | if (cfun->has_nonlocal_label | |
1211 | || find_reg_note (insn, REG_SETJMP, | |
1212 | NULL_RTX) != NULL_RTX) | |
47dd2e78 | 1213 | { |
ae9587ed | 1214 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1215 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
47dd2e78 | 1216 | } |
cab55469 | 1217 | if (can_throw_internal (insn)) |
1218 | { | |
ae9587ed | 1219 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
754158d9 | 1220 | this_call_used_reg_set); |
be18556f | 1221 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
754158d9 | 1222 | this_call_used_reg_set); |
cab55469 | 1223 | } |
be18556f | 1224 | |
1225 | if (sparseset_bit_p (allocnos_processed, num)) | |
1226 | continue; | |
1227 | sparseset_set_bit (allocnos_processed, num); | |
1228 | ||
1229 | if (allocno_saved_at_call[num] != last_call_num) | |
1230 | /* Here we are mimicking caller-save.c behaviour | |
1231 | which does not save hard register at a call if | |
1232 | it was saved on previous call in the same basic | |
1233 | block and the hard register was not mentioned | |
1234 | between the two calls. */ | |
1235 | ALLOCNO_CALL_FREQ (a) += freq; | |
1236 | /* Mark it as saved at the next call. */ | |
1237 | allocno_saved_at_call[num] = last_call_num + 1; | |
1238 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
754158d9 | 1239 | IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), |
1240 | this_call_used_reg_set); | |
c8010b80 | 1241 | if (cheap_reg != NULL_RTX |
1242 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1243 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
47dd2e78 | 1244 | } |
1245 | } | |
48e1416a | 1246 | |
7173d4d0 | 1247 | make_early_clobber_and_input_conflicts (); |
1248 | ||
7e03a244 | 1249 | curr_point++; |
1250 | ||
1251 | /* Mark each used value as live. */ | |
be10bb5a | 1252 | FOR_EACH_INSN_USE (use, insn) |
1253 | mark_ref_live (use); | |
7e03a244 | 1254 | |
7e03a244 | 1255 | process_single_reg_class_operands (true, freq); |
48e1416a | 1256 | |
7173d4d0 | 1257 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1258 | ||
793e7497 | 1259 | if (set_p) |
1260 | { | |
7173d4d0 | 1261 | mark_hard_reg_early_clobbers (insn, false); |
793e7497 | 1262 | |
7173d4d0 | 1263 | /* Mark each hard reg as live again. For example, a |
793e7497 | 1264 | hard register can be in clobber and in an insn |
1265 | input. */ | |
be10bb5a | 1266 | FOR_EACH_INSN_USE (use, insn) |
7173d4d0 | 1267 | { |
be10bb5a | 1268 | rtx ureg = DF_REF_REG (use); |
48e1416a | 1269 | |
7173d4d0 | 1270 | if (GET_CODE (ureg) == SUBREG) |
1271 | ureg = SUBREG_REG (ureg); | |
1272 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1273 | continue; | |
48e1416a | 1274 | |
be10bb5a | 1275 | mark_ref_live (use); |
7173d4d0 | 1276 | } |
793e7497 | 1277 | } |
47dd2e78 | 1278 | |
47dd2e78 | 1279 | curr_point++; |
1280 | } | |
7e03a244 | 1281 | |
fee75d9b | 1282 | #ifdef EH_RETURN_DATA_REGNO |
1283 | if (bb_has_eh_pred (bb)) | |
1284 | for (j = 0; ; ++j) | |
1285 | { | |
1286 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1287 | if (regno == INVALID_REGNUM) | |
1288 | break; | |
b4f5e198 | 1289 | make_hard_regno_born (regno); |
fee75d9b | 1290 | } |
1291 | #endif | |
1292 | ||
7e03a244 | 1293 | /* Allocnos can't go in stack regs at the start of a basic block |
1294 | that is reached by an abnormal edge. Likewise for call | |
1295 | clobbered regs, because caller-save, fixup_abnormal_edges and | |
1296 | possibly the table driven EH machinery are not quite ready to | |
1297 | handle such allocnos live across such edges. */ | |
fee75d9b | 1298 | if (bb_has_abnormal_pred (bb)) |
7e03a244 | 1299 | { |
1300 | #ifdef STACK_REGS | |
be18556f | 1301 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
7e03a244 | 1302 | { |
be18556f | 1303 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
66d9a7b9 | 1304 | |
be18556f | 1305 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1306 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
7e03a244 | 1307 | } |
1308 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
b4f5e198 | 1309 | make_hard_regno_born (px); |
7e03a244 | 1310 | #endif |
1311 | /* No need to record conflicts for call clobbered regs if we | |
1312 | have nonlocal labels around, as we don't ever try to | |
1313 | allocate such regs in this case. */ | |
9f724a58 | 1314 | if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb)) |
7e03a244 | 1315 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
1316 | if (call_used_regs[px]) | |
b4f5e198 | 1317 | make_hard_regno_born (px); |
7e03a244 | 1318 | } |
1319 | ||
be18556f | 1320 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1321 | make_object_dead (ira_object_id_map[i]); | |
47dd2e78 | 1322 | |
1323 | curr_point++; | |
1324 | ||
1325 | } | |
3ad55f68 | 1326 | /* Propagate register pressure to upper loop tree nodes. */ |
47dd2e78 | 1327 | if (loop_tree_node != ira_loop_tree_root) |
66d9a7b9 | 1328 | for (i = 0; i < ira_pressure_classes_num; i++) |
47dd2e78 | 1329 | { |
66d9a7b9 | 1330 | enum reg_class pclass; |
47dd2e78 | 1331 | |
66d9a7b9 | 1332 | pclass = ira_pressure_classes[i]; |
1333 | if (loop_tree_node->reg_pressure[pclass] | |
1334 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1335 | loop_tree_node->parent->reg_pressure[pclass] | |
1336 | = loop_tree_node->reg_pressure[pclass]; | |
47dd2e78 | 1337 | } |
1338 | } | |
1339 | ||
1340 | /* Create and set up IRA_START_POINT_RANGES and | |
1341 | IRA_FINISH_POINT_RANGES. */ | |
1342 | static void | |
1343 | create_start_finish_chains (void) | |
1344 | { | |
be18556f | 1345 | ira_object_t obj; |
1346 | ira_object_iterator oi; | |
fbff82f4 | 1347 | live_range_t r; |
47dd2e78 | 1348 | |
1349 | ira_start_point_ranges | |
be18556f | 1350 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1351 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
47dd2e78 | 1352 | ira_finish_point_ranges |
be18556f | 1353 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1354 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1355 | FOR_EACH_OBJECT (obj, oi) | |
1356 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1357 | { | |
1358 | r->start_next = ira_start_point_ranges[r->start]; | |
1359 | ira_start_point_ranges[r->start] = r; | |
1360 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
47dd2e78 | 1361 | ira_finish_point_ranges[r->finish] = r; |
be18556f | 1362 | } |
47dd2e78 | 1363 | } |
1364 | ||
1365 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1366 | new live ranges and program points were added as a result if new | |
1367 | insn generation. */ | |
1368 | void | |
1369 | ira_rebuild_start_finish_chains (void) | |
1370 | { | |
1371 | ira_free (ira_finish_point_ranges); | |
1372 | ira_free (ira_start_point_ranges); | |
1373 | create_start_finish_chains (); | |
1374 | } | |
1375 | ||
7f36fbdf | 1376 | /* Compress allocno live ranges by removing program points where |
1377 | nothing happens. */ | |
1378 | static void | |
1379 | remove_some_program_points_and_update_live_ranges (void) | |
1380 | { | |
1381 | unsigned i; | |
1382 | int n; | |
1383 | int *map; | |
9d53e372 | 1384 | ira_object_t obj; |
1385 | ira_object_iterator oi; | |
d068a2f3 | 1386 | live_range_t r, prev_r, next_r; |
82cc92bf | 1387 | sbitmap born_or_dead, born, dead; |
1388 | sbitmap_iterator sbi; | |
1389 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1390 | ||
1391 | born = sbitmap_alloc (ira_max_point); | |
1392 | dead = sbitmap_alloc (ira_max_point); | |
53c5d9d4 | 1393 | bitmap_clear (born); |
1394 | bitmap_clear (dead); | |
9d53e372 | 1395 | FOR_EACH_OBJECT (obj, oi) |
1396 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1397 | { | |
1398 | ira_assert (r->start <= r->finish); | |
08b7917c | 1399 | bitmap_set_bit (born, r->start); |
1400 | bitmap_set_bit (dead, r->finish); | |
9d53e372 | 1401 | } |
1402 | ||
82cc92bf | 1403 | born_or_dead = sbitmap_alloc (ira_max_point); |
53c5d9d4 | 1404 | bitmap_ior (born_or_dead, born, dead); |
7f36fbdf | 1405 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
82cc92bf | 1406 | n = -1; |
1407 | prev_born_p = prev_dead_p = false; | |
0d211963 | 1408 | EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi) |
7f36fbdf | 1409 | { |
08b7917c | 1410 | born_p = bitmap_bit_p (born, i); |
1411 | dead_p = bitmap_bit_p (dead, i); | |
82cc92bf | 1412 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
1413 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1414 | map[i] = n; | |
1415 | else | |
1416 | map[i] = ++n; | |
1417 | prev_born_p = born_p; | |
1418 | prev_dead_p = dead_p; | |
7f36fbdf | 1419 | } |
82cc92bf | 1420 | sbitmap_free (born_or_dead); |
1421 | sbitmap_free (born); | |
1422 | sbitmap_free (dead); | |
1423 | n++; | |
7f36fbdf | 1424 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1425 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1426 | ira_max_point, n, 100 * n / ira_max_point); | |
1427 | ira_max_point = n; | |
9d53e372 | 1428 | |
1429 | FOR_EACH_OBJECT (obj, oi) | |
d068a2f3 | 1430 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9d53e372 | 1431 | { |
d068a2f3 | 1432 | next_r = r->next; |
9d53e372 | 1433 | r->start = map[r->start]; |
1434 | r->finish = map[r->finish]; | |
d068a2f3 | 1435 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1436 | { | |
1437 | prev_r = r; | |
1438 | continue; | |
1439 | } | |
1440 | prev_r->start = r->start; | |
1441 | prev_r->next = next_r; | |
1442 | ira_finish_live_range (r); | |
9d53e372 | 1443 | } |
be18556f | 1444 | |
7f36fbdf | 1445 | ira_free (map); |
1446 | } | |
1447 | ||
47dd2e78 | 1448 | /* Print live ranges R to file F. */ |
1449 | void | |
fbff82f4 | 1450 | ira_print_live_range_list (FILE *f, live_range_t r) |
47dd2e78 | 1451 | { |
1452 | for (; r != NULL; r = r->next) | |
1453 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1454 | fprintf (f, "\n"); | |
1455 | } | |
1456 | ||
c7d89805 | 1457 | DEBUG_FUNCTION void |
1458 | debug (live_range &ref) | |
1459 | { | |
1460 | ira_print_live_range_list (stderr, &ref); | |
1461 | } | |
1462 | ||
1463 | DEBUG_FUNCTION void | |
1464 | debug (live_range *ptr) | |
1465 | { | |
1466 | if (ptr) | |
1467 | debug (*ptr); | |
1468 | else | |
1469 | fprintf (stderr, "<nil>\n"); | |
1470 | } | |
1471 | ||
47dd2e78 | 1472 | /* Print live ranges R to stderr. */ |
1473 | void | |
fbff82f4 | 1474 | ira_debug_live_range_list (live_range_t r) |
47dd2e78 | 1475 | { |
1476 | ira_print_live_range_list (stderr, r); | |
1477 | } | |
1478 | ||
be18556f | 1479 | /* Print live ranges of object OBJ to file F. */ |
1480 | static void | |
1481 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1482 | { | |
1483 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1484 | } | |
1485 | ||
47dd2e78 | 1486 | /* Print live ranges of allocno A to file F. */ |
1487 | static void | |
1488 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1489 | { | |
be18556f | 1490 | int n = ALLOCNO_NUM_OBJECTS (a); |
1491 | int i; | |
66d9a7b9 | 1492 | |
be18556f | 1493 | for (i = 0; i < n; i++) |
1494 | { | |
1495 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1496 | if (n > 1) | |
1497 | fprintf (f, " [%d]", i); | |
1498 | fprintf (f, "):"); | |
1499 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1500 | } | |
47dd2e78 | 1501 | } |
1502 | ||
1503 | /* Print live ranges of allocno A to stderr. */ | |
1504 | void | |
1505 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1506 | { | |
1507 | print_allocno_live_ranges (stderr, a); | |
1508 | } | |
1509 | ||
1510 | /* Print live ranges of all allocnos to file F. */ | |
1511 | static void | |
1512 | print_live_ranges (FILE *f) | |
1513 | { | |
1514 | ira_allocno_t a; | |
1515 | ira_allocno_iterator ai; | |
1516 | ||
1517 | FOR_EACH_ALLOCNO (a, ai) | |
1518 | print_allocno_live_ranges (f, a); | |
1519 | } | |
1520 | ||
1521 | /* Print live ranges of all allocnos to stderr. */ | |
1522 | void | |
1523 | ira_debug_live_ranges (void) | |
1524 | { | |
1525 | print_live_ranges (stderr); | |
1526 | } | |
1527 | ||
1528 | /* The main entry function creates live ranges, set up | |
be18556f | 1529 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
47dd2e78 | 1530 | calculate register pressure info. */ |
1531 | void | |
1532 | ira_create_allocno_live_ranges (void) | |
1533 | { | |
be18556f | 1534 | objects_live = sparseset_alloc (ira_objects_num); |
1535 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
47dd2e78 | 1536 | curr_point = 0; |
df07a54c | 1537 | last_call_num = 0; |
1538 | allocno_saved_at_call | |
1539 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1540 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
47dd2e78 | 1541 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1542 | process_bb_node_lives); | |
1543 | ira_max_point = curr_point; | |
1544 | create_start_finish_chains (); | |
1545 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1546 | print_live_ranges (ira_dump_file); | |
1547 | /* Clean up. */ | |
df07a54c | 1548 | ira_free (allocno_saved_at_call); |
be18556f | 1549 | sparseset_free (objects_live); |
1550 | sparseset_free (allocnos_processed); | |
47dd2e78 | 1551 | } |
1552 | ||
7f36fbdf | 1553 | /* Compress allocno live ranges. */ |
1554 | void | |
1555 | ira_compress_allocno_live_ranges (void) | |
1556 | { | |
1557 | remove_some_program_points_and_update_live_ranges (); | |
1558 | ira_rebuild_start_finish_chains (); | |
1559 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1560 | { | |
1561 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1562 | print_live_ranges (ira_dump_file); | |
1563 | } | |
1564 | } | |
1565 | ||
47dd2e78 | 1566 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1567 | void | |
1568 | ira_finish_allocno_live_ranges (void) | |
1569 | { | |
1570 | ira_free (ira_finish_point_ranges); | |
1571 | ira_free (ira_start_point_ranges); | |
1572 | } |