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47dd2e78 | 1 | /* IRA processing allocno lives to build allocno live ranges. |
7cf0dbf3 | 2 | Copyright (C) 2006, 2007, 2008, 2009, 2010 |
47dd2e78 | 3 | Free Software Foundation, Inc. |
4 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it under | |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 3, or (at your option) any later | |
11 | version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "system.h" | |
24 | #include "coretypes.h" | |
25 | #include "tm.h" | |
26 | #include "regs.h" | |
27 | #include "rtl.h" | |
28 | #include "tm_p.h" | |
29 | #include "target.h" | |
30 | #include "flags.h" | |
cab55469 | 31 | #include "except.h" |
47dd2e78 | 32 | #include "hard-reg-set.h" |
33 | #include "basic-block.h" | |
34 | #include "insn-config.h" | |
35 | #include "recog.h" | |
0b205f4c | 36 | #include "diagnostic-core.h" |
47dd2e78 | 37 | #include "params.h" |
38 | #include "df.h" | |
82cc92bf | 39 | #include "sbitmap.h" |
47dd2e78 | 40 | #include "sparseset.h" |
41 | #include "ira-int.h" | |
42 | ||
43 | /* The code in this file is similar to one in global but the code | |
44 | works on the allocno basis and creates live ranges instead of | |
45 | pseudo-register conflicts. */ | |
46 | ||
47 | /* Program points are enumerated by numbers from range | |
48 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
49 | points than insns. Program points are places in the program where | |
50 | liveness info can be changed. In most general case (there are more | |
51 | complicated cases too) some program points correspond to places | |
52 | where input operand dies and other ones correspond to places where | |
53 | output operands are born. */ | |
54 | int ira_max_point; | |
55 | ||
56 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
57 | live ranges with given start/finish point. */ | |
fbff82f4 | 58 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
47dd2e78 | 59 | |
60 | /* Number of the current program point. */ | |
61 | static int curr_point; | |
62 | ||
63 | /* Point where register pressure excess started or -1 if there is no | |
64 | register pressure excess. Excess pressure for a register class at | |
65 | some point means that there are more allocnos of given register | |
66 | class living at the point than number of hard-registers of the | |
66d9a7b9 | 67 | class available for the allocation. It is defined only for |
68 | pressure classes. */ | |
47dd2e78 | 69 | static int high_pressure_start_point[N_REG_CLASSES]; |
70 | ||
be18556f | 71 | /* Objects live at current point in the scan. */ |
72 | static sparseset objects_live; | |
73 | ||
74 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
75 | multiple times. */ | |
76 | static sparseset allocnos_processed; | |
47dd2e78 | 77 | |
78 | /* Set of hard regs (except eliminable ones) currently live. */ | |
79 | static HARD_REG_SET hard_regs_live; | |
80 | ||
81 | /* The loop tree node corresponding to the current basic block. */ | |
82 | static ira_loop_tree_node_t curr_bb_node; | |
83 | ||
df07a54c | 84 | /* The number of the last processed call. */ |
85 | static int last_call_num; | |
86 | /* The number of last call at which given allocno was saved. */ | |
87 | static int *allocno_saved_at_call; | |
88 | ||
be18556f | 89 | /* Record the birth of hard register REGNO, updating hard_regs_live and |
90 | hard reg conflict information for living allocnos. */ | |
47dd2e78 | 91 | static void |
b4f5e198 | 92 | make_hard_regno_born (int regno) |
47dd2e78 | 93 | { |
94 | unsigned int i; | |
47dd2e78 | 95 | |
b4f5e198 | 96 | SET_HARD_REG_BIT (hard_regs_live, regno); |
be18556f | 97 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
47dd2e78 | 98 | { |
be18556f | 99 | ira_object_t obj = ira_object_id_map[i]; |
66d9a7b9 | 100 | |
ae9587ed | 101 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
102 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
47dd2e78 | 103 | } |
b4f5e198 | 104 | } |
105 | ||
106 | /* Process the death of hard register REGNO. This updates | |
107 | hard_regs_live. */ | |
108 | static void | |
109 | make_hard_regno_dead (int regno) | |
110 | { | |
111 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); | |
112 | } | |
113 | ||
be18556f | 114 | /* Record the birth of object OBJ. Set a bit for it in objects_live, |
115 | start a new live range for it if necessary and update hard register | |
116 | conflicts. */ | |
b4f5e198 | 117 | static void |
be18556f | 118 | make_object_born (ira_object_t obj) |
b4f5e198 | 119 | { |
be18556f | 120 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
b4f5e198 | 121 | |
be18556f | 122 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
ae9587ed | 123 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
124 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); | |
b4f5e198 | 125 | |
be18556f | 126 | if (lr == NULL |
127 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
128 | ira_add_live_range_to_object (obj, curr_point, -1); | |
47dd2e78 | 129 | } |
130 | ||
be18556f | 131 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
132 | associated with object OBJ. */ | |
47dd2e78 | 133 | static void |
be18556f | 134 | update_allocno_pressure_excess_length (ira_object_t obj) |
47dd2e78 | 135 | { |
be18556f | 136 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
14792f4e | 137 | int start, i; |
66d9a7b9 | 138 | enum reg_class aclass, pclass, cl; |
fbff82f4 | 139 | live_range_t p; |
47dd2e78 | 140 | |
66d9a7b9 | 141 | aclass = ALLOCNO_CLASS (a); |
142 | pclass = ira_pressure_class_translate[aclass]; | |
14792f4e | 143 | for (i = 0; |
66d9a7b9 | 144 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 145 | i++) |
146 | { | |
66d9a7b9 | 147 | if (! ira_reg_pressure_class_p[cl]) |
148 | continue; | |
14792f4e | 149 | if (high_pressure_start_point[cl] < 0) |
150 | continue; | |
9d53e372 | 151 | p = OBJECT_LIVE_RANGES (obj); |
14792f4e | 152 | ira_assert (p != NULL); |
153 | start = (high_pressure_start_point[cl] > p->start | |
154 | ? high_pressure_start_point[cl] : p->start); | |
155 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
156 | } | |
47dd2e78 | 157 | } |
158 | ||
be18556f | 159 | /* Process the death of object OBJ, which is associated with allocno |
160 | A. This finishes the current live range for it. */ | |
47dd2e78 | 161 | static void |
be18556f | 162 | make_object_dead (ira_object_t obj) |
47dd2e78 | 163 | { |
be18556f | 164 | live_range_t lr; |
47dd2e78 | 165 | |
be18556f | 166 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
167 | lr = OBJECT_LIVE_RANGES (obj); | |
168 | ira_assert (lr != NULL); | |
169 | lr->finish = curr_point; | |
170 | update_allocno_pressure_excess_length (obj); | |
47dd2e78 | 171 | } |
172 | ||
66d9a7b9 | 173 | /* The current register pressures for each pressure class for the current |
47dd2e78 | 174 | basic block. */ |
175 | static int curr_reg_pressure[N_REG_CLASSES]; | |
176 | ||
66d9a7b9 | 177 | /* Record that register pressure for PCLASS increased by N registers. |
178 | Update the current register pressure, maximal register pressure for | |
179 | the current BB and the start point of the register pressure | |
180 | excess. */ | |
47dd2e78 | 181 | static void |
66d9a7b9 | 182 | inc_register_pressure (enum reg_class pclass, int n) |
47dd2e78 | 183 | { |
14792f4e | 184 | int i; |
b4f5e198 | 185 | enum reg_class cl; |
47dd2e78 | 186 | |
14792f4e | 187 | for (i = 0; |
66d9a7b9 | 188 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 189 | i++) |
190 | { | |
66d9a7b9 | 191 | if (! ira_reg_pressure_class_p[cl]) |
192 | continue; | |
b4f5e198 | 193 | curr_reg_pressure[cl] += n; |
14792f4e | 194 | if (high_pressure_start_point[cl] < 0 |
1072fecf | 195 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
14792f4e | 196 | high_pressure_start_point[cl] = curr_point; |
197 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
198 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
199 | } | |
47dd2e78 | 200 | } |
201 | ||
66d9a7b9 | 202 | /* Record that register pressure for PCLASS has decreased by NREGS |
203 | registers; update current register pressure, start point of the | |
204 | register pressure excess, and register pressure excess length for | |
205 | living allocnos. */ | |
b4f5e198 | 206 | |
47dd2e78 | 207 | static void |
66d9a7b9 | 208 | dec_register_pressure (enum reg_class pclass, int nregs) |
47dd2e78 | 209 | { |
14792f4e | 210 | int i; |
211 | unsigned int j; | |
b4f5e198 | 212 | enum reg_class cl; |
213 | bool set_p = false; | |
47dd2e78 | 214 | |
b4f5e198 | 215 | for (i = 0; |
66d9a7b9 | 216 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
b4f5e198 | 217 | i++) |
47dd2e78 | 218 | { |
66d9a7b9 | 219 | if (! ira_reg_pressure_class_p[cl]) |
220 | continue; | |
b4f5e198 | 221 | curr_reg_pressure[cl] -= nregs; |
222 | ira_assert (curr_reg_pressure[cl] >= 0); | |
223 | if (high_pressure_start_point[cl] >= 0 | |
1072fecf | 224 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
b4f5e198 | 225 | set_p = true; |
226 | } | |
227 | if (set_p) | |
228 | { | |
be18556f | 229 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
230 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
14792f4e | 231 | for (i = 0; |
66d9a7b9 | 232 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 233 | i++) |
66d9a7b9 | 234 | { |
235 | if (! ira_reg_pressure_class_p[cl]) | |
236 | continue; | |
237 | if (high_pressure_start_point[cl] >= 0 | |
1072fecf | 238 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
66d9a7b9 | 239 | high_pressure_start_point[cl] = -1; |
240 | } | |
47dd2e78 | 241 | } |
47dd2e78 | 242 | } |
243 | ||
c8010b80 | 244 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
245 | and occupies only one object. Return false if we have no information. */ | |
246 | static bool | |
247 | pseudo_regno_single_word_and_live_p (int regno) | |
248 | { | |
249 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
250 | ira_object_t obj; | |
251 | ||
252 | if (a == NULL) | |
253 | return false; | |
254 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
255 | return false; | |
256 | ||
257 | obj = ALLOCNO_OBJECT (a, 0); | |
258 | ||
259 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
260 | } | |
261 | ||
b4f5e198 | 262 | /* Mark the pseudo register REGNO as live. Update all information about |
263 | live ranges and register pressure. */ | |
47dd2e78 | 264 | static void |
b4f5e198 | 265 | mark_pseudo_regno_live (int regno) |
47dd2e78 | 266 | { |
b4f5e198 | 267 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
66d9a7b9 | 268 | enum reg_class pclass; |
be18556f | 269 | int i, n, nregs; |
47dd2e78 | 270 | |
b4f5e198 | 271 | if (a == NULL) |
272 | return; | |
47dd2e78 | 273 | |
b4f5e198 | 274 | /* Invalidate because it is referenced. */ |
275 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
47dd2e78 | 276 | |
be18556f | 277 | n = ALLOCNO_NUM_OBJECTS (a); |
66d9a7b9 | 278 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
279 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
be18556f | 280 | if (n > 1) |
281 | { | |
282 | /* We track every subobject separately. */ | |
283 | gcc_assert (nregs == n); | |
284 | nregs = 1; | |
285 | } | |
286 | ||
287 | for (i = 0; i < n; i++) | |
288 | { | |
289 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
66d9a7b9 | 290 | |
be18556f | 291 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
292 | continue; | |
293 | ||
66d9a7b9 | 294 | inc_register_pressure (pclass, nregs); |
be18556f | 295 | make_object_born (obj); |
296 | } | |
297 | } | |
298 | ||
299 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
300 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
301 | indicates the low part. */ | |
302 | static void | |
303 | mark_pseudo_regno_subword_live (int regno, int subword) | |
304 | { | |
305 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
342f23d2 | 306 | int n; |
66d9a7b9 | 307 | enum reg_class pclass; |
be18556f | 308 | ira_object_t obj; |
309 | ||
310 | if (a == NULL) | |
b4f5e198 | 311 | return; |
312 | ||
be18556f | 313 | /* Invalidate because it is referenced. */ |
314 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
315 | ||
316 | n = ALLOCNO_NUM_OBJECTS (a); | |
317 | if (n == 1) | |
318 | { | |
319 | mark_pseudo_regno_live (regno); | |
320 | return; | |
321 | } | |
322 | ||
66d9a7b9 | 323 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
342f23d2 | 324 | gcc_assert |
325 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
be18556f | 326 | obj = ALLOCNO_OBJECT (a, subword); |
327 | ||
328 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
329 | return; | |
330 | ||
342f23d2 | 331 | inc_register_pressure (pclass, 1); |
be18556f | 332 | make_object_born (obj); |
b4f5e198 | 333 | } |
334 | ||
be18556f | 335 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
336 | this register, record how many consecutive hardware registers it | |
337 | actually needs. */ | |
b4f5e198 | 338 | static void |
339 | mark_hard_reg_live (rtx reg) | |
340 | { | |
341 | int regno = REGNO (reg); | |
342 | ||
343 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
47dd2e78 | 344 | { |
345 | int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
66d9a7b9 | 346 | enum reg_class aclass, pclass; |
47dd2e78 | 347 | |
348 | while (regno < last) | |
349 | { | |
350 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
351 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
352 | { | |
66d9a7b9 | 353 | aclass = ira_hard_regno_allocno_class[regno]; |
354 | pclass = ira_pressure_class_translate[aclass]; | |
355 | inc_register_pressure (pclass, 1); | |
b4f5e198 | 356 | make_hard_regno_born (regno); |
47dd2e78 | 357 | } |
358 | regno++; | |
359 | } | |
360 | } | |
361 | } | |
362 | ||
044621b2 | 363 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
364 | register number; ORIG_REG is the access in the insn, which may be a | |
365 | subreg. */ | |
366 | static void | |
367 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
368 | { | |
369 | if (df_read_modify_subreg_p (orig_reg)) | |
370 | { | |
371 | mark_pseudo_regno_subword_live (regno, | |
372 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
373 | } | |
374 | else | |
375 | mark_pseudo_regno_live (regno); | |
376 | } | |
377 | ||
793e7497 | 378 | /* Mark the register referenced by use or def REF as live. */ |
379 | static void | |
ed6e85ae | 380 | mark_ref_live (df_ref ref) |
47dd2e78 | 381 | { |
be18556f | 382 | rtx reg = DF_REF_REG (ref); |
383 | rtx orig_reg = reg; | |
793e7497 | 384 | |
793e7497 | 385 | if (GET_CODE (reg) == SUBREG) |
386 | reg = SUBREG_REG (reg); | |
be18556f | 387 | |
b4f5e198 | 388 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
044621b2 | 389 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
b4f5e198 | 390 | else |
391 | mark_hard_reg_live (reg); | |
47dd2e78 | 392 | } |
393 | ||
b4f5e198 | 394 | /* Mark the pseudo register REGNO as dead. Update all information about |
395 | live ranges and register pressure. */ | |
47dd2e78 | 396 | static void |
b4f5e198 | 397 | mark_pseudo_regno_dead (int regno) |
47dd2e78 | 398 | { |
b4f5e198 | 399 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
be18556f | 400 | int n, i, nregs; |
b4f5e198 | 401 | enum reg_class cl; |
47dd2e78 | 402 | |
b4f5e198 | 403 | if (a == NULL) |
404 | return; | |
47dd2e78 | 405 | |
b4f5e198 | 406 | /* Invalidate because it is referenced. */ |
407 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
47dd2e78 | 408 | |
be18556f | 409 | n = ALLOCNO_NUM_OBJECTS (a); |
66d9a7b9 | 410 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
411 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
be18556f | 412 | if (n > 1) |
413 | { | |
414 | /* We track every subobject separately. */ | |
415 | gcc_assert (nregs == n); | |
416 | nregs = 1; | |
417 | } | |
418 | for (i = 0; i < n; i++) | |
419 | { | |
420 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
421 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
422 | continue; | |
423 | ||
424 | dec_register_pressure (cl, nregs); | |
425 | make_object_dead (obj); | |
426 | } | |
427 | } | |
428 | ||
429 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
430 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
431 | static void | |
432 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
433 | { | |
434 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
342f23d2 | 435 | int n; |
be18556f | 436 | enum reg_class cl; |
437 | ira_object_t obj; | |
438 | ||
439 | if (a == NULL) | |
440 | return; | |
441 | ||
442 | /* Invalidate because it is referenced. */ | |
443 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
444 | ||
445 | n = ALLOCNO_NUM_OBJECTS (a); | |
446 | if (n == 1) | |
447 | /* The allocno as a whole doesn't die in this case. */ | |
b4f5e198 | 448 | return; |
449 | ||
66d9a7b9 | 450 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
342f23d2 | 451 | gcc_assert |
452 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
be18556f | 453 | |
454 | obj = ALLOCNO_OBJECT (a, subword); | |
455 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
456 | return; | |
b4f5e198 | 457 | |
be18556f | 458 | dec_register_pressure (cl, 1); |
459 | make_object_dead (obj); | |
b4f5e198 | 460 | } |
461 | ||
be18556f | 462 | /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
463 | register. */ | |
b4f5e198 | 464 | static void |
465 | mark_hard_reg_dead (rtx reg) | |
466 | { | |
467 | int regno = REGNO (reg); | |
468 | ||
469 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
47dd2e78 | 470 | { |
471 | int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
66d9a7b9 | 472 | enum reg_class aclass, pclass; |
47dd2e78 | 473 | |
474 | while (regno < last) | |
475 | { | |
476 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
477 | { | |
66d9a7b9 | 478 | aclass = ira_hard_regno_allocno_class[regno]; |
479 | pclass = ira_pressure_class_translate[aclass]; | |
480 | dec_register_pressure (pclass, 1); | |
b4f5e198 | 481 | make_hard_regno_dead (regno); |
47dd2e78 | 482 | } |
483 | regno++; | |
484 | } | |
485 | } | |
486 | } | |
487 | ||
044621b2 | 488 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
489 | register number; ORIG_REG is the access in the insn, which may be a | |
490 | subreg. */ | |
491 | static void | |
492 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
493 | { | |
494 | if (df_read_modify_subreg_p (orig_reg)) | |
495 | { | |
496 | mark_pseudo_regno_subword_dead (regno, | |
497 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
498 | } | |
499 | else | |
500 | mark_pseudo_regno_dead (regno); | |
501 | } | |
502 | ||
793e7497 | 503 | /* Mark the register referenced by definition DEF as dead, if the |
504 | definition is a total one. */ | |
505 | static void | |
ed6e85ae | 506 | mark_ref_dead (df_ref def) |
793e7497 | 507 | { |
be18556f | 508 | rtx reg = DF_REF_REG (def); |
509 | rtx orig_reg = reg; | |
793e7497 | 510 | |
be18556f | 511 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
793e7497 | 512 | return; |
513 | ||
793e7497 | 514 | if (GET_CODE (reg) == SUBREG) |
515 | reg = SUBREG_REG (reg); | |
be18556f | 516 | |
517 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
518 | && (GET_CODE (orig_reg) != SUBREG | |
519 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
520 | || !df_read_modify_subreg_p (orig_reg))) | |
521 | return; | |
522 | ||
b4f5e198 | 523 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
044621b2 | 524 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
b4f5e198 | 525 | else |
526 | mark_hard_reg_dead (reg); | |
793e7497 | 527 | } |
528 | ||
044621b2 | 529 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
530 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
9d75589a | 531 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
044621b2 | 532 | Advance the current program point before making the conflict if |
533 | ADVANCE_P. Return TRUE if we will need to advance the current | |
534 | program point. */ | |
793e7497 | 535 | static bool |
044621b2 | 536 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
537 | bool advance_p) | |
793e7497 | 538 | { |
044621b2 | 539 | rtx orig_reg = reg; |
7173d4d0 | 540 | ira_allocno_t a; |
793e7497 | 541 | |
7173d4d0 | 542 | if (GET_CODE (reg) == SUBREG) |
543 | reg = SUBREG_REG (reg); | |
48e1416a | 544 | |
7173d4d0 | 545 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
546 | return advance_p; | |
48e1416a | 547 | |
7173d4d0 | 548 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
66d9a7b9 | 549 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
7173d4d0 | 550 | return advance_p; |
793e7497 | 551 | |
7173d4d0 | 552 | if (advance_p) |
553 | curr_point++; | |
793e7497 | 554 | |
044621b2 | 555 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
556 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
557 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
558 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
7173d4d0 | 559 | |
560 | return false; | |
561 | } | |
793e7497 | 562 | |
7173d4d0 | 563 | /* Check and make if necessary conflicts for pseudo DREG of class |
564 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
9d75589a | 565 | ORIG_DREG is the rtx actually accessed, it may be identical to |
044621b2 | 566 | DREG or a subreg of it. Advance the current program point before |
567 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
568 | advance the current program point. */ | |
7173d4d0 | 569 | static bool |
044621b2 | 570 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
571 | enum reg_class def_cl, int use, | |
572 | enum reg_class use_cl, bool advance_p) | |
7173d4d0 | 573 | { |
574 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
575 | return advance_p; | |
48e1416a | 576 | |
7173d4d0 | 577 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
044621b2 | 578 | use_cl, dreg, orig_dreg, advance_p); |
579 | ||
7173d4d0 | 580 | /* Reload may end up swapping commutative operands, so you |
581 | have to take both orderings into account. The | |
582 | constraints for the two operands can be completely | |
583 | different. (Indeed, if the constraints for the two | |
584 | operands are the same for all alternatives, there's no | |
585 | point marking them as commutative.) */ | |
e91a9c3f | 586 | if (use < recog_data.n_operands - 1 |
7173d4d0 | 587 | && recog_data.constraints[use][0] == '%') |
588 | advance_p | |
589 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
044621b2 | 590 | use_cl, dreg, orig_dreg, advance_p); |
7173d4d0 | 591 | if (use >= 1 |
592 | && recog_data.constraints[use - 1][0] == '%') | |
593 | advance_p | |
594 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
044621b2 | 595 | use_cl, dreg, orig_dreg, advance_p); |
7173d4d0 | 596 | return advance_p; |
597 | } | |
598 | ||
599 | /* Check and make if necessary conflicts for definition DEF of class | |
600 | DEF_CL of the current insn with input operands. Process only | |
601 | constraints of alternative ALT. */ | |
602 | static void | |
603 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
604 | { | |
605 | int use, use_match; | |
606 | ira_allocno_t a; | |
607 | enum reg_class use_cl, acl; | |
608 | bool advance_p; | |
609 | rtx dreg = recog_data.operand[def]; | |
044621b2 | 610 | rtx orig_dreg = dreg; |
48e1416a | 611 | |
7173d4d0 | 612 | if (def_cl == NO_REGS) |
613 | return; | |
48e1416a | 614 | |
7173d4d0 | 615 | if (GET_CODE (dreg) == SUBREG) |
616 | dreg = SUBREG_REG (dreg); | |
48e1416a | 617 | |
7173d4d0 | 618 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
619 | return; | |
48e1416a | 620 | |
7173d4d0 | 621 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
66d9a7b9 | 622 | acl = ALLOCNO_CLASS (a); |
7173d4d0 | 623 | if (! reg_classes_intersect_p (acl, def_cl)) |
624 | return; | |
48e1416a | 625 | |
7173d4d0 | 626 | advance_p = true; |
48e1416a | 627 | |
7173d4d0 | 628 | for (use = 0; use < recog_data.n_operands; use++) |
629 | { | |
d09294c0 | 630 | int alt1; |
631 | ||
7173d4d0 | 632 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
c2b66149 | 633 | continue; |
48e1416a | 634 | |
7173d4d0 | 635 | if (recog_op_alt[use][alt].anything_ok) |
636 | use_cl = ALL_REGS; | |
793e7497 | 637 | else |
7173d4d0 | 638 | use_cl = recog_op_alt[use][alt].cl; |
48e1416a | 639 | |
d09294c0 | 640 | /* If there's any alternative that allows USE to match DEF, do not |
641 | record a conflict. If that causes us to create an invalid | |
be18556f | 642 | instruction due to the earlyclobber, reload must fix it up. */ |
d09294c0 | 643 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
644 | if (recog_op_alt[use][alt1].matches == def | |
645 | || (use < recog_data.n_operands - 1 | |
646 | && recog_data.constraints[use][0] == '%' | |
647 | && recog_op_alt[use + 1][alt1].matches == def) | |
648 | || (use >= 1 | |
649 | && recog_data.constraints[use - 1][0] == '%' | |
650 | && recog_op_alt[use - 1][alt1].matches == def)) | |
651 | break; | |
652 | ||
653 | if (alt1 < recog_data.n_alternatives) | |
654 | continue; | |
655 | ||
044621b2 | 656 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
657 | use, use_cl, advance_p); | |
48e1416a | 658 | |
7173d4d0 | 659 | if ((use_match = recog_op_alt[use][alt].matches) >= 0) |
660 | { | |
661 | if (use_match == def) | |
c2b66149 | 662 | continue; |
48e1416a | 663 | |
7173d4d0 | 664 | if (recog_op_alt[use_match][alt].anything_ok) |
665 | use_cl = ALL_REGS; | |
666 | else | |
667 | use_cl = recog_op_alt[use_match][alt].cl; | |
044621b2 | 668 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
669 | use, use_cl, advance_p); | |
7173d4d0 | 670 | } |
793e7497 | 671 | } |
7173d4d0 | 672 | } |
673 | ||
674 | /* Make conflicts of early clobber pseudo registers of the current | |
675 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
676 | checking classes of the constraints and pseudos because otherwise | |
677 | significant code degradation is possible for some targets. */ | |
678 | static void | |
679 | make_early_clobber_and_input_conflicts (void) | |
680 | { | |
681 | int alt; | |
682 | int def, def_match; | |
683 | enum reg_class def_cl; | |
684 | ||
685 | for (alt = 0; alt < recog_data.n_alternatives; alt++) | |
686 | for (def = 0; def < recog_data.n_operands; def++) | |
687 | { | |
688 | def_cl = NO_REGS; | |
689 | if (recog_op_alt[def][alt].earlyclobber) | |
690 | { | |
691 | if (recog_op_alt[def][alt].anything_ok) | |
692 | def_cl = ALL_REGS; | |
693 | else | |
694 | def_cl = recog_op_alt[def][alt].cl; | |
695 | check_and_make_def_conflict (alt, def, def_cl); | |
696 | } | |
697 | if ((def_match = recog_op_alt[def][alt].matches) >= 0 | |
698 | && (recog_op_alt[def_match][alt].earlyclobber | |
699 | || recog_op_alt[def][alt].earlyclobber)) | |
700 | { | |
701 | if (recog_op_alt[def_match][alt].anything_ok) | |
702 | def_cl = ALL_REGS; | |
703 | else | |
704 | def_cl = recog_op_alt[def_match][alt].cl; | |
705 | check_and_make_def_conflict (alt, def, def_cl); | |
706 | } | |
707 | } | |
708 | } | |
709 | ||
710 | /* Mark early clobber hard registers of the current INSN as live (if | |
711 | LIVE_P) or dead. Return true if there are such registers. */ | |
712 | static bool | |
713 | mark_hard_reg_early_clobbers (rtx insn, bool live_p) | |
714 | { | |
715 | df_ref *def_rec; | |
716 | bool set_p = false; | |
793e7497 | 717 | |
718 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
719 | if (DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MUST_CLOBBER)) | |
720 | { | |
721 | rtx dreg = DF_REF_REG (*def_rec); | |
48e1416a | 722 | |
793e7497 | 723 | if (GET_CODE (dreg) == SUBREG) |
724 | dreg = SUBREG_REG (dreg); | |
725 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
726 | continue; | |
727 | ||
728 | /* Hard register clobbers are believed to be early clobber | |
729 | because there is no way to say that non-operand hard | |
48e1416a | 730 | register clobbers are not early ones. */ |
793e7497 | 731 | if (live_p) |
732 | mark_ref_live (*def_rec); | |
733 | else | |
734 | mark_ref_dead (*def_rec); | |
735 | set_p = true; | |
736 | } | |
737 | ||
738 | return set_p; | |
739 | } | |
740 | ||
47dd2e78 | 741 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
742 | it is so, the function returns the class of the hard register. | |
743 | Otherwise it returns NO_REGS. */ | |
744 | static enum reg_class | |
745 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
746 | { | |
34347cd4 | 747 | int curr_alt, c; |
748 | bool ignore_p; | |
47dd2e78 | 749 | enum reg_class cl, next_cl; |
47dd2e78 | 750 | |
751 | cl = NO_REGS; | |
34347cd4 | 752 | for (ignore_p = false, curr_alt = 0; |
47dd2e78 | 753 | (c = *constraints); |
754 | constraints += CONSTRAINT_LEN (c, constraints)) | |
34347cd4 | 755 | if (c == '#' || !recog_data.alternative_enabled_p[curr_alt]) |
47dd2e78 | 756 | ignore_p = true; |
757 | else if (c == ',') | |
34347cd4 | 758 | { |
759 | curr_alt++; | |
760 | ignore_p = false; | |
761 | } | |
47dd2e78 | 762 | else if (! ignore_p) |
763 | switch (c) | |
764 | { | |
765 | case ' ': | |
766 | case '\t': | |
767 | case '=': | |
768 | case '+': | |
769 | case '*': | |
770 | case '&': | |
771 | case '%': | |
772 | case '!': | |
773 | case '?': | |
774 | break; | |
775 | case 'i': | |
776 | if (CONSTANT_P (op) | |
777 | || (equiv_const != NULL_RTX && CONSTANT_P (equiv_const))) | |
778 | return NO_REGS; | |
779 | break; | |
780 | ||
781 | case 'n': | |
971ba038 | 782 | if (CONST_INT_P (op) |
78f1962f | 783 | || CONST_DOUBLE_AS_INT_P (op) |
47dd2e78 | 784 | || (equiv_const != NULL_RTX |
971ba038 | 785 | && (CONST_INT_P (equiv_const) |
78f1962f | 786 | || CONST_DOUBLE_AS_INT_P (equiv_const)))) |
47dd2e78 | 787 | return NO_REGS; |
788 | break; | |
48e1416a | 789 | |
47dd2e78 | 790 | case 's': |
78f1962f | 791 | if ((CONSTANT_P (op) |
792 | && !CONST_INT_P (op) | |
793 | && !CONST_DOUBLE_AS_INT_P (op)) | |
47dd2e78 | 794 | || (equiv_const != NULL_RTX |
795 | && CONSTANT_P (equiv_const) | |
971ba038 | 796 | && !CONST_INT_P (equiv_const) |
78f1962f | 797 | && !CONST_DOUBLE_AS_INT_P (equiv_const))) |
47dd2e78 | 798 | return NO_REGS; |
799 | break; | |
48e1416a | 800 | |
47dd2e78 | 801 | case 'I': |
802 | case 'J': | |
803 | case 'K': | |
804 | case 'L': | |
805 | case 'M': | |
806 | case 'N': | |
807 | case 'O': | |
808 | case 'P': | |
971ba038 | 809 | if ((CONST_INT_P (op) |
47dd2e78 | 810 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, constraints)) |
811 | || (equiv_const != NULL_RTX | |
971ba038 | 812 | && CONST_INT_P (equiv_const) |
47dd2e78 | 813 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (equiv_const), |
814 | c, constraints))) | |
815 | return NO_REGS; | |
816 | break; | |
48e1416a | 817 | |
47dd2e78 | 818 | case 'E': |
819 | case 'F': | |
78f1962f | 820 | if (CONST_DOUBLE_AS_FLOAT_P (op) |
47dd2e78 | 821 | || (GET_CODE (op) == CONST_VECTOR |
822 | && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT) | |
823 | || (equiv_const != NULL_RTX | |
78f1962f | 824 | && (CONST_DOUBLE_AS_FLOAT_P (equiv_const) |
47dd2e78 | 825 | || (GET_CODE (equiv_const) == CONST_VECTOR |
826 | && (GET_MODE_CLASS (GET_MODE (equiv_const)) | |
827 | == MODE_VECTOR_FLOAT))))) | |
828 | return NO_REGS; | |
829 | break; | |
48e1416a | 830 | |
47dd2e78 | 831 | case 'G': |
832 | case 'H': | |
78f1962f | 833 | if ((CONST_DOUBLE_AS_FLOAT_P (op) |
47dd2e78 | 834 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, constraints)) |
835 | || (equiv_const != NULL_RTX | |
78f1962f | 836 | && CONST_DOUBLE_AS_FLOAT_P (equiv_const) |
47dd2e78 | 837 | && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (equiv_const, |
838 | c, constraints))) | |
839 | return NO_REGS; | |
840 | /* ??? what about memory */ | |
841 | case 'r': | |
842 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': | |
843 | case 'h': case 'j': case 'k': case 'l': | |
844 | case 'q': case 't': case 'u': | |
845 | case 'v': case 'w': case 'x': case 'y': case 'z': | |
846 | case 'A': case 'B': case 'C': case 'D': | |
847 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
848 | case 'W': case 'Y': case 'Z': | |
849 | next_cl = (c == 'r' | |
850 | ? GENERAL_REGS | |
851 | : REG_CLASS_FROM_CONSTRAINT (c, constraints)); | |
c259678f | 852 | if (cl == NO_REGS |
853 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
854 | : (ira_class_singleton[cl][GET_MODE (op)] | |
855 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
47dd2e78 | 856 | return NO_REGS; |
857 | cl = next_cl; | |
858 | break; | |
48e1416a | 859 | |
47dd2e78 | 860 | case '0': case '1': case '2': case '3': case '4': |
861 | case '5': case '6': case '7': case '8': case '9': | |
862 | next_cl | |
863 | = single_reg_class (recog_data.constraints[c - '0'], | |
864 | recog_data.operand[c - '0'], NULL_RTX); | |
c259678f | 865 | if (cl == NO_REGS |
866 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
867 | : (ira_class_singleton[cl][GET_MODE (op)] | |
868 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
47dd2e78 | 869 | return NO_REGS; |
870 | cl = next_cl; | |
871 | break; | |
48e1416a | 872 | |
47dd2e78 | 873 | default: |
874 | return NO_REGS; | |
875 | } | |
876 | return cl; | |
877 | } | |
878 | ||
879 | /* The function checks that operand OP_NUM of the current insn can use | |
880 | only one hard register. If it is so, the function returns the | |
881 | class of the hard register. Otherwise it returns NO_REGS. */ | |
882 | static enum reg_class | |
883 | single_reg_operand_class (int op_num) | |
884 | { | |
885 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
886 | return NO_REGS; | |
887 | return single_reg_class (recog_data.constraints[op_num], | |
888 | recog_data.operand[op_num], NULL_RTX); | |
889 | } | |
890 | ||
a7dcf969 | 891 | /* The function sets up hard register set *SET to hard registers which |
892 | might be used by insn reloads because the constraints are too | |
893 | strict. */ | |
894 | void | |
895 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set) | |
896 | { | |
34347cd4 | 897 | int i, curr_alt, c, regno = 0; |
a7dcf969 | 898 | bool ignore_p; |
899 | enum reg_class cl; | |
900 | rtx op; | |
901 | enum machine_mode mode; | |
902 | ||
903 | CLEAR_HARD_REG_SET (*set); | |
904 | for (i = 0; i < recog_data.n_operands; i++) | |
905 | { | |
906 | op = recog_data.operand[i]; | |
907 | ||
908 | if (GET_CODE (op) == SUBREG) | |
909 | op = SUBREG_REG (op); | |
48e1416a | 910 | |
a7dcf969 | 911 | if (GET_CODE (op) == SCRATCH |
912 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
913 | { | |
914 | const char *p = recog_data.constraints[i]; | |
915 | ||
916 | mode = (GET_CODE (op) == SCRATCH | |
917 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
918 | cl = NO_REGS; | |
34347cd4 | 919 | for (ignore_p = false, curr_alt = 0; |
920 | (c = *p); | |
921 | p += CONSTRAINT_LEN (c, p)) | |
922 | if (c == '#' || !recog_data.alternative_enabled_p[curr_alt]) | |
a7dcf969 | 923 | ignore_p = true; |
924 | else if (c == ',') | |
34347cd4 | 925 | { |
926 | curr_alt++; | |
927 | ignore_p = false; | |
928 | } | |
a7dcf969 | 929 | else if (! ignore_p) |
930 | switch (c) | |
931 | { | |
932 | case 'r': | |
933 | case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': | |
934 | case 'h': case 'j': case 'k': case 'l': | |
935 | case 'q': case 't': case 'u': | |
936 | case 'v': case 'w': case 'x': case 'y': case 'z': | |
937 | case 'A': case 'B': case 'C': case 'D': | |
938 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
939 | case 'W': case 'Y': case 'Z': | |
940 | cl = (c == 'r' | |
941 | ? GENERAL_REGS | |
942 | : REG_CLASS_FROM_CONSTRAINT (c, p)); | |
c259678f | 943 | if (cl != NO_REGS) |
944 | { | |
0cc9609c | 945 | /* There is no register pressure problem if all of the |
946 | regs in this class are fixed. */ | |
c259678f | 947 | int regno = ira_class_singleton[cl][mode]; |
948 | if (regno >= 0) | |
949 | add_to_hard_reg_set (set, mode, regno); | |
950 | } | |
a7dcf969 | 951 | break; |
952 | } | |
953 | } | |
954 | } | |
955 | } | |
47dd2e78 | 956 | /* Processes input operands, if IN_P, or output operands otherwise of |
957 | the current insn with FREQ to find allocno which can use only one | |
958 | hard register and makes other currently living allocnos conflicting | |
959 | with the hard register. */ | |
960 | static void | |
961 | process_single_reg_class_operands (bool in_p, int freq) | |
962 | { | |
744d7848 | 963 | int i, regno; |
47dd2e78 | 964 | unsigned int px; |
da7a04f1 | 965 | enum reg_class cl; |
47dd2e78 | 966 | rtx operand; |
967 | ira_allocno_t operand_a, a; | |
968 | ||
969 | for (i = 0; i < recog_data.n_operands; i++) | |
970 | { | |
971 | operand = recog_data.operand[i]; | |
972 | if (in_p && recog_data.operand_type[i] != OP_IN | |
973 | && recog_data.operand_type[i] != OP_INOUT) | |
974 | continue; | |
975 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
976 | && recog_data.operand_type[i] != OP_INOUT) | |
977 | continue; | |
978 | cl = single_reg_operand_class (i); | |
979 | if (cl == NO_REGS) | |
980 | continue; | |
981 | ||
982 | operand_a = NULL; | |
983 | ||
984 | if (GET_CODE (operand) == SUBREG) | |
985 | operand = SUBREG_REG (operand); | |
48e1416a | 986 | |
47dd2e78 | 987 | if (REG_P (operand) |
988 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
989 | { | |
66d9a7b9 | 990 | enum reg_class aclass; |
47dd2e78 | 991 | |
992 | operand_a = ira_curr_regno_allocno_map[regno]; | |
66d9a7b9 | 993 | aclass = ALLOCNO_CLASS (operand_a); |
c259678f | 994 | if (ira_class_subset_p[cl][aclass]) |
47dd2e78 | 995 | { |
744d7848 | 996 | /* View the desired allocation of OPERAND as: |
997 | ||
998 | (REG:YMODE YREGNO), | |
999 | ||
1000 | a simplification of: | |
1001 | ||
1002 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
1003 | enum machine_mode ymode, xmode; | |
1004 | int xregno, yregno; | |
1005 | HOST_WIDE_INT offset; | |
1006 | ||
1007 | xmode = recog_data.operand_mode[i]; | |
c259678f | 1008 | xregno = ira_class_singleton[cl][xmode]; |
1009 | gcc_assert (xregno >= 0); | |
744d7848 | 1010 | ymode = ALLOCNO_MODE (operand_a); |
1011 | offset = subreg_lowpart_offset (ymode, xmode); | |
1012 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
1013 | if (yregno >= 0 | |
66d9a7b9 | 1014 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
744d7848 | 1015 | { |
1016 | int cost; | |
1017 | ||
1018 | ira_allocate_and_set_costs | |
1019 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
66d9a7b9 | 1020 | aclass, 0); |
1021 | ira_init_register_move_cost_if_necessary (xmode); | |
1022 | cost = freq * (in_p | |
1023 | ? ira_register_move_cost[xmode][aclass][cl] | |
1024 | : ira_register_move_cost[xmode][cl][aclass]); | |
744d7848 | 1025 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
66d9a7b9 | 1026 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
744d7848 | 1027 | } |
47dd2e78 | 1028 | } |
1029 | } | |
1030 | ||
be18556f | 1031 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
47dd2e78 | 1032 | { |
be18556f | 1033 | ira_object_t obj = ira_object_id_map[px]; |
1034 | a = OBJECT_ALLOCNO (obj); | |
47dd2e78 | 1035 | if (a != operand_a) |
1036 | { | |
1037 | /* We could increase costs of A instead of making it | |
1038 | conflicting with the hard register. But it works worse | |
1039 | because it will be spilled in reload in anyway. */ | |
ae9587ed | 1040 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
47dd2e78 | 1041 | reg_class_contents[cl]); |
ae9587ed | 1042 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
47dd2e78 | 1043 | reg_class_contents[cl]); |
1044 | } | |
1045 | } | |
1046 | } | |
1047 | } | |
1048 | ||
9f724a58 | 1049 | /* Return true when one of the predecessor edges of BB is marked with |
1050 | EDGE_ABNORMAL_CALL or EDGE_EH. */ | |
1051 | static bool | |
1052 | bb_has_abnormal_call_pred (basic_block bb) | |
1053 | { | |
1054 | edge e; | |
1055 | edge_iterator ei; | |
48e1416a | 1056 | |
9f724a58 | 1057 | FOR_EACH_EDGE (e, ei, bb->preds) |
1058 | { | |
1059 | if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH)) | |
1060 | return true; | |
1061 | } | |
1062 | return false; | |
1063 | } | |
1064 | ||
c8010b80 | 1065 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
1066 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
1067 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
1068 | static rtx | |
1069 | find_call_crossed_cheap_reg (rtx insn) | |
1070 | { | |
1071 | rtx cheap_reg = NULL_RTX; | |
1072 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
1073 | ||
1074 | while (exp != NULL) | |
1075 | { | |
1076 | rtx x = XEXP (exp, 0); | |
1077 | if (GET_CODE (x) == SET) | |
1078 | { | |
1079 | exp = x; | |
1080 | break; | |
1081 | } | |
1082 | exp = XEXP (exp, 1); | |
1083 | } | |
1084 | if (exp != NULL) | |
1085 | { | |
1086 | basic_block bb = BLOCK_FOR_INSN (insn); | |
1087 | rtx reg = SET_SRC (exp); | |
1088 | rtx prev = PREV_INSN (insn); | |
1089 | while (prev && !(INSN_P (prev) | |
1090 | && BLOCK_FOR_INSN (prev) != bb)) | |
1091 | { | |
1092 | if (NONDEBUG_INSN_P (prev)) | |
1093 | { | |
1094 | rtx set = single_set (prev); | |
1095 | ||
1096 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
1097 | { | |
1098 | rtx src = SET_SRC (set); | |
1099 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
1100 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1101 | break; | |
1102 | if (!modified_between_p (src, prev, insn)) | |
1103 | cheap_reg = src; | |
1104 | break; | |
1105 | } | |
1106 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1107 | { | |
1108 | rtx dest = SET_DEST (set); | |
1109 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1110 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1111 | break; | |
1112 | if (!modified_between_p (dest, prev, insn)) | |
1113 | cheap_reg = dest; | |
1114 | break; | |
1115 | } | |
1116 | ||
1117 | if (reg_overlap_mentioned_p (reg, PATTERN (prev))) | |
1118 | break; | |
1119 | } | |
1120 | prev = PREV_INSN (prev); | |
1121 | } | |
1122 | } | |
1123 | return cheap_reg; | |
1124 | } | |
1125 | ||
47dd2e78 | 1126 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1127 | update allocno live ranges, allocno hard register conflicts, | |
1128 | intersected calls, and register pressure info for allocnos for the | |
1129 | basic block for and regions containing the basic block. */ | |
1130 | static void | |
1131 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1132 | { | |
7e03a244 | 1133 | int i, freq; |
47dd2e78 | 1134 | unsigned int j; |
1135 | basic_block bb; | |
1136 | rtx insn; | |
47dd2e78 | 1137 | bitmap_iterator bi; |
7e03a244 | 1138 | bitmap reg_live_out; |
47dd2e78 | 1139 | unsigned int px; |
793e7497 | 1140 | bool set_p; |
47dd2e78 | 1141 | |
1142 | bb = loop_tree_node->bb; | |
1143 | if (bb != NULL) | |
1144 | { | |
66d9a7b9 | 1145 | for (i = 0; i < ira_pressure_classes_num; i++) |
47dd2e78 | 1146 | { |
66d9a7b9 | 1147 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1148 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
47dd2e78 | 1149 | } |
1150 | curr_bb_node = loop_tree_node; | |
0841d295 | 1151 | reg_live_out = df_get_live_out (bb); |
be18556f | 1152 | sparseset_clear (objects_live); |
7e03a244 | 1153 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
47dd2e78 | 1154 | AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); |
1155 | AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
1156 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1157 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1158 | { | |
66d9a7b9 | 1159 | enum reg_class aclass, pclass, cl; |
48e1416a | 1160 | |
66d9a7b9 | 1161 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1162 | pclass = ira_pressure_class_translate[aclass]; | |
14792f4e | 1163 | for (j = 0; |
66d9a7b9 | 1164 | (cl = ira_reg_class_super_classes[pclass][j]) |
14792f4e | 1165 | != LIM_REG_CLASSES; |
1166 | j++) | |
1167 | { | |
66d9a7b9 | 1168 | if (! ira_reg_pressure_class_p[cl]) |
1169 | continue; | |
14792f4e | 1170 | curr_reg_pressure[cl]++; |
1171 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1172 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1173 | ira_assert (curr_reg_pressure[cl] | |
1072fecf | 1174 | <= ira_class_hard_regs_num[cl]); |
14792f4e | 1175 | } |
47dd2e78 | 1176 | } |
7e03a244 | 1177 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
b4f5e198 | 1178 | mark_pseudo_regno_live (j); |
48e1416a | 1179 | |
7e03a244 | 1180 | freq = REG_FREQ_FROM_BB (bb); |
1181 | if (freq == 0) | |
1182 | freq = 1; | |
1183 | ||
df07a54c | 1184 | /* Invalidate all allocno_saved_at_call entries. */ |
1185 | last_call_num++; | |
1186 | ||
47dd2e78 | 1187 | /* Scan the code of this basic block, noting which allocnos and |
7e03a244 | 1188 | hard regs are born or die. |
1189 | ||
1190 | Note that this loop treats uninitialized values as live until | |
1191 | the beginning of the block. For example, if an instruction | |
1192 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1193 | set, FOO will remain live until the beginning of the block. | |
1194 | Likewise if FOO is not set at all. This is unnecessarily | |
1195 | pessimistic, but it probably doesn't matter much in practice. */ | |
1196 | FOR_BB_INSNS_REVERSE (bb, insn) | |
47dd2e78 | 1197 | { |
ed6e85ae | 1198 | df_ref *def_rec, *use_rec; |
7e03a244 | 1199 | bool call_p; |
48e1416a | 1200 | |
9845d120 | 1201 | if (!NONDEBUG_INSN_P (insn)) |
47dd2e78 | 1202 | continue; |
48e1416a | 1203 | |
47dd2e78 | 1204 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1205 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
9f8ac546 | 1206 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
47dd2e78 | 1207 | curr_point); |
1208 | ||
7e03a244 | 1209 | /* Mark each defined value as live. We need to do this for |
1210 | unused values because they still conflict with quantities | |
1211 | that are live at the time of the definition. | |
1212 | ||
1213 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1214 | references represent the effect of the called function | |
1215 | on a call-clobbered register. Marking the register as | |
1216 | live would stop us from allocating it to a call-crossing | |
1217 | allocno. */ | |
1218 | call_p = CALL_P (insn); | |
1219 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
1220 | if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER)) | |
1221 | mark_ref_live (*def_rec); | |
1222 | ||
1223 | /* If INSN has multiple outputs, then any value used in one | |
1224 | of the outputs conflicts with the other outputs. Model this | |
1225 | by making the used value live during the output phase. | |
1226 | ||
1227 | It is unsafe to use !single_set here since it will ignore | |
1228 | an unused output. Just because an output is unused does | |
1229 | not mean the compiler can assume the side effect will not | |
1230 | occur. Consider if ALLOCNO appears in the address of an | |
1231 | output and we reload the output. If we allocate ALLOCNO | |
1232 | to the same hard register as an unused output we could | |
1233 | set the hard register before the output reload insn. */ | |
1234 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
1235 | for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
1236 | { | |
1237 | int i; | |
1238 | rtx reg; | |
1239 | ||
1240 | reg = DF_REF_REG (*use_rec); | |
1241 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
1242 | { | |
1243 | rtx set; | |
1244 | ||
1245 | set = XVECEXP (PATTERN (insn), 0, i); | |
1246 | if (GET_CODE (set) == SET | |
1247 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1248 | { | |
1249 | /* After the previous loop, this is a no-op if | |
1250 | REG is contained within SET_DEST (SET). */ | |
1251 | mark_ref_live (*use_rec); | |
1252 | break; | |
1253 | } | |
1254 | } | |
1255 | } | |
48e1416a | 1256 | |
47dd2e78 | 1257 | extract_insn (insn); |
793e7497 | 1258 | preprocess_constraints (); |
7e03a244 | 1259 | process_single_reg_class_operands (false, freq); |
48e1416a | 1260 | |
7e03a244 | 1261 | /* See which defined values die here. */ |
1262 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
1263 | if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER)) | |
1264 | mark_ref_dead (*def_rec); | |
47dd2e78 | 1265 | |
7e03a244 | 1266 | if (call_p) |
47dd2e78 | 1267 | { |
c8010b80 | 1268 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1269 | there, try to find a pseudo that is live across the call but | |
1270 | can be cheaply reconstructed from the return value. */ | |
1271 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1272 | if (cheap_reg != NULL_RTX) | |
1273 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1274 | ||
df07a54c | 1275 | last_call_num++; |
be18556f | 1276 | sparseset_clear (allocnos_processed); |
7e03a244 | 1277 | /* The current set of live allocnos are live across the call. */ |
be18556f | 1278 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
47dd2e78 | 1279 | { |
be18556f | 1280 | ira_object_t obj = ira_object_id_map[i]; |
1281 | ira_allocno_t a = OBJECT_ALLOCNO (obj); | |
1282 | int num = ALLOCNO_NUM (a); | |
48e1416a | 1283 | |
d6a421d5 | 1284 | /* Don't allocate allocnos that cross setjmps or any |
1285 | call, if this function receives a nonlocal | |
1286 | goto. */ | |
1287 | if (cfun->has_nonlocal_label | |
1288 | || find_reg_note (insn, REG_SETJMP, | |
1289 | NULL_RTX) != NULL_RTX) | |
47dd2e78 | 1290 | { |
ae9587ed | 1291 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1292 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
47dd2e78 | 1293 | } |
cab55469 | 1294 | if (can_throw_internal (insn)) |
1295 | { | |
ae9587ed | 1296 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
cab55469 | 1297 | call_used_reg_set); |
be18556f | 1298 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
1299 | call_used_reg_set); | |
cab55469 | 1300 | } |
be18556f | 1301 | |
1302 | if (sparseset_bit_p (allocnos_processed, num)) | |
1303 | continue; | |
1304 | sparseset_set_bit (allocnos_processed, num); | |
1305 | ||
1306 | if (allocno_saved_at_call[num] != last_call_num) | |
1307 | /* Here we are mimicking caller-save.c behaviour | |
1308 | which does not save hard register at a call if | |
1309 | it was saved on previous call in the same basic | |
1310 | block and the hard register was not mentioned | |
1311 | between the two calls. */ | |
1312 | ALLOCNO_CALL_FREQ (a) += freq; | |
1313 | /* Mark it as saved at the next call. */ | |
1314 | allocno_saved_at_call[num] = last_call_num + 1; | |
1315 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
c8010b80 | 1316 | if (cheap_reg != NULL_RTX |
1317 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1318 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
47dd2e78 | 1319 | } |
1320 | } | |
48e1416a | 1321 | |
7173d4d0 | 1322 | make_early_clobber_and_input_conflicts (); |
1323 | ||
7e03a244 | 1324 | curr_point++; |
1325 | ||
1326 | /* Mark each used value as live. */ | |
1327 | for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
1328 | mark_ref_live (*use_rec); | |
1329 | ||
7e03a244 | 1330 | process_single_reg_class_operands (true, freq); |
48e1416a | 1331 | |
7173d4d0 | 1332 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1333 | ||
793e7497 | 1334 | if (set_p) |
1335 | { | |
7173d4d0 | 1336 | mark_hard_reg_early_clobbers (insn, false); |
793e7497 | 1337 | |
7173d4d0 | 1338 | /* Mark each hard reg as live again. For example, a |
793e7497 | 1339 | hard register can be in clobber and in an insn |
1340 | input. */ | |
1341 | for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
7173d4d0 | 1342 | { |
1343 | rtx ureg = DF_REF_REG (*use_rec); | |
48e1416a | 1344 | |
7173d4d0 | 1345 | if (GET_CODE (ureg) == SUBREG) |
1346 | ureg = SUBREG_REG (ureg); | |
1347 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1348 | continue; | |
48e1416a | 1349 | |
7173d4d0 | 1350 | mark_ref_live (*use_rec); |
1351 | } | |
793e7497 | 1352 | } |
47dd2e78 | 1353 | |
47dd2e78 | 1354 | curr_point++; |
1355 | } | |
7e03a244 | 1356 | |
fee75d9b | 1357 | #ifdef EH_RETURN_DATA_REGNO |
1358 | if (bb_has_eh_pred (bb)) | |
1359 | for (j = 0; ; ++j) | |
1360 | { | |
1361 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1362 | if (regno == INVALID_REGNUM) | |
1363 | break; | |
b4f5e198 | 1364 | make_hard_regno_born (regno); |
fee75d9b | 1365 | } |
1366 | #endif | |
1367 | ||
7e03a244 | 1368 | /* Allocnos can't go in stack regs at the start of a basic block |
1369 | that is reached by an abnormal edge. Likewise for call | |
1370 | clobbered regs, because caller-save, fixup_abnormal_edges and | |
1371 | possibly the table driven EH machinery are not quite ready to | |
1372 | handle such allocnos live across such edges. */ | |
fee75d9b | 1373 | if (bb_has_abnormal_pred (bb)) |
7e03a244 | 1374 | { |
1375 | #ifdef STACK_REGS | |
be18556f | 1376 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
7e03a244 | 1377 | { |
be18556f | 1378 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
66d9a7b9 | 1379 | |
be18556f | 1380 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1381 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
7e03a244 | 1382 | } |
1383 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
b4f5e198 | 1384 | make_hard_regno_born (px); |
7e03a244 | 1385 | #endif |
1386 | /* No need to record conflicts for call clobbered regs if we | |
1387 | have nonlocal labels around, as we don't ever try to | |
1388 | allocate such regs in this case. */ | |
9f724a58 | 1389 | if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb)) |
7e03a244 | 1390 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
1391 | if (call_used_regs[px]) | |
b4f5e198 | 1392 | make_hard_regno_born (px); |
7e03a244 | 1393 | } |
1394 | ||
be18556f | 1395 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1396 | make_object_dead (ira_object_id_map[i]); | |
47dd2e78 | 1397 | |
1398 | curr_point++; | |
1399 | ||
1400 | } | |
1401 | /* Propagate register pressure to upper loop tree nodes: */ | |
1402 | if (loop_tree_node != ira_loop_tree_root) | |
66d9a7b9 | 1403 | for (i = 0; i < ira_pressure_classes_num; i++) |
47dd2e78 | 1404 | { |
66d9a7b9 | 1405 | enum reg_class pclass; |
47dd2e78 | 1406 | |
66d9a7b9 | 1407 | pclass = ira_pressure_classes[i]; |
1408 | if (loop_tree_node->reg_pressure[pclass] | |
1409 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1410 | loop_tree_node->parent->reg_pressure[pclass] | |
1411 | = loop_tree_node->reg_pressure[pclass]; | |
47dd2e78 | 1412 | } |
1413 | } | |
1414 | ||
1415 | /* Create and set up IRA_START_POINT_RANGES and | |
1416 | IRA_FINISH_POINT_RANGES. */ | |
1417 | static void | |
1418 | create_start_finish_chains (void) | |
1419 | { | |
be18556f | 1420 | ira_object_t obj; |
1421 | ira_object_iterator oi; | |
fbff82f4 | 1422 | live_range_t r; |
47dd2e78 | 1423 | |
1424 | ira_start_point_ranges | |
be18556f | 1425 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1426 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
47dd2e78 | 1427 | ira_finish_point_ranges |
be18556f | 1428 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1429 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1430 | FOR_EACH_OBJECT (obj, oi) | |
1431 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1432 | { | |
1433 | r->start_next = ira_start_point_ranges[r->start]; | |
1434 | ira_start_point_ranges[r->start] = r; | |
1435 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
47dd2e78 | 1436 | ira_finish_point_ranges[r->finish] = r; |
be18556f | 1437 | } |
47dd2e78 | 1438 | } |
1439 | ||
1440 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1441 | new live ranges and program points were added as a result if new | |
1442 | insn generation. */ | |
1443 | void | |
1444 | ira_rebuild_start_finish_chains (void) | |
1445 | { | |
1446 | ira_free (ira_finish_point_ranges); | |
1447 | ira_free (ira_start_point_ranges); | |
1448 | create_start_finish_chains (); | |
1449 | } | |
1450 | ||
7f36fbdf | 1451 | /* Compress allocno live ranges by removing program points where |
1452 | nothing happens. */ | |
1453 | static void | |
1454 | remove_some_program_points_and_update_live_ranges (void) | |
1455 | { | |
1456 | unsigned i; | |
1457 | int n; | |
1458 | int *map; | |
9d53e372 | 1459 | ira_object_t obj; |
1460 | ira_object_iterator oi; | |
d068a2f3 | 1461 | live_range_t r, prev_r, next_r; |
82cc92bf | 1462 | sbitmap born_or_dead, born, dead; |
1463 | sbitmap_iterator sbi; | |
1464 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1465 | ||
1466 | born = sbitmap_alloc (ira_max_point); | |
1467 | dead = sbitmap_alloc (ira_max_point); | |
1468 | sbitmap_zero (born); | |
1469 | sbitmap_zero (dead); | |
9d53e372 | 1470 | FOR_EACH_OBJECT (obj, oi) |
1471 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1472 | { | |
1473 | ira_assert (r->start <= r->finish); | |
82cc92bf | 1474 | SET_BIT (born, r->start); |
1475 | SET_BIT (dead, r->finish); | |
9d53e372 | 1476 | } |
1477 | ||
82cc92bf | 1478 | born_or_dead = sbitmap_alloc (ira_max_point); |
1479 | sbitmap_a_or_b (born_or_dead, born, dead); | |
7f36fbdf | 1480 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
82cc92bf | 1481 | n = -1; |
1482 | prev_born_p = prev_dead_p = false; | |
1483 | EXECUTE_IF_SET_IN_SBITMAP (born_or_dead, 0, i, sbi) | |
7f36fbdf | 1484 | { |
82cc92bf | 1485 | born_p = TEST_BIT (born, i); |
1486 | dead_p = TEST_BIT (dead, i); | |
1487 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) | |
1488 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1489 | map[i] = n; | |
1490 | else | |
1491 | map[i] = ++n; | |
1492 | prev_born_p = born_p; | |
1493 | prev_dead_p = dead_p; | |
7f36fbdf | 1494 | } |
82cc92bf | 1495 | sbitmap_free (born_or_dead); |
1496 | sbitmap_free (born); | |
1497 | sbitmap_free (dead); | |
1498 | n++; | |
7f36fbdf | 1499 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1500 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1501 | ira_max_point, n, 100 * n / ira_max_point); | |
1502 | ira_max_point = n; | |
9d53e372 | 1503 | |
1504 | FOR_EACH_OBJECT (obj, oi) | |
d068a2f3 | 1505 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9d53e372 | 1506 | { |
d068a2f3 | 1507 | next_r = r->next; |
9d53e372 | 1508 | r->start = map[r->start]; |
1509 | r->finish = map[r->finish]; | |
d068a2f3 | 1510 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1511 | { | |
1512 | prev_r = r; | |
1513 | continue; | |
1514 | } | |
1515 | prev_r->start = r->start; | |
1516 | prev_r->next = next_r; | |
1517 | ira_finish_live_range (r); | |
9d53e372 | 1518 | } |
be18556f | 1519 | |
7f36fbdf | 1520 | ira_free (map); |
1521 | } | |
1522 | ||
47dd2e78 | 1523 | /* Print live ranges R to file F. */ |
1524 | void | |
fbff82f4 | 1525 | ira_print_live_range_list (FILE *f, live_range_t r) |
47dd2e78 | 1526 | { |
1527 | for (; r != NULL; r = r->next) | |
1528 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1529 | fprintf (f, "\n"); | |
1530 | } | |
1531 | ||
1532 | /* Print live ranges R to stderr. */ | |
1533 | void | |
fbff82f4 | 1534 | ira_debug_live_range_list (live_range_t r) |
47dd2e78 | 1535 | { |
1536 | ira_print_live_range_list (stderr, r); | |
1537 | } | |
1538 | ||
be18556f | 1539 | /* Print live ranges of object OBJ to file F. */ |
1540 | static void | |
1541 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1542 | { | |
1543 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1544 | } | |
1545 | ||
47dd2e78 | 1546 | /* Print live ranges of allocno A to file F. */ |
1547 | static void | |
1548 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1549 | { | |
be18556f | 1550 | int n = ALLOCNO_NUM_OBJECTS (a); |
1551 | int i; | |
66d9a7b9 | 1552 | |
be18556f | 1553 | for (i = 0; i < n; i++) |
1554 | { | |
1555 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1556 | if (n > 1) | |
1557 | fprintf (f, " [%d]", i); | |
1558 | fprintf (f, "):"); | |
1559 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1560 | } | |
47dd2e78 | 1561 | } |
1562 | ||
1563 | /* Print live ranges of allocno A to stderr. */ | |
1564 | void | |
1565 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1566 | { | |
1567 | print_allocno_live_ranges (stderr, a); | |
1568 | } | |
1569 | ||
1570 | /* Print live ranges of all allocnos to file F. */ | |
1571 | static void | |
1572 | print_live_ranges (FILE *f) | |
1573 | { | |
1574 | ira_allocno_t a; | |
1575 | ira_allocno_iterator ai; | |
1576 | ||
1577 | FOR_EACH_ALLOCNO (a, ai) | |
1578 | print_allocno_live_ranges (f, a); | |
1579 | } | |
1580 | ||
1581 | /* Print live ranges of all allocnos to stderr. */ | |
1582 | void | |
1583 | ira_debug_live_ranges (void) | |
1584 | { | |
1585 | print_live_ranges (stderr); | |
1586 | } | |
1587 | ||
1588 | /* The main entry function creates live ranges, set up | |
be18556f | 1589 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
47dd2e78 | 1590 | calculate register pressure info. */ |
1591 | void | |
1592 | ira_create_allocno_live_ranges (void) | |
1593 | { | |
be18556f | 1594 | objects_live = sparseset_alloc (ira_objects_num); |
1595 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
47dd2e78 | 1596 | curr_point = 0; |
df07a54c | 1597 | last_call_num = 0; |
1598 | allocno_saved_at_call | |
1599 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1600 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
47dd2e78 | 1601 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1602 | process_bb_node_lives); | |
1603 | ira_max_point = curr_point; | |
1604 | create_start_finish_chains (); | |
1605 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1606 | print_live_ranges (ira_dump_file); | |
1607 | /* Clean up. */ | |
df07a54c | 1608 | ira_free (allocno_saved_at_call); |
be18556f | 1609 | sparseset_free (objects_live); |
1610 | sparseset_free (allocnos_processed); | |
47dd2e78 | 1611 | } |
1612 | ||
7f36fbdf | 1613 | /* Compress allocno live ranges. */ |
1614 | void | |
1615 | ira_compress_allocno_live_ranges (void) | |
1616 | { | |
1617 | remove_some_program_points_and_update_live_ranges (); | |
1618 | ira_rebuild_start_finish_chains (); | |
1619 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1620 | { | |
1621 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1622 | print_live_ranges (ira_dump_file); | |
1623 | } | |
1624 | } | |
1625 | ||
47dd2e78 | 1626 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1627 | void | |
1628 | ira_finish_allocno_live_ranges (void) | |
1629 | { | |
1630 | ira_free (ira_finish_point_ranges); | |
1631 | ira_free (ira_start_point_ranges); | |
1632 | } |