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058e97ec | 1 | /* IRA processing allocno lives to build allocno live ranges. |
5624e564 | 2 | Copyright (C) 2006-2015 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
c7131fb2 | 24 | #include "backend.h" |
957060b5 | 25 | #include "target.h" |
058e97ec | 26 | #include "rtl.h" |
957060b5 | 27 | #include "predict.h" |
c7131fb2 | 28 | #include "df.h" |
058e97ec | 29 | #include "tm_p.h" |
058e97ec | 30 | #include "insn-config.h" |
957060b5 AM |
31 | #include "regs.h" |
32 | #include "ira.h" | |
33 | #include "ira-int.h" | |
718f9c0f | 34 | #include "diagnostic-core.h" |
957060b5 AM |
35 | #include "flags.h" |
36 | #include "except.h" | |
058e97ec | 37 | #include "params.h" |
058e97ec | 38 | #include "sparseset.h" |
c7131fb2 | 39 | #include "cfgloop.h" |
058e97ec VM |
40 | |
41 | /* The code in this file is similar to one in global but the code | |
42 | works on the allocno basis and creates live ranges instead of | |
43 | pseudo-register conflicts. */ | |
44 | ||
45 | /* Program points are enumerated by numbers from range | |
46 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
47 | points than insns. Program points are places in the program where | |
48 | liveness info can be changed. In most general case (there are more | |
49 | complicated cases too) some program points correspond to places | |
50 | where input operand dies and other ones correspond to places where | |
51 | output operands are born. */ | |
52 | int ira_max_point; | |
53 | ||
54 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
55 | live ranges with given start/finish point. */ | |
b14151b5 | 56 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec VM |
57 | |
58 | /* Number of the current program point. */ | |
59 | static int curr_point; | |
60 | ||
61 | /* Point where register pressure excess started or -1 if there is no | |
62 | register pressure excess. Excess pressure for a register class at | |
63 | some point means that there are more allocnos of given register | |
64 | class living at the point than number of hard-registers of the | |
1756cb66 VM |
65 | class available for the allocation. It is defined only for |
66 | pressure classes. */ | |
058e97ec VM |
67 | static int high_pressure_start_point[N_REG_CLASSES]; |
68 | ||
ac0ab4f7 BS |
69 | /* Objects live at current point in the scan. */ |
70 | static sparseset objects_live; | |
71 | ||
72 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
73 | multiple times. */ | |
74 | static sparseset allocnos_processed; | |
058e97ec VM |
75 | |
76 | /* Set of hard regs (except eliminable ones) currently live. */ | |
77 | static HARD_REG_SET hard_regs_live; | |
78 | ||
79 | /* The loop tree node corresponding to the current basic block. */ | |
80 | static ira_loop_tree_node_t curr_bb_node; | |
81 | ||
cb1ca6ac VM |
82 | /* The number of the last processed call. */ |
83 | static int last_call_num; | |
84 | /* The number of last call at which given allocno was saved. */ | |
85 | static int *allocno_saved_at_call; | |
86 | ||
9840b2fa RS |
87 | /* The value of get_preferred_alternatives for the current instruction, |
88 | supplemental to recog_data. */ | |
89 | static alternative_mask preferred_alternatives; | |
90 | ||
ac0ab4f7 BS |
91 | /* Record the birth of hard register REGNO, updating hard_regs_live and |
92 | hard reg conflict information for living allocnos. */ | |
058e97ec | 93 | static void |
3c55880a | 94 | make_hard_regno_born (int regno) |
058e97ec VM |
95 | { |
96 | unsigned int i; | |
058e97ec | 97 | |
3c55880a | 98 | SET_HARD_REG_BIT (hard_regs_live, regno); |
ac0ab4f7 | 99 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 100 | { |
ac0ab4f7 | 101 | ira_object_t obj = ira_object_id_map[i]; |
1756cb66 | 102 | |
a49ae217 BS |
103 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
104 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
058e97ec | 105 | } |
3c55880a BS |
106 | } |
107 | ||
108 | /* Process the death of hard register REGNO. This updates | |
109 | hard_regs_live. */ | |
110 | static void | |
111 | make_hard_regno_dead (int regno) | |
112 | { | |
113 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); | |
114 | } | |
115 | ||
ac0ab4f7 BS |
116 | /* Record the birth of object OBJ. Set a bit for it in objects_live, |
117 | start a new live range for it if necessary and update hard register | |
118 | conflicts. */ | |
3c55880a | 119 | static void |
ac0ab4f7 | 120 | make_object_born (ira_object_t obj) |
3c55880a | 121 | { |
ac0ab4f7 | 122 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
3c55880a | 123 | |
ac0ab4f7 | 124 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
a49ae217 BS |
125 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
126 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); | |
3c55880a | 127 | |
ac0ab4f7 BS |
128 | if (lr == NULL |
129 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
130 | ira_add_live_range_to_object (obj, curr_point, -1); | |
058e97ec VM |
131 | } |
132 | ||
ac0ab4f7 BS |
133 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
134 | associated with object OBJ. */ | |
058e97ec | 135 | static void |
ac0ab4f7 | 136 | update_allocno_pressure_excess_length (ira_object_t obj) |
058e97ec | 137 | { |
ac0ab4f7 | 138 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
7db7ed3c | 139 | int start, i; |
1756cb66 | 140 | enum reg_class aclass, pclass, cl; |
b14151b5 | 141 | live_range_t p; |
058e97ec | 142 | |
1756cb66 VM |
143 | aclass = ALLOCNO_CLASS (a); |
144 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 145 | for (i = 0; |
1756cb66 | 146 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
147 | i++) |
148 | { | |
1756cb66 VM |
149 | if (! ira_reg_pressure_class_p[cl]) |
150 | continue; | |
7db7ed3c VM |
151 | if (high_pressure_start_point[cl] < 0) |
152 | continue; | |
9140d27b | 153 | p = OBJECT_LIVE_RANGES (obj); |
7db7ed3c VM |
154 | ira_assert (p != NULL); |
155 | start = (high_pressure_start_point[cl] > p->start | |
156 | ? high_pressure_start_point[cl] : p->start); | |
157 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
158 | } | |
058e97ec VM |
159 | } |
160 | ||
ac0ab4f7 BS |
161 | /* Process the death of object OBJ, which is associated with allocno |
162 | A. This finishes the current live range for it. */ | |
058e97ec | 163 | static void |
ac0ab4f7 | 164 | make_object_dead (ira_object_t obj) |
058e97ec | 165 | { |
ac0ab4f7 | 166 | live_range_t lr; |
058e97ec | 167 | |
ac0ab4f7 BS |
168 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
169 | lr = OBJECT_LIVE_RANGES (obj); | |
170 | ira_assert (lr != NULL); | |
171 | lr->finish = curr_point; | |
172 | update_allocno_pressure_excess_length (obj); | |
058e97ec VM |
173 | } |
174 | ||
1756cb66 | 175 | /* The current register pressures for each pressure class for the current |
058e97ec VM |
176 | basic block. */ |
177 | static int curr_reg_pressure[N_REG_CLASSES]; | |
178 | ||
1756cb66 VM |
179 | /* Record that register pressure for PCLASS increased by N registers. |
180 | Update the current register pressure, maximal register pressure for | |
181 | the current BB and the start point of the register pressure | |
182 | excess. */ | |
058e97ec | 183 | static void |
1756cb66 | 184 | inc_register_pressure (enum reg_class pclass, int n) |
058e97ec | 185 | { |
7db7ed3c | 186 | int i; |
3c55880a | 187 | enum reg_class cl; |
058e97ec | 188 | |
7db7ed3c | 189 | for (i = 0; |
1756cb66 | 190 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
191 | i++) |
192 | { | |
1756cb66 VM |
193 | if (! ira_reg_pressure_class_p[cl]) |
194 | continue; | |
3c55880a | 195 | curr_reg_pressure[cl] += n; |
7db7ed3c | 196 | if (high_pressure_start_point[cl] < 0 |
f508f827 | 197 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
7db7ed3c VM |
198 | high_pressure_start_point[cl] = curr_point; |
199 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
200 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
201 | } | |
058e97ec VM |
202 | } |
203 | ||
1756cb66 VM |
204 | /* Record that register pressure for PCLASS has decreased by NREGS |
205 | registers; update current register pressure, start point of the | |
206 | register pressure excess, and register pressure excess length for | |
207 | living allocnos. */ | |
3c55880a | 208 | |
058e97ec | 209 | static void |
1756cb66 | 210 | dec_register_pressure (enum reg_class pclass, int nregs) |
058e97ec | 211 | { |
7db7ed3c VM |
212 | int i; |
213 | unsigned int j; | |
3c55880a BS |
214 | enum reg_class cl; |
215 | bool set_p = false; | |
058e97ec | 216 | |
3c55880a | 217 | for (i = 0; |
1756cb66 | 218 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
3c55880a | 219 | i++) |
058e97ec | 220 | { |
1756cb66 VM |
221 | if (! ira_reg_pressure_class_p[cl]) |
222 | continue; | |
3c55880a BS |
223 | curr_reg_pressure[cl] -= nregs; |
224 | ira_assert (curr_reg_pressure[cl] >= 0); | |
225 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 226 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
3c55880a BS |
227 | set_p = true; |
228 | } | |
229 | if (set_p) | |
230 | { | |
ac0ab4f7 BS |
231 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
232 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
7db7ed3c | 233 | for (i = 0; |
1756cb66 | 234 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c | 235 | i++) |
1756cb66 VM |
236 | { |
237 | if (! ira_reg_pressure_class_p[cl]) | |
238 | continue; | |
239 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 240 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
1756cb66 VM |
241 | high_pressure_start_point[cl] = -1; |
242 | } | |
058e97ec | 243 | } |
058e97ec VM |
244 | } |
245 | ||
e384e6b5 BS |
246 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
247 | and occupies only one object. Return false if we have no information. */ | |
248 | static bool | |
249 | pseudo_regno_single_word_and_live_p (int regno) | |
250 | { | |
251 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
252 | ira_object_t obj; | |
253 | ||
254 | if (a == NULL) | |
255 | return false; | |
256 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
257 | return false; | |
258 | ||
259 | obj = ALLOCNO_OBJECT (a, 0); | |
260 | ||
261 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
262 | } | |
263 | ||
3c55880a BS |
264 | /* Mark the pseudo register REGNO as live. Update all information about |
265 | live ranges and register pressure. */ | |
058e97ec | 266 | static void |
3c55880a | 267 | mark_pseudo_regno_live (int regno) |
058e97ec | 268 | { |
3c55880a | 269 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
1756cb66 | 270 | enum reg_class pclass; |
ac0ab4f7 | 271 | int i, n, nregs; |
058e97ec | 272 | |
3c55880a BS |
273 | if (a == NULL) |
274 | return; | |
058e97ec | 275 | |
3c55880a BS |
276 | /* Invalidate because it is referenced. */ |
277 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 278 | |
ac0ab4f7 | 279 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
280 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
281 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
282 | if (n > 1) |
283 | { | |
284 | /* We track every subobject separately. */ | |
285 | gcc_assert (nregs == n); | |
286 | nregs = 1; | |
287 | } | |
288 | ||
289 | for (i = 0; i < n; i++) | |
290 | { | |
291 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1756cb66 | 292 | |
ac0ab4f7 BS |
293 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
294 | continue; | |
295 | ||
1756cb66 | 296 | inc_register_pressure (pclass, nregs); |
ac0ab4f7 BS |
297 | make_object_born (obj); |
298 | } | |
299 | } | |
300 | ||
301 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
302 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
303 | indicates the low part. */ | |
304 | static void | |
305 | mark_pseudo_regno_subword_live (int regno, int subword) | |
306 | { | |
307 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 308 | int n; |
1756cb66 | 309 | enum reg_class pclass; |
ac0ab4f7 BS |
310 | ira_object_t obj; |
311 | ||
312 | if (a == NULL) | |
3c55880a BS |
313 | return; |
314 | ||
ac0ab4f7 BS |
315 | /* Invalidate because it is referenced. */ |
316 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
317 | ||
318 | n = ALLOCNO_NUM_OBJECTS (a); | |
319 | if (n == 1) | |
320 | { | |
321 | mark_pseudo_regno_live (regno); | |
322 | return; | |
323 | } | |
324 | ||
1756cb66 | 325 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
326 | gcc_assert |
327 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
328 | obj = ALLOCNO_OBJECT (a, subword); |
329 | ||
330 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
331 | return; | |
332 | ||
51935358 | 333 | inc_register_pressure (pclass, 1); |
ac0ab4f7 | 334 | make_object_born (obj); |
3c55880a BS |
335 | } |
336 | ||
ac0ab4f7 BS |
337 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
338 | this register, record how many consecutive hardware registers it | |
339 | actually needs. */ | |
3c55880a BS |
340 | static void |
341 | mark_hard_reg_live (rtx reg) | |
342 | { | |
343 | int regno = REGNO (reg); | |
344 | ||
345 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec | 346 | { |
dc8afb70 | 347 | int last = END_REGNO (reg); |
1756cb66 | 348 | enum reg_class aclass, pclass; |
058e97ec VM |
349 | |
350 | while (regno < last) | |
351 | { | |
352 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
353 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
354 | { | |
1756cb66 VM |
355 | aclass = ira_hard_regno_allocno_class[regno]; |
356 | pclass = ira_pressure_class_translate[aclass]; | |
357 | inc_register_pressure (pclass, 1); | |
3c55880a | 358 | make_hard_regno_born (regno); |
058e97ec VM |
359 | } |
360 | regno++; | |
361 | } | |
362 | } | |
363 | } | |
364 | ||
579c1bf3 BS |
365 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
366 | register number; ORIG_REG is the access in the insn, which may be a | |
367 | subreg. */ | |
368 | static void | |
369 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
370 | { | |
371 | if (df_read_modify_subreg_p (orig_reg)) | |
372 | { | |
373 | mark_pseudo_regno_subword_live (regno, | |
374 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
375 | } | |
376 | else | |
377 | mark_pseudo_regno_live (regno); | |
378 | } | |
379 | ||
3517d3a0 VM |
380 | /* Mark the register referenced by use or def REF as live. */ |
381 | static void | |
57512f53 | 382 | mark_ref_live (df_ref ref) |
058e97ec | 383 | { |
ac0ab4f7 BS |
384 | rtx reg = DF_REF_REG (ref); |
385 | rtx orig_reg = reg; | |
3517d3a0 | 386 | |
3517d3a0 VM |
387 | if (GET_CODE (reg) == SUBREG) |
388 | reg = SUBREG_REG (reg); | |
ac0ab4f7 | 389 | |
3c55880a | 390 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 391 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
3c55880a BS |
392 | else |
393 | mark_hard_reg_live (reg); | |
058e97ec VM |
394 | } |
395 | ||
3c55880a BS |
396 | /* Mark the pseudo register REGNO as dead. Update all information about |
397 | live ranges and register pressure. */ | |
058e97ec | 398 | static void |
3c55880a | 399 | mark_pseudo_regno_dead (int regno) |
058e97ec | 400 | { |
3c55880a | 401 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
ac0ab4f7 | 402 | int n, i, nregs; |
3c55880a | 403 | enum reg_class cl; |
058e97ec | 404 | |
3c55880a BS |
405 | if (a == NULL) |
406 | return; | |
058e97ec | 407 | |
3c55880a BS |
408 | /* Invalidate because it is referenced. */ |
409 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 410 | |
ac0ab4f7 | 411 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
412 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
413 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
414 | if (n > 1) |
415 | { | |
416 | /* We track every subobject separately. */ | |
417 | gcc_assert (nregs == n); | |
418 | nregs = 1; | |
419 | } | |
420 | for (i = 0; i < n; i++) | |
421 | { | |
422 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
423 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
424 | continue; | |
425 | ||
426 | dec_register_pressure (cl, nregs); | |
427 | make_object_dead (obj); | |
428 | } | |
429 | } | |
430 | ||
431 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
432 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
433 | static void | |
434 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
435 | { | |
436 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 437 | int n; |
ac0ab4f7 BS |
438 | enum reg_class cl; |
439 | ira_object_t obj; | |
440 | ||
441 | if (a == NULL) | |
442 | return; | |
443 | ||
444 | /* Invalidate because it is referenced. */ | |
445 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
446 | ||
447 | n = ALLOCNO_NUM_OBJECTS (a); | |
448 | if (n == 1) | |
449 | /* The allocno as a whole doesn't die in this case. */ | |
3c55880a BS |
450 | return; |
451 | ||
1756cb66 | 452 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
453 | gcc_assert |
454 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
455 | |
456 | obj = ALLOCNO_OBJECT (a, subword); | |
457 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
458 | return; | |
3c55880a | 459 | |
ac0ab4f7 BS |
460 | dec_register_pressure (cl, 1); |
461 | make_object_dead (obj); | |
3c55880a BS |
462 | } |
463 | ||
ac0ab4f7 BS |
464 | /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
465 | register. */ | |
3c55880a BS |
466 | static void |
467 | mark_hard_reg_dead (rtx reg) | |
468 | { | |
469 | int regno = REGNO (reg); | |
470 | ||
471 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec | 472 | { |
53d1bae9 | 473 | int last = END_REGNO (reg); |
1756cb66 | 474 | enum reg_class aclass, pclass; |
058e97ec VM |
475 | |
476 | while (regno < last) | |
477 | { | |
478 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
479 | { | |
1756cb66 VM |
480 | aclass = ira_hard_regno_allocno_class[regno]; |
481 | pclass = ira_pressure_class_translate[aclass]; | |
482 | dec_register_pressure (pclass, 1); | |
3c55880a | 483 | make_hard_regno_dead (regno); |
058e97ec VM |
484 | } |
485 | regno++; | |
486 | } | |
487 | } | |
488 | } | |
489 | ||
579c1bf3 BS |
490 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
491 | register number; ORIG_REG is the access in the insn, which may be a | |
492 | subreg. */ | |
493 | static void | |
494 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
495 | { | |
496 | if (df_read_modify_subreg_p (orig_reg)) | |
497 | { | |
498 | mark_pseudo_regno_subword_dead (regno, | |
499 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
500 | } | |
501 | else | |
502 | mark_pseudo_regno_dead (regno); | |
503 | } | |
504 | ||
3517d3a0 VM |
505 | /* Mark the register referenced by definition DEF as dead, if the |
506 | definition is a total one. */ | |
507 | static void | |
57512f53 | 508 | mark_ref_dead (df_ref def) |
3517d3a0 | 509 | { |
ac0ab4f7 BS |
510 | rtx reg = DF_REF_REG (def); |
511 | rtx orig_reg = reg; | |
3517d3a0 | 512 | |
ac0ab4f7 | 513 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
3517d3a0 VM |
514 | return; |
515 | ||
3517d3a0 VM |
516 | if (GET_CODE (reg) == SUBREG) |
517 | reg = SUBREG_REG (reg); | |
ac0ab4f7 BS |
518 | |
519 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
520 | && (GET_CODE (orig_reg) != SUBREG | |
521 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
522 | || !df_read_modify_subreg_p (orig_reg))) | |
523 | return; | |
524 | ||
3c55880a | 525 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 526 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
3c55880a BS |
527 | else |
528 | mark_hard_reg_dead (reg); | |
3517d3a0 VM |
529 | } |
530 | ||
579c1bf3 BS |
531 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
532 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
073a8998 | 533 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
579c1bf3 BS |
534 | Advance the current program point before making the conflict if |
535 | ADVANCE_P. Return TRUE if we will need to advance the current | |
536 | program point. */ | |
3517d3a0 | 537 | static bool |
579c1bf3 BS |
538 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
539 | bool advance_p) | |
3517d3a0 | 540 | { |
579c1bf3 | 541 | rtx orig_reg = reg; |
22c02455 | 542 | ira_allocno_t a; |
3517d3a0 | 543 | |
22c02455 VM |
544 | if (GET_CODE (reg) == SUBREG) |
545 | reg = SUBREG_REG (reg); | |
b8698a0f | 546 | |
22c02455 VM |
547 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
548 | return advance_p; | |
b8698a0f | 549 | |
22c02455 | 550 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
1756cb66 | 551 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
22c02455 | 552 | return advance_p; |
3517d3a0 | 553 | |
22c02455 VM |
554 | if (advance_p) |
555 | curr_point++; | |
3517d3a0 | 556 | |
579c1bf3 BS |
557 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
558 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
559 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
560 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
22c02455 VM |
561 | |
562 | return false; | |
563 | } | |
3517d3a0 | 564 | |
22c02455 VM |
565 | /* Check and make if necessary conflicts for pseudo DREG of class |
566 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
073a8998 | 567 | ORIG_DREG is the rtx actually accessed, it may be identical to |
579c1bf3 BS |
568 | DREG or a subreg of it. Advance the current program point before |
569 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
570 | advance the current program point. */ | |
22c02455 | 571 | static bool |
579c1bf3 BS |
572 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
573 | enum reg_class def_cl, int use, | |
574 | enum reg_class use_cl, bool advance_p) | |
22c02455 VM |
575 | { |
576 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
577 | return advance_p; | |
b8698a0f | 578 | |
22c02455 | 579 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
579c1bf3 BS |
580 | use_cl, dreg, orig_dreg, advance_p); |
581 | ||
22c02455 VM |
582 | /* Reload may end up swapping commutative operands, so you |
583 | have to take both orderings into account. The | |
584 | constraints for the two operands can be completely | |
585 | different. (Indeed, if the constraints for the two | |
586 | operands are the same for all alternatives, there's no | |
587 | point marking them as commutative.) */ | |
dc344e87 | 588 | if (use < recog_data.n_operands - 1 |
22c02455 VM |
589 | && recog_data.constraints[use][0] == '%') |
590 | advance_p | |
591 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
579c1bf3 | 592 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
593 | if (use >= 1 |
594 | && recog_data.constraints[use - 1][0] == '%') | |
595 | advance_p | |
596 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
579c1bf3 | 597 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
598 | return advance_p; |
599 | } | |
600 | ||
601 | /* Check and make if necessary conflicts for definition DEF of class | |
602 | DEF_CL of the current insn with input operands. Process only | |
603 | constraints of alternative ALT. */ | |
604 | static void | |
605 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
606 | { | |
607 | int use, use_match; | |
608 | ira_allocno_t a; | |
609 | enum reg_class use_cl, acl; | |
610 | bool advance_p; | |
611 | rtx dreg = recog_data.operand[def]; | |
579c1bf3 | 612 | rtx orig_dreg = dreg; |
b8698a0f | 613 | |
22c02455 VM |
614 | if (def_cl == NO_REGS) |
615 | return; | |
b8698a0f | 616 | |
22c02455 VM |
617 | if (GET_CODE (dreg) == SUBREG) |
618 | dreg = SUBREG_REG (dreg); | |
b8698a0f | 619 | |
22c02455 VM |
620 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
621 | return; | |
b8698a0f | 622 | |
22c02455 | 623 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
1756cb66 | 624 | acl = ALLOCNO_CLASS (a); |
22c02455 VM |
625 | if (! reg_classes_intersect_p (acl, def_cl)) |
626 | return; | |
b8698a0f | 627 | |
22c02455 | 628 | advance_p = true; |
b8698a0f | 629 | |
29d70a0f | 630 | int n_operands = recog_data.n_operands; |
1145837d | 631 | const operand_alternative *op_alt = &recog_op_alt[alt * n_operands]; |
29d70a0f | 632 | for (use = 0; use < n_operands; use++) |
22c02455 | 633 | { |
002b2dee BS |
634 | int alt1; |
635 | ||
22c02455 | 636 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
7ba06dee | 637 | continue; |
b8698a0f | 638 | |
29d70a0f | 639 | if (op_alt[use].anything_ok) |
22c02455 | 640 | use_cl = ALL_REGS; |
3517d3a0 | 641 | else |
29d70a0f | 642 | use_cl = op_alt[use].cl; |
b8698a0f | 643 | |
002b2dee BS |
644 | /* If there's any alternative that allows USE to match DEF, do not |
645 | record a conflict. If that causes us to create an invalid | |
ac0ab4f7 | 646 | instruction due to the earlyclobber, reload must fix it up. */ |
002b2dee | 647 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
29d70a0f | 648 | { |
9840b2fa | 649 | if (!TEST_BIT (preferred_alternatives, alt1)) |
5f2e0797 | 650 | continue; |
1145837d RS |
651 | const operand_alternative *op_alt1 |
652 | = &recog_op_alt[alt1 * n_operands]; | |
29d70a0f RS |
653 | if (op_alt1[use].matches == def |
654 | || (use < n_operands - 1 | |
655 | && recog_data.constraints[use][0] == '%' | |
656 | && op_alt1[use + 1].matches == def) | |
657 | || (use >= 1 | |
658 | && recog_data.constraints[use - 1][0] == '%' | |
659 | && op_alt1[use - 1].matches == def)) | |
660 | break; | |
661 | } | |
002b2dee BS |
662 | |
663 | if (alt1 < recog_data.n_alternatives) | |
664 | continue; | |
665 | ||
579c1bf3 BS |
666 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
667 | use, use_cl, advance_p); | |
b8698a0f | 668 | |
29d70a0f | 669 | if ((use_match = op_alt[use].matches) >= 0) |
22c02455 VM |
670 | { |
671 | if (use_match == def) | |
7ba06dee | 672 | continue; |
b8698a0f | 673 | |
29d70a0f | 674 | if (op_alt[use_match].anything_ok) |
22c02455 VM |
675 | use_cl = ALL_REGS; |
676 | else | |
29d70a0f | 677 | use_cl = op_alt[use_match].cl; |
579c1bf3 BS |
678 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
679 | use, use_cl, advance_p); | |
22c02455 | 680 | } |
3517d3a0 | 681 | } |
22c02455 VM |
682 | } |
683 | ||
684 | /* Make conflicts of early clobber pseudo registers of the current | |
685 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
686 | checking classes of the constraints and pseudos because otherwise | |
687 | significant code degradation is possible for some targets. */ | |
688 | static void | |
689 | make_early_clobber_and_input_conflicts (void) | |
690 | { | |
691 | int alt; | |
692 | int def, def_match; | |
693 | enum reg_class def_cl; | |
694 | ||
29d70a0f RS |
695 | int n_alternatives = recog_data.n_alternatives; |
696 | int n_operands = recog_data.n_operands; | |
1145837d | 697 | const operand_alternative *op_alt = recog_op_alt; |
29d70a0f | 698 | for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands) |
9840b2fa | 699 | if (TEST_BIT (preferred_alternatives, alt)) |
5f2e0797 RS |
700 | for (def = 0; def < n_operands; def++) |
701 | { | |
702 | def_cl = NO_REGS; | |
703 | if (op_alt[def].earlyclobber) | |
704 | { | |
705 | if (op_alt[def].anything_ok) | |
706 | def_cl = ALL_REGS; | |
707 | else | |
708 | def_cl = op_alt[def].cl; | |
709 | check_and_make_def_conflict (alt, def, def_cl); | |
710 | } | |
711 | if ((def_match = op_alt[def].matches) >= 0 | |
712 | && (op_alt[def_match].earlyclobber | |
713 | || op_alt[def].earlyclobber)) | |
714 | { | |
715 | if (op_alt[def_match].anything_ok) | |
716 | def_cl = ALL_REGS; | |
717 | else | |
718 | def_cl = op_alt[def_match].cl; | |
719 | check_and_make_def_conflict (alt, def, def_cl); | |
720 | } | |
721 | } | |
22c02455 VM |
722 | } |
723 | ||
724 | /* Mark early clobber hard registers of the current INSN as live (if | |
725 | LIVE_P) or dead. Return true if there are such registers. */ | |
726 | static bool | |
070a1983 | 727 | mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p) |
22c02455 | 728 | { |
bfac633a | 729 | df_ref def; |
22c02455 | 730 | bool set_p = false; |
3517d3a0 | 731 | |
bfac633a RS |
732 | FOR_EACH_INSN_DEF (def, insn) |
733 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)) | |
3517d3a0 | 734 | { |
bfac633a | 735 | rtx dreg = DF_REF_REG (def); |
b8698a0f | 736 | |
3517d3a0 VM |
737 | if (GET_CODE (dreg) == SUBREG) |
738 | dreg = SUBREG_REG (dreg); | |
739 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
740 | continue; | |
741 | ||
742 | /* Hard register clobbers are believed to be early clobber | |
743 | because there is no way to say that non-operand hard | |
b8698a0f | 744 | register clobbers are not early ones. */ |
3517d3a0 | 745 | if (live_p) |
bfac633a | 746 | mark_ref_live (def); |
3517d3a0 | 747 | else |
bfac633a | 748 | mark_ref_dead (def); |
3517d3a0 VM |
749 | set_p = true; |
750 | } | |
751 | ||
752 | return set_p; | |
753 | } | |
754 | ||
058e97ec VM |
755 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
756 | it is so, the function returns the class of the hard register. | |
757 | Otherwise it returns NO_REGS. */ | |
758 | static enum reg_class | |
759 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
760 | { | |
4cc8d9d2 | 761 | int c; |
058e97ec | 762 | enum reg_class cl, next_cl; |
777e635f | 763 | enum constraint_num cn; |
058e97ec VM |
764 | |
765 | cl = NO_REGS; | |
9840b2fa | 766 | alternative_mask preferred = preferred_alternatives; |
4cc8d9d2 RS |
767 | for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)) |
768 | if (c == '#') | |
9840b2fa | 769 | preferred &= ~ALTERNATIVE_BIT (0); |
058e97ec | 770 | else if (c == ',') |
9840b2fa RS |
771 | preferred >>= 1; |
772 | else if (preferred & 1) | |
058e97ec VM |
773 | switch (c) |
774 | { | |
8677664e RS |
775 | case 'g': |
776 | return NO_REGS; | |
b8698a0f | 777 | |
8677664e | 778 | default: |
b58923e2 | 779 | /* ??? Is this the best way to handle memory constraints? */ |
777e635f RS |
780 | cn = lookup_constraint (constraints); |
781 | if (insn_extra_memory_constraint (cn) | |
782 | || insn_extra_address_constraint (cn)) | |
b58923e2 | 783 | return NO_REGS; |
777e635f | 784 | if (constraint_satisfied_p (op, cn) |
b58923e2 RS |
785 | || (equiv_const != NULL_RTX |
786 | && CONSTANT_P (equiv_const) | |
777e635f | 787 | && constraint_satisfied_p (equiv_const, cn))) |
b58923e2 | 788 | return NO_REGS; |
8677664e | 789 | next_cl = reg_class_for_constraint (cn); |
b58923e2 RS |
790 | if (next_cl == NO_REGS) |
791 | break; | |
c9d74da6 RS |
792 | if (cl == NO_REGS |
793 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
794 | : (ira_class_singleton[cl][GET_MODE (op)] | |
795 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
796 | return NO_REGS; |
797 | cl = next_cl; | |
798 | break; | |
b8698a0f | 799 | |
058e97ec VM |
800 | case '0': case '1': case '2': case '3': case '4': |
801 | case '5': case '6': case '7': case '8': case '9': | |
802 | next_cl | |
803 | = single_reg_class (recog_data.constraints[c - '0'], | |
804 | recog_data.operand[c - '0'], NULL_RTX); | |
c9d74da6 RS |
805 | if (cl == NO_REGS |
806 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
807 | : (ira_class_singleton[cl][GET_MODE (op)] | |
808 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
809 | return NO_REGS; |
810 | cl = next_cl; | |
811 | break; | |
058e97ec VM |
812 | } |
813 | return cl; | |
814 | } | |
815 | ||
816 | /* The function checks that operand OP_NUM of the current insn can use | |
817 | only one hard register. If it is so, the function returns the | |
818 | class of the hard register. Otherwise it returns NO_REGS. */ | |
819 | static enum reg_class | |
820 | single_reg_operand_class (int op_num) | |
821 | { | |
822 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
823 | return NO_REGS; | |
824 | return single_reg_class (recog_data.constraints[op_num], | |
825 | recog_data.operand[op_num], NULL_RTX); | |
826 | } | |
827 | ||
ce18efcb VM |
828 | /* The function sets up hard register set *SET to hard registers which |
829 | might be used by insn reloads because the constraints are too | |
830 | strict. */ | |
831 | void | |
8f3f5ac0 L |
832 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set, |
833 | alternative_mask preferred) | |
ce18efcb | 834 | { |
4cc8d9d2 | 835 | int i, c, regno = 0; |
ce18efcb VM |
836 | enum reg_class cl; |
837 | rtx op; | |
ef4bddc2 | 838 | machine_mode mode; |
ce18efcb VM |
839 | |
840 | CLEAR_HARD_REG_SET (*set); | |
841 | for (i = 0; i < recog_data.n_operands; i++) | |
842 | { | |
843 | op = recog_data.operand[i]; | |
844 | ||
845 | if (GET_CODE (op) == SUBREG) | |
846 | op = SUBREG_REG (op); | |
b8698a0f | 847 | |
ce18efcb VM |
848 | if (GET_CODE (op) == SCRATCH |
849 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
850 | { | |
851 | const char *p = recog_data.constraints[i]; | |
852 | ||
853 | mode = (GET_CODE (op) == SCRATCH | |
854 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
855 | cl = NO_REGS; | |
4cc8d9d2 RS |
856 | for (; (c = *p); p += CONSTRAINT_LEN (c, p)) |
857 | if (c == '#') | |
9840b2fa | 858 | preferred &= ~ALTERNATIVE_BIT (0); |
ce18efcb | 859 | else if (c == ',') |
9840b2fa RS |
860 | preferred >>= 1; |
861 | else if (preferred & 1) | |
8677664e RS |
862 | { |
863 | cl = reg_class_for_constraint (lookup_constraint (p)); | |
864 | if (cl != NO_REGS) | |
865 | { | |
866 | /* There is no register pressure problem if all of the | |
867 | regs in this class are fixed. */ | |
868 | int regno = ira_class_singleton[cl][mode]; | |
869 | if (regno >= 0) | |
870 | add_to_hard_reg_set (set, mode, regno); | |
871 | } | |
872 | } | |
ce18efcb VM |
873 | } |
874 | } | |
875 | } | |
058e97ec VM |
876 | /* Processes input operands, if IN_P, or output operands otherwise of |
877 | the current insn with FREQ to find allocno which can use only one | |
878 | hard register and makes other currently living allocnos conflicting | |
879 | with the hard register. */ | |
880 | static void | |
881 | process_single_reg_class_operands (bool in_p, int freq) | |
882 | { | |
6d1e1a26 | 883 | int i, regno; |
058e97ec | 884 | unsigned int px; |
11895e28 | 885 | enum reg_class cl; |
058e97ec VM |
886 | rtx operand; |
887 | ira_allocno_t operand_a, a; | |
888 | ||
889 | for (i = 0; i < recog_data.n_operands; i++) | |
890 | { | |
891 | operand = recog_data.operand[i]; | |
892 | if (in_p && recog_data.operand_type[i] != OP_IN | |
893 | && recog_data.operand_type[i] != OP_INOUT) | |
894 | continue; | |
895 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
896 | && recog_data.operand_type[i] != OP_INOUT) | |
897 | continue; | |
898 | cl = single_reg_operand_class (i); | |
899 | if (cl == NO_REGS) | |
900 | continue; | |
901 | ||
902 | operand_a = NULL; | |
903 | ||
904 | if (GET_CODE (operand) == SUBREG) | |
905 | operand = SUBREG_REG (operand); | |
b8698a0f | 906 | |
058e97ec VM |
907 | if (REG_P (operand) |
908 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
909 | { | |
1756cb66 | 910 | enum reg_class aclass; |
058e97ec VM |
911 | |
912 | operand_a = ira_curr_regno_allocno_map[regno]; | |
1756cb66 | 913 | aclass = ALLOCNO_CLASS (operand_a); |
c9d74da6 | 914 | if (ira_class_subset_p[cl][aclass]) |
058e97ec | 915 | { |
6d1e1a26 RS |
916 | /* View the desired allocation of OPERAND as: |
917 | ||
918 | (REG:YMODE YREGNO), | |
919 | ||
920 | a simplification of: | |
921 | ||
922 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
ef4bddc2 | 923 | machine_mode ymode, xmode; |
6d1e1a26 RS |
924 | int xregno, yregno; |
925 | HOST_WIDE_INT offset; | |
926 | ||
927 | xmode = recog_data.operand_mode[i]; | |
c9d74da6 RS |
928 | xregno = ira_class_singleton[cl][xmode]; |
929 | gcc_assert (xregno >= 0); | |
6d1e1a26 RS |
930 | ymode = ALLOCNO_MODE (operand_a); |
931 | offset = subreg_lowpart_offset (ymode, xmode); | |
932 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
933 | if (yregno >= 0 | |
1756cb66 | 934 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
6d1e1a26 RS |
935 | { |
936 | int cost; | |
937 | ||
938 | ira_allocate_and_set_costs | |
939 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
1756cb66 VM |
940 | aclass, 0); |
941 | ira_init_register_move_cost_if_necessary (xmode); | |
942 | cost = freq * (in_p | |
943 | ? ira_register_move_cost[xmode][aclass][cl] | |
944 | : ira_register_move_cost[xmode][cl][aclass]); | |
6d1e1a26 | 945 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
1756cb66 | 946 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
6d1e1a26 | 947 | } |
058e97ec VM |
948 | } |
949 | } | |
950 | ||
ac0ab4f7 | 951 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
058e97ec | 952 | { |
ac0ab4f7 BS |
953 | ira_object_t obj = ira_object_id_map[px]; |
954 | a = OBJECT_ALLOCNO (obj); | |
058e97ec VM |
955 | if (a != operand_a) |
956 | { | |
957 | /* We could increase costs of A instead of making it | |
958 | conflicting with the hard register. But it works worse | |
959 | because it will be spilled in reload in anyway. */ | |
a49ae217 | 960 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
058e97ec | 961 | reg_class_contents[cl]); |
a49ae217 | 962 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
058e97ec VM |
963 | reg_class_contents[cl]); |
964 | } | |
965 | } | |
966 | } | |
967 | } | |
968 | ||
e384e6b5 BS |
969 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
970 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
971 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
972 | static rtx | |
070a1983 | 973 | find_call_crossed_cheap_reg (rtx_insn *insn) |
e384e6b5 BS |
974 | { |
975 | rtx cheap_reg = NULL_RTX; | |
976 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
977 | ||
978 | while (exp != NULL) | |
979 | { | |
980 | rtx x = XEXP (exp, 0); | |
981 | if (GET_CODE (x) == SET) | |
982 | { | |
983 | exp = x; | |
984 | break; | |
985 | } | |
986 | exp = XEXP (exp, 1); | |
987 | } | |
988 | if (exp != NULL) | |
989 | { | |
990 | basic_block bb = BLOCK_FOR_INSN (insn); | |
991 | rtx reg = SET_SRC (exp); | |
c74ef30d | 992 | rtx_insn *prev = PREV_INSN (insn); |
e384e6b5 BS |
993 | while (prev && !(INSN_P (prev) |
994 | && BLOCK_FOR_INSN (prev) != bb)) | |
995 | { | |
996 | if (NONDEBUG_INSN_P (prev)) | |
997 | { | |
998 | rtx set = single_set (prev); | |
999 | ||
1000 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
1001 | { | |
1002 | rtx src = SET_SRC (set); | |
1003 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
1004 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1005 | break; | |
1006 | if (!modified_between_p (src, prev, insn)) | |
1007 | cheap_reg = src; | |
1008 | break; | |
1009 | } | |
1010 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1011 | { | |
1012 | rtx dest = SET_DEST (set); | |
1013 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1014 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1015 | break; | |
1016 | if (!modified_between_p (dest, prev, insn)) | |
1017 | cheap_reg = dest; | |
1018 | break; | |
1019 | } | |
1020 | ||
1021 | if (reg_overlap_mentioned_p (reg, PATTERN (prev))) | |
1022 | break; | |
1023 | } | |
1024 | prev = PREV_INSN (prev); | |
1025 | } | |
1026 | } | |
1027 | return cheap_reg; | |
1028 | } | |
1029 | ||
058e97ec VM |
1030 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1031 | update allocno live ranges, allocno hard register conflicts, | |
1032 | intersected calls, and register pressure info for allocnos for the | |
1033 | basic block for and regions containing the basic block. */ | |
1034 | static void | |
1035 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1036 | { | |
acb37d29 | 1037 | int i, freq; |
058e97ec VM |
1038 | unsigned int j; |
1039 | basic_block bb; | |
070a1983 | 1040 | rtx_insn *insn; |
058e97ec | 1041 | bitmap_iterator bi; |
acb37d29 | 1042 | bitmap reg_live_out; |
058e97ec | 1043 | unsigned int px; |
3517d3a0 | 1044 | bool set_p; |
058e97ec VM |
1045 | |
1046 | bb = loop_tree_node->bb; | |
1047 | if (bb != NULL) | |
1048 | { | |
1756cb66 | 1049 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1050 | { |
1756cb66 VM |
1051 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1052 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
058e97ec VM |
1053 | } |
1054 | curr_bb_node = loop_tree_node; | |
bf744527 | 1055 | reg_live_out = df_get_live_out (bb); |
ac0ab4f7 | 1056 | sparseset_clear (objects_live); |
acb37d29 | 1057 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
058e97ec VM |
1058 | AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); |
1059 | AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
1060 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1061 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1062 | { | |
1756cb66 | 1063 | enum reg_class aclass, pclass, cl; |
b8698a0f | 1064 | |
1756cb66 VM |
1065 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1066 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 1067 | for (j = 0; |
1756cb66 | 1068 | (cl = ira_reg_class_super_classes[pclass][j]) |
7db7ed3c VM |
1069 | != LIM_REG_CLASSES; |
1070 | j++) | |
1071 | { | |
1756cb66 VM |
1072 | if (! ira_reg_pressure_class_p[cl]) |
1073 | continue; | |
7db7ed3c VM |
1074 | curr_reg_pressure[cl]++; |
1075 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1076 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1077 | ira_assert (curr_reg_pressure[cl] | |
f508f827 | 1078 | <= ira_class_hard_regs_num[cl]); |
7db7ed3c | 1079 | } |
058e97ec | 1080 | } |
acb37d29 | 1081 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
3c55880a | 1082 | mark_pseudo_regno_live (j); |
b8698a0f | 1083 | |
acb37d29 RS |
1084 | freq = REG_FREQ_FROM_BB (bb); |
1085 | if (freq == 0) | |
1086 | freq = 1; | |
1087 | ||
cb1ca6ac VM |
1088 | /* Invalidate all allocno_saved_at_call entries. */ |
1089 | last_call_num++; | |
1090 | ||
058e97ec | 1091 | /* Scan the code of this basic block, noting which allocnos and |
acb37d29 RS |
1092 | hard regs are born or die. |
1093 | ||
1094 | Note that this loop treats uninitialized values as live until | |
1095 | the beginning of the block. For example, if an instruction | |
1096 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1097 | set, FOO will remain live until the beginning of the block. | |
1098 | Likewise if FOO is not set at all. This is unnecessarily | |
1099 | pessimistic, but it probably doesn't matter much in practice. */ | |
1100 | FOR_BB_INSNS_REVERSE (bb, insn) | |
058e97ec | 1101 | { |
21c6c24f | 1102 | ira_allocno_t a; |
bfac633a | 1103 | df_ref def, use; |
61001a35 | 1104 | bool call_p; |
b8698a0f | 1105 | |
b5b8b0ac | 1106 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec | 1107 | continue; |
b8698a0f | 1108 | |
058e97ec VM |
1109 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1110 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
2608d841 | 1111 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
058e97ec VM |
1112 | curr_point); |
1113 | ||
21c6c24f | 1114 | call_p = CALL_P (insn); |
61001a35 VM |
1115 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
1116 | int regno; | |
1117 | bool clear_pic_use_conflict_p = false; | |
21c6c24f VM |
1118 | /* Processing insn usage in call insn can create conflict |
1119 | with pic pseudo and pic hard reg and that is wrong. | |
1120 | Check this situation and fix it at the end of the insn | |
1121 | processing. */ | |
1122 | if (call_p && pic_offset_table_rtx != NULL_RTX | |
1123 | && (regno = REGNO (pic_offset_table_rtx)) >= FIRST_PSEUDO_REGISTER | |
1124 | && (a = ira_curr_regno_allocno_map[regno]) != NULL) | |
1125 | clear_pic_use_conflict_p | |
1126 | = (find_regno_fusage (insn, USE, REAL_PIC_OFFSET_TABLE_REGNUM) | |
1127 | && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS | |
1128 | (ALLOCNO_OBJECT (a, 0)), | |
1129 | REAL_PIC_OFFSET_TABLE_REGNUM)); | |
61001a35 | 1130 | #endif |
21c6c24f | 1131 | |
acb37d29 RS |
1132 | /* Mark each defined value as live. We need to do this for |
1133 | unused values because they still conflict with quantities | |
1134 | that are live at the time of the definition. | |
1135 | ||
1136 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1137 | references represent the effect of the called function | |
1138 | on a call-clobbered register. Marking the register as | |
1139 | live would stop us from allocating it to a call-crossing | |
1140 | allocno. */ | |
bfac633a RS |
1141 | FOR_EACH_INSN_DEF (def, insn) |
1142 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1143 | mark_ref_live (def); | |
acb37d29 RS |
1144 | |
1145 | /* If INSN has multiple outputs, then any value used in one | |
1146 | of the outputs conflicts with the other outputs. Model this | |
1147 | by making the used value live during the output phase. | |
1148 | ||
1149 | It is unsafe to use !single_set here since it will ignore | |
1150 | an unused output. Just because an output is unused does | |
1151 | not mean the compiler can assume the side effect will not | |
1152 | occur. Consider if ALLOCNO appears in the address of an | |
1153 | output and we reload the output. If we allocate ALLOCNO | |
1154 | to the same hard register as an unused output we could | |
1155 | set the hard register before the output reload insn. */ | |
1156 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
bfac633a | 1157 | FOR_EACH_INSN_USE (use, insn) |
acb37d29 RS |
1158 | { |
1159 | int i; | |
1160 | rtx reg; | |
1161 | ||
bfac633a | 1162 | reg = DF_REF_REG (use); |
acb37d29 RS |
1163 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
1164 | { | |
1165 | rtx set; | |
1166 | ||
1167 | set = XVECEXP (PATTERN (insn), 0, i); | |
1168 | if (GET_CODE (set) == SET | |
1169 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1170 | { | |
1171 | /* After the previous loop, this is a no-op if | |
1172 | REG is contained within SET_DEST (SET). */ | |
bfac633a | 1173 | mark_ref_live (use); |
acb37d29 RS |
1174 | break; |
1175 | } | |
1176 | } | |
1177 | } | |
b8698a0f | 1178 | |
058e97ec | 1179 | extract_insn (insn); |
9840b2fa | 1180 | preferred_alternatives = get_preferred_alternatives (insn); |
1145837d | 1181 | preprocess_constraints (insn); |
acb37d29 | 1182 | process_single_reg_class_operands (false, freq); |
b8698a0f | 1183 | |
acb37d29 | 1184 | /* See which defined values die here. */ |
bfac633a RS |
1185 | FOR_EACH_INSN_DEF (def, insn) |
1186 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1187 | mark_ref_dead (def); | |
058e97ec | 1188 | |
acb37d29 | 1189 | if (call_p) |
058e97ec | 1190 | { |
e384e6b5 BS |
1191 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1192 | there, try to find a pseudo that is live across the call but | |
1193 | can be cheaply reconstructed from the return value. */ | |
1194 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1195 | if (cheap_reg != NULL_RTX) | |
1196 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1197 | ||
cb1ca6ac | 1198 | last_call_num++; |
ac0ab4f7 | 1199 | sparseset_clear (allocnos_processed); |
acb37d29 | 1200 | /* The current set of live allocnos are live across the call. */ |
ac0ab4f7 | 1201 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 1202 | { |
ac0ab4f7 | 1203 | ira_object_t obj = ira_object_id_map[i]; |
21c6c24f | 1204 | a = OBJECT_ALLOCNO (obj); |
ac0ab4f7 | 1205 | int num = ALLOCNO_NUM (a); |
c2ba7e7a RO |
1206 | HARD_REG_SET this_call_used_reg_set; |
1207 | ||
1208 | get_call_reg_set_usage (insn, &this_call_used_reg_set, | |
1209 | call_used_reg_set); | |
b8698a0f | 1210 | |
5feec5c1 VM |
1211 | /* Don't allocate allocnos that cross setjmps or any |
1212 | call, if this function receives a nonlocal | |
1213 | goto. */ | |
1214 | if (cfun->has_nonlocal_label | |
1215 | || find_reg_note (insn, REG_SETJMP, | |
1216 | NULL_RTX) != NULL_RTX) | |
058e97ec | 1217 | { |
a49ae217 BS |
1218 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1219 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
058e97ec | 1220 | } |
cf0c2a60 VM |
1221 | if (can_throw_internal (insn)) |
1222 | { | |
a49ae217 | 1223 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
c2ba7e7a | 1224 | this_call_used_reg_set); |
ac0ab4f7 | 1225 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
c2ba7e7a | 1226 | this_call_used_reg_set); |
cf0c2a60 | 1227 | } |
ac0ab4f7 BS |
1228 | |
1229 | if (sparseset_bit_p (allocnos_processed, num)) | |
1230 | continue; | |
1231 | sparseset_set_bit (allocnos_processed, num); | |
1232 | ||
1233 | if (allocno_saved_at_call[num] != last_call_num) | |
df3e3493 | 1234 | /* Here we are mimicking caller-save.c behavior |
ac0ab4f7 BS |
1235 | which does not save hard register at a call if |
1236 | it was saved on previous call in the same basic | |
1237 | block and the hard register was not mentioned | |
1238 | between the two calls. */ | |
1239 | ALLOCNO_CALL_FREQ (a) += freq; | |
1240 | /* Mark it as saved at the next call. */ | |
1241 | allocno_saved_at_call[num] = last_call_num + 1; | |
1242 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
c2ba7e7a RO |
1243 | IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), |
1244 | this_call_used_reg_set); | |
e384e6b5 BS |
1245 | if (cheap_reg != NULL_RTX |
1246 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1247 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
058e97ec VM |
1248 | } |
1249 | } | |
b8698a0f | 1250 | |
22c02455 VM |
1251 | make_early_clobber_and_input_conflicts (); |
1252 | ||
acb37d29 | 1253 | curr_point++; |
21c6c24f | 1254 | |
acb37d29 | 1255 | /* Mark each used value as live. */ |
bfac633a RS |
1256 | FOR_EACH_INSN_USE (use, insn) |
1257 | mark_ref_live (use); | |
acb37d29 | 1258 | |
acb37d29 | 1259 | process_single_reg_class_operands (true, freq); |
b8698a0f | 1260 | |
22c02455 VM |
1261 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1262 | ||
3517d3a0 VM |
1263 | if (set_p) |
1264 | { | |
22c02455 | 1265 | mark_hard_reg_early_clobbers (insn, false); |
3517d3a0 | 1266 | |
22c02455 | 1267 | /* Mark each hard reg as live again. For example, a |
3517d3a0 VM |
1268 | hard register can be in clobber and in an insn |
1269 | input. */ | |
bfac633a | 1270 | FOR_EACH_INSN_USE (use, insn) |
22c02455 | 1271 | { |
bfac633a | 1272 | rtx ureg = DF_REF_REG (use); |
b8698a0f | 1273 | |
22c02455 VM |
1274 | if (GET_CODE (ureg) == SUBREG) |
1275 | ureg = SUBREG_REG (ureg); | |
1276 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1277 | continue; | |
b8698a0f | 1278 | |
bfac633a | 1279 | mark_ref_live (use); |
22c02455 | 1280 | } |
3517d3a0 | 1281 | } |
058e97ec | 1282 | |
61001a35 | 1283 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
21c6c24f VM |
1284 | if (clear_pic_use_conflict_p) |
1285 | { | |
1286 | regno = REGNO (pic_offset_table_rtx); | |
1287 | a = ira_curr_regno_allocno_map[regno]; | |
1288 | CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a, 0)), | |
1289 | REAL_PIC_OFFSET_TABLE_REGNUM); | |
1290 | CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS | |
1291 | (ALLOCNO_OBJECT (a, 0)), | |
1292 | REAL_PIC_OFFSET_TABLE_REGNUM); | |
1293 | } | |
61001a35 | 1294 | #endif |
058e97ec VM |
1295 | curr_point++; |
1296 | } | |
acb37d29 | 1297 | |
5dbd125c EB |
1298 | if (bb_has_eh_pred (bb)) |
1299 | for (j = 0; ; ++j) | |
1300 | { | |
1301 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1302 | if (regno == INVALID_REGNUM) | |
1303 | break; | |
3c55880a | 1304 | make_hard_regno_born (regno); |
5dbd125c | 1305 | } |
5dbd125c | 1306 | |
acb37d29 RS |
1307 | /* Allocnos can't go in stack regs at the start of a basic block |
1308 | that is reached by an abnormal edge. Likewise for call | |
1309 | clobbered regs, because caller-save, fixup_abnormal_edges and | |
1310 | possibly the table driven EH machinery are not quite ready to | |
1311 | handle such allocnos live across such edges. */ | |
5dbd125c | 1312 | if (bb_has_abnormal_pred (bb)) |
acb37d29 RS |
1313 | { |
1314 | #ifdef STACK_REGS | |
ac0ab4f7 | 1315 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
acb37d29 | 1316 | { |
ac0ab4f7 | 1317 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
1756cb66 | 1318 | |
ac0ab4f7 BS |
1319 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1320 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
acb37d29 RS |
1321 | } |
1322 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
3c55880a | 1323 | make_hard_regno_born (px); |
acb37d29 RS |
1324 | #endif |
1325 | /* No need to record conflicts for call clobbered regs if we | |
1326 | have nonlocal labels around, as we don't ever try to | |
1327 | allocate such regs in this case. */ | |
f1544089 MP |
1328 | if (!cfun->has_nonlocal_label |
1329 | && has_abnormal_call_or_eh_pred_edge_p (bb)) | |
acb37d29 | 1330 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
1d6cc2e4 VM |
1331 | if (call_used_regs[px] |
1332 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM | |
1333 | /* We should create a conflict of PIC pseudo with | |
1334 | PIC hard reg as PIC hard reg can have a wrong | |
1335 | value after jump described by the abnormal edge. | |
1336 | In this case we can not allocate PIC hard reg to | |
1337 | PIC pseudo as PIC pseudo will also have a wrong | |
1338 | value. This code is not critical as LRA can fix | |
1339 | it but it is better to have the right allocation | |
1340 | earlier. */ | |
1341 | || (px == REAL_PIC_OFFSET_TABLE_REGNUM | |
1342 | && pic_offset_table_rtx != NULL_RTX | |
1343 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
1344 | #endif | |
1345 | ) | |
3c55880a | 1346 | make_hard_regno_born (px); |
acb37d29 RS |
1347 | } |
1348 | ||
ac0ab4f7 BS |
1349 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1350 | make_object_dead (ira_object_id_map[i]); | |
058e97ec VM |
1351 | |
1352 | curr_point++; | |
1353 | ||
1354 | } | |
2b9c63a2 | 1355 | /* Propagate register pressure to upper loop tree nodes. */ |
058e97ec | 1356 | if (loop_tree_node != ira_loop_tree_root) |
1756cb66 | 1357 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1358 | { |
1756cb66 | 1359 | enum reg_class pclass; |
058e97ec | 1360 | |
1756cb66 VM |
1361 | pclass = ira_pressure_classes[i]; |
1362 | if (loop_tree_node->reg_pressure[pclass] | |
1363 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1364 | loop_tree_node->parent->reg_pressure[pclass] | |
1365 | = loop_tree_node->reg_pressure[pclass]; | |
058e97ec VM |
1366 | } |
1367 | } | |
1368 | ||
1369 | /* Create and set up IRA_START_POINT_RANGES and | |
1370 | IRA_FINISH_POINT_RANGES. */ | |
1371 | static void | |
1372 | create_start_finish_chains (void) | |
1373 | { | |
ac0ab4f7 BS |
1374 | ira_object_t obj; |
1375 | ira_object_iterator oi; | |
b14151b5 | 1376 | live_range_t r; |
058e97ec VM |
1377 | |
1378 | ira_start_point_ranges | |
ac0ab4f7 BS |
1379 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1380 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
058e97ec | 1381 | ira_finish_point_ranges |
ac0ab4f7 BS |
1382 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1383 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1384 | FOR_EACH_OBJECT (obj, oi) | |
1385 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1386 | { | |
1387 | r->start_next = ira_start_point_ranges[r->start]; | |
1388 | ira_start_point_ranges[r->start] = r; | |
1389 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
058e97ec | 1390 | ira_finish_point_ranges[r->finish] = r; |
ac0ab4f7 | 1391 | } |
058e97ec VM |
1392 | } |
1393 | ||
1394 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1395 | new live ranges and program points were added as a result if new | |
1396 | insn generation. */ | |
1397 | void | |
1398 | ira_rebuild_start_finish_chains (void) | |
1399 | { | |
1400 | ira_free (ira_finish_point_ranges); | |
1401 | ira_free (ira_start_point_ranges); | |
1402 | create_start_finish_chains (); | |
1403 | } | |
1404 | ||
b15a7ae6 VM |
1405 | /* Compress allocno live ranges by removing program points where |
1406 | nothing happens. */ | |
1407 | static void | |
1408 | remove_some_program_points_and_update_live_ranges (void) | |
1409 | { | |
1410 | unsigned i; | |
1411 | int n; | |
1412 | int *map; | |
9140d27b BS |
1413 | ira_object_t obj; |
1414 | ira_object_iterator oi; | |
e6a7da82 | 1415 | live_range_t r, prev_r, next_r; |
9995f209 VM |
1416 | sbitmap born_or_dead, born, dead; |
1417 | sbitmap_iterator sbi; | |
1418 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1419 | ||
1420 | born = sbitmap_alloc (ira_max_point); | |
1421 | dead = sbitmap_alloc (ira_max_point); | |
f61e445a LC |
1422 | bitmap_clear (born); |
1423 | bitmap_clear (dead); | |
9140d27b BS |
1424 | FOR_EACH_OBJECT (obj, oi) |
1425 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1426 | { | |
1427 | ira_assert (r->start <= r->finish); | |
d7c028c0 LC |
1428 | bitmap_set_bit (born, r->start); |
1429 | bitmap_set_bit (dead, r->finish); | |
9140d27b BS |
1430 | } |
1431 | ||
9995f209 | 1432 | born_or_dead = sbitmap_alloc (ira_max_point); |
f61e445a | 1433 | bitmap_ior (born_or_dead, born, dead); |
b15a7ae6 | 1434 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
9995f209 VM |
1435 | n = -1; |
1436 | prev_born_p = prev_dead_p = false; | |
d4ac4ce2 | 1437 | EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi) |
b15a7ae6 | 1438 | { |
d7c028c0 LC |
1439 | born_p = bitmap_bit_p (born, i); |
1440 | dead_p = bitmap_bit_p (dead, i); | |
9995f209 VM |
1441 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
1442 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1443 | map[i] = n; | |
1444 | else | |
1445 | map[i] = ++n; | |
1446 | prev_born_p = born_p; | |
1447 | prev_dead_p = dead_p; | |
b15a7ae6 | 1448 | } |
9995f209 VM |
1449 | sbitmap_free (born_or_dead); |
1450 | sbitmap_free (born); | |
1451 | sbitmap_free (dead); | |
1452 | n++; | |
b15a7ae6 VM |
1453 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1454 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1455 | ira_max_point, n, 100 * n / ira_max_point); | |
1456 | ira_max_point = n; | |
9140d27b BS |
1457 | |
1458 | FOR_EACH_OBJECT (obj, oi) | |
e6a7da82 | 1459 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9140d27b | 1460 | { |
e6a7da82 | 1461 | next_r = r->next; |
9140d27b BS |
1462 | r->start = map[r->start]; |
1463 | r->finish = map[r->finish]; | |
e6a7da82 SB |
1464 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1465 | { | |
1466 | prev_r = r; | |
1467 | continue; | |
1468 | } | |
1469 | prev_r->start = r->start; | |
1470 | prev_r->next = next_r; | |
1471 | ira_finish_live_range (r); | |
9140d27b | 1472 | } |
ac0ab4f7 | 1473 | |
b15a7ae6 VM |
1474 | ira_free (map); |
1475 | } | |
1476 | ||
058e97ec VM |
1477 | /* Print live ranges R to file F. */ |
1478 | void | |
b14151b5 | 1479 | ira_print_live_range_list (FILE *f, live_range_t r) |
058e97ec VM |
1480 | { |
1481 | for (; r != NULL; r = r->next) | |
1482 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1483 | fprintf (f, "\n"); | |
1484 | } | |
1485 | ||
7b3b6ae4 LC |
1486 | DEBUG_FUNCTION void |
1487 | debug (live_range &ref) | |
1488 | { | |
1489 | ira_print_live_range_list (stderr, &ref); | |
1490 | } | |
1491 | ||
1492 | DEBUG_FUNCTION void | |
1493 | debug (live_range *ptr) | |
1494 | { | |
1495 | if (ptr) | |
1496 | debug (*ptr); | |
1497 | else | |
1498 | fprintf (stderr, "<nil>\n"); | |
1499 | } | |
1500 | ||
058e97ec VM |
1501 | /* Print live ranges R to stderr. */ |
1502 | void | |
b14151b5 | 1503 | ira_debug_live_range_list (live_range_t r) |
058e97ec VM |
1504 | { |
1505 | ira_print_live_range_list (stderr, r); | |
1506 | } | |
1507 | ||
ac0ab4f7 BS |
1508 | /* Print live ranges of object OBJ to file F. */ |
1509 | static void | |
1510 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1511 | { | |
1512 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1513 | } | |
1514 | ||
058e97ec VM |
1515 | /* Print live ranges of allocno A to file F. */ |
1516 | static void | |
1517 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1518 | { | |
ac0ab4f7 BS |
1519 | int n = ALLOCNO_NUM_OBJECTS (a); |
1520 | int i; | |
1756cb66 | 1521 | |
ac0ab4f7 BS |
1522 | for (i = 0; i < n; i++) |
1523 | { | |
1524 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1525 | if (n > 1) | |
1526 | fprintf (f, " [%d]", i); | |
1527 | fprintf (f, "):"); | |
1528 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1529 | } | |
058e97ec VM |
1530 | } |
1531 | ||
1532 | /* Print live ranges of allocno A to stderr. */ | |
1533 | void | |
1534 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1535 | { | |
1536 | print_allocno_live_ranges (stderr, a); | |
1537 | } | |
1538 | ||
1539 | /* Print live ranges of all allocnos to file F. */ | |
1540 | static void | |
1541 | print_live_ranges (FILE *f) | |
1542 | { | |
1543 | ira_allocno_t a; | |
1544 | ira_allocno_iterator ai; | |
1545 | ||
1546 | FOR_EACH_ALLOCNO (a, ai) | |
1547 | print_allocno_live_ranges (f, a); | |
1548 | } | |
1549 | ||
1550 | /* Print live ranges of all allocnos to stderr. */ | |
1551 | void | |
1552 | ira_debug_live_ranges (void) | |
1553 | { | |
1554 | print_live_ranges (stderr); | |
1555 | } | |
1556 | ||
1557 | /* The main entry function creates live ranges, set up | |
ac0ab4f7 | 1558 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
058e97ec VM |
1559 | calculate register pressure info. */ |
1560 | void | |
1561 | ira_create_allocno_live_ranges (void) | |
1562 | { | |
ac0ab4f7 BS |
1563 | objects_live = sparseset_alloc (ira_objects_num); |
1564 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
058e97ec | 1565 | curr_point = 0; |
cb1ca6ac VM |
1566 | last_call_num = 0; |
1567 | allocno_saved_at_call | |
1568 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1569 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
058e97ec VM |
1570 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1571 | process_bb_node_lives); | |
1572 | ira_max_point = curr_point; | |
1573 | create_start_finish_chains (); | |
1574 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1575 | print_live_ranges (ira_dump_file); | |
1576 | /* Clean up. */ | |
cb1ca6ac | 1577 | ira_free (allocno_saved_at_call); |
ac0ab4f7 BS |
1578 | sparseset_free (objects_live); |
1579 | sparseset_free (allocnos_processed); | |
058e97ec VM |
1580 | } |
1581 | ||
b15a7ae6 VM |
1582 | /* Compress allocno live ranges. */ |
1583 | void | |
1584 | ira_compress_allocno_live_ranges (void) | |
1585 | { | |
1586 | remove_some_program_points_and_update_live_ranges (); | |
1587 | ira_rebuild_start_finish_chains (); | |
1588 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1589 | { | |
1590 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1591 | print_live_ranges (ira_dump_file); | |
1592 | } | |
1593 | } | |
1594 | ||
058e97ec VM |
1595 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1596 | void | |
1597 | ira_finish_allocno_live_ranges (void) | |
1598 | { | |
1599 | ira_free (ira_finish_point_ranges); | |
1600 | ira_free (ira_start_point_ranges); | |
1601 | } |