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058e97ec | 1 | /* IRA processing allocno lives to build allocno live ranges. |
5624e564 | 2 | Copyright (C) 2006-2015 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
c7131fb2 | 24 | #include "backend.h" |
058e97ec | 25 | #include "rtl.h" |
c7131fb2 AM |
26 | #include "df.h" |
27 | #include "regs.h" | |
058e97ec VM |
28 | #include "tm_p.h" |
29 | #include "target.h" | |
30 | #include "flags.h" | |
cf0c2a60 | 31 | #include "except.h" |
058e97ec VM |
32 | #include "insn-config.h" |
33 | #include "recog.h" | |
718f9c0f | 34 | #include "diagnostic-core.h" |
058e97ec | 35 | #include "params.h" |
058e97ec | 36 | #include "sparseset.h" |
c7131fb2 AM |
37 | #include "cfgloop.h" |
38 | #include "ira.h" | |
39 | #include "alloc-pool.h" | |
058e97ec VM |
40 | #include "ira-int.h" |
41 | ||
42 | /* The code in this file is similar to one in global but the code | |
43 | works on the allocno basis and creates live ranges instead of | |
44 | pseudo-register conflicts. */ | |
45 | ||
46 | /* Program points are enumerated by numbers from range | |
47 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
48 | points than insns. Program points are places in the program where | |
49 | liveness info can be changed. In most general case (there are more | |
50 | complicated cases too) some program points correspond to places | |
51 | where input operand dies and other ones correspond to places where | |
52 | output operands are born. */ | |
53 | int ira_max_point; | |
54 | ||
55 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
56 | live ranges with given start/finish point. */ | |
b14151b5 | 57 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec VM |
58 | |
59 | /* Number of the current program point. */ | |
60 | static int curr_point; | |
61 | ||
62 | /* Point where register pressure excess started or -1 if there is no | |
63 | register pressure excess. Excess pressure for a register class at | |
64 | some point means that there are more allocnos of given register | |
65 | class living at the point than number of hard-registers of the | |
1756cb66 VM |
66 | class available for the allocation. It is defined only for |
67 | pressure classes. */ | |
058e97ec VM |
68 | static int high_pressure_start_point[N_REG_CLASSES]; |
69 | ||
ac0ab4f7 BS |
70 | /* Objects live at current point in the scan. */ |
71 | static sparseset objects_live; | |
72 | ||
73 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
74 | multiple times. */ | |
75 | static sparseset allocnos_processed; | |
058e97ec VM |
76 | |
77 | /* Set of hard regs (except eliminable ones) currently live. */ | |
78 | static HARD_REG_SET hard_regs_live; | |
79 | ||
80 | /* The loop tree node corresponding to the current basic block. */ | |
81 | static ira_loop_tree_node_t curr_bb_node; | |
82 | ||
cb1ca6ac VM |
83 | /* The number of the last processed call. */ |
84 | static int last_call_num; | |
85 | /* The number of last call at which given allocno was saved. */ | |
86 | static int *allocno_saved_at_call; | |
87 | ||
9840b2fa RS |
88 | /* The value of get_preferred_alternatives for the current instruction, |
89 | supplemental to recog_data. */ | |
90 | static alternative_mask preferred_alternatives; | |
91 | ||
ac0ab4f7 BS |
92 | /* Record the birth of hard register REGNO, updating hard_regs_live and |
93 | hard reg conflict information for living allocnos. */ | |
058e97ec | 94 | static void |
3c55880a | 95 | make_hard_regno_born (int regno) |
058e97ec VM |
96 | { |
97 | unsigned int i; | |
058e97ec | 98 | |
3c55880a | 99 | SET_HARD_REG_BIT (hard_regs_live, regno); |
ac0ab4f7 | 100 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 101 | { |
ac0ab4f7 | 102 | ira_object_t obj = ira_object_id_map[i]; |
1756cb66 | 103 | |
a49ae217 BS |
104 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
105 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
058e97ec | 106 | } |
3c55880a BS |
107 | } |
108 | ||
109 | /* Process the death of hard register REGNO. This updates | |
110 | hard_regs_live. */ | |
111 | static void | |
112 | make_hard_regno_dead (int regno) | |
113 | { | |
114 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); | |
115 | } | |
116 | ||
ac0ab4f7 BS |
117 | /* Record the birth of object OBJ. Set a bit for it in objects_live, |
118 | start a new live range for it if necessary and update hard register | |
119 | conflicts. */ | |
3c55880a | 120 | static void |
ac0ab4f7 | 121 | make_object_born (ira_object_t obj) |
3c55880a | 122 | { |
ac0ab4f7 | 123 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
3c55880a | 124 | |
ac0ab4f7 | 125 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
a49ae217 BS |
126 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
127 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); | |
3c55880a | 128 | |
ac0ab4f7 BS |
129 | if (lr == NULL |
130 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
131 | ira_add_live_range_to_object (obj, curr_point, -1); | |
058e97ec VM |
132 | } |
133 | ||
ac0ab4f7 BS |
134 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
135 | associated with object OBJ. */ | |
058e97ec | 136 | static void |
ac0ab4f7 | 137 | update_allocno_pressure_excess_length (ira_object_t obj) |
058e97ec | 138 | { |
ac0ab4f7 | 139 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
7db7ed3c | 140 | int start, i; |
1756cb66 | 141 | enum reg_class aclass, pclass, cl; |
b14151b5 | 142 | live_range_t p; |
058e97ec | 143 | |
1756cb66 VM |
144 | aclass = ALLOCNO_CLASS (a); |
145 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 146 | for (i = 0; |
1756cb66 | 147 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
148 | i++) |
149 | { | |
1756cb66 VM |
150 | if (! ira_reg_pressure_class_p[cl]) |
151 | continue; | |
7db7ed3c VM |
152 | if (high_pressure_start_point[cl] < 0) |
153 | continue; | |
9140d27b | 154 | p = OBJECT_LIVE_RANGES (obj); |
7db7ed3c VM |
155 | ira_assert (p != NULL); |
156 | start = (high_pressure_start_point[cl] > p->start | |
157 | ? high_pressure_start_point[cl] : p->start); | |
158 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
159 | } | |
058e97ec VM |
160 | } |
161 | ||
ac0ab4f7 BS |
162 | /* Process the death of object OBJ, which is associated with allocno |
163 | A. This finishes the current live range for it. */ | |
058e97ec | 164 | static void |
ac0ab4f7 | 165 | make_object_dead (ira_object_t obj) |
058e97ec | 166 | { |
ac0ab4f7 | 167 | live_range_t lr; |
058e97ec | 168 | |
ac0ab4f7 BS |
169 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
170 | lr = OBJECT_LIVE_RANGES (obj); | |
171 | ira_assert (lr != NULL); | |
172 | lr->finish = curr_point; | |
173 | update_allocno_pressure_excess_length (obj); | |
058e97ec VM |
174 | } |
175 | ||
1756cb66 | 176 | /* The current register pressures for each pressure class for the current |
058e97ec VM |
177 | basic block. */ |
178 | static int curr_reg_pressure[N_REG_CLASSES]; | |
179 | ||
1756cb66 VM |
180 | /* Record that register pressure for PCLASS increased by N registers. |
181 | Update the current register pressure, maximal register pressure for | |
182 | the current BB and the start point of the register pressure | |
183 | excess. */ | |
058e97ec | 184 | static void |
1756cb66 | 185 | inc_register_pressure (enum reg_class pclass, int n) |
058e97ec | 186 | { |
7db7ed3c | 187 | int i; |
3c55880a | 188 | enum reg_class cl; |
058e97ec | 189 | |
7db7ed3c | 190 | for (i = 0; |
1756cb66 | 191 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
192 | i++) |
193 | { | |
1756cb66 VM |
194 | if (! ira_reg_pressure_class_p[cl]) |
195 | continue; | |
3c55880a | 196 | curr_reg_pressure[cl] += n; |
7db7ed3c | 197 | if (high_pressure_start_point[cl] < 0 |
f508f827 | 198 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
7db7ed3c VM |
199 | high_pressure_start_point[cl] = curr_point; |
200 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
201 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
202 | } | |
058e97ec VM |
203 | } |
204 | ||
1756cb66 VM |
205 | /* Record that register pressure for PCLASS has decreased by NREGS |
206 | registers; update current register pressure, start point of the | |
207 | register pressure excess, and register pressure excess length for | |
208 | living allocnos. */ | |
3c55880a | 209 | |
058e97ec | 210 | static void |
1756cb66 | 211 | dec_register_pressure (enum reg_class pclass, int nregs) |
058e97ec | 212 | { |
7db7ed3c VM |
213 | int i; |
214 | unsigned int j; | |
3c55880a BS |
215 | enum reg_class cl; |
216 | bool set_p = false; | |
058e97ec | 217 | |
3c55880a | 218 | for (i = 0; |
1756cb66 | 219 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
3c55880a | 220 | i++) |
058e97ec | 221 | { |
1756cb66 VM |
222 | if (! ira_reg_pressure_class_p[cl]) |
223 | continue; | |
3c55880a BS |
224 | curr_reg_pressure[cl] -= nregs; |
225 | ira_assert (curr_reg_pressure[cl] >= 0); | |
226 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 227 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
3c55880a BS |
228 | set_p = true; |
229 | } | |
230 | if (set_p) | |
231 | { | |
ac0ab4f7 BS |
232 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
233 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
7db7ed3c | 234 | for (i = 0; |
1756cb66 | 235 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c | 236 | i++) |
1756cb66 VM |
237 | { |
238 | if (! ira_reg_pressure_class_p[cl]) | |
239 | continue; | |
240 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 241 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
1756cb66 VM |
242 | high_pressure_start_point[cl] = -1; |
243 | } | |
058e97ec | 244 | } |
058e97ec VM |
245 | } |
246 | ||
e384e6b5 BS |
247 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
248 | and occupies only one object. Return false if we have no information. */ | |
249 | static bool | |
250 | pseudo_regno_single_word_and_live_p (int regno) | |
251 | { | |
252 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
253 | ira_object_t obj; | |
254 | ||
255 | if (a == NULL) | |
256 | return false; | |
257 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
258 | return false; | |
259 | ||
260 | obj = ALLOCNO_OBJECT (a, 0); | |
261 | ||
262 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
263 | } | |
264 | ||
3c55880a BS |
265 | /* Mark the pseudo register REGNO as live. Update all information about |
266 | live ranges and register pressure. */ | |
058e97ec | 267 | static void |
3c55880a | 268 | mark_pseudo_regno_live (int regno) |
058e97ec | 269 | { |
3c55880a | 270 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
1756cb66 | 271 | enum reg_class pclass; |
ac0ab4f7 | 272 | int i, n, nregs; |
058e97ec | 273 | |
3c55880a BS |
274 | if (a == NULL) |
275 | return; | |
058e97ec | 276 | |
3c55880a BS |
277 | /* Invalidate because it is referenced. */ |
278 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 279 | |
ac0ab4f7 | 280 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
281 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
282 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
283 | if (n > 1) |
284 | { | |
285 | /* We track every subobject separately. */ | |
286 | gcc_assert (nregs == n); | |
287 | nregs = 1; | |
288 | } | |
289 | ||
290 | for (i = 0; i < n; i++) | |
291 | { | |
292 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1756cb66 | 293 | |
ac0ab4f7 BS |
294 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
295 | continue; | |
296 | ||
1756cb66 | 297 | inc_register_pressure (pclass, nregs); |
ac0ab4f7 BS |
298 | make_object_born (obj); |
299 | } | |
300 | } | |
301 | ||
302 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
303 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
304 | indicates the low part. */ | |
305 | static void | |
306 | mark_pseudo_regno_subword_live (int regno, int subword) | |
307 | { | |
308 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 309 | int n; |
1756cb66 | 310 | enum reg_class pclass; |
ac0ab4f7 BS |
311 | ira_object_t obj; |
312 | ||
313 | if (a == NULL) | |
3c55880a BS |
314 | return; |
315 | ||
ac0ab4f7 BS |
316 | /* Invalidate because it is referenced. */ |
317 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
318 | ||
319 | n = ALLOCNO_NUM_OBJECTS (a); | |
320 | if (n == 1) | |
321 | { | |
322 | mark_pseudo_regno_live (regno); | |
323 | return; | |
324 | } | |
325 | ||
1756cb66 | 326 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
327 | gcc_assert |
328 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
329 | obj = ALLOCNO_OBJECT (a, subword); |
330 | ||
331 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
332 | return; | |
333 | ||
51935358 | 334 | inc_register_pressure (pclass, 1); |
ac0ab4f7 | 335 | make_object_born (obj); |
3c55880a BS |
336 | } |
337 | ||
ac0ab4f7 BS |
338 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
339 | this register, record how many consecutive hardware registers it | |
340 | actually needs. */ | |
3c55880a BS |
341 | static void |
342 | mark_hard_reg_live (rtx reg) | |
343 | { | |
344 | int regno = REGNO (reg); | |
345 | ||
346 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec | 347 | { |
dc8afb70 | 348 | int last = END_REGNO (reg); |
1756cb66 | 349 | enum reg_class aclass, pclass; |
058e97ec VM |
350 | |
351 | while (regno < last) | |
352 | { | |
353 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
354 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
355 | { | |
1756cb66 VM |
356 | aclass = ira_hard_regno_allocno_class[regno]; |
357 | pclass = ira_pressure_class_translate[aclass]; | |
358 | inc_register_pressure (pclass, 1); | |
3c55880a | 359 | make_hard_regno_born (regno); |
058e97ec VM |
360 | } |
361 | regno++; | |
362 | } | |
363 | } | |
364 | } | |
365 | ||
579c1bf3 BS |
366 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
367 | register number; ORIG_REG is the access in the insn, which may be a | |
368 | subreg. */ | |
369 | static void | |
370 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
371 | { | |
372 | if (df_read_modify_subreg_p (orig_reg)) | |
373 | { | |
374 | mark_pseudo_regno_subword_live (regno, | |
375 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
376 | } | |
377 | else | |
378 | mark_pseudo_regno_live (regno); | |
379 | } | |
380 | ||
3517d3a0 VM |
381 | /* Mark the register referenced by use or def REF as live. */ |
382 | static void | |
57512f53 | 383 | mark_ref_live (df_ref ref) |
058e97ec | 384 | { |
ac0ab4f7 BS |
385 | rtx reg = DF_REF_REG (ref); |
386 | rtx orig_reg = reg; | |
3517d3a0 | 387 | |
3517d3a0 VM |
388 | if (GET_CODE (reg) == SUBREG) |
389 | reg = SUBREG_REG (reg); | |
ac0ab4f7 | 390 | |
3c55880a | 391 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 392 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
3c55880a BS |
393 | else |
394 | mark_hard_reg_live (reg); | |
058e97ec VM |
395 | } |
396 | ||
3c55880a BS |
397 | /* Mark the pseudo register REGNO as dead. Update all information about |
398 | live ranges and register pressure. */ | |
058e97ec | 399 | static void |
3c55880a | 400 | mark_pseudo_regno_dead (int regno) |
058e97ec | 401 | { |
3c55880a | 402 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
ac0ab4f7 | 403 | int n, i, nregs; |
3c55880a | 404 | enum reg_class cl; |
058e97ec | 405 | |
3c55880a BS |
406 | if (a == NULL) |
407 | return; | |
058e97ec | 408 | |
3c55880a BS |
409 | /* Invalidate because it is referenced. */ |
410 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 411 | |
ac0ab4f7 | 412 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
413 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
414 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
415 | if (n > 1) |
416 | { | |
417 | /* We track every subobject separately. */ | |
418 | gcc_assert (nregs == n); | |
419 | nregs = 1; | |
420 | } | |
421 | for (i = 0; i < n; i++) | |
422 | { | |
423 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
424 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
425 | continue; | |
426 | ||
427 | dec_register_pressure (cl, nregs); | |
428 | make_object_dead (obj); | |
429 | } | |
430 | } | |
431 | ||
432 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
433 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
434 | static void | |
435 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
436 | { | |
437 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 438 | int n; |
ac0ab4f7 BS |
439 | enum reg_class cl; |
440 | ira_object_t obj; | |
441 | ||
442 | if (a == NULL) | |
443 | return; | |
444 | ||
445 | /* Invalidate because it is referenced. */ | |
446 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
447 | ||
448 | n = ALLOCNO_NUM_OBJECTS (a); | |
449 | if (n == 1) | |
450 | /* The allocno as a whole doesn't die in this case. */ | |
3c55880a BS |
451 | return; |
452 | ||
1756cb66 | 453 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
454 | gcc_assert |
455 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
456 | |
457 | obj = ALLOCNO_OBJECT (a, subword); | |
458 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
459 | return; | |
3c55880a | 460 | |
ac0ab4f7 BS |
461 | dec_register_pressure (cl, 1); |
462 | make_object_dead (obj); | |
3c55880a BS |
463 | } |
464 | ||
ac0ab4f7 BS |
465 | /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
466 | register. */ | |
3c55880a BS |
467 | static void |
468 | mark_hard_reg_dead (rtx reg) | |
469 | { | |
470 | int regno = REGNO (reg); | |
471 | ||
472 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec | 473 | { |
53d1bae9 | 474 | int last = END_REGNO (reg); |
1756cb66 | 475 | enum reg_class aclass, pclass; |
058e97ec VM |
476 | |
477 | while (regno < last) | |
478 | { | |
479 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
480 | { | |
1756cb66 VM |
481 | aclass = ira_hard_regno_allocno_class[regno]; |
482 | pclass = ira_pressure_class_translate[aclass]; | |
483 | dec_register_pressure (pclass, 1); | |
3c55880a | 484 | make_hard_regno_dead (regno); |
058e97ec VM |
485 | } |
486 | regno++; | |
487 | } | |
488 | } | |
489 | } | |
490 | ||
579c1bf3 BS |
491 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
492 | register number; ORIG_REG is the access in the insn, which may be a | |
493 | subreg. */ | |
494 | static void | |
495 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
496 | { | |
497 | if (df_read_modify_subreg_p (orig_reg)) | |
498 | { | |
499 | mark_pseudo_regno_subword_dead (regno, | |
500 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
501 | } | |
502 | else | |
503 | mark_pseudo_regno_dead (regno); | |
504 | } | |
505 | ||
3517d3a0 VM |
506 | /* Mark the register referenced by definition DEF as dead, if the |
507 | definition is a total one. */ | |
508 | static void | |
57512f53 | 509 | mark_ref_dead (df_ref def) |
3517d3a0 | 510 | { |
ac0ab4f7 BS |
511 | rtx reg = DF_REF_REG (def); |
512 | rtx orig_reg = reg; | |
3517d3a0 | 513 | |
ac0ab4f7 | 514 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
3517d3a0 VM |
515 | return; |
516 | ||
3517d3a0 VM |
517 | if (GET_CODE (reg) == SUBREG) |
518 | reg = SUBREG_REG (reg); | |
ac0ab4f7 BS |
519 | |
520 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
521 | && (GET_CODE (orig_reg) != SUBREG | |
522 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
523 | || !df_read_modify_subreg_p (orig_reg))) | |
524 | return; | |
525 | ||
3c55880a | 526 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 527 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
3c55880a BS |
528 | else |
529 | mark_hard_reg_dead (reg); | |
3517d3a0 VM |
530 | } |
531 | ||
579c1bf3 BS |
532 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
533 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
073a8998 | 534 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
579c1bf3 BS |
535 | Advance the current program point before making the conflict if |
536 | ADVANCE_P. Return TRUE if we will need to advance the current | |
537 | program point. */ | |
3517d3a0 | 538 | static bool |
579c1bf3 BS |
539 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
540 | bool advance_p) | |
3517d3a0 | 541 | { |
579c1bf3 | 542 | rtx orig_reg = reg; |
22c02455 | 543 | ira_allocno_t a; |
3517d3a0 | 544 | |
22c02455 VM |
545 | if (GET_CODE (reg) == SUBREG) |
546 | reg = SUBREG_REG (reg); | |
b8698a0f | 547 | |
22c02455 VM |
548 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
549 | return advance_p; | |
b8698a0f | 550 | |
22c02455 | 551 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
1756cb66 | 552 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
22c02455 | 553 | return advance_p; |
3517d3a0 | 554 | |
22c02455 VM |
555 | if (advance_p) |
556 | curr_point++; | |
3517d3a0 | 557 | |
579c1bf3 BS |
558 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
559 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
560 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
561 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
22c02455 VM |
562 | |
563 | return false; | |
564 | } | |
3517d3a0 | 565 | |
22c02455 VM |
566 | /* Check and make if necessary conflicts for pseudo DREG of class |
567 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
073a8998 | 568 | ORIG_DREG is the rtx actually accessed, it may be identical to |
579c1bf3 BS |
569 | DREG or a subreg of it. Advance the current program point before |
570 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
571 | advance the current program point. */ | |
22c02455 | 572 | static bool |
579c1bf3 BS |
573 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
574 | enum reg_class def_cl, int use, | |
575 | enum reg_class use_cl, bool advance_p) | |
22c02455 VM |
576 | { |
577 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
578 | return advance_p; | |
b8698a0f | 579 | |
22c02455 | 580 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
579c1bf3 BS |
581 | use_cl, dreg, orig_dreg, advance_p); |
582 | ||
22c02455 VM |
583 | /* Reload may end up swapping commutative operands, so you |
584 | have to take both orderings into account. The | |
585 | constraints for the two operands can be completely | |
586 | different. (Indeed, if the constraints for the two | |
587 | operands are the same for all alternatives, there's no | |
588 | point marking them as commutative.) */ | |
dc344e87 | 589 | if (use < recog_data.n_operands - 1 |
22c02455 VM |
590 | && recog_data.constraints[use][0] == '%') |
591 | advance_p | |
592 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
579c1bf3 | 593 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
594 | if (use >= 1 |
595 | && recog_data.constraints[use - 1][0] == '%') | |
596 | advance_p | |
597 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
579c1bf3 | 598 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
599 | return advance_p; |
600 | } | |
601 | ||
602 | /* Check and make if necessary conflicts for definition DEF of class | |
603 | DEF_CL of the current insn with input operands. Process only | |
604 | constraints of alternative ALT. */ | |
605 | static void | |
606 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
607 | { | |
608 | int use, use_match; | |
609 | ira_allocno_t a; | |
610 | enum reg_class use_cl, acl; | |
611 | bool advance_p; | |
612 | rtx dreg = recog_data.operand[def]; | |
579c1bf3 | 613 | rtx orig_dreg = dreg; |
b8698a0f | 614 | |
22c02455 VM |
615 | if (def_cl == NO_REGS) |
616 | return; | |
b8698a0f | 617 | |
22c02455 VM |
618 | if (GET_CODE (dreg) == SUBREG) |
619 | dreg = SUBREG_REG (dreg); | |
b8698a0f | 620 | |
22c02455 VM |
621 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
622 | return; | |
b8698a0f | 623 | |
22c02455 | 624 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
1756cb66 | 625 | acl = ALLOCNO_CLASS (a); |
22c02455 VM |
626 | if (! reg_classes_intersect_p (acl, def_cl)) |
627 | return; | |
b8698a0f | 628 | |
22c02455 | 629 | advance_p = true; |
b8698a0f | 630 | |
29d70a0f | 631 | int n_operands = recog_data.n_operands; |
1145837d | 632 | const operand_alternative *op_alt = &recog_op_alt[alt * n_operands]; |
29d70a0f | 633 | for (use = 0; use < n_operands; use++) |
22c02455 | 634 | { |
002b2dee BS |
635 | int alt1; |
636 | ||
22c02455 | 637 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
7ba06dee | 638 | continue; |
b8698a0f | 639 | |
29d70a0f | 640 | if (op_alt[use].anything_ok) |
22c02455 | 641 | use_cl = ALL_REGS; |
3517d3a0 | 642 | else |
29d70a0f | 643 | use_cl = op_alt[use].cl; |
b8698a0f | 644 | |
002b2dee BS |
645 | /* If there's any alternative that allows USE to match DEF, do not |
646 | record a conflict. If that causes us to create an invalid | |
ac0ab4f7 | 647 | instruction due to the earlyclobber, reload must fix it up. */ |
002b2dee | 648 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
29d70a0f | 649 | { |
9840b2fa | 650 | if (!TEST_BIT (preferred_alternatives, alt1)) |
5f2e0797 | 651 | continue; |
1145837d RS |
652 | const operand_alternative *op_alt1 |
653 | = &recog_op_alt[alt1 * n_operands]; | |
29d70a0f RS |
654 | if (op_alt1[use].matches == def |
655 | || (use < n_operands - 1 | |
656 | && recog_data.constraints[use][0] == '%' | |
657 | && op_alt1[use + 1].matches == def) | |
658 | || (use >= 1 | |
659 | && recog_data.constraints[use - 1][0] == '%' | |
660 | && op_alt1[use - 1].matches == def)) | |
661 | break; | |
662 | } | |
002b2dee BS |
663 | |
664 | if (alt1 < recog_data.n_alternatives) | |
665 | continue; | |
666 | ||
579c1bf3 BS |
667 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
668 | use, use_cl, advance_p); | |
b8698a0f | 669 | |
29d70a0f | 670 | if ((use_match = op_alt[use].matches) >= 0) |
22c02455 VM |
671 | { |
672 | if (use_match == def) | |
7ba06dee | 673 | continue; |
b8698a0f | 674 | |
29d70a0f | 675 | if (op_alt[use_match].anything_ok) |
22c02455 VM |
676 | use_cl = ALL_REGS; |
677 | else | |
29d70a0f | 678 | use_cl = op_alt[use_match].cl; |
579c1bf3 BS |
679 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
680 | use, use_cl, advance_p); | |
22c02455 | 681 | } |
3517d3a0 | 682 | } |
22c02455 VM |
683 | } |
684 | ||
685 | /* Make conflicts of early clobber pseudo registers of the current | |
686 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
687 | checking classes of the constraints and pseudos because otherwise | |
688 | significant code degradation is possible for some targets. */ | |
689 | static void | |
690 | make_early_clobber_and_input_conflicts (void) | |
691 | { | |
692 | int alt; | |
693 | int def, def_match; | |
694 | enum reg_class def_cl; | |
695 | ||
29d70a0f RS |
696 | int n_alternatives = recog_data.n_alternatives; |
697 | int n_operands = recog_data.n_operands; | |
1145837d | 698 | const operand_alternative *op_alt = recog_op_alt; |
29d70a0f | 699 | for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands) |
9840b2fa | 700 | if (TEST_BIT (preferred_alternatives, alt)) |
5f2e0797 RS |
701 | for (def = 0; def < n_operands; def++) |
702 | { | |
703 | def_cl = NO_REGS; | |
704 | if (op_alt[def].earlyclobber) | |
705 | { | |
706 | if (op_alt[def].anything_ok) | |
707 | def_cl = ALL_REGS; | |
708 | else | |
709 | def_cl = op_alt[def].cl; | |
710 | check_and_make_def_conflict (alt, def, def_cl); | |
711 | } | |
712 | if ((def_match = op_alt[def].matches) >= 0 | |
713 | && (op_alt[def_match].earlyclobber | |
714 | || op_alt[def].earlyclobber)) | |
715 | { | |
716 | if (op_alt[def_match].anything_ok) | |
717 | def_cl = ALL_REGS; | |
718 | else | |
719 | def_cl = op_alt[def_match].cl; | |
720 | check_and_make_def_conflict (alt, def, def_cl); | |
721 | } | |
722 | } | |
22c02455 VM |
723 | } |
724 | ||
725 | /* Mark early clobber hard registers of the current INSN as live (if | |
726 | LIVE_P) or dead. Return true if there are such registers. */ | |
727 | static bool | |
070a1983 | 728 | mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p) |
22c02455 | 729 | { |
bfac633a | 730 | df_ref def; |
22c02455 | 731 | bool set_p = false; |
3517d3a0 | 732 | |
bfac633a RS |
733 | FOR_EACH_INSN_DEF (def, insn) |
734 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)) | |
3517d3a0 | 735 | { |
bfac633a | 736 | rtx dreg = DF_REF_REG (def); |
b8698a0f | 737 | |
3517d3a0 VM |
738 | if (GET_CODE (dreg) == SUBREG) |
739 | dreg = SUBREG_REG (dreg); | |
740 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
741 | continue; | |
742 | ||
743 | /* Hard register clobbers are believed to be early clobber | |
744 | because there is no way to say that non-operand hard | |
b8698a0f | 745 | register clobbers are not early ones. */ |
3517d3a0 | 746 | if (live_p) |
bfac633a | 747 | mark_ref_live (def); |
3517d3a0 | 748 | else |
bfac633a | 749 | mark_ref_dead (def); |
3517d3a0 VM |
750 | set_p = true; |
751 | } | |
752 | ||
753 | return set_p; | |
754 | } | |
755 | ||
058e97ec VM |
756 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
757 | it is so, the function returns the class of the hard register. | |
758 | Otherwise it returns NO_REGS. */ | |
759 | static enum reg_class | |
760 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
761 | { | |
4cc8d9d2 | 762 | int c; |
058e97ec | 763 | enum reg_class cl, next_cl; |
777e635f | 764 | enum constraint_num cn; |
058e97ec VM |
765 | |
766 | cl = NO_REGS; | |
9840b2fa | 767 | alternative_mask preferred = preferred_alternatives; |
4cc8d9d2 RS |
768 | for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)) |
769 | if (c == '#') | |
9840b2fa | 770 | preferred &= ~ALTERNATIVE_BIT (0); |
058e97ec | 771 | else if (c == ',') |
9840b2fa RS |
772 | preferred >>= 1; |
773 | else if (preferred & 1) | |
058e97ec VM |
774 | switch (c) |
775 | { | |
8677664e RS |
776 | case 'g': |
777 | return NO_REGS; | |
b8698a0f | 778 | |
8677664e | 779 | default: |
b58923e2 | 780 | /* ??? Is this the best way to handle memory constraints? */ |
777e635f RS |
781 | cn = lookup_constraint (constraints); |
782 | if (insn_extra_memory_constraint (cn) | |
783 | || insn_extra_address_constraint (cn)) | |
b58923e2 | 784 | return NO_REGS; |
777e635f | 785 | if (constraint_satisfied_p (op, cn) |
b58923e2 RS |
786 | || (equiv_const != NULL_RTX |
787 | && CONSTANT_P (equiv_const) | |
777e635f | 788 | && constraint_satisfied_p (equiv_const, cn))) |
b58923e2 | 789 | return NO_REGS; |
8677664e | 790 | next_cl = reg_class_for_constraint (cn); |
b58923e2 RS |
791 | if (next_cl == NO_REGS) |
792 | break; | |
c9d74da6 RS |
793 | if (cl == NO_REGS |
794 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
795 | : (ira_class_singleton[cl][GET_MODE (op)] | |
796 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
797 | return NO_REGS; |
798 | cl = next_cl; | |
799 | break; | |
b8698a0f | 800 | |
058e97ec VM |
801 | case '0': case '1': case '2': case '3': case '4': |
802 | case '5': case '6': case '7': case '8': case '9': | |
803 | next_cl | |
804 | = single_reg_class (recog_data.constraints[c - '0'], | |
805 | recog_data.operand[c - '0'], NULL_RTX); | |
c9d74da6 RS |
806 | if (cl == NO_REGS |
807 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
808 | : (ira_class_singleton[cl][GET_MODE (op)] | |
809 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
810 | return NO_REGS; |
811 | cl = next_cl; | |
812 | break; | |
058e97ec VM |
813 | } |
814 | return cl; | |
815 | } | |
816 | ||
817 | /* The function checks that operand OP_NUM of the current insn can use | |
818 | only one hard register. If it is so, the function returns the | |
819 | class of the hard register. Otherwise it returns NO_REGS. */ | |
820 | static enum reg_class | |
821 | single_reg_operand_class (int op_num) | |
822 | { | |
823 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
824 | return NO_REGS; | |
825 | return single_reg_class (recog_data.constraints[op_num], | |
826 | recog_data.operand[op_num], NULL_RTX); | |
827 | } | |
828 | ||
ce18efcb VM |
829 | /* The function sets up hard register set *SET to hard registers which |
830 | might be used by insn reloads because the constraints are too | |
831 | strict. */ | |
832 | void | |
833 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set) | |
834 | { | |
4cc8d9d2 | 835 | int i, c, regno = 0; |
ce18efcb VM |
836 | enum reg_class cl; |
837 | rtx op; | |
ef4bddc2 | 838 | machine_mode mode; |
ce18efcb VM |
839 | |
840 | CLEAR_HARD_REG_SET (*set); | |
841 | for (i = 0; i < recog_data.n_operands; i++) | |
842 | { | |
843 | op = recog_data.operand[i]; | |
844 | ||
845 | if (GET_CODE (op) == SUBREG) | |
846 | op = SUBREG_REG (op); | |
b8698a0f | 847 | |
ce18efcb VM |
848 | if (GET_CODE (op) == SCRATCH |
849 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
850 | { | |
851 | const char *p = recog_data.constraints[i]; | |
852 | ||
853 | mode = (GET_CODE (op) == SCRATCH | |
854 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
855 | cl = NO_REGS; | |
9840b2fa | 856 | alternative_mask preferred = preferred_alternatives; |
4cc8d9d2 RS |
857 | for (; (c = *p); p += CONSTRAINT_LEN (c, p)) |
858 | if (c == '#') | |
9840b2fa | 859 | preferred &= ~ALTERNATIVE_BIT (0); |
ce18efcb | 860 | else if (c == ',') |
9840b2fa RS |
861 | preferred >>= 1; |
862 | else if (preferred & 1) | |
8677664e RS |
863 | { |
864 | cl = reg_class_for_constraint (lookup_constraint (p)); | |
865 | if (cl != NO_REGS) | |
866 | { | |
867 | /* There is no register pressure problem if all of the | |
868 | regs in this class are fixed. */ | |
869 | int regno = ira_class_singleton[cl][mode]; | |
870 | if (regno >= 0) | |
871 | add_to_hard_reg_set (set, mode, regno); | |
872 | } | |
873 | } | |
ce18efcb VM |
874 | } |
875 | } | |
876 | } | |
058e97ec VM |
877 | /* Processes input operands, if IN_P, or output operands otherwise of |
878 | the current insn with FREQ to find allocno which can use only one | |
879 | hard register and makes other currently living allocnos conflicting | |
880 | with the hard register. */ | |
881 | static void | |
882 | process_single_reg_class_operands (bool in_p, int freq) | |
883 | { | |
6d1e1a26 | 884 | int i, regno; |
058e97ec | 885 | unsigned int px; |
11895e28 | 886 | enum reg_class cl; |
058e97ec VM |
887 | rtx operand; |
888 | ira_allocno_t operand_a, a; | |
889 | ||
890 | for (i = 0; i < recog_data.n_operands; i++) | |
891 | { | |
892 | operand = recog_data.operand[i]; | |
893 | if (in_p && recog_data.operand_type[i] != OP_IN | |
894 | && recog_data.operand_type[i] != OP_INOUT) | |
895 | continue; | |
896 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
897 | && recog_data.operand_type[i] != OP_INOUT) | |
898 | continue; | |
899 | cl = single_reg_operand_class (i); | |
900 | if (cl == NO_REGS) | |
901 | continue; | |
902 | ||
903 | operand_a = NULL; | |
904 | ||
905 | if (GET_CODE (operand) == SUBREG) | |
906 | operand = SUBREG_REG (operand); | |
b8698a0f | 907 | |
058e97ec VM |
908 | if (REG_P (operand) |
909 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
910 | { | |
1756cb66 | 911 | enum reg_class aclass; |
058e97ec VM |
912 | |
913 | operand_a = ira_curr_regno_allocno_map[regno]; | |
1756cb66 | 914 | aclass = ALLOCNO_CLASS (operand_a); |
c9d74da6 | 915 | if (ira_class_subset_p[cl][aclass]) |
058e97ec | 916 | { |
6d1e1a26 RS |
917 | /* View the desired allocation of OPERAND as: |
918 | ||
919 | (REG:YMODE YREGNO), | |
920 | ||
921 | a simplification of: | |
922 | ||
923 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
ef4bddc2 | 924 | machine_mode ymode, xmode; |
6d1e1a26 RS |
925 | int xregno, yregno; |
926 | HOST_WIDE_INT offset; | |
927 | ||
928 | xmode = recog_data.operand_mode[i]; | |
c9d74da6 RS |
929 | xregno = ira_class_singleton[cl][xmode]; |
930 | gcc_assert (xregno >= 0); | |
6d1e1a26 RS |
931 | ymode = ALLOCNO_MODE (operand_a); |
932 | offset = subreg_lowpart_offset (ymode, xmode); | |
933 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
934 | if (yregno >= 0 | |
1756cb66 | 935 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
6d1e1a26 RS |
936 | { |
937 | int cost; | |
938 | ||
939 | ira_allocate_and_set_costs | |
940 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
1756cb66 VM |
941 | aclass, 0); |
942 | ira_init_register_move_cost_if_necessary (xmode); | |
943 | cost = freq * (in_p | |
944 | ? ira_register_move_cost[xmode][aclass][cl] | |
945 | : ira_register_move_cost[xmode][cl][aclass]); | |
6d1e1a26 | 946 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
1756cb66 | 947 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
6d1e1a26 | 948 | } |
058e97ec VM |
949 | } |
950 | } | |
951 | ||
ac0ab4f7 | 952 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
058e97ec | 953 | { |
ac0ab4f7 BS |
954 | ira_object_t obj = ira_object_id_map[px]; |
955 | a = OBJECT_ALLOCNO (obj); | |
058e97ec VM |
956 | if (a != operand_a) |
957 | { | |
958 | /* We could increase costs of A instead of making it | |
959 | conflicting with the hard register. But it works worse | |
960 | because it will be spilled in reload in anyway. */ | |
a49ae217 | 961 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
058e97ec | 962 | reg_class_contents[cl]); |
a49ae217 | 963 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
058e97ec VM |
964 | reg_class_contents[cl]); |
965 | } | |
966 | } | |
967 | } | |
968 | } | |
969 | ||
db1a8d98 VM |
970 | /* Return true when one of the predecessor edges of BB is marked with |
971 | EDGE_ABNORMAL_CALL or EDGE_EH. */ | |
972 | static bool | |
973 | bb_has_abnormal_call_pred (basic_block bb) | |
974 | { | |
975 | edge e; | |
976 | edge_iterator ei; | |
b8698a0f | 977 | |
db1a8d98 VM |
978 | FOR_EACH_EDGE (e, ei, bb->preds) |
979 | { | |
980 | if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH)) | |
981 | return true; | |
982 | } | |
983 | return false; | |
984 | } | |
985 | ||
e384e6b5 BS |
986 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
987 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
988 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
989 | static rtx | |
070a1983 | 990 | find_call_crossed_cheap_reg (rtx_insn *insn) |
e384e6b5 BS |
991 | { |
992 | rtx cheap_reg = NULL_RTX; | |
993 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
994 | ||
995 | while (exp != NULL) | |
996 | { | |
997 | rtx x = XEXP (exp, 0); | |
998 | if (GET_CODE (x) == SET) | |
999 | { | |
1000 | exp = x; | |
1001 | break; | |
1002 | } | |
1003 | exp = XEXP (exp, 1); | |
1004 | } | |
1005 | if (exp != NULL) | |
1006 | { | |
1007 | basic_block bb = BLOCK_FOR_INSN (insn); | |
1008 | rtx reg = SET_SRC (exp); | |
c74ef30d | 1009 | rtx_insn *prev = PREV_INSN (insn); |
e384e6b5 BS |
1010 | while (prev && !(INSN_P (prev) |
1011 | && BLOCK_FOR_INSN (prev) != bb)) | |
1012 | { | |
1013 | if (NONDEBUG_INSN_P (prev)) | |
1014 | { | |
1015 | rtx set = single_set (prev); | |
1016 | ||
1017 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
1018 | { | |
1019 | rtx src = SET_SRC (set); | |
1020 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
1021 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1022 | break; | |
1023 | if (!modified_between_p (src, prev, insn)) | |
1024 | cheap_reg = src; | |
1025 | break; | |
1026 | } | |
1027 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1028 | { | |
1029 | rtx dest = SET_DEST (set); | |
1030 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1031 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1032 | break; | |
1033 | if (!modified_between_p (dest, prev, insn)) | |
1034 | cheap_reg = dest; | |
1035 | break; | |
1036 | } | |
1037 | ||
1038 | if (reg_overlap_mentioned_p (reg, PATTERN (prev))) | |
1039 | break; | |
1040 | } | |
1041 | prev = PREV_INSN (prev); | |
1042 | } | |
1043 | } | |
1044 | return cheap_reg; | |
1045 | } | |
1046 | ||
058e97ec VM |
1047 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1048 | update allocno live ranges, allocno hard register conflicts, | |
1049 | intersected calls, and register pressure info for allocnos for the | |
1050 | basic block for and regions containing the basic block. */ | |
1051 | static void | |
1052 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1053 | { | |
acb37d29 | 1054 | int i, freq; |
058e97ec VM |
1055 | unsigned int j; |
1056 | basic_block bb; | |
070a1983 | 1057 | rtx_insn *insn; |
058e97ec | 1058 | bitmap_iterator bi; |
acb37d29 | 1059 | bitmap reg_live_out; |
058e97ec | 1060 | unsigned int px; |
3517d3a0 | 1061 | bool set_p; |
058e97ec VM |
1062 | |
1063 | bb = loop_tree_node->bb; | |
1064 | if (bb != NULL) | |
1065 | { | |
1756cb66 | 1066 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1067 | { |
1756cb66 VM |
1068 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1069 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
058e97ec VM |
1070 | } |
1071 | curr_bb_node = loop_tree_node; | |
bf744527 | 1072 | reg_live_out = df_get_live_out (bb); |
ac0ab4f7 | 1073 | sparseset_clear (objects_live); |
acb37d29 | 1074 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
058e97ec VM |
1075 | AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); |
1076 | AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
1077 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1078 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1079 | { | |
1756cb66 | 1080 | enum reg_class aclass, pclass, cl; |
b8698a0f | 1081 | |
1756cb66 VM |
1082 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1083 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 1084 | for (j = 0; |
1756cb66 | 1085 | (cl = ira_reg_class_super_classes[pclass][j]) |
7db7ed3c VM |
1086 | != LIM_REG_CLASSES; |
1087 | j++) | |
1088 | { | |
1756cb66 VM |
1089 | if (! ira_reg_pressure_class_p[cl]) |
1090 | continue; | |
7db7ed3c VM |
1091 | curr_reg_pressure[cl]++; |
1092 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1093 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1094 | ira_assert (curr_reg_pressure[cl] | |
f508f827 | 1095 | <= ira_class_hard_regs_num[cl]); |
7db7ed3c | 1096 | } |
058e97ec | 1097 | } |
acb37d29 | 1098 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
3c55880a | 1099 | mark_pseudo_regno_live (j); |
b8698a0f | 1100 | |
acb37d29 RS |
1101 | freq = REG_FREQ_FROM_BB (bb); |
1102 | if (freq == 0) | |
1103 | freq = 1; | |
1104 | ||
cb1ca6ac VM |
1105 | /* Invalidate all allocno_saved_at_call entries. */ |
1106 | last_call_num++; | |
1107 | ||
058e97ec | 1108 | /* Scan the code of this basic block, noting which allocnos and |
acb37d29 RS |
1109 | hard regs are born or die. |
1110 | ||
1111 | Note that this loop treats uninitialized values as live until | |
1112 | the beginning of the block. For example, if an instruction | |
1113 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1114 | set, FOO will remain live until the beginning of the block. | |
1115 | Likewise if FOO is not set at all. This is unnecessarily | |
1116 | pessimistic, but it probably doesn't matter much in practice. */ | |
1117 | FOR_BB_INSNS_REVERSE (bb, insn) | |
058e97ec | 1118 | { |
21c6c24f | 1119 | ira_allocno_t a; |
bfac633a | 1120 | df_ref def, use; |
61001a35 | 1121 | bool call_p; |
b8698a0f | 1122 | |
b5b8b0ac | 1123 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec | 1124 | continue; |
b8698a0f | 1125 | |
058e97ec VM |
1126 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1127 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
2608d841 | 1128 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
058e97ec VM |
1129 | curr_point); |
1130 | ||
21c6c24f | 1131 | call_p = CALL_P (insn); |
61001a35 VM |
1132 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
1133 | int regno; | |
1134 | bool clear_pic_use_conflict_p = false; | |
21c6c24f VM |
1135 | /* Processing insn usage in call insn can create conflict |
1136 | with pic pseudo and pic hard reg and that is wrong. | |
1137 | Check this situation and fix it at the end of the insn | |
1138 | processing. */ | |
1139 | if (call_p && pic_offset_table_rtx != NULL_RTX | |
1140 | && (regno = REGNO (pic_offset_table_rtx)) >= FIRST_PSEUDO_REGISTER | |
1141 | && (a = ira_curr_regno_allocno_map[regno]) != NULL) | |
1142 | clear_pic_use_conflict_p | |
1143 | = (find_regno_fusage (insn, USE, REAL_PIC_OFFSET_TABLE_REGNUM) | |
1144 | && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS | |
1145 | (ALLOCNO_OBJECT (a, 0)), | |
1146 | REAL_PIC_OFFSET_TABLE_REGNUM)); | |
61001a35 | 1147 | #endif |
21c6c24f | 1148 | |
acb37d29 RS |
1149 | /* Mark each defined value as live. We need to do this for |
1150 | unused values because they still conflict with quantities | |
1151 | that are live at the time of the definition. | |
1152 | ||
1153 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1154 | references represent the effect of the called function | |
1155 | on a call-clobbered register. Marking the register as | |
1156 | live would stop us from allocating it to a call-crossing | |
1157 | allocno. */ | |
bfac633a RS |
1158 | FOR_EACH_INSN_DEF (def, insn) |
1159 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1160 | mark_ref_live (def); | |
acb37d29 RS |
1161 | |
1162 | /* If INSN has multiple outputs, then any value used in one | |
1163 | of the outputs conflicts with the other outputs. Model this | |
1164 | by making the used value live during the output phase. | |
1165 | ||
1166 | It is unsafe to use !single_set here since it will ignore | |
1167 | an unused output. Just because an output is unused does | |
1168 | not mean the compiler can assume the side effect will not | |
1169 | occur. Consider if ALLOCNO appears in the address of an | |
1170 | output and we reload the output. If we allocate ALLOCNO | |
1171 | to the same hard register as an unused output we could | |
1172 | set the hard register before the output reload insn. */ | |
1173 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
bfac633a | 1174 | FOR_EACH_INSN_USE (use, insn) |
acb37d29 RS |
1175 | { |
1176 | int i; | |
1177 | rtx reg; | |
1178 | ||
bfac633a | 1179 | reg = DF_REF_REG (use); |
acb37d29 RS |
1180 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
1181 | { | |
1182 | rtx set; | |
1183 | ||
1184 | set = XVECEXP (PATTERN (insn), 0, i); | |
1185 | if (GET_CODE (set) == SET | |
1186 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1187 | { | |
1188 | /* After the previous loop, this is a no-op if | |
1189 | REG is contained within SET_DEST (SET). */ | |
bfac633a | 1190 | mark_ref_live (use); |
acb37d29 RS |
1191 | break; |
1192 | } | |
1193 | } | |
1194 | } | |
b8698a0f | 1195 | |
058e97ec | 1196 | extract_insn (insn); |
9840b2fa | 1197 | preferred_alternatives = get_preferred_alternatives (insn); |
1145837d | 1198 | preprocess_constraints (insn); |
acb37d29 | 1199 | process_single_reg_class_operands (false, freq); |
b8698a0f | 1200 | |
acb37d29 | 1201 | /* See which defined values die here. */ |
bfac633a RS |
1202 | FOR_EACH_INSN_DEF (def, insn) |
1203 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1204 | mark_ref_dead (def); | |
058e97ec | 1205 | |
acb37d29 | 1206 | if (call_p) |
058e97ec | 1207 | { |
e384e6b5 BS |
1208 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1209 | there, try to find a pseudo that is live across the call but | |
1210 | can be cheaply reconstructed from the return value. */ | |
1211 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1212 | if (cheap_reg != NULL_RTX) | |
1213 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1214 | ||
cb1ca6ac | 1215 | last_call_num++; |
ac0ab4f7 | 1216 | sparseset_clear (allocnos_processed); |
acb37d29 | 1217 | /* The current set of live allocnos are live across the call. */ |
ac0ab4f7 | 1218 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 1219 | { |
ac0ab4f7 | 1220 | ira_object_t obj = ira_object_id_map[i]; |
21c6c24f | 1221 | a = OBJECT_ALLOCNO (obj); |
ac0ab4f7 | 1222 | int num = ALLOCNO_NUM (a); |
c2ba7e7a RO |
1223 | HARD_REG_SET this_call_used_reg_set; |
1224 | ||
1225 | get_call_reg_set_usage (insn, &this_call_used_reg_set, | |
1226 | call_used_reg_set); | |
b8698a0f | 1227 | |
5feec5c1 VM |
1228 | /* Don't allocate allocnos that cross setjmps or any |
1229 | call, if this function receives a nonlocal | |
1230 | goto. */ | |
1231 | if (cfun->has_nonlocal_label | |
1232 | || find_reg_note (insn, REG_SETJMP, | |
1233 | NULL_RTX) != NULL_RTX) | |
058e97ec | 1234 | { |
a49ae217 BS |
1235 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1236 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
058e97ec | 1237 | } |
cf0c2a60 VM |
1238 | if (can_throw_internal (insn)) |
1239 | { | |
a49ae217 | 1240 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
c2ba7e7a | 1241 | this_call_used_reg_set); |
ac0ab4f7 | 1242 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
c2ba7e7a | 1243 | this_call_used_reg_set); |
cf0c2a60 | 1244 | } |
ac0ab4f7 BS |
1245 | |
1246 | if (sparseset_bit_p (allocnos_processed, num)) | |
1247 | continue; | |
1248 | sparseset_set_bit (allocnos_processed, num); | |
1249 | ||
1250 | if (allocno_saved_at_call[num] != last_call_num) | |
df3e3493 | 1251 | /* Here we are mimicking caller-save.c behavior |
ac0ab4f7 BS |
1252 | which does not save hard register at a call if |
1253 | it was saved on previous call in the same basic | |
1254 | block and the hard register was not mentioned | |
1255 | between the two calls. */ | |
1256 | ALLOCNO_CALL_FREQ (a) += freq; | |
1257 | /* Mark it as saved at the next call. */ | |
1258 | allocno_saved_at_call[num] = last_call_num + 1; | |
1259 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
c2ba7e7a RO |
1260 | IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), |
1261 | this_call_used_reg_set); | |
e384e6b5 BS |
1262 | if (cheap_reg != NULL_RTX |
1263 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1264 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
058e97ec VM |
1265 | } |
1266 | } | |
b8698a0f | 1267 | |
22c02455 VM |
1268 | make_early_clobber_and_input_conflicts (); |
1269 | ||
acb37d29 | 1270 | curr_point++; |
21c6c24f | 1271 | |
acb37d29 | 1272 | /* Mark each used value as live. */ |
bfac633a RS |
1273 | FOR_EACH_INSN_USE (use, insn) |
1274 | mark_ref_live (use); | |
acb37d29 | 1275 | |
acb37d29 | 1276 | process_single_reg_class_operands (true, freq); |
b8698a0f | 1277 | |
22c02455 VM |
1278 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1279 | ||
3517d3a0 VM |
1280 | if (set_p) |
1281 | { | |
22c02455 | 1282 | mark_hard_reg_early_clobbers (insn, false); |
3517d3a0 | 1283 | |
22c02455 | 1284 | /* Mark each hard reg as live again. For example, a |
3517d3a0 VM |
1285 | hard register can be in clobber and in an insn |
1286 | input. */ | |
bfac633a | 1287 | FOR_EACH_INSN_USE (use, insn) |
22c02455 | 1288 | { |
bfac633a | 1289 | rtx ureg = DF_REF_REG (use); |
b8698a0f | 1290 | |
22c02455 VM |
1291 | if (GET_CODE (ureg) == SUBREG) |
1292 | ureg = SUBREG_REG (ureg); | |
1293 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1294 | continue; | |
b8698a0f | 1295 | |
bfac633a | 1296 | mark_ref_live (use); |
22c02455 | 1297 | } |
3517d3a0 | 1298 | } |
058e97ec | 1299 | |
61001a35 | 1300 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
21c6c24f VM |
1301 | if (clear_pic_use_conflict_p) |
1302 | { | |
1303 | regno = REGNO (pic_offset_table_rtx); | |
1304 | a = ira_curr_regno_allocno_map[regno]; | |
1305 | CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a, 0)), | |
1306 | REAL_PIC_OFFSET_TABLE_REGNUM); | |
1307 | CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS | |
1308 | (ALLOCNO_OBJECT (a, 0)), | |
1309 | REAL_PIC_OFFSET_TABLE_REGNUM); | |
1310 | } | |
61001a35 | 1311 | #endif |
058e97ec VM |
1312 | curr_point++; |
1313 | } | |
acb37d29 | 1314 | |
5dbd125c EB |
1315 | if (bb_has_eh_pred (bb)) |
1316 | for (j = 0; ; ++j) | |
1317 | { | |
1318 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1319 | if (regno == INVALID_REGNUM) | |
1320 | break; | |
3c55880a | 1321 | make_hard_regno_born (regno); |
5dbd125c | 1322 | } |
5dbd125c | 1323 | |
acb37d29 RS |
1324 | /* Allocnos can't go in stack regs at the start of a basic block |
1325 | that is reached by an abnormal edge. Likewise for call | |
1326 | clobbered regs, because caller-save, fixup_abnormal_edges and | |
1327 | possibly the table driven EH machinery are not quite ready to | |
1328 | handle such allocnos live across such edges. */ | |
5dbd125c | 1329 | if (bb_has_abnormal_pred (bb)) |
acb37d29 RS |
1330 | { |
1331 | #ifdef STACK_REGS | |
ac0ab4f7 | 1332 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
acb37d29 | 1333 | { |
ac0ab4f7 | 1334 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
1756cb66 | 1335 | |
ac0ab4f7 BS |
1336 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1337 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
acb37d29 RS |
1338 | } |
1339 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
3c55880a | 1340 | make_hard_regno_born (px); |
acb37d29 RS |
1341 | #endif |
1342 | /* No need to record conflicts for call clobbered regs if we | |
1343 | have nonlocal labels around, as we don't ever try to | |
1344 | allocate such regs in this case. */ | |
db1a8d98 | 1345 | if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb)) |
acb37d29 RS |
1346 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
1347 | if (call_used_regs[px]) | |
3c55880a | 1348 | make_hard_regno_born (px); |
acb37d29 RS |
1349 | } |
1350 | ||
ac0ab4f7 BS |
1351 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1352 | make_object_dead (ira_object_id_map[i]); | |
058e97ec VM |
1353 | |
1354 | curr_point++; | |
1355 | ||
1356 | } | |
2b9c63a2 | 1357 | /* Propagate register pressure to upper loop tree nodes. */ |
058e97ec | 1358 | if (loop_tree_node != ira_loop_tree_root) |
1756cb66 | 1359 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1360 | { |
1756cb66 | 1361 | enum reg_class pclass; |
058e97ec | 1362 | |
1756cb66 VM |
1363 | pclass = ira_pressure_classes[i]; |
1364 | if (loop_tree_node->reg_pressure[pclass] | |
1365 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1366 | loop_tree_node->parent->reg_pressure[pclass] | |
1367 | = loop_tree_node->reg_pressure[pclass]; | |
058e97ec VM |
1368 | } |
1369 | } | |
1370 | ||
1371 | /* Create and set up IRA_START_POINT_RANGES and | |
1372 | IRA_FINISH_POINT_RANGES. */ | |
1373 | static void | |
1374 | create_start_finish_chains (void) | |
1375 | { | |
ac0ab4f7 BS |
1376 | ira_object_t obj; |
1377 | ira_object_iterator oi; | |
b14151b5 | 1378 | live_range_t r; |
058e97ec VM |
1379 | |
1380 | ira_start_point_ranges | |
ac0ab4f7 BS |
1381 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1382 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
058e97ec | 1383 | ira_finish_point_ranges |
ac0ab4f7 BS |
1384 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1385 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1386 | FOR_EACH_OBJECT (obj, oi) | |
1387 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1388 | { | |
1389 | r->start_next = ira_start_point_ranges[r->start]; | |
1390 | ira_start_point_ranges[r->start] = r; | |
1391 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
058e97ec | 1392 | ira_finish_point_ranges[r->finish] = r; |
ac0ab4f7 | 1393 | } |
058e97ec VM |
1394 | } |
1395 | ||
1396 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1397 | new live ranges and program points were added as a result if new | |
1398 | insn generation. */ | |
1399 | void | |
1400 | ira_rebuild_start_finish_chains (void) | |
1401 | { | |
1402 | ira_free (ira_finish_point_ranges); | |
1403 | ira_free (ira_start_point_ranges); | |
1404 | create_start_finish_chains (); | |
1405 | } | |
1406 | ||
b15a7ae6 VM |
1407 | /* Compress allocno live ranges by removing program points where |
1408 | nothing happens. */ | |
1409 | static void | |
1410 | remove_some_program_points_and_update_live_ranges (void) | |
1411 | { | |
1412 | unsigned i; | |
1413 | int n; | |
1414 | int *map; | |
9140d27b BS |
1415 | ira_object_t obj; |
1416 | ira_object_iterator oi; | |
e6a7da82 | 1417 | live_range_t r, prev_r, next_r; |
9995f209 VM |
1418 | sbitmap born_or_dead, born, dead; |
1419 | sbitmap_iterator sbi; | |
1420 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1421 | ||
1422 | born = sbitmap_alloc (ira_max_point); | |
1423 | dead = sbitmap_alloc (ira_max_point); | |
f61e445a LC |
1424 | bitmap_clear (born); |
1425 | bitmap_clear (dead); | |
9140d27b BS |
1426 | FOR_EACH_OBJECT (obj, oi) |
1427 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1428 | { | |
1429 | ira_assert (r->start <= r->finish); | |
d7c028c0 LC |
1430 | bitmap_set_bit (born, r->start); |
1431 | bitmap_set_bit (dead, r->finish); | |
9140d27b BS |
1432 | } |
1433 | ||
9995f209 | 1434 | born_or_dead = sbitmap_alloc (ira_max_point); |
f61e445a | 1435 | bitmap_ior (born_or_dead, born, dead); |
b15a7ae6 | 1436 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
9995f209 VM |
1437 | n = -1; |
1438 | prev_born_p = prev_dead_p = false; | |
d4ac4ce2 | 1439 | EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi) |
b15a7ae6 | 1440 | { |
d7c028c0 LC |
1441 | born_p = bitmap_bit_p (born, i); |
1442 | dead_p = bitmap_bit_p (dead, i); | |
9995f209 VM |
1443 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
1444 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1445 | map[i] = n; | |
1446 | else | |
1447 | map[i] = ++n; | |
1448 | prev_born_p = born_p; | |
1449 | prev_dead_p = dead_p; | |
b15a7ae6 | 1450 | } |
9995f209 VM |
1451 | sbitmap_free (born_or_dead); |
1452 | sbitmap_free (born); | |
1453 | sbitmap_free (dead); | |
1454 | n++; | |
b15a7ae6 VM |
1455 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1456 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1457 | ira_max_point, n, 100 * n / ira_max_point); | |
1458 | ira_max_point = n; | |
9140d27b BS |
1459 | |
1460 | FOR_EACH_OBJECT (obj, oi) | |
e6a7da82 | 1461 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9140d27b | 1462 | { |
e6a7da82 | 1463 | next_r = r->next; |
9140d27b BS |
1464 | r->start = map[r->start]; |
1465 | r->finish = map[r->finish]; | |
e6a7da82 SB |
1466 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1467 | { | |
1468 | prev_r = r; | |
1469 | continue; | |
1470 | } | |
1471 | prev_r->start = r->start; | |
1472 | prev_r->next = next_r; | |
1473 | ira_finish_live_range (r); | |
9140d27b | 1474 | } |
ac0ab4f7 | 1475 | |
b15a7ae6 VM |
1476 | ira_free (map); |
1477 | } | |
1478 | ||
058e97ec VM |
1479 | /* Print live ranges R to file F. */ |
1480 | void | |
b14151b5 | 1481 | ira_print_live_range_list (FILE *f, live_range_t r) |
058e97ec VM |
1482 | { |
1483 | for (; r != NULL; r = r->next) | |
1484 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1485 | fprintf (f, "\n"); | |
1486 | } | |
1487 | ||
7b3b6ae4 LC |
1488 | DEBUG_FUNCTION void |
1489 | debug (live_range &ref) | |
1490 | { | |
1491 | ira_print_live_range_list (stderr, &ref); | |
1492 | } | |
1493 | ||
1494 | DEBUG_FUNCTION void | |
1495 | debug (live_range *ptr) | |
1496 | { | |
1497 | if (ptr) | |
1498 | debug (*ptr); | |
1499 | else | |
1500 | fprintf (stderr, "<nil>\n"); | |
1501 | } | |
1502 | ||
058e97ec VM |
1503 | /* Print live ranges R to stderr. */ |
1504 | void | |
b14151b5 | 1505 | ira_debug_live_range_list (live_range_t r) |
058e97ec VM |
1506 | { |
1507 | ira_print_live_range_list (stderr, r); | |
1508 | } | |
1509 | ||
ac0ab4f7 BS |
1510 | /* Print live ranges of object OBJ to file F. */ |
1511 | static void | |
1512 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1513 | { | |
1514 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1515 | } | |
1516 | ||
058e97ec VM |
1517 | /* Print live ranges of allocno A to file F. */ |
1518 | static void | |
1519 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1520 | { | |
ac0ab4f7 BS |
1521 | int n = ALLOCNO_NUM_OBJECTS (a); |
1522 | int i; | |
1756cb66 | 1523 | |
ac0ab4f7 BS |
1524 | for (i = 0; i < n; i++) |
1525 | { | |
1526 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1527 | if (n > 1) | |
1528 | fprintf (f, " [%d]", i); | |
1529 | fprintf (f, "):"); | |
1530 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1531 | } | |
058e97ec VM |
1532 | } |
1533 | ||
1534 | /* Print live ranges of allocno A to stderr. */ | |
1535 | void | |
1536 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1537 | { | |
1538 | print_allocno_live_ranges (stderr, a); | |
1539 | } | |
1540 | ||
1541 | /* Print live ranges of all allocnos to file F. */ | |
1542 | static void | |
1543 | print_live_ranges (FILE *f) | |
1544 | { | |
1545 | ira_allocno_t a; | |
1546 | ira_allocno_iterator ai; | |
1547 | ||
1548 | FOR_EACH_ALLOCNO (a, ai) | |
1549 | print_allocno_live_ranges (f, a); | |
1550 | } | |
1551 | ||
1552 | /* Print live ranges of all allocnos to stderr. */ | |
1553 | void | |
1554 | ira_debug_live_ranges (void) | |
1555 | { | |
1556 | print_live_ranges (stderr); | |
1557 | } | |
1558 | ||
1559 | /* The main entry function creates live ranges, set up | |
ac0ab4f7 | 1560 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
058e97ec VM |
1561 | calculate register pressure info. */ |
1562 | void | |
1563 | ira_create_allocno_live_ranges (void) | |
1564 | { | |
ac0ab4f7 BS |
1565 | objects_live = sparseset_alloc (ira_objects_num); |
1566 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
058e97ec | 1567 | curr_point = 0; |
cb1ca6ac VM |
1568 | last_call_num = 0; |
1569 | allocno_saved_at_call | |
1570 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1571 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
058e97ec VM |
1572 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1573 | process_bb_node_lives); | |
1574 | ira_max_point = curr_point; | |
1575 | create_start_finish_chains (); | |
1576 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1577 | print_live_ranges (ira_dump_file); | |
1578 | /* Clean up. */ | |
cb1ca6ac | 1579 | ira_free (allocno_saved_at_call); |
ac0ab4f7 BS |
1580 | sparseset_free (objects_live); |
1581 | sparseset_free (allocnos_processed); | |
058e97ec VM |
1582 | } |
1583 | ||
b15a7ae6 VM |
1584 | /* Compress allocno live ranges. */ |
1585 | void | |
1586 | ira_compress_allocno_live_ranges (void) | |
1587 | { | |
1588 | remove_some_program_points_and_update_live_ranges (); | |
1589 | ira_rebuild_start_finish_chains (); | |
1590 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1591 | { | |
1592 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1593 | print_live_ranges (ira_dump_file); | |
1594 | } | |
1595 | } | |
1596 | ||
058e97ec VM |
1597 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1598 | void | |
1599 | ira_finish_allocno_live_ranges (void) | |
1600 | { | |
1601 | ira_free (ira_finish_point_ranges); | |
1602 | ira_free (ira_start_point_ranges); | |
1603 | } |