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058e97ec | 1 | /* IRA processing allocno lives to build allocno live ranges. |
23a5b65a | 2 | Copyright (C) 2006-2014 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "tm.h" | |
25 | #include "regs.h" | |
26 | #include "rtl.h" | |
27 | #include "tm_p.h" | |
28 | #include "target.h" | |
29 | #include "flags.h" | |
cf0c2a60 | 30 | #include "except.h" |
058e97ec | 31 | #include "hard-reg-set.h" |
60393bbc AM |
32 | #include "predict.h" |
33 | #include "vec.h" | |
34 | #include "hashtab.h" | |
35 | #include "hash-set.h" | |
36 | #include "machmode.h" | |
37 | #include "input.h" | |
38 | #include "function.h" | |
058e97ec VM |
39 | #include "basic-block.h" |
40 | #include "insn-config.h" | |
41 | #include "recog.h" | |
718f9c0f | 42 | #include "diagnostic-core.h" |
058e97ec VM |
43 | #include "params.h" |
44 | #include "df.h" | |
9995f209 | 45 | #include "sbitmap.h" |
058e97ec VM |
46 | #include "sparseset.h" |
47 | #include "ira-int.h" | |
48 | ||
49 | /* The code in this file is similar to one in global but the code | |
50 | works on the allocno basis and creates live ranges instead of | |
51 | pseudo-register conflicts. */ | |
52 | ||
53 | /* Program points are enumerated by numbers from range | |
54 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
55 | points than insns. Program points are places in the program where | |
56 | liveness info can be changed. In most general case (there are more | |
57 | complicated cases too) some program points correspond to places | |
58 | where input operand dies and other ones correspond to places where | |
59 | output operands are born. */ | |
60 | int ira_max_point; | |
61 | ||
62 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
63 | live ranges with given start/finish point. */ | |
b14151b5 | 64 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
058e97ec VM |
65 | |
66 | /* Number of the current program point. */ | |
67 | static int curr_point; | |
68 | ||
69 | /* Point where register pressure excess started or -1 if there is no | |
70 | register pressure excess. Excess pressure for a register class at | |
71 | some point means that there are more allocnos of given register | |
72 | class living at the point than number of hard-registers of the | |
1756cb66 VM |
73 | class available for the allocation. It is defined only for |
74 | pressure classes. */ | |
058e97ec VM |
75 | static int high_pressure_start_point[N_REG_CLASSES]; |
76 | ||
ac0ab4f7 BS |
77 | /* Objects live at current point in the scan. */ |
78 | static sparseset objects_live; | |
79 | ||
80 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
81 | multiple times. */ | |
82 | static sparseset allocnos_processed; | |
058e97ec VM |
83 | |
84 | /* Set of hard regs (except eliminable ones) currently live. */ | |
85 | static HARD_REG_SET hard_regs_live; | |
86 | ||
87 | /* The loop tree node corresponding to the current basic block. */ | |
88 | static ira_loop_tree_node_t curr_bb_node; | |
89 | ||
cb1ca6ac VM |
90 | /* The number of the last processed call. */ |
91 | static int last_call_num; | |
92 | /* The number of last call at which given allocno was saved. */ | |
93 | static int *allocno_saved_at_call; | |
94 | ||
9840b2fa RS |
95 | /* The value of get_preferred_alternatives for the current instruction, |
96 | supplemental to recog_data. */ | |
97 | static alternative_mask preferred_alternatives; | |
98 | ||
ac0ab4f7 BS |
99 | /* Record the birth of hard register REGNO, updating hard_regs_live and |
100 | hard reg conflict information for living allocnos. */ | |
058e97ec | 101 | static void |
3c55880a | 102 | make_hard_regno_born (int regno) |
058e97ec VM |
103 | { |
104 | unsigned int i; | |
058e97ec | 105 | |
3c55880a | 106 | SET_HARD_REG_BIT (hard_regs_live, regno); |
ac0ab4f7 | 107 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 108 | { |
ac0ab4f7 | 109 | ira_object_t obj = ira_object_id_map[i]; |
1756cb66 | 110 | |
a49ae217 BS |
111 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
112 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
058e97ec | 113 | } |
3c55880a BS |
114 | } |
115 | ||
116 | /* Process the death of hard register REGNO. This updates | |
117 | hard_regs_live. */ | |
118 | static void | |
119 | make_hard_regno_dead (int regno) | |
120 | { | |
121 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); | |
122 | } | |
123 | ||
ac0ab4f7 BS |
124 | /* Record the birth of object OBJ. Set a bit for it in objects_live, |
125 | start a new live range for it if necessary and update hard register | |
126 | conflicts. */ | |
3c55880a | 127 | static void |
ac0ab4f7 | 128 | make_object_born (ira_object_t obj) |
3c55880a | 129 | { |
ac0ab4f7 | 130 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
3c55880a | 131 | |
ac0ab4f7 | 132 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
a49ae217 BS |
133 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
134 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); | |
3c55880a | 135 | |
ac0ab4f7 BS |
136 | if (lr == NULL |
137 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
138 | ira_add_live_range_to_object (obj, curr_point, -1); | |
058e97ec VM |
139 | } |
140 | ||
ac0ab4f7 BS |
141 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
142 | associated with object OBJ. */ | |
058e97ec | 143 | static void |
ac0ab4f7 | 144 | update_allocno_pressure_excess_length (ira_object_t obj) |
058e97ec | 145 | { |
ac0ab4f7 | 146 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
7db7ed3c | 147 | int start, i; |
1756cb66 | 148 | enum reg_class aclass, pclass, cl; |
b14151b5 | 149 | live_range_t p; |
058e97ec | 150 | |
1756cb66 VM |
151 | aclass = ALLOCNO_CLASS (a); |
152 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 153 | for (i = 0; |
1756cb66 | 154 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
155 | i++) |
156 | { | |
1756cb66 VM |
157 | if (! ira_reg_pressure_class_p[cl]) |
158 | continue; | |
7db7ed3c VM |
159 | if (high_pressure_start_point[cl] < 0) |
160 | continue; | |
9140d27b | 161 | p = OBJECT_LIVE_RANGES (obj); |
7db7ed3c VM |
162 | ira_assert (p != NULL); |
163 | start = (high_pressure_start_point[cl] > p->start | |
164 | ? high_pressure_start_point[cl] : p->start); | |
165 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
166 | } | |
058e97ec VM |
167 | } |
168 | ||
ac0ab4f7 BS |
169 | /* Process the death of object OBJ, which is associated with allocno |
170 | A. This finishes the current live range for it. */ | |
058e97ec | 171 | static void |
ac0ab4f7 | 172 | make_object_dead (ira_object_t obj) |
058e97ec | 173 | { |
ac0ab4f7 | 174 | live_range_t lr; |
058e97ec | 175 | |
ac0ab4f7 BS |
176 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
177 | lr = OBJECT_LIVE_RANGES (obj); | |
178 | ira_assert (lr != NULL); | |
179 | lr->finish = curr_point; | |
180 | update_allocno_pressure_excess_length (obj); | |
058e97ec VM |
181 | } |
182 | ||
1756cb66 | 183 | /* The current register pressures for each pressure class for the current |
058e97ec VM |
184 | basic block. */ |
185 | static int curr_reg_pressure[N_REG_CLASSES]; | |
186 | ||
1756cb66 VM |
187 | /* Record that register pressure for PCLASS increased by N registers. |
188 | Update the current register pressure, maximal register pressure for | |
189 | the current BB and the start point of the register pressure | |
190 | excess. */ | |
058e97ec | 191 | static void |
1756cb66 | 192 | inc_register_pressure (enum reg_class pclass, int n) |
058e97ec | 193 | { |
7db7ed3c | 194 | int i; |
3c55880a | 195 | enum reg_class cl; |
058e97ec | 196 | |
7db7ed3c | 197 | for (i = 0; |
1756cb66 | 198 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c VM |
199 | i++) |
200 | { | |
1756cb66 VM |
201 | if (! ira_reg_pressure_class_p[cl]) |
202 | continue; | |
3c55880a | 203 | curr_reg_pressure[cl] += n; |
7db7ed3c | 204 | if (high_pressure_start_point[cl] < 0 |
f508f827 | 205 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
7db7ed3c VM |
206 | high_pressure_start_point[cl] = curr_point; |
207 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
208 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
209 | } | |
058e97ec VM |
210 | } |
211 | ||
1756cb66 VM |
212 | /* Record that register pressure for PCLASS has decreased by NREGS |
213 | registers; update current register pressure, start point of the | |
214 | register pressure excess, and register pressure excess length for | |
215 | living allocnos. */ | |
3c55880a | 216 | |
058e97ec | 217 | static void |
1756cb66 | 218 | dec_register_pressure (enum reg_class pclass, int nregs) |
058e97ec | 219 | { |
7db7ed3c VM |
220 | int i; |
221 | unsigned int j; | |
3c55880a BS |
222 | enum reg_class cl; |
223 | bool set_p = false; | |
058e97ec | 224 | |
3c55880a | 225 | for (i = 0; |
1756cb66 | 226 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
3c55880a | 227 | i++) |
058e97ec | 228 | { |
1756cb66 VM |
229 | if (! ira_reg_pressure_class_p[cl]) |
230 | continue; | |
3c55880a BS |
231 | curr_reg_pressure[cl] -= nregs; |
232 | ira_assert (curr_reg_pressure[cl] >= 0); | |
233 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 234 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
3c55880a BS |
235 | set_p = true; |
236 | } | |
237 | if (set_p) | |
238 | { | |
ac0ab4f7 BS |
239 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
240 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
7db7ed3c | 241 | for (i = 0; |
1756cb66 | 242 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
7db7ed3c | 243 | i++) |
1756cb66 VM |
244 | { |
245 | if (! ira_reg_pressure_class_p[cl]) | |
246 | continue; | |
247 | if (high_pressure_start_point[cl] >= 0 | |
f508f827 | 248 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
1756cb66 VM |
249 | high_pressure_start_point[cl] = -1; |
250 | } | |
058e97ec | 251 | } |
058e97ec VM |
252 | } |
253 | ||
e384e6b5 BS |
254 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
255 | and occupies only one object. Return false if we have no information. */ | |
256 | static bool | |
257 | pseudo_regno_single_word_and_live_p (int regno) | |
258 | { | |
259 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
260 | ira_object_t obj; | |
261 | ||
262 | if (a == NULL) | |
263 | return false; | |
264 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
265 | return false; | |
266 | ||
267 | obj = ALLOCNO_OBJECT (a, 0); | |
268 | ||
269 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
270 | } | |
271 | ||
3c55880a BS |
272 | /* Mark the pseudo register REGNO as live. Update all information about |
273 | live ranges and register pressure. */ | |
058e97ec | 274 | static void |
3c55880a | 275 | mark_pseudo_regno_live (int regno) |
058e97ec | 276 | { |
3c55880a | 277 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
1756cb66 | 278 | enum reg_class pclass; |
ac0ab4f7 | 279 | int i, n, nregs; |
058e97ec | 280 | |
3c55880a BS |
281 | if (a == NULL) |
282 | return; | |
058e97ec | 283 | |
3c55880a BS |
284 | /* Invalidate because it is referenced. */ |
285 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 286 | |
ac0ab4f7 | 287 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
288 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
289 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
290 | if (n > 1) |
291 | { | |
292 | /* We track every subobject separately. */ | |
293 | gcc_assert (nregs == n); | |
294 | nregs = 1; | |
295 | } | |
296 | ||
297 | for (i = 0; i < n; i++) | |
298 | { | |
299 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
1756cb66 | 300 | |
ac0ab4f7 BS |
301 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
302 | continue; | |
303 | ||
1756cb66 | 304 | inc_register_pressure (pclass, nregs); |
ac0ab4f7 BS |
305 | make_object_born (obj); |
306 | } | |
307 | } | |
308 | ||
309 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
310 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
311 | indicates the low part. */ | |
312 | static void | |
313 | mark_pseudo_regno_subword_live (int regno, int subword) | |
314 | { | |
315 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 316 | int n; |
1756cb66 | 317 | enum reg_class pclass; |
ac0ab4f7 BS |
318 | ira_object_t obj; |
319 | ||
320 | if (a == NULL) | |
3c55880a BS |
321 | return; |
322 | ||
ac0ab4f7 BS |
323 | /* Invalidate because it is referenced. */ |
324 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
325 | ||
326 | n = ALLOCNO_NUM_OBJECTS (a); | |
327 | if (n == 1) | |
328 | { | |
329 | mark_pseudo_regno_live (regno); | |
330 | return; | |
331 | } | |
332 | ||
1756cb66 | 333 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
334 | gcc_assert |
335 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
336 | obj = ALLOCNO_OBJECT (a, subword); |
337 | ||
338 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
339 | return; | |
340 | ||
51935358 | 341 | inc_register_pressure (pclass, 1); |
ac0ab4f7 | 342 | make_object_born (obj); |
3c55880a BS |
343 | } |
344 | ||
ac0ab4f7 BS |
345 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
346 | this register, record how many consecutive hardware registers it | |
347 | actually needs. */ | |
3c55880a BS |
348 | static void |
349 | mark_hard_reg_live (rtx reg) | |
350 | { | |
351 | int regno = REGNO (reg); | |
352 | ||
353 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec VM |
354 | { |
355 | int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
1756cb66 | 356 | enum reg_class aclass, pclass; |
058e97ec VM |
357 | |
358 | while (regno < last) | |
359 | { | |
360 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
361 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
362 | { | |
1756cb66 VM |
363 | aclass = ira_hard_regno_allocno_class[regno]; |
364 | pclass = ira_pressure_class_translate[aclass]; | |
365 | inc_register_pressure (pclass, 1); | |
3c55880a | 366 | make_hard_regno_born (regno); |
058e97ec VM |
367 | } |
368 | regno++; | |
369 | } | |
370 | } | |
371 | } | |
372 | ||
579c1bf3 BS |
373 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
374 | register number; ORIG_REG is the access in the insn, which may be a | |
375 | subreg. */ | |
376 | static void | |
377 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
378 | { | |
379 | if (df_read_modify_subreg_p (orig_reg)) | |
380 | { | |
381 | mark_pseudo_regno_subword_live (regno, | |
382 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
383 | } | |
384 | else | |
385 | mark_pseudo_regno_live (regno); | |
386 | } | |
387 | ||
3517d3a0 VM |
388 | /* Mark the register referenced by use or def REF as live. */ |
389 | static void | |
57512f53 | 390 | mark_ref_live (df_ref ref) |
058e97ec | 391 | { |
ac0ab4f7 BS |
392 | rtx reg = DF_REF_REG (ref); |
393 | rtx orig_reg = reg; | |
3517d3a0 | 394 | |
3517d3a0 VM |
395 | if (GET_CODE (reg) == SUBREG) |
396 | reg = SUBREG_REG (reg); | |
ac0ab4f7 | 397 | |
3c55880a | 398 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 399 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
3c55880a BS |
400 | else |
401 | mark_hard_reg_live (reg); | |
058e97ec VM |
402 | } |
403 | ||
3c55880a BS |
404 | /* Mark the pseudo register REGNO as dead. Update all information about |
405 | live ranges and register pressure. */ | |
058e97ec | 406 | static void |
3c55880a | 407 | mark_pseudo_regno_dead (int regno) |
058e97ec | 408 | { |
3c55880a | 409 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
ac0ab4f7 | 410 | int n, i, nregs; |
3c55880a | 411 | enum reg_class cl; |
058e97ec | 412 | |
3c55880a BS |
413 | if (a == NULL) |
414 | return; | |
058e97ec | 415 | |
3c55880a BS |
416 | /* Invalidate because it is referenced. */ |
417 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
058e97ec | 418 | |
ac0ab4f7 | 419 | n = ALLOCNO_NUM_OBJECTS (a); |
1756cb66 VM |
420 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
421 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
ac0ab4f7 BS |
422 | if (n > 1) |
423 | { | |
424 | /* We track every subobject separately. */ | |
425 | gcc_assert (nregs == n); | |
426 | nregs = 1; | |
427 | } | |
428 | for (i = 0; i < n; i++) | |
429 | { | |
430 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
431 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
432 | continue; | |
433 | ||
434 | dec_register_pressure (cl, nregs); | |
435 | make_object_dead (obj); | |
436 | } | |
437 | } | |
438 | ||
439 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
440 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
441 | static void | |
442 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
443 | { | |
444 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
51935358 | 445 | int n; |
ac0ab4f7 BS |
446 | enum reg_class cl; |
447 | ira_object_t obj; | |
448 | ||
449 | if (a == NULL) | |
450 | return; | |
451 | ||
452 | /* Invalidate because it is referenced. */ | |
453 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
454 | ||
455 | n = ALLOCNO_NUM_OBJECTS (a); | |
456 | if (n == 1) | |
457 | /* The allocno as a whole doesn't die in this case. */ | |
3c55880a BS |
458 | return; |
459 | ||
1756cb66 | 460 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
51935358 VM |
461 | gcc_assert |
462 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
ac0ab4f7 BS |
463 | |
464 | obj = ALLOCNO_OBJECT (a, subword); | |
465 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
466 | return; | |
3c55880a | 467 | |
ac0ab4f7 BS |
468 | dec_register_pressure (cl, 1); |
469 | make_object_dead (obj); | |
3c55880a BS |
470 | } |
471 | ||
ac0ab4f7 BS |
472 | /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
473 | register. */ | |
3c55880a BS |
474 | static void |
475 | mark_hard_reg_dead (rtx reg) | |
476 | { | |
477 | int regno = REGNO (reg); | |
478 | ||
479 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
058e97ec VM |
480 | { |
481 | int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
1756cb66 | 482 | enum reg_class aclass, pclass; |
058e97ec VM |
483 | |
484 | while (regno < last) | |
485 | { | |
486 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
487 | { | |
1756cb66 VM |
488 | aclass = ira_hard_regno_allocno_class[regno]; |
489 | pclass = ira_pressure_class_translate[aclass]; | |
490 | dec_register_pressure (pclass, 1); | |
3c55880a | 491 | make_hard_regno_dead (regno); |
058e97ec VM |
492 | } |
493 | regno++; | |
494 | } | |
495 | } | |
496 | } | |
497 | ||
579c1bf3 BS |
498 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
499 | register number; ORIG_REG is the access in the insn, which may be a | |
500 | subreg. */ | |
501 | static void | |
502 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
503 | { | |
504 | if (df_read_modify_subreg_p (orig_reg)) | |
505 | { | |
506 | mark_pseudo_regno_subword_dead (regno, | |
507 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
508 | } | |
509 | else | |
510 | mark_pseudo_regno_dead (regno); | |
511 | } | |
512 | ||
3517d3a0 VM |
513 | /* Mark the register referenced by definition DEF as dead, if the |
514 | definition is a total one. */ | |
515 | static void | |
57512f53 | 516 | mark_ref_dead (df_ref def) |
3517d3a0 | 517 | { |
ac0ab4f7 BS |
518 | rtx reg = DF_REF_REG (def); |
519 | rtx orig_reg = reg; | |
3517d3a0 | 520 | |
ac0ab4f7 | 521 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
3517d3a0 VM |
522 | return; |
523 | ||
3517d3a0 VM |
524 | if (GET_CODE (reg) == SUBREG) |
525 | reg = SUBREG_REG (reg); | |
ac0ab4f7 BS |
526 | |
527 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
528 | && (GET_CODE (orig_reg) != SUBREG | |
529 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
530 | || !df_read_modify_subreg_p (orig_reg))) | |
531 | return; | |
532 | ||
3c55880a | 533 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
579c1bf3 | 534 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
3c55880a BS |
535 | else |
536 | mark_hard_reg_dead (reg); | |
3517d3a0 VM |
537 | } |
538 | ||
579c1bf3 BS |
539 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
540 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
073a8998 | 541 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
579c1bf3 BS |
542 | Advance the current program point before making the conflict if |
543 | ADVANCE_P. Return TRUE if we will need to advance the current | |
544 | program point. */ | |
3517d3a0 | 545 | static bool |
579c1bf3 BS |
546 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
547 | bool advance_p) | |
3517d3a0 | 548 | { |
579c1bf3 | 549 | rtx orig_reg = reg; |
22c02455 | 550 | ira_allocno_t a; |
3517d3a0 | 551 | |
22c02455 VM |
552 | if (GET_CODE (reg) == SUBREG) |
553 | reg = SUBREG_REG (reg); | |
b8698a0f | 554 | |
22c02455 VM |
555 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
556 | return advance_p; | |
b8698a0f | 557 | |
22c02455 | 558 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
1756cb66 | 559 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
22c02455 | 560 | return advance_p; |
3517d3a0 | 561 | |
22c02455 VM |
562 | if (advance_p) |
563 | curr_point++; | |
3517d3a0 | 564 | |
579c1bf3 BS |
565 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
566 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
567 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
568 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
22c02455 VM |
569 | |
570 | return false; | |
571 | } | |
3517d3a0 | 572 | |
22c02455 VM |
573 | /* Check and make if necessary conflicts for pseudo DREG of class |
574 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
073a8998 | 575 | ORIG_DREG is the rtx actually accessed, it may be identical to |
579c1bf3 BS |
576 | DREG or a subreg of it. Advance the current program point before |
577 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
578 | advance the current program point. */ | |
22c02455 | 579 | static bool |
579c1bf3 BS |
580 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
581 | enum reg_class def_cl, int use, | |
582 | enum reg_class use_cl, bool advance_p) | |
22c02455 VM |
583 | { |
584 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
585 | return advance_p; | |
b8698a0f | 586 | |
22c02455 | 587 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
579c1bf3 BS |
588 | use_cl, dreg, orig_dreg, advance_p); |
589 | ||
22c02455 VM |
590 | /* Reload may end up swapping commutative operands, so you |
591 | have to take both orderings into account. The | |
592 | constraints for the two operands can be completely | |
593 | different. (Indeed, if the constraints for the two | |
594 | operands are the same for all alternatives, there's no | |
595 | point marking them as commutative.) */ | |
dc344e87 | 596 | if (use < recog_data.n_operands - 1 |
22c02455 VM |
597 | && recog_data.constraints[use][0] == '%') |
598 | advance_p | |
599 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
579c1bf3 | 600 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
601 | if (use >= 1 |
602 | && recog_data.constraints[use - 1][0] == '%') | |
603 | advance_p | |
604 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
579c1bf3 | 605 | use_cl, dreg, orig_dreg, advance_p); |
22c02455 VM |
606 | return advance_p; |
607 | } | |
608 | ||
609 | /* Check and make if necessary conflicts for definition DEF of class | |
610 | DEF_CL of the current insn with input operands. Process only | |
611 | constraints of alternative ALT. */ | |
612 | static void | |
613 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
614 | { | |
615 | int use, use_match; | |
616 | ira_allocno_t a; | |
617 | enum reg_class use_cl, acl; | |
618 | bool advance_p; | |
619 | rtx dreg = recog_data.operand[def]; | |
579c1bf3 | 620 | rtx orig_dreg = dreg; |
b8698a0f | 621 | |
22c02455 VM |
622 | if (def_cl == NO_REGS) |
623 | return; | |
b8698a0f | 624 | |
22c02455 VM |
625 | if (GET_CODE (dreg) == SUBREG) |
626 | dreg = SUBREG_REG (dreg); | |
b8698a0f | 627 | |
22c02455 VM |
628 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
629 | return; | |
b8698a0f | 630 | |
22c02455 | 631 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
1756cb66 | 632 | acl = ALLOCNO_CLASS (a); |
22c02455 VM |
633 | if (! reg_classes_intersect_p (acl, def_cl)) |
634 | return; | |
b8698a0f | 635 | |
22c02455 | 636 | advance_p = true; |
b8698a0f | 637 | |
29d70a0f | 638 | int n_operands = recog_data.n_operands; |
1145837d | 639 | const operand_alternative *op_alt = &recog_op_alt[alt * n_operands]; |
29d70a0f | 640 | for (use = 0; use < n_operands; use++) |
22c02455 | 641 | { |
002b2dee BS |
642 | int alt1; |
643 | ||
22c02455 | 644 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
7ba06dee | 645 | continue; |
b8698a0f | 646 | |
29d70a0f | 647 | if (op_alt[use].anything_ok) |
22c02455 | 648 | use_cl = ALL_REGS; |
3517d3a0 | 649 | else |
29d70a0f | 650 | use_cl = op_alt[use].cl; |
b8698a0f | 651 | |
002b2dee BS |
652 | /* If there's any alternative that allows USE to match DEF, do not |
653 | record a conflict. If that causes us to create an invalid | |
ac0ab4f7 | 654 | instruction due to the earlyclobber, reload must fix it up. */ |
002b2dee | 655 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
29d70a0f | 656 | { |
9840b2fa | 657 | if (!TEST_BIT (preferred_alternatives, alt1)) |
5f2e0797 | 658 | continue; |
1145837d RS |
659 | const operand_alternative *op_alt1 |
660 | = &recog_op_alt[alt1 * n_operands]; | |
29d70a0f RS |
661 | if (op_alt1[use].matches == def |
662 | || (use < n_operands - 1 | |
663 | && recog_data.constraints[use][0] == '%' | |
664 | && op_alt1[use + 1].matches == def) | |
665 | || (use >= 1 | |
666 | && recog_data.constraints[use - 1][0] == '%' | |
667 | && op_alt1[use - 1].matches == def)) | |
668 | break; | |
669 | } | |
002b2dee BS |
670 | |
671 | if (alt1 < recog_data.n_alternatives) | |
672 | continue; | |
673 | ||
579c1bf3 BS |
674 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
675 | use, use_cl, advance_p); | |
b8698a0f | 676 | |
29d70a0f | 677 | if ((use_match = op_alt[use].matches) >= 0) |
22c02455 VM |
678 | { |
679 | if (use_match == def) | |
7ba06dee | 680 | continue; |
b8698a0f | 681 | |
29d70a0f | 682 | if (op_alt[use_match].anything_ok) |
22c02455 VM |
683 | use_cl = ALL_REGS; |
684 | else | |
29d70a0f | 685 | use_cl = op_alt[use_match].cl; |
579c1bf3 BS |
686 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
687 | use, use_cl, advance_p); | |
22c02455 | 688 | } |
3517d3a0 | 689 | } |
22c02455 VM |
690 | } |
691 | ||
692 | /* Make conflicts of early clobber pseudo registers of the current | |
693 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
694 | checking classes of the constraints and pseudos because otherwise | |
695 | significant code degradation is possible for some targets. */ | |
696 | static void | |
697 | make_early_clobber_and_input_conflicts (void) | |
698 | { | |
699 | int alt; | |
700 | int def, def_match; | |
701 | enum reg_class def_cl; | |
702 | ||
29d70a0f RS |
703 | int n_alternatives = recog_data.n_alternatives; |
704 | int n_operands = recog_data.n_operands; | |
1145837d | 705 | const operand_alternative *op_alt = recog_op_alt; |
29d70a0f | 706 | for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands) |
9840b2fa | 707 | if (TEST_BIT (preferred_alternatives, alt)) |
5f2e0797 RS |
708 | for (def = 0; def < n_operands; def++) |
709 | { | |
710 | def_cl = NO_REGS; | |
711 | if (op_alt[def].earlyclobber) | |
712 | { | |
713 | if (op_alt[def].anything_ok) | |
714 | def_cl = ALL_REGS; | |
715 | else | |
716 | def_cl = op_alt[def].cl; | |
717 | check_and_make_def_conflict (alt, def, def_cl); | |
718 | } | |
719 | if ((def_match = op_alt[def].matches) >= 0 | |
720 | && (op_alt[def_match].earlyclobber | |
721 | || op_alt[def].earlyclobber)) | |
722 | { | |
723 | if (op_alt[def_match].anything_ok) | |
724 | def_cl = ALL_REGS; | |
725 | else | |
726 | def_cl = op_alt[def_match].cl; | |
727 | check_and_make_def_conflict (alt, def, def_cl); | |
728 | } | |
729 | } | |
22c02455 VM |
730 | } |
731 | ||
732 | /* Mark early clobber hard registers of the current INSN as live (if | |
733 | LIVE_P) or dead. Return true if there are such registers. */ | |
734 | static bool | |
070a1983 | 735 | mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p) |
22c02455 | 736 | { |
bfac633a | 737 | df_ref def; |
22c02455 | 738 | bool set_p = false; |
3517d3a0 | 739 | |
bfac633a RS |
740 | FOR_EACH_INSN_DEF (def, insn) |
741 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)) | |
3517d3a0 | 742 | { |
bfac633a | 743 | rtx dreg = DF_REF_REG (def); |
b8698a0f | 744 | |
3517d3a0 VM |
745 | if (GET_CODE (dreg) == SUBREG) |
746 | dreg = SUBREG_REG (dreg); | |
747 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
748 | continue; | |
749 | ||
750 | /* Hard register clobbers are believed to be early clobber | |
751 | because there is no way to say that non-operand hard | |
b8698a0f | 752 | register clobbers are not early ones. */ |
3517d3a0 | 753 | if (live_p) |
bfac633a | 754 | mark_ref_live (def); |
3517d3a0 | 755 | else |
bfac633a | 756 | mark_ref_dead (def); |
3517d3a0 VM |
757 | set_p = true; |
758 | } | |
759 | ||
760 | return set_p; | |
761 | } | |
762 | ||
058e97ec VM |
763 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
764 | it is so, the function returns the class of the hard register. | |
765 | Otherwise it returns NO_REGS. */ | |
766 | static enum reg_class | |
767 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
768 | { | |
4cc8d9d2 | 769 | int c; |
058e97ec | 770 | enum reg_class cl, next_cl; |
777e635f | 771 | enum constraint_num cn; |
058e97ec VM |
772 | |
773 | cl = NO_REGS; | |
9840b2fa | 774 | alternative_mask preferred = preferred_alternatives; |
4cc8d9d2 RS |
775 | for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)) |
776 | if (c == '#') | |
9840b2fa | 777 | preferred &= ~ALTERNATIVE_BIT (0); |
058e97ec | 778 | else if (c == ',') |
9840b2fa RS |
779 | preferred >>= 1; |
780 | else if (preferred & 1) | |
058e97ec VM |
781 | switch (c) |
782 | { | |
8677664e RS |
783 | case 'g': |
784 | return NO_REGS; | |
b8698a0f | 785 | |
8677664e | 786 | default: |
b58923e2 | 787 | /* ??? Is this the best way to handle memory constraints? */ |
777e635f RS |
788 | cn = lookup_constraint (constraints); |
789 | if (insn_extra_memory_constraint (cn) | |
790 | || insn_extra_address_constraint (cn)) | |
b58923e2 | 791 | return NO_REGS; |
777e635f | 792 | if (constraint_satisfied_p (op, cn) |
b58923e2 RS |
793 | || (equiv_const != NULL_RTX |
794 | && CONSTANT_P (equiv_const) | |
777e635f | 795 | && constraint_satisfied_p (equiv_const, cn))) |
b58923e2 | 796 | return NO_REGS; |
8677664e | 797 | next_cl = reg_class_for_constraint (cn); |
b58923e2 RS |
798 | if (next_cl == NO_REGS) |
799 | break; | |
c9d74da6 RS |
800 | if (cl == NO_REGS |
801 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
802 | : (ira_class_singleton[cl][GET_MODE (op)] | |
803 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
804 | return NO_REGS; |
805 | cl = next_cl; | |
806 | break; | |
b8698a0f | 807 | |
058e97ec VM |
808 | case '0': case '1': case '2': case '3': case '4': |
809 | case '5': case '6': case '7': case '8': case '9': | |
810 | next_cl | |
811 | = single_reg_class (recog_data.constraints[c - '0'], | |
812 | recog_data.operand[c - '0'], NULL_RTX); | |
c9d74da6 RS |
813 | if (cl == NO_REGS |
814 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
815 | : (ira_class_singleton[cl][GET_MODE (op)] | |
816 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
058e97ec VM |
817 | return NO_REGS; |
818 | cl = next_cl; | |
819 | break; | |
058e97ec VM |
820 | } |
821 | return cl; | |
822 | } | |
823 | ||
824 | /* The function checks that operand OP_NUM of the current insn can use | |
825 | only one hard register. If it is so, the function returns the | |
826 | class of the hard register. Otherwise it returns NO_REGS. */ | |
827 | static enum reg_class | |
828 | single_reg_operand_class (int op_num) | |
829 | { | |
830 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
831 | return NO_REGS; | |
832 | return single_reg_class (recog_data.constraints[op_num], | |
833 | recog_data.operand[op_num], NULL_RTX); | |
834 | } | |
835 | ||
ce18efcb VM |
836 | /* The function sets up hard register set *SET to hard registers which |
837 | might be used by insn reloads because the constraints are too | |
838 | strict. */ | |
839 | void | |
840 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set) | |
841 | { | |
4cc8d9d2 | 842 | int i, c, regno = 0; |
ce18efcb VM |
843 | enum reg_class cl; |
844 | rtx op; | |
ef4bddc2 | 845 | machine_mode mode; |
ce18efcb VM |
846 | |
847 | CLEAR_HARD_REG_SET (*set); | |
848 | for (i = 0; i < recog_data.n_operands; i++) | |
849 | { | |
850 | op = recog_data.operand[i]; | |
851 | ||
852 | if (GET_CODE (op) == SUBREG) | |
853 | op = SUBREG_REG (op); | |
b8698a0f | 854 | |
ce18efcb VM |
855 | if (GET_CODE (op) == SCRATCH |
856 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
857 | { | |
858 | const char *p = recog_data.constraints[i]; | |
859 | ||
860 | mode = (GET_CODE (op) == SCRATCH | |
861 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
862 | cl = NO_REGS; | |
9840b2fa | 863 | alternative_mask preferred = preferred_alternatives; |
4cc8d9d2 RS |
864 | for (; (c = *p); p += CONSTRAINT_LEN (c, p)) |
865 | if (c == '#') | |
9840b2fa | 866 | preferred &= ~ALTERNATIVE_BIT (0); |
ce18efcb | 867 | else if (c == ',') |
9840b2fa RS |
868 | preferred >>= 1; |
869 | else if (preferred & 1) | |
8677664e RS |
870 | { |
871 | cl = reg_class_for_constraint (lookup_constraint (p)); | |
872 | if (cl != NO_REGS) | |
873 | { | |
874 | /* There is no register pressure problem if all of the | |
875 | regs in this class are fixed. */ | |
876 | int regno = ira_class_singleton[cl][mode]; | |
877 | if (regno >= 0) | |
878 | add_to_hard_reg_set (set, mode, regno); | |
879 | } | |
880 | } | |
ce18efcb VM |
881 | } |
882 | } | |
883 | } | |
058e97ec VM |
884 | /* Processes input operands, if IN_P, or output operands otherwise of |
885 | the current insn with FREQ to find allocno which can use only one | |
886 | hard register and makes other currently living allocnos conflicting | |
887 | with the hard register. */ | |
888 | static void | |
889 | process_single_reg_class_operands (bool in_p, int freq) | |
890 | { | |
6d1e1a26 | 891 | int i, regno; |
058e97ec | 892 | unsigned int px; |
11895e28 | 893 | enum reg_class cl; |
058e97ec VM |
894 | rtx operand; |
895 | ira_allocno_t operand_a, a; | |
896 | ||
897 | for (i = 0; i < recog_data.n_operands; i++) | |
898 | { | |
899 | operand = recog_data.operand[i]; | |
900 | if (in_p && recog_data.operand_type[i] != OP_IN | |
901 | && recog_data.operand_type[i] != OP_INOUT) | |
902 | continue; | |
903 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
904 | && recog_data.operand_type[i] != OP_INOUT) | |
905 | continue; | |
906 | cl = single_reg_operand_class (i); | |
907 | if (cl == NO_REGS) | |
908 | continue; | |
909 | ||
910 | operand_a = NULL; | |
911 | ||
912 | if (GET_CODE (operand) == SUBREG) | |
913 | operand = SUBREG_REG (operand); | |
b8698a0f | 914 | |
058e97ec VM |
915 | if (REG_P (operand) |
916 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
917 | { | |
1756cb66 | 918 | enum reg_class aclass; |
058e97ec VM |
919 | |
920 | operand_a = ira_curr_regno_allocno_map[regno]; | |
1756cb66 | 921 | aclass = ALLOCNO_CLASS (operand_a); |
c9d74da6 | 922 | if (ira_class_subset_p[cl][aclass]) |
058e97ec | 923 | { |
6d1e1a26 RS |
924 | /* View the desired allocation of OPERAND as: |
925 | ||
926 | (REG:YMODE YREGNO), | |
927 | ||
928 | a simplification of: | |
929 | ||
930 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
ef4bddc2 | 931 | machine_mode ymode, xmode; |
6d1e1a26 RS |
932 | int xregno, yregno; |
933 | HOST_WIDE_INT offset; | |
934 | ||
935 | xmode = recog_data.operand_mode[i]; | |
c9d74da6 RS |
936 | xregno = ira_class_singleton[cl][xmode]; |
937 | gcc_assert (xregno >= 0); | |
6d1e1a26 RS |
938 | ymode = ALLOCNO_MODE (operand_a); |
939 | offset = subreg_lowpart_offset (ymode, xmode); | |
940 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
941 | if (yregno >= 0 | |
1756cb66 | 942 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
6d1e1a26 RS |
943 | { |
944 | int cost; | |
945 | ||
946 | ira_allocate_and_set_costs | |
947 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
1756cb66 VM |
948 | aclass, 0); |
949 | ira_init_register_move_cost_if_necessary (xmode); | |
950 | cost = freq * (in_p | |
951 | ? ira_register_move_cost[xmode][aclass][cl] | |
952 | : ira_register_move_cost[xmode][cl][aclass]); | |
6d1e1a26 | 953 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
1756cb66 | 954 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
6d1e1a26 | 955 | } |
058e97ec VM |
956 | } |
957 | } | |
958 | ||
ac0ab4f7 | 959 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
058e97ec | 960 | { |
ac0ab4f7 BS |
961 | ira_object_t obj = ira_object_id_map[px]; |
962 | a = OBJECT_ALLOCNO (obj); | |
058e97ec VM |
963 | if (a != operand_a) |
964 | { | |
965 | /* We could increase costs of A instead of making it | |
966 | conflicting with the hard register. But it works worse | |
967 | because it will be spilled in reload in anyway. */ | |
a49ae217 | 968 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
058e97ec | 969 | reg_class_contents[cl]); |
a49ae217 | 970 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
058e97ec VM |
971 | reg_class_contents[cl]); |
972 | } | |
973 | } | |
974 | } | |
975 | } | |
976 | ||
db1a8d98 VM |
977 | /* Return true when one of the predecessor edges of BB is marked with |
978 | EDGE_ABNORMAL_CALL or EDGE_EH. */ | |
979 | static bool | |
980 | bb_has_abnormal_call_pred (basic_block bb) | |
981 | { | |
982 | edge e; | |
983 | edge_iterator ei; | |
b8698a0f | 984 | |
db1a8d98 VM |
985 | FOR_EACH_EDGE (e, ei, bb->preds) |
986 | { | |
987 | if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH)) | |
988 | return true; | |
989 | } | |
990 | return false; | |
991 | } | |
992 | ||
e384e6b5 BS |
993 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
994 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
995 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
996 | static rtx | |
070a1983 | 997 | find_call_crossed_cheap_reg (rtx_insn *insn) |
e384e6b5 BS |
998 | { |
999 | rtx cheap_reg = NULL_RTX; | |
1000 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
1001 | ||
1002 | while (exp != NULL) | |
1003 | { | |
1004 | rtx x = XEXP (exp, 0); | |
1005 | if (GET_CODE (x) == SET) | |
1006 | { | |
1007 | exp = x; | |
1008 | break; | |
1009 | } | |
1010 | exp = XEXP (exp, 1); | |
1011 | } | |
1012 | if (exp != NULL) | |
1013 | { | |
1014 | basic_block bb = BLOCK_FOR_INSN (insn); | |
1015 | rtx reg = SET_SRC (exp); | |
c74ef30d | 1016 | rtx_insn *prev = PREV_INSN (insn); |
e384e6b5 BS |
1017 | while (prev && !(INSN_P (prev) |
1018 | && BLOCK_FOR_INSN (prev) != bb)) | |
1019 | { | |
1020 | if (NONDEBUG_INSN_P (prev)) | |
1021 | { | |
1022 | rtx set = single_set (prev); | |
1023 | ||
1024 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
1025 | { | |
1026 | rtx src = SET_SRC (set); | |
1027 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
1028 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1029 | break; | |
1030 | if (!modified_between_p (src, prev, insn)) | |
1031 | cheap_reg = src; | |
1032 | break; | |
1033 | } | |
1034 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1035 | { | |
1036 | rtx dest = SET_DEST (set); | |
1037 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1038 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1039 | break; | |
1040 | if (!modified_between_p (dest, prev, insn)) | |
1041 | cheap_reg = dest; | |
1042 | break; | |
1043 | } | |
1044 | ||
1045 | if (reg_overlap_mentioned_p (reg, PATTERN (prev))) | |
1046 | break; | |
1047 | } | |
1048 | prev = PREV_INSN (prev); | |
1049 | } | |
1050 | } | |
1051 | return cheap_reg; | |
1052 | } | |
1053 | ||
058e97ec VM |
1054 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1055 | update allocno live ranges, allocno hard register conflicts, | |
1056 | intersected calls, and register pressure info for allocnos for the | |
1057 | basic block for and regions containing the basic block. */ | |
1058 | static void | |
1059 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1060 | { | |
acb37d29 | 1061 | int i, freq; |
058e97ec VM |
1062 | unsigned int j; |
1063 | basic_block bb; | |
070a1983 | 1064 | rtx_insn *insn; |
058e97ec | 1065 | bitmap_iterator bi; |
acb37d29 | 1066 | bitmap reg_live_out; |
058e97ec | 1067 | unsigned int px; |
3517d3a0 | 1068 | bool set_p; |
058e97ec VM |
1069 | |
1070 | bb = loop_tree_node->bb; | |
1071 | if (bb != NULL) | |
1072 | { | |
1756cb66 | 1073 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1074 | { |
1756cb66 VM |
1075 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1076 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
058e97ec VM |
1077 | } |
1078 | curr_bb_node = loop_tree_node; | |
bf744527 | 1079 | reg_live_out = df_get_live_out (bb); |
ac0ab4f7 | 1080 | sparseset_clear (objects_live); |
acb37d29 | 1081 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
058e97ec VM |
1082 | AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); |
1083 | AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
1084 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1085 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1086 | { | |
1756cb66 | 1087 | enum reg_class aclass, pclass, cl; |
b8698a0f | 1088 | |
1756cb66 VM |
1089 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1090 | pclass = ira_pressure_class_translate[aclass]; | |
7db7ed3c | 1091 | for (j = 0; |
1756cb66 | 1092 | (cl = ira_reg_class_super_classes[pclass][j]) |
7db7ed3c VM |
1093 | != LIM_REG_CLASSES; |
1094 | j++) | |
1095 | { | |
1756cb66 VM |
1096 | if (! ira_reg_pressure_class_p[cl]) |
1097 | continue; | |
7db7ed3c VM |
1098 | curr_reg_pressure[cl]++; |
1099 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1100 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1101 | ira_assert (curr_reg_pressure[cl] | |
f508f827 | 1102 | <= ira_class_hard_regs_num[cl]); |
7db7ed3c | 1103 | } |
058e97ec | 1104 | } |
acb37d29 | 1105 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
3c55880a | 1106 | mark_pseudo_regno_live (j); |
b8698a0f | 1107 | |
acb37d29 RS |
1108 | freq = REG_FREQ_FROM_BB (bb); |
1109 | if (freq == 0) | |
1110 | freq = 1; | |
1111 | ||
cb1ca6ac VM |
1112 | /* Invalidate all allocno_saved_at_call entries. */ |
1113 | last_call_num++; | |
1114 | ||
058e97ec | 1115 | /* Scan the code of this basic block, noting which allocnos and |
acb37d29 RS |
1116 | hard regs are born or die. |
1117 | ||
1118 | Note that this loop treats uninitialized values as live until | |
1119 | the beginning of the block. For example, if an instruction | |
1120 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1121 | set, FOO will remain live until the beginning of the block. | |
1122 | Likewise if FOO is not set at all. This is unnecessarily | |
1123 | pessimistic, but it probably doesn't matter much in practice. */ | |
1124 | FOR_BB_INSNS_REVERSE (bb, insn) | |
058e97ec | 1125 | { |
bfac633a | 1126 | df_ref def, use; |
acb37d29 | 1127 | bool call_p; |
b8698a0f | 1128 | |
b5b8b0ac | 1129 | if (!NONDEBUG_INSN_P (insn)) |
058e97ec | 1130 | continue; |
b8698a0f | 1131 | |
058e97ec VM |
1132 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1133 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
2608d841 | 1134 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
058e97ec VM |
1135 | curr_point); |
1136 | ||
acb37d29 RS |
1137 | /* Mark each defined value as live. We need to do this for |
1138 | unused values because they still conflict with quantities | |
1139 | that are live at the time of the definition. | |
1140 | ||
1141 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1142 | references represent the effect of the called function | |
1143 | on a call-clobbered register. Marking the register as | |
1144 | live would stop us from allocating it to a call-crossing | |
1145 | allocno. */ | |
1146 | call_p = CALL_P (insn); | |
bfac633a RS |
1147 | FOR_EACH_INSN_DEF (def, insn) |
1148 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1149 | mark_ref_live (def); | |
acb37d29 RS |
1150 | |
1151 | /* If INSN has multiple outputs, then any value used in one | |
1152 | of the outputs conflicts with the other outputs. Model this | |
1153 | by making the used value live during the output phase. | |
1154 | ||
1155 | It is unsafe to use !single_set here since it will ignore | |
1156 | an unused output. Just because an output is unused does | |
1157 | not mean the compiler can assume the side effect will not | |
1158 | occur. Consider if ALLOCNO appears in the address of an | |
1159 | output and we reload the output. If we allocate ALLOCNO | |
1160 | to the same hard register as an unused output we could | |
1161 | set the hard register before the output reload insn. */ | |
1162 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
bfac633a | 1163 | FOR_EACH_INSN_USE (use, insn) |
acb37d29 RS |
1164 | { |
1165 | int i; | |
1166 | rtx reg; | |
1167 | ||
bfac633a | 1168 | reg = DF_REF_REG (use); |
acb37d29 RS |
1169 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
1170 | { | |
1171 | rtx set; | |
1172 | ||
1173 | set = XVECEXP (PATTERN (insn), 0, i); | |
1174 | if (GET_CODE (set) == SET | |
1175 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1176 | { | |
1177 | /* After the previous loop, this is a no-op if | |
1178 | REG is contained within SET_DEST (SET). */ | |
bfac633a | 1179 | mark_ref_live (use); |
acb37d29 RS |
1180 | break; |
1181 | } | |
1182 | } | |
1183 | } | |
b8698a0f | 1184 | |
058e97ec | 1185 | extract_insn (insn); |
9840b2fa | 1186 | preferred_alternatives = get_preferred_alternatives (insn); |
1145837d | 1187 | preprocess_constraints (insn); |
acb37d29 | 1188 | process_single_reg_class_operands (false, freq); |
b8698a0f | 1189 | |
acb37d29 | 1190 | /* See which defined values die here. */ |
bfac633a RS |
1191 | FOR_EACH_INSN_DEF (def, insn) |
1192 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1193 | mark_ref_dead (def); | |
058e97ec | 1194 | |
acb37d29 | 1195 | if (call_p) |
058e97ec | 1196 | { |
e384e6b5 BS |
1197 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1198 | there, try to find a pseudo that is live across the call but | |
1199 | can be cheaply reconstructed from the return value. */ | |
1200 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1201 | if (cheap_reg != NULL_RTX) | |
1202 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1203 | ||
cb1ca6ac | 1204 | last_call_num++; |
ac0ab4f7 | 1205 | sparseset_clear (allocnos_processed); |
acb37d29 | 1206 | /* The current set of live allocnos are live across the call. */ |
ac0ab4f7 | 1207 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
058e97ec | 1208 | { |
ac0ab4f7 BS |
1209 | ira_object_t obj = ira_object_id_map[i]; |
1210 | ira_allocno_t a = OBJECT_ALLOCNO (obj); | |
1211 | int num = ALLOCNO_NUM (a); | |
c2ba7e7a RO |
1212 | HARD_REG_SET this_call_used_reg_set; |
1213 | ||
1214 | get_call_reg_set_usage (insn, &this_call_used_reg_set, | |
1215 | call_used_reg_set); | |
b8698a0f | 1216 | |
5feec5c1 VM |
1217 | /* Don't allocate allocnos that cross setjmps or any |
1218 | call, if this function receives a nonlocal | |
1219 | goto. */ | |
1220 | if (cfun->has_nonlocal_label | |
1221 | || find_reg_note (insn, REG_SETJMP, | |
1222 | NULL_RTX) != NULL_RTX) | |
058e97ec | 1223 | { |
a49ae217 BS |
1224 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1225 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
058e97ec | 1226 | } |
cf0c2a60 VM |
1227 | if (can_throw_internal (insn)) |
1228 | { | |
a49ae217 | 1229 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
c2ba7e7a | 1230 | this_call_used_reg_set); |
ac0ab4f7 | 1231 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
c2ba7e7a | 1232 | this_call_used_reg_set); |
cf0c2a60 | 1233 | } |
ac0ab4f7 BS |
1234 | |
1235 | if (sparseset_bit_p (allocnos_processed, num)) | |
1236 | continue; | |
1237 | sparseset_set_bit (allocnos_processed, num); | |
1238 | ||
1239 | if (allocno_saved_at_call[num] != last_call_num) | |
df3e3493 | 1240 | /* Here we are mimicking caller-save.c behavior |
ac0ab4f7 BS |
1241 | which does not save hard register at a call if |
1242 | it was saved on previous call in the same basic | |
1243 | block and the hard register was not mentioned | |
1244 | between the two calls. */ | |
1245 | ALLOCNO_CALL_FREQ (a) += freq; | |
1246 | /* Mark it as saved at the next call. */ | |
1247 | allocno_saved_at_call[num] = last_call_num + 1; | |
1248 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
c2ba7e7a RO |
1249 | IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), |
1250 | this_call_used_reg_set); | |
e384e6b5 BS |
1251 | if (cheap_reg != NULL_RTX |
1252 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1253 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
058e97ec VM |
1254 | } |
1255 | } | |
b8698a0f | 1256 | |
22c02455 VM |
1257 | make_early_clobber_and_input_conflicts (); |
1258 | ||
acb37d29 RS |
1259 | curr_point++; |
1260 | ||
1261 | /* Mark each used value as live. */ | |
bfac633a RS |
1262 | FOR_EACH_INSN_USE (use, insn) |
1263 | mark_ref_live (use); | |
acb37d29 | 1264 | |
acb37d29 | 1265 | process_single_reg_class_operands (true, freq); |
b8698a0f | 1266 | |
22c02455 VM |
1267 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1268 | ||
3517d3a0 VM |
1269 | if (set_p) |
1270 | { | |
22c02455 | 1271 | mark_hard_reg_early_clobbers (insn, false); |
3517d3a0 | 1272 | |
22c02455 | 1273 | /* Mark each hard reg as live again. For example, a |
3517d3a0 VM |
1274 | hard register can be in clobber and in an insn |
1275 | input. */ | |
bfac633a | 1276 | FOR_EACH_INSN_USE (use, insn) |
22c02455 | 1277 | { |
bfac633a | 1278 | rtx ureg = DF_REF_REG (use); |
b8698a0f | 1279 | |
22c02455 VM |
1280 | if (GET_CODE (ureg) == SUBREG) |
1281 | ureg = SUBREG_REG (ureg); | |
1282 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1283 | continue; | |
b8698a0f | 1284 | |
bfac633a | 1285 | mark_ref_live (use); |
22c02455 | 1286 | } |
3517d3a0 | 1287 | } |
058e97ec | 1288 | |
058e97ec VM |
1289 | curr_point++; |
1290 | } | |
acb37d29 | 1291 | |
5dbd125c EB |
1292 | #ifdef EH_RETURN_DATA_REGNO |
1293 | if (bb_has_eh_pred (bb)) | |
1294 | for (j = 0; ; ++j) | |
1295 | { | |
1296 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1297 | if (regno == INVALID_REGNUM) | |
1298 | break; | |
3c55880a | 1299 | make_hard_regno_born (regno); |
5dbd125c EB |
1300 | } |
1301 | #endif | |
1302 | ||
acb37d29 RS |
1303 | /* Allocnos can't go in stack regs at the start of a basic block |
1304 | that is reached by an abnormal edge. Likewise for call | |
1305 | clobbered regs, because caller-save, fixup_abnormal_edges and | |
1306 | possibly the table driven EH machinery are not quite ready to | |
1307 | handle such allocnos live across such edges. */ | |
5dbd125c | 1308 | if (bb_has_abnormal_pred (bb)) |
acb37d29 RS |
1309 | { |
1310 | #ifdef STACK_REGS | |
ac0ab4f7 | 1311 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
acb37d29 | 1312 | { |
ac0ab4f7 | 1313 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
1756cb66 | 1314 | |
ac0ab4f7 BS |
1315 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1316 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
acb37d29 RS |
1317 | } |
1318 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
3c55880a | 1319 | make_hard_regno_born (px); |
acb37d29 RS |
1320 | #endif |
1321 | /* No need to record conflicts for call clobbered regs if we | |
1322 | have nonlocal labels around, as we don't ever try to | |
1323 | allocate such regs in this case. */ | |
db1a8d98 | 1324 | if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb)) |
acb37d29 RS |
1325 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
1326 | if (call_used_regs[px]) | |
3c55880a | 1327 | make_hard_regno_born (px); |
acb37d29 RS |
1328 | } |
1329 | ||
ac0ab4f7 BS |
1330 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1331 | make_object_dead (ira_object_id_map[i]); | |
058e97ec VM |
1332 | |
1333 | curr_point++; | |
1334 | ||
1335 | } | |
2b9c63a2 | 1336 | /* Propagate register pressure to upper loop tree nodes. */ |
058e97ec | 1337 | if (loop_tree_node != ira_loop_tree_root) |
1756cb66 | 1338 | for (i = 0; i < ira_pressure_classes_num; i++) |
058e97ec | 1339 | { |
1756cb66 | 1340 | enum reg_class pclass; |
058e97ec | 1341 | |
1756cb66 VM |
1342 | pclass = ira_pressure_classes[i]; |
1343 | if (loop_tree_node->reg_pressure[pclass] | |
1344 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1345 | loop_tree_node->parent->reg_pressure[pclass] | |
1346 | = loop_tree_node->reg_pressure[pclass]; | |
058e97ec VM |
1347 | } |
1348 | } | |
1349 | ||
1350 | /* Create and set up IRA_START_POINT_RANGES and | |
1351 | IRA_FINISH_POINT_RANGES. */ | |
1352 | static void | |
1353 | create_start_finish_chains (void) | |
1354 | { | |
ac0ab4f7 BS |
1355 | ira_object_t obj; |
1356 | ira_object_iterator oi; | |
b14151b5 | 1357 | live_range_t r; |
058e97ec VM |
1358 | |
1359 | ira_start_point_ranges | |
ac0ab4f7 BS |
1360 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1361 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
058e97ec | 1362 | ira_finish_point_ranges |
ac0ab4f7 BS |
1363 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1364 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1365 | FOR_EACH_OBJECT (obj, oi) | |
1366 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1367 | { | |
1368 | r->start_next = ira_start_point_ranges[r->start]; | |
1369 | ira_start_point_ranges[r->start] = r; | |
1370 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
058e97ec | 1371 | ira_finish_point_ranges[r->finish] = r; |
ac0ab4f7 | 1372 | } |
058e97ec VM |
1373 | } |
1374 | ||
1375 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1376 | new live ranges and program points were added as a result if new | |
1377 | insn generation. */ | |
1378 | void | |
1379 | ira_rebuild_start_finish_chains (void) | |
1380 | { | |
1381 | ira_free (ira_finish_point_ranges); | |
1382 | ira_free (ira_start_point_ranges); | |
1383 | create_start_finish_chains (); | |
1384 | } | |
1385 | ||
b15a7ae6 VM |
1386 | /* Compress allocno live ranges by removing program points where |
1387 | nothing happens. */ | |
1388 | static void | |
1389 | remove_some_program_points_and_update_live_ranges (void) | |
1390 | { | |
1391 | unsigned i; | |
1392 | int n; | |
1393 | int *map; | |
9140d27b BS |
1394 | ira_object_t obj; |
1395 | ira_object_iterator oi; | |
e6a7da82 | 1396 | live_range_t r, prev_r, next_r; |
9995f209 VM |
1397 | sbitmap born_or_dead, born, dead; |
1398 | sbitmap_iterator sbi; | |
1399 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1400 | ||
1401 | born = sbitmap_alloc (ira_max_point); | |
1402 | dead = sbitmap_alloc (ira_max_point); | |
f61e445a LC |
1403 | bitmap_clear (born); |
1404 | bitmap_clear (dead); | |
9140d27b BS |
1405 | FOR_EACH_OBJECT (obj, oi) |
1406 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1407 | { | |
1408 | ira_assert (r->start <= r->finish); | |
d7c028c0 LC |
1409 | bitmap_set_bit (born, r->start); |
1410 | bitmap_set_bit (dead, r->finish); | |
9140d27b BS |
1411 | } |
1412 | ||
9995f209 | 1413 | born_or_dead = sbitmap_alloc (ira_max_point); |
f61e445a | 1414 | bitmap_ior (born_or_dead, born, dead); |
b15a7ae6 | 1415 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
9995f209 VM |
1416 | n = -1; |
1417 | prev_born_p = prev_dead_p = false; | |
d4ac4ce2 | 1418 | EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi) |
b15a7ae6 | 1419 | { |
d7c028c0 LC |
1420 | born_p = bitmap_bit_p (born, i); |
1421 | dead_p = bitmap_bit_p (dead, i); | |
9995f209 VM |
1422 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
1423 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1424 | map[i] = n; | |
1425 | else | |
1426 | map[i] = ++n; | |
1427 | prev_born_p = born_p; | |
1428 | prev_dead_p = dead_p; | |
b15a7ae6 | 1429 | } |
9995f209 VM |
1430 | sbitmap_free (born_or_dead); |
1431 | sbitmap_free (born); | |
1432 | sbitmap_free (dead); | |
1433 | n++; | |
b15a7ae6 VM |
1434 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1435 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1436 | ira_max_point, n, 100 * n / ira_max_point); | |
1437 | ira_max_point = n; | |
9140d27b BS |
1438 | |
1439 | FOR_EACH_OBJECT (obj, oi) | |
e6a7da82 | 1440 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9140d27b | 1441 | { |
e6a7da82 | 1442 | next_r = r->next; |
9140d27b BS |
1443 | r->start = map[r->start]; |
1444 | r->finish = map[r->finish]; | |
e6a7da82 SB |
1445 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1446 | { | |
1447 | prev_r = r; | |
1448 | continue; | |
1449 | } | |
1450 | prev_r->start = r->start; | |
1451 | prev_r->next = next_r; | |
1452 | ira_finish_live_range (r); | |
9140d27b | 1453 | } |
ac0ab4f7 | 1454 | |
b15a7ae6 VM |
1455 | ira_free (map); |
1456 | } | |
1457 | ||
058e97ec VM |
1458 | /* Print live ranges R to file F. */ |
1459 | void | |
b14151b5 | 1460 | ira_print_live_range_list (FILE *f, live_range_t r) |
058e97ec VM |
1461 | { |
1462 | for (; r != NULL; r = r->next) | |
1463 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1464 | fprintf (f, "\n"); | |
1465 | } | |
1466 | ||
7b3b6ae4 LC |
1467 | DEBUG_FUNCTION void |
1468 | debug (live_range &ref) | |
1469 | { | |
1470 | ira_print_live_range_list (stderr, &ref); | |
1471 | } | |
1472 | ||
1473 | DEBUG_FUNCTION void | |
1474 | debug (live_range *ptr) | |
1475 | { | |
1476 | if (ptr) | |
1477 | debug (*ptr); | |
1478 | else | |
1479 | fprintf (stderr, "<nil>\n"); | |
1480 | } | |
1481 | ||
058e97ec VM |
1482 | /* Print live ranges R to stderr. */ |
1483 | void | |
b14151b5 | 1484 | ira_debug_live_range_list (live_range_t r) |
058e97ec VM |
1485 | { |
1486 | ira_print_live_range_list (stderr, r); | |
1487 | } | |
1488 | ||
ac0ab4f7 BS |
1489 | /* Print live ranges of object OBJ to file F. */ |
1490 | static void | |
1491 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1492 | { | |
1493 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1494 | } | |
1495 | ||
058e97ec VM |
1496 | /* Print live ranges of allocno A to file F. */ |
1497 | static void | |
1498 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1499 | { | |
ac0ab4f7 BS |
1500 | int n = ALLOCNO_NUM_OBJECTS (a); |
1501 | int i; | |
1756cb66 | 1502 | |
ac0ab4f7 BS |
1503 | for (i = 0; i < n; i++) |
1504 | { | |
1505 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1506 | if (n > 1) | |
1507 | fprintf (f, " [%d]", i); | |
1508 | fprintf (f, "):"); | |
1509 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1510 | } | |
058e97ec VM |
1511 | } |
1512 | ||
1513 | /* Print live ranges of allocno A to stderr. */ | |
1514 | void | |
1515 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1516 | { | |
1517 | print_allocno_live_ranges (stderr, a); | |
1518 | } | |
1519 | ||
1520 | /* Print live ranges of all allocnos to file F. */ | |
1521 | static void | |
1522 | print_live_ranges (FILE *f) | |
1523 | { | |
1524 | ira_allocno_t a; | |
1525 | ira_allocno_iterator ai; | |
1526 | ||
1527 | FOR_EACH_ALLOCNO (a, ai) | |
1528 | print_allocno_live_ranges (f, a); | |
1529 | } | |
1530 | ||
1531 | /* Print live ranges of all allocnos to stderr. */ | |
1532 | void | |
1533 | ira_debug_live_ranges (void) | |
1534 | { | |
1535 | print_live_ranges (stderr); | |
1536 | } | |
1537 | ||
1538 | /* The main entry function creates live ranges, set up | |
ac0ab4f7 | 1539 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
058e97ec VM |
1540 | calculate register pressure info. */ |
1541 | void | |
1542 | ira_create_allocno_live_ranges (void) | |
1543 | { | |
ac0ab4f7 BS |
1544 | objects_live = sparseset_alloc (ira_objects_num); |
1545 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
058e97ec | 1546 | curr_point = 0; |
cb1ca6ac VM |
1547 | last_call_num = 0; |
1548 | allocno_saved_at_call | |
1549 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1550 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
058e97ec VM |
1551 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1552 | process_bb_node_lives); | |
1553 | ira_max_point = curr_point; | |
1554 | create_start_finish_chains (); | |
1555 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1556 | print_live_ranges (ira_dump_file); | |
1557 | /* Clean up. */ | |
cb1ca6ac | 1558 | ira_free (allocno_saved_at_call); |
ac0ab4f7 BS |
1559 | sparseset_free (objects_live); |
1560 | sparseset_free (allocnos_processed); | |
058e97ec VM |
1561 | } |
1562 | ||
b15a7ae6 VM |
1563 | /* Compress allocno live ranges. */ |
1564 | void | |
1565 | ira_compress_allocno_live_ranges (void) | |
1566 | { | |
1567 | remove_some_program_points_and_update_live_ranges (); | |
1568 | ira_rebuild_start_finish_chains (); | |
1569 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1570 | { | |
1571 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1572 | print_live_ranges (ira_dump_file); | |
1573 | } | |
1574 | } | |
1575 | ||
058e97ec VM |
1576 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1577 | void | |
1578 | ira_finish_allocno_live_ranges (void) | |
1579 | { | |
1580 | ira_free (ira_finish_point_ranges); | |
1581 | ira_free (ira_start_point_ranges); | |
1582 | } |