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47dd2e78 | 1 | /* IRA processing allocno lives to build allocno live ranges. |
f1717362 | 2 | Copyright (C) 2006-2016 Free Software Foundation, Inc. |
47dd2e78 | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
9ef16211 | 24 | #include "backend.h" |
7c29e30e | 25 | #include "target.h" |
47dd2e78 | 26 | #include "rtl.h" |
7c29e30e | 27 | #include "predict.h" |
9ef16211 | 28 | #include "df.h" |
47dd2e78 | 29 | #include "tm_p.h" |
47dd2e78 | 30 | #include "insn-config.h" |
7c29e30e | 31 | #include "regs.h" |
32 | #include "ira.h" | |
33 | #include "ira-int.h" | |
47dd2e78 | 34 | #include "sparseset.h" |
47dd2e78 | 35 | |
36 | /* The code in this file is similar to one in global but the code | |
37 | works on the allocno basis and creates live ranges instead of | |
38 | pseudo-register conflicts. */ | |
39 | ||
40 | /* Program points are enumerated by numbers from range | |
41 | 0..IRA_MAX_POINT-1. There are approximately two times more program | |
42 | points than insns. Program points are places in the program where | |
43 | liveness info can be changed. In most general case (there are more | |
44 | complicated cases too) some program points correspond to places | |
45 | where input operand dies and other ones correspond to places where | |
46 | output operands are born. */ | |
47 | int ira_max_point; | |
48 | ||
49 | /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
50 | live ranges with given start/finish point. */ | |
fbff82f4 | 51 | live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
47dd2e78 | 52 | |
53 | /* Number of the current program point. */ | |
54 | static int curr_point; | |
55 | ||
56 | /* Point where register pressure excess started or -1 if there is no | |
57 | register pressure excess. Excess pressure for a register class at | |
58 | some point means that there are more allocnos of given register | |
59 | class living at the point than number of hard-registers of the | |
66d9a7b9 | 60 | class available for the allocation. It is defined only for |
61 | pressure classes. */ | |
47dd2e78 | 62 | static int high_pressure_start_point[N_REG_CLASSES]; |
63 | ||
be18556f | 64 | /* Objects live at current point in the scan. */ |
65 | static sparseset objects_live; | |
66 | ||
67 | /* A temporary bitmap used in functions that wish to avoid visiting an allocno | |
68 | multiple times. */ | |
69 | static sparseset allocnos_processed; | |
47dd2e78 | 70 | |
71 | /* Set of hard regs (except eliminable ones) currently live. */ | |
72 | static HARD_REG_SET hard_regs_live; | |
73 | ||
74 | /* The loop tree node corresponding to the current basic block. */ | |
75 | static ira_loop_tree_node_t curr_bb_node; | |
76 | ||
df07a54c | 77 | /* The number of the last processed call. */ |
78 | static int last_call_num; | |
79 | /* The number of last call at which given allocno was saved. */ | |
80 | static int *allocno_saved_at_call; | |
81 | ||
e1a797ad | 82 | /* The value of get_preferred_alternatives for the current instruction, |
83 | supplemental to recog_data. */ | |
84 | static alternative_mask preferred_alternatives; | |
85 | ||
be18556f | 86 | /* Record the birth of hard register REGNO, updating hard_regs_live and |
87 | hard reg conflict information for living allocnos. */ | |
47dd2e78 | 88 | static void |
b4f5e198 | 89 | make_hard_regno_born (int regno) |
47dd2e78 | 90 | { |
91 | unsigned int i; | |
47dd2e78 | 92 | |
b4f5e198 | 93 | SET_HARD_REG_BIT (hard_regs_live, regno); |
be18556f | 94 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
47dd2e78 | 95 | { |
be18556f | 96 | ira_object_t obj = ira_object_id_map[i]; |
66d9a7b9 | 97 | |
ae9587ed | 98 | SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
99 | SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); | |
47dd2e78 | 100 | } |
b4f5e198 | 101 | } |
102 | ||
103 | /* Process the death of hard register REGNO. This updates | |
104 | hard_regs_live. */ | |
105 | static void | |
106 | make_hard_regno_dead (int regno) | |
107 | { | |
108 | CLEAR_HARD_REG_BIT (hard_regs_live, regno); | |
109 | } | |
110 | ||
be18556f | 111 | /* Record the birth of object OBJ. Set a bit for it in objects_live, |
112 | start a new live range for it if necessary and update hard register | |
113 | conflicts. */ | |
b4f5e198 | 114 | static void |
be18556f | 115 | make_object_born (ira_object_t obj) |
b4f5e198 | 116 | { |
be18556f | 117 | live_range_t lr = OBJECT_LIVE_RANGES (obj); |
b4f5e198 | 118 | |
be18556f | 119 | sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
ae9587ed | 120 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
121 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); | |
b4f5e198 | 122 | |
be18556f | 123 | if (lr == NULL |
124 | || (lr->finish != curr_point && lr->finish + 1 != curr_point)) | |
125 | ira_add_live_range_to_object (obj, curr_point, -1); | |
47dd2e78 | 126 | } |
127 | ||
be18556f | 128 | /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
129 | associated with object OBJ. */ | |
47dd2e78 | 130 | static void |
be18556f | 131 | update_allocno_pressure_excess_length (ira_object_t obj) |
47dd2e78 | 132 | { |
be18556f | 133 | ira_allocno_t a = OBJECT_ALLOCNO (obj); |
14792f4e | 134 | int start, i; |
66d9a7b9 | 135 | enum reg_class aclass, pclass, cl; |
fbff82f4 | 136 | live_range_t p; |
47dd2e78 | 137 | |
66d9a7b9 | 138 | aclass = ALLOCNO_CLASS (a); |
139 | pclass = ira_pressure_class_translate[aclass]; | |
14792f4e | 140 | for (i = 0; |
66d9a7b9 | 141 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 142 | i++) |
143 | { | |
66d9a7b9 | 144 | if (! ira_reg_pressure_class_p[cl]) |
145 | continue; | |
14792f4e | 146 | if (high_pressure_start_point[cl] < 0) |
147 | continue; | |
9d53e372 | 148 | p = OBJECT_LIVE_RANGES (obj); |
14792f4e | 149 | ira_assert (p != NULL); |
150 | start = (high_pressure_start_point[cl] > p->start | |
151 | ? high_pressure_start_point[cl] : p->start); | |
152 | ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
153 | } | |
47dd2e78 | 154 | } |
155 | ||
be18556f | 156 | /* Process the death of object OBJ, which is associated with allocno |
157 | A. This finishes the current live range for it. */ | |
47dd2e78 | 158 | static void |
be18556f | 159 | make_object_dead (ira_object_t obj) |
47dd2e78 | 160 | { |
be18556f | 161 | live_range_t lr; |
47dd2e78 | 162 | |
be18556f | 163 | sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
164 | lr = OBJECT_LIVE_RANGES (obj); | |
165 | ira_assert (lr != NULL); | |
166 | lr->finish = curr_point; | |
167 | update_allocno_pressure_excess_length (obj); | |
47dd2e78 | 168 | } |
169 | ||
66d9a7b9 | 170 | /* The current register pressures for each pressure class for the current |
47dd2e78 | 171 | basic block. */ |
172 | static int curr_reg_pressure[N_REG_CLASSES]; | |
173 | ||
66d9a7b9 | 174 | /* Record that register pressure for PCLASS increased by N registers. |
175 | Update the current register pressure, maximal register pressure for | |
176 | the current BB and the start point of the register pressure | |
177 | excess. */ | |
47dd2e78 | 178 | static void |
66d9a7b9 | 179 | inc_register_pressure (enum reg_class pclass, int n) |
47dd2e78 | 180 | { |
14792f4e | 181 | int i; |
b4f5e198 | 182 | enum reg_class cl; |
47dd2e78 | 183 | |
14792f4e | 184 | for (i = 0; |
66d9a7b9 | 185 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 186 | i++) |
187 | { | |
66d9a7b9 | 188 | if (! ira_reg_pressure_class_p[cl]) |
189 | continue; | |
b4f5e198 | 190 | curr_reg_pressure[cl] += n; |
14792f4e | 191 | if (high_pressure_start_point[cl] < 0 |
1072fecf | 192 | && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl])) |
14792f4e | 193 | high_pressure_start_point[cl] = curr_point; |
194 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
195 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
196 | } | |
47dd2e78 | 197 | } |
198 | ||
66d9a7b9 | 199 | /* Record that register pressure for PCLASS has decreased by NREGS |
200 | registers; update current register pressure, start point of the | |
201 | register pressure excess, and register pressure excess length for | |
202 | living allocnos. */ | |
b4f5e198 | 203 | |
47dd2e78 | 204 | static void |
66d9a7b9 | 205 | dec_register_pressure (enum reg_class pclass, int nregs) |
47dd2e78 | 206 | { |
14792f4e | 207 | int i; |
208 | unsigned int j; | |
b4f5e198 | 209 | enum reg_class cl; |
210 | bool set_p = false; | |
47dd2e78 | 211 | |
b4f5e198 | 212 | for (i = 0; |
66d9a7b9 | 213 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
b4f5e198 | 214 | i++) |
47dd2e78 | 215 | { |
66d9a7b9 | 216 | if (! ira_reg_pressure_class_p[cl]) |
217 | continue; | |
b4f5e198 | 218 | curr_reg_pressure[cl] -= nregs; |
219 | ira_assert (curr_reg_pressure[cl] >= 0); | |
220 | if (high_pressure_start_point[cl] >= 0 | |
1072fecf | 221 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
b4f5e198 | 222 | set_p = true; |
223 | } | |
224 | if (set_p) | |
225 | { | |
be18556f | 226 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
227 | update_allocno_pressure_excess_length (ira_object_id_map[j]); | |
14792f4e | 228 | for (i = 0; |
66d9a7b9 | 229 | (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES; |
14792f4e | 230 | i++) |
66d9a7b9 | 231 | { |
232 | if (! ira_reg_pressure_class_p[cl]) | |
233 | continue; | |
234 | if (high_pressure_start_point[cl] >= 0 | |
1072fecf | 235 | && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl]) |
66d9a7b9 | 236 | high_pressure_start_point[cl] = -1; |
237 | } | |
47dd2e78 | 238 | } |
47dd2e78 | 239 | } |
240 | ||
c8010b80 | 241 | /* Determine from the objects_live bitmap whether REGNO is currently live, |
242 | and occupies only one object. Return false if we have no information. */ | |
243 | static bool | |
244 | pseudo_regno_single_word_and_live_p (int regno) | |
245 | { | |
246 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
247 | ira_object_t obj; | |
248 | ||
249 | if (a == NULL) | |
250 | return false; | |
251 | if (ALLOCNO_NUM_OBJECTS (a) > 1) | |
252 | return false; | |
253 | ||
254 | obj = ALLOCNO_OBJECT (a, 0); | |
255 | ||
256 | return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)); | |
257 | } | |
258 | ||
b4f5e198 | 259 | /* Mark the pseudo register REGNO as live. Update all information about |
260 | live ranges and register pressure. */ | |
47dd2e78 | 261 | static void |
b4f5e198 | 262 | mark_pseudo_regno_live (int regno) |
47dd2e78 | 263 | { |
b4f5e198 | 264 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
66d9a7b9 | 265 | enum reg_class pclass; |
be18556f | 266 | int i, n, nregs; |
47dd2e78 | 267 | |
b4f5e198 | 268 | if (a == NULL) |
269 | return; | |
47dd2e78 | 270 | |
b4f5e198 | 271 | /* Invalidate because it is referenced. */ |
272 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
47dd2e78 | 273 | |
be18556f | 274 | n = ALLOCNO_NUM_OBJECTS (a); |
66d9a7b9 | 275 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
276 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
be18556f | 277 | if (n > 1) |
278 | { | |
279 | /* We track every subobject separately. */ | |
280 | gcc_assert (nregs == n); | |
281 | nregs = 1; | |
282 | } | |
283 | ||
284 | for (i = 0; i < n; i++) | |
285 | { | |
286 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
66d9a7b9 | 287 | |
be18556f | 288 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
289 | continue; | |
290 | ||
66d9a7b9 | 291 | inc_register_pressure (pclass, nregs); |
be18556f | 292 | make_object_born (obj); |
293 | } | |
294 | } | |
295 | ||
296 | /* Like mark_pseudo_regno_live, but try to only mark one subword of | |
297 | the pseudo as live. SUBWORD indicates which; a value of 0 | |
298 | indicates the low part. */ | |
299 | static void | |
300 | mark_pseudo_regno_subword_live (int regno, int subword) | |
301 | { | |
302 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
342f23d2 | 303 | int n; |
66d9a7b9 | 304 | enum reg_class pclass; |
be18556f | 305 | ira_object_t obj; |
306 | ||
307 | if (a == NULL) | |
b4f5e198 | 308 | return; |
309 | ||
be18556f | 310 | /* Invalidate because it is referenced. */ |
311 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
312 | ||
313 | n = ALLOCNO_NUM_OBJECTS (a); | |
314 | if (n == 1) | |
315 | { | |
316 | mark_pseudo_regno_live (regno); | |
317 | return; | |
318 | } | |
319 | ||
66d9a7b9 | 320 | pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
342f23d2 | 321 | gcc_assert |
322 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
be18556f | 323 | obj = ALLOCNO_OBJECT (a, subword); |
324 | ||
325 | if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
326 | return; | |
327 | ||
342f23d2 | 328 | inc_register_pressure (pclass, 1); |
be18556f | 329 | make_object_born (obj); |
b4f5e198 | 330 | } |
331 | ||
be18556f | 332 | /* Mark the register REG as live. Store a 1 in hard_regs_live for |
333 | this register, record how many consecutive hardware registers it | |
334 | actually needs. */ | |
b4f5e198 | 335 | static void |
336 | mark_hard_reg_live (rtx reg) | |
337 | { | |
338 | int regno = REGNO (reg); | |
339 | ||
340 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
47dd2e78 | 341 | { |
0933f1d9 | 342 | int last = END_REGNO (reg); |
66d9a7b9 | 343 | enum reg_class aclass, pclass; |
47dd2e78 | 344 | |
345 | while (regno < last) | |
346 | { | |
347 | if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
348 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
349 | { | |
66d9a7b9 | 350 | aclass = ira_hard_regno_allocno_class[regno]; |
351 | pclass = ira_pressure_class_translate[aclass]; | |
352 | inc_register_pressure (pclass, 1); | |
b4f5e198 | 353 | make_hard_regno_born (regno); |
47dd2e78 | 354 | } |
355 | regno++; | |
356 | } | |
357 | } | |
358 | } | |
359 | ||
044621b2 | 360 | /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
361 | register number; ORIG_REG is the access in the insn, which may be a | |
362 | subreg. */ | |
363 | static void | |
364 | mark_pseudo_reg_live (rtx orig_reg, unsigned regno) | |
365 | { | |
366 | if (df_read_modify_subreg_p (orig_reg)) | |
367 | { | |
368 | mark_pseudo_regno_subword_live (regno, | |
369 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
370 | } | |
371 | else | |
372 | mark_pseudo_regno_live (regno); | |
373 | } | |
374 | ||
793e7497 | 375 | /* Mark the register referenced by use or def REF as live. */ |
376 | static void | |
ed6e85ae | 377 | mark_ref_live (df_ref ref) |
47dd2e78 | 378 | { |
be18556f | 379 | rtx reg = DF_REF_REG (ref); |
380 | rtx orig_reg = reg; | |
793e7497 | 381 | |
793e7497 | 382 | if (GET_CODE (reg) == SUBREG) |
383 | reg = SUBREG_REG (reg); | |
be18556f | 384 | |
b4f5e198 | 385 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
044621b2 | 386 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
b4f5e198 | 387 | else |
388 | mark_hard_reg_live (reg); | |
47dd2e78 | 389 | } |
390 | ||
b4f5e198 | 391 | /* Mark the pseudo register REGNO as dead. Update all information about |
392 | live ranges and register pressure. */ | |
47dd2e78 | 393 | static void |
b4f5e198 | 394 | mark_pseudo_regno_dead (int regno) |
47dd2e78 | 395 | { |
b4f5e198 | 396 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
be18556f | 397 | int n, i, nregs; |
b4f5e198 | 398 | enum reg_class cl; |
47dd2e78 | 399 | |
b4f5e198 | 400 | if (a == NULL) |
401 | return; | |
47dd2e78 | 402 | |
b4f5e198 | 403 | /* Invalidate because it is referenced. */ |
404 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
47dd2e78 | 405 | |
be18556f | 406 | n = ALLOCNO_NUM_OBJECTS (a); |
66d9a7b9 | 407 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
408 | nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]; | |
be18556f | 409 | if (n > 1) |
410 | { | |
411 | /* We track every subobject separately. */ | |
412 | gcc_assert (nregs == n); | |
413 | nregs = 1; | |
414 | } | |
415 | for (i = 0; i < n; i++) | |
416 | { | |
417 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
418 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
419 | continue; | |
420 | ||
421 | dec_register_pressure (cl, nregs); | |
422 | make_object_dead (obj); | |
423 | } | |
424 | } | |
425 | ||
426 | /* Like mark_pseudo_regno_dead, but called when we know that only part of the | |
427 | register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ | |
428 | static void | |
429 | mark_pseudo_regno_subword_dead (int regno, int subword) | |
430 | { | |
431 | ira_allocno_t a = ira_curr_regno_allocno_map[regno]; | |
342f23d2 | 432 | int n; |
be18556f | 433 | enum reg_class cl; |
434 | ira_object_t obj; | |
435 | ||
436 | if (a == NULL) | |
437 | return; | |
438 | ||
439 | /* Invalidate because it is referenced. */ | |
440 | allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; | |
441 | ||
442 | n = ALLOCNO_NUM_OBJECTS (a); | |
443 | if (n == 1) | |
444 | /* The allocno as a whole doesn't die in this case. */ | |
b4f5e198 | 445 | return; |
446 | ||
66d9a7b9 | 447 | cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)]; |
342f23d2 | 448 | gcc_assert |
449 | (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]); | |
be18556f | 450 | |
451 | obj = ALLOCNO_OBJECT (a, subword); | |
452 | if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) | |
453 | return; | |
b4f5e198 | 454 | |
be18556f | 455 | dec_register_pressure (cl, 1); |
456 | make_object_dead (obj); | |
b4f5e198 | 457 | } |
458 | ||
be18556f | 459 | /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
460 | register. */ | |
b4f5e198 | 461 | static void |
462 | mark_hard_reg_dead (rtx reg) | |
463 | { | |
464 | int regno = REGNO (reg); | |
465 | ||
466 | if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) | |
47dd2e78 | 467 | { |
6a298741 | 468 | int last = END_REGNO (reg); |
66d9a7b9 | 469 | enum reg_class aclass, pclass; |
47dd2e78 | 470 | |
471 | while (regno < last) | |
472 | { | |
473 | if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
474 | { | |
66d9a7b9 | 475 | aclass = ira_hard_regno_allocno_class[regno]; |
476 | pclass = ira_pressure_class_translate[aclass]; | |
477 | dec_register_pressure (pclass, 1); | |
b4f5e198 | 478 | make_hard_regno_dead (regno); |
47dd2e78 | 479 | } |
480 | regno++; | |
481 | } | |
482 | } | |
483 | } | |
484 | ||
044621b2 | 485 | /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
486 | register number; ORIG_REG is the access in the insn, which may be a | |
487 | subreg. */ | |
488 | static void | |
489 | mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) | |
490 | { | |
491 | if (df_read_modify_subreg_p (orig_reg)) | |
492 | { | |
493 | mark_pseudo_regno_subword_dead (regno, | |
494 | subreg_lowpart_p (orig_reg) ? 0 : 1); | |
495 | } | |
496 | else | |
497 | mark_pseudo_regno_dead (regno); | |
498 | } | |
499 | ||
793e7497 | 500 | /* Mark the register referenced by definition DEF as dead, if the |
501 | definition is a total one. */ | |
502 | static void | |
ed6e85ae | 503 | mark_ref_dead (df_ref def) |
793e7497 | 504 | { |
be18556f | 505 | rtx reg = DF_REF_REG (def); |
506 | rtx orig_reg = reg; | |
793e7497 | 507 | |
be18556f | 508 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
793e7497 | 509 | return; |
510 | ||
793e7497 | 511 | if (GET_CODE (reg) == SUBREG) |
512 | reg = SUBREG_REG (reg); | |
be18556f | 513 | |
514 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
515 | && (GET_CODE (orig_reg) != SUBREG | |
516 | || REGNO (reg) < FIRST_PSEUDO_REGISTER | |
517 | || !df_read_modify_subreg_p (orig_reg))) | |
518 | return; | |
519 | ||
b4f5e198 | 520 | if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
044621b2 | 521 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
b4f5e198 | 522 | else |
523 | mark_hard_reg_dead (reg); | |
793e7497 | 524 | } |
525 | ||
044621b2 | 526 | /* If REG is a pseudo or a subreg of it, and the class of its allocno |
527 | intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the | |
9d75589a | 528 | rtx actually accessed, it may be identical to DREG or a subreg of it. |
044621b2 | 529 | Advance the current program point before making the conflict if |
530 | ADVANCE_P. Return TRUE if we will need to advance the current | |
531 | program point. */ | |
793e7497 | 532 | static bool |
044621b2 | 533 | make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
534 | bool advance_p) | |
793e7497 | 535 | { |
044621b2 | 536 | rtx orig_reg = reg; |
7173d4d0 | 537 | ira_allocno_t a; |
793e7497 | 538 | |
7173d4d0 | 539 | if (GET_CODE (reg) == SUBREG) |
540 | reg = SUBREG_REG (reg); | |
48e1416a | 541 | |
7173d4d0 | 542 | if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
543 | return advance_p; | |
48e1416a | 544 | |
7173d4d0 | 545 | a = ira_curr_regno_allocno_map[REGNO (reg)]; |
66d9a7b9 | 546 | if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a))) |
7173d4d0 | 547 | return advance_p; |
793e7497 | 548 | |
7173d4d0 | 549 | if (advance_p) |
550 | curr_point++; | |
793e7497 | 551 | |
044621b2 | 552 | mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
553 | mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); | |
554 | mark_pseudo_reg_dead (orig_reg, REGNO (reg)); | |
555 | mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); | |
7173d4d0 | 556 | |
557 | return false; | |
558 | } | |
793e7497 | 559 | |
7173d4d0 | 560 | /* Check and make if necessary conflicts for pseudo DREG of class |
561 | DEF_CL of the current insn with input operand USE of class USE_CL. | |
9d75589a | 562 | ORIG_DREG is the rtx actually accessed, it may be identical to |
044621b2 | 563 | DREG or a subreg of it. Advance the current program point before |
564 | making the conflict if ADVANCE_P. Return TRUE if we will need to | |
565 | advance the current program point. */ | |
7173d4d0 | 566 | static bool |
044621b2 | 567 | check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
568 | enum reg_class def_cl, int use, | |
569 | enum reg_class use_cl, bool advance_p) | |
7173d4d0 | 570 | { |
571 | if (! reg_classes_intersect_p (def_cl, use_cl)) | |
572 | return advance_p; | |
48e1416a | 573 | |
7173d4d0 | 574 | advance_p = make_pseudo_conflict (recog_data.operand[use], |
044621b2 | 575 | use_cl, dreg, orig_dreg, advance_p); |
576 | ||
7173d4d0 | 577 | /* Reload may end up swapping commutative operands, so you |
578 | have to take both orderings into account. The | |
579 | constraints for the two operands can be completely | |
580 | different. (Indeed, if the constraints for the two | |
581 | operands are the same for all alternatives, there's no | |
582 | point marking them as commutative.) */ | |
e91a9c3f | 583 | if (use < recog_data.n_operands - 1 |
7173d4d0 | 584 | && recog_data.constraints[use][0] == '%') |
585 | advance_p | |
586 | = make_pseudo_conflict (recog_data.operand[use + 1], | |
044621b2 | 587 | use_cl, dreg, orig_dreg, advance_p); |
7173d4d0 | 588 | if (use >= 1 |
589 | && recog_data.constraints[use - 1][0] == '%') | |
590 | advance_p | |
591 | = make_pseudo_conflict (recog_data.operand[use - 1], | |
044621b2 | 592 | use_cl, dreg, orig_dreg, advance_p); |
7173d4d0 | 593 | return advance_p; |
594 | } | |
595 | ||
596 | /* Check and make if necessary conflicts for definition DEF of class | |
597 | DEF_CL of the current insn with input operands. Process only | |
598 | constraints of alternative ALT. */ | |
599 | static void | |
600 | check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
601 | { | |
602 | int use, use_match; | |
603 | ira_allocno_t a; | |
604 | enum reg_class use_cl, acl; | |
605 | bool advance_p; | |
606 | rtx dreg = recog_data.operand[def]; | |
044621b2 | 607 | rtx orig_dreg = dreg; |
48e1416a | 608 | |
7173d4d0 | 609 | if (def_cl == NO_REGS) |
610 | return; | |
48e1416a | 611 | |
7173d4d0 | 612 | if (GET_CODE (dreg) == SUBREG) |
613 | dreg = SUBREG_REG (dreg); | |
48e1416a | 614 | |
7173d4d0 | 615 | if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
616 | return; | |
48e1416a | 617 | |
7173d4d0 | 618 | a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
66d9a7b9 | 619 | acl = ALLOCNO_CLASS (a); |
7173d4d0 | 620 | if (! reg_classes_intersect_p (acl, def_cl)) |
621 | return; | |
48e1416a | 622 | |
7173d4d0 | 623 | advance_p = true; |
48e1416a | 624 | |
757fefec | 625 | int n_operands = recog_data.n_operands; |
8eaaac4d | 626 | const operand_alternative *op_alt = &recog_op_alt[alt * n_operands]; |
757fefec | 627 | for (use = 0; use < n_operands; use++) |
7173d4d0 | 628 | { |
d09294c0 | 629 | int alt1; |
630 | ||
7173d4d0 | 631 | if (use == def || recog_data.operand_type[use] == OP_OUT) |
c2b66149 | 632 | continue; |
48e1416a | 633 | |
757fefec | 634 | if (op_alt[use].anything_ok) |
7173d4d0 | 635 | use_cl = ALL_REGS; |
793e7497 | 636 | else |
757fefec | 637 | use_cl = op_alt[use].cl; |
48e1416a | 638 | |
d09294c0 | 639 | /* If there's any alternative that allows USE to match DEF, do not |
640 | record a conflict. If that causes us to create an invalid | |
be18556f | 641 | instruction due to the earlyclobber, reload must fix it up. */ |
d09294c0 | 642 | for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
757fefec | 643 | { |
e1a797ad | 644 | if (!TEST_BIT (preferred_alternatives, alt1)) |
b5b87913 | 645 | continue; |
8eaaac4d | 646 | const operand_alternative *op_alt1 |
647 | = &recog_op_alt[alt1 * n_operands]; | |
757fefec | 648 | if (op_alt1[use].matches == def |
649 | || (use < n_operands - 1 | |
650 | && recog_data.constraints[use][0] == '%' | |
651 | && op_alt1[use + 1].matches == def) | |
652 | || (use >= 1 | |
653 | && recog_data.constraints[use - 1][0] == '%' | |
654 | && op_alt1[use - 1].matches == def)) | |
655 | break; | |
656 | } | |
d09294c0 | 657 | |
658 | if (alt1 < recog_data.n_alternatives) | |
659 | continue; | |
660 | ||
044621b2 | 661 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
662 | use, use_cl, advance_p); | |
48e1416a | 663 | |
757fefec | 664 | if ((use_match = op_alt[use].matches) >= 0) |
7173d4d0 | 665 | { |
666 | if (use_match == def) | |
c2b66149 | 667 | continue; |
48e1416a | 668 | |
757fefec | 669 | if (op_alt[use_match].anything_ok) |
7173d4d0 | 670 | use_cl = ALL_REGS; |
671 | else | |
757fefec | 672 | use_cl = op_alt[use_match].cl; |
044621b2 | 673 | advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
674 | use, use_cl, advance_p); | |
7173d4d0 | 675 | } |
793e7497 | 676 | } |
7173d4d0 | 677 | } |
678 | ||
679 | /* Make conflicts of early clobber pseudo registers of the current | |
680 | insn with its inputs. Avoid introducing unnecessary conflicts by | |
681 | checking classes of the constraints and pseudos because otherwise | |
682 | significant code degradation is possible for some targets. */ | |
683 | static void | |
684 | make_early_clobber_and_input_conflicts (void) | |
685 | { | |
686 | int alt; | |
687 | int def, def_match; | |
688 | enum reg_class def_cl; | |
689 | ||
757fefec | 690 | int n_alternatives = recog_data.n_alternatives; |
691 | int n_operands = recog_data.n_operands; | |
8eaaac4d | 692 | const operand_alternative *op_alt = recog_op_alt; |
757fefec | 693 | for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands) |
e1a797ad | 694 | if (TEST_BIT (preferred_alternatives, alt)) |
b5b87913 | 695 | for (def = 0; def < n_operands; def++) |
696 | { | |
697 | def_cl = NO_REGS; | |
698 | if (op_alt[def].earlyclobber) | |
699 | { | |
700 | if (op_alt[def].anything_ok) | |
701 | def_cl = ALL_REGS; | |
702 | else | |
703 | def_cl = op_alt[def].cl; | |
704 | check_and_make_def_conflict (alt, def, def_cl); | |
705 | } | |
706 | if ((def_match = op_alt[def].matches) >= 0 | |
707 | && (op_alt[def_match].earlyclobber | |
708 | || op_alt[def].earlyclobber)) | |
709 | { | |
710 | if (op_alt[def_match].anything_ok) | |
711 | def_cl = ALL_REGS; | |
712 | else | |
713 | def_cl = op_alt[def_match].cl; | |
714 | check_and_make_def_conflict (alt, def, def_cl); | |
715 | } | |
716 | } | |
7173d4d0 | 717 | } |
718 | ||
719 | /* Mark early clobber hard registers of the current INSN as live (if | |
720 | LIVE_P) or dead. Return true if there are such registers. */ | |
721 | static bool | |
56067879 | 722 | mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p) |
7173d4d0 | 723 | { |
be10bb5a | 724 | df_ref def; |
7173d4d0 | 725 | bool set_p = false; |
793e7497 | 726 | |
be10bb5a | 727 | FOR_EACH_INSN_DEF (def, insn) |
728 | if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)) | |
793e7497 | 729 | { |
be10bb5a | 730 | rtx dreg = DF_REF_REG (def); |
48e1416a | 731 | |
793e7497 | 732 | if (GET_CODE (dreg) == SUBREG) |
733 | dreg = SUBREG_REG (dreg); | |
734 | if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
735 | continue; | |
736 | ||
737 | /* Hard register clobbers are believed to be early clobber | |
738 | because there is no way to say that non-operand hard | |
48e1416a | 739 | register clobbers are not early ones. */ |
793e7497 | 740 | if (live_p) |
be10bb5a | 741 | mark_ref_live (def); |
793e7497 | 742 | else |
be10bb5a | 743 | mark_ref_dead (def); |
793e7497 | 744 | set_p = true; |
745 | } | |
746 | ||
747 | return set_p; | |
748 | } | |
749 | ||
47dd2e78 | 750 | /* Checks that CONSTRAINTS permits to use only one hard register. If |
751 | it is so, the function returns the class of the hard register. | |
752 | Otherwise it returns NO_REGS. */ | |
753 | static enum reg_class | |
754 | single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
755 | { | |
d2b854bc | 756 | int c; |
47dd2e78 | 757 | enum reg_class cl, next_cl; |
79bc09fb | 758 | enum constraint_num cn; |
47dd2e78 | 759 | |
760 | cl = NO_REGS; | |
e1a797ad | 761 | alternative_mask preferred = preferred_alternatives; |
d2b854bc | 762 | for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)) |
763 | if (c == '#') | |
e1a797ad | 764 | preferred &= ~ALTERNATIVE_BIT (0); |
47dd2e78 | 765 | else if (c == ',') |
e1a797ad | 766 | preferred >>= 1; |
767 | else if (preferred & 1) | |
47dd2e78 | 768 | switch (c) |
769 | { | |
69449463 | 770 | case 'g': |
771 | return NO_REGS; | |
48e1416a | 772 | |
69449463 | 773 | default: |
c91b6d86 | 774 | /* ??? Is this the best way to handle memory constraints? */ |
79bc09fb | 775 | cn = lookup_constraint (constraints); |
776 | if (insn_extra_memory_constraint (cn) | |
777 | || insn_extra_address_constraint (cn)) | |
c91b6d86 | 778 | return NO_REGS; |
79bc09fb | 779 | if (constraint_satisfied_p (op, cn) |
c91b6d86 | 780 | || (equiv_const != NULL_RTX |
781 | && CONSTANT_P (equiv_const) | |
79bc09fb | 782 | && constraint_satisfied_p (equiv_const, cn))) |
c91b6d86 | 783 | return NO_REGS; |
69449463 | 784 | next_cl = reg_class_for_constraint (cn); |
c91b6d86 | 785 | if (next_cl == NO_REGS) |
786 | break; | |
c259678f | 787 | if (cl == NO_REGS |
788 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
789 | : (ira_class_singleton[cl][GET_MODE (op)] | |
790 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
47dd2e78 | 791 | return NO_REGS; |
792 | cl = next_cl; | |
793 | break; | |
48e1416a | 794 | |
47dd2e78 | 795 | case '0': case '1': case '2': case '3': case '4': |
796 | case '5': case '6': case '7': case '8': case '9': | |
797 | next_cl | |
798 | = single_reg_class (recog_data.constraints[c - '0'], | |
799 | recog_data.operand[c - '0'], NULL_RTX); | |
c259678f | 800 | if (cl == NO_REGS |
801 | ? ira_class_singleton[next_cl][GET_MODE (op)] < 0 | |
802 | : (ira_class_singleton[cl][GET_MODE (op)] | |
803 | != ira_class_singleton[next_cl][GET_MODE (op)])) | |
47dd2e78 | 804 | return NO_REGS; |
805 | cl = next_cl; | |
806 | break; | |
47dd2e78 | 807 | } |
808 | return cl; | |
809 | } | |
810 | ||
811 | /* The function checks that operand OP_NUM of the current insn can use | |
812 | only one hard register. If it is so, the function returns the | |
813 | class of the hard register. Otherwise it returns NO_REGS. */ | |
814 | static enum reg_class | |
815 | single_reg_operand_class (int op_num) | |
816 | { | |
817 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
818 | return NO_REGS; | |
819 | return single_reg_class (recog_data.constraints[op_num], | |
820 | recog_data.operand[op_num], NULL_RTX); | |
821 | } | |
822 | ||
a7dcf969 | 823 | /* The function sets up hard register set *SET to hard registers which |
824 | might be used by insn reloads because the constraints are too | |
825 | strict. */ | |
826 | void | |
ca3be54b | 827 | ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set, |
828 | alternative_mask preferred) | |
a7dcf969 | 829 | { |
d2b854bc | 830 | int i, c, regno = 0; |
a7dcf969 | 831 | enum reg_class cl; |
832 | rtx op; | |
3754d046 | 833 | machine_mode mode; |
a7dcf969 | 834 | |
835 | CLEAR_HARD_REG_SET (*set); | |
836 | for (i = 0; i < recog_data.n_operands; i++) | |
837 | { | |
838 | op = recog_data.operand[i]; | |
839 | ||
840 | if (GET_CODE (op) == SUBREG) | |
841 | op = SUBREG_REG (op); | |
48e1416a | 842 | |
a7dcf969 | 843 | if (GET_CODE (op) == SCRATCH |
844 | || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) | |
845 | { | |
846 | const char *p = recog_data.constraints[i]; | |
847 | ||
848 | mode = (GET_CODE (op) == SCRATCH | |
849 | ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); | |
850 | cl = NO_REGS; | |
d2b854bc | 851 | for (; (c = *p); p += CONSTRAINT_LEN (c, p)) |
852 | if (c == '#') | |
e1a797ad | 853 | preferred &= ~ALTERNATIVE_BIT (0); |
a7dcf969 | 854 | else if (c == ',') |
e1a797ad | 855 | preferred >>= 1; |
856 | else if (preferred & 1) | |
69449463 | 857 | { |
858 | cl = reg_class_for_constraint (lookup_constraint (p)); | |
859 | if (cl != NO_REGS) | |
860 | { | |
861 | /* There is no register pressure problem if all of the | |
862 | regs in this class are fixed. */ | |
863 | int regno = ira_class_singleton[cl][mode]; | |
864 | if (regno >= 0) | |
865 | add_to_hard_reg_set (set, mode, regno); | |
866 | } | |
867 | } | |
a7dcf969 | 868 | } |
869 | } | |
870 | } | |
47dd2e78 | 871 | /* Processes input operands, if IN_P, or output operands otherwise of |
872 | the current insn with FREQ to find allocno which can use only one | |
873 | hard register and makes other currently living allocnos conflicting | |
874 | with the hard register. */ | |
875 | static void | |
876 | process_single_reg_class_operands (bool in_p, int freq) | |
877 | { | |
744d7848 | 878 | int i, regno; |
47dd2e78 | 879 | unsigned int px; |
da7a04f1 | 880 | enum reg_class cl; |
47dd2e78 | 881 | rtx operand; |
882 | ira_allocno_t operand_a, a; | |
883 | ||
884 | for (i = 0; i < recog_data.n_operands; i++) | |
885 | { | |
886 | operand = recog_data.operand[i]; | |
887 | if (in_p && recog_data.operand_type[i] != OP_IN | |
888 | && recog_data.operand_type[i] != OP_INOUT) | |
889 | continue; | |
890 | if (! in_p && recog_data.operand_type[i] != OP_OUT | |
891 | && recog_data.operand_type[i] != OP_INOUT) | |
892 | continue; | |
893 | cl = single_reg_operand_class (i); | |
894 | if (cl == NO_REGS) | |
895 | continue; | |
896 | ||
897 | operand_a = NULL; | |
898 | ||
899 | if (GET_CODE (operand) == SUBREG) | |
900 | operand = SUBREG_REG (operand); | |
48e1416a | 901 | |
47dd2e78 | 902 | if (REG_P (operand) |
903 | && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
904 | { | |
66d9a7b9 | 905 | enum reg_class aclass; |
47dd2e78 | 906 | |
907 | operand_a = ira_curr_regno_allocno_map[regno]; | |
66d9a7b9 | 908 | aclass = ALLOCNO_CLASS (operand_a); |
c259678f | 909 | if (ira_class_subset_p[cl][aclass]) |
47dd2e78 | 910 | { |
744d7848 | 911 | /* View the desired allocation of OPERAND as: |
912 | ||
913 | (REG:YMODE YREGNO), | |
914 | ||
915 | a simplification of: | |
916 | ||
917 | (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ | |
3754d046 | 918 | machine_mode ymode, xmode; |
744d7848 | 919 | int xregno, yregno; |
920 | HOST_WIDE_INT offset; | |
921 | ||
922 | xmode = recog_data.operand_mode[i]; | |
c259678f | 923 | xregno = ira_class_singleton[cl][xmode]; |
924 | gcc_assert (xregno >= 0); | |
744d7848 | 925 | ymode = ALLOCNO_MODE (operand_a); |
926 | offset = subreg_lowpart_offset (ymode, xmode); | |
927 | yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); | |
928 | if (yregno >= 0 | |
66d9a7b9 | 929 | && ira_class_hard_reg_index[aclass][yregno] >= 0) |
744d7848 | 930 | { |
931 | int cost; | |
932 | ||
933 | ira_allocate_and_set_costs | |
934 | (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), | |
66d9a7b9 | 935 | aclass, 0); |
936 | ira_init_register_move_cost_if_necessary (xmode); | |
937 | cost = freq * (in_p | |
938 | ? ira_register_move_cost[xmode][aclass][cl] | |
939 | : ira_register_move_cost[xmode][cl][aclass]); | |
744d7848 | 940 | ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
66d9a7b9 | 941 | [ira_class_hard_reg_index[aclass][yregno]] -= cost; |
744d7848 | 942 | } |
47dd2e78 | 943 | } |
944 | } | |
945 | ||
be18556f | 946 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
47dd2e78 | 947 | { |
be18556f | 948 | ira_object_t obj = ira_object_id_map[px]; |
949 | a = OBJECT_ALLOCNO (obj); | |
47dd2e78 | 950 | if (a != operand_a) |
951 | { | |
952 | /* We could increase costs of A instead of making it | |
953 | conflicting with the hard register. But it works worse | |
954 | because it will be spilled in reload in anyway. */ | |
ae9587ed | 955 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
47dd2e78 | 956 | reg_class_contents[cl]); |
ae9587ed | 957 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
47dd2e78 | 958 | reg_class_contents[cl]); |
959 | } | |
960 | } | |
961 | } | |
962 | } | |
963 | ||
c8010b80 | 964 | /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if |
965 | we find a SET rtx that we can use to deduce that a register can be cheaply | |
966 | caller-saved. Return such a register, or NULL_RTX if none is found. */ | |
967 | static rtx | |
56067879 | 968 | find_call_crossed_cheap_reg (rtx_insn *insn) |
c8010b80 | 969 | { |
970 | rtx cheap_reg = NULL_RTX; | |
971 | rtx exp = CALL_INSN_FUNCTION_USAGE (insn); | |
972 | ||
973 | while (exp != NULL) | |
974 | { | |
975 | rtx x = XEXP (exp, 0); | |
976 | if (GET_CODE (x) == SET) | |
977 | { | |
978 | exp = x; | |
979 | break; | |
980 | } | |
981 | exp = XEXP (exp, 1); | |
982 | } | |
983 | if (exp != NULL) | |
984 | { | |
985 | basic_block bb = BLOCK_FOR_INSN (insn); | |
986 | rtx reg = SET_SRC (exp); | |
fde37bf5 | 987 | rtx_insn *prev = PREV_INSN (insn); |
c8010b80 | 988 | while (prev && !(INSN_P (prev) |
989 | && BLOCK_FOR_INSN (prev) != bb)) | |
990 | { | |
991 | if (NONDEBUG_INSN_P (prev)) | |
992 | { | |
993 | rtx set = single_set (prev); | |
994 | ||
995 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
996 | { | |
997 | rtx src = SET_SRC (set); | |
998 | if (!REG_P (src) || HARD_REGISTER_P (src) | |
999 | || !pseudo_regno_single_word_and_live_p (REGNO (src))) | |
1000 | break; | |
1001 | if (!modified_between_p (src, prev, insn)) | |
1002 | cheap_reg = src; | |
1003 | break; | |
1004 | } | |
1005 | if (set && rtx_equal_p (SET_SRC (set), reg)) | |
1006 | { | |
1007 | rtx dest = SET_DEST (set); | |
1008 | if (!REG_P (dest) || HARD_REGISTER_P (dest) | |
1009 | || !pseudo_regno_single_word_and_live_p (REGNO (dest))) | |
1010 | break; | |
1011 | if (!modified_between_p (dest, prev, insn)) | |
1012 | cheap_reg = dest; | |
1013 | break; | |
1014 | } | |
1015 | ||
1016 | if (reg_overlap_mentioned_p (reg, PATTERN (prev))) | |
1017 | break; | |
1018 | } | |
1019 | prev = PREV_INSN (prev); | |
1020 | } | |
1021 | } | |
1022 | return cheap_reg; | |
1023 | } | |
1024 | ||
47dd2e78 | 1025 | /* Process insns of the basic block given by its LOOP_TREE_NODE to |
1026 | update allocno live ranges, allocno hard register conflicts, | |
1027 | intersected calls, and register pressure info for allocnos for the | |
1028 | basic block for and regions containing the basic block. */ | |
1029 | static void | |
1030 | process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
1031 | { | |
7e03a244 | 1032 | int i, freq; |
47dd2e78 | 1033 | unsigned int j; |
1034 | basic_block bb; | |
56067879 | 1035 | rtx_insn *insn; |
47dd2e78 | 1036 | bitmap_iterator bi; |
7e03a244 | 1037 | bitmap reg_live_out; |
47dd2e78 | 1038 | unsigned int px; |
793e7497 | 1039 | bool set_p; |
47dd2e78 | 1040 | |
1041 | bb = loop_tree_node->bb; | |
1042 | if (bb != NULL) | |
1043 | { | |
66d9a7b9 | 1044 | for (i = 0; i < ira_pressure_classes_num; i++) |
47dd2e78 | 1045 | { |
66d9a7b9 | 1046 | curr_reg_pressure[ira_pressure_classes[i]] = 0; |
1047 | high_pressure_start_point[ira_pressure_classes[i]] = -1; | |
47dd2e78 | 1048 | } |
1049 | curr_bb_node = loop_tree_node; | |
0841d295 | 1050 | reg_live_out = df_get_live_out (bb); |
be18556f | 1051 | sparseset_clear (objects_live); |
7e03a244 | 1052 | REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
47dd2e78 | 1053 | AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); |
1054 | AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
1055 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1056 | if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
1057 | { | |
66d9a7b9 | 1058 | enum reg_class aclass, pclass, cl; |
48e1416a | 1059 | |
66d9a7b9 | 1060 | aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)]; |
1061 | pclass = ira_pressure_class_translate[aclass]; | |
14792f4e | 1062 | for (j = 0; |
66d9a7b9 | 1063 | (cl = ira_reg_class_super_classes[pclass][j]) |
14792f4e | 1064 | != LIM_REG_CLASSES; |
1065 | j++) | |
1066 | { | |
66d9a7b9 | 1067 | if (! ira_reg_pressure_class_p[cl]) |
1068 | continue; | |
14792f4e | 1069 | curr_reg_pressure[cl]++; |
1070 | if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
1071 | curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
1072 | ira_assert (curr_reg_pressure[cl] | |
1072fecf | 1073 | <= ira_class_hard_regs_num[cl]); |
14792f4e | 1074 | } |
47dd2e78 | 1075 | } |
7e03a244 | 1076 | EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) |
b4f5e198 | 1077 | mark_pseudo_regno_live (j); |
48e1416a | 1078 | |
7e03a244 | 1079 | freq = REG_FREQ_FROM_BB (bb); |
1080 | if (freq == 0) | |
1081 | freq = 1; | |
1082 | ||
df07a54c | 1083 | /* Invalidate all allocno_saved_at_call entries. */ |
1084 | last_call_num++; | |
1085 | ||
47dd2e78 | 1086 | /* Scan the code of this basic block, noting which allocnos and |
7e03a244 | 1087 | hard regs are born or die. |
1088 | ||
1089 | Note that this loop treats uninitialized values as live until | |
1090 | the beginning of the block. For example, if an instruction | |
1091 | uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
1092 | set, FOO will remain live until the beginning of the block. | |
1093 | Likewise if FOO is not set at all. This is unnecessarily | |
1094 | pessimistic, but it probably doesn't matter much in practice. */ | |
1095 | FOR_BB_INSNS_REVERSE (bb, insn) | |
47dd2e78 | 1096 | { |
0f0f5d1a | 1097 | ira_allocno_t a; |
be10bb5a | 1098 | df_ref def, use; |
e73e23ef | 1099 | bool call_p; |
48e1416a | 1100 | |
9845d120 | 1101 | if (!NONDEBUG_INSN_P (insn)) |
47dd2e78 | 1102 | continue; |
48e1416a | 1103 | |
47dd2e78 | 1104 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
1105 | fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
9f8ac546 | 1106 | INSN_UID (insn), loop_tree_node->parent->loop_num, |
47dd2e78 | 1107 | curr_point); |
1108 | ||
0f0f5d1a | 1109 | call_p = CALL_P (insn); |
e73e23ef | 1110 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
1111 | int regno; | |
1112 | bool clear_pic_use_conflict_p = false; | |
0f0f5d1a | 1113 | /* Processing insn usage in call insn can create conflict |
1114 | with pic pseudo and pic hard reg and that is wrong. | |
1115 | Check this situation and fix it at the end of the insn | |
1116 | processing. */ | |
1117 | if (call_p && pic_offset_table_rtx != NULL_RTX | |
1118 | && (regno = REGNO (pic_offset_table_rtx)) >= FIRST_PSEUDO_REGISTER | |
1119 | && (a = ira_curr_regno_allocno_map[regno]) != NULL) | |
1120 | clear_pic_use_conflict_p | |
1121 | = (find_regno_fusage (insn, USE, REAL_PIC_OFFSET_TABLE_REGNUM) | |
1122 | && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS | |
1123 | (ALLOCNO_OBJECT (a, 0)), | |
1124 | REAL_PIC_OFFSET_TABLE_REGNUM)); | |
e73e23ef | 1125 | #endif |
0f0f5d1a | 1126 | |
7e03a244 | 1127 | /* Mark each defined value as live. We need to do this for |
1128 | unused values because they still conflict with quantities | |
1129 | that are live at the time of the definition. | |
1130 | ||
1131 | Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
1132 | references represent the effect of the called function | |
1133 | on a call-clobbered register. Marking the register as | |
1134 | live would stop us from allocating it to a call-crossing | |
1135 | allocno. */ | |
be10bb5a | 1136 | FOR_EACH_INSN_DEF (def, insn) |
1137 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1138 | mark_ref_live (def); | |
7e03a244 | 1139 | |
1140 | /* If INSN has multiple outputs, then any value used in one | |
1141 | of the outputs conflicts with the other outputs. Model this | |
1142 | by making the used value live during the output phase. | |
1143 | ||
1144 | It is unsafe to use !single_set here since it will ignore | |
1145 | an unused output. Just because an output is unused does | |
1146 | not mean the compiler can assume the side effect will not | |
1147 | occur. Consider if ALLOCNO appears in the address of an | |
1148 | output and we reload the output. If we allocate ALLOCNO | |
1149 | to the same hard register as an unused output we could | |
1150 | set the hard register before the output reload insn. */ | |
1151 | if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
be10bb5a | 1152 | FOR_EACH_INSN_USE (use, insn) |
7e03a244 | 1153 | { |
1154 | int i; | |
1155 | rtx reg; | |
1156 | ||
be10bb5a | 1157 | reg = DF_REF_REG (use); |
7e03a244 | 1158 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) |
1159 | { | |
1160 | rtx set; | |
1161 | ||
1162 | set = XVECEXP (PATTERN (insn), 0, i); | |
1163 | if (GET_CODE (set) == SET | |
1164 | && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1165 | { | |
1166 | /* After the previous loop, this is a no-op if | |
1167 | REG is contained within SET_DEST (SET). */ | |
be10bb5a | 1168 | mark_ref_live (use); |
7e03a244 | 1169 | break; |
1170 | } | |
1171 | } | |
1172 | } | |
48e1416a | 1173 | |
47dd2e78 | 1174 | extract_insn (insn); |
e1a797ad | 1175 | preferred_alternatives = get_preferred_alternatives (insn); |
8eaaac4d | 1176 | preprocess_constraints (insn); |
7e03a244 | 1177 | process_single_reg_class_operands (false, freq); |
48e1416a | 1178 | |
7e03a244 | 1179 | /* See which defined values die here. */ |
be10bb5a | 1180 | FOR_EACH_INSN_DEF (def, insn) |
1181 | if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
1182 | mark_ref_dead (def); | |
47dd2e78 | 1183 | |
7e03a244 | 1184 | if (call_p) |
47dd2e78 | 1185 | { |
c8010b80 | 1186 | /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from |
1187 | there, try to find a pseudo that is live across the call but | |
1188 | can be cheaply reconstructed from the return value. */ | |
1189 | rtx cheap_reg = find_call_crossed_cheap_reg (insn); | |
1190 | if (cheap_reg != NULL_RTX) | |
1191 | add_reg_note (insn, REG_RETURNED, cheap_reg); | |
1192 | ||
df07a54c | 1193 | last_call_num++; |
be18556f | 1194 | sparseset_clear (allocnos_processed); |
7e03a244 | 1195 | /* The current set of live allocnos are live across the call. */ |
be18556f | 1196 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
47dd2e78 | 1197 | { |
be18556f | 1198 | ira_object_t obj = ira_object_id_map[i]; |
0f0f5d1a | 1199 | a = OBJECT_ALLOCNO (obj); |
be18556f | 1200 | int num = ALLOCNO_NUM (a); |
754158d9 | 1201 | HARD_REG_SET this_call_used_reg_set; |
1202 | ||
1203 | get_call_reg_set_usage (insn, &this_call_used_reg_set, | |
1204 | call_used_reg_set); | |
48e1416a | 1205 | |
d6a421d5 | 1206 | /* Don't allocate allocnos that cross setjmps or any |
1207 | call, if this function receives a nonlocal | |
1208 | goto. */ | |
1209 | if (cfun->has_nonlocal_label | |
1210 | || find_reg_note (insn, REG_SETJMP, | |
1211 | NULL_RTX) != NULL_RTX) | |
47dd2e78 | 1212 | { |
ae9587ed | 1213 | SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
1214 | SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); | |
47dd2e78 | 1215 | } |
cab55469 | 1216 | if (can_throw_internal (insn)) |
1217 | { | |
ae9587ed | 1218 | IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
754158d9 | 1219 | this_call_used_reg_set); |
be18556f | 1220 | IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
754158d9 | 1221 | this_call_used_reg_set); |
cab55469 | 1222 | } |
be18556f | 1223 | |
1224 | if (sparseset_bit_p (allocnos_processed, num)) | |
1225 | continue; | |
1226 | sparseset_set_bit (allocnos_processed, num); | |
1227 | ||
1228 | if (allocno_saved_at_call[num] != last_call_num) | |
b59bd98f | 1229 | /* Here we are mimicking caller-save.c behavior |
be18556f | 1230 | which does not save hard register at a call if |
1231 | it was saved on previous call in the same basic | |
1232 | block and the hard register was not mentioned | |
1233 | between the two calls. */ | |
1234 | ALLOCNO_CALL_FREQ (a) += freq; | |
1235 | /* Mark it as saved at the next call. */ | |
1236 | allocno_saved_at_call[num] = last_call_num + 1; | |
1237 | ALLOCNO_CALLS_CROSSED_NUM (a)++; | |
754158d9 | 1238 | IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a), |
1239 | this_call_used_reg_set); | |
c8010b80 | 1240 | if (cheap_reg != NULL_RTX |
1241 | && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg)) | |
1242 | ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++; | |
47dd2e78 | 1243 | } |
1244 | } | |
48e1416a | 1245 | |
7173d4d0 | 1246 | make_early_clobber_and_input_conflicts (); |
1247 | ||
7e03a244 | 1248 | curr_point++; |
0f0f5d1a | 1249 | |
7e03a244 | 1250 | /* Mark each used value as live. */ |
be10bb5a | 1251 | FOR_EACH_INSN_USE (use, insn) |
1252 | mark_ref_live (use); | |
7e03a244 | 1253 | |
7e03a244 | 1254 | process_single_reg_class_operands (true, freq); |
48e1416a | 1255 | |
7173d4d0 | 1256 | set_p = mark_hard_reg_early_clobbers (insn, true); |
1257 | ||
793e7497 | 1258 | if (set_p) |
1259 | { | |
7173d4d0 | 1260 | mark_hard_reg_early_clobbers (insn, false); |
793e7497 | 1261 | |
7173d4d0 | 1262 | /* Mark each hard reg as live again. For example, a |
793e7497 | 1263 | hard register can be in clobber and in an insn |
1264 | input. */ | |
be10bb5a | 1265 | FOR_EACH_INSN_USE (use, insn) |
7173d4d0 | 1266 | { |
be10bb5a | 1267 | rtx ureg = DF_REF_REG (use); |
48e1416a | 1268 | |
7173d4d0 | 1269 | if (GET_CODE (ureg) == SUBREG) |
1270 | ureg = SUBREG_REG (ureg); | |
1271 | if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
1272 | continue; | |
48e1416a | 1273 | |
be10bb5a | 1274 | mark_ref_live (use); |
7173d4d0 | 1275 | } |
793e7497 | 1276 | } |
47dd2e78 | 1277 | |
e73e23ef | 1278 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM |
0f0f5d1a | 1279 | if (clear_pic_use_conflict_p) |
1280 | { | |
1281 | regno = REGNO (pic_offset_table_rtx); | |
1282 | a = ira_curr_regno_allocno_map[regno]; | |
1283 | CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a, 0)), | |
1284 | REAL_PIC_OFFSET_TABLE_REGNUM); | |
1285 | CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS | |
1286 | (ALLOCNO_OBJECT (a, 0)), | |
1287 | REAL_PIC_OFFSET_TABLE_REGNUM); | |
1288 | } | |
e73e23ef | 1289 | #endif |
47dd2e78 | 1290 | curr_point++; |
1291 | } | |
7e03a244 | 1292 | |
fee75d9b | 1293 | if (bb_has_eh_pred (bb)) |
1294 | for (j = 0; ; ++j) | |
1295 | { | |
1296 | unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
1297 | if (regno == INVALID_REGNUM) | |
1298 | break; | |
b4f5e198 | 1299 | make_hard_regno_born (regno); |
fee75d9b | 1300 | } |
fee75d9b | 1301 | |
7e03a244 | 1302 | /* Allocnos can't go in stack regs at the start of a basic block |
1303 | that is reached by an abnormal edge. Likewise for call | |
1304 | clobbered regs, because caller-save, fixup_abnormal_edges and | |
1305 | possibly the table driven EH machinery are not quite ready to | |
1306 | handle such allocnos live across such edges. */ | |
fee75d9b | 1307 | if (bb_has_abnormal_pred (bb)) |
7e03a244 | 1308 | { |
1309 | #ifdef STACK_REGS | |
be18556f | 1310 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
7e03a244 | 1311 | { |
be18556f | 1312 | ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
66d9a7b9 | 1313 | |
be18556f | 1314 | ALLOCNO_NO_STACK_REG_P (a) = true; |
1315 | ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; | |
7e03a244 | 1316 | } |
1317 | for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
b4f5e198 | 1318 | make_hard_regno_born (px); |
7e03a244 | 1319 | #endif |
1320 | /* No need to record conflicts for call clobbered regs if we | |
1321 | have nonlocal labels around, as we don't ever try to | |
1322 | allocate such regs in this case. */ | |
a0a565a9 | 1323 | if (!cfun->has_nonlocal_label |
1324 | && has_abnormal_call_or_eh_pred_edge_p (bb)) | |
7e03a244 | 1325 | for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
15d96f90 | 1326 | if (call_used_regs[px] |
1327 | #ifdef REAL_PIC_OFFSET_TABLE_REGNUM | |
1328 | /* We should create a conflict of PIC pseudo with | |
1329 | PIC hard reg as PIC hard reg can have a wrong | |
1330 | value after jump described by the abnormal edge. | |
1331 | In this case we can not allocate PIC hard reg to | |
1332 | PIC pseudo as PIC pseudo will also have a wrong | |
1333 | value. This code is not critical as LRA can fix | |
1334 | it but it is better to have the right allocation | |
1335 | earlier. */ | |
1336 | || (px == REAL_PIC_OFFSET_TABLE_REGNUM | |
1337 | && pic_offset_table_rtx != NULL_RTX | |
1338 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
1339 | #endif | |
1340 | ) | |
b4f5e198 | 1341 | make_hard_regno_born (px); |
7e03a244 | 1342 | } |
1343 | ||
be18556f | 1344 | EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
1345 | make_object_dead (ira_object_id_map[i]); | |
47dd2e78 | 1346 | |
1347 | curr_point++; | |
1348 | ||
1349 | } | |
3ad55f68 | 1350 | /* Propagate register pressure to upper loop tree nodes. */ |
47dd2e78 | 1351 | if (loop_tree_node != ira_loop_tree_root) |
66d9a7b9 | 1352 | for (i = 0; i < ira_pressure_classes_num; i++) |
47dd2e78 | 1353 | { |
66d9a7b9 | 1354 | enum reg_class pclass; |
47dd2e78 | 1355 | |
66d9a7b9 | 1356 | pclass = ira_pressure_classes[i]; |
1357 | if (loop_tree_node->reg_pressure[pclass] | |
1358 | > loop_tree_node->parent->reg_pressure[pclass]) | |
1359 | loop_tree_node->parent->reg_pressure[pclass] | |
1360 | = loop_tree_node->reg_pressure[pclass]; | |
47dd2e78 | 1361 | } |
1362 | } | |
1363 | ||
1364 | /* Create and set up IRA_START_POINT_RANGES and | |
1365 | IRA_FINISH_POINT_RANGES. */ | |
1366 | static void | |
1367 | create_start_finish_chains (void) | |
1368 | { | |
be18556f | 1369 | ira_object_t obj; |
1370 | ira_object_iterator oi; | |
fbff82f4 | 1371 | live_range_t r; |
47dd2e78 | 1372 | |
1373 | ira_start_point_ranges | |
be18556f | 1374 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1375 | memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
47dd2e78 | 1376 | ira_finish_point_ranges |
be18556f | 1377 | = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
1378 | memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); | |
1379 | FOR_EACH_OBJECT (obj, oi) | |
1380 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1381 | { | |
1382 | r->start_next = ira_start_point_ranges[r->start]; | |
1383 | ira_start_point_ranges[r->start] = r; | |
1384 | r->finish_next = ira_finish_point_ranges[r->finish]; | |
47dd2e78 | 1385 | ira_finish_point_ranges[r->finish] = r; |
be18556f | 1386 | } |
47dd2e78 | 1387 | } |
1388 | ||
1389 | /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
1390 | new live ranges and program points were added as a result if new | |
1391 | insn generation. */ | |
1392 | void | |
1393 | ira_rebuild_start_finish_chains (void) | |
1394 | { | |
1395 | ira_free (ira_finish_point_ranges); | |
1396 | ira_free (ira_start_point_ranges); | |
1397 | create_start_finish_chains (); | |
1398 | } | |
1399 | ||
7f36fbdf | 1400 | /* Compress allocno live ranges by removing program points where |
1401 | nothing happens. */ | |
1402 | static void | |
1403 | remove_some_program_points_and_update_live_ranges (void) | |
1404 | { | |
1405 | unsigned i; | |
1406 | int n; | |
1407 | int *map; | |
9d53e372 | 1408 | ira_object_t obj; |
1409 | ira_object_iterator oi; | |
d068a2f3 | 1410 | live_range_t r, prev_r, next_r; |
82cc92bf | 1411 | sbitmap born_or_dead, born, dead; |
1412 | sbitmap_iterator sbi; | |
1413 | bool born_p, dead_p, prev_born_p, prev_dead_p; | |
1414 | ||
1415 | born = sbitmap_alloc (ira_max_point); | |
1416 | dead = sbitmap_alloc (ira_max_point); | |
53c5d9d4 | 1417 | bitmap_clear (born); |
1418 | bitmap_clear (dead); | |
9d53e372 | 1419 | FOR_EACH_OBJECT (obj, oi) |
1420 | for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) | |
1421 | { | |
1422 | ira_assert (r->start <= r->finish); | |
08b7917c | 1423 | bitmap_set_bit (born, r->start); |
1424 | bitmap_set_bit (dead, r->finish); | |
9d53e372 | 1425 | } |
1426 | ||
82cc92bf | 1427 | born_or_dead = sbitmap_alloc (ira_max_point); |
53c5d9d4 | 1428 | bitmap_ior (born_or_dead, born, dead); |
7f36fbdf | 1429 | map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
82cc92bf | 1430 | n = -1; |
1431 | prev_born_p = prev_dead_p = false; | |
0d211963 | 1432 | EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi) |
7f36fbdf | 1433 | { |
08b7917c | 1434 | born_p = bitmap_bit_p (born, i); |
1435 | dead_p = bitmap_bit_p (dead, i); | |
82cc92bf | 1436 | if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
1437 | || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) | |
1438 | map[i] = n; | |
1439 | else | |
1440 | map[i] = ++n; | |
1441 | prev_born_p = born_p; | |
1442 | prev_dead_p = dead_p; | |
7f36fbdf | 1443 | } |
82cc92bf | 1444 | sbitmap_free (born_or_dead); |
1445 | sbitmap_free (born); | |
1446 | sbitmap_free (dead); | |
1447 | n++; | |
7f36fbdf | 1448 | if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
1449 | fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
1450 | ira_max_point, n, 100 * n / ira_max_point); | |
1451 | ira_max_point = n; | |
9d53e372 | 1452 | |
1453 | FOR_EACH_OBJECT (obj, oi) | |
d068a2f3 | 1454 | for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r) |
9d53e372 | 1455 | { |
d068a2f3 | 1456 | next_r = r->next; |
9d53e372 | 1457 | r->start = map[r->start]; |
1458 | r->finish = map[r->finish]; | |
d068a2f3 | 1459 | if (prev_r == NULL || prev_r->start > r->finish + 1) |
1460 | { | |
1461 | prev_r = r; | |
1462 | continue; | |
1463 | } | |
1464 | prev_r->start = r->start; | |
1465 | prev_r->next = next_r; | |
1466 | ira_finish_live_range (r); | |
9d53e372 | 1467 | } |
be18556f | 1468 | |
7f36fbdf | 1469 | ira_free (map); |
1470 | } | |
1471 | ||
47dd2e78 | 1472 | /* Print live ranges R to file F. */ |
1473 | void | |
fbff82f4 | 1474 | ira_print_live_range_list (FILE *f, live_range_t r) |
47dd2e78 | 1475 | { |
1476 | for (; r != NULL; r = r->next) | |
1477 | fprintf (f, " [%d..%d]", r->start, r->finish); | |
1478 | fprintf (f, "\n"); | |
1479 | } | |
1480 | ||
c7d89805 | 1481 | DEBUG_FUNCTION void |
1482 | debug (live_range &ref) | |
1483 | { | |
1484 | ira_print_live_range_list (stderr, &ref); | |
1485 | } | |
1486 | ||
1487 | DEBUG_FUNCTION void | |
1488 | debug (live_range *ptr) | |
1489 | { | |
1490 | if (ptr) | |
1491 | debug (*ptr); | |
1492 | else | |
1493 | fprintf (stderr, "<nil>\n"); | |
1494 | } | |
1495 | ||
47dd2e78 | 1496 | /* Print live ranges R to stderr. */ |
1497 | void | |
fbff82f4 | 1498 | ira_debug_live_range_list (live_range_t r) |
47dd2e78 | 1499 | { |
1500 | ira_print_live_range_list (stderr, r); | |
1501 | } | |
1502 | ||
be18556f | 1503 | /* Print live ranges of object OBJ to file F. */ |
1504 | static void | |
1505 | print_object_live_ranges (FILE *f, ira_object_t obj) | |
1506 | { | |
1507 | ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); | |
1508 | } | |
1509 | ||
47dd2e78 | 1510 | /* Print live ranges of allocno A to file F. */ |
1511 | static void | |
1512 | print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
1513 | { | |
be18556f | 1514 | int n = ALLOCNO_NUM_OBJECTS (a); |
1515 | int i; | |
66d9a7b9 | 1516 | |
be18556f | 1517 | for (i = 0; i < n; i++) |
1518 | { | |
1519 | fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
1520 | if (n > 1) | |
1521 | fprintf (f, " [%d]", i); | |
1522 | fprintf (f, "):"); | |
1523 | print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); | |
1524 | } | |
47dd2e78 | 1525 | } |
1526 | ||
1527 | /* Print live ranges of allocno A to stderr. */ | |
1528 | void | |
1529 | ira_debug_allocno_live_ranges (ira_allocno_t a) | |
1530 | { | |
1531 | print_allocno_live_ranges (stderr, a); | |
1532 | } | |
1533 | ||
1534 | /* Print live ranges of all allocnos to file F. */ | |
1535 | static void | |
1536 | print_live_ranges (FILE *f) | |
1537 | { | |
1538 | ira_allocno_t a; | |
1539 | ira_allocno_iterator ai; | |
1540 | ||
1541 | FOR_EACH_ALLOCNO (a, ai) | |
1542 | print_allocno_live_ranges (f, a); | |
1543 | } | |
1544 | ||
1545 | /* Print live ranges of all allocnos to stderr. */ | |
1546 | void | |
1547 | ira_debug_live_ranges (void) | |
1548 | { | |
1549 | print_live_ranges (stderr); | |
1550 | } | |
1551 | ||
1552 | /* The main entry function creates live ranges, set up | |
be18556f | 1553 | CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
47dd2e78 | 1554 | calculate register pressure info. */ |
1555 | void | |
1556 | ira_create_allocno_live_ranges (void) | |
1557 | { | |
be18556f | 1558 | objects_live = sparseset_alloc (ira_objects_num); |
1559 | allocnos_processed = sparseset_alloc (ira_allocnos_num); | |
47dd2e78 | 1560 | curr_point = 0; |
df07a54c | 1561 | last_call_num = 0; |
1562 | allocno_saved_at_call | |
1563 | = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
1564 | memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
47dd2e78 | 1565 | ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, |
1566 | process_bb_node_lives); | |
1567 | ira_max_point = curr_point; | |
1568 | create_start_finish_chains (); | |
1569 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1570 | print_live_ranges (ira_dump_file); | |
1571 | /* Clean up. */ | |
df07a54c | 1572 | ira_free (allocno_saved_at_call); |
be18556f | 1573 | sparseset_free (objects_live); |
1574 | sparseset_free (allocnos_processed); | |
47dd2e78 | 1575 | } |
1576 | ||
7f36fbdf | 1577 | /* Compress allocno live ranges. */ |
1578 | void | |
1579 | ira_compress_allocno_live_ranges (void) | |
1580 | { | |
1581 | remove_some_program_points_and_update_live_ranges (); | |
1582 | ira_rebuild_start_finish_chains (); | |
1583 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
1584 | { | |
1585 | fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
1586 | print_live_ranges (ira_dump_file); | |
1587 | } | |
1588 | } | |
1589 | ||
47dd2e78 | 1590 | /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ |
1591 | void | |
1592 | ira_finish_allocno_live_ranges (void) | |
1593 | { | |
1594 | ira_free (ira_finish_point_ranges); | |
1595 | ira_free (ira_start_point_ranges); | |
1596 | } |