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058e97ec | 1 | /* Integrated Register Allocator (IRA) entry point. |
5624e564 | 2 | Copyright (C) 2006-2015 Free Software Foundation, Inc. |
058e97ec VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | /* The integrated register allocator (IRA) is a | |
22 | regional register allocator performing graph coloring on a top-down | |
23 | traversal of nested regions. Graph coloring in a region is based | |
24 | on Chaitin-Briggs algorithm. It is called integrated because | |
25 | register coalescing, register live range splitting, and choosing a | |
26 | better hard register are done on-the-fly during coloring. Register | |
27 | coalescing and choosing a cheaper hard register is done by hard | |
28 | register preferencing during hard register assigning. The live | |
29 | range splitting is a byproduct of the regional register allocation. | |
30 | ||
31 | Major IRA notions are: | |
32 | ||
33 | o *Region* is a part of CFG where graph coloring based on | |
34 | Chaitin-Briggs algorithm is done. IRA can work on any set of | |
35 | nested CFG regions forming a tree. Currently the regions are | |
36 | the entire function for the root region and natural loops for | |
37 | the other regions. Therefore data structure representing a | |
38 | region is called loop_tree_node. | |
39 | ||
1756cb66 VM |
40 | o *Allocno class* is a register class used for allocation of |
41 | given allocno. It means that only hard register of given | |
42 | register class can be assigned to given allocno. In reality, | |
43 | even smaller subset of (*profitable*) hard registers can be | |
44 | assigned. In rare cases, the subset can be even smaller | |
45 | because our modification of Chaitin-Briggs algorithm requires | |
46 | that sets of hard registers can be assigned to allocnos forms a | |
47 | forest, i.e. the sets can be ordered in a way where any | |
48 | previous set is not intersected with given set or is a superset | |
49 | of given set. | |
50 | ||
51 | o *Pressure class* is a register class belonging to a set of | |
52 | register classes containing all of the hard-registers available | |
53 | for register allocation. The set of all pressure classes for a | |
54 | target is defined in the corresponding machine-description file | |
55 | according some criteria. Register pressure is calculated only | |
56 | for pressure classes and it affects some IRA decisions as | |
57 | forming allocation regions. | |
058e97ec VM |
58 | |
59 | o *Allocno* represents the live range of a pseudo-register in a | |
60 | region. Besides the obvious attributes like the corresponding | |
1756cb66 | 61 | pseudo-register number, allocno class, conflicting allocnos and |
058e97ec VM |
62 | conflicting hard-registers, there are a few allocno attributes |
63 | which are important for understanding the allocation algorithm: | |
64 | ||
1756cb66 VM |
65 | - *Live ranges*. This is a list of ranges of *program points* |
66 | where the allocno lives. Program points represent places | |
67 | where a pseudo can be born or become dead (there are | |
058e97ec VM |
68 | approximately two times more program points than the insns) |
69 | and they are represented by integers starting with 0. The | |
1756cb66 VM |
70 | live ranges are used to find conflicts between allocnos. |
71 | They also play very important role for the transformation of | |
72 | the IRA internal representation of several regions into a one | |
73 | region representation. The later is used during the reload | |
74 | pass work because each allocno represents all of the | |
75 | corresponding pseudo-registers. | |
058e97ec VM |
76 | |
77 | - *Hard-register costs*. This is a vector of size equal to the | |
1756cb66 VM |
78 | number of available hard-registers of the allocno class. The |
79 | cost of a callee-clobbered hard-register for an allocno is | |
80 | increased by the cost of save/restore code around the calls | |
81 | through the given allocno's life. If the allocno is a move | |
82 | instruction operand and another operand is a hard-register of | |
83 | the allocno class, the cost of the hard-register is decreased | |
84 | by the move cost. | |
058e97ec VM |
85 | |
86 | When an allocno is assigned, the hard-register with minimal | |
87 | full cost is used. Initially, a hard-register's full cost is | |
88 | the corresponding value from the hard-register's cost vector. | |
89 | If the allocno is connected by a *copy* (see below) to | |
90 | another allocno which has just received a hard-register, the | |
91 | cost of the hard-register is decreased. Before choosing a | |
92 | hard-register for an allocno, the allocno's current costs of | |
93 | the hard-registers are modified by the conflict hard-register | |
94 | costs of all of the conflicting allocnos which are not | |
95 | assigned yet. | |
96 | ||
97 | - *Conflict hard-register costs*. This is a vector of the same | |
98 | size as the hard-register costs vector. To permit an | |
99 | unassigned allocno to get a better hard-register, IRA uses | |
100 | this vector to calculate the final full cost of the | |
101 | available hard-registers. Conflict hard-register costs of an | |
102 | unassigned allocno are also changed with a change of the | |
103 | hard-register cost of the allocno when a copy involving the | |
104 | allocno is processed as described above. This is done to | |
105 | show other unassigned allocnos that a given allocno prefers | |
106 | some hard-registers in order to remove the move instruction | |
107 | corresponding to the copy. | |
108 | ||
109 | o *Cap*. If a pseudo-register does not live in a region but | |
110 | lives in a nested region, IRA creates a special allocno called | |
111 | a cap in the outer region. A region cap is also created for a | |
112 | subregion cap. | |
113 | ||
114 | o *Copy*. Allocnos can be connected by copies. Copies are used | |
115 | to modify hard-register costs for allocnos during coloring. | |
116 | Such modifications reflects a preference to use the same | |
117 | hard-register for the allocnos connected by copies. Usually | |
118 | copies are created for move insns (in this case it results in | |
119 | register coalescing). But IRA also creates copies for operands | |
120 | of an insn which should be assigned to the same hard-register | |
121 | due to constraints in the machine description (it usually | |
122 | results in removing a move generated in reload to satisfy | |
123 | the constraints) and copies referring to the allocno which is | |
124 | the output operand of an instruction and the allocno which is | |
125 | an input operand dying in the instruction (creation of such | |
126 | copies results in less register shuffling). IRA *does not* | |
127 | create copies between the same register allocnos from different | |
128 | regions because we use another technique for propagating | |
129 | hard-register preference on the borders of regions. | |
130 | ||
131 | Allocnos (including caps) for the upper region in the region tree | |
132 | *accumulate* information important for coloring from allocnos with | |
133 | the same pseudo-register from nested regions. This includes | |
134 | hard-register and memory costs, conflicts with hard-registers, | |
135 | allocno conflicts, allocno copies and more. *Thus, attributes for | |
136 | allocnos in a region have the same values as if the region had no | |
137 | subregions*. It means that attributes for allocnos in the | |
138 | outermost region corresponding to the function have the same values | |
139 | as though the allocation used only one region which is the entire | |
140 | function. It also means that we can look at IRA work as if the | |
141 | first IRA did allocation for all function then it improved the | |
142 | allocation for loops then their subloops and so on. | |
143 | ||
144 | IRA major passes are: | |
145 | ||
146 | o Building IRA internal representation which consists of the | |
147 | following subpasses: | |
148 | ||
149 | * First, IRA builds regions and creates allocnos (file | |
150 | ira-build.c) and initializes most of their attributes. | |
151 | ||
1756cb66 VM |
152 | * Then IRA finds an allocno class for each allocno and |
153 | calculates its initial (non-accumulated) cost of memory and | |
154 | each hard-register of its allocno class (file ira-cost.c). | |
058e97ec | 155 | |
df3e3493 | 156 | * IRA creates live ranges of each allocno, calculates register |
1756cb66 | 157 | pressure for each pressure class in each region, sets up |
058e97ec VM |
158 | conflict hard registers for each allocno and info about calls |
159 | the allocno lives through (file ira-lives.c). | |
160 | ||
161 | * IRA removes low register pressure loops from the regions | |
162 | mostly to speed IRA up (file ira-build.c). | |
163 | ||
164 | * IRA propagates accumulated allocno info from lower region | |
165 | allocnos to corresponding upper region allocnos (file | |
166 | ira-build.c). | |
167 | ||
168 | * IRA creates all caps (file ira-build.c). | |
169 | ||
1756cb66 VM |
170 | * Having live-ranges of allocnos and their classes, IRA creates |
171 | conflicting allocnos for each allocno. Conflicting allocnos | |
172 | are stored as a bit vector or array of pointers to the | |
173 | conflicting allocnos whatever is more profitable (file | |
174 | ira-conflicts.c). At this point IRA creates allocno copies. | |
058e97ec VM |
175 | |
176 | o Coloring. Now IRA has all necessary info to start graph coloring | |
177 | process. It is done in each region on top-down traverse of the | |
178 | region tree (file ira-color.c). There are following subpasses: | |
b8698a0f | 179 | |
1756cb66 VM |
180 | * Finding profitable hard registers of corresponding allocno |
181 | class for each allocno. For example, only callee-saved hard | |
182 | registers are frequently profitable for allocnos living | |
183 | through colors. If the profitable hard register set of | |
184 | allocno does not form a tree based on subset relation, we use | |
185 | some approximation to form the tree. This approximation is | |
186 | used to figure out trivial colorability of allocnos. The | |
187 | approximation is a pretty rare case. | |
188 | ||
058e97ec VM |
189 | * Putting allocnos onto the coloring stack. IRA uses Briggs |
190 | optimistic coloring which is a major improvement over | |
191 | Chaitin's coloring. Therefore IRA does not spill allocnos at | |
192 | this point. There is some freedom in the order of putting | |
193 | allocnos on the stack which can affect the final result of | |
1756cb66 | 194 | the allocation. IRA uses some heuristics to improve the |
41808d15 VM |
195 | order. The major one is to form *threads* from colorable |
196 | allocnos and push them on the stack by threads. Thread is a | |
197 | set of non-conflicting colorable allocnos connected by | |
198 | copies. The thread contains allocnos from the colorable | |
199 | bucket or colorable allocnos already pushed onto the coloring | |
200 | stack. Pushing thread allocnos one after another onto the | |
201 | stack increases chances of removing copies when the allocnos | |
202 | get the same hard reg. | |
1756cb66 VM |
203 | |
204 | We also use a modification of Chaitin-Briggs algorithm which | |
205 | works for intersected register classes of allocnos. To | |
206 | figure out trivial colorability of allocnos, the mentioned | |
207 | above tree of hard register sets is used. To get an idea how | |
208 | the algorithm works in i386 example, let us consider an | |
209 | allocno to which any general hard register can be assigned. | |
210 | If the allocno conflicts with eight allocnos to which only | |
211 | EAX register can be assigned, given allocno is still | |
212 | trivially colorable because all conflicting allocnos might be | |
213 | assigned only to EAX and all other general hard registers are | |
214 | still free. | |
215 | ||
216 | To get an idea of the used trivial colorability criterion, it | |
217 | is also useful to read article "Graph-Coloring Register | |
218 | Allocation for Irregular Architectures" by Michael D. Smith | |
219 | and Glen Holloway. Major difference between the article | |
220 | approach and approach used in IRA is that Smith's approach | |
221 | takes register classes only from machine description and IRA | |
222 | calculate register classes from intermediate code too | |
223 | (e.g. an explicit usage of hard registers in RTL code for | |
224 | parameter passing can result in creation of additional | |
225 | register classes which contain or exclude the hard | |
226 | registers). That makes IRA approach useful for improving | |
227 | coloring even for architectures with regular register files | |
228 | and in fact some benchmarking shows the improvement for | |
229 | regular class architectures is even bigger than for irregular | |
230 | ones. Another difference is that Smith's approach chooses | |
231 | intersection of classes of all insn operands in which a given | |
232 | pseudo occurs. IRA can use bigger classes if it is still | |
233 | more profitable than memory usage. | |
058e97ec VM |
234 | |
235 | * Popping the allocnos from the stack and assigning them hard | |
236 | registers. If IRA can not assign a hard register to an | |
237 | allocno and the allocno is coalesced, IRA undoes the | |
238 | coalescing and puts the uncoalesced allocnos onto the stack in | |
239 | the hope that some such allocnos will get a hard register | |
240 | separately. If IRA fails to assign hard register or memory | |
241 | is more profitable for it, IRA spills the allocno. IRA | |
242 | assigns the allocno the hard-register with minimal full | |
243 | allocation cost which reflects the cost of usage of the | |
244 | hard-register for the allocno and cost of usage of the | |
245 | hard-register for allocnos conflicting with given allocno. | |
246 | ||
1756cb66 | 247 | * Chaitin-Briggs coloring assigns as many pseudos as possible |
df3e3493 | 248 | to hard registers. After coloring we try to improve |
1756cb66 VM |
249 | allocation with cost point of view. We improve the |
250 | allocation by spilling some allocnos and assigning the freed | |
251 | hard registers to other allocnos if it decreases the overall | |
252 | allocation cost. | |
253 | ||
3447fefe | 254 | * After allocno assigning in the region, IRA modifies the hard |
058e97ec VM |
255 | register and memory costs for the corresponding allocnos in |
256 | the subregions to reflect the cost of possible loads, stores, | |
257 | or moves on the border of the region and its subregions. | |
258 | When default regional allocation algorithm is used | |
259 | (-fira-algorithm=mixed), IRA just propagates the assignment | |
260 | for allocnos if the register pressure in the region for the | |
1756cb66 VM |
261 | corresponding pressure class is less than number of available |
262 | hard registers for given pressure class. | |
058e97ec VM |
263 | |
264 | o Spill/restore code moving. When IRA performs an allocation | |
265 | by traversing regions in top-down order, it does not know what | |
266 | happens below in the region tree. Therefore, sometimes IRA | |
267 | misses opportunities to perform a better allocation. A simple | |
268 | optimization tries to improve allocation in a region having | |
269 | subregions and containing in another region. If the | |
270 | corresponding allocnos in the subregion are spilled, it spills | |
271 | the region allocno if it is profitable. The optimization | |
272 | implements a simple iterative algorithm performing profitable | |
273 | transformations while they are still possible. It is fast in | |
274 | practice, so there is no real need for a better time complexity | |
275 | algorithm. | |
276 | ||
1756cb66 VM |
277 | o Code change. After coloring, two allocnos representing the |
278 | same pseudo-register outside and inside a region respectively | |
279 | may be assigned to different locations (hard-registers or | |
280 | memory). In this case IRA creates and uses a new | |
281 | pseudo-register inside the region and adds code to move allocno | |
282 | values on the region's borders. This is done during top-down | |
283 | traversal of the regions (file ira-emit.c). In some | |
284 | complicated cases IRA can create a new allocno to move allocno | |
285 | values (e.g. when a swap of values stored in two hard-registers | |
286 | is needed). At this stage, the new allocno is marked as | |
287 | spilled. IRA still creates the pseudo-register and the moves | |
288 | on the region borders even when both allocnos were assigned to | |
289 | the same hard-register. If the reload pass spills a | |
290 | pseudo-register for some reason, the effect will be smaller | |
291 | because another allocno will still be in the hard-register. In | |
292 | most cases, this is better then spilling both allocnos. If | |
293 | reload does not change the allocation for the two | |
294 | pseudo-registers, the trivial move will be removed by | |
295 | post-reload optimizations. IRA does not generate moves for | |
058e97ec VM |
296 | allocnos assigned to the same hard register when the default |
297 | regional allocation algorithm is used and the register pressure | |
1756cb66 VM |
298 | in the region for the corresponding pressure class is less than |
299 | number of available hard registers for given pressure class. | |
058e97ec VM |
300 | IRA also does some optimizations to remove redundant stores and |
301 | to reduce code duplication on the region borders. | |
302 | ||
303 | o Flattening internal representation. After changing code, IRA | |
304 | transforms its internal representation for several regions into | |
305 | one region representation (file ira-build.c). This process is | |
306 | called IR flattening. Such process is more complicated than IR | |
307 | rebuilding would be, but is much faster. | |
308 | ||
309 | o After IR flattening, IRA tries to assign hard registers to all | |
df3e3493 | 310 | spilled allocnos. This is implemented by a simple and fast |
058e97ec VM |
311 | priority coloring algorithm (see function |
312 | ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos | |
313 | created during the code change pass can be assigned to hard | |
314 | registers. | |
315 | ||
316 | o At the end IRA calls the reload pass. The reload pass | |
317 | communicates with IRA through several functions in file | |
318 | ira-color.c to improve its decisions in | |
319 | ||
320 | * sharing stack slots for the spilled pseudos based on IRA info | |
321 | about pseudo-register conflicts. | |
322 | ||
323 | * reassigning hard-registers to all spilled pseudos at the end | |
324 | of each reload iteration. | |
325 | ||
326 | * choosing a better hard-register to spill based on IRA info | |
327 | about pseudo-register live ranges and the register pressure | |
328 | in places where the pseudo-register lives. | |
329 | ||
330 | IRA uses a lot of data representing the target processors. These | |
df3e3493 | 331 | data are initialized in file ira.c. |
058e97ec VM |
332 | |
333 | If function has no loops (or the loops are ignored when | |
334 | -fira-algorithm=CB is used), we have classic Chaitin-Briggs | |
335 | coloring (only instead of separate pass of coalescing, we use hard | |
336 | register preferencing). In such case, IRA works much faster | |
337 | because many things are not made (like IR flattening, the | |
338 | spill/restore optimization, and the code change). | |
339 | ||
340 | Literature is worth to read for better understanding the code: | |
341 | ||
342 | o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to | |
343 | Graph Coloring Register Allocation. | |
344 | ||
345 | o David Callahan, Brian Koblenz. Register allocation via | |
346 | hierarchical graph coloring. | |
347 | ||
348 | o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph | |
349 | Coloring Register Allocation: A Study of the Chaitin-Briggs and | |
350 | Callahan-Koblenz Algorithms. | |
351 | ||
352 | o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global | |
353 | Register Allocation Based on Graph Fusion. | |
354 | ||
1756cb66 VM |
355 | o Michael D. Smith and Glenn Holloway. Graph-Coloring Register |
356 | Allocation for Irregular Architectures | |
357 | ||
058e97ec VM |
358 | o Vladimir Makarov. The Integrated Register Allocator for GCC. |
359 | ||
360 | o Vladimir Makarov. The top-down register allocator for irregular | |
361 | register file architectures. | |
362 | ||
363 | */ | |
364 | ||
365 | ||
366 | #include "config.h" | |
367 | #include "system.h" | |
368 | #include "coretypes.h" | |
369 | #include "tm.h" | |
370 | #include "regs.h" | |
40e23961 MC |
371 | #include "hash-set.h" |
372 | #include "machmode.h" | |
373 | #include "vec.h" | |
374 | #include "double-int.h" | |
375 | #include "input.h" | |
376 | #include "alias.h" | |
377 | #include "symtab.h" | |
378 | #include "wide-int.h" | |
379 | #include "inchash.h" | |
4d648807 | 380 | #include "tree.h" |
058e97ec VM |
381 | #include "rtl.h" |
382 | #include "tm_p.h" | |
383 | #include "target.h" | |
384 | #include "flags.h" | |
385 | #include "obstack.h" | |
386 | #include "bitmap.h" | |
387 | #include "hard-reg-set.h" | |
60393bbc | 388 | #include "predict.h" |
60393bbc AM |
389 | #include "function.h" |
390 | #include "dominance.h" | |
391 | #include "cfg.h" | |
392 | #include "cfgrtl.h" | |
393 | #include "cfgbuild.h" | |
394 | #include "cfgcleanup.h" | |
058e97ec | 395 | #include "basic-block.h" |
7a8cba34 | 396 | #include "df.h" |
36566b39 PK |
397 | #include "hashtab.h" |
398 | #include "statistics.h" | |
399 | #include "real.h" | |
400 | #include "fixed-value.h" | |
401 | #include "insn-config.h" | |
402 | #include "expmed.h" | |
403 | #include "dojump.h" | |
404 | #include "explow.h" | |
405 | #include "calls.h" | |
406 | #include "emit-rtl.h" | |
407 | #include "varasm.h" | |
408 | #include "stmt.h" | |
058e97ec VM |
409 | #include "expr.h" |
410 | #include "recog.h" | |
411 | #include "params.h" | |
058e97ec VM |
412 | #include "tree-pass.h" |
413 | #include "output.h" | |
2af2dbdc | 414 | #include "except.h" |
058e97ec | 415 | #include "reload.h" |
718f9c0f | 416 | #include "diagnostic-core.h" |
058e97ec VM |
417 | #include "ggc.h" |
418 | #include "ira-int.h" | |
55a2c322 | 419 | #include "lra.h" |
b0c11403 | 420 | #include "dce.h" |
acf41a74 | 421 | #include "dbgcnt.h" |
40954ce5 | 422 | #include "rtl-iter.h" |
a5e022d5 | 423 | #include "shrink-wrap.h" |
058e97ec | 424 | |
afcc66c4 RS |
425 | struct target_ira default_target_ira; |
426 | struct target_ira_int default_target_ira_int; | |
427 | #if SWITCHABLE_TARGET | |
428 | struct target_ira *this_target_ira = &default_target_ira; | |
429 | struct target_ira_int *this_target_ira_int = &default_target_ira_int; | |
430 | #endif | |
431 | ||
058e97ec VM |
432 | /* A modified value of flag `-fira-verbose' used internally. */ |
433 | int internal_flag_ira_verbose; | |
434 | ||
435 | /* Dump file of the allocator if it is not NULL. */ | |
436 | FILE *ira_dump_file; | |
437 | ||
058e97ec VM |
438 | /* The number of elements in the following array. */ |
439 | int ira_spilled_reg_stack_slots_num; | |
440 | ||
441 | /* The following array contains info about spilled pseudo-registers | |
442 | stack slots used in current function so far. */ | |
443 | struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; | |
444 | ||
ae2b9cb6 BS |
445 | /* Correspondingly overall cost of the allocation, overall cost before |
446 | reload, cost of the allocnos assigned to hard-registers, cost of | |
447 | the allocnos assigned to memory, cost of loads, stores and register | |
448 | move insns generated for pseudo-register live range splitting (see | |
449 | ira-emit.c). */ | |
2bf7560b VM |
450 | int64_t ira_overall_cost, overall_cost_before; |
451 | int64_t ira_reg_cost, ira_mem_cost; | |
452 | int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; | |
058e97ec VM |
453 | int ira_move_loops_num, ira_additional_jumps_num; |
454 | ||
2af2dbdc VM |
455 | /* All registers that can be eliminated. */ |
456 | ||
457 | HARD_REG_SET eliminable_regset; | |
458 | ||
70cc3288 VM |
459 | /* Value of max_reg_num () before IRA work start. This value helps |
460 | us to recognize a situation when new pseudos were created during | |
461 | IRA work. */ | |
462 | static int max_regno_before_ira; | |
463 | ||
058e97ec VM |
464 | /* Temporary hard reg set used for a different calculation. */ |
465 | static HARD_REG_SET temp_hard_regset; | |
466 | ||
e80ccebc RS |
467 | #define last_mode_for_init_move_cost \ |
468 | (this_target_ira_int->x_last_mode_for_init_move_cost) | |
058e97ec VM |
469 | \f |
470 | ||
471 | /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ | |
472 | static void | |
473 | setup_reg_mode_hard_regset (void) | |
474 | { | |
475 | int i, m, hard_regno; | |
476 | ||
477 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
478 | for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) | |
479 | { | |
480 | CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); | |
481 | for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) | |
482 | if (hard_regno + i < FIRST_PSEUDO_REGISTER) | |
483 | SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], | |
484 | hard_regno + i); | |
485 | } | |
486 | } | |
487 | ||
488 | \f | |
afcc66c4 RS |
489 | #define no_unit_alloc_regs \ |
490 | (this_target_ira_int->x_no_unit_alloc_regs) | |
058e97ec VM |
491 | |
492 | /* The function sets up the three arrays declared above. */ | |
493 | static void | |
494 | setup_class_hard_regs (void) | |
495 | { | |
496 | int cl, i, hard_regno, n; | |
497 | HARD_REG_SET processed_hard_reg_set; | |
498 | ||
499 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | |
058e97ec VM |
500 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
501 | { | |
502 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
503 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
504 | CLEAR_HARD_REG_SET (processed_hard_reg_set); | |
7db7ed3c | 505 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
0583835c | 506 | { |
854edfcd VM |
507 | ira_non_ordered_class_hard_regs[cl][i] = -1; |
508 | ira_class_hard_reg_index[cl][i] = -1; | |
0583835c | 509 | } |
058e97ec VM |
510 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
511 | { | |
512 | #ifdef REG_ALLOC_ORDER | |
513 | hard_regno = reg_alloc_order[i]; | |
514 | #else | |
515 | hard_regno = i; | |
b8698a0f | 516 | #endif |
058e97ec VM |
517 | if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) |
518 | continue; | |
519 | SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); | |
520 | if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) | |
521 | ira_class_hard_reg_index[cl][hard_regno] = -1; | |
522 | else | |
523 | { | |
524 | ira_class_hard_reg_index[cl][hard_regno] = n; | |
525 | ira_class_hard_regs[cl][n++] = hard_regno; | |
526 | } | |
527 | } | |
528 | ira_class_hard_regs_num[cl] = n; | |
0583835c VM |
529 | for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
530 | if (TEST_HARD_REG_BIT (temp_hard_regset, i)) | |
531 | ira_non_ordered_class_hard_regs[cl][n++] = i; | |
532 | ira_assert (ira_class_hard_regs_num[cl] == n); | |
058e97ec VM |
533 | } |
534 | } | |
535 | ||
058e97ec VM |
536 | /* Set up global variables defining info about hard registers for the |
537 | allocation. These depend on USE_HARD_FRAME_P whose TRUE value means | |
538 | that we can use the hard frame pointer for the allocation. */ | |
539 | static void | |
540 | setup_alloc_regs (bool use_hard_frame_p) | |
541 | { | |
5a733826 BS |
542 | #ifdef ADJUST_REG_ALLOC_ORDER |
543 | ADJUST_REG_ALLOC_ORDER; | |
544 | #endif | |
058e97ec VM |
545 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); |
546 | if (! use_hard_frame_p) | |
547 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | |
548 | setup_class_hard_regs (); | |
058e97ec VM |
549 | } |
550 | ||
551 | \f | |
552 | ||
1756cb66 VM |
553 | #define alloc_reg_class_subclasses \ |
554 | (this_target_ira_int->x_alloc_reg_class_subclasses) | |
555 | ||
556 | /* Initialize the table of subclasses of each reg class. */ | |
557 | static void | |
558 | setup_reg_subclasses (void) | |
559 | { | |
560 | int i, j; | |
561 | HARD_REG_SET temp_hard_regset2; | |
562 | ||
563 | for (i = 0; i < N_REG_CLASSES; i++) | |
564 | for (j = 0; j < N_REG_CLASSES; j++) | |
565 | alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
566 | ||
567 | for (i = 0; i < N_REG_CLASSES; i++) | |
568 | { | |
569 | if (i == (int) NO_REGS) | |
570 | continue; | |
571 | ||
572 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); | |
573 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
574 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
575 | continue; | |
576 | for (j = 0; j < N_REG_CLASSES; j++) | |
577 | if (i != j) | |
578 | { | |
579 | enum reg_class *p; | |
580 | ||
581 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); | |
582 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
583 | if (! hard_reg_set_subset_p (temp_hard_regset, | |
584 | temp_hard_regset2)) | |
585 | continue; | |
586 | p = &alloc_reg_class_subclasses[j][0]; | |
587 | while (*p != LIM_REG_CLASSES) p++; | |
588 | *p = (enum reg_class) i; | |
589 | } | |
590 | } | |
591 | } | |
592 | ||
593 | \f | |
594 | ||
595 | /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ | |
058e97ec VM |
596 | static void |
597 | setup_class_subset_and_memory_move_costs (void) | |
598 | { | |
1756cb66 | 599 | int cl, cl2, mode, cost; |
058e97ec VM |
600 | HARD_REG_SET temp_hard_regset2; |
601 | ||
602 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
603 | ira_memory_move_cost[mode][NO_REGS][0] | |
604 | = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; | |
605 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
606 | { | |
607 | if (cl != (int) NO_REGS) | |
608 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
609 | { | |
1756cb66 VM |
610 | ira_max_memory_move_cost[mode][cl][0] |
611 | = ira_memory_move_cost[mode][cl][0] | |
ef4bddc2 | 612 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 613 | (reg_class_t) cl, false); |
1756cb66 VM |
614 | ira_max_memory_move_cost[mode][cl][1] |
615 | = ira_memory_move_cost[mode][cl][1] | |
ef4bddc2 | 616 | = memory_move_cost ((machine_mode) mode, |
6f76a878 | 617 | (reg_class_t) cl, true); |
058e97ec VM |
618 | /* Costs for NO_REGS are used in cost calculation on the |
619 | 1st pass when the preferred register classes are not | |
620 | known yet. In this case we take the best scenario. */ | |
621 | if (ira_memory_move_cost[mode][NO_REGS][0] | |
622 | > ira_memory_move_cost[mode][cl][0]) | |
1756cb66 VM |
623 | ira_max_memory_move_cost[mode][NO_REGS][0] |
624 | = ira_memory_move_cost[mode][NO_REGS][0] | |
058e97ec VM |
625 | = ira_memory_move_cost[mode][cl][0]; |
626 | if (ira_memory_move_cost[mode][NO_REGS][1] | |
627 | > ira_memory_move_cost[mode][cl][1]) | |
1756cb66 VM |
628 | ira_max_memory_move_cost[mode][NO_REGS][1] |
629 | = ira_memory_move_cost[mode][NO_REGS][1] | |
058e97ec VM |
630 | = ira_memory_move_cost[mode][cl][1]; |
631 | } | |
058e97ec | 632 | } |
1756cb66 VM |
633 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
634 | for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) | |
635 | { | |
636 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
637 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
638 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
639 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
640 | ira_class_subset_p[cl][cl2] | |
641 | = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); | |
642 | if (! hard_reg_set_empty_p (temp_hard_regset2) | |
643 | && hard_reg_set_subset_p (reg_class_contents[cl2], | |
644 | reg_class_contents[cl])) | |
645 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
646 | { | |
647 | cost = ira_memory_move_cost[mode][cl2][0]; | |
648 | if (cost > ira_max_memory_move_cost[mode][cl][0]) | |
649 | ira_max_memory_move_cost[mode][cl][0] = cost; | |
650 | cost = ira_memory_move_cost[mode][cl2][1]; | |
651 | if (cost > ira_max_memory_move_cost[mode][cl][1]) | |
652 | ira_max_memory_move_cost[mode][cl][1] = cost; | |
653 | } | |
654 | } | |
655 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
656 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
657 | { | |
658 | ira_memory_move_cost[mode][cl][0] | |
659 | = ira_max_memory_move_cost[mode][cl][0]; | |
660 | ira_memory_move_cost[mode][cl][1] | |
661 | = ira_max_memory_move_cost[mode][cl][1]; | |
662 | } | |
663 | setup_reg_subclasses (); | |
058e97ec VM |
664 | } |
665 | ||
666 | \f | |
667 | ||
668 | /* Define the following macro if allocation through malloc if | |
669 | preferable. */ | |
670 | #define IRA_NO_OBSTACK | |
671 | ||
672 | #ifndef IRA_NO_OBSTACK | |
673 | /* Obstack used for storing all dynamic data (except bitmaps) of the | |
674 | IRA. */ | |
675 | static struct obstack ira_obstack; | |
676 | #endif | |
677 | ||
678 | /* Obstack used for storing all bitmaps of the IRA. */ | |
679 | static struct bitmap_obstack ira_bitmap_obstack; | |
680 | ||
681 | /* Allocate memory of size LEN for IRA data. */ | |
682 | void * | |
683 | ira_allocate (size_t len) | |
684 | { | |
685 | void *res; | |
686 | ||
687 | #ifndef IRA_NO_OBSTACK | |
688 | res = obstack_alloc (&ira_obstack, len); | |
689 | #else | |
690 | res = xmalloc (len); | |
691 | #endif | |
692 | return res; | |
693 | } | |
694 | ||
058e97ec VM |
695 | /* Free memory ADDR allocated for IRA data. */ |
696 | void | |
697 | ira_free (void *addr ATTRIBUTE_UNUSED) | |
698 | { | |
699 | #ifndef IRA_NO_OBSTACK | |
700 | /* do nothing */ | |
701 | #else | |
702 | free (addr); | |
703 | #endif | |
704 | } | |
705 | ||
706 | ||
707 | /* Allocate and returns bitmap for IRA. */ | |
708 | bitmap | |
709 | ira_allocate_bitmap (void) | |
710 | { | |
711 | return BITMAP_ALLOC (&ira_bitmap_obstack); | |
712 | } | |
713 | ||
714 | /* Free bitmap B allocated for IRA. */ | |
715 | void | |
716 | ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) | |
717 | { | |
718 | /* do nothing */ | |
719 | } | |
720 | ||
721 | \f | |
722 | ||
723 | /* Output information about allocation of all allocnos (except for | |
724 | caps) into file F. */ | |
725 | void | |
726 | ira_print_disposition (FILE *f) | |
727 | { | |
728 | int i, n, max_regno; | |
729 | ira_allocno_t a; | |
730 | basic_block bb; | |
731 | ||
732 | fprintf (f, "Disposition:"); | |
733 | max_regno = max_reg_num (); | |
734 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
735 | for (a = ira_regno_allocno_map[i]; | |
736 | a != NULL; | |
737 | a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
738 | { | |
739 | if (n % 4 == 0) | |
740 | fprintf (f, "\n"); | |
741 | n++; | |
742 | fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); | |
743 | if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
744 | fprintf (f, "b%-3d", bb->index); | |
745 | else | |
2608d841 | 746 | fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); |
058e97ec VM |
747 | if (ALLOCNO_HARD_REGNO (a) >= 0) |
748 | fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); | |
749 | else | |
750 | fprintf (f, " mem"); | |
751 | } | |
752 | fprintf (f, "\n"); | |
753 | } | |
754 | ||
755 | /* Outputs information about allocation of all allocnos into | |
756 | stderr. */ | |
757 | void | |
758 | ira_debug_disposition (void) | |
759 | { | |
760 | ira_print_disposition (stderr); | |
761 | } | |
762 | ||
763 | \f | |
058e97ec | 764 | |
1756cb66 VM |
765 | /* Set up ira_stack_reg_pressure_class which is the biggest pressure |
766 | register class containing stack registers or NO_REGS if there are | |
767 | no stack registers. To find this class, we iterate through all | |
768 | register pressure classes and choose the first register pressure | |
769 | class containing all the stack registers and having the biggest | |
770 | size. */ | |
fe82cdfb | 771 | static void |
1756cb66 VM |
772 | setup_stack_reg_pressure_class (void) |
773 | { | |
774 | ira_stack_reg_pressure_class = NO_REGS; | |
775 | #ifdef STACK_REGS | |
776 | { | |
777 | int i, best, size; | |
778 | enum reg_class cl; | |
779 | HARD_REG_SET temp_hard_regset2; | |
780 | ||
781 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
782 | for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) | |
783 | SET_HARD_REG_BIT (temp_hard_regset, i); | |
784 | best = 0; | |
785 | for (i = 0; i < ira_pressure_classes_num; i++) | |
786 | { | |
787 | cl = ira_pressure_classes[i]; | |
788 | COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); | |
789 | AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
790 | size = hard_reg_set_size (temp_hard_regset2); | |
791 | if (best < size) | |
792 | { | |
793 | best = size; | |
794 | ira_stack_reg_pressure_class = cl; | |
795 | } | |
796 | } | |
797 | } | |
798 | #endif | |
799 | } | |
800 | ||
801 | /* Find pressure classes which are register classes for which we | |
802 | calculate register pressure in IRA, register pressure sensitive | |
803 | insn scheduling, and register pressure sensitive loop invariant | |
804 | motion. | |
805 | ||
806 | To make register pressure calculation easy, we always use | |
807 | non-intersected register pressure classes. A move of hard | |
808 | registers from one register pressure class is not more expensive | |
809 | than load and store of the hard registers. Most likely an allocno | |
810 | class will be a subset of a register pressure class and in many | |
811 | cases a register pressure class. That makes usage of register | |
812 | pressure classes a good approximation to find a high register | |
813 | pressure. */ | |
814 | static void | |
815 | setup_pressure_classes (void) | |
058e97ec | 816 | { |
1756cb66 VM |
817 | int cost, i, n, curr; |
818 | int cl, cl2; | |
819 | enum reg_class pressure_classes[N_REG_CLASSES]; | |
820 | int m; | |
058e97ec | 821 | HARD_REG_SET temp_hard_regset2; |
1756cb66 | 822 | bool insert_p; |
058e97ec | 823 | |
1756cb66 VM |
824 | n = 0; |
825 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
058e97ec | 826 | { |
f508f827 | 827 | if (ira_class_hard_regs_num[cl] == 0) |
058e97ec | 828 | continue; |
f508f827 | 829 | if (ira_class_hard_regs_num[cl] != 1 |
574e418a VM |
830 | /* A register class without subclasses may contain a few |
831 | hard registers and movement between them is costly | |
832 | (e.g. SPARC FPCC registers). We still should consider it | |
833 | as a candidate for a pressure class. */ | |
af2b97c4 | 834 | && alloc_reg_class_subclasses[cl][0] < cl) |
1756cb66 | 835 | { |
113a5be6 VM |
836 | /* Check that the moves between any hard registers of the |
837 | current class are not more expensive for a legal mode | |
838 | than load/store of the hard registers of the current | |
839 | class. Such class is a potential candidate to be a | |
840 | register pressure class. */ | |
841 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
842 | { | |
843 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
844 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
845 | AND_COMPL_HARD_REG_SET (temp_hard_regset, | |
846 | ira_prohibited_class_mode_regs[cl][m]); | |
847 | if (hard_reg_set_empty_p (temp_hard_regset)) | |
848 | continue; | |
ef4bddc2 | 849 | ira_init_register_move_cost_if_necessary ((machine_mode) m); |
113a5be6 VM |
850 | cost = ira_register_move_cost[m][cl][cl]; |
851 | if (cost <= ira_max_memory_move_cost[m][cl][1] | |
852 | || cost <= ira_max_memory_move_cost[m][cl][0]) | |
853 | break; | |
854 | } | |
855 | if (m >= NUM_MACHINE_MODES) | |
1756cb66 | 856 | continue; |
1756cb66 | 857 | } |
1756cb66 VM |
858 | curr = 0; |
859 | insert_p = true; | |
860 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
861 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
862 | /* Remove so far added pressure classes which are subset of the | |
863 | current candidate class. Prefer GENERAL_REGS as a pressure | |
864 | register class to another class containing the same | |
865 | allocatable hard registers. We do this because machine | |
866 | dependent cost hooks might give wrong costs for the latter | |
867 | class but always give the right cost for the former class | |
868 | (GENERAL_REGS). */ | |
869 | for (i = 0; i < n; i++) | |
870 | { | |
871 | cl2 = pressure_classes[i]; | |
872 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); | |
873 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
874 | if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) | |
875 | && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2) | |
876 | || cl2 == (int) GENERAL_REGS)) | |
877 | { | |
878 | pressure_classes[curr++] = (enum reg_class) cl2; | |
879 | insert_p = false; | |
058e97ec | 880 | continue; |
1756cb66 VM |
881 | } |
882 | if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) | |
883 | && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) | |
884 | || cl == (int) GENERAL_REGS)) | |
885 | continue; | |
113a5be6 VM |
886 | if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) |
887 | insert_p = false; | |
1756cb66 VM |
888 | pressure_classes[curr++] = (enum reg_class) cl2; |
889 | } | |
890 | /* If the current candidate is a subset of a so far added | |
891 | pressure class, don't add it to the list of the pressure | |
892 | classes. */ | |
893 | if (insert_p) | |
894 | pressure_classes[curr++] = (enum reg_class) cl; | |
895 | n = curr; | |
fe82cdfb | 896 | } |
1756cb66 | 897 | #ifdef ENABLE_IRA_CHECKING |
113a5be6 VM |
898 | { |
899 | HARD_REG_SET ignore_hard_regs; | |
900 | ||
901 | /* Check pressure classes correctness: here we check that hard | |
902 | registers from all register pressure classes contains all hard | |
903 | registers available for the allocation. */ | |
904 | CLEAR_HARD_REG_SET (temp_hard_regset); | |
905 | CLEAR_HARD_REG_SET (temp_hard_regset2); | |
906 | COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); | |
907 | for (cl = 0; cl < LIM_REG_CLASSES; cl++) | |
908 | { | |
909 | /* For some targets (like MIPS with MD_REGS), there are some | |
910 | classes with hard registers available for allocation but | |
911 | not able to hold value of any mode. */ | |
912 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
913 | if (contains_reg_of_mode[cl][m]) | |
914 | break; | |
915 | if (m >= NUM_MACHINE_MODES) | |
916 | { | |
917 | IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); | |
918 | continue; | |
919 | } | |
920 | for (i = 0; i < n; i++) | |
921 | if ((int) pressure_classes[i] == cl) | |
922 | break; | |
923 | IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
924 | if (i < n) | |
925 | IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
926 | } | |
927 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
df3e3493 | 928 | /* Some targets (like SPARC with ICC reg) have allocatable regs |
113a5be6 VM |
929 | for which no reg class is defined. */ |
930 | if (REGNO_REG_CLASS (i) == NO_REGS) | |
931 | SET_HARD_REG_BIT (ignore_hard_regs, i); | |
932 | AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); | |
933 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); | |
934 | ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); | |
935 | } | |
1756cb66 VM |
936 | #endif |
937 | ira_pressure_classes_num = 0; | |
938 | for (i = 0; i < n; i++) | |
939 | { | |
940 | cl = (int) pressure_classes[i]; | |
941 | ira_reg_pressure_class_p[cl] = true; | |
942 | ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; | |
943 | } | |
944 | setup_stack_reg_pressure_class (); | |
058e97ec VM |
945 | } |
946 | ||
165f639c VM |
947 | /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class |
948 | whose register move cost between any registers of the class is the | |
949 | same as for all its subclasses. We use the data to speed up the | |
950 | 2nd pass of calculations of allocno costs. */ | |
951 | static void | |
952 | setup_uniform_class_p (void) | |
953 | { | |
954 | int i, cl, cl2, m; | |
955 | ||
956 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
957 | { | |
958 | ira_uniform_class_p[cl] = false; | |
959 | if (ira_class_hard_regs_num[cl] == 0) | |
960 | continue; | |
961 | /* We can not use alloc_reg_class_subclasses here because move | |
962 | cost hooks does not take into account that some registers are | |
963 | unavailable for the subtarget. E.g. for i686, INT_SSE_REGS | |
964 | is element of alloc_reg_class_subclasses for GENERAL_REGS | |
965 | because SSE regs are unavailable. */ | |
966 | for (i = 0; (cl2 = reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; i++) | |
967 | { | |
968 | if (ira_class_hard_regs_num[cl2] == 0) | |
969 | continue; | |
970 | for (m = 0; m < NUM_MACHINE_MODES; m++) | |
971 | if (contains_reg_of_mode[cl][m] && contains_reg_of_mode[cl2][m]) | |
972 | { | |
ef4bddc2 | 973 | ira_init_register_move_cost_if_necessary ((machine_mode) m); |
165f639c VM |
974 | if (ira_register_move_cost[m][cl][cl] |
975 | != ira_register_move_cost[m][cl2][cl2]) | |
976 | break; | |
977 | } | |
978 | if (m < NUM_MACHINE_MODES) | |
979 | break; | |
980 | } | |
981 | if (cl2 == LIM_REG_CLASSES) | |
982 | ira_uniform_class_p[cl] = true; | |
983 | } | |
984 | } | |
985 | ||
1756cb66 VM |
986 | /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, |
987 | IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. | |
988 | ||
df3e3493 | 989 | Target may have many subtargets and not all target hard registers can |
1756cb66 VM |
990 | be used for allocation, e.g. x86 port in 32-bit mode can not use |
991 | hard registers introduced in x86-64 like r8-r15). Some classes | |
992 | might have the same allocatable hard registers, e.g. INDEX_REGS | |
993 | and GENERAL_REGS in x86 port in 32-bit mode. To decrease different | |
994 | calculations efforts we introduce allocno classes which contain | |
995 | unique non-empty sets of allocatable hard-registers. | |
996 | ||
997 | Pseudo class cost calculation in ira-costs.c is very expensive. | |
998 | Therefore we are trying to decrease number of classes involved in | |
999 | such calculation. Register classes used in the cost calculation | |
1000 | are called important classes. They are allocno classes and other | |
1001 | non-empty classes whose allocatable hard register sets are inside | |
1002 | of an allocno class hard register set. From the first sight, it | |
1003 | looks like that they are just allocno classes. It is not true. In | |
1004 | example of x86-port in 32-bit mode, allocno classes will contain | |
1005 | GENERAL_REGS but not LEGACY_REGS (because allocatable hard | |
1006 | registers are the same for the both classes). The important | |
1007 | classes will contain GENERAL_REGS and LEGACY_REGS. It is done | |
1008 | because a machine description insn constraint may refers for | |
1009 | LEGACY_REGS and code in ira-costs.c is mostly base on investigation | |
1010 | of the insn constraints. */ | |
058e97ec | 1011 | static void |
1756cb66 | 1012 | setup_allocno_and_important_classes (void) |
058e97ec | 1013 | { |
32e8bb8e | 1014 | int i, j, n, cl; |
db1a8d98 | 1015 | bool set_p; |
058e97ec | 1016 | HARD_REG_SET temp_hard_regset2; |
7db7ed3c VM |
1017 | static enum reg_class classes[LIM_REG_CLASSES + 1]; |
1018 | ||
1756cb66 VM |
1019 | n = 0; |
1020 | /* Collect classes which contain unique sets of allocatable hard | |
1021 | registers. Prefer GENERAL_REGS to other classes containing the | |
1022 | same set of hard registers. */ | |
a58dfa49 | 1023 | for (i = 0; i < LIM_REG_CLASSES; i++) |
99710245 | 1024 | { |
1756cb66 VM |
1025 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); |
1026 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1027 | for (j = 0; j < n; j++) | |
7db7ed3c | 1028 | { |
1756cb66 VM |
1029 | cl = classes[j]; |
1030 | COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); | |
1031 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, | |
1032 | no_unit_alloc_regs); | |
1033 | if (hard_reg_set_equal_p (temp_hard_regset, | |
1034 | temp_hard_regset2)) | |
1035 | break; | |
7db7ed3c | 1036 | } |
1756cb66 VM |
1037 | if (j >= n) |
1038 | classes[n++] = (enum reg_class) i; | |
1039 | else if (i == GENERAL_REGS) | |
1040 | /* Prefer general regs. For i386 example, it means that | |
1041 | we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS | |
1042 | (all of them consists of the same available hard | |
1043 | registers). */ | |
1044 | classes[j] = (enum reg_class) i; | |
7db7ed3c | 1045 | } |
1756cb66 | 1046 | classes[n] = LIM_REG_CLASSES; |
058e97ec | 1047 | |
1756cb66 | 1048 | /* Set up classes which can be used for allocnos as classes |
df3e3493 | 1049 | containing non-empty unique sets of allocatable hard |
1756cb66 VM |
1050 | registers. */ |
1051 | ira_allocno_classes_num = 0; | |
058e97ec | 1052 | for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) |
3e575fe2 | 1053 | if (ira_class_hard_regs_num[cl] > 0) |
1756cb66 | 1054 | ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; |
058e97ec | 1055 | ira_important_classes_num = 0; |
1756cb66 VM |
1056 | /* Add non-allocno classes containing to non-empty set of |
1057 | allocatable hard regs. */ | |
058e97ec | 1058 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
3e575fe2 RS |
1059 | if (ira_class_hard_regs_num[cl] > 0) |
1060 | { | |
1061 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | |
1062 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1063 | set_p = false; | |
1064 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1065 | { | |
1066 | COPY_HARD_REG_SET (temp_hard_regset2, | |
1067 | reg_class_contents[ira_allocno_classes[j]]); | |
1068 | AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); | |
1069 | if ((enum reg_class) cl == ira_allocno_classes[j]) | |
1070 | break; | |
1071 | else if (hard_reg_set_subset_p (temp_hard_regset, | |
1072 | temp_hard_regset2)) | |
1073 | set_p = true; | |
1074 | } | |
1075 | if (set_p && j >= ira_allocno_classes_num) | |
1076 | ira_important_classes[ira_important_classes_num++] | |
1077 | = (enum reg_class) cl; | |
1078 | } | |
1756cb66 VM |
1079 | /* Now add allocno classes to the important classes. */ |
1080 | for (j = 0; j < ira_allocno_classes_num; j++) | |
db1a8d98 | 1081 | ira_important_classes[ira_important_classes_num++] |
1756cb66 VM |
1082 | = ira_allocno_classes[j]; |
1083 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1084 | { | |
1085 | ira_reg_allocno_class_p[cl] = false; | |
1086 | ira_reg_pressure_class_p[cl] = false; | |
1087 | } | |
1088 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1089 | ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; | |
1090 | setup_pressure_classes (); | |
165f639c | 1091 | setup_uniform_class_p (); |
058e97ec | 1092 | } |
058e97ec | 1093 | |
1756cb66 VM |
1094 | /* Setup translation in CLASS_TRANSLATE of all classes into a class |
1095 | given by array CLASSES of length CLASSES_NUM. The function is used | |
1096 | make translation any reg class to an allocno class or to an | |
1097 | pressure class. This translation is necessary for some | |
1098 | calculations when we can use only allocno or pressure classes and | |
1099 | such translation represents an approximate representation of all | |
1100 | classes. | |
1101 | ||
1102 | The translation in case when allocatable hard register set of a | |
1103 | given class is subset of allocatable hard register set of a class | |
1104 | in CLASSES is pretty simple. We use smallest classes from CLASSES | |
1105 | containing a given class. If allocatable hard register set of a | |
1106 | given class is not a subset of any corresponding set of a class | |
1107 | from CLASSES, we use the cheapest (with load/store point of view) | |
2b9c63a2 | 1108 | class from CLASSES whose set intersects with given class set. */ |
058e97ec | 1109 | static void |
1756cb66 VM |
1110 | setup_class_translate_array (enum reg_class *class_translate, |
1111 | int classes_num, enum reg_class *classes) | |
058e97ec | 1112 | { |
32e8bb8e | 1113 | int cl, mode; |
1756cb66 | 1114 | enum reg_class aclass, best_class, *cl_ptr; |
058e97ec VM |
1115 | int i, cost, min_cost, best_cost; |
1116 | ||
1117 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1756cb66 | 1118 | class_translate[cl] = NO_REGS; |
b8698a0f | 1119 | |
1756cb66 | 1120 | for (i = 0; i < classes_num; i++) |
058e97ec | 1121 | { |
1756cb66 VM |
1122 | aclass = classes[i]; |
1123 | for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; | |
1124 | (cl = *cl_ptr) != LIM_REG_CLASSES; | |
1125 | cl_ptr++) | |
1126 | if (class_translate[cl] == NO_REGS) | |
1127 | class_translate[cl] = aclass; | |
1128 | class_translate[aclass] = aclass; | |
058e97ec | 1129 | } |
1756cb66 VM |
1130 | /* For classes which are not fully covered by one of given classes |
1131 | (in other words covered by more one given class), use the | |
1132 | cheapest class. */ | |
058e97ec VM |
1133 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1134 | { | |
1756cb66 | 1135 | if (cl == NO_REGS || class_translate[cl] != NO_REGS) |
058e97ec VM |
1136 | continue; |
1137 | best_class = NO_REGS; | |
1138 | best_cost = INT_MAX; | |
1756cb66 | 1139 | for (i = 0; i < classes_num; i++) |
058e97ec | 1140 | { |
1756cb66 | 1141 | aclass = classes[i]; |
058e97ec | 1142 | COPY_HARD_REG_SET (temp_hard_regset, |
1756cb66 | 1143 | reg_class_contents[aclass]); |
058e97ec VM |
1144 | AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1145 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
4f341ea0 | 1146 | if (! hard_reg_set_empty_p (temp_hard_regset)) |
058e97ec VM |
1147 | { |
1148 | min_cost = INT_MAX; | |
1149 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
1150 | { | |
761a8eb7 VM |
1151 | cost = (ira_memory_move_cost[mode][aclass][0] |
1152 | + ira_memory_move_cost[mode][aclass][1]); | |
058e97ec VM |
1153 | if (min_cost > cost) |
1154 | min_cost = cost; | |
1155 | } | |
1156 | if (best_class == NO_REGS || best_cost > min_cost) | |
1157 | { | |
1756cb66 | 1158 | best_class = aclass; |
058e97ec VM |
1159 | best_cost = min_cost; |
1160 | } | |
1161 | } | |
1162 | } | |
1756cb66 | 1163 | class_translate[cl] = best_class; |
058e97ec VM |
1164 | } |
1165 | } | |
058e97ec | 1166 | |
1756cb66 VM |
1167 | /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and |
1168 | IRA_PRESSURE_CLASS_TRANSLATE. */ | |
1169 | static void | |
1170 | setup_class_translate (void) | |
1171 | { | |
1172 | setup_class_translate_array (ira_allocno_class_translate, | |
1173 | ira_allocno_classes_num, ira_allocno_classes); | |
1174 | setup_class_translate_array (ira_pressure_class_translate, | |
1175 | ira_pressure_classes_num, ira_pressure_classes); | |
1176 | } | |
1177 | ||
1178 | /* Order numbers of allocno classes in original target allocno class | |
1179 | array, -1 for non-allocno classes. */ | |
1180 | static int allocno_class_order[N_REG_CLASSES]; | |
db1a8d98 VM |
1181 | |
1182 | /* The function used to sort the important classes. */ | |
1183 | static int | |
1184 | comp_reg_classes_func (const void *v1p, const void *v2p) | |
1185 | { | |
1186 | enum reg_class cl1 = *(const enum reg_class *) v1p; | |
1187 | enum reg_class cl2 = *(const enum reg_class *) v2p; | |
1756cb66 | 1188 | enum reg_class tcl1, tcl2; |
db1a8d98 VM |
1189 | int diff; |
1190 | ||
1756cb66 VM |
1191 | tcl1 = ira_allocno_class_translate[cl1]; |
1192 | tcl2 = ira_allocno_class_translate[cl2]; | |
1193 | if (tcl1 != NO_REGS && tcl2 != NO_REGS | |
1194 | && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) | |
db1a8d98 VM |
1195 | return diff; |
1196 | return (int) cl1 - (int) cl2; | |
1197 | } | |
1198 | ||
1756cb66 VM |
1199 | /* For correct work of function setup_reg_class_relation we need to |
1200 | reorder important classes according to the order of their allocno | |
1201 | classes. It places important classes containing the same | |
1202 | allocatable hard register set adjacent to each other and allocno | |
1203 | class with the allocatable hard register set right after the other | |
1204 | important classes with the same set. | |
1205 | ||
1206 | In example from comments of function | |
1207 | setup_allocno_and_important_classes, it places LEGACY_REGS and | |
1208 | GENERAL_REGS close to each other and GENERAL_REGS is after | |
1209 | LEGACY_REGS. */ | |
db1a8d98 VM |
1210 | static void |
1211 | reorder_important_classes (void) | |
1212 | { | |
1213 | int i; | |
1214 | ||
1215 | for (i = 0; i < N_REG_CLASSES; i++) | |
1756cb66 VM |
1216 | allocno_class_order[i] = -1; |
1217 | for (i = 0; i < ira_allocno_classes_num; i++) | |
1218 | allocno_class_order[ira_allocno_classes[i]] = i; | |
db1a8d98 VM |
1219 | qsort (ira_important_classes, ira_important_classes_num, |
1220 | sizeof (enum reg_class), comp_reg_classes_func); | |
1756cb66 VM |
1221 | for (i = 0; i < ira_important_classes_num; i++) |
1222 | ira_important_class_nums[ira_important_classes[i]] = i; | |
db1a8d98 VM |
1223 | } |
1224 | ||
1756cb66 VM |
1225 | /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, |
1226 | IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and | |
1227 | IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, | |
1228 | please see corresponding comments in ira-int.h. */ | |
058e97ec | 1229 | static void |
7db7ed3c | 1230 | setup_reg_class_relations (void) |
058e97ec VM |
1231 | { |
1232 | int i, cl1, cl2, cl3; | |
1233 | HARD_REG_SET intersection_set, union_set, temp_set2; | |
7db7ed3c | 1234 | bool important_class_p[N_REG_CLASSES]; |
058e97ec | 1235 | |
7db7ed3c VM |
1236 | memset (important_class_p, 0, sizeof (important_class_p)); |
1237 | for (i = 0; i < ira_important_classes_num; i++) | |
1238 | important_class_p[ira_important_classes[i]] = true; | |
058e97ec VM |
1239 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
1240 | { | |
7db7ed3c | 1241 | ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; |
058e97ec VM |
1242 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1243 | { | |
7db7ed3c | 1244 | ira_reg_classes_intersect_p[cl1][cl2] = false; |
058e97ec | 1245 | ira_reg_class_intersect[cl1][cl2] = NO_REGS; |
55a2c322 | 1246 | ira_reg_class_subset[cl1][cl2] = NO_REGS; |
058e97ec VM |
1247 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); |
1248 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1249 | COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); | |
1250 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
4f341ea0 RS |
1251 | if (hard_reg_set_empty_p (temp_hard_regset) |
1252 | && hard_reg_set_empty_p (temp_set2)) | |
058e97ec | 1253 | { |
1756cb66 VM |
1254 | /* The both classes have no allocatable hard registers |
1255 | -- take all class hard registers into account and use | |
1256 | reg_class_subunion and reg_class_superunion. */ | |
058e97ec VM |
1257 | for (i = 0;; i++) |
1258 | { | |
1259 | cl3 = reg_class_subclasses[cl1][i]; | |
1260 | if (cl3 == LIM_REG_CLASSES) | |
1261 | break; | |
1262 | if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], | |
bbbbb16a ILT |
1263 | (enum reg_class) cl3)) |
1264 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1265 | } |
1756cb66 VM |
1266 | ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; |
1267 | ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; | |
058e97ec VM |
1268 | continue; |
1269 | } | |
7db7ed3c VM |
1270 | ira_reg_classes_intersect_p[cl1][cl2] |
1271 | = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); | |
1272 | if (important_class_p[cl1] && important_class_p[cl2] | |
1273 | && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) | |
1274 | { | |
1756cb66 VM |
1275 | /* CL1 and CL2 are important classes and CL1 allocatable |
1276 | hard register set is inside of CL2 allocatable hard | |
1277 | registers -- make CL1 a superset of CL2. */ | |
7db7ed3c VM |
1278 | enum reg_class *p; |
1279 | ||
1280 | p = &ira_reg_class_super_classes[cl1][0]; | |
1281 | while (*p != LIM_REG_CLASSES) | |
1282 | p++; | |
1283 | *p++ = (enum reg_class) cl2; | |
1284 | *p = LIM_REG_CLASSES; | |
1285 | } | |
1756cb66 VM |
1286 | ira_reg_class_subunion[cl1][cl2] = NO_REGS; |
1287 | ira_reg_class_superunion[cl1][cl2] = NO_REGS; | |
058e97ec VM |
1288 | COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); |
1289 | AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); | |
1290 | AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); | |
1291 | COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); | |
1292 | IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); | |
1293 | AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); | |
55a2c322 | 1294 | for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) |
058e97ec | 1295 | { |
058e97ec VM |
1296 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); |
1297 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
1298 | if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) | |
1299 | { | |
1756cb66 VM |
1300 | /* CL3 allocatable hard register set is inside of |
1301 | intersection of allocatable hard register sets | |
1302 | of CL1 and CL2. */ | |
55a2c322 VM |
1303 | if (important_class_p[cl3]) |
1304 | { | |
1305 | COPY_HARD_REG_SET | |
1306 | (temp_set2, | |
1307 | reg_class_contents | |
1308 | [(int) ira_reg_class_intersect[cl1][cl2]]); | |
1309 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1310 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
1311 | /* If the allocatable hard register sets are | |
1312 | the same, prefer GENERAL_REGS or the | |
1313 | smallest class for debugging | |
1314 | purposes. */ | |
1315 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) | |
1316 | && (cl3 == GENERAL_REGS | |
1317 | || ((ira_reg_class_intersect[cl1][cl2] | |
1318 | != GENERAL_REGS) | |
1319 | && hard_reg_set_subset_p | |
1320 | (reg_class_contents[cl3], | |
1321 | reg_class_contents | |
1322 | [(int) | |
1323 | ira_reg_class_intersect[cl1][cl2]]))))) | |
1324 | ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; | |
1325 | } | |
058e97ec VM |
1326 | COPY_HARD_REG_SET |
1327 | (temp_set2, | |
55a2c322 | 1328 | reg_class_contents[(int) ira_reg_class_subset[cl1][cl2]]); |
058e97ec | 1329 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
55a2c322 VM |
1330 | if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) |
1331 | /* Ignore unavailable hard registers and prefer | |
1332 | smallest class for debugging purposes. */ | |
058e97ec | 1333 | || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) |
55a2c322 VM |
1334 | && hard_reg_set_subset_p |
1335 | (reg_class_contents[cl3], | |
1336 | reg_class_contents | |
1337 | [(int) ira_reg_class_subset[cl1][cl2]]))) | |
1338 | ira_reg_class_subset[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec | 1339 | } |
55a2c322 VM |
1340 | if (important_class_p[cl3] |
1341 | && hard_reg_set_subset_p (temp_hard_regset, union_set)) | |
058e97ec | 1342 | { |
df3e3493 | 1343 | /* CL3 allocatable hard register set is inside of |
1756cb66 VM |
1344 | union of allocatable hard register sets of CL1 |
1345 | and CL2. */ | |
058e97ec VM |
1346 | COPY_HARD_REG_SET |
1347 | (temp_set2, | |
1756cb66 | 1348 | reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); |
058e97ec | 1349 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); |
1756cb66 | 1350 | if (ira_reg_class_subunion[cl1][cl2] == NO_REGS |
058e97ec | 1351 | || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) |
1756cb66 VM |
1352 | |
1353 | && (! hard_reg_set_equal_p (temp_set2, | |
1354 | temp_hard_regset) | |
1355 | || cl3 == GENERAL_REGS | |
1356 | /* If the allocatable hard register sets are the | |
1357 | same, prefer GENERAL_REGS or the smallest | |
1358 | class for debugging purposes. */ | |
1359 | || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS | |
1360 | && hard_reg_set_subset_p | |
1361 | (reg_class_contents[cl3], | |
1362 | reg_class_contents | |
1363 | [(int) ira_reg_class_subunion[cl1][cl2]]))))) | |
1364 | ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; | |
1365 | } | |
1366 | if (hard_reg_set_subset_p (union_set, temp_hard_regset)) | |
1367 | { | |
1368 | /* CL3 allocatable hard register set contains union | |
1369 | of allocatable hard register sets of CL1 and | |
1370 | CL2. */ | |
1371 | COPY_HARD_REG_SET | |
1372 | (temp_set2, | |
1373 | reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); | |
1374 | AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); | |
1375 | if (ira_reg_class_superunion[cl1][cl2] == NO_REGS | |
1376 | || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) | |
b8698a0f | 1377 | |
058e97ec VM |
1378 | && (! hard_reg_set_equal_p (temp_set2, |
1379 | temp_hard_regset) | |
1756cb66 VM |
1380 | || cl3 == GENERAL_REGS |
1381 | /* If the allocatable hard register sets are the | |
1382 | same, prefer GENERAL_REGS or the smallest | |
1383 | class for debugging purposes. */ | |
1384 | || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS | |
1385 | && hard_reg_set_subset_p | |
1386 | (reg_class_contents[cl3], | |
1387 | reg_class_contents | |
1388 | [(int) ira_reg_class_superunion[cl1][cl2]]))))) | |
1389 | ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; | |
058e97ec VM |
1390 | } |
1391 | } | |
1392 | } | |
1393 | } | |
1394 | } | |
1395 | ||
df3e3493 | 1396 | /* Output all uniform and important classes into file F. */ |
165f639c VM |
1397 | static void |
1398 | print_unform_and_important_classes (FILE *f) | |
1399 | { | |
1400 | static const char *const reg_class_names[] = REG_CLASS_NAMES; | |
1401 | int i, cl; | |
1402 | ||
1403 | fprintf (f, "Uniform classes:\n"); | |
1404 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1405 | if (ira_uniform_class_p[cl]) | |
1406 | fprintf (f, " %s", reg_class_names[cl]); | |
1407 | fprintf (f, "\nImportant classes:\n"); | |
1408 | for (i = 0; i < ira_important_classes_num; i++) | |
1409 | fprintf (f, " %s", reg_class_names[ira_important_classes[i]]); | |
1410 | fprintf (f, "\n"); | |
1411 | } | |
1412 | ||
1413 | /* Output all possible allocno or pressure classes and their | |
1414 | translation map into file F. */ | |
058e97ec | 1415 | static void |
165f639c | 1416 | print_translated_classes (FILE *f, bool pressure_p) |
1756cb66 VM |
1417 | { |
1418 | int classes_num = (pressure_p | |
1419 | ? ira_pressure_classes_num : ira_allocno_classes_num); | |
1420 | enum reg_class *classes = (pressure_p | |
1421 | ? ira_pressure_classes : ira_allocno_classes); | |
1422 | enum reg_class *class_translate = (pressure_p | |
1423 | ? ira_pressure_class_translate | |
1424 | : ira_allocno_class_translate); | |
058e97ec VM |
1425 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
1426 | int i; | |
1427 | ||
1756cb66 VM |
1428 | fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); |
1429 | for (i = 0; i < classes_num; i++) | |
1430 | fprintf (f, " %s", reg_class_names[classes[i]]); | |
058e97ec VM |
1431 | fprintf (f, "\nClass translation:\n"); |
1432 | for (i = 0; i < N_REG_CLASSES; i++) | |
1433 | fprintf (f, " %s -> %s\n", reg_class_names[i], | |
1756cb66 | 1434 | reg_class_names[class_translate[i]]); |
058e97ec VM |
1435 | } |
1436 | ||
1756cb66 VM |
1437 | /* Output all possible allocno and translation classes and the |
1438 | translation maps into stderr. */ | |
058e97ec | 1439 | void |
1756cb66 | 1440 | ira_debug_allocno_classes (void) |
058e97ec | 1441 | { |
165f639c VM |
1442 | print_unform_and_important_classes (stderr); |
1443 | print_translated_classes (stderr, false); | |
1444 | print_translated_classes (stderr, true); | |
058e97ec VM |
1445 | } |
1446 | ||
1756cb66 | 1447 | /* Set up different arrays concerning class subsets, allocno and |
058e97ec VM |
1448 | important classes. */ |
1449 | static void | |
1756cb66 | 1450 | find_reg_classes (void) |
058e97ec | 1451 | { |
1756cb66 | 1452 | setup_allocno_and_important_classes (); |
7db7ed3c | 1453 | setup_class_translate (); |
db1a8d98 | 1454 | reorder_important_classes (); |
7db7ed3c | 1455 | setup_reg_class_relations (); |
058e97ec VM |
1456 | } |
1457 | ||
1458 | \f | |
1459 | ||
c0683a82 VM |
1460 | /* Set up the array above. */ |
1461 | static void | |
1756cb66 | 1462 | setup_hard_regno_aclass (void) |
c0683a82 | 1463 | { |
7efcf910 | 1464 | int i; |
c0683a82 VM |
1465 | |
1466 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1467 | { | |
1756cb66 VM |
1468 | #if 1 |
1469 | ira_hard_regno_allocno_class[i] | |
7efcf910 CLT |
1470 | = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) |
1471 | ? NO_REGS | |
1756cb66 VM |
1472 | : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); |
1473 | #else | |
1474 | int j; | |
1475 | enum reg_class cl; | |
1476 | ira_hard_regno_allocno_class[i] = NO_REGS; | |
1477 | for (j = 0; j < ira_allocno_classes_num; j++) | |
1478 | { | |
1479 | cl = ira_allocno_classes[j]; | |
1480 | if (ira_class_hard_reg_index[cl][i] >= 0) | |
1481 | { | |
1482 | ira_hard_regno_allocno_class[i] = cl; | |
1483 | break; | |
1484 | } | |
1485 | } | |
1486 | #endif | |
c0683a82 VM |
1487 | } |
1488 | } | |
1489 | ||
1490 | \f | |
1491 | ||
1756cb66 | 1492 | /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ |
058e97ec VM |
1493 | static void |
1494 | setup_reg_class_nregs (void) | |
1495 | { | |
1756cb66 | 1496 | int i, cl, cl2, m; |
058e97ec | 1497 | |
1756cb66 VM |
1498 | for (m = 0; m < MAX_MACHINE_MODE; m++) |
1499 | { | |
1500 | for (cl = 0; cl < N_REG_CLASSES; cl++) | |
1501 | ira_reg_class_max_nregs[cl][m] | |
1502 | = ira_reg_class_min_nregs[cl][m] | |
ef4bddc2 | 1503 | = targetm.class_max_nregs ((reg_class_t) cl, (machine_mode) m); |
1756cb66 VM |
1504 | for (cl = 0; cl < N_REG_CLASSES; cl++) |
1505 | for (i = 0; | |
1506 | (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; | |
1507 | i++) | |
1508 | if (ira_reg_class_min_nregs[cl2][m] | |
1509 | < ira_reg_class_min_nregs[cl][m]) | |
1510 | ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; | |
1511 | } | |
058e97ec VM |
1512 | } |
1513 | ||
1514 | \f | |
1515 | ||
c9d74da6 RS |
1516 | /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. |
1517 | This function is called once IRA_CLASS_HARD_REGS has been initialized. */ | |
058e97ec VM |
1518 | static void |
1519 | setup_prohibited_class_mode_regs (void) | |
1520 | { | |
c9d74da6 | 1521 | int j, k, hard_regno, cl, last_hard_regno, count; |
058e97ec | 1522 | |
1756cb66 | 1523 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) |
058e97ec | 1524 | { |
c9d74da6 RS |
1525 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); |
1526 | AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); | |
058e97ec VM |
1527 | for (j = 0; j < NUM_MACHINE_MODES; j++) |
1528 | { | |
c9d74da6 RS |
1529 | count = 0; |
1530 | last_hard_regno = -1; | |
1756cb66 | 1531 | CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); |
058e97ec VM |
1532 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) |
1533 | { | |
1534 | hard_regno = ira_class_hard_regs[cl][k]; | |
ef4bddc2 | 1535 | if (! HARD_REGNO_MODE_OK (hard_regno, (machine_mode) j)) |
1756cb66 | 1536 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], |
058e97ec | 1537 | hard_regno); |
c9d74da6 | 1538 | else if (in_hard_reg_set_p (temp_hard_regset, |
ef4bddc2 | 1539 | (machine_mode) j, hard_regno)) |
c9d74da6 RS |
1540 | { |
1541 | last_hard_regno = hard_regno; | |
1542 | count++; | |
1543 | } | |
058e97ec | 1544 | } |
c9d74da6 | 1545 | ira_class_singleton[cl][j] = (count == 1 ? last_hard_regno : -1); |
058e97ec VM |
1546 | } |
1547 | } | |
1548 | } | |
1549 | ||
1756cb66 VM |
1550 | /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers |
1551 | spanning from one register pressure class to another one. It is | |
1552 | called after defining the pressure classes. */ | |
1553 | static void | |
1554 | clarify_prohibited_class_mode_regs (void) | |
1555 | { | |
1556 | int j, k, hard_regno, cl, pclass, nregs; | |
1557 | ||
1558 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | |
1559 | for (j = 0; j < NUM_MACHINE_MODES; j++) | |
a2c19e93 RS |
1560 | { |
1561 | CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); | |
1562 | for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) | |
1563 | { | |
1564 | hard_regno = ira_class_hard_regs[cl][k]; | |
1565 | if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) | |
1566 | continue; | |
1567 | nregs = hard_regno_nregs[hard_regno][j]; | |
1568 | if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) | |
1756cb66 VM |
1569 | { |
1570 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1571 | hard_regno); | |
a2c19e93 | 1572 | continue; |
1756cb66 | 1573 | } |
a2c19e93 RS |
1574 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; |
1575 | for (nregs-- ;nregs >= 0; nregs--) | |
1576 | if (((enum reg_class) pclass | |
1577 | != ira_pressure_class_translate[REGNO_REG_CLASS | |
1578 | (hard_regno + nregs)])) | |
1579 | { | |
1580 | SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1581 | hard_regno); | |
1582 | break; | |
1583 | } | |
1584 | if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], | |
1585 | hard_regno)) | |
1586 | add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], | |
ef4bddc2 | 1587 | (machine_mode) j, hard_regno); |
a2c19e93 RS |
1588 | } |
1589 | } | |
1756cb66 | 1590 | } |
058e97ec | 1591 | \f |
7cc61ee4 RS |
1592 | /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST |
1593 | and IRA_MAY_MOVE_OUT_COST for MODE. */ | |
1594 | void | |
ef4bddc2 | 1595 | ira_init_register_move_cost (machine_mode mode) |
e80ccebc RS |
1596 | { |
1597 | static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES]; | |
1598 | bool all_match = true; | |
ed9e2ed0 | 1599 | unsigned int cl1, cl2; |
e80ccebc | 1600 | |
7cc61ee4 RS |
1601 | ira_assert (ira_register_move_cost[mode] == NULL |
1602 | && ira_may_move_in_cost[mode] == NULL | |
1603 | && ira_may_move_out_cost[mode] == NULL); | |
ed9e2ed0 RS |
1604 | ira_assert (have_regs_of_mode[mode]); |
1605 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) | |
fef37404 VM |
1606 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1607 | { | |
1608 | int cost; | |
1609 | if (!contains_reg_of_mode[cl1][mode] | |
1610 | || !contains_reg_of_mode[cl2][mode]) | |
1611 | { | |
1612 | if ((ira_reg_class_max_nregs[cl1][mode] | |
1613 | > ira_class_hard_regs_num[cl1]) | |
1614 | || (ira_reg_class_max_nregs[cl2][mode] | |
1615 | > ira_class_hard_regs_num[cl2])) | |
1616 | cost = 65535; | |
1617 | else | |
1618 | cost = (ira_memory_move_cost[mode][cl1][0] | |
1a788c05 | 1619 | + ira_memory_move_cost[mode][cl2][1]) * 2; |
fef37404 VM |
1620 | } |
1621 | else | |
1622 | { | |
1623 | cost = register_move_cost (mode, (enum reg_class) cl1, | |
1624 | (enum reg_class) cl2); | |
1625 | ira_assert (cost < 65535); | |
1626 | } | |
1627 | all_match &= (last_move_cost[cl1][cl2] == cost); | |
1628 | last_move_cost[cl1][cl2] = cost; | |
1629 | } | |
e80ccebc RS |
1630 | if (all_match && last_mode_for_init_move_cost != -1) |
1631 | { | |
7cc61ee4 RS |
1632 | ira_register_move_cost[mode] |
1633 | = ira_register_move_cost[last_mode_for_init_move_cost]; | |
1634 | ira_may_move_in_cost[mode] | |
1635 | = ira_may_move_in_cost[last_mode_for_init_move_cost]; | |
1636 | ira_may_move_out_cost[mode] | |
1637 | = ira_may_move_out_cost[last_mode_for_init_move_cost]; | |
e80ccebc RS |
1638 | return; |
1639 | } | |
ed9e2ed0 | 1640 | last_mode_for_init_move_cost = mode; |
7cc61ee4 RS |
1641 | ira_register_move_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); |
1642 | ira_may_move_in_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
1643 | ira_may_move_out_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); | |
ed9e2ed0 | 1644 | for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) |
fef37404 VM |
1645 | for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) |
1646 | { | |
1647 | int cost; | |
1648 | enum reg_class *p1, *p2; | |
1649 | ||
1650 | if (last_move_cost[cl1][cl2] == 65535) | |
1651 | { | |
1652 | ira_register_move_cost[mode][cl1][cl2] = 65535; | |
1653 | ira_may_move_in_cost[mode][cl1][cl2] = 65535; | |
1654 | ira_may_move_out_cost[mode][cl1][cl2] = 65535; | |
1655 | } | |
1656 | else | |
1657 | { | |
1658 | cost = last_move_cost[cl1][cl2]; | |
1659 | ||
1660 | for (p2 = ®_class_subclasses[cl2][0]; | |
1661 | *p2 != LIM_REG_CLASSES; p2++) | |
1662 | if (ira_class_hard_regs_num[*p2] > 0 | |
1663 | && (ira_reg_class_max_nregs[*p2][mode] | |
1664 | <= ira_class_hard_regs_num[*p2])) | |
1665 | cost = MAX (cost, ira_register_move_cost[mode][cl1][*p2]); | |
1666 | ||
1667 | for (p1 = ®_class_subclasses[cl1][0]; | |
1668 | *p1 != LIM_REG_CLASSES; p1++) | |
1669 | if (ira_class_hard_regs_num[*p1] > 0 | |
1670 | && (ira_reg_class_max_nregs[*p1][mode] | |
1671 | <= ira_class_hard_regs_num[*p1])) | |
1672 | cost = MAX (cost, ira_register_move_cost[mode][*p1][cl2]); | |
1673 | ||
1674 | ira_assert (cost <= 65535); | |
1675 | ira_register_move_cost[mode][cl1][cl2] = cost; | |
1676 | ||
1677 | if (ira_class_subset_p[cl1][cl2]) | |
1678 | ira_may_move_in_cost[mode][cl1][cl2] = 0; | |
1679 | else | |
1680 | ira_may_move_in_cost[mode][cl1][cl2] = cost; | |
1681 | ||
1682 | if (ira_class_subset_p[cl2][cl1]) | |
1683 | ira_may_move_out_cost[mode][cl1][cl2] = 0; | |
1684 | else | |
1685 | ira_may_move_out_cost[mode][cl1][cl2] = cost; | |
1686 | } | |
1687 | } | |
058e97ec | 1688 | } |
fef37404 | 1689 | |
058e97ec VM |
1690 | \f |
1691 | ||
058e97ec VM |
1692 | /* This is called once during compiler work. It sets up |
1693 | different arrays whose values don't depend on the compiled | |
1694 | function. */ | |
1695 | void | |
1696 | ira_init_once (void) | |
1697 | { | |
058e97ec | 1698 | ira_init_costs_once (); |
55a2c322 | 1699 | lra_init_once (); |
058e97ec VM |
1700 | } |
1701 | ||
7cc61ee4 RS |
1702 | /* Free ira_max_register_move_cost, ira_may_move_in_cost and |
1703 | ira_may_move_out_cost for each mode. */ | |
19c708dc RS |
1704 | void |
1705 | target_ira_int::free_register_move_costs (void) | |
058e97ec | 1706 | { |
e80ccebc | 1707 | int mode, i; |
058e97ec | 1708 | |
e80ccebc RS |
1709 | /* Reset move_cost and friends, making sure we only free shared |
1710 | table entries once. */ | |
1711 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
19c708dc | 1712 | if (x_ira_register_move_cost[mode]) |
e80ccebc | 1713 | { |
7cc61ee4 | 1714 | for (i = 0; |
19c708dc RS |
1715 | i < mode && (x_ira_register_move_cost[i] |
1716 | != x_ira_register_move_cost[mode]); | |
7cc61ee4 | 1717 | i++) |
e80ccebc RS |
1718 | ; |
1719 | if (i == mode) | |
1720 | { | |
19c708dc RS |
1721 | free (x_ira_register_move_cost[mode]); |
1722 | free (x_ira_may_move_in_cost[mode]); | |
1723 | free (x_ira_may_move_out_cost[mode]); | |
e80ccebc RS |
1724 | } |
1725 | } | |
19c708dc RS |
1726 | memset (x_ira_register_move_cost, 0, sizeof x_ira_register_move_cost); |
1727 | memset (x_ira_may_move_in_cost, 0, sizeof x_ira_may_move_in_cost); | |
1728 | memset (x_ira_may_move_out_cost, 0, sizeof x_ira_may_move_out_cost); | |
e80ccebc | 1729 | last_mode_for_init_move_cost = -1; |
058e97ec VM |
1730 | } |
1731 | ||
19c708dc RS |
1732 | target_ira_int::~target_ira_int () |
1733 | { | |
1734 | free_ira_costs (); | |
1735 | free_register_move_costs (); | |
1736 | } | |
1737 | ||
058e97ec VM |
1738 | /* This is called every time when register related information is |
1739 | changed. */ | |
1740 | void | |
1741 | ira_init (void) | |
1742 | { | |
19c708dc | 1743 | this_target_ira_int->free_register_move_costs (); |
058e97ec VM |
1744 | setup_reg_mode_hard_regset (); |
1745 | setup_alloc_regs (flag_omit_frame_pointer != 0); | |
1746 | setup_class_subset_and_memory_move_costs (); | |
058e97ec VM |
1747 | setup_reg_class_nregs (); |
1748 | setup_prohibited_class_mode_regs (); | |
1756cb66 VM |
1749 | find_reg_classes (); |
1750 | clarify_prohibited_class_mode_regs (); | |
1751 | setup_hard_regno_aclass (); | |
058e97ec VM |
1752 | ira_init_costs (); |
1753 | } | |
1754 | ||
058e97ec | 1755 | \f |
15e7b94f RS |
1756 | #define ira_prohibited_mode_move_regs_initialized_p \ |
1757 | (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) | |
058e97ec VM |
1758 | |
1759 | /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ | |
1760 | static void | |
1761 | setup_prohibited_mode_move_regs (void) | |
1762 | { | |
1763 | int i, j; | |
647d790d DM |
1764 | rtx test_reg1, test_reg2, move_pat; |
1765 | rtx_insn *move_insn; | |
058e97ec VM |
1766 | |
1767 | if (ira_prohibited_mode_move_regs_initialized_p) | |
1768 | return; | |
1769 | ira_prohibited_mode_move_regs_initialized_p = true; | |
1770 | test_reg1 = gen_rtx_REG (VOIDmode, 0); | |
1771 | test_reg2 = gen_rtx_REG (VOIDmode, 0); | |
1772 | move_pat = gen_rtx_SET (VOIDmode, test_reg1, test_reg2); | |
ed8921dc | 1773 | move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, move_pat, 0, -1, 0); |
058e97ec VM |
1774 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
1775 | { | |
1776 | SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); | |
1777 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
1778 | { | |
ef4bddc2 | 1779 | if (! HARD_REGNO_MODE_OK (j, (machine_mode) i)) |
058e97ec | 1780 | continue; |
5444da31 | 1781 | SET_REGNO_RAW (test_reg1, j); |
ef4bddc2 | 1782 | PUT_MODE (test_reg1, (machine_mode) i); |
5444da31 | 1783 | SET_REGNO_RAW (test_reg2, j); |
ef4bddc2 | 1784 | PUT_MODE (test_reg2, (machine_mode) i); |
058e97ec VM |
1785 | INSN_CODE (move_insn) = -1; |
1786 | recog_memoized (move_insn); | |
1787 | if (INSN_CODE (move_insn) < 0) | |
1788 | continue; | |
1789 | extract_insn (move_insn); | |
daca1a96 RS |
1790 | /* We don't know whether the move will be in code that is optimized |
1791 | for size or speed, so consider all enabled alternatives. */ | |
1792 | if (! constrain_operands (1, get_enabled_alternatives (move_insn))) | |
058e97ec VM |
1793 | continue; |
1794 | CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); | |
1795 | } | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | \f | |
1800 | ||
3b6d1699 VM |
1801 | /* Setup possible alternatives in ALTS for INSN. */ |
1802 | void | |
647d790d | 1803 | ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts) |
3b6d1699 VM |
1804 | { |
1805 | /* MAP nalt * nop -> start of constraints for given operand and | |
2b9c63a2 | 1806 | alternative. */ |
3b6d1699 VM |
1807 | static vec<const char *> insn_constraints; |
1808 | int nop, nalt; | |
1809 | bool curr_swapped; | |
1810 | const char *p; | |
1811 | rtx op; | |
1812 | int commutative = -1; | |
1813 | ||
1814 | extract_insn (insn); | |
9840b2fa | 1815 | alternative_mask preferred = get_preferred_alternatives (insn); |
3b6d1699 VM |
1816 | CLEAR_HARD_REG_SET (alts); |
1817 | insn_constraints.release (); | |
1818 | insn_constraints.safe_grow_cleared (recog_data.n_operands | |
1819 | * recog_data.n_alternatives + 1); | |
1820 | /* Check that the hard reg set is enough for holding all | |
1821 | alternatives. It is hard to imagine the situation when the | |
1822 | assertion is wrong. */ | |
1823 | ira_assert (recog_data.n_alternatives | |
1824 | <= (int) MAX (sizeof (HARD_REG_ELT_TYPE) * CHAR_BIT, | |
1825 | FIRST_PSEUDO_REGISTER)); | |
1826 | for (curr_swapped = false;; curr_swapped = true) | |
1827 | { | |
1828 | /* Calculate some data common for all alternatives to speed up the | |
1829 | function. */ | |
1830 | for (nop = 0; nop < recog_data.n_operands; nop++) | |
1831 | { | |
1832 | for (nalt = 0, p = recog_data.constraints[nop]; | |
1833 | nalt < recog_data.n_alternatives; | |
1834 | nalt++) | |
1835 | { | |
1836 | insn_constraints[nop * recog_data.n_alternatives + nalt] = p; | |
1837 | while (*p && *p != ',') | |
1838 | p++; | |
1839 | if (*p) | |
1840 | p++; | |
1841 | } | |
1842 | } | |
1843 | for (nalt = 0; nalt < recog_data.n_alternatives; nalt++) | |
1844 | { | |
9840b2fa | 1845 | if (!TEST_BIT (preferred, nalt) |
4cc8d9d2 | 1846 | || TEST_HARD_REG_BIT (alts, nalt)) |
3b6d1699 VM |
1847 | continue; |
1848 | ||
1849 | for (nop = 0; nop < recog_data.n_operands; nop++) | |
1850 | { | |
1851 | int c, len; | |
1852 | ||
1853 | op = recog_data.operand[nop]; | |
1854 | p = insn_constraints[nop * recog_data.n_alternatives + nalt]; | |
1855 | if (*p == 0 || *p == ',') | |
1856 | continue; | |
1857 | ||
1858 | do | |
1859 | switch (c = *p, len = CONSTRAINT_LEN (c, p), c) | |
1860 | { | |
1861 | case '#': | |
1862 | case ',': | |
1863 | c = '\0'; | |
1864 | case '\0': | |
1865 | len = 0; | |
1866 | break; | |
1867 | ||
3b6d1699 VM |
1868 | case '%': |
1869 | /* We only support one commutative marker, the | |
1870 | first one. We already set commutative | |
1871 | above. */ | |
1872 | if (commutative < 0) | |
1873 | commutative = nop; | |
1874 | break; | |
1875 | ||
3b6d1699 VM |
1876 | case '0': case '1': case '2': case '3': case '4': |
1877 | case '5': case '6': case '7': case '8': case '9': | |
1878 | goto op_success; | |
1879 | break; | |
1880 | ||
3b6d1699 | 1881 | case 'g': |
3b6d1699 VM |
1882 | goto op_success; |
1883 | break; | |
1884 | ||
1885 | default: | |
1886 | { | |
777e635f RS |
1887 | enum constraint_num cn = lookup_constraint (p); |
1888 | switch (get_constraint_type (cn)) | |
1889 | { | |
1890 | case CT_REGISTER: | |
1891 | if (reg_class_for_constraint (cn) != NO_REGS) | |
1892 | goto op_success; | |
1893 | break; | |
1894 | ||
d9c35eee RS |
1895 | case CT_CONST_INT: |
1896 | if (CONST_INT_P (op) | |
1897 | && (insn_const_int_ok_for_constraint | |
1898 | (INTVAL (op), cn))) | |
1899 | goto op_success; | |
1900 | break; | |
1901 | ||
777e635f RS |
1902 | case CT_ADDRESS: |
1903 | case CT_MEMORY: | |
1904 | goto op_success; | |
1905 | ||
1906 | case CT_FIXED_FORM: | |
1907 | if (constraint_satisfied_p (op, cn)) | |
1908 | goto op_success; | |
1909 | break; | |
1910 | } | |
3b6d1699 VM |
1911 | break; |
1912 | } | |
1913 | } | |
1914 | while (p += len, c); | |
1915 | break; | |
1916 | op_success: | |
1917 | ; | |
1918 | } | |
1919 | if (nop >= recog_data.n_operands) | |
1920 | SET_HARD_REG_BIT (alts, nalt); | |
1921 | } | |
1922 | if (commutative < 0) | |
1923 | break; | |
1924 | if (curr_swapped) | |
1925 | break; | |
1926 | op = recog_data.operand[commutative]; | |
1927 | recog_data.operand[commutative] = recog_data.operand[commutative + 1]; | |
1928 | recog_data.operand[commutative + 1] = op; | |
1929 | ||
1930 | } | |
1931 | } | |
1932 | ||
1933 | /* Return the number of the output non-early clobber operand which | |
1934 | should be the same in any case as operand with number OP_NUM (or | |
1935 | negative value if there is no such operand). The function takes | |
1936 | only really possible alternatives into consideration. */ | |
1937 | int | |
1938 | ira_get_dup_out_num (int op_num, HARD_REG_SET &alts) | |
1939 | { | |
1940 | int curr_alt, c, original, dup; | |
1941 | bool ignore_p, use_commut_op_p; | |
1942 | const char *str; | |
3b6d1699 VM |
1943 | |
1944 | if (op_num < 0 || recog_data.n_alternatives == 0) | |
1945 | return -1; | |
98f2f031 RS |
1946 | /* We should find duplications only for input operands. */ |
1947 | if (recog_data.operand_type[op_num] != OP_IN) | |
1948 | return -1; | |
3b6d1699 | 1949 | str = recog_data.constraints[op_num]; |
98f2f031 | 1950 | use_commut_op_p = false; |
3b6d1699 VM |
1951 | for (;;) |
1952 | { | |
777e635f | 1953 | rtx op = recog_data.operand[op_num]; |
3b6d1699 | 1954 | |
98f2f031 RS |
1955 | for (curr_alt = 0, ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt), |
1956 | original = -1;;) | |
3b6d1699 VM |
1957 | { |
1958 | c = *str; | |
1959 | if (c == '\0') | |
1960 | break; | |
98f2f031 | 1961 | if (c == '#') |
3b6d1699 VM |
1962 | ignore_p = true; |
1963 | else if (c == ',') | |
1964 | { | |
1965 | curr_alt++; | |
98f2f031 | 1966 | ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt); |
3b6d1699 VM |
1967 | } |
1968 | else if (! ignore_p) | |
1969 | switch (c) | |
1970 | { | |
3b6d1699 VM |
1971 | case 'g': |
1972 | goto fail; | |
8677664e | 1973 | default: |
3b6d1699 | 1974 | { |
777e635f RS |
1975 | enum constraint_num cn = lookup_constraint (str); |
1976 | enum reg_class cl = reg_class_for_constraint (cn); | |
1977 | if (cl != NO_REGS | |
1978 | && !targetm.class_likely_spilled_p (cl)) | |
1979 | goto fail; | |
1980 | if (constraint_satisfied_p (op, cn)) | |
3b6d1699 | 1981 | goto fail; |
3b6d1699 VM |
1982 | break; |
1983 | } | |
1984 | ||
1985 | case '0': case '1': case '2': case '3': case '4': | |
1986 | case '5': case '6': case '7': case '8': case '9': | |
1987 | if (original != -1 && original != c) | |
1988 | goto fail; | |
1989 | original = c; | |
1990 | break; | |
1991 | } | |
1992 | str += CONSTRAINT_LEN (c, str); | |
1993 | } | |
1994 | if (original == -1) | |
1995 | goto fail; | |
1996 | dup = -1; | |
1997 | for (ignore_p = false, str = recog_data.constraints[original - '0']; | |
1998 | *str != 0; | |
1999 | str++) | |
2000 | if (ignore_p) | |
2001 | { | |
2002 | if (*str == ',') | |
2003 | ignore_p = false; | |
2004 | } | |
2005 | else if (*str == '#') | |
2006 | ignore_p = true; | |
2007 | else if (! ignore_p) | |
2008 | { | |
2009 | if (*str == '=') | |
2010 | dup = original - '0'; | |
2011 | /* It is better ignore an alternative with early clobber. */ | |
2012 | else if (*str == '&') | |
2013 | goto fail; | |
2014 | } | |
2015 | if (dup >= 0) | |
2016 | return dup; | |
2017 | fail: | |
2018 | if (use_commut_op_p) | |
2019 | break; | |
2020 | use_commut_op_p = true; | |
73f793e3 | 2021 | if (recog_data.constraints[op_num][0] == '%') |
3b6d1699 | 2022 | str = recog_data.constraints[op_num + 1]; |
73f793e3 | 2023 | else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%') |
3b6d1699 VM |
2024 | str = recog_data.constraints[op_num - 1]; |
2025 | else | |
2026 | break; | |
2027 | } | |
2028 | return -1; | |
2029 | } | |
2030 | ||
2031 | \f | |
2032 | ||
2033 | /* Search forward to see if the source register of a copy insn dies | |
2034 | before either it or the destination register is modified, but don't | |
2035 | scan past the end of the basic block. If so, we can replace the | |
2036 | source with the destination and let the source die in the copy | |
2037 | insn. | |
2038 | ||
2039 | This will reduce the number of registers live in that range and may | |
2040 | enable the destination and the source coalescing, thus often saving | |
2041 | one register in addition to a register-register copy. */ | |
2042 | ||
2043 | static void | |
2044 | decrease_live_ranges_number (void) | |
2045 | { | |
2046 | basic_block bb; | |
070a1983 | 2047 | rtx_insn *insn; |
b32d5189 DM |
2048 | rtx set, src, dest, dest_death, q, note; |
2049 | rtx_insn *p; | |
3b6d1699 VM |
2050 | int sregno, dregno; |
2051 | ||
2052 | if (! flag_expensive_optimizations) | |
2053 | return; | |
2054 | ||
2055 | if (ira_dump_file) | |
2056 | fprintf (ira_dump_file, "Starting decreasing number of live ranges...\n"); | |
2057 | ||
11cd3bed | 2058 | FOR_EACH_BB_FN (bb, cfun) |
3b6d1699 VM |
2059 | FOR_BB_INSNS (bb, insn) |
2060 | { | |
2061 | set = single_set (insn); | |
2062 | if (! set) | |
2063 | continue; | |
2064 | src = SET_SRC (set); | |
2065 | dest = SET_DEST (set); | |
2066 | if (! REG_P (src) || ! REG_P (dest) | |
2067 | || find_reg_note (insn, REG_DEAD, src)) | |
2068 | continue; | |
2069 | sregno = REGNO (src); | |
2070 | dregno = REGNO (dest); | |
2071 | ||
2072 | /* We don't want to mess with hard regs if register classes | |
2073 | are small. */ | |
2074 | if (sregno == dregno | |
2075 | || (targetm.small_register_classes_for_mode_p (GET_MODE (src)) | |
2076 | && (sregno < FIRST_PSEUDO_REGISTER | |
2077 | || dregno < FIRST_PSEUDO_REGISTER)) | |
2078 | /* We don't see all updates to SP if they are in an | |
2079 | auto-inc memory reference, so we must disallow this | |
2080 | optimization on them. */ | |
2081 | || sregno == STACK_POINTER_REGNUM | |
2082 | || dregno == STACK_POINTER_REGNUM) | |
2083 | continue; | |
2084 | ||
2085 | dest_death = NULL_RTX; | |
2086 | ||
2087 | for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) | |
2088 | { | |
2089 | if (! INSN_P (p)) | |
2090 | continue; | |
2091 | if (BLOCK_FOR_INSN (p) != bb) | |
2092 | break; | |
2093 | ||
2094 | if (reg_set_p (src, p) || reg_set_p (dest, p) | |
2095 | /* If SRC is an asm-declared register, it must not be | |
2096 | replaced in any asm. Unfortunately, the REG_EXPR | |
2097 | tree for the asm variable may be absent in the SRC | |
2098 | rtx, so we can't check the actual register | |
2099 | declaration easily (the asm operand will have it, | |
2100 | though). To avoid complicating the test for a rare | |
2101 | case, we just don't perform register replacement | |
2102 | for a hard reg mentioned in an asm. */ | |
2103 | || (sregno < FIRST_PSEUDO_REGISTER | |
2104 | && asm_noperands (PATTERN (p)) >= 0 | |
2105 | && reg_overlap_mentioned_p (src, PATTERN (p))) | |
2106 | /* Don't change hard registers used by a call. */ | |
2107 | || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER | |
2108 | && find_reg_fusage (p, USE, src)) | |
2109 | /* Don't change a USE of a register. */ | |
2110 | || (GET_CODE (PATTERN (p)) == USE | |
2111 | && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) | |
2112 | break; | |
2113 | ||
2114 | /* See if all of SRC dies in P. This test is slightly | |
2115 | more conservative than it needs to be. */ | |
2116 | if ((note = find_regno_note (p, REG_DEAD, sregno)) | |
2117 | && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) | |
2118 | { | |
2119 | int failed = 0; | |
2120 | ||
2121 | /* We can do the optimization. Scan forward from INSN | |
2122 | again, replacing regs as we go. Set FAILED if a | |
2123 | replacement can't be done. In that case, we can't | |
2124 | move the death note for SRC. This should be | |
2125 | rare. */ | |
2126 | ||
2127 | /* Set to stop at next insn. */ | |
2128 | for (q = next_real_insn (insn); | |
2129 | q != next_real_insn (p); | |
2130 | q = next_real_insn (q)) | |
2131 | { | |
2132 | if (reg_overlap_mentioned_p (src, PATTERN (q))) | |
2133 | { | |
2134 | /* If SRC is a hard register, we might miss | |
2135 | some overlapping registers with | |
2136 | validate_replace_rtx, so we would have to | |
2137 | undo it. We can't if DEST is present in | |
2138 | the insn, so fail in that combination of | |
2139 | cases. */ | |
2140 | if (sregno < FIRST_PSEUDO_REGISTER | |
2141 | && reg_mentioned_p (dest, PATTERN (q))) | |
2142 | failed = 1; | |
2143 | ||
2144 | /* Attempt to replace all uses. */ | |
2145 | else if (!validate_replace_rtx (src, dest, q)) | |
2146 | failed = 1; | |
2147 | ||
2148 | /* If this succeeded, but some part of the | |
2149 | register is still present, undo the | |
2150 | replacement. */ | |
2151 | else if (sregno < FIRST_PSEUDO_REGISTER | |
2152 | && reg_overlap_mentioned_p (src, PATTERN (q))) | |
2153 | { | |
2154 | validate_replace_rtx (dest, src, q); | |
2155 | failed = 1; | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | /* If DEST dies here, remove the death note and | |
2160 | save it for later. Make sure ALL of DEST dies | |
2161 | here; again, this is overly conservative. */ | |
2162 | if (! dest_death | |
2163 | && (dest_death = find_regno_note (q, REG_DEAD, dregno))) | |
2164 | { | |
2165 | if (GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) | |
2166 | remove_note (q, dest_death); | |
2167 | else | |
2168 | { | |
2169 | failed = 1; | |
2170 | dest_death = 0; | |
2171 | } | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | if (! failed) | |
2176 | { | |
2177 | /* Move death note of SRC from P to INSN. */ | |
2178 | remove_note (p, note); | |
2179 | XEXP (note, 1) = REG_NOTES (insn); | |
2180 | REG_NOTES (insn) = note; | |
2181 | } | |
2182 | ||
2183 | /* DEST is also dead if INSN has a REG_UNUSED note for | |
2184 | DEST. */ | |
2185 | if (! dest_death | |
2186 | && (dest_death | |
2187 | = find_regno_note (insn, REG_UNUSED, dregno))) | |
2188 | { | |
2189 | PUT_REG_NOTE_KIND (dest_death, REG_DEAD); | |
2190 | remove_note (insn, dest_death); | |
2191 | } | |
2192 | ||
2193 | /* Put death note of DEST on P if we saw it die. */ | |
2194 | if (dest_death) | |
2195 | { | |
2196 | XEXP (dest_death, 1) = REG_NOTES (p); | |
2197 | REG_NOTES (p) = dest_death; | |
2198 | } | |
2199 | break; | |
2200 | } | |
2201 | ||
2202 | /* If SRC is a hard register which is set or killed in | |
2203 | some other way, we can't do this optimization. */ | |
2204 | else if (sregno < FIRST_PSEUDO_REGISTER && dead_or_set_p (p, src)) | |
2205 | break; | |
2206 | } | |
2207 | } | |
2208 | } | |
2209 | ||
2210 | \f | |
2211 | ||
0896cc66 JL |
2212 | /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ |
2213 | static bool | |
2214 | ira_bad_reload_regno_1 (int regno, rtx x) | |
2215 | { | |
ac0ab4f7 | 2216 | int x_regno, n, i; |
0896cc66 JL |
2217 | ira_allocno_t a; |
2218 | enum reg_class pref; | |
2219 | ||
2220 | /* We only deal with pseudo regs. */ | |
2221 | if (! x || GET_CODE (x) != REG) | |
2222 | return false; | |
2223 | ||
2224 | x_regno = REGNO (x); | |
2225 | if (x_regno < FIRST_PSEUDO_REGISTER) | |
2226 | return false; | |
2227 | ||
2228 | /* If the pseudo prefers REGNO explicitly, then do not consider | |
2229 | REGNO a bad spill choice. */ | |
2230 | pref = reg_preferred_class (x_regno); | |
2231 | if (reg_class_size[pref] == 1) | |
2232 | return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); | |
2233 | ||
2234 | /* If the pseudo conflicts with REGNO, then we consider REGNO a | |
2235 | poor choice for a reload regno. */ | |
2236 | a = ira_regno_allocno_map[x_regno]; | |
ac0ab4f7 BS |
2237 | n = ALLOCNO_NUM_OBJECTS (a); |
2238 | for (i = 0; i < n; i++) | |
2239 | { | |
2240 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2241 | if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) | |
2242 | return true; | |
2243 | } | |
0896cc66 JL |
2244 | return false; |
2245 | } | |
2246 | ||
2247 | /* Return nonzero if REGNO is a particularly bad choice for reloading | |
2248 | IN or OUT. */ | |
2249 | bool | |
2250 | ira_bad_reload_regno (int regno, rtx in, rtx out) | |
2251 | { | |
2252 | return (ira_bad_reload_regno_1 (regno, in) | |
2253 | || ira_bad_reload_regno_1 (regno, out)); | |
2254 | } | |
2255 | ||
b748fbd6 | 2256 | /* Add register clobbers from asm statements. */ |
058e97ec | 2257 | static void |
b748fbd6 | 2258 | compute_regs_asm_clobbered (void) |
058e97ec VM |
2259 | { |
2260 | basic_block bb; | |
2261 | ||
11cd3bed | 2262 | FOR_EACH_BB_FN (bb, cfun) |
058e97ec | 2263 | { |
070a1983 | 2264 | rtx_insn *insn; |
058e97ec VM |
2265 | FOR_BB_INSNS_REVERSE (bb, insn) |
2266 | { | |
bfac633a | 2267 | df_ref def; |
058e97ec | 2268 | |
f33a8d10 | 2269 | if (NONDEBUG_INSN_P (insn) && extract_asm_operands (PATTERN (insn))) |
bfac633a | 2270 | FOR_EACH_INSN_DEF (def, insn) |
058e97ec | 2271 | { |
058e97ec | 2272 | unsigned int dregno = DF_REF_REGNO (def); |
d108e679 AS |
2273 | if (HARD_REGISTER_NUM_P (dregno)) |
2274 | add_to_hard_reg_set (&crtl->asm_clobbers, | |
2275 | GET_MODE (DF_REF_REAL_REG (def)), | |
2276 | dregno); | |
058e97ec VM |
2277 | } |
2278 | } | |
2279 | } | |
2280 | } | |
2281 | ||
2282 | ||
8d49e7ef VM |
2283 | /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and |
2284 | REGS_EVER_LIVE. */ | |
ce18efcb | 2285 | void |
8d49e7ef | 2286 | ira_setup_eliminable_regset (void) |
058e97ec | 2287 | { |
058e97ec | 2288 | #ifdef ELIMINABLE_REGS |
89ceba31 | 2289 | int i; |
058e97ec VM |
2290 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; |
2291 | #endif | |
2292 | /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore | |
2293 | sp for alloca. So we can't eliminate the frame pointer in that | |
2294 | case. At some point, we should improve this by emitting the | |
2295 | sp-adjusting insns for this case. */ | |
55a2c322 | 2296 | frame_pointer_needed |
058e97ec VM |
2297 | = (! flag_omit_frame_pointer |
2298 | || (cfun->calls_alloca && EXIT_IGNORE_STACK) | |
d809253a EB |
2299 | /* We need the frame pointer to catch stack overflow exceptions |
2300 | if the stack pointer is moving. */ | |
2301 | || (flag_stack_check && STACK_CHECK_MOVING_SP) | |
058e97ec | 2302 | || crtl->accesses_prior_frames |
8d49e7ef | 2303 | || (SUPPORTS_STACK_ALIGNMENT && crtl->stack_realign_needed) |
939b37da BI |
2304 | /* We need a frame pointer for all Cilk Plus functions that use |
2305 | Cilk keywords. */ | |
b72271b9 | 2306 | || (flag_cilkplus && cfun->is_cilk_function) |
b52b1749 | 2307 | || targetm.frame_pointer_required ()); |
058e97ec | 2308 | |
8d49e7ef VM |
2309 | /* The chance that FRAME_POINTER_NEEDED is changed from inspecting |
2310 | RTL is very small. So if we use frame pointer for RA and RTL | |
2311 | actually prevents this, we will spill pseudos assigned to the | |
2312 | frame pointer in LRA. */ | |
058e97ec | 2313 | |
55a2c322 VM |
2314 | if (frame_pointer_needed) |
2315 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
2316 | ||
058e97ec VM |
2317 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); |
2318 | CLEAR_HARD_REG_SET (eliminable_regset); | |
2319 | ||
b748fbd6 PB |
2320 | compute_regs_asm_clobbered (); |
2321 | ||
058e97ec VM |
2322 | /* Build the regset of all eliminable registers and show we can't |
2323 | use those that we already know won't be eliminated. */ | |
2324 | #ifdef ELIMINABLE_REGS | |
2325 | for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) | |
2326 | { | |
2327 | bool cannot_elim | |
7b5cbb57 | 2328 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) |
55a2c322 | 2329 | || (eliminables[i].to == STACK_POINTER_REGNUM && frame_pointer_needed)); |
058e97ec | 2330 | |
b748fbd6 | 2331 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) |
058e97ec VM |
2332 | { |
2333 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | |
2334 | ||
2335 | if (cannot_elim) | |
2336 | SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); | |
2337 | } | |
2338 | else if (cannot_elim) | |
2339 | error ("%s cannot be used in asm here", | |
2340 | reg_names[eliminables[i].from]); | |
2341 | else | |
2342 | df_set_regs_ever_live (eliminables[i].from, true); | |
2343 | } | |
e3339d0f | 2344 | #if !HARD_FRAME_POINTER_IS_FRAME_POINTER |
b748fbd6 | 2345 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
2346 | { |
2347 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | |
55a2c322 | 2348 | if (frame_pointer_needed) |
058e97ec VM |
2349 | SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); |
2350 | } | |
55a2c322 | 2351 | else if (frame_pointer_needed) |
058e97ec VM |
2352 | error ("%s cannot be used in asm here", |
2353 | reg_names[HARD_FRAME_POINTER_REGNUM]); | |
2354 | else | |
2355 | df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); | |
2356 | #endif | |
2357 | ||
2358 | #else | |
b748fbd6 | 2359 | if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) |
058e97ec VM |
2360 | { |
2361 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | |
55a2c322 | 2362 | if (frame_pointer_needed) |
058e97ec VM |
2363 | SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); |
2364 | } | |
55a2c322 | 2365 | else if (frame_pointer_needed) |
058e97ec VM |
2366 | error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); |
2367 | else | |
2368 | df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); | |
2369 | #endif | |
2370 | } | |
2371 | ||
2372 | \f | |
2373 | ||
2af2dbdc VM |
2374 | /* Vector of substitutions of register numbers, |
2375 | used to map pseudo regs into hardware regs. | |
2376 | This is set up as a result of register allocation. | |
2377 | Element N is the hard reg assigned to pseudo reg N, | |
2378 | or is -1 if no hard reg was assigned. | |
2379 | If N is a hard reg number, element N is N. */ | |
2380 | short *reg_renumber; | |
2381 | ||
058e97ec VM |
2382 | /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from |
2383 | the allocation found by IRA. */ | |
2384 | static void | |
2385 | setup_reg_renumber (void) | |
2386 | { | |
2387 | int regno, hard_regno; | |
2388 | ira_allocno_t a; | |
2389 | ira_allocno_iterator ai; | |
2390 | ||
2391 | caller_save_needed = 0; | |
2392 | FOR_EACH_ALLOCNO (a, ai) | |
2393 | { | |
55a2c322 VM |
2394 | if (ira_use_lra_p && ALLOCNO_CAP_MEMBER (a) != NULL) |
2395 | continue; | |
058e97ec VM |
2396 | /* There are no caps at this point. */ |
2397 | ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); | |
2398 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2399 | /* It can happen if A is not referenced but partially anticipated | |
2400 | somewhere in a region. */ | |
2401 | ALLOCNO_ASSIGNED_P (a) = true; | |
2402 | ira_free_allocno_updated_costs (a); | |
2403 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
1756cb66 | 2404 | regno = ALLOCNO_REGNO (a); |
058e97ec | 2405 | reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); |
1756cb66 | 2406 | if (hard_regno >= 0) |
058e97ec | 2407 | { |
1756cb66 VM |
2408 | int i, nwords; |
2409 | enum reg_class pclass; | |
2410 | ira_object_t obj; | |
2411 | ||
2412 | pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; | |
2413 | nwords = ALLOCNO_NUM_OBJECTS (a); | |
2414 | for (i = 0; i < nwords; i++) | |
2415 | { | |
2416 | obj = ALLOCNO_OBJECT (a, i); | |
2417 | IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), | |
2418 | reg_class_contents[pclass]); | |
2419 | } | |
2420 | if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 | |
9181a6e5 VM |
2421 | && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a), |
2422 | call_used_reg_set)) | |
1756cb66 VM |
2423 | { |
2424 | ira_assert (!optimize || flag_caller_saves | |
e384e6b5 BS |
2425 | || (ALLOCNO_CALLS_CROSSED_NUM (a) |
2426 | == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) | |
15652f68 | 2427 | || regno >= ira_reg_equiv_len |
55a2c322 | 2428 | || ira_equiv_no_lvalue_p (regno)); |
1756cb66 VM |
2429 | caller_save_needed = 1; |
2430 | } | |
058e97ec VM |
2431 | } |
2432 | } | |
2433 | } | |
2434 | ||
2435 | /* Set up allocno assignment flags for further allocation | |
2436 | improvements. */ | |
2437 | static void | |
2438 | setup_allocno_assignment_flags (void) | |
2439 | { | |
2440 | int hard_regno; | |
2441 | ira_allocno_t a; | |
2442 | ira_allocno_iterator ai; | |
2443 | ||
2444 | FOR_EACH_ALLOCNO (a, ai) | |
2445 | { | |
2446 | if (! ALLOCNO_ASSIGNED_P (a)) | |
2447 | /* It can happen if A is not referenced but partially anticipated | |
2448 | somewhere in a region. */ | |
2449 | ira_free_allocno_updated_costs (a); | |
2450 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2451 | /* Don't assign hard registers to allocnos which are destination | |
2452 | of removed store at the end of loop. It has no sense to keep | |
2453 | the same value in different hard registers. It is also | |
2454 | impossible to assign hard registers correctly to such | |
2455 | allocnos because the cost info and info about intersected | |
2456 | calls are incorrect for them. */ | |
2457 | ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 | |
1756cb66 | 2458 | || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p |
058e97ec | 2459 | || (ALLOCNO_MEMORY_COST (a) |
1756cb66 | 2460 | - ALLOCNO_CLASS_COST (a)) < 0); |
9181a6e5 VM |
2461 | ira_assert |
2462 | (hard_regno < 0 | |
2463 | || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), | |
2464 | reg_class_contents[ALLOCNO_CLASS (a)])); | |
058e97ec VM |
2465 | } |
2466 | } | |
2467 | ||
2468 | /* Evaluate overall allocation cost and the costs for using hard | |
2469 | registers and memory for allocnos. */ | |
2470 | static void | |
2471 | calculate_allocation_cost (void) | |
2472 | { | |
2473 | int hard_regno, cost; | |
2474 | ira_allocno_t a; | |
2475 | ira_allocno_iterator ai; | |
2476 | ||
2477 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; | |
2478 | FOR_EACH_ALLOCNO (a, ai) | |
2479 | { | |
2480 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2481 | ira_assert (hard_regno < 0 | |
9181a6e5 VM |
2482 | || (ira_hard_reg_in_set_p |
2483 | (hard_regno, ALLOCNO_MODE (a), | |
2484 | reg_class_contents[ALLOCNO_CLASS (a)]))); | |
058e97ec VM |
2485 | if (hard_regno < 0) |
2486 | { | |
2487 | cost = ALLOCNO_MEMORY_COST (a); | |
2488 | ira_mem_cost += cost; | |
2489 | } | |
2490 | else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) | |
2491 | { | |
2492 | cost = (ALLOCNO_HARD_REG_COSTS (a) | |
2493 | [ira_class_hard_reg_index | |
1756cb66 | 2494 | [ALLOCNO_CLASS (a)][hard_regno]]); |
058e97ec VM |
2495 | ira_reg_cost += cost; |
2496 | } | |
2497 | else | |
2498 | { | |
1756cb66 | 2499 | cost = ALLOCNO_CLASS_COST (a); |
058e97ec VM |
2500 | ira_reg_cost += cost; |
2501 | } | |
2502 | ira_overall_cost += cost; | |
2503 | } | |
2504 | ||
2505 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
2506 | { | |
2507 | fprintf (ira_dump_file, | |
2bf7560b VM |
2508 | "+++Costs: overall %"PRId64 |
2509 | ", reg %"PRId64 | |
2510 | ", mem %"PRId64 | |
2511 | ", ld %"PRId64 | |
2512 | ", st %"PRId64 | |
2513 | ", move %"PRId64, | |
058e97ec VM |
2514 | ira_overall_cost, ira_reg_cost, ira_mem_cost, |
2515 | ira_load_cost, ira_store_cost, ira_shuffle_cost); | |
2bf7560b | 2516 | fprintf (ira_dump_file, "\n+++ move loops %d, new jumps %d\n", |
058e97ec VM |
2517 | ira_move_loops_num, ira_additional_jumps_num); |
2518 | } | |
2519 | ||
2520 | } | |
2521 | ||
2522 | #ifdef ENABLE_IRA_CHECKING | |
2523 | /* Check the correctness of the allocation. We do need this because | |
2524 | of complicated code to transform more one region internal | |
2525 | representation into one region representation. */ | |
2526 | static void | |
2527 | check_allocation (void) | |
2528 | { | |
fa86d337 | 2529 | ira_allocno_t a; |
ac0ab4f7 | 2530 | int hard_regno, nregs, conflict_nregs; |
058e97ec VM |
2531 | ira_allocno_iterator ai; |
2532 | ||
2533 | FOR_EACH_ALLOCNO (a, ai) | |
2534 | { | |
ac0ab4f7 BS |
2535 | int n = ALLOCNO_NUM_OBJECTS (a); |
2536 | int i; | |
fa86d337 | 2537 | |
058e97ec VM |
2538 | if (ALLOCNO_CAP_MEMBER (a) != NULL |
2539 | || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) | |
2540 | continue; | |
2541 | nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; | |
8cfd82bf BS |
2542 | if (nregs == 1) |
2543 | /* We allocated a single hard register. */ | |
2544 | n = 1; | |
2545 | else if (n > 1) | |
2546 | /* We allocated multiple hard registers, and we will test | |
2547 | conflicts in a granularity of single hard regs. */ | |
2548 | nregs = 1; | |
2549 | ||
ac0ab4f7 BS |
2550 | for (i = 0; i < n; i++) |
2551 | { | |
2552 | ira_object_t obj = ALLOCNO_OBJECT (a, i); | |
2553 | ira_object_t conflict_obj; | |
2554 | ira_object_conflict_iterator oci; | |
2555 | int this_regno = hard_regno; | |
2556 | if (n > 1) | |
fa86d337 | 2557 | { |
2805e6c0 | 2558 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2559 | this_regno += n - i - 1; |
2560 | else | |
2561 | this_regno += i; | |
2562 | } | |
2563 | FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) | |
2564 | { | |
2565 | ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); | |
2566 | int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); | |
2567 | if (conflict_hard_regno < 0) | |
2568 | continue; | |
8cfd82bf BS |
2569 | |
2570 | conflict_nregs | |
2571 | = (hard_regno_nregs | |
2572 | [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); | |
2573 | ||
2574 | if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 | |
2575 | && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) | |
ac0ab4f7 | 2576 | { |
2805e6c0 | 2577 | if (REG_WORDS_BIG_ENDIAN) |
ac0ab4f7 BS |
2578 | conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) |
2579 | - OBJECT_SUBWORD (conflict_obj) - 1); | |
2580 | else | |
2581 | conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); | |
2582 | conflict_nregs = 1; | |
2583 | } | |
ac0ab4f7 BS |
2584 | |
2585 | if ((conflict_hard_regno <= this_regno | |
2586 | && this_regno < conflict_hard_regno + conflict_nregs) | |
2587 | || (this_regno <= conflict_hard_regno | |
2588 | && conflict_hard_regno < this_regno + nregs)) | |
fa86d337 BS |
2589 | { |
2590 | fprintf (stderr, "bad allocation for %d and %d\n", | |
2591 | ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); | |
2592 | gcc_unreachable (); | |
2593 | } | |
2594 | } | |
2595 | } | |
058e97ec VM |
2596 | } |
2597 | } | |
2598 | #endif | |
2599 | ||
55a2c322 VM |
2600 | /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should |
2601 | be already calculated. */ | |
2602 | static void | |
2603 | setup_reg_equiv_init (void) | |
2604 | { | |
2605 | int i; | |
2606 | int max_regno = max_reg_num (); | |
2607 | ||
2608 | for (i = 0; i < max_regno; i++) | |
2609 | reg_equiv_init (i) = ira_reg_equiv[i].init_insns; | |
2610 | } | |
2611 | ||
2612 | /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS | |
2613 | are insns which were generated for such movement. It is assumed | |
2614 | that FROM_REGNO and TO_REGNO always have the same value at the | |
2615 | point of any move containing such registers. This function is used | |
2616 | to update equiv info for register shuffles on the region borders | |
2617 | and for caller save/restore insns. */ | |
2618 | void | |
b32d5189 | 2619 | ira_update_equiv_info_by_shuffle_insn (int to_regno, int from_regno, rtx_insn *insns) |
55a2c322 | 2620 | { |
b32d5189 DM |
2621 | rtx_insn *insn; |
2622 | rtx x, note; | |
55a2c322 VM |
2623 | |
2624 | if (! ira_reg_equiv[from_regno].defined_p | |
2625 | && (! ira_reg_equiv[to_regno].defined_p | |
2626 | || ((x = ira_reg_equiv[to_regno].memory) != NULL_RTX | |
2627 | && ! MEM_READONLY_P (x)))) | |
5a107a0f | 2628 | return; |
55a2c322 VM |
2629 | insn = insns; |
2630 | if (NEXT_INSN (insn) != NULL_RTX) | |
2631 | { | |
2632 | if (! ira_reg_equiv[to_regno].defined_p) | |
2633 | { | |
2634 | ira_assert (ira_reg_equiv[to_regno].init_insns == NULL_RTX); | |
2635 | return; | |
2636 | } | |
2637 | ira_reg_equiv[to_regno].defined_p = false; | |
2638 | ira_reg_equiv[to_regno].memory | |
2639 | = ira_reg_equiv[to_regno].constant | |
2640 | = ira_reg_equiv[to_regno].invariant | |
0cc97fc5 | 2641 | = ira_reg_equiv[to_regno].init_insns = NULL; |
55a2c322 VM |
2642 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) |
2643 | fprintf (ira_dump_file, | |
2644 | " Invalidating equiv info for reg %d\n", to_regno); | |
2645 | return; | |
2646 | } | |
2647 | /* It is possible that FROM_REGNO still has no equivalence because | |
2648 | in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd | |
2649 | insn was not processed yet. */ | |
2650 | if (ira_reg_equiv[from_regno].defined_p) | |
2651 | { | |
2652 | ira_reg_equiv[to_regno].defined_p = true; | |
2653 | if ((x = ira_reg_equiv[from_regno].memory) != NULL_RTX) | |
2654 | { | |
2655 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX | |
2656 | && ira_reg_equiv[from_regno].constant == NULL_RTX); | |
2657 | ira_assert (ira_reg_equiv[to_regno].memory == NULL_RTX | |
2658 | || rtx_equal_p (ira_reg_equiv[to_regno].memory, x)); | |
2659 | ira_reg_equiv[to_regno].memory = x; | |
2660 | if (! MEM_READONLY_P (x)) | |
2661 | /* We don't add the insn to insn init list because memory | |
2662 | equivalence is just to say what memory is better to use | |
2663 | when the pseudo is spilled. */ | |
2664 | return; | |
2665 | } | |
2666 | else if ((x = ira_reg_equiv[from_regno].constant) != NULL_RTX) | |
2667 | { | |
2668 | ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX); | |
2669 | ira_assert (ira_reg_equiv[to_regno].constant == NULL_RTX | |
2670 | || rtx_equal_p (ira_reg_equiv[to_regno].constant, x)); | |
2671 | ira_reg_equiv[to_regno].constant = x; | |
2672 | } | |
2673 | else | |
2674 | { | |
2675 | x = ira_reg_equiv[from_regno].invariant; | |
2676 | ira_assert (x != NULL_RTX); | |
2677 | ira_assert (ira_reg_equiv[to_regno].invariant == NULL_RTX | |
2678 | || rtx_equal_p (ira_reg_equiv[to_regno].invariant, x)); | |
2679 | ira_reg_equiv[to_regno].invariant = x; | |
2680 | } | |
2681 | if (find_reg_note (insn, REG_EQUIV, x) == NULL_RTX) | |
2682 | { | |
2683 | note = set_unique_reg_note (insn, REG_EQUIV, x); | |
2684 | gcc_assert (note != NULL_RTX); | |
2685 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2686 | { | |
2687 | fprintf (ira_dump_file, | |
2688 | " Adding equiv note to insn %u for reg %d ", | |
2689 | INSN_UID (insn), to_regno); | |
cfbeaedf | 2690 | dump_value_slim (ira_dump_file, x, 1); |
55a2c322 VM |
2691 | fprintf (ira_dump_file, "\n"); |
2692 | } | |
2693 | } | |
2694 | } | |
2695 | ira_reg_equiv[to_regno].init_insns | |
2696 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
2697 | ira_reg_equiv[to_regno].init_insns); | |
2698 | if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) | |
2699 | fprintf (ira_dump_file, | |
2700 | " Adding equiv init move insn %u to reg %d\n", | |
2701 | INSN_UID (insn), to_regno); | |
2702 | } | |
2703 | ||
058e97ec VM |
2704 | /* Fix values of array REG_EQUIV_INIT after live range splitting done |
2705 | by IRA. */ | |
2706 | static void | |
2707 | fix_reg_equiv_init (void) | |
2708 | { | |
70cc3288 | 2709 | int max_regno = max_reg_num (); |
f2034d06 | 2710 | int i, new_regno, max; |
058e97ec | 2711 | rtx x, prev, next, insn, set; |
b8698a0f | 2712 | |
70cc3288 | 2713 | if (max_regno_before_ira < max_regno) |
058e97ec | 2714 | { |
9771b263 | 2715 | max = vec_safe_length (reg_equivs); |
f2034d06 JL |
2716 | grow_reg_equivs (); |
2717 | for (i = FIRST_PSEUDO_REGISTER; i < max; i++) | |
2718 | for (prev = NULL_RTX, x = reg_equiv_init (i); | |
2719 | x != NULL_RTX; | |
2720 | x = next) | |
058e97ec VM |
2721 | { |
2722 | next = XEXP (x, 1); | |
2723 | insn = XEXP (x, 0); | |
e8a54173 | 2724 | set = single_set (as_a <rtx_insn *> (insn)); |
058e97ec VM |
2725 | ira_assert (set != NULL_RTX |
2726 | && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); | |
2727 | if (REG_P (SET_DEST (set)) | |
2728 | && ((int) REGNO (SET_DEST (set)) == i | |
2729 | || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) | |
2730 | new_regno = REGNO (SET_DEST (set)); | |
2731 | else if (REG_P (SET_SRC (set)) | |
2732 | && ((int) REGNO (SET_SRC (set)) == i | |
2733 | || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) | |
2734 | new_regno = REGNO (SET_SRC (set)); | |
2735 | else | |
2736 | gcc_unreachable (); | |
2737 | if (new_regno == i) | |
2738 | prev = x; | |
2739 | else | |
2740 | { | |
55a2c322 | 2741 | /* Remove the wrong list element. */ |
058e97ec | 2742 | if (prev == NULL_RTX) |
f2034d06 | 2743 | reg_equiv_init (i) = next; |
058e97ec VM |
2744 | else |
2745 | XEXP (prev, 1) = next; | |
f2034d06 JL |
2746 | XEXP (x, 1) = reg_equiv_init (new_regno); |
2747 | reg_equiv_init (new_regno) = x; | |
058e97ec VM |
2748 | } |
2749 | } | |
2750 | } | |
2751 | } | |
2752 | ||
2753 | #ifdef ENABLE_IRA_CHECKING | |
2754 | /* Print redundant memory-memory copies. */ | |
2755 | static void | |
2756 | print_redundant_copies (void) | |
2757 | { | |
2758 | int hard_regno; | |
2759 | ira_allocno_t a; | |
2760 | ira_copy_t cp, next_cp; | |
2761 | ira_allocno_iterator ai; | |
b8698a0f | 2762 | |
058e97ec VM |
2763 | FOR_EACH_ALLOCNO (a, ai) |
2764 | { | |
2765 | if (ALLOCNO_CAP_MEMBER (a) != NULL) | |
2b9c63a2 | 2766 | /* It is a cap. */ |
058e97ec VM |
2767 | continue; |
2768 | hard_regno = ALLOCNO_HARD_REGNO (a); | |
2769 | if (hard_regno >= 0) | |
2770 | continue; | |
2771 | for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) | |
2772 | if (cp->first == a) | |
2773 | next_cp = cp->next_first_allocno_copy; | |
2774 | else | |
2775 | { | |
2776 | next_cp = cp->next_second_allocno_copy; | |
2777 | if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL | |
2778 | && cp->insn != NULL_RTX | |
2779 | && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) | |
2780 | fprintf (ira_dump_file, | |
2781 | " Redundant move from %d(freq %d):%d\n", | |
2782 | INSN_UID (cp->insn), cp->freq, hard_regno); | |
2783 | } | |
2784 | } | |
2785 | } | |
2786 | #endif | |
2787 | ||
2788 | /* Setup preferred and alternative classes for new pseudo-registers | |
2789 | created by IRA starting with START. */ | |
2790 | static void | |
2791 | setup_preferred_alternate_classes_for_new_pseudos (int start) | |
2792 | { | |
2793 | int i, old_regno; | |
2794 | int max_regno = max_reg_num (); | |
2795 | ||
2796 | for (i = start; i < max_regno; i++) | |
2797 | { | |
2798 | old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); | |
b8698a0f | 2799 | ira_assert (i != old_regno); |
058e97ec | 2800 | setup_reg_classes (i, reg_preferred_class (old_regno), |
ce18efcb | 2801 | reg_alternate_class (old_regno), |
1756cb66 | 2802 | reg_allocno_class (old_regno)); |
058e97ec VM |
2803 | if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
2804 | fprintf (ira_dump_file, | |
2805 | " New r%d: setting preferred %s, alternative %s\n", | |
2806 | i, reg_class_names[reg_preferred_class (old_regno)], | |
2807 | reg_class_names[reg_alternate_class (old_regno)]); | |
2808 | } | |
2809 | } | |
2810 | ||
2811 | \f | |
df3e3493 | 2812 | /* The number of entries allocated in reg_info. */ |
fb99ee9b | 2813 | static int allocated_reg_info_size; |
058e97ec VM |
2814 | |
2815 | /* Regional allocation can create new pseudo-registers. This function | |
2816 | expands some arrays for pseudo-registers. */ | |
2817 | static void | |
fb99ee9b | 2818 | expand_reg_info (void) |
058e97ec VM |
2819 | { |
2820 | int i; | |
2821 | int size = max_reg_num (); | |
2822 | ||
2823 | resize_reg_info (); | |
fb99ee9b | 2824 | for (i = allocated_reg_info_size; i < size; i++) |
ce18efcb | 2825 | setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); |
fb99ee9b BS |
2826 | setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); |
2827 | allocated_reg_info_size = size; | |
058e97ec VM |
2828 | } |
2829 | ||
3553f0bb VM |
2830 | /* Return TRUE if there is too high register pressure in the function. |
2831 | It is used to decide when stack slot sharing is worth to do. */ | |
2832 | static bool | |
2833 | too_high_register_pressure_p (void) | |
2834 | { | |
2835 | int i; | |
1756cb66 | 2836 | enum reg_class pclass; |
b8698a0f | 2837 | |
1756cb66 | 2838 | for (i = 0; i < ira_pressure_classes_num; i++) |
3553f0bb | 2839 | { |
1756cb66 VM |
2840 | pclass = ira_pressure_classes[i]; |
2841 | if (ira_loop_tree_root->reg_pressure[pclass] > 10000) | |
3553f0bb VM |
2842 | return true; |
2843 | } | |
2844 | return false; | |
2845 | } | |
2846 | ||
058e97ec VM |
2847 | \f |
2848 | ||
2af2dbdc VM |
2849 | /* Indicate that hard register number FROM was eliminated and replaced with |
2850 | an offset from hard register number TO. The status of hard registers live | |
2851 | at the start of a basic block is updated by replacing a use of FROM with | |
2852 | a use of TO. */ | |
2853 | ||
2854 | void | |
2855 | mark_elimination (int from, int to) | |
2856 | { | |
2857 | basic_block bb; | |
bf744527 | 2858 | bitmap r; |
2af2dbdc | 2859 | |
11cd3bed | 2860 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 2861 | { |
bf744527 SB |
2862 | r = DF_LR_IN (bb); |
2863 | if (bitmap_bit_p (r, from)) | |
2864 | { | |
2865 | bitmap_clear_bit (r, from); | |
2866 | bitmap_set_bit (r, to); | |
2867 | } | |
2868 | if (! df_live) | |
2869 | continue; | |
2870 | r = DF_LIVE_IN (bb); | |
2871 | if (bitmap_bit_p (r, from)) | |
2af2dbdc | 2872 | { |
bf744527 SB |
2873 | bitmap_clear_bit (r, from); |
2874 | bitmap_set_bit (r, to); | |
2af2dbdc VM |
2875 | } |
2876 | } | |
2877 | } | |
2878 | ||
2879 | \f | |
2880 | ||
55a2c322 VM |
2881 | /* The length of the following array. */ |
2882 | int ira_reg_equiv_len; | |
2883 | ||
2884 | /* Info about equiv. info for each register. */ | |
4c2b2d79 | 2885 | struct ira_reg_equiv_s *ira_reg_equiv; |
55a2c322 VM |
2886 | |
2887 | /* Expand ira_reg_equiv if necessary. */ | |
2888 | void | |
2889 | ira_expand_reg_equiv (void) | |
2890 | { | |
2891 | int old = ira_reg_equiv_len; | |
2892 | ||
2893 | if (ira_reg_equiv_len > max_reg_num ()) | |
2894 | return; | |
2895 | ira_reg_equiv_len = max_reg_num () * 3 / 2 + 1; | |
2896 | ira_reg_equiv | |
4c2b2d79 | 2897 | = (struct ira_reg_equiv_s *) xrealloc (ira_reg_equiv, |
55a2c322 | 2898 | ira_reg_equiv_len |
4c2b2d79 | 2899 | * sizeof (struct ira_reg_equiv_s)); |
55a2c322 VM |
2900 | gcc_assert (old < ira_reg_equiv_len); |
2901 | memset (ira_reg_equiv + old, 0, | |
4c2b2d79 | 2902 | sizeof (struct ira_reg_equiv_s) * (ira_reg_equiv_len - old)); |
55a2c322 VM |
2903 | } |
2904 | ||
2905 | static void | |
2906 | init_reg_equiv (void) | |
2907 | { | |
2908 | ira_reg_equiv_len = 0; | |
2909 | ira_reg_equiv = NULL; | |
2910 | ira_expand_reg_equiv (); | |
2911 | } | |
2912 | ||
2913 | static void | |
2914 | finish_reg_equiv (void) | |
2915 | { | |
2916 | free (ira_reg_equiv); | |
2917 | } | |
2918 | ||
2919 | \f | |
2920 | ||
2af2dbdc VM |
2921 | struct equivalence |
2922 | { | |
2af2dbdc VM |
2923 | /* Set when a REG_EQUIV note is found or created. Use to |
2924 | keep track of what memory accesses might be created later, | |
2925 | e.g. by reload. */ | |
2926 | rtx replacement; | |
2927 | rtx *src_p; | |
fb0ab697 JL |
2928 | |
2929 | /* The list of each instruction which initializes this register. | |
2930 | ||
2931 | NULL indicates we know nothing about this register's equivalence | |
2932 | properties. | |
2933 | ||
2934 | An INSN_LIST with a NULL insn indicates this pseudo is already | |
2935 | known to not have a valid equivalence. */ | |
2936 | rtx_insn_list *init_insns; | |
2937 | ||
2af2dbdc VM |
2938 | /* Loop depth is used to recognize equivalences which appear |
2939 | to be present within the same loop (or in an inner loop). */ | |
5ffa4e6a | 2940 | short loop_depth; |
2af2dbdc | 2941 | /* Nonzero if this had a preexisting REG_EQUIV note. */ |
5ffa4e6a | 2942 | unsigned char is_arg_equivalence : 1; |
8f5929e1 JJ |
2943 | /* Set when an attempt should be made to replace a register |
2944 | with the associated src_p entry. */ | |
5ffa4e6a FY |
2945 | unsigned char replace : 1; |
2946 | /* Set if this register has no known equivalence. */ | |
2947 | unsigned char no_equiv : 1; | |
2af2dbdc VM |
2948 | }; |
2949 | ||
2950 | /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence | |
2951 | structure for that register. */ | |
2952 | static struct equivalence *reg_equiv; | |
2953 | ||
2954 | /* Used for communication between the following two functions: contains | |
2955 | a MEM that we wish to ensure remains unchanged. */ | |
2956 | static rtx equiv_mem; | |
2957 | ||
2958 | /* Set nonzero if EQUIV_MEM is modified. */ | |
2959 | static int equiv_mem_modified; | |
2960 | ||
2961 | /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. | |
2962 | Called via note_stores. */ | |
2963 | static void | |
2964 | validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, | |
2965 | void *data ATTRIBUTE_UNUSED) | |
2966 | { | |
2967 | if ((REG_P (dest) | |
2968 | && reg_overlap_mentioned_p (dest, equiv_mem)) | |
2969 | || (MEM_P (dest) | |
a55757ea | 2970 | && anti_dependence (equiv_mem, dest))) |
2af2dbdc VM |
2971 | equiv_mem_modified = 1; |
2972 | } | |
2973 | ||
2974 | /* Verify that no store between START and the death of REG invalidates | |
2975 | MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, | |
2976 | by storing into an overlapping memory location, or with a non-const | |
2977 | CALL_INSN. | |
2978 | ||
2979 | Return 1 if MEMREF remains valid. */ | |
2980 | static int | |
b32d5189 | 2981 | validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref) |
2af2dbdc | 2982 | { |
b32d5189 | 2983 | rtx_insn *insn; |
2af2dbdc VM |
2984 | rtx note; |
2985 | ||
2986 | equiv_mem = memref; | |
2987 | equiv_mem_modified = 0; | |
2988 | ||
2989 | /* If the memory reference has side effects or is volatile, it isn't a | |
2990 | valid equivalence. */ | |
2991 | if (side_effects_p (memref)) | |
2992 | return 0; | |
2993 | ||
2994 | for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) | |
2995 | { | |
2996 | if (! INSN_P (insn)) | |
2997 | continue; | |
2998 | ||
2999 | if (find_reg_note (insn, REG_DEAD, reg)) | |
3000 | return 1; | |
3001 | ||
a22265a4 JL |
3002 | /* This used to ignore readonly memory and const/pure calls. The problem |
3003 | is the equivalent form may reference a pseudo which gets assigned a | |
3004 | call clobbered hard reg. When we later replace REG with its | |
3005 | equivalent form, the value in the call-clobbered reg has been | |
3006 | changed and all hell breaks loose. */ | |
3007 | if (CALL_P (insn)) | |
2af2dbdc VM |
3008 | return 0; |
3009 | ||
3010 | note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); | |
3011 | ||
3012 | /* If a register mentioned in MEMREF is modified via an | |
3013 | auto-increment, we lose the equivalence. Do the same if one | |
3014 | dies; although we could extend the life, it doesn't seem worth | |
3015 | the trouble. */ | |
3016 | ||
3017 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
3018 | if ((REG_NOTE_KIND (note) == REG_INC | |
3019 | || REG_NOTE_KIND (note) == REG_DEAD) | |
3020 | && REG_P (XEXP (note, 0)) | |
3021 | && reg_overlap_mentioned_p (XEXP (note, 0), memref)) | |
3022 | return 0; | |
3023 | } | |
3024 | ||
3025 | return 0; | |
3026 | } | |
3027 | ||
3028 | /* Returns zero if X is known to be invariant. */ | |
3029 | static int | |
3030 | equiv_init_varies_p (rtx x) | |
3031 | { | |
3032 | RTX_CODE code = GET_CODE (x); | |
3033 | int i; | |
3034 | const char *fmt; | |
3035 | ||
3036 | switch (code) | |
3037 | { | |
3038 | case MEM: | |
3039 | return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); | |
3040 | ||
3041 | case CONST: | |
d8116890 | 3042 | CASE_CONST_ANY: |
2af2dbdc VM |
3043 | case SYMBOL_REF: |
3044 | case LABEL_REF: | |
3045 | return 0; | |
3046 | ||
3047 | case REG: | |
3048 | return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); | |
3049 | ||
3050 | case ASM_OPERANDS: | |
3051 | if (MEM_VOLATILE_P (x)) | |
3052 | return 1; | |
3053 | ||
3054 | /* Fall through. */ | |
3055 | ||
3056 | default: | |
3057 | break; | |
3058 | } | |
3059 | ||
3060 | fmt = GET_RTX_FORMAT (code); | |
3061 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3062 | if (fmt[i] == 'e') | |
3063 | { | |
3064 | if (equiv_init_varies_p (XEXP (x, i))) | |
3065 | return 1; | |
3066 | } | |
3067 | else if (fmt[i] == 'E') | |
3068 | { | |
3069 | int j; | |
3070 | for (j = 0; j < XVECLEN (x, i); j++) | |
3071 | if (equiv_init_varies_p (XVECEXP (x, i, j))) | |
3072 | return 1; | |
3073 | } | |
3074 | ||
3075 | return 0; | |
3076 | } | |
3077 | ||
3078 | /* Returns nonzero if X (used to initialize register REGNO) is movable. | |
3079 | X is only movable if the registers it uses have equivalent initializations | |
3080 | which appear to be within the same loop (or in an inner loop) and movable | |
3081 | or if they are not candidates for local_alloc and don't vary. */ | |
3082 | static int | |
3083 | equiv_init_movable_p (rtx x, int regno) | |
3084 | { | |
3085 | int i, j; | |
3086 | const char *fmt; | |
3087 | enum rtx_code code = GET_CODE (x); | |
3088 | ||
3089 | switch (code) | |
3090 | { | |
3091 | case SET: | |
3092 | return equiv_init_movable_p (SET_SRC (x), regno); | |
3093 | ||
3094 | case CC0: | |
3095 | case CLOBBER: | |
3096 | return 0; | |
3097 | ||
3098 | case PRE_INC: | |
3099 | case PRE_DEC: | |
3100 | case POST_INC: | |
3101 | case POST_DEC: | |
3102 | case PRE_MODIFY: | |
3103 | case POST_MODIFY: | |
3104 | return 0; | |
3105 | ||
3106 | case REG: | |
1756cb66 VM |
3107 | return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth |
3108 | && reg_equiv[REGNO (x)].replace) | |
3109 | || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS | |
3110 | && ! rtx_varies_p (x, 0))); | |
2af2dbdc VM |
3111 | |
3112 | case UNSPEC_VOLATILE: | |
3113 | return 0; | |
3114 | ||
3115 | case ASM_OPERANDS: | |
3116 | if (MEM_VOLATILE_P (x)) | |
3117 | return 0; | |
3118 | ||
3119 | /* Fall through. */ | |
3120 | ||
3121 | default: | |
3122 | break; | |
3123 | } | |
3124 | ||
3125 | fmt = GET_RTX_FORMAT (code); | |
3126 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3127 | switch (fmt[i]) | |
3128 | { | |
3129 | case 'e': | |
3130 | if (! equiv_init_movable_p (XEXP (x, i), regno)) | |
3131 | return 0; | |
3132 | break; | |
3133 | case 'E': | |
3134 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3135 | if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) | |
3136 | return 0; | |
3137 | break; | |
3138 | } | |
3139 | ||
3140 | return 1; | |
3141 | } | |
3142 | ||
1756cb66 VM |
3143 | /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is |
3144 | true. */ | |
2af2dbdc VM |
3145 | static int |
3146 | contains_replace_regs (rtx x) | |
3147 | { | |
3148 | int i, j; | |
3149 | const char *fmt; | |
3150 | enum rtx_code code = GET_CODE (x); | |
3151 | ||
3152 | switch (code) | |
3153 | { | |
2af2dbdc VM |
3154 | case CONST: |
3155 | case LABEL_REF: | |
3156 | case SYMBOL_REF: | |
d8116890 | 3157 | CASE_CONST_ANY: |
2af2dbdc VM |
3158 | case PC: |
3159 | case CC0: | |
3160 | case HIGH: | |
3161 | return 0; | |
3162 | ||
3163 | case REG: | |
3164 | return reg_equiv[REGNO (x)].replace; | |
3165 | ||
3166 | default: | |
3167 | break; | |
3168 | } | |
3169 | ||
3170 | fmt = GET_RTX_FORMAT (code); | |
3171 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3172 | switch (fmt[i]) | |
3173 | { | |
3174 | case 'e': | |
3175 | if (contains_replace_regs (XEXP (x, i))) | |
3176 | return 1; | |
3177 | break; | |
3178 | case 'E': | |
3179 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3180 | if (contains_replace_regs (XVECEXP (x, i, j))) | |
3181 | return 1; | |
3182 | break; | |
3183 | } | |
3184 | ||
3185 | return 0; | |
3186 | } | |
3187 | ||
3188 | /* TRUE if X references a memory location that would be affected by a store | |
3189 | to MEMREF. */ | |
3190 | static int | |
3191 | memref_referenced_p (rtx memref, rtx x) | |
3192 | { | |
3193 | int i, j; | |
3194 | const char *fmt; | |
3195 | enum rtx_code code = GET_CODE (x); | |
3196 | ||
3197 | switch (code) | |
3198 | { | |
2af2dbdc VM |
3199 | case CONST: |
3200 | case LABEL_REF: | |
3201 | case SYMBOL_REF: | |
d8116890 | 3202 | CASE_CONST_ANY: |
2af2dbdc VM |
3203 | case PC: |
3204 | case CC0: | |
3205 | case HIGH: | |
3206 | case LO_SUM: | |
3207 | return 0; | |
3208 | ||
3209 | case REG: | |
3210 | return (reg_equiv[REGNO (x)].replacement | |
3211 | && memref_referenced_p (memref, | |
3212 | reg_equiv[REGNO (x)].replacement)); | |
3213 | ||
3214 | case MEM: | |
53d9622b | 3215 | if (true_dependence (memref, VOIDmode, x)) |
2af2dbdc VM |
3216 | return 1; |
3217 | break; | |
3218 | ||
3219 | case SET: | |
3220 | /* If we are setting a MEM, it doesn't count (its address does), but any | |
3221 | other SET_DEST that has a MEM in it is referencing the MEM. */ | |
3222 | if (MEM_P (SET_DEST (x))) | |
3223 | { | |
3224 | if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) | |
3225 | return 1; | |
3226 | } | |
3227 | else if (memref_referenced_p (memref, SET_DEST (x))) | |
3228 | return 1; | |
3229 | ||
3230 | return memref_referenced_p (memref, SET_SRC (x)); | |
3231 | ||
3232 | default: | |
3233 | break; | |
3234 | } | |
3235 | ||
3236 | fmt = GET_RTX_FORMAT (code); | |
3237 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3238 | switch (fmt[i]) | |
3239 | { | |
3240 | case 'e': | |
3241 | if (memref_referenced_p (memref, XEXP (x, i))) | |
3242 | return 1; | |
3243 | break; | |
3244 | case 'E': | |
3245 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3246 | if (memref_referenced_p (memref, XVECEXP (x, i, j))) | |
3247 | return 1; | |
3248 | break; | |
3249 | } | |
3250 | ||
3251 | return 0; | |
3252 | } | |
3253 | ||
3254 | /* TRUE if some insn in the range (START, END] references a memory location | |
3255 | that would be affected by a store to MEMREF. */ | |
3256 | static int | |
b32d5189 | 3257 | memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) |
2af2dbdc | 3258 | { |
b32d5189 | 3259 | rtx_insn *insn; |
2af2dbdc VM |
3260 | |
3261 | for (insn = NEXT_INSN (start); insn != NEXT_INSN (end); | |
3262 | insn = NEXT_INSN (insn)) | |
3263 | { | |
b5b8b0ac | 3264 | if (!NONDEBUG_INSN_P (insn)) |
2af2dbdc | 3265 | continue; |
b8698a0f | 3266 | |
2af2dbdc VM |
3267 | if (memref_referenced_p (memref, PATTERN (insn))) |
3268 | return 1; | |
3269 | ||
3270 | /* Nonconst functions may access memory. */ | |
3271 | if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) | |
3272 | return 1; | |
3273 | } | |
3274 | ||
3275 | return 0; | |
3276 | } | |
3277 | ||
3278 | /* Mark REG as having no known equivalence. | |
3279 | Some instructions might have been processed before and furnished | |
3280 | with REG_EQUIV notes for this register; these notes will have to be | |
3281 | removed. | |
3282 | STORE is the piece of RTL that does the non-constant / conflicting | |
3283 | assignment - a SET, CLOBBER or REG_INC note. It is currently not used, | |
3284 | but needs to be there because this function is called from note_stores. */ | |
3285 | static void | |
1756cb66 VM |
3286 | no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, |
3287 | void *data ATTRIBUTE_UNUSED) | |
2af2dbdc VM |
3288 | { |
3289 | int regno; | |
fb0ab697 | 3290 | rtx_insn_list *list; |
2af2dbdc VM |
3291 | |
3292 | if (!REG_P (reg)) | |
3293 | return; | |
3294 | regno = REGNO (reg); | |
5ffa4e6a | 3295 | reg_equiv[regno].no_equiv = 1; |
2af2dbdc | 3296 | list = reg_equiv[regno].init_insns; |
fb0ab697 | 3297 | if (list && list->insn () == NULL) |
2af2dbdc | 3298 | return; |
fb0ab697 | 3299 | reg_equiv[regno].init_insns = gen_rtx_INSN_LIST (VOIDmode, NULL_RTX, NULL); |
2af2dbdc VM |
3300 | reg_equiv[regno].replacement = NULL_RTX; |
3301 | /* This doesn't matter for equivalences made for argument registers, we | |
3302 | should keep their initialization insns. */ | |
3303 | if (reg_equiv[regno].is_arg_equivalence) | |
3304 | return; | |
55a2c322 | 3305 | ira_reg_equiv[regno].defined_p = false; |
0cc97fc5 | 3306 | ira_reg_equiv[regno].init_insns = NULL; |
fb0ab697 | 3307 | for (; list; list = list->next ()) |
2af2dbdc | 3308 | { |
fb0ab697 | 3309 | rtx_insn *insn = list->insn (); |
2af2dbdc VM |
3310 | remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); |
3311 | } | |
3312 | } | |
3313 | ||
e3f9e0ac WM |
3314 | /* Check whether the SUBREG is a paradoxical subreg and set the result |
3315 | in PDX_SUBREGS. */ | |
3316 | ||
40954ce5 RS |
3317 | static void |
3318 | set_paradoxical_subreg (rtx_insn *insn, bool *pdx_subregs) | |
e3f9e0ac | 3319 | { |
40954ce5 RS |
3320 | subrtx_iterator::array_type array; |
3321 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
3322 | { | |
3323 | const_rtx subreg = *iter; | |
3324 | if (GET_CODE (subreg) == SUBREG) | |
3325 | { | |
3326 | const_rtx reg = SUBREG_REG (subreg); | |
3327 | if (REG_P (reg) && paradoxical_subreg_p (subreg)) | |
3328 | pdx_subregs[REGNO (reg)] = true; | |
3329 | } | |
3330 | } | |
e3f9e0ac WM |
3331 | } |
3332 | ||
3a6191b1 JJ |
3333 | /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the |
3334 | equivalent replacement. */ | |
3335 | ||
3336 | static rtx | |
3337 | adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
3338 | { | |
3339 | if (REG_P (loc)) | |
3340 | { | |
3341 | bitmap cleared_regs = (bitmap) data; | |
3342 | if (bitmap_bit_p (cleared_regs, REGNO (loc))) | |
b8f045e2 | 3343 | return simplify_replace_fn_rtx (copy_rtx (*reg_equiv[REGNO (loc)].src_p), |
3a6191b1 JJ |
3344 | NULL_RTX, adjust_cleared_regs, data); |
3345 | } | |
3346 | return NULL_RTX; | |
3347 | } | |
3348 | ||
2af2dbdc VM |
3349 | /* Nonzero if we recorded an equivalence for a LABEL_REF. */ |
3350 | static int recorded_label_ref; | |
3351 | ||
3352 | /* Find registers that are equivalent to a single value throughout the | |
1756cb66 VM |
3353 | compilation (either because they can be referenced in memory or are |
3354 | set once from a single constant). Lower their priority for a | |
3355 | register. | |
2af2dbdc | 3356 | |
1756cb66 VM |
3357 | If such a register is only referenced once, try substituting its |
3358 | value into the using insn. If it succeeds, we can eliminate the | |
3359 | register completely. | |
2af2dbdc | 3360 | |
55a2c322 | 3361 | Initialize init_insns in ira_reg_equiv array. |
2af2dbdc VM |
3362 | |
3363 | Return non-zero if jump label rebuilding should be done. */ | |
3364 | static int | |
3365 | update_equiv_regs (void) | |
3366 | { | |
b2908ba6 | 3367 | rtx_insn *insn; |
2af2dbdc VM |
3368 | basic_block bb; |
3369 | int loop_depth; | |
3370 | bitmap cleared_regs; | |
e3f9e0ac | 3371 | bool *pdx_subregs; |
b8698a0f | 3372 | |
2af2dbdc VM |
3373 | /* We need to keep track of whether or not we recorded a LABEL_REF so |
3374 | that we know if the jump optimizer needs to be rerun. */ | |
3375 | recorded_label_ref = 0; | |
3376 | ||
e3f9e0ac WM |
3377 | /* Use pdx_subregs to show whether a reg is used in a paradoxical |
3378 | subreg. */ | |
3379 | pdx_subregs = XCNEWVEC (bool, max_regno); | |
3380 | ||
2af2dbdc | 3381 | reg_equiv = XCNEWVEC (struct equivalence, max_regno); |
f2034d06 | 3382 | grow_reg_equivs (); |
2af2dbdc VM |
3383 | |
3384 | init_alias_analysis (); | |
3385 | ||
e3f9e0ac | 3386 | /* Scan insns and set pdx_subregs[regno] if the reg is used in a |
df3e3493 | 3387 | paradoxical subreg. Don't set such reg equivalent to a mem, |
e3f9e0ac WM |
3388 | because lra will not substitute such equiv memory in order to |
3389 | prevent access beyond allocated memory for paradoxical memory subreg. */ | |
11cd3bed | 3390 | FOR_EACH_BB_FN (bb, cfun) |
e3f9e0ac | 3391 | FOR_BB_INSNS (bb, insn) |
c34c46dd | 3392 | if (NONDEBUG_INSN_P (insn)) |
40954ce5 | 3393 | set_paradoxical_subreg (insn, pdx_subregs); |
e3f9e0ac | 3394 | |
2af2dbdc VM |
3395 | /* Scan the insns and find which registers have equivalences. Do this |
3396 | in a separate scan of the insns because (due to -fcse-follow-jumps) | |
3397 | a register can be set below its use. */ | |
11cd3bed | 3398 | FOR_EACH_BB_FN (bb, cfun) |
2af2dbdc | 3399 | { |
391886c8 | 3400 | loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3401 | |
3402 | for (insn = BB_HEAD (bb); | |
3403 | insn != NEXT_INSN (BB_END (bb)); | |
3404 | insn = NEXT_INSN (insn)) | |
3405 | { | |
3406 | rtx note; | |
3407 | rtx set; | |
3408 | rtx dest, src; | |
3409 | int regno; | |
3410 | ||
3411 | if (! INSN_P (insn)) | |
3412 | continue; | |
3413 | ||
3414 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
3415 | if (REG_NOTE_KIND (note) == REG_INC) | |
3416 | no_equiv (XEXP (note, 0), note, NULL); | |
3417 | ||
3418 | set = single_set (insn); | |
3419 | ||
3420 | /* If this insn contains more (or less) than a single SET, | |
3421 | only mark all destinations as having no known equivalence. */ | |
5ffa4e6a | 3422 | if (set == NULL_RTX) |
2af2dbdc VM |
3423 | { |
3424 | note_stores (PATTERN (insn), no_equiv, NULL); | |
3425 | continue; | |
3426 | } | |
3427 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
3428 | { | |
3429 | int i; | |
3430 | ||
3431 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
3432 | { | |
3433 | rtx part = XVECEXP (PATTERN (insn), 0, i); | |
3434 | if (part != set) | |
3435 | note_stores (part, no_equiv, NULL); | |
3436 | } | |
3437 | } | |
3438 | ||
3439 | dest = SET_DEST (set); | |
3440 | src = SET_SRC (set); | |
3441 | ||
3442 | /* See if this is setting up the equivalence between an argument | |
3443 | register and its stack slot. */ | |
3444 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | |
3445 | if (note) | |
3446 | { | |
3447 | gcc_assert (REG_P (dest)); | |
3448 | regno = REGNO (dest); | |
3449 | ||
55a2c322 VM |
3450 | /* Note that we don't want to clear init_insns in |
3451 | ira_reg_equiv even if there are multiple sets of this | |
3452 | register. */ | |
2af2dbdc VM |
3453 | reg_equiv[regno].is_arg_equivalence = 1; |
3454 | ||
5a107a0f VM |
3455 | /* The insn result can have equivalence memory although |
3456 | the equivalence is not set up by the insn. We add | |
3457 | this insn to init insns as it is a flag for now that | |
3458 | regno has an equivalence. We will remove the insn | |
3459 | from init insn list later. */ | |
3460 | if (rtx_equal_p (src, XEXP (note, 0)) || MEM_P (XEXP (note, 0))) | |
55a2c322 VM |
3461 | ira_reg_equiv[regno].init_insns |
3462 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3463 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3464 | |
3465 | /* Continue normally in case this is a candidate for | |
3466 | replacements. */ | |
3467 | } | |
3468 | ||
3469 | if (!optimize) | |
3470 | continue; | |
3471 | ||
3472 | /* We only handle the case of a pseudo register being set | |
3473 | once, or always to the same value. */ | |
1fe28116 VM |
3474 | /* ??? The mn10200 port breaks if we add equivalences for |
3475 | values that need an ADDRESS_REGS register and set them equivalent | |
3476 | to a MEM of a pseudo. The actual problem is in the over-conservative | |
3477 | handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in | |
3478 | calculate_needs, but we traditionally work around this problem | |
3479 | here by rejecting equivalences when the destination is in a register | |
3480 | that's likely spilled. This is fragile, of course, since the | |
3481 | preferred class of a pseudo depends on all instructions that set | |
3482 | or use it. */ | |
3483 | ||
2af2dbdc VM |
3484 | if (!REG_P (dest) |
3485 | || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER | |
fb0ab697 JL |
3486 | || (reg_equiv[regno].init_insns |
3487 | && reg_equiv[regno].init_insns->insn () == NULL) | |
07b8f0a8 | 3488 | || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) |
1fe28116 | 3489 | && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) |
2af2dbdc VM |
3490 | { |
3491 | /* This might be setting a SUBREG of a pseudo, a pseudo that is | |
3492 | also set somewhere else to a constant. */ | |
3493 | note_stores (set, no_equiv, NULL); | |
3494 | continue; | |
3495 | } | |
3496 | ||
e3f9e0ac WM |
3497 | /* Don't set reg (if pdx_subregs[regno] == true) equivalent to a mem. */ |
3498 | if (MEM_P (src) && pdx_subregs[regno]) | |
3499 | { | |
3500 | note_stores (set, no_equiv, NULL); | |
3501 | continue; | |
3502 | } | |
3503 | ||
2af2dbdc VM |
3504 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); |
3505 | ||
3506 | /* cse sometimes generates function invariants, but doesn't put a | |
3507 | REG_EQUAL note on the insn. Since this note would be redundant, | |
3508 | there's no point creating it earlier than here. */ | |
3509 | if (! note && ! rtx_varies_p (src, 0)) | |
3510 | note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); | |
3511 | ||
3512 | /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST | |
2b9c63a2 | 3513 | since it represents a function call. */ |
2af2dbdc VM |
3514 | if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) |
3515 | note = NULL_RTX; | |
3516 | ||
5ffa4e6a FY |
3517 | if (DF_REG_DEF_COUNT (regno) != 1) |
3518 | { | |
3519 | bool equal_p = true; | |
3520 | rtx_insn_list *list; | |
3521 | ||
3522 | /* If we have already processed this pseudo and determined it | |
3523 | can not have an equivalence, then honor that decision. */ | |
3524 | if (reg_equiv[regno].no_equiv) | |
3525 | continue; | |
3526 | ||
3527 | if (! note | |
2af2dbdc VM |
3528 | || rtx_varies_p (XEXP (note, 0), 0) |
3529 | || (reg_equiv[regno].replacement | |
3530 | && ! rtx_equal_p (XEXP (note, 0), | |
5ffa4e6a FY |
3531 | reg_equiv[regno].replacement))) |
3532 | { | |
3533 | no_equiv (dest, set, NULL); | |
3534 | continue; | |
3535 | } | |
3536 | ||
3537 | list = reg_equiv[regno].init_insns; | |
3538 | for (; list; list = list->next ()) | |
3539 | { | |
3540 | rtx note_tmp; | |
3541 | rtx_insn *insn_tmp; | |
3542 | ||
3543 | insn_tmp = list->insn (); | |
3544 | note_tmp = find_reg_note (insn_tmp, REG_EQUAL, NULL_RTX); | |
3545 | gcc_assert (note_tmp); | |
3546 | if (! rtx_equal_p (XEXP (note, 0), XEXP (note_tmp, 0))) | |
3547 | { | |
3548 | equal_p = false; | |
3549 | break; | |
3550 | } | |
3551 | } | |
3552 | ||
3553 | if (! equal_p) | |
3554 | { | |
3555 | no_equiv (dest, set, NULL); | |
3556 | continue; | |
3557 | } | |
2af2dbdc | 3558 | } |
5ffa4e6a | 3559 | |
2af2dbdc VM |
3560 | /* Record this insn as initializing this register. */ |
3561 | reg_equiv[regno].init_insns | |
3562 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); | |
3563 | ||
3564 | /* If this register is known to be equal to a constant, record that | |
3565 | it is always equivalent to the constant. */ | |
3566 | if (DF_REG_DEF_COUNT (regno) == 1 | |
3567 | && note && ! rtx_varies_p (XEXP (note, 0), 0)) | |
3568 | { | |
3569 | rtx note_value = XEXP (note, 0); | |
3570 | remove_note (insn, note); | |
3571 | set_unique_reg_note (insn, REG_EQUIV, note_value); | |
3572 | } | |
3573 | ||
3574 | /* If this insn introduces a "constant" register, decrease the priority | |
3575 | of that register. Record this insn if the register is only used once | |
3576 | more and the equivalence value is the same as our source. | |
3577 | ||
3578 | The latter condition is checked for two reasons: First, it is an | |
3579 | indication that it may be more efficient to actually emit the insn | |
3580 | as written (if no registers are available, reload will substitute | |
3581 | the equivalence). Secondly, it avoids problems with any registers | |
3582 | dying in this insn whose death notes would be missed. | |
3583 | ||
3584 | If we don't have a REG_EQUIV note, see if this insn is loading | |
3585 | a register used only in one basic block from a MEM. If so, and the | |
3586 | MEM remains unchanged for the life of the register, add a REG_EQUIV | |
3587 | note. */ | |
2af2dbdc VM |
3588 | note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
3589 | ||
5ffa4e6a | 3590 | if (note == NULL_RTX && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS |
2af2dbdc VM |
3591 | && MEM_P (SET_SRC (set)) |
3592 | && validate_equiv_mem (insn, dest, SET_SRC (set))) | |
3593 | note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); | |
3594 | ||
3595 | if (note) | |
3596 | { | |
3597 | int regno = REGNO (dest); | |
3598 | rtx x = XEXP (note, 0); | |
3599 | ||
3600 | /* If we haven't done so, record for reload that this is an | |
3601 | equivalencing insn. */ | |
3602 | if (!reg_equiv[regno].is_arg_equivalence) | |
55a2c322 VM |
3603 | ira_reg_equiv[regno].init_insns |
3604 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
3605 | ira_reg_equiv[regno].init_insns); | |
2af2dbdc VM |
3606 | |
3607 | /* Record whether or not we created a REG_EQUIV note for a LABEL_REF. | |
3608 | We might end up substituting the LABEL_REF for uses of the | |
3609 | pseudo here or later. That kind of transformation may turn an | |
3610 | indirect jump into a direct jump, in which case we must rerun the | |
3611 | jump optimizer to ensure that the JUMP_LABEL fields are valid. */ | |
3612 | if (GET_CODE (x) == LABEL_REF | |
3613 | || (GET_CODE (x) == CONST | |
3614 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3615 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF))) | |
3616 | recorded_label_ref = 1; | |
3617 | ||
3618 | reg_equiv[regno].replacement = x; | |
3619 | reg_equiv[regno].src_p = &SET_SRC (set); | |
5ffa4e6a | 3620 | reg_equiv[regno].loop_depth = (short) loop_depth; |
2af2dbdc VM |
3621 | |
3622 | /* Don't mess with things live during setjmp. */ | |
3623 | if (REG_LIVE_LENGTH (regno) >= 0 && optimize) | |
3624 | { | |
3625 | /* Note that the statement below does not affect the priority | |
3626 | in local-alloc! */ | |
3627 | REG_LIVE_LENGTH (regno) *= 2; | |
3628 | ||
3629 | /* If the register is referenced exactly twice, meaning it is | |
3630 | set once and used once, indicate that the reference may be | |
3631 | replaced by the equivalence we computed above. Do this | |
3632 | even if the register is only used in one block so that | |
3633 | dependencies can be handled where the last register is | |
3634 | used in a different block (i.e. HIGH / LO_SUM sequences) | |
3635 | and to reduce the number of registers alive across | |
3636 | calls. */ | |
3637 | ||
3638 | if (REG_N_REFS (regno) == 2 | |
3639 | && (rtx_equal_p (x, src) | |
3640 | || ! equiv_init_varies_p (src)) | |
3641 | && NONJUMP_INSN_P (insn) | |
3642 | && equiv_init_movable_p (PATTERN (insn), regno)) | |
3643 | reg_equiv[regno].replace = 1; | |
3644 | } | |
3645 | } | |
3646 | } | |
3647 | } | |
3648 | ||
3649 | if (!optimize) | |
3650 | goto out; | |
3651 | ||
3652 | /* A second pass, to gather additional equivalences with memory. This needs | |
3653 | to be done after we know which registers we are going to replace. */ | |
3654 | ||
3655 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3656 | { | |
3657 | rtx set, src, dest; | |
3658 | unsigned regno; | |
3659 | ||
3660 | if (! INSN_P (insn)) | |
3661 | continue; | |
3662 | ||
3663 | set = single_set (insn); | |
3664 | if (! set) | |
3665 | continue; | |
3666 | ||
3667 | dest = SET_DEST (set); | |
3668 | src = SET_SRC (set); | |
3669 | ||
3670 | /* If this sets a MEM to the contents of a REG that is only used | |
3671 | in a single basic block, see if the register is always equivalent | |
3672 | to that memory location and if moving the store from INSN to the | |
3673 | insn that set REG is safe. If so, put a REG_EQUIV note on the | |
3674 | initializing insn. | |
3675 | ||
3676 | Don't add a REG_EQUIV note if the insn already has one. The existing | |
3677 | REG_EQUIV is likely more useful than the one we are adding. | |
3678 | ||
3679 | If one of the regs in the address has reg_equiv[REGNO].replace set, | |
3680 | then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace | |
3681 | optimization may move the set of this register immediately before | |
3682 | insn, which puts it after reg_equiv[REGNO].init_insns, and hence | |
3683 | the mention in the REG_EQUIV note would be to an uninitialized | |
3684 | pseudo. */ | |
3685 | ||
3686 | if (MEM_P (dest) && REG_P (src) | |
3687 | && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER | |
3688 | && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS | |
3689 | && DF_REG_DEF_COUNT (regno) == 1 | |
fb0ab697 JL |
3690 | && reg_equiv[regno].init_insns != NULL |
3691 | && reg_equiv[regno].init_insns->insn () != NULL | |
2af2dbdc VM |
3692 | && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), |
3693 | REG_EQUIV, NULL_RTX) | |
e3f9e0ac WM |
3694 | && ! contains_replace_regs (XEXP (dest, 0)) |
3695 | && ! pdx_subregs[regno]) | |
2af2dbdc | 3696 | { |
b2908ba6 DM |
3697 | rtx_insn *init_insn = |
3698 | as_a <rtx_insn *> (XEXP (reg_equiv[regno].init_insns, 0)); | |
2af2dbdc VM |
3699 | if (validate_equiv_mem (init_insn, src, dest) |
3700 | && ! memref_used_between_p (dest, init_insn, insn) | |
3701 | /* Attaching a REG_EQUIV note will fail if INIT_INSN has | |
3702 | multiple sets. */ | |
3703 | && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) | |
3704 | { | |
3705 | /* This insn makes the equivalence, not the one initializing | |
3706 | the register. */ | |
55a2c322 | 3707 | ira_reg_equiv[regno].init_insns |
2af2dbdc VM |
3708 | = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); |
3709 | df_notes_rescan (init_insn); | |
3710 | } | |
3711 | } | |
3712 | } | |
3713 | ||
3714 | cleared_regs = BITMAP_ALLOC (NULL); | |
3715 | /* Now scan all regs killed in an insn to see if any of them are | |
3716 | registers only used that once. If so, see if we can replace the | |
3717 | reference with the equivalent form. If we can, delete the | |
3718 | initializing reference and this register will go away. If we | |
3719 | can't replace the reference, and the initializing reference is | |
3720 | within the same loop (or in an inner loop), then move the register | |
3721 | initialization just before the use, so that they are in the same | |
3722 | basic block. */ | |
4f42035e | 3723 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
2af2dbdc | 3724 | { |
391886c8 | 3725 | loop_depth = bb_loop_depth (bb); |
2af2dbdc VM |
3726 | for (insn = BB_END (bb); |
3727 | insn != PREV_INSN (BB_HEAD (bb)); | |
3728 | insn = PREV_INSN (insn)) | |
3729 | { | |
3730 | rtx link; | |
3731 | ||
3732 | if (! INSN_P (insn)) | |
3733 | continue; | |
3734 | ||
3735 | /* Don't substitute into a non-local goto, this confuses CFG. */ | |
3736 | if (JUMP_P (insn) | |
3737 | && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
3738 | continue; | |
3739 | ||
3740 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
3741 | { | |
3742 | if (REG_NOTE_KIND (link) == REG_DEAD | |
3743 | /* Make sure this insn still refers to the register. */ | |
3744 | && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) | |
3745 | { | |
3746 | int regno = REGNO (XEXP (link, 0)); | |
3747 | rtx equiv_insn; | |
3748 | ||
3749 | if (! reg_equiv[regno].replace | |
5ffa4e6a | 3750 | || reg_equiv[regno].loop_depth < (short) loop_depth |
f20f2613 VM |
3751 | /* There is no sense to move insns if live range |
3752 | shrinkage or register pressure-sensitive | |
3753 | scheduling were done because it will not | |
3754 | improve allocation but worsen insn schedule | |
3755 | with a big probability. */ | |
3756 | || flag_live_range_shrinkage | |
0cad4827 | 3757 | || (flag_sched_pressure && flag_schedule_insns)) |
2af2dbdc VM |
3758 | continue; |
3759 | ||
3760 | /* reg_equiv[REGNO].replace gets set only when | |
3761 | REG_N_REFS[REGNO] is 2, i.e. the register is set | |
55a2c322 VM |
3762 | once and used once. (If it were only set, but |
3763 | not used, flow would have deleted the setting | |
3764 | insns.) Hence there can only be one insn in | |
3765 | reg_equiv[REGNO].init_insns. */ | |
2af2dbdc VM |
3766 | gcc_assert (reg_equiv[regno].init_insns |
3767 | && !XEXP (reg_equiv[regno].init_insns, 1)); | |
3768 | equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); | |
3769 | ||
3770 | /* We may not move instructions that can throw, since | |
3771 | that changes basic block boundaries and we are not | |
3772 | prepared to adjust the CFG to match. */ | |
3773 | if (can_throw_internal (equiv_insn)) | |
3774 | continue; | |
3775 | ||
3776 | if (asm_noperands (PATTERN (equiv_insn)) < 0 | |
3777 | && validate_replace_rtx (regno_reg_rtx[regno], | |
3778 | *(reg_equiv[regno].src_p), insn)) | |
3779 | { | |
3780 | rtx equiv_link; | |
3781 | rtx last_link; | |
3782 | rtx note; | |
3783 | ||
3784 | /* Find the last note. */ | |
3785 | for (last_link = link; XEXP (last_link, 1); | |
3786 | last_link = XEXP (last_link, 1)) | |
3787 | ; | |
3788 | ||
3789 | /* Append the REG_DEAD notes from equiv_insn. */ | |
3790 | equiv_link = REG_NOTES (equiv_insn); | |
3791 | while (equiv_link) | |
3792 | { | |
3793 | note = equiv_link; | |
3794 | equiv_link = XEXP (equiv_link, 1); | |
3795 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
3796 | { | |
3797 | remove_note (equiv_insn, note); | |
3798 | XEXP (last_link, 1) = note; | |
3799 | XEXP (note, 1) = NULL_RTX; | |
3800 | last_link = note; | |
3801 | } | |
3802 | } | |
3803 | ||
3804 | remove_death (regno, insn); | |
3805 | SET_REG_N_REFS (regno, 0); | |
3806 | REG_FREQ (regno) = 0; | |
3807 | delete_insn (equiv_insn); | |
3808 | ||
3809 | reg_equiv[regno].init_insns | |
fb0ab697 | 3810 | = reg_equiv[regno].init_insns->next (); |
2af2dbdc | 3811 | |
0cc97fc5 | 3812 | ira_reg_equiv[regno].init_insns = NULL; |
2af2dbdc VM |
3813 | bitmap_set_bit (cleared_regs, regno); |
3814 | } | |
3815 | /* Move the initialization of the register to just before | |
3816 | INSN. Update the flow information. */ | |
b5b8b0ac | 3817 | else if (prev_nondebug_insn (insn) != equiv_insn) |
2af2dbdc | 3818 | { |
b2908ba6 | 3819 | rtx_insn *new_insn; |
2af2dbdc VM |
3820 | |
3821 | new_insn = emit_insn_before (PATTERN (equiv_insn), insn); | |
3822 | REG_NOTES (new_insn) = REG_NOTES (equiv_insn); | |
3823 | REG_NOTES (equiv_insn) = 0; | |
3824 | /* Rescan it to process the notes. */ | |
3825 | df_insn_rescan (new_insn); | |
3826 | ||
3827 | /* Make sure this insn is recognized before | |
3828 | reload begins, otherwise | |
3829 | eliminate_regs_in_insn will die. */ | |
3830 | INSN_CODE (new_insn) = INSN_CODE (equiv_insn); | |
3831 | ||
3832 | delete_insn (equiv_insn); | |
3833 | ||
3834 | XEXP (reg_equiv[regno].init_insns, 0) = new_insn; | |
3835 | ||
3836 | REG_BASIC_BLOCK (regno) = bb->index; | |
3837 | REG_N_CALLS_CROSSED (regno) = 0; | |
3838 | REG_FREQ_CALLS_CROSSED (regno) = 0; | |
3839 | REG_N_THROWING_CALLS_CROSSED (regno) = 0; | |
3840 | REG_LIVE_LENGTH (regno) = 2; | |
3841 | ||
3842 | if (insn == BB_HEAD (bb)) | |
1130d5e3 | 3843 | BB_HEAD (bb) = PREV_INSN (insn); |
2af2dbdc | 3844 | |
55a2c322 | 3845 | ira_reg_equiv[regno].init_insns |
2af2dbdc VM |
3846 | = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); |
3847 | bitmap_set_bit (cleared_regs, regno); | |
3848 | } | |
3849 | } | |
3850 | } | |
3851 | } | |
3852 | } | |
3853 | ||
3854 | if (!bitmap_empty_p (cleared_regs)) | |
3a6191b1 | 3855 | { |
11cd3bed | 3856 | FOR_EACH_BB_FN (bb, cfun) |
3a6191b1 | 3857 | { |
3a6191b1 JJ |
3858 | bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); |
3859 | bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); | |
bf744527 SB |
3860 | if (! df_live) |
3861 | continue; | |
3862 | bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); | |
3863 | bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); | |
3a6191b1 JJ |
3864 | } |
3865 | ||
3866 | /* Last pass - adjust debug insns referencing cleared regs. */ | |
3867 | if (MAY_HAVE_DEBUG_INSNS) | |
3868 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3869 | if (DEBUG_INSN_P (insn)) | |
3870 | { | |
3871 | rtx old_loc = INSN_VAR_LOCATION_LOC (insn); | |
3872 | INSN_VAR_LOCATION_LOC (insn) | |
3873 | = simplify_replace_fn_rtx (old_loc, NULL_RTX, | |
3874 | adjust_cleared_regs, | |
3875 | (void *) cleared_regs); | |
3876 | if (old_loc != INSN_VAR_LOCATION_LOC (insn)) | |
3877 | df_insn_rescan (insn); | |
3878 | } | |
3879 | } | |
2af2dbdc VM |
3880 | |
3881 | BITMAP_FREE (cleared_regs); | |
3882 | ||
3883 | out: | |
3884 | /* Clean up. */ | |
3885 | ||
3886 | end_alias_analysis (); | |
3887 | free (reg_equiv); | |
e3f9e0ac | 3888 | free (pdx_subregs); |
2af2dbdc VM |
3889 | return recorded_label_ref; |
3890 | } | |
3891 | ||
3892 | \f | |
3893 | ||
55a2c322 VM |
3894 | /* Set up fields memory, constant, and invariant from init_insns in |
3895 | the structures of array ira_reg_equiv. */ | |
3896 | static void | |
3897 | setup_reg_equiv (void) | |
3898 | { | |
3899 | int i; | |
0cc97fc5 DM |
3900 | rtx_insn_list *elem, *prev_elem, *next_elem; |
3901 | rtx_insn *insn; | |
3902 | rtx set, x; | |
55a2c322 VM |
3903 | |
3904 | for (i = FIRST_PSEUDO_REGISTER; i < ira_reg_equiv_len; i++) | |
5a107a0f VM |
3905 | for (prev_elem = NULL, elem = ira_reg_equiv[i].init_insns; |
3906 | elem; | |
3907 | prev_elem = elem, elem = next_elem) | |
55a2c322 | 3908 | { |
0cc97fc5 DM |
3909 | next_elem = elem->next (); |
3910 | insn = elem->insn (); | |
55a2c322 VM |
3911 | set = single_set (insn); |
3912 | ||
3913 | /* Init insns can set up equivalence when the reg is a destination or | |
3914 | a source (in this case the destination is memory). */ | |
3915 | if (set != 0 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))) | |
3916 | { | |
3917 | if ((x = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL) | |
5a107a0f VM |
3918 | { |
3919 | x = XEXP (x, 0); | |
3920 | if (REG_P (SET_DEST (set)) | |
3921 | && REGNO (SET_DEST (set)) == (unsigned int) i | |
3922 | && ! rtx_equal_p (SET_SRC (set), x) && MEM_P (x)) | |
3923 | { | |
3924 | /* This insn reporting the equivalence but | |
3925 | actually not setting it. Remove it from the | |
3926 | list. */ | |
3927 | if (prev_elem == NULL) | |
3928 | ira_reg_equiv[i].init_insns = next_elem; | |
3929 | else | |
3930 | XEXP (prev_elem, 1) = next_elem; | |
3931 | elem = prev_elem; | |
3932 | } | |
3933 | } | |
55a2c322 VM |
3934 | else if (REG_P (SET_DEST (set)) |
3935 | && REGNO (SET_DEST (set)) == (unsigned int) i) | |
3936 | x = SET_SRC (set); | |
3937 | else | |
3938 | { | |
3939 | gcc_assert (REG_P (SET_SRC (set)) | |
3940 | && REGNO (SET_SRC (set)) == (unsigned int) i); | |
3941 | x = SET_DEST (set); | |
3942 | } | |
3943 | if (! function_invariant_p (x) | |
3944 | || ! flag_pic | |
3945 | /* A function invariant is often CONSTANT_P but may | |
3946 | include a register. We promise to only pass | |
3947 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
3948 | || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | |
3949 | { | |
3950 | /* It can happen that a REG_EQUIV note contains a MEM | |
3951 | that is not a legitimate memory operand. As later | |
3952 | stages of reload assume that all addresses found in | |
3953 | the lra_regno_equiv_* arrays were originally | |
3954 | legitimate, we ignore such REG_EQUIV notes. */ | |
3955 | if (memory_operand (x, VOIDmode)) | |
3956 | { | |
3957 | ira_reg_equiv[i].defined_p = true; | |
3958 | ira_reg_equiv[i].memory = x; | |
3959 | continue; | |
3960 | } | |
3961 | else if (function_invariant_p (x)) | |
3962 | { | |
ef4bddc2 | 3963 | machine_mode mode; |
55a2c322 VM |
3964 | |
3965 | mode = GET_MODE (SET_DEST (set)); | |
3966 | if (GET_CODE (x) == PLUS | |
3967 | || x == frame_pointer_rtx || x == arg_pointer_rtx) | |
3968 | /* This is PLUS of frame pointer and a constant, | |
3969 | or fp, or argp. */ | |
3970 | ira_reg_equiv[i].invariant = x; | |
3971 | else if (targetm.legitimate_constant_p (mode, x)) | |
3972 | ira_reg_equiv[i].constant = x; | |
3973 | else | |
3974 | { | |
3975 | ira_reg_equiv[i].memory = force_const_mem (mode, x); | |
3976 | if (ira_reg_equiv[i].memory == NULL_RTX) | |
3977 | { | |
3978 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 3979 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
3980 | break; |
3981 | } | |
3982 | } | |
3983 | ira_reg_equiv[i].defined_p = true; | |
3984 | continue; | |
3985 | } | |
3986 | } | |
3987 | } | |
3988 | ira_reg_equiv[i].defined_p = false; | |
0cc97fc5 | 3989 | ira_reg_equiv[i].init_insns = NULL; |
55a2c322 VM |
3990 | break; |
3991 | } | |
3992 | } | |
3993 | ||
3994 | \f | |
3995 | ||
2af2dbdc VM |
3996 | /* Print chain C to FILE. */ |
3997 | static void | |
3998 | print_insn_chain (FILE *file, struct insn_chain *c) | |
3999 | { | |
c3284718 | 4000 | fprintf (file, "insn=%d, ", INSN_UID (c->insn)); |
2af2dbdc VM |
4001 | bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); |
4002 | bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); | |
4003 | } | |
4004 | ||
4005 | ||
4006 | /* Print all reload_insn_chains to FILE. */ | |
4007 | static void | |
4008 | print_insn_chains (FILE *file) | |
4009 | { | |
4010 | struct insn_chain *c; | |
4011 | for (c = reload_insn_chain; c ; c = c->next) | |
4012 | print_insn_chain (file, c); | |
4013 | } | |
4014 | ||
4015 | /* Return true if pseudo REGNO should be added to set live_throughout | |
4016 | or dead_or_set of the insn chains for reload consideration. */ | |
4017 | static bool | |
4018 | pseudo_for_reload_consideration_p (int regno) | |
4019 | { | |
4020 | /* Consider spilled pseudos too for IRA because they still have a | |
4021 | chance to get hard-registers in the reload when IRA is used. */ | |
b100151b | 4022 | return (reg_renumber[regno] >= 0 || ira_conflicts_p); |
2af2dbdc VM |
4023 | } |
4024 | ||
4025 | /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using | |
4026 | REG to the number of nregs, and INIT_VALUE to get the | |
4027 | initialization. ALLOCNUM need not be the regno of REG. */ | |
4028 | static void | |
4029 | init_live_subregs (bool init_value, sbitmap *live_subregs, | |
cee784f5 | 4030 | bitmap live_subregs_used, int allocnum, rtx reg) |
2af2dbdc VM |
4031 | { |
4032 | unsigned int regno = REGNO (SUBREG_REG (reg)); | |
4033 | int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); | |
4034 | ||
4035 | gcc_assert (size > 0); | |
4036 | ||
4037 | /* Been there, done that. */ | |
cee784f5 | 4038 | if (bitmap_bit_p (live_subregs_used, allocnum)) |
2af2dbdc VM |
4039 | return; |
4040 | ||
cee784f5 | 4041 | /* Create a new one. */ |
2af2dbdc VM |
4042 | if (live_subregs[allocnum] == NULL) |
4043 | live_subregs[allocnum] = sbitmap_alloc (size); | |
4044 | ||
4045 | /* If the entire reg was live before blasting into subregs, we need | |
4046 | to init all of the subregs to ones else init to 0. */ | |
4047 | if (init_value) | |
f61e445a | 4048 | bitmap_ones (live_subregs[allocnum]); |
b8698a0f | 4049 | else |
f61e445a | 4050 | bitmap_clear (live_subregs[allocnum]); |
2af2dbdc | 4051 | |
cee784f5 | 4052 | bitmap_set_bit (live_subregs_used, allocnum); |
2af2dbdc VM |
4053 | } |
4054 | ||
4055 | /* Walk the insns of the current function and build reload_insn_chain, | |
4056 | and record register life information. */ | |
4057 | static void | |
4058 | build_insn_chain (void) | |
4059 | { | |
4060 | unsigned int i; | |
4061 | struct insn_chain **p = &reload_insn_chain; | |
4062 | basic_block bb; | |
4063 | struct insn_chain *c = NULL; | |
4064 | struct insn_chain *next = NULL; | |
4065 | bitmap live_relevant_regs = BITMAP_ALLOC (NULL); | |
4066 | bitmap elim_regset = BITMAP_ALLOC (NULL); | |
4067 | /* live_subregs is a vector used to keep accurate information about | |
4068 | which hardregs are live in multiword pseudos. live_subregs and | |
4069 | live_subregs_used are indexed by pseudo number. The live_subreg | |
4070 | entry for a particular pseudo is only used if the corresponding | |
cee784f5 SB |
4071 | element is non zero in live_subregs_used. The sbitmap size of |
4072 | live_subreg[allocno] is number of bytes that the pseudo can | |
2af2dbdc VM |
4073 | occupy. */ |
4074 | sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); | |
cee784f5 | 4075 | bitmap live_subregs_used = BITMAP_ALLOC (NULL); |
2af2dbdc VM |
4076 | |
4077 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
4078 | if (TEST_HARD_REG_BIT (eliminable_regset, i)) | |
4079 | bitmap_set_bit (elim_regset, i); | |
4f42035e | 4080 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
2af2dbdc VM |
4081 | { |
4082 | bitmap_iterator bi; | |
070a1983 | 4083 | rtx_insn *insn; |
b8698a0f | 4084 | |
2af2dbdc | 4085 | CLEAR_REG_SET (live_relevant_regs); |
cee784f5 | 4086 | bitmap_clear (live_subregs_used); |
b8698a0f | 4087 | |
bf744527 | 4088 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi) |
2af2dbdc VM |
4089 | { |
4090 | if (i >= FIRST_PSEUDO_REGISTER) | |
4091 | break; | |
4092 | bitmap_set_bit (live_relevant_regs, i); | |
4093 | } | |
4094 | ||
bf744527 | 4095 | EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), |
2af2dbdc VM |
4096 | FIRST_PSEUDO_REGISTER, i, bi) |
4097 | { | |
4098 | if (pseudo_for_reload_consideration_p (i)) | |
4099 | bitmap_set_bit (live_relevant_regs, i); | |
4100 | } | |
4101 | ||
4102 | FOR_BB_INSNS_REVERSE (bb, insn) | |
4103 | { | |
4104 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4105 | { | |
bfac633a RS |
4106 | struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
4107 | df_ref def, use; | |
2af2dbdc VM |
4108 | |
4109 | c = new_insn_chain (); | |
4110 | c->next = next; | |
4111 | next = c; | |
4112 | *p = c; | |
4113 | p = &c->prev; | |
b8698a0f | 4114 | |
2af2dbdc VM |
4115 | c->insn = insn; |
4116 | c->block = bb->index; | |
4117 | ||
4b71920a | 4118 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4119 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
2af2dbdc | 4120 | { |
2af2dbdc | 4121 | unsigned int regno = DF_REF_REGNO (def); |
b8698a0f | 4122 | |
2af2dbdc VM |
4123 | /* Ignore may clobbers because these are generated |
4124 | from calls. However, every other kind of def is | |
4125 | added to dead_or_set. */ | |
4126 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) | |
4127 | { | |
4128 | if (regno < FIRST_PSEUDO_REGISTER) | |
4129 | { | |
4130 | if (!fixed_regs[regno]) | |
4131 | bitmap_set_bit (&c->dead_or_set, regno); | |
4132 | } | |
4133 | else if (pseudo_for_reload_consideration_p (regno)) | |
4134 | bitmap_set_bit (&c->dead_or_set, regno); | |
4135 | } | |
4136 | ||
4137 | if ((regno < FIRST_PSEUDO_REGISTER | |
4138 | || reg_renumber[regno] >= 0 | |
4139 | || ira_conflicts_p) | |
4140 | && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) | |
4141 | { | |
4142 | rtx reg = DF_REF_REG (def); | |
4143 | ||
4144 | /* We can model subregs, but not if they are | |
4145 | wrapped in ZERO_EXTRACTS. */ | |
4146 | if (GET_CODE (reg) == SUBREG | |
4147 | && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) | |
4148 | { | |
4149 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 4150 | unsigned int last = start |
2af2dbdc VM |
4151 | + GET_MODE_SIZE (GET_MODE (reg)); |
4152 | ||
4153 | init_live_subregs | |
b8698a0f | 4154 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc VM |
4155 | live_subregs, live_subregs_used, regno, reg); |
4156 | ||
4157 | if (!DF_REF_FLAGS_IS_SET | |
4158 | (def, DF_REF_STRICT_LOW_PART)) | |
4159 | { | |
4160 | /* Expand the range to cover entire words. | |
4161 | Bytes added here are "don't care". */ | |
4162 | start | |
4163 | = start / UNITS_PER_WORD * UNITS_PER_WORD; | |
4164 | last = ((last + UNITS_PER_WORD - 1) | |
4165 | / UNITS_PER_WORD * UNITS_PER_WORD); | |
4166 | } | |
4167 | ||
4168 | /* Ignore the paradoxical bits. */ | |
cee784f5 SB |
4169 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4170 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4171 | |
4172 | while (start < last) | |
4173 | { | |
d7c028c0 | 4174 | bitmap_clear_bit (live_subregs[regno], start); |
2af2dbdc VM |
4175 | start++; |
4176 | } | |
b8698a0f | 4177 | |
f61e445a | 4178 | if (bitmap_empty_p (live_subregs[regno])) |
2af2dbdc | 4179 | { |
cee784f5 | 4180 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4181 | bitmap_clear_bit (live_relevant_regs, regno); |
4182 | } | |
4183 | else | |
4184 | /* Set live_relevant_regs here because | |
4185 | that bit has to be true to get us to | |
4186 | look at the live_subregs fields. */ | |
4187 | bitmap_set_bit (live_relevant_regs, regno); | |
4188 | } | |
4189 | else | |
4190 | { | |
4191 | /* DF_REF_PARTIAL is generated for | |
4192 | subregs, STRICT_LOW_PART, and | |
4193 | ZERO_EXTRACT. We handle the subreg | |
4194 | case above so here we have to keep from | |
4195 | modeling the def as a killing def. */ | |
4196 | if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) | |
4197 | { | |
cee784f5 | 4198 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc | 4199 | bitmap_clear_bit (live_relevant_regs, regno); |
2af2dbdc VM |
4200 | } |
4201 | } | |
4202 | } | |
4203 | } | |
b8698a0f | 4204 | |
2af2dbdc VM |
4205 | bitmap_and_compl_into (live_relevant_regs, elim_regset); |
4206 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
4207 | ||
4b71920a | 4208 | if (NONDEBUG_INSN_P (insn)) |
bfac633a | 4209 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
2af2dbdc | 4210 | { |
2af2dbdc VM |
4211 | unsigned int regno = DF_REF_REGNO (use); |
4212 | rtx reg = DF_REF_REG (use); | |
b8698a0f | 4213 | |
2af2dbdc VM |
4214 | /* DF_REF_READ_WRITE on a use means that this use |
4215 | is fabricated from a def that is a partial set | |
4216 | to a multiword reg. Here, we only model the | |
4217 | subreg case that is not wrapped in ZERO_EXTRACT | |
4218 | precisely so we do not need to look at the | |
2b9c63a2 | 4219 | fabricated use. */ |
b8698a0f L |
4220 | if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) |
4221 | && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) | |
2af2dbdc VM |
4222 | && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) |
4223 | continue; | |
b8698a0f | 4224 | |
2af2dbdc VM |
4225 | /* Add the last use of each var to dead_or_set. */ |
4226 | if (!bitmap_bit_p (live_relevant_regs, regno)) | |
4227 | { | |
4228 | if (regno < FIRST_PSEUDO_REGISTER) | |
4229 | { | |
4230 | if (!fixed_regs[regno]) | |
4231 | bitmap_set_bit (&c->dead_or_set, regno); | |
4232 | } | |
4233 | else if (pseudo_for_reload_consideration_p (regno)) | |
4234 | bitmap_set_bit (&c->dead_or_set, regno); | |
4235 | } | |
b8698a0f | 4236 | |
2af2dbdc VM |
4237 | if (regno < FIRST_PSEUDO_REGISTER |
4238 | || pseudo_for_reload_consideration_p (regno)) | |
4239 | { | |
4240 | if (GET_CODE (reg) == SUBREG | |
4241 | && !DF_REF_FLAGS_IS_SET (use, | |
4242 | DF_REF_SIGN_EXTRACT | |
b8698a0f | 4243 | | DF_REF_ZERO_EXTRACT)) |
2af2dbdc VM |
4244 | { |
4245 | unsigned int start = SUBREG_BYTE (reg); | |
b8698a0f | 4246 | unsigned int last = start |
2af2dbdc | 4247 | + GET_MODE_SIZE (GET_MODE (reg)); |
b8698a0f | 4248 | |
2af2dbdc | 4249 | init_live_subregs |
b8698a0f | 4250 | (bitmap_bit_p (live_relevant_regs, regno), |
2af2dbdc | 4251 | live_subregs, live_subregs_used, regno, reg); |
b8698a0f | 4252 | |
2af2dbdc | 4253 | /* Ignore the paradoxical bits. */ |
cee784f5 SB |
4254 | if (last > SBITMAP_SIZE (live_subregs[regno])) |
4255 | last = SBITMAP_SIZE (live_subregs[regno]); | |
2af2dbdc VM |
4256 | |
4257 | while (start < last) | |
4258 | { | |
d7c028c0 | 4259 | bitmap_set_bit (live_subregs[regno], start); |
2af2dbdc VM |
4260 | start++; |
4261 | } | |
4262 | } | |
4263 | else | |
4264 | /* Resetting the live_subregs_used is | |
4265 | effectively saying do not use the subregs | |
4266 | because we are reading the whole | |
4267 | pseudo. */ | |
cee784f5 | 4268 | bitmap_clear_bit (live_subregs_used, regno); |
2af2dbdc VM |
4269 | bitmap_set_bit (live_relevant_regs, regno); |
4270 | } | |
4271 | } | |
4272 | } | |
4273 | } | |
4274 | ||
4275 | /* FIXME!! The following code is a disaster. Reload needs to see the | |
4276 | labels and jump tables that are just hanging out in between | |
4277 | the basic blocks. See pr33676. */ | |
4278 | insn = BB_HEAD (bb); | |
b8698a0f | 4279 | |
2af2dbdc | 4280 | /* Skip over the barriers and cruft. */ |
b8698a0f | 4281 | while (insn && (BARRIER_P (insn) || NOTE_P (insn) |
2af2dbdc VM |
4282 | || BLOCK_FOR_INSN (insn) == bb)) |
4283 | insn = PREV_INSN (insn); | |
b8698a0f | 4284 | |
2af2dbdc VM |
4285 | /* While we add anything except barriers and notes, the focus is |
4286 | to get the labels and jump tables into the | |
4287 | reload_insn_chain. */ | |
4288 | while (insn) | |
4289 | { | |
4290 | if (!NOTE_P (insn) && !BARRIER_P (insn)) | |
4291 | { | |
4292 | if (BLOCK_FOR_INSN (insn)) | |
4293 | break; | |
b8698a0f | 4294 | |
2af2dbdc VM |
4295 | c = new_insn_chain (); |
4296 | c->next = next; | |
4297 | next = c; | |
4298 | *p = c; | |
4299 | p = &c->prev; | |
b8698a0f | 4300 | |
2af2dbdc VM |
4301 | /* The block makes no sense here, but it is what the old |
4302 | code did. */ | |
4303 | c->block = bb->index; | |
4304 | c->insn = insn; | |
4305 | bitmap_copy (&c->live_throughout, live_relevant_regs); | |
b8698a0f | 4306 | } |
2af2dbdc VM |
4307 | insn = PREV_INSN (insn); |
4308 | } | |
4309 | } | |
4310 | ||
2af2dbdc VM |
4311 | reload_insn_chain = c; |
4312 | *p = NULL; | |
4313 | ||
cee784f5 SB |
4314 | for (i = 0; i < (unsigned int) max_regno; i++) |
4315 | if (live_subregs[i] != NULL) | |
4316 | sbitmap_free (live_subregs[i]); | |
2af2dbdc | 4317 | free (live_subregs); |
cee784f5 | 4318 | BITMAP_FREE (live_subregs_used); |
2af2dbdc VM |
4319 | BITMAP_FREE (live_relevant_regs); |
4320 | BITMAP_FREE (elim_regset); | |
4321 | ||
4322 | if (dump_file) | |
4323 | print_insn_chains (dump_file); | |
4324 | } | |
acf41a74 BS |
4325 | \f |
4326 | /* Examine the rtx found in *LOC, which is read or written to as determined | |
4327 | by TYPE. Return false if we find a reason why an insn containing this | |
4328 | rtx should not be moved (such as accesses to non-constant memory), true | |
4329 | otherwise. */ | |
4330 | static bool | |
4331 | rtx_moveable_p (rtx *loc, enum op_type type) | |
4332 | { | |
4333 | const char *fmt; | |
4334 | rtx x = *loc; | |
4335 | enum rtx_code code = GET_CODE (x); | |
4336 | int i, j; | |
4337 | ||
4338 | code = GET_CODE (x); | |
4339 | switch (code) | |
4340 | { | |
4341 | case CONST: | |
d8116890 | 4342 | CASE_CONST_ANY: |
acf41a74 BS |
4343 | case SYMBOL_REF: |
4344 | case LABEL_REF: | |
4345 | return true; | |
4346 | ||
4347 | case PC: | |
4348 | return type == OP_IN; | |
4349 | ||
4350 | case CC0: | |
4351 | return false; | |
4352 | ||
4353 | case REG: | |
4354 | if (x == frame_pointer_rtx) | |
4355 | return true; | |
4356 | if (HARD_REGISTER_P (x)) | |
4357 | return false; | |
4358 | ||
4359 | return true; | |
4360 | ||
4361 | case MEM: | |
4362 | if (type == OP_IN && MEM_READONLY_P (x)) | |
4363 | return rtx_moveable_p (&XEXP (x, 0), OP_IN); | |
4364 | return false; | |
4365 | ||
4366 | case SET: | |
4367 | return (rtx_moveable_p (&SET_SRC (x), OP_IN) | |
4368 | && rtx_moveable_p (&SET_DEST (x), OP_OUT)); | |
4369 | ||
4370 | case STRICT_LOW_PART: | |
4371 | return rtx_moveable_p (&XEXP (x, 0), OP_OUT); | |
4372 | ||
4373 | case ZERO_EXTRACT: | |
4374 | case SIGN_EXTRACT: | |
4375 | return (rtx_moveable_p (&XEXP (x, 0), type) | |
4376 | && rtx_moveable_p (&XEXP (x, 1), OP_IN) | |
4377 | && rtx_moveable_p (&XEXP (x, 2), OP_IN)); | |
4378 | ||
4379 | case CLOBBER: | |
4380 | return rtx_moveable_p (&SET_DEST (x), OP_OUT); | |
4381 | ||
d8c16744 VM |
4382 | case UNSPEC_VOLATILE: |
4383 | /* It is a bad idea to consider insns with with such rtl | |
4384 | as moveable ones. The insn scheduler also considers them as barrier | |
4385 | for a reason. */ | |
4386 | return false; | |
4387 | ||
acf41a74 BS |
4388 | default: |
4389 | break; | |
4390 | } | |
4391 | ||
4392 | fmt = GET_RTX_FORMAT (code); | |
4393 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4394 | { | |
4395 | if (fmt[i] == 'e') | |
4396 | { | |
4397 | if (!rtx_moveable_p (&XEXP (x, i), type)) | |
4398 | return false; | |
4399 | } | |
4400 | else if (fmt[i] == 'E') | |
4401 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4402 | { | |
4403 | if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) | |
4404 | return false; | |
4405 | } | |
4406 | } | |
4407 | return true; | |
4408 | } | |
4409 | ||
4410 | /* A wrapper around dominated_by_p, which uses the information in UID_LUID | |
4411 | to give dominance relationships between two insns I1 and I2. */ | |
4412 | static bool | |
4413 | insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) | |
4414 | { | |
4415 | basic_block bb1 = BLOCK_FOR_INSN (i1); | |
4416 | basic_block bb2 = BLOCK_FOR_INSN (i2); | |
4417 | ||
4418 | if (bb1 == bb2) | |
4419 | return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; | |
4420 | return dominated_by_p (CDI_DOMINATORS, bb1, bb2); | |
4421 | } | |
4422 | ||
4423 | /* Record the range of register numbers added by find_moveable_pseudos. */ | |
4424 | int first_moveable_pseudo, last_moveable_pseudo; | |
4425 | ||
4426 | /* These two vectors hold data for every register added by | |
4427 | find_movable_pseudos, with index 0 holding data for the | |
4428 | first_moveable_pseudo. */ | |
4429 | /* The original home register. */ | |
9771b263 | 4430 | static vec<rtx> pseudo_replaced_reg; |
acf41a74 BS |
4431 | |
4432 | /* Look for instances where we have an instruction that is known to increase | |
4433 | register pressure, and whose result is not used immediately. If it is | |
4434 | possible to move the instruction downwards to just before its first use, | |
4435 | split its lifetime into two ranges. We create a new pseudo to compute the | |
4436 | value, and emit a move instruction just before the first use. If, after | |
4437 | register allocation, the new pseudo remains unallocated, the function | |
4438 | move_unallocated_pseudos then deletes the move instruction and places | |
4439 | the computation just before the first use. | |
4440 | ||
4441 | Such a move is safe and profitable if all the input registers remain live | |
4442 | and unchanged between the original computation and its first use. In such | |
4443 | a situation, the computation is known to increase register pressure, and | |
4444 | moving it is known to at least not worsen it. | |
4445 | ||
4446 | We restrict moves to only those cases where a register remains unallocated, | |
4447 | in order to avoid interfering too much with the instruction schedule. As | |
4448 | an exception, we may move insns which only modify their input register | |
4449 | (typically induction variables), as this increases the freedom for our | |
4450 | intended transformation, and does not limit the second instruction | |
4451 | scheduler pass. */ | |
4452 | ||
4453 | static void | |
4454 | find_moveable_pseudos (void) | |
4455 | { | |
4456 | unsigned i; | |
4457 | int max_regs = max_reg_num (); | |
4458 | int max_uid = get_max_uid (); | |
4459 | basic_block bb; | |
4460 | int *uid_luid = XNEWVEC (int, max_uid); | |
070a1983 | 4461 | rtx_insn **closest_uses = XNEWVEC (rtx_insn *, max_regs); |
acf41a74 | 4462 | /* A set of registers which are live but not modified throughout a block. */ |
8b1c6fd7 DM |
4463 | bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, |
4464 | last_basic_block_for_fn (cfun)); | |
acf41a74 | 4465 | /* A set of registers which only exist in a given basic block. */ |
8b1c6fd7 DM |
4466 | bitmap_head *bb_local = XNEWVEC (bitmap_head, |
4467 | last_basic_block_for_fn (cfun)); | |
acf41a74 BS |
4468 | /* A set of registers which are set once, in an instruction that can be |
4469 | moved freely downwards, but are otherwise transparent to a block. */ | |
8b1c6fd7 DM |
4470 | bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, |
4471 | last_basic_block_for_fn (cfun)); | |
acf41a74 BS |
4472 | bitmap_head live, used, set, interesting, unusable_as_input; |
4473 | bitmap_iterator bi; | |
4474 | bitmap_initialize (&interesting, 0); | |
4475 | ||
4476 | first_moveable_pseudo = max_regs; | |
9771b263 DN |
4477 | pseudo_replaced_reg.release (); |
4478 | pseudo_replaced_reg.safe_grow_cleared (max_regs); | |
acf41a74 | 4479 | |
2d73cc45 MJ |
4480 | df_analyze (); |
4481 | calculate_dominance_info (CDI_DOMINATORS); | |
4482 | ||
acf41a74 BS |
4483 | i = 0; |
4484 | bitmap_initialize (&live, 0); | |
4485 | bitmap_initialize (&used, 0); | |
4486 | bitmap_initialize (&set, 0); | |
4487 | bitmap_initialize (&unusable_as_input, 0); | |
11cd3bed | 4488 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 | 4489 | { |
070a1983 | 4490 | rtx_insn *insn; |
acf41a74 BS |
4491 | bitmap transp = bb_transp_live + bb->index; |
4492 | bitmap moveable = bb_moveable_reg_sets + bb->index; | |
4493 | bitmap local = bb_local + bb->index; | |
4494 | ||
4495 | bitmap_initialize (local, 0); | |
4496 | bitmap_initialize (transp, 0); | |
4497 | bitmap_initialize (moveable, 0); | |
4498 | bitmap_copy (&live, df_get_live_out (bb)); | |
4499 | bitmap_and_into (&live, df_get_live_in (bb)); | |
4500 | bitmap_copy (transp, &live); | |
4501 | bitmap_clear (moveable); | |
4502 | bitmap_clear (&live); | |
4503 | bitmap_clear (&used); | |
4504 | bitmap_clear (&set); | |
4505 | FOR_BB_INSNS (bb, insn) | |
4506 | if (NONDEBUG_INSN_P (insn)) | |
4507 | { | |
bfac633a | 4508 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
bfac633a | 4509 | df_ref def, use; |
acf41a74 BS |
4510 | |
4511 | uid_luid[INSN_UID (insn)] = i++; | |
4512 | ||
74e59b6c RS |
4513 | def = df_single_def (insn_info); |
4514 | use = df_single_use (insn_info); | |
4515 | if (use | |
4516 | && def | |
4517 | && DF_REF_REGNO (use) == DF_REF_REGNO (def) | |
4518 | && !bitmap_bit_p (&set, DF_REF_REGNO (use)) | |
acf41a74 BS |
4519 | && rtx_moveable_p (&PATTERN (insn), OP_IN)) |
4520 | { | |
74e59b6c | 4521 | unsigned regno = DF_REF_REGNO (use); |
acf41a74 BS |
4522 | bitmap_set_bit (moveable, regno); |
4523 | bitmap_set_bit (&set, regno); | |
4524 | bitmap_set_bit (&used, regno); | |
4525 | bitmap_clear_bit (transp, regno); | |
4526 | continue; | |
4527 | } | |
bfac633a | 4528 | FOR_EACH_INSN_INFO_USE (use, insn_info) |
acf41a74 | 4529 | { |
bfac633a | 4530 | unsigned regno = DF_REF_REGNO (use); |
acf41a74 BS |
4531 | bitmap_set_bit (&used, regno); |
4532 | if (bitmap_clear_bit (moveable, regno)) | |
4533 | bitmap_clear_bit (transp, regno); | |
acf41a74 BS |
4534 | } |
4535 | ||
bfac633a | 4536 | FOR_EACH_INSN_INFO_DEF (def, insn_info) |
acf41a74 | 4537 | { |
bfac633a | 4538 | unsigned regno = DF_REF_REGNO (def); |
acf41a74 BS |
4539 | bitmap_set_bit (&set, regno); |
4540 | bitmap_clear_bit (transp, regno); | |
4541 | bitmap_clear_bit (moveable, regno); | |
acf41a74 BS |
4542 | } |
4543 | } | |
4544 | } | |
4545 | ||
4546 | bitmap_clear (&live); | |
4547 | bitmap_clear (&used); | |
4548 | bitmap_clear (&set); | |
4549 | ||
11cd3bed | 4550 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4551 | { |
4552 | bitmap local = bb_local + bb->index; | |
070a1983 | 4553 | rtx_insn *insn; |
acf41a74 BS |
4554 | |
4555 | FOR_BB_INSNS (bb, insn) | |
4556 | if (NONDEBUG_INSN_P (insn)) | |
4557 | { | |
74e59b6c | 4558 | df_insn_info *insn_info = DF_INSN_INFO_GET (insn); |
070a1983 DM |
4559 | rtx_insn *def_insn; |
4560 | rtx closest_use, note; | |
74e59b6c | 4561 | df_ref def, use; |
acf41a74 BS |
4562 | unsigned regno; |
4563 | bool all_dominated, all_local; | |
ef4bddc2 | 4564 | machine_mode mode; |
acf41a74 | 4565 | |
74e59b6c | 4566 | def = df_single_def (insn_info); |
acf41a74 | 4567 | /* There must be exactly one def in this insn. */ |
74e59b6c | 4568 | if (!def || !single_set (insn)) |
acf41a74 BS |
4569 | continue; |
4570 | /* This must be the only definition of the reg. We also limit | |
4571 | which modes we deal with so that we can assume we can generate | |
4572 | move instructions. */ | |
4573 | regno = DF_REF_REGNO (def); | |
4574 | mode = GET_MODE (DF_REF_REG (def)); | |
4575 | if (DF_REG_DEF_COUNT (regno) != 1 | |
4576 | || !DF_REF_INSN_INFO (def) | |
4577 | || HARD_REGISTER_NUM_P (regno) | |
aa44c80c | 4578 | || DF_REG_EQ_USE_COUNT (regno) > 0 |
acf41a74 BS |
4579 | || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) |
4580 | continue; | |
4581 | def_insn = DF_REF_INSN (def); | |
4582 | ||
4583 | for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) | |
4584 | if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) | |
4585 | break; | |
4586 | ||
4587 | if (note) | |
4588 | { | |
4589 | if (dump_file) | |
4590 | fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", | |
4591 | regno); | |
4592 | bitmap_set_bit (&unusable_as_input, regno); | |
4593 | continue; | |
4594 | } | |
4595 | ||
4596 | use = DF_REG_USE_CHAIN (regno); | |
4597 | all_dominated = true; | |
4598 | all_local = true; | |
4599 | closest_use = NULL_RTX; | |
4600 | for (; use; use = DF_REF_NEXT_REG (use)) | |
4601 | { | |
070a1983 | 4602 | rtx_insn *insn; |
acf41a74 BS |
4603 | if (!DF_REF_INSN_INFO (use)) |
4604 | { | |
4605 | all_dominated = false; | |
4606 | all_local = false; | |
4607 | break; | |
4608 | } | |
4609 | insn = DF_REF_INSN (use); | |
4610 | if (DEBUG_INSN_P (insn)) | |
4611 | continue; | |
4612 | if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) | |
4613 | all_local = false; | |
4614 | if (!insn_dominated_by_p (insn, def_insn, uid_luid)) | |
4615 | all_dominated = false; | |
4616 | if (closest_use != insn && closest_use != const0_rtx) | |
4617 | { | |
4618 | if (closest_use == NULL_RTX) | |
4619 | closest_use = insn; | |
4620 | else if (insn_dominated_by_p (closest_use, insn, uid_luid)) | |
4621 | closest_use = insn; | |
4622 | else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) | |
4623 | closest_use = const0_rtx; | |
4624 | } | |
4625 | } | |
4626 | if (!all_dominated) | |
4627 | { | |
4628 | if (dump_file) | |
4629 | fprintf (dump_file, "Reg %d not all uses dominated by set\n", | |
4630 | regno); | |
4631 | continue; | |
4632 | } | |
4633 | if (all_local) | |
4634 | bitmap_set_bit (local, regno); | |
4635 | if (closest_use == const0_rtx || closest_use == NULL | |
4636 | || next_nonnote_nondebug_insn (def_insn) == closest_use) | |
4637 | { | |
4638 | if (dump_file) | |
4639 | fprintf (dump_file, "Reg %d uninteresting%s\n", regno, | |
4640 | closest_use == const0_rtx || closest_use == NULL | |
4641 | ? " (no unique first use)" : ""); | |
4642 | continue; | |
4643 | } | |
4644 | #ifdef HAVE_cc0 | |
4645 | if (reg_referenced_p (cc0_rtx, PATTERN (closest_use))) | |
4646 | { | |
4647 | if (dump_file) | |
4648 | fprintf (dump_file, "Reg %d: closest user uses cc0\n", | |
4649 | regno); | |
4650 | continue; | |
4651 | } | |
4652 | #endif | |
4653 | bitmap_set_bit (&interesting, regno); | |
070a1983 DM |
4654 | /* If we get here, we know closest_use is a non-NULL insn |
4655 | (as opposed to const_0_rtx). */ | |
4656 | closest_uses[regno] = as_a <rtx_insn *> (closest_use); | |
acf41a74 BS |
4657 | |
4658 | if (dump_file && (all_local || all_dominated)) | |
4659 | { | |
4660 | fprintf (dump_file, "Reg %u:", regno); | |
4661 | if (all_local) | |
4662 | fprintf (dump_file, " local to bb %d", bb->index); | |
4663 | if (all_dominated) | |
4664 | fprintf (dump_file, " def dominates all uses"); | |
4665 | if (closest_use != const0_rtx) | |
4666 | fprintf (dump_file, " has unique first use"); | |
4667 | fputs ("\n", dump_file); | |
4668 | } | |
4669 | } | |
4670 | } | |
4671 | ||
4672 | EXECUTE_IF_SET_IN_BITMAP (&interesting, 0, i, bi) | |
4673 | { | |
4674 | df_ref def = DF_REG_DEF_CHAIN (i); | |
070a1983 | 4675 | rtx_insn *def_insn = DF_REF_INSN (def); |
acf41a74 BS |
4676 | basic_block def_block = BLOCK_FOR_INSN (def_insn); |
4677 | bitmap def_bb_local = bb_local + def_block->index; | |
4678 | bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; | |
4679 | bitmap def_bb_transp = bb_transp_live + def_block->index; | |
4680 | bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); | |
070a1983 | 4681 | rtx_insn *use_insn = closest_uses[i]; |
bfac633a | 4682 | df_ref use; |
acf41a74 BS |
4683 | bool all_ok = true; |
4684 | bool all_transp = true; | |
4685 | ||
4686 | if (!REG_P (DF_REF_REG (def))) | |
4687 | continue; | |
4688 | ||
4689 | if (!local_to_bb_p) | |
4690 | { | |
4691 | if (dump_file) | |
4692 | fprintf (dump_file, "Reg %u not local to one basic block\n", | |
4693 | i); | |
4694 | continue; | |
4695 | } | |
4696 | if (reg_equiv_init (i) != NULL_RTX) | |
4697 | { | |
4698 | if (dump_file) | |
4699 | fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", | |
4700 | i); | |
4701 | continue; | |
4702 | } | |
4703 | if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) | |
4704 | { | |
4705 | if (dump_file) | |
4706 | fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", | |
4707 | INSN_UID (def_insn), i); | |
4708 | continue; | |
4709 | } | |
4710 | if (dump_file) | |
4711 | fprintf (dump_file, "Examining insn %d, def for %d\n", | |
4712 | INSN_UID (def_insn), i); | |
bfac633a | 4713 | FOR_EACH_INSN_USE (use, def_insn) |
acf41a74 | 4714 | { |
acf41a74 BS |
4715 | unsigned regno = DF_REF_REGNO (use); |
4716 | if (bitmap_bit_p (&unusable_as_input, regno)) | |
4717 | { | |
4718 | all_ok = false; | |
4719 | if (dump_file) | |
4720 | fprintf (dump_file, " found unusable input reg %u.\n", regno); | |
4721 | break; | |
4722 | } | |
4723 | if (!bitmap_bit_p (def_bb_transp, regno)) | |
4724 | { | |
4725 | if (bitmap_bit_p (def_bb_moveable, regno) | |
4726 | && !control_flow_insn_p (use_insn) | |
4727 | #ifdef HAVE_cc0 | |
4728 | && !sets_cc0_p (use_insn) | |
4729 | #endif | |
4730 | ) | |
4731 | { | |
4732 | if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) | |
4733 | { | |
070a1983 | 4734 | rtx_insn *x = NEXT_INSN (def_insn); |
acf41a74 BS |
4735 | while (!modified_in_p (DF_REF_REG (use), x)) |
4736 | { | |
4737 | gcc_assert (x != use_insn); | |
4738 | x = NEXT_INSN (x); | |
4739 | } | |
4740 | if (dump_file) | |
4741 | fprintf (dump_file, " input reg %u modified but insn %d moveable\n", | |
4742 | regno, INSN_UID (x)); | |
4743 | emit_insn_after (PATTERN (x), use_insn); | |
4744 | set_insn_deleted (x); | |
4745 | } | |
4746 | else | |
4747 | { | |
4748 | if (dump_file) | |
4749 | fprintf (dump_file, " input reg %u modified between def and use\n", | |
4750 | regno); | |
4751 | all_transp = false; | |
4752 | } | |
4753 | } | |
4754 | else | |
4755 | all_transp = false; | |
4756 | } | |
acf41a74 BS |
4757 | } |
4758 | if (!all_ok) | |
4759 | continue; | |
4760 | if (!dbg_cnt (ira_move)) | |
4761 | break; | |
4762 | if (dump_file) | |
4763 | fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); | |
4764 | ||
4765 | if (all_transp) | |
4766 | { | |
4767 | rtx def_reg = DF_REF_REG (def); | |
4768 | rtx newreg = ira_create_new_reg (def_reg); | |
9e3de74c | 4769 | if (validate_change (def_insn, DF_REF_REAL_LOC (def), newreg, 0)) |
acf41a74 BS |
4770 | { |
4771 | unsigned nregno = REGNO (newreg); | |
a36b2706 | 4772 | emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); |
acf41a74 | 4773 | nregno -= max_regs; |
9771b263 | 4774 | pseudo_replaced_reg[nregno] = def_reg; |
acf41a74 BS |
4775 | } |
4776 | } | |
4777 | } | |
4778 | ||
11cd3bed | 4779 | FOR_EACH_BB_FN (bb, cfun) |
acf41a74 BS |
4780 | { |
4781 | bitmap_clear (bb_local + bb->index); | |
4782 | bitmap_clear (bb_transp_live + bb->index); | |
4783 | bitmap_clear (bb_moveable_reg_sets + bb->index); | |
4784 | } | |
4785 | bitmap_clear (&interesting); | |
4786 | bitmap_clear (&unusable_as_input); | |
4787 | free (uid_luid); | |
4788 | free (closest_uses); | |
4789 | free (bb_local); | |
4790 | free (bb_transp_live); | |
4791 | free (bb_moveable_reg_sets); | |
4792 | ||
4793 | last_moveable_pseudo = max_reg_num (); | |
2d73cc45 MJ |
4794 | |
4795 | fix_reg_equiv_init (); | |
4796 | expand_reg_info (); | |
4797 | regstat_free_n_sets_and_refs (); | |
4798 | regstat_free_ri (); | |
4799 | regstat_init_n_sets_and_refs (); | |
4800 | regstat_compute_ri (); | |
4801 | free_dominance_info (CDI_DOMINATORS); | |
732dad8f | 4802 | } |
acf41a74 | 4803 | |
3e749749 MJ |
4804 | /* If SET pattern SET is an assignment from a hard register to a pseudo which |
4805 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return | |
4806 | the destination. Otherwise return NULL. */ | |
732dad8f MJ |
4807 | |
4808 | static rtx | |
3e749749 | 4809 | interesting_dest_for_shprep_1 (rtx set, basic_block call_dom) |
732dad8f | 4810 | { |
732dad8f MJ |
4811 | rtx src = SET_SRC (set); |
4812 | rtx dest = SET_DEST (set); | |
4813 | if (!REG_P (src) || !HARD_REGISTER_P (src) | |
4814 | || !REG_P (dest) || HARD_REGISTER_P (dest) | |
4815 | || (call_dom && !bitmap_bit_p (df_get_live_in (call_dom), REGNO (dest)))) | |
4816 | return NULL; | |
4817 | return dest; | |
4818 | } | |
4819 | ||
df3e3493 | 4820 | /* If insn is interesting for parameter range-splitting shrink-wrapping |
3e749749 MJ |
4821 | preparation, i.e. it is a single set from a hard register to a pseudo, which |
4822 | is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a | |
4823 | parallel statement with only one such statement, return the destination. | |
4824 | Otherwise return NULL. */ | |
4825 | ||
4826 | static rtx | |
070a1983 | 4827 | interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom) |
3e749749 MJ |
4828 | { |
4829 | if (!INSN_P (insn)) | |
4830 | return NULL; | |
4831 | rtx pat = PATTERN (insn); | |
4832 | if (GET_CODE (pat) == SET) | |
4833 | return interesting_dest_for_shprep_1 (pat, call_dom); | |
4834 | ||
4835 | if (GET_CODE (pat) != PARALLEL) | |
4836 | return NULL; | |
4837 | rtx ret = NULL; | |
4838 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
4839 | { | |
4840 | rtx sub = XVECEXP (pat, 0, i); | |
4841 | if (GET_CODE (sub) == USE || GET_CODE (sub) == CLOBBER) | |
4842 | continue; | |
4843 | if (GET_CODE (sub) != SET | |
4844 | || side_effects_p (sub)) | |
4845 | return NULL; | |
4846 | rtx dest = interesting_dest_for_shprep_1 (sub, call_dom); | |
4847 | if (dest && ret) | |
4848 | return NULL; | |
4849 | if (dest) | |
4850 | ret = dest; | |
4851 | } | |
4852 | return ret; | |
4853 | } | |
4854 | ||
732dad8f MJ |
4855 | /* Split live ranges of pseudos that are loaded from hard registers in the |
4856 | first BB in a BB that dominates all non-sibling call if such a BB can be | |
4857 | found and is not in a loop. Return true if the function has made any | |
4858 | changes. */ | |
4859 | ||
4860 | static bool | |
4861 | split_live_ranges_for_shrink_wrap (void) | |
4862 | { | |
4863 | basic_block bb, call_dom = NULL; | |
fefa31b5 | 4864 | basic_block first = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)); |
070a1983 | 4865 | rtx_insn *insn, *last_interesting_insn = NULL; |
732dad8f MJ |
4866 | bitmap_head need_new, reachable; |
4867 | vec<basic_block> queue; | |
4868 | ||
a5e022d5 | 4869 | if (!SHRINK_WRAPPING_ENABLED) |
732dad8f MJ |
4870 | return false; |
4871 | ||
4872 | bitmap_initialize (&need_new, 0); | |
4873 | bitmap_initialize (&reachable, 0); | |
0cae8d31 | 4874 | queue.create (n_basic_blocks_for_fn (cfun)); |
732dad8f | 4875 | |
11cd3bed | 4876 | FOR_EACH_BB_FN (bb, cfun) |
732dad8f MJ |
4877 | FOR_BB_INSNS (bb, insn) |
4878 | if (CALL_P (insn) && !SIBLING_CALL_P (insn)) | |
4879 | { | |
4880 | if (bb == first) | |
4881 | { | |
4882 | bitmap_clear (&need_new); | |
4883 | bitmap_clear (&reachable); | |
4884 | queue.release (); | |
4885 | return false; | |
4886 | } | |
4887 | ||
4888 | bitmap_set_bit (&need_new, bb->index); | |
4889 | bitmap_set_bit (&reachable, bb->index); | |
4890 | queue.quick_push (bb); | |
4891 | break; | |
4892 | } | |
4893 | ||
4894 | if (queue.is_empty ()) | |
4895 | { | |
4896 | bitmap_clear (&need_new); | |
4897 | bitmap_clear (&reachable); | |
4898 | queue.release (); | |
4899 | return false; | |
4900 | } | |
4901 | ||
4902 | while (!queue.is_empty ()) | |
4903 | { | |
4904 | edge e; | |
4905 | edge_iterator ei; | |
4906 | ||
4907 | bb = queue.pop (); | |
4908 | FOR_EACH_EDGE (e, ei, bb->succs) | |
fefa31b5 | 4909 | if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) |
732dad8f MJ |
4910 | && bitmap_set_bit (&reachable, e->dest->index)) |
4911 | queue.quick_push (e->dest); | |
4912 | } | |
4913 | queue.release (); | |
4914 | ||
4915 | FOR_BB_INSNS (first, insn) | |
4916 | { | |
4917 | rtx dest = interesting_dest_for_shprep (insn, NULL); | |
4918 | if (!dest) | |
4919 | continue; | |
4920 | ||
4921 | if (DF_REG_DEF_COUNT (REGNO (dest)) > 1) | |
4922 | { | |
4923 | bitmap_clear (&need_new); | |
4924 | bitmap_clear (&reachable); | |
4925 | return false; | |
4926 | } | |
4927 | ||
4928 | for (df_ref use = DF_REG_USE_CHAIN (REGNO(dest)); | |
4929 | use; | |
4930 | use = DF_REF_NEXT_REG (use)) | |
4931 | { | |
732dad8f MJ |
4932 | int ubbi = DF_REF_BB (use)->index; |
4933 | if (bitmap_bit_p (&reachable, ubbi)) | |
4934 | bitmap_set_bit (&need_new, ubbi); | |
4935 | } | |
4936 | last_interesting_insn = insn; | |
4937 | } | |
4938 | ||
4939 | bitmap_clear (&reachable); | |
4940 | if (!last_interesting_insn) | |
4941 | { | |
4942 | bitmap_clear (&need_new); | |
4943 | return false; | |
4944 | } | |
4945 | ||
4946 | call_dom = nearest_common_dominator_for_set (CDI_DOMINATORS, &need_new); | |
4947 | bitmap_clear (&need_new); | |
4948 | if (call_dom == first) | |
4949 | return false; | |
4950 | ||
4951 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
4952 | while (bb_loop_depth (call_dom) > 0) | |
4953 | call_dom = get_immediate_dominator (CDI_DOMINATORS, call_dom); | |
4954 | loop_optimizer_finalize (); | |
4955 | ||
4956 | if (call_dom == first) | |
4957 | return false; | |
4958 | ||
4959 | calculate_dominance_info (CDI_POST_DOMINATORS); | |
4960 | if (dominated_by_p (CDI_POST_DOMINATORS, first, call_dom)) | |
4961 | { | |
4962 | free_dominance_info (CDI_POST_DOMINATORS); | |
4963 | return false; | |
4964 | } | |
4965 | free_dominance_info (CDI_POST_DOMINATORS); | |
4966 | ||
4967 | if (dump_file) | |
4968 | fprintf (dump_file, "Will split live ranges of parameters at BB %i\n", | |
4969 | call_dom->index); | |
4970 | ||
4971 | bool ret = false; | |
4972 | FOR_BB_INSNS (first, insn) | |
4973 | { | |
4974 | rtx dest = interesting_dest_for_shprep (insn, call_dom); | |
bcb21886 | 4975 | if (!dest || dest == pic_offset_table_rtx) |
732dad8f MJ |
4976 | continue; |
4977 | ||
4978 | rtx newreg = NULL_RTX; | |
4979 | df_ref use, next; | |
9e3de74c | 4980 | for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) |
732dad8f | 4981 | { |
070a1983 | 4982 | rtx_insn *uin = DF_REF_INSN (use); |
732dad8f MJ |
4983 | next = DF_REF_NEXT_REG (use); |
4984 | ||
4985 | basic_block ubb = BLOCK_FOR_INSN (uin); | |
4986 | if (ubb == call_dom | |
4987 | || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) | |
4988 | { | |
4989 | if (!newreg) | |
4990 | newreg = ira_create_new_reg (dest); | |
9e3de74c | 4991 | validate_change (uin, DF_REF_REAL_LOC (use), newreg, true); |
732dad8f MJ |
4992 | } |
4993 | } | |
4994 | ||
4995 | if (newreg) | |
4996 | { | |
4997 | rtx new_move = gen_move_insn (newreg, dest); | |
4998 | emit_insn_after (new_move, bb_note (call_dom)); | |
4999 | if (dump_file) | |
5000 | { | |
5001 | fprintf (dump_file, "Split live-range of register "); | |
5002 | print_rtl_single (dump_file, dest); | |
5003 | } | |
5004 | ret = true; | |
5005 | } | |
5006 | ||
5007 | if (insn == last_interesting_insn) | |
5008 | break; | |
5009 | } | |
5010 | apply_change_group (); | |
5011 | return ret; | |
acf41a74 | 5012 | } |
8ff49c29 | 5013 | |
acf41a74 BS |
5014 | /* Perform the second half of the transformation started in |
5015 | find_moveable_pseudos. We look for instances where the newly introduced | |
5016 | pseudo remains unallocated, and remove it by moving the definition to | |
5017 | just before its use, replacing the move instruction generated by | |
5018 | find_moveable_pseudos. */ | |
5019 | static void | |
5020 | move_unallocated_pseudos (void) | |
5021 | { | |
5022 | int i; | |
5023 | for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) | |
5024 | if (reg_renumber[i] < 0) | |
5025 | { | |
acf41a74 | 5026 | int idx = i - first_moveable_pseudo; |
9771b263 | 5027 | rtx other_reg = pseudo_replaced_reg[idx]; |
070a1983 | 5028 | rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); |
a36b2706 RS |
5029 | /* The use must follow all definitions of OTHER_REG, so we can |
5030 | insert the new definition immediately after any of them. */ | |
5031 | df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); | |
070a1983 DM |
5032 | rtx_insn *move_insn = DF_REF_INSN (other_def); |
5033 | rtx_insn *newinsn = emit_insn_after (PATTERN (def_insn), move_insn); | |
a36b2706 | 5034 | rtx set; |
acf41a74 BS |
5035 | int success; |
5036 | ||
5037 | if (dump_file) | |
5038 | fprintf (dump_file, "moving def of %d (insn %d now) ", | |
5039 | REGNO (other_reg), INSN_UID (def_insn)); | |
5040 | ||
a36b2706 RS |
5041 | delete_insn (move_insn); |
5042 | while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) | |
5043 | delete_insn (DF_REF_INSN (other_def)); | |
5044 | delete_insn (def_insn); | |
5045 | ||
acf41a74 BS |
5046 | set = single_set (newinsn); |
5047 | success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); | |
5048 | gcc_assert (success); | |
5049 | if (dump_file) | |
5050 | fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", | |
5051 | INSN_UID (newinsn), i); | |
acf41a74 BS |
5052 | SET_REG_N_REFS (i, 0); |
5053 | } | |
5054 | } | |
f2034d06 | 5055 | \f |
6399c0ab SB |
5056 | /* If the backend knows where to allocate pseudos for hard |
5057 | register initial values, register these allocations now. */ | |
a932fb89 | 5058 | static void |
6399c0ab SB |
5059 | allocate_initial_values (void) |
5060 | { | |
5061 | if (targetm.allocate_initial_value) | |
5062 | { | |
5063 | rtx hreg, preg, x; | |
5064 | int i, regno; | |
5065 | ||
5066 | for (i = 0; HARD_REGISTER_NUM_P (i); i++) | |
5067 | { | |
5068 | if (! initial_value_entry (i, &hreg, &preg)) | |
5069 | break; | |
5070 | ||
5071 | x = targetm.allocate_initial_value (hreg); | |
5072 | regno = REGNO (preg); | |
5073 | if (x && REG_N_SETS (regno) <= 1) | |
5074 | { | |
5075 | if (MEM_P (x)) | |
5076 | reg_equiv_memory_loc (regno) = x; | |
5077 | else | |
5078 | { | |
5079 | basic_block bb; | |
5080 | int new_regno; | |
5081 | ||
5082 | gcc_assert (REG_P (x)); | |
5083 | new_regno = REGNO (x); | |
5084 | reg_renumber[regno] = new_regno; | |
5085 | /* Poke the regno right into regno_reg_rtx so that even | |
5086 | fixed regs are accepted. */ | |
5087 | SET_REGNO (preg, new_regno); | |
5088 | /* Update global register liveness information. */ | |
11cd3bed | 5089 | FOR_EACH_BB_FN (bb, cfun) |
6399c0ab | 5090 | { |
c3284718 | 5091 | if (REGNO_REG_SET_P (df_get_live_in (bb), regno)) |
6399c0ab | 5092 | SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); |
c3284718 | 5093 | if (REGNO_REG_SET_P (df_get_live_out (bb), regno)) |
6399c0ab SB |
5094 | SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); |
5095 | } | |
5096 | } | |
5097 | } | |
5098 | } | |
2af2dbdc | 5099 | |
6399c0ab SB |
5100 | gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, |
5101 | &hreg, &preg)); | |
5102 | } | |
5103 | } | |
5104 | \f | |
55a2c322 VM |
5105 | |
5106 | /* True when we use LRA instead of reload pass for the current | |
5107 | function. */ | |
5108 | bool ira_use_lra_p; | |
5109 | ||
311aab06 VM |
5110 | /* True if we have allocno conflicts. It is false for non-optimized |
5111 | mode or when the conflict table is too big. */ | |
5112 | bool ira_conflicts_p; | |
5113 | ||
ae2b9cb6 BS |
5114 | /* Saved between IRA and reload. */ |
5115 | static int saved_flag_ira_share_spill_slots; | |
5116 | ||
058e97ec VM |
5117 | /* This is the main entry of IRA. */ |
5118 | static void | |
5119 | ira (FILE *f) | |
5120 | { | |
058e97ec | 5121 | bool loops_p; |
70cc3288 | 5122 | int ira_max_point_before_emit; |
058e97ec | 5123 | int rebuild_p; |
55a2c322 VM |
5124 | bool saved_flag_caller_saves = flag_caller_saves; |
5125 | enum ira_region saved_flag_ira_region = flag_ira_region; | |
5126 | ||
bcb21886 KY |
5127 | /* Perform target specific PIC register initialization. */ |
5128 | targetm.init_pic_reg (); | |
5129 | ||
55a2c322 VM |
5130 | ira_conflicts_p = optimize > 0; |
5131 | ||
5132 | ira_use_lra_p = targetm.lra_p (); | |
5133 | /* If there are too many pseudos and/or basic blocks (e.g. 10K | |
5134 | pseudos and 10K blocks or 100K pseudos and 1K blocks), we will | |
5135 | use simplified and faster algorithms in LRA. */ | |
5136 | lra_simple_p | |
8b1c6fd7 DM |
5137 | = (ira_use_lra_p |
5138 | && max_reg_num () >= (1 << 26) / last_basic_block_for_fn (cfun)); | |
55a2c322 VM |
5139 | if (lra_simple_p) |
5140 | { | |
5141 | /* It permits to skip live range splitting in LRA. */ | |
5142 | flag_caller_saves = false; | |
5143 | /* There is no sense to do regional allocation when we use | |
5144 | simplified LRA. */ | |
5145 | flag_ira_region = IRA_REGION_ONE; | |
5146 | ira_conflicts_p = false; | |
5147 | } | |
5148 | ||
5149 | #ifndef IRA_NO_OBSTACK | |
5150 | gcc_obstack_init (&ira_obstack); | |
5151 | #endif | |
5152 | bitmap_obstack_initialize (&ira_bitmap_obstack); | |
058e97ec | 5153 | |
001010df KC |
5154 | /* LRA uses its own infrastructure to handle caller save registers. */ |
5155 | if (flag_caller_saves && !ira_use_lra_p) | |
dc12b70e JZ |
5156 | init_caller_save (); |
5157 | ||
058e97ec VM |
5158 | if (flag_ira_verbose < 10) |
5159 | { | |
5160 | internal_flag_ira_verbose = flag_ira_verbose; | |
5161 | ira_dump_file = f; | |
5162 | } | |
5163 | else | |
5164 | { | |
5165 | internal_flag_ira_verbose = flag_ira_verbose - 10; | |
5166 | ira_dump_file = stderr; | |
5167 | } | |
5168 | ||
5169 | setup_prohibited_mode_move_regs (); | |
3b6d1699 | 5170 | decrease_live_ranges_number (); |
058e97ec | 5171 | df_note_add_problem (); |
5d517141 SB |
5172 | |
5173 | /* DF_LIVE can't be used in the register allocator, too many other | |
5174 | parts of the compiler depend on using the "classic" liveness | |
5175 | interpretation of the DF_LR problem. See PR38711. | |
5176 | Remove the problem, so that we don't spend time updating it in | |
5177 | any of the df_analyze() calls during IRA/LRA. */ | |
5178 | if (optimize > 1) | |
5179 | df_remove_problem (df_live); | |
5180 | gcc_checking_assert (df_live == NULL); | |
5181 | ||
058e97ec VM |
5182 | #ifdef ENABLE_CHECKING |
5183 | df->changeable_flags |= DF_VERIFY_SCHEDULED; | |
5184 | #endif | |
5185 | df_analyze (); | |
3b6d1699 | 5186 | |
2d73cc45 MJ |
5187 | init_reg_equiv (); |
5188 | if (ira_conflicts_p) | |
5189 | { | |
5190 | calculate_dominance_info (CDI_DOMINATORS); | |
5191 | ||
5192 | if (split_live_ranges_for_shrink_wrap ()) | |
5193 | df_analyze (); | |
5194 | ||
5195 | free_dominance_info (CDI_DOMINATORS); | |
5196 | } | |
5197 | ||
058e97ec | 5198 | df_clear_flags (DF_NO_INSN_RESCAN); |
2d73cc45 | 5199 | |
058e97ec VM |
5200 | regstat_init_n_sets_and_refs (); |
5201 | regstat_compute_ri (); | |
5202 | ||
5203 | /* If we are not optimizing, then this is the only place before | |
5204 | register allocation where dataflow is done. And that is needed | |
5205 | to generate these warnings. */ | |
5206 | if (warn_clobbered) | |
5207 | generate_setjmp_warnings (); | |
5208 | ||
ace984c8 RS |
5209 | /* Determine if the current function is a leaf before running IRA |
5210 | since this can impact optimizations done by the prologue and | |
5211 | epilogue thus changing register elimination offsets. */ | |
416ff32e | 5212 | crtl->is_leaf = leaf_function_p (); |
ace984c8 | 5213 | |
1833192f | 5214 | if (resize_reg_info () && flag_ira_loop_pressure) |
b11f0116 | 5215 | ira_set_pseudo_classes (true, ira_dump_file); |
1833192f | 5216 | |
058e97ec | 5217 | rebuild_p = update_equiv_regs (); |
55a2c322 VM |
5218 | setup_reg_equiv (); |
5219 | setup_reg_equiv_init (); | |
058e97ec | 5220 | |
55a2c322 | 5221 | if (optimize && rebuild_p) |
b8698a0f | 5222 | { |
55a2c322 | 5223 | timevar_push (TV_JUMP); |
29f3fd5b | 5224 | rebuild_jump_labels (get_insns ()); |
55a2c322 VM |
5225 | if (purge_all_dead_edges ()) |
5226 | delete_unreachable_blocks (); | |
5227 | timevar_pop (TV_JUMP); | |
058e97ec VM |
5228 | } |
5229 | ||
fb99ee9b | 5230 | allocated_reg_info_size = max_reg_num (); |
e8d7e3e7 | 5231 | |
dbabddf3 JJ |
5232 | if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) |
5233 | df_analyze (); | |
5234 | ||
e8d7e3e7 VM |
5235 | /* It is not worth to do such improvement when we use a simple |
5236 | allocation because of -O0 usage or because the function is too | |
5237 | big. */ | |
5238 | if (ira_conflicts_p) | |
2d73cc45 | 5239 | find_moveable_pseudos (); |
acf41a74 | 5240 | |
fb99ee9b | 5241 | max_regno_before_ira = max_reg_num (); |
8d49e7ef | 5242 | ira_setup_eliminable_regset (); |
b8698a0f | 5243 | |
058e97ec VM |
5244 | ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; |
5245 | ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; | |
5246 | ira_move_loops_num = ira_additional_jumps_num = 0; | |
b8698a0f | 5247 | |
058e97ec | 5248 | ira_assert (current_loops == NULL); |
2608d841 | 5249 | if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) |
661bc682 | 5250 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS | LOOPS_HAVE_RECORDED_EXITS); |
b8698a0f | 5251 | |
058e97ec VM |
5252 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) |
5253 | fprintf (ira_dump_file, "Building IRA IR\n"); | |
2608d841 | 5254 | loops_p = ira_build (); |
b8698a0f | 5255 | |
311aab06 | 5256 | ira_assert (ira_conflicts_p || !loops_p); |
3553f0bb VM |
5257 | |
5258 | saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; | |
de8e52f0 | 5259 | if (too_high_register_pressure_p () || cfun->calls_setjmp) |
3553f0bb | 5260 | /* It is just wasting compiler's time to pack spilled pseudos into |
de8e52f0 VM |
5261 | stack slots in this case -- prohibit it. We also do this if |
5262 | there is setjmp call because a variable not modified between | |
5263 | setjmp and longjmp the compiler is required to preserve its | |
5264 | value and sharing slots does not guarantee it. */ | |
3553f0bb VM |
5265 | flag_ira_share_spill_slots = FALSE; |
5266 | ||
cb1ca6ac | 5267 | ira_color (); |
b8698a0f | 5268 | |
058e97ec | 5269 | ira_max_point_before_emit = ira_max_point; |
b8698a0f | 5270 | |
1756cb66 VM |
5271 | ira_initiate_emit_data (); |
5272 | ||
058e97ec | 5273 | ira_emit (loops_p); |
b8698a0f | 5274 | |
55a2c322 | 5275 | max_regno = max_reg_num (); |
311aab06 | 5276 | if (ira_conflicts_p) |
058e97ec | 5277 | { |
058e97ec | 5278 | if (! loops_p) |
55a2c322 VM |
5279 | { |
5280 | if (! ira_use_lra_p) | |
5281 | ira_initiate_assign (); | |
5282 | } | |
058e97ec VM |
5283 | else |
5284 | { | |
fb99ee9b | 5285 | expand_reg_info (); |
b8698a0f | 5286 | |
55a2c322 VM |
5287 | if (ira_use_lra_p) |
5288 | { | |
5289 | ira_allocno_t a; | |
5290 | ira_allocno_iterator ai; | |
5291 | ||
5292 | FOR_EACH_ALLOCNO (a, ai) | |
9d6e10c7 RL |
5293 | { |
5294 | int old_regno = ALLOCNO_REGNO (a); | |
5295 | int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg); | |
5296 | ||
5297 | ALLOCNO_REGNO (a) = new_regno; | |
5298 | ||
5299 | if (old_regno != new_regno) | |
5300 | setup_reg_classes (new_regno, reg_preferred_class (old_regno), | |
5301 | reg_alternate_class (old_regno), | |
5302 | reg_allocno_class (old_regno)); | |
5303 | } | |
5304 | ||
55a2c322 VM |
5305 | } |
5306 | else | |
5307 | { | |
5308 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | |
5309 | fprintf (ira_dump_file, "Flattening IR\n"); | |
5310 | ira_flattening (max_regno_before_ira, ira_max_point_before_emit); | |
5311 | } | |
058e97ec VM |
5312 | /* New insns were generated: add notes and recalculate live |
5313 | info. */ | |
5314 | df_analyze (); | |
b8698a0f | 5315 | |
544e7e78 SB |
5316 | /* ??? Rebuild the loop tree, but why? Does the loop tree |
5317 | change if new insns were generated? Can that be handled | |
5318 | by updating the loop tree incrementally? */ | |
661bc682 | 5319 | loop_optimizer_finalize (); |
57548aa2 | 5320 | free_dominance_info (CDI_DOMINATORS); |
661bc682 RB |
5321 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS |
5322 | | LOOPS_HAVE_RECORDED_EXITS); | |
058e97ec | 5323 | |
55a2c322 VM |
5324 | if (! ira_use_lra_p) |
5325 | { | |
5326 | setup_allocno_assignment_flags (); | |
5327 | ira_initiate_assign (); | |
5328 | ira_reassign_conflict_allocnos (max_regno); | |
5329 | } | |
058e97ec VM |
5330 | } |
5331 | } | |
5332 | ||
1756cb66 VM |
5333 | ira_finish_emit_data (); |
5334 | ||
058e97ec | 5335 | setup_reg_renumber (); |
b8698a0f | 5336 | |
058e97ec | 5337 | calculate_allocation_cost (); |
b8698a0f | 5338 | |
058e97ec | 5339 | #ifdef ENABLE_IRA_CHECKING |
311aab06 | 5340 | if (ira_conflicts_p) |
058e97ec VM |
5341 | check_allocation (); |
5342 | #endif | |
b8698a0f | 5343 | |
058e97ec VM |
5344 | if (max_regno != max_regno_before_ira) |
5345 | { | |
5346 | regstat_free_n_sets_and_refs (); | |
5347 | regstat_free_ri (); | |
5348 | regstat_init_n_sets_and_refs (); | |
5349 | regstat_compute_ri (); | |
5350 | } | |
5351 | ||
058e97ec | 5352 | overall_cost_before = ira_overall_cost; |
e5b0e1ca VM |
5353 | if (! ira_conflicts_p) |
5354 | grow_reg_equivs (); | |
5355 | else | |
058e97ec VM |
5356 | { |
5357 | fix_reg_equiv_init (); | |
b8698a0f | 5358 | |
058e97ec VM |
5359 | #ifdef ENABLE_IRA_CHECKING |
5360 | print_redundant_copies (); | |
5361 | #endif | |
9994ad20 KC |
5362 | if (! ira_use_lra_p) |
5363 | { | |
5364 | ira_spilled_reg_stack_slots_num = 0; | |
5365 | ira_spilled_reg_stack_slots | |
5366 | = ((struct ira_spilled_reg_stack_slot *) | |
5367 | ira_allocate (max_regno | |
5368 | * sizeof (struct ira_spilled_reg_stack_slot))); | |
5369 | memset (ira_spilled_reg_stack_slots, 0, | |
5370 | max_regno * sizeof (struct ira_spilled_reg_stack_slot)); | |
5371 | } | |
058e97ec | 5372 | } |
6399c0ab | 5373 | allocate_initial_values (); |
e8d7e3e7 VM |
5374 | |
5375 | /* See comment for find_moveable_pseudos call. */ | |
5376 | if (ira_conflicts_p) | |
5377 | move_unallocated_pseudos (); | |
55a2c322 VM |
5378 | |
5379 | /* Restore original values. */ | |
5380 | if (lra_simple_p) | |
5381 | { | |
5382 | flag_caller_saves = saved_flag_caller_saves; | |
5383 | flag_ira_region = saved_flag_ira_region; | |
5384 | } | |
d3afd9aa RB |
5385 | } |
5386 | ||
5387 | static void | |
5388 | do_reload (void) | |
5389 | { | |
5390 | basic_block bb; | |
5391 | bool need_dce; | |
bcb21886 | 5392 | unsigned pic_offset_table_regno = INVALID_REGNUM; |
ae2b9cb6 | 5393 | |
67463efb | 5394 | if (flag_ira_verbose < 10) |
ae2b9cb6 | 5395 | ira_dump_file = dump_file; |
058e97ec | 5396 | |
bcb21886 KY |
5397 | /* If pic_offset_table_rtx is a pseudo register, then keep it so |
5398 | after reload to avoid possible wrong usages of hard reg assigned | |
5399 | to it. */ | |
5400 | if (pic_offset_table_rtx | |
5401 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
5402 | pic_offset_table_regno = REGNO (pic_offset_table_rtx); | |
5403 | ||
55a2c322 VM |
5404 | timevar_push (TV_RELOAD); |
5405 | if (ira_use_lra_p) | |
5406 | { | |
5407 | if (current_loops != NULL) | |
5408 | { | |
661bc682 | 5409 | loop_optimizer_finalize (); |
55a2c322 VM |
5410 | free_dominance_info (CDI_DOMINATORS); |
5411 | } | |
04a90bec | 5412 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5413 | bb->loop_father = NULL; |
5414 | current_loops = NULL; | |
55a2c322 VM |
5415 | |
5416 | ira_destroy (); | |
058e97ec | 5417 | |
55a2c322 VM |
5418 | lra (ira_dump_file); |
5419 | /* ???!!! Move it before lra () when we use ira_reg_equiv in | |
5420 | LRA. */ | |
9771b263 | 5421 | vec_free (reg_equivs); |
55a2c322 VM |
5422 | reg_equivs = NULL; |
5423 | need_dce = false; | |
5424 | } | |
5425 | else | |
5426 | { | |
5427 | df_set_flags (DF_NO_INSN_RESCAN); | |
5428 | build_insn_chain (); | |
5429 | ||
5430 | need_dce = reload (get_insns (), ira_conflicts_p); | |
5431 | ||
5432 | } | |
5433 | ||
5434 | timevar_pop (TV_RELOAD); | |
058e97ec | 5435 | |
d3afd9aa RB |
5436 | timevar_push (TV_IRA); |
5437 | ||
55a2c322 | 5438 | if (ira_conflicts_p && ! ira_use_lra_p) |
058e97ec VM |
5439 | { |
5440 | ira_free (ira_spilled_reg_stack_slots); | |
058e97ec | 5441 | ira_finish_assign (); |
b8698a0f | 5442 | } |
55a2c322 | 5443 | |
058e97ec VM |
5444 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL |
5445 | && overall_cost_before != ira_overall_cost) | |
2bf7560b VM |
5446 | fprintf (ira_dump_file, "+++Overall after reload %"PRId64 "\n", |
5447 | ira_overall_cost); | |
b8698a0f | 5448 | |
3553f0bb VM |
5449 | flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; |
5450 | ||
55a2c322 | 5451 | if (! ira_use_lra_p) |
2608d841 | 5452 | { |
55a2c322 VM |
5453 | ira_destroy (); |
5454 | if (current_loops != NULL) | |
5455 | { | |
661bc682 | 5456 | loop_optimizer_finalize (); |
55a2c322 VM |
5457 | free_dominance_info (CDI_DOMINATORS); |
5458 | } | |
04a90bec | 5459 | FOR_ALL_BB_FN (bb, cfun) |
55a2c322 VM |
5460 | bb->loop_father = NULL; |
5461 | current_loops = NULL; | |
5462 | ||
5463 | regstat_free_ri (); | |
5464 | regstat_free_n_sets_and_refs (); | |
2608d841 | 5465 | } |
b8698a0f | 5466 | |
058e97ec | 5467 | if (optimize) |
55a2c322 | 5468 | cleanup_cfg (CLEANUP_EXPENSIVE); |
b8698a0f | 5469 | |
55a2c322 | 5470 | finish_reg_equiv (); |
058e97ec VM |
5471 | |
5472 | bitmap_obstack_release (&ira_bitmap_obstack); | |
5473 | #ifndef IRA_NO_OBSTACK | |
5474 | obstack_free (&ira_obstack, NULL); | |
5475 | #endif | |
5476 | ||
5477 | /* The code after the reload has changed so much that at this point | |
b0c11403 | 5478 | we might as well just rescan everything. Note that |
058e97ec VM |
5479 | df_rescan_all_insns is not going to help here because it does not |
5480 | touch the artificial uses and defs. */ | |
5481 | df_finish_pass (true); | |
058e97ec VM |
5482 | df_scan_alloc (NULL); |
5483 | df_scan_blocks (); | |
5484 | ||
5d517141 SB |
5485 | if (optimize > 1) |
5486 | { | |
5487 | df_live_add_problem (); | |
5488 | df_live_set_all_dirty (); | |
5489 | } | |
5490 | ||
058e97ec VM |
5491 | if (optimize) |
5492 | df_analyze (); | |
5493 | ||
b0c11403 JL |
5494 | if (need_dce && optimize) |
5495 | run_fast_dce (); | |
d3afd9aa | 5496 | |
af6e8467 RH |
5497 | /* Diagnose uses of the hard frame pointer when it is used as a global |
5498 | register. Often we can get away with letting the user appropriate | |
5499 | the frame pointer, but we should let them know when code generation | |
5500 | makes that impossible. */ | |
5501 | if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) | |
5502 | { | |
5503 | tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; | |
5504 | error_at (DECL_SOURCE_LOCATION (current_function_decl), | |
5505 | "frame pointer required, but reserved"); | |
5506 | inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); | |
5507 | } | |
5508 | ||
bcb21886 KY |
5509 | if (pic_offset_table_regno != INVALID_REGNUM) |
5510 | pic_offset_table_rtx = gen_rtx_REG (Pmode, pic_offset_table_regno); | |
5511 | ||
d3afd9aa | 5512 | timevar_pop (TV_IRA); |
058e97ec | 5513 | } |
058e97ec | 5514 | \f |
058e97ec | 5515 | /* Run the integrated register allocator. */ |
058e97ec | 5516 | |
27a4cd48 DM |
5517 | namespace { |
5518 | ||
5519 | const pass_data pass_data_ira = | |
058e97ec | 5520 | { |
27a4cd48 DM |
5521 | RTL_PASS, /* type */ |
5522 | "ira", /* name */ | |
5523 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5524 | TV_IRA, /* tv_id */ |
5525 | 0, /* properties_required */ | |
5526 | 0, /* properties_provided */ | |
5527 | 0, /* properties_destroyed */ | |
5528 | 0, /* todo_flags_start */ | |
5529 | TODO_do_not_ggc_collect, /* todo_flags_finish */ | |
d3afd9aa RB |
5530 | }; |
5531 | ||
27a4cd48 DM |
5532 | class pass_ira : public rtl_opt_pass |
5533 | { | |
5534 | public: | |
c3284718 RS |
5535 | pass_ira (gcc::context *ctxt) |
5536 | : rtl_opt_pass (pass_data_ira, ctxt) | |
27a4cd48 DM |
5537 | {} |
5538 | ||
5539 | /* opt_pass methods: */ | |
a50fa76a BS |
5540 | virtual bool gate (function *) |
5541 | { | |
5542 | return !targetm.no_register_allocation; | |
5543 | } | |
be55bfe6 TS |
5544 | virtual unsigned int execute (function *) |
5545 | { | |
5546 | ira (dump_file); | |
5547 | return 0; | |
5548 | } | |
27a4cd48 DM |
5549 | |
5550 | }; // class pass_ira | |
5551 | ||
5552 | } // anon namespace | |
5553 | ||
5554 | rtl_opt_pass * | |
5555 | make_pass_ira (gcc::context *ctxt) | |
5556 | { | |
5557 | return new pass_ira (ctxt); | |
5558 | } | |
5559 | ||
27a4cd48 DM |
5560 | namespace { |
5561 | ||
5562 | const pass_data pass_data_reload = | |
d3afd9aa | 5563 | { |
27a4cd48 DM |
5564 | RTL_PASS, /* type */ |
5565 | "reload", /* name */ | |
5566 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
5567 | TV_RELOAD, /* tv_id */ |
5568 | 0, /* properties_required */ | |
5569 | 0, /* properties_provided */ | |
5570 | 0, /* properties_destroyed */ | |
5571 | 0, /* todo_flags_start */ | |
5572 | 0, /* todo_flags_finish */ | |
058e97ec | 5573 | }; |
27a4cd48 DM |
5574 | |
5575 | class pass_reload : public rtl_opt_pass | |
5576 | { | |
5577 | public: | |
c3284718 RS |
5578 | pass_reload (gcc::context *ctxt) |
5579 | : rtl_opt_pass (pass_data_reload, ctxt) | |
27a4cd48 DM |
5580 | {} |
5581 | ||
5582 | /* opt_pass methods: */ | |
a50fa76a BS |
5583 | virtual bool gate (function *) |
5584 | { | |
5585 | return !targetm.no_register_allocation; | |
5586 | } | |
be55bfe6 TS |
5587 | virtual unsigned int execute (function *) |
5588 | { | |
5589 | do_reload (); | |
5590 | return 0; | |
5591 | } | |
27a4cd48 DM |
5592 | |
5593 | }; // class pass_reload | |
5594 | ||
5595 | } // anon namespace | |
5596 | ||
5597 | rtl_opt_pass * | |
5598 | make_pass_reload (gcc::context *ctxt) | |
5599 | { | |
5600 | return new pass_reload (ctxt); | |
5601 | } |